EB78 - MachXO2-4000HC Control Development Kit User's Guide

EB78 - MachXO2-4000HC Control Development Kit User's Guide

MachXO2-4000HC Control Development Kit
User’s Guide
November 2013
Revision: EB78_01.1

MachXO2-4000HC Control Development Kit
User’s Guide
Introduction
Thank you for choosing the Lattice Semiconductor MachXO2™-4000HC Control Development Kit!
This guide describes how to start using the MachXO2-4000HC Control Development Kit, an easy-to-use platform
for rapidly prototyping system control designs using MachXO2 PLDs. Along with the evaluation board and accessories, this kit includes a pre-loaded control system-on-chip (Control SoC) design that demonstrates board diagnostic
functions including I/O control, voltage monitoring, time-stamps and data logging to non-volatile memory. The
Power Manager II ispPAC®-POWR1014A and 8-bit LatticeMico8™ microcontroller are featured in the board and
demonstration design.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of
the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and bill of
materials for the MachXO2-4000HC Control Evaluation Board.
Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO2-4000HC
Control Development Kit QuickSTART Guide for handling and storage tips.
Features
The MachXO2-4000HC Control Development Kit includes:
• MachXO2-4000HC Control Evaluation Board – The MachXO2-4000HC Control Evaluation Board features the
following on-board components and circuits:
– MachXO2 LCMXO2-4000HC-csBGA132 PLD
– Power Manager II POWR1014A mixed-signal PLD
– 4 Mbit SPI Flash memory
– microSD (micro Secure Digital) memory socket
– Current and voltage sensor circuits
– Voltage ramp circuits
– Electret microphone
– Audio amplifier and Delta-Sigma ADC
– PWM analog output circuit
– Audio output channel
– Up to two DVI sources and one DVI output
– Up to two 7:1 LVDS sources and one 7:1:VDS output (e.g. Camera Link)
– Expansion header for JTAG, SPI, I2C and PLD I/Os
– LEDs and switches
– Standard USB cable for device programming
– RS-232/USB and JTAG/USB interface
– RoHS-compliant packaging and process
– AC adapter (international plugs)
• Pre-loaded Reference Designs and Demo – The kit includes the pre-loaded Control SoC demo design that
integrates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus
controller, soft Delta-Sigma ADC, SPI master controller, UART peripheral, Embedded Block RAM and additional
control functions.
• USB connector Cable – A mini B USB port provides a communication and debug port via a USB-to-RS-232
physical channel and programming interface to the MachXO2 JTAG port.
• AC Adapter (international plugs) with 5V DC output.
• QuickSTART Guide – Provides information on connecting the MachXO2-4000HC Control Evaluation Board,
installing Windows hardware drivers, and running the Control SoC demo.
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MachXO2-4000HC Control Development Kit
User’s Guide
Figure 1 shows the top side of the MachXO2-4000HC Control Evaluation Board with comments on the specific features that are designed in the board.
Figure 1. MachXO2-4000HC Control Evaluation Board, Top Side
DVI
Video Output
7:1 LVDS
Video Output
GSR Push-button
5V Power Indicator
MachXO2 DIP Switches
Electret Microphone
2x20 GPIO Header
Speaker/Headphone Jack
MachXO2-4000HC
AC-DC Adapter Jack
microSD Socket
ADC Input (J9: Pin 2)
LPDDR Memory
POWR1014A
JTAG Device Select (J6),
MachXO2 Position Shown
MachXO2 LED Field
7:1 LVDS
Video Source
(Camera Link)
DVI Video Source
USB 2.0
Interface Socket
Notes:
– Video Source 1 is available in both DVI and 7:1 LVDS interfaces. Video Source 2 is not populated.
– An LPDDR memory device is installed on the PCB, but performance is limited to 20MHz max.
Lattice Semiconductor Devices
MachXO2
This board features a 3.3V MachXO2 PLD packaged in a 132-ball csBGA package. This package allows density
migration to devices from 256 to 4340 LUTs. A complete description of this device can be found in the MachXO2
Family Handbook.
Power Manager II
This board also features a Power Manager II mixed-signal PLD. The POWR1014A device serves as a general-purpose
power supply monitor, reset generator, sequence controller, and high-voltage FET drivers. More information about
Power Manager II devices can be found on the Lattice web site at www.latticesemi.com/products/powermanager.
Software Requirements
You should install Lattice Diamond® design software version 2.0 (or higher) before you begin developing designs for
the evaluation board.
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MachXO2-4000HC Control Development Kit
User’s Guide
Control SoC Demonstration Design
The Control System-on-Chip (SoC) demonstration illustrates the use of the LatticeMico8 microcontroller, peripherals, and firmware integrated to provide system control features such as power supply sequencing, voltage monitoring, data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication and
PLL status monitoring.
• The Power Manager II device sequences the power-up of voltage rails on the board and performs reset distribution.
• LatticeMico8 executable program initializes the peripherals that are embedded in the SoC design. During initialization, LatticeMico8 uploads the user menu on a Terminal emulator (e.g. HyperTerminal, Tera Term) of a PC.
• Users interact with LatticeMico8 and the board through the Terminal emulator of a PC.
Figure 2. Control SoC Demo Block Diagram
MachXO2 Control Evaluation Board
MachXO2-1200
PC
USB/
RS232
UART
Timer/
Counter
LatticeMico8
Microcontroller
LEDs/
DIP Switches
WISHBONE Bus
Soft
ADC
Master
SPI
Analog
Signal
SPI
Flash
Embedded
Block RAM
Power management is handled in two phases by the MachXO2-4000HC Control Evaluation Board system:
1. Power On – After power is supplied to the board and the 3.3V rail is stable, the POWR1014A sequences four
supply rails. Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETs using the high-voltage
(HVOUT) outputs and two demonstrate power rail enable of VCC_CORE and VCCP of the MachXO2 using
digital outputs. Next, the POWR1014A asserts the MachXO2 reset. Finally, the POWR1014A enters a supply
monitoring state.
2. Post Power On – During the second phase of power management, the board’s “condition” is monitored. Power
supply rail voltage, and current is monitored by the POWR1014A. If any supply rail fails, the POWR1014A
asserts a reset for the MachXO2.
MachXO2 Function – After the reset is de-asserted, LatticeMico8 initializes the peripherals embedded in the
MachXO2 device and uploads the user menu onto the Terminal emulator window of a PC.
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MachXO2-4000HC Control Development Kit
User’s Guide
Figure 3. HyperTerminal User Menu
Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the Terminal
emulator menu. The available options are:
• ‘m’ – This option will re-display the main menu anytime during the demonstration.
• ‘a’ – This option will sample the voltage in the pin #2 of header J9. By default, the node is biased at 1.65V, which
is half of the VCCIO = 3.30V. The voltage will be displayed in the HyperTerminal window. The ADC input voltage
should be limited to the range 0 to 3.0V to avoid device damage.
• ‘s’ – This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal. The
resulting ID is hexadecimal 0x44, which corresponds to AT25DF041A device.
• ‘t’ – This option samples and displays the elapsed time since the reset was de-asserted.
• ‘r’ - This option samples the DIP switches (reference designator SW1) on the board and displays the data in the
HyperTerminal. Users can change the DIP switches on the board and press ‘r’ to display the new value.
• “0-9” – These are BCD numerical values that can be typed on the keyboard. The value will be received by
LatticeMico8, which will update the LEDs (D0-D3) on the board.
• ‘l’ – This is a lower case ‘L’ character. Pressing ‘l’ will sample the voltage in pin #2 of header J9 and log the data
in the SPI Flash device on the board. The WRITE page pointer will increment when ‘l’ is pressed. The initial value
of the page pointer after power-up or after a reset is 0.
• ‘d’ – This option will read the data from SPI Flash device and display it on the HyperTerminal window. The READ
page pointer will increment when ‘d’ is pressed. The initial value of the page pointer after power-up or after a
reset is 0.
• ‘c’ – This option will clear (reset) the WRITE and READ page pointers.
• ‘e’ – This selection will perform a bulk-erase of the Flash memory in the SPI Flash device.
Setting up the Board
Drivers and Firmware
Before you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site.
1. Browse to the www.latticesemi.com/MachXO2-control-kit and locate the hardware device drivers for the USB
interface.
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MachXO2-4000HC Control Development Kit
User’s Guide
2. Download the ZIP file to your system and unzip it to a location on your PC.
Linux Support:
The USB interface drivers for the evaluation board are included in Linux kernel 2.4.20 or greater including distributions compatible with Lattice Diamond design software (Red Hat Enterprise v.3, v.4 or Novell SUSE Enterprise
v.10).
The Control SoC Demo is preprogrammed into the MachXO2-4000HC Control Evaluation Board, however over
time it is likely that your board will be modified.
To download the demo source files and reprogram the MachXO2-4000HC Control Evaluation Board:
1. Download demo application source code from www.latticesemi.com/mxo2-control-kit.
2. Use .\Demo_MachXO2_Control_SoC\project\control_soc_demo.jed to restore the MachXO2-4000HC
Control SoC demo design.
3. Use .\Demo_PM_Control_BM\project\bm_demo.jed to restore the POWR1014A Board Management demo
design.
Connecting to the MachXO2-4000HC Control Evaluation Board
1. Plug the AC-DC adopter to an outlet.
2. Power the board by inserting the AC-DC adopter into the power jack with reference designator J11. Once the
connection is made, a red LED with reference designator D12 will illuminate.
3. Connect the evaluation board to your PC using the USB cable provided. The USB connector in the board has
reference designator J5.
4. If you are prompted, “Windows may connect to Windows Update”, select No, not this time from available
options and click Next to proceed with the installation.
5. Choose the Install from specific location (Advanced) option and click Next.
6. Select Search for the best driver in these locations and click the Browse button to browse to the Windows
driver folder created earlier. Select the CDM 2.04.06 WHQL Certified folder and click OK.
7. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
Programming the PLDs
The three-pin header with reference designator J6 is used to select between the JTAG port of the MachXO2 or
POWR1014A device. Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device.
Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device.
Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4. This example shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been
selected.
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MachXO2-4000HC Control Development Kit
User’s Guide
Figure 4. J6 Header Used for Selecting the JTAG Port of the PLDs
Using Diamond Programmer software (included with the Diamond installation), users can scan and perform JTAG
operations, including programming, with the MachXO2 and POWR1014A devices.
Setting Up Windows HyperTerminal
You will use a terminal emulator program to communicate with the evaluation board. The following instructions
describe the Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program if desired although setup will be different. Windows 7 does not include HyperTerminal. Tera Term has
been verified to work with Windows 7. For Linux, Minicom is a good alternative.
Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows version.
1. From the Start menu, select Control Panel > System. The “System Properties” dialog appears.
2. Select the Hardware tab and click Device Manager. The “Device Manager” dialog appears.
Figure 5. Device Manager – COM Port
3. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port.
4. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTerminal application and a “Connection Description” dialog appear.
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MachXO2-4000HC Control Development Kit
User’s Guide
Figure 6. New Connection – COM Port
5. Specify a Name and Icon for the new connection. Click OK. The “Connect To” dialog appears.
6. Select the COM port identified in Step 3 from the Connect using: list. Click OK.
Figure 7. Selecting the COM Port
7. The “COMn Properties” dialog appears where n is the COM port selected from the list.
8. Select the following Port Settings and click OK.
Bits per second: 115200
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
Figure 8. COM Port Properties
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MachXO2-4000HC Control Development Kit
User’s Guide
9. The HyperTerminal window appears.
10. From the MachXO2-4000HC Control Evaluation Board, press the reset push-button with reference designator
S1. The Control SoC demo main menu appears.
Setting Up Linux Minicom
Minicom is a terminal program found with most Linux distributions. It can be used to communicate with the
MachXO2-4000HC Control Evaluation Board.
To setup Minicom:
1. Check active serial ports:
#dmesg | grep tty
Note the tty label assigned to the USB port
2. From a command prompt, start Minicom:
#minicom –s
The configuration menu appears.
3. Highlight Serial port setup and press Enter. Serial port settings appear.
4. Press A (Serial Device). Specify the active serial device noted in Step 1 and press Enter.
5. Press E (Bps/Par/Bits). Specify 115200, None, 8 and press Enter.
6. Press F (Hardware Flow Control). Specify None and press Enter.
7. Press Esc. The configuration menu appears.
8. Select Save setup as dfl. Minicom saves the port setup as the new default.
9. Select Exit. The Minicom interface appears.
10. From the evaluation board, press the S1 push-button (GSR).The Control SoC demo main menu appears.
Ordering Information
Description
MachXO2-4000HC Control Development Kit
Ordering Part Number
LCMXO2-4000HC-C-EVN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
9
China RoHS Environment-Friendly
Use Period (EFUP)
MachXO2-4000HC Control Development Kit
User’s Guide
Revision History
Date
Version
October 2012
01.0
Initial release.
Change Summary
November 2013
01.1
Removed LPDDR from features list, added performance note.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
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MachXO2-4000HC Control Development Kit
User’s Guide
Appendix A. Schematic
Figure 9. Architecture
5
JTAG Chain
UART &
USB PORT
Page 3,5
Board Power
Managment
Voltage Monitor
High Voltage Drivers
Page 8
MachXO2 Control Board Architecture
SPI
4Mbit
Page 7
5
GPIO
SPI Bus
I2C Bus
Page 4
4
Page 4
RESET
Page 7
DVI Conn
7:1LVDS TX
3
Page 11
3
7:1LVDS RX
MachXO2
7:1LVDS to DVI
Conversion
GPIO
DVI Conn
DVI to 7:1LVDS
Conversion
Page 9
7:1LVDS Conn
UART
SW & LEDs
ispPAC POWR1014A
Power Manager II
Page 6
4
7:1LVDS Conn
ADC: Page 14
DAC: Page 12
ADC-DAC
Page 13,14
2
Page 12
Page 7
Page 7
Page 8
Page 8
Page 12
7:1LVDS Conn
Page 10
DVI to 7:1LVDS
Conversion
DVI Conn
2
Audio IN
Audio OUT
SD Flash
LPDDR 128Mb
SW & LEDs
Tuesday, June 26, 2012
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14
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Hillsboro, Oregon. 97124
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MachXO2 Control Board
Project
Architecture
Crystal
Title
Size
B
Date:
D
C
B
A
11
D
C
B
A
2x20 Header
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 10. Power, VCC33, VCC18, VCC12
D
C
B
A
5
J11
DI
AC-DC Jack - 5V
5V
Input
VCC33
C33
10uF
DI
1
2
3
PWR_JACK
1
2
3
4
BYPASS
NC
GND
INPUT
VCC5
U17
LP3879MR_1_2
DNI
IO19
IO20
OUTPUT
SENSE
NC_1
~SD
9
5
6
7
8
9
Linear VREG Step Down 3.3V to 1.2V Rail
C108
0_01uF
DI
5
DI
4
VCC33 VCC12
R200
10K
4
C106
10uF
DI
VCC_CORE
Q6
BSS138LT1
DI
VCC33
R81
10K
PM_OUT8
3
3
[4,5]
R122
470
2
3
C54
10uF
DI
U11
IN
OUT
TAB
2
4
1 DI
NCP1117ST33
GND
DI
Linear VREG Step Down 5V to 3.3V Rail
VCC5
DI
DI
C66
10uF
DI
3
U12
IN
Title
Size
B
Date:
OUT
TAB
2
4
1 DI
NCP1117ST18
GND
C53
22uF
C65
22uF
Tuesday, June 26, 2012
VCC33
VCC18
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MachXO2 Control Board
Project
Power VCC33, VCC18, VCC12
DI
Linear VREG Step Down 3.3V to 1.8V Rail
VCC33
2
D
C
B
A
12
D12
LED
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 11. Power ispPAC-POWR1014A
D
VCC_CORE
5
VCCIO33
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
25
26
27
28
32
33
34
35
36
37
39
38
19
17
18
16
22
21
44
46
47
48
SCL
SDA
PM_IN1
PM_IN2
PM_IN3
PM_IN4
VMON1
1
1
VCC33
Q5
2N7002E
DI
R179
200
DI
VCC33
Q2
2N7002E
DI
R198
200
DI
4
ispPAC-POWR1014A
DI
SCL
SDA
TDISEL
ATDI
TDI
TMS
TCK
TDO
IN1
IN2
IN3
IN4
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
U7
POWER MANAGER II
[5] ICC_Sense
[5] ICCIO33_Sense
[5] ICCIO18_Sense
[7] VMON9
[7] VMON10
SCL
SDA
PM_TDI
PM_TMS
PM_TCK
PM_TDO
[14] PM_IN1
[14] PM_IN2
[6]
[6]
[6]
[6]
[7,14]
[7,14]
1KDI
R196
C83
1uF
DI
R195
VMON8
VMON7
Voltage Ramp Circuit
HVOUT1
HVOUT2
1KDI
C35
1uF
DI
IO18
VCC33
15
14
PM_SMBA_OUT3
PM_LED0
PM_LED1
PM_LED2
PM_LED3
PM_OUT8
PM_OUT9
PM_OUT10
PM_OUT11
PM_OUT12
PM_OUT13
PM_OUT14
HVOUT1
HVOUT2
C99
0_1uF
DI
13
12
11
10
9
8
6
5
4
3
2
1
PM_PLDCLK
PM_MCLK
30
31
7
42
43
40
C89
0_1uF
DI
HVOUT1
HVOUT2
SMBA_OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
PLDCLK
MCLK
RESETB
GNDA
GNDD
GNDD
DI DI DI DI
RN4
RN2_4_470
DI
PM LEDs
VCC33
LED LED LED LED
D10 D9 D8 D7
PM_LED0
PM_LED1
PM_LED2
PM_LED3
C107
0_1uF
DI
3
HVOUT1
HVOUT2
[7]
[7]
PM_SMBA_OUT3 [14]
PM_OUT8
[3,5]
PM_OUT9
[5]
XO2_RESETn [7,14]
PM_OUT11 [14]
PM_OUT12 [14]
PM_OUT13 [14]
PM_OUT14
PM_IN3
PM_IN4
VCC33
SW DIP_2
DI
SW2
PM DIP Switch
PM DIP SWITCH
PM_PLDCLK [7,14]
PM_MCLK
[7,14]
3
2
2
Title
Size
B
Date:
1
1
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Power ispPAC-POWR1014A
Project
Tuesday, June 26, 2012
MachXO2 Control Board
D
C
B
A
13
VCCD
VCCD
VCCA
VCCINP
VCCPROG
VCCJ
23
41
29
45
24
20
4
DI 10K R164
DI 10K R163
C
B
A
5
8
7
6
5
1
2
3
4
3
2
3
2
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 12. Power Current Sense
D
C
B
A
[3,4]
PM_OUT8
PM_OUT9
5
MachXO2 Power Rails
C142
10uF
DI
ICC_P
4
R232
1K
DI
IO9
R59
1
DI
R58
0
DNI
VCC12
DI
ZDT758
Q7A
5
VCC33
MachXO2 - Core Current
DI
R219
220
R60
220
DI
C143
10uF
DI
R235
2
DI
ZDT758
Q7B
7DI
VCC33
IO8
ICCIO33_P
2
R67
1K
DI
IO7
VCC18
ICCIO18_P
IO14
R148
2
DI
ICCIO18_N
VCCIO18
IO15
ICC_N
VCC_CORE
IO11
ICCIO33_N
VCCIO33
MachXO2 - ICCIO33 Current
C142, C143 to limit Vcc, Vccio
ramp rates to data sheet spec.
[4]
3
6
MachXO2 - ICCIO18 Current
5
4
4
3
5 +
R201
100
DI
6 -
9 -
10 +
ICC_P
R191
100
DI
DI
100
R185
R192
3_92K
DI
ICC_N
ICCIO33_N
ICCIO33_P
DI
100
R206
R197
2K
DI
3
VCC33
VCC33
C44
0_1uF
DI
U16B
C41
0_01uF
DI
R204
2K
DI
AD8604ARZ
7
C46
0_1uF
DI
U16C
AD8604ARZ
8
R190
3_92K
DI
C38
0_01uF
DI
ICC_Sense
[4]
[4]
2
ICCIO18_N
ICCIO18_P
DI
100
R184
R194
100
DI
Current Sense
ICCIO33_Sense
2
R193
3_92K
DI
Title
Size
B
Date:
2 -
3 +
12 +
13 -
VCC33
VCC33
U16A
AD8604ARZ
1
C105
AD8604ARZ
U16D
0_1uF
DI
14
R189
3_92K
DI
C91
0_01uF
DI
1
1
Sheet
ICCIO18_Sense
5
of
[4]
14
Rev
G
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Hillsboro, Oregon. 97124
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Power Current Sense
Project
Tuesday, June 26, 2012
MachXO2 Control Board
D
C
B
A
14
4
11
4
11
4
11
4
11
1
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MachXO2-4000HC Control Development Kit
User’s Guide
Figure 13. Configuration USB Port
DI
R63
0
R68
DI
0
R203
10k
Dm
R202
10k
R241
10k
2.2K
FT_EECS
FT_EECLK
FT_EEDATA
R240
1
2
DI
4
C29
18pF
VCC18FT
1
2
3
12k 1%
2
R56
2
2k2
1
C23
18pF
FT_EECS
FT_EECLK
FT_EEDATA
R199
1
C28
10u
L3
1
2
600ohm 500mA
4
3
VCC33
VCC33
1
X3
G1 G2
12MHZ
1
2
1
2
5
C32
DI
1
2
3
4
The USB interface draws no power from
the USB bus. It is self-powered.
VBUS
SHLD_Debug
0_01uF
R79 100K
DI
U21
CS
CLK
DI
DO
93LC56-SO8
VCC
NU
ORG
VSS
Dp
USB Port: CPLD Configuration & USB<->UART Communication
1
USB_MINI_B DI
VCC
2
3
4
5
VCC33
8
7
6
5
3
2
63
62
61
6
14
7
8
49
50
C104
0.1uF
4
9
3
12
37
64
C48
0.1uF
cc0402
FT2232H
C82
0.1uF
cc0402
VCC33
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
PWREN#
C85
0.1uF
cc0402
SUSPEND#
FTDI High-Speed USB
TEST
OSCO
OSCI
EECS
EECLK
EEDATA
REF
RESET#
DM
DP
VREGOUT
VREGIN
U20
FT2232HL
C144
4u7
C145
0.1uF
1
13
VCCIO
VCCIO
VCCIO
VCCIO
1
2
VCC33
C31
0.1uF
cc0402
3
16
17
18
19
21
22
23
24
26
27
28
29
30
32
33
34
38
39
40
41
43
44
45
46
48
52
53
54
55
57
58
59
36
60
C30
0.1uF
cc0402
J6
1
2
3
Pin 1 - PM is Selected
Pin 3 - XO2 is Selected
VBUS
Jumper_2way
DI
R205
4_7K
DI
R249
10k
VCC33
2
R36
R37
R38
R39
R78
R75
2
0 DI
0 DI
0 DI
0 DI
0 DI
0 DI
VCC33
C109
0_1uF
DI
2
16
5
8
13
3
10
11
U5
15
1
4
6
7
9
12
14
STG3693QTR
VCC
1S1
1S2
D1
D2
2S1
D3
2S2
D4
3S1
123SEL 3S2
4SEL
4S1
4S2
GND
R82
DI
DI
0 DI
0 DI
R84
4_7K
DI
R85
4_7K
DI
68 PM_TCK
XO2_TDI
PM_TDI
VCC33
XO2_TMS
PM_TMS
XO2_TDO
R65
4_7K
DI
1
[4]
R55
4_7K
DI
[4]
R54
4_7K
DI
PM_TCK
[7,13,14]
[4]
[4]
[13,14]
XO2_TCK
PM_TDO
[13]
1
Sheet
R66
4_7K
DI
6
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
[7,13,14]
XO2_TDO
XO2_TMS
PM_TMS
XO2_TDI
PM_TDI
R88
4_7K
DI
R89
4_7K
DI
68 XO2_TCK
0 DI
PM_TDO
0 DI
0 DI
0 DI
R70
R71
R87
0 DI
Tuesday, June 26, 2012
MachXO2 Control Board
Project
Configuration USB Port
USB_UART_TX [14]
USB_UART_RX [14]
R76
R62
R61
R80
R86
PM_TMS
XO2_TMS
PM_TDI
XO2_TDI
PM_TDO
XO2_TDO
PM_TCK
XO2_TCK
R83
0 DI
Title
Date:
Size
C
D
C
B
A
15
DD+
NC
GND
6
7
8
9
10
11
C27
0.1uF
2
1
CASE
CASE
CASE
CASE
MH1
MH2
C126
0.1uF
2
1
D
J5
C119
0.1uF
4
1
2
C
B
A
5
1
2
1
2
20
31
42
56
1
2
1
2
VCORE
VCORE
VCORE
GND
GND
GND
GND
GND
GND
GND
GND
1
5
11
15
25
35
47
51
1
2
VPHY
VPLL
10
AGND
1
2
1
2
2
1
2
1
2
1
2
1
2
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 14. Software, LED, Crystal, Header
D
C
B
A
[14]
[14]
[14]
[14]
5
LED
D1
VCC33
VMON10
VMON9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
CON40A
DNI
2x20x100mil
J4
RN1
RN2_4_470
DI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DI DI DI DI
XO2_GPIO_0
XO2_GPIO_1
XO2_GPIO_2
XO2_GPIO_3
XO2_GPIO_4
XO2_GPIO_5
XO2_GPIO_6
XO2_GPIO_7
VCC33
XO2_LED0
XO2_LED1
XO2_LED2
XO2_LED3
LED
D2
XO2 LEDs
LED LED
D4 D3
XO2_LED0
XO2_LED1
XO2_LED2
XO2_LED3
2x20 Header
VCC12
[14] XO2_GPIO_0
[14] XO2_GPIO_1
[14] XO2_GPIO_2
[14] XO2_GPIO_3
[14] XO2_GPIO_4
[14] XO2_GPIO_5
[14] XO2_GPIO_6
[14] XO2_GPIO_7
TDO_HDR
[13]
[13]
TDI_HDR
[6,13,14] TMS_HDR
[6,13,14] TCK_HDR
[4] VMON9
[4] VMON10
5
4
1
2
DI
[4]
[4,14]
[4,14]
[14]
[14]
[14]
[8,14]
[8,14]
[8,14]
3
4
XO2 Global Reset
S1
Reset Push-Button Switch
SCL
SDA
XO2_GPIO_10
XO2_GPIO_9
XO2_GPIO_8
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_OUT
HVOUT2
[4]
PM_OUT14
PM_PLDCLK [4,14]
PM_MCLK
[4,14]
HVOUT1
XO2_GPIO_11 [14]
XO2_ADC_IN [14]
[4,14] XO2_RESETn
VCC18
XO2_ADC_IN
XO2_GPIO_11
HVOUT1
HVOUT2
PM_OUT14
PM_PLDCLK
PM_MCLK
SCL
SDA
XO2_GPIO_10
XO2_GPIO_9
XO2_GPIO_8
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_OUT
4
R128
10K
VCC33
DI
C63
0_1uF
DI
3
24 MHz Crystal
X2
DI
2
HCM49 24.000MABJ-UT
1
DI
C4
12pF
18pF = 12pF + Ground Plane ( 6pF )
EOH
R1
X1
10K DI
25 MHz OSC
1
2
R4
1K
C11
12pF
DI
VCC
OUTPUT
CTS-CB3LV-3C-25MHz
GND
3
[14]
[14]
[14]
[14]
DI
4
3
SW0
SW1
SW2
SW3
IO3
X_1
IO2
X_2
SW0
SW1
SW2
SW3
X_1
[14]
[14]
2
R126
10K
DI
VCC33
R127
10K
DI
X_2
4-DIP Switch
R2
1M
DI
R3
0
DNI
VCC33
C8
0_1uF
DI
2
R125
10K
DI
R124
10K
DI
1
2
3
4
SW1
DI
CT1934MS-ND
8
7
6
5
Tuesday, June 26, 2012
1
7
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
1
Sheet
MachXO2 Control Board
Project
SW, LED, Crystal, Header
SWDIP_4
Title
Size
B
Date:
D
C
B
A
16
8
7
6
5
1
2
3
4
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 15. Memory LPDDR, SD, SPI
D
C
B
A
5
4MBit SPI
C74
0_1uF
DI
VCC33
VCC33
8
7
3
4
8
7
3
4
U14
1
6
5
2
U1
DAT2
CD/DAT3
CMD
CLK
DAT0
DAT1
microSD Socket
4
4
VSS
VDD
XO2_SPI_CS0
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_OUT
XO2_SPI_CS0
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_OUT
Package: SOIC8 (WIDE)
S
C
D
Q
1
6
5
2
AT25DF041A-SH-B
Vcc
Reset
W
Vss
U15
S
C
D
Q
AT25DF041A-MH-B
Vcc
Reset
W
Vss
1
2
3
5
7
8
Package: UDFN
uSD_DAT2
uSD_DAT3
uSD_CMD
uSD_CLK
uSD_DAT0
uSD_DAT1
Micro SD Card Socket
[14] uSD_DAT2
[14] uSD_DAT3
[14] uSD_CMD
uSD_CLK
[14]
[14] uSD_DAT0
[14] uSD_DAT1
5
C81
0_1uF
DI
VCC33
XO2_SPI_CS0
XO2_SPI_CLK
XO2_SPI_IN
XO2_SPI_OUT
R234
1K
DI
VCC33
4
6
[14]
[7,14]
[7,14]
[7,14]
3
3
LPDDR_A0
LPDDR_A1
LPDDR_A2
LPDDR_A3
LPDDR_A4
LPDDR_A5
LPDDR_A6
LPDDR_A7
LPDDR_A8
LPDDR_A9
LPDDR_A10
LPDDR_A11
LPDDR_A12
C71
0_001uF
DI
2
C79
0_1uF
DI
J8
J9
K7
K8
K2
K3
J1
J2
J3
H1
J7
H2
H3
C75
0_1uF
DI
LPDDR_A0
LPDDR_A1
LPDDR_A2
LPDDR_A3
LPDDR_A4
LPDDR_A5
LPDDR_A6
LPDDR_A7
LPDDR_A8
LPDDR_A9
LPDDR_A10
LPDDR_A11
LPDDR_A12
H7
G2
G3
G1
G9
G8
LPDDR_CK
LPDDR_CKn
LPDDR_CKE
LPDDR_RASn
LPDDR_CASn
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CK
CK#
CKE
CS#
RAS#
CAS#
BA0
BA1
WE#
NC
NC
NC
VCC18
9
8
10
7
11
6
5
12
4
13
3
14
2
15
16
1
RN1_8_10K DNI
F7
F3
D9
G7
H8
H9
LPDDR_WEn
LPDDR_BA0
LPDDR_BA1
LPDDR_CSn
C72
0_01uF
DI
LPDDR - 128Mb (4 Meg x 4 banks x 8 data)
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14] LPDDR_CK
[14] LPDDR_CKn
[14] LPDDR_CKE
[14] LPDDR_CSn
[14] LPDDR_RASn
[14] LPDDR_CASn
[14] LPDDR_BA0
[14] LPDDR_BA1
[14] LPDDR_WEn
R186
0
DI
LPDDR_DQ0
LPDDR_DQ1
LPDDR_DQ2
LPDDR_DQ3
LPDDR_DQ4
LPDDR_DQ5
LPDDR_DQ6
LPDDR_DQ7
RN2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDM
UDQS
LDM
LDQS
Date:
Size
B
Title
A8
B7
B8
C7
C8
D7
D8
E7
E3
D2
D3
C2
C3
B2
B3
A2
F2
E2
10K DI
10K DI
1
LPDDR_DQ0
LPDDR_DQ0
LPDDR_DQ1
LPDDR_DQ1
LPDDR_DQ2
LPDDR_DQ2
LPDDR_DQ3
LPDDR_DQ3
LPDDR_DQ4
LPDDR_DQ4
LPDDR_DQ5
LPDDR_DQ5
LPDDR_DQ6
LPDDR_DQ6
LPDDR_DQ7
LPDDR_DQ7
9
8
7
10
6
11
5
12
4
13
14
3
15
2
16
1
RN1_8_10K DI
RN3
R158
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
VCC18
LPDDR_LDM [14]
LPDDR_LDQS [14]
R159
LPDDR_LDM
LPDDR_LDQS
Lower Byte Mask & Strobe
F8
E8
MT46H16M16LFBF
U6
VCC18
Memory LPDDR, SD, SPI
Project
Tuesday, June 26, 2012
1
Sheet
MachXO2 Control Board
8
of
14
R ev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
Empty External Pull-UP resistors. The internal XO2 resistors are used for bias.
2
D
C
B
A
17
A9
F9
K9
A7
B1
C9
D1
E9
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
A1
F1
K1
A3
B9
C1
E1
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 16. Video Input 1
D
C
B
A
5
C5
C6
C4
C1
C2
C3
23
24
22
20
21
19
17
18
16
14
15
12
13
11
9
10
8
6
7
4
5
3
1
2
DDC_CLK
DDC_DATA
[10,11]
[10,11]
[14]
Hot_Plug_Video
DI
Hot_Plug_Video
0
[14]
[14]
[14]
[14]
Camera Link - RX
(Frame Grabber)
SERTC1+
SERTC1SERTFG1SERTFG1+
MDR_TX_OUT0_N_1
MDR_TX_OUT0_P_1
MDR_TX_OUT1_N_1
MDR_TX_OUT1_P_1
MDR_TX_OUT2_N_1
MDR_TX_OUT2_P_1
MDR_TX_CLKOUT_N_1
MDR_TX_CLKOUT_P_1
MDR_TX_OUT3_N_1
MDR_TX_OUT3_P_1
TMDS_1_CLK_P
TMDS_1_CLK_N
TMDS_1_DATA0_N
TMDS_1_DATA0_P
R248
TMDS_1_DATA1_N
TMDS_1_DATA1_P
DDC_CLK
DDC_DATA
TMDS_1_DATA2_N
TMDS_1_DATA2_P
79
82
83
84
80
81
TI_AVDD_1
85
86
87
88
89
90
91
92
93
94
95
99
96
2
9
100
1
4
7
3
PDN_1
PDON_1
6
38
67
5
39
68
18
29
43
57
78
19
28
45
58
76
97
4
AGND
Rx2P
Rx2N
Rx1P
Rx1N
AVDD
AGND
AVDD
AGND
AVDD
AGND
Rx0P
Rx0N
AGND
RxCP
RxCN
AVDD
R-in
G-in
B-in
Clk-in
EXT_RES
CTL1_1
U2
RSVD (Tie high)
OCK_INV
DFO
PIXS
STAGN
ST
PDN
PDON
DVDD
DVDD
DVDD
DGND
DGND
DGND
OVDD
OVDD
OVDD
OVDD
OVDD
OGND
OGND
OGND
OGND
OGND
PVDD
PGND
DNI
TFP401A
0
98
TXIN7_1 R8
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
QO23
QO22
QO21
QO20
QO19
QO18
QO17
QO16
QE15
QE14
QE13
QE12
QE11
QE10
QE9
QE8
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
QE7
QE6
QE5
QE4
QE3
QE2
QE1
QE0
QO7
QO6
QO5
QO4
QO3
QO2
QO1
QO0
CTL3
CTL2
CTL1
ODCK
DE
SCDT
VSYNC
HSYNC
37
36
35
34
33
32
31
30
77
75
74
73
72
71
70
69
27
26
25
24
23
22
21
20
66
65
64
63
62
61
60
59
17
16
15
14
13
12
11
10
R
TXIN1_1
TXIN0_1
TXIN17_1
TXIN16_1
TXIN11_1
TXIN10_1
TXIN5_1
TXIN27_1
G
TXIN3_1
TXIN2_1
TXIN24_1
TXIN22_1
TXIN21_1
TXIN20_1
TXIN19_1
TXIN23_1
42
41
40
44
TXIN15_1
TXIN14_1
TXIN18_1
CTL3_1
CTL2_1
CTL1_1
TXCLKIN_1
B
46
SCDT_1
TXIN6_1
TXIN4_1
TXIN13_1
TXIN12_1
TXIN9_1
TXIN8_1
TXIN26_1
TXIN25_1
47
48
56
55
54
53
52
51
50
49
8
DVDD_1
IO5
IO4
R27
DI
470
10K
DNI
DNI
NS_STB_1
OCK_INV_1
ST_1
3
(2) Source
(3) Drain
TOP Package View
SOT-23
(1) Gate
3
TXCLKIN_1
TXIN27_1
TXIN26_1
TXIN25_1
TXIN24_1
TXIN23_1
TXIN22_1
TXIN21_1
TXIN20_1
TXIN19_1
TXIN18_1
TXIN17_1
TXIN16_1
TXIN15_1
TXIN14_1
TXIN13_1
TXIN12_1
TXIN11_1
TXIN10_1
TXIN9_1
TXIN8_1
TXIN7_1
TXIN6_1
TXIN5_1
TXIN4_1
TXIN3_1
TXIN2_1
TXIN1_1
TXIN0_1
32
31
50
30
28
27
25
24
23
22
20
19
18
16
15
14
12
11
10
8
7
6
4
3
2
56
55
54
52
51
VCC33
PWRDWN_1
LVDS Translator
3
D5
LED_Green
PDN_1
OCK_INV_1
Q1
BSS138LT1
CTL2_1
DI
DI
PDON_1
CTL3_1
10K
DI
NS_STB_1
PWRDWN_1
DI
10K
DI
DNI
10K
DI
DFO_1
0
R20
DVDD_1 R21
10K
DI
STAGN_1
PIXS_1
0
R18
10K
DI
R5
LED will be ON
when link is
active.
(SCDT high)
R233
DI
SCDT_1
R236
10K
DI
R22
10K
2
R244
10K
10K
10K
1
R19
4
ODCK opposite edge from Video Source 2
R237
R242
R239
R6
Supporting Circuits
TI_PVDD_1
TI_OVDD_1
DVDD_1
OCK_INV_1
DFO_1
PIXS_1
STAGN_1
ST_1
DVDD_1
TMDS_1_CLK_P
TMDS_1_CLK_N
TMDS_1_DATA0_P
TMDS_1_DATA0_N
TMDS_1_DATA1_P
TMDS_1_DATA1_N
TMDS_1_DATA2_P
TMDS_1_DATA2_N
DVI - TMDS Decoder
Video Input Source 1 : DVI or MDR for direct 7:1LVDS
DVI Connector
DVI-Integrated
TMDS_Data2TMDS_Data2+
TMDS_Data4TMDS_Data4+
TMDS_Data2/4_Shield
DDC_Clock
DDC_Data
Analog_Vertical_Sync
TMDS_Data1TMDS_Data1+
TMDS_Data1/3_Shield
TMDS_Data3TMDS_Data3+
+5V_Power
GND(for +5V)
Hot_Plug_Detect
TMDS_Data0TMDS_Data0+
TMDS_Data0/5_Shield
TMDS_Data5TMDS_Data5+
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-
Analog_Red
Analog_Green
Analog_Blue
J2
27
28
1
14
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
13
26
Analog_Ground_1
Analog_Ground_2
Analog_Horizontal_Sync
DVI_I
MDR Connector
J1
inner shield1
inner shield2
X0X0+
X1X1+
X2X2+
XCLKXCLK+
X3X3+
SerTC+
SerTCSerTFGSerTFG+
CC1CC1+
CC2+
CC2CC3CC3+
CC4+
CC4inner shield3
inner shield4
mount-L
mount-R
10226-1A10PE-ND
3M 10226-1210VE
5
TxIN27
TxIN26
TxIN25
TxIN24
TxIN23
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxCLKIN
PWRDWN
DS90CR287
TxOUT0N
TxOUT0P
TxOUT1N
TxOUT1P
TxOUT2N
TxOUT2P
TxOUT3N
TxOUT3P
TxCLKOUTN
TxCLKOUTP
LVDSVCC
2
48
47
TX_OUT1_N_1
TX_OUT1_P_1
TX_OUT0_N_1
TX_OUT0_P_1
TX_OUT1_N_1
TX_OUT1_P_1
TX_OUT0_N_1
TX_OUT0_P_1
R229
R228
R231
R230
0
0
0
0
DI
DI
DI
DI
DI
DI
Resistor MUX
46
45
0
0
DNI
DNI
DNI
DNI
R227
R226
0
0
DNI
DNI
TX_OUT2_N_1
TX_OUT2_P_1
MDR_TX_OUT0_N_1 R218
MDR_TX_OUT0_P_1 R217
0
0
DNI
DNI
TX_OUT2_N_1
TX_OUT2_P_1
42
41
MDR_TX_OUT1_N_1 R216
MDR_TX_OUT1_P_1 R215
0
0
DI
DI
MDR_TX_OUT2_N_1 R214
MDR_TX_OUT2_P_1 R213
10uF
DI
0_1uF
DI
C141
0_01uF
DI
C136
0_001uF
DI
C135
C20
0_1uF
DI
C19
0_01uF
DI
C18
0_001uF
DI
C17
C22
C112
0_01uF
DI
C15
0_001uF
DI
C14
Tuesday, June 26, 2012
1
1
XO2_IN3_1_N
XO2_IN3_1_P
XO2_IN2_1_N
XO2_IN2_1_P
XO2_IN1_1_N
XO2_IN1_1_P
XO2_IN0_1_N
XO2_IN0_1_P
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
XO2_CLKIN_1_N [14]
XO2_CLKIN_1_P [14]
9
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
Sheet
MachXO2 Control Board
Project
Video Input 1
0_1uF
DI
Date:
Size
C
Title
10uF
DI
NS_PVCC_1
10uF
DI
NS_LVCC_1
C140
TI_PVDD_1
DNI
DNI
DI
DI
C125
C113
0
0
0
0
0_001uF
DI
C137
C5
0_001uF
DI
0
0
0
0
TX_OUT3_N_1
TX_OUT3_P_1
C124
C6
0_001uF
DI
C16
0_01uF
DI
MDR_TX_OUT3_N_1 R210
MDR_TX_OUT3_P_1 R209
R223
R222
TX_CLKOUT_N_1
TX_CLKOUT_P_1
0_01uF
DI
C115
0_01uF
DI
C21
0_1uF
DI
MDR_TX_CLKOUT_N_1 R212
MDR_TX_CLKOUT_P_1 R211
TX_OUT3_N_1
TX_OUT3_P_1
VCC33
TX_CLKOUT_N_1 R225
TX_CLKOUT_P_1 R224
38
37
NS_STB_1
DVDD_1
NS_PVCC_1
NS_LVCC_1
40
39
36
43
49
44
34
33
35
1
9
17
26
C123
5
13
21
29
53
0_1uF
DI
TI_AVDD_1
10uF
DI
C121
0_1uF
DI
10uF
DI
TI_OVDD_1
10uF
DI
DVDD_1
C122
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
PLLGND
PLLGND
PLLVCC
LVDSGND
LVDSGND
LVDSGND
U19
2
D
C
B
A
18
R-even
R-odd
G-even
G-odd
B-even
B-odd
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 17. Video Input 2
D
C
B
A
5
C5
C6
C4
C1
C2
C3
23
24
22
20
21
19
17
18
16
14
15
12
13
11
9
10
8
6
7
4
5
3
1
2
DDC_CLK
DDC_DATA
[9,11]
[9,11]
[14]
Hot_Plug_Video
DI
Hot_Plug_Video
0
TMDS_2_CLK_P
TMDS_2_CLK_N
TMDS_2_DATA0_N
TMDS_2_DATA0_P
R247
TMDS_2_DATA1_N
TMDS_2_DATA1_P
DDC_CLK
DDC_DATA
TMDS_2_DATA2_N
TMDS_2_DATA2_P
79
80
81
TI_AVDD_2
85
86
82
83
84
87
88
89
90
91
92
95
93
94
96
99
2
9
100
1
4
7
3
PDN_2
PDON_2
6
38
67
5
39
68
18
29
43
57
78
19
28
45
58
76
97
4
AGND
Rx2P
Rx2N
AVDD
AGND
AVDD
Rx1P
Rx1N
Rx0P
Rx0N
AGND
AVDD
AGND
AGND
RxCP
RxCN
AVDD
R-in
G-in
B-in
Clk-in
EXT_RES
DNI
CTL2_2
CTL1_2
U9
RSVD (Tie high)
OCK_INV
DFO
PIXS
STAGN
ST
PDN
PDON
DVDD
DVDD
DVDD
DGND
DGND
DGND
OVDD
OVDD
OVDD
OVDD
OVDD
OGND
OGND
OGND
OGND
OGND
PVDD
PGND
DNI
DI
TFP401A
0
98
0
0
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
QO23
QO22
QO21
QO20
QO19
QO18
QO17
QO16
QE15
QE14
QE13
QE12
QE11
QE10
QE9
QE8
QO15
QO14
QO13
QO12
QO11
QO10
QO9
QO8
QE7
QE6
QE5
QE4
QE3
QE2
QE1
QE0
QO7
QO6
QO5
QO4
QO3
QO2
QO1
QO0
ODCK
DE
CTL3
CTL2
CTL1
OCK_INV_2
SCDT
VSYNC
HSYNC
PDN_2
PWRDWN_2
PDON_2
DI
DI
DI
DI
10K
10K
10K
10K
10K
R115
R243
R118
R116
R117
R120
10K
10K
10K
10K
10K
10K
DNI
DNI
DI
DI
DI
DI
DI
NS_STB_2
OCK_INV_2
ST_2
STAGN_2
PIXS_2
DFO_2
NS_STB_2
R97
R94
R119
4
DVDD_2 R121
CTL3_2
R100
R103
TXIN7_2 R105
Supporting Circuits
TI_PVDD_2
TI_OVDD_2
DVDD_2
OCK_INV_2
DFO_2
PIXS_2
STAGN_2
ST_2
DVDD_2
TMDS_2_CLK_P
TMDS_2_CLK_N
TMDS_2_DATA0_P
TMDS_2_DATA0_N
TMDS_2_DATA1_P
TMDS_2_DATA1_N
TMDS_2_DATA2_P
TMDS_2_DATA2_N
DVI - TMDS Decoder
Video Input Source 2 : DVI or MDR for direct 7:1LVDS
DVI Connector
DVI-Integrated
TMDS_Data2TMDS_Data2+
TMDS_Data4TMDS_Data4+
TMDS_Data2/4_Shield
DDC_Clock
DDC_Data
Analog_Vertical_Sync
TMDS_Data1TMDS_Data1+
TMDS_Data1/3_Shield
+5V_Power
GND(for +5V)
TMDS_Data3TMDS_Data3+
Hot_Plug_Detect
TMDS_Data0TMDS_Data0+
TMDS_Data0/5_Shield
TMDS_Data5TMDS_Data5+
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-
Analog_Red
Analog_Green
Analog_Blue
J10
MDR_TX_OUT0_N_2
MDR_TX_OUT0_P_2
MDR_TX_OUT1_N_2
MDR_TX_OUT1_P_2
MDR_TX_OUT2_N_2
MDR_TX_OUT2_P_2
MDR_TX_CLKOUT_N_2
MDR_TX_CLKOUT_P_2
MDR_TX_OUT3_N_2
MDR_TX_OUT3_P_2
1
14
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
13
26
R101
Camera Link - RX
(Frame Grabber)
SERTC2+ [14]
SERTC2- [14]
SERTFG2- [14]
SERTFG2+ [14]
27
28
Analog_Ground_1
Analog_Ground_2
Analog_Horizontal_Sync
DVI_I
MDR Connector
J13
inner shield1
inner shield2
X0X0+
X1X1+
X2X2+
XCLKXCLK+
X3X3+
SerTC+
SerTCSerTFGSerTFG+
CC1CC1+
CC2+
CC2CC3CC3+
CC4+
CC4inner shield3
inner shield4
mount-L
mount-R
10226-1A10PE-ND
3M 10226-1210VE
5
37
36
35
34
33
32
31
30
77
75
74
73
72
71
70
69
27
26
25
24
23
22
21
20
66
65
64
63
62
61
60
59
17
16
15
14
13
12
11
10
R
TXIN1_2
TXIN0_2
TXIN17_2
TXIN16_2
TXIN11_2
TXIN10_2
TXIN5_2
TXIN27_2
G
TXIN3_2
TXIN2_2
TXIN24_2
TXIN22_2
TXIN21_2
TXIN20_2
TXIN19_2
TXIN23_2
B
TXCLKIN_2
TXIN6_2
TXIN4_2
TXIN13_2
TXIN12_2
TXIN9_2
TXIN8_2
TXIN26_2
TXIN25_2
CTL3_2
CTL2_2
CTL1_2
56
55
54
53
52
51
50
49
42
41
40
44
SCDT_2
TXIN15_2
TXIN14_2
TXIN18_2
8
47
48
46
DVDD_2
IO17
IO16
R114
DI
470
LED will be ON
when link is
active.
(SCDT high)
SCDT_2
1
3
PWRDWN_2
TXIN27_2
TXIN26_2
TXIN25_2
TXIN24_2
TXIN23_2
TXIN22_2
TXIN21_2
TXIN20_2
TXIN19_2
TXIN18_2
TXIN17_2
TXIN16_2
TXIN15_2
TXIN14_2
TXIN13_2
TXIN12_2
TXIN11_2
TXIN10_2
TXIN9_2
TXIN8_2
TXIN7_2
TXIN6_2
TXIN5_2
TXIN4_2
TXIN3_2
TXIN2_2
TXIN1_2
TXIN0_2
32
31
50
30
28
27
25
24
23
22
20
19
18
16
15
14
12
11
10
8
7
6
4
3
2
56
55
54
52
51
VCC33
TXCLKIN_2
LVDS Translator
D11
LED_Green
3
Q8
BSS138LT1
2
(2) Source
(3) Drain
TOP Package View
SOT-23
(1) Gate
3
TxIN27
TxIN26
TxIN25
TxIN24
TxIN23
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxIN16
TxIN15
TxIN14
TxIN13
TxIN12
TxIN11
TxIN10
TxIN9
TxIN8
TxIN7
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN1
TxIN0
TxCLKIN
PWRDWN
DS90CR287
TxOUT0N
TxOUT0P
TxOUT1N
TxOUT1P
TxOUT2N
TxOUT2P
TxOUT3N
TxOUT3P
TxCLKOUTN
TxCLKOUTP
LVDSVCC
2
Resistor MUX
42
41
46
45
48
47
TX_OUT3_N_2
TX_OUT3_P_2
TX_OUT2_N_2
TX_OUT2_P_2
TX_OUT1_N_2
TX_OUT1_P_2
TX_OUT0_N_2
TX_OUT0_P_2
TX_OUT3_N_2
TX_OUT3_P_2
TX_OUT2_N_2
TX_OUT2_P_2
TX_OUT1_N_2
TX_OUT1_P_2
TX_OUT0_N_2
TX_OUT0_P_2
R102
R99
R108
R107
R221
R220
R112
R111
0
0
0
0
0
0
0
0
0
0
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
C132
0_1uF
DI
C116
0_01uF
DI
C34
0_001uF
DI
C139
C118
0_1uF
DI
C45
0_01uF
DI
C117
0_001uF
DI
C114
MDR_TX_OUT2_N_2 R109
MDR_TX_OUT2_P_2 R106
MDR_TX_OUT1_N_2 R208
MDR_TX_OUT1_P_2 R207
MDR_TX_OUT0_N_2 R113
MDR_TX_OUT0_P_2 R110
0
0
0
0
0
0
0
0
0
0
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
10uF
DI
C129
0_1uF
DI
C42
0_1uF
DI
C133
0_01uF
DI
C40
0_01uF
DI
C138
0_001uF
DI
C39
0_001uF
DI
C131
MDR_TX_CLKOUT_N_2 R96
MDR_TX_CLKOUT_P_2 R92
C43
C111
C110
0_01uF
DI
C36
0_001uF
DI
C37
Tuesday, June 26, 2012
1
1
XO2_IN1_2_N
XO2_IN1_2_P
XO2_IN0_2_N
XO2_IN0_2_P
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
XO2_IN2_2_N
XO2_IN2_2_P
XO2_CLKIN_2_N [14]
XO2_CLKIN_2_P [14]
XO2_IN3_2_N
XO2_IN3_2_P
10
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
Sheet
MachXO2 Control Board
Project
Video Input 2
0_1uF
DI
Date:
Size
C
Title
10uF
DI
NS_PVCC_2
NS_LVCC_2
10uF
DI
TI_PVDD_2
MDR_TX_OUT3_N_2 R104
MDR_TX_OUT3_P_2 R98
TX_CLKOUT_N_2 R95
TX_CLKOUT_P_2 R93
38
37
NS_STB_2
DVDD_2
NS_PVCC_2
NS_LVCC_2
TX_CLKOUT_N_2
TX_CLKOUT_P_2
VCC33
40
39
36
43
49
44
34
33
35
1
9
17
26
C130
0_001uF
DI
5
13
21
29
53
C128
0_01uF
DI
TI_AVDD_2
C127
0_1uF
DI
C120
10uF
DI
TI_OVDD_2
10uF
DI
DVDD_2
10uF
DI
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
PLLGND
PLLGND
PLLVCC
LVDSGND
LVDSGND
LVDSGND
U18
2
D
C
B
A
19
R-even
R-odd
G-even
G-odd
B-even
B-odd
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 18. Video Output
D
C
B
A
5
J8
inner shield1
inner shield2
X0X0+
X1X1+
X2X2+
XCLKXCLK+
X3X3+
SerTC+
SerTCSerTFGSerTFG+
CC1CC1+
CC2+
CC2CC3CC3+
CC4+
CC4inner shield3
inner shield4
mount-L
mount-R
3M 10226-1210VE
10226-1A10PE-ND
27
28
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
26
0 R170
0 R167
RX_IN0_N
RX_IN0_P
R135
100
SM_R_0603
RX_IN1_N
0 R9
RX_IN2_N
RX_IN1_P
0 R12
0 R171
R130
100
SM_R_0603
DI
DI
0 R17
0 R174
RX_IN3_N
RX_IN2_P
DI
0 R34
0 R13
RX_CLKIN_N
RX_IN3_P
RX_IN0_N
RX_IN0_P
11
12
9
10
RxIN0N
RxIN0P
RxIN1N
RxIN1P
RxIN2N
RxIN2P
RxIN3N
RxIN3P
RxCLKINN
RxCLKINP
PWRDWN
LVDSVCC
LVDSGND
LVDSGND
LVDSGND
PLLVCC
PLLGND
PLLGND
RxOUT27
RxOUT26
RxOUT25
RxOUT24
RxOUT23
RxOUT22
RxOUT21
RxOUT20
RxOUT19
RxOUT18
RxOUT17
RxOUT16
RxOUT15
RxOUT14
RxOUT13
RxOUT12
RxOUT11
RxOUT10
RxOUT9
RxOUT8
RxOUT7
RxOUT6
RxOUT5
RxOUT4
RxOUT3
RxOUT2
RxOUT1
RxOUT0
RxCLKOUT
7
6
5
3
2
1
55
54
53
51
50
49
47
46
45
43
42
41
39
38
37
35
34
33
32
30
29
27
RXCLKOUT
RXOUT27
RXOUT26
RXOUT25
RXOUT24
RXOUT23
RXOUT22
RXOUT21
RXOUT20
RXOUT19
RXOUT18
RXOUT17
RXOUT16
RXOUT15
RXOUT14
RXOUT13
RXOUT12
RXOUT11
RXOUT10
RXOUT9
RXOUT8
RXOUT7
RXOUT6
RXOUT5
RXOUT4
RXOUT3
RXOUT2
RXOUT1
RXOUT0
3
26
RXOUT1
RXOUT0
RXOUT17
RXOUT16
RXOUT11
RXOUT10
RXOUT5
RXOUT27
RXOUT3
RXOUT2
RXOUT24
RXOUT22
50
51
52
53
54
55
58
59
60
61
62
63
36
37
38
39
40
41
42
43
44
45
46
47
RXOUT18
3
5
4
2
57
56
RXOUT15
RXOUT14
0 R14
0 R131
RXOUT21
RXOUT20
RXOUT19
RXOUT23
RXOUT6
RXOUT4
RXOUT13
RXOUT12
RXOUT9
RXOUT8
RXOUT26
RXOUT25
TMDS - DVI Decoder
RXCLKOUT
DI
DI
VREF
13
35
IO13
IO10
DKEN
6
7
8
4
RX_IN1_N
RX_IN1_P
15
16
LVDS Translator
RX_IN2_N
RX_IN2_P
19
20
25
17
18
RX_IN3_N
RX_IN3_P
PWRDWN
23
8
14
21
13
RX_CLKIN_N
RX_CLKIN_P
NS_LVCC
NS_PVCC
22
24
VCC
VCC
VCC
VCC
ISEL
15
14
NS_DVDD
31
40
48
56
CTL3
CTL2
CTL1
10
9
BSEL
DSEL
EDGE
PDN
GND
GND
GND
GND
GND
MDR_RX_IN0_N
MDR_RX_IN0_P
4
28
36
44
52
MDR_RX_IN1_N
MDR_RX_IN1_P
RX_CLKIN_P
R129
100
SM_R_0603
0 R169
0 R168
0 R23
0 R11
0 R10
U10
DNI
DNI
DS90CR288A
DNI
DNI
MDR_RX_IN3_N
MDR_RX_IN3_P
3
Q3
BSS138LT1
2
(2) Source
(3) Drain
TOP Package View
SOT-23
(1) Gate
3
VCC33
MDR_RX_IN2_N
MDR_RX_IN2_P
470
0 R172
0 R173
MDR_RX_CLKOUT_N
MDR_RX_CLKOUT_P
Supporting Circuits
DVDD
DI
0 R16
0 R15
R64
LED will be OFF when
a powered receiver is
attached to DVI.
(MSEN low)
DNI
DNI
CTL2
MSEN
D6
LED_Green
DNI
DNI
DI
BSEL
RXOUT7 R50
DVDD
PWRDWN
PDN
VREF
DI
DI
DI
DI
10K
10K
DKEN
10K
10K
EDGE
R43
R132
DI
DI
R46
R32
10K
ISEL
10K
DSEL
R47
CTL1
R7
DI
DI
CTL3
DI
EDGE
0
DI
10K
DNI
10K
0
R49
10K
R45
R51
R44
R48
4
R123
10K
DI
0 R29
0 R25
0
1
DNI
DNI
DI
DI
R133
100
SM_R_0603
DI
R134
100
SM_R_0603
DI
DI
DI
DI
Video Output : DVI or MDR for direct 7:1LVDS
Resistor De-MUX
[14] XO2_OUT0_N
[14] XO2_OUT0_P
[14] XO2_OUT1_N
[14] XO2_OUT1_P
[14] XO2_OUT2_N
[14] XO2_OUT2_P
[14] XO2_OUT3_N
[14] XO2_OUT3_P
[14] XO2_CLKOUT_N
[14] XO2_CLKOUT_P
MDR Connector
MDR_RX_IN0_N
MDR_RX_IN0_P
MDR_RX_IN1_N
MDR_RX_IN1_P
MDR_RX_IN2_N
MDR_RX_IN2_P
MDR_RX_CLKOUT_N
MDR_RX_CLKOUT_P
MDR_RX_IN3_N
MDR_RX_IN3_P
[14] SERTC+
[14] SERTC[14] SERTFG[14] SERTFG+
Camera Link - TX
(Camera)
5
U3
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
IDCKP
IDCKN
VSYNC
HSYNC
DE
VREF
EDGE/HTPLG
DKEN
ISEL/RSTN
CTL3/A3/DK3
CTL2/A2/DK2
CTL1/A1/DK1
2
R/HVSync
G/CTL1
B/CTL3:2
Clk Out
TGND
TX2P
TX2N
TVDD
TX1P
TX1N
TX0P
TX0N
TGND
TVDD
TXCP
TXCN
TGND
TFADJ
PVDD
DVDD
DVDD
DVDD
PGND
DGND
DGND
DGND
RESERVED (Tie to GND)
N/C
MSEN/PO1
1
4
5
3
1
2
C51
0_001uF
DI
C50
C1
C2
C3
C4
0_1uF
DI
C61
0_01uF
DI
C56
0_001uF
DI
C55
C5
C6
C13
TI_PVDD
10uF
DI
C9
0_1uF
DI
C10
0_01uF
DI
C52
0_001uF
DI
C7
NS_LVCC
10uF
DI
0_1uF
DI
C64
0_01uF
DI
C2
0_001uF
DI
C1
NS_PVCC
C3
Tuesday, June 26, 2012
1
DVI-Integrated
TMDS_Data2/4_Shield
TMDS_Data2TMDS_Data2+
TMDS_Data4TMDS_Data4+
DDC_Clock
DDC_Data
Analog_Vertical_Sync
TMDS_Data1TMDS_Data1+
TMDS_Data1/3_Shield
TMDS_Data3TMDS_Data3+
+5V_Power
GND(for +5V)
Hot_Plug_Detect
TMDS_Data5TMDS_Data5+
TMDS_Data0/5_Shield
TMDS_Data0TMDS_Data0+
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-
Analog_Horizontal_Sync
Analog_Red
Analog_Green
Analog_Blue
DVI_I
Analog_Ground_1
Analog_Ground_2
11
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
Sheet
MachXO2 Control Board
Project
Video Output
10uF
DI
Title
Date:
Size
C
J3
TMDS - DVI Connector
DNI
VCC5
10K
TMDS_DATA2_N
TMDS_DATA2_P
R246
TMDS_DATA2_P
TMDS_DATA2_N
TI_TVDD
31
30
32
29
DNI
6
7
8
DDC_CLK
DDC_DATA
10K
DDC_CLK
DDC_DATA
[9,10]
[9,10]
R245
TMDS_DATA0_P
TMDS_DATA0_N
TMDS_DATA1_P
TMDS_DATA1_N
26
23
25
24
9
10
11
TMDS_CLK_P
TMDS_CLK_N
TI_TVDD
20
22
21
TMDS_DATA1_N
TMDS_DATA1_P
28
27
R31
19
12
13
16
510, 1%
SM_R_0603
C134
[14]
0_1uF Hot_Plug_Video
DI
14
15
DVDD
TI_PVDD
17
18
1
12
33
17
18
19
TMDS_DATA0_N
TMDS_DATA0_P
16
48
64
0_001uF
DI
C26
C12
0_01uF
DI
23
24
20
21
C25
C24
0_001uF
DI
C57
TMDS_CLK_P
TMDS_CLK_N
34
MSEN
22
0_01uF
DI
11
C59
C58
0_01uF
DI
0_1uF
DI
VCC33
49
0_1uF
DI
BSEL/SCL
DSEL/SDA
PDN
TFP410
C60
TI_TVDD
10uF
DI
C62
0_1uF
DI
DVDD
10uF
DI
C49
NS_DVDD
10uF
DI
2
D
C
B
A
20
C69
0_1uF
DI
1
2
VCC33
R147
2_2K
DI
C70
DI
10uF
DI
10K
VCC33
C47
0_1uF
DI
680K
R154 0
R160 DI
-
5
Microphone
U8
TERM1
R150 DI
3
4
4
AUDIO_SIG
AUDIO_SIG
AUDIO_IN
[14]
R161
0
DNI
Optional Bypass
1
AUDIO_IN
3
3
AUDIO_OUT
AUDIO_OUT
PWM Analog Signal Output
[14]
R151
2
2
2
VCC5
DI
R145
330
R146
100
DI
R136
100
DI
Q4
2N2369A
DI
2
3
1
PHONEJACK STEREO
J12
10K
DI
3
1
TERM2
DI
10uF
AUDIO_SIG
U13
MCP6L71R
4
Title
Size
B
Date:
D2A_OUT
C67
10uF
DI
C68
0_1uF
DNI
Audio In / Audio Out
Project
Tuesday, June 26, 2012
1
12
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
1
Sheet
MachXO2 Control Board
D
C
B
A
21
CMA-4544PF-W
C73
Audio Amplifier
VCC33
R162
1000K
DI
R149
1000K
DI
2
5
D
C
B
A
5
+
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 19. Audio In/Audio Out
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 20. MachXO2 Supplies, JTAG
U4B
5
MachXO2 Bank 1
PR2A/PR1A/PR2A/R_GPLLT_FB
PR2B/PR1B/PR2B/R_GPLLC_FB
PR3A/PR3A/PR5A
PR3B/PR3B/PR5B
PR2C/PR2A/PR3A/R_GPLLT_IN
PR2D/PR2B/PR3B/R_GPLLC_IN
DQ0
PR4A/PR4A/PR6A
PR4B/PR4B/PR6B
PR4C/PR5A/PR8A
PR4D/PR5B/PR8B
PR5A/PR6A/PR9A DQS
PR5B/PR6B/PR9B DQSN
PR5C/PR7A/PR10A/PCLKT1_0
PR5D/PR7B/PR10B/PCLKC1_0
PR8C/PR10A/PR14A
PR8D/PR10B/PR14B
PR8A/PR9A/PR13A DQS
PR8B/PR9B/PR13B DQSN
DQ1
PR9A/PR11A/PR15A
PR9B/PR11B/PR15B
E12
E14
C14
D12
B14
C13
LPDDR_A7
LPDDR_A6
LPDDR_A9
LPDDR_A8
LPDDR_A12
LPDDR_A11
LPDDR_A5
LPDDR_A4
LPDDR_A3
LPDDR_A2
E13
F12
F13
F14
LPDDR_CK
LPDDR_CKn
LPDDR_A10
LPDDR_LDM
G12
G14
G13
H12
LPDDR_DQ7
LPDDR_DQ6
LPDDR_LDQS
XO2_GPIO_10
LPDDR_DQ5
LPDDR_DQ4
J13
K12
K13
K14
LPDDR_DQ3
LPDDR_DQ1
J12
J14
L14
M13
LPDDR_DQ2
LPDDR_DQ0
C90
0_1uF
DI
C76
[8]
[8]
4
U4D
MachXO2 Bank 3
PL8C/PL11A/PL16A
PL8D/PL11B/PL16B
PL9A/PL12A/PL17A PCLKT3_0
PL9B/PL12B/PL17B PCLKC3_0
[8]
[8]
1.2K/2K/4K
LPDDR_A12
LPDDR_A11
PL10B/PL13B/PL19B
LPDDR_A9
LPDDR_A8
[8]
[8]
LCMXO2-1_2K/2K/4K-MN132
VCCIO3
PL10C/PL14A/PL20A
PL10D/PL14B/PL20B
LPDDR_A7
LPDDR_A6
[8]
[8]
[8]
[8]
U4F
VCCIO3
2nd Fn
2nd Fn
VCCIO3/VCCIO5/VCCIO5
PL4A/PL5A/PL8A
PL4B/PL5B/PL8B
PL3C/PL4A/PL7A
PL3D/PL4B/PL7B
PL3A/PL3A/PL6A PCLKT5_0
PL3B/PL3B/PL6B PCLKC5_0
PL2C/PL2A/PL4A L_GPLLT_IN
PL2D/PL2B/PL4B L_GPLLC_IN
PL2A/PL1A/PL3A L_GPLLT_FB
PL2B/PL1B/PL3B L_GPLLC_FB
MachXO2 Bank 5
LCMXO2-1_2K/2K/4K-MN132
1.2K/2K/4K
PL8A/PL10A/PL14A
PL8B/PL10B/PL14B
PL5C/PL9A/PL13A
PL5D/PL9B/PL13B
PL5A/PL7C/PL10C PCLKT4_0
PL5B/PL7D/PL10D PCLKC4_0
PL4C/PL6A/PL9A
PL4D/PL6B/PL9B
MachXO2 Bank 4
2nd Fn
LPDDR_A3
LPDDR_A2
[8]
[8]
[8]
[8]
[8]
[8]
U4E
LPDDR_A5
LPDDR_A4
LPDDR_CK
LPDDR_CKn
LPDDR_A10
LPDDR_LDM
C87
LPDDR_A0
LPDDR_A1
LPDDR_DQ2 [8]
LPDDR_DQ0 [8]
LPDDR_DQ3 [8]
LPDDR_DQ1 [8]
LPDDR_DQ5 [8]
LPDDR_DQ4 [8]
LPDDR_DQ7 [8]
LPDDR_DQ6 [8]
DI VCC18
10K R73
LPDDR_LDQS [8]
XO2_GPIO_10 [7]
C95
0_1uF 0_1uF
DNI
DNI
0_1uF
DI
C98
VCC_CORE
0_1uF 0_1uF
DI
DI
C84
VCCIO18
LPDDR_A0
LPDDR_A1
M12
M14
N13
N14
H14
D14
L12
C97
0_1uF
DI
1.2K/2K/4K
LCMXO2-1_2K/2K/4K-MN132
J3
K2
K1
K3
L3
M1
M2
L1
uSD_DAT0
XO2_RESETn
PM_MCLK
uSD_DAT1
PM_OUT11
PM_OUT12
PM_OUT13
VCCIO33
XO2_LED0
XO2_LED2
PM_PLDCLK
XO2_LED3
F1
F3
G3
H2
USB_UART_TX
USB_UART_RX
PWM_FB_Delta_Sigma
uSD_DAT3
SW3
uSD_DAT2
VCCIO33
uSD_CMD
uSD_CLK
H1
H3
J1
J2
G1
B1
B2
C1
C3
3
uSD_DAT0 [8]
XO2_RESETn [4,7]
[7]
[7]
[4]
[4]
[4]
PM_MCLK [4,7]
uSD_DAT1 [8]
PM_OUT11
PM_OUT12
PM_OUT13
XO2_LED0
XO2_LED2
PM_PLDCLK [4,7]
XO2_LED3
[7]
[8]
[8]
USB_UART_TX [6]
USB_UART_RX [6]
uSD_CMD
uSD_CLK
uSD_DAT3
[7]
[7]
[8]
[7]
[8]
X_2
X_1
SW3
uSD_DAT2
LVDS_COMP_P_VREF
LVDS_COMP_N
XIN
XOUT
[12]
[7]
2
XO2_TDI
XO2_TDO
VCC33
2
4
6
5
7
8
XO2_TCK
XO2_TMS
3
1
MachXO2 JTAG Port
J7
POWER
TDI
TDO
NC
TMS
TRST
GND
TCK
XO2 JTAG HD
NOT Populated
JTAG Header
J12
TDO
TDI
MH16
1
MH2
1
MH1
DNI
XO2_TMS
XO2_TCK
XO2_TDO
XO2_TDI
XO2_TMS
XO2_TCK
1
1
TDI_HDR
[7]
[7]
TMS_HDR
TCK_HDR
[6]
[6,14]
[6,7,14]
[6,7,14]
[6,7,14]
[6,7,14]
R156
0
DNI
XO2_TDI
XO2_TMS
XO2_TCK
XO2_TDO_PIN [14]
XO2_TDO
Sheet
13
of
14
R ev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
3300pF
DI
C78
DNI
XO2_TDO_PIN
J9
Jumper_2way
1
2
3
R157
0
DI XO2_TDO
R155 0
R181
10K
LVDS_COMP_N
R180
10K
PWM_FB_Delta_Sigma
TDO_HDR
Expand JTAG Chain to Prototype Header:
DI
MachXO2
XO2_TDO_PIN
DI
TDO
AUDIO_IN R166 0
DI
IO12
Title
Tuesday, June 26, 2012
MachXO2 Control Board
Project
XO2 Banks 1, 3, 4, 5 & JTAG
ADC_IN R165 0
TDI
R203
To Prototype Header
AUDIO_IN
XO2_ADC_IN
MH13
1
Size
B
Date:
DI
Expand JTAG Chain to Prototype Header:
VCCIO33
R41
10K
LVDS_COMP_P_VREF
R53
10K
ADC Delta-Sigma Interface
DI
DI
1
M_HOLE1 M_HOLE1 M_HOLE1 M_HOLE1
DI
DI
DI
DI
IW_MNT0 IW_MNT0 IW_MNT0 IW_MNT0
2
Socket (080SQ 132U6618A) Mounting Holes
0_1uF 0_1uF
DNI
DNI
C93
AUDIO_OUT
XO2_LED1
C2
D1
AUDIO_OUT
XO2_LED1
VCCIO33
C80
C94
E1
E2
E3
F2
D3
C77
0_1uF 0_1uF
DI
DI
3
D
C
B
A
22
PR9C/PR12A/PR16A
PR9D/PR12B/PR16B
PR10A/PR13A/PR18A
PR10B/PR13B/PR18B
C7
P14
A1
N1
A14
2nd Fn
VCCIO1
VCCIO1
VCCIO1
PR10C/PR14A/PR19A
PR10D/PR14B/PR19B
1.2K/2K/4K
LCMXO2-1_2K/2K/4K-MN132
U4G
NC
VCC
VCC
VCC
VCC
B11
D2
D13
L2
A5
L13
P5
P10
G2
H13
4
R201
D
C
B
A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LCMXO2-1_2K/2K/4K-MN132
5
R202
MachXO2-4000HC Control Development Kit
User’s Guide
Figure 21. MachXO2 Top, Bottom
D
C
XO2_GPIO_0
XO2_GPIO_1
XO2_GPIO_2
XO2_GPIO_3
XO2_GPIO_4
XO2_GPIO_5
XO2_GPIO_6
XO2_GPIO_7
5
XO2_GPIO_0
XO2_IN3_2_P
0 R35 DNI
0 R144DI
0 R30 DNI
0 R33 DNI
0 R143DI
0 R142DI
XO2_GPIO_1
XO2_GPIO_2
0 R28 DNI
0 R141DI
0 R140DI
0 R40 DNI
XO2_GPIO_4
0 R139DI
0 R42 DNI
XO2_GPIO_3
XO2_GPIO_5
0 R138DI
0 R57 DNI
0 R52 DNI
0 R137DI
XO2_GPIO_6
XO2_GPIO_7
0 R152DI
0 R24 DNI
0 R26 DNI
0 R153DI
XO2_GPIO_8
XO2_GPIO_9
XO2_IO_0
XO2_IO_1
XO2_IO_2
XO2_IO_3
XO2_IO_4
XO2_IO_5
XO2_IO_6
XO2_IO_7
XO2_IO_8
XO2_IO_9
4
[8] XO2_SPI_CS0
[9] SERTC1+
[9] SERTC1[4] PM_SMBA_OUT3
[7,8] XO2_SPI_CLK
[9] SERTFG1+
[9] SERTFG1[7,8] XO2_SPI_OUT
PM_IN1
[4]
[11] SERTC2+
[11] SERTC2[4]
PM_IN2
XO2_SPI_CS0
SERTC1+
SERTC1PM_SMBA_OUT3
XO2_SPI_CLK
SERTFG1+
SERTFG1MISO
0
0
0
0
0
0
0
0
0
0
XO2_GPIO_110
SERTFG2+
SERTFG2- 0
MOSI
0
PM_IN1
SERTC2+
SERTC2PM_IN2
[7] XO2_GPIO_11
[11] SERTFG2+
[11] SERTFG2XO2_SPI_IN
[7,8]
R262
R258
R259
R263
R264
R260
R261
R265
R256
DI
DNI
DNI
DI
DI
DNI
DNI
DI
DI
DI
DI
R254
DNI
DI
R255
R257
R253
[9]
[9]
XO2_IN1_1_P
XO2_IN1_1_N
XO2_IN3_1_P
XO2_IN3_1_N
3
[9]
[9]
XO2_IN2_1_P
XO2_IN2_1_N
XO2_IN0_1_P
XO2_IN0_1_N
[9] XO2_CLKIN_1_P
[9] XO2_CLKIN_1_N
[9]
[9]
[9]
[9]
C100 C103
SERTC+
SERTC-
0 R238DI
0 R252DI
SERTFG-
SERTFG+
VCCIO33
SW1
0 R250DI
0 R251DI
SW2
XO2_IN0_2_N
XO2_IN0_2_P
XO2_IN1_2_N
XO2_IN1_2_P
XO2_IN2_2_N
XO2_IN2_2_P
XO2_CLKIN_2_N
XO2_CLKIN_2_P
XO2_IN3_2_N
Resistor Mux between Prototype Header
and Video Channel 2 (7:1LVDS)
[7]
[10] XO2_IN3_2_P
[7]
[10] XO2_IN3_2_N
[7]
[10] XO2_CLKIN_2_P
[7]
[10] XO2_CLKIN_2_N
[7]
[10] XO2_IN2_2_P
[7]
[10] XO2_IN2_2_N
[7]
[10] XO2_IN1_2_P
[7]
[10] XO2_IN1_2_N
[10] XO2_IN0_2_P
XO2_GPIO_8
SW2
SW0
LPDDR_CKE_3p3
LPDDR_CKE
LPDDR_CKE_1p8
LPDDR_CKE_3p3
LPDDR_BA0_1p8
LPDDR_BA0_3p3
LVCMOS33 Voltage Devider
[8]
LPDDR_BA0
XO2_IN3_1_P
XO2_IN3_1_N
XO2_IN1_1_P
XO2_IN1_1_N
P2
N2
P3
M3
N3
P4
M4
N4
XO2_CLKIN_1_PN6
XO2_CLKIN_1_NP6
M7
N8
N5
M5
XO2_IO_2
XO2_IO_3
P7
N7
P9
N9
P8
M8
XO2_IO_4
XO2_IO_5
M9
N10
XO2_IO_0
XO2_IO_1
XO2_IO_6
XO2_IO_7
M10
P11
XO2_IN0_1_P
XO2_IN0_1_N
XO2_IO_8
XO2_IO_9
M6
N11
P1
N12
P13
XO2_IN2_1_P M11
XO2_IN2_1_N P12
C102 C101
VCCIO33
0_1uF 0_1uF
DNI
DNI
MachXO2 Bank 2
PB4A/PB3A/PB3A
PB4B/PB3B/PB3B
PB4C/PB5A/PB4A CSSPIN
PB4D/PB5B/PB4B
PB6A/PB6A/PB7A
PB6B/PB6B/PB7B
PB6C/PB8A/PB9A MCLK/CCLK
PB6D/PB8B/PB9B SO/SPISO
PB9A/PB11A/PB13A PCLKT2_0
PB9B/PB11B/PB13B PCLKC2_0
PB9C/PB9A/PB10A
PB9D/PB9B/PB10B
PB11A/PB16A/PB20A PCLKT2_1
PB11B/PB16B/PB20B PCLKC2_1
PB11C/PB12A/PB15A
PB11D/PB12B/PB15B
PB15A/PB18A/PB21A
PB15B/PB18B/PB21B
PB15C/PB19A/PB23A
PB15D/PB19B/PB23B
PB18A/PB21A/PB24A
PB18B/PB21B/PB24B
PB18C/PB22A/PB27A
PB18D/PB22B/PB27B
PB20A/PB24A/PB29A
PB20B/PB24B/PB29B
2nd Fn
PB20C/PB25A/PB30A SN
PB20D/PB25B/PB30B SI/SISPI
VCCIO2
VCCIO2
VCCIO2
1.2K/2K/4K
U4C
LCMXO2-1_2K/2K/4K-MN132
VCC33
2
U4A
MachXO2 Bank 0
PT9A^/PT9A^/PT9A^
PT9B^/PT9B^/PT9B^
PT10A^/PT11A^/PT11A^
PT10B^/PT11B^/PT11B^
PT10C/PT12C/PT13C TDO
PT10D/PT12D/PT13D TDI
PT11A^/PT13A^/PT14A^
PT11B^/PT13B^/PT14B^
PT11C/PT16C/PT15C TCK
PT11D/PT16D/PT15D TMS
PT12A^/PT17A^/PT18A^ PCLKT0_1
PT12B^/PT17B^/PT18B^ PCLKC0_1
PT15A^/PT19A^/PT21A^
PT15B^/PT19B^/PT21B^
PT12C/PT18C/PT20C/SCL PCLKT0_0
PT12D/PT18D/PT20D/SDA PCLKC0_0
PT15C/PT20C/PT23C JTAGENB
PT15D/PT20D/PT23D PROGRAMN
PT16A^/PT21A^/PT24A^
PT16B^/PT21B^/PT24B^
PT16C/PT22A^/PT25A^
PT16D/PT22B^/PT25B^
PT17A^/PT23A^/PT27A^
PT17B^/PT23B^/PT27B^
PT17C/PT24C/PT28C INITN
PT17D/PT24D/PT28D DONE
VCCIO0
VCCIO0
VCCIO0
2nd Fn
^ = True LVDS
1.2K/2K/4K
Title
Size
B
Date:
A2
B3
XO2_CLKOUT_P
XO2_CLKOUT_N
XO2_OUT3_P
XO2_OUT3_N
XO2_TDO_PIN
XO2_TDI
A3
C4
XO2_OUT1_P
XO2_OUT1_N
XO2_TCK
XO2_TMS
XO2_OUT2_P
XO2_OUT2_N
B6
A6
B5
C6
A4
B4
A7
B7
SCL
SDA
1
XO2_OUT3_P [11]
XO2_OUT3_N [11]
XO2_TDO_PIN [13]
XO2_TDI
[6,13]
XO2_CLKOUT_P [11]
XO2_CLKOUT_N [11]
XO2_TCK [6,7,13]
XO2_TMS [6,7,13]
XO2_OUT2_P [11]
XO2_OUT2_N [11]
SCL
SDA
[4,7]
[4,7]
XO2_OUT1_P [11]
XO2_OUT1_N [11]
XO2_OUT0_P
XO2_OUT0_N
IO22
IO21
C8
B8
LPDDR_BA0_3p3
LPDDR_RASn
[11]
[11]
LPDDR_CASn [8]
LPDDR_CSn [8]
LPDDR_WEn [8]
SERTFG+
SERTFG-
XO2_OUT0_P [11]
XO2_OUT0_N [11]
C9
A9
SERTC+
SERTC-
SERTFG+
SERTFG-
B9
C10
A11
B12
LPDDR_BA1_3p3
LPDDR_WEn
A10
C11
C12
A12
LPDDR_CASn
LPDDR_CSn
LPDDR_RASn [8]
SERTC+
[11]
SERTC[11]
B13
A13
C88
C86
VCCIO33 VCCIO33
0_1uF 0_1uF
DNI
DNI
C92
C96
1
Sheet
14
of
14
Rev
G
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
www.latticesemi.com
0_1uF 0_1uF
DI
DI
A8
B10
C5
Tuesday, June 26, 2012
MachXO2 Control Board
Project
XO2 Banks 0, 2
LCMXO2-1_2K/2K/4K-MN132
I2C Bus Pull-up Resistors
SCL
SDA
2
D
C
B
A
23
[7]
[7]
SW0
SW1
XO2_GPIO_9
[10] XO2_IN0_2_N
[7]
[7]
[7]
1K
R177
LPDDR_BA1_3p3
LPDDR_BA1_1p8
LPDDR_BA1 [8]
4_7K
0_1uF 0_1uF
DI
DI
[8]
3
4_7K
Interface between LVCMOS33 and LPDDR1.8V
DI
VCC18
1K
R176
R91
DI
R90
DI
LVCMOS33 Open Drain
DI
LPDDR_RASn
1K
R178
LPDDR_CASn
1K
DI
LPDDR_CSn
R69
DI
820
R74
DI
1K
R175
LPDDR_WEn
4
820
1K
R187
DI
R183
DI
B
A
5
820
1K
R188
DI
R182
DI
DI
MachXO2-4000HC Control Development Kit
User’s Guide
Appendix B. Bill of Materials
Table 1. Bill of Materials
Item Quantity
Reference
1
19
C1, C7, C12, C14, C17,
C26, C37, C39, C50, C55,
C71, C113, C114, C125,
C131, C132, C135, C137,
C139
2
23
3
4
Value
0_001uF
PCB Footprint
Manufacturer
Part Number
Manufacturer
Description
Populate
SM_C_0201
DI
C2, C5, C6, C15, C18, C24,
C25, C32, C34, C36, C38,
C40, C41, C51, C52, C56, 0_01uF
C72, C91, C117, C124,
C130, C136, C138
SM_C_0201
DI
18
C3, C9, C13, C20, C21,
C22, C43, C49, C60, C62,
C111, C118, C120, C121,
C122, C127, C129, C140
10uF
SM_C_0603
2
C4, C11
12pF
SM_C_0603
DI
5
32
C8, C10, C16, C19, C42,
C44, C45, C46, C47, C57,
C58, C59, C61, C63, C64,
C69, C74, C81, C89, C99,
C105, C107, C109, C110,
C112, C115, C116, C123,
C128, C133, C134, C141
0_1uF
SM_C_0603
DI
6
2
C23, C29
18pF
cc0402
C0402C180K3GACTU
Kemet
CAP CER 18PF
25V C0G 0402
DI
7
10
C27, C30, C31, C48, C82,
C85, C104, C119, C126,
C145
0.1uF
cc0402
C0402C104K4RACTU
Kemet
Cap Cer 0.1uF
16V X7R 0402
DI
8
1
C28
10u
cc0603
ECJ-1VB0J106M
Panasonic
Cap Cer 10uF
6.3V 20% X5R
0603
DI
JMK212BJ106KD-T
TAIYO YUDEN
LMK212BJ226MG-T
TAIYO YUDEN
C1608Y5V0J106Z
TDK
DI
9
4
C33, C106, C142, C143
10uF
SM_C_0805
10
2
C35, C83
1uF
SM_C_0805
DI
11
2
C53, C65
22uF
SM_C_0805
12
4
C54, C66, C70, C73
10uF
SM_C_0805
13
1
C67
10uF
SM_C_0603
DI
14
1
C68
0_1uF
SM_C_0603
DNI
15
13
C75, C76, C77, C79, C80,
C84, C90, C92, C96, C97,
C98, C100, C103
0_1uF
SM_C_0201
DI
16
1
C78
3300pF
SM_C_0603
DI
17
8
C86, C87, C88, C93, C94,
C95, C101, C102
0_1uF
SM_C_0201
DNI
18
1
C108
0_01uF
SM_C_0201
DI
DI
DI
DI
Cap Cer 4.7uF
6.3V 10% X5R
0603
19
1
C144
4u7
cc0603
ECJ-1VB0J475K
Panasonic
DI
20
8
D1, D2, D3, D4, D7, D8,
D9, D10
LED
SM_D_0603
LTST-C190CKT
LITE ON
21
2
D5, D6
LED_Green
SM_D_0603
LTST-C190KGKT
LITE ON
DI
22
1
D11
LED_Green
SM_D_0603
LTST-C190KGKT
LITE ON
DNI
23
1
D12
LED
SM_D_0603
LTST-C190CKT
LITE ON
DI
24
20
IO2, IO3, IO4, IO5, IO7,
IO8, IO9, IO10, IO11, IO12,
IO13, IO14, IO15, IO16,
T POINT R
IO17, IO18, IO19, IO20,
IO21, IO22
TP
25
2
J1, J8
10226-1A10PE-ND
10226-1A10PE-ND
10226-1A10PE
3M
CONN RECEPT
26POS R/A .050"
SMD
DI
26
1
J13
10226-1A10PE-ND
10226-1A10PE-ND
10226-1A10PE
3M
CONN RECEPT
26POS R/A .050"
SMD
DNI
27
2
J2, J3
DVI_I
DVI_I
74320-1004
Molex
DI
28
1
J4
CON40A
2x20x100mil
TSW-120-07-T-D
Samtec
DI
29
1
J5
USB_MINI_B
TYPE_B
UX60-MB-5ST
Hirose
DI
30
1
J6
Jumper_2way
JP_2WY
TSW-103-07-G-S
Samtec Inc.
31
1
J7
XO2 JTAG HD
XO2_JTAG_HD
32
1
J9
Jumper_2way
JP_2WY
TSW-103-07-G-S
Samtec Inc.
DNI
33
1
J10
DVI_I
DVI_I
74320-1004
Molex
DNI
34
1
J11
PWR_JACK
PWR_CON
RAPC712
Switchcraft
DI
DNI
DI
DNI
24
DI
MachXO2-4000HC Control Development Kit
User’s Guide
Table 1. Bill of Materials (Continued)
Item Quantity
35
1
Reference
J12
Value
PHONEJACK STEREO
Manufacturer
Part Number
PCB Footprint
SM
MJ1-3510-SMT
Manufacturer
Description
CUI
DI
Ferrite Bead
[email protected]
z 500mA 0603
DI
BUMPON HEMISPHERE .44X.20
BLACK
DI
36
1
L3
600ohm 500mA
FB0603
BLM18AG601SN1D
37
4
MH1, MH2, MH13, MH16
M_HOLE1
IW_MNT0
SJ-5003 (BLACK)
38
4
Q1, Q3, Q6, Q8
BSS138LT1
SOT_23
BSS138LT3G
ON Semi
DI
39
2
Q2, Q5
2N7002E
SM_SOT23
2N7002ET1G
ON_Semi
DI
40
1
Q4
2N2369A
2N2369A_SOT23
MMBT2369A
Fairchild
DI
41
1
Q7
ZDT758
SM_8_DUAL_PNP
ZDT758
Diodes/Zetex
DI
42
2
RN1, RN4
RN2_4_470
RN2_4_470_0603
TC164-JR-07470RL
Yageo
DI
43
1
RN2
RN1_8_10K
RN1_8_10K_0603
MNR18E0APJ103
Rohm Semi
DI
44
1
RN3
RN1_8_10K
RN1_8_10K_0603
MNR18E0APJ103
Rohm Semi
DI
45
45
R1, R7, R18, R19, R20,
R21, R32, R41, R43, R44,
R45, R46, R47, R53, R73,
R81, R94, R97, R115,
R116, R117, R118, R119,
R120, R121, R123, R124,
R125, R126, R127, R128,
R132, R151, R158, R159,
R163, R164, R180, R181,
R200, R233, R236, R239,
R242, R244
10K
SM_R_0402
DI
46
1
R2
1M
SM_R_0603
DI
47
53
R3, R5, R8, R10, R11, R15,
R16, R24, R25, R26, R28,
R29, R30, R33, R35, R40,
R42, R52, R57, R92, R96,
R98, R100, R104, R105,
R106, R109, R110, R113,
0
R155, R156, R161, R168,
R169, R172, R173, R207,
R208, R209, R210, R211,
R212, R213, R214, R215,
R216, R217, R218, R257,
R258, R259, R260, R261
SM_R_0402
DNI
48
5
R4, R67, R195, R196,
R232
1K
SM_R_0603
DI
49
80
R6, R9, R12, R13, R14,
R17, R23, R34, R36, R37,
R38, R39, R49, R50, R51,
R61, R62, R70, R71, R75,
R76, R78, R82, R83, R87,
R93, R95, R99, R102,
R103, R107, R108, R111,
R112, R131, R137, R138,
R139, R140, R141, R142,
R143, R144, R152, R153,
R154, R157, R165, R166,
R167, R170, R171, R174,
R186, R220, R221, R222,
R223, R224, R225, R226,
R227, R228, R229, R230,
R231, R238, R247, R248,
R250, R251, R252, R253,
R254, R255, R256, R262,
R263, R264, R265
0
SM_R_0402
DI
50
7
R22, R48, R101, R237,
R243, R245, R246
10K
SM_R_0402
DNI
51
4
R27, R64, R114, R122
470
SM_R_0603
52
1
R31
510, 1%
SM_R_0603
DI
53
9
R54, R55, R65, R66, R84,
R85, R88, R89, R205
4_7K
SM_R_0603
DI
54
1
R56
2k2
cr0402
55
1
R58
0
SM_R_0805
DNI
56
1
R59
1
SM_R_0805
DI
57
2
R60, R219
220
SM_R_0603
DI
58
2
R63, R68
0
SM_R_0603
DI
59
3
R69, R187, R188
820
SM_R_0402
DI
60
8
R74, R175, R176, R177,
R178, R182, R183, R234
1K
SM_R_0402
DI
61
1
R79
100K
SM_R_0603
DI
62
2
R80, R86
68
SM_R_0402
DI
63
2
R90, R91
4_7K
SM_R_0402
DI
ERJ-3EKF4700V
TNPW04022K20BEED
25
Murata
Populate
Panasonic ECG
Vishay/Dale
DI
RES 2.20K OHM
1/16W 0.1% 0402
DI
MachXO2-4000HC Control Development Kit
User’s Guide
Table 1. Bill of Materials (Continued)
Item Quantity
Reference
Value
PCB Footprint
Manufacturer
Part Number
Manufacturer
Description
Populate
64
13
R129, R130, R133, R134,
R135, R136, R146, R184,
R185, R191, R194, R201,
R206
65
1
R145
330
SM_R_0603
DI
66
1
R147
2_2K
SM_R_0603
DI
67
2
R148, R235
2
SM_R_0805
DI
68
2
R149, R162
1000K
SM_R_0603
DI
69
1
R150
10K
SM_R_0603
DI
70
1
R160
680K
SM_R_0603
DI
71
2
R179, R198
200
SM_R_0603
DI
72
4
R189, R190, R192, R193
3_92K
SM_R_0603
DI
73
2
R197, R204
2K
SM_R_0603
100
SM_R_0603
DI
DI
74
1
R199
12k
cr0402
RC0402FR-0712KL
Yageo
Res 1/16W 12.0K
1% 0402
75
4
R202, R203, R241, R249
10k
cr0402
RC0402FR-0710KL
Yageo
Res 1/16W 10.0K
1% 0402
DI
76
1
R240
2.2K
SM_R_0402
RC0402FR-072K2L
Yageo
Res 1/16W 2.2K
1% 0402
DI
77
1
SW1
SWDIP_4
SMD_8check
3-5435640-5
Tyco
SWITCH DIP
4POS SEALED
GOLD
DI
78
1
SW2
SW DIP_2
SP_75
195-2MST
CTS
SWITCH SIDE
ACTUATED 2
SEC
DI
79
1
S1
XO2 Global Reset
SMT_SW
EVQ-Q2K03W
Panasonic
SWITCH LT 6MM
130GF H=3.1MM
SMD
DI
80
1
U1
microSD Socket
SM_SD
460DE08C3
MULTICOMP
DI
81
1
U2
TFP401A
HTQFP_100
TFP401APZPG4
TI
DI
82
1
U3
TFP410
HTQFP_64
TFP410PAP
TI
DI
83
1
U4
LCMXO2-4000HC
-6MG132
CSBGA132
LCMXO2-4000HC-6MG132
Lattice Semi
DI
84
1
U5
STG3693QTR
QFN
STG3693QTR
STMicroelectronics
DI
85
1
U6
MT46H16M16LFBF
SM/60VFBGA
MT46H16M16LFBF
Micron
DI
86
1
U7
ispPAC-POWR1014A
TQFP_48
ispPAC-POWR1014A-01TN48I Lattice
DI
87
1
U8
CMA-4544PF-W
2 Solder Pins (TH)
CMA-4544PF-W
CUI Inc
88
1
U9
TFP401A
HTQFP_100
TFP401APZPG4
TI
89
1
U10
DS90CR288A
TSSOP_56
DS90CR288AMTD/NOPB
National Semi
DI
90
1
U11
NCP1117ST33
SOT_223
NCP1117ST33T3G
ONSemi
DI
91
1
U12
NCP1117ST18
SOT_223
NCP1117ST18T3G
ONSemi
DI
92
1
U13
MCP6L71R
SOT_23_5_MC
MCP6L71RT-E/OT
Microchip
DI
93
1
U14
AT25DF041A-SH-B
SOIC_8
AT25DF041A-SH-B
Atmel
DI
94
1
U15
AT25DF041A-MH-B
UDFN
AT25DF041A-MH-B
Atmel
DNI
95
1
U16
AD8604ARZ
14_SOIC
AD8604ARZ
Analog Devices
96
1
U17
Value
MRA08A_M
LP3879MR-1.2
National
DNI
97
1
U18
DS90CR287
TSSOP_56
DS90CR287MTD/NOPB
TI
DNI
98
1
U19
DS90CR287
TSSOP_56
DS90CR287MTD/NOPB
TI
DI
99
1
U20
FT2232HL
tqfp64_0p5_12p2x12p2_h1p6 FT2232HL
FTDI
100
1
U21
93LC56-SO8
so8_50_244
93LC56T-I/SN
Microchip
IC 93LC56
EEPROM
101
1
X1
CTS-CB3LV-3C-25MHz
SMD 7.00mm x 5.00mm
CB3LV-3C-25M0000
CTS
OSC 25.000 MHZ
3.3V SMD
DNI
DI
DI
DI
DNI
DI
DI
102
1
X2
HCM49 24.000MABJ-UT SMD
HCM49 24.000MABJ-UT
Citizen Finetech
CRYSTAL 24.000
MHZ 18PF SMD
103
1
X3
12MHZ
7M-12.000MAAJ-T
TXC
CRYSTAL 12.000
MHZ 18PF SMD
crystal_4p_3p2x2p5
26
DI
DI
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