Model 4P Service Manual (1984)(Tandy)

Model 4P Service Manual (1984)(Tandy)
 Radio Jhaek
Service Manual
Pa
TRS-80
Model 4P, 4P Gate Array
Catalog Number 26-1080
CUSTOM MANUFACTURED IN U.S.A. BY RADIO SHACK, A DIVISION OF TANDY CORPORATION
TRS-80™ Model 4P/4P Gate Array Service Manual
Copyright® 1984 Tandy Corporation
All Rights Reserved.
Reproduction or use, without express written permission from Tandy Corporation, of any
portion of this manual is prohibited. While reasonable efforts have been taken in the
preparation of this manual to assure its accuracy, Tandy Corporation assumes no liability
resulting from any errors or omissions in this manual, or from the use of the information
contained herein.
овен
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SECTION |
1.1
1.2
1.3
SECTION II
2.1
2.2
2.3
2.4
2.5
SECTION III
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
SECTION IV
SECTION V
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1.12
51.13
51.14
51.15
5.1.16
5.1.17
5.2
5.2.1
5.2.2
5.2.3
TABLE OF CONTENTS
Introduction ........1120200 0002 LL A AA AAA Se 4 A A A ee ee 6 0 A a ee A ae a ee a a ee nee» 1
SYS EM OVE BW Lo eee 3
Optional Features ‚0.00.0000 KERN 3
System Block Diagram... a 5
SpecificationS ........0.0.00000000 ea eee ve 7
MicroproceSSOF 1... ES o
Peripheral Interfaces. .................e0r0rirrrirrrerirerer en en ereecerr eres g
Power Requirements ...............esc00rííriri0 2er EKEREEKEK q
Operating Temperature ..............or-eevmrierriirreverecen ener ee een DA 9
Dimensions ........12212 000044 Aa A a A A A da A 4 A ee ee 9
Disassembly/Assembly ....... анна ново вевнввеа на еововнанонно 11
0-1 - EEE 13
Internal Rear Mounting Plat&. ........0.0000000000000 REKEN 13
FrontBezel........... ooo reee aarra era edeoaaaaanacananeroevarrrnanenvoarrooneZ a 13
Top Cover/Power Supply ..............e_...e000008r00re.rarier ea 13
Cathode Ray Tube ..............ee-.0000eerrereierrecrereere eee 0er RRA 14
CRT SweepBoard 124104440444 44 4 444 ea ee a a a ae ae ea AA Re ea ee ee 46 14
Main Logic PCB... ea ea Aa ee ee 4e Rd Re ee ee A ee EN RES 0 14
Keyboard Assembly ............. eee 14
Disk Drive Assembly ...............—..ee0e0rroricorrerverceeearrarrereecrererat er mer 0 15
Control MOAUIE oe A 4 ee Re ee ee ee 4e ee ee ea 4e 0 0 15
Maintenance/Troubleshooting (general suggestions, reference
to section below for specific troubleshooting hints) ............... iia 17
4P Theory Of Operation ....... oo ieee ea 21
CPU Theory of Operation... anns 23
Introduction .............. ES 23
ResetCircuit . o.oo RAA 23
CPU Le eee ee 23
SYStEM TIMING. oo ri erver rre recente. 23
Address Decode ................e0e0000x0rerri rear reia ro a ea Se ea ea ae ee ee 00 26
ROM... ee ecvacrereve— 26
RAM ...000aaererac re eaceaaeaceredecoerarrererearerravrerecrerorrerari rece, 37
Video Circuit ...................e..ecieedecderedarrrrerereerreroroocrnarerareorrenD. 51
Keyboard .............oeeeeeeérecceereorererrórorereerec re ererecarererrereccrere. 53
Real Time Clock ............... e0d0000rereereree een eererec ar arcecorenarereveaarernna 53
Line Printer Port. ...................022020 00022 e esremerecararareaFÉeeevvvrvaaa are. 53
Graphics Port. .............._..000000000000ir ii ir Rae ee ee ee ee Resa 57
COUN ott et a 57
VOBusPort ee ee ee 57
FDC CirCUIt «oot ee RRKKRRRR 59
RS-232C Circuit .............. eee 64
Troubleshooting (specific) ................... Le ee A a A a a a a a ee A A ee A a a a a 0e 66
Schematic 8000192 ........111 012204 eee 67
PCBArt(1700254) 1.112010 ee 75
Parts List, PCB Assembly .......02100 00244 A Aa AA ea a a sa RAA a a a re ee ea ee ea ee 0e 79
4P Gate Array Theory of Operation ...... aa eee ae A aa ee ee SE 85
CPU Theory of Operation ....0.00000000040000 RR KK KK ene 85
Introduction ............ 2... aa esse ae ea ea a RR RRA 85
ResetCircuit .......1222000 0404444444 ea eee a ea a eee A a AA A ee ee ee ee er es 85
TT 85
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10
5.2.11
5.2.12
5.2.13
5.2.14
5.2.15
5.2.16
5.2.17
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
54.7
5.5
5.5.1
5.5.2
5.5.3
5.6
5.6.1
SECTION VI
ADDENDA
А.
SYSIEM TIMING Looe es 85
_ Address Decode Lo ee 87
ROM © tte ee 87
N BE 98
Video Circuit ........11111002 0004 4 4 a 4 Aa A a 4e a ea 4 4 KK KK a a a a ae een 6 112
Keyboard .........10200 004444 a ee ee eee ea a aa eee eee ta a a ea ee er ee ea ee tee 114
RealTime Clock .......11110200 000414 4 4 a a ae A 4 4 ee ee 8 ee a ae ee a a eee 4 eee NS 114
Line Printer Port............. eo ererraera 0.0 reaare0 errar are ienrecer er 114
Graphics POM. «ooo a a. 118
Sound .......... eases 118
/OBus Port ............... 2.2... 00nericieei erre ver enrecoro»,a ari rrrarcereareree 118
FDCCircuit ........... rr diderrerecoredenenercaneeneererenarearerererecrman 120
RS-232C Circuit EEE 124
Troubleshooting (specific) ..............0020000 00e ea ee as a aa eee eee ae ee a eee ee 126
Schematic8000192 RK 127
PCBArt(1700254) tite ee a a a a ee Re ee ee a 134
Parts List, PCB Assembly .........22000 00 aa aa aa a ea ee eee eee ae ee ee a ae ere ee tt 137
Mini-Disk Drives (Tandon TM-50) ................000xerrereeerererererer erecta e 143
Power Supply Assembly LL... ea 143
Power Supply Description o.oo. a 143
Technical Specifications... i er AG 147
Theory of Operation ....... rene A 148
Troubleshooting Chart ...... co i ea 158
Testing and AdjustmentsS ..... oa 159
Schematic 8000164, 66W Power Supply 8790049 ...... i 161
Component Layout, 65W Power Supply 8790049 . ........ KK eee 163
Circuit Trace, 65W Power Supply 8790049 . . LL. er E 164
Parts List, 65W Power Supply 8790049... . A 165
CRT DSP AY « «+ RK eee ee eee et 169
Specifications o.oo A AAA AS 169
AdjustmentProcedures ...........000000 0004 rase aa ee ee eee sa ae ae eee ee eee see 171
Theory of Operation ... aa ae see ee ea eee ea a a eee eee etes 174
Schematic 23533 (B/W) and 23757 (Green).............00004001 ee ass eee ea ae e a eee eee 179
Parts list 8790612 (B/W) and 8790613 (Green) .........220 040044 a Les eee sa sa aa aa eee 181
ОрНоп8 .......... EE EER 189
GraphicsBoard.........122000 04e eee ae La ea ee A eee ee ee ete eee a a a eee ss 189
Exploded View/Parts Lists ...........200 000040 sea a ea ee eee ES a eee a eee eee tes 199
Case Assembly eK 202
Main Chassis Assembly ................_e.xererrereevrerererrererrcare rene e 204
Disk Drive Assembly. LL... rra aa ae eee 206
Keyboard Assembly . oa 208
Tandon Operating and Service Manual, TM50-1 and TM50-2 5-1/4" Flexible Disk Drives
MODEL 4P/4P GATE ARRAY
HARDWARE
SECTION |
INTRODUCTION
INTRODUCTION
1.1 SYSTEM OVERVIEW
The TRS-80 Model 4P Microcomputer is a complete, self-con-
tained portable (transportable) version of the popular TRS-80
Model 4 Microcomputer. it provides a carrying/protective case
which has a recessed carrying handle, removable front cover
which protects the CRT and disk drives and serves as a hase
when in the portable configuration, and self-contained key-
board conveniently stowed away in a recess in the main case.
Power cord, floppy disk and manual storage are provided in-
side the removable cover/base. All connections to peripheral
equipment are made at the rear of the Model 4P and optional
feature connections are made by removing a rear cover plate.
Proper care and handling must be observed to prevent damage
to the computer,
The Model 4P is 100% compatible with all Model III and Model
4 disk software, System capability for Model Il compatibility in-
cludes: Z80A CPU, 2 MHz operation, programmable RAM to
emulate ROM for BASIC operating system, memory-mapped
keyboard, memory-mapped video with 64-character by 16-line
display, and full 48K Random Access Memory (RAM). Model 4
compatibility includes: Z80A CPU, 4 MHz operation, memory-
mapped keyboard in upper memory, memory-mapped video in
upper memory with 80-character by 24-line display. standard
64K RAM expandable to 128K RAM. Other standard features
of the Model 4P which were options on the Model lil and Model
4 are built-in FDC Circuit with two 184K Floppy Disk Drives and
an RS-232-C Serial Communications interface Circuit.
1.2 OPTIONAL FEATURES
Optional features available on the Model 4P include: 640 by
240 pixel High Resolution graphics Board, Direct-connect,
auto-dial, auto-answer 300 bps Modem Board. The Model 4P
does not support cassette operation or external Floppy Disk
Drive.
COVER/BASE
CONTROL
MODULE
KEYBOARD
TOP COVER/POWER SUPPLY
PAN/MAIN
LOGIC PCR
DRIVE
ASSEMBLY
MOUNTING
FLATE
Figure 1-1.
1.3 SYSTEM BLOCK DIAGRAM
The System Block Diagram (Figure 1.2) shows the various internal components and connections of the Model 4P
Microcomputer.
POWER CORD
#8709475
=D
LINE I/O RS-232-C
FDC CABLE
PRINTER BUS SERIAL
#870945 7
PORT PORT PORT
POWER SWITCH
#8489073
2-80A
4K BOCT ROM
64K OR 128K RAM
REAL TIME A
AC HARN 45
ESS #8709255 CLOCK VIDEO
INTERFACE FLOPPY FLOPPY
GRAPHICS LINE PRINTER INT. DRIVE DRIVE
BOARD 1/0 PORT INT.
POWER (OPTIONAL) RS232-C SERIAL # 0 # 1
INT. FLOPPY
SUPPLY an DRIVE INT. 8790121 8790121
48790049 HI-RES GRAPHICS
BOARD INT.
CIC 48709427
и y | ——
VIDEO HARNESS | RESET SWITCH
CABLE
#8703452 | 48709457 pc HARNESS | | #8709456
KEYBOARD CABLE | #8709460
CRT PC MODEM
BOARD BOARD
(OPTIONAL)
#8790612
70-KEY KEYBOARD
| 48790530
CONNECT TO
RS-232-C
RESET SERIAL
SWITCH PORT
BRIGHTNESS CONTRAST 8489071
CONTROL CONTROL De FAN
e
#8262450 #8261150 CRT 8750406
48790612 ap
Figure 1-2. Model 4P Block Diagram
SECTION II
SPECIFICATIONS
SPECIFICATIONS
2.1 MICROPROCESSOR: 4 MHz Z80A, 8-bit CPU
Memory:
Keyboard:
Video Display:
Floppy Disk Drives:
64K RAM bytes, expandable to 128K bytes 4K boot ROM, 2K video memory
70-key standard typewriter keyboard, including 12-key numeric entry keypad. Special keys include
BREAK, CTRL, CAPS, CLEAR, plus three programmable special function keys (F1, F2, and F3).
High-resolution 9” black and white display monitor with 64 or 32 characters per line by 16 lines in
Model IH mode and 80 or 40 characters per line by 24 lines in Model 4/4P mode. Displays upper
and lower case ASCII characters, with descenders, 96 special characters, 64 alternate characters,
64 graphics characters, plus reverse video of all ASCII alpha-numeric characters.
Two built-in single-sided, double-density 5-1/4" thin-line floppy disk drives. Each drive stores up to
184K bytes. Data transfer rate is 250K bits per second.
2.2 PERIPHERAL INTERFACES
Standard;
Optionat:
HO BUS for connection of hard disk and other peripherals.
Serial Interface (RS-232-C port) One RS-232-C Serial Communications interface port which allows
asynchronous and synchronous transmission. Mates with DB-25 connector on back of the Model
4Р.
Parallel Printer Interface Connection to a line printer via the 34-pin connector on the back of the
Model 4P.
640 x 240 High-Resolution graphics board
Auto-answer Modem (300 baud)
2.3 POWER REQUIREMENTS
105-130 Vac, 60 Hz
240 Vac, 50 Hz (Australian)
220 Vac, 50 Hz (European)
(Grounded Outlet
Maximum Current Drain: 1.7 Amperes
Typical Current Drain: 1.5 Amperes
2.4 OPERATING TEMPERATURE: 55t0 80° F (13 to 27° C)
2.5 DIMENSIONS: 9.3" H x 16.5" W x 13.25" D, 26 Ibs carrying weight.
SECTION III
DISASSEMBLY/ASSEMBLY
11
DISASSEMBLY/ ASSEMBLY
3.1 OVERVIEW AND CASE
The Model 4P is modular in construction in that it can be disas-
sembled in major component blocks after removal of the case
cover. These major component blocks include the disk drives,
the power supply, main CPU board, the CRT display, and the
monitor board. Accessory components such as the power cord,
additional diskettes, and operating manual can be stored in
convenient recesses in the removable front cover/base. This
cover/base provides protection for the CRT and disk drives dur-
Ing transport, It also serves as the base in the non-operating po-
sition of the computer.
The cover/base is held in place with snap locks on each side.
These locks are positive action with a protective boss to pre-
vent accidental opening of the cover/base. To remove, merely
unsnap the lock and release the catch from the main assembly
latch. The following procedures are noted in sequential order
required to provide access to some of the components. Some
parts removal does not require previous steps. Those which do
are noted. For reassembly of unit, reverse order of disassembly
instructions.
1. The main assembly of the Model 4P has a removable
cover which allows access to all internal components when
removed. Remove all connections to the rear of the unit.
These include the AC power cord, printer cable, I/O port
connector, and RS-232-C connector. The printer cable and
I/O port connectors are edge card type connectors — ex-
ercise care in their removal.
2. Place the unit Bezel/CRT face-down on a soft surface to
prevent damage to the CRT.
3. The case is held in place with six screws. Remove two
screws from either side of the case at the front of the unit.
To gain access to the last two screws, press down on one
end of the carrying handle and then lift the handle from its
recess. The final two case mounting screws are accessible
under the handle assembly. These two screws attach the
handle assembly as well as the case to the internal rear
mounting plate.
4, After removing all six screws, lift the cover off the computer
and set it aside for reassembly. Exercise care to prevent
scratching or damaging the cover.
3.2 INTERNAL REAR MOUNTING PLATE
1. Remove the case from the unit as noted in Paragraph 3.1
2. The rear mounting plate serves to provide mounting for the
case carrying handle and protection for the CRT. There are
ten mounting screws which attach this plate to the main
metal chassis of the computer. Four screws (Item 53 on
exploded view p. 144, two on each side) mount the handle
support (Item 16) and are accessible from the LH and RH
13
side of the unit. With the rear of the unit toward you, two of
these screws are located at the left just in front of the Disk
Drive Assembly and accessible from the left side of the
chassis assembly. The two on the right are accessible from
the rear of the chassis assembly.
3. Six other screws are located around the outside edges of
the rear mounting plate. Remove the plate and set it aside
for reassembly.
3.3 FRONT BEZEL
1. The front bezel can be removed from the unit after the case
and rear mounting plate have been removed as noted in
Paragraphs 3.1 and 3.2.
2. Pullthe brightness and contrast knobs off the pots from the
front.
3. The rear mounting plate removal allows access to the six
bezel-mounting screws. Four screws attach to the outside
flanges of the metal chassis. The other two screws are lo-
cated to the right of the metal partition separating the Disk
Drives from the CRT section of the unit. Access to these
two screws is with a long shank 1/4" nutdriver above and
below the fan assembly.
4. Once these six screws are removed, remove the bezel and
set it aside for reassembly. Exercise care in handling to
prevent scratching or marring the surface.
3.4 TOP COVER/POWER SUPPLY
1. The Power Supply for the Model 4P is located on the un-
derside of the top cover. Remove the case and rear ter-
minal plate as noted in Paragraphs 3.1 and 3.2.
SCREWS
DISK — |
DRIVE
ASSEMBLY
VIEW
REAR
Figure 3-1. Bezel Mounting Screws
2. The cover is attached to the metal chassis with six screws.
Remove these screws and then flip the cover to the right.
A convenient arrangement for storing the cover/power
supply while working on other modules is to reattach the
cover/power supply to the chassis with two screws, allow-
ing the assembly to rest above the disk drive assembly.
3. The power supply is attached to the top cover with four
screws. Remove the connectors attached to the power
supply at the left and then four screws to remove the sup-
ply completely from the unit.
4. When reassembling, ensure that the mylar insulator is po-
sitioned between the power supply and the top cover to
provide proper insulation.
3.5 CATHODE RAY TUBE
The CRT is mechanically attached to the metal chassis with
four screws which are accessible from the front of the unit.
1. Remove the case rear terminal cover, and top cover/power
supply as noted in Paragraphs 3.1, 3.2, 3.3, and 3.4. This
allows access to the connections on the CRT.
2. Disconnect the deflection yoke cable from the CRT PC
board.
2. Disconnect the connector on the rear of the CRT neck
which is attached to a small PC board.
WARNING
The anode of the CRT may have a high voltage charge.
Before removing the high voltage (anode) lead, discharge
the CRT as follows to prevent a serious shock. Connect
one end of a wire to a known good ground and the other
end of the wire to the metal shaft of an insulated-handie
screwdriver. Insert the screwdriver blade under the suction
cup and touch it to the clip holding the high voltage lead.
4. Disconnect the high voltage lead by inserting a grounded
screwdriver under the cup. Use the screwdriver to com-
press the clip and pull the wire free.
5. Disconnect the ground wire (fastened at the splice) to the
CRT neck connector PCB.
CAUTION:
If the CRT is dropped, it may implode. To avoid this kind of
accident, carefully support the CRT when removing it from
the chassis. Do not handle the CRT by the neck as this
may cause the tube to break and cause personal injury.
6. Remove the four screws and washer from the front of the
CRT which attach it to the metal chassis. Carefully slide the
CRT out of the chassis through the front.
3.6 SWEEP BOARD
The CRT Sweep Board is accessible after the CRT is removed
from the unit. It is mounted to the left side of the metal chassis
with four screws. An insulated plate is located between the PCB
and the metal chassis. Make sure this plate is in place on
reassembly.
3.7 MAIN LOGIC PCB
The main logic PCB is a large board nested inside a metal pan
at the bottom of the main metal chassis. To gain access to this
assembly, remove unit parts as noted in Paragraphs 3.1 and
3.2. It is not necessary to remove the power supply assembly,
or the CRT and associated PCB. Remove all connectors at the
rear of the unit. These include the Modem connector, 1/O port
edge-card connector, printer edge-card connector, and floppy
disk edge-card connector.
1. There are four screws on each side of the metal PCB
mounting pan which attach the pan to the metal chassis.
Remove these screws and the board and pan can be re-
moved as a subassembly from the chassis.
2 Atthe front of the board, remove the four connectors at the
left front of the board. These include the reset, video, and
power connectors, and a grounding wire.
3. Nine screws attach the main logic PCB to the metal pan.
The board is spaced away from the pan with raised bosses
stamped into the pan.
3.8 KEYBOARD ASSEMBLY
1. The keyboard assembly is attached to the Main Logic PCB
with a connector located at the right rear of the board. The
PCB must be removed from the pan to allow this connector
to be removed. Therefore, disassembly procedures for the
main PCB must be followed.
2. The keyboard assembly is disassembled by removing the
7 mounting screws from the underside of the assembly.
One of these screws is under a cork non-skid strip and care
should be taken in removing this strip so that itis not ripped
or punctured.
3. Remove the top cover, lift the keyboard PCB from its po-
sitioning bosses, and then remove the keyboard
connector.
4. If the cable assembly requires replacement, feed the con-
nector through the opening in the keyboard base, then in-
stall a tiewrap around the cable just before the insulation
sleeve. This serves as a strain relief for the cable when the
keyboard is reassembled. Ensure that this tiewrap is in the
recess between the opening in the case and the clamping
bosses on the bottom of the case.
5. Also ensure that on reassembly the PCB is properly posi-
tioned on the bosses of the base before attaching the top
cover.
KEYBCARD
CABLE ASSEMBLY
Figure 3-2. Keyboard Cable Strain Relief
3.9 DISK DRIVE ASSEMBLY
The disk drive assembly contains two floppy disk drives. It must
be removed as a subassembly to the main metal chassis before
the mounting screws for the drives themselves are accessible.
1. There are seven mounting screws which attach this
subassembly to the main metal chassis, all of which are
accessible from the right side of the unit. Four of these are
located at the top of the assembly. Two screws are located
under the disk drive assembly at the front, but accessible
with a long shank screwdriver from the right side. A sev-
enth screw mounts a tab to the metal chassis at the rear of
the assembly.
2. After this subassembly is removed from the unit, screws
which mount the drives in the housing are accessible.
There are two screws at the top and one at the bottom.
NOTE:
Do not place a screw in the bottom rear mounting hole
when reinstalling the disk drives into the metal housing. In-
stallation of this screw can cause possible flexing of the
drive and alignment problems.
15
MOUNTING _ DISK DRIVE
SUBASSEMBLY
o
A 2 _ Bio 2
Y
BOTTOM PAN
Figure 3-3. Disk Drive Assembly
RH Side View
3.10 CONTROL MODULE
The control module is attached to the left front of the metal
chassis with two screws. Remove component parts as noted in
Paragraphs 3.1, 3.2, and 3.3 to allow access to the control
module.
1. The module contains the unit power switch, reset switch,
and brightness/contrast controls for the CRT display. All
wiring to the control module is the plug-in kind attached to
terminals or connectors from the rear of the module.
2. If the module is to be removed, tag all wiring so that proper
reassembly is assured.
(O) «LI BRIGHTNESS
(0) -— contrast
| I A — POWER
| ON/OFF
[114 RESET
—
FRONT
O |
AN VIO/GRY
BLK/WHT/VIO
BRN _
BRN —
BLU =
— — BLU
—l PT
ral — [LK
Figure 3-4. Control Module
16
CRT
BOARD
SECTION IV
MAINTENANCE/TROUBLESHOOTING
17
—-
MAINTENANCE/TROUBLESHOOTING
4.1 INTRODUCTION
This section is a general guide for use by service personnel. It
contains the Maintenance and Troubleshooting procedures
necessary to help isolate the problem area to a faulty board or
subsystem. After board or subsystem has been identified, refer
to specific section for more detailed troubleshooting
information.
Refer to the schematics and the theory of operation during
maintenance and troubleshooting for specific checkpoints and
testing.
4.2 MAINTENANCE
The only part of the Model 4P that requires maintenance is the
two Floppy Disk Drives. Periodical cleaning of the Read/Write
Heads are recommended to assure error-free operation. For all
other maintenance or alignments required, refer to Section 5.3
Mini-Disk Drives Maintenance Checks and Adjustments.
4.3 TROUBLESHOOTING
Please be sure that the power cord is properly connected to AC
power before starting troubleshooting.
1. Turn Model 4P “ON” by toggling power switch. If power
light indicator is on then go to 4, if not, go to 2.
2. Recheck AC power and power cord. If okay go to 3, if bad
replace or repair.
3. Check power switch and bulb. if okay go to 1, it bad replace
power switch or bulb.
4. Wait a few seconds for CRT to warm up. Adjust brightness
and contrast at the front of console. If video display comes
on go to 9, if not go to 5.
5. Check power switch. If okay go to 6, if bad replace.
6. Check for AC power at input to power supply. If okay go to
7, if bad replace or repair AC wiring harness.
7. Check power supply for correct output voltages. (Refer to
Power Supply Section 5.4.) If okay go to 8, if bad refer to
Power Supply Troubleshooting 5.3.4.
8. Check for video and sync signals from Main Logic Board at
J9. (Refer to CPU Board Section and Schematic.) If okay
refer to CRT Display Adjustment Section 5.5.2, if bad refer
to CPU Board Troubleshooting Section 5.1.17 or 5.2.17.
9. Does message “The Floppy Disk Drive Is Not Ready” ap-
pear? If yes go to 15, if not go to 10.
19
10.
12.
13.
14.
15.
16.
17.
18.
19.
Does message “Close the Floppy Drive Door And Try
Again” appear? If yes, go to 17, if not go to 11.
. Does message “The Floppy Disk Drive Is Not Available”
appear? If yes then go to 19, if not go to 12.
Does message "CRC Error, Try Again Or Use Another
Disk” appear? If yes then go to 19, if not go to 13.
Does message ‘Seek Error, Try Again Or Use Another
Disk” appear? If yes then go to 19, if not go to 14.
Does any other message appear? If yes then refer to Ap-
pendix B Startup Error Messages in Introduction to Your
Disk System TRS-80 Model 4P, if not then go to 5.
Insert Write Protected Diskette with TRSDOS 6.1.1 or later
into Drive 0, close door and toggle RESET Switch. Does
4P boot up to TRSDOS Logo and prompt for date? If yes
then go to 18, if not then go to 16.
Does message “The Floppy Disk Drive Is Not Ready” still
appear? If yes then go to 17, if not then go to 10.
Try to boot again or use another diskette. If okay go to 18.
If still same message then go to 19. lf another message ap-
pears, goto 9.
This indicates that the problem area exists on the Main
Logic CPU Board. Refer to Section 5.1.17 or 5.2.17 CPU
Board Troubleshooting for more detailed troubleshooting
procedures.
This indicates a hardware failure of Floppy Disk interface
or Floppy Disk Drive. Refer to Section 5.1.17 or 5.2.17
CPU Board Troubleshooting or Section 5.3 Mini-Disk Drive
Maintenance Checks or Adjustments.
SECTION V
4P THEORY OF OPERATION
21
4P THEORY OF OPERATION
5.1 CPU THEORY OF OPERATION
5.1.1 Introduction
Contained in the following paragraphs is a description of the
component parts of the Model 4P CPU. ltis divided into the log-
ical operational functions of the computer. All components are
located on the Main CPU board inside the case housing. Refer
to Section 3 for disassembly/assembly procedures.
5.1.2 Reset Circuit
The Model 4P reset circuit provides the neccessary reset
pulses to all circuits during power up and reset operations. R25
and C218 provide a time constant which holds the input of U121
low during power-up. This allows power to be stable to all cir-
cuits before the RESET™ and RESET signals are applied. When
C218 charges to a logic high, the output of U121 triggers the
input of a retriggerable one-shot multivibrator (U1). U1 outputs
a pulse with an approximate width of 70 microsecs. When the
reset switch is pressed on the front panel, this discharges C218
and holds the input of U121 low until the switch is released. On
release of the switch, C218 again charges up, triggering U121
and U1 to reset the microcomputer.
5.1.3 CPU
The central processing unit (CPU) of the Model 4P microcom-
puter is a Z80A microprocessor. The Z80A is capable of run-
ning in either 2 MHz or 4 MHz mode. The CPU controls all
functions of the microcomputer through use of its address lines
(AO-A15), data lines (D0-D7), and control lines {{M1, /IOREQ,
/RD, /WR, /MREQ, and /RFSH). The address lines (AO-A15)
are buffered to other ICs through two 74LS244s (U68 and U26)
which are enabled all the time with their enables pulled to GND.
The control lines are buffered to other ICs through a 74F04
(U86). The data lines (DO-D7) are buffered through a bi-direc-
tional 74L5245 (U71) which is enabled by BUSEN* and the di-
rection is controlled by BUSDIR*.
5.1.4 System Timing
The main timing reference of the microcomputer, with the ex-
ception of the FDC circuit, comes from a 20.2752 MHz Crystal
Oscillator (Y1). This reference is divided and used for gener-
ating all necessary timing for the CPU, video circuit, and RS-
232-C circuit. The output of the crystal oscillator is filtered by a
territte bead (FBS), 470 ohm resistor (R46), and a 68 pf ca-
pacitor (C242). After being filtered, it is fed into U126, a 16R6A
PAL (Programmable Array Logic), where it is divided by 2 to
generate a 10.1376 MHz signal (10M) for the 64 X 16 video dis-
play. U126 divides the 20.2752 MHz by 4 to generate a 5.0688
MHz signal (RS232CLK) for the baud rate generator in the RS-
232-C circuit. The CPU clock is also generated by U126 which
can be either 2 or 4 MHz depending on the state of FAST input
23
(pin 9 of U126). If FAST is a logic low, the 20.2752 MHz is di-
vided by 10 which generates a 2.2752 MHz signal. If FAST is a
logic high, the 20.2752 MHz is divided by 5 which generates a
4.05504 MHz signal. The CPU clock (PCLK) is fed through an
active pull-up circuit which generates a full 5-volt swing with fast
rise and fall times required by the Z80A. U126, the 16R6A PAL,
generates all symmetrical output signals and also does not al-
low the PCLK output to short cycle or generate a low or high
pulse under 110 nanoseconds which the Z80A also requires.
Refer to System Timing Fig. 5-2.
5.1.4.1 Video Timing
The video timing is controlled by a 10L8 PAL (U127) and a four-
bit synchronous counter U128 (74L5161). These two ICs gen-
erate all the necessary timing signals for the four video modes:
64 x 16, 32 x 16, 80 x 24, and 40 x 24. Two reference clock sig-
nals are required for the four video modes. One reference
clock, the 10.1376 MHz signal (10M), is generated by U126 and
is used by the 64 x 16 and 32 x 16 modes. The second refer-
ence clock is a 12.672 MHz (12M) signal which is generated by
a Phase Locked Loop (PLL) circuit and is used by the 80 x 24
and 40 x 24 modes. The PLL circuit consists of U147 (741593),
U148 (NE564 PLL), and U149 (74LS90). The original 20.2752
MHz clock is divided by 16 through U147 which generates a
1.2672 MHz signal. The output of U147 is reduced in amplitude
by the voltage divider network R27 and R28 and the output is
coupled to the reference input of U148 by C227.
The PLL (NE564) is adjusted to oscillate at 12.672 MHz by the
tuning capacitor C231. This 12.672 MHz clock is then divided
by 10 through U149 to generate a second 1.2672 MHz signal
which is fed to a second input of U148. The two 1.2672 MHz
signals are compared internally to the PLL where it corrects the
12.672 MHz output so it is synchronized with the 20.2752 MHz
clock.
MODSEL and 8064" signals are used to select the desired
video mode. 8064" controls which reference clock is used by
U127 and MODSEL controls the single or double character
width mode. Refer to the following chart for selecting each
video mode.
8064" MODSEL Video Mode
: 0 0 64 x 16
0 1 32x16
1 0 80 x 24
1 1 40 x 24
*This is the state to be written to latch U89. Signal is inverted
before being input to U127.
‚Ноа
sng 0/1
TUNYHEINT
HATIOHINOD
Ноа
HJ003d |
a
ONIWIL =
won pa SENIT VIVO =
Y SINIT TOUINOJ =
SANIT SSIUJAY =
1
=
m na DNIWIL
TYNHALXI =
——
L
YALNTUAd
ANT 0/1
Е
<
agvod WYH
SOIBIVID
m
=
LYOd WYH =
ANNOS OAGTA
LINOWIS
LYOd OJQIA
OTOIA ONY
Эно
ОНМЧОНАЧУ
LL UH
agram
-1. Model 4P Functional Block Di
5
Figure
24
| | | I ] (LT NId 9ZTN
WTOZEZSA
| =] (61 NId 92TN)
Г (1SVA) WTID4
| 1 [C(8T NId эста)
(DSYA) LISA
J | (61 NId 9ZTN)
— L Г. (I1SVA) Мята
f 1 (8T NId 9ZTN)
| À Г (1SVA) LASd
I 1 Г” 1 [(€T NIG 9zTn)
55°
| “LL | | | (YT NIE 9710)
Sg
Г 1 Г Г Г posi NId 9ZTN)
SOT
WT
WAZ
Igz ‘OW gz
Figure 5-2. System Timing
25
DCLK, the reference clock selected, is output from U127. DCLK
is fed back into U127 for internal timing reference and is also
fed to the clock input of U128 (74LS161). U128 is configured to
preload with a count of 9 each time it reaches a count of 0. This
generates a signal output of TC (128 pin 15) that occurs at the
start of every character time of video output. TC is used to gen-
erate LOADS* (Load Shift Register). QA and QC of U128 are
used to generate SHIFT*, XADR7", CRTCLK and LOAD" for
proper timing for the four video modes. QA, QB, and QC which
are referred to as H, |, and J are fed to the Graphics Port J7 for
reference timings of Hires graphics video. Refer to Video Tim-
ing, Figs. 5-3 and 5-4 for timing reference.
5.1.5 Address Decode
The Address Decode section will be divided into two subsec-
tions: Memory Map decoding and Port Map decoding.
5.1.5.1 Memory Map Decoding
Memory Map Decoding is accomplished by a 16L8 PAL (U109).
Four memory map modes are available which are compatible
with the Model lil and Mode! 4 microcomputers. A second 16L8
PAL (U110) is used in conjunction with U109 for the memory
map control which also controls page mapping of the 32K RAM
pages. Refer to Memory Maps below.
5.1.5.2 Port Map Decoding
Port Map Decoding is accomplished by three 741.5138s (U87,
UB8, and U107). These ICs decode the low order address (AO-
A7) from the CPU and decode the port being selected. The IN*
signal from U108 enables U87 which allows the CPU to read
from a selected port and the OUT" signal, also from U108, en-
ables U8B8 which allows the CPU to write to the selected port.
U107 only decodes the address and the IN* and OUT" signals
are ANDed with the generated signals.
5.1.6 ROM
The Model 4P contains only a 4K x 8 Boot ROM (U70). This
ROM is used only to boot up a Disk Operating System into the
RAM memory. If Model lll operation or DOS is required, then
the RAM from location 0000-37FFH must be loaded with an im-
age of the Model Ill or 4 ROM code and then executed. A sys-
tem program called MODEL A/lll is supplied with the Model 4P
to provide the ROM image for proper Mode! Ill operation. On
power-up, the Boot ROM is selected and mapped into location
0000-0FFFH. If the Boot ROM is not required after boot up, the
Boot ROM must be mapped out by OU Ting to port SCH with DO
set or by selecting Memory Map modes 2 or 3. In Mode 1 the
RAM is write enabled for the full 14K. This allows the RAM area
mapped where Boot ROM is located to be written to while ex-
ecuting out of the Boot ROM. Refer to Memory Maps.
The Model 4P Boot ROM contains all the code necessary to
initialize hardware, detect options selected from the keyboard,
read a sector from a hard disk or floppy, and load a copy of the
Model Ill ROM-image (as mentioned) into the lower 14K of
RAM.
The firmware is divided into the foliowing routines:
* Hardware Initialization
* Keyboard Scanner
* Control
* Floppy and Hard Disk Driver
* Disk Directory Searcher
* File Loader
* Error Handler and Displayer
* RS$-232 Boot
* Diagnostic Package
Theory of Operation
This section describes the operation of various routines in the
ROM. Normally, the ROM is not addressable by normal use.
However, there are several routines that are available through
fixed calling locations and these may be used by operating sys-
tems that are booting.
On a power-up or RESET condition, the Z80's program counter
is set to address 0 and the boot ROM is switched-in. The mem-
ory map of the system is set to Mode O. (See Memory Map for
details.) This will cause the Z80 to fetch instructions from the
boot ROM.
The Initialization section of the Boot ROM now performs these
functions:
. Disables maskable and non-maskable interrupts
. Interrupt mode 1 is selected
. Programs the CRT Controller
. Initializes the boot ROM control areas in RAM.
. Sets up a stack pointer
. Issues a Force Interrupt to the Floppy Disk Controller
to abort any current activity
. Sets the system clock to 4mhz
. Sets the screen to 64 x 16
9. Disables reverse video and the alternate character
sets
10. Tests for < . > key being pressed”
11. Clears all 2K of video memory
60 Nn LE WOW —
Oo <<
* This is a special test. If the < . > is being pressed, then
control is transferred to the diagnostic package in the
ROM. All other keys are scanned via the Keyboard
Scanner.
» LHAYYX
ATOLED
+ VOI
y SOYOT
y L TT HS
ON
JL
r
I
H
y 100
MIDA
UU US wer ‘кит
80 x 24 Mode
64 x 16 Mode
Figure 5-3. Video Timing
27
| al | 1 | * LEX
XTILUO
AL ML
+ ОМ ОЧ
— I
J WE x SAYOT
Je Imo IE SL LIEST LaTRS
— 1 f gen
— LT 1 >
À ] LL | L г
х ЮО
УЧ 20
WZT ‘WAT
40 x 24 Mode
32 x 16 Mode
Figure 5-4. Video Timing
28
The Keyboard scanner is now called. It scans the keyboard for
a set period of time and returns several parameters based on
which, if any, keys were pressed.
The keyboard scanner checks for several different groups of
keys. These are shown below:
Function Group
<F1>
<F2>
<F3>
<1>
<2>
<>
<Left-Shift>
<Right-Shift>
<Ctrl>
<Caps>
Selection Group
о MOD >
Special Keys
<P>
<L>
<N>
Misc Keys
<Enter>
<Break>
When any key in the Function Group is pressed, it is recorded
in RAM and will be used by the Control routine in directing the
action of the boot. If more than one of these keys are pressed
during the keyboard scan, the last one detected will be the one
that is used. The Function group keys are currently defined as:
Will cause hard disk boot
Will cause floppy disk boot
Will force Model Ill mode
Reserved for future use
Boot from RS-232 port
Reserved for future use
Reserved for future use
<F1> or <1>
<F2> or <2>
<F3> or <3>
<Left-Shift=
<Right-Shift>
<Gtrl>
<Caps>
The Special keys are commands to the Control routine which
direct handling of the Model lll ROM-image. Each key is de-
tected individually.
<P> When loading the Model Ill
ROM-image, the user will be
prompted when the disks can
be switched or when ROM
BASIC can be entered by
pressing <Break:>.
Instructs the Control routine to
not load the Model l|| ROM-
image, even if it appears that
the operating system being
booted requires it.
<N>
29
Instructs the Control routine to
load the Model III ROM-image,
even if it is already loaded. This
is useful if the ROM-image has
been corrupted or when switch-
ing ROM-images. (Note that
this will not cause the ROM-
image 10 be loaded if the boot
sector check indicates that the
Model II ROM image is not
needed. Press <F37 or <F37
and = L> to accomplish that.
<L>
The Selection group keys are used in determining which file will
be read from disk when the ROM-image is loaded, For details
of this operation, see the Disk Directory Searcher. If more than
one of the Selection group keys are pressed, the last one de-
tected will be the one that is used.
The Miscellaneous keys are:
<Break> Pressing this key is simpiy re-
corded by setting location
405BH non-zero. lt is up to an
operating system to use this
flag if desired.
Terminates the Keyboard rou-
tine. Any other keys pressed up
to that time will be acted upon.
< Enter is useful for experi-
enced users who do not want to
wait until the keyboard timer
expires.
<Enter>
The Control section now takes over and follows the following
flowchart.
Begin
<F1>
or <l>
pressed 7
<F2>
or <2>
pressed ?
<F3>
or <3>
pressed ?
No
<Right- Shift>
pressed ?
At this point,
No
ARCNET
Controller
Board
Present ?
NO
D
®
Yes
(1) (Hard Disk Boot]
Yes Goto [2]
(2) {Floppy Disk Boot)
Yes Goto [3]
(3) {Model III Boot)
Yes Goto [4]
(R5-232 Boot)
have been pressed.
Display an error
message. (ARCNET
Boot ROM required
for ARCNET Boot)
Hard
Disk Drive
Present ?
Attempt to
read boot
sector
Yes An
<F1>
or <l>
pressed ?
No
no valid Function keys
Floppy
Disk Drive
Present ?
No
error
Display
Yes Hard Disk
Error
Message
Stop
Attempt to
read boot
sector
Yes
<F2>
or <2>
pressed ?
Yes
Display
Floppy Disk
Error
Message
No
Stop
Model III
ROM Image
Present ?
Note: 3
<N>
nressed
7
Sector
256 bytes,
Model III
pr
Yes
and no ref.s
Set Transfer
Address to
4309H
Note: 2
<L>
assed
?
1
31
/
Transfer
Address to
38915H
Note: 2
Attempt to
locate
ROM Image
on
Floppy Disk
Note: 4
Write-enable
P-37FFH
{Mode 1)
Load ROM
Image
Note: 5
Errors
while loading
ROM Image ?
Display
Set Transfer Error
Address at end Message
of ROM Image
(Normally [email protected])
Note: 2 Y
Stop
ROM
Image
Present ?
<P>
pressed
>
+
Display
"ROM Image
is loaded"
message
Wait for
<ENTER> or
<BREAK> to
be pressed
Write-protect
memory (Mode $)
Set CPU speed
to 2MHz
Switch boot RCM
out of Memory
Jump to
Transfer Address
Initialize
RS-232 Port
Note: 6
Wait for
Carrier Detect
Determine
Correct
Baud Rate
Transmit Baud
Rate Detect
Message
Wait for
Sync Byte
(РЕН)
Load program
from RS-232
Display and
transmit error
Transfer
control
to address
received
Notes:
(1) If the boot sector was not 256 bytes in length, then it is as-
sumed to be a Model ill package, and the ROM-image will
be needed. If the sector is 256 bytes in length, then the
sector is scanned for the sequence CDxx00H. The CD is
the first byte of a Z80 unconditional subroutine call. The
next byte can have any value. The third byte is tested
against a zero. What this check does is test for any refer-
ences to the first 256 bytes of memory. All Radio Shack
Model Ill operating systems, and many other packages all
reference the ROM at some point during the boot sector,
Most boot sectors will display a message if the system can-
not be loaded. To save space, these routines use the
Model Ill ROM calls to display the message. Several ROM
calls have their entry points in the first 256 bytes of mem-
Ory, and these references are detected by the boot ROM.
33
Packages that do not reference the Model! II! ROM in the
boot sector can still cause the Model Ill ROM image to be
loaded by coding a CDxx00 somewhere in the boot sector.
It does not have to be executable. At the same time, Моде!
4 packages must take care that there is no sequence of
bytes in the boot sector that could be mis-interpreted to be
a reference to the Boot ROM. An example of this would be
sequence O6CDOE00, which is a LD B,OCDH and a LD
C,0. If the boot sector cannot be changed, then the user
must press the <F3> key each time the system is started
to inform the ROM that the disk contains a Model IH pack-
age which needs the Model III ROM-image.
If you are toading a Model 4 operating system, then the
boot ROM will always transfer control to the first byte of the
boot sector, which is at 4300H. 1f you are loading a Model
IH operating system or about to use Model III ROM BASIC,
then the transfer address is 3015H. This is the address of
a jump vector in the “C” ROM of the Model II! ROM image,
and this will cause the system io behave exactly like a
Mode! III. If the ROM-image file that is loaded has a differ-
ent transfer address, then that address will be used when
loading is complete. If the image is already present, it will
use 3015H.
(3) Two different tests are done to insure that the Model |||
ROM image is present. The first test is to check ever third
location starting at 3000H for a C3H. This is done for 10 lo-
cations. If any of these locations does not contain a C3H,
then the ROM image is considered to be ‘not present”.
The next test is to check two bytes at location OOOBH. №
these addresses contain E9E1H, then the ROM image is
considered to be “present”.
(4) See Disk Director Searcher for more information.
(5) See File Loader for more information.
(6) The RS-232 loader is described under RS-232 Boot.
Disk Directory Searcher
When the Model [Il ROM image is to be loaded, it is always read
from the floppy in drive O.
Before the operation begins, some checks are made. First, the
boot sector is read in from the floppy and the first byte is
checked to make sure it is either a 00H or a FEH. If the byte
contains some other value, no attempt will be made to read the
ROM image trom that disk. The location of the directory cylinder
Is then taken from the boot sector and the type of disk is deter-
mined. This is done by examining the Data Address Mark that
was picked up by the Floppy Disk Controller (FDC) during the
read of the sector. If the DAM equals 1, the disk is a TRSDOS
1.x style disk. If the DAM equals 0, then the disk is a LDOS 5.1/
TRSDOS 6 style disk. This is important since TRSDOS 1.x
disks number sectors starting with 1 and LDOS style disks
number sectors starting with 0.
Once the disk type has been determined, an extra test is made
if the disk is a LDOS style disk. This test reads the Granule Al-
location Table (GAT) to determine if the disk is single sided or
double sided.
The directory is then read one record at a time and a compare
is made against the pattern 'MODEL% for the filename and
IH for the extension. The '%' means that any character will
match this position. If the user pressed one of the selection
keys (A-G) during the keyboard scan, then that character is
substituted in place of the '%’ character. For example, if you
pressed 'D’, then the search would be for the file ' MODELD ;
with the extension 'lII'. The searching algorithm searches until
it finds the entry or it reaches the end of the directory.
Once the entry has been found, the extent information for that
file is copied into a control block for later use.
File Loader
The file loader is actually two modules — the actual loader and
a set of routines to fetch bytes from the file on disk. The loader
is invoked via a RST 28H. The byte fetcher is called by the
loader using RST 20H. Since restart vectors can be re-directed,
the same loader is used by the RS-232 boot. The difference is
that the RST 20H is redirected to point to the RS-232 data re-
ceiving routine. The loader reads standard loader records and
acts upon two types:
01 Data Load
1 byte with length of block, including address
1 word with address to load the data
n bytes of data, where n + 2 equals the length specified
02 Transfer Address
1 byte with the value of 02
1 word with the address to start execution at.
Any other loader code is treated as a comment block and is ig-
nored. Once an 02 record has been found, the loader stops
reading, even if there is additional data, so be sure to place the
02 record at the end of the file.
34
Floppy and Hard Disk Driver
The disk drivers are entered via RST 8H and will read a sector
anywhere on a floppy disk and anywhere on head 1 (top-head”
in a hard disk drive. Either 256 or 512 byte sectors are readable
by these routines and they make the determination of the sector
size. Thehard disk driver is compatible with both the WD1000
and the WD1010 controllers. The floppy disk driver is written for
the WD1793 controller.
Serial Loader
Invoking the serial loader is simitar to forcing a boot from hard
disk or floppy. In this case the right shift key must be pressed at
some time during the first three seconds after reset. The pro-
gram does not care if the key is pressed forever, making it con-
venient to connect pins 8 and 10 of the keyboard connector with
a shorting plug for bench testing of boards. This assumes that
the object program being loaded does not care about the key
closure,
Upon entry, the program first asserts DTR (J4 pin 20) and RTS
(J4 pin 4) true. Next, “Not Ready” is printed on the topmost line
of the video display. Modem status line CD (J4 pin 8) is then
sampled. The program loops until it finds CD asserted true. At
that time the message “Ready” is displayed. Then the program
sets about determining the baud rate from the host computer.
To determine the baud rate, the program compares data re-
ceived by the UART to atest byte equal to '55' hex. The receive
is first set to 19200 baud. If ten bytes are received which are not
equal to the test byte, the baud rate is reduced. This sequence
is repeated until a valid test byte is received. If ten failures occur
at 50 baud, the entire process begins again at 19200 baud. If a
valid test byte is received, the program waits for ten more to ar-
rive before concluding that it has determined the correct baud
rate. If at this time an improper byte is received or a receiver er-
ror (overrun, framing, or parity) is intercepted, the task begins
again at 19200 baud.
In order to get to this point, the host or the modem must assert
CD true. The host must transmit a sequence of test bytes equal
to '55' hex with 8 data bits, odd parity, and 1 or 2 stop bits. The
test bytes should be separated by approximately 0.1 second to
avoid overrun errors.
When the program has determined the baud rate, the message:
“Found Baud Rate x”
is displayed on the screen, where "x" is a letter from A to P,
meaning:
А — 50baud E = 150 | = 1800 M = 4800
B=75 F = 300 J = 2000 N = 7200
С = 110 G — 600 K = 2400 O = 9600
D = 134.5 Н = 1200 | = 3600 Р = 19200
The same message less the character signifying the baud rate
is transmitted to the host, with the same baud rate and protocol.
This message is the signal to the host to stop transmitting test
bytes.
After the program has transmitted the baud rate message, it
reads from the UART data register in order to clear any overrun
error that may have occurred due to the test bytes coming in
during the transmission of the message. This Is because the re-
ceiver must be made ready to receive a sync byte signalling the
beginning of the command file. For this reason, it is important
that the host wait until the entire baud rate message (16 char-
acters) is received before transmitting the sync byte, which is
equal to 'FF' hex.
When the loader receives the sync byte, the message:
“Loading”
is displayed on the screen. Again, the same message is trans-
mitted to the host, and, again, the host must wait for the entire
transmission before starting into the command file.
If the receiver should intercept a receive error while waiting for
the sync byte, the entire operation up to this point is aborted.
The video display is cleared and the message:
“Error, x”
is displayed near the bottom of the screen, where ‘x’ is a letter
from B to H, meaning:
B = parity error
C = framing error
D = parity & framing errors
E = overrun error
Р = parity & overrun errors
G = framing & overrun errors
H = parity & framing & overrun errors
The message:
“Error”
is then transmitted to the host. The entire process is then re-
peated from the “Not Ready” message. A six second delay is
inserted before reinitialization. This is longer than the time re-
quired to transmit five bytes at 50 baud, so there is no need to
be extra careful here.
If the sync byte is received without error, then the “Loading”
message is transmitted and the program is ready to receive the
command file. After receiving the “Loading” message the host
can transmit the file without nulls or delays between bytes.
35
(Since the file represents Z80 machine code and all 256
combinations are meaningful, it would be disastrous to
transmit nulls or other ASCII controi codes as fillers, ac-
knowledgement, or start-stop bytes. The only control
codes needed are the standard command file control
bytes.)
Data can be transmitted to the loader at 19200 baud with no de-
lays inserted. Two stop bits are recommended at high baud
rates.
See the File Loader description for more information on file
loading.
If a receive error should occur during file loading, the abort pro-
cedure described above will take place, so when attempting re-
mote control, it is wise to monitor the host receiver during
transmission of the file. When the host is near the object board,
as is the case in the factory application, or when more than one
board is being loaded, it may be advantageous or even nec-
essary to ignore the transmitted responses of the object
board(s) and to manually pace the test byte, sync byte, and
command file phases of the transmission process, using the
video display for handshaking.
System Programmers Information
The Model 4P Boot ROM uses two areas of RAM while itis run-
ning. These are 4000H to 40FFH and 4300H to 43FFH. (For
512 byte boot sectors, the second area is 4300H to 44FFH.} If
the Model [Il ROM Image is loaded, additional areas are used.
See the technical reference manual for the system you are us-
ing for a list of these areas.
Operating systems that want to support a software restart by re-
executing the contents of the boot ROM can accomplish this in
one of two ways. If the operating system relies on the Model Il
ROM-Image, then jump to location 0 as you have in the past. If
the operating system is a Model 4 mode package, a simple way
is to code the following instructions in your assembly and load
them before you want to reset:
Absolute Location Instruction
0000 DI
0001 LD À,1
0003 OUT (9CH),A
These instructions cause the boot ROM to become address-
able. After executing the OUT instruction, the next instruction
executed will be one in the boot ROM. (These instructions also
exist in the Model lil ROM image at location 0.) The boot ROM
has been written so that the first instruction is at address 0005.
The hardware must be in memory mode 0 or else the boot ROM
will not be switched in. This operation can be done with an OUT
instruction and then a RST 0 can be executed to have the ROM
switched in.
Restarts can be redirected at any time while the ROM is
switched in. All restarts jump to fixed locations in RAM and
these areas may be changed to point to the routine that is to be
executed.
Restart RAM Location Default Use
0 none Cold Start/Boot
8 4000H Disk 1/0 Request
10 4003H Display string
18 4006H Display block
20 4009H Byte Fetch (Called by Loader)
28 400CH File Loader
30 400FH Keyboard scanner
38 4012H Reserved for future use
66 4015H NM! (Floppy МО Command
Complete)
The above routines have fixed entry parameters. These are de-
scribed here.
Disk I/0 Request (RST 8H)
Accepts
A 1 for floppy, 2 for hard disk
B Command
Initialize 1
Restore 4
Seek 6
Read 12 (All reads have an im-
plied seek)
GC Sector number to read
The contents of the location disktype
(405CH) are added to this value before
an actual read. If the disk is a two sided
floppy, just add 18 to the sector number.
DE Cylinder number. (Only E is used in
floppy operations)
HL Address where data from a read opera-
tion is to be stored.
Returns
Z Success, Operation Completed
NZ Error, Error code in A
Error Codes
3 Hard Disk drive is not ready
4 Floppy disk drive is not ready
5 Hard Disk drive is not available
6 Floppy disk drive is not available
7 Drive Not Ready and no Index (Disk in
drive, door open)
8 CRC Error
9 Seek Error
11 Lost Data
12 ID Not Found
Display String (RST 10H)
Accepts
HL Pointer to text to be displayed.
Text must be terminated with a null (0).
DE Offset position on screen where text is to
be displayed.
(A 0000H will be the upper left-hand cor-
ner of the display.)
Returns
Success Always
A Altered
DE Points to next position on video
HL Points to the null (0).
Display Block (RST 18H)
Accepts
HL Points to control vector in the format:
+0 Screen Offset
+2 Pointer to text, terminated with
null
+4 Pointer to text, terminated with
null
+n word FFFFH End of control
vector
or +n word FFFEH Next word is
new Screen
Offset
If Z flag is set on entry, then the first screen offset is read from
DE instead of from the control vector.
Each string is positioned after the previous string, unless a
FFFEH entry is found. This is used heavily in the ROM to re-
duce duplication of words in error messages.
Returns
Success Always
DE Points to next position on video
Byte Fetch (RST 20H)
Accepts None
Returns
Z Success, byte in À
NZ Failure, error code in À
Errors
Any errors from the disk I/O call and:
2 ROM Image can't be loaded — Too many
extents
10 ROM Image can't be loaded — Disk drive
is not ready
Flle Loader (RST 28H)
Accepts None
Returns
2 Success
NZ Failure, error code in A
Errors
Any errors from the disk 1/0 call of the
byte fetch call and:
0 The ROM image was not found on drive O
There are several pieces of information left in memory by the
boot ROM which are useful to system programmers. These are
shown below:
RAM Location Description
401DH ROM Image Selected (% for none
selected or A-G)
4055H Boot type
1 = Floppy
2 = Hard disk
3 = ARCNET
4 = RS-232C
5-7 = Reserved
4056H Boot Sector Size (1 for 256, 2 for 512)
4057H RS-232 Baud Rate (only valid on RS-
232 hoot)
4059H Function Key Selected
0 = No function key selected
<Р1> ог<1> = 86
<F2> or <2> 87
<F3> or <3> 88
<Caps> 85
<Ctrl> 84
<Left-Shift> 82
<Right-Shift> 83
Reserved 80-81 and 89-90
405BH Break Key Indication (non-zero if
<Break> pressed)
405CH Disk type (0 for LDOS/
TRSDOS 6,1 for
TRSDOS 1.x)
Keep in mind that Model IH ROM image will initialize these
areas, so this information is useful only to the Model 4 mode
programmer.
5.1.7 RAM
Two configurations of Random Access Memory (RAM) are
available on the Model 4P: 64K and 128K. The 64K and 128K
option use the 6665-type 64K x 1 200NS Dynamic RAM, which
requires only a single + 5v supply voltage.
37
The DRAMs require multiplexed incoming address lines. This
is accomplished by ICs U111+ and U112 which are 74L5157
multiplexers. Data to and from the DRAMs are buffered by a
741.5245 (U117) which is controlled by Page Map PAL, U110.
The proper timing signals RASO*, RAS1*, MUX*, and CAS” are
generated by a delay line circuit U97. U115 (1/2 of a 745112)
and U116 (1/4 of a 74F08) are used the generate a precharge
circuit. During M1 cycles of the Z80A in 4 MHz mode, the high
time in MREQ has a minimum time of 110 nanosecs. The spec-
ification of 6665 DRAM requires a minimum of 120 nanosecs so
this circuit will shorten the MBEQ signal during the M1 cycle.
The resulting signal PMREQ is used to start a RAM memory
cycle through U113 (a 74564). Each different cycle is controlled
at U113 to maintain a fast M1 cycle so no wait states are re-
quired. The output of U113 (PRAS*) is ANDed with RFSH to not
allow MUX" and CAS* to be generated during a REFRESH
cycle. PRAS* also generates either RASO* or RAS1*, depend-
ing on which bank of RAM the CPU is selecting. GCAS” gen-
erated by the delay line U97 is latched by U115 (1/2 of a
745112) and held to the end of the memory cycle. The output
of U115 is ANDed with VIDEO signal to disable the CAS" signal
from occurring if the cycle is a video memory access. Refer to
M1 Cycle Timing (Figure 5-8. and 5-9.), Memory Read and
Memory Write Cycle Timing (Figure 5-10.) and (Figure 5-11.).
AG g = НОМ
АЙ o = TTAS
AB g = gIHsS
TIJAHT HIVIS
WYE Nz сту) ”” | ze wed
Wed Yet
(DIG)
(ATT)
(HDYdDUS
'HOVANE ‘чочабна)
js aE. aE ES A
AIT WYVE
a
AT OJXGIA
XT CAMA
AINO CVHN
APT WYY
Ag T = WOY
Ag a = [TAS
Ag й = glas
THAHT AIYLS
WY MZE (TT) » MZ2t WYH
(OTE)
M91 WYN
Wa YE (MTI) zum SUCCIÓN
XT C9ASM
(H9VADES
'HIVYANA “99YdSHd) E AINO avdd
MAT WYY
Xy WON 1008
8 00W
# HGON
Figure 5-5. Memory
38
АЙ T = WOH
AB g = [185
AG T = gTHS
THANT LY LS
WYM MZE TTD an
(g1'd}
AZE WYH
Jo — o — Say a
WYY MZE
HOT WH
(B'1'T1T) > MT 09dIA
YT CHA
(A9YdIYS
'SIYANA '99YdS0)
MPT WYH
AS й = WOM
AB y = TIXS
AS I = 195
THAUT LY LS
WYH WZE
ID 7 NZ£ WYy
(g‘T1’‘g)
ha aE A SEs ay al: ar En a owe ol
MOT WVHA
WHvä MCE duo » XT OJdIÍA
MT QOUAHM
(ADYdI3HS
“HOVANH ‘HOYVASHA) AF LINO TITHM
HPT МЧ
Xt WON 100d
T CON
T COW
Figure 5-6. Memory
39
X = WOy
AS T = 1745
AS T = PIS
THAT ULYLS
ИМЯ MZE pe ZTE WYN
(IT)
WYd XZE
(‘т’)
(MDYdOHS
“HOVANZ ‘ADVYASHO)
E JOOW
XZE WYU
X = WOH
AS T = T'IHS
AB g = #795
THAT J LYLE
NZ OHOIA
—Ñ—————]] o
AT OGAUN
HYH “ZE — Ти» A6Z WH
(IT)
fa EE нь N |
WYH MZE
(B*1‘1)}
{dDV¥dods
“HOVANA ‘“JOVASHA)
© JaOW
ju dos — NX |
ACE NV
Figure 5-7. Memory
40
HO] 7 wily
H Gl FT WC
woes LL
aBUEYVOI [AA
aJuLenad.. E
Ubi, 5, 7 Ol H wey лор нос.)
abuegd (ras abueyo ON
LAA JA Palas
êleis sbueu3 Aux XX pies, PLEA
Bey 2:83 | USG ЭН Ал ЭН Ели
inang indu oa ind) indu rome
SHHOIIAVA
x 4
— viva aIVA) г аи-йая
“dav HSdUAdI MN "day 165 NX dav mou XA Lvua-gvua
J L
x SYD
* X AN
| 1 — »x[SYU
10 4GSYA
\ | \ + INASTA
10 xÿNASYU
\ | |
+ ОМУ На
— МНН
1 | Озниа
HSA
Г ad
r Od IW
— W
X STV-0Y
(ZHWZ )
| Tod
L Ez
Figure 5-8. M1 Cycle Timing (2MHZ) 100ns/dir.
41
{ YIVA JITYA > LOW-gOR
“dav ESSUudHA Xx CE X adv mox YY 1yaa-gwua
+5V0
» X [IW
TSYH
1 J L 10 USVA
LJ 1 + TNASYH
10 4 GNASVA
жом на
A | МЯЧИ Ч
] | | OTUWA
r HSA
Г a
Г f OHM
\ PO °®
xX } STV-6V
ws se
Figure 5-9. M1 Cycle Timing (4MHZ) 50ns/dir.
42
pre
VIC QGITUVA
—
“dav “TOD
EX “adv MO
L
L AW- 9 aW
LYBO-GVIC
М
»SYD
x X OWN
x TSUVA
ло x PSYA
1 x INASVH
10 x09NASVY
+ ЭМ ча
f МЧ ОНИ
OHYWd
ad
OF UW
rd
X STY-GY
Г уча
Figure 5-10. Memory Read Cycle Timing
43
ММО HLIUM
LAN —9aN
AY
“dav “TOD
A
“dav MON
NTE <<
x» SYD
x X IN
x TSYEH
10 SV
—
] x INASVY
10 xANYSVY
x SYUd
| NAUMWNYVE
CHYIWS
UM
CHAN
Y STY-ÓYV
\ rr Уча
Figure 5-11. Memory Write Cycle Timing
44
Mode 0
0000 — OFFF
1000 — 37FF
37E8 — 37E9
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode 0
0000 — 37FF
37E8 — 37E9
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode 1
0000 — OFFF
0000 — OFFF
1000 — 37FF
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Memory Map — Model 4P
SELO
SEL1
ROM
=0 =0V
= 0 =0V
= 1 = OV
Boot ROM
RAM (Read Only)
Printer Status (Read Only)
Keyboard
Video
RAM
SELO = 0 = OV
SEL1
ROM
SELO
SEL1
ROM
OV
+5V
= 0
= 0
Ц
RAM (Read Only)
Printer Status (Read Only}
Keyboard
Video
RAM
I
—
|
- + 5\
= OV
1 = OV
|
©
Boot ROM
RAM (Write Only)
RAM
Keyboard
Video
RAM
4K
10K
1K
1K
48K
14K
1K
1K
48K
4K
4K
10K
1K
1K
48K
45
Mode 1
0000 — 37FF
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode 2
0000 — F3FF
F400 — F7FF
F800 — FFFF
Mode 3
0000 — FFFF
SELO = 1 = +5V
SEL1 =0 = OV
ROM = 0 = +5V
RAM
Keyboard
Video
RAM
SELO = 0 = OV
SEL1 = 1 = +5V
ROM = X = Don't Care
RAM
Keyboard
Video
SELO =1 = +5V
SEL1 =1 = +5V
ROM = X = Don't Care
RAM
14K
1K
1K
48K
61K
1K
2K
64K
I/O Port Assignment
Normally
Port # Used
FC — FF FF
F8 — FB F8
F4 — F7 F4
FO— F3 —
FO FO
F1 F1
F2 F2
F3 F3
ЕС — ЕЁ ЕС
ЕВ — ЕВ —
ЕВ E8
E9 E9
EA EA
EB EB
Е4 — E7 Е4
ЕО — E3 ЕО
AD — DF —
9C — 9+ aC
94 — 8B —
90 — 93 90
8C -— BF —
88 — 8B —
88, BA 88
89, 8B 89
84 — 87 84
80 — 83 —
Out
CASSOUT *
LPOUT *
DRVSEL *
DISKOUT *
FDC COMMAND REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
MODOUT *
RS2320UT *
UART MASTER RESET
BAUD RATE GEN. REG.
UART CONTROL AND
MODEM CONTROL REG.
UART TRANSMIT
HOLDING REG.
WR NMI MASK REG. *
WR INT MASK REG. *
(RESERVED)
BOOT *
(RESERVED)
SEN *
GSELO*
CRTCCS *
CRCT ADD. REG.
CRCT DATA REG.
OPREG *
GSEL1 *
In
MODIN*
СРМ"
(RESERVED)
DISKIN *
FDC STATUS REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
RTCIN *
RS232IN *
MODEM STATUS
(RESERVED)
UART STATUS REG.
UART HOLDING REG.
(ВЕЗЕТ О.В.)
RD NMI STATUS *
RD INT MASK REG. *
(RESERVED)
(RESERVED)
(RESERVED)
(RESERVED)
GSELO *
(RESERVED)
(RESERVED)
(RESERVED)
(RESERVED)
GSEL1*
46
I/O Port Description
CASSOUT *
Name:
Port Address: FC — FF
Access: WRITE ONLY
Description: Output data to cassette or for sound
generation
Note: The Model 4P does not support cassette storage,
this port is only used to generate sound that was to
be output via cassette port. The Model 4P sends
data to onboard sound circuit.
DO = Cassette output level (sound data output)
DA = Reserved
D2 — D7 = Undefined
Name: MODIN * (CASSIN *)
Port Address: FC — FF
Access: READ ONLY
Description: Configuration Status
DO = 0
D1 = CASSMOTORON STATUS
D2 = MODSEL STATUS
D3 = ENALTSET STATUS
D4 = ENEXTIO STATUS
D5 = (NOT USED)
DE = FAST STATUS
D7 = 0
Name: LPOUT *
Port Address: F8 — FB
Access: WRITE ONLY
Description: Output data to line printer
D0 —D7 = ASCIIBYTE TO BE PRINTED
47
Name: LPIN *
Port Address: F8 — FB
Access: READ ONLY
Description: Input line printer status
DO —D3 = (RESERVED)
D4 = FAULT
1 = TRUE
0 = FALSE
D5 = UNIT SELECT
1 = TRUE
0 = FALSE
D6 = OUTPAPER
1 = TRUE
0 — FALSE
D7 = BUSY
1 = TRUE
0 = FALSE
Name: DAVSEL *
Port Address: F4 — F7
Access: WRITE ONLY
Description: Output FDC Configuration
Note: Output to this port will ALWAYS cause a 1-2 mscc.
(Microsecond) wait to the Z80.
DO = DRIVE SELECT 0
D1 — DRIVE SELECT 1
D2 — (RESERVED)
D3 = (RESERVED)
D4 = SDSEL
0 = SIDE O
1 = SIDE 1
D5 = PRECOMPEN
0 = No write precompensation
1 = Write Precompensation enabled
D6 = WSGEN
0 = No wait state generated
1 = wait state generated
Note: This wait state is to sync Z80 with FDC chip during
FDC operation.
D7 = DDEN *
0 = Single Density enabled (FM)
= Double Density enabled (MFM)
Name: DISKOUT *
Port Address: FO — F3
Access: WRITE ONLY
Description: Output to FDC Control Registers
Port FO = FDC Command Register
Port F1 = FDC Track Register
Port F2
FDC Sector Register
Port F3 = FDC Data Register
(Refer to FDC Manual for Bit Assignments)
Name: DISKIN *
Port Address: FO — F3
Access: READ ONLY
Description: Input FDC Control Registers
Fort FO
|!
FDC Status Register
Port F1 = FDC Track Register
Port F2 = FDC Sector Register
Port F3 = FDC Data Register
(Refer to FDC Manual for Bit Assignment)
Name: MODOUT *
Port Address: EC — EF
Access: WRITE ONLY
Description: Output to Configuration Latch
DO = (RESERVED)
D1 = CASSMOTORON (Sound enable)
0 = Cassette Motor Off (Sound enabled)
1 = Cassette Motor On (Sound disabled)
D2 = MODSEL
0 = 64 or 80 character mode
1 = 32 or 40 character mode
D3 = ENALTSET
0 = Alternate character set disabled
1 = Alternate character set enabled
D4 = ENEXTIO
0 = External 10 Bus disabled
1 = External IQ Bus enabled
D5 = (RESERVED)
DE = FAST
0 = 2 MHZ Mode
1 = 4 MHZ Mode
D7 = (RESERVED)
Name: RTCIN *
Port Address: EC — EF
Access: READ ONLY
Description: Clear Real Time Clock Interrupt
DO—D7 = DON'T CARE
Name: RS2320UT *
Port Address: E8— EB
Access: WRITE ONLY
Description: UART Control, Data Control, Modem Control,
BRG Control
Port E8 = UART Master Reset
Port E9 = BAUD Rate Gen. Register
Port EA = UART Control Register (Modem Control Reg.)
Port EB = UART Transmit Holding Reg.
(Refer to Model Ш! ог 4 Manual for Bit Assignments)
Name: RS232IN *
Port Address: £8 — EB
Access: READ ONLY
Description: Input UART and Modem Status
Port £8 = MODEM STATUS
Port E9 = (RESERVED)
Port EA = UART Status Register
Port EB = UART Receive Holding Register (Resets DR)
(Refer to Model Ш! ог 4 Manual for Bit Assignments)
Name: WRNMIMASKREG *
Port Address: Е4— Е7
Access: WRITE ONLY
Description: Qutput NMI Latch
DO—D5 = (RESERVED)
DE = ENMOTOROFFINT
0 = Disables Motorotf NMI
1 = Enables Motoroff NIH
D7 = ENINTRQ
0 = Disables INTRQ NMI
1 = Enables INTRQ NMI
Name: RDNMISTATUS *
Port Address: E4 — E7
Access: READ ONLY
Description: Input NMI Status
DO =0
D2—D4 = (RESERVED)
D5 = RESET (not needed)
O = Reset Asserted (Problem)
1 = Reset Negated
D6 = MOTOROFF
0 = Motoroff Asserted
1 = Motoroff Negated
D7 = INTRQ
0 = INTRQ Asserted
1 = INTRQ Negated
Name: WRINTMASKREG *
Port Address: EO — E3
Access: WRITE ONLY
Description: Output INT Latch
DO—D1 = (RESERVED)
D2 = ENRTC
0 = Real time ciock interrupt disabled
1 = Real time clock interrupt enabled
D3 = ENIOBUSINT
0 = External IO Bus interrupt disabled
1 = External IO Bus interrupt enabled
|
D4 = ENXMITINT
0 = RS232 Xmit Holding Reg. empty int.
disabled
1 = RS232 Xmit Holding Reg. empty int.
enabled
D5 = ENRECINT
0 = R5232 Rec. Data Reg. full int. disabled
1 = RS232 Rec. Data Reg. full int. enabled
D6 = ENERRORINT
0 = RS232 UART Error interrupts disabled
1 = RS5232 UART Error interrupts enabled
D7 = (RESERVED)
Name: RDINTSTATUS *
Port Address: E0 — E3
Access: READ ONLY
Description: Input INT Status
DO—D1 = (RESERVED)
D2 = RTC INT
D3 = IOBUS INT
D4 — RS232 XMIT INT
D5 = RS232 REC INT
D6 = RS232 UART ERROR INT
D7 = (RESERVED)
Name: BOOT *
Port Address: 9C — 9F
Access: WRITE ONLY
Description: Enable or Disable Boot ROM
DO = ROM *
0 = Boot ROM Disabled
1 Boot ROM Enabled
D1—D7 = (RESERVED)
Name: SEN *
Port Address: 90 — 93
Access: WRITE ONLY
Description: Sound output
DO = SOUND DATA
D1—D7 = (RESERVED)
Name:
OPREG *
Port Address: 84
Access:
WRITE ONLY
Description: Output to operation reg.
DO
D1
D2
D3
D4
D5
D6
D7
SEL1
0
0
1
1
= SELO
= SEL1
SELO MODE
0 0
1 1
0 2
1 3
= 8064
O = 64 character mode
1 = 80 character mode
= INVERSE
0 = Inverse video disabled
1 = inverse video enabled
= SRCPAGE — Points to the page to be mapped
as new page
0 = U64K, L32K Page
1 = U64K, U32K Page
= ENPAGE — Enables mapping of new page
0 = Page mapping disabled
1 = Page mapping enabled
= DESPAGE — Points to the page where new
page is to be mapped
0 = L64K, U32K Page
1 = L64K, L32K Page
= PAGE
0 = Page 0 of Video Memory
1 = Page 1 of Video Memory
50
5.1.8 Video Circuit
The heart of the video display circuit in the Model 4P is the
~ 68045 Cathode Ray Tube Controller (CRTC), U85. The CRTC
is a preprogrammed video controller that provides two screen
formats: 64 by 16 and 80 by 24. The format is controlled by pin
3 of the CRTC (8064*). The CRTC generates all of the neces-
sary signals required for the video display. These signals are
VSYNC (Vertical Sync), HSYNC (Horizontal Sync) for proper
sync of the monitor, DISPEN (Display Enable) which indicates
when video data should be output to the monitor, the refresh
memory addresses (MAO-MA13) which addresses the video
RAM, and the row addresses (RAO-RA4) which indicates which
scan line row is being displayed. The CRTC also provides hard-
ware scroiling by writing to the internal Memory Start Address
Register by OUTing to Port 88H. The internal cursor control of
the 68045 is not used in the Model 4P video circuit.
Since the 80 by 24 screen requires 1,920 screen memory lo-
cations, a 2K by 8 static RAM (U82) is used for the video RAM.
Addressing to the video RAM (U82) is provided by the 68045
when refreshing the screen and by the CPU when updating of
the data is performed. These two sets of address lines are mul-
tiplexed by three 74LS157s (U83, U84, and U104). The multi-
plexers are switched by CRTCLK which allows the CRTC to
address the video RAM during the high state of CRTCLK and
the CPU access during the low state. A10 from the CPU is con-
trolled by PAGE™ which allows two display pages in the 64 by
16 format. When updates to the video RAM are performed by
. the CPU, the CPU is held in a WAIT state until the CRTC is not
addressing the video RAM. This operation allows reads and
writes to video RAM without causing hashing on the screen.
The circuit that performs this function is a 74LS5244 buffer
(U103), an 8 bittransparent latch, 74LS373 (U102) and a Delay
line circuit shared with Dynamic RAM timing circuit consisting
of a 74LS74 (U95), 741.832 (U94), 74L.504 (U74), 74LS00
(U96), 74LS02 (U75), and Delay Line (U97). During a CPU
Read Access to the Video RAM, the address is decoded by the
PAL U109 and asserts VIDEO" low. This is inverted by U74 (1/
6 of 74LS04) which pulls one input of U96 (1/4 of 74LS00) and
in turn asserts VWAIT * low to the CPU. RD is high at this time
and is latched into U95 (1/2 of 74LS74) on the rising edge of
XADR7*. XADR7* is inverse of CRTCLK which drives the
CRTC (68045), and the address multiplexers U83, U84, and
U104.
When RD is latched by U95, the Q output goes low releasing
WAIT" from the CPU. The same signal also is sent to the Delay
Line (U97) through U116 (1/4 of 74F08). The Delay line delays
the falling edge 240 ns for VLATCH" which latches the read
data from the video RAM at U102. The data is latched so the
CRTC can refresh the next address location and prevent any
hashing. MRD* decoded by U108 and a memory read is ORed
with VIDEO” which enables the data from U102 to the data bus.
The CPU then reads the data and completes the cycle. A CPU
write is slightly more complex in operation. As in the RD cycle,
VIDEO" is asserted low which asserts VWAIT"® low to the CPU.
WR is high at this time which is NANDed with VIDEO and
synced with CRTCLK to create VRAMDIS that disables the
video RAM output. On the rising edge of XADR7”, WR is
latched into U95 (1/2 of 74L574) which releases VWAIT” and
starts cycle through the Delay Line. After 30ns DLYVWR" (De-
layed video write) is asserted low which also asserts VBUFEN"
(Video Buffer Enable) low. VBUFEN" enabled data from the
Data bus to the video RAM. Approximately 120ns later
DLYVWR" is negated high which writes the data to the video
RAM and negates VBUFEN" turning off buffer. The CPU then
completes WR cycle to the video RAM. Refer to Video HAM
CPU Access Timing Figure 5-12 for timing of above RD or WR
cycles.
During screen refresh, CRTCLK is high allowing the CRTC to
address Video RAM. The data out of the video RAM is latched
by LOAD* into a 74LS273 (U101). D7 is generated by IN-
VERSE* through U125 (1/6 of 74504), and U123 (1/4 of
74L508). This decoding determines if character should be al-
pha-numeric only (if inverse high) or unchanged (INVERSE”
low). The outputs of U101 are used as address inputs the char-
acter generator ROM (J42). AS is decoded with ENALTSET
(Enable Alternate Set) and Q7 of U101, which resets A9 to a
low if Q7 and ENALTSET are high. See ENALTSET Control Ta-
ble below.
ENALTSET
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FIGURE 5-12. Video RAM CPU Access Timing
52
RAO-RA3, row addresses from the CRTC are used to control
which scan line is being displayed. The Model 4P has a 4-bit full
adder 74L.5283 (U61) to modify the Row address. During a
character display DLYGRAPHIC* is high which applies a high to
all 4 bits to be added to row address. This will result in subtract-
ing one from Row address count and allow all characters to be
displayed one scan line lower. The purpose is so inverse char-
acters will appear within the inverse block. When a graphic
block is displayed DLY GRAPHIC" is low which causes the row
address to be unmodified. Moving jumper from E14-E15 to
E15-E16 will disable this circuit.
DLYCHAR* and DLYGRAPHICS are inverse signals and con-
trol which data is to be loaded into the shift register UGS.
When DLYCHAR® is low and DLYGRAPHIC* is high, the
Character Generator ROM (U42) is enabled to output data:
when DLYCHAR" is high and DLYGRAPHIC* is low the
graphics characters from U41 (74LS15) is buffered by U43
(741.5244) to the shift register. The data is loaded into the
shift register on the rising edge of SHIFT* when LOADS” is
low. Blanking is accomplished by masking off LOADS* so no
data will be loaded and zero data will be shifted out with the
serial input of U63, pin 1, grounded. Serial video data is out-
put U63 pin 13 and is mixed with inverse and/or hires graph-
ics information by (1/4 or 74L586) U143. The video data is
then mixed with a DO7 Rate clock, either DOT* and DCLK,
to create distinct dots on the monitor. DOT* and DCLK are
inverse signals and are provided to allow a choice to obtain
the best video results. The video information is filtered by
F34, R45 (47 ohm resistor), and C241 (100 pf Cap) and out-
put to video monitor. VSYNC and HSYNC are buffered by
(1/2 of 74L586) U143 and are also output to video monitor.
Refer to Video Circuit Timing Figure 5-13, Video Blanking
Timing Figure 5-14., and Inverse Video Timing Figure 5-1 for
timing relationships of Video Circuit.
5.1.9 Keyboard
The keyboard interface of the Model 4P consists of open col-
lector drivers which drive an 8 by 8 key matrix keyboard and an
inverting buffer which buffers the key or keys pressed on the
data bus. The open collector drivers (U56 and U57 (7416) are
driven by address lines AO-A7 which drive the column lines of
the keyboard matrix. The ROW lines of the keyboard are pulled
up by a 1.5 kohm resistor pack RP2. The ROW lines are buff-
ered and inverted onto the data bus by U58 (740.5240) which is
enabled when KEYBD" is a logic low. KEYBD* is a memory
mapped decode of addresses 3800-3BFF in Model III Mode
and F400-F7FF in Model 4/4P mode. Refer to the Memory Map
under Address Decode for more information. During real time
operation, the CPU will scan the keyboard periodicaily to check
if any keys are pressed. If no key is pressed, the resistor pack
RP2 keeps the inputs of US8 at a logic high. U58 inverts the
data to a logic low and buffers it to the data bus which is read
by the CPU. If a key is pressed when the CPU scans the correct
column line, the key pressed will pull the corresponding row to
a logic low. U58 inverts the signal to a logic high which is read
by the CPU.
53
5.1.10 Real Time Clock
The Real Time Clock circuit in the Model 4P provides a 30 Hz
(in the 2 MHz CPU mode) or 60 Hz (in the 4 MHz CPU mode)
interrupt to the CPU. By counting the number of interrupts that
have occurred, the CPU can keep track of the time. The 60 Hz
vertical sync signal (VSYNC) from the video circuitry is used for
the Real Time Clock's reference. In the 2 MHz mode, FAST is
a logic low which sets the Preset input, pin 4 of U22 (74LS74),
to a logic high. This allows the 60 Hz (VSYNC) to be divided by
2 to 30 Hz. The output of 1/2 of U22 is ORed with the original
60 Hz and then clocks another 74LS74 (1/2 of U22). If the real
time clock is enabled (ENRTC at a logic high), the interrupt is
latched and pulls the INT* line low to the CPU. When the CPU
recognizes the interrupt, the pulse is counted and the latch re-
set by pulling RTCIN* low. In the 4 MHz mode, FAST is a logic
high which keeps the first half of U22 in a preset state {the Q"
output at a logic low). The 60 Hz is used to clock the interrupts.
NOTE: If interrupts are disabled, the accuracy of the real
time clock wili suffer.
5.1.11 Line Printer Port
The Line Printer Port Interface consists of a pulse generator, an
eight-bit latch, and a status line buffer. The status of the line
printer is read by the CPU by enabling buffer U3 (74L5244).
This buffer is enabled by LPRD* which is a memory map and
port map decode. In Model Ill mode, only the status can be read
from memory location 37E8 or 37E9. The status can be read in
all modes by an input from ports F8-FB. For a listing of the bit
status, refer to Port Map section.
After the printer driver software determines that the printer is
ready for printing (by reading the correct status), the characters
to be printed are output to Port F8-FB. U2, a 74LS374 eight-bit
latch, latches the character byte and outputs to the line printer.
One-half of U1 (74LS123), a one-shot, is then triggered which
generates an appropriate strobe signal to the printer which sig-
nifies a valid character is ready. The output of the one-shot is
buffered by 1/6th of the U21 (74LS04) to prevent noise from the
printer cable from flase-triggering the one-shot.
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Figure 5-15. Inverse Video T
56
5.1.12 Graphics Port
The Graphics Port (J7) on the Model 4P is provided to attach
the optional Graphics Board. The port provides DO-D7 (Data
Lines), AO-A3 (Address Lines), IN*, GEN* and RESET* for the
necessary interface signals for the Graphics Board. GEN* is
generated by negative ORing Port selects GSELO” (8C-8FH)
and GSELI* (80-83H) together by (1/4 of 74L508) U23. The re-
sulting signal is negative ANDed with IORG” by (1/4 of 74532)
U62. Seven timing signals are provided to allow synchroniza-
tion of Main Logic Board Video and Graphics Board Video.
These timing signals are VSYNC, HSYNC, DISPEN, DCLK, H,
|, and J. Three control signals from the Graphics Board are
used to sync to CPU access and select different video modes.
WAIT* controls the CPU access by causing the CPU to WAIT till
video is in retrace area before allowing any writes or reads to
Graphics Board RAM. ENGRAF is asserted when Graphics
video is displayed. ENGRAF also disables inverse video mode
on Main Logic Board Video. CL166* (Clear 74L 166) is used to
enable or disable mixing of Main Logic Board Video and Graph-
ics Board Video. If CL166" is negated high, then mixing is al-
lowed in all for video modes 80 x 24, 40 x 24, 64 x 16, and 32 x
16. If CL166” is asserted low, this will clear the video shift reg-
ister UB3, which aliows no video from the Main Logic Board. In
this state 8064" is automatically asserted low to put screen in
80 x 24 video mode. Refer to Figure 5-16. Graphic Board Video
Timing for timing relationships. Refer to the Model 4/4P Graph-
ics Board Service information for service or technical informa-
tion on the Graphics Board.
5.1.13 Sound
The sound circuit in the Model 4P is compatible with the Sound
Board which was optional in the Model 4. Sound is generated
by alternately setting and clearing data bit DO during an OUT to
port 90H. The state of DO is latched by U130 (1/2 of a 74LS74)
and the output is amplified by Q2 which drives a piezoelectric
sound transducer. The speed of the software loop determines
the frequency, and thus, the pitch of the resulting tone. Since
the Model 4P does not have a cassette circuit, some existing
software that used the cassette output for sound would have
been lost. The Model 4P routes the cassette latch to the sound
board through U142. When the CASSMOTORON signal is a
logic tow, the cassette motor is off, then the cassette output is
sent to the sound circuit.
5.1.14 МО Bus Port
The Model 4P Bus is designed to allow easy and convenient in-
terfacing of I/O devices to the Model 4P. The I/O Bus supports
all the signals necessary to implement a device compatible with
the Z80s 1/0 structure.
57
Addresses;
AO to A7 allow selection of up to 256" input and 256 output
devices if external I/O is enabled.
“Ports 80H to OFFH are reserved for System use.
Data:
DBO to DB7 allow transfer of 8-bit data onto the processor
data bus is external 1/O is enabled.
Control Lines:
1. Mi" — Z80A signal specifying an Mt or Operation Code
Fetch Cycle or with IOREQ”, it specifies an Interrupt
acknowledge.
2. IN*— Z80A signal specifying than an input is in progress.
Logic AND of IOREQ" and WR".
3. OUT" — Z80A signal specifying that an output is in prog-
ress. Logic AND of IOREQ” and WR".
4. IOREQ* — Z80A signal specifying that an input or output
is in progress or with M1*, it specifies an interrupt
acknowledge.
5. RESET” — system reset signal.
6. IOBUSINT* — input to the CPU signaling an interrupt from
an 1/0 Bus device if I;O Bus interrupts are enabied.
7. 10BUSWAIT* — input to the CPU wait line allowing I/O Bus
device to force wait states on the Z80 if external 1/O is
enabled.
8. EXTIOSEL" — input to I/O Bus Port circuit which switches
the I/O Bus data bus transceiver and allows and INPUT in-
struction to read 1/0 Bus data.
The address line, data line, and all control lines except RESET"
are enabled only when the ENEXIO bit in port EC is set to one.
To enable I/O interrupts, the ENIOBUSINT bit in the PORT EG
(output port) must be a one. However, even if it is disabled from
generating interrupts, the status of the IOBUSINT™ line can still
read on the appropriate bit of CPU IOPORT EO (input port).
See Model 4P Port Bit assignments for port OFF, OEC, and OEO.
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Figure 5-16. Graphic Board Video Timing
58
The Model 4P CPU board is fully protected from “foreign 1/0 de-
vices” in that all the IO Bus signals are buffered and can be dis-
abled under software control. To attach and use and VO device
on the I/O Bus, certain requirements (both hardware and soft-
ware) must be met.
For input port device use, you must enable external 1/O devices
by writing to port OECH with bit 4 on in the user software. This
will enable the data bus address lings and control signals to the
1/O Bus edge connector. When the input device is selected, the
hardware should acknowledge by asserting EXTIOSEL" low.
This switches the data bus transceiver and allows the CPU to
read the contents of the 1/0 Bus data lines. See Figure 5-17 for
the timing. EXTIOSEL" can be generated by NANDing IN and
the 1/O port address.
Output port device use is the same as the input port device in
use, in that the external I/O devices must be enabled by writing
to port OECH with bit 4 on in the user software — in the same
fashion.
For either input or output devices, the ¡OBUSWAIT* control line
can be used in the normal way for synchronizing slow devices
to the CPU. Note that since dynamic memories are used in the
Model 4P, the wait line should be used with caution. Holding the
CPU in a wait state for 2 msec or more may cause loss of mem-
ory contents since refresh is inhibited during this time. It is rec-
ommended that the IOBUSWAIT* line be held active no more
than 500 psec with a 25% duty cycle.
The Model 4P will support Z80 Mode 1 interrupts. A RAM jump
table is supported by the LEVEL Il BASIC ROMs image and the
user must supply the address of his interrupt service routine by
writing this address to locations 403E and 403F. When an in-
terrupt occurs, the program will be vectored to the user-sup-
plied address if 1/0 Bus interrupts have been enabled. To
enable I/O Bus interrupts, the user must set bit 3 of Port OEOH.
5.1.15 FDC Circuit
The TRS-80 Model 4P Floppy Disk Interface provices a stan-
dard 5-1/4" floppy disk controller. The Floppy Disk Interface
supports both single and double density encoding schemes.
Write precompensation can be software enabled or disabled
beginning at any track, although the system software enables
write precompensation for all tracks greater than twenty-one.
The amount of write precompensation is 250 nsec and is not
adjustable. The data clock recovery logic incorporates a digital
data separator which achieves state-of-the-art reliability. One
or two drives may be controlled by the interface. All data trans-
fers are accomplished by CPU data requests. In double density
operation, data transfers are synchronized to the CPU by forc-
ing a wait to the CPU and clearing the wait by a data request
from the FDC chip. The end of the data transfer is indicated by
generation of a non-maskable interrupt from the interrupt re-
quest output of the FDC chip. A hardware watchdog timer in-
sures that any error condition will not hang the wait line to the
CPU for a period long enough to destroy RAM contents.
59
Input or Output Cycles.
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Figure 5-17. 1/0 Bus Timing Diagram
60
Control and Data Buffering
The Floppy Disk Controller Board is an VO port-mapped device
which utilizes ports E4H, FOH, F1H, F2H, F3H, and F4H. The
decoding logic is implemented on the CPU board. (Referto Par-
agraph 5.1.5 Address Decoding for more information on Port
Map). U31 is a bi-directional, 8-bit transceiver used to buffer
data to and from the FDC and RS-232 circuits. The direction of
data transfer is controlled by the combination of control signals
DISKIN* and RS232IN*. If either signal is active (logic low), U31
is enabled to drive data onto the CPU data bus. If both signals
are inactive (logic high), U31 is enabled to receive data fromthe
CPU board data bus. A second buffer (U12) is used to buffer the
FDC chip data to the FDC/RS232 Data Bus, (BDO0-BD7), U12 is
enabled ail the time and it's direction controlled by DISKIN”.
Again, if DISKIN* is active (logic low), data is enabled to drive
from the FDC chip to the Main Data Busses. If DISKIN™ is in-
active (logic high), data is enabled to be transferred to the FDC
chip.
Nonmaskable Interrupt Logic
Dual D flip-flop U100 (74LS74) is used to latch data bits D6 and
D7 оп the rising edge of the control signal WRNMIMASKREG".
The outputs of U100 enable the conditions which will generate
a non-maskable interrupt to the CPU, The NMI interrupt con-
ditions which are programmed by doing an OUT instruction to
port E4H with the appropriate bits set. if data bit 7 is set, an FDC
interrupt is enabled to generate an NMI interrupt. If data bit 7 is
reset, interrupt requests request from the FDC are disabled. If
data bit 6 is set, a Motor Time Out is enabled to generate an
NMl interrupt. If data bit 6 is reset, interrupts on Motor Time Out
are disabled. An IN instruction from port E4H enables the CPU
to determine the source of the non-maskable interrupt. Data bit
7 indicates the status of FDC interrupt request (INTRQ)
(0 =true, 1 =false). Data bit 6 indicates the status of Motor
Time Out (0 = true, 1 = false). Data bit 5 indicates the status of
the Reset signal (0 = true, 1 =false). The control signal
RDNMISTATUS" gates this status onto the CPU data bus when
active (fogic low).
Drive Select Latch and Motor ON Logic
Selecting a drive prior to disk 1/O operation is accomplished by
doing an QUT instruction to port F4H with the proper bit set. The
following table describes the bit allocation of the Drive Select
Latch:
Data Bit Function
DO Selects Drive 0 when set"
D1 Selects Drive 1 when set"
D2 Selects Drive 2 when set”
D3 Selects Drive 3 when set”
D4 Selects Side 0 when reset
Selects Side 1 when set
D5 Write precompensation enabled when set,
disabled when reset
D6 Generates WAIT if set
D7 Selects MFM mode if set
Selects FM mode if reset
61
*Only one of these bits should be set per output
Hex D flip-flop U32 (741.174) latches the drive select bits, side
select and FM*/MFM bits on the rising edge of the contro! signal
DRVSEL”, A dual D flip-flop (U98) is used to latch the Wait En-
able and Write precompensation enable bits on the rising edge
of DAVSEL*. The rising edge of DRVSEL* also triggers a one-
shot (1/2 of U54, 74LS123) which produces a Motor On to the
disk drives. The duration of the Motor On signal is approxi-
mately three seconds. The spindle motors are not designed for
continuous operation. Therefore, the inactive state of the Motor
On signal is used to clear the Drive Select Latch, which de-se-
lects any drives which were previously selected. The Motor On
one-shot is retriggerable by simply executing another OUT in-
struction to the Drive Select Latch.
Wait State Generation and WAITIMOUT Logic
As previously mentioned, a wait state to the CPU can be initi-
ated by an OUT to the Drive Select Latch with D6 set. Pin 5 of
U98 will go high after this operation. This signal is inverted by
1/4th of U79 and is routed to the CPU where it forces the Z80A
into a wait state. The Z80A will remain in the wait state as long
as WAIT" is low. Once initiated, the WAIT* will remain low until
one of five conditions is satisfied. One half of U77 (a five input
NOR gate) is used to perform this function. INTQ, DRQ, RE-
SET, CLRWAIT, and WAITIMOUT are the inputs to the NOR
gate. If any one of these inputs is active (logic high), the output
of the NOR gate (U77 pin 5) will go low. This output is tied to the
clear input of the wait latch. When this signal goes low, it will
clear the Q output (U98 pin 5) and set the Q* output (U98 pin
6). This condition causes WAIT* to go high which allows the
Z80 to exit the wait state. U99 is a 12-bit binary counter which
serves as a watchdog timer to insure that a wait condition will
not persist long enough to destroy dynamic RAM contents. The
counter is clocked by a 1 MHz clock and is enabled to count
when its reset pin is low (U99 pin 11). A logic high on U99 pin
11 resets the counter outputs. U99 pin 15 is a divide-by-1024
output and is used to generate the signal WAITIMOUT. This
watchdog timer logic will limit the duration of a wait to
1024psec, even if the FDC chip should fail to generate a DRQ
or an INTRQ.
If an OUT to Drive Select Latch is initiated with D6 reset (logic
low), a WAIT is still generated. The 12-bit binary counter will
count to 2 which will output CLRWAIT and clear the WAIT state.
This allows the WAIT to oceur only during the OUT instruction
to prevent violating any Dynamic RAM parameters.
NOTE: This automatic WAIT will cause a 1-2 psec wait each
time an out to Drive Select Latch is performed.
Clock Generation Logic
A 4 MHz crystal oscillator and a 4-bit binary counter are used to
generate the clock signals required by the FDC board. The 4
MHz oscillator is implemented with two inverters (1/3 of U39)
and a quartz crystal (Y2). The output of the oscillator is inverted
and buffered by 1/6 of U39 to generate a TTL level square wave
signal. U37 is a 4-bit binary counter which is divided into a di-
vide-by-2 and a divide-by-8 section. The divide-by-2 section is
used to generate the 2 MHz output at pin 12. The 2 MHz'is
NANDed with 4MHz by 1/4 of U19 and the output is used to
clock the divide-by-8 section of U37. A 1 MHz clock is gener-
ated at pin 9 of U37 which is 90° phase-shifted from the 2 MHz
clock. This phase relationship is used to gate the guaranteed
Write Data Pulse (WD) to the Write precompensation circuit.
The 4 MHz is used to clock the digital data separator U18 and
the Write precompensation shift register U55. The 1 MHz clock
is used to drive the clock input of the FDC chip (U13) and the
clock input of the watchdog timer (U99).
Disk Bus Output Drivers
High current open collector drivers U20 and U56 are used to
buffer the output signals from the FDC circuit to the disk drives.
Write Precompensation and Write Data Pulse Shap-
ing Logic
The Write Precompensation logic is comprised of U55
(741.8195), 1/4 of U19 (74LS00), 1/4 of U74 (741504), and
1/2 of U77 (74LS260). U55 is a parallel in, serial out shift reg-
ister and is clocked by 4 MHz which generates a precompen-
sation value of 250 nsec. The output signals EARLY and LATE
of the FDC chip (U13) are input to PO and P2 of the shift reg-
ister. A third signal is generated by 1/4 of U75 when neither
EARLY nor LATE is active low and is input to P1 of U55. WD of
the FDC chip is NANDed with 2 MHz to gate the guaranteed
Write Data Pulse to U55 for the parallel load signal SHFT/LD.
When U55 pin 9 is active low, the signals preset at P1-P3 are
clocked in on the rising edge of the 4 MHz clock. After U55 pin
9 goes high, the data is shifted out at a 250 nsec rate. EARLY
will generate a 250 nsec delay, NOT EARLY AND NOT LATE
will generate a 500 nsec delay, and LATE will generate a 750
nsec delay. This provides the necessary precompensation for
the write data. As mentioned previously, Write Precompensa-
tion is enabled through software by an OUT to the Drive Select
Latch with bit 5 set. This sets the Q output of the 74LS74 (U98
pin 9) which is ANDed with DDEN which disables the shift reg-
ister U55. DDEN disables Write Precompensation in the single
density mode. The resulting signal also enables U75 to allow
the write data (WD) to bypass the Write Precompensation cir-
cuit. The Write Data (WD) pulse is shaped by a one-shot (1/2 of
U54) which stretches the data pulses to approximately 500
nsec.
62
4 MHZ
2 MHZ
LLL LOL USES
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WD
U21.1 (CP.)
Figure 5-18. Write Precompensation Timing
63
U10.9 (SHFT/LD)
Clock and Read Data Recovery Logic
The Clock and Read Data Recovery Logic is comprised of one
chip U18 (FDC9216). The FDC9216 is a Floppy Disk Data Sep-
arator (FDDS) which converts a single stream of pulses from
the disk drive into separate clock and data pulses for input to
the FDC chip. The FDDS consists of a clock divider, a long-term
timing corrector, a short-time timing corrector and reclocking
circuitry. The reference clock (REFCLK) is a 4 MHz and is di-
vided by the internal clock divider. CDO and CD1 of the FDDS
chip control the divisor which divides REFCLK. With DCA
grounded (logic tow), CDQ (when a logic low) generates a di-
vide-by-1 for MFM mode and when logic high generates a di-
vide-by-2 for FM mode. CDO is controlled by the signal DDEN”
which is Double Density enable or MFM enable. The FDDS de-
tects the leading edges of RD" pulses and adjusts the phase of
the internal clock to generate the separated clock (SEPCLK) to
the FDC chip. The separate long and short term timing correc-
tors assure the clock separation to be accurate. The separated
Data (SEPD*) is used as the RDD* input to the FDC chip.
Floppy Disk Controller Chip
The 1793 is an MOS LSI device which performs the functions
of a floppy disk formatter/controller in a single chip implemen-
tation. The following port addresses are assigned to the internal
registers of the 1793 FDC chip:
Port No. Function
FOH Command/Status Register
F1H Track Register
F2H Sector Register
F3H Data Register
5.1.16 RS-232-C Circuit
RS-232C Technical Description
The RS-232C circuit tor the Model 4P computer supports asyn-
chronous serial transmissions and conforms to the EIA RS-
232C standards at the input-output interface connector (J4).
The heart of the circuit is the TR1865 Asynchronous Receiver!
Transmitter U30. It performs the job of converting the parallel
byte data from the CPU to a serial data stream including start,
stop, and parity bits. For a more detailed description of how this
LSI circuit performs these functions, refer to the TR1865 data
sheets and application notes. The transmit and receive clock
rates that the TR1865 needs are supplied by the Baud Rate
Generator U52 (BR1941L) or (BR1943). This circuit takes the
5.0688 MHz supplied by the system timing circuit ang the pro-
grammed information received from the CPU over the data bus
and divides the basic clock rate to provide two clocks. The rates
available from the BRG go from 50 Baud to 19200 Baud. See
the BRG table for the complete list.
64
BRG Programming Table
Transmit/
Receive Supported
Nibble Baud 16X by
Loaded Rate Clock SETCOM
OH 50 0.8 kHz Yes
1H 75 1.2 kHz Yes
2H 110 1.76 kHz Yes
3H 134.5 2.1523 kHz Yes
4H 150 2.4 kHz Yes
5H 300 4.8 kHz Yes
6H 600 9.6 kHz Yes
7H 1200 19.2 kHz Yes
8H 1800 28.8 kHz Yes
9H 2000 32.081 kHz Yes
AH 2400 38.4 kHz Yes
BH 3600 57.6 kHz Yes
CH 4800 76.8 kHz Yes
DH 7200 115.2 kHz Yes
EH 9600 153.6 kHz Yes
FH 19200 307.2 kHz Yes
The RS-232C circuit is port mapped and the ports used are E8
to EB. Following is a description of each port on both input and
output.
Port input Output
ES Modem status Master Reset, enables UART
control register load
EA UART status UART control register oad and
modem control
ES Not Used Baud rate register load enable
bit
EB Receiver Holding Transmitter Holding register
register
Interrupts are supported in the RS-232C circuit by the Interrupt
mask register (U92) and the Status register (U44) which allow
the CPU to see which kind of interrupt has occurred. Interrupts
can be generated on receiver data register full, transmitter reg-
ister empty, and any one of the errors — parity, framing, or data
overrun. This allows a minimum of CPU overhead in transfer-
ring data to or from the UART. The interrupt mask register is
port EQ (write) and the interrupt status register is port EO (read).
Refer to the IO Port description for a full breakdown of all inter-
rupts and their bit positions.
All Model |, Ill, and 4 software written for the RS-232-C interface
is compatible with the Model 4P RS-232-C circuit, provided the
software does not use the sense switches to configure the in-
terface. The programmer can get around this problem by di-
rectly programming the BRG and UART for the desired
configuration or by using the SETCOM command of the disk
operating system to configure the interface . The TRS-80 RS-
232C Interface hardware manual has a good discussion of the
RS-232C standard and specific programming examples (Cat-
alog Number 26-1145).
Pinout Listing
The following list is a pinout description of the DB-25 connector
(P1).
Pin No. Signal
1 PGND (Protective Ground)
TD (Transmit Data)
RD (Receive Data)
RTS (Request to Send)
CTS (Clear To Send)
DSR (Data Set Ready)
SGND (Signal Ground)
CD (Carrier Detect)
SRTS (Spare Request to Send)
DTR (Data Terminal Ready)
RI (Ring Indicate)
woo I OO aw
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65
5.1.17 CPU Board Troubleshooting Guide
This section is a general guide for service personnel to check
out and troubleshoot the Model 4P Main Logic CPU Board. Pro-
cedures in section 4 Troubleshooting should be followed before
proceeding to following steps. This guide will provide step by
step procedures to help isolate the faulty area on the CPU
board. Knowledge of each area of the CPU board is necessary
to determine exact component failure. Refer of CPU Board
Schematics and Theory of Operation during troubleshooting for
specific check points and testing.
1.
10.
11.
12.
No video messages are displayed and correct data does
not appear at video output connector J9.
If above condition exists, go to 2; if video okay, but Model
4P does not boot properly, go to 10.
If video and boot-up is okay, go to 15.
Check for video timing signals 12M and 10M and input of
U127.
If okay, go to 3; it one or both bad, go to 7.
Check for proper timing signals output from U127 (SHIFT™,
XADR7*, CRTCLK, POT*, LOAD", LOADS*, DCLK).
If okay, then go to 4; if one or more bad, replace U127 or
U128.
Check if 68046 U85 is working properly and has correct in-
put signals.
If all okay, then go to 5. If bad, replace U85 or check for in-
put signals where they originate.
Check for timing and proper signals at U82 and U42.
If bad, replace as necessary; if okay, go to 6.
Check shift register and repair.
Check for 20M output of Y 1 pin 8.
If okay, go to 8; if bad, replace Y1.
Check for outputs of U126 (PCLK, R5232CLK, and 10M).
If okay, then go to 9; if any bad, replace U126.
. Check for 12M at output of U148 pin 9.
If okay, then video should work; if bad, check Ut47, U148,
and U149 and replace if necessary.
Run Memory Test in Boot ROM by hoiding down period (.)
and toggling Reset.
If memory checks okay, then go to 11; it not, check mem-
ory circuit and/or replace RAM chips.
Check Clock circuit of Floppy Disk Controller.
It AMHz, 2MH, and 1MHz okay, go to 12; if bad, repair or
replace necessary components.
Check for all incoming signals to the FDC chip U13.
If any bad, repair as necessary; if okay, go to 13.
66
13.
14.
15.
Check all handshaking signals to FDC chip from CPU.
If okay, go to 14; if bad, repair as necessary.
Check Data Bus and control lines.
If okay, then problem still exists in Floppy Disk Circuit or
Floppy Disk Drive. Refer to each section accordingly. If
bad, replace as necessary.
If unit boots okay, then boot Model 4P Diagnostics Diskette
and execute each diagnostic to isolate any minor problems
on CPU Board.
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Parts List
Item Sym Description Part Number
1 1 PCB, Main Logic 8709427
2 21 Staking Pin 8529414
3 1 Socket, 8-Pin DIP (079) 8509811
4 16 Socket, l6-Pin DIP (U115-139) 8509093
5 1 Socket, 18-Pin DIP (U76) 8509006
6 18 Socket, 289-Pin DIP (U39-41, 85990099
47,58 ,51,62,63,84,1186)
7 3 Socket, 24-Pin DIP (Ul6,24,44) 8509901
8 4 Socket, 409-Pin DIP (026,43, 8599092
U72,81)
9 1 Connector, 4-Pin (J8) 8519210
18 1 Connector, 3-Pin (J1)
11 1 Connector, 6-Pin (J9) 8519211
12 1 Connector, Dual 8 (J6) 8519184
13 1 Connector, 34-Pin (J5)
14 1 Connector, 34-Pin (J7)
15 1 Connector, 25-Pin (J4) 85191099
Bl Transducer, Sound 84208903
Cl Capacitor, .1 m£fd, 59%V Mono Axial 8374144
thru
Cll
Cl3 Capacitor, .1 mfd, 59V Mono Axial 8374144
cl15 Capacitor, .l1 mfd, 58V Mono Axial 8374104
thru
C24
C22 Capacitor, .l1 mfd, 58V Mono Axial 8374104
thru
C48
C58 Capacitor, .l1 mfd, 59V Mono Axial 8374144
thru
C64
C66 Capacitor, .1 mfd, 59V Mono Axial 8374104
thru
c88
cog Capacitor, .l1 mfd, 50V Mono Axial 8374104
thru
C130
Parts List
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Item Sym Description
C131 Capacitor, 22 mfd, 16V Elec Radial 8326221
thru
C138
Cl39 Capacitor, 18088 pfd, 59V Cer Disk 8382184
C148 Capacitor, .822 mfd, 59V Cer Disk 8383224
С141 Capacitor, .022 mfd, 59V Cer Disk 83983224
Cl42 Capacitor, 33 pfd, 50V Cer Disk 8300334
Cl43 Capacitor, 1588 pfd, 58V Cer Disk |
Cl44 Capacitor, 15йй рЁа, 5й\у Cer Disk
Cl45 Capacitor, .1 mfd, 58V Mono Axial 8374184
Cl46 Capacitor, .1 mfd, 59V Mono Axial 8374194
Cl48 Capacitor, 9-35 mfd, Trimmer
C149 Capacitor, .1 míd, 59V Mono Axial 8374194
C158 Capacitor, 188 pfd, 58vV C.Disk 250 8391184
thru
C152
C153 Capacitor, 1998 pfd, 59V Cer Disk 83811084
C154 Capacitor, 478 pfd, 58V Cer Disk 8301474
C155 Capacitor, 188 pfd, 59V Cer Disk 250 8391184
C156 Capacitor, 198 pfd, 589V Cer Disk 8301184
C157 Capacitor, 33 mfd, l6V Elec Radial 8326331
C158 Capacitor, 298 pfd, 59V Cer Disk Z5U 8391223
C159 cCapacitor, .1 m£d, 5%V Mono Axial 8374104
C161 Capacitor, 18 mfd, l6V Elec Radial 8326191
Cl62 Capacitor, 18 mfd, 16V Elec Radial 8326181
C166 Capacitor, .l1 mfd, [email protected] Mono Axial 8374194
C172 Capacitor, .1 mfd, 59V Mono Axial 8374194
C176 Capacitor, .1 mfd, 59V Mono Axial 8374194
c181 Capacitor, .1 mfd, 59V Mono Axial 8374144
C284 capacitor, .1 mfd, 56V Mono Axial 8374104
C2ÿ1 Capacitor, 22 mfd, l6V Elec Radial 8326221
C282 Capacitor, 18 mfd, l6V Elec Radial 8326191
c203 Capacitor, .1 mfd, 59V Mono Axial 8374104
c204 Capacitor, 19 mfd, 16V Elec Radial 8326101
C285 Capacitor, 198 pfd, 59V Cer Disk 8301104
CRI Diode, 1N4148 8159148
Ol Transistor, 2N3996 8189996
02 Transistor, 2N3996 8100906
80
Parts List
Main PCB Assembly, Model 4P Computer
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Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
Resistor,
750 ohm, 1/4W 5%
198 kohm, 1/4W 5%
4.7 kohm, 1/4W 5%
22 ohm,
228 ohm,
1.2 kohm,
2.2 kohm,
108 ohm,
138 onm,
13% ohm,
1 kohm,
1 kohm,
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
3 kohm, 1/4W 5%
B28 ohm, 1/4W 5%
299 ohm, 1/4W 5%
162 kohm, 1/4W 5%
27 ohm, 1/4W 5%
918 ohm,
914 ohm,
158 ohm,
18 kohm, 1/4W 5%
14 kohm, 1/4W 5%
270 kohm, 1/4W 5%
28 kohm, 1/4W 5%
4.7 kohm, 1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 5%
1/4W 53
3.6 kohm,
128 ohm,
159 ohm,
4.7 kohm, 1/4W 5%
19 kohm, 1/4W. 5%
Resistor Pak 27 ohm, l6-Pin DIP
Resistor Pak 1.5 kohm, 19-Pin SIP
Resistor Pak 158 ohm, 1ÿ-Pin SIP
81
8207175
8207419
8207247
8297022
8297122
8297212
8207222
8297119
8207113
8297113
8287218
8207218
8287230
8207182
8207128
8207416
82970927
8207191
8247191
8207115
8207318
8207310
8207427
8207328
8207247
8207236
8297112
8207115
8297247
8287310
8299927
8290015
8299013
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Parts List
Main PCB Assembly, Model 4P Computer
— bi zen EEE EEE ELLE EEE EEE PEIN TEEN SEE LE — —
— т =
Item Sym Description
Part Number
— pampas pos plis bs EEE
Ul IC, 7418123, Multivibrator
U2 IC, 7415374, Flip Flop
U3 IC, 741.5244, Octal Buffer
U4 IC, 74LS38, Quad 2-Input NAND
US IC, 74LS£8, Quad 2-Input AND
U6 IC, 741LS94, Hex Inverter
U7 IC, 7415245, Transceiver
08 IC, 741.5244, Octal Buffer
ug IC, 74L5367, Hex Driver
U1G IC, 741594, Hex Inverter
Ull IC, 741574, Flip Flop
U13 IC, [email protected], 2-Input NOR
015 IC, 74532, Quad 2-Input OR
Ul6 IC, MCM6BA316E, Character ROM
U17 IC, 74L5244, Octal Buffer
Ul8 IC, 74SLS166, 8-Bit Shift Reg
Ul9 IC, 74LS175, Quad Flip Flop
U28 IC, 74584, Hex Inverter
U22 IC, 74145153, Multiplexer
U23 IC, 74185244, Octal Buffer
U24 IC, 4016, 2K x 8 RAM Static
U25 IC, 7416585157, Multiplexer
U26 IC, 68345, CRTC
U27 IC, 7418273, Flip Flop
U28 IC, 7418373, Octal Latch
U29 IC, 74LS157, Multiplexer
U3A ТС, 741514, Hex Inverter
031 IC, 741582, 2-Input NOR
U32 IC, 741598, Quad 2-Input AND
U33 IC, 741.588, Quad 2-Input NAND
U34 IC, 74LS157, Multiplexer
U35 IC, 74LS51, AND-OR Inverter
U36 IC, 741LS98, Quad 2-Input NAND
U37 IC, 74L586, Quad 2-Input OR
U38 IC, 74L5368, Hex Driver
U39 IC, 7415244, Octal Buffer
U4p IC, 74LS245, Transceiver
U4l IC, 74LS244, Octal Buffer
U42 IC, 74F84, Hex Inverter
U43 IC, Z8BA, CPU
U44 IC, MCM68A322, Boot ROM
U45 IC, 74LS138, 1 of 8 Demultiplexer
U46 IC, 74LS138, 1 of 8 Demultiplexer
82
8020123
8828374
89828244
80290038
8920098
8929094
80280245
8020244
8020367
8029794
8029074
8929802
801098032
804909097
8020244
8020166
8028175
8910004
8028153
8928244
8848116
88628157
8040845
8020273
8020373
8020157
8020814
8920902
8927098
8020099
8020157
8020051
80200809
8020086
8020368
8029244
8020245
8020244
8015074
8047888
89289138
8920138
Parts List
Main PCB Assembly, Model 4P Computer
ls ip — — — — LE EE SE EE E— —
EE EE EE EE — A EE EE EE —Z— ду АА
Item Sym Description Part Number
U47 IC, [email protected], Control Decode 8975608
U48 IC, 741598, Counter 8920999
usd IC, PALI6R6A, System Timing 89759606
U51 IC, PAL19L8, Video Timing 8875788
U52 IC, NE564, PLL/VCO 8040564
U53 IC, [email protected], Binary Counter 8920004
Us4 IC, 74LS161, Counter 8920161
U55 IC, 74LS138, 1 of 8 Demultiplexer 8928138
U56 IC, 74LS244, Octal Buffer 8027244
U57 IC, 74LS174, Flip Flop 8929174
U58 IC, 7415273, Flip Flop 8820273
U59 IC, 7418174, Flip Flop 8920174
ued IC, 74LS74, Flip Flop 8820874
U62 IC, PAL16L8, Memory Map 89756068
U63 IC, PAL16L8, Page Map 89875568
U64 IC, 74LS32, Quad 2-Input OR 8920032
U66 IC, 1488, Driver 8959188
U67 IC, 1489, Receiver 89050189
U68 IC, 1489, Receiver 8059189
U69 IC, 741LS244, Octal Buffer 89289244
U78 IC, 7415367, Hex Driver 8720367
071 IC, 741,527, Triple 3-Input NOR 8029827
U72 IC, TR1865, UART 8040865
U73 IC, 7418174, Flip Flop 8020174
U74 IC, 7415367, Hex Driver 89290367
U75 IC, 7415139, 1 of 4 Demultiplexer 8020139
U76 IC, BR1943-99, Clock Generator 8040943
U77 IC, 741538, Quad 2-Input NAND 8020038
U78 IC, [email protected], Hex Inverter 8920994
U79 IC, FDC9216 8840216
UBA IC, 7418245, Transceiver 8028245
081 IC, WD1793 8030793
82 IC, 74LS269, 5-Input NOR 80280269
U83 IC, 7416, Hex Inverter 8000016
U84 IC, 7418245, Transceiver 8920245
U85 IC, 741802, 2-Input NOR 80208902
U86 IC, 74LS174, Flip Flop 8729174
U87 IC, 741,584, Hex Inverter 8029084
U88 IC, 74LS368, Hex Driver 8020368
UY IC, 741538, Quad 2-Input NAND 89828838
U91 IC, 7416, Hex Inverter 8000016
092 IC, 74LS93, Binary Counter 8920093
U93 IC, 7416, Hex Inverter 8000016
U94 IC, 74LS08, Quad 2-Input AND 8729008
83
Parts List
Main PCB Assembly, Model 4P Computer
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Item Sym Description Part Number
U95 IC, [email protected], Hex Inverter 8020084
U96 IC, [email protected]@, Quad 2-Input NAND 8020008
097 IC, 74L874, Flip Flop 8920074
U98 IC, 74LS9B, Quad 2-Input NAND 8920099
U99 IC, 7415195, Shift Register 8920195
ulgd IC, 74LS240, Octal Buffer 89028248
ulgl IC, 74LS32, Quad 2-Input OR 8920032
U192 IC, 7419874, Flip Flop 8029974
0194 IC, Delay Line 8429828
[email protected] IC, 74LS74, Flip Flop 8920074
Ulge IC, MC14848, Binary Counter 8030049
U197 IC, 74LS123, Multivibrator 8020123
U198 IC, 74L5157, Multiplexer 8828157
U189 IC, 74LS157, Multiplexer 8028157
U118 IC, 74L5245, Transceiver 8028245
Ulll IC, 74564, AND-OR Inverter 8010064
U112 IC, 74532, Quad 2-Input OR 8019832
U113 IC, 748112, J-K Flip Flop 8910112
Ull4 IC, 74Fÿ8, Quad 2-Input AND 80150908
U115 IC, MCM6665, 64K DRAM, 298 nsec 8040665
thru
U138
U131 IC, 7415283, Binary Adder 8020283
0161 IC, 74LS11, Triple 3-Input AND 8070911
Yl Crystal, 20.2752 MHz 8409032
Y? Crystal, 4 MHZ 8409918
4P GATE ARRAY THEORY OF OPERATION
5.2 CPU THEORY OF OPERATION
5.2.1 Introduction
Contained in the following paragraphs is a description of the
component parts of the Model 4P CPU Gate Array. It is divided
into the logical operational functions of the computer. All com-
ponents are located on the Main CPU board inside the case
housing. Refer to Section 3 for disassembly/assembly
procedures.
5.2.2 Reset Circuit
The Model 4P reset circuit provides the neccessary reset
pulses to all circuits during power up and reset operations. R25
and C214 provide a time constant which holds the input of U121
low during power-up. This allows power to be stable to all cir-
cuits before the RESET* and RESET signals are applied. When
C214 charges to a logic high, the output of U121 triggers the
input of a retriggerable one-shot multivibrator (U1). U1 outputs
a pulse with an approximate width of 70 microsecs. When the
reset switch is pressed on the front panel, this discharges C214
and holds the input of U121 low until the switch is released. On
release of the switch, C214 again charges up, triggering U121
and U1 to reset the microcomputer. Another signal POWRST"
is generated to clear drive select circuit immediately when
reset switch is pressed.
5.2.3 CPU
The central processing unit (CPU) of the Model 4P microcom-
puter is a Z80A microprocessor. The Z80A is capable of run-
ning in either 2 MHz or 4 MHz mode. The CPU controls all
functions of the microcomputer through use of its address lines
(AO-A15), data lines (DO-D7), and control lines (/M1, /IOREQ,
/RD, WA, /MREQ, and /RFSH). The address lines (AO-A15)
are buffered to other ICs through two 74LS244s (U67 and U27)
which are enabled all the time with their enables pulled to GND.
The control lines are buffered to other ICs through a 74F04
(U87). The data lines (D0-D7) are buffered through a bi-direc-
tional 74L5245 (U86) which is enabled by BUSEN* and the di-
rection is controlled by BUSDIR*.
5.2.4 System Timing
The main timing reference of the microcomputer, with the
exception of the FDC circuit, is generated by a Gate Array
U148 and a 20.2752 MHz Crystal. This reference is inter-
nally divided in the Gate Array to generate all necessary tim-
ing for the CPU, video circuit, and RS-232-C circuit. The
CPU clock is generated U148 which can be either 2 or
4MHz depending on the logic state of FAST input (pin 6 of
148). If FAST is a logic low, the U148 generates a 2.02752
MHz clock. If FAST is a logic high, U148 generates a
4.05504 MHz signal. PCLK (pin 23 of U148) is filtered
through a ferrite bead (FB2) and 22) Resistor (R9) and then
85
fed to the CPU U45. PCLK is generated as a symmetrical
clock and is never allowed to be short cycled. (eg.) Not al-
lowed to generate a low or high pulse under 110
nanoseconds.
9.2.4.1 Video Timing
The video timing is also generated by U148 with the help of a
PLL Multiplier Module (PMM) U146. These two ICs generate all
the necessary timing signals for the four video modes: 64 x 16,
32 x 16, 80 x 24, and 40 x 24. Two reference clocks are required
for the four video modes. One reference clock is 10.1376 MHz.
Itis generated internally to U148, and is used by the 64 x 16 and
32 x 16 modes. The second reference clock is a 12.672 MHz
(12M) clock which is generated by the PMM U146. 12M clock
is used by the 80 x 24 and 40 x 24 modes. A 1.2672 MHz
(1.2M16) signal is output from pin 3 of U148 and is generated
from the master reference clock, the 20.2752 MHz crystal.
1.2M16 is used for a reference clock for the PMM. The PMM is
internally set to oscillate at 12.672 MHz which is output as 12M.
U148 divides 12M by 10 to generate a second 1.2672 MHz
clock (1.2M10) which is fed into pin 5 of U146 (PMM). The two
1.2672 MHz signals are internaily compared in the PMM where
it corrects the 12.672 MHz output so it is synchronized with the
20.2752 MHz clock.
MODSEL and 8064“ signals are used to select the desired
video mode, 8064" controls which reference clock is used by
U127 and MODSEL controls the single or double character
width mode. Refer to the following chart for selecting each
video mode.
8064" MODSEL Video Mode
0 0 64 x 16
0 1 32x 16
1 0 80 x 24
1 1 40 x 24
“This is the state to be written to latch U85. Signal is inverted
before being input to U1 48.
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Figure 5-19. Model 4P Functional Block Diagram
86
DCLK, the reference clock selected, is output from U148. U148
generates SHIFT, XADR7*, CRTCLK, LOADS", and LOAD"
for proper timing for the four video modes. U149 also generated
H, 1, and J which are fed to the Graphics Port J7 for reference
timings of Hires graphics video. Refer to Video Timing, Figs. 5-
3 and 5-4 for timing reference.
5.2.5 Address Decode
The Address Decode section will be divided into two subsec-
tions: Memory Map decoding and Port Map decoding.
5.2.5.1 Memory Map Decoding
Memory Map Decoding is accomplished by Gate Array 4.2
(U106). Four memory map modes are available which are com-
patible with the Model Ill and Model 4 microcomputers. U106 is
used for memory map control which also controls page map-
ping of the 32K RAM pages. Refer to Memory Maps below.
5.2.5.2 Port Map Decoding
Port Map Decoding is accomplished by Gate Array 4.2 (U106).
U106 decodes the low order address (AO-A7) from the CPU
and decodes the port being selected. The IN* signal allows the
CPU to read from a selected port and the QUT* signal allows
the CPU to write to the selected port. Refer to IO Por
Assignment.
5.2.6 ROM
The Model 4P contains only a 4K x 8 Boot ROM (U69). This
ROM is used only to boot up a Disk Operating System into the
RAM memory. If Model Il! operation or DOS is required, then
the RAM from location 0000-37FFH must be loaded with an im-
age of the Model II! or 4 ROM code and then executed. A sys-
tem program called MODEL Alis supplied with the Model 4P
to provide the ROM image for proper Model Ill operation. On
power-up, the Boot ROM is selected and mapped into location
0000-0FFFH. Ifthe Boot ROM is not required after boot up, the
Boot ROM must be mapped out by OUTing to port 9CH with DO
set or by selecting Memory Map modes 2 or 3. In Mode 1 the
RAM is write enabled for the full 14K. This allows the RAM area
mapped where Boot ROM is located to be written to while ex-
ecuting out of the Boot ROM. Refer to Memory Maps.
The Model 4P Boot ROM contains all the code necessary to
initialize hardware, detect options selected from the keyboard,
read a sector from a hard disk or floppy, and load a copy of the
Model lll ROM-Image (as mentioned) into the lower 14K of
RAM.
87
The firmware is divided into the following routines:
* Hardware Initialization
* Keyboard Scanner
* Control
* Floppy and Hard Disk Driver
* Disk Directory Searcher
* File Loader
* Error Handler and Displayer
* RS-232 Boot
* Diagnostic Package
Theory of Operation
This section describes the operation of various routines in the
ROM. Normally, the ROM is not addressable by normal use.
However, there are several routines that are available through
fixed calling locations and these may be used by operating sys-
tems that are booting.
On a power-up or RESET condition, the Z80's program counter
is set to address 0 and the boot ROM is switched-in. The mem-
ory map of the system is set to Mode 0. (See Memory Map for
details.) This will cause the Z80 to fetch instructions from the
boot ROM.
The Initialization section of the Boot ROM now performs these
functions:
Disables maskabie and non-maskable interrupts
Interrupt mode 1 is selected
Programs the CRT Controller
Initializes the boot ROM control areas in RAM.
Sets up a stack pointer
issues a Force Interrupt to the Floppy Disk Controiler
to abort any current activity
Sets the system clock to 4mhz
Sets the screen to 64 x 16
9. Disables reverse video and the alternate character
sets
Tests for < . > key being pressed”"
Clears all 2K of video memory
о сл A ON —
© N
10.
11.
* This is a special test. If the < , > is being pressed, then
control is transferred to the diagnostic package in the
ROM. All other keys are scanned vía the Keyboard
Scanner.
hv
pe
| x L'HOVX
1 ATOLIO
Г x VO
I | » SAVOQT]
x LATHS
OY
1 р
LS LS US US LIULI UI LILILIL y
» LOC
XT <!
WZT ‘WAT
80 x 24 Mode
64 x 16 Mode
Figure 5-20. Video Timing
88
| На | 1 I * LAJYX
УЧ Эно
+ VO"
J J ren... nnn NAN x LATHS
J À | gun
x LOC
ATOA
WZT ‘WET
40 x 24 Mode
32 x 16 Mode
Figure 5-21. Video Timing
89
The Keyboard scanner is now called. It scans the keyboard for
a set period of time and returns several parameters based on
which, if any, keys were pressed.
The keyboard scanner checks for several different groups of
keys. These are shown below:
Function Group
<F1>
<F2>
<F3>
<1>
<2>
<3>
<Left-Shift>
<Right-Shift>
<Ctrl>
<Caps>
Selection Group
OO NMO O0 >
Special Keys
<P>
<i>
<N>
Misc Keys
<Enter>
<Break>
When any key in the Function Group is pressed, it is recorded
in RAM and will be used by the Control routine in directing the
action of the boot. If more than one of these keys are pressed
during the keyboard scan, the last one detected will be the one
that is used. The Function group keys are currently defined as:
Will cause hard disk boot
Will cause floppy disk boot
Will force Model lll mode
Reserved for future use
Boot from RS-232 port
Reserved for future use
Reserved for future use
<F1> or <i>
<F2> or <2>
<F3> or <3>
<Left-Shift>
<Right-Shift>
<Ctrl>
<Caps>
The Special keys are commands to the Control routine which
direct handling of the Model III ROM-image. Each key is de-
tected individually.
<P> When loading the Model Ili
ROM-image, the user will be
prompted when the disks can
be switched or when ROM
BASIC can be entered by
pressing <Break>.
Instructs the Control routine to
not load the Model I! ROM-
image, even if it appears that
the operating system being
booted requires it.
<N>
90
Instructs the Control routine to
load the Model Itt ROM-image,
even if it is already loaded. This
is useful if the ROM-image has
been corrupted or when switch-
ing ROM-images. (Note that
this will not cause the ROM-
image to be loaded if the boot
sector check indicates that the
Model [li ROM image is not
needed. Press <F3> or <F3>
and <L> to accomplish that.
<L>
The Selection group keys are used in determining which file will
be read from disk when the ROM-image is loaded. For details
of this operation, see the Disk Directory Searcher. If more than
one of the Selection group keys are pressed, the last one de-
tected will be the one that is used.
The Miscellaneous keys are:
<Break> Pressing this key is simpiy re-
corded by setting location
4058BH non-zero. It is up to an
operating system to use this
flag if desired.
Terminates the Keyboard rou-
tine. Any other keys pressed up
to that time will be acted upon.
<Enter> is useful for experi-
enced users who do not want to
wait until the keyboard timer
expires.
<Enter>
The Control section now takes over and follows the following
flowchart.
Begin
Hard
Attempt to
<F1>
ob Yes Goto [1] Disk Drive read boot
pressed ? (1) (Hard Disk Boot) Present 7? sector
No
No e error
2
<F2>
or <2> Yes Goto [2]
pressed ? 2) {Floppy Disk Boot) <Fl> Display
or <l> Yes Hard Disk
pressed ? | Error
Message
No
No
<F3>
or <3>
pressed ?
Yes Goto [14]
(3) (Model III Boot) A
O) > stop
No
<Right- Shift>
Yes Goto [4]
(RS-232 Boot)
pressed ?
At this point, no valid Function keys
p Y Floppy Attempt to
No have been pressed. Disk Drive read boot
Present ? sector
ARCNET Display an error
Controller Yes message, (ARCNET
proare Boot ROM required No
resent ?
for ARCNET Boot) Yes
No
No
a O
91
<F2> у
or <2> ES
pressed ?
Display
Floppy Disk
Error
Message
No
stop
<N>
pressed
>
Sector
256 bytes,
Model ITI
Model II
ROM Image
Present ?
Note: 3
PI
Yes
and no ref.s
Set Transfer
Address to
4399H
Note: 2
®
<L>
essed
?
92
(3)— > Set
Transfer
Address to
3815H
Note: 2
Attempt to
locate
ROM Image
on
Floppy Disk
Note: 4
Write-enable
B-37FFH
{Mode 1)
Load ROM
Image
Note: 5
Errors
while loading
ROM Image ?
Display
Set Transfer Error
Address at end Message
of ROM Image
(Normally 3815H)
Note: 2 V
stop
Switch boot ROM
cut of Memory
ROM
Image
Present ?
Jump to
Transfer Address
<P>
pressed
7
Display
"RCM Image
is loaded" Initialize
message RS-232 Port
Note: 6
Wait for
<ENTER> or
<BREAK> to .
be pressed Wait for
Carrier Detect
Determine
Y Correct
Baud Rate
Write-protect
memory (Mode $)
Transmit Baud
Rate Detect
Message
Set CPU speed
to 2MHz
93
Walt for
Sync Byte
(FFH)
Load program
from R5-232
Display and
transmit error
Transfer
control
to address
recelved
Notes:
(1) If the boot sector was not 256 bytes in length, then itis as-
sumed to be a Model lll package, and the ROM-image will
be needed. If the sector is 256 bytes in length, then the
sector is scanned for the sequence CDxx00H. The CD is
the first byte of a Z80 unconditional subroutine call. The
next byte can have any value. The third byte is tested
against a zero. What this check does is test for any refer-
ences to the first 256 bytes of memory. All Radio Shack
Model ill operating systems, and many other packages all
reference the ROM at some point during the boot sector.
Most boot sectors will display a message if the system can-
not be loaded. To save space, these routines use the
Model HI ROM calls to display the message. Several ROM
calls have their entry points in the first 256 bytes of mem-
ory, and these references are detected by the boot ROM.
94
Packages that do not reference the Model Ill ROM in the
boot sector can still cause the Model Hl ROM image to be
loaded by coding a COxx00 somewhere in the boot sector.
It does not have to be executable. At the same time, Model
4 packages must take care that there is no sequence of
bytes in the boot sector that could be mis-interpreted to be
a reference to the Boot ROM. An example of this would be
sequence 06CDOEQO, which is a LD B,0CDH and a LD
C,0. If the boot sector cannot be changed, then the user
must press the <F3> key each time the system is started
to inform the ROM that the disk contains a Model ill pack-
age which needs the Model lll ROM-image.
If you are loading a Model 4 operating system, then the
boot ROM will always transfer control to the first byte of the
boot sector, which is at 4300H. If you are loading a Mode!
ll operating system or about to use Model lil ROM BASIC,
then the transfer address is 3015H. This is the address of
a jump vector in the “CG” ROM of the Model III ROM image,
and this will cause the system to behave exactly like a
Model Ill. If the ROM-image file that is loaded has a differ-
ent transfer address, then that address will be used when
loading is complete. If the image is already present, it will
use 3015H.
Two different tests are done to insure that the Model II
ROM image is present. The first test is to check ever third
location starting at 3000H for a C3H. This is done for 10 lo-
cations. If any of these locations does not contain a C3H,
then the ROM image is considered to be “not present”.
The next test is to check two bytes at location OOOBH. If
these addresses contain ESE1H, then the ROM image is
considered to be “present”.
(4) See Disk Director Searcher for more information.
(5) See File Loader for more information.
(6) The RS-232 loader is described under RS-232 Boot.
Disk Directory Searcher
When the Model [ll ROM image is to be loaded, it is always read
from the floppy in drive 0.
Before the operation begins, some checks are made. First, the
boot sector is read in from the floppy and the first byte is
checked to make sure it is either a 00H or a FEH. If the byte
contains some other value, no attempt will be made to read the
ROM image from that disk. The location of the directory cytinder
is then taken from the boot sector and the type of disk is deter-
mined. This is done by examining the Data Address Mark that
was picked up by the Floppy Disk Controller (FDC) during the
read of the sector. If the DAM equals 1, the disk is a TRSDOS
1.x style disk. If the DAM equals 0, then the disk is a LDOS 5.1/
TRSDOS 6 style disk. This is important since TRSDOS 1.x
disks number sectors starting with 1 and LDOS style disks
number sectors starting with 0.
Once the disk type has been determined, an extra test is made
if the disk is a LDOS style disk. This test reads the Granule Al-
location Table (GAT) to determine if the disk is single sided or
double sided.
The directory is then read one record at a time and a compare
is made against the pattern 'MODEL% ' for the filename and
111 for the extension. The '%' means that any character will
match this position. If the user pressed one of the selection
keys (A-G) during the keyboard scan, then that character is
substituted in place of the '‘%' character. For example, if you
pressed 'D', then the search would be for the file MODELD
with the extension ‘Il’. The searching algorithm searches until
it finds the entry or it reaches the end of the directory.
Once the entry has been found, the extent information for that
file is copied into a control block for tater use.
File Loader
The file loader is actually two modules — the actual loader and
a set of routines to fetch bytes from the file on disk. The loader
is invoked via a RST 28H. The byte fetcher is called by the
loader using RST 20H. Since restart vectors can be re-directed,
the same loader is used by the RS-232 boot. The difference is
that the RST 20H is redirected to point to the RS-232 data re-
ceiving routine. The loader reads standard loader records and
acts upon two types:
01 Data Load
1 byte with length of block, including address
1 word with address to load the data
n bytes of data, where n + 2 equals the length specified
02 Transfer Address
1 byte with the value of 02
1 word with the address to start execution at.
Any other loader code is treated as a comment block and is ig-
nored. Once an 02 record has been found, the loader stops
reading, even if there is additional data, so be sure to place the
02 record at the end of the file.
95
Floppy and Hard Disk Driver
The disk drivers are entered via RST 8H and will read a sector
anywhere on a floppy disk and anywhere on head 1 (top-head)
in a hard disk drive. Either 256 or 512 byte sectors are readable
by these routines and they make the determination of the sector
size. The hard disk driver is compatible with both the WD1000
and the WD1010 controllers. The floppy disk driver is written for
the WD 1793 controller.
Serial Loader
Invoking the serial loader is similar to forcing a boot from hard
disk or floppy. In this case the right shift key must be pressed at
some time during the first three seconds after reset. The pro-
gram does not care it the key is pressed forever, making it con-
venient to connect pins 8 and 10 of the keyboard connector with
a shorting plug for bench testing of boards. This assumes that
the object program being loaded does not care about the key
closure.
Upon entry, the program first asserts DTR (J4 pin 20) and RTS
(J4 pin 4) true. Next, “Not Ready” is printed on the topmost line
of the video display. Modem status line CD (J4 pin 8} is then
sampled. The program loops until it finds CD asserted true. At
that time the message “Ready” is displayed. Then the program
sets about determining the baud rate from the host computer.
To determine the baud rate, the program compares data re-
ceived by the UART to a test byte equal to '55' hex. The receiver
IS first set to 19200 baud. Iften bytes are received which are not
equal to the test byte, the baud rate is reduced. This sequence
is repeated until a valid test byte is received. If ten failures occur
at 50 baud, the entire process begins again at 19200 baud. If a
valid test byte is received, the program waits for ten more to ar-
rive before concluding that it has determined the correct baud
rate. If at this time an improper byte is received or a receiver er-
ror (overrun, framing, or parity) is intercepted, the task begins
again at 19200 baud.
In order to get to this point, the host or the modem must assert
CD true. The host must transmit a sequence of test bytes equal
to '55" hex with 8 data bits, odd parity, and 1 or 2 stop bits. The
test bytes should be separated by approximately 0.1 second to
avoid overrun errors.
When the program has determined the baud rate, the message:
“Found Baud Rate x"
is displayed on the screen, where “x” is a letter from A to P,
meaning:
A = 50baud E = 150 | = 1800 M = 4800
B=75 F = 300 J = 2000 N = 7200
С = 110 G = 600 K = 2400 O = 9600
D = 134.5 H = 1200 L = 3600 P = 19200
The same message less the character signifying the baud rate
is transmitted to the host, with the same baud rate and protocol.
This message is the signal to the host to stop transmitting test
bytes.
After the program has transmitted the baud rate message, it
reads from the UART data register in order to clear any overrun
error that may have occurred due to the test bytes coming in
during the transmission of the message. This is because the re-
ceiver must be made ready to receive a sync byte signalling the
beginning of the command file. For this reason, it is important
that the host wait until the entire baud rate message (16 char-
acters) is received before transmitting the sync byte, which is
equal to ‘FF’ hex.
When the loader receives the sync byte, the message.
“Loading”
is displayed on the screen. Again, the same message is trans-
mitted to the host, and, again, the host must wait for the entire
transmission before starting into the command file.
If the receiver should intercept a receive error while waiting for
the sync byte, the entire operation up to this point is aborted.
The video display is cleared and the message:
“Error, x”
is displayed near the bottom of the screen, where "x" is a letter
from B to H, meaning:
B = parity error
C = framing error
D = parity & framing errors
E = overrun error
F = parity & overrun errors
G = framing & overrun errors
H = parity & framing & overrun errors
The message:
él Error”
is then transmitted to the host. The entire process is then re-
peated from the “Not Ready” message. A six second delay 15
inserted before reinitialization. This is longer than the time re-
quired to transmit five bytes at 50 baud, so there is no need to
be extra careful here.
If the sync byte is received without error, then the “Loading”
message is transmitted and the program is ready to receive the
command file. After receiving the “Loading” message the host
can transmit the file without nulls or delays between bytes.
96
(Since the file represents Z80 machine code and all 256
combinations are meaningful, it would be disastrous to
transmit nulls or other ASCII control codes as fillers, ac-
knowledgement, or start-stop bytes. The oniy control
codes needed are the standard command file control
bytes.)
Data can be transmitted to the loader at 19200 baud with no de-
lays inserted. Two stop bits are recommended at high baud
rates.
See the File Loader description for more information on file
loading.
If a receive error should occur during file loading, the abort pro-
cedure described above will take place, so when attempting re-
mote control, it is wise to monitor the host receiver during
transmission of the file. When the host is near the object board,
as is the case in the factory application, or when more than one
board is being loaded, it may be advantageous or even nec-
essary to ignore the transmitted responses of the object
board(s) and to manually pace the test byte, sync byte, and
command file phases of the transmission process, using the
video display for handshaking.
System Programmers Information
The Model 4P Boot ROM uses two areas of RAM while itis run-
ning. These are 4000H to 40FFH and 4300H to 43FFH. (For
512 byte boot sectors, the second area is 4300H to 44FFH.) If
the Model Ill ROM Image is loaded, additional areas are used.
See the technical reference manual for the system you are us-
ing for a list of these areas.
Operating systems that want to support a software restart by re-
executing the contents of the boot ROM can accomplish this in
one of two ways. If the operating system relies on the Model III
ROM-Image, then jump to location 0 as you have in the past. If
the operating system is a Model 4 mode package, a simple way
is to code the following instructions in your assembly and load
them before you want to reset:
Absolute Location Instruction
0000 DI
0001 LD A 1
0003 OUT (9CH),A
These instructions cause the boot ROM to become address-
able. After executing the QUT instruction, the next instruction
executed will be one in the boot ROM. (These instructions also
exist in the Model Ill ROM image at location 0.) The boot ROM
has been written so that the first instruction is at address 0005.
The hardware must be in memory mode 0 or eise the boot ROM
will not be switched in. This operation can be done with an OUT
instruction and then a RST 0 can be executed to have the ROM
switched in.
Restarts can be redirected at any time while the ROM is
switched in. All restarts jump to fixed locations in RAM and
these areas may be changed to point to the routine that is to be
executed.
Restart RAM Location Default Use
0 попе Cold Start/Boot
8 4000H Disk I/O Request
10 4003H Display string
18 4006H Display block
20 4009H Byte Fetch (Called by Loader)
28 400CH File Loader
30 400FH Keyboard scanner
38 4012H Reserved for future use
66 4015H NMI (Floppy 1/0 Command
Complete)
The above routines have fixed entry parameters. These are de-
scribed here.
Disk I/O Request (RST 8H)
Accepts
A 1 for floppy, 2 for hard disk
B Command
Initialize 1
Restore 4
Seek 6
Read 12 (All reads have an im-
plied seek)
С Sector number to read
The contents of the location disktype
(405CH) are added to this value before
an actual read. If the disk is a two sided
floppy, just add 18 to the sector number.
DE Cylinder number. (Only E is used in
floppy operations)
HL Address where data from a read opera-
tion is to be stored.
Returns
Z Success, Operation Completed
NZ Error, Error code in A
Error Codes
3 Hard Disk drive is not ready
4 Floppy disk drive is not ready
5 Hard Disk drive is not available
6 Floppy disk drive is not available
7 Drive Not Ready and no Index (Disk in
drive, door open)
8 CRC Error
9 Seek Error
11 Lost Data
12 ID Not Found
Display String (RST 10H)
Accepts
HL Pointer to text to be displayed.
Text must be terminated with a null (0).
DE Offset position on screen where text is to
be displayed.
(A OOOOH will be the upper left-hand cor-
ner of the display.)
Returns
Success Always
A Altered
DE Points to next position on video
HL Points to the null (0).
Display Block (RST 18H)
Accepts
HL Points to control vector in the format:
+0 Screen Offset
+2 Pointer to text, terminated with
null
+4 Pointer to text, terminated with
null
+n word FFFFH End of control
vector
or +n word FFFEH Next word is
new Screen
Offset
It Z flag is set on entry, then the first screen offset is read from
DE instead of from the control vector.
Each string is positioned after the previous string, unless a
FFFEH entry is found. This is used heavily in the ROM to re-
duce duplication of words in error messages.
Returns
Success Always
DE Points to next position on video
Byte Fetch (RST 20H)
Accepts None
Returns
Z Success, byte in A
NZ Failure, error code in A
Errors
Any errors from the disk I/O call and:
2 ROM Image can't be loaded — Too many
extents
10 ROM Image can't be loaded — Disk drive
is not ready
Flle Loader (RST 28H)
Accepts None
Returns
Z Success
NZ Failure, error code in A
Errors
Any errors from the disk VO call of the
byte fetch call and:
0 The ROM image was not found on drive 0
There are several pieces of information left in memory by the
boot ROM which are useful to system programmers. These are
shown below:
RAM Location Description
401DH ROM Image Selected (% for none
selected or A-G)
4055H Boot type
1 = Floppy
2 = Hard disk
3 = ARCNET
4 = RS-232C
5-7 = Reserved
4056H Boot Sector Size (1 for 256, 2 for 512)
4057H RS-232 Baud Rate (only valid on RS-
232 boot)
4059H Function Key Selected
0 = No function key selected
<F1> or <1> 86
<F2> or <2> 87
<F3> or <3> 88
<Caps> 85
<Ctrl> 84
<Left-Shift> 82
<Right-Shift> 83
Reserved 80-81 and 89-50
405BH Break Key Indication {non-zero if
<Break> pressed)
405CH Disk type (0 for LDOS/
TRSDOS 6,1 for
TRSDOS 1.x)
Keep in mind that Model Hl ROM image will initialize these
areas, so this information is useful only to the Model 4 mode
programmer.
5.2.7 RAM
Two configurations of Random Access Memory (RAM) are
available on the Model 4P: 64K and 128K. The 64K and 128K
option use the 6665-type 64K x 1 200NS Dynamic RAM, which
requires only a single + 5v supply voltage.
98
The DRAMs require multiplexed incoming address lines. This
is accomplished by ICs U110 and U111 which are 74LS157
multiplexers. Data to and from the DRAMs are buffered by a
741.8245 (U118) which is controlled by Gate Array 4.2 (U106).
The proper timing signals RAS0*, RASt*, MUX*, and CAS” are
generated by a delay line circuit U94. U116 (1/2 of a 748112)
and U117 (1/4 of a 74F08) are used to generate a precharge
circuit. During M1 cycles of the Z80A in 4 MHz mode, the high
time in MREQ has a minimum time of 110 nanosecs. The spec-
ification of 6665 DRAM requires a minimum of 120 nanosecs so
this circuit will shorten the MREQ signal during the M1 cycle.
The resulting signal PMREQ is used to start a RAM memory
cycle through U114 (a 74564). Each different cycle is controlled
at U114 to maintain a fast M1 cycle so no wait states are re-
quired. The output of U114 (PRAS*) is ANDed with RFSH to not
allow MUX* and CAS* to be generated during a REFRESH
cycle. PRAS" also generates either RASO" or RAS1”, depend-
ing on which bank of RAM the CPU is selecting. GCAS* gen-
grated by the delay line U94 is latched by U116 (1/2 of a
74S112) and held to the end of the memory cycle. The output
of U116 is ANDed with VIDEO signal to disable the CAS" signal
from occurring if the cycle is a video memory access. Refer to
M1 Cycle Timing (Figure 5-8. and 5-9.), Memory Read and
Memory Write Cycle Timing (Figure 5-10.) and (Figure 5-11.).
AS g = WOY
A8 B = TAS
Ag g = A195
THAHT ЧМ
WYd ¥Z¢ (1‘T‘g) zum HZE WYA
(4°19)
EE TE EE a EE dal o a
A9T WVH
XT CdAMdX
{(MOYdOYS
“HOYANA “HOYASHA)
ATNO OVH
APT WYM
ÿ AJOW
АЙ = WOH
АЙ = ТП 5
АЙ = PIS
TJAJI HIVLS
NYH HZE (1‘T’@) mm HZE NYX
WHya MZE
IIE EEE ED EE sae an
MOT HV
(g’'1'1) zum MT OJGIA
MT OHAHM
(HDYÆDUS
'IYdNa 'A9VASAO) NN AINO OYAN
HAT HWVX
Mb WOE 100d
gd 00N
Figure 5-22. Memory
99
Ag T = WOH
АЙ g = 1195
AS T = IS
TAXI CHAAR
ИМЯ XCE
WYEU HCE
MZE WYY
(TIT) MOT WYvY
(#11) » HIT OHOIA
MT аНАЧУ
(ADYd IIS
'ISvaáNd “HOYdSHO)
MPT WWXx
T ACIÓN
AS g = WOH
AB B = TIHS
AS I = ÿTHS
THAT FIVY.LS
ИМЯ Y NY
NTE ID J ce
MOT WH
WYd MZE O TT № лат
MT ОСЯАЧУЯ
(HDVdOUS
IVANA “*A9VASACG) IM AINO ALIYM
AFT WYH
YY WOY 100g
T CIÓN
Figure 5-23. Memory
100
X = HOW
AS I = 1145
AS T = gas
THAT HLVLS
WVYM MZE 2 MAZE WY
(TIT)
WYYd XCE
(g'1'1T) »
(HOYAIDES
‘чочамя ‘HOVASHG)
£ HOON
Da a TEES a an
MZE WYd
X = WOH
AS T = [IAS
АЙ | = IS
THAI HLYVLS
HZ OHOIA
——
AT CHAN
ini
WE MZE Эн A67 WYH
(T*T“#)
WYH MZE
Дн
(ATT)
(HOVd OHS
“HOVYINA ‘HOVASAG)
¿ dOON
HCE HYU
Figure 5-24. Memory
101
H 51 7] O4 HOD] UA
abuey7 (AA Sabe / ,Ç , , ,
Nr. a — 7 01 Hwy TOI H Did
эбиечО 1’ abueyz AAA"
Cas 880849 zer DON pen рчел
бабье д” ae | чо) SE A a
intino Indu: ae nang Indu a
SWYO43AYA
Viva CGITVA ) LON-—g'AH
D ‘ ‘OOŸ HSHUJEE IC -aa 102 XI mos YODA -vaa-gvua
L
x STD
E \ x X AA
x SV
\ ] \ 10 few
\ | \ 4 TNASYH
10 xGNISYU
À | \
* SVNd
A | NHCYUNVA
Г \ | ÖHMMWd
HSAH
|
\ J a
A] Fr peux
\ fo
xX X STY-GV
\ r Г \ Im \ | [олова (ZHN7
Ш, EL SL ti |
Figure 5-25. M1 Cycle Timing (2MHZ)
102
< viva ariva ) LAH FAW
YC "dav HSdUJHN X “day ‘105 X “cat mou YY YY ¿vad-gwua
| \
SV
J L xXOW
ISWM
f L ] LC 10 4ÿsva
TNASVH
J J L хо » UNAS YE
| L J LL
xSVud
L A NACUWYY
1 [ 1 | CHHWA
1 f HSAY
1 J ae
L I L | ON
LL (UT
X LC STY-9Y
LI UM ULT LL MTOd (ZHWF)
Pa | EL C1 Ir |
LN
Figure 5-26. M1 Cycle Timing (4MHZ)
103
yr
Ума ат МА
ang?
"dav “TOD
LaW-y an
X ‘сач моя ААУ 1 vua-gvaa
* ЭМО
x X [IN
x TSYA
10 SV
х TNASYY
до xYNASVE
x SYUd
NACUNV di
OHHWA
dd
OT UW
Figure 5-27. Memory Read Cycle Timing
104
YLVO SLIUM
LAN-GIW
ХУ
“dav "7100
A
“Cav mOY
xSYO
+ X (IN
x 1SYd
20 4ÿSvVa
pases
mu
1 x TNI STH
ICO xGNAISYA
x SYAd
| NAUMNYVA
OCHYAWA
ЧМ
OHIW
X STV-0V
| Г A10d
Figure 5-28. Memory Write Cycle Timing
105
Mode 0
0000 — OFFF
1000 — 37FF
3/E8 — 37E9
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode O
0000 — 37FF
37E8 — 37E9
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode 1
0000 — OFFF
0000 — OFFF
1000 — 37FF
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Memory Map — Model 4P
SELO = 0 = OV
SEL1
ROM
SELO
SEL1
ROM
SELO =
SEL1
ROM
=0 =0V
=1 =0V
Boot ROM
RAM (Read Only)
Printer Status (Read Only)
Keyboard
Video
RAM
=0 =0V
=0 =0V
=0 = +5V
RAM (Read Only)
Printer Status (Read Only)
Keyboard
Video
RAM
|
H
+5V
= OV
=1 =0V
|
©
|
Boot ROM
RAM (Write Only)
RAM
Keyboard
Video
RAM
4K
10K
1K
1K
48K
14K
1K
1K
48K
4K
4K
10K
1K
1K
48K
106
Mode 1
0000 — 37FF
3800 — 3BFF
3C00 — 3FFF
4000 — FFFF
Mode 2
0000 — F3FF
F400 — F7FF
F800 — FFFF
Mode 3
0000 — FFFF
SELO =1 = +5V
SEL1 =0 = 0V
ROM =0 = +5V
RAM
Keyboard
Video
RAM
SELO = 0 = OV
SEL1 = 1 = +5V
ROM = X = Don’t Care
RAM
Keyboard
Video
SELO =1 = +5V
SEL1 =1 = +5V
ROM = Don't Care
|
x
|
RAM
14K
1K
1K
48K
61K
1K
2K
64K
I/O Port Assignment
Normally
Port # Used
FC —FF FF
F8 — FB F8
F4 — F7 F4
FO—F3 —
FO FO
F1 F1
F2 F2
F3 F3
EC — EF EC
ES — EB —
ES ES
E9 E9
EA EA
EB EB
E4 — E7 E4
E0 — E3 ЕО
АО — DF —
9С — 9F aC
94 — 9B —
90 — 93 90
8С — ВЕ —
88 — 8В —
88, 8A 88
89, 88 89
84 — 87 84
80 — 83 —
Out
CASSOUT *
LPOUT *
DRVSEL *
DISKOUT *
FDC COMMAND REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
MODOUT *
RS2320UT *
UART MASTER RESET
BAUD RATE GEN. REG.
UART CONTROL AND
MODEM CONTROL REG.
UART TRANSMIT
HOLDING REG.
WR NMI MASK REG. *
WR INT MASK REG. *
(RESERVED)
BOOT *
(RESERVED)
SEN *
GSELO *
CRTCCS *
CRCT ADD. REG.
CRCT DATA REG.
OPREG *
GSEL1 *
In
MODIN *
LPIN *
(RESERVED)
DISKIN *
FDC STATUS REG.
FDC TRACK REG.
FDC SECTOR REG.
FDC DATA REG.
RTCIN *
RS232IN *
MODEM STATUS
(RESERVED)
UART STATUS REG.
UART HOLDING REG.
(RESET D.R.)
RD NMI STATUS *
RD INT MASK REG. *
(RESERVED)
(RESERVED
(RESERVED
(RESERVED
GSELO *
(RESERVED)
(RESERVED)
(RESERVED)
(RESERVED)
GSEL1*
)
)
)
107
1/0 Port Description
CASSOUT *
Name:
Port Address: FC — FF
Access: WRITE ONLY
Description: Output data to cassette or for sound
generation
Note: The Model 4P does not support cassette storage,
this port is only used to generate sound that was to
be output via cassette port. The Model 4P sends
data to onboard sound circuit.
DO = Cassette output level (sound data output)
D1 = Reserved
D2—D7 = Undefined
Name: MODIN * (CASSIN *)
Port Address: FC — FF
Access: READ ONLY
Description: Configuration Status
DO =0
D1 = CASSMOTORON STATUS
D2 = MODSEL STATUS
D3 = ENALTSET STATUS
D4 = ENEXTIO STATUS
D5 = (NOT USED)
D6 = FAST STATUS
D7 = 0
Name: LPOUT *
Port Address: F8 — FB
Access: WRITE ONLY
Description: Output data to line printer
D0 —D7 = ASCIIBYTE TO BE PRINTED
Name: LPIN *
Port Address: F8— FB
Access: READ ONLY
Description: input line printer status
DO—D3 = (RESERVED)
D4 = FAULT
1 = TRUE
0 = FALSE
D5 = UNIT SELECT
1 = TRUE
0 = FALSE
D6 = OUTPAPER
1 = TRUE
0 = FALSE
D7 = BUSY
1 = TRUE
0 = FALSE
Name: DAVSEL *
Port Address: F4 — F7
Access: WRITE ONLY
Description: Output FDC Configuration
Note: Output to this port will ALWAYS cause a 1-2 mscc.
(Microsecond) wait to the Z80.
DO = DRIVE SELECTO
Di = DRIVE SELECT 1
D? = (RESERVED)
D3 = (RESERVED)
D4 = SDSEL
0 = SIDEO
1 = SIDE 1
D5 = PRECOMPEN
0 = No write precompensation
1 = Write Precompensation enabled
D6 = WSGEN
0 = No wait state generated
1 = wait state generated
Note: This wait state is to sync Z80 with FDC chip during
FDC operation.
D7 = DDEN *
108
0 = Single Density enabled (FM)
1 — Double Density enabled (MFM)
Name: DISKOUT *
Port Address: FO — F3
Access: WRITE ONLY
Description: Output to FDC Control Registers
Port FO = FDC Command Register
Port F1 = FDC Track Register
Port F2 = FDC Sector Register
Port F3 = FDC Data Register
(Refer to FDC Manual for Bit Assignments)
Name: DISKIN *
Port Address: FO — F3
Access: READ ONLY
Description: Input FDC Control Registers
I
Port FO = FDC Status Register
|
Port F1 = FDC Track Register
Port F2 = FDC Sector Register
Port F3 = FDC Data Register
{Refer to FDC Manual for Bit Assignment)
Name; MODOUT *
Port Address: EC — EF
Access: WRITE ONLY
Description: Qutput to Configuration Latch
DO = (RESERVED)
Dt — CASSMOTORON (Sound enable)
0 = Cassette Motor Off (Sound enabled)
1 = Cassette Motor On (Sound disabled)
D2 = MODSEL
О = 64 or 80 character mode
1 = 32 or 40 character mode
D3 = ENALTSET
0 = Alternate character set disabled
1 = Alternate character set enabled
D4 = ENEXTIO
0 = External IO Bus disabled
1 = External IO Bus enabled
D5 = (RESERVED)
D6 = FAST
0 = 2 MHZ Mode
1 = 4 MHZ Mode
D7 = (RESERVED)
Name: RTCIN *
Port Address: EC — EF
Access: READ ONLY
Description: Clear Real Time Clock Interrupt
DO—D7 = DON'T CARE
Name: RS2320UT *
Port Address: E8 — EB
Access: WRITE ONLY
Description: UART Control, Data Control, Modem Control,
BRG Control
Port EB = UART Master Reset
Port E9 — BAUD Rate Gen. Register
Port EA = UART Control Register (Modem Control Reg.)
Port EB = UART Transmit Holding Reg.
(Refer to Model ill or 4 Manual for Bit Assignments)
Name: RS232IN *
Port Address: E8 — EB
Access: READ ONLY
Description: Input UART and Modem Status
Port E8 = MODEM STATUS
Port E9 = (RESERVED)
Port EA = UART Status Register
Port EB = UART Receive Holding Register (Resets DR)
(Refer to Model III or 4 Manual for Bit Assignments)
Name: WRNMIMASKREG *
Port Address: E4 — E7
Access: WRITE ONLY
Description: Output NM! Latch
DO—D5 = (RESERVED)
D6 = ENMOTOROFFINT
0 = Disables Motoroff NMI
1 = Enables Motoroff NMI
D7 = ENINTRQ
0 = Disables INTRQ NMI
1 = Enables INTRQ NMI
Name: RDNMISTATUS *
Port Address: E4 — E7
Access: READ ONLY
Description: Input NMI Status
DO = 0
D2—D4 = (RESERVED)
D5 = RESET (not needed)
О = Reset Asserted (Problem)
1 = Reset Negated
D6 = MOTOROFF
0 = Motoroft Asserted
1 = Motoroff Negated
D7 = INTRQ
0 = INTRQ Asserted
1 = INTRQ Negated
Name: WRINTMASKREG *
Port Address: ЕО — ЕЗ
Access: WRITE ONLY
Description: Output INT Latch
DO—D1 = (RESERVED)
D2 = ENRTC
0 = Real time clock interrupt disabled
1 = Real time clock interrupt enabled
D3 = ENIOBUSINT
0 = External IQ Bus interrupt disabled
1 = External IO Bus interrupt enabled
Da = ENXMITINT
0 = RS232 Xmit Holding Reg. empty int.
disabled
1 = RS232 Xmit Holding Reg. empty int.
enabled
D5 = ENRECINT
0 = RS232 Rec. Data Reg. full int. disabled
1 = RS232 Rec. Data Reg. full int. enabled
Ds = ENERRORINT
0 = RS232 UART Error interrupts disabled
1 = RS8232 UART Error interrupts enabled
D7 = (RESERVED)
Name: RDINTSTATUS *
Port Address: EO— E3
Access: READ ONLY
Description: Input INT Status
Do—D1 = (RESERVED)
D2 = RTC INT
D3 = IOBUS INT
D4 = RS232 XMIT INT
D5 = RS232 REC INT
D6 = RS232 UART ERROR INT
D7 = (RESERVED)
Name: BOOT *
Port Address: 9C— 9F
Access: WRITE ONLY
Description: Enable or Disable Boot ROM
DO = ROM”
0 = Boot ROM Disabled
1 = Boot ROM Enabled
01—07 = (RESERVED)
Name: SEN"
Port Address: 90 — 93
Âccess: WRITE ONLY
Description: Sound output
DO = SOUND DATA
D1—D7 = (RESERVED)
Name:
ОРНЕС *
Port Address: 84
Access:
WRITE ONLY
Description: Output to operation reg.
DO
D1
D2
D3
D4
D5
D6
D7
SEL1
= — ©
= SELO
= SEL1
SELO MODE
0 0
1 1
0 2
1 3
= 8064
0 = 64 character mode
1 = 80 character mode
= INVERSE
0 = Inverse video disabled
1 = Inverse video enabled
= SRCPAGE — Points to the page to be mapped
as new page
Q = U64K, L32K Page
1 = U64K, U32K Page
ENPAGE — Enables mapping of new page
0 = Page mapping disabled
1 = Page mapping enabled
||
|
DESPAGE — Points to the page where new
page is to be mapped;
0 = L64K, U32K Page
1 = L64K, L32K Page
PAGE
0 = Page 0 of Video Memory
1 = Page 1 of Video Memory
111
5.2.8 Video Circuit
The heart of the video display circuit in the Model 4P is the
68045 Cathode Ray Tube Controller (CRTC), U42. The CRTC
is a preprogrammed video controller that provides two screen
formats: 64 by 16 and 80 by 24. The format is controlled by pin
3 of the CRTC (8064*). The CRTC generates ail of the neces-
sary signals required for the video display, These signals are
VSYNC {Vertical Sync}, HSYNC (Horizontal Sync) for proper
sync of the monitor, DISPEN (Display Enable) which indicates
when video data should be output to the monitor, the refresh
memory addresses (MAO-MA13) which addresses the video
RAM, and the row addresses (RAO-RA4) which indicates which
scan line row is being displayed. The CRTC also provides hard-
ware scrolling by writing to the internal Memory Start Address
Register by OUTing to Port 88H. The internal cursor control of
the 68045 is not used in the Model 4P video circuit.
Since the 80 by 24 screen requires 1,920 screen memory lo-
cations, a 2K by 8 static RAM (U82) is used for the video RAM.
Addressing to the video RAM (U82) is provided by the 68045
when refreshing the screen and by the CPU when updating of
the data is performed. These two sets of address lines are mul-
tiplexed by three 74LS157s (U41, U61, and U81). The multi-
plexers are switched by CRTCLK which allows the CRTC to
address the video RAM during the high state of CRTCLK and
the CPU access during the low state. A10 from the CPU is con-
trolled by PAGE* which allows two display pages in the 64 by
16 format. When updates to the video RAM are performed by
the CPU, the CPU is held in a WAIT state until the CRTC is not
addressing the video RAM. This operation allows reads and
writes to video RAM without causing hashing on the screen.
The circuit that performs this function is a 74LS244 buffer
(U84), an 8 bit transparent latch, 74L5373 (U83) and a Delay
line circuit shared with Dynamic RAM timing circuit consisting
of a 74LS74 (U98), 74LS32 (U96), 74L504 (U95), 74L500
(U92), 74LS02 (U69), and Delay Line (U94). During a CPU
Read Access to the Video RAM, the address is decoded by the
GA 4.2 and asserts VIDEO* low. This is inverted by USS (1/6 of
74LS04) which pulls one input of U92 (1/4 of 74L500) and in
turn asserts VWAIT * low to the CPU, RD is high at this time and
is latched into U98 (1/2 of 74LS74) on the rising edge of
XADR7*, inverse of CRTCLK.
112
When RD is latched by U98, the Q output goes low releasing
WAIT* from the CPU. The same signal also is sent to the Delay
Line (U94) through U117 (1/4 of 7408). The Delay line delays
the falling edge 240 ns for VLATCH* which latches the read
data from the vídeo RAM at U83. The data is latched so the
CRTC can refresh the next address location and prevent any
hashing. MRD* decoded by U106 and a memory read is ORed
with VIDEO* which enables the data from U83 to the data bus.
The CPU then reads the data and completes the cycle. A CPU
write is slightly more complex in operation. As in the RD cycle,
VIDEO" is asserted iow which asserts VWAIT” low ta the CPU.
WR is high at this time which is NANDed with VIDEO and
synced with CRTCLK to create VRAMDIS that disables the
video RAM output. On the rising edge of XADR7”, WR is
latched into U98 (1/2 of 74LS74) which releases VWAIT” and
starts cycle through the Delay Line. After 30ns DLYVWR” (De-
layed video write) is asserted low which also asserts VBUFEN"
(Video Buffer Enable) low. VBUFEN" enabled data from the
Data bus to the video RAM. Approximately 120ns later
DLYVWR* is negated high which writes the data to the video
RAM and negates VBUFEN* turning off buffer. The CPU then
completes WR cycle to the video RAM. Refer to Video RAM
CPU Access Timing Figure 5-12 for timing of above RD or WR
cycles.
During screen refresh, CRTCLK is high allowing the CRTC
to address Video RAM. The data out of the video RAM is
latched by LOAD” into Gate Array 4.3 (U102). INVERSE"
determines if character should be alpha-numeric only (IN-
VERSE* high) or unchanged (INVERSE™ low). A9 Is de-
coded with ENALTSET (Enable Alternate Set) and 7, which
controls the alternate set in the character generator ROM.
See ENALTSET Control Table below.
ENALTSET
0
Q7
bay
ATOAD UE
EEN
y HIOLVIA
+ NAANGA
+ UMAATO
SITWHVHA
x LIVMA
87860
OTOIA
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y LIX
HTOLHO
UM
ad
OH AW
STY-ÿY
x H'IOJ
WAZ
FIGURE 5-29. Video RAM CPU Access Timing
113
RAO-RA3, row addresses from the CRTC are used to control
which scan line is being displayed. The Model 4P has a 4-bit full
adder 74.5283 (U101) to modify the Row address. During a
character display DLYGRAPHIC* is high which applies a high to
all 4 bits to be added to row address. This will result in subtract-
ing one from Row address count and allow all characters to be
displayed one scan line lower. The purpose is so inverse char-
acters will appear within the inverse block. When a graphic
block is displayed DLY GRAPHIC" is low which causes the row
address to be unmodified. Moving jumper from E14-E15 to
E15-E16 will disable this circuit.
DLYCHAR* and DLYGRAPHICS are inverse signais and control
which data is to be loaded into the internal shift register of U102.
When DLYCHAR* is low and DLY GRAPHIC* is high, the Char-
acter Generator ROM (U103) is enabled to output data. When
DLYCHAR* is high and DLY GRAPHIC” is low the graphics char-
acters are internally buffered to the shift register. The data is
loaded into the internal shift register on the rising edge of
SHIFT* when LOADS* is low. Serial video data is output
U102.19. The video information is inverted by U142 and F83, is
filtered by R14 (47 ohm resistor), and C227 (100 pf Cap) and
output to video monitor. VSYNC and HSYNC are buffered by (17
2 of 74LS86) U143 and are also output to video monitor. Refer
to Video Circuit Timing Figure 5-30 and Inverse Video Timing
Figure 5-19 for timing relationships of Video Circuit.
5.2.9 Keyboard
The keyboard interface of the Model 4P consists of open col-
lector drivers which drive an 8 by 8 key matrix keyboard and an
inverting buffer which buffers the key or keys pressed on the
data bus. The open collector drivers (U57 and U77 (7416) are
driven by address lines AQ-A7 which drive the column lines of
the keyboard matrix. The ROW lines of the keyboard are pulled
up by a 1.5 kohm resistor pack RP2. The ROW lines are Бий-
ered and inverted onto the data bus by U78 (74LS240) which is
enabled when KEYBD* is a logic low. KEYBD" is a memory
mapped decode of addresses 3800-3BFF in Model III Mode
and F400-F7FF in Model 4/4P mode. Refer to the Memory Map
under Address Decode for more information. During real time
operation, the CPU will scan the keyboard periodically to check
if any keys are pressed. If no key is pressed, the resistor pack
RP2 keeps the inputs of U78 at a logic high. U78 inverts the
data to a logic low and buffers it to the data bus which is read
by the CPU. If a key is pressed when the CPU scans the correct
column line, the key pressed will pull the corresponding row to
a logic low. U78 inverts the signal to a logic high which is read
by the CPU.
114
5.2.10 Real Time Clock
The Real Time Clock circuit in the Model 4P provides a 30 Hz
(in the 2 MHz CPU mode) or 60 Hz (in the 4 MHz CPU mode)
interrupt to the CPU. By counting the number of interrupts that
have occurred, the CPU can keep track of the time. The 60 Hz
vertical sync signal (VSYNC) from the video circuitry is used for
the Real Time Clock's reference. In the 2 MHz mode, FAST is
a logic low which sets the Preset input, pin 4 of U23 (74L574),
to a logic high. This allows the 60 Hz (VSYNC) to be divided by
2 to 30 Hz. The output of 1/2 of U23 is ORed with the original
60 Hz and then clocks another 74LS74 (1/2 of U23). It the real
time clock is enabled (ENRTC at a logic high), the interrupt is
latched and pulls the INT* line low to the CPU. When the CPU
recognizes the interrupt, the pulse is counted and the latch re-
set by pulling RTCIN* low. In the 4 MHz mode, FAST is a logic
high which keeps the first half of U23 in a preset state (the Q”
output at a logic low). The 60 Hz is used to clock the interrupts.
NOTE: If interrupts are disabled, the accuracy of the real
time clock will suffer.
5.2.11 Line Printer Port
The Line Printer Port Interface consists of a pulse generator, an
eight-bit latch, and a status line buffer. The status of the line
printer is read by the CPU by enabling buffer U3 (74L5244).
This buffer is enabled by LPRD* which is a memory map and
port map decode. In Model Ill mode, only the status can be read
from memory location 37E8 or 37E9. The status can be read in
all modes by an input from ports F8-FB. For a listing of the bit
status, refer to Port Map section.
After the printer driver software determines that the printer is
ready for printing (by reading the correct status}, the characters
to be printed are output to Port F8-FB. U2, a 74.5374 eight-bit
latch, latches the character byte and outputs to the line printer.
One-half of U1 (74LS123), a one-shot, is then triggered which
generates an appropriate strobe signal to the printer which sig-
nifies a valid character is ready. The output of the one-shot is
buffered by 1/6th of the U51 (74L504) to prevent noise from the
printer cable from false-triggering the one-shot.
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Figure 5-30. Video C
115
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Figure 5-31. Video Blanking Timing
116
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Figure 5-32. Inverse V
117
5.2.12 Graphics Port
The Graphics Port (J7) on the Model 4P is provided to attach
the optional Graphics Board. The port provides DO-D7 (Data
Lines), AO-A3 (Address Lines), IN*, GEN" and RESET" for the
necessary interface signals for the Graphics Board. GEN" is
generated by negative ORing Port selects GSELO” (8C-8FH)
and GSELI" (80-83H) together by (1/4 of 74L508) U4. The re-
sulting signa! is negative ANDed with IORQ* by (1/4 о! 74532)
U24. Seven timing signals are provided to allow synchroniza-
tion of Main Logic Board Video and Graphics Board Video.
These timing signals are VSYNC, HSYNC, DISPEN, DCLK, H,
|, and J. Three control signals from the Graphics Board are
used to sync to CPU access and select different video modes.
WAIT* controls the CPU access by causing the CPU to WAIT till
video is in retrace area before allowing any writes or reads to
Graphics Board RAM. ENGRAF is asserted when Graphics
video is displayed. ENGRAF also disables inverse video mode
on Main Logic Board Video. CL166* (Clear 74L166) is used to
enable or disable mixing of Main Logic Board Video and Graph-
ics Board Video. If CL166* is negated high, then mixing is al-
lowed in all for video modes 80 x 24, 40 x 24, 64 x 16, and 32 x
16. If CL166* is asserted low, this will clear the video shift reg-
ister U63, which allows no video from the Main Logic Board. In
this state 8064" is automatically asserted low to put screen in
80 x 24 video mode. Refer to Figure 5-16. Graphic Board Video
Timing for timing relationships. Refer to the Model 4/4P Graph-
ics Board Service information for service or technical informa-
tion on the Graphics Board.
5.2.13 Sound
The sound circuit in the Model 4P is compatible with the Sound
Board which was optional in the Model 4. Sound is generated
by alternately setting and clearing data bit DO during an OUT to
port 90H. The state of DO is latched by U129 (1/2 ot a 74LS74)
and the output is amplified by Q2 which drives a 8{} speaker.
The speed of the software loop determines the frequency, and
thus, the pitch of the resulting tone. Since the Mode! 4P does
not have a cassette circuit, some existing software that used
the cassette output for sound would have been lost. The Model
4P routes the cassette latch to the sound board through U109.
When the CASSMOTORON signal is a logic low, the cassette
motor is off, then the cassette output is sent to the sound circuit.
5.2.14 I/O Bus Port
The Model 4P Bus is designed to allow easy and convenient in-
terfacing of I/O devices to the Model 4P. The 1/0 Bus supports
all the signals necessary to implement a device compatible with
the Z80s I/O structure.
118
Addresses:
AO to A7 allow selection of up to 256" input and 256 output
devices if external 1/0 is enabled.
*Ports 80H to OFFH are reserved for System use.
Data:
DBO to DB7 allow transfer of 8-bit data onto the processor
data bus is external I/Q is enabled.
Control Lines:
1. M1* — Z80A signal specifying an M1 or Operation Code
Fetch Cycle or with IOREQ", it specifies an Interrupt
acknowledge.
2. IN* — Z80A signal specifying than an input is in progress.
Logic AND ot IOREQ* and WR”.
3. OUT* — ZBOA signal specifying that an output is in prog-
ress. Logic AND of IOREQ* and WR”.
4. IOREQ* — Z80A signal specitying that an input or output
is in progress or with M1”, it specifies an interrupt
acknowledge.
5. RESET* — system reset signal.
6. IOBUSINT* —inputto the CPU signaling an interrupt from
an 1/0 Bus device if VO Bus interrupts are enabled.
7. IOBUSWAIT* —input to the CPU wait line allowing I/O Bus
device to force wait states on the Z80 if external МО is
enabled.
8. EXTIOSEL" — input to /O Bus Port circuit which switches
the 1/O Bus data bus transceiver and allows and INPUT in-
struction to read 1/O Bus data.
The address line, data line, and all control lines except RESET"
are enabled only when the ENEXIO bit in port EC is set to one.
To enable I/O interrupts, the ENIOBUSINT bit in the PORT EQ
(output port) must be a one. However, even if itis disabled from
generating interrupts, the status of the IOBUSINT" line can still
read-on the appropriate bit of CPU IOPORT EQ (input port).
See Model 4P Port Bit assignments for port OFF, OEC, and OEO.
J J U J UJ UJ UT UOT TJ TT Lao
JS US Г Г Г Г Г Г Гог Го
EX Y TULL xXx x
В° Е ТО
/ ‚A 99172
‚A 7 IVANA
Figure 5-33. Graphic Board Video Timing
119
The Model 4P CPU board is fully protected from “foreign МО de-
vices” in that all the ИО Bus signals are buffered and can be dis-
abled under software control. To attach and use and I/O device
on the 1/O Bus, certain requirements (both hardware and soft-
ware) must be met.
For input port device use, you must enable external I/O devices
by writing to port OECH with bit 4 on in the user software. This
will enable the data bus address lines and control signals to the
I/O Bus edge connector. When the input device is selected, the
hardware should acknowledge by asserting EXTIOSEL” low.
This switches the data bus transceiver and allows the CPU to
read the contents of the 1/0 Bus data lines. See Figure 5-17 for
the timing. EXTIOSEL* can be generated by NANDing IN and
the VO port address.
Output port device use is the same as the input port device in
use, in that the external 1/O devices must be enabled by writing
to port OECH with bit 4 on in the user software — in the same
fashion.
For either input or output devices, the IOBUSWAIT" control line
can be used in the normal way for synchronizing slow devices
to the CPU. Note that since dynamic memories are used in the
Model 4P, the wait line should be used with caution. Holding the
CPU in a wait state for 2 msec or more may cause loss of mem-
ory contents since refresh is inhibited during this time. It is rec-
ommended that the IOBUSWAIT* line be held active no more
than 500 psec with a 25% duty cycle.
The Model 4P will support Z80 Mode 1 interrupts. A RAM jump
table is supported by the LEVEL I| BASIC ROMs image and the
user must supply the address of his interrupt service routine by
writing this address to locations 403E and 403F. When an in-
terrupt occurs, the program will be vectored to the user-sup-
plied address if I/O Bus interrupts have been enabled. To
enable I/O Bus interrupts, the user must set bit 3 of Port OEOH.
5.2.15 FDC Circuit
The TRS-80 Model 4P Floppy Disk Interface provices a stan-
dard 5-1/4” floppy disk controller. The Floppy Disk Interface
supports both single and double density encoding schemes.
Write precompensation can be software enabled or disabled
beginning at any track, although the system software enables
write precompensation for all tracks greater than twenty-one.
The amount of write precompensation is 125 nsec and is not
adjustable. One or two drives may be controlled by the inter-
face. All data transfers are accomplished by CPU data re-
quests. In double density operation, data transfers are
synchronized to the CPU by forcing a wait to the CPU and clear-
ing the wait by a data request from the FDC chip. The end of the
data transfer is indicated by generation of a non-maskable in-
terrupt from the interrupt request output of the FDC chip. A
hardware watchdog timer insures that any error condition will
not hang the wait line to the CPU for a period long enough to
destroy RAM contents.
120
Input or Output Cycles.
T2
T4
IA XX EX EX ETE
AD- A?
ORO"
RD"
DATA BUS
WAIT*
WAR"
PORT ADDRESS
\
A_
DATA BLS
“inserted by Z80 CPU
Input or Qutput Cycles with Wait States.
АВ. А?
IORG"
DATA BUS
RD*
WAIT"
DATA BUS
WA *
+EXTIOSEL*
READ
CYCLE
{ IN Y
И
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PORT ADDRESS Y
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dr A — em | — —_— dr —— — tte — — — ——1 _— —. —
LIN UL НИ
——< OUT \
ve WRITE
CYCLE
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“Inserted by Z80 CPU
tCoincident with IORQ* only on INPUT cycle.
Figure 5-34. 1/O Bus Timing Diagram
121
Control and Data Buffering
The Floppy Disk Controller Board is an I/O port-mapped device
which utilizes ports E4H, FOH, F1H, F2H, F3H, and F4H. The
decoding logic is implemented on the CPU board. (Refer to Par-
agraph 5.1.5 Address Decoding for more information on Port
Map). U70 is a bi-directional, 8-bit transceiver used to buffer
data to and from the FDC and RS-232 circuits. The direction of
data transfer is controlled by the combination of control signals
DISKIN*, RS232IN*, ADINT*, and RDNMI*. If any of these sig-
nals is active (logic low), U70 is enabled to drive data onto the
CPU data bus. If both signals are inactive (logic high), U70 is
enabled to receive data from the CPU board data bus. A sec-
ond buffer (U36) is used to buffer the FDC chip data to the FDC/
RS232 Data Bus, (BD0-BD7), U36 is enabled all the time and
its direction controlled by DISKIN*. Again, if DISKIN" is active
{logic low), data is enabled to drive from the FDC chip to the
Main Data Busses. If DISKIN" is inactive (logic high), data is en-
abled to be transferred to the FDC chip.
Nonmaskable Interrupt Logic
Gate Array 4.4 (U18) is used to latch data bits D6 and D7 on the
rising edge of the control signal WANMF. This enables the con-
ditions which will generate a non-maskable interrupt to the
CPU. The NMI interrupt conditions which are programmed by
doing an OUT instruction to port E4H with the appropriate bits
set. If data bit 7 is set, an FDC interrupt is enabled to generate
an NMI interrupt. If data bit 7 is reset, interrupt requests request
from the FDC are disabled. If data bit 6 is set, a Motor Time Out
is enabled to generate an NMI interrupt. If data bit 6 is reset, in-
terrupts on Motor Time Out are disabled. An IN instruction from
port E4H enables the CPU to determine the source of the non-
maskable interrupt. Data bit 7 indicates the status of FDC in-
terrupt request (INTRQ) (0 = true, 1 = false). Data bit 6 indicates
the status of Motor Time Out (0 = true, 1 = false). Data bit 5 in-
dicates the status of the Reset signal (0 =true, 1 =false). The
control signal RDNMI* gates this status onto the CPU data bus
when active (logic low).
Drive Select Latch and Motor ON Logic
Selecting a drive prior to disk I/O operation is accomplished by
doing an OUT instruction to port F4H with the proper bit set. The
following table describes the bit allocation of the Drive Select
Latch:
Data Bit Function
DO Selects Drive 0 when set”
D1 Selects Drive 1 when set”
D2 Selects Drive 2 when set”
D3 Selects Drive 3 when set”
D4 Selects Side 0 when reset
Selects Side 1 when set
D5 Write precompensation enabled when set,
disabled when reset
D6 Generates WAIT if set
D7 Selects MFM mode if set
Selects FM mode if reset
*Only one of these bits should be set per output
Hex D flip-flop U54 (74L174) latches the drive select bits, side
select and FM*/MFM bits on the rising edge of the control signal
DAVSEL”. Gate Array 4.4 (U18) is used to latch the Wait Ena-
ble and Write precompensation enable bits on the rising edge
of DRVSEL*. The rising edge of DRVSEL” also triggers a one-
shot (1/2 of U54, 74LS123) which produces a Motor On to the
disk drives. The duration of the Motor On signal is approxi-
mately three seconds. The spindle motors are not designed for
continuous operation. Therefore, the inactive state of the Motor
On signal is used to clear the Drive Select Latch, which de-se-
lects any drives which were previously selected. The Motor On
one-shot is retriggerable by simply executing another OUT in-
struction to the Drive Select Latch.
Wait State Generation and WAITIMOUT Logic
As previously mentioned, a wait state to the CPU can be initi-
ated by an OUT to the Drive Select Latch with D6 set. Pin 18 of
U18 will go high after this operation. This signal is inverted by
1/4th of U15 and is routed to the CPU where it forces the Z80A
into a wait state. The Z80A will remain in the wait state as long
as WAIT* is low. Once initiated, the WAIT* will remain low until
one of five conditions is satisfied. If INTRQ, DRQ, and RESET,
inputs become active (logic high), it causes WAIT” to go high
which allows the Z80 to exit the wait state. An internal timer in
U18 serves as a watchdog timer to insure that a wait condition
will not persist long enough to destroy dynamic RAM contents.
This internal watchdog timer logic will limit the duration of a wait
to 1024 usec, even if the FDC chip should fail to generate a
DRQ or an INTRQ.
If an QUT to Drive Select Latch is initiated with D6 reset (logic
low), a WAIT is still generated. The internal timer in U18 will
count to 2 which will clear the WAIT state. This allows the WAIT
to occur only during the OUT instruction to prevent violating any
Dynamic RAM parameters.
NOTE: This automatic WAIT will cause a .5-1 psec wait each
time an out to Drive Select Latch is performed.
Clock Generation Logic
A 16 MHz crystal oscillator and a Gate Array 4.4 (U18) are used
to generate the clock signals required by the FDC board. The 6
MHz oscillator is implemented internal to U18 and a quartz
crystal (Y2). The output of the oscillator is divided by 2 to gen-
erate an 8 MHz clock. This is used by the FDC 1773 for all in-
ternal timing and data separation. U18 further divides the 16
MHz clock to drive the watchdog timer circuit.
Disk Bus Output Drivers
High current open collector drivers U15 and U34 are used to
buffer the output signals from the FDC circuit to the disk drives.
Write Precompensation and Write Data Pulse Shap-
ing Logic
Ali Write Precompensation is generated internal to the FDC
chip 1773 (U17). Write Precompensation is enabled when
W6 goes high and Write Precompensation is enabled from
software. This signal is multiplexed with RDY by W6 is fed
into pin 20 of U17. Write Data is output pin 22 of U17 and is
shaped by a one-shot (1/2 of U56) which stretches the data
pulses to approximately 500 nsec.
123
Floppy Disk Controller Chip
The 1773 is an MOS LSI device which performs the functions
of a floppy disk formatter/controller in a single chip implemen-
tation. The following port addresses are assigned to the internal
registers of the 1773 FDC chip:
Port No. Function
FOH Command/Status Register
F1H Track Register
F2H Sector Register
F3H Data Register
5.2.16 RS-232-C Circuit
RS-232C Technical Description
The RS-232C circuit for the Model 4P computer supports
asynchronous serial transmissions and conforms to the ElA
RS-232C standards at the input-output interface connector
(J4), The heart of the circuit is the TR1865 Asynchronous
Receiver/Transmitter U33. It performs the job of converting
the parallel byte data from the CPU to a serial data stream
including start, stop, and parity bits. For a more detailed de-
scription of how this LSI circuit performs these functions, re-
fer to the TR1865 data sheets and application notes. The
transmit and receive clock rates that the TR1865 needs are
supplied by the Baud Rate Generator U73 (BR1943). This
circuit takes the 5.0688 MHz supplied by the system timing
circuit and the programmed information received from the
CPU over the data bus and divides the basic clock rate to
provide two clocks. The rates available from the BRG go
from 50 Baud to 19200 Baud. See the BRG table for the
complete list.
124
BRG Programming Table
Transmit/
Receive Supported
Nibble Baud 16X by
Loaded Rate Clock SETCOM
OH 50 0.8 kHz Yes
1H 75 1.2 kHz Yes
2H 110 1.76 kHz Yes
3H 134.5 2.1523 kHz Yes
4H 150 2.4 kHz Yes
5H 300 4.8 kHz Yes
6H 600 9.6 kHz Yes
7H 1200 19.2 kHz Yes
8H 1800 28.8 kHz Yes
9H 2000 32.081 kHz Yes
AH 2400 38.4 kHz Yes
BH 3600 57.6 kHz Yes
CH 4800 76.8 kHz Yes
DH 7200 115.2 kHz Yes
EH 9600 153.6 kHz Yes
FH 19200 307.2 kHz Yes
The RS-232C circuit is port mapped and the ports used are E8
to EB. Following is a description of each port on both input and
output.
Port Input Output
ЕВ Modem status Master Reset, enables UART
control register load
EA UART status UART control register load and
modem control
E9 Not Used Baud rate register load enable
bit
EB Receiver Holding Transmitter Holding
register register
Interrupts are supported in the RS-232C circuit by the Interrupt
mask register and the Status register internal to GA 4.5 (U31)
which allow the CPU to see which kind of interrupt has oc-
curred. Interrupts can be generated on receiver data register
full, transmitter register empty, and any one of the errors — par-
ity, framing, or data overrun. This allows a minimum of CPU
overhead in transferring data to or from the UART. The interrupt
mask register is port EQ (write) and the interrupt status register
is port EO (read). Refer to the IO Port description for a full break-
down of all interrupts and their bit positions.
All Model |, lll, and 4 software written for the RS-232-C interface
is compatible with the Model 4P RS-232-C circuit, provided the
software does not use the sense switches to configure the in-
terface. The programmer can get around this problem by di-
rectly programming the BRG and UART for the desired
configuration or by using the SETCOM command of the disk
operating system to configure the interface. The TRS-80 RS-
232C Interface hardware manual has a good discussion of the
RS-232C standard and specific programming examples (Cat-
alog Number 26-1145).
Pinout Listing
The following list is a pinout description of the DB-25 connector
(P1).
Pin No. Signal
1 PGND (Protective Ground)
TD (Transmit Data)
RD {Receive Data)
RTS (Request to Send)
CTS (Clear To Send)
DSR (Data Set Ready)
SGND (Signal Ground)
CD (Carrier Detect)
SATS (Spare Request to Send)
DTR (Data Terminal Ready)
RI (Ring Indicate)
> Co o O сл + WR
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125
5.2.17 CPU Board Troubleshooting Guide
This section is a general guide for service personnel to check
out and troubleshoot the Model 4P Main Logic CPU Board. Pro-
cedures in section 4 Troubleshooting should be followed before
proceeding to following steps. This guide will provide step by
step procedures to help isolate the faulty area on the CPU
board. Knowledge of each area of the CPU board is necessary
to determine exact component failure. Refer of CPU Board
Schematics and Theory of Operation during troubleshooting for
specific check points and testing.
1. No video messages are displayed and correct data does
not appear at video output connector J9.
If above condition exists, go to 2; if video okay, but Model
4P does not boot properly, go to 10.
If video and boot-up is okay, go to 15.
2. Check for video timing signal DCLK from Gate Array 4.1
(U148) in 64 x 16 and 80 x 24.
If okay, go to 3; if one or both modes bad, goto 7.
3. Check for proper timing signals output from U148 (SHIFT",
XADR7*, CRTCLK, POT", LOAD*, LOADS").
If okay, then go to 4; if one or more bad, replace U148 or
U128.
4. Check it 68046 U42 is working properly and has correct in-
put signals.
If all okay, then go to 5. If bad, replace U42 or check for in-
put signals where they originate.
5. Check for timing and proper signals U102.
If bad, replace as necessary; if okay, go to 6.
6. Check output of pin 4 of U142 and repair as necessary.
7. Check for 20M clock at pin 2 of U148.
If okay, go to 8; if bad, replace Y1 or U148.
8. Check for outputs of U148 (PCLK, RS232CLK).
If okay, then go to 9; if any bad, replace U148.
9. Check for 12M at output of U146 pin 8.
If okay, then video should work; if bad, replace 146.
10. Run Memory Test in Boot ROM by holding down period (.)
and toggling Reset.
if memory checks okay, then go to 11; if not, check mem-
ory circuit and/or replace RAM chips.
11. Check Clock circuit of Floppy Disk Controller.
If 16MHz and 8 MHz okay, go to 12; if bad, repair or replace
necessary components.
12. Check for all incoming signals to the FDC chip U17.
if any bad, repair as necessary; if okay, go to 13.
13.
14.
15.
Check all handshaking signals to FDC chip from CPU.
If okay, go to 14; if bad, repair as necessary.
Check Data Bus and control lines.
If okay, then problem still exists in Floppy Disk Circuit or
Floppy Disk Drive. Refer to each section accordingly. If
bad, replace as necessary.
If unit boots okay, then boot Mode! 4P Diagnostics Diskette
and execute each diagnostic to isolate any minor problems
on CPU Board.
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+5v
FLOPPY DISK CONTROLLER LOGIC
SCALE JSHEET OF
N/A
33
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RS232INX
RS2320UT*
NN DW
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U73
BRI943
1
133
RS232C LOGIC
JA
RS232C
(0825)
. REV.
8000233
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136
Parts List
Model 4P Gate Array PC Board
Sym Description Part Number
Cl-6 Capacitor .1 mfd 50V Mono Axial 8374104
C9-18 Capacitor .1 mfd 50V Mono Axial 8374104
С22-24 Capacitor .1 mfd 50V Mono Axial 8374104
C27-31 Capacitor .1 mfd 50V Mono Axial 8374104
C33 Capacitor .l1 mfd 50Y Mono Axial 8374104
C34 Capacitor .l1 mfd 50V Mono Axial 8374104
C36 Capacitor .l1 mfd 50V Mono Axial 8374104
C41 Capacitor .1 mfd 50V Mono Axial 8374104
C42 Capacitor .1 mfd 50V Mono Axial 8374104
C45 Capacitor .1 mfd 50V Mono Axial 8374104
C50 Capacitor .1 mfd 50V Mono Axial 8374104
C55-57 Capacitor .1 mfd 50V Mono Axial 8374104
Cel Capacitor .1 mfd 50V Mono Axial 8374104
C67 Capacitor .l mfd 50V Mono Axial 8374104
C69 Capacitor .1 mfd 50V Mono Axial 8374104
C70 Capacitor .l1 mfd 50V Mono Axial 8374104
C72 Capacitor .1 mfd 50V Mono Axial 8374104
C73 Capacitor .1 mfd 50V Mono Axial 8374104
C77 Capacitor .1 mfd 50V Mono Axial 8374104
C78 Capacitor .l1 mfd 50V Mono Axial 8374104
C81-89 Capacitor .1 mfd 50V Mono Axial 8374104
Col Capacitor .1 mfd 50V Mono Axial 8374104
C92 Capacitor .1 mfd 50V Mono Axial 8374104
C94-96 Capacitor .l1 mfd 50V Mono Axial 8374104
C98 Capacitor .1 mfd 50V Mono Axial 8374104
C101-106 Capacitor .1 mfd 50V Mono Axial 8374104
C108-111 Capacitor .1 mfd 50V Mono Axial 8374104
C114-118 Capacitor .1 mfd 50V Mono Axial 8374104
cl121 Capacitor .1 mfd 50V Mono Axial 8374104
cl124 Capacitor .1 mfd 50V Mono Axial 8374104
C125 Capacitor .l mfd 50V Mono Axial 8374104
C129 Capacitor .1 mfd 50V Mono Axial 8374104
C133-140 Capacitor .1 míd 50V Mono Axial 8374104
Cl42 Capacitor .l1 mfd 50V Mono Axial 8374104
C143 Capacitor .1 mfd 50V Mono Axial 8374104
C146 Capacitor .1 mfd 50V Mono Axial 8374104
C148 Capacitor ,1 mfd 50V Mono Axial 8374104
C153-160 Capacitor .1 mfd 50V Mono Axial 8374104
C201-211 Capacitor 22 mfd 16V Elec. Rad 8326221
C212 Capacitor 1000 pfd 50V C. Disk Rad 8302104
C213 Capacitor .022 mfd 50V C. Disk 8303224
C214 Capacitor .022 m£d 50V C. Disk 8303224
C215 Capacitor 10 mfd 16V Elec. Rad 8326101
C216 Capacitor 33 pfd 50V C. Disk Npo Ax 8300334
C217, Capacitor 22 pfd 50vV С. Disk МРО Ах 8300224
C218 Capacitor .l1 mfd 50V Mono Axial 8374104
C219 Capacitor 200 pfd 50V C. Disk Z5U 8301223
Rad
C220 Capacitor 22 pfd 50V C. Disk NPO Ax 8300224
137
Parts List
Model A4P Gate Array PC Board
— -E BA SEEN р o wl Sy —
чин ————— A o m li EEE
Description
Capacitor 22 pfd 50vV C. Disk NPO Ax
Capacitor 100 pfd 50vV C. Disk AX
Capacitor 100 pfd 50V C. Disk Ax
Capacitor .1 mfd 50V Mono Axial
Capacitor 100 pfd 50V C. Disk Ax
Capacitor 100 pfd 50V C. Disk Ax
Capacitor .1 mfd 50V Mono Axial
Diode 1N4148
Staking Pins
J10
Ql
RI
R2
R3-5
R6
R8
R9
R10
R11
R12
R13
R14
R15-17
R18
R19
R20
R21-23
R24
R25
R26
R27
R28
R29
R30
Ferrite B
Connector
Connector
Header
Connector
Header
Connector, 34-Pin (Graphics) Header
Connector
Connector
Connector
— —[ a — —— — _——— —]Ñ— ¿Ll E MN — —] — ———;—;——] — A mm PTR [—] ——_——— o Ño—— —
— —— — — — ALE LE ETRY SER re—
ead
‚ 25-Pin (RS232) DB25
, 34-Pin (Floppy Disk)
, Dual 8 (Keyboard)
Rt. Angle
, 3-Pin (Reset) Header
, 6-Pin (Video) Header
, 4-Pin (Power) Header
Transistor 2N3906
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
20 kohm 1/4W 5%
160 kohm 1/4W 5%
4.7 kohm 1/4W 5%
4.7 Meg ohm 1/4W 5%
4.7 kohm 1/4W 5%
22 ohm 1/4W 5%
47 ohm 1/4W 5%
56 ohm 1/4W 5%
4.7 kohm 1/4W 5%
27 ohm 1/4W 5%
47 ohm 1/4W 5%
150 ohm 1/4W 5%
3.6 kohm 1/4W 5%
22 ohm 1/2W 5%
4.7 kohm 1/4W 5%
27 ohm 1/4W 5%
2.2 kohm 1/4W 5%
100 kohm 1/4W 5%
750 ohm 1/4W 5%
4.7 kohm 1/4W 5%
10 kohm 1/4W 5%
10 kohm 1/4W 5%
150 ohm 1/4W 5%
138
il EEE rw ie lee EEE НЫ bl PUN PEN = === НН
= === == LE — las a A a A o O
8300224
8301104
8301104
8374104
8301104
8301104
8374104
8150148
8529014
8419014
8519109
8519120
8519184
8519120
8519215
8519211
8519210
8100906
8207320
8207416
8207247
8207457
8207247
8207022
8207047
8207056
8207247
8207027
8207047
8207115
8207236
8217022
8207247
8207027
8207222
8207410
8207175
8207247
8207310
8207310
8207115
Parts List
—— TE A ЧЕН НН ты ину ЧЕН НЫ МНН EE — —
Sym Description Part Number
RP1 Resistor Pak 27 ohm DIP 16-Pin 8290027
RP2 Resistor Pak 1.5 kohm SIP l0-Pin 8230015
RP4 Resistor Pak 150 ohm SIP l0-Pin 8290013
Sl Speaker 8 ohm 8490008
Ul IC 7415123 Multivibrator 8020123
U2 IC 7415374 Flip Flop 8020374
U3 IC 7415244 Octal Buffer 8020244
U4 IC 741,508 Quad 2-In AND 8020008
US IC 74L504 Hex Inverter 8020004
U6 IC 74L5245 Tranceiver 8020245
U9 IC 74LS244 Octal Buffer 8020244
010 IC 7415367 Hex Driver 8020367
Ull IC 1489 Receiver 8050189
Ul2 IC 1488 Driver 8050188
Ul3 IC 1489 Receiver 8050189
Ulá4 IC 7416 Hex Inverter 8000016
Ul15 IC 7416 Hex Inverter 8000016
Ul6 IC 74LS367 Hex Driver 8020367
Uul7 IC WD1773 8040773
Ul8 IC 4.4 Floppy Support Array 8040544
U22 ТС 741,502 2-1п NOR 8020002
023 IC 74LS74 Flip Flop 8020074
U24 IC 741532 Quad 2-In OR 8020032
027 IC 74LS244 Octal Buffer 8020244
028-30 IC 741.5138 Quad 2-In NAND 8020138
U3l IC 4.5 RS232C Support Array 8040545
U33 IC TR1865 UART 8040865
U34 IC 74LS174 Hex Flip-Flop 8020174
U36 IC 7415245 Tranceiver 8020245
U41 IC 74LS157 Multiplexer 8020157
U42 IC 68A045 CRTC 8040045
U45 IC Z80A CPU 8047880
U50 IC 74L521 Dual 4-In AND 8020021
U55 IC 74LS08 Quad 2-In AND 8020008
U56 IC 7415123 Multivibrator 8020123
U57 IC 7416 Hex Inverter 8000016
U61 IC 74LS157 Multiplexer 8020157
U67 IC 7415244 Octal Buffer | 8020244
U69 IC 68A332 4K X 8 300NS ROM 8075332
u70* IC 74LS245 Tranceiver 8020245
U72 IC 741L5244 Octal Buffer 8020244
U73 IC BR1943 Clock Gen. 8040943
U77 IC 7416 Hex Inverter 8000016
U78 IC 7415240 Octal Buffer 8020240
* NOTE: Starred (*) IC to be socketed
139
Parts List
Model 4P Gate Array PC Board
Part Number
Sym Description
U81 IC 74LS157 Multiplexer
U82 IC 4016 2K X 8 RAM Static 200NS
U83 IC 74LS373 Octal Latch
U84 IC 7415244 Octal Buffer
U85 IC 7415273 Octal Flip-Flop
U86* IC 74LS245 Tranceiver
U87 IC 74F04 Hex Inverter
u88 IC 7ALS11 Triple 3-In AND
U89 IC 741527 Triple 3-In NOR
U9l IC 74L504 Hex Inverter
U92 IC 74LS00 Quad 2-In NAND
U94 Delay Line
U95 IC 74LS04 Hex Inverter
U96 IC 741532 Quad 2-In OR
U98 IC 741574 Flip Flop
0101 ТС 7415283 В1пагу Adder
0102 IC 4.3 Video Support Array
Ul03 IC MCM68A316E Character ROM
Ulo4 IC 741504 Hex Inverter
0105 IC 741,532 Quad 2-In OR
0106 IC 4.2 Address Decode Array
U108 IC 74LS51 AND-OR Invert
U109 IC 74L502 2-In NOR
0110 IC 74LS157 Multiplexer
Ulll IC 74LS157 Multiplexer
Ull4 IC 74564 AND-OR-Invert
Ul15 IC 74532 Quad 2-In OR
U116 IC 745112 J-K Flip Flop
U117 IC 74F08 Quad 2-In AND
Ulls IC 74L5245 Tranceiver
Ul121 IC 741,514 Hex Inverter
Ul124 IC 741.8174 Hex Flip-Flop
Ul25 IC 74LS244 Octal Buffer
U129 IC 74LS74 Flip Flop
0133-1490 IC MCM6665 64K DRAM 200NS
0142 IC 741,502 2-In NOR
0146 IC PLL Multimodule
0148 IC 4.1 System Timing Array
* NOTE: Starred (*) IC to be socketed
140
8020157
8040116
8020373
8020244
8020273
8020245
8015004
8020011
8020027
8020004
8020000
8429020
8020004
8020032
8020074
8020283
8040543
8049007
8020004
8020032
8040542
8020051
8020002
8020157
8020157
8010064
8010032
8010112
8015008
8020245
8020014
8020174
8020244
8020074
8040665
8020002
8409036
8040541
Parts List
Model 4P Gate Array PC B
TE nL i — NL SEE i ———— НН UU
oard
Sym Description Part Number
U17 Socket 28-Pin DIP 8509007
Ul8, Socket 24-Pin DIP 8509001
U3l Socket 40-Pin DIP 8509002
U33 Socket 40-Pin DIP 8509002
U42 Socket 40-Pin DIP 8509002
U45 Socket 40-Pin DIP 8509002
U69, Socket 24-Pin DIP 8509001
U70 Socket 20-Pin DIP 8509009
U73 Socket 18-Pin DIP 8509006
082, Socket 24-Pin DIP 8509001
U86 Socket 20-Pin DIP 8509009
0102 Socket 40-Pin DIP 8509002
U1l03 Socket 24-Pin DIP 8509001
Ul06 Socket 40-Pin DIP 8509002
U133-140, Socket 16-Pin DIP 8509003
U148 Socket 24-Pin DIP 8509001
Ul53-160, Socket 16-Pin DIP 8509003
Yl Crystal 20.2752 MHz (2 Lead) 8409031
Y? Crystal 16 MHz Parallel Resonant 8409038
Low Cost Model 4P PC Board Sub 8858011
Assy.
Low Cost Model 4P Board Rev, "-" 8709524
141
5.3 MINI-DISK DRIVES
The Model 4P utilizes two 5-1/4” Flexible Disk Drive assem-
blies. These drives are internally mounted with Drive O at the
left and Drive 1 at the right when facing the CRT display. They
are compact, low profile drives that require only half the space
normally required. The drives use an ANSI-compatible, Indus-
try Standard, 5-1/4 inch diskette and contain 48 tracks per inch.
Two different types of drives are used in the Model 4P. One is
a double-sided recording device. Both are capable of reading
and writing in single-density format on a diskette. The drives
have double density capability when a Modified Frequency
Modulated (MFM) or other appropriate recording technique is
used. Encoding and decoding of the data is done by the user's
controller.
Service information and schematics for the Mini-Disk Drive are
contained in the Manufacturer's Operating and Service Manual
at the rear of this manual.
5.4 POWER SUPPLY ASSEMBLY
5.4.1 Power Supply
Basic Principle
A switching power supply circuit employs a high-speed semi-
conductor switch to control the storage and release of electrical
energy in an inductor and provide regulated DC output voltages
with a minimum loss of energy in heat-dissipating elements.
There are several schemes for achieving this result which differ
primarily in the arrangement of the basic circuit elements.
These elements include a switch, an inductor, a rectifier, a ca-
pacitor and a DC voltage source.
An arrangement well-suited for economical power supplies with
rated power outputs under 100 watts is the FLYBACK CON-
VERTER shown in Figure 5-35. The waveforms in Figure 5-36
are used to describe the operation of the Flyback Converter cir-
cuit. For the purpose of this discussion we will assume that the
duration of the “ON” time equals the duration of the “OFF” time
and Vo = rated output voltage.
L
nel D
® Isec e
— | |
> Vin E
-— . +
= С
Fa
Vsec Vo
Switch
| Е
Y 6
Figure 5-35. Basic Flyback Converter
143
a. Switch
—
time,microsec.
Timing
amps
&х Рам
lav
b. Isw o
volts
A
|
|
|
|
|
|
|
|
|
|
|
2xvin,pk + |
|
|
1
|
vin , DE =
vin ,avd
c. Vsw
2xVin,pk-
п
мо = Мал ‚ау |
ан
time,microsec.
time,microsec.
Tis
[ii
time,microsec.
—
me
Ta
time,microsec.
d. Vsec
amps |
A |
|
ах то ча |
|
|
|
|
|
|
Io+ |
\
e, Isec o
|
|
-“
— — EE = = == le JU EEE SEES EEE Wey em bell EEE
Figure 5-36.
When the switch is closed (ON) at time ta, Vin is impressed
across the primary winding of inductor L and the current Isw in-
creases linearly from zero until the switch opens (OFF) at time
tb. Note that Isec is zero while the switch is closed. This is be-
cause Vsec is negative with respect to Vo thus reverse-biasing
diode D. Note that Vsw is also zero while the switch is closed.
When the switch opens at time tb, the magnetic field of L in-
stantly collapses and reverses polarity. At this moment, Vsw is
equal to Vin plus the voltage across L just before the switch
opened (also equal to Vin). Therefore, at the instant the mag-
netic field reverses polarity, Vsw = 2Vin.
144
During the interval when the switch is open (tb to tc), the sec-
ondary voltage, Vsec, is a replica of the primary voltage Vsw.
Diode D is now forward biased due to the polarity of the inductor
windings and because the turns ratio, n, is such that:
Vsec x n > Vo
This biasing replenishes the charge in capacitor C that was de-
livered to the load R during the ta-tb interval. This is the “fly-
back” interval and is so named because the inductor releases
the energy stored in its magnetic field while the switch is OFF.
Several other facts are illustrated by the waveforms of Figure 5-
36. First, the voltage across the switch Vsw decays exponen-
tiaily from 2Vin to Vin during the “OFF” interval. This is because
the inductor and the switch timing are adjusted to transfer all of
the energy that was stored in the inductor while the switch was
ON, into the secondary while the switch is OFF. (Observe that
Isec DECREASES linearly with time to zero at the end of the
“OFF” time period.) This is known as resetting the core. Thus,
at time tc when the switch is ready to turn on again, the DC input
voltage Vin is again available to charge the inductor. Also at this
time, all currents in the inductor are zero.
Second, since we have assumed that Isw increases linearly
with time and that the ON and OFF time periods are equal (50%
duty cycle), the average current in the primary, Isw (av), is 1/4
the peak current Isw. Also, the average current in the second-
ary, which is equal to the load current lo, is 1/4 the peak current
in the secondary.
Third, the turns ratio is set by the ratio of the average primary
voltage (Vsw) over a full cycle at its lowest value to the maxi-
mum permissible output voltage, Vo. The lowest Vsw value oc-
curs at low AC line and maximum output load. In practice, the
actual turns ratio, the ratio of peak-to-average voltages and
currents, and the duty cycle may be adjusted to compensate for
circuit losses.
AC Line
fuse & EMI input DC
surge ‚ filter supply
limiting
|
|
|
y |
Fourth, notice the ringing or oscillation that appears on the peak
portion of Vsw and Vsec. This oscillation occurs at the resonant
frequency of the leakage inductance of the inductor L and the
parasitic capacitance of the circuit. The parasitic capacitance
includes the interwinding capacitance of the inductor and stray
capacitance of the switch. If this oscillation is not damped by a
suitable means, the peak voltages may easily exceed the
breakdown rating of the switch or the insulation in the inductor.
Block Diagram
The basic circuit illustrated in Figure 5-35 can be divided into
three functional blocks: Input DC supply, primary, and second-
ary. To make use of this model, we need to expand it to provide
control for the switch timing and to include sufficient circuitry to
satisfy performance and reliability specifications. The complete
block diagram is shown in Figure 5-37.
auxillary
power supply
(+12)
soft start latch
Control IC
duty cycle control
oscillator
current limit
base
_
Semiconductor
Switch
mu
1
|
output griver drive
reference with
soft start
current
sense
+12V
© |.
disk
+12V output is
secondary filters sav
CRT
I
|
|
overvoltage
crowbar
!
|
|
+5V output
i 0 +5V
E secondary filter
-12V > output o -12v
secondary filter
— №»
load sense
+5V adj. jek
feedback
signal
feedback compensation
isolation |
Figure 5-37. Power Supply Block Diagram
145
The other blocks provide additional output voltages, add safety
or protective features, reduce circuit noise, and develop signals
for use by the control section. The control section continuously
operates the bipolar transistor switch and varies the proportion
of ON time to OFF time in response to changes in AC input line
voltage or output load current. This is accomplished by feeding
back a signal from the output terminals and instructs the control
section to increase or decrease the ON time to compensate for
a change in the output voltage.
The DC voltage supply to the control section is controlled by the
latch circuit when AC power is first applied to the power supply.
A built-in timing circuit allows the input DC supply filter capaci-
tor to become fully charged before power is applied to the con-
trol section. After the control section circuit starts and
secondary voltages reach their regulated output levels, the
auxiliary power supply provides the required DC voltage to op-
erate the control section. The latch is reset when the current
limit or under-voltage sensors operate, thus removing DC voit-
age to the Control IC.
There are four secondary or output voltages in addition to the
auxiliary supply: + 5.05 volt, +12 voit CRT, + 12 volt Disk, and
— 12 volt. The + 5.05 and + 12 DISK voltages are regulated by
the control circuit response to the frequency compensated
feedback control signal which comes from the load sense sec-
tion. Since the load sensing occurs on the secondary side, an
optical coupler circuit is necessary to provide safety isolation
between the primary side common ground and the secondary
side common ground.
All secondary voltages, including the auxiliary + 12 voltage,
share the same magnetic flux linkage in the transformer core
and are controlled by the flyback inductor. Any change in sec-
ondary load currents cause a change in the shared magnetic
flux. This change in the flux of the inductor sets up an EMF
(electromotive force) which causes a flux in opposition to the
one which resulted from the change in load current. Thus, the
original change tends to be counteracted and the current deliv-
ered to the load remains constant.
146
The output filters reduce the remaining ripple voltage compo-
nents of the AC line and switching frequencies to levels low
enough to prevent interference with the circuits operated by the
supply. Switching frequency components that could be con-
ducted out the AC input terminals are suppressed by the EM!
filter to avoid interference with other equipment connected to
the power line.
The overvoltage crowbar senses an abnormal rise in the +5.1
volt output and short-circuits the voltage line to the common
secondary ground, thus tripping the current limiting circuit
which finally shuts down the supply.
The surge limiter at the AC line input prevents the input filter ca-
pacitor in-rush current surge from exceeding component rat-
ings or unnecessarily tripping external fuses.
5.4.2 Technical Specifications
Environment:
Temperature; Operating Storage
0 to 50 C (32 to 122 Е)
— 40 to 85 C {(— 40 to 185 F)
Humidity; Operating Storage
85% r.h. (ee 35 C (95 F) max.
95% r.h. (1-55 C (131 F) max.
Input Voltage:
90 to 135 VAC rms, 47 to 63 Hz
Input Surge Current;
48 amps max.
Efficiency:
70% min. at full load with 115 VAC rms input
Output Voltages:
V1, +5.05 VDC
V2, +12 VDC CRT
V3, +12 VDC DISK
V4, —12VDC
Output Power:
continuous 65 watts max.
Qutput Current:
Load
Output Min. Max.
V1 1.35 А 4.0 A
Condition 1 V2 0.60 A 1.5A
(Model Ill use) V3 0.40 À 21A
V4 0.005 A 0.10 A
Condition 2 V1 25 A 50A
(Hard Disk use) V3 0.75 A 2.0 А*
V4 0.005 А 0.10 A
*NOTE: V2 and V3 connect in parallel to provide the V3
output. The V3 output will support a 5.0 A peak
load which decays to 1.0 A in approx. 8 seconds.
V1 and V3 must be within specified regulation
when this surge decays to 4.0 A.
Output Ripple Voltage:
V1 (5.05VDC) 50mV p-p
V2 (+12VDC) 150mV p-p
V3 (+12VDC) 150mV p-p
V4 (—12VDC) 150т\ р-р
NOTE: Ripple is the composite 100/120 Hz ripple due to
the line, plus the high frequency ripple due to the
power oscillator. Common mode noise which may
be observed due to oscilloscope connections
should be ignored.
147
Output Voltage Regulation:
After initially setting V1, output voltage tolerances under all
conditions of rated line, load, and temperature should re-
main within the following limits:
V1 (+5.05 VDC) +/- 3%
V2 (+12 VDC) see "NOTE
V3 (+12VDC) +/- 5%
V4 (-12VDC) +25%, -8.3%
*NOTE: a) The initial value of V2 must not change by
more than +/— 100mV under the following
load conditions of V3:
— À step increase in output current from 0.4
À (initial condition) to 2.4 À, decaying
within 60 msec to 2.1 À.
— À step decrease in output current from 2.1
À (initial condition) to 0.4 À.
V2 output voltage may vary +/— 5% under all
other conditions of rated line, load, and tem-
perature as defined in the specification.
b
—
Over-Current Protection:
Power supply will shut down before total power exceeds
the point where damage would result. No damage will re-
sult when any output is short circuited continuously with
100 milliohms or less.
Over-Voltage Protection:
The + 5.05 VDC circuit is protected with a “crowbar” circuit
with a trip range of 5.8 to 6.8 VDC.
Hold-Up Time at Continuous Max Load:
Nominal Line 16 mSec minimum
Low Line 10 mSec minimum
5.4.3 Theory of Operation
The basic operating principles of a flyback converter and the
necessary functional blocks to form a complete power supply
were reviewed in the System Description section. in this part,
the operation of each section of the circuit will be analyzed and
later these sections will be connected to illustrate the signal
flow in the power supply.
AC Input
A conventional bridge rectifier and a filter capacitor are con-
nected directly across the AC line to provide the DC input volt-
age to the power supply.
Fl r- e =ттт A A E ut aan === === === =
3 amp EMI filter 1
LO y © T2 ‘
90 to 135 VAC | T el, | cn | |
50/60 Hz | c33 32] A
| . |
C30
R38 | 1 | 160 VDC
NO WV | ! + +
' | C29 == $ R39
| J
C28
во ++ LL.
Figure 5-38. Input AC Supply
148
An EMI filter consisting of capacitors C30-C33 and choke T2
are inserted at the input to the rectifier. This filter circuit keeps
the high frequency signals generated in the power supply from
being conducted into the AC power line. C30 and C31 provide
a low impedance to the earth ground terminal for signals com-
mon to both hot and neutral sides of the AC line. C32 provides
a low impedance dissipative path for the RF signal energy
which appears across the line. T2 blocks RF signals common
to both sides of the line and reflects them back toward the lower
impedance elements near the rectifier. T2 also helps block dif-
ferential {across-the-line) signals by using the EMF set up by
the signal current on one side of the line to oppose the signal
current flowing in the other side. C33 serves as a transient by-
pass capacitor to protect the power supply from large transient
voltages that appear on the AC power line. C33 also improves
the efficiency of the RFI filter choke T2 by terminating the line
in a low impedance to absorb and dissipate any remaining dif-
ferential RF energy.
R38 is a negative-temperature-coefficient-thermistor which lim-
its the turn-on surge current of the power supply filter capacitor
C29. The resistance of this thermistor when “cold” is approxi-
mately 10 ohms. As the filter capacitor charges toward the peak
value of the AC input voltage, it draws less current from the line.
Atthe same time, the heating effect of the current flowing in the
thermistor causes its resistance to decrease until it reaches its
rated “hot” resistance of less than 1 ohm. As you can see, the
thermistor dissipates very little power when the power supply is
in operation. The thermistor is designed to cool rapidly enough,
during power loss or turn-off, to limit the turn-on surge after only
a few seconds cool-down.
fay Latch Circuit
VR]
30v
To UL, de
vel | T
The fuse, a fast acting 3.0 amp unit, is selected to ignore the
short term turn-on surges, but open quickly in the event of an
abnormally high current that would result from a component
failure in the DC input supply or current limiting circuits.
Auxiliary Power Supply
The auxiliary power supply is operational when the main supply
is on and not in a shut-down condition. This power supply con-
sists of winding 2-3 on T1, half-wave rectifier CR4, and filter ca-
pacitor C14. The voltage output is approximately + 15 volts
under normal conditions but momentarily reaches about + 31
volts during start-up.
Kick Start Latch
Start up of the circuit is initiated by the kick start latch. This latch
is shown in simplified form in Figure 5-39 (a) along with the ac-
companying waveforms in Figure 5-39 (b). When power is ap-
plied, C14 charges toward Vin = + 160 volts through R26 with
a time constant of approximately RC or 37.5 seconds. How-
ever, as we'll see, the kick start latch turns on in 2 or 3 seconds,
the time required for the voltage across C14 to reach 30 +
Vbe4 = 30.7 volts. At this point Q4 turns on and develops a
bias across R21 which turns on Q5.
Referring to Figure 5-39b, as C14 dumps its charge into C1 be-
ginning at time t2, the voltage across C14 starts to decrease to-
ward a level that will be determined by the load composed of U1
and the base drive circuit. Notice that the voltage across C1
momentarily approaches the full 31 volts at time t3 before it
drops down under load to about + 15 volts at time t4.
tb) Waveforms
—= — — — — — ее mer — т Ме ст AML mem === ===
l4+-—— ——— «E Vstart
time
time
t2t3 td
El: Power applied
t2: Latch turns ON
t3: Cl peak charge
tá: 1 voltage at loaded value
Yin = 160 volts
Figure 5-39. Kick-Start Latch
149
With C1 charging rapidly through the low resistance of a satu-
rated Q4 via Vbes, the reference supply inside U1 develops its
5.0 volt output when the voltage across C1 exceeds about 8
volts. At this point, the supply has not quite yet started, but U1
has a DC supply at pin 10. All that remains is to start up the
pulse generator so that the supply operates and replenishes
the charge in C14 on each cycle, thus maintaining a DC source
for U1 of about + 15 volts. Completion of the start-up sequence
occurs when the soft start circuit, described in the next section,
has started the pulse generator.
Control Section
The control section consists of the control 1C, the primary half
of the feedback optocoupler U2, and the base drive circuit for
the switching transistor. The control circuit IC has three major
parts: an internal regulator, a pulse generator, and an error am-
plifier section.
The internal reference is a regulated + 5.0 DC voltage. This
voltage provides the reference voltages for the comparators
used in the pulse generator as weli as the DC supply voltage for
the feedback optical coupler and the internal circuits of U1 ex-
cept for its output transistors.
The pulse generator section of the control IC has four major
parts: (a) sawtooth oscillator; (b) wave-shaping and output cir-
cuit; (c) regulating comparator; (d) dead-time comparator. Fig-
ure 5-40 illustrates the sawtooth oscillator and output circuit
waveforms and the approximate levels of the DC control volt-
ages applied by the comparators to the wave-shaping logic.
The oscillator frequency is set by the values of R3 and C7
shown in Figure 5-41.
The amplitude of the sawtooth is set at 3.0 volts (approximately
60% of the 5.0 volt reference voltage). Whenever the sawtooth
voltage, Vosc, exceeds both of the DC control voltages, Vreg
and Vdt, the output circuit will be in the ON condition.
The DC contro! voltage, Vreg, set at a quiescent value by R6
and RS, varies in response to changes in the supply’s DC out-
put voltages as sensed by U3 and coupled through U2. Notice
that these voltages will vary because of changes in output load-
ing, AC input voltage, and also because of the residual 120 Hz
ripple component from the main DC supply.
The dead-time control voltage, Vdt, is set at a constant value by
R4 and R5 and ensures that the pulse generator “OFF” time
will be at least 50% of the sawtooth period. This allows ade-
quate time for the complete transfer of stored energy from the
primary to the secondary of transformer T1 as discussed in the
section on basic principles.
150
A concept known as duty cycle was introduced in earlier para-
graphs. Duty cycle is defined as the ratio of the “ON” time of the
sawtooth cycle to the total length of the sawtooth period. Since
the sawtooth has a linear ramp characteristic, the duty cycle is
also equal to:
Vosc, pk - Vreg ton
duty cycled =
Vosc, pk T period
There are three possible conditions of the duty cycle:
а = 0 which occurs when either control voltage
Vreg or Vdt exceeds the peak value of the
sawtooth waveform Vosc.
d = 50% which occurs when Vreg is less than Vat.
This happens when the loading on the output
of the supply is heaviest and the AC input
voltage is at its lowest permitted level (see
specifications)
0 < d <50% which occurs during normal operation.
The dead-time control voltage is used in one other important
way. Notice the 4.7 ufd capacitor, C2, connected across R4 in
Figure 5-41. When power is first applied to the supply, the volt-
age across the capacitor is zero. Therefore, Vdt = Vref = 5.0
volts and no pulses appear at the output because Vdtis greater
than Vosc,pk. As C2 charges, Vdt decreases toward 1/2
(Vosc, pk) in a time determined by R5 and C2 ast = 5x15k ohm
X 4.7 ufd = 1/3 second. As Vdt decreases past Vosc,pk, very
narrow puises begin appearing at pin 8 of U1. The pulses be-
come successively wider until Vdt is less than Vreg. C2 contin-
ues charging until Vdt reaches the final correct value of about
1.5 volts. This action provides the soft start feature of the power
supply and allows sufficient time for the DC input supply and
latch to reach normal operating conditions before the supply is
started. In effect, the load is connected to the supply gradually
by the soft start circuit.
vVosc,volts (Ul, pin 5)
Vlogic
A
5
4
3 | Vosc,pk
r 2.5V = Vreg
2
) ) 1 1.5V = Vdt
1 | |
| |
7 I = time
| | |
Vout,volts (Ul, pin 8) | | 1
I | l |
| | ||
| | | |
| | po 1
| | | | |
0 e tj
i | | | | time
| |
— | ен tON | I
ı | | |
| 1 |
| [Фо БОРЕ — — |
l 1
| |
| «т — — =
T “Y 25 microsec,
Figure 5-40. Osciltator, Pulse Generator Waveforms
+VYC7
U1 MC34060 A
Regulator Section
12 5 volt 10
Reference
Regulator
$ R23
—— — EEE ее ен === —]]DH EEE кн к — === EEE UA o = = = === === == —— в
Pulse Generator Section
soft y
start Г ==]
| Dead- Time Oscillator pulse-width 5 К” 03
Comparat
J 3 parator 11 Comparator
C2 $ R4 + — — A
| 4
To C8
a — -— — — — — 4 но = В = —
2 R5 Error Amplifier Section
A A 6
ZL Shut-down Modulator
time Error Amp Error Amp
+ — — + R19
7 6 |s 14 [13 |3 в |2 |1
R3 C7 +
1 —^^^-Ф VIE Base Drive
Feedback = = Ra
+ e
e R10 >
> SHE
ñ U2B $
LH 1/2 from current limit > |
r
C3 oH
A
R7
Figure 5-41. Control Section
151
Frequency stability of the sawtooth oscillator is provided by the
2% tolerance and polyester construction of the timing capaci-
tor, C7, and the 100 parts-per-million temperature stability and
1% tolerance of R3. Voltage stability of the DC control voltages
is provided by the +/— 2 1/2 percent stability of the 5.0 volt
reference.
The control section consists of two error amplifiers in U1, the
primary half of U2, and associated circuitry shown in Figure 5-
41. One of the error amplifiers serves as a regulator or pulse-
width modulator which derives the DC control voltage, Vreg,
from the signal voltage developed across R7 by the current in
U2. This current is a replica of the current developed by U3 in
response to the condition of the output voltage at the +5.1v
and + 12v outputs. This amplifier has a gain of about 10 deter-
mined by:
R8 22k ohm
10
R9 RE 2.35k ohm
The other error amplifier in U1 serves as a shut-down compar-
ator. The positive terminal, pin 14, is set at the +5.0 volt ref-
erence and pin 13, the negative terminal or shut-down pin, is
tied to the current limit latch. The output of this error amplifier
(equal to Vreg since both error amplifier outputs are tied to the
wave-shaping logic) will rapidly increase toward the + 5.0 volts.
Recall that if Vreg exceeds the peak sawtooth voltage, pulses
are inhibited and the power supply shuts-down.
+15V
/ R23
ul q
——
ul Q3
Æ—————
Base Drive
Figure 5-42 illustrates the BASE DRIVE circuitry which turns
switching transistor Q7 on and off in response to the output
of the pulse generator portion of U1. The “ON” circuit is
shown in Figure 8a and the “OFF” circuit is shown in Figure
8b. Waveforms for these circuits appear in Figure 5-43.
The output transistor of U1 combined with Q3 forms a Darling-
ton pair. This circuit provides the relatively large current nec-
essary (through coupling capacitor C8) to turn on Q7. R23 limits
this base current to a value large enough to turn on Q7 quickly,
but not so targe that it will exceed the ratings of Q3, C8, or the
base emitter junction of Q7, or so large that the turn-off time of
Q7 is excessive.
As Q3 turns on, C8 charges to approximately +5 volts and Q7
is driven into saturation. Energy is stored in the primary winding
of T1 as the collector current of Q7 increases or “ramps up" at
a rate determined by the inductance of the transformer primary
winding.
When the output transistor of U1 turns off, the emitters of Q1
and Q2 are initially at the + 6 volt level determined by the
charge on C8, the Vbe drop of Q7, and the drop across R37.
Both base-emitter junctions of the Q1-Q2 Darlington pair are
biased ON and the positive terminal of C8 is clamped to near-
ground by the saturating Q1. At this point, C8 still has most of
its charge and the base voltage of Q7 is approximately — 4.5
volts with respect to ground.
+160V
(a) Turn Q7 ON
(b) Turn Q7 OFF
Figure 5-42. Base Drive Circuit
152
V 97 Base
A
10 +
+1V
> T -4.5y
-10 Ee
ha—r=25usec —
Figure 5-43. Q7 Base Voltage Waveform
With the strong reverse polarity provided by C8 across the base
emitter junction of Q7, the “forward” charge stored in the junc-
tion capacitance is quickly swept out and Q7 is turned off. C8
continues to discharge through R24 to prepare for the next
“ON” cycle. R19 limits the initial discharge of C8 while Q7 is
turning off.
Notice the symmetry in the base drive circuit and the key role
played by C8 in both the turn-on and turn-off sequences. Be-
cause of this crucial role in the circuit, this capacitor is specified
as a high temperature, low-equivalent-series-resistance
component.
|
+160V | )
| |
| |
| |
| |
TZ | R40]
I
primary
| c37
Jo
| |
| |
| |
| |
| |
JT
ON 97 | |
| Ï
| |
| |
| |
;
| |
| |
| |
1 |
L
= | |
= \ |
|
(a) Primary | (5) Snubber |
Primary Circuit and Current Limit Shutdown
The Primary Circuit
The Primary circuit, shown in Figure 5-44 (a), functions exactly
as described earlier in the “Basic Principle” section. That is, the
switch (Q7) is controlled by the base drive waveform developed
by the control section.
shut-down
kick-start control
reset
Cl
CR1 L
Control Bus
CR2 y CR3 И
R33
Xx Latch
No
Detector
(c) Current Limit Sense
Figure 5-44. Primary Side Protection
153
The Snubber Circuit
Practical transformers cannot couple 100% of the stored en-
ergy from the primary to the secondary since all of the flux from
the primary fails to link all the secondary turns. A circuit using
this practical transformer behaves as though a small fraction of
the primary inductance was not wound on the core of the trans-
former, but instead placed apart from the primary and in series
with it. This small, separately-acting inductance does not par-
ticipate in the transformer action and is called the leakage
inductance.
If the resonant circuit, consisting of this leakage inductance and
the stray capacitance in the adjacent circuit, has sufficient Q
(relatively low resistance losses), a damped oscillation will oc-
cur in this resonant circuit when the transistor switch opens.
The peak value of this oscillation will add to the Vce = 2x Vin
which appears across the transistor switch just after turn-off.
The combined peak Vce may exceed the transistor breakdown
rating if not damped out by the action of a snubber circuit.
When Q7 turns off, the energy stored in the leakage inductance
is transferred to the electric field of the total capacitance of C37
plus stray capacitance. (Since C37 capacitance is much larger
than the strays, it dominates in this action and tends to limit the
peak value of the Q7 turn-off voltage.) If there were no resist-
ance in this series connection of C37-plus-parasitics and leak-
age inductance, they would exchange this energy back and
forth indefinitely. R40 is used to damp this oscillation without
excessively slowing the turn-off voltage spike at the collector of
Q7.
Current Limit Circuit and the Shut-Down Sequence
The current limit circuit forces the voltage level at a control pin
of U1 to change to a near-zero value very quickly when the cur-
rent in the transistor switch exceeds a predetermined point. №
also removes the supply voltage from the control circuit and re-
sets the kick start latch and soft-start circuits.
The current limit circuit shown in Figure 5-44(c) has three parts:
a control bus, a detector, and a latch. The control bus supplies
the operating DC voltage to the current limit circuit. It also con-
ducts the current limit signal to control pin 13 and to the reset
point in the kick start latch circuit. Diodes CR2 and CR3 steer
this signal.
The normal maximum peak current in switching transistor Q7 is
3 amps. The detector transistor Q8 is biased to turn on by the
divider action of R35 and R36 whenever the Q7 peak current
through R37 exceeds 4 amps. A low-pass filter, formed by R35
and C22, prevents false detections on transient signals that
don't represent an over-current condition.
164
As soon as QO turns on, its collector current develops the turn-
on bias for ОВ across R33, and the Q8-Q9 pair “latches” in the
“ON” state until the DC source for the latch is removed. Re-
moval of this DC source occurs when C1 discharges through
CR1, thus removing DC voltage from the control IC. Notice also
that the Kick start latch, Q4 and QS, is still in the “ON” state and
thus provides a discharge path for C14. When the decreasing
voltage across C14 is less than approximately one volt, the Q4-
Q5 latch also switches off.
At this point in time, all circuits are in an OFF condition except
the input DC supply. C14 now begins to re-charge toward the
input DC supply to restart the power supply. If a fault remains,
the kick start and current limit circuits will continue to shut-down
and re-start the power supply several times per second until the
fault is removed or AC power to the supply is turned-off.
Under-Voltage Lockout
The Under-Voltage Lockout, UVL, shuts down the supply
whenever the AC input voltage drops below about 90 volts. This
occurs when the voltage at pin 13, set by the divider action of
R27 and R25, diminishes to a level below the internal reference
supply of the control IC. Pulses are inhibited immediately and
because the DC supply to the Control IC is no longer replen-
ished by the auxiliary supply, it discharges toward zero.
Why is it important to shut down the supply if the input AC tine
drops below 90 volts? The answer will become clear when an
inherent characteristic of the circuit is discussed, namely, its
negative input resistance.
Imagine the situation where the supply is delivering full power
to its load and the AC input voltage drops five or ten volts. The
supply control circuit responds by increasing the “ON” time of
the switching transistor thus increasing the average current in
the primary winding. The only way the DC supply can deliver
more current is to draw it from the AC line. So the negative
change in AC input voltage was accompanied by a positive
change in AC input current.
Another way to describe this characteristic is that the supply is
a constant power device, that is:
Pin = Vin x lin = constant.
Thus if V decreases, | will increase, and vice versa. The supply
will thus draw more and more current from the AC line if the AC
voltage continues to decrease. In order to limit the average cur-
rent to a safe value, the control circuit senses the input voltage
and shuts down the supply before the AC voltage level be-
comes too low or the AC current input becomes too high.
Secondary Outputs
Each of the secondary windings consist of a half-wave rectifier
followed by a pi filter. The input capacitor of the filter stores the
charge delivered to it when the rectifier is biased ON by the po-
larity of the transformer winding. The inductor and the output
capacitor form a low-pass filter which removes the switching
frequency ripple component.
The current output of the — 12 volt supply is much smaller than
that of the positive voltage outputs. Because of this, the current
limit circuit response is not sufficiently effective to prevent dam-
age to the — 12 volt circuit. Therefore, a three terminal regulator
with its own current limiting circuit is used to protect the — 12
volt output.
All of the 12-volt rectifiers are fast recovery types and the +5
volt rectifier is a Schottky type. These diodes feature high
switching speeds during turn-off. Their low forward voltage
drop minimizes dissipation resulting in maximum efficiency.
Each of the positive outputs has a bleeder resistor.
The reason for two separate + 12 volt outputs is to provide suf-
ficient isolation between different types of loads. It is easier to
regulate the + 12 volts if the toad which contains the DC motors
In the disk drives is separated from the rest of the loads. In ad-
dition, the +12 volt “Disk” output (V3) is included in the load
sense network in order to minimize the load transients which
occur when the disk drives turn on and off. The supply is then
better able to regulate the other + 12 volt output (V2) during the
severe V3 transitions.
Load Sense and Feedback Signal Development
The circuit of Figure 5-45 has three parts. In part (a), the 1C's
U2 and U3 are biased ON by resistors R11 and R22. These re-
sistors also sense the changes in AC line input voltage to pro-
vide line regulation. U2A is the LED half of an optocoupler
which serves to isolate the DC ground circuits of primary and
secondary while coupling the AC feedback signal via optical
coupling. U3 serves as both a stable DC reference voltage
which the output voltages are compared against and as an er-
ror amplifier which provides the gain necessary for adequate
sensitivity of the control IC to load changes.
+12V
+12V Qutput
| | Input
| |
| |
Ll | |
+ | | О +
т À
R22 R11 R12] > R14 | c13 $R29 $ RIO
i L
1 | |
UZA —— С5
5 Volt MZ | T™ 5 Volt
Input 2 | C4 R13 Output
Ra SE | R15
© [ VV * >
U3 | |
7 | R16
| |
— O- O -
| |
+ | |
= |
| |
(a) Feedback | (b) Frequency | (c) Load Sense
Signal Processor | Response |
| | |
Figure 5-45. Feedback Signal Development
155
Each of the passive components in the load sensing network is
a high stability (+/— 100ppm) part to assure stability of the net-
work over the operating temperature range of the power supply.
Part (b) of Figure 5-45 includes the network which tailors the
frequency response of the error amplifier so that it responds to
low frequency change only. This network, consisting of R14/C5
and R13/C4, also determines the stability of the power supply
by ensuring that the power supply control circuit has no tend-
ency to oscillate.
Part (c) illustrates the load sensing network. Equal currents
through R15 are supplied from the +12V DISK and +5.05V
outputs by R29 and R30. In addition, a portion of the transient
signal occurring on the +12V CRT output (when the motors
turn on or off) is fed to R15 by C17. The wiper of R15 feeds a
control signal which represents the status of the current loads
to the error amplifier U3. U3 amplifies and compensates it then
U2 couples that control signal to U1 where it is used to vary the
switching transistor (Q7) ON time to adjust the output voltages
as necessary. R15 is adjustable to provide the initial set-up of
the + 5.05V output when it is installed in a computer.
oO —{ +
VR2 5 Volt
Output
06 $ RIS
$ R17 je
1
— ЩИ ЧЩ —) -
Figure 5-46. Overvoltage Crowbar
Overvoltage Crowbar
Some of the circuits supplied by the +5 voit output are quite
sensitive to voltages in excess of 7 volts. Since some circuits
require both +5 and + 12 volts, a failure in those circuits could
apply +12 volts to the + 5-volt bus and thus damage some of
the + 5-volt circuits. To prevent the + 5-volt bus from exceeding
a safe level, an SCR, Q8, is used to “crowbar” or short-circuit
the + 5.05 volt output to the secondary ground bus. This short
circuit triggers the current limiting circuit and the supply shuts
down until it tries to restan.
Referring to Figure 5-46, VR2 sets the turn-on point of the SCR
and R17 develops the gate signal when VR2's Zener break-
down voltage of 5.6 volts is exceeded. C6 and R17 provide cur-
rent limiting for VR2 and filter the gate signal so Q6 won't
respond to transient signals.
156
Power Chain
In a sense we have already analyzed the power chain in the
section on basic principle of operation. The base drive causes
the switching transistor to turn on and off at a prescribed rate.
This action alternately stores energy from the DC input in the
primary inductance and releases it into the secondary through
the flyback transformer action. The energy is then stored in the
input filter capacitor at a voltage determined by the transformer
turns ratio. Notice that the turns ratio determines the ratio of col-
lector voltage to secondary voltage, both of which are alternat-
ing voltages. The ratio of input-to-output DC voltage is
determined by the duty cycle and the turns ratio together.
For example, let's look at the +5 volt output of Figure 5-31 at
normal loading and approximtely 120 VAC input. Under these
conditions, the DC input voltage is 168 VDC and the duty cycle
is approximately 40%. Thus, our average DC voltage at the
switching transistor collector (or across the primary) is 40% of
168 or 67.5 volts. Dividing this average DC voltage by the turns
for the 5 volt secondary (54 : 4 = 13.5) gives us 5.0 volts.
67.5V
____- = 5V
13.5
+168 VDC
TI CRS
4 11 - +5 VDC
54t at C10
5,6 10 + ©
| | | 07
base drive
Figure 5-47. Power Chain
Control Chain
Imagine the load end of the feedback path disconnected from
the + 5.05 volt output terminal and unfolded so that the load
sense network is now at the “input”. The secondary rectifier
(CAS) and filter (C10-C12, L1,) remain as the output. The circuit
as it now appears, redrawn in simplified form in Figure 5-48, is
known as the control chain. To see how the regulation action
occurs, assume a small negative voltage change at the “input”
of the feedback network and follow it through the control chain.
This negative voltage change, which would correspond to a
slightly heavier load current, appears at pin 1 of U3 as a de-
creasing voltage. The error amplifier in U3 inverts and amplifies
this signal. The positive-going output voltage of U3 at pin 3
causes less current to flow in the internal LED of UZA. À replica
of this smaller current, optically coupled and induced in the pho-
totransistor of U2B, develops a reduced voltage across R7 at
the non-inverting input of the regulator error amplifier in U1,
The regulator error amplifier in U1 does not invert the signal, but
further amplifies it, improving the sensitivity of the control chain
to small changes at the power supply output. The regulator er-
ror amplifier output is Vreg. Since we established earlier that a
negative-going Yreg increases the length of the base drive
pulse, Q7 is turned on a little sooner so that it can store more
energy from the AC line in the primary inductance. Finally, this
increased energy is stored in the filter capacitor C10, C11 dur-
ing the fiyback interval and supplies the increased demand for
current that resulted in the original reduction in the output
voltage.
More simply stated, the control chain uses an amplified version
of the output voltage CHANGE to adjust the width of the base
drive pulse through the action of a control voltage at a compar-
ator input.
from from SV
CRS reference
I in Ul
I
| = Voltage e0es down
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= Secondary -— |-> Primary
|
compensating change
|
|
+15V +160V | in output
ul |
from MC34060 |
oscillator | CRS a b
Modulator Pulse-width |
Error -Amp Comparator | m €l10/1]1
a > + i y
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4 |
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Q7
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Primary #——;-—#— Secondary
Figure 5-48. Control Chain Simplified Schematic
5.4.4 Troubleshooting Chart for 65 Watt Power Supply
Trouble
open fuse
Current limit cycle
no pulses at pin 8 of U1,
(i.e., supply shut down)
Cause
shorted line input filter capacitor
shorted bridge
shorted filter capacitor
shorted switching transistor
single rectifier open in bridge
open filter capacitor
shorted snubber capacitor or resistor
open opto-coupler
shorted supply output
shorted output rectifier
open or shorted output filter capacitor
defective crowbar
no aux. DC supply
no “kick start”
no base drive
dead-time control divider malfunction
under-voitage protect divider
malfunction
PWM feedback malfunction
158
Remedy
check and/or replace C33, C32, C31, C30
check BR1
check C29, C26, R39
check Q7, C37, R40, C26, T1 pri, Q3,
Q1, R37
check and/or replace BR1
check C29
check C37, R40
check U2
check computer for shorton +5V, +12V
CRT, +12V DISK, —12V outputs and
clear shorted condition
check CR5, CR6, CR7, CR8
check C16, C18, C25, C23, C10, C11,
C12, C19, C20
check Q6
Check and/or repiace CR4, C14, T1 aux.
check R26, Q4, Q5, VR1, CR1, C1
check Ut, Q3, R23, C8, R24
check C2, R4, R5, U1 (for V ref.)
check R27, R25, C9, Q9
check and/or replace U1, U2, C3
9.4.5 Testing and Adjustments
The following tests should be performed to guarantee correct
operation of the power suply after repairs have been made. The
first test checks the primary circuits and is to be made without
AC power applied. The second test is a complete operational
test with AC power applied.
Primary, Checks T2, U1
NO AC POWER APPLIED
1. Apply +35 volts DC via 170 ohm, 5 watt resistor from Q4
emitter to the primary side of ground. Primary side ground
is the point labeled 1 on the schematic. Also apply 35
volts DC via a 120k ohm resistor and a normally closed
SPST switch from Pin 13 of U1 to primary ground. Observe
the voltage across C14 as it charges. As it reaches a value
near +31 volts, it should drop to near + 16 volts as Q5 and
U1 turnon.
2. Check U1 pin 8 and/or Q7 base for a base drive pulse: a 40
kHz square wave of 8/4 volts respectively.
3. Switch the SPST switch connecting the 120k ohm resistor
from Pin 13 of U1 and check for loss of base drive pulses
on Q7.
Operational, Checks T2, U1, U2
APPLY AC POWER
1. Apply rated maximum loading for condition 1 (Model Ill
use) or condition 2 (5 1/4" Hard Disk use).
2. Apply 120 VAC input voltage and observe Q7 current (via
ivop on PCB) and voltage (at TP2). Supply should start in
two to four seconds.
3. Observe the +5.05 olt output and adjust R15 until the out-
put is exactly + 5.05 volts DC.
4. Measure +12V and —12V outputs.
5. Check all outputs at Vin = 90 VAC and 135 VAC at:
(a) minimum and maximum loads
(b) check + 12V CRT when + 12V DISK varies in transient
test.
6. Measure ripple. See Measurement Techniques below.
7. Measure efficiency. See Measurement Techniques below.
8. Test operation of current limit and over-voitage protection
circuits by applying + 7.0 volts to the +5 volt output.
159
Measurement Techniques
1. Ripple — Unit connected to full load at low line. One end of
50 ohm coaxial cable connected to output terminals. Other
end of cable (terminated with 0.01uF ceramic cap in series
with 51 ohm resistor) connected to scope using BNC T-fit-
ting. Two components at 120 Hz and 40 kHz.
2. Efficiency — Use Diego Systems Series 200 power
monitor.
Power Out
Efficiency —
Power In
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PARTS LIST
Power Supply Assembly 8790049, 65W
Item Sym
a EE
— —:
1 1
1 Jl
BR1
Cl
C2
C3
C4
C5
C6
C7
C8
C9
Cl0
Cll
C12
Cl3
Cl4
Cl5
C16
Cl7
C18
Cl9
C20
С21
C22
C23
C24
C25
C26
С27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
Description
Printed Circuit Board
Fan Output 2-pin verticle
Bridge, 2A, 600PIV
10pF, 35V, elect., radial
4.7uF, 50V, elect., radial
0.047uF, 50/63V stacked metal
0.47uF, 50/63V stacked metal
0.068uF, 50/63V stacked metal
luF, 50, elect., radial
0.001uF, 63V poly
47uF, 25V, elect., radial
luF, 50V, elect., radial
2200pF, 10v, elect., radial
2200uF, 10V, elect., radial
2200uF, 6.3V, elect., radial
0.01pF, 50/63V stacked metal
100uF, 35V, elect., radial
1000pF, 100м, ceramic disc
2200uF, 16V, elect., radial
O.luF, 50/63V stacked metal
3300uF, l6V, elect., radial
100uF, 35V, elect., radial
100uF, 25V, elect., radial
.047uF, 50/63V stacked metal
.O0lpF, 50/63V stacked metal
470uF, 16V, elect., radial
0.1pF, 250VDC metal poly
2200uF, 16V, elect., radial
220uF, 200V, elect., radial
Not Used
4700 pF, 125VAC, ceramic disc
220uF, 200V, elect., radial
4700pF, 125VAC, ceramic disc
4700pF, 125VAC, ceramic disc
.22UF, 125VAC, ceramic disc
.OluF, 250VAC, metal paper
Not Used |
Not Used
.001uF, 50/63V stacked metal
.OOluF, 630V, poly
.022uF, 63V, poly
165
8709365
8519214
8160402
8326103
8325474
8393474
8394474
8393684
8325014
8392104
8326472
8325014
8328224
8328224
8328220
8393104
8327103
8302106
8328221
8304104
8328331
8327103
8327102
8393474
8393104
8327461
8394106
8328221
8327226
8303475
8327226
8303475
8303475
8393432
8393106
8392014
8392017
8393422
PARTS LIST
Power Supply Assembly 8790049, 65W
— E EEE nn a ara PEE EE e ES EE
Item Sym Description
C39 .022uF, 63V, poly
CR1 Diode, 1N4148, switching
CR2 Diode, 1N4002, 1A/5OPIV
CR3 Diode, 1N4002, 1A/50PIV
CRA Diode, 1N4934, 1A/100PIV
CR5 Diode, MBR1035, 8/10A, 35V, TO-220
CRO Diode, MUR810, 8A/100PIV, TO-220
CR7 Diode, 1N4934, 8A/100PIV
CR8 MURB10, 8A/100PIV, TO-220
CR9 Not Used
CR10 Diode, 1N4002, 1A/50 PIV
CR11 Diode, 1N4002, 1A/50 PIV
Fl 3 amp, AGC
Ll Inductor, 5.0uh, 10А
L2 Inductor, 30ph, 5A
L3 Not Used
L4 Inductor, 30uh, 5A
L5 Inductor, 100uh, 3A
Ql Transistor, MPSUS51A, PNP, TO-202
Q2 Transistor, MPSA55, PNP, TO-92
Q3 Transistor, MPSUOlA, NPN, TO-202
Q4 Transistor, MPSU51A, PNP, TO-202
05 Transistor, MPSUOlA, NPN, TO-202
06 SCR, 8A/50PIV, TO-220
Q7 Transistor, MJE1l3006, NPN, 8A,
Q8 Transistor, MPSA55, PNP, TO-92
Q9 Transistor, MPSAO5, NPN, TO-92
Ul IC, MC34060 Switching Regulator or
IC, uA/TL494 Switching Regulator
02 IC, Opto-isolator, 4N35
U3 IC, yA/TL431, Positive Shunt Reg.
Е]. Resistor, 1K, 1/4W, 5%
R2 Resistor, 68 ohm, 1/4W, 5%
R3 Resistor, 28K, 1/4W, 1%
R4 Resistor, 39K, 1/4W, 5%
RS Resistor, 15K, 1/4W, 5%
166
8393422
8150148
8150002
8150002
8150934
8150035
8150810
8150934
8150810
8150002
8150002
8479104
8419006
8419008
8419008
8419009
8100051
8100055
8111001
8100051
8111001
8140122
8110006
8100055
8110005
8060060
8060494
8170035
8060428
8207210
8207068
8200328
8207339
8207315
= ля =
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EE nn ll PA al
PARTS LIST
Power Supply Assembly 8790049, 65W
— == FE ET A TE TE EE EE AN TE FE TE CEE TEE SE TEEN TENE EE сути == ту ету === === = на = === te ———
== == —— "E" a VU mae a e e o a o a, AU NU DEN DE DE PEN DE NU EE al —
Item Sym Description Part Number
R6 Resistor, 4.7K, 1/4W, 5% 8207247
R7 Resistor, 10K, 1/4W, 5% 8207310
R8 Resistor, 22K, 1/4W, 5% 8207322
RY Resistor, 4.7K, 1/4W, 5% 8207247
R10 Resistor, 4.7K, 1/4W, 5% 8207247
R11 Resistor, 100 ohm, 1/4W, 5% 8207110
R12 Not Used
R13 Resistor, 18K, 1/4W, 5% 8207318
R14 Resistor, 330 ohm, 1/4W, 5% 8207133
R15 1K, 20%, linear Pot. 8279211
R16 Resistor, 3.32K, 1/4W, 1% 8200232
R17 Resistor, 100 ohm, 1/4W, 5% 8207110
R18 Resistor, 10 ohm, 1/4W, 5% 8207010
R19 Resistor, 1 ohm, 1/4W, 5% 8207001
R20 Resistor, 10K, 1/4W, 5% 8207310
R21 Resistor, 150 ohm, 1/4W, 5% 8207115
R22 Resistor, 330 ohm, 1/4W, 5% 8207133
R23 Resistor, 27 ohm, 2W, 10% 8248127
R24 Resistor, 22 ohm, 1/2W, 5% 8217022
R25 Resistor, 22K, 1/4W, 5% 8207322
R26 Resistor, 56K, 1W, 5% 8247356
R27 Resistor, 390K, 1/4W, 5% 8207439
R28 Resistor, 22 ohm, 1/4W, 5% 8207022
R29 Resistor, 28K, 1/4W, 1% 8200328
R30 Resistor, 6.65K, 1/4W, 1% 8200266
R31 Not Used
R32 Resistor, 1K, 1/4W, 5% 8207210
R33 Resistor, 100 ohm, 1/4W, 5% 8207110
R34 Resistor, 1K, 1/4W, 5% 8207210
R35 Resistor, 68 ohm, 1/4W, 5% 8207068
R36 Resistor, 100, 1/4W, 5% 8207110
R37 Resistor, 0.22 ohm, 2W, 10% 8248022
R38 Thermistor 10 ohm 25c 8298010
R39 Resistor, 56K, 1W, 5% 8248356
R40 Resistor, 82 ohm, 5W, 5% 8248082
R41 Resistor, 56K, 1/4W, 5% 8207356
R42 Resistor, 4.7K, 1/4W, 5% 8207247
T1 Transformer, Power, 65W flyback 8790063
T2 Line Choke, 5.5mH/side, 2A 8790045
VR2 Zener, 1N5232B, 5.6V 8150232
VR1 Zener, 1N5256B, 30V 8150256
VR3 Voltage Regulator 79M12 -12V 8051912
167
MISCELLANEOUS HARDWARE
Wire, Jumper 20 Ga. (W1,2,5,6) BH"
Wire, Jumper 20 Ga. (W7)
Wire, Jumper 20 Ga. (W4)
Wire, Stranded 600V (W3) 8433006
2 Clip, Fuse, PC Mount 1/4" Fuse (Fl) 8559042
1 Connector, 2 Pin, Vert. (Jl) 8519214
1 Connector, 3 Pin (J3) 8519153
1 Connector, 13 Pin (J2) 8519154
1 Bracket, Heatsink, T0-220 (CR5,6,8) 8729167
1 Heatsink, Transistor, ТО-220 (07) 8549003
4 Insulator, T0O-220, Mica (Q7,CR5,6,8) 8539003
4 Nut, KEPS, #4-40 (Q7,CR5,6,8) 8579003
4 Screw, #4-40 x 3/8" (Q7, CR5,6,8) 8569002
4 Washer, Shoulder (Q7, CR5,6,8) 8589026
4
1
1
1
168
5.5 CRT DISPLAY
5.5.1 Specifications
The supply voltage is 12.000 DC, +/--0.10V, from a regulated power supply. The room temperature is 25 degrees C.
Power Input {1K =30uA},12V
Input Level
Horizontal (Positive-going Sync)
Vertical (Negative-going Sync)
Video (Positive-White)
Video Bandwidth (10Hz - 12MHz)
Horizontal Retrace
Vertical Retrace
Scanning Frequency
Horizontal
Vertical
Resolution at Center
Resolution at Corner
Geometric Distortion
Pin/Barrel distortion on top/bottom
on Sides
Trapezoidal Distortion top/bottom
left/right
Pareilogram Distortion
Raster Tilt
Linearity
Vertical Size
Video (24 rows)
Horizontal Size
Video (80 characters/Row)
169
Nominal
0.85
8.2
700
15,840
Limit
1.0
TTL Compatible
TTL Compatible
TTL Compatible
+/-3
9.5
1,000
+/—500
47 - 63
800
680
+/— 0,05
+/— 0.038
0.150
0.100
0.100
+/—- 1.0
+/— 10
+ — 0.20
+/— 0.20
MOT 149
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Figure 5-49. Video Monitor 8790613 (612)
170
5.5.2 Adjustment Procedures
Horizontal Synchronization Adjustment (Figures 5-50 thru 5-
52)
When there is a pattern on the CRT as shown in Figure 5-50, 5-
51, adjust VR301 to terminate scrolling, and then do VR301
slightly to move the video into the center of the raster as illus-
trated in Figure 5-52.
N
N
Figure 5-50.
7
Figure 5-51.
je =
PICTURE
RASTER
Figure 5-52.
Vertical Synchronization Adjustment (Figures 5-53, 5-54)
Adjust VR201 to stop scrolling, when video is rolling upward or
downward as shown in Figure 5-53. By turning VR201 clock-
wise and counter-clockwise, the initial points of scrolling can be
confirmed. Consequently, set VR201 at the center between the
confirmed points.
Ш
Figure 5-53.
V- HOLD
PULL IN RANGE
e
VR2OI
Figure 5-54.
Vertical Size Adjustment (Figure 5-55)
Generate a full white screen on the CRT, and adjust the video's
vertical size to be 4.5".
VIDEO
|
HEIGHT
RASTER
VERTICAL
am
r
— Ú—É —:——]
Figure 5-55.
Horizontal Size Adjustment (Figure 5-56) Raster Tilt Adjustment (Figures 5-58, 5-59)
Generate a full white screen on the CRT. Adjust video's hori- Forma series of “ —” characters along the horizontal center line
zontal size with L302 to be 6.0”. as shown in Figure 5-58. Adjust the center line to make A1 = À2
by turning the deflection yoke left and right.
| A VIDEO
ai"
RASTER
Pme mr === f \ АЙ Y
O
HORIZONTAL
WIDTH O LHC НН —
Ä 4
Figure 5-56. |] A ho
с
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NODUUNAOEOCENGrEO OSADO OO OENOFUCOROOZ OO OONOOOOANICONAUELA
Focus Adjustment (Figure 5-57) L D
Display a full screen of the character “H” and adjust VR303 so Figure 5-58.
that all the characters are the same size and shape and in sharp
focus. While adjusting, observe both peripheral and central
areas of the display. Note: Loosen the cramp screw on the deflection yoke for tilt ad-
justment as shown in Figure 5-59.
DEFLECTION
YOKE
Figure 5-57.
CENTERING
MAGNETS
Figure 5-59.
172
Video Centering Adjustment (Figure 5-60)
Display a white screen or a full screen of the character “H” and
adjust the centering magnet on the deflection yoke to make
L=Rand T=B.
Figure 5-60.
Internal Brightness Adjustment (Figure 5-61)
Set the remote brightness control to the center position, and ad-
just VR302 to hold the raster at the point at which it is first
visible.
\
\
VIDEO
RASTER
Figure 5-61.
Video Distortion Adjustment (Figures 5-62, 5-63)
Insert a video distortion-correcting magnet onto the magnetic
holder if required, and rotate it for adjustment.
Pincushion/Barrel Correction (Top, Bottom and Sides)
Perform this adjustment if the CRT exhibits the abnormal ef-
fects shown in Figure 5-62.
Step 1. Push the magnet on the yoke mounting pin as shown
Figure 5-63. A magnet should be placed only on the
pin that corresponds to the affected area.
Step 2. Rotate the magnet to obtain the desired video display
labeled “NORMAL” on Figure 5-62.
Step 3. Ifthe desired video display cannot be obtained, replace
with a proper magnet.
oo IES
| co o M
a | Hh
FL Ch, aADJUSTING [|
ba" MAGNET |
NORMAL
| | | "о
|
ai e 0 ЗН
||| |
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Figure 5-62.
Trapezoidal Correction (Corners) Procedure
Perform this adjustment if the CRT exhibits the abnormal ef-
fects as shown in Figure 5-63.
Step 1. Push a magnet onto the yoke mounting pin as shown
in Figure 5-63. Magnet should be placed only on the
pin that corresponds to the affected area.
Step 2. Rotate the magnet to obtain the desired video display,
labeled “NORMAL” in Figure 5-63.
Step 3. Ifthe desired video display cannot be obtained, replace
with a proper magnet.
— — —— — — —
— —
— —
— rm ——
—
== o
= =
NORMAL
Figure 5-63.
5.5.3 Theory of Operation
Video Control
The DC controlling voltage from P8 determines the level of TTL
compatible, positive and non-composite video signal which is
provided by the CPU.
Video Drive and Video Out
Q102 and Q103 are connected in a cascade configuration. The
video signal, of which the level is subject to the video control as
stated above, comes into the base of Q102. C102 and R105
compensate high frequency. The video out signal (with flat re-
sponse) is amplified via Q103 and provided to the cathode of
CRT501.
The Vertical Control Process
The vertical control process consists of four stages: Vertical
Oscillator, Vertical Drive, Vertical Out and Flyback Generator.
These four stages are processed by (C201.
Vertical Oscillator
A sawtooth wave pattern is generated through C204, R204,
VR201 and an oscillator circuit, and synchronized with the neg-
ative-going vertical sync signal which is applied to pin 1 of
IC201.
Vertical Drive
À vertical sawtooth wave is AC coupled to the vertical drive amp
for linear amplification via C207.
Vertical Out
The vertical drive is linked to vertical out within IC 201. Vertical
output from Pin 8 of 1C201 is applied to DY501, and is AC cou-
pled by C209. Part of the output power at R206 is returned to a
vertical drive by the NF loop which is made up of C205, C206,
R207, and VR202, providing lineality compensation to the elec-
tric current which passes across the deflection yoke.
Fiyback Generator
A pulse that exceeds the source voltage (=20V) is generated
at the vertical output terminal, Pin 8 of i{C201, during retrace.
The Flyback pulse generator which consists of D201, C211 and
a part of 1IC201 boosts the source voltage for that period
accordingly.
Horizontal Sync Amp
A TTL compatible, positive-going horizontal drive signal from P-
6 is wave-shaped by C301 and R301, amplified by Q301 and
applied to the Pin 1 of IC301.
174
Phase Detector
The negative-going horizontal pulse is applied to a filter that
consists of R306, C306 and C310, used as a sawtooth wave for
comparison and is AC coupled via C305 and flows to Pin 3 of
IC301. The retrace part of horizontal sawtooth wave and the
horizontal sync signal are applied to a phase detector and exist
on Pin 4 of the phase detector. This output is used for the phase
control of DC through the filter, consisting of C307, C308 and
R305.
Horizontal Oscillator
A horizontal pulse is provided through the horizontal oscillator
circuit consisting of C311 and IC301. This oscillator signal is
phase-controlled according to the signal from the phase detec-
tor out (Pin 4 of C301). The horizontal oscillator frequency is
adjusted by VR301.
Horizontal Drive
The horizontal oscillator output (which is phase-controlled as
stated above), is applied to the horizontal drive buffer for am-
plification through IC301, and goes out on Pin 7 of IC301.
X-Ray Protection
When supplied with excessive source voltage (more than about
14V), the X-ray protection of IC301 works to terminate the hor-
izontal oscillator to prevent the CRT from emiting X-rays over
the regulated amount. High voltage causes CRT's to emit more
X-ray radiation than allowed.
Horizontal Out
Output power at Pin 7 of the horizontal control process IC is ap-
plied to Q303 through T301. Q303 operates a switching func-
tion with about 211. sec OFF and 42p sec ON. An electrical
current of sawtooth waves comes to DY501 through Q303 ac-
tuating a switching function and a dumper-diode, which helps to
deflect the electron beams.
Electrical current passes across DY501. This pulse voltage is
enhanced by the FBT, rectified, and used as the anode voltage
(11kV), focus voltage (450V) or video voltage (60V).
The output pulse at the collector of Q303 is rectified to be dou-
bled (— 160V) and provided as the voltage for internal bright-
ness and focus.
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DEFLECTION P.C.B. TOP VIEW
176
Parts List
9" Video Monitor 8799612, Model 4P Computer
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Item Sym Description Part Number
1 PCB Assembly, CRT U319ÿ5
1 Clip, Fuse 197393980A
1 Connector, Pin 19411878GA
1 Fuse, 2A 258V 251203794 A
1 Spring, Tension 434Й1 12 ВА
1 Socket, Pin 194919378A
1 Socket, Cylindrical [email protected]ÿA
1 Cord, Terminal 316010150B
1 Cord, Terminal 316B1P140A
С1й1 Capacitor, 4.7 uF, 50V Elec 20% CEBA (RB) 475M50V
c192 Capacitor, 128 pF, 50V Cer 19% CK45B1H121K
C103 Capacitor, 8.1 uF, 59V Mylar 10% CQ92M1H184K
C194 Capacitor, 22 uF, 19ÿV Elec 28% CED4C226M100V
C195 Capacitor, B.0022 uF, 500V Cer CK45 E2H222P
C281 Capacitor, #.822 uF, 58V Mylar 19% CQ92M1H223K
C282 Capacitor, 8.8022 uF, 58V Mylar 18% CQ92M1H223K
С2й3 Capacitor, 8.891 uF, 59V Mylar 19% [email protected]
C294 Capacitor, #.33 uF, 16V Tant 19% CS15E1C334K
C285 Capacitor, 4.7 uF, 16V Tant 14% CS15E1C475K
C246 Capacitor, 4.7 uF, 16V Tant 19% CS15El1C475K
C287 Capacitor, 33 uF, 16V Elec 20% CEB4C336M16V
C208 Capacitor, 33 uF, 16V Elec 20% CEB4C336M16V
C209 Capacitor, 338 uF, 35V Elec 28% CE(4C337M35V
C214 Capacitor, 8.833 uF, 50V Mylar 19% CQ92M1H333K
C211 Capacitor, 228 uF, 16V Elec 20% CEB4C227M16V
C212 Capacitor, 1008 uF, 16V Elec 24% [email protected]
C341 Capacitor, 228 pF, 58V Cer 18% CK45B1H221K
C302 Capacitor, 9.47 uF, 50V Elec 18% CEBA(RB) 474K509V
C383 Capacitor, 199 pr, 59v Cer 10% CK4581HI181K
c394 Capacitor, 9.022 uF, 50V Mylar 18% CQ92M1H223K
C395 Capacitor, 0.818 uF, 59V Mylar 19% CQ92M1H183K
C396 Capacitor, 2.818 ur, 58V Mylar 10% CQ92M1H183K
C397 Capacitor, 4.7 uF, 58V Elec 20% CEf4C475M50V
C3048 Capacitor, 9.41 uF, 58V Mylar 10% CQO92M1H183K
C3989 Capacitor, 220 uF, 16V Elec 28% CEd4C227M16V
C319 Capacitor, 18d pF, 58V Cer NPO CC45CH1H181J
C311 Capacitor, 2.9047 uF,59V Poly 5% CO92P1H4720J
C313 Capacitor, 1980 uF, 25V Elec 20% CEM4C198M25V
C314 Capacitor, 2.933 uF, 400V Poly 5% CQ92P2G333J
C315 Capacitor, 9.047 uF, 400V Poly 19% CQ92P2G473K
C316 Capacitor, 1 uF, 258V Elec 28% [email protected]
C317 Capacitor, 9.81 uF, 6308V Poly 18% CQ92P2J183K
181
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178
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