Triple-Speed Ethernet MegaCore Function User Guide

Triple-Speed Ethernet MegaCore Function User Guide

Triple-Speed Ethernet MegaCore

Function

User Guide

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TOC-2

Contents

About This MegaCore Function......................................................................... 1-1

About This MegaCore Function................................................................................................................1-1

Device Family Support................................................................................................................................1-1

Features......................................................................................................................................................... 1-2

10/100/1000 Ethernet MAC Versus Small MAC.....................................................................................1-3

High-Level Block Diagrams........................................................................................................................1-3

Example Applications..................................................................................................................................1-5

MegaCore Verification................................................................................................................................1-6

Optical Platform...............................................................................................................................1-7

Copper Platform...............................................................................................................................1-7

Performance and Resource Utilization.....................................................................................................1-7

Release Information...................................................................................................................................1-12

Getting Started with Altera IP Cores..................................................................2-1

Design Walkthrough................................................................................................................................... 2-1

Creating a New Quartus II Project................................................................................................ 2-1

Generating a Design Example or Simulation Model.................................................................. 2-2

Simulate the System.........................................................................................................................2-2

Compiling the Triple-Speed Ethernet MegaCore Function Design......................................... 2-2

Programming an FPGA Device..................................................................................................... 2-3

Generated Files.............................................................................................................................................2-3

Design Constraint File No Longer Generated............................................................................. 2-4

Parameter Settings.............................................................................................. 3-1

Parameter Settings....................................................................................................................................... 3-1

Core Configuration......................................................................................................................................3-1

Ethernet MAC Options...............................................................................................................................3-2

FIFO Options................................................................................................................................................3-4

Timestamp Options.....................................................................................................................................3-5

PCS/Transceiver Options........................................................................................................................... 3-5

Functional Description....................................................................................... 4-1

10/100/1000 Ethernet MAC....................................................................................................................... 4-1

MAC Architecture........................................................................................................................... 4-2

MAC Interfaces................................................................................................................................ 4-3

MAC Transmit Datapath................................................................................................................4-4

MAC Receive Datapath...................................................................................................................4-7

MAC Transmit and Receive Latencies........................................................................................4-12

FIFO Buffer Thresholds................................................................................................................ 4-13

Congestion and Flow Control......................................................................................................4-18

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TOC-3

Magic Packets................................................................................................................................. 4-19

MAC Local Loopback....................................................................................................................4-20

MAC Error Correction Code....................................................................................................... 4-20

MAC Reset......................................................................................................................................4-21

PHY Management (MDIO)......................................................................................................... 4-22

Connecting MAC to External PHYs........................................................................................... 4-24

1000BASE-X/SGMII PCS With Optional Embedded PMA................................................................4-28

1000BASE-X/SGMII PCS Architecture......................................................................................4-29

Transmit Operation.......................................................................................................................4-30

Receive Operation..........................................................................................................................4-31

Transmit and Receive Latencies...................................................................................................4-32

SGMII Converter........................................................................................................................... 4-32

Auto-Negotiation...........................................................................................................................4-33

Ten-bit Interface............................................................................................................................ 4-36

PHY Loopback............................................................................................................................... 4-37

PHY Power-Down.........................................................................................................................4-38

1000BASE-X/SGMII PCS Reset...................................................................................................4-39

Altera IEEE 1588v2 Feature......................................................................................................................4-40

IEEE 1588v2 Supported Configurations.....................................................................................4-40

IEEE 1588v2 Features....................................................................................................................4-41

IEEE 1588v2 Architecture.............................................................................................................4-42

IEEE 1588v2 Transmit Datapath................................................................................................. 4-42

IEEE 1588v2 Receive Datapath.................................................................................................... 4-43

IEEE 1588v2 Frame Format......................................................................................................... 4-43

Triple-Speed Ethernet with IEEE 1588v2 Design Example................................5-1

Software Requirements............................................................................................................................... 5-1

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components........................................... 5-2

Base Addresses..................................................................................................................................5-3

Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files............................................... 5-3

Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design............................................ 5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench .............................................................................5-4

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files.........................................................5-5

Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow....................................5-6

Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim

Simulator..................................................................................................................................... 5-7

Configuration Register Space............................................................................. 6-1

MAC Configuration Register Space.......................................................................................................... 6-1

Base Configuration Registers (Dword Offset 0x00 – 0x17)....................................................... 6-3

Statistics Counters (Dword Offset 0x18 – 0x38)....................................................................... 6-11

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)............................6-13

Supplementary Address (Dword Offset 0xC0 – 0xC7)............................................................ 6-15

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)................................................................. 6-16

IEEE 1588v2 Feature PMA Delay................................................................................................6-17

PCS Configuration Register Space.......................................................................................................... 6-18

Control Register (Word Offset 0x00)..........................................................................................6-20

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TOC-4

Status Register (Word Offset 0x01).............................................................................................6-22

Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)................................6-23

An_Expansion Register (Word Offset 0x06)............................................................................. 6-26

If_Mode Register (Word Offset 0x14)........................................................................................ 6-26

Register Initialization................................................................................................................................ 6-27

Triple-Speed Ethernet System with MII/GMII or RGMII.......................................................6-27

Triple-Speed Ethernet System with SGMII................................................................................6-30

Triple-Speed Ethernet System with 1000BASE-X Interface.................................................... 6-31

Interface Signals.................................................................................................. 7-1

Interface Signals........................................................................................................................................... 7-1

10/100/1000 Ethernet MAC Signals.............................................................................................. 7-2

10/100/1000 Multiport Ethernet MAC Signals..........................................................................7-13

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals.....................................7-18

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals...................7-22

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA

Signals........................................................................................................................................ 7-24

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded

PMA........................................................................................................................................... 7-27

1000BASE-X/SGMII PCS Signals................................................................................................7-36

1000BASE-X/SGMII PCS and PMA Signals..............................................................................7-41

Timing......................................................................................................................................................... 7-42

Avalon-ST Receive Interface........................................................................................................ 7-42

Avalon-ST Transmit Interface..................................................................................................... 7-44

GMII Transmit...............................................................................................................................7-45

GMII Receive..................................................................................................................................7-45

RGMII Transmit............................................................................................................................ 7-45

RGMII Receive............................................................................................................................... 7-46

MII Transmit..................................................................................................................................7-47

MII Receive.....................................................................................................................................7-47

IEEE 1588v2 Timestamp...............................................................................................................7-47

Design Considerations........................................................................................ 8-1

Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA.............................8-1

MAC and PCS With GX Transceivers..........................................................................................8-2

MAC and PCS With LVDS Soft-CDR I/O...................................................................................8-4

Sharing PLLs in Devices with LVDS Soft-CDR I/O................................................................................8-6

Sharing PLLs in Devices with GIGE PHY................................................................................................8-7

Sharing Transceiver Quads.........................................................................................................................8-7

Migrating From Old to New User Interface For Existing Designs....................................................... 8-7

Exposed Ports in the New User Interface.....................................................................................8-7

Timing Constraints............................................................................................. 9-1

Creating Clock Constraints........................................................................................................................ 9-1

Recommended Clock Frequency...............................................................................................................9-3

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TOC-5

Testbench...........................................................................................................10-1

Triple-Speed Ethernet Testbench Architecture ....................................................................................10-1

Testbench Components............................................................................................................................ 10-2

Testbench Verification..............................................................................................................................10-2

Testbench Configuration..........................................................................................................................10-3

Test Flow.....................................................................................................................................................10-3

Simulation Model...................................................................................................................................... 10-4

Generate the Simulation Model...................................................................................................10-4

Simulate the IP Core......................................................................................................................10-4

Simulation Model Files................................................................................................................. 10-5

Software Programming Interface..................................................................... 11-1

Driver Architecture................................................................................................................................... 11-1

Directory Structure....................................................................................................................................11-2

PHY Definition ......................................................................................................................................... 11-2

Using Multiple SG-DMA Descriptors.................................................................................................... 11-4

Using Jumbo Frames.................................................................................................................................11-4

API Functions.............................................................................................................................................11-5 alt_tse_mac_get_common_speed().............................................................................................11-5

alt_tse_mac_set_common_speed().............................................................................................11-6 alt_tse_phy_add_profile()............................................................................................................ 11-6 alt_tse_system_add_sys()............................................................................................................. 11-6

triple_speed_ethernet_init().........................................................................................................11-7

tse_mac_close()..............................................................................................................................11-8

tse_mac_raw_send()......................................................................................................................11-9 tse_mac_setGMII mode().............................................................................................................11-9

tse_mac_setMIImode()...............................................................................................................11-10 tse_mac_SwReset()...................................................................................................................... 11-10

Constants.................................................................................................................................................. 11-10

Ethernet Frame Format......................................................................................A-1

Basic Frame Format....................................................................................................................................A-1

VLAN and Stacked VLAN Frame Format.............................................................................................. A-2

Pause Frame Format...................................................................................................................................A-3

Pause Frame Generation................................................................................................................A-4

Simulation Parameters....................................................................................... B-1

Functionality Configuration Parameters................................................................................................. B-1

Test Configuration Parameters................................................................................................................. B-3

Time-of-Day (ToD) Clock.................................................................................. C-1

ToD Clock Features.................................................................................................................................... C-1

ToD Clock Device Family Support...........................................................................................................C-1

ToD Clock Performance and Resource Utilization................................................................................C-1

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TOC-6

ToD Clock Parameter Setting....................................................................................................................C-2

ToD Clock Interface Signals...................................................................................................................... C-3

ToD Clock Avalon-MM Control Interface Signals.................................................................... C-3

ToD Clock Avalon-ST Transmit Interface Signals.....................................................................C-4

ToD Clock Configuration Register Space................................................................................................C-5

Using ToD Clock SecondsH, SecondsL, and NanoSec Registers............................................. C-6

Adjusting ToD Clock Drift............................................................................................................ C-6

ToD Synchronizer.............................................................................................. D-1

ToD Synchronizer Block............................................................................................................................D-2

ToD Synchronizer Parameter Settings.....................................................................................................D-3

ToD Synchronizer Signals......................................................................................................................... D-4

ToD Synchronizer Common Clock and Reset Signals..............................................................D-4

ToD Synchronizer Interface Signals.............................................................................................D-5

Packet Classifier.................................................................................................. E-1

Packet Classifier Block................................................................................................................................ E-1

Packet Classifier Signals..............................................................................................................................E-2

Packet Classifier Common Clock and Reset Signals.................................................................. E-2

Packet Classifier Avalon-ST Interface Signals.............................................................................E-2

Packet Classifier Ingress Control Signals..................................................................................... E-3

Packet Classifier Control Insert Signals........................................................................................E-4

Packet Classifier Timestamp Field Location Signals.................................................................. E-5

Additional Information...................................................................................... F-1

Triple-Speed Ethernet IP Core Document Revision History................................................................ F-2

How to Contact Altera................................................................................................................................F-8

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About This MegaCore Function

The Altera

®

Triple-Speed Ethernet MegaCore

®

function is a configurable intellectual property (IP) core that complies with the IEEE 802.3 standard. The IP core was tested and successfully validated by the

University of New Hampshire (UNH) interoperability lab. It combines the features of a 10/100/1000-

Mbps Ethernet media access controller (MAC) and 1000BASE-X/SGMII physical coding sublayer (PCS) with an optional physical medium attachment (PMA).

Device Family Support

For new additions and enhancements to the latest Quartus II software and Altera IP, refer to the

What’s

New for Altera IP

page of the Altera website.

For a list of IP support for all device families, refer to the

All Intellectual Property

page of the Altera website.

Related Information

Altera Triple-Speed Ethernet MegaCore Function

1

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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9001:2008

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1-2

Features

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Features

• Complete triple-speed Ethernet IP: 10/100/1000-Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and embedded PMA.

• Successful validation from the University of New Hampshire (UNH) InterOperability Lab.

• 10/100/1000-Mbps Ethernet MAC features:

• Multiple variations: 10/100/1000-Mbps Ethernet MAC in full duplex, 10/100-Mbps Ethernet MAC in half duplex, 10/100-Mbps or 1000-Mbps small MAC (resource-efficient variant), and multiport

MAC that supports up to 24 ports.

• Support for basic, VLAN, stacked VLAN, and jumbo Ethernet frames. Also supports control frames including pause frames.

• Optional internal FIFO buffers, depth from 64 bytes to 256 Kbytes.

• Optional statistics counters.

• 1000BASE-X/SGMII PCS features:

• Compliance with Clause 36 of the IEEE standard 802.3.

• Optional embedded PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera devices that support this interface at 1.25-Gbps data rate.

• Support for auto-negotiation as defined in Clause 37.

• Support for connection to 1000BASE-X PHYs. Support for 10BASE-T, 100BASE-T, and

1000BASE-T PHYs if the PHYs support SGMII.

• MAC interfaces:

• Client side—8-bit or 32-bit Avalon

®

Streaming (Avalon-ST)

• Network side—medium independent interface (MII), gigabit medium independent interface

(GMII), or reduced gigabit medium independent interface (RGMII) on the network side. Optional loopback on these interfaces.

• Optional management data I/O (MDIO) master interface for PHY device management.

• PCS interfaces:

• Client side—MII or GMII

• Network side—ten-bit interface (TBI) for PCS without PMA; 1.25-Gbps serial interface for PCS with PMA implemented with serial transceiver or LVDS I/O and soft CDR in Altera devices that support this interface at 1.25-Gbps data rate.

• Programmable features via 32-bit configuration registers:

• FIFO buffer thresholds.

• Pause quanta for flow control.

• Source and destination MAC addresses.

• Address filtering on receive, up to 5 unicast and 64 multicast MAC addresses.

• Promiscuous mode—receive frame filtering is disabled in this mode.

• Frame length—in MAC only variation, up to 64 Kbytes including jumbo frames. In all variants containing 1000BASE-X/SGMII PCS, the frame length is up to 10 Kbytes.

• Optional auto-negotiation for the 1000BASE-X/SGMII PCS.

• Error correction code protection feature for internal memory blocks.

• Optional IEEE 1588v2 feature for 10/100/1000-Mbps Ethernet MAC with SGMII PCS and embedded serial PMA variation operating without internal FIFO buffer in full-duplex mode, 10/100/1000-Mbps

MAC with SGMII PCS and embedded LVDS I/O, or MAC only variation operating without internal

FIFO buffer in full-duplex mode. These features are supported in Arria V, Arria 10, Cyclone V, MAX

10, and Stratix V device families.

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10/100/1000 Ethernet MAC Versus Small MAC

10/100/1000 Ethernet MAC Versus Small MAC

Table 1-1: Feature Comparison between 10/100/1000 Ethernet MAC and Small MAC

Feature

Speed

External interfaces

Control interface registers

Synthesis options

10/100/1000 Ethernet MAC Small MAC

Triple speed (10/100/1000 Mbps) 10/100 Mbps or 1000 Mbps

MII/GMII or RGMII MII only for 10/100 Mbps small MAC, GMII or

RGMII for 1000 Mbps small MAC

Fully programmable Limited programmable options. The following options are fixed:

• Maximum frame length is fixed to 1518. Jumbo frames are not supported.

• FIFO buffer thresholds are set to fixed values.

• Store and forward option is not available.

• Interpacket gap is set to 12.

• Flow control is not supported; pause quanta is not in use.

• Checking of payload length is disabled.

• Supplementary MAC addresses are disabled.

• Padding removal is disabled.

• Sleep mode and magic packet detection is not supported.

Fully configurable Limited configurable options. The following options are NOT available:

• Flow control

• VLAN

• Statistics counters

• Multicast hash table

• Loopback

• TBI and 1.25 Gbps serial interface

• 8-bit wide FIFO buffers

1-3

High-Level Block Diagrams

High-level block diagrams of different variations of the Triple-Speed Ethernet MegaCore function.

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High-Level Block Diagrams

Figure 1-1: 10/100/1000-Mbps Ethernet MAC

Avalon-ST

(Transmit and Receive)

10/100/1000-Mbps

Ethernet MAC

Avalon-MM

(Management and Control)

Figure 1-2: Multi-port MAC

Avalon-MM

(Management and Control)

Avalon-ST

(Transmit and Receive)

Multi-Port MAC

10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

MII/GMII/RGMII

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Avalon-ST

(Transmit and Receive)

10/100/1000-Mbps

Ethernet MAC

MII/GMII/RGMII

Figure 1-3: 10/100/1000-Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA

Avalon-MM

(Management and Control)

Avalon-ST

(Transmit and

Receive)

MAC and PCS with Optional Embedded PMA

10/100/1000-Mbps

Ethernet MAC

MII/

GMII

1000BASE-X/SGMII

PCS

TBI

PMA

(Optional)

1.25-Gbps

Serial

Figure 1-4: 1000BASE-X/SGMII PCS with Optional PMA

MII/GMII

PCS with Optional Embedded PMA

1000BASE-X/SGMII

PCS

TBI

PMA

(Optional)

1.25-Gbps

Serial

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Figure 1-5: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Altera Device

Triple-Speed Ethernet MegaCore Function

Example Applications

1-5

User

Application

10/100/1000-Mbps

Ethernet MAC

Gigabit or Fast

Ethernet PHY

Device

Copper

Management

Application

Host Interface MDIO Master

Example Applications

This section shows example applications of different variations of the Triple-Speed Ethernet MegaCore function.

The 10/100/1000-Gbps Ethernet MAC only variation can serve as a bridge between the user application and standard fast or gigabit Ethernet PHY devices.

Figure 1-6: Stand-Alone 10/100/1000 Mbps Ethernet MAC

Example application using this variation for a copper network.

Altera Device

Triple-Speed Ethernet MegaCore Function

User

Application

10/100/1000-Mbps

Ethernet MAC

Gigabit or Fast

Ethernet PHY

Device

Copper

Management

Application

Host Interface MDIO Master

When configured to include the 1000BASE-X/SGMII PCS function, the MegaCore function can seamlessly connect to any industry standard gigabit Ethernet PHY device via a TBI. Alternatively, when the 1000BASE-X/SGMII PCS function is configured to include an embedded PMA, the MegaCore function can connect directly to a gigabit interface converter (GBIC), small form-factor pluggable (SFP) module, or an SGMII PHY.

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MegaCore Verification

Figure 1-7: 10/100/1000 Mbps Ethernet MAC and 1000BASE-X PCS with Embedded PMA

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Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA.

The PMA block connects to an off-the-shelf GBIC or SFP module to communicate directly over the optical link.

Altera Device

Triple-Speed Ethernet MegaCore Function

10/100/1000-Mbps

Ethernet MAC

GMII

1000BASE-X

PCS

TBI

PMA

Fiber

Figure 1-8: 10/100/1000 Mbps Ethernet MAC and SGMII PCS with Embedded PMA—GMII/MII to 1.25-

Gbps Serial Bridge Mode

Example application using the Triple-Speed Ethernet MegaCore function with 1000BASE-X and PMA, in which the PCS function is configured to operate in SGMII mode and acts as a GMII-to-SGMII bridge. In this case, the transceiver I/O connects to an off-the-shelf Ethernet PHY that supports SGMII (10BASE-T,

100BASE-T, or 1000BASE-T Ethernet PHY).

Altera Device

Triple-Speed Ethernet MegaCore Function

10/100/

1000-Mbps

Ethernet MAC

MII/GMII

SGMII PCS

TBI

PMA

Gbps

SGMII

10/100/1000

BASE-T PHY

Copper

MegaCore Verification

For each release, Altera verifies the Triple-Speed Ethernet MegaCore function through extensive simulation and internal hardware verification in various Altera device families. The University of New

Hampshire (UNH) InterOperability Lab also successfully verified the MegaCore function prior to its release.

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Optical Platform

Altera used a highly parameterizeable transaction-based testbench to test the following aspects of the

MegaCore function:

• Register access

• MDIO access

• Frame transmission and error handling

• Frame reception and error handling

• Ethernet frame MAC address filtering

• Flow control

• Retransmission in half-duplex

Altera has also validated the Triple-Speed Ethernet MegaCore function in both optical and copper platforms using the following development kits:

• Altera Nios II Development Kit, Cyclone II Edition (2C35)

• Altera Stratix III FPGA Development Kit

• Altera Stratix IV FPGA Development Kit

• Quad 10/100/1000 Marvell PHY

• MorethanIP 10/100 and 10/100/1000 Ethernet PHY Daughtercards

1-7

Optical Platform

In the optical platform, the 10/100/1000 Mbps Ethernet MAC, 1000BASE-X/SGMII PCS, and PMA functions are instantiated.

The FPGA application implements the Ethernet MAC, the 1000BASE-X PCS, and an internal system using Ethernet connectivity. This internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an optical module is provided through an external SFP optical module. Certified 1.25

GBaud optical SFP transceivers are Finisar 1000BASE-SX FTLF8519P2BNL, Finisar 1000BASE-LX

FTRJ-1319-3, and Avago Technologies AFBR-5710Z.

Copper Platform

In the copper platform, Altera tested the Triple-Speed Ethernet MegaCore function with an external

1000BASE-T PHY devices. The MegaCore function is connected to the external PHY device using MII,

GMII, RGMII, and SGMII, in conjunction with the 1000BASE-X/SGMII PCS and PMA functions.

A 10/100/1000 Mbps Ethernet MAC and an internal system are implemented in the FPGA. The internal system retrieves all frames received by the MAC function and returns them to the sender by manipulating the MAC address fields, thus implementing a loopback. A direct connection to an Ethernet link is provided through a combined MII to an external PHY module. Certified 1.25 GBaud copper SFP transceivers are Finisar FCMJ-8521-3, Methode DM7041, and Avago Technologies ABCU-5700RZ.

Performance and Resource Utilization

In the following tables, the f

MAX

of the configurations is more than 125 MHz.

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Performance and Resource Utilization

Table 1-2: Arria II GX Performance and Resource Utilization

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The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the Arria

II GX device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting an Arria II GX (EP2AGX260EF29I3) device with speed grade -3.

MegaCore Function Settings FIFO Buffer

Size (Bits)

Combina‐ tional

ALUTs

Logic

Registers

Memory

(M9K Blocks/

M144K Blocks/

MLAB Bits)

2048x32 3357 3947 26/0/1828 10/100/1000-Mbps

Ethernet MAC

RGMII

All MAC options enabled

Full and half-duplex modes supported

8-port 10/100/

1000-Mbps

Ethernet MAC

1000BASE-X/

SGMII PCS

MII/GMII

All MAC options enabled

Full and half-duplex modes supported

1000BASE-X

1000BASE-X

SGMII bridge enabled

PMA block (GXB)

20201

624

1191

22292

661

1214

32/0/14624

0/0/0

1/0/160

Table 1-3: Stratix IV Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the

Stratix IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix IV GX (EP4SGX530NF45C4) device with speed grade -4.

MegaCore

Function

Settings FIFO Buffer

Size (Bits)

Combina‐ tional

ALUTs

Logic

Registers

Memory

(M9K Blocks/

M144K Blocks/

MLAB Bits)

2048x32 1410 2127 12/1/1408

10/100-

Mbps Small

MAC

1000-Mbps

Small MAC

MII

Full and half-duplex modes supported

MII

All MAC options enabled

GMII

All MAC options enabled

RGMII

All MAC options enabled

2048x32

2048x32

2048x32

1157

1160

1170

1894

1827

1861

12/1/128

12/1/176

12/1/176

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MegaCore

Function

Settings

10/100/

1000-Mbps

Ethernet

MAC

MII/GMII

Full and half-duplex modes supported

MII/GMII

All MAC options enabled

RGMII

All MAC options enabled

12-port 10/

100/1000-

Mbps

Ethernet

MAC

24-port 10/

100/1000-

Mbps

Ethernet

MAC

MII/GMII

All MAC options enabled

1000BASE-

X/SGMII

PCS

10/100/

1000-Mbps

Ethernet

MAC and

1000BASE-

X/SGMII

PCS

1000BASE-X

1000BASE-X

SGMII bridge enabled

1000BASE-X

SGMII bridge enabled

PMA block (LVDS_IO)

1000BASE-X

SGMII bridge enabled

PMA block (GXB)

All MAC options enabled

SGMII bridge enabled

FIFO Buffer

Size (Bits)

2048x8

2048x32

2048x32

Performance and Resource Utilization

Combina‐ tional

ALUTs

2721

3201

3345

3125

Logic

Registers

3395

3977

4425

3994

1-9

Memory

(M9K Blocks/

M144K Blocks/

MLAB Bits)

0/0/3364

8/0/3620

12/1/3364

12/1/2084

2048x32 3133 4021 12/1/2084

— 27215 34372 0/0/25008

54123

2048×32 3971

624

808

819

1189

68404

661

986

1057

1212

4950

0/0/50016

0/0/0

2/0/0

2/0/0

1/0/160

14/1/2084

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Performance and Resource Utilization

Table 1-4: Cyclone IV GX Performance and Resource Utilization

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The estimated resource utilization and performance of the Triple Speed Ethernet MegaCore function for the

Cyclone IV device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Cyclone IV GX (EP4CGX150DF27C7) device with speed grade -7.

MegaCore

Function

Settings FIFO Buffer

Size (Bits)

Logic

Elements

Logic

Registers

Memory

(M9K Blocks/ Mi44K

Blocks/ MLAB Bits)

1000-Mbps

Small MAC

10/100/

1000-Mbps

Ethernet

MAC

4-port 10/

100/

1000-Mbps

Ethernet

MAC

RGMII

Only full-duplex mode supported

MII/GMII

Full and half-duplex modes supported

MII/GMII

All MAC options enabled

Full and half-duplex modes supported

2048x32

2048x32

2161

5614

17017

1699

3666

10612

24/0/0

31/0/0

36/0/0

1000BASE-

X/SGMII

PCS

1000BASE-X

1000BASE-X

SGMII bridge enabled

PMA block (GXB)

1149

2001

661

1127

0/0/0

2/0/0

Table 1-5: Stratix V Performance and Resource Utilization

The estimated resource utilization and performance of the Triple-Speed Ethernet MegaCore function for the

Stratix V device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX (5SGXMA7N3F45C3) device with speed grade -3.

MegaCore

Function

Settings FIFO Buffer

Size (Bits)

Combina‐ tional

ALUTs

Logic

Registers

Memory

(M20K Blocks/

MLAB Bits)

10/100-

Mbps Small

MAC

1000-Mbps

Small MAC

MII

Full and half-duplex modes supported

MII

All MAC options enabled

GMII

All MAC options enabled

RGMII

All MAC options enabled

2048x32

2048x32

2048x32

2048x32

1261

1261

1227

1237

2018

2018

1959

1984

11/0

11/0

10/128

10/128

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MegaCore

Function

Settings

10/100/

1000-Mbps

Ethernet

MAC

MII/GMII

Full and half-duplex modes supported

MII/GMII

All MAC options enabled

RGMII

All MAC options enabled

12-port 10/

100/1000-

Mbps

Ethernet

MAC

24-port 10/

100/1000-

Mbps

Ethernet

MAC

MII/GMII

All MAC options enabled

1000BASE-

X/SGMII

PCS

10/100/

1000-Mbps

Ethernet

MAC and

1000BASE-

X/SGMII

PCS

1000BASE-X

1000BASE-X

SGMII bridge enabled

1000BASE-X

SGMII bridge enabled

PMA block (LVDS_IO)

1000BASE-X

SGMII bridge enabled

PMA block (GXB)

(reconfig controller has been compiled together with

1000BASE-X SGMII bridge enabled PMA block (GXB))

Combinational ALUTs =1441,

Logic Registers = 903 and

Memory(M20K Block/MLAB

Bits) = 4/~2048

All MAC options enabled

SGMII bridge enabled

Default MAC option

SGMII bridge enabled

IEEE 1588v2 feature enabled

FIFO Buffer

Size (Bits)

2048x8

2048x32

2048x32

Performance and Resource Utilization

Combina‐ tional

ALUTs

3137

3627

3777

3454

Logic

Registers

4298

4971

5145

4928

1-11

Memory

(M20K Blocks/

MLAB Bits)

5/2048

10/2048

16/2048

16/768

2048x32 3466 4933 16/768

— 35303 48365 60/24576

2048×32

0

70079

614

839

857

2203

4306

5062

96092

786

1160

1250

1991

6132

5318

120/49152

0/0

0/480

0/480

5/2208

16/1248

4/1536

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Release Information

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Release Information

Table 1-6: Triple-Speed Ethernet MegaCore Function Release Information

Version

Release Date

Ordering Code

Product ID(s)

Item Description

15.0

June 2015

IP-TRIETHERNET

00BD (Triple-Speed Ethernet MegaCore function)

0104 (IEEE 1588v2)

6AF7 Vendor ID(s)

Altera verifies that the current version of the Quartus ® II software compiles the previous version of each

MegaCore function. The

MegaCore IP Library Release Notes and Errata

report any exceptions to this verification. Altera does not verify compilation with MegaCore function versions older than one release.

Related Information

MegaCore IP Library Release Notes and Errata

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Design Walkthrough

This walkthrough explains how to create a Triple-Speed Ethernet MegaCore function design using Qsys in the Quartus II software. After you generate a custom variation of the Triple-Speed Ethernet MegaCore function, you can incorporate it into your overall project.

This walkthrough includes the following steps:

1.

Creating a New Quartus II Project

on page 2-1

2.

Generating a Design Example or Simulation Model

on page 2-2

3.

Simulate the System

on page 2-2

4.

Compiling the Triple-Speed Ethernet MegaCore Function Design

on page 2-2

5.

Programming an FPGA Device

on page 2-3

Creating a New Quartus II Project

You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity.

To create a new project, follow these steps:

1. From the Windows Start menu, select Programs > Altera > Quartus II <version> to launch the

Quartus II software. Alternatively, you can use the Quartus II Web Edition software.

2. On the File menu, click New Project Wizard.

3. In the New Project Wizard: Directory, Name, Top-Level Entity page, specify the working directory, project name, and top-level design entity name. Click Next.

4. In the New Project Wizard: Add Files page, select the existing design files (if any) you want to include in the project.

(1) Click Next.

2

(1) To include existing files, you must specify the directory path to where you installed the MegaCore function.

You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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ISO

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Registered

2-2

Generating a Design Example or Simulation Model

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5. In the New Project Wizard: Family & Device Settings page, select the device family and specific device you want to target for compilation. Click Next.

6. In the EDA Tool Settings page, select the EDA tools you want to use with the Quartus II software to develop your project.

7. The last page in the New Project Wizard window shows the summary of your chosen settings. Click

Finish to complete the Quartus II project creation.

Generating a Design Example or Simulation Model

After you have parameterized the MegaCore function, you can also generate a design example, in addition to generating the MegaCore component files.

In the parameter editor, click Example Design to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the

<variation name>_testbench directory.

Note: Generating a design example can increase processing time.

You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

Related Information

Testbench

More information about the MegaCore function simulation model.

Quartus II Help

More information about the Quartus II software, including virtual pins.

Simulate the System

During system generation, Qsys generates a functional simulation model—or design example that includes a testbench—which you can use to simulate your system in any Altera-supported simulation tool.

Related Information

Quartus II Software Release Notes

More information about the latest Altera-supported simulation tools.

Simulating Altera Designs

More information in volume 3 of the Quartus II Handbook about simulating Altera IP cores.

System Design with Qsys

More information in volume 1 of the Quartus II Handbook about simulating Qsys systems.

Compiling the Triple-Speed Ethernet MegaCore Function Design

Before you begin

Refer to

Design Considerations

on page 8-1 chapter before compiling the Triple-Speed Ethernet

MegaCore function design.

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Programming an FPGA Device

2-3

To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You can use the generated .qip file to include relevant files into your project.

Related Information

Quartus II Help

More information about compilation in Quartus II software.

Programming an FPGA Device

After successfully compiling your design, program the targeted Altera device with the Quartus II

Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer to the Device Programming section in volume 3 of the Quartus II Handbook.

Related Information

Device Programming

Generated Files

The type of files generated in your project directory and their names may vary depending on the custom variation of the MegaCore function you created.

Table 2-1: Generated Files

File Name

<variation_name>

.v

or

<variation_name>

.vhd

<variation_name>

.bsf

Description

A MegaCore function variation file, which defines a VHDL or

Verilog HDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the

Quartus II software.

Quartus II symbol file for the MegaCore function variation.

You can use this file in the Quartus II block diagram editor.

Contains Quartus II project information for your MegaCore function variations.

<variation_name>

.qip

and

<variation_name>.sip

<variation_name>

<variation_name>

.cmp

.spd

A VHDL component declaration file for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore.

Simulation Package Descriptor file. Specifies the files required for simulation.

Testbench Files (in <variation_name>_testbench folder)

README.txt

Read me file for the testbench design.

generate_sim.qpf and

generate_sim.qsf

generate_sim_verilog.tcl and

generate_sim_vhdl.tcl

Dummy Quartus II project and project setting file. Use this to start the Quartus II in the correct directory to launch the

generate_sim_verilog.tcl

and

generate_sim_vhdl.tcl

files.

A Tcl script to generate the DUT VHDL or Verilog HDL simulation model for use in the testbench.

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Design Constraint File No Longer Generated

File Name

/testbench_vhdl/<variation_name>/

<variation_name>_tb.vhd or

/testbench_verilog/<variation_name>/

<variation_name>_tb.v

/testbench_vhdl/<variation_name>/

run_

<variation_name>_tb.tcl or

/testbench_verilog/<variation_name>/

run_

<variation_name>_tb.tcl

/testbench_vhdl/<variation_name>/

<variation_name>_wave.do or

/testbench_verilog/<variation_name>/

<variation_name>_wave.do

/testbench_vhdl/models or

/testbench_verilog/models

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Description

VHDL or Verilog HDL testbench that exercises your MegaCore function variation in a third party simulator.

A Tcl script for use with the ModelSim simulation software.

A signal tracing macro script used with the ModelSim simulation software to display testbench signals.

A directory containing VHDL and Verilog HDL models of the

Ethernet generators and monitors used by the generated testbench.

Design Constraint File No Longer Generated

For a new Triple-Speed Ethernet MegaCore function created using the Quartus II software ACDS 13.0 or later, the Quartus II software no longer generate the <variation_name>

_constraints.tcl

file that contains the necessary constraints for the compilation of your MegaCore Function variation.

Table 2-2

lists the recommended Quartus II pin assignments that you can set in your design.

Table 2-2: Recommended Quartus II Pin Assignments

Quartus II Pin

Assignment

FAST_

INPUT_

REGISTER

FAST_

OUTPUT_

REGISTER

IO_

STANDARD

IO_

STANDARD

Assignment

Value

ON

ON

1.4-V PCML or 1.5-V

PCML

LVDS

Description

To optimize I/O timing for MII,

GMII and TBI interface.

To optimize I/O timing for MII,

GMII and TBI interface.

I/O standard for GXB serial input and output pins.

I/O standard for LVDS/IO serial input and output pins.

Design Pin

MII, GMII, RGMII, TBI input pins.

MII, GMII, RGMII, TBI output pins.

GXB transceiver serial input and output pins.

LVDS/IO transceiver serial input and output pins.

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Quartus II Pin

Assignment

GLOBAL_

SIGNAL

GLOBAL_

SIGNAL

GLOBAL_

SIGNAL

Design Constraint File No Longer Generated

2-5

Assignment

Value

Description

Global clock To assign clock signals to use the global clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

Design Pin

• ref_clk

for MAC and PCS with LVDS/IO (with internal

FIFO).

• clk

and reset

pins for MAC only (without internal FIFO).

• clk

and ref_clk

input pins for MAC and PCS with transceiver (without internal

FIFO).

Regional clock

OFF

To assign clock signals to use the regional clock network. Use this setting to guide the Quartus II in the fitter process for better timing closure.

To prevent a signal to be used as a global signal.

• rx_clk <n>

and internal FIFO).

tx_clk <n> input pins for MAC only using

MII/GMII interface (without

• rx_clk <n>

input pin for

MAC only using RGMII interface (without internal

FIFO).

Signals for Arria V devices:

*reset_ff_wr

and

*reset_ ff_rd

*| altera_tse_reset_ synchronizer_chain_out

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Parameter Settings

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Parameter Settings

You customize the Triple-Speed Ethernet MegaCore function by specifying parameters using the Triple-

Speed Ethernet parameter editor, launched from Qsys in the Quartus II software. The customization enables specific core features during synthesis and generation.

This chapter describes the parameters and how they affect the behavior of the MegaCore function. Each section corresponds to a page in the Parameter Settings tab in the parameter editor interface.

Core Configuration

Table 3-1: Core Configuration Parameters

Name

Core Variation

Enable ECC protection

Value

• 10/100/1000 Mb

Ethernet MAC

• 10/100/1000 Mb

Ethernet MAC with

1000BASE-X/SGMII

PCS

• 1000BASE-X/SGMII

PCS only

• 1000 Mb Small MAC

• 10/100 Mb Small MAC

On/Off

Description

Determines the primary blocks to include in the variation.

Turn on this option to enable ECC protection for internal memory blocks.

3

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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101 Innovation Drive, San Jose, CA 95134

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Ethernet MAC Options

Name

Interface

Use clock enable for MAC

On/Off

Value

• MII

• GMII

• RGMII

• MII/GMII

Use internal FIFO On/Off

Number of ports 1, 4, 8, 12, 16, 20, and 24

Transceiver type • None

• LVDS I/O

• GXB

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Description

Determines the Ethernet-side interface of the MAC block.

MII—The only option available for 10/100 Mb

Small MAC core variations.

GMII—Available only for 1000 Mb Small MAC core variations.

RGMII—Available for 10/100/1000 Mb Ethernet

MAC and 1000 Mb Small MAC core variations.

MII/GMII—Available only for 10/100/1000 Mb

Ethernet MAC core variations. If this is selected, media independent interface (MII) is used for the

10/100 interface, and gigabit media independent interface (GMII) for the gigabit interface.

Turn on this option to include clock enable signals for the MAC. This option is only applicable for 10/100/

1000 Mb Ethernet MAC and 1000 Mb Small MAC core variations.

Turn on this option to include internal FIFO buffers in the core. You can only include internal FIFO buffers in single-port MACs.

Specifies the number of Ethernet ports supported by the IP core. This parameter is enabled if the parameter

Use internal FIFO is turned off. A multiport MAC does not support internal FIFO buffers.

This option is only available for variations that include the PCS block.

None—the PCS block does not include an integrated transceiver module. The PCS block implements a ten-bit interface (TBI) to an external

SERDES chip.

LVDS I/O or GXB—the MegaCore function includes an integrated transceiver module to implement a 1.25 Gbps transceiver. Respective GXB module is included for target devices with GX transceivers. For target devices with LVDS I/O including Soft-CDR such as Stratix III, the

ALTLVDS module is included.

Ethernet MAC Options

These options are enabled when your variation includes the MAC function. In small MACs, only the following options are available:

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Enable MAC 10/100 half duplex support (10/100 Small MAC variations)

Align packet headers to 32-bit boundary (10/100 and 1000 Small MAC variations)

Table 3-2: MAC Options Parameters

Ethernet MAC Options

Name

Ethernet MAC Options

Enable MAC 10/

100 half duplex support

On/Off

Enable local loopback on MII/

GMII/RGMII

On/Off

Value Description

Turn on this option to include support for half duplex operation on 10/100 Mbps connections.

Enable supplemental

MAC unicast addresses

Include statistics counters

On/Off

On/Off

3-3

Turn on this option to enable local loopback on the

MAC’s MII, GMII, or RGMII interface. If you turn on this option, the loopback function can be dynamically enabled or disabled during system operation via the

MAC configuration register.

Turn on this option to include support for supplemen‐ tary destination MAC unicast addresses for fast hardware-based received frame filtering.

Enable 64-bit statistics byte counters

Include multicast hashtable

Align packet headers to 32-bit boundary

On/Off

On/Off

On/Off

Turn on this option to include support for simple network monitoring protocol (SNMP) management information base (MIB) and remote monitoring

(RMON) statistics counter registers for incoming and outgoing Ethernet packets.

By default, the width of all statistics counters are 32 bits.

Turn on this option to extend the width of selected statistics counters— aOctetsTransmittedOK

, aOctetsReceivedOK

, and etherStatsOctets

—to 64 bits.

Turn on this option to implement a hash table, a fast hardware-based mechanism to detect and filter multicast destination MAC address in received

Ethernet packets.

Turn on this option to include logic that aligns all packet headers to a 32-bit boundary. This helps reduce software overhead processing in realignment of data buffers.

This option is available for MAC variations with 32 bits wide internal FIFO buffers and MAC variations without internal FIFO buffers.

You must turn on this option if you intend to use the

Triple-Speed Ethernet MegaCore function with the

Interniche TCP/IP protocol stack.

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FIFO Options

Name

Enable full-duplex flow control

On/Off

Enable VLAN detection

On/Off

Value

Enable magic packet detection

MDIO Module

Include MDIO module (MDC/

MDIO)

On/Off

On/Off

Host clock divisor

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Description

Turn on this option to include the logic for full-duplex flow control that includes pause frames generation and termination.

Turn on this option to include the logic for VLAN and stacked VLAN frame detection. When turned off, the

MAC does not detect VLAN and staked VLAN frames.

The MAC forwards these frames to the user applica‐ tion without processing them.

Turn on this option to include logic for magic packet detection (Wake-on LAN).

Turn on this option if you want to access external PHY devices connected to the MAC function. When turned off, the core does not include the logic or signals associated with the MDIO interface.

Clock divisor to divide the MAC control interface clock to produce the MDC clock output on the MDIO interface. The default value is 40.

For example, if the MAC control interface clock frequency is 100 MHz and the desired MDC clock frequency is 2.5 MHz, a host clock divisor of 40 should be specified.

Altera recommends that the division factor is defined such that the MDC frequency does not exceed 2.5

MHz.

FIFO Options

The FIFO options are enabled only for MAC variations that include internal FIFO buffers.

Table 3-3: FIFO Options Parameters

Name

Width

Width

Value

8 Bits and 32 Bits

Parameter

Determines the data width in bits of the transmit and receive FIFO buffers.

Depth

Transmit

Receive

Between 64 and 64K Determines the depth of the internal FIFO buffers.

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Timestamp Options

Table 3-4: Timestamp Options Parameters

Name

Timestamp

Enable timestamping

Enable PTP 1-step clock

On/Off

On/Off

Timestamp fingerprint width

Value

Timestamp Options

3-5

Parameter

Turn on this parameter to enable time stamping on the transmitted and received frames.

Turn on this parameter to insert timestamp on PTP messages for 1-step clock based on the TX Timestamp

Insert Control interface.

This parameter is disabled if you do not turn on

Enable timestamping.

Use this parameter to set the width in bits for the timestamp fingerprint on the TX path. The default value is 4 bits.

PCS/Transceiver Options

The PCS/Transceiver options are enabled only if your core variation includes the PCS function.

Table 3-5: PCS/Transceiver Options Parameters

Name

PCS Options

PHY ID (32 bit)

Enable SGMII bridge

On/Off

Value Parameter

Configures the PHY ID of the PCS block.

Turn on this option to add the SGMII clock and rateadaptation logic to the PCS block. This option allows you to configure the PCS either in SGMII mode or

1000Base-X mode. If your application only requires

1000BASE-X PCS, turning off this option reduces resource usage.

In Cyclone IV GX devices,

REFCLK[0,1]

and

REFCLK[4,5]

cannot connect directly to the GCLK network. If you enable the SGMII bridge, you must connect ref_clk

to an alternative dedicated clock input pin.

Transceiver Options—apply only to variations that include GXB transceiver blocks

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PCS/Transceiver Options

Name

Export transceiver powerdown signal

On/Off

Value

Enable transceiver dynamic reconfi‐ guration

On/Off

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Parameter

This option is not supported in Stratix V, Arria V,

Arria V GZ, and Cyclone V devices.

Turn on this option to export the powerdown signal of the GX transceiver to the top-level of your design.

Powerdown is shared among the transceivers in a quad. Therefore, turning on this option in multiport

Ethernet configurations maximizes efficient use of transceivers within the quad.

Turn off this option to connect the powerdown signal internally to the PCS control register interface. This connection allows the host processor to control the transceiver powerdown in your system.

This option is always turned on in devices other than

Arria GX and Stratix II GX. When this option is turned on, the MegaCore function includes the dynamic reconfiguration signals.

For designs targeting devices other than Arria V,

Cyclone V, Stratix V, and Arria 10, Altera recommends that you instantiate the ALTGX_RECONFIG megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation.

For Arria V, Cyclone V, and Stratix V designs, Altera recommends that you instantiate the Transceiver

Reconfiguration Controller megafunction and connect the megafunction to the dynamic reconfiguration signals to enable offset cancellation. The transceivers in the Arria V, Cyclone V, and Stratix V designs are configured with Altera Custom PHY IP core. The

Custom PHY IP core require two reconfiguration interfaces for external reconfiguration controller. For more information on the reconfiguration interfaces required, refer to the

Altera Transceiver PHY IP Core

User Guide

and the respective device handbook.

For more information about quad sharing considera‐ tions, refer to

Sharing PLLs in Devices with GIGE

PHY

on page 8-7 .

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PCS/Transceiver Options

3-7

Name

Starting channel number

0284

Value Parameter

Specifies the channel number for the GXB transceiver block. In a multiport MAC, this parameter specifies the channel number for the first port. Subsequent channel numbers are in four increments.

In designs with multiple instances of GXB transceiver block (multiple instances of Triple-Speed Ethernet IP core with GXB transceiver block or a combination of

Triple-Speed Ethernet IP core and other IP cores),

Altera recommends that you set a unique starting channel number for each instance to eliminate conflicts when the GXB transceiver blocks share a transceiver quad.

This option is not supported in Arria V, Cyclone V,

Stratix V, and Arria 10 devices. For these devices, the channel numbers depends on the dynamic reconfigu‐ ration controller.

Series V GXB Transceiver Options

TX PLLs type

Enable SyncE

Support

TX PLL clock network

CMU

ATX

On/Off

x1

xN

This option is only available for variations that include the PCS block for Stratix V and Arria V GZ devices.

Specifies the TX phase-locked loops (PLLs) type—

CMU or ATX—in the GXB transceiver for Series V devices.

Turn on this option to enable SyncE support by separating the TX PLL and RX PLL reference clock.

This option is only available for variations that include the PCS block for Arria V and Cyclone V devices.

Specifies the TX PLL clock network type.

Arria 10 GXB Transceiver Options

Enable Arria 10 transceiver dynamic reconfi‐ guration

On/Off Turn on this option for the MegaCore function to include the dynamic reconfiguration signals.

Note: You must configure the Arria 10 Transceiver ATX PLL with an output clock frequency of 1250.0

MHz (instead of applying the default value of 625 MHz) when using the Arria 10 Transceiver

Native PHY with the Triple-Speed Ethernet IP core.

Refer to the respective device handbook for more information on dynamic reconfiguration in Altera devices.

Related Information

Arria 10 Transceiver PHY User Guide

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The Triple-Speed Ethernet MegaCore function includes the following functions:

• 10/100/1000 Ethernet MAC

• 1000BASE-X/SGMII PCS With Optional Embedded PMA

• Altera IEEE 1588v2

10/100/1000 Ethernet MAC

The Altera 10/100/1000 Ethernet MAC function handles the flow of data between user applications and

Ethernet network through an internal or external Ethernet PHY. Altera offers the following MAC variations:

• Variations with internal FIFO buffers—supports only single port.

• Variations without internal FIFO buffers—supports up to 24 ports and the ports can operate at different speeds.

• Small MAC—provides basic functionalities of a MAC function using minimal resources.

Refer to

10/100/1000 Ethernet MAC Versus Small MAC

on page 1-3 for a feature comparison between the 10/100/1000 Ethernet MAC and small MAC.

The MAC function supports the following Ethernet frames: basic, VLAN and stacked VLAN, jumbo, and control frames. For more information about these frame formats, refer to

Ethernet Frame Format

on

page 12-1.

4

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

4-2

MAC Architecture

MAC Architecture

Figure 4-1: 10/100/1000 Ethernet MAC With Internal FIFO Buffers

System Side

10/100/1000 Ethernet MAC with Internal FIFO Buffers

Receiver Control

MAC Receive

Interface

(Avalon-ST)

CRC Check Frame

Termination

MAC Transmit

Interface

(Avalon-ST)

Transmitter Control

CRC

Generation

Pause

Generation

Ethernet Side

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Magic Packet

Detection

Configuration and

Statistics

Control Interface

(Avalon-MM)

MDIO Master

The FIFO buffers, which you can configure to 8- or 32-bits wide, store the transmit and receive data. The buffer width determines the data width on the Avalon-ST receive and transmit interfaces. You can configure the FIFO buffers to operate in cut-through or store-and-forward mode using the rx_section_full

and tx_section_full

registers.

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Figure 4-2: Multiport MAC Without Internal FIFO Buffers

System Side

(Avalon-ST)

Port 0

Multiport MAC (Without Internal FIFO Buffers) Ethernet Side

Receiver Control

Loopback

(MII/GMII/RGMII)

CRC Check

Transmit / Receive

Interfaces

Transmitter Control

CRC Generation

MAC Interfaces

4-3

To/From

External PHY

Transmit / Receive

Interfaces

Port n

Receiver Control

CRC Check

Transmitter Control

CRC Generation

Loopback

To/From

External PHY

MDIO Master

Avalon-MM Interface

In a multiport MAC, the instances share the MDIO master and some configuration registers. You can use the Avalon-ST Multi-Channel Shared Memory FIFO core in Qsys to store the transmit and receive data.

Related Information

MAC Configuration Register Space

on page 6-1

MAC Interfaces

The MAC function implements the following interfaces:

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MAC Transmit Datapath

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• Avalon-ST on the system side.

• Avalon-ST sink port on transmit with the following properties:

• Fixed data width, 8 bits, in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.

• Packet support using start-of-packet (SOP) and end-of-packet (EOP) signals, and partial final packet signals.

• Error reporting.

• Variable-length ready latency specified by the tx_almost_full

register.

• Avalon-ST source port on receive with the following properties:

• Fixed data width of 8 bits in MAC variations without internal FIFO buffers; configurable data width, 8 or 32 bits, in MAC variations with internal FIFO buffers.

• Backpressure is supported only in MAC variations with internal FIFO buffers. Transmission stops when the level of the FIFO buffer reaches the respective programmable thresholds.

• Packet support using SOP and EOP signals, and partial final packet signals.

• Error reporting.

• Ready latency is zero in MAC variations without internal FIFO buffers. In MAC variations with internal FIFO buffers, the ready latency is two.

• Media independent interfaces on the network side—select MII, GMII, or RGMII by setting the

Interface option on the Core Configuration page or the

ETH_SPEED

bit in the command_config register.

• Control interface—an Avalon-MM slave port that provides access to 256 32-bit configuration and status registers, and statistics counters. This interface supports the use of waitrequest

to stall the interconnect fabric for as many cycles as required.

• PHY management interface—implements the standard MDIO specification, IEEE 803.2 standard

Clause 22, to access the PHY device management registers. This interface supports up to 32 PHY devices.

MAC variations without internal FIFO buffers implement the following additional interfaces:

• FIFO status interface—an Avalon-ST sink port that streams in the fill level of an external FIFO buffer.

Only MAC variations without internal buffers implement this interface.

• Packet classification interface—an Avalon-ST source port that streams out receive packet classification information. Only MAC variations without internal buffers implement this interface.

Related Information

Transmit Thresholds

on page 4-16

Interface Signals

on page 7-1

MAC Configuration Register Space

on page 6-1

Avalon Interface Specifications

More information about the Avalon interfaces.

MAC Transmit Datapath

On the transmit path, the MAC function accepts frames from a user application and constructs Ethernet frames before forwarding them to the PHY. Depending on the MAC configuration, the MAC function could perform the following tasks: realigns the payload, modifies the source address, calculates and appends the CRC-32 field, and inserts interpacket gap (IPG) bytes. In half-duplex mode, the MAC

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function also detects collision and attempts to retransmit frames when a collision occurs. The following conditions trigger transmission:

• In MAC variations with internal FIFO buffers:

• Cut-through mode—transmission starts when the level of the FIFO level hits the transmit sectionfull threshold.

• Store and forward mode—transmission starts when a full packet is received.

• In MAC variations without internal FIFO buffers, transmission starts as soon as data is available on the

Avalon-ST transmit interface.

Related Information

Ethernet Frame Format

on page 12-1

IP Payload Re-alignment

If you turn the Align packet headers to 32-bit boundaries option, the MAC function removes the additional two bytes from the beginning of Ethernet frames.

Related Information

IP Payload Alignment

on page 4-11

Address Insertion

By default, the MAC function retains the source address received from the user application. You can configure the MAC function to replace the source address with the primary MAC address or any of the supplementary addresses by setting the

TX_ADDR_INS

bit in the command_config

register to 1. The

TX_ADDR_SEL

bits in the command_config

register determines the address selection.

Related Information

Command_Config Register (Dword Offset 0x02)

on page 6-7

Frame Payload Padding

The MAC function inserts padding bytes (

0x00

) when the payload length does not meet the minimum length required:

• 46 bytes for basic frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

CRC-32 Generation

To turn on CRC-32 generation, you must set the

OMIT_CRC

bit in the tx_cmd_stat

register to 0 and send the frame to the MAC function with the ff_tx_crc_fwd

signal deasserted.

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X

32

+X

26

+X

23

+X

22

+X

16

+X

12

+X

11

+X

10

+X

8

+X

7

+X

5

+X

4

+X

2

+X

1

+1

The 32-bit CRC value occupies the FCS field with

X

31 in the least significant bit of the first byte. The CRC bits are thus transmitted in the following order:

X

31,

X

30,...,

X

1,

X

0.

Interpacket Gap Insertion

In full-duplex mode, the MAC function maintains the minimum number of IPG configured in the tx_ipg_length

register between transmissions. You can configure the minimum IPG to any value

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between 64 and 216 bit times, where 64 bit times is the time it takes to transmit 64 bits of raw data on the medium.

In half-duplex mode, the MAC function constantly monitors the line. Transmission starts only when the line has been idle for a period of 96 bit times and any backoff time requirements have been satisfied. In accordance with the standard, the MAC function begins to measure the IPG when the m_rx_crs

signal is deasserted.

Collision Detection in Half-Duplex Mode

Collision occurs only in a half-duplex network. It occurs when two or more nodes transmit concurrently.

The PHY device asserts the m_rx_col

signal to indicate collision.

When the MAC function detects collision during transmission, it stops the transmission and sends a 32bit jam pattern instead. A jam pattern is a fixed pattern, 0x648532A6, and is not compared to the CRC of the frame. The probability of a jam pattern to be identical to the CRC is very low, 0.532%.

If the MAC function detects collision while transmitting the preamble or SFD field, it sends the jam pattern only after transmitting the SFD field, which subsequently results in a minimum of 96-bit fragment.

If the MAC function detects collision while transmitting the first 64 bytes, including the preamble and

SFD fields, the MAC function waits for an interval equal to the backoff period and then retransmits the frame. The frame is stored in a 64-byte retransmit buffer. The backoff period is generated from a pseudorandom process, truncated binary exponential backoff.

Figure 4-3: Frame Retransmission

MAC Transmit

LFSR

Backoff

Period

Col

PHY Control

Retransmission Block

Rd_en

Buffer

Control

WAddr

64x8

Buffer

RAddr

Frame

Discard

Avalon-ST

Interface

MAC Transmit

Datapath

PHY Interface

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The backoff time is a multiple of slot times. One slot is equal to a 512 bit times period. The number of the delay slot times, before the Nth retransmission attempt, is chosen as a uniformly distributed random integer in the following range:

0

r < 2 k k = min(n, N),

where n is the number of retransmissions and N = 10.

For example, after the first collision, the backoff period, in slot time, is 0 or 1. If a collision occurs during the first retransmission, the backoff period, in slot time, is 0, 1, 2, or 3.

The maximum backoff time, in 512 bit times slots, is limited by N set to 10 as specified in the IEEE

Standard 802.3.

If collision occurs after 16 consecutive retransmissions, the MAC function reports an excessive collision condition by setting the

EXCESS_COL

bit in the command_config

register to 1, and discards the current frame from the transmit FIFO buffer.

In networks that violate standard requirements, collision may occur after the transmission of the first 64 bytes. If this happens, the MAC function stops transmitting the current frame, discards the rest of the frame from the transmit FIFO buffer, and resumes transmitting the next available frame. You can check the

LATE_COL

register ( command_config [12]

) to verify if the MAC has discarded any frame due to collision.

MAC Receive Datapath

The MAC function receives Ethernet frames from the network via a PHY and forwards the payload with relevant frame fields to the user application after performing checks, filtering invalid frames, and removing the preamble and SFD.

Preamble Processing

The MAC function uses the SFD (

0xD5

) to identify the last byte of the preamble. If an SFD is not found after the seventh byte, the MAC function rejects the frame and discards it.

The IEEE standard specifies that frames must be separated by an interpacket gap (IPG) of at least 96 bit times. The MAC function, however, can accept frames with an IPG of less than 96 bit times; at least 8bytes and 6-bytes in RGMII/GMII (1000 Mbps operation) and RGMII/MII (10/100 Mbps operation) respectively.

The MAC function removes the preamble and SFD fields from valid frames.

Collision Detection in Half-Duplex Mode

In half-duplex mode, the MAC function checks for collisions during frame reception. When collision is detected during the reception of the first 64 bytes, the MAC function discards the frame if the

RX_ERR_DISC

bit is set to 1. Otherwise, the MAC function forwards the frame to the user application with error.

Address Checking

The MAC function can accept frames with the following address types:

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Unicast Address Checking

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• Unicast address—bit 0 of the destination address is 0.

• Multicast address—bit 0 of the destination address is 1.

• Broadcast address—all 48 bits of the destination address are 1.

The MAC function always accepts broadcast frames. If promiscuous mode is enabled (

PROMIS_EN

bit in the command_config

register = 1), the MAC function omits address filtering and accepts all frames.

Unicast Address Checking

When promiscuous mode is disabled, the MAC function only accepts unicast frames if the destination address matches any of the following addresses:

• The primary address, configured in the registers mac_0

and mac_1

• The supplementary addresses, configured in the following registers: smac_0_0/smac_0_1

, smac_1_0/ smac_1_1

, smac_2_0/smac_2_1

and smac_3_0/smac_3_1

Otherwise, the MAC function discards the frame.

Multicast Address Resolution

You can use either a software program running on the host processor or a hardware multicast address resolution engine to resolve multicast addresses. Address resolution using a software program can affect the system performance, especially in gigabit mode.

The MAC function uses a 64-entry hash table in the register space, multicast hash table, to implement the hardware multicast address resolution engine as shown in figure below. The host processor must build the hash table according to the specified algorithm. A 6-bit code is generated from each multicast address by

XOR ing the address bits as shown in table below. This code represents the address of an entry in the hash table. Write one to the most significant bit in the table entry. All multicast addresses that hash to the address of this entry are valid and accepted.

You can choose to generate the 6-bit code from all 48 bits of the destination address by setting the

MHASH_SEL

bit in the command_config

register to 0, or from the lower 24 bits by setting the

MHASH_SEL

bit to 1. The latter option is provided if you want to omit the manufacturer's code, which typically resides in the upper 24 bits of the destination address, when generating the 6-bit code.

Figure 4-4: Hardware Multicast Address Resolution Engine

multicast_match dout

Look-Up Table

(64x1 DPRAM) din read_addr(5:0) write_port

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Table 4-1: Hash Code Generation—Full Destination Address

Frame Type Validation

Algorithm for generating the 6-bit code from the entire destination address.

Hash Code Bit

2

3

4

5

0

1 xor xor xor

Value

multicast MAC address bits 7:0

multicast MAC address bits 15:8

multicast MAC address bits 23:16 xor

multicast MAC address bits 31:24 xor

multicast MAC address bits 39:32 xor

multicast MAC address bits 47:40

Table 4-2: Hash Code Generation—Lower 24 Bits of Destination Address

Algorithm for generating the 6-bit code from the lower 24 bits of the destination address.

Hash Code Bit Value

2

3

0

1

4

5 xor xor xor xor xor xor

multicast MAC address bits 3:0

multicast MAC address bits 7:4

multicast MAC address bits 11:8

multicast MAC address bits 15:12

multicast MAC address bits 19:16

multicast MAC address bits 23:20

4-9

The MAC function checks each multicast address received against the hash table, which serves as a fast matching engine, and a match is returned within one clock cycle. If there is no match, the MAC function discards the frame.

All multicast frames are accepted if all entries in the hash table are one.

Frame Type Validation

The MAC function checks the length/type field to determine the frame type:

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• Length/type < 0x600—the field represents the payload length of a basic Ethernet frame. The MAC function continues to check the frame and payload lengths.

• Length/type >= 0x600—the field represents the frame type.

• Length/type = 0x8100—VLAN or stacked VLAN tagged frames. The MAC function continues to check the frame and payload lengths, and asserts the following signals:

• for VLAN frames, rx_err_stat[16]

in MAC variations with internal FIFO buffers or pkt_class_data[1]

in MAC variations without internal FIFO buffers

• for stacked VLAN frames, rx_err_stat

[17] in MAC variations with internal FIFO buffers or pkt_class_data[0]

in MAC variations without internal FIFO buffers.

• Length/type = 0x8088—control frames. The next two bytes, the Opcode field, indicate the type of control frame.

• For pause frames (Opcode = 0x0001), the MAC function continues to check the frame and payload lengths. For valid pause frames, the MAC function proceeds with pause frame processing. The MAC function forwards pause frames to the user application only when the

PAUSE_FWD

bit in the command_config

register is set to 1.

• For other types of control frames, the MAC function accepts the frames and forwards them to the user application only when the

CNTL_FRM_ENA

bit in the command_config

register is set to 1.

• For other field values, the MAC function forwards the receive frame to the user application.

Related Information

Remote Device Congestion

on page 4-18

Payload Pad Removal

You can turn on padding removal by setting the

PAD_EN

bit in the command_config

register to 1. The

MAC function removes the padding, prior to forwarding the frames to the user application, when the payload length is less than the following values for the different frame types:

• 46 bytes for basic MAC frames

• 42 bytes for VLAN tagged frames

• 38 bytes for stacked VLAN tagged frames

When padding removal is turned off, complete frames including the padding are forwarded to the

Avalon-ST receive interface.

CRC Checking

The following equation shows the CRC polynomial, as specified in the IEEE 802.3 standard:

FCS(X) = X

32

+X

26

+X

23

+X

22

+X

16

+X

12

+X

11

+X

10

+X

8

+X

7

+X

5

+X

4

+X

2

+X

1

+1

The 32-bit CRC value occupies the FCS field with

X

31 in the least significant bit of the first byte. The CRC bits are thus received in the following order:

X

31,

X

30,...,

X

1,

X

0.

If the MAC function detects CRC-32 error, it marks the frame invalid by asserting the following signals:

• rx_err[2]

in MAC variations with internal FIFO buffers.

• data_rx_error[1]

in MAC variations without internal FIFO buffers.

The MAC function discards frames with CRC-32 error if the

RX_ERR_DISC

bit in the command_config register is set to 1.

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Length Checking

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The MAC function forwards the CRC-32 field to the user application if the

CRC_FWD

and

PAD_EN

bits in the command_config

register are 1 and 0 respectively. Otherwise, the CRC-32 field is removed from the frame.

Length Checking

The MAC function checks the frame and payload lengths of basic, VLAN tagged, and stacked VLAN tagged frames.

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

• Basic frames—the value specified in the frm_length

register

• VLAN tagged frames—the value specified in the frm_length

register plus four

• Stacked VLAN tagged frames—the value specified in the frm_length

register plus eight

To prevent FIFO buffer overflow, the MAC function truncates the frame if it is more than 11 bytes longer than the allowed maximum length.

For frames of a valid length, the MAC function continues to check the payload length if the

NO_LGTH_CHECK

bit in the command_config

register is set to 0. The MAC function keeps track of the payload length as it receives a frame, and checks the length against the length/type field in basic MAC frames or the client length/type field in VLAN tagged frames. The payload length is valid if it satisfies the following conditions:

• The actual payload length matches the value in the length/type or client length/type field.

• Basic frames—the payload length is between 46 (0x2E)and 1536 (0x0600) bytes, excluding 1536.

• VLAN tagged frames—the payload length is between 42 (0x2A)and 1536 (0x0600), excluding 1536.

• Stacked VLAN tagged frames—the payload length is between 38 (0x26) and 1536 (0x0600), excluding

1536.

If the frame or payload length is not valid, the MAC function asserts one of the following signals to indicate length error:

• rx_err[1]

in MACs with internal FIFO buffers.

• data_rx_error[0]

in MACs without internal FIFO buffers.

Frame Writing

The MegaCore function removes the preamble and SFD fields from the frame. The CRC field and padding bytes may be removed depending on the configuration.

For MAC variations with internal FIFO buffers, the MAC function writes the frame to the internal receive

FIFO buffers.For MAC variations without internal FIFO buffers, it forwards the frame to the Avalon-ST receive interface.

MAC variations without internal FIFO buffers do not support backpressure on the Avalon-ST receive interface. In this variation, if the receiving component is not ready to receive data from the MAC function, the frame gets truncated with error and subsequent frames are also dropped with error.

IP Payload Alignment

The network stack makes frequent use of the IP addresses stored in Ethernet frames. When you turn on the Align packet headers to 32-bit boundaries option, the MAC function aligns the IP payload on a 32-

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MAC Transmit and Receive Latencies

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bit boundary by adding two bytes to the beginning of Ethernet frames. The padding of Ethernet frames are determined by the registers tx_cmd_stat

and rx_cmd_stat

on transmit and receive, respectively.

Table 4-3: 32-Bit Interface Data Structure — Non-IP Aligned Ethernet Frame

31...24

Byte 0

Byte 4

23...16

Byte 1

Byte 5

Bits

15...8

Byte 2

Byte 6

Table 4-4: 32-Bit Interface Data Structure — IP Aligned Ethernet Frame

7...0

Byte 3

Byte 7

31...24

padded with zeros

Byte 2

23...16

Byte 3

Bits

15...8

Byte 0

Byte 4

7...0

Byte 1

Byte 5

MAC Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies:

• Transmit latency is the number of clock cycles the MAC function takes to transmit the first bit on the network-side interface (MII/GMII/RGMII) after the bit was first available on the Avalon-ST interface.

• Receive latency is the number of clock cycles the MAC function takes to present the first bit on the

Avalon-ST interface after the bit was received on the network-side interface (MII/GMII/RGMII).

Table 4-5: Transmit and Receive Nominal Latency

The transmit and receive nominal latencies in various modes. The FIFO buffer thresholds are set to the typical values specified in this user guide when deriving the latencies.

Latency (Clock Cycles) (1)

MAC Configuration

Transmit Receive

MAC with Internal FIFO Buffers

(2)

GMII in cut-through mode

MII in cut-through mode

RGMII in gigabit and cut-through mode

RGMII in 10/100 Mbps and cut-through mode

MAC without Internal FIFO Buffers

(3)

GMII

MII

RGMII in gigabit mode

RGMII in10/100 Mbps

32

41

33

42

11

22

12

23

110

218

113

221

37

77

40

80

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MAC Configuration

Notes to

Table 4-5

:

1. The clocks in all domains are running at the same frequency.

2. The data width is set to 32 bits.

3. The data width is set to 8 bits.

FIFO Buffer Thresholds

4-13

Latency (Clock Cycles) (1)

Transmit Receive

Related Information

Base Configuration Registers (Dword Offset 0x00 – 0x17)

on page 6-3

FIFO Buffer Thresholds

For MAC variations with internal FIFO buffers, you can change the operations of the FIFO buffers, and manage potential FIFO buffer overflow or underflow by configuring the following thresholds:

• Almost empty

• Almost full

• Section empty

• Section full

These thresholds are defined in bytes for 8-bit wide FIFO buffers and in words for 32-bit wide FIFO buffers. The FIFO buffer thresholds are configured via the registers.

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Receive Thresholds

Receive Thresholds

Figure 4-5: Receive FIFO Thresholds

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Network

The remaining unwritten entries in the FIFO buffer before it is full.

The remaining unread entries in the FIFO buffer before it is empty.

Almost full

Frame Buffer n

Frame Buffer n - 1

Almost empty

Frame Buffer k

Frame Buffer 2

Frame Buffer 1

Section Empty

Section full entries in the FIFO buffer for the user application to start reading from it.

An early indication that the FIFO buffer is getting full.

Switch Fabric

Table 4-6: Receive Thresholds

Threshold

Almost empty

Register Name

rx_almost_empty

Description

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_rx_a_empty signal. The MAC function stops reading from the FIFO buffer and subsequently stops transferring data to the user application to avoid buffer underflow.

When the MAC function detects an EOP, it transfers all data to the user application even if the number of unread entries is below this threshold.

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Threshold

Almost full

Register Name

rx_almost_full

Section empty rx_section_empty

Receive Thresholds

4-15

Description

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the

MAC function asserts the ff_rx_a_full signal. If the user application is not ready to receive data ( ff_rx_rdy

= 0), the MAC function performs the following operations:

• Stops writing data to the FIFO buffer.

• Truncates received frames to avoid FIFO buffer overflow.

• Asserts the rx_err[0]

signal when the ff_ rx_eop

signal is asserted.

• Marks the truncated frame invalid by setting the rx_err[3]

signal to 1.

If the

RX_ERR_DISC

bit in the command_config register is set to 1 and the section-full ( rx_ section_full

) threshold is set to 0, the MAC function discards frames with error received on the Avalon-ST interface.

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer hits this threshold, the MAC function generates an XOFF pause frame to indicate

FIFO congestion to the remote Ethernet device. When the FIFO level goes below this threshold, the MAC function generates an

XON pause frame to indicate its readiness to receive new frames.

To avoid data loss, you can use this threshold as an early warning to the remote Ethernet device on the potential FIFO buffer congestion before the buffer level hits the almost-full threshold. The MAC function truncates receive frames when the buffer level hits the almost-full threshold.

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Transmit Thresholds

Threshold

Section full

Register Name

rx_section_full

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Description

The section-full threshold indicates that there are sufficient entries in the FIFO buffer for the user application to start reading from it. The

MAC function asserts the ff_rx_dsav

signal when the buffer level hits this threshold.

Set this threshold to 0 to enable store and forward on the receive datapath. In the store and forward mode, the ff_rx_dsav

signal remains deasserted. The MAC function asserts the ff_rx_dval

signal as soon as a complete frame is written to the FIFO buffer.

Transmit Thresholds

Figure 4-6: Transmit FIFO Thresholds

Switch Fabric

The remaining unwritten entries in the FIFO buffer before it is full.

The remaining unread entries in the FIFO buffer before it is empty.

Almost full

Frame Buffer n

Frame Buffer n - 1

Almost empty

Frame Buffer k

Frame Buffer 2

Frame Buffer 1

Section Empty

Section full entries in the FIFO buffer for the transmitter to start transmission.

An early indication that the FIFO buffer is getting full.

Network

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Table 4-7: Transmit Thresholds

Threshold

Almost empty

Register Name

tx_almost_empty

Almost full

Section empty

Section full tx_almost_full tx_section_empty tx_section_full

Transmit FIFO Buffer Underflow

4-17

Description

The number of unread entries in the FIFO buffer before the buffer is empty. When the level of the FIFO buffer reaches this threshold, the MAC function asserts the ff_tx_a_empty signal. The MAC function stops reading from the FIFO buffer and sends the Ethernet frame with GMII / MII/ RGMII error to avoid FIFO underflow.

The number of unwritten entries in the FIFO buffer before the buffer is full. When the level of the FIFO buffer reaches this threshold, the

MAC function asserts the ff_tx_a_full signal. The MAC function deasserts the ff_ tx_rdy

signal to backpressure the Avalon-ST transmit interface.

An early indication that the FIFO buffer is getting full. When the level of the FIFO buffer reaches this threshold, the MAC function deasserts the ff_tx_septy

signal. This threshold can serve as a warning about potential FIFO buffer congestion.

This threshold indicates that there are sufficient entries in the FIFO buffer to start frame transmission.

Set this threshold to 0 to enable store and forward on the transmit path. When you enable the store and forward mode, the MAC function forwards each frame as soon as it is completely written to the transmit FIFO buffer.

Transmit FIFO Buffer Underflow

If the transmit FIFO buffer hits the almost-empty threshold during transmission and the FIFO buffer does not contain the end-of-packet indication, the MAC function stops reading data from the FIFO buffer and initiates the following actions:

1. The MAC function asserts the RGMII/GMII/MII error signals ( tx_control

/ gm_tx_err

/ m_tx_err

) to indicate that the fragment transferred is not valid.

2. The MAC function deasserts the RGMII/GMII/MII transmit enable signals ( tx_control

/ gm_tx_en

/ m_tx_en

) to terminate the frame transmission.

3. After the underflow, the user application completes the frame transmission.

4. The transmitter control discards any new data in the FIFO buffer until the end of frame is reached.

5. The MAC function starts to transfer data on the RGMII/GMII/MII when the user application sends a new frame with an SOP.

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Congestion and Flow Control

Figure 4-7: Transmit FIFO Buffer Underflow

Figure illustrates the FIFO buffer underflow protection algorithm for gigabit Ethernet system.

Transmit FIFO ff_tx_data valid

[3] [4] valid ff_tx_sop ff_tx_eop ff_tx_rdy ff_tx_wren ff_tx_crc_fwd ff_tx_err ff_tx_septy ff_tx_uflow ff_tx_a_full ff_tx_a_empty

GMII Transmit gm_tx_en gm_tx_d gm_tx_err valid valid

[1] [2]

[5]

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Congestion and Flow Control

In full-duplex mode, the MAC function implements flow control to manage the following types of congestion:

• Remote device congestion—the receiving device experiences congestion and requests the MAC function to stop sending data.

• Receive FIFO buffer congestion—when the receive FIFO buffer is almost full, the MAC function sends a pause frame to the remote device requesting the remote device to stop sending data.

• Local device congestion—any device connected to the MAC function, such as a processor, can request the remote device to stop data transmission.

Related Information

MAC Configuration Register Space

on page 6-1

Remote Device Congestion

When the MAC function receives an XOFF pause frame and the

PAUSE_IGNORE

bit in the command_config

register is set to 0, the MAC function completes the transfer of the current frame and stops transmission for the amount of time specified by the pause quanta in 512 bit times increments.

Transmission resumes when the timer expires or when the MAC function receives an XON frame.

You can configure the MAC function to ignore pause frames by setting the

PAUSE_IGNORE

bit in the command_config

register is set to 1.

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Receive FIFO Buffer and Local Device Congestion

4-19

Receive FIFO Buffer and Local Device Congestion

Pause frames generated are compliant to the IEEE Standard 802.3 annex 31A & B. The MAC function generates pause frames when the level of the receive FIFO buffer hits a level that can potentially cause an overflow, or at the request of the user application. The user application can trigger the generation of an

XOFF pause frame by setting the

XOFF_GEN

bit in the command_config

register to 1 or asserting the xoff_gen

signal.

For MAC variations with internal FIFO buffers, the MAC function generates an XOFF pause frame when the level of the FIFO buffer reaches the section-empty threshold ( rx_section_empty

). If transmission is in progress, the MAC function waits for the transmission to complete before generating the pause frame.

The fill level of an external FIFO buffer is obtained via the Avalon-ST receive FIFO status interface.

When generating a pause frame, the MAC function fills the pause quanta bytes P1 and P2 with the value configured in the pause_quant

register. The source address is set to the primary MAC address configured in the mac_0

and mac_1

registers, and the destination address is set to a fixed multicast address, 01-80-

C2-00-00-01 (0x010000c28001).

The MAC function automatically generates an XON pause frame when the FIFO buffer section-empty flag is deasserted and the current frame transmission is completed. The user application can trigger the generation of an XON pause frame by clearing the

XOFF_GEN

bit and signal, and subsequently setting the

XON_GEN

bit to 1 or asserting the

XON_GEN

signal.

When generating an XON pause frame, the MAC function fills the pause quanta (payload bytes P1 and

P2) with 0x0000 (zero quanta). The source address is set to the primary MAC address configured in the mac_0

and mac_1

registers and the destination address is set to a fixed multicast address, 01-80-

C2-00-00-01 (0x010000c28001).

In addition to the flow control mechanism, the MAC function prevents an overflow by truncating excess frames. The status bit, rx_err[3]

, is set to 1 to indicate such errors. The user application should subsequently discard these frames by setting the

RX_ERR_DISC

bit in the command_config

register to 1.

Magic Packets

A magic packet can be a unicast, multicast, or broadcast packet which carries a defined sequence in the payload section. Magic packets are received and acted upon only under specific conditions, typically in power-down mode.

The defined sequence is a stream of six consecutive 0xFF bytes followed by a sequence of 16 consecutive unicast MAC addresses. The unicast address is the address of the node to be awakened.

The sequence can be located anywhere in the magic packet payload and the magic packet is formed with a standard Ethernet header, optional padding and CRC.

Sleep Mode

You can only put a node to sleep (set

SLEEP

bit in the command_config

register to 1 and deassert the magic_sleep_n

signal) if magic packet detection is enabled (set the

MAGIC_ENA

bit in the command_config register to 1).

Altera recommends that you do not put a node to sleep if you disable magic packet detection.

Network transmission is disabled when a node is put to sleep. The receiver remains enabled, but it ignores all traffic from the line except magic packets to allow a remote agent to wake up the node. In the sleep mode, only etherStatsPkts

and etherStatsOctets

count the traffic statistics.

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Magic Packet Detection

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Magic Packet Detection

Magic packet detection wakes up a node that was put to sleep. The MAC function detects magic packets with any of the following destination addresses:

• Any multicast address

• A broadcast address

• The primary MAC address configured in the mac_0

and mac_1

registers

• Any of the supplementary MAC addresses configured in the following registers if they are enabled: smac_0_0

, smac_0_1

, smac_1_0

, smac_1_1

, smac_2_0

, smac_2_1

, smac_3_0

and smac_3_1

When the MAC function detects a magic packet, the

WAKEUP

bit in the command_config

register is set to 1, and the etherStatsPkts

and etherStatsOctets

statistics registers are incremented.

Magic packet detection is disabled when the

SLEEP

bit in the command_config

register is set to 0. Setting the

SLEEP

bit to 0 also resets the

WAKEUP

bit to 0 and resumes the transmit and receive operations.

MAC Local Loopback

You can enable local loopback on the MII/GMII/RGMII of the MAC function to exercise the transmit and receive paths. If you enable local loopback, use the same clock source for both the transmit and receive clocks. If you use different clock sources, ensure that the difference between the transmit and receive clocks is less than ±100 ppm.

To enable local loopback:

1. Initiate software reset by setting the

SW_RESET

bit in command_config

register to 1.

Software reset disables the transmit and receive operations, flushes the internal FIFOs, and clears the statistics counters. The

SW_RESET

bit is automatically cleared upon completion.

2. When software reset is complete, enable local loopback on the MAC's MII/GMII/RGMII by setting the

LOOP_ENA

bit in command_config

register to 1.

3. Enable transmit and receive operations by setting the

TX_ENA

and

RX_ENA

bits in command_config register to 1.

4. Initiate frame transmission.

5. Compare the statistics counters aFramesTransmittedOK

and aFramesReceivedOK

to verify that the transmit and receive frame counts are equal.

6. Check the statistics counters ifInErrors and ifOutErrors

to determine the number of packets transmitted and received with errors.

7. To disable loopback, initiate a software reset and set the

LOOP_ENA

bit in command_config

register to 0.

MAC Error Correction Code

The error correction code feature is implemented to the memory instances in the MegaCore function.

This feature is capable of detecting single and double bit errors, and can fix single bit errors in the corrupted data.

Note: This feature is only applicable for Stratix V and Arria 10 devices.

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Table 4-8: Core Variation and ECC Protection Support

Core Variation

10/100/1000 Mb Ethernet MAC

10/100/1000 Mb Ethernet MAC with

1000BASE-X/SGMII PCS

1000BASE-X/SGMII PCS only

1000 Mb Small MAC

10/100 Mb Small MAC

ECC Protection Support

Protects the following options: transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

Protects the following options: transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

Statistic counters (if enabled)

Multicast hashtable (if enabled)

SGMII bridge (if enabled)

Protects the SGMII bridge (if enabled)

Protects the transmit and receive FIFO buffer

Protects the following options: transmit and receive FIFO buffer

Retransmit buffer (if half duplex is enabled)

MAC Reset

4-21

When you enable this feature, the following output ports are added for 10/100/1000 Mb Ethernet MAC and 1000BASE-X/SGMII PCS variants to provide ECC status of all the memory instances in the

MegaCore function.

• Single channel core configuration— eccstatus[1:0]

output ports.

• Multi-channel core configuration— eccstatus_<n>[1:0]

output ports, where eccstatus_0[1:0]

is for channel 0, eccstatus_1[1:0] for channel 1, and so on.

MAC Reset

A hardware reset resets all logic. A software reset only disables the transmit and receive paths, clears all statistics registers, and flushes the receive FIFO buffer. The values of configuration registers, such as the

MAC address and thresholds of the FIFO buffers, are preserved during a software reset.

When you trigger a software reset, the MAC function sets the

TX_ENA

and

RX_ENA

bits in the command_config

register to 0 to disable the transmit and receive paths. However, the transmit and receive paths are only disabled when the current frame transmission and reception complete.

• To trigger a hardware reset, assert the reset

signal.

• To trigger a software reset, set the

SW_RESET

bit in the command_config

register to 1. The

SW_RESET

bit is cleared automatically when the software reset ends.

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PHY Management (MDIO)

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Altera recommends that you perform a software reset and wait for the software reset sequence to complete before changing the MAC operating speed and mode (full/half duplex). If you want to change the operating speed or mode without changing other configurations, preserve the command_config register before performing the software reset and restore the register after the changing the MAC operating speed or mode.

Figure 4-8: Software Reset Sequence

START

(SW_RESET = 1)

Frame

Reception

Completed?

No

Yes

Receive Frames

Frame

Transmission

Completed?

No

Yes

Transmit Frames

MAC with internal FIFO?

Yes

Receive

FIFO empty?

No

No

Yes

Flush FIFO

Statistics

Counters

Enabled?

Yes

No

END

(SW_RESET = 0)

Note: If the

SW_RESET

bit is 1 when the line clocks are not available (for example, cable is disconnected), the statistics registers may not be cleared. The read_timeout

register is then set to 1 to indicate that the statistics registers were not cleared.

PHY Management (MDIO)

This module implements the standard MDIO specification, IEEE 803.2 standard Clause 22, to access the

PHY device management registers, and supports up to 32 PHY devices.

To access each PHY device, write the PHY address to the MDIO register ( mdio_addr0

/

1

) followed by the transaction data (MDIO Space 0/1). For faster access, the MAC function allows up to two PHY devices to be mapped in its register space at any one time. Subsequent transactions to the same PHYs do not require

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MDIO Connection

4-23

writing the PHY addresses to the register space thus reducing the transaction overhead. You can access the MDIO registers via the Avalon-MM interface.

For more information about the registers of a PHY device, refer to the specification provided with the device.

For more information about the MDIO registers, refer to

MAC Configuration Register Space

on page 6-

1.

MDIO Connection

Figure 4-9: MDIO Interface

addr mdc mdio addr mdc mdio

mdc mdio_in mdio_out mdio_oen

10/100/1000 Ethernet MAC

Avalon-MM Control

Interface

MDIO Frame Format

The MDIO master communicates with the slave PHY device using MDIO frames. A complete frame is 64 bits long and consists of 32-bit preamble, 14-bit command, 2-bit bus direction change, and 16-bit data.

Each bit is transferred on the rising edge of the MDIO clock, mdc

.

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Connecting MAC to External PHYs

Table 4-9: MDIO Frame Formats (Read/Write)

Field settings for MDIO transactions.

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Type PRE

Read 1 ... 1

Write 1 ... 1

ST

MSB LSB

01

01

OP

MSB LSB

10

01

Addr1

MSB LSB

xxxxx xxxxx

Command

Addr2

MSB LSB

xxxxx xxxxx

TA Data

MSB LSB

Z0 xxxxxxxxxxxxxxxx

10 xxxxxxxxxxxxxxxx

Idle

Table 4-10: MDIO Frame Field Descriptions

PRE

ST

OP

Addr1

Addr2

TA

Data

Idle

Name Description

Preamble. 32 bits of logical 1 sent prior to every transaction.

Start indication. Standard MDIO (Clause 22): 0b01.

Opcode. Defines the transaction type.

The PHY device address (PHYAD). Up to 32 devices can be addressed. For PHY device 0, the Addr1 field is set to the value configured in the mdio_addr0 register. For PHY device 1, the Addr1 field is set to the value configured in the mdio_addr1

register.

Register Address. Each PHY can have up to 32 registers.

Turnaround time. Two bit times are reserved for read operations to switch the data bus from write to read for read operations. The PHY device presents its register contents in the data phase and drives the bus from the 2 nd turnaround phase.

bit of the

16-bit data written to or read from the PHY device.

Between frames, the MDIO data signal is tri-stated.

Z

Z

Connecting MAC to External PHYs

The MAC function implements a flexible network interface—MII for 10/100-Mbps interfaces, RGMII or

GMII for 1000-Mbps interfaces—that you can use in multiple applications. This section provides the guidelines for implementing the following network applications:

• Gigabit Ethernet operation

• Programmable 10/100 Ethernet operation

• Programmable 10/100/1000 Ethernet operation

Gigabit Ethernet

You can connect gigabit Ethernet PHYs to the MAC function via GMII or RGMII. On the receive path, connect the 125-MHz clock provided by the PHY device to the MAC clock, rx_clk

. On transmit, drive a

125-MHz clock to the PHY GMII or RGMII. Connect a 125-MHz clock source to the MAC transmit clock, tx_clk

.

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Programmable 10/100 Ethernet

4-25

A technology specific clock driver is required to generate a clock centered with the GMII or RGMII data from the MAC. The clock driver can be a PLL, a delay line or a DDR flip-flop.

Figure 4-10: Gigabit PHY to MAC via GMII

Altera FPGA

clk_in/xtali gtx_clk tx_en

Gigabit

PHY

Vcc m_tx_en m_tx_err eth_mode set_1000 set_10

10/100/1000

Ethernet

MAC

rx_clk rxd(7:0)

Programmable 10/100 Ethernet

Connect 10/100 Ethernet PHYs to the MAC function via MII. On the receive path, connect the 25-MHz

(100 Mbps) or 2.5-MHz (10 Mbps) clock provided by the PHY device to the MAC clock, rx_clk

. On the transmit path, connect the 25 MHz (100 Mbps) or a 2.5 MHz (10 Mbps) clock provided by the PHY to the

MAC clock, tx_clk

.

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Programmable 10/100/1000 Ethernet Operation

Figure 4-11: 10/100 PHY Interface

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clk_in/xtali tx_clk txd(3:0) tx_en tx_err

10/100

PHY

rx_clk rxd(3:0) rx_err m_rx_col m_rx_crs

Altera FPGA

tx_clk m_tx_d(3:0) m_tx_en m_tx_err gm_tx_d(7:0) gm_tx_en gm_tx_err ena_10 eth_mode set_10 set_1000 gm_rx_d(7:0) gm_rx_dv gm_rx_err rx_clk m_rx_d(3:0) m_rx_en m_rx_err

10/100/1000

Ethernet

MAC

Programmable 10/100/1000 Ethernet Operation

Typically, 10/100/1000 Ethernet PHY devices implement a shared interface that you connect to a 10/100-

Mbps MAC via MII/RGMII or to a gigabit MAC via GMII/RGMII.

On the receive path, connect the clock provided by the PHY device (2.5 MHz, 25 MHz or 125 MHz) to the

MAC clock, rx_clk

. The PHY interface is connected to both the MII (active PHY signals) and GMII of the MAC function.

On the transmit path, standard programmable PHY devices operating in 10/100 mode generate a 2.5 MHz

(10 Mbps) or a 25 MHz (100 Mbps) clock. In gigabit mode, the PHY device expects a 125-MHz clock from the MAC function. Because the MAC function does not generate a clock output, an external clock module is introduced to drive the 125 MHz clock to the MAC function and PHY devices. In 10/100 mode, the clock generated by the MAC to the PHY can be tri-stated.

During transmission, the MAC control signal eth_mode

selects either MII or GMII. The MAC function asserts the eth_mode

signal when the MAC function operates in gigabit mode, which subsequently drives the MAC GMII to the PHY interface. The eth_mode

signal is deasserted when the MAC function operates in 10/100 mode. In this mode, the MAC MII is driven to the PHY interface.

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Figure 4-12: 10/100/1000 PHY Interface via MII/GMII

Programmable 10/100/1000 Ethernet Operation

Altera FPGA

25MHz

Osc clk_in/xtali tx_clk gtx_clk txd(7:0)

25MHz

25/2.5 MHz x5

10/100/1000

PHY

Optional tie to 0

if not used rx_clk

125/25/2.5 MHz rxd(7:0) rx_err

Unused tx_clk m_tx_d(3:0) m_tx_en m_tx_err gm_tx_d(7:0) gm_tx_en gm_tx_err eth_mode set_1000 set_10 en_10

10/100/1000

Ethernet

MAC

m_rx_d(3:0) m_rx_err gm_rx_d(7:0) gm_rx_dv gm_rx_err

4-27

Figure 4-13: 10/100/1000 PHY Interface via RGMII

clk_in/xtali

10/100/1000

PHY

gtx_clk tx_en txd[3:0]

Optional tie to 0

if not used

Functional Description

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rx_clk rx_dv rxd[3:0]

Altera FPGA

ena_10 eth_mode tx_clk tx_control rgmii_out[3:0] set_1000 set_10

10/100/1000

Ethernet

MAC

rx_control rgmii_in[3:0]

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1000BASE-X/SGMII PCS With Optional Embedded PMA

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1000BASE-X/SGMII PCS With Optional Embedded PMA

The Altera 1000BASE-X/SGMII PCS function implements the functionality specified by IEEE 802.3

Clause 36. The PCS function is accessible via MII (SGMII) or GMII (1000BASE-X/SGMII). The PCS function interfaces to an on- or off-chip SERDES component via the industry standard ten-bit interface

(TBI).

You can configure the PCS function to include an embedded physical medium attachment (PMA) with a a serial transceiver or LVDS I/O and soft CDR. The PMA interoperates with an external physical medium dependent (PMD) device, which drives the external copper or fiber network. The interconnect between

Altera and PMD devices can be TBI or 1.25 Gbps serial.

The PCS function supports the following external PHYs:

• 1000 BASE-X PHYs as is.

• 10BASE-T, 100BASE-T and 1000BASE-T PHYs if the PHYs support SGMII.

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1000BASE-X/SGMII PCS Architecture

Figure 4-14: 1000BASE-X/SGMII PCS

MAC Side

1000BASE-X/SGMII PCS Architecture

1000BASE-X/SGMII PCS

1000 Base-X PCS Receive Control

4-29

Ethernet Side

8b/10b

Decoder

Auto-Negotiation

1000 Base-X PCS Transmit Control

Encapsulation

8b/10b

Encoder

Configuration

Avalon-MM Interface

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Transmit Operation

Figure 4-15: 1000BASE-X/SGMII PCS with Embedded PMA

MAC Side

1000BASE-X/SGMII PCS with PMA

1000 Base-X PCS Receive Control

8b/10b

Decoder

Auto-Negotiation

1000 Base-X PCS Transmit Control

Encapsulation

8b/10b

Encoder

PMA

CDR &

Deserializer

PHY

Loopback

Serializer

Ethernet Side

1.25 Gbps

Serial Receive

1.25 Gbps

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Serial Transmit

Configuration

Avalon-MM Interface

Transmit Operation

The transmit operation includes frame encapsulation and encoding.

Frame Encapsulation

The PCS function replaces the first preamble byte in the MAC frame with the start of frame /S/ symbol.

Then, the PCS function encodes the rest of the bytes in the MAC frame with standard 8B/10B encoded characters. After the last FCS byte, the PCS function inserts the end of frame sequence, /T/ /R/ /R/ or /T/ /R/, depending on the number of character transmitted. Between frames, the PCS function transmits /I/ symbols.

If the PCS function receives a frame from the MAC function with an error ( gm_tx_err

asserted during frame transmission), the PCS function encodes the error by inserting a /V/ character.

8b/10b Encoding

The 8B/10B encoder maps 8-bit words to 10-bit symbols to generate a DC balance and ensure disparity of the stream with a maximum run length of 5.

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Receive Operation

Receive Operation

The receive operation includes comma detection, decoding, de-encapsulation, synchronization, and carrier sense.

4-31

Comma Detection

The comma detection function searches for the 10-bit encoded comma character, K28.1/K28.5/K28.7, in consecutive samples received from PMA devices. When the K28.1/K28.5/K28.7 comma code group is detected, the PCS function realigns the data stream on a valid 10-bit character boundary. A standard

8b/10b decoder can subsequently decodes the aligned stream.

The comma detection function restarts the search for a valid comma character if the receive synchroniza‐ tion state machine loses the link synchronization.

8b/10b Decoding

The 8b/10b decoder performs the disparity checking to ensure DC balancing and produces a decoded 8bit stream of data for the frame de-encapsulation function.

Frame De-encapsulation

The frame de-encapsulation state machine detects the start of frame when the /I/ /S/ sequence is received and replaces the /S/ with a preamble byte (0x55). It continues decoding the frame bytes and transmits them to the MAC function. The /T/ /R/ /R/ or the /T/ /R/ sequence is decoded as an end of frame.

A /V/ character is decoded and sent to the MAC function as frame error. The state machine decodes sequences other than /I/ /I/ (Idle) or /I/ /S/ (Start of Frame) as wrong carrier.

During frame reception, the de-encapsulation state machine checks for invalid characters. When the state machine detects invalid characters, it indicates an error to the MAC function.

Synchronization

The link synchronization constantly monitors the decoded data stream and determines if the underlying receive channel is ready for operation. The link synchronization state machine acquires link synchronization if the state machine receives three code groups with comma consecutively without error.

When link synchronization is acquired, the link synchronization state machine counts the number of invalid characters received. The state machine increments an internal error counter for each invalid character received and incorrectly positioned comma character. The internal error counter is decremented when four consecutive valid characters are received. When the counter reaches 4, the link synchronization is lost.

The PCS function drives the led_link

signal to 1 when link synchronization is acquired. This signal can be used as a common visual activity check using a board LED.

The PCS function drives the led_panel_link

signal to 1 when link synchronization is acquired for the

PCS operating in 1000 Base-X without auto negotiation and SGMII mode without auto negotiation.

Carrier Sense

The carrier sense state machine detects an activity when the link synchronization is acquired and when the transmit and receive encapsulation or de-encapsulation state machines are not in the idle or error states.

The carrier sense state machine drives the mii_rx_crs

and led_crs

signals to 1 when it detects an activity. The led_crs

signal can be used as a common visual activity check using a board LED.

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Collision Detection

Collision Detection

A collision happens when non-idle frames are received from the PHY and transmitted to the PHY simultaneously. Collisions can be detected only in SGMII and half-duplex mode.

When a collision happens, the collision detection state machine drives the mii_rx_col

and led_col signals to 1. You can use the led_col

signal as a visual check using a board LED.

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Transmit and Receive Latencies

Altera uses the following definitions for the transmit and receive latencies for the PCS function with an embedded PMA:

• Transmit latency is the time the PCS function takes to transmit the first bit on the PMA-PCS interface after the bit was first available on the MAC side interface (MII/GMII).

• Receive latency is the time the PCS function takes to present the first bit on the MAC side interface

(MII/GMII) after the bit was received on the PMA-PCS interface.

Table 4-11: PCS Transmit and Receive Latency

These latencies are derived from a simulation. For transceiver latency, refer to the transceiver handbook of the respective device family.

Latency (ns)

PCS Configuration

Transmit Receive

PCS with GX transceivers

10-Mbps SGMII

100-Mbps SGMII

1000-Mbps SGMII

1000BASE-X

PCS with LVDS Soft-CDR I/O

10-Mbps SGMII

100-Mbps SGMII

1000-Mbps SGMII

1000BASE-X

3368

488

184

24

3600

440

192

40

2489

335

135

40

2344

344

184

104

SGMII Converter

You can enable the SGMII converter by setting the

SGMII_ENA

bit in the if_mode

register to 1. When enabled and the

USE_SGMII_AN

bit in the

if_mode

register is set to 1, the SGMII converter is automatically configured with the capabilities advertised by the PHY. Otherwise, Altera recommends that you configure the SGMII converter with the

SGMII_SPEED

bits in the if_mode

register.

In 1000BASE-X mode, the PCS function always operates in gigabit mode and data duplication is disabled.

Transmit

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the MAC function once to the PCS function.

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Receive

4-33

In 100-Mbps mode, the transmit converter replicates each byte received by the PCS function 10 times. In

10 Mbps, the transmit converter replicates each byte transmitted from the MAC function to the PCS function 100 times.

Receive

In gigabit mode, the PCS and MAC functions must operate at the same rate. The transmit converter transmits each byte from the PCS function once to the MAC function.

In 100-Mbps mode, the receive converter transmits one byte out of 10 bytes received from the PCS function to the MAC function. In 10-Mbps, the receive converter transmits one byte out of 100 bytes received from the PCS function to the MAC function.

Auto-Negotiation

Auto-negotiation is an optional function that can be started when link synchronization is acquired during system start up. To start auto-negotiation automatically, set the

AUTO_NEGOTIATION_ENABLE

bit in the

PCS control

register to 1. During auto-negotiation, the PCS function advertises its device features and exchanges them with a link partner device.

If the

SGMII_ENA

bit in the if_mode

register is set to 0, the PCS function operates in 1000BASE-X.

Otherwise, the operating mode is SGMII. The following sections describe the auto-negotiation process for each operating mode.

When simulating your design, you can disable auto-negotiation to reduce the simulation time. If you enable auto-negotiation in your design, set the link_timer

time to a smaller value to reduce the autonegotiation link timer in the simulation.

Related Information

PCS Configuration Register Space

on page 6-18

1000BASE-X Auto-Negotiation

When link synchronization is acquired, the PCS function starts sending a /C/ sequence (configuration sequence) to the link partner device with the advertised register set to 0x00. The sequence is sent for a time specified in the PCS link_timer

register mapped in the PCS register space.

When the link_timer

time expires, the PCS dev_ability

register is advertised, with the

ACK

bit set to 0 for the link partner. The auto-negotiation state machine checks for three consecutive /C/ sequences received from the link partner.

The auto-negotiation state machine then sets the

ACK

bit to 1 in the advertised dev_ability

register and checks if three consecutive /C/ sequences are received from the link partner with the

ACK

bit set to 1.

Auto-negotiation waits for the value configured in the link_timer

register to ensure no more consecu‐ tive /C/sequences are received from the link partner. The auto-negotiation is successfully completed when three consecutive idle sequences are received after the link timer expires.

After auto-negotiation completes successfully, the user software reads both the dev_ability

and partner_ability

register and proceed to resolve priority for duplex mode and pause mode. If the design contains a MAC and PCS, the user software configures the MAC with a proper resolved pause mode by setting the

PAUSE_IGNORE

bit in command_config

register. To disable pause frame generation based on the receive FIFO buffer level, you should set the rx_section_empty

register accordingly.

Functional Description

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SGMII Auto-Negotiation

Figure 4-16: Auto-Negotiation Activity (Simplified)

Link Partner PCS

/C/ with 0x00 ability

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/C/ with dev_ability register and

ACK bit set to 0

/C/ with dev_ability register and

ACK bit set to 1

Send /I/ (Idle) sequence

Link Timer

= 10 ms

Data

Once auto-negotiation completes successfully, the ability advertised by the link partner device is available in the partner_ability

register and the

AUTO_NEGOTIATION_COMPLETE

bit in the status register is set to

1.

The PCS function restarts auto-negotiation when link synchronization is lost and reacquired, or when you set the

RESTART_AUTO_NEGOTIATION

bit in the PCS control register to 1.

SGMII Auto-Negotiation

In SGMII mode, the capabilities of the PHY device are advertised and exchanged with a link partner PHY device.

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SGMII Auto-Negotiation

Possible application of SGMII auto-negotiation in MAC mode and PHY mode.

Figure 4-17: SGMII Auto-Negotiation in MAC Mode and PHY Mode

10/100/1000BASE-T PHY

4-35

10/100/1000BASE-T PHY

Link Partner

Altera Device

Triple Speed Ethernet

MegaCore Function

SGMII PCS

(MAC Mode)

Device Ability

Link Partner Ability

SGMII Link

Altera Device

Triple Speed Ethernet

MegaCore Function

SGMII PCS with PMA

(PHY Mode)

Device Ability

Link Partner Ability

Device Ability

Link Partner Ability

Medium

Twisted

Copper

Pair

Device Ability

Link Partner Ability

If the

SGMII_ENA

and

USE_SGMII_AN

bits in the if_mode

register are 1, the PCS function is automatically configured with the capabilities advertised by the PHY device once the auto-negotiation completes.

If the

SGMII_ENA

bit is 1 and the

USE_SGMII_AN

bit is 0, the PCS function can be configured with the

SGMII_SPEED

and

SGMII_DUPLEX

bits in the if_mode

register.

If the

SGMII_ENA

bit is 1 and the

SGMII_AN_MODE

bit is 1 (SGMII PHY Mode auto-negotiation is enabled) the speed and duplex mode resolution will be resolved based on the value that you set in the dev_ability register once auto negotiation is done. You should use set to the PHY mode if you want to advertise the link speed and duplex mode to the link partner.

Functional Description

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Ten-bit Interface

Figure 4-18: SGMII Auto-Negotiation Activity

PHY

SGMII PCS

/C/ with 0x00 ability

Link

Synchronization

Acquired

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/C/ with 0x0001 /C/ with dev_ability

Link Timer

= 1.6 ms

/C/ with dev_ability and ACK

Send /I/ (Idle) sequence

Data

For more information, refer to CISCO Serial-GMII Specifications.

Ten-bit Interface

In PCS variations with embedded PMA, the PCS function implements a TBI to an external SERDES.

On transmit, the SERDES must serialize tbi_tx_d[0]

, the least significant bit of the TBI output bus first and tbi_tx_d[9]

, the most significant bit of the TBI output bus last to ensure the remote node receives the data correctly, as figure below illustrates.

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Figure 4-19: SERDES Serialization Overview

tbi_tx_d(9:0)

9 serialization

0

PHY Loopback

4-37

On receive, the SERDES must serialize the TBI least significant bit first and the TBI most significant bit last, as figure below illustrates.

Figure 4-20: SERDES De-Serialization Overview

tbi_rx_d(9:0)

9 0 de-serialization

PHY Loopback

In PCS variations with embedded PMA targeting devices with GX transceivers, you can enable loopback on the serial interface to test the PCS and embedded PMA functions in isolation of the PMD. To enable loopback, set the sd_loopback

bit in the PCS control

register to 1.

The serial loopback option is not supported in Cyclone IV devices with GX transceiver.

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PHY Power-Down

Figure 4-21: Serial Loopback

1000BASE-X PCS

PCS Transmit

Control

PCS Receive sd_loopback

MDIO

Slave Ten-bit

Interface

SERDES

Transmit

SERDES

Receive

SERDES

Serial Transmit

Serial Receive

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PHY Power-Down

Power-down is controlled by the

POWERDOWN

bit in the PCS control

register. When the system management agent enables power-down, the PCS function drives the powerdown

signal, which can be used to control a technology specific circuit to switch off the PCS function clocks to reduce the application activity.

When the PHY is in power-down state, the PCS function is in reset and any activities on the GMII transmit and the TBI receive interfaces are ignored. The management interface remains active and responds to management transactions from the MAC layer device.

Figure 4-22: Power-Down

1000BASE-X PCS

Control powerdown

Power-Down in PCS Variations with Embedded PMA

In PCS variations with embedded PMA targeting devices with GX transceivers, the power-down signal is internally connected to the power-down of the GX transceiver. In these devices, the power-down functionality is shared across quad-port transceiver blocks. Ethernet designs must share a common gbx_pwrdn_in

signal to use the same quad-port transceiver block.

For designs targeting devices other than Stratix V, you can export the power-down signals to implement your own power-down logic to efficiently use the transceivers within a particular transceiver quad. Turn on the Export transceiver powerdown signal parameter to export the signals.

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1000BASE-X/SGMII PCS Reset

Figure 4-23: Power-Down with Export Transceiver Power-Down Signal

4-39

1000BASE-X PCS pcs_pwrdn_out

PMA gxb_pwrdn_in

1000BASE-X/SGMII PCS Reset

A hardware reset resets all logic synchronized to the respective clock domains whereas a software reset only resets the PCS state machines, comma detection function, and 8B10B encoder and decoder. To trigger a hardware reset on the PCS, assert the respective reset signals: reset_reg_clk

, reset_tx_clk

, and reset_rx_clk

. To trigger a software reset, set the

RESET

bit in the control

register to 1.

In PCS variations with embedded PMA, assert the respective reset signals or the power-down signal to trigger a hardware reset. You must assert the reset

signal subsequent to asserting the reset_rx_clk

, reset_tx_clk

, or gbx_pwrdn_in

signal. The reset sequence is also initiated when the active-low rx_freqlocked

signal goes low.

Figure 4-24: Reset Distribution in PCS with Embedded PMA

reset reset_rx_clk reset_tx_clk gbx_pwrdn_in

PCS

Reset

Synchronizer

Reset

Synchronizer

Reset

Sequencer rx_freqlocked

PMA

For more information about the rx_freqlocked

signal and transceiver reset, refer to the transceiver handbook of the respective device family.

Assert the reset

or gxb_pwrdn_in

signals to perform a hardware reset on MAC with PCS and embedded

PMA variation.

Note: You must assert the reset

signal for at least three clock cycles.

Functional Description

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Altera IEEE 1588v2 Feature

Figure 4-25: Reset Distribution in MAC with PCS and Embedded PMA

reset gbx_pwrdwn

Reset

Synchronizer

Reset

Synchronizer

Reset

Sequencer

MAC

PCS

PMA

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Altera IEEE 1588v2 Feature

The Altera IEEE 1588v2 feature provides timestamp for receive and transmit frames in the Triple-Speed

Ethernet MegaCore function designs. The feature consists of Precision Time Protocol (PTP). PTP is a layer-3 protocol that accurately synchronizes all real time-of-day clocks in a network to a master clock.

This feature is supported in Arria V, Arria 10, Cyclone V, MAX10, and Stratix V device families.

IEEE 1588v2 Supported Configurations

The Triple-Speed Ethernet MegaCore functions support the IEEE 1588v2 feature only in the following configurations:

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded serial PMA without FIFO buffer in full-duplex mode

• 10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS and embedded LVDS I/O without FIFO buffer in full-duplex mode

• 10/100/1000-Mbps MAC without FIFO buffer in full-duplex mode

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IEEE 1588v2 Features

IEEE 1588v2 Features

4-41

• Supports 4 types of PTP clock on the transmit datapath:

• Master and slave ordinary clock

• Master and slave boundary clock

• End-to-end (E2E) transparent clock

• Peer-to-peer (P2P) transparent clock

• Supports PTP message types:

• PTP event messages—Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.

• PTP general messages—Follow_Up, Delay_Resp, Pdelay_Resp_Follow_Up, Announce,

Management, and Signaling.

• Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath.

• 1-step clock synchronization—The MAC function inserts accurate timestamp in Sync PTP message or updates the correction field with residence time.

• 2-step clock synchronization—The MAC function provides accurate timestamp and the related fingerprint for all PTP message.

• Supports the following PHY operating speed accuracy:

• random error:

• 10Mbps—NA

• 100Mbps—timestamp accuracy of ± 5 ns

• 1000Mbps—timestamp accuracy of ± 2 ns

• static error—timestamp accuracy of ± 3 ns

• Supports IEEE 802.3, UDP/IPv4, and UDP/IPv6 transfer protocols for the PTP frames.

• Supports untagged, VLAN tagged, Stacked VLAN Tagged PTP frames, and any number of MPLS labels.

• Supports configurable register for timestamp correction on both transmit and receive datapaths.

• Supports Time-of-Day (ToD) clock that provides a stream of 64-bit and 96-bit timestamps.

Functional Description

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IEEE 1588v2 Architecture

IEEE 1588v2 Architecture

Figure 4-26: Overview of the IEEE 1588v2 Feature

This figure shows only the datapaths related to the IEEE 1588v2 feature.

tx_path_delay

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Timestamp &

User Fingerprint

PTP Software

Stack

tx_egress_timestamp_request tx_ingress_timestamp

Time-of-Day

Clock

Correction

tx_time_of_day rx_time_of_day

Timestamp Aligned to

Receive Frame

IEEE 1588v2

Tx Logic

MAC

Time of Day

IEEE 1588v2

Rx Logic

PHY

Tx

PHY

PHY

Rx rx_path_delay

IEEE 1588v2 Transmit Datapath

The IEEE 1588v2 feature supports 1-step and 2-step clock synchronizations on the transmit datapath.

• For 1-step clock synchronization:

• Timestamp insertion depends on the PTP device and message type.

• The MAC function inserts a timestamp in the Sync PTP message if the PTP clock operates as ordinary or boundary clock.

• Depending on the PTP device and message type, the MAC function updates the residence time in the correction field of the PTP frame when the client asserts tx_etstamp_ins_ctrl_residence_time_update

. The residence time is the difference between the egress and ingress timestamps.

• For PTP frames encapsulated using the UDP/IPv6 protocol, the MAC function performs UDP checksum correction using extended bytes in the PTP frame.

• The MAC function re-computes and re-inserts CRC-32 into the PTP frames after each timestamp or correction field insertion.

• For 2-step clock synchronization, the MAC function returns the timestamp and the associated fingerprint for all transmit frames when the client asserts tx_egress_timestamp_request_valid

.

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IEEE 1588v2 Receive Datapath

Table 4-12: Timestamp and Correction Insertion for 1-Step Clock Synchronization

4-43

This table summarizes the timestamp and correction field insertions for various PTP messages in different PTP clocks.

Ordinary Clock Boundary Clock E2E Transparent Clock P2P Transparent Clock

PTP Message

Insert

Time stamp

Insert

Correction

Insert

Time stamp

Insert

Correction

Insert

Time stamp

Insert

Correction

Sync Yes

(1)

Delay_Req No

Pdelay_

Req

No

No Pdelay_

Resp

Delay_

Resp

No

No

No

No

Yes

No

(1)

,

(2)

Yes

No

No

No

No

(1)

No

No

No

Yes

No

(1)

,

(2)

No

No

No

No

No

Yes

Yes

Yes

Yes

No

Follow_

Up

Pdelay_

Resp_

Follow_

Up

No

No

Announce No

Signaling No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

No

Managem ent

No

Notes to

Table 4-12

:

No No No No

1. Applicable only when 2-step flag in flagField

of the PTP frame is 0.

2. Applicable when you assert tx_ingress_timestamp_request_valid

.

No

(2)

(2)

(2)

(2)

No

No

No

No

No

No

No

No

No

No

Insert

Time stamp

Insert

Correction

Yes

Yes

No

Yes

(2)

No

No

No

No

No

No

(2)

(2)

(1)

,

IEEE 1588v2 Receive Datapath

In the receive datapath, the IEEE 1588v2 feature provides a timestamp for all receive frames. The timestamp is aligned with the avalon_st_rx_startofpacket

signal.

IEEE 1588v2 Frame Format

The MAC function, with the IEEE 1588v2 feature, supports PTP frame transfer for the following transport protocols:

• IEEE 802.3

• UDP/IPv4

• UDP/IPv6

Functional Description

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PTP Frame in IEEE 802.3

PTP Frame in IEEE 802.3

Figure 4-27: PTP Frame in IEEE 8002.3

2 Octets

1 Octet

1 Octet

2 Octets

8 Octets

4 Octets

10 Octets

2 Octets

1 Octet

1 Octet

10 Octets

6 Octets

6 Octets

2 Octets

1 Octet

1 Octet

0..1500/9600 Octets

4 Octets

Destination Address

Source Address

Length/Type = 0x88F7

(1) transportSpecific | messageType reserved | versionPTP messageLength domainNumber reserved flagField correctionField reserved

SourcePortIdentify sequenceId controlField logMessageInterval

TimeStamp

Payload

CRC

MAC Header

PTP Header

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Note to

Figure 4–27

:

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

PTP Frame over UDP/IPv4

Checksum calculation is optional for the UDP/IPv4 protocol. The 1588v2 Tx logic should set the checksum to zero.

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Figure 4-28: PTP Frame over UDP/IPv4

6 Octets

6 Octets

2 Octets

1 Octet

1 Octet

2 Octets

2 Octets

2 Octets

1 Octet

1 Octet

2 Octets

4 Octets

4 Octets

0 Octet

2 Octets

2 Octets

2 Octets

2 Octets

1 Octet

1 Octet

2 Octets

1 Octet

1 Octet

2 Octets

8 Octets

4 Octets

10 Octets

2 Octets

1 Octet

1 Octet

10 Octets

0..1500/9600 Octets

4 Octets

Destination Address

Source Address

Length/Type = 0x0800

(1)

Version | Internet Header Length

Differentiated Services

Total Length

Identification

Flags | Fragment Offsets

Time To Live

Protocol = 0x11

Header Checksum

Source IP Address

Destination IP Address

Options | Padding

Source Port

Destination Port = 319 / 320

Length

Checksum transportSpecific | messageType reserved | versionPTP messageLength domainNumber reserved flagField correctionField reserved

SourcePortIdentify sequenceId controlField logMessageInterval

TimeStamp

Payload

CRC

PTP Frame over UDP/IPv6

MAC Header

IP Header

UDP Header

PTP Header

4-45

Note to

Figure 4-28

:

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

PTP Frame over UDP/IPv6

Checksum calculation is mandatory for the UDP/IPv6 protocol. You must extend 2 bytes at the end of the

UDP payload of the PTP frame. The MAC function modifies the extended bytes to ensure that the UDP checksum remains uncompromised.

Functional Description

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PTP Frame over UDP/IPv6

Figure 4-29: PTP Frame over UDP/IPv6

2 Octets

2 Octets

1 Octet

1 Octet

2 Octets

1 Octet

1 Octet

2 Octets

8 Octets

4 Octets

10 Octets

2 Octets

1 Octet

1 Octet

10 Octets

6 Octets

6 Octets

2 Octets

4 Octet

2 Octets

1 Octet

1 Octet

16 Octets

16 Octets

2 Octets

2 Octets

0..1500/9600

Octets

2 Octets

4 Octets

Destination Address

Source Address

Length/Type = 0x86DD

(1)

Version | Traffic Class | Flow Label

Payload Length

Next Header = 0x11

Hop Limit

Source IP Address

Destination IP Address

Source Port

Destination Port = 319 / 320

Length

Checksum transportSpecific | messageType reserved | versionPTP messageLength domainNumber reserved flagField correctionField reserved

SourcePortIdentify sequenceId controlField logMessageInterval

TimeStamp

Payload extended bytes

CRC

MAC Header

IP Header

UDP Header

PTP Header

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Note to

Figure 4-29

:

1. For frames with VLAN or Stacked VLAN tag, add 4 or 8 octets offsets before the length/type field.

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Triple-Speed Ethernet with IEEE 1588v2 Design

Example

2015.06.15

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Software Requirements

Altera uses the following software to test the Triple-Speed Ethernet with IEEE 1588v2 design example and testbench:

• Altera Complete Design Suite 14.0

• ModelSim-SE 10.0b or higher

5

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

5-2

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components

Triple-Speed Ethernet with IEEE 1588v2 Design Example Components

Figure 5-1: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Block Diagram

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Altera FPGA

Client Application

(Configuration,

Status & Statistics)

32-Bit

Avalon MM

Pulse Per

Second

Client Application

64-Bit

Avalon ST

Design Example

Pulse Per

Second

Module

Time of Day

Time of

Day

Clock

Time of Day

Ethernet

Packet

Classifier

64-Bit

Avalon ST

Avalon MM Master

Translator

32-Bit

Avalon MM

Triple-Speed

Ethernet

Transceiver

Reconfiguration

Bundle

Reconfiguration

Serial Signal

External PHY

Timestamp &

Fingerprint

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Base Addresses

5-3

The Triple-Speed Ethernet with IEEE 1588v2 design example comprises the following components:

• Triple-Speed Ethernet design that has the following parameter settings:

• 10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS

• SGMII bridge enabled

• Used GXB transceiver block

• Number of port = 1

• Timestamping enabled

• PTP 1-step clock enabled

• Timestamp fingerprint width = 4

• Internal FIFO not used

• Transceiver Reconfiguration Controller—dynamically calibrates and reconfigures the features of the

PHY IP cores.

• Ethernet Packet Classifier—decodes the packet type of incoming PTP packets and returns the decoded information to the Triple-Speed Ethernet MAC.

• Ethernet ToD Clock—provides 64-bits and/or 96-bits time-of-day to TX and RX of Triple-Speed

Ethernet MAC.

• Pulse Per Second Module—returns pulse per second (pps) to user.

• Avalon-MM Master Translator—provides access to the registers of the following components through the Avalon-MM interface:

• Triple-Speed Ethernet MAC

• Transceiver Reconfiguration Controller

• ToD Clock

Base Addresses

Table below lists the design example components that you can reconfigure to suit your verification objectives. To reconfigure the components, write to their registers using the base addresses listed in the table and the register offsets described in the components' user guides.

Table 5-1: Base Addresses of Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Components

Component

Triple-Speed Ethernet

Time of Day Clock

Transceiver Reconfiguration Controller

0x0000

0x1000

0x2000

Base Address

Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files

Figure 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Folders

<ip_library>/ethernet/altera_eth_tse_design_example tse_ieee1588 testbench

Triple-Speed Ethernet with IEEE 1588v2 Design Example

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Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design

Table 5-2: Triple-Speed Ethernet MAC with IEEE 1588v2 Design Example Files

These files are located in the ..\tse_ieee1588 directory.

File Name tse_1588_top.v

tse_1588_top.sdc

tse_1588.qsys

tb_run_simulation.tcl

Description

The top-level entity file of the design example for verification in hardware.

The Quartus II SDC constraint file for use with the TimeQuest timing analyzer.

A Qsys file for the Triple-Speed Ethernet design example with IEEE

1588v2 option enabled.

Tcl script to run testbench simulation.

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Creating a New Triple-Speed Ethernet MAC with IEEE 1588v2 Design

You can use the Quartus II software to create a new Triple-Speed Ethernet MAC with IEEE 1588v2 design. Altera provides a Qsys design example file that you can customize to facilitate the development of your Triple-Speed Ethernet MAC with IEEE 1588v2 design.

1. Launch the Quartus II software and open the tse_1588.top.v file from the project directory.

2. Launch Qsys from the Tools menu and open the tse_1588.qsys file. By default, the design example targets the Stratix V device family. To change the target family, click on the Project Settings tab and select the desired device from the Device family list.

3. Turn off the additional module under the Use column if your design does not require it. This action disconnects the module from the Triple-Speed Ethernet MAC with IEEE 1588v2 system.

4. Double-click on triple_speed_ethernet_0 to launch the parameter editor.

5. Specify the required parameters in the parameter editor.

6. Click Finish.

7. On the Generation tab, select either a Verilog HDL or VHDL simulation model and make sure that the Create HDL design files for synthesis option is turned on.

8. Click Generate to generate the simulation and synthesis files.

Triple-Speed Ethernet with IEEE 1588v2 Testbench

Altera provides a testbench for you to verify the Triple-Speed Ethernet with IEEE 1588v2 design example.

The following sections describe the testbench, its components, and use.

The testbench operates in loopback mode.

Figure 5-3

shows the flow of the packets in the design example.

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Figure 5-3: Testbench Block Diagram

Testbench

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

5-5

Avalon-MM

Control

Register

Avalon-ST

Transmit

Frame

Generator

Avalon-ST

Receive

Frame

Monitor avalon_bfm_wrapper.sv

Avalon Driver

Ethernet

Packet

Monitor

Avalon-ST

Avalon-ST

DUT

Avalon-MM

Loopback on serial interface

Ethernet

Packet

Monitor

The testbenches comprise the following modules:

• Device under test (DUT)—the design example.

• Avalon driver—uses Avalon-ST master bus functional models (BFMs) to exercise the transmit and receive paths. The driver also uses the master Avalon-MM BFM to access the Avalon-MM interfaces of the design example components.

• Packet monitors—monitors the transmit and receive datapaths, and displays the frames in the simulator console.

Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

The <ip library>/ethernet/altera_eth_tse_design_example/tse_ieee1588/ testbench directory contains the testbench files.

Table 5-3: Triple-Speed Ethernet with IEEE 1588v2 Testbench Files

File Name avalon_bfm_wrapper.sv

avalon_driver.sv

Description

A wrapper for the Avalon BFMs that the

avalon_driver.sv

file uses.

A SystemVerilog HDL driver that utilizes the BFMs to exercise the transmit and receive path, and access the Avalon-MM interface.

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Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow

File Name avalon_if_params_pkg.sv

avalon_st_eth_packet_monitor.sv

default_test_params_pkg.sv

eth_mac_frame.sv

eth_register_map_params_pkg.sv

ptp_timestamp.sv

tb_testcase.sv

tb_top.sv

wave.do

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Description

A SystemVerilog HDL testbench that contains parameters to configure the BFMs. Because the configuration is specific to the DUT, you must not change the contents of this file.

A SystemVerilog HDL testbench that monitors the Avalon-ST transmit and receive interfaces.

A SystemVerilog HDL package that contains the default parameter settings of the testbench.

A SystemVerilog HDL class that defines the Ethernet frames. The

avalon_driver.sv

file uses this class.

A SystemVerilog HDL package that maps addresses to the Avalon-MM control registers.

A SystemVerilog HDL class that defines the timestamp in the testbench.

A SystemVerilog HDL testbench file that controls the flow of the testbench.

The top-level testbench file. This file includes the customized Triple-

Speed Ethernet MAC, which is the device under test (DUT), a client packet generator, and a client packet monitor along with other logic blocks.

A signal tracing macro script for use with the ModelSim simulation software to display testbench signals.

Triple-Speed Ethernet with IEEE 1588v2 Testbench Simulation Flow

Upon a simulated power-on reset, each testbench performs the following operations:

1. Initializes the DUT by configuring the following options through the Avalon-MM interface:

• Configures the MAC. In the MAC, sets the transmit primary MAC address to EE-CC-88-CC-AA-

EE, sets the speed to 1000 Mbps, enables TX and RX MAC, enables pad removal at receive, sets IPG to 12, and sets maximum packet size to 1518.

• Configures PCS and SGMII interface to 1000BASE-X.

• Configures Timestamp Unit in the MAC, by setting periods and path delay adjustments of the clocks.

• Configures ToD clock by loading a predefined time value.

• Configures clock mode of Packet Classifier to Ordinary Clock mode.

2. Starts packet transmission with different clock mode. The testbench sends a total of three packets:

• 1-step PTP Sync message over Ethernet

• 1-step PTP Sync message over UDP/IPv4 with VLAN tag

• 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

3. Configures clock mode of Packet Classifier to End-to-end Transparent Clock mode.

4. Starts packet transmission. The testbench sends a total of three packets:

• 1-step PTP Sync message over Ethernet

• 1-step PTP Sync message over UDP/IPv4 with VLAN tag

• 2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag

5. Ends transmission.

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Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with...

Simulating Triple-Speed Ethernet with IEEE 1588v2 Testbench with ModelSim

Simulator

5-7

To use the ModelSim simulator to simulate the testbench design:

1. Copy the respective design example directory to your preferred project directory: tse_ieee1588 from

<ip library>/ethernet/altera_eth_tse_design_example.

2. Launch Qsys from the Tools menu and open the tse_1588.qsys file.

3. On the Generation tab, select either a Verilog HDL or VHDL simulation model.

4. Click Generate to generate the simulation and synthesis files.

5. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench: do tb_run.tcl

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MAC Configuration Register Space

Use the registers to configure the different aspects of the MAC function and retrieve its status and statistics counters.

In multiport MACs, a contiguous register space is allocated for all ports and accessed via the Avalon-MM control interface. For example, if the register space base address for the first port is 0x00, the base address for the next port is 0x100 and so forth. The registers that are shared among the instances occupy the register space of the first port. Updating these registers in the register space of other ports has no effect on the configuration.

Table 6-1: Overview of MAC Register Space

Dword Offset

0x00 –

0x17

Section

Base Configuration

0x18 –

0x38

Statistics Counters

Description

Base registers to configure the MAC function. At the minimum, you must configure the following functions:

• Primary MAC address ( mac_0

/ mac_1

)

• Enable transmit and receive paths (

TX_ENA

and

RX_ENA

bits in the command_config

register)

The following registers are shared among all instances of a multiport

MAC:

• rev

• scratch

• frm_length

• pause_quant

• mdio_addr0

and mdio_addr1

• tx_ipg_length

For more information about the base configuration registers, refer to

Base Configuration Registers (Dword Offset 0x00 – 0x17)

on page

6-3.

Counters collecting traffic statistics. For more information about the statistics counters, refer to

Statistics Counters (Dword Offset 0x18 –

0x38)

on page 6-11.

6

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

6-2

MAC Configuration Register Space

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Dword Offset

0x3A

0x3B

0x3C –

0x3E

0x3F

0x40 –

0x7F

0x80 –

0x9F

0xA0 –

0xBF

Section Description

Transmit Command Transmit and receive datapaths control register. For more informa‐

Receive Command tion about these registers, see

Transmit and Receive Command

Registers (Dword Offset 0x3A – 0x3B)

on page 6-13.

Extended Statistics

Counters

Upper 32 bits of selected statistics counters. These registers are used if you turn on the option to use extended statistics counters. For more

information about these counters, refer to

Statistics Counters

(Dword Offset 0x18 – 0x38)

on page 6-11 .

Reserved Unused.

Multicast Hash Table 64-entry write-only hash table to resolve multicast addresses. Only bit

0 in each entry is significant. When you write a 1 to a dword offset in the hash table, the MAC accepts all multicast MAC addresses that hash to the value of the address (bits 5:0). Otherwise, the MAC rejects the multicast address. This table is cleared during reset.

Hashing is not supported in 10/100 and 1000 Mbps Small MAC core variations.

MDIO Space 0 or PCS Function

Configuration

MDIO Space 1

MDIO Space 0 and MDIO Space 1 map to registers 0 to 31 of the

PHY devices whose addresses are configured in the mdio_addr0

and mdio_addr1

registers respectively. For example, register 0 of PHY device 0 maps to dword offset 0x80, register 1 maps to dword offset

0x81 and so forth.

Reading or writing to MDIO Space 0 or MDIO Space 1 immediately triggers a corresponding MDIO transaction to read or write the PHY register. Only bits [15:0] of each register are significant. Write 0 to bits [31:16] and ignore them on reads.

If your variation does not include the PCS function, you can use

MDIO Space 0 and MDIO Space 1 to map to two PHY devices.

If your MAC variation includes the PCS function, the PCS function is always device 0 and its configuration registers (

PCS Configuration

Register Space

on page 6-18) occupy MDIO Space 0. You can use

MDIO Space 1 to map to a PHY device.

0xC0 –

0xC7

Supplementary

Address

Supplementary unicast addresses. For more information about these

addresses, refer to

Supplementary Address (Dword Offset 0xC0 –

0xC7)

on page 6-15.

Unused.

0xC8 –

0xCF

Reserved

(1)

0xD0 –

0xD6

IEEE 1588v2 Feature Registers to configure the IEEE 1588v2 feature. For more information

about these registers, refer to

IEEE 1588v2 Feature (Dword Offset

0xD0 – 0xD6)

on page 6-16.

Reserved

(1)

Unused.

0xD7 –

0xFF

Note to

Table 6-1

:

1. Altera recommends that you set all bits in the reserved registers to 0 and ignore them on reads.

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Base Configuration Registers (Dword Offset 0x00 – 0x17)

Base Configuration Registers (Dword Offset 0x00 – 0x17)

6-3

Table 6-2

lists the base registers you can use to configure the MAC function. A software reset does not

reset these registers except the first two bits (

TX_ENA

and

RX_ENA

= 0) in the command_config

register.

Table 6-2: Base Configuration Register Map

Dword

Offset

Name R/W Description HW Reset

0x00 rev

RO

• Bits[15:0]—Set to the current version of the

MegaCore function.

• Bits[31:16]—Customer specific revision, specified by the

CUST_VERSION

parameter defined in the top-level file generated for the instance of the MegaCore function. These bits are set to 0 during the configura‐ tion of the MegaCore function.

0x01

scratch

(1)

RW Scratch register. Provides a memory location for you to test the device memory operation.

0x02 command_config

RW MAC configuration register. Use this register to control and configure the MAC function. The MAC function starts operation as soon as the transmit and receive enable bits in this register are turned on. Altera, therefore, recommends that you configure this register last.

See

Command_Config Register (Dword Offset 0x02)

on page 6-7 for the bit description.

0x03 mac_0

0x04 mac_1

<IP version number>

0

0

0x05 frm_length

RW 6-byte MAC primary address. The first four most

RW significant bytes of the MAC address occupy mac_0

in reverse order. The last two bytes of the MAC address occupy the two least significant bytes of mac_1

in reverse order.

For example, if the MAC address is 00-1C-23-17-4A-

CB, the following assignments are made: mac_0

= 0x17231c00 mac_1

= 0x0000CB4a

Ensure that you configure these registers with a valid

MAC address if you disable the promiscuous mode

(

PROMIS_EN

bit in command_config

= 0).

RW/

RO

• Bits[15:0]—16-bit maximum frame length in bytes.

The MegaCore function checks the length of receive frames against this value. Typical value is 1518.

In 10/100 and 1000 Small MAC core variations, this register is RO and the maximum frame length is fixed to 1518.

• Bits[31:16]—unused.

0

0

1518

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Dword

Offset

Base Configuration Registers (Dword Offset 0x00 – 0x17)

Name

0x06 pause_quant

R/W

RW

0x07

0x08

0x09 rx_section_ empty rx_section_ full tx_section_ empty

RW/

RO

RW/

RO

RW/

RO

Description

• Bits[15:0]—16-bit pause quanta. Use this register to specify the pause quanta to be sent to remote devices when the local device is congested. The MegaCore function sets the pause quanta (P1, P2) field in pause frames to the value of this register.

10/100 and 1000 Small MAC core variations do not support flow control.

• Bits[31:16]—unused.

Variable-length section-empty threshold of the receive

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16).

Set this threshold to a value that is below the rx_ almost_full

threshold and above the rx_section_ full

or rx_almost_empty

threshold.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of

(FIFO Depth – 16).

Variable-length section-full threshold of the receive

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

For cut-through mode, this threshold is typically set to

16. Set this threshold to a value that is above the rx_ almost_empty

threshold.

For store-and-forward mode, set this threshold to 0.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of

16.

Variable-length section-empty threshold of the transmit

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold. This threshold is typically set to (FIFO Depth – 16).

Set this threshold to a value below the rx_almost_full threshold and above the rx_section_full

or rx_ almost_empty

threshold.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of

(FIFO Depth – 16).

0

0

0

0

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Dword

Offset

Name

0x0A tx_section_ full

R/W

Base Configuration Registers (Dword Offset 0x00 – 0x17)

Description

6-5

HW Reset

0x0B

0x0D rx_almost_ empty tx_almost_ empty

RW/

RO

RW/

RO

0x0C rx_almost_full

RW/

RO

RW/

RO

Variable-length section-full threshold of the transmit

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

For cut-through mode, this threshold is typically set to

16. Set this threshold to a value above the tx_almost_ empty

threshold.

For store-and-forward mode, set this threshold to 0.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of

16.

Variable-length almost-empty threshold of the receive

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

Variable-length almost-full threshold of the receive

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

Variable-length almost-empty threshold of the transmit

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

Due to internal pipeline latency, you must set this threshold to a value greater than 3. This threshold is typically set to 8.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 8.

0

0

0

0

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Base Configuration Registers (Dword Offset 0x00 – 0x17)

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Dword

Offset

Name R/W Description HW Reset

0x0E tx_almost_full

RW/

RO

Variable-length almost-full threshold of the transmit

FIFO buffer. Use the depth of your FIFO buffer to determine this threshold.

You must set this register to a value greater than or equal to 3. A value of 3 indicates 0 ready latency; a value of 4 indicates 1 ready latency, and so forth. Because the maximum ready latency on the Avalon-ST interface is 8, you can only set this register to a maximum value of 11.

This threshold is typically set to 3.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 3.

0x0F

0x10 mdio_addr0 mdio_addr1

RW

RW

• Bits[4:0]—5-bit PHY address. Set these registers to the addresses of any connected PHY devices you want to access. The mdio_addr0

and mdio_addr1 registers contain the addresses of the PHY whose registers are mapped to MDIO Space 0 and MDIO

Space 1 respectively.

• Bits[31:5]—unused. Set to read-only value of 0.

0x11 holdoff_quant

RW

• Bit[15:0]—16-bit holdoff quanta. When you enable the flow control, use this register to specify the gap between consecutive XOFF requests.

• Bits[31:16]—unused.

— 0x12 –

0x16

Reserved —

0x17 tx_ipg_length

RW

• Bits[4:0]—minimum IPG. Valid values are between 8 and 26 byte-times. If this register is set to an invalid value, the MAC still maintains a typical minimum

IPG value of 12 bytes between packets, although a read back to the register reflects the invalid value written.

In 10/100 and 1000 Small MAC core variations, this register is RO and the register is set to a fixed value of 12.

Bits[31:5]—unused. Set to read-only value 0.

Note to

Table 6-2

:

1. Register is not available in 10/100 and 1000 Small MAC variations.

0

0

1

0xFFFF

0

0

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Command_Config Register (Dword Offset 0x02)

Figure 6-1: Command_Config Register Fields

Command_Config Register (Dword Offset 0x02)

6-7

At the minimum, you must configure the

TX_ENA

and

RX_ENA

bits to 1 to start the MAC operations. When configuring the command_config

register, Altera recommends that you configure the

TX_ENA

and

RX_ENA bits the last because the MAC function immediately starts its operations once these bits are set to 1.

Table 6-3: Command_Config Register Field Descriptions

Bit(s)

0

TX_ENA

Name

1

2

3

RX_ENA

XON_GEN

ETH_SPEED

R/W Description

RW Transmit enable. Set this bit to 1 to enable the transmit datapath. The MAC function clears this bit following a hardware or software reset. See the

SW_RESET

bit descrip‐ tion.

RW Receive enable. Set this bit to 1 to enable the receive datapath. The MAC function clears this bit following a hardware or software reset. See the

SW_RESET

bit descrip‐ tion.

RW Pause frame generation. When you set this bit to 1, the

MAC function generates a pause frame with a pause quanta of 0, independent of the status of the receive FIFO buffer.

RW Ethernet speed control.

• Set this bit to 1 to enable gigabit Ethernet operation. The set_1000

signal is masked and does not affect the operation.

• If you set this bit to 0, gigabit Ethernet operation is enabled only if the set_1000

signal is asserted.

Otherwise, the MAC function operates in 10/100 Mbps

Ethernet mode.

When the MAC operates in gigabit mode, the eth_mode signal is asserted. This bit is not available in the small MAC variation.

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Command_Config Register (Dword Offset 0x02)

Bit(s) Name

4

PROMIS_EN

5

6

7

8

9

10

PAD_EN

CRC_FWD

PAUSE_FWD

PAUSE_IGNORE

TX_ADDR_INS

HD_ENA

R/W Description

RW Promiscuous enable. Set this bit to 1 to enable promiscuous mode. In this mode, the MAC function receives all frames without address filtering.

RW Padding removal on receive. Set this bit to 1 to remove padding from receive frames before the MAC function forwards the frames to the user application. This bit has no effect on transmit frames.

This bit is not available in the small MAC variation.

RW CRC forwarding on receive.

• Set this bit to 1 to forward the CRC field to the user application.

• Set this bit to 0 to remove the CRC field from receive frames before the MAC function forwards the frame to the user application.

• The MAC function ignores this bit when it receives a padded frame and the

PAD_EN bit is 1. In this case, the

MAC function checks the CRC field and removes the checksum and padding from the frame before forwarding the frame to the user application.

RW Pause frame forwarding on receive.

• Set this bit to 1 to forward receive pause frames to the user application.

• Set this bit to 0 to terminate and discard receive pause frames.

RW Pause frame processing on receive.

• Set this bit to 1 to ignore receive pause frames.

• Set this bit to 0 to process receive pause frames. The

MAC function suspends transmission for an amount of time specified by the pause quanta.

RW MAC address on transmit.

• Set this bit to 1 to overwrite the source MAC address in transmit frames received from the user application with the MAC primary or supplementary address configured in the registers. The

TX_ADDR_SEL

bit determines the address selection.

• Set this bit to 0 to retain the source MAC address in transmit frames received from the user application.

RW Half-duplex enable.

• Set this bit to 1 to enable half-duplex.

• Set this bit to 0 to enable full-duplex.

• The MAC function ignores this bit if you set the

ETH_

SPEED

bit to 1.

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Bit(s)

12

13

14

15

Name

11

EXCESS_COL

LATE_COL

SW_RESET

MHASH_SEL

LOOP_ENA

18

16

TX_ADDR_SEL

[2:0]

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Command_Config Register (Dword Offset 0x02)

R/W Description

RO Excessive collision condition.

• The MAC function sets this bit to 1 when it discards a frame after detecting a collision on 16 consecutive frame retransmissions.

• The MAC function clears this bit following a hardware or software reset. See the

SW_RESET

bit description.

RO Late collision condition.

• The MAC function sets this bit to 1 when it detects a collision after transmitting 64 bytes and discards the frame.

• The MAC function clears this bit following a hardware or software reset. See the

SW_RESET

bit description.

RW Software reset. Set this bit to 1 to trigger a software reset.

The MAC function clears this bit when it completes the software reset sequence.

When software reset is triggered, the MAC function completes the current transmission or reception, and subsequently disables the transmit and receive logic, flushes the receive FIFO buffer, and resets the statistics counters.

RW Hash-code mode selection for multicast address resolution.

• Set this bit to 0 to generate the hash code from the full

48-bit destination address.

• Set this bit to 1 to generate the hash code from the lower

24 bits of the destination MAC address.

RW Local loopback enable. Set this bit to 1 to enable local loopback on the RGMII/GMII/MII of the MAC. The MAC function sends transmit frames back to the receive path.

This bit is not available in the small MAC variation.

RW Source MAC address selection on transmit. If you set the

TX_ADDR_INS

bit to 1, the value of these bits determines the

MAC address the MAC function selects to overwrite the source MAC address in frames received from the user application.

• 000 = primary address configured in the mac_0 and mac_1

registers.

• 100 = supplementary address configured in the smac_0_

0

and smac_0_1

registers.

• 101 = supplementary address configured in the smac_1_

0

and smac_1_1

registers.

• 110 = supplementary address configured in the smac_2_

0

and smac_2_1 registers.

• 111 = supplementary address configured in the smac_3_

0 and smac_3_1 registers.

6-9

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6-10

Bit(s) Name

19

MAGIC_ENA

20

21

22

23

24

25

26

Command_Config Register (Dword Offset 0x02)

SLEEP

WAKEUP

XOFF_GEN

CNTL_FRM_ENA

NO_LGTH_CHECK

ENA_10

RX_ERR_DISC

R/W Description

RW Magic packet detection. Set this bit to 1 to enable magic packet detection.

This bit is not available in the small MAC variation.

RW Sleep mode enable. When the

MAGIC_ENA

bit is 1, set this bit to 1 to put the MAC function to sleep and enable magic packet detection.

This bit is not available in the small MAC variation.

RO Node wake-up request. Valid only when the

MAGIC_ENA

bit is 1.

• The MAC function sets this bit to 1 when a magic packet is detected.

• The MAC function clears this bit when the

SLEEP

bit is set to 0.

RW Pause frame generation. Set this bit to 1 to generate a pause frame independent of the status of the receive FIFO buffer.

The MAC function sets the pause quanta field in the pause frame to the value configured in the pause_quant

register.

RW MAC control frame enable on receive.

• Set this bit to 1 to accept control frames other than pause frames (opcode = 0x0001) and forward them to the user application.

• Set this bit to 0 to discard control frames other than pause frames.

RW Payload length check on receive.

• Set this bit to 0 to check the actual payload length of receive frames against the length/type field in receive frames.

• Set this bit to 1 to omit length checking.

This bit is not available in the small MAC variation

RW 10-Mbps interface enable. Set this bit to 1 to enable the 10-

Mbps interface. The MAC function asserts the ena_10 signal when you enable the 10-Mbps interface. You can also enable the 10-Mbps interface by asserting the set_10 signal.

RW Erroneous frames processing on receive.

• Set this bit to 1 to discard erroneous frames received.

This applies only when you enable store and forward operation in the receive FIFO buffer by setting the rx_ section_full

register to 0.

• Set this bit to 0 to forward erroneous frames to the user application with rx_err[0]

asserted.

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Bit(s) Name

27

DISABLE_READ_

TIMEOUT

28

30

Reserved

31

CNT_RESET

Statistics Counters (Dword Offset 0x18 – 0x38)

R/W Description

RW Set this bit to 1 to disable MAC configuration register read timeout.

— —

6-11

RW Statistics counters reset. Set this bit to 1 to clear the statistics counters. The MAC function clears this bit when the reset sequence completes.

Statistics Counters (Dword Offset 0x18 – 0x38)

Table 6-4

describes the read-only registers that collect the statistics on the transmit and receive datapaths.

A hardware reset clears these registers; a software reset also clears these registers except aMacID

. The statistics counters roll up when the counter is full.

The register description uses the following definitions:

• Good frame—error-free frames with valid frame length.

• Error frame—frames that contain errors or whose length is invalid.

• Invalid frame—frames that are not addressed to the MAC function. The MAC function drops this frame.

Table 6-4: Statistics Counters

Description Dword

Offset

Name

0x18 –

0x19 aMacID

0x1A aFramesTransmitt edOK

0x1B aFramesReceivedO

K

0x1C aFrameCheck

SequenceErrors

RO

RO

RO

RO

0x1D aAlignmentErrors

RO

0x1E aOctetsTransmitt

RO edOK

R/W

The MAC address. This register is wired to the primary

MAC address in the mac_0

and mac_1

registers.

The number of frames that are successfully transmitted including the pause frames.

The number of frames that are successfully received including the pause frames.

The number of receive frames with CRC error.

The number of receive frames with alignment error.

The number of data and padding octets that are successfully transmitted.

This register contains the lower 32 bits of the aOctetsTransmittedOK

counter. The upper 32 bits of this statistics counter reside at the dword offset 0x0F.

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6-12

Dword

Offset

0x1F

Statistics Counters (Dword Offset 0x18 – 0x38)

Name R/W

aOctetsReceivedO

K

RO

0x20

Description

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The number of data and padding octets that are successfully received.

The lower 32 bits of the aOctetsReceivedOK

counter. The upper 32 bits of this statistics counter reside at the dword offset 0x3D.

The number of pause frames transmitted.

0x21

0x22

0x23 aTxPAUSEMACCtrlF rames

RO aRxPAUSEMACCtrlF rames

RO ifInErrors ifOutErrors

RO

RO

The number received pause frames received.

0x24

0x25

0x26

0x27 ifInUcastPkts ifInMulticastPkt s ifInBroadcastPkt s ifOutDiscards

RO

RO

RO

The number of errored frames received.

The number of transmit frames with one the following errors:

• FIFO overflow error

• FIFO underflow error

• Errors defined by the user application

The number of valid unicast frames received.

The number of valid multicast frames received. The count does not include pause frames.

The number of valid broadcast frames received.

0x28

0x29 ifOutUcastPkts

RO

RO ifOutMulticastPk ts

0x2A ifOutBroadcastPk ts

0x2B etherStatsDropEv ents

RO

RO

0x2C etherStatsOctets

RO

This statistics counter is not in use.

The MAC function does not discard frames that are written to the FIFO buffer by the user application.

The number of valid unicast frames transmitted.

The number of valid multicast frames transmitted, excluding pause frames.

The number of valid broadcast frames transmitted.

0x2D etherStatsPkts

0x2E etherStatsUnders izePkts

RO

RO

The number of frames that are dropped due to MAC internal errors when FIFO buffer overflow persists.

The total number of octets received. This count includes both good and errored frames.

This register is the lower 32 bits of etherStatsOctets

. The upper 32 bits of this statistics counter reside at the dword offset 0x3E.

The total number of good and errored frames received.

The number of frames received with length less than 64 bytes. This count does not include errored frames.

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Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

6-13

Dword

Offset

Name R/W Description

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36 etherStatsOversi zePkts etherStatsPkts64

Octets etherStatsPkts65 to127Octets etherStatsPkts12

8to255Octets etherStatsPkts25

6to511Octets etherStatsPkts51

2to1023Octets etherStatsPkts10

24to1518Octets etherStatsPkts15

19toXOctets

RO

RO

RO

RO

RO

RO

RO

RO

The number of frames received that are longer than the value configured in the frm_length

register. This count does not include errored frames.

The number of 64-byte frames received. This count includes good and errored frames.

The number of received good and errored frames between the length of 65 and 127 bytes.

The number of received good and errored frames between the length of 128 and 255 bytes.

The number of received good and errored frames between the length of 256 and 511 bytes.

The number of received good and errored frames between the length of 512 and 1023 bytes.

The number of received good and errored frames between the length of 1024 and 1518 bytes.

The number of received good and errored frames between the length of 1519 and the maximum frame length configured in the frm_length

register.

Too long frames with CRC error.

0x37 etherStatsJabber s

RO

0x38 etherStatsFragme nts

RO Too short frames with CRC error.

0x39 Reserved — Unused

Extended Statistics Counters (0x3C – 0x3E)

0x3C

0x3D msb_ aOctetsTransmitt edOK msb_ aOctetsReceivedO

RO

RO

Upper 32 bits of the respective statistics counters. By default all statistics counters are 32 bits wide. These statistics counters can be extended to 64 bits by turning on the Enable

64-bit byte counters parameter.

0x3E

K msb_

RO

To read the counter, read the lower 32 bits first, then followed by the extended statistic counter bits.

etherStatsOctets

Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

Table 6-5

describes the registers that determine how the MAC function processes transmit and receive

frames. A software reset does not change the values in these registers.

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Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)

Table 6-5: Transmit and Receive Command Registers

R/W Dword

Offset

Name

0x3A tx_cmd_stat

RW

0x3B rx_cmd_stat

RW

Description

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Specifies how the MAC function processes transmit frames.

When you turn on the Align packet headers to 32-bit

boundaries option, this register resets to 0x00040000 upon a hardware reset. Otherwise, it resets to 0x00.

• Bits 0 to 16—unused.

• Bit 17 (

OMIT_CRC

)—Set this bit to 1 to omit CRC calcula‐ tion and insertion on the transmit path. The user applica‐ tion is therefore responsible for providing the correct data and CRC. This bit, when set to 1, always takes precedence over the ff_tx_crc_fwd

signal.

• Bit 18 (

TX_SHIFT16

)—Set this bit to 1 if the frames from the user application are aligned on 32-bit boundary. For more information, refer to

IP Payload Re-alignment

on

page 4-5.

This setting applies only when you turn on the Align

packet headers to 32-bit boundary option and in MAC variations with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0.

In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet

headers to 32-bit boundary option.

• Bits 19 to 31—unused.

Specifies how the MAC function processes receive frames.

When you turn on the Align packet headers to 32-bit

boundaries option, this register resets to 0x02000000 upon a hardware reset. Otherwise, it resets to 0x00.

• Bits 0 to 24—unused.

• Bit 25 (

RX_SHIFT16

)—Set this bit to 1 to instruct the

MAC function to align receive frames on 32-bit boundary. For more information on frame alignment,

refer to

IP Payload Alignment

on page 4-11.

This setting applies only when you turn on the Align

packet headers to 32-bit boundary option and in MAC variations with 32-bit internal FIFO buffers. Otherwise, reading this bit always return a 0.

In MAC variations without internal FIFO buffers, this bit is a read-only bit and takes the value of the Align packet

headers to 32-bit boundary option.

• Bits 26 to 31—unused.

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Supplementary Address (Dword Offset 0xC0 – 0xC7)

Supplementary Address (Dword Offset 0xC0 – 0xC7)

A software reset has no impact on these registers. MAC supplementary addresses are not available in

10/100 and 1000 Small MAC variations.

6-15

Table 6-6: Supplementary Address Registers

R/W Description HW Reset Dword

Offset

Name

0xC0 smac_0_0

0xC1 smac_0_1

0xC2 smac_1_0

0xC3 smac_1_1

0xC4 smac_2_0

0xC5 smac_2_1

0xC6 smac_3_0

0xC7 smac_3_1

RW

You can specify up to four 6-byte supplementary addresses:

• smac_0_0/1

• smac_1_0/1

• smac_2_0/1

• smac_3_0/1

Map the supplementary addresses to the respective registers in the same manner as the primary MAC address. Refer to the description of mac_0 and ma c_1

.

The MAC function uses the supplementary addresses for the following operations:

• to filter unicast frames when the promiscuous mode is disabled (refer to

Command_Config Register

(Dword Offset 0x02)

on page 6-7 for the description

of the

PROMIS_EN

bit).

• to replace the source address in transmit frames received from the user application when address

insertion is enabled (refer to

Command_Config

Register (Dword Offset 0x02)

on page 6-7 for the description of the

TX_ADDR_INS

and

TX_ADDR_SEL bits).

If you do not require the use of supplementary addresses, configure them to the primary address.

0

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IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)

IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)

Table 6-7: IEEE 1588v2 MAC Registers

Dword

Offset

Name

0xD0 tx_period

R/W

RW

Description

0xD1 tx_adjust_fns

RW

0xD2 tx_adjust_ns

0xD3 rx_period

RW

RW

0xD4 rx_adjust_fns

RW

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HW Reset

Clock period for timestamp adjustment on the transmit datapath. The period register is multiplied by the number of stages separating actual timestamp and the

GMII bus.

• Bits 0 to 15: Period in fractional nanoseconds (

TX_

PERIOD_FNS

).

• Bits 16 to 24: Period in nanoseconds (

TX_PERIOD_NS

).

• Bits 25 to 31: Not used.

The default value for the period is 0. For 125-MHz clock, set this register to 8 ns.

0x0

Static timing adjustment in fractional nanoseconds for outbound timestamps on the transmit datapath.

• Bits 0 to 15: Timing adjustment in fractional nanosec‐ onds.

• Bits 16 to 31: Not used.

0x0

Static timing adjustment in nanoseconds for outbound timestamps on the transmit datapath.

• Bits 0 to 15: Timing adjustment in nanoseconds.

• Bits 16 to 23: Not used.

0x0

Clock period for timestamp adjustment on the receive datapath. The period register is multiplied by the number of stages separating actual timestamp and the

GMII bus.

• Bits 0 to 15: Period in fractional nanoseconds (

RX_

PERIOD_FNS

).

• Bits 16 to 24: Period in nanoseconds (

RX_PERIOD_NS

).

• Bits 25 to 31: Not used.

The default value for the period is 0. For 125-MHz clock, set this register to 8 ns.

0x0

Static timing adjustment in fractional nanoseconds for outbound timestamps on the receive datapath.

• Bits 0 to 15: Timing adjustment in fractional nanosec‐ onds.

• Bits 16 to 31: Not used.

0x0

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Dword

Offset

Name

0xD5 rx_adjust_ns

R/W

RW

IEEE 1588v2 Feature PMA Delay

Description

6-17

HW Reset

Static timing adjustment in nanoseconds for outbound timestamps on the receive datapath.

• Bits 0 to 15: Timing adjustment in nanoseconds.

• Bits 16 to 23: Not used.

0x0

IEEE 1588v2 Feature PMA Delay

PMA digital and analog delay of hardware for the IEEE 1588v2 feature and the register timing adjustment.

1 UI is equivalent to 800 ps.

Table 6-8: IEEE 1588v2 Feature PMA Delay—Hardware

Delay Device

Digital

Analog

Stratix V or Arria V GZ

Arria V GX, Arria V GT, or Arria V SoC

Cyclone V GX or Cyclone V SoC

Stratix V

Arria V

Cyclone V

Table 6-9: IEEE 1588v2 Feature LVDS I/O Delay—Hardware

TX register

53 UI

52 UI

32 UI

-1.1 ns

-1.1 ns

-1.1 ns

Timing Adjustment

RX register

26 UI

34 UI

44 UI

1.75 ns

1.75 ns

1.75 ns

Delay

Digital

Device

Stratix V or Arria V GZ

Arria V GX, Arria V GT, or Arria V SoC

TX register

11 UI

11 UI

Timing Adjustment

RX register

36 UI

36 UI

PMA digital and analog delay of simulation model for the IEEE 1588v2 feature and the register timing adjustment.

Table 6-10: IEEE 1588v2 Feature PMA Delay—Simulation Model

Delay

Digital

Device

Stratix V or Arria V GZ

Arria V GX, Arria V GT, or Arria V SoC

Arria 10

Cyclone V GX or Cyclone V SoC

TX register

11 UI

10 UI

32 UI

10 UI

Timing Adjustment

RX register

33.5 UI

23.5 UI

23.5 UI

23.5 UI

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PCS Configuration Register Space

Table 6-11: IEEE 1588v2 Feature LVDS I/O Delay—Simulation Model

Delay

Digital

Device

Stratix V or Arria V GZ

Arria V GX, Arria V GT, or Arria V SoC

Arria 10

Cyclone V GX or Cyclone V SoC

TX register

19.5 UI

19.5 UI

19.5 UI

19.5 UI

Timing Adjustment

RX register

26 UI

26 UI

24.5 UI

26 UI

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PCS Configuration Register Space

This section describes the PCS registers. Use the registers to configure the PCS function or retrieve its status.

Note: In MAC and PCS variations, the PCS registers occupy the MAC register space and you access these registers via the MAC 32-bit Avalon-MM control interface. PCS registers are 16 bits wide, they therefore occupy only the lower 16 bits and the upper 16 bits are set to 0. The offset of the first PCS register in this variation is mapped to dword offset 0x80.

If you instantiate the IP core using the MegaWizard Plug-in Manager flow, use word addressing to access the register spaces. When you instantiate MAC and PCS variations, map the PCS registers to the respective dword offsets in the MAC register space by adding the PCS word offset to the offset of the first

PCS. For example,

• In PCS only variation, you can access the if_mode

register at word offset 0x14.

• In MAC and PCS variations, map the if_mode

register to the MAC register space:

• Offset of the first PCS register = 0x80

• if_mode

word offset = 0x14

• if_mode

dword offset = 0x80 + 0x14 = 0x94

If you instantiate the MAC and PCS variation using the Qsys system, access the register spaces using byte addressing. Convert the dword offsets to byte offsets by multiplying the dword offsets by 4. For example,

• For MAC registers:

• comand_config

dword offset = 0x02

• comand_config

byte offset = 0x02 × 4 = 0x08

• For PCS registers, map the registers to the dword offsets in the MAC register space before you convert the dword offsets to byte offsets:

• if_mode

word offset = 0x14

• if_mode

dword offset = 0x80 + 0x14 = 0x94

• if_mode

byte offset = 0x94 × 4 = 0x250

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Table 6-12: PCS Configuration Registers

R/W Word

Offset

Register Name

0x00 control

0x01

0x02

0x03

0x04

0x05

0x06 status phy_identifier dev_ability partner_ability an_expansion

PCS Configuration Register Space

Description

RW PCS control register. Use this register to control and configure the PCS function. For the bit description, see

Control Register (Word Offset 0x00)

on page 6-20.

RO

RO

Status register. Provides information on the operation of the PCS function.

32-bit PHY identification register. This register is set to the value of the PHY ID parameter. Bits 31:16 are written to word offset 0x02. Bits 15:0 are written to word offset 0x03.

RW Use this register to advertise the device abilities to a link partner during auto-negotiation. In SGMII MAC mode, the PHY does not use this register during auto-negotia‐ tion. For the register bits description in 1000BASE-X and SGMII mode, see

1000BASE-X

on page 6-23 and

SGMII PHY Mode Auto Negotiation

on page 6-25.

RO Contains the device abilities advertised by the link partner during auto-negotiation. For the register bits description in 1000BASE-X and SGMII mode, refer to

1000BASE-X

on page 6-23 and

SGMII PHY Mode

Auto Negotiation

on page 6-25, respectively.

RO Auto-negotiation expansion register. Contains the PCS function capability and auto-negotiation status.

0x07 device_next_page

0x08 partner_next_page

0x09 master_slave_cntl

0x0A master_slave_stat

0x0B

0x0E

Reserved

0x0F extended_status

RO

RO

The PCS function does not support these features.

These registers are always set to 0x0000 and any write access to the registers is ignored.

The PCS function does not implement extended status registers.

Specific Extended Registers

0x10 scratch

0x11 rev

RW Scratch register. Provides a memory location to test register read and write operations.

RO The PCS function revision. Always set to the current version of the MegaCore function.

6-19

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Control Register (Word Offset 0x00)

Word

Offset

Register Name R/W Description

0x12

0x13 link_timer

RW

21-bit auto-negotiation link timer. Set the link timer value from 0 to 16 ms in 8 ns steps (125 MHz clock periods). The reset value sets the link timer to 10 ms.

• Bits 15:0 are written to word offset 0x12. Bit 0 of word offset 0x12 is always set to 0, thus any value written to it is ignored.

• Bits 20:16 are written to word offset 0x13. The remaining bits are reserved and always set to 0.

0x14 if_mode

RW Interface mode. Use this register to specify the operating mode of the PCS function; 1000BASE-X or

SGMII.

0x15 disable_read_timeout

RW

• Bit[0]—Set this bit to 1 to disable PCS register read timeout.

• Bits[31:1]—unused. Set to read-only value 0.

0x16 read_timeout

RO

• Bit[0]—PCS register read timeout indication. Valid only when disable_read_timeout

is set to 0. This bit is cleared after it is read.

The PCS function sets this bit to 0 when the register read ends normally; and sets this bit to 1 when the register read ends with a timeout.

• Bits[31:1]—unused.

0x17

0x1F

Reserved — —

Control Register (Word Offset 0x00)

Table 6-13: PCS Control Register Bit Descriptions

Bit(s)

0:4 Reserved

Name

R/W

Description

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Bit(s)

5

6, 13

7

COLLISION_TEST

8

DUPLEX_MODE

9

RESTART_AUTO_

NEGOTIATION

10

ISOLATE

11

Name

UNIDIRECTIONAL_

ENABLE

SPEED_SELECTION

POWERDOWN

12

AUTO_NEGOTIATION_

ENABLE

Control Register (Word Offset 0x00)

R/W Description

RW Enables the unidirectional function. This bit depends on bit 12. When bit 12 is one, this bit is ignored.

When bit 12 is zero, bit 5 indicates the unidirectional function:

• A value of 1 enables transmit from media independent interface regardless of whether the PHY has determined that a valid link has been established.

• A value of 0 enables transmit from media independent interface only when the PHY has determined that a valid link has been established.

The reset value of this bit is zero.

RO Indicates the operating mode of the PCS function. Bits 6 and 13 are set to 1 and 0 respectively. This combination of values represent the gigabit mode.

Bit [6, 13]:

• 00: 10 Mbps

• 01: 100 Mbps

• 10: 1 Gigabit

• 11: Reserved

RO

RO

The PCS function does not support half-duplex mode.

This bit is always set to 0.

The PCS function only supports full-duplex mode. This bit is always set to 1.

RW Set this bit to 1 to restart the auto-negotiation sequence.

For normal operation, set this bit to 0 (reset value).

RW Set this bit to 1 to isolate the PCS function from the

MAC layer device. For normal operation, set this bit to

0 (reset value).

RW Set this bit to 1 to power down the transceiver quad.

The PCS function then asserts the powerdown

signal to indicate the state it is in.

RW Set this bit to 1 (reset value) to enable auto-negotiation.

6-21

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6-22

Status Register (Word Offset 0x01)

Bit(s)

14

LOOPBACK

Name

15

RESET

R/W Description

RW PHY loopback. Set this bit to 1 to implement loopback in the GX transceiver. For normal operation, set this bit to 0 (reset value). This bit is ignored if reduced ten-bit interface (RTBI) is implemented.

This feature is supported in all device families except the Cyclone IV GX device families.

RW Self-clearing reset bit. Set this bit to 1 to generate a synchronous reset pulse which resets all the PCS function state machines, comma detection function, and 8b/10b encoder and decoder. For normal operation, set this bit to 0 (asynchronous reset value).

Status Register (Word Offset 0x01)

Table 6-14: Status Register Bit Descriptions

Bit

0

Name

EXTENDED_CAPABILITY

RO

R/W

1

2

3

4

5

6

7

8

JABBER_DETECT

LINK_STATUS

AUTO_NEGOTIATION_

ABILITY

REMOTE_FAULT

AUTO_NEGOTIATION_

COMPLETE

MF_PREAMBLE_

SUPPRESSION

UNIDIRECTIONAL_

ABILITY

EXTENDED_STATUS

RO

RO

RO

RO

Description

A value of 1 indicates that the PCS function supports extended registers.

Unused. Always set to 0.

A value of 1 indicates that a valid link is established. A value of 0 indicates an invalid link.

If the link synchronization is lost, a 0 is latched.

A value of 1 indicates that the PCS function supports auto-negotiation.

Unused. Always set to 0.

A value of 1 indicates the following status:

• The auto-negotiation process is completed.

• The auto-negotiation control registers are valid.

Unused. Always set to 0.

A value of 1 indicates that the PCS is able to transmit from MII/GMII regardless of whether the PCS has established a valid link.

Unused. Always set to 0.

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Bit

9

Name

100BASET2_HALF_

DUPLEX

10

100BASET2_FULL_

DUPLEX

11

10MBPS_HALF_

DUPLEX

12

10MBPS_FULL_

DUPLEX

13

100BASE-X_HALF_

DUPLEX

14

100BASE-X_FULL_

DUPLEX

15

100BASE-T4

RO

Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)

R/W Description

The PCS function does not support 100Base-T2,

10-Mbps, 100BASE-X, and 100Base-T4 operation. Always set to 0.

6-23

Dev_Ability and Partner_Ability Registers (Word Offset 0x04 – 0x05)

The definition of each field in the partner_ability

registers depends on the mode in which the PCS function operates.

In this mode, the definition of the fields in the dev_ability

register are the same as the fields in the partner_ability

register. The contents of these registers are valid only when the auto-negotiation completes (

AUTO_NEGOTIATION_COMPLETE

bit in the status

register = 1).

1000BASE-X

Table 6-15: Dev_Ability and Partner_Ability Registers Bits Description in 1000BASE-X

Bit(s)

0:4 Reserved

5

FD

Name

6

7

8

HD

PS1

PS2

9:11 Reserved

R/W

RW/RO

(1) (2)

Description

Always set these bits to 0.

Full-duplex mode enable. A value of 1 indicates support for full duplex.

Half-duplex mode enable. A value of 1 indicates support for half duplex.

Pause support.

PS1

=0 /

PS2

=0: Pause is not supported.

PS1

=0 /

PS2

=1: Asymmetric pause toward link partner.

PS1

=1 /

PS2

=0: Symmetric pause.

PS1

=1/

PS2

=1: Pause is supported on transmit and receive.

— Always set these bits to 0.

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SGMII MAC Mode Auto Negotiation

Bit(s)

12

RF1

13

RF2

Name R/W

RW/RO

(1) (2)

Description

Remote fault condition:

RF1

=0 /

RF2

=0: No error, link is valid (reset condition).

RF1

=0 /

RF2

=1: Offline.

RF1

=1 /

RF2

=0: Failure condition.

RF1

=1 /

RF2

=1: Auto-negotiation error.

14

15

ACK

NP

RO Acknowledge. A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.

RW/RO

(1) (2)

Next page. In dev_ability

register, this bit is always set to 0.

Notes to

Table 6-15

:

1. All bits in the dev_ability

register have RW access.

2. All bits in the partner_ability

register are read-only.

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SGMII MAC Mode Auto Negotiation

When the SGMII mode and the SGMII MAC mode auto-negotiation are enabled, the Triple-Speed

Ethernet IP core ignores the value in the dev_ability

register and automatically sets the value to

16’h4001

as specified in the SGMII specification for SGMII auto-negotiation.

When the auto-negotiation is complete, the Triple-Speed Ethernet IP core speed and the duplex mode will be resolved based on the value in the partner_ability

register. The partner_ability

register is received from the link partner during the auto-negotiation process.

Table 6-16: Partner_Ability Register Bits Description in SGMII MAC Mode

Bit(s) Name

9:0 Reserved

11:10

COPPER_SPEED[1:0]

RO

R/W

12

13

COPPER_DUPLEX_

STATUS

Reserved

RO

Description

Link partner interface speed:

• 00: copper interface speed is 10 Mbps

• 01: copper interface speed is 100 Mbps

• 10: copper interface speed is 1 gigabit

• 11: reserved

Link partner duplex capability:

• 1: copper interface is capable of operating in full-duplex mode

• 0: copper interface is capable of operating in half-duplex mode

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Bit(s)

14

ACK

15

Name

RO

R/W

COPPER_LINK_STATUS

RO

SGMII PHY Mode Auto Negotiation

Description

Acknowledge. A value of 1 indicates that the link partner has received 3 consecutive matching ability values from the device.

Copper link partner status:

• 1: copper interface link is up

• 0: copper interface link is down

6-25

SGMII PHY Mode Auto Negotiation

When the SGMII mode and the SGMII PHY mode auto-negotiation is enabled, set the dev_ability register before the auto-negotiation process so that the link partner can identify the copper speed, duplex status, and link status.

When the auto-negotiation is complete, Triple-Speed Ethernet IP core speed and the duplex mode will be resolved based on the value that you set in the dev_ability

register. You can get the value for the dev_ability

register from the system level where the Triple-Speed Ethernet IP core is integrated. If the

IP core is integrated in the system level with another IP that resolves the copper speed and duplex information, use these values to set the dev_ability

register.

Table 6-17: Dev_Ability Register Bits Description in SGMII PHY Mode

Bit(s) Name

9:0 Reserved

11:10

SPEED[1:0]

12

13

14

15

COPPER_DUPLEX_

STATUS

Reserved

ACK

COPPER_LINK_STATUS

RW

RW

RO

RW

R/W Description

Always set bit 0 to 1 and bits1–9 to 0.

Link partner interface speed:

• 00: copper interface speed is 10 Mbps

• 01: copper interface speed is 100 Mbps

• 10: copper interface speed is 1 gigabit

• 11: reserved

Link partner duplex capability:

• 1: copper interface is capable of operating in full-duplex mode

• 0: copper interface is capable of operating in half-duplex mode

• 1 Gbps speed does not support half-duplex mode.

Always set this bit to 0.

Acknowledge. Value as specified in the IEEE

802.3z standard.

Copper link partner status:

• 1: copper interface link is up

• 0: copper interface link is down

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An_Expansion Register (Word Offset 0x06)

An_Expansion Register (Word Offset 0x06)

Table 6-18: An_Expansion Register Description

Bit(s)

0

1

Name

LINK_PARTNER_AUTO_

NEGOTIATION_ABLE

PAGE_RECEIVE

2

NEXT_PAGE_ABLE

15:3 Reserved

RO

RO

R/W Description

A value of 1 indicates that the link partner supports auto-negotiation. The reset value is 0.

A value of 1 indicates that a new page is received with new partner ability available in the register partner_ability

. The bit is set to

0 (reset value) when the system management agent performs a read access.

Unused. Always set to 0.

If_Mode Register (Word Offset 0x14)

Table 6-19: IF_Mode Register Description

Bit(s)

0

SGMII_ENA

Name R/W

RW

1

USE_SGMII_AN

3:2

SGMII_SPEED[1:0]

RW

RW

Description

Determines the PCS function operating mode.

Setting this bit to 1 enables SGMII mode. Setting this bit to 0 enables 1000BASE-X gigabit mode.

This bit applies only to SGMII mode. Setting this bit to 1 causes the PCS function to be configured with the link partner abilities advertised during auto-negotiation. If this bit is set to 0, it is recommended for the PCS function to be configured with the

SGMII_SPEED

and

SGMII_

DUPLEX

bits.

SGMII speed. When the PCS function operates in

SGMII mode (

SGMII_ENA

= 1) and programed not to be automatically configured (

USE_SGMII_AN

=

0), set the speed as follows:

• 00: 10 Mbps

• 01: 100 Mbps

• 10: 1 Gigabit

• 11: Reserved

These bits are ignored when

SGMII_ENA

is 0 or

USE_SGMII_AN

is 1. These bits are only valid if you only enable the SGMII mode and not the autonegotiation mode.

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Bit(s)

4

Name

SGMII_DUPLEX

5

SGMII_AN_MODE

R/W

RW

RW

Register Initialization

Description

SGMII half-duplex mode. Setting this bit to 1 enables half duplex for 10/100 Mbps speed. This bit is ignored when

SGMII_ENA

is 0 or

USE_SGMII_

AN

is 1. These bits are only valid if you only enable the SGMII mode and not the auto-negotiation mode.

SGMII auto-negotiation mode:

• 1: enable SGMII PHY mode

• 0: enable SGMII MAC mode

This bit resets to 0, which defaults to SGMII MAC mode.

6-27

15:6 Reserved

Register Initialization

The Triple-Speed Ethernet MegaCore function supports various types of interface commonly used by the following Ethernet solutions:

• MII/GMII

• RGMII

• 10-bit Interface

• SGMII

• 1000BASE-X

• Management Data Input/Output (MDIO) for external PHY register configuration

When using the Triple-Speed Ethernet MegaCore function with an external interface, you must understand the requirements and initialize the registers.

Register initialization mainly performed in the following configurations:

• External PHY Initialization using MDIO (Optional)

• PCS Configuration Register Initialization

• MAC Configuration Register Initialization

This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences:

Triple-Speed Ethernet System with MII/GMII or RGMII

on page 6-27

Triple-Speed Ethernet System with SGMII

on page 6-30

Triple-Speed Ethernet System with 1000BASE-X Interface

on page 6-31

Triple-Speed Ethernet System with MII/GMII or RGMII

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Triple-Speed Ethernet System with MII/GMII or RGMII

Figure 6-2: Triple-Speed Ethernet System with MII/GMII or RGMII with Register Initialization

Recommendation

10/100/1000 Mbps MAC

MII/GMII/RGMII Interface

External PHY

Avalon ST TX

Avalon ST RX

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Copper/Fiber

Interface

Avalon MM

MAC

Register

Space

MDIO Space 0

MDIO Space 1

MDIO

Host

PHY

Register

Space

MDIO

Slave

MDIO

Use the following recommended initialization sequences for the example in

Figure 6–2

.

1. External PHY Initialization using MDIO

//Assume the External PHY Address is 0x0A mdio_addr0 = 0x0A

//External PHY Register will Map to MDIO Space 0

Read/write to MDIO space 0 (dword offset 0x80 - 0x9F) = Read/write to PHY Register 0 to 31

2. MAC Configuration Register Initialization

a. Disable MAC Transmit and Receive DatapathDisable the MAC transmit and receive datapath before performing any changes to configuration.

//Set TX_ENA and RX_ENA bit to 0 in Command Config Register

Command_config Register = 0x00802220

//Read the TX_ENA and RX_ENA bit is set 0 to ensure TX and RX path is disable

Wait Command_config Register = 0x00802220

b. MAC FIFO Configuration

Tx_section_empty = Max FIFO size - 16

Tx_almost_full = 3

Tx_almost_empty = 8

Rx_section_empty = Max FIFO size - 16

Rx_almost_full = 8

Rx_almost_empty = 8

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Triple-Speed Ethernet System with MII/GMII or RGMII

6-29

//Cut Throught Mode, Set this Threshold to 0 to enable Store and Forward Mode

Tx_section_full = 16

//Cut Throught Mode, Set this Threshold to 0 to enable Store and Forward Mode

Rx_section_full = 16

c. MAC Address Configuration

//MAC address is 00-1C-23-17-4A-CB mac_0 = 0x17231C00 mac_1 = 0x0000CB4A

d. MAC Function Configuration

//Maximum Frame Length is 1518 bytes

Frm_length = 1518

//Minimum Inter Packet Gap is 12 bytes

Tx_ipg_length = 12

//Maximum Pause Quanta Value for Flow Control

Pause_quant = 0xFFFF

//Set the MAC with the following option:

// 100Mbps, User can get this information from the PHY status/PCS status

//Full Duplex, User can get this information from the PHY status/PCS status

//Padding Removal on Receive

//CRC Removal

//TX MAC Address Insertion on Transmit Packet

//Select mac_0 and mac_1 as the source MAC Address

Command_config Register = 0x00800220

e. Reset MAC

Altera recommends that you perform a software reset when there is a change in the MAC speed or duplex. The MAC software reset bit self-clears when the software reset is complete.

//Set SW_RESET bit to 1

Command_config Register = 0x00802220

Wait Command_config Register = 0x00800220

f. Enable MAC Transmit and Receive Datapath

//Set TX_ENA and RX_ENA to 1 in Command Config Register

Command_config Register = 0x00800223

//Read the TX_ENA and RX_ENA bit is set 1 to ensure TX and RX path is enable

Wait Command_config Register = 0x00800223

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Triple-Speed Ethernet System with SGMII

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Triple-Speed Ethernet System with SGMII

Figure 6-3: Triple-Speed Ethernet System with SGMII with Register Initialization Recommendation

Avalon ST TX

10/100/1000 Mbps MAC 1000BASE-X/

SGMII PCS

SGMII Interface (1.25 Gbps)

External PHY

Avalon ST RX

Copper/Fiber

Interface

Avalon MM

MAC

Register

Space

MDIO Space 0

MDIO Space 1

MDIO

Host

PCS

Register

Space

PHY

Register

Space

MDIO

Slave

MDIO

Use the following recommended initialization sequences for the example in

Figure 6–4

.

1. External PHY Initialization using MDIO

Refer to step 1 in

Triple-Speed Ethernet System with MII/GMII or RGMII

on page 6-27.

2. PCS Configuration Register Initialization

a. Set Auto Negotiation Link Timer

//Set Link timer to 1.6ms for SGMII link_timer (address offset 0x12) = 0x0D40

Link_timer (address offset 0x13) = 0x03

b. Configure SGMII

//Enable SGMII Interface and Enable SGMII Auto Negotiation

//SGMII_ENA = 1, USE_SGMII_AN = 1 if_mode = 0x0003

c. Enable Auto Negotiation

//Enable Auto Negotiation

//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 can be ignore

PCS Control Register = 0x1140

d. PCS Reset

//PCS Software reset is recommended where there any configuration changed

//RESET = 1

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Triple-Speed Ethernet System with 1000BASE-X Interface

6-31

PCS Control Register = 0x9140

Wait PCS Control Register RESET bit is clear

3. MAC Configuration Register Initialization

Refer to step 2 in

Triple-Speed Ethernet System with MII/GMII or RGMII

on page 6-27.

Note: If 1000BASE-X/SGMII PCS is initialized, set the

ETH_SPEED

(bit 3) and

ENA_10

(bit 25) in command_config

HD_ENA

register to 0. If half duplex is reported in the PHY/PCS status register, set the

(bit 10) to 1 in command_config

register.

Triple-Speed Ethernet System with 1000BASE-X Interface

Figure 6-4: Triple-Speed Ethernet System with 1000BASE-X Interface with Register Initialization

Recommendation

Avalon ST TX

10/100/1000 Mbps MAC

1000BASE-X Interface (1.25 Gbps)

1000BASE-X/

SGMII PCS

1000BASE-X

Optical

Tranceiver (SFP)

Avalon ST RX

Fiber

Interface

Avalon MM

MAC

Register

Space

MDIO Space 0

MDIO Space 1

MDIO

Host

PCS

Register

Space

Use the following recommended initialization sequences for the example in

Figure 6–5

.

1. External PHY Initialization using MDIO

Refer to step 1 in

Triple-Speed Ethernet System with MII/GMII or RGMII

on page 6-27.

2. PCS Configuration Register Initialization

a. Set Auto Negotiation Link Timer

//Set Link timer to 10ms for 1000BASE-X link_timer (address offset 0x12) = 0x12D0 link_timer (address offset 0x13) = 0x13

b. Configure SGMII

//1000BASE-X/SGMII PCS is default in 1000BASE-X Mode

//SGMII_ENA = 0, USE_SGMII_AN = 0 if_mode = 0x0000

c. Enable Auto Negotiation

//Enable Auto Negotiation

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Triple-Speed Ethernet System with 1000BASE-X Interface

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//AUTO_NEGOTIATION_ENA = 1, Bit 6,8,13 is Read Only

PCS Control Register = 0x1140

d. PCS Reset

//PCS Software reset is recommended where there any configuration changed

//RESET = 1

PCS Control Register = 0x9140

Wait PCS Control Register RESET bit is clear

3. MAC Configuration Register Initialization

Refer to step 2 in

Triple-Speed Ethernet System with MII/GMII or RGMII

on page 6-27.

Note: If 1000BASE-X/SGMII PCS is initialized, set the

ETH_SPEED

(bit 3) and

ENA_10

(bit 25) in command_config

HD_ENA

register to 0. If half duplex is reported in the PHY/PCS status register, set the

(bit 10) to 1 in command_config

register.

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Interface Signals

The following sections describe the Triple-Speed Ethernet MegaCore function interface signals:

10/100/1000 Ethernet MAC Signals

on page 7-2

10/100/1000 Multiport Ethernet MAC Signals

on page 7-13

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals

on page 7-18

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

on page 7-22

10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals

on page 7-

24

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA

on page

7-27

1000BASE-X/SGMII PCS Signals

on page 7-36

1000BASE-X/SGMII PCS and PMA Signals

on page 7-41

Note: To view all the interface signal names, turn on Show Signals in the Block Diagram tab in the

Triple-Speed Ethernet parameter editor interface. Otherwise, only the connection signal names are shown.

7

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

7-2

10/100/1000 Ethernet MAC Signals

10/100/1000 Ethernet MAC Signals

Figure 7-1: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers Signals

MAC Transmit

Interface Signals

MAC Receive

Interface Signals

Pause and Magic

Packet Signals

MAC Control

Interface

Signals

n

2

n

2

8

32

32

6

18

4

10/100/1000 Ethernet MAC

ff_tx_clk ff_tx_data [DATAWIDTH-1:0] ff_tx_mod [1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc _fwd tx_ff_uflow ff_tx_rdy ff_tx_septy ff_tx_a_full ff_tx_a_empty ff_rx_clk ff_rx_rdy ff_rx_data [DATAWIDTH-1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_rx_a_full ff_rx_a_empty xon _gen xoff_gen magic _sleep _n magic _wakeup clk reg _addr [7:0] reg _wr reg _rd reg _data _in[31:0] reg _data _out[31:0] reg _busy reset rx_clk tx_clk rx_clkena tx_clkena gm_rx_d[7:0] gm_rx_dv gm_rx_err gm_tx_d[7:0] gm_tx_en gm_tx_err rgmii_in[3:0] rx_control rgmii_out[3:0] tx_control m_rx_d[3:0] m_rx_en m_rx_err m_rx_col m_rx_crs m_tx_d[3:0] m_tx_en m_tx_err mdio_in mdc mdio_oen mdio_out mac _eccstatus [1:0] set_10_n set_1000_n ena_10_n eth_mode_n

8

8

4

4

4

4

Reset

Signal

Clock

Signals

GMII

Signals

RGMII

Signals

MII

Signals

PHY

Management

Signals

ECC

Status

Signal

MAC

Status

Signals

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Clock and Reset Signal

Data transfers on the MAC Ethernet-side interface are synchronous to the receive and transmit clocks.

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Table 7-1: GMII/RGMII/MII Clock Signal

I/O Name

tx_clk

(In Qsys: pcs_ mac_tx_clock_ connection

)

I

I rx_clk

(In Qsys: pcs_ mac_rx_clock_ connection

) tx_clkena

I

MAC Control Interface Signals

Description

GMII / RGMII/ MII transmit clock. Provides the timing reference for all GMII / MII transmit signals. The values of gm_tx_d[7:0], gm_tx_en, gm_tx_err

, and of m_tx_d[3:0]

, m_tx_en

, m_tx_err are valid on the rising edge of tx_clk

.

GMII /RGMII/ MII receive clock. Provides the timing reference for all rx related signals. The values of gm_rx_err

, and of m_rx_d[3:0]

, m_rx_en, m_rx_err

are valid on the rising edge of rx_clk

.

gm_rx_d[7:0]

, gm_rx_dv

, rx_clkena

I

Clock enable from the PHY IP. When you turn on the Use clock

enable for MAC parameter, this signal is used together with tx_ clk

and rx_clk

to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. (2)

Clock enable from the PHY IP. When you turn on the Use clock

enable for MAC parameter, this signal is used together with tx_ clk

and rx_clk

to generate 125 MHz, 25 MHz, and 2.5 MHz clocks.

(3)

Table 7-2: Reset Signal

Name

reset

I

I/O Description

Assert this signal to reset all logic in the MAC and PCS control interface. The signal must be asserted for at least three clock cycles.

MAC Control Interface Signals

The MAC control interface is an Avalon-MM slave port that provides access to the register space.

Table 7-3: MAC Control Interface Signals

Name I/O Description

clk clk

Avalon-MM

Signal Type

I reg_wr reg_rd reg_addr[7:0] reg_data_in[31:0] write read address writedata

I

I

I

I

Register access reference clock. Set the signal to a value less than or equal to 125 MHz.

Register write enable.

Register read enable.

32-bit word-aligned register address.

Register write data. Bit 0 is the least signifi‐ cant bit.

7-3

(2)

(3)

For configurations without internal FIFO, this signal is called tx_clkena_<n>

For configurations without internal FIFO, this signal is called rx_clkena_<n>

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MAC Status Signals

Name Avalon-MM

Signal Type

reg_data_out[31:0] readdata

I/O Description

reg_busy waitrequest

O

O

Register read data. Bit 0 is the least significant bit.

Register interface busy. Asserted during register read or register write access; deasserted when the current register access completes.

MAC Status Signals

The MAC status signals which allow you to set the transfer mode of the Ethernet-side interface.

Table 7-4: MAC Status Signals

Name

eth_mode ena_10 set_1000 set_10

I/O Description

I

O Ethernet mode. This signal is set to 1 when the MAC function is configured to operate at 1000 Mbps; set to 0 when it is configured to operate at 10/100 Mbps.

I

O 10 Mbps enable. This signal is set to 1 to indicate that the PHY interface should operate at 10 Mbps. Valid only when the eth_ mode

signal is set to 0.

Gigabit mode selection. Can be driven to 1 by an external device, for example a PHY device, to set the MAC function to operate in gigabit. When set to 0, the MAC is set to operate in 10/100 Mbps.

This signal is ignored when the

ETH_SPEED

bit in the command_ config

register is set to 1.

10 Mbps selection. Can be driven to 1 by an external device, for example a PHY device, to indicate that the MAC function is connected to a 10-Mbps PHY device. When set to 0, the MAC function is set to operate in 100-Mbps or gigabit mode. This signal is ignored when the

ETH_SPEED

or

ENA_10

bit in the command_config

register is set to 1. The priority than this signal.

ENA_10

bit has a higher

MAC Receive Interface Signals

Table 7-5: MAC Receive Interface Signals

Name Avalon-ST

Signal Type

Avalon-ST Signals

ff_rx_clk

(In Qsys: receive_ clock_connection

) clk

I

I/O Description

Receive clock. All signals on the Avalon-ST receive interface are synchronized on the rising edge of this clock. Set this clock to the frequency required to get the desired bandwidth on this interface. This clock can be completely independent from rx_clk

.

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Name

ff_rx_dval ff_rx_data

[(DATAWIDTH-1):0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop ff_rx_rdy rx_err[5:0]

Avalon-ST

Signal Type

valid data empty startofpacket endofpacket ready error

I

O

I/O

O

O

O

O

O

MAC Receive Interface Signals

Description

Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: ff_rx_data[(DATAWIDTH -1):0]

, ff_rx_sop

, ff_rx_eop

,

rx_err[5:0]

, rx_ frm_type[3:0]

, and

rx_err_stat[17:0]

.

Receive data. When

DATAWIDTH

is 32, the first byte received is ff_rx_data[31:24]

followed by ff_rx_data[23:16]

and so forth.

Receive data modulo. Indicates invalid bytes in the final frame word:

• 11:

ff_rx_data[23:0]

is not valid

• 10: ff_rx_data[15:0]

is not valid

• 01: ff_rx_data[7:0]

is not valid

• 00: ff_rx_data[31:0]

is valid

This signal applies only when

DATAWIDTH

is set to 32.

Receive start of packet. Asserted when the first byte or word of a frame is driven on ff_rx_ data[(DATAWIDTH-1):0]

.

Receive end of packet. Asserted when the last byte or word of frame data is driven on ff_ rx_data[(DATAWIDTH-1):0]

.

Receive application ready. Assert this signal on the rising edge of ff_rx_clk

when the user application is ready to receive data from the

MAC function.

Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. See

Table

7-7

for the bit description.

Component-Specific Signals

ff_rx_dsav

— O Receive frame available. When asserted, this signal indicates that the internal receive FIFO buffer contains some data to be read but not necessarily a complete frame. The user application may want to start reading from the FIFO buffer.

This signal remains deasserted in the store and forward mode.

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MAC Receive Interface Signals

Name

rx_frm_type[3:0]

Avalon-ST

Signal Type

I/O Description

ff_rx_a_full ff_rx_a_empty rx_err_stat[17:0]

O

O

O

O

Frame type. See

Table 7-6

for the bit descrip‐

tion.

Asserted when the FIFO buffer reaches the almost-full threshold.

Asserted when the FIFO buffer goes below the almost-empty threshold.

rx_err_stat[17]

: One indicates that the receive frame is a stacked VLAN frame.

rx_err_stat[16]

: One indicates that the receive frame is either a VLAN or stacked

VLAN frame.

rx_err_stat[15:0]

: The value of the length/ type field of the receive frame.

Table 7-6: rx_frm_type Bit Description

Bit

3

2

1

0

Description

Indicates VLAN frames. Asserted with ff_rx_sop

and remains asserted until the end of the frame.

Indicates broadcast frames. Asserted with ff_rx_sop

and remains asserted until the end of the frame.

Indicates multicast frames. Asserted with ff_rx_sop

and remains asserted until the end of the frame.

Indicates unicast frames. Asserted with ff_rx_sop

and remains asserted until the end of the frame.

Table 7-7: rx_err Bit Description

Bit

5

4

3

2

1

(1)

(1)

Description

Collision error. Asserted when the frame was received with a collision.

Corrupted receive frame caused by PHY or PCS error. Asserted when the error is detected on the MII/GMII/RGMII.

Truncated receive frame. Asserted when the receive frame is truncated due to an overflow in the receive FIFO buffer.

CRC error. Asserted when the frame is received with a CRC-32 error. This error bit applies only to frames with a valid length. Refer to

Length Checking

on page 4-11.

Invalid length error. Asserted when the receive frame has an invalid length as defined by the IEEE Standard 802.3. For more information on the frame length, refer to

Length Checking

on page 4-11 .

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MAC Transmit Interface Signals

Bit Description

0

Receive frame error. Indicates that an error has occurred. It is the logical OR of rx_ err

[5:1].

Note to

Table 7-7

:

1. Bits 1 and 2 are not mutually exclusive. Ignore CRC error rx_err[2]

signal if it is asserted at the same time as the invalid length error rx_err[1]

signal.

MAC Transmit Interface Signals

Table 7-8: MAC Transmit Interface Signals

Name Avalon-ST Signal

Type

Avalon-ST Signals

ff_tx_clk

(In Qsys: transmit_ clock_connection

) clk

I

I/O

ff_tx_wren ff_tx_data

[(DATAWIDTH-1):0] valid data

I

I

Description

Transmit clock. All transmit signals are synchronized on the rising edge of this clock.

Set this clock to the required frequency to get the desired bandwidth on the Avalon-ST transmit interface. This clock can be completely independent from tx_clk

.

Transmit data write enable. Assert this signal to indicate that the data on the following signals are valid: ff_tx_data[(DATAWIDTH-

1):0]

, ff_tx_sop

, and ff_tx_eop

.

In cut-through mode, keep this signal asserted throughout the frame transmission.

Otherwise, the frame is truncated and forwarded to the Ethernet-side interface with an error.

Transmit data.

DATAWIDTH

can be either 8 or

32 depending on the FIFO data width configured. When

DATAWIDTH

is 32, the first byte transmitted is ff_tx_data[31:24] followed by ff_tx_data[23:16]

and so forth.

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MAC Transmit Interface Signals

Name

ff_tx_mod[1:0]

Avalon-ST Signal

empty

Type

I

I/O

ff_tx_sop ff_tx_eop ff_tx_err ff_tx_rdy startofpacket endofpacket error ready

I

I

I

O

Description

Transmit data modulo. Indicates invalid bytes in the final frame word:

• 11: ff_tx_data[23:0]

is not valid

• 10: ff_tx_data[15:0]

is not valid

• 01: ff_tx_data[7:0]

is not valid

• 00: ff_tx_data[31:0]

is valid

This signal applies only when

DATAWIDTH

is set to 32.

Transmit start of packet. Assert this signal when the first byte in the frame (the first byte of the destination address) is driven on ff_ tx_data

.

Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on ff_tx_data

.

Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function forwards the invalid frame to the GMII with an error.

MAC ready. When asserted, the MAC function is ready to accept data from the user application.

Component-Specific Signals

ff_tx_crc_fwd

— I tx_ff_uflow ff_tx_septy ff_tx_a_full

O

O

O

Transmit CRC insertion. Set this signal to 0 when ff_tx_eop

is set to 1 to instruct the

MAC function to compute a CRC and insert it into the frame. If this signal is set to 1, the user application is expected to provide the

CRC.

Asserted when an underflow occurs on the transmit FIFO buffer.

Deasserted when the FIFO buffer is filled to or above the section-empty threshold defined in the tx_section_empty

register. User applications can use this signal to indicate when to stop writing to the FIFO buffer and initiate backpressure.

Asserted when the transmit FIFO buffer reaches the almost- full threshold.

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Name

ff_tx_a_empty

Avalon-ST Signal

Type

— O

I/O

Pause and Magic Packet Signals

Description

Asserted when the transmit FIFO buffer goes below the almost-empty threshold.

Pause and Magic Packet Signals

The pause and magic packet signals are component-specific signals.

Table 7-9: Pause and Magic Packet Signals

Name

xon_gen xoff_gen magic_slee p_n magic_wakeup

I

I

I

I/O

0

Description

Assert this signal for at least 1 tx_clk

clock cycle to trigger the generation of a pause frame with a 0 pause quanta. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.

This signal is not in use in the following conditions:

• Ignored when the xon_gen

bit in the command_config

register is set to 1.

• Absent when the Enable full duplex flow control option is turned off.

Assert this signal for at least one tx_clk

clock cycle to trigger the generation of a pause frame with a pause quanta configured in the pause_quant

register. The MAC function generates the pause frame independent of the status of the receive FIFO buffer.

This signal is not in use in the following conditions:

• Ignored if the xoff_gen

bit in the command_config register is set to 1.

• Absent when the Enable full duplex flow control option is turned off.

Assert this active-low signal to put the node into a power-down state.

If magic packets are supported (the

MAGIC_ENA

bit in the command_config register is set to 1), the receiver logic stops writing data to the receive FIFO buffer and the magic packet detection logic is enabled. Setting this signal to 1 restores the normal frame reception mode.

This signal is present only if the Enable magic packet detection option is turned on.

If the MAC function is in the power-down state, the MAC function asserts this signal to indicate that a magic packet has been detected and the node is requested to restore its normal frame reception mode.

This signal is present only if the Enable magic packet detection option is turned on.

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7-10

MII/GMII/RGMII Signals

MII/GMII/RGMII Signals

Table 7-10: GMII/RGMII/MII Signals

I/O Name

GMII Transmit

gm_tx_d[7:0] gm_tx_en

I

O

O

Description

GMII transmit data bus.

Asserted to indicate that the data on the GMII transmit data bus is valid.

Asserted to indicate to the PHY that the frame sent is invalid.

gm_tx_err

GMII Receive

gm_rx_d[7:0] gm_rx_dv gm_rx_err

I

I

I GMII receive data bus.

Assert this signal to indicate that the data on the GMII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.

The PHY asserts this signal to indicate that the receive frame contains errors.

RGMII Transmit

rgmii_out[3:0]

O tx_control

O

RGMII transmit data bus. Drives gm_tx_d[3:0]

on the positive edge of tx_clk

and gm_tx_d[7:4]

on the negative edge of tx_ clk

.

Control output signal. Drives gm_tx_en

on the positive edge of tx_clk

and a logical derivative of ( gm_tx_en XOR gm_tx_err)

on the negative edge of tx_clk

.

RGMII Receive

rgmii_in[3:0]

I rx_control

I

RGMII receive data bus. Expects gm_rx_d[3:0]

on the positive edge of rx_clk

and gm_rx_d[7:4]

on the negative edge of rx_ clk

.

RGMII control input signal. Expects gm_rx_dv

on the positive edge of rx_clk

and a logical derivative of ( gm_rx_dv XOR gm_rx_ err)

on the negative edge of rx_clk

.

MII Transmit

m_tx_d[3:0] m_tx_en m_tx_err

O

O

O

MII transmit data bus.

Asserted to indicate that the data on the MII transmit data bus is valid.

Asserted to indicate to the PHY device that the frame sent is invalid.

MII Receive

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Name

m_rx_d[3:0] m_rx_en m_rx_err

PHY Management Signals

I

I

I

I/O Description

MII receive data bus.

Assert this signal to indicate that the data on the MII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.

The PHY asserts this signal to Indicate that the receive frame contains errors.

MII PHY Status

m_rx_col m_rx_crs

I

I Collision detection. The PHY asserts this signal to indicate a collision during frame transmission. This signal is not used in fullduplex or gigabit mode.

Carrier sense detection. The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line. This signal is not used in full-duplex or gigabit mode.

PHY Management Signals

Table 7-11: PHY Management Interface Signals

Name

mdio_in mdio_out mdio_oen mdc

I

O

O

I/O

O

Description

Management data input.

Management data output.

An active-low signal that enables mdio_in

or mdio_out

. For more information about the MDIO connection, refer to

MDIO

Connection

on page 4-23.

Management data clock. Generated from the Avalon-MM interface clock signal, clk

. Specify the division factor using the

Host clock divisor parameter such that the frequency of this clock does not exceed 2.5 MHz. For more information about the

parameters, refer to

Ethernet MAC Options

on page 3-2.

A data bit is shifted in/out on each rising edge of this clock. All fields are shifted in and out starting from the most significant bit.

7-11

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ECC Status Signals

ECC Status Signals

Table 7-12: ECC Status Signals

Name

mac_eccstatus[1:0]

O

I/O Description

Indicates the ECC status. This signal is synchronized to the reg_ clk

clock domain.

• 11: An uncorrectable error occurred and the error data appears at the output.

• 10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.

• 01: Not valid.

• 00: No error.

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10/100/1000 Multiport Ethernet MAC Signals

10/100/1000 Multiport Ethernet MAC Signals

Figure 7-2: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers Signals

7-13

Clock

Signals

MAC Receive

Interface Signals

Classification

Signals

Pause and Magic

Packet Signals

MAC Control

Signals n

2

5

8

8

8

5

32

32

Multi-Port MAC

mac_tx_clk_n mac_rx_clk_n data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n pkt_class _valid_n pkt_class _data_n[4:0] rx_afull_channel[CHANNEL _WIDTH -1:0] rx_afull_data[1:0] rx_afull_valid rx_afull_clk xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n clk reg_addr[7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy reset rx_clk_n tx_clk_n rx_clkena_n tx_clkena_n gm_rx_d_n[7:0] gm_rx_dv_n gm_rx_err_n gm_tx_d_n[7:0] gm_tx_en_n gm_tx_err_n

8

8 rgmii_in_n[3:0] rx_control_n rgmii_out_n[3:0] tx_control_n m

_rx_d_n[3:0] m_rx_dv_n m_rx_err_n m_col_n m_crs_n m_tx_d_n[3:0] m_tx_en_n m_tx_err_n mdio_in mdc mdio_oen mdio_out

4

4

4

4 set_10_n set_1000_n ena_10_n eth_mode_n mac_eccstatus[1:0]

Clock

Signals

MII

Signals

PHY

Signals

MAC

Signals

ECC Status

Signal

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Multiport MAC Clock and Reset Signals

Multiport MAC Clock and Reset Signals

Table 7-13: Clock Signals

Name

mac_rx_clk clk

Avalon-ST

Signal Type

O

I/O

mac_tx_clk clk

O

Description

Receive MAC clock (2.5/25/125 MHz) for the

Avalon-ST receive data and receive packet classification interfaces.

Transmit MAC clock (2.5/25/125 MHz) for the Avalon-ST transmit data interface.

Multiport MAC Receive Interface Signals

Table 7-14: MAC Receive Interface Signals

Name

data_rx_valid

_n

Avalon-ST

Signal Type

valid

O

I/O

data_rx_data_ n

[7:0] data data_rx_sop_ n startofpacket

O

O data_rx_eop_ n data_rx_ready_ n data_rx_error_ n

[4:0] endofpacket ready error

I

O

O

Description

Receive data valid. When asserted, this signal indicates that the data on the following signals are valid: data_rx_data

_n, data_rx_sop

_n, data_rx_eop

_n, and data_rx_error

_n.

Receive data.

Receive start of packet. Asserted when the first byte or word of a frame is driven on data_rx_ data

_n.

Receive end of packet. Asserted when the last byte or word of frame data is driven on data_ rx_data

_n.

Receive application ready. Assert this signal on the rising edge of data_rx_clk

_n when the user application is ready to receive data from the MAC function.

If the user application is not ready to receive data, the packet is dropped or truncated with an error.

Receive error. Asserted with the final byte in the frame to indicate that an error was detected when receiving the frame. For the description of each bit, refer to the description

of bits 5 to 1 in

MAC Receive Interface

Signals

on page 7-4 . Bit 4 of this signal maps to bit 5 in the table and so forth.

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Multiport MAC Transmit Interface Signals

Table 7-15: MAC Transmit Interface Signals

Name Avalon-ST

Signal Type

I/O

Avalon-ST Signals

data_tx_valid_ n valid I data_tx_data

_n[7:0] data data_tx_sop

_n startofpacket

I

I data_tx_eop

_n data_tx_error

_n data_tx_ready

_n endofpacket error ready

I

I

O

Multiport MAC Transmit Interface Signals

Description

Transmit data valid. Assert this signal to indicate that the data on the following signals are valid: data_tx_data

_n, data_tx_sop

_n, data_tx_eop

_n, and data_tx_error

_n.

Transmit data.

Transmit start of packet. Assert this signal when the first byte in the frame is driven on data_tx_data

_n.

Transmit end of packet. Assert this signal when the last byte in the frame (the last byte of the FCS field) is driven on data_tx_data

_n.

Transmit frame error. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. The MAC function then forwards the frame to the GMII with error.

MAC ready. When asserted, this signal indicates that the MAC function is ready to accept data from the user application.

Component-Specific Signal

tx_crc_fwd

_n

I Transmit CRC insertion. Assert this active-low signal when data_tx_eop

_n is asserted for the

MAC function to compute the CRC and insert it into the frame. Otherwise, the user applica‐ tion is expected to provide the CRC.

7-15

Multiport MAC Packet Classification Signals

The MAC packet classification interface is an Avalon-ST source port which streams out receive packet classifications.

Table 7-16: MAC Packet Classification Signals

Name Avalon-ST

Signal Type

pkt_class_valid_ n valid

O

I/O Description

When asserted, this signal indicates that classifi‐ cation data is valid.

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Multiport MAC FIFO Status Signals

Name

pkt_class_data n[4:0]

_

Avalon-ST

Signal Type

data

O

I/O Description

Classification presented at the beginning of each packet:

Bit 4—Set to 1 for unicast frames.

Bit 3—Set to 1 for broadcast frames.

Bit 2—Set to 1 for multicast frames.

Bit 1—Set to 1 for VLAN frames.

Bit 0—Set to 1 for stacked VLAN frames.

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Multiport MAC FIFO Status Signals

The MAC FIFO status interface is an Avalon-ST sink port which streams in information on the fill level of the external FIFO buffer to the MAC function.

Table 7-17: MAC FIFO Status Signals

Signal Name

rx_afull_valid_ n

Avalon-ST

Signal Type

valid I

I/O Description

rx_afull_data

_n[1:0] data

I

I

Assert this signal to indicate that the fill level of the external FIFO buffer, rx_afull_data

_ n[1:0],is valid.

Carries the fill level of the external FIFO buffer: rx_afull_data

_n[1]—Set to 1 if the external receive FIFO buffer reaches the initial warning level indicating that it is almost full. Upon detecting this, the MAC function generates pause frames.

rx_afull_data

_n[0]—Set to 1 if the external receive FIFO buffer reaches the critical level before it overflows. The FIFO buffer can be considered overflow if this bit is set to 1 in the middle of a packet transfer.

The port number the status applies to.

rx_afull_channel

[(CHANNEL_WIDTH-1):

0] rx_afull_clk channel clk I The clock that drives the MAC FIFO status interface.

Table 7-18: References

Interface Signal

Clock and reset signals

MAC control interface

Section

Clock and Reset Signal

on page 7-2

MAC Control Interface Signals

on page 7-3

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Multiport MAC FIFO Status Signals

Interface Signal Section

MAC transmit interface

MAC Transmit Interface Signals

on page 7-7

MAC receive interface

Status signals

MAC Receive Interface Signals

MAC Status Signals

on page 7-4

on page 7-4

Pause and Magic Packet Signals

on page 7-9

Pause and magic packet signals

MII/GMII/RGMII interface

MII/GMII/RGMII Signals

on page 7-10

PHY management signals

PHY Management Signals

on page 7-11

ECC status signals

ECC Status Signals

on page 7-12

7-17

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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals

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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals

Figure 7-3: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, with 1000BASE-X/SGMII

PCS Signals

MAC Transmit

Interface Signals

MAC Receive

Interface Signals

Pause and Magic

Packet Signals

8

MAC Control

Interface

Signals

32

32

6

18

4 n

2 n

2

10/100/1000 Ethernet MAC with 1000 Base-X PCS/SGMII

ff_tx_clk ff_tx_data[DATAWIDTH-1:0] ff_tx_mod[1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc_fwd tx_ff_uflow ff_tx_rdy ff_tx_septy ff_tx_a_full ff_tx_a_empty reset tbi_rx_clk tbi_rx_d[9:0] tbi_tx_clk tbi_tx_d[9:0] led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err ff_rx_clk ff_rx_rdy ff_rx_data[DATAWIDTH-1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_rx_a_full ff_rx_a_empty xon_gen xoff_gen magic_sleep_n magic_wakeup mdio_in mdc mdio_oen mdio_out tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_locktodata rx_is_locktoref clk address [7:0] write read writedata[31:0] readdata[31:0] waitrequest pcs_eccstatus [1:0] sd_loopback powerdown

10

10

Reset

Signal

Ten Bit

Interface

Signals

Status

LED

Signals

PHY

Signals

Arria 10

Transceiver

Native PHY

Signals

ECC

Status

Signal

SERDES

Control

Signals

TBI Interface Signals

If the core variation does not include an embedded PMA, the PCS block provides a 125-MHz ten-bit interface (TBI) to an external SERDES chip.

Table 7-19: TBI Interface Signals for External SERDES Chip

Name

tbi_tx_d(9:0)

O

I/O Description

TBI transmit data. The PCS function transmits data on this bus synchronous to tbi_tx_clk

.

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Name

tbi_tx_clk tbi_rx_clk tbi_rx_d[9:0]

I

I

I

I/O

Status LED Control Signals

Description

125-MHz TBI transmit clock from external SERDES, typically sourced by the local reference clock oscillator.

125-MHz TBI receive clock from external SERDES, typically sourced by the line clock recovered from the encoded line stream.

TBI receive data. This bus carries the data from the external

SERDES. Synchronize the bus with tbi_rx_clk

. The data can be arbitrary aligned.

Status LED Control Signals

Table 7-20: Status LED Interface Signals

Name

led_link led_panel_link

O

I/O

O

Description

When asserted, this signal indicates a successful link synchroni‐ zation.

When asserted, this signal indicates the following behavior:

Mode

1000 Base-X without auto negotiation

SGMII mode without auto negotiation

1000 Base-X with auto negotia‐ tion

SGMII mode with MAC mode auto negotiation

SGMII mode with PHY mode auto negotiation

Signal Behavior

Similar to led_link

Similar to

Similar to

Similar to led_link led_an partner_ability

[15] led_an

and

Similar to led_an

and dev_ability [15] led_crs led_col led_an led_char_err

O

O

O

O

When asserted, this signal indicates some activities on the transmit and receive paths. When deasserted, it indicates no traffic on the paths.

When asserted, this signal indicates that a collision was detected during frame transmission. This signal is always deasserted when the PCS function operates in standard 1000BASE-X mode or in full-duplex mode when SGMII is enabled.

Auto-negotiation status. The PCS function asserts this signal when an auto-negotiation completes.

10-bit character error. Asserted for one tbi_rx_clk

cycle when an erroneous 10-bit character is detected.

7-19

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SERDES Control Signals

Name

led_disp_err

O

I/O Description

10-bit running disparity error. Asserted for one tbi_rx_clk cycle when a disparity error is detected. A running disparity error indicates that more than the previous and perhaps the current received group had an error.

SERDES Control Signals

Table 7-21: SERDES Control Signal

Name

powerdown

O

I/O

sd_loopback

O

Description

Power-down enable. Asserted when the PCS function is in power-down mode; deasserted when the PCS function is operating in normal mode. This signal is implemented only when an external SERDES is used.

SERDES Loopback Control. Asserted when the PCS function operates in loopback mode. You can use this signal to configure an external SERDES device to operate in loopback mode.

Arria 10 Transceiver Native PHY Signals

Table 7-22: Arria 10 Transceiver Native PHY Signals

Name

tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_lockedtodata

I

I

I

I

I

I

O

I

I

I/O

O

O

Description

Serial clock input from the transceiver PLL. The frequency of this clock depends on the data rate and clock division factor.

Reference clock input to the receive clock data recovery (CDR) circuitry.

Resets the analog transmit portion of the transceiver PHY.

Resets the digital transmit portion of the transceiver PHY.

Resets the analog receive portion of the transceiver PHY.

Resets the digital receive portion of the transceiver PHY.

When asserted, this signal indicates that the transmit channel is being calibrated.

When asserted, this signal indicates that the receive channel is being calibrated.

Force the receiver CDR to lock to the incoming data.

Force the receiver CDR to lock to the phase and frequency of the input reference clock.

When asserted, this signal indicates that the CDR PLL is locked to the incoming data rx_serial_data

.

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Name

rx_is_lockedtoref

O

I/O

ECC Status Signals

Description

When asserted, this signal indicates that the CDR PLL is locked to the incoming reference clock, rx_cdr_refclk

.

7-21

Related Information

Arria 10 Transceiver PHY User Guide

More information about Gigabit Ethernet (GbE) and GbE with 1588, the connection guidelines for a PHY design, and how to implement GbE/GbE with 1588 in Arria 10 Transceivers

ECC Status Signals

Table 7-23: ECC Status Signals

Name

pcs_eccstatus[1:0]

O

I/O Description

Indicates the ECC status. This signal is synchronized to the reg_ clk

clock domain.

11: An uncorrectable error occurred and the error data appears at the output.

10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.

01: Not valid.

00: No error.

For more information on the signals, refer to the respective sections shown in

Table 7-18

.

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10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

Figure 7-4: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers with

1000BASE-X/SGMII PCS Signals

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Clock

Signals

MAC Transmit

Interface Signals

MAC Receive

Interface Signals

MAC Packet

Signals

MAC FIFO

Status Signals

MAC Control

Interface

Signals

8

8

8

5

5 n

32

32

Multi-Port MAC with 1000BASE-X/SGMII PCS

mac_tx_clk_n mac_rx_clk_n reset data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n pkt_class _valid_n pkt_class _data_n[4:0] tbi_rx_clk_n tbi_rx_d_n[9:0] tbi_tx_clk_n tbi_tx_d_n[9:0] led_an_n led_crs_n led_col_n led_char_err_n led_link_n led_panel_link_n led_disp_err_n rx_afull_channel[CHANNEL_WIDTH-1:0] rx_afull_data[1:0] rx_afull_valid rx_afull_clk xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n clk reg_addr[(log2 MAX_CHANNELS+7):0][7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy mdio_in mdc mdio_oen mdio_out sd_loopback_n powerdown_n pcs_eccstatus[1:0]

10

10

Ten Bit

Interface

Signals

Status

LED

Signals

PHY

Management

Signals

Control

Signals

ECC Status

Signal

Table 7-24: References

Interface Signal

Clock and reset signals

MAC control interface

Section

Clock and Reset Signal

on page 7-2

MAC Control Interface Signals

on page 7-3

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Interface Signal

MAC transmit interface

MAC receive interface

MAC packet classification signals

MAC FIFO status signals

Pause and magic packet signals

PHY management signals

Ten-bit interface

Status LED signals

SERDES control signals

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals

Section

MAC Transmit Interface Signals

on page 7-7

MAC Receive Interface Signals

on page 7-4

Multiport MAC Packet Classification Signals

on page 7-15

Multiport MAC FIFO Status Signals

on page 7-16

Pause and Magic Packet Signals

on page 7-9

PHY Management Signals

on page 7-11

TBI Interface Signals

on page 7-18

Status LED Control Signals

on page 7-19

SERDES Control Signals

on page 7-20

7-23

Interface Signals

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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA...

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10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA

Signals

Figure 7-5: 10/100/1000 Ethernet MAC Function with Internal FIFO Buffers, and 1000BASE-X/SGMII PCS

With Embedded PMA Signals

MAC Transmit

Interface Signals

MAC Receive

Interface Signals

Pause and Magic

Packet Signals

MAC Control

Interface

Signals n

2 n

2

8

6

18

4

32

32

10/100/1000 Ethernet MAC and 1000BASE-X/SGMII PCS

ff_tx_clk ff_tx_data[DATAWIDTH -1:0] ff_tx_mod[1:0] ff_tx_sop ff_tx_eop ff_tx_err ff_tx_wren ff_tx_crc_fwd tx_ff_uflow ff_tx_rdy

with Embedded PMA

reset ref_clk rx_p tx_p ff_tx_septy ff_tx_a_full ff_tx_a_empty ff_rx_clk ff_rx_rdy ff_rx_data[DATAWIDTH -1:0] ff_rx_mod[1:0] ff_rx_sop ff_rx_eop rx_err[5:0] rx_err_stat[17:0] rx_frm_type[3:0] ff_rx_dsav ff_rx_dval ff_tx_a_full ff_tx_a_empty led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err mdio_in mdc mdio_oen mdio_out cdr_ref_clk_n xon_gen xoff_gen magic_sleep_n magic_wakeup mac_eccstatus[1:0] clk reg_addr[7:0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy rx_recovclkout gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in reconfig_clk reconfig_togxb reconfig_fromgxb

Reset

Signal

1.25 Gbps

Serial Signals

LED

Signals

PHY

Management

Signals

Transceiver

Native PHY

Signal

ECC Status

Signal

Control

Signals

Note to

Figure 7–5

:

1. The SERDES control signals are present in variations targeting devices with GX transceivers. For

Stratix II GX and Arria GX devices, the reconfiguration signals— reconfig_clk

,

reconfig_togxb

, and reconfig_fromgxb

—are included only when the option, Enable transceiver dynamic reconfigu‐

ration, is turned on. The reconfiguration signals— gxb_cal_blk_clk

, pcs_pwrdwn_out

,

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1.25 Gbps Serial Interface

7-25

gxb_pwrdn_in

, reconfig_clk

, and reconfig_busy

—are not present in variations targeting Arria 10,

Stratix V, Arria V, and Cyclone V devices with GX transceivers.

1.25 Gbps Serial Interface

If the variant includes an embedded PMA, the PMA provides a 1.25-GHz serial interface.

Table 7-25: 1.25 Gbps MDI Interface Signals

Name

ref_clk rx_p tx_p

I

I

O

I/O Description

125 MHz local reference clock oscillator.

Serial Differential Receive Interface.

Serial Differential Transmit Interface.

Transceiver Native PHY Signal

Table 7-26: Transceiver Native PHY Signal

Name

cdr_ref_clk_n

I

I/O Description

Port to connect the RX PLL reference clock with a frequency of

125 MHz when you enable SyncE support.

SERDES Control Signals

These signals apply only to PMA blocks implemented in devices with GX transceivers.

Table 7-27: SERDES Control Signal

Name

rx_recovclkout pcs_pwrdn_out gxb_pwrdn_in

I

O

O

I/O Description

Recovered clock from the PMA block.

Power-down status. Asserted when the PCS function is in power-down mode; deasserted when the PCS function is operating in normal mode. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.

This signal is not present in PMA blocks implemented in Arria

10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.

Power-down enable. Assert this signal to power down the transceiver quad block. This signal is implemented only when an internal SERDES is used with the option to export the power-down signal.

This signal is not present in PMA blocks implemented in Arria

10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.

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SERDES Control Signals

Name

gxb_cal_blk_clk reconfig_clk reconfig_togxb[n:0] reconfig_fromgxb[n:0] reconfig_busy I

I

I

I

I/O

O

Description

Calibration block clock for the ALT2GXB module (SERDES).

This clock is typically tied to the 125 MHz ref_clk

. Only implemented when an internal SERDES is used.

This signal is not present in PMA blocks implemented in Arria

10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.

Reference clock for the dynamic reconfiguration controller. If you use a dynamic reconfiguration controller in your design to dynamically control the transceiver, both the reconfiguration controller and the MegaCore function require this clock. This clock must operate between 37.5–50 MHz. Tie this clock low if you are not using an external reconfiguration controller.

This signal is not present in PMA blocks implemented in Arria

10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.

Driven from an external dynamic reconfiguration controller.

Supports the selection of multiple transceiver channels for dynamic reconfiguration.

For PMA blocks implemented in Stratix V devices with GX transceivers, the bus width is [139:0]. For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfiguration chapter of the respective device handbook.

Connects to an external dynamic reconfiguration controller.

The bus identifies the transceiver channel whose settings are being transmitted to the reconfiguration controller. Leave this bus disconnected if you are not using an external reconfigura‐ tion controller.

For more information about the bus width for PMA blocks implemented in each device, refer to the Dynamic Reconfigura‐ tion chapter of the respective device handbook.

Driven from an external dynamic reconfiguration controller.

This signal will indicate the busy status of the dynamic reconfi‐ guration controller during offset cancellation. Tie this signal to

1'b0 if you are not using an external reconfiguration controller.

This signal is not present in PMA blocks implemented in Arria

10, Stratix V, Arria V, and Cyclone V devices with GX transceivers.

For more information on the signals, refer to the respective sections shown in

Table 7-24

.

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10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and...

7-27

10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded

PMA

Figure 7-6: 10/100/1000 Multiport Ethernet MAC Function without Internal FIFO Buffers, with IEEE

1588v2, 1000BASE-X/SGMII PCS and Embedded PMA Signals

Transceiver

Native PHY

Signal n

5 n

8

8

5

32

32

Multi-Port MAC and 1000BASE-X/SGMII PCS with Embedded PMA

mac_tx_clk_n mac_rx_clk_n reset ref_clk_n rx_p_n tx_p_n data_tx_data_n[7:0] data_tx_sop_n data_tx_eop_n data_tx_error_n data_tx_valid_n data_tx_ready_n tx_crc_fwd_n tx_ff_uflow_n led_an_n led_crs_n led_col_n led_char_err_n led_link_n led_panel_link_n led_disp_err_n data_rx_data_n[7:0] data_rx_sop_n data_rx_eop_n data_rx_error_n[4:0] data_rx_ready_n data_rx_valid_n xon_gen_n xoff_gen_n magic_sleep_n_n magic_wakeup_n pkt_class_valid_n pkt_class_data_n[4:0] mdio_in mdc mdio_oen mdio_out rx_afull_channel(CHANNEL_WIDTH-1:0) rx_afull_data[1:0] rx_afull_valid rx_afull_clk clk reg_addr[(log2 MAX_CHANNELS+7):0] reg_wr reg_rd reg_data_in[31:0] reg_data_out[31:0] reg_busy cdr_ref_clk_n gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in_n reconfig_clk_n reconfig_togxb_n reconfig_fromgxb_n rx_recovclkout reconfig_busy tx_egress_timestamp_96b_n tx_egress_timestamp_64b_n rx_ingress_timestamp_96b_n rx_ingress_timestamp_64b_n tx_egress_timestamp_request_n tx_etstamp_ins_ctrl_n tx_time_of_day_96b_n tx_time_of_day_64b_n rx_time_of_day_96b_n rx_time_of_day_64b_n pcs_phase_measure_clk pcs_eccstatus[1:0]

IEEE 1588v2

Signals

ECC Status

Signal

Note to

Figure 7–6

:

1. The SERDES control signals are present in variations targeting devices with GX transceivers. For

Stratix II GX and Arria GX devices, the reconfiguration signals—reconfig_clk, reconfig_togxb, and reconfig_fromgxb—are included only when the Enable transceiver dynamic reconfiguration option is turned on. The reconfiguration signals— gxb_cal_blk_clk

, pcs_pwrdwn_out

, gxb_pwrdn_in

,

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IEEE 1588v2 RX Timestamp Signals

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reconfig_clk

, and reconfig_busy

—are not present in variations targeting Arria 10, Stratix V, Arria

V, and Cyclone V devices with GX transceivers.

Table 7-28: References

Interface Signal

Clock and reset signals

MAC control interface

MAC transmit interface

MAC receive interface

MAC packet classification signals

MAC FIFO status signals

Pause and magic packet signals

PHY management signals

1.25 Gbps Serial Signals

Status LED signals

SERDES control signals

Transceiver Native PHY signal

IEEE 1588v2 RX Timestamp Signals

IEEE 1588v2 TX Timestamp Signals

IEEE 1588v2 TX Timestamp Request

Signals

IEEE 1588v2 TX Insert Control

Timestamp Signals

IEEE 1588v2 ToD Clock Interface

Signals

Section

Clock and Reset Signal

on page 7-2

MAC Control Interface Signals

on page 7-3

MAC Transmit Interface Signals

on page 7-7

MAC Receive Interface Signals

on page 7-4

Multiport MAC Packet Classification Signals

on page 7-15

Multiport MAC FIFO Status Signals

on page 7-16

Pause and Magic Packet Signals

on page 7-9

PHY Management Signals

on page 7-11

1.25 Gbps Serial Interface

on page 7-25

Status LED Control Signals

on page 7-19

SERDES Control Signals

on page 7-20

Transceiver Native PHY Signal

on page 7-25

IEEE 1588v2 RX Timestamp Signals

on page 7-28

IEEE 1588v2 TX Timestamp Signals

on page 7-29

IEEE 1588v2 TX Timestamp Request Signals

on page 7-31

IEEE 1588v2 TX Insert Control Timestamp Signals

7-31 page 7-34

on page

IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals

on

IEEE 1588v2 RX Timestamp Signals

Table 7-29: IEEE 1588v2 RX Timestamp Interface Signals

I/O Signal

rx_ingress_timestamp_96b_ data_n

O

Width

96

Description

Carries the ingress timestamp on the receive datapath. Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.

The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress_timestamp_96b_valid

.

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Signal

rx_ingress_timestamp_96b_ valid

O

I/O

rx_ingress_timestamp_64b_data

O rx_ingress_timestamp_64b_ valid

O

IEEE 1588v2 TX Timestamp Signals

1

Width

64

1

Description

When asserted, this signal indicates that rx_ingress_timestamp_96b_ data

contains valid timestamp.

For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet ( avalon_ st_rx_startofpacket

is asserted).

Carries the ingress timestamp on the receive datapath. Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.

The MAC presents the timestamp for all receive frames and asserts this signal in the same clock cycle it asserts rx_ ingress_timestamp_64b_valid

.

When asserted, this signal indicates that rx_ingress_timestamp_64b_ data

contains valid timestamp.

For all receive frame, the MAC asserts this signal in the same clock cycle it receives the start of packet ( avalon_ st_rx_startofpacket

is asserted).

IEEE 1588v2 TX Timestamp Signals

Table 7-30: IEEE 1588v2 TX Timestamp Interface Signals

Signal

tx_egress_timestamp_96b_data_ n

O

I/O Width

96

Description

A transmit interface signal. This signal requests timestamp of frames on the

TX path. The timestamp is used to calculate the residence time.

Consists of 48-bit seconds field, 32-bit nanoseconds field, and 16-bit fractional nanoseconds field.

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IEEE 1588v2 TX Timestamp Signals

Signal

tx_egress_timestamp_96b_valid

O

I/O

tx_egress_timestamp_96b_ fingerprint tx_egress_timestamp_64b_data tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_ fingerprint

O

O

O

O

1

Width

n

64

1

n

Description

A transmit interface signal. Assert this signal to indicate that a timestamp is obtained and a timestamp request is valid for the particular frame.

Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket

is asserted).

Configurable width fingerprint that returns with correlated timestamps.

The signal width is determined by the

TSTAMP_FP_WIDTH parameter

(default parameter value is 4).

A transmit interface signal. This signal requests timestamp of frames on the

TX path. The timestamp is used to calculate the residence time.

Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field.

A transmit interface signal. Assert this signal to indicate that a timestamp is obtained and a timestamp request is valid for the particular frame.

Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket

or avalon_st_ tx_startofpacket_n

is asserted).

Configurable width fingerprint that returns with correlated timestamps.

The signal width is determined by the

TSTAMP_FP_WIDTH parameter

(default parameter value is 4).

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IEEE 1588v2 TX Timestamp Request Signals

Table 7-31: IEEE 1588v2 TX Timestamp Request Signals

I/O Signal

tx_egress_timestamp_request_ valid_n tx_egress_timestamp_request_ fingerprint

I

I

IEEE 1588v2 TX Timestamp Request Signals

1

Width

n

Description

Assert this signal when a user-defined tx_egress_timestamp

is required for a transmit frame.

Assert this signal in the same clock cycle as the start of packet ( avalon_ st_tx_startofpacket

or avalon_st_ tx_startofpacket_n

is asserted).

Use this bus to specify fingerprint for the user-defined tx_egress_ timestamp

. The fingerprint is used to identify the user-defined timestamp.

The signal width is determined by the

TSTAMP_FP_WIDTH parameter

(default parameter value is 4).

The value of this signal is mapped to user_fingerprint

.

This signal is only valid when you assert tx_egress_timestamp_ request_valid

.

IEEE 1588v2 TX Insert Control Timestamp Signals

Table 7-32: IEEE 1588v2 TX Insert Control Timestamp Interface Signals

Signal

tx_etstamp_ins_ctrl_timestamp_ insert_n

I

I/O

1

Width Description

Assert this signal to insert egress timestamp into the associated frame.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

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IEEE 1588v2 TX Insert Control Timestamp Signals

Signal

tx_etstamp_ins_ctrl_timestamp_ format

I

I/O

tx_etstamp_ins_ctrl_residence_ time_update tx_etstamp_ins_ctrl_ingress_ timestamp_96b[] tx_etstamp_ins_ ctrl_ingress_ timestamp_64b[]

I

I

I

1

Width Description

Timestamp format of the frame, which the timestamp inserts.

0: 1588v2 format (48-bits second field +

32-bits nanosecond field + 16-bits correction field for fractional nanosecond)

Required offset location of timestamp and correction field.

1: 1588v1 format (32-bits second field +

32-bits nanosecond field)

Required offset location of timestamp.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

1

96

64

Assert this signal to add residence time

(egress timestamp –ingress timestamp) into correction field of PTP frame.

Required offset location of correction field.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

96-bit format of ingress timestamp.

(48 bits second + 32 bits nanosecond +

16 bits fractional nanosecond).

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

64-bit format of ingress timestamp.

(48-bits nanosecond + 16-bits fractional nanosecond).

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

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Signal

tx_etstamp_ins_ctrl_residence_ time_calc_format

I

I/O

tx_etstamp_ins_ctrl_checksum_ zero tx_etstamp_ins_ctrl_checksum_ correct tx_etstamp_ins_ctrl_offset_ timestamp tx_etstamp_ins_ctrl_offset_ correction_field[]

I

I

I

I

IEEE 1588v2 TX Insert Control Timestamp Signals

1

Width Description

Format of timestamp to be used for residence time calculation.

0: 96-bits (96-bits egress timestamp -

96-bits ingress timestamp).

1: 64-bits (64-bits egress timestamp -

64-bits ingress timestamp).

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

1

1

1

16

Assert this signal to set the checksum field of UDP/IPv4 to zero.

Required offset location of checksum field.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

Assert this signal to correct UDP/IPv6 packet checksum, by updating the checksum correction, which is specified by checksum correction offset.

Required offset location of checksum correction.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

The location of the timestamp field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

The location of the correction field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

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IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals

Signal

tx_etstamp_ins_ctrl_offset_ checksum_field[]

I

I/O

tx_etstamp_ins_ctrl_offset_ checksum_correction[]

I

Width

16

16

Description

The location of the checksum field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

The location of the checksum correction field, relative to the first byte of the packet.

Assert this signal in the same clock cycle as the start of packet ( avalon_st_ tx_startofpacket

is asserted).

IEEE 1588v2 Time-of-Day (ToD) Clock Interface Signals

Table 7-33: IEEE 1588v2 ToD Clock Interface Signals

Signal

tx_time_of_day_96b_data_n rx_time_of_day_96b_data tx_time_of_day_64b_data rx_time_of_day_64b_data

I

I

I

I

I/O Width

96

96

64

64

Description

Use this bus to carry the time-of-day from external ToD module to 96-bit

MAC TX clock.

Consists of 48 bits seconds field, 32 bits nanoseconds field, and 16 bits fractional nanoseconds field

Use this bus to carry the time-of-day from external ToD module to 96-bit

MAC RX clock.

Consists of 48 bits seconds field, 32 bits nanoseconds field, and 16 bits fractional nanoseconds field

Use this bus to carry the time-of-day from external ToD module to 64-bit

MAC TX clock.

Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field

Use this bus to carry the time-of-day from external ToD module to 64-bit

MAC RX clock.

Consists of 48-bit nanoseconds field and 16-bit fractional nanoseconds field

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IEEE 1588v2 PCS Phase Measurement Clock Signal

IEEE 1588v2 PCS Phase Measurement Clock Signal

Table 7-34: IEEE 1588v2 PCS Phase Measurement Clock Signal

Signal

pcs_phase_measure_clk

I

I/O

1

Width Description

Sampling clock to measure the latency through the PCS FIFO buffer. The recommended frequency is 80 MHz.

IEEE 1588v2 PHY Path Delay Interface Signals

Table 7-35: IEEE 1588v2 PHY Path Delay Interface Signals

Signal

tx_path_delay_data rx_path_delay_data

I

I

I/O Width

22

22

Description

Use this bus to carry the path delay on the transmit datapath. The delay is measured between the physical network and MII/GMII to adjust the egress timestamp.

Bits 0 to 9—Fractional number of clock cycles

Bits 10 to 21—Number of clock cycles

Use this bus to carry the path delay on the receive datapath. The delay is measured between the physical network and MII/GMII to adjust the ingress timestamp.

Bits 0 to 9—Fractional number of clock cycles

Bits 10 to 21—Number of clock cycles

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1000BASE-X/SGMII PCS Signals

1000BASE-X/SGMII PCS Signals

Figure 7-7: 1000BASE-X/SGMII PCS Function Signals

MII/GMII

Signals

SGMII

Signals

4

4

8

8 gmii_tx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_d[7:0] gmii_rx_dv gmii_rx_err

1000 BASE-X/SGMII PCS Function

reset_rx_clk reset_tx_clk reset_reg_clk tbi_rx_clk tbi_rx_d[9:0] tbi_tx_clk tbi_tx_d[9:0] mii_tx_d[3:0] mii_tx_en mii_tx_err mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs led_an led_crs led_col led_char_err led_link led_panel_link led_disp_err sd_loopback powerdown rx_clkena tx_clkena

10

10 rx_clk tx_clk reg_clk reg_addr[4:0] reg_wr reg_rd reg_data_in[15:0] reg_data_out[15:0] reg_busy

5

16

16 set_10 set_100 set_1000 hd_ena tx_serial_clk rx_cdr_refclk tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset tx_cal_busy rx_cal_busy rx_set_locktodata rx_set_locktoref rx_is_locktodata rx_is_locktoref

Note to

Figure 7–7

:

1. The clock enabler signals are present only in SGMII mode.

Status

Signals

PCS

Control

Arria 10

Transceiver

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PCS Control Interface Signals

Table 7-36: Register Interface Signals

Name

reg_clk

Avalon-MM

Signal Type

clk

I

I/O

reset_reg_clk reg_wr reg_rd reg_addr[4:0] reg_data_in[15:0] reg_busy reset write read address writedata reg_data_out[15:0] readdata

I

I

I

I

I

O waitrequest

O

PCS Control Interface Signals

Description

Register access reference clock. Set the signal to a value less than or equal to 125-MHz.

Active-high reset signal for reg_clk

clock domain.

Register write enable.

Register read enable.

16-bit word-aligned register address.

Register write data. Bit 0 is the least significant bit.

Register read data. Bit 0 is the least significant bit.

Register interface busy. Asserted during register read or register write. A value of 0 indicates that the read or write is complete.

PCS Reset Signals

Table 7-37: Reset Signals

Name

reset_rx_clk reset_tx_clk

I

I

I/O Description

Active-high reset signal for PCS rx_clk

clock domain. Assert this signal to reset the logic synchronized by rx_clk

.

Active-high reset signal for PCS tx_clk

clock domain. Assert this signal to reset the logic synchronized by tx_clk

.

MII/GMII Clocks and Clock Enablers

Data transfers on the MII/GMII interface are synchronous to the receive and transmit clocks.

Table 7-38: MAC Clock Signals

rx_clk

Name

tx_clk rx_clkena

O

I/O

O

O

Description

Receive clock. This clock is derived from the TBI clock tbi_rx_ clk and set to 125 MHz.

Transmit clock. This clock is derived from the TBI clock tbi_tx_ clk

and set to 125 MHz.

Receive clock enabler. In SGMII mode, this signal enables rx_clk

.

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GMII

Name

tx_clkena

O

I/O Description

Transmit clock enabler. In SGMII mode, this signal enables tx_ clk

.

Figure 7-8: Clock Enabler Signal Behavior

125 MHz Clock

25 MHz Clock Enable

Input Data

Output Data

0xAA

0xAA

0xBB

0xBB

0xCC

0xCC

0xDD

0xDD

GMII

Table 7-39: GMII Signals

Name

GMII Transmit Interface

gmii_tx_d[7:0]

I gmii_tx_en

I

I/O

gmii_tx_err

I

Description

GMII transmit data bus.

Assert this signal to indicate that the data on gmii_tx_d[7:0] is valid.

Assert this signal to indicate to the PHY device that the current frame sent is invalid.

GMII Receive Interface

gmii_rx_d[7:0] gmii_rx_dv

O

O gmii_rx_err

O

GMII receive data bus.

Asserted to indicate that the data on gmii_rx_d[7:0]

is valid.

Stays asserted during frame reception, from the first preamble byte until the last byte in the CRC field is received.

Asserted by the PHY to indicate that the current frame contains errors.

MII

Table 7-40: MII Signals

Name

MII Transmit Interface

mii_tx_d[3:0] mii_tx_en

I

I

I/O Description

MII transmit data bus.

Assert this signal to indicate that the data on mii_tx_d[3:0] is valid.

0xEE

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SGMII Status Signals

Name

mii_tx_err

I

I/O Description

Assert this signal to indicate to the PHY device that the frame sent is invalid.

MII Receive Interface

mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs

O

O

MII receive data bus.

Asserted to indicate that the data on mii_rx_d[3:0] is valid. The signal stays asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received.

O Asserted by the PHY to indicate that the current frame contains errors.

Out Collision detection. Asserted by the PCS function to indicate that a collision was detected during frame transmission.

Out Carrier sense detection. Asserted by the PCS function to indicate that a transmit or receive activity is detected on the Ethernet line.

SGMII Status Signals

The SGMII status signals provide status information to the PCS block. When the PCS is instantiated standalone, these signals are inputs to the MAC and serve as interface control signals for that block.

Table 7-41: SGMII Status Signals

Name

set_1000 set_100

O

I/O

O

Description

Gigabit mode enabled. In 1000BASE-X, this signal is always set to

1. In SGMII, this signal is set to 1 if one of the following conditions is met: the

USE_SGMII_AN

bit is set to 1 and a gigabit link is established with the link partner, as decoded from the partner_ability register the

USE_SGMII_AN

bit is set to 0 and the

SGMII_SPEED

bit is set to

10

100 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the

USE_SGMII_AN

bit is set to 1 and a 100Mbps link is established with the link partner, as decoded from the partner_ ability register the

USE_SGMII_AN

bit is set to 0 and the

SGMII_SPEED

bit is set to

01

7-39

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SGMII Status Signals

set_10

Name

O

I/O

hd_ena

O

Description

10 -Mbps mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the

USE_SGMII_AN

bit is set to 1 and a 10Mbps link is established with the link partner, as decoded from the partner_ability register the

USE_SGMII_AN

bit is set to 0 and the

SGMII_SPEED

bit is set to

00

Half-duplex mode enabled. In 1000BASE-X, this signal is always set to 0. In SGMII, this signal is set to 1 if one of the following conditions is met: the

USE_SGMII_AN

bit is set to 1 and a half-duplex link is established with the link partner, as decoded from the partner_ ability register the

USE_SGMII_AN

bit is set to 0 and the

SGMII_DUPLEX

bit is set to 1

Table 7-42: References

Interface Signal Section

Ten-bit interface

Status LED signals

TBI Interface Signals

on page 7-18

Status LED Control Signals

on page 7-19

SERDES control signals

SERDES Control Signals

on page 7-20

Arria 10 Transceiver

Native PHY signals

Arria 10 Transceiver Native PHY Signals

on

page 7-20

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1000BASE-X/SGMII PCS and PMA Signals

1000BASE-X/SGMII PCS and PMA Signals

Figure 7-9: 1000BASE-X/SGMII PCS Function and PMA Signals

GMII

Signals

MII

Signals

Clock

Enabler

Signals

MII/GMII

Clock

Signals

SGMII

Status

Signals

8

8

4

4

1000BASE-X/SGMII PCS Function With Embedded PMA

gmii_tx_d[7:0] gmii_tx_en gmii_tx_err gmii_rx_d[7:0] gmii_rx_dv gmii_rx_err reset _rx_clk reset _tx_clk reset ref_clk rx_p tx_p mii_tx_d[3:0] mii_tx_en mii_tx_err mii_rx_d[3:0] mii_rx_dv mii_rx_err mii_col mii_crs led_crs led_col led_char _err led_link led_panel_link led_disp _err rx_clkena tx_clkena rx_clk tx_clk gxb_cal_blk_clk pcs_pwrdn_out gxb_pwrdn_in reconfig_clk reconfig_togxb reconfig_fromgxb rx_recovclkout reconfig_busy set _10 set _100 set _1000 hd_ena clk address [4:0] write read writedata [15:0] readdata [15:0] waitrequest

5

16

16

Reset

Signals

1.25 Gbps

Serial Signals

Status

LED

Signals

SERDES

Control

Signals

PCS

Control

Interface

Signals

7-41

Notes to

Figure 7–9

:

1. The clock enabler signals are present only in SGMII mode.

2. The SERDES control signals are present in variations targeting devices with GX transceivers. For

Stratix II GX and Arria GX devices, the reconfiguration signals— reconfig_clk

,

reconfig_togxb

, and reconfig_fromgxb

—are included only when the option, Enable transceiver dynamic reconfigu‐

ration, is turned on. The reconfiguration signals— gxb_cal_blk_clk

,

pcs_pwrdwn_out

, gxb_pwrdn_in

,

reconfig_clk

, and reconfig_busy

—are not present in variations targeting Stratix V devices with GX transceivers.

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Timing

Table 7-43: References

Interface Signal

Reset signals

MII/GMII clocks and clock enablers

PCS control interface

GMII signals

MII signals

SGMII status signals

1.25 Gbps Serial Signals

Status LED signals

SERDES control signals

Transceiver Native PHY signal

Section

PCS Reset Signals

on page 7-37

MII/GMII Clocks and Clock Enablers

on page 7-37

PCS Control Interface Signals

on page 7-37

GMII

on page 7-38

MII

on page 7-38

SGMII Status Signals

on page 7-39

1.25 Gbps Serial Interface

on page 7-25

Status LED Control Signals

on page 7-19

SERDES Control Signals

on page 7-20

Transceiver Native PHY Signal

on page 7-25

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Timing

This section shows the timing on the Triple-Speed Ethernet transmit and receive interfaces as well as the timestamp signals for the IEEE 1588v2 feature.

Related Information

Avalon Interface Specifications

More information on Avalon-MM control interface timing

Avalon-ST Receive Interface

Figure 7-10: Receive Operation—MAC With Internal FIFO Buffers

ff_rx_clk ff_rx_data[31:0] ff_rx_sop ff_rx_eop ff_rx_rdy ff_rx_dval ff_rx_dsav rx_frm_type[3:0] rx_err_stat[17:0] rx_err[5:0] ff_rx_mod[1:0]

00

00000000 00000001 00000002 00000003 00000004 00000005 00000000

00

0

1

00064

0

00000

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Figure 7-11: Receive Operation—MAC Without Internal FIFO Buffers

Avalon-ST Receive Interface

mac_rx_clk_0 data_rx_data_0[7:0] data_rx_sop_0 data_rx_eop_0 data_rx_ready_0 data_rx_error_0[4:0] data_rx_valid_0 pkt_class_data_0[4:0] pkt_class_valid_0

00 10

03 04 05 06 07 08 09 10 10 10 10 00

00

0

Figure 7-12: Invalid Length Error During Receive Operation—MAC With Internal FIFO Buffer

ff_rx_clk ff_rx_data[31:0] ff_rx_sop ff_rx_eop ff_rx_rdy ff_rx_dval ff_rx_dsav rx_frm_type[3:0] rx_err_stat[17:0] rx_err[5:0] ff_rx_mod[1:0]

00

00000001 00000002 00000003 00000004 00000005 00000006 00000007

00

1

005DD

03

3

0

00000

00

0

7-43

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Avalon-ST Transmit Interface

Figure 7-13: Invalid Length Error During Receive Operation—MAC Without Internal FIFO Buffers

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mac_rx_clk_0 data_rx_data_0[7:0] data_rx_sop_0 data_rx_eop_0 data_rx_ready_0 data_rx_error_0[4:0] data_rx_valid_0 pkt_class_data_0[4:0] pkt_class_valid_0

00 10

03 04 05 06 06 07 08 09 09 09 09 09 00

0

01

Avalon-ST Transmit Interface

Figure 7-14: Transmit Operation—MAC With Internal FIFO Buffers

ff_tx_clk ff_tx_data[31:0] ff_tx_sop ff_tx_eop ff_tx_rdy ff_tx_wren ff_tx_crc_fwd ff_tx_err ff_tx_mod[1:0] ff_tx_septy tx_ff_uflow

00000001 00000002 00000003 00000004 00000005 00000006

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Figure 7-15: Transmit Operation—MAC Without Internal FIFO Buffers

mac_tx_clk_0 data_tx_data_0[7:0] 00 01 data_tx_sop_0 data_tx_eop_0 data_tx_ready_0 data_tx_err_0 data_tx_valid_0

01 01 02 03 04

GMII Transmit

05 06 07 08 09

7-45

GMII Transmit

On transmit, all data transfers are synchronous to the rising edge of tx_clk

. The GMII data enable signal gm_tx_en

is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on gm_tx_d[7:0]

bus. Between frames, gm_tx_en

remains deasserted.

If a frame is received on the Avalon-ST interface with an error (asserted with ff_tx_eop

), the frame is subsequently transmitted with the GMII gm_tx_err

error signal at any time during the frame transfer.

GMII Receive

On receive, all signals are sampled on the rising edge of rx_clk

. The GMII data enable signal gm_rx_dv

is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on the gm_rx_d[7:0]

bus. Between frames, gm_rx_dv

remains deasserted.

If the PHY detects an error on the frame received from the line, the PHY asserts the GMII error signal, gm_rx_err

, for at least one clock cycle at any time during the frame transfer.

A frame received on the GMII interface with a PHY error indication is subsequently transferred on the

Avalon-ST interface with the error signal rx_err[0]

asserted.

RGMII Transmit

On transmit, all data transfers are synchronous to both edges of tx_clk

. The RGMII control signal tx_control

is asserted to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on the rgmii_out[3:0]

bus. Between frames, tx_control

remains deasserted.

Figure 7-16: RGMII Transmit in 10/100 Mbps

tx_clk tx_control rgmii_out[3:0] 00 5 D 0 5 1 6 1 9 1

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RGMII Receive

Figure 7-17: RGMII Transmit in Gigabit Mode

0 4 6 0 1 0 0 8 0 9 0

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tx_clk tx_control rgmii_out[3:0] 00 5 D 0 5 4 5 E 5 F 5 0 6 0

If a frame is received on the Avalon-ST interface with an error ( ff_tx_err

asserted with ff_tx_eop

), the frame is subsequently transmitted with the RGMII tx_control

error signal (at the falling edge of tx_clk

) at any time during the frame transfer.

Figure 7-18: RGMII Transmit with Error in 1000 Mbps

tx_clk tx_control rgmii_out[3:0] 00 5

RGMII Receive

On receive all signals are sampled on both edges of rx_clk

. The RGMII control signal rx_control

is asserted by the PHY to indicate the start of a new frame and remains asserted until the last upper nibble of the frame is present on rgmii_in[3:0]

bus. Between frames, rx_control

remains deasserted.

Figure 7-19: RGMII Receive in 10/100 Mbps

rx_clk rx_control rgmii_in[3:0] 00

Figure 7-20: RGMII Receive in 1000 Mbps

5

D 0

5

1 6 1 9 0 rx_clk rx_control rgmii_in[3:0] 00 5 D 0 5 4 5 E 5 F 5 0 6 0

A frame received on the RGMII interface with a PHY error indication is subsequently transferred on the

Avalon-ST interface with the error signal rx_err[0] asserted.

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Figure 7-21: RGMII Receive with Error in Gigabit Mode

rx_clk rx_control rgmii_in[3:0] 00 5 0 4 6 0 1 0 0 8 0 9

MII Transmit

0

7-47

The current implementation of the RGMII receive interface expects a positive-delay rx_clk

relative to the receive data (the clock comes after the data).

MII Transmit

On transmit, all data transfers are synchronous to the rising edge of tx_clk

. The MII data enable signal, m_tx_en,

is asserted to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m_tx_d[3:0]

bus. Between frames, m_tx_en

remains deasserted.

If a frame is received on the FIFO interface with an error ( ff_tx_err

asserted) the frame is subsequently transmitted with the MII error signal m_tx_err

for one clock cycle at any time during the frame transfer.

MII Receive

On receive, all signals are sampled on the rising edge of rx_clk

. The MII data enable signal m_rx_en

is asserted by the PHY to indicate the start of a new frame and remains asserted until the last byte of the frame is present on m_rx_d[3:0]

bus. Between frames, m_rx_en

remains deasserted.

If the PHY detects an error on the frame received from the line, the PHY asserts the MII error signal, m_rx_err

, for at least one clock cycle at any time during the frame transfer.

A frame received on the MII interface with a PHY error indication is subsequently transferred on the

FIFO interface with the error signal rx_err[0]

asserted.

IEEE 1588v2 Timestamp

The following timing diagrams show the timestamp of frames observed on TX path for the IEEE 1588v2 feature.

Figure below shows the TX timestamp signals for the IEEE 1588v2 feature in a 1-step operation.

In a 1-step operation, a TX egress timestamp is inserted into timestamp field of the PTP frame in the

MAC. You need to drive the 1-step related signal appropriately so that the timestamp can be inserted into the correct location of the packet. The input signals related to the 2-step operation are not important and can be driven low or ignored.

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IEEE 1588v2 Timestamp

Figure 7-22: Egress Timestamp Insert for IEEE 1588v2 PTP Packet Encapsulated in IEEE 802.3

Egress Timestamp Insert, IEEE 1588v2, PTP Packet

2-step Timestamp Request,Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data[N:0]

2-step Timestamp Return,Output tx_egress_timestamp_96b_valid tx_egress_timestamp_96b_fingerprint[N:0] tx_egress_timestamp_96b_data[95:0] tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_fingerprint[N:0] tx_egress_timestamp_64b_data[63:0]

1-step Timestamp Insert,Input tx_etstamp_ins_ctrl_timestamp_insert tx_etstamp_ins_ctrl_timestamp_format

1-step Residence Time Update,Input tx_etstamp_ins_ctrl_residence_time_update tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] tx_etstamp_ins_ctrl_residence_time_calc_format

1-step IPv4 and IPv6 Checksum,Input tx_etstamp_ins_ctrl_checksum_zero tx_etstamp_ins_ctrl_checksum_correct

1-step Location Offset,Input tx_etstamp_ins_ctrl_offset_timestamp[15:0] tx_etstamp_ins_ctrl_offset_correction_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Offset 1

Offset 2

Don’t-care

Don’t-care

UG-01008

2015.06.15

Figure 7-23

shows the TX timestamp signals for the first type of egress correction field update, where the residence time is calculated by subtracting 96 bit ingress timestamp from 96 bit egress timestamp. The result is updated in the correction field of the PTP frame encapsulated over UDP/IPv4.

The tx_etstamp_ins_ctrl_residence_time_calc_format

signal is driven low to indicate that this is a

96b residence time calculation. The tx_etstamp_ins_ctrl_checksum_zero

signal is driven high to clear the UDP/IPv4 checksum field to all 0.

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Figure 7-23: Type 1 Egress Correction Field Update

IEEE 1588v2 Timestamp

Type 1 Egress Correction Field Update, 96b, IPV4

2-step Timestamp Request,Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data[N:0]

2-step Timestamp Return,Output tx_egress_timestamp_96b_valid tx_egress_timestamp_96b_fingerprint[N:0] tx_egress_timestamp_96b_data[95:0] tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_fingerprint[N:0] tx_egress_timestamp_64b_data[63:0]

1-step Timestamp Insert,Input tx_etstamp_ins_ctrl_timestamp_insert tx_etstamp_ins_ctrl_timestamp_format

1-step Residence Time Update,Input tx_etstamp_ins_ctrl_residence_time_update tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] tx_etstamp_ins_ctrl_residence_time_calc_format

1-step IPv4 and IPv6 Checksum,Input tx_etstamp_ins_ctrl_checksum_zero tx_etstamp_ins_ctrl_checksum_correct

1-step Location Offset,Input tx_etstamp_ins_ctrl_offset_timestamp[15:0] tx_etstamp_ins_ctrl_offset_correction_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Ingress Timestamp

Don’t-care

Don’t-care

Offset 1

Offset 2

Don’t-care

7-49

Figure 7-24

shows the TX timestamp signals for the second type of egress correction field update, where the 64 bit ingress timestamp has been pre-subtracted from the correction field at the ingress port. At the egress port, the 64 bit egress timestamp is added into the correction field and the correct residence time is updated in the correction field. This is the example of PTP frame encapsulated over UPD/IPV6.

The tx_etstamp_ins_ctrl_residence_time_calc_format

signal is driven high to indicate that this is a

64b residence time calculation. The tx_etstamp_ins_ctrl_checksum_correct

signal is driven high to correct the packet UPD/IPV6 checksum by updating the checksum correction field.

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IEEE 1588v2 Timestamp

Figure 7-24: Type 2 Egress Correction Field Update

Type 2 Egress Correction Field Update, 64b, IPV6

2-step Timestamp Request,Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data[N:0]

2-step Timestamp Return,Output tx_egress_timestamp_96b_valid tx_egress_timestamp_96b_fingerprint[N:0] tx_egress_timestamp_96b_data[95:0] tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_fingerprint[N:0] tx_egress_timestamp_64b_data[63:0]

1-step Timestamp Insert,Input tx_etstamp_ins_ctrl_timestamp_insert tx_etstamp_ins_ctrl_timestamp_format

1-step Residence Time Update,Input tx_etstamp_ins_ctrl_residence_time_update tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] tx_etstamp_ins_ctrl_residence_time_calc_format

1-step IPv4 and IPv6 Checksum,Input tx_etstamp_ins_ctrl_checksum_zero tx_etstamp_ins_ctrl_checksum_correct

1-step Location Offset,Input tx_etstamp_ins_ctrl_offset_timestamp[15:0] tx_etstamp_ins_ctrl_offset_correction_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

64’b0

Don’t-care

Offset 1

Don’t-care

Offset 2

UG-01008

2015.06.15

Figure 7-25

shows the TX timestamp signals for the IEEE 1588v2 feature in a two step operation.

When the tx_egress_timestamp_request_valid

signal is driven high with a unique fingerprint, the

MAC returns an egress timestamp associated with that unique fingerprint. The signals related to the 1step operation can be driven low or ignored. There is no modification to the packet content.

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Figure 7-25: Egress 2-Step Operation

IEEE 1588v2 Timestamp

7-51

Egress Two-Step Operation, IEEE 1588v2, PTP Packet

2-step Timestamp Request,Input tx_egress_timestamp_request_valid tx_egress_timestamp_request_data[N:0]

2-step Timestamp Return,Output tx_egress_timestamp_96b_valid tx_egress_timestamp_96b_fingerprint[N:0] tx_egress_timestamp_96b_data[95:0] tx_egress_timestamp_64b_valid tx_egress_timestamp_64b_fingerprint[N:0] tx_egress_timestamp_64b_data[63:0]

1-step Timestamp Insert,Input tx_etstamp_ins_ctrl_timestamp_insert tx_etstamp_ins_ctrl_timestamp_format

1-step Residence Time Update,Input tx_etstamp_ins_ctrl_residence_time_update tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] tx_etstamp_ins_ctrl_residence_time_calc_format

1-step IPv4 and IPv6 Checksum,Input tx_etstamp_ins_ctrl_checksum_zero tx_etstamp_ins_ctrl_checksum_correct

1-step Location Offset,Input tx_etstamp_ins_ctrl_offset_timestamp[15:0] tx_etstamp_ins_ctrl_offset_correction_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_field[15:0] tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]

Fingerprint

Don’t-care

Don’t-care

Don’t-care

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Don’t-care

Don’t-care

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Fingerprint

96b Egress Timestamp

Fingerprint

64b Egress Timestamp

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

Don’t-care

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Optimizing Clock Resources in Multiport MAC with PCS and Embedded

PMA

The following factors determine the total number of global and regional clock resources required by your system:

• Configuration of the Triple-Speed Ethernet MegaCore function and the blocks it contains

• PCS operating mode (SGMII or 1000BASE-X)

• PMA technology implemented in the target device

• Number of clocks that can share a single source

• Number of PMAs required in the design

• ALTGX megafunction operating mode

You can use the same clock source to drive clocks that are visible at the top-level design, thus reducing the total number of clock sources required by the entire design.

Table 8-1: Clock Signals Visible at Top-Level Design

Clock and reset signals that are visible at the top-level design for each possible configuration.

Configurations

(1)

Clocks

MAC Only MAC and PCS MAC and PCS with PMA

rx_recovclkout ref_clk clk ff_tx_clk ff_rx_clk tx_clk rx_clk tbi_rx_clk tbi_tx_clk

gxb_cal_blk_clk

(2)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

No

No

No

Yes

8

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

8-2

MAC and PCS With GX Transceivers

Configurations

(1)

Clocks

MAC Only MAC and PCS

reconfig_clk

— —

Notes to

Table 8-1

:

1. Yes indicates that the clock is visible at the top-level design.

No indicates that the clock is not visible at the top-level design.

— indicates that the clock is not applicable for the given configuration.

2. Applies to GX transceiver.

Yes

MAC and PCS with PMA

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MAC and PCS With GX Transceivers

In configurations that contain the MAC, PCS, and GX transceivers, you have the following options in optimizing clock resources:

• Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.

• Utilize the same reference clock for all PMA quads

• Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system clocks, if these clocks run at the same frequency.

The Quartus II software automatically optimizes the TBI transmit clocks. Only one clock source drives the

TBI transmit clocks from each PMA quad.

The calibration clock ( gxb_cal_blk_clk

) calibrates the termination resistors in all transceiver channels in a device. As there is only one calibration circuit in each device, one clock source suffices.

Note: If you do not constrain the PLL inputs and outputs in your design, add derive_pll_clocks

in the timing constraint file to ensure that the TimeQuest timing analyzer automatically creates derived clocks for the PLL outputs.

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MAC and PCS With GX Transceivers

Figure 8-1: Clock Distribution in MAC and SGMII PCS with GXB Configuration—Optimal Case

8-3

Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the

10/100/1000 Ethernet MAC, SGMII PCS, and GX transceivers.

ref_clk clk1

4-port MAC

Port 1 clk2 clk3

Port 3 clk4

Port 2

Port 4 tx_clk_en1 rx_clk1 tx_clk1 rx_clk_en1 rx_clk1 tx_clk1 tbi_rx_clk1

PCS 1 tbi_tx_clk1 tx_clk_en2 rx_clk2 tx_clk2 rx_clk_en2 rx_clk2 tx_clk2 tbi_rx_clk2

PCS 2 tbi_tx_clk2 tx_clk_en3 rx_clk3 tx_clk3 rx_clk_en3 rx_clk3 tx_clk3

PCS 3 tbi_rx_clk3 tbi_tx_clk3 tx_clk_en1 rx_clk4 tx_clk4 rx_clk_en1 rx_clk4 tx_clk4

PCS 4 tbi_rx_clk4 tbi_tx_clk4 ref_clk

Quad

Transceivers

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode )

Note to

Figure 8-1

:

1. The PMA layer in devices with GX transceivers uses ALTGX megafunctions.

In addition to the aforementioned optimization options, the TBI transmit and receive clocks can be used to drive the MAC transmit and receive clocks, respectively.

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Figure 8-2: Clock Distribution in MAC and 1000BASE-X PCS with GXB Configuration—Optimal Case

Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the

10/100/1000 Ethernet MAC, 1000Base-X PCS, and GX transceivers.

ref_clk clk1

4-port MAC

Port 1 rx_clk1 tx_clk1

PCS 1 clk2 clk3 clk4

Port 2

Port 3

Port 4 rx_clk2 tx_clk2 rx_clk3 tx_clk3 rx_clk4 tx_clk4

PCS 2

PCS 3

PCS 4 tbi_rx_clk1 tbi_rx_clk2

Quad

Transceivers

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode ) tbi_tx_clk tbi_rx_clk3

ALTGX

(GIGE Mode )

ALTGX

(GIGE Mode ) tbi_rx_clk4

Note to

Figure 8–2

:

1. The PMA layer in devices with GX transceivers uses ALTGX megafunctions.

MAC and PCS With LVDS Soft-CDR I/O

In configurations that contain the MAC, PCS, and LVDS Soft-CDR I/O, you have the following options in optimizing clock resources:

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MAC and PCS With LVDS Soft-CDR I/O

• Utilize the same reset signal for all MAC instances if you do not require a separate reset for each instance.

• Utilize the same clock source to drive the reference clock, FIFO transmit and receive clocks, and system clocks, if these clocks run at the same frequency.

Figure 8-3: Clock Distribution in MAC and SGMII PCS with LVDS Configuration—Optimal Case

8-5

Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the

MAC, SGMII PCS and LVDS Soft-CDR I/O.

ref_clk clk1

4-port

MAC

Port 1 clk2 clk3 clk4

Port 2

Port 3

Port 4 tx_clk_en1 rx_clk1 tx_clk1 rx_clk_en1 rx_clk1 tx_clk1

PCS 1 tbi_rx_clk1 tbi_tx_clk

ALTLVDS _RX _

COMPONENT pll pll~clk1

PLL

ALTLVDS _TX _

COMPONENT tx_clk_en2 rx_clk2 tx_clk2 rx_clk_en2 rx_clk2 tx_clk2

PCS 2 tbi_rx_clk2

ALTLVDS _RX _

COMPONENT

ALTLVDS _TX _

COMPONENT tx_clk_en3 rx_clk3 tx_clk3 rx_clk_en3 rx_clk3 tx_clk3

PCS 3 tbi_rx_clk3

ALTLVDS _RX _

COMPONENT

ALTLVDS _TX _

COMPONENT tx_clk_en4 rx_clk4 tx_clk4 rx_clk_en4 rx_clk4 tx_clk4

PCS 4 tbi_rx_clk4

ALTLVDS _RX _

COMPONENT

ALTLVDS _TX _

COMPONENT

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Figure 8-4: Clock Distribution in MAC and 1000BASE-X PCS with LVDS Configuration—Optimal Case

Figure shows the optimal clock distribution scheme you can achieve in configurations that contain the

MAC, 1000BASE-X PCS, and LVDS Soft-CDR I/O.

ref_clk clk1

4-port MAC

Port 1 rx_clk1 tx_clk1

PCS 1 tbi_rx_clk1 tbi_tx_clk

ALTLVDS_RX_

COMPONENT

ALTLVDS_TX_

COMPONENT pll pll~clk1

PLL clk2

Port 2 rx_clk2 tx_clk2

PCS 2 tbi_rx_clk2 ALTLVDS_RX_

COMPONENT

ALTLVDS_TX_

COMPONENT clk3 clk4

Port 3 rx_clk3 tx_clk3

Port 4 rx_clk4 tx_clk4

PCS 3

PCS 4 tbi_rx_clk3 ALTLVDS_RX_

COMPONENT

ALTLVDS_TX_

COMPONENT tbi_rx_clk4

ALTLVDS_RX_

COMPONENT

ALTLVDS_TX_

COMPONENT

Sharing PLLs in Devices with LVDS Soft-CDR I/O

For designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with LVDS soft-CDR I/O, you can optimize resource utilization by sharing the PLLs.

The Quartus II software merges the PLLs for these instances if you implement the following items in your design:

• Connect the reference clock of each instance to the same source.

• Place the LVDS I/O pins on the same side of the FPGA.

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Sharing PLLs in Devices with GIGE PHY

8-7

Sharing PLLs in Devices with GIGE PHY

For Cyclone V designs that contain multiple instances of MAC and PCS with PMA or PCS with PMA variation targeting devices with GIGE PHY, you can share the PLLs by placing the associated signals

( tx_p

, rx_p

, and ref_clk

) to the same I/O block of transceiver bank through pin assignment.

Additionally, the rx_recovclkout

clock must be buffered by two levels of inverter in the top level module so that it can be fitted to the general I/O pins.

Sharing Transceiver Quads

For designs that contain multiple PMA blocks targeting Altera device families with GX transceivers, you can combine the transceiver channels in the same quad. To share the same transceiver quad, the transceiver channels must have the same dynamic reconfiguration setting. In other words, you must turn on dynamic reconfiguration capabilities in all channels in a quad even though you only intend to use these capabilities in some of the channels.

The dynamic reconfiguration is always turned on in devices other than Arria GX and Stratix II GX. When the dynamic reconfiguration is turned on in designs targeting devices other than Arria 10, Stratix V, Arria

V, and Cyclone V, Altera recommends that you connect the dynamic reconfiguration signals to the

ALTGX_RECONFIG megafunction.

In Stratix V, Arria V, and Cyclone V devices, Altera recommends that you connect the dynamic reconfi‐ guration signals to the Transceiver Reconfiguration Controller megafunction. For transceiver quad sharing between Triple-Speed Ethernet IP core and other IP cores that target these devices, reset signal for all the cores must be from the same source.

Refer to the respective device handbook for more information on dynamic reconfiguration signals in

Altera devices.

Migrating From Old to New User Interface For Existing Designs

In Quartus II software ACDS 13.0 release, the old Triple-Speed Ethernet MegaCore function user interface is deprecated. Existing Triple-Speed Ethernet designs generated prior to the ACDS 13.0 release can still load properly in ACDS 13.0. However, starting from ACDS 13.1 release, the old Triple-Speed

Ethernet interface and the design generated using the old interface will not be supported.

You need to manually migrate your design to the new user interface. Reopening and saving the existing design created with the old user interface will not automatically convert the design to the new user interface.

To migrate your design to the new user interface, launch the Quartus II software ACDS 13.0 or higher, create a new project, and specify the parameters as described in

Design Walkthrough

on page 2-1.

Exposed Ports in the New User Interface

In the new user interface in Qsys, for a design that has a MAC function, you have to manually connect the exposed ports or terminate them.

In MAC variation with internal FIFO buffers, the ready latency is two in both standalone and Qsys flow.

The Qsys system inserts a timing adapter to change the ready latency to zero.

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Exposed Ports in the New User Interface

Table 8-2: Exposed Ports and Recommended Termination Value for MAC Variation With Internal FIFO

Buffers

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Port Name

xon_gen xoff_gen magic_wakeup magic_sleep_n ff_tx_crc_fwd ff_tx_septy tx_ff_uflow ff_tx_a_full ff_tx_a_empty rx_err_stat rx_frm_type ff_rx_dsav ff_rx_a_full ff_rx_a_empty

I

I

O

I

I

O

O

O

O

O

O

O

O

O

I/O

1

1

1

1

1

1

1

1

1

1

1

1

18

4

Width Recommended Termination

Value

1'b0

1'b0

Left open

1'b1

1'b0

Left open

Left open

Left open

Left open

Left open

Left open

Left open

Left open

Left open

Table 8-3

lists the following ports that are exposed in the Qsys system for a design that has MAC variation

without internal FIFO buffers.

Table 8-3: Exposed Ports and Recommended Termination Value for MAC Variation Without Internal FIFO

Buffers

Port Name

xon_gen_<n> xoff_gen_<n> magic_wakeup_<n> magic_sleep_n_<n> ff_tx_crc_fwd_<n>

I

I

I

I

O

I/O

1

1

1

1

1

Width Recommended Termination

Value

1'b0

1'b0

Left open

1'b1

1'b0

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Altera provides timing constraint files (

.sdc

) to ensure that the Triple-Speed Ethernet MegaCore function meets the design timing requirements in Altera devices. The files constraints the false paths and multicycle paths in the Triple-Speed Ethernet Megacore function. The timing constraints files are specified in the <variation_name>

.qip

file and is automatically included in the Quartus II project files.

You may need to add timing constraints that are external to the MegaCore function. The following sections describe the procedure to create the timing constraint file.

9

Creating Clock Constraints

After you generate and integrate the Triple-Speed Ethernet MegaCore function into the system, you need to create a timing constraints file to specify the clock constraint requirement.

You can specify the clock requirement in the timing constraint file using the following command: create_clock

For example, for a new clock named " reg_clk

", with a 50 MHz clock targeted to the top level input port

" clk

", enter the following command line: create_clock -name "reg_clk" -period "50 MHz" [get_ports "clk"]

Figure below shows an example of how you can create a timing constraint file to constrain the Triple-

Speed Ethernet MegaCore function clocks.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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ISO

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Registered

9-2

Creating Clock Constraints

Figure 9-1: Triple-Speed Ethernet Timing Constraint Example

The reconfig_clk

signal is not shown in this example. Constrain the reconfig_clk

based on your design implementation.

TOP.v

pll_inclk

100-Mhz ext_clk

50-Mhz

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inclk0

Altera PLL c1 c0

110-Mhz user_instance.v

tse_variation.v

clk

10/100/1000-Mbps Ethernet MAC with 1000BASE-X/SGMII ff_tx_clk

PCS and PMA

(with internal FIFO) ff_rx_clk ref_clk xcvr_ref_clk

125-Mhz

The example above consists of the following Verilog modules:

TOP.v

—The top level design module which contains an Altera PLL and a user-defined instance. The top level input clocks consist of pll_inclk

, ext_clk

, and xcvr_ref_clk

.

user_instance.v

—The user-defined instance that instantiates the Triple-Speed Ethernet MegaCore function.

tse_variation.v

—A Triple-Speed Ethernet MegaCore function variation. This example uses a

10/100/1000-Mbps Ethernet MAC with an internal FIFO buffer, a 1000BASE-X/SGMII PCS, and an embedded PMA.

The frequency for the PLL clock input, inclk0

, is 100 MHz, and the frequency for the PLL clock output, c0

, is 110 MHz. The Triple-Speed Ethernet MAC Avalon-ST clocks, ff_tx_clk

and ff_rx_clk

, use c0

as the clock source. The input clock frequency for the transceiver reference clock, xcvr_ref_clk

, is

125 MHz.

Example of the Triple-Speed Ethernet MegaCore function timing constraint file:

# PLL clock input, 100 MHz create_clock -name pll_inclk -period 10.000 [get_ports {pll_inclk}]

# ext_clk, 50 MHz create_clock -name ext_clk -period 20.000 [get_ports {pll_ext_clk}]

# xcvr_ref_clk, 125 MHz create_clock -name xcvr_ref_clk -period 8.000 [get_ports

{xcvr_ref_clk}]

# Derive PLL generated output clocks.

derive_pll_clocks

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Recommended Clock Frequency

9-3

Recommended Clock Frequency

Table 9-1: Recommended Clock Input Frequency For Each MegaCore Function Variant

MegaCore Function Variant Clock

10/100/1000-Mbps Ethernet MAC (with Internal

FIFO buffers)

CLK

TX_CLK

RX_CLK

FF_TX_CLK

FF_RX_CLK

CLK

10/100/1000-Mbps Ethernet MAC (without Internal

FIFO buffers)

TX_CLK <N>

RX_CLK <N>

RX_AFULL_CLK

CLK

FF_TX_CLK

FF_RX_CLK

10/100/1000-Mbps Ethernet MAC with 1000BASE-

X/SGMII PCS (with Internal FIFO buffers)

TBI_TX_CLK

TBI_RX_CLK

REF_CLK

RECONFIG_CLK

(4)

GXB_CAL_BLK_CLK

CLK

RX_AFULL_CLK

TBI_TX_CLK <N>

10/100/1000-Mbps Ethernet MAC with 1000BASE-

X/SGMII PCS (without Internal FIFO buffers)

TBI_RX_CLK <N>

REF_CLK

RECONFIG_CLK <N>

(4)

GXB_CAL_BLK_CLK

Recommended Frequency

(MHz)

125

100

50–100

100

100

125

125

125

37.5–50

50–100

125

125

100

100

50–100

125

125

50–100

100

125

125

125

37.5–50

125

(4) This signal is only applicable to all device family prior to the 28-nm devices, which consists of the Stratix V,

Arria V, Arria V GZ, and Cyclone V devices.

Timing Constraints

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Recommended Clock Frequency

MegaCore Function Variant

1000BASE-X/SGMII PCS only

Clock

CLK

REF_CLK

TBI_TX_CLK

TBI_RX_CLK

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Recommended Frequency

(MHz)

50–100

125

125

125

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Testbench

10

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You can use the testbench provided with the Triple-Speed Ethernet MegaCore function to exercise your custom MegaCore function variation. The testbench includes the following features:

• Easy-to-use simulation environment for any standard HDL simulator.

• Simulation of all basic Ethernet packet transactions.

• Open source Verilog HDL and VHDL testbench files.

The provided testbench applies only to custom MegaCore function variations created using Qsys.

Triple-Speed Ethernet Testbench Architecture

Figure 10-1: Triple-Speed Ethernet Testbench Architecture

Device Under Test

Port 0

Port 1

Port 2

Port n

Testbench Control

Simulation Configuration Parameters

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

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Registered

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Testbench Components

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Testbench Components

The testbench comprises the following modules:

• Device under test (DUT)—Your custom MegaCore function variation

• Avalon-ST Ethernet frame generator—Simulates a user application connected to the MAC system-side interface. It generates frames on the Avalon-ST transmit interface.

• Avalon-ST Ethernet frame monitor—Simulates a user application receiving frames from the MAC system-side interface. It monitors the Avalon-ST receive interface and decodes all data received.

• MII/RGMII/GMII Ethernet frame generator—Simulates a MAC function that sends frames to the PCS function.

• MII/RGMII/GMII Ethernet frame monitor—Simulates a MAC function that receives frames from the

PCS function and decodes them.

• MDIO slaves—Simulates a PHY management interface. It responds to an MDIO master transactor.

• Clock and reset generator.

Table 10-1: Testbench Components

Configuration

MAC only

System-Side

Interface

Avalon-ST

MAC with PCS Avalon-ST

MAC with PCS and embedded

PMA

PCS only

Avalon-ST

GMII/MII

Ethernet-Side

Interface

Frame Generator

GMII/MII/RGMII Avalon-ST Frame

Generator

TBI

1.25 Gbps

Avalon-ST Frame

Generator

Avalon-ST Frame

Generator

TBI

Frame Monitor

Avalon-ST Frame

Monitor

Avalon-ST Frame

Monitor

Avalon-ST Frame

Monitor

PCS with embedded

PMA

GMII/MII 1.25 Gbps

GMII/MII Frame

Generator

GMII/MII Frame

Generator

GMII/MII Frame

Monitor

GMII/MII Frame

Monitor

Testbench Verification

The testbench is self-checking and determines the success of a simulation by verifying the frames received.

It also checks for any errors detected by the frame monitors. The testbench does not verify the IEEE statistics generated by the MAC layer. Simulation fails only if the testbench is not able to detect deliberately inserted errors. At the end of a simulation, the testbench displays messages in the simulator console indicating its results.

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Testbench Configuration

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The testbench verifies the following functionality:

• Transmit and receive datapaths are functionally correct.

• Ethernet frames generated by the frame generator are received by the frame monitor.

• Additional checks for configurations that contain the MAC function:

• Correct CRC-32 is inserted.

• Short frames are padded up to at least 64 bytes in length.

• Untagged received frames of size greater than the maximum frame length are truncated to the maximum frame length with additional bytes up to 12.

• CRC-32 is optionally discarded before the frames are received by the traffic monitor.

• Additional checks for configurations that contain the PCS function with optional embedded PMA:

• Transmit frames generated by the frame generator are correctly encapsulated.

• Received frames are de-encapsulated before they are forwarded to the frame monitor.

Testbench Configuration

The testbench is configured, by default, to operate in loopback mode. Frames sent through the transmit path are looped back into the receive path.

Separate data paths can be configured for single-channel MAC with internal FIFO buffers. In this configuration, the MII/GMII Ethernet frame generator is enabled and the testbench control block simulates independent yet complete receive and transmit datapaths.

You can also customize other aspects of the testbench using the testbench simulation parameters.

The device under test is configured with the following default settings:

• Link speed is set to Gigabit except for configurations that contain Small MAC. For Small MACs, the default speed is 100 Mbps.

• Five Ethernet frames of payload length 100, 101, 102, 103 and 104 bytes are transmitted to the systemside interface and looped back on the ethernet-side interface.

• Default settings for the MAC function:

• The command_config

register is set to 0x0408003B.

• Promiscuous mode is enabled.

• The maximum frame length, register frm_length,

is configured to 1518.

• For a single-channel MAC with internal FIFO buffers, the transmit FIFO buffer is set to start data transmission as soon as its level reaches tx_section_full

. The receive FIFO buffer is set to begin forwarding Ethernet frames to the Avalon-ST receive interface when its level reaches rx_section_full

.

• Default setting for the PCS function:

• The if_mode

register is set to 0x0000.

• Auto-negotiation between the local PHY and remote link PHY is bypassed.

Test Flow

The testbench performs the following operations upon a simulated power-on reset:

Testbench

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• Initializes the DUT registers.

• Starts transmission. For a single-channel MAC with internal FIFO buffers, clears the FIFOs.

• Ends transmission and checks the following elements to determine that the simulation is successful:

• No Ethernet protocol errors detected.

• Ethernet frames generated and transmitted are received by the frame monitor.

Simulation Model

This section describes the step-by-step instructions for generating the simulation model and simulating your design using the ModelSim simulator or other simulators.

Generate the Simulation Model

The generated design example includes both Verilog HDL and VHDL testbench files for the device under test (DUT)—your custom MegaCore function variation.

To generate a Verilog functional simulation model, use the command prompt and run the

quartus_sh -t generate_sim_verilog.tcl

file. Alternatively, perform the following steps:

1. Launch the Quartus II software and browse to the <variation name>_testbench directory.

2. Open the generate_sim.qpf file from the project directory.

3. On the Tools menu, select Tcl Scripts and select the generate_sim_verilog.tcl file.

4. Click Run.

To generate a VHDL functional simulation model, you can use the command prompt and run the

quartus_sh -t generate_sim_vhdl.tcl

file. Alternatively, perform the following steps:

1. Launch the Quartus II software and browse to the <variation name>_testbench directory.

2. Open the generate_sim.qpf file from the project directory.

3. On the Tools menu, select Tcl Scripts and browse to the generate_sim_vhdl.tcl file.

4. Click Run.

Simulate the IP Core

You can simulate your IP core variation with the functional simulation model and the testbench or design example generated with your IP core. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench.

For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided

with the testbench in

Simulation Model Files

on page 10-5.

Before you begin

Generate the simulation model as shown in

Generate the Simulation Model

on page 10-4 before simulating the testbench design.

To use the ModelSim ® simulation software to simulate the testbench design, follow these steps:

1. For Verilog testbench design:

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Simulation Model Files

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a. Browse to the following project directory: <variation name>_testbench/testbench_verilog/

<variation name>

b. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench: run_<variation_name>_tb.tcl

2. For VHDL testbench design:

a. Browse to the following project directory: <variation name>_testbench/testbench_vhdl/

<variation name>

b. Run the following command to set up the required libraries, to compile the generated IP Functional simulation model, and to exercise the simulation model with the provided testbench: run_<variation_name>_tb.tcl

For more information about simulating Altera IP cores, refer to

Simulating Altera Designs

in volume

3 of the Quartus II Handbook.

Note: Use the simulation models only for simulation and not for synthesis or any other purposes.

Using these models for synthesis creates a nonfunctional design.

Simulation Model Files

Previously, the Triple-Speed Ethernet MegaCore function generates a <variation_name>

.vho

or

<variation_name>

.vo

file for VHDL or Verilog HDL IP functional simulation model.

For the new Triple-Speed Ethernet MegaCore function created in Quartus II ACDS 13.0, the simulation model will be generated using the industrial standard IEEE simulation encryption.

Table 10-2

lists the scripts available for you to compile the simulation model files in a standalone flow.

Table 10-2: Simulation Model Files

Directory Name Description

<variation_name>_sim/mentor/ Contains a ModelSim script

msim_setup.tcl

to set up and run a simulation.

<variation_name>_sim/synopsys/vcs Contains a shell script

vcs_setup.sh

to set up and run a VCS ® simulation.

<variation_name>_sim/synopsys/

vcsmx

<variation_name>_sim/mentor/

cadence

Contains a shell script

vcsmx_setup.sh

and synopsys_sim.setup to set up and run a VCS MX simulation.

Contains a shell script

ncsim_setup.sh

up and run an NCSIM simulation.

and other setup files to set

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Software Programming Interface

11

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Driver Architecture

Figure 11-1: Triple-Speed Ethernet Software Driver Architecture

Avalon-MM Interface

TX SGDMA

Nios II CPU

Client

Apps

Interniche

Stack

TX Path

TSE Driver

RX Path

Setup

Descriptors

Descriptor Memory (1)

TX Descriptor

RX Descriptor

TSE MAC

Control Interface

TX FIFO (2)

MII/GMII

RX FIFO (2)

MII/GMII

RX SGDMA

Memory

Notes to

Figure 11–1

:

1. The first n bytes are reserved for SGDMA descriptors, where n = (Total number of descriptors + 3) ×

32. Applications must not use this memory region.

2. For MAC variations without internal FIFO buffers, the transmit and receive FIFOs are external to the

MAC function.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

11-2

Directory Structure

Directory Structure

Structure of the altera_triple_speed_ethernet directory.

Figure 11-2: Directory Structure

altera_triple_speed_ethernet

HAL triple_speed_ethernet.h

altera_avalon_tse.h

altera_avalon_tse.c

altera_avalon_tse_system_info.c

UCOSII inc src ins_tse_mac.h

triple_speed_ethernet_iniche.h

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PHY Definition

By default, the software driver only supports the following PHYs:

• National DP83848C (10/100 Mbps)

• National DP83865 (10/100/1000 Mbps)

• Marvell 88E1111 (10/100/1000 Mbps)

• Marvell 88E1145 (Quad PHY, 10/100/1000 Mbps).

You can extend the software driver to support other PHYs by defining the PHY profile using the structure alt_tse_phy_profile

and adding it to the system using the function alt_tse_phy_add_profile()

. For each PHY instance, use the structure alt_tse_system_phy_struct

to define it and the function alt_tse_system_add_sys()

to add the instance to the system.

The software driver automatically detects the PHY’s operating mode and speed if the PHY conforms to the following specifications:

• One bit to specify duplex and two consecutive bits (the higher bit being the most significant bit) to specify the speed in the same extended PHY specific register.

• The speed bits are set according to the convention shown in

Table 11-1

.

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Table 11-1: PHY Speed Bit Values

PHY Definition

11-3

Speed (Mbps)

MSB

PHY Speed Bits

0

1

0

LSB

1000

100

10

1

0

0

For PHYs that do not conform to the aforementioned specifications, you can write a function to retrieve the PHY’s operating mode and speed, and set the field

*link_status_read

in the PHY data structure to your function’s address.

You can also execute a function to initialize a PHY profile or a PHY instance by setting the function pointer (

*phy_cfg

and

*tse_phy_cfg

) in the respective structures to the function’s address.

Example of PHY Profile Structure

typedef struct alt_tse_phy_profile_struct{ /* PHY profile */

/*The name of the PHY*/ char name[80];

/*Organizationally Unique Identififier*/ alt_u32 oui;

/*PHY model number*/ alt_u8 model_number;

/*PHY revision number*/ alt_u8 revision_number;

/*The location of the PHY Specific Status Register*/ alt_u8 status_reg_location;

/*The location of the Speed Status bit in the PHY Specific Status

Register*/ alt_u8 speed_lsb_location;

/*The location of the Duplex Status bit in the PHY Status Specific

Register*/ alt_u8 duplex_bit_location;

/*The location of the Link Status bit in PHY Status Specific

Register*/ alt_u8 link_bit_location;

/*PHY initialization function pointer—profile specific*/ alt_32 (*phy_cfg)(np_tse_mac *pmac);

/*Pointer to the function that reads and returns 32-bit link status.Possible status: full duplex (bit 0 = 1), half duplex (bit 0 = 0),gigabit (bit 1 = 1),

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Using Multiple SG-DMA Descriptors

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100Mbps (bit 2 = 1), 10Mbps (bit 3 = 1),invalid speed (bit 16 = 1).*/ alt_u32 (*link_status_read)(np_tse_mac *pmac);

} alt_tse_phy_profile;

Example of PHY Instance Structure

typedef struct alt_tse_system_phy_struct { /* PHY instance */

/* PHY's MDIO address */ alt_32tse_phy_mdio_address;

/* PHY initialization function pointer—instance specific */ alt_32 (*tse_phy_cfg)(np_tse_mac *pmac);

} alt_tse_system_phy;

Using Multiple SG-DMA Descriptors

To successfully use multiple SG-DMA descriptors in your application, make the following modifications:

• Set the value of the constant

ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE

in

altera_avalon_tse.h

to the number of descriptors optimal for your application. The default value is 1 and the maximum value is determined by the constant

NUMBIGBUFFS

. For TCP applications, Altera recommends that you use the default value.

• Increase the amount of memory allocated for the Interniche stack.

The memory space for the Interniche stack is allocated using the Interniche function pk_alloc().

Although user applications and other network interfaces such as LAN91C111 can share the memory space, Altera recommends that you use this memory space for only one purpose, that is storing unprocessed packets for the Triple-Speed Ethernet MegaCore function. Each SG-DMA descriptor used by the device driver consumes a buffer size of 1536 bytes (defined by the constant

BIGBUFSIZE

) in the memory space. To achieve reasonable performance and to avoid memory exhaustion, add a new constant named

NUMBIGBUFS

to your application and set its value using the following guideline:

NUMBIGBUFS

= <current value> + <number of SG-DMA descriptors>

By default, the constant

NUMBIGBUFS

is set to

30

in

ipport.h

. If you changed the default value in the previous release of the MegaCore function to optimize performance and resource usage, use the modified value to compute the new value of

NUMBIGBUFS

.

Using Jumbo Frames

To use jumbo frames, set the frm_length

register to 9600 and edit the files and definitions.

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Table 11-2: Jumbo Frames Definitions

API Functions

File ip\altera\ethernet\altera_eth_tse\src\ software\lib\UCOSII\inc\iniche\altera_ eth_tse_iniche.h

Definition

#define ALTERA_TSE_PKT_INIT_LEN 8206

#define ALTERA_TSE_MAX_MTU_SIZE 8192

#define ALTERA_TSE_MIN_MTU_SIZE 14

ip\altera\ethernet\altera_eth_tse\src\ software\lib\HAL\inc\altera_avalon_tse.h

<BSP project directory>

\iniche\src\h\nios2\ipport.h

#define ALTERA_TSE_MAC_MAX_FRAME_LENGTH 8196

(1)

#ifndef BIGBUFSIZE

#define BIGBUFSIZE 1536

#endif

Note to

Table 11-2

:

1. The maximum value for

ALTERA_TSE_MAC_MAX_FRAME_LENGTH

is defined by the frm_length register.

11-5

API Functions

This section describes each provided API function in alphabetical order.

alt_tse_mac_get_common_speed()

Details

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

alt_tse_mac_get_common_speed(np_tse_mac *pmac)

No

No

Parameter:

Return:

See also:

<

altera_avalon_tse.h

>

The alt_tse_mac_get_common_speed() obtains the common speed supported by the PHYs connected to a multiport MAC and remote link partners.

pmac

—A pointer to the base of the MAC control interface.

TSE_PHY_SPEED_1000

if the PHYs common speed is 1000 Mbps.

TSE_PHY_SPEED_100

if the PHYs common speed is 100 Mbps.

TSE_PHY_SPEED_10

if the PHYs common speed is 10 Mbps.

TSE_PHY_SPEED_NO_COMMON

if there isn’t a common speed among the PHYs.

alt_32 alt_tse_mac_set_common_speed()

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11-6 alt_tse_mac_set_common_speed()

alt_tse_mac_set_common_speed()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Details

alt_tse_mac_set_common_speed(np_tse_mac *pmac, alt_32 common_ speed)

No

No

Parameter:

Return:

<

altera_avalon_tse.h

>

The alt_tse_mac_set_common_speed()

sets the speed of a multiport MAC and the PHYs connected to it.

pmac

—A pointer to the base of the MAC control interface.

common_speed

—The speed to set.

TSE_PHY_SPEED_1000

if the PHYs common speed is 1000 Mbps.

TSE_PHY_SPEED_100

if the PHYs common speed is 100 Mbps.

TSE_PHY_SPEED_10

if the PHYs common speed is 10 Mbps.

TSE_PHY_SPEED_NO_COMMON

if there isn’t a common speed among the PHYs.

The current speed of the MAC and PHYs is not changed.

See also:

alt_32 alt_tse_mac_get_common_speed()

alt_tse_phy_add_profile()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Details

alt_tse_phy_add_profile(alt_tse_phy_profile *phy)

No

No

Parameter:

Return:

<

altera_avalon_tse.h

>

The alt_tse_phy_add_profile()

function adds a new PHY to the PHY profile. Use this function if you want to use PHYs other than Marvell

88E1111, Marvell Quad PHY 88E1145, National DP83865, and National

DP83848C.

phy

—A pointer to the PHY structure.

ALTERA_TSE_MALLOC_FAILED

if the operation is not successful. Otherwise, the index of the newly added PHY is returned.

alt_tse_system_add_sys()

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Prototype: triple_speed_ethernet_init()

Details

alt_tse_system_add_sys(alt_tse_system_mac *psys_mac, alt_tse_ system_sgdma *psys_sgdma, alt_tse_system_desc_mem *psys_mem, alt_tse_system_shared_fifo *psys_shared_fifo, alt_tse_system_ phy *psys_phy)

No

No

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

<

system.h

><

system.h

><

altera_avalon_tse_system_info.h

>

<

altera_avalon_tse.h

><

altera_avalon_tse_system_info.h

>

<

altera_avalon_tse_system_info.h

><

altera_avalon_tse_system_info.h

>

The alt_tse_system_add_sys()

function defines the TSE system’s components: MAC, scatter-gather DMA, memory, FIFO and PHY. This needs to be done for each port in the system.

psys_mac

—A pointer to the MAC structure.

psys_sgdma

—A pointer to the scatter-gather DMA structure.

psys_mem

—A pointer to the memory structure.

psys_shared_fifo

—A pointer to the FIFO structure.

psys_phy

—A pointer to the PHY structure.

SUCCESS

if the operation is successful.

SUCCESS

if the operation is successful.

ALTERA_TSE_MALLOC_FAILED

if the operation fails.

ALTERA_TSE_SYSTEM_DEF_ERROR

if one or more of the definitions are incorrect, or empty.

triple_speed_ethernet_init()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Details

error_t triple_speed_ethernet_init(alt_niche_dev *p_dev)

No

No

<

triple_speed_ethernet_iniche.h

>

11-7

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11-8 tse_mac_close()

Description:

Parameter:

Return:

See also:

tse_mac_close()

Details

The triple_speed ethernet_init()

function opens and initializes the

Triple-Speed Ethernet driver. Initialization involves the following operations:

• Set up the NET structure of the MAC device instance.

• Configure the MAC PHY Address.

• Register and open the SGDMA RX and TX Module of the MAC device instance.

• Enable the SGDMA RX interrupt and register it to the Operating System.

• Register the SGDMA RX callback function.

• Obtains the PHY Speed of the MAC.

• Set up the Ethernet MAC Register settings for the Triple-Speed Ethernet driver operation.

• Set up the initial descriptor chain to start the SGDMA RX operation.

p_dev

—A pointer to the Triple-Speed Ethernet device instance.

SUCCESS

if the Triple-Speed Ethernet driver is successfully initialized.

tse_mac_close()

Details

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

int tse_mac_close(int iface)

No

No

Parameter:

Return:

See also:

<

triple_speed_ethernet_iniche.h

>

The tse_mac_close()

closes the Triple-Speed Ethernet driver by performing the following operations:

• Configure the admin and operation status of the NET structure of the

Triple-Speed Ethernet driver instance to

ALTERA_TSE_ADMIN_STATUS_

DOWN

.

• De-register the SGDMA RX interrupt from the operating system.

• Clear the RX_ENA bit in the command_config register to disable the RX datapath.

iface

—The index of the MAC interface. This argument is reserved for configurations that contain multiple MAC instances.

SUCCESS

if the close operations are successful.

An error code if de-registration of SGDMA RX from the operating system failed.

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tse_mac_raw_send()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description: tse_mac_raw_send()

Details

int tse_mac_raw_send(NET net, char *data, unsigned data_bytes)

No

No

Parameter:

Return:

<

triple_speed_ethernet_iniche.h

>

The tse_mac_raw_send()

function sends Ethernet frames data to the MAC function. It validates the arguments to ensure the data length is greater than the ethernet header size specified by

ALTERA_TSE_MIN_MTU_SIZE

. The function also ensures the SGDMA TX engine is not busy prior to constructing the descriptor for the current transmit operation.

Upon successful validations, this function calls the internal API, tse_mac_ sTxWrite,

to initiate the synchronous SGDMA transmit operation on the current data buffer.

net

—The NET structure of the Triple-Speed Ethernet MAC instance.

data

—A data pointer to the base of the Ethernet frame data, including the header, to be transmitted to the MAC. The data pointer is assumed to be word-aligned.

data_bytes

—The total number of bytes in the Ethernet frame including the additional padding bytes as specified by ETHHDR_BIAS.

SUCCESS

if the current data buffer is successfully transmitted.

SEND_DROPPED

if the number of data bytes is less than the Ethernet header size.

ENP_RESOURCE

if the SGDMA TX engine is busy.

tse_mac_setGMII mode()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

Details

int tse_mac_setGMIImode(np_tse_mac *pmac)

No

No

<

triple_speed_ethernet_iniche.h

>

The tse_mac_setGMIImode()

function sets the MAC function operation mode to Gigabit (GMII). The settings of the command_config

register are restored at the end of the function.

pmac

—A pointer to the MAC control interface base address.

SUCCESS

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11-10 tse_mac_setMIImode()

Details

See also:

tse_mac_setMIImode()

tse_mac_setMIImode()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

See also:

Details

int tse_mac_setMIImode(np_tse_mac *pmac)

No

No

<

triple_speed_ethernet_iniche.h

>

The tse_mac_setMIImode()

function sets the MAC function operation mode to MII (10/100). The settings of the command_config

register are restored at the end of the function.

pmac

—A pointer to the MAC control interface base address.

SUCCESS tse_mac_setGMIImode()

tse_mac_SwReset()

Prototype:

Thread-safe:

Available from

ISR:

Include:

Description:

Parameter:

Return:

Details

int tse_mac_SwReset(np_tse_mac *pmac)

No

No

<

triple_speed_ethernet_iniche.h

>

The tse_mac_SwReset()

performs a software reset on the MAC function. A software reset occurs with some latency as specified by

ALTERA_TSE_SW_

RESET_TIME_OUT_CNT

. The settings of the command_config

register are restored at the end of the function.

pmac

—A pointer to the MAC control interface base address.

SUCCESS

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Constants

Table 11-3

lists all constants defined for the MAC registers manipulation and provides links to detailed

descriptions of the registers. It also list the constants that define the MAC operating mode and timeout values.

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Table 11-3: Constants Mapping

Constants

Constant Value Description

ALTERA_TSE_DUPLEX_MODE_DEFAULT

ALTERA_TSE_MAC_SPEED_DEFAULT

ALTERA_TSE_SGDMA_RX_DESC_CHAIN_SIZE

ALTERA_CHECKLINK_TIMEOUT_THRESHOLD

ALTERA_AUTONEG_TIMEOUT_THRESHOLD

1

0

1

1000000

250000

0: Half-duplex

1: Full-duplex

0: 10 Mbps

1: 100 Mbps

2: 1000 Mbps

The number of SG-DMA descriptors required for the current operating mode.

The timeout value when the

MAC tries to establish a link with a PHY.

The auto-negotiation timeout value.

Command_Config Register (

Command_Config Register (Dword Offset 0x02)

on page 6-7)

ALTERA_TSEMAC_CMD_TX_ENA_OFST

0

Configures the

TX_ENA bit.

ALTERA_TSEMAC_CMD_TX_ENA_MSK

0x1

ALTERA_TSEMAC_CMD_RX_ENA_OFST

1

Configures the

RX_ENA

bit.

ALTERA_TSEMAC_CMD_RX_ENA_MSK

0x2

ALTERA_TSEMAC_CMD_XON_GEN_OFST

ALTERA_TSEMAC_CMD_XON_GEN_MSK

ALTERA_TSEMAC_CMD_ETH_SPEED_OFST

2

0x4

3

Configures the

Configures the

XON_GEN bit.

ETH_SPEED

bit.

ALTERA_TSEMAC_CMD_ETH_SPEED_MSK

ALTERA_TSEMAC_CMD_PROMIS_EN_OFST

ALTERA_TSEMAC_CMD_PROMIS_EN_MSK

ALTERA_TSEMAC_CMD_PAD_EN_OFST

0x8

4

0x10

5

Configures the

Configures the

PROMIS_EN

PAD_EN

bit.

bit.

ALTERA_TSEMAC_CMD_PAD_EN_MSK

ALTERA_TSEMAC_CMD_CRC_FWD_OFST

ALTERA_TSEMAC_CMD_CRC_FWD_MSK

ALTERA_TSEMAC_CMD_PAUSE_FWD_OFST

0x20

6

0x40

7

Configures the

Configures the

CRC_FWD

bit.

PAUSE_FWD

bit.

ALTERA_TSEMAC_CMD_PAUSE_FWD_MSK

ALTERA_TSEMAC_CMD_PAUSE_IGNORE_OFST

ALTERA_TSEMAC_CMD_PAUSE_IGNORE_MSK

0x80

8

Configures the bit.

PAUSE_IGNORE

ALTERA_TSEMAC_CMD_TX_ADDR_INS_OFST

ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK

0x100

9

0x200

Configures the bit.

TX_ADDR_INS

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11-12

Constants

Constant

ALTERA_TSEMAC_CMD_HD_ENA_OFST

ALTERA_TSEMAC_CMD_HD_ENA_MSK

ALTERA_TSEMAC_CMD_EXCESS_COL_OFST

ALTERA_TSEMAC_CMD_EXCESS_COL_MSK

ALTERA_TSEMAC_CMD_LATE_COL_OFST

ALTERA_TSEMAC_CMD_LATE_COL_MSK

ALTERA_TSEMAC_CMD_SW_RESET_OFST

ALTERA_TSEMAC_CMD_SW_RESET_MSK

ALTERA_TSEMAC_CMD_MHASH_SEL_OFST

ALTERA_TSEMAC_CMD_MHASH_SEL_MSK

ALTERA_TSEMAC_CMD_LOOPBACK_OFST

ALTERA_TSEMAC_CMD_LOOPBACK_MSK

ALTERA_TSEMAC_CMD_TX_ADDR_SEL_OFST

ALTERA_TSEMAC_CMD_TX_ADDR_SEL_MSK

ALTERA_TSEMAC_CMD_MAGIC_ENA_OFST

ALTERA_TSEMAC_CMD_MAGIC_ENA_MSK

ALTERA_TSEMAC_CMD_SLEEP_OFST

ALTERA_TSEMAC_CMD_SLEEP_MSK

ALTERA_TSEMAC_CMD_WAKEUP_OFST

ALTERA_TSEMAC_CMD_WAKEUP_MSK

ALTERA_TSEMAC_CMD_XOFF_GEN_OFST

ALTERA_TSEMAC_CMD_XOFF_GEN_MSK

ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_OFST

ALTERA_TSEMAC_CMD_CNTL_FRM_ENA_MSK

ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_OFST

ALTERA_TSEMAC_CMD_NO_LENGTH_CHECK_MSK

ALTERA_TSEMAC_CMD_ENA_10_OFST

ALTERA_TSEMAC_CMD_ENA_10_MSK

Value

10

0x8000

16

0x70000

19

0x80000

20

0x10000

0

21

0x400

11

0x800

12

0x1000

13

0x2000

14

0x4000

15

0x20000

0

22

0x40000

0

23

0x80000

0

24

0x10000

00

25

0x20000

00

Description

Configures the

HD_ENA

bit.

Configures the

EXCESS_COL

bit.

Configures the

LATE_COL

bit.

Configures the

SW_RESET

bit.

Configures the

MHASH_SEL

bit.

Configures the

LOOP_ENA

bit.

Configures the

TX_ADDR_SEL bits (bits 16 - 18).

Configures the

MAGIC_ENA bit.

Configures the

SLEEP

bit.

Configures the

WAKEUP

bit.

Configures the

XOFF_GEN

bit.

Configures the

CNTL_FRM_ENA bit.

Configures the

NO_LENGTH_

CHECK

bit.

Configures the

ENA_10

bit.

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Constants

Constant Value Description

ALTERA_TSEMAC_CMD_RX_ERR_DISC_OFST

ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK

ALTERA_TSEMAC_CMD_CNT_RESET_OFST

26

0x40000

00

31

Configures the bit.

RX_ERR_DISC

ALTERA_TSEMAC_CMD_CNT_RESET_MSK

0x80000

000

Configures the

CNT_RESET

Tx_Cmd_Stat Register (

Transmit and Receive Command Registers (Dword Offset 0x3A –

0x3B)

on page 6-13)

bit.

ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_OFST

ALTERA_TSEMAC_TX_CMD_STAT_OMITCRC_MSK

17

0x20000

Configures the

OMIT_CRC bit.

ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_OFST

ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK

ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_OFST

18

0x40000

25

Configures the

TX_SHIFT16

Rx_Cmd_Stat Register (

Transmit and Receive Command Registers (Dword Offset 0x3A –

0x3B)

on page 6-13)

bit.

ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK

0x20000

00

Configures the

RX_SHIFT16

bit

11-13

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Ethernet Frame Format

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Basic Frame Format

Figure A-1: MAC Frame Format

Frame length

7 octets

1 octet

6 octets

6 octets

2 octets

0..1500/9600 octets

0..46 octets

4 octets

PREAMBLE

SFD

DESTINATION ADDRESS

SOURCE ADDRESS

LENGTH/TYPE

PAYLOAD DATA

PAD

FRAME CHECK SEQUENCE

EXTENSION

(half duplex only)

A basic Ethernet frame comprises the following fields:

• Preamble—a maximum of 7-octet fixed value of 0x55.

• Start frame delimiter (SFD)—a 1-octet fixed value of 0xD5 which marks the beginning of a frame.

• Destination and source addresses—6 octets each. The least significant byte is transmitted first.

• Length or type—a 2-octet value equal to or greater than 1536 (0x600) indicates a type field. Otherwise, this field contains the length of the payload data. The most significant byte of this field is transmitted first.

• Payload Data and Pad—variable length data and padding.

• Frame check sequence (FCS)—a 4-octet cyclic redundancy check (CRC) value for detecting frame errors during transmission.

• An extension field—Required only for gigabit Ethernet operating in half-duplex mode. The MAC function does not support this implementation.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

A-2

VLAN and Stacked VLAN Frame Format

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VLAN and Stacked VLAN Frame Format

The extension of a basic MAC frame is a virtual local area network (VLAN) tagged frame, which contains an additional 4-byte field for the VLAN tag and information between the source address and length/type fields. VLAN tagging is defined by the IEEE Standard 802.1Q. VLAN tagging can identify and separate many groups' network traffic from each other in enterprise and metro networks. Each VLAN group can consist of many users with varied MAC address in different geographical locations of a network. VLAN tagging increases and scales the network performance and add privacy and safety to various groups and customers' network traffic.

VLAN tagged frames have a maximum length of 1522 bytes, excluding the preamble and the SFD fields.

Figure A-2: VLAN Tagged MAC Frame Format

Frame length

7 octets

1 octet

6 octets

6 octets

2 octets

2 octets

2 octets

0..1500/9600 octets

0..42 octets

4 octets

PREAMBLE

SFD

DESTINATION ADDRESS

SOURCE ADDRESS

LENGTH/TYPE (VLAN Tag 0x8100)

VLAN info

CLIENT LENGTH/TYPE

PAYLOAD DATA

PAD

FRAME CHECK SEQUENCE

EXTENSION (half duplex only)

In metro Ethernet applications, which require more scalability and security due to the sharing of an

Ethernet link by many service providers, MAC frames can be tagged with two consecutive VLAN tags

(stacked VLAN). Stacked VLAN frames contain an additional 8-byte field between the source address and client length/type fields, as illustrated.

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Figure A-3: Stacked VLAN Tagged MAC Frame Format

Frame length

7 octets

1 octet

6 octets

6 octets

2 octets

2 octets

2 octets

2 octets

2 octets

0..1500/9600 octets

0..38 octets

4 octets

Pause Frame Format

PREAMBLE

SFD

DESTINATION ADDRESS

SOURCE ADDRESS

LENGTH/TYPE (VLAN Tag 0x8100)

VLAN info

LENGTH/TYPE (VLAN Tag 0x8100)

VLAN info

CLIENT LENGTH/TYPE

PAYLOAD DATA

PAD

FRAME CHECK SEQUENCE

EXTENSION (half duplex only)

A-3

Stacked VLANs

Pause Frame Format

A pause frame is generated by the receiving device to indicate congestion to the emitting device. If flow control is supported, the emitting device should stop sending data upon receiving pause frames.

The length/type field has a fixed value of 0x8808, followed by a 2-octet opcode field of 0x0001. A 2-octet pause quanta is defined in the second and third bytes of the frame payload (P1 and P2). The pause quanta,

P1, is the most significant byte. A pause frame has no payload length field, and is always padded with

42 bytes of 0x00.

Figure A-4: Pause Frame Format

7octets

1 octet

6 octets

6 octets

2 octets

2 octets

2 octets

42 octets

4 octets

PREAMBLE

SFD

DESTINATION ADDRESS

SOURCE ADDRESS

TYPE (0x8808)

OPCODE (0X0001)

PAUSE QUANTA (P1, P2)

PAD

CRC

Payload

Ethernet Frame Format

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Pause Frame Generation

When you turn on the Enable full-duplex flow control option, pause frame generation is triggered by the following events:

• RX FIFO fill level hits the rx_section_empty

threshold.

• XOFF register write.

• XON register write.

• XOFF I/O pin ( xoff_gen

) assertion.

• XON I/O pin ( xon_gen

) assertion.

If the RX FIFO buffer is almost full, the MAC function triggers the pause frame generation to the remote

Ethernet device.

If the local Ethernet device needs to generate pause frame via XOFF or XON register write or I/O pin assertion, it is recommended to set the rx_section_empty

register to a larger value to avoid nondeterministic result.

Table A-1

summarizes the pause frame generation based on the above events.

Table A-1: Pause Frame Generation

Register Write or I/O Pin Assertion

(1)

Description

XOFF_GEN XON_GEN

1

0

0

1

If the

XOFF_GEN

bit is set to 1, the XOFF pause frames are continu‐ ously generated and sent to the MII/GMII TX interface until the

XOFF_GEN

bit is cleared.

If the

XON_GEN

bit is set to 1, the XON pause frames are continu‐ ously generated and sent to the MII/GMII TX interface until the

XON_GEN

bit is cleared.

1 1 This event is not recommended as it will produce non-determin‐ istic result.

Note to

Table A-1

:

1. Set the XON and XOFF registers to 0 when you use the I/O pin to generate the pause frame and vice versa.

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Functionality Configuration Parameters

You can use these parameters to enable or disable specific functionality in the MAC and PCS.

Table B-1: MegaCore Functionality Configuration Parameters

Parameter Description

Supported in configurations that contain the 10/100/1000 Ethernet MAC

ETH_MODE

10: Enables MII.

100: Enables MII.

1000: Enables GMII.

HD_ENA

TB_MACPAUSEQ

TB_MACIGNORE_

PAUSE

TB_MACFWD_PAUSE

TB_MACFWD_CRC

TB_MACINSERT_

ADDR

TB_PROMIS_ENA

TB_MACPADEN

TB_MACLENMAX

TB_IPG_LENGTH

Sets the

HD_ENA

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the pause_quant

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the

PAUSE_IGNORE

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the

PAUSE_FWD

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the

CRC_FWD

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the

ADDR_INS

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the

PROMIS_EN

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Sets the

PAD_EN

bit in the command_config

register. See

Command_Config Register (Dword Offset 0x02)

on page 6-7.

Maximum frame length.

Sets the tx_ipg_length

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

1000

0

15

0

0

0

0

1

1

1518

12

Default

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. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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B-2

Functionality Configuration Parameters

Parameter

TB_MDIO_ADDR0

TB_MDIO_ADDR1

TX_FIFO_AE

TX_FIFO_AF

RX_FIFO_AE

RX_FIFO_AF

TX_FIFO_

SECTION_EMPTY

TX_FIFO_

SECTION_FULL

RX_FIFO_

SECTION_EMPTY

RX_FIFO_

SECTION_FULL

MCAST_TABLEN

MCAST_ADDRESS-

LIST

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Default Description

Sets the mdio_addr0

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the mdio_addr1

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the tx_almost_empty

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the tx_almost_full

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the rx_almost_empty

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the rx_almost_full

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the tx_section_empty

register. See

Base Configuration

Registers (Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the tx_section_full

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the rx_section_empty

register. See

Base Configuration

Registers (Dword Offset 0x00 – 0x17)

on page 6-3.

Sets the rx_section_full

register. See

Base Configuration Registers

(Dword Offset 0x00 – 0x17)

on page 6-3.

Specifies the first n addresses from

MCAST_ADDRESSLIST

from which multicast address is selected.

A list of multicast addresses.

0

1

8

10

8

8

16

16

0

16

9

0x887654332

211

0x886644352

611

0xABCDEF0

12313

0x92456545

AB15

0x432680010

217

0xADB5892

15439

0xFFEACFE

3434B

0xFFCCDD

AA3123

0xADB3584

15439

Supported in configurations that contain the 1000BASE-X/SGMII PCS

TB_SGMII_ENA

Sets the

SGMII_ENA

bit in the if_mode

register. See

If_Mode Register

(Word Offset 0x14)

on page 6-26.

0

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Parameter

TB_SGMII_AUTO_

CONF

Description

Test Configuration Parameters

Default

B-3

Sets the

USE_GMII_AN

bit in the if_mode

register. See

If_Mode

Register (Word Offset 0x14)

on page 6-26.

0

Test Configuration Parameters

You can use these parameters to create custom test scenarios.

Table B-2: Test Configuration Parameters

Parameter Description

Supported in configurations that contain the 10/100/1000 Ethernet MAC

TB_RXFRAMES

TB_TXFRAMES

Enables local loopback on the Ethernet side (GMII/MII/RGMII). The value must always be set to 0.

Specifies the number of frames to be generated by the Avalon-ST

Ethernet frame generator.

TB_RXIPG

TB_ENA_VAR_IPG

IPG on the receive path.

0: A constant IPG,

TB_RXIPG

, is used by the GMII/RGMII/MII

Ethernet frame generator.

0

5

12

0

Default

TB_LENSTART

TB_LENSTEP

TB_LENMAX

TB_ENA_PADDING

1: Enables variable IPG on the receive path.

Specifies the payload length of the first frame generated by the frame generators. The payload length of each subsequent frame is incremented by the value of

TB_LENSTEP

.

Specifies the payload length increment.

Specifies the maximum payload length generated by the frame generators. If the payload length exceeds this value, it wraps around to

TB_LENSTART

. This parameter can be used to test frame length error by setting it to a value larger than the value of

TB_MACLENMAX

.

0: Disables padding.

100

1

1500

1

TB_ENA_VLAN

TB_STOPREAD

1: If the length of frames generated by the GMII/RGMII/MII Ethernet frame generator is less than the minimum frame length (64 bytes), the generator inserts padding bytes to the frames to make up the minimum length.

0: Only basic frames are generated.

1: Enables VLAN frames generation. This value specifies the number of basic frames generated before a VLAN frame is generated followed by a stacked VLAN frame.

Specifies the number of packets to be read from the receive FIFO before reading is suspended. You can use this parameter to test FIFO overflow and flow control.

0

0

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Test Configuration Parameters

Parameter

TB_HOLDREAD

TB_TX_FF_ERR

Description

Specifies the number of clock cycles before the Avalon-ST monitor stops reading from the receive FIFO.

0: Normal behavior.

0

TB_TRIGGERXOFF

TB_TRIGGERXON

RX_COL_FRM

RX_COL_GEN

TX_COL_FRM

TX_COL_GEN

TX_COL_NUM

TX_COL_DELAY

TB_PAUSECONTROL

1: Drives the Avalon-ST error signal high to simulate erroneous frames transmission.

Specifies the number of clock cycles from the start of simulation before the xoff_gen

signal is driven.

Specifies the number of clock cycles from the start of simulation before the xon_gen

signal is driven high.

Specifies which frame is received with collision. Valid in fast Ethernet and half-duplex mode only.

Specifies which nibble within the frame collision occurs.

0

0

0

Specifies which frame is transmitted with a collision. Valid in fast

Ethernet and half-duplex mode only.

Specifies which nibble within the frame collision occurs on the transmit path.

0

Specifies the number of consecutive collisions during retransmission. 0

Specifies the delay, in nibbles, between collision and retransmission.

0

0: GMII frame generator does not respond to pause frames.

1: Enables flow control in the GMII frame generator.

1

0

0

0

TB_MDIO_

SIMULATION

Enable / Disable MDIO simulation.

Supported in configurations that contain the 1000BASE-X/SGMII PCS

TB_SGMII_HD

0: Disables half-duplex mode.

0

TB_SGMII_1000

TB_SGMII_100

1: Enables half-duplex mode.

0: Disables gigabit operation.

1: Enables gigabit operation.

0: Disables 100 Mbps operation.

1

0

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1000

Default

TB_SGMII_10

1: Enables 100 Mbps operation.

0: Disables 10 Mbps operation.

1: Enables 10 Mbps operation.

0

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Parameter

TB_TX_ERR

0: Disables error generation.

1: Enables error generation.

Description

Test Configuration Parameters

Default

B-5

0

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Time-of-Day (ToD) Clock

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The Time-of-Day (ToD) clock provides a stream of timestamps for the IEEE 1588v2 feature.

ToD Clock Features

• Provides a stream of 64-bit and 96-bit timestamps.

• The 64-bit timestamp has 48-bit nanosecond field and 16-bit fractional nanosecond field.

• The 96-bit timestamp has 48-bit second field, 32-bit nanosecond field, and 16-bit fractional nanosecond field.

• Runs at 125-MHz for the Triple-Speed Ethernet MegaCore function.

• Supports coarse adjustment and fine adjustments through clean frequency adjustment.

• Supports period adjustment for frequency control using the Period register.

• Supports offset adjustment using the AdjustPeriod register.

ToD Clock Device Family Support

Table C-1: Device Family Support

Device Family

Arria V GX/GT/GZ/SoC

Cyclone V GX/GT/SoC

Stratix V GX/GT

Other device families

Preliminary

Preliminary

Preliminary

No support

Support

C

ToD Clock Performance and Resource Utilization

Table C-2

provides the estimated resource utilization and performance of the ToD clock for the Stratix V

device family. The estimates are obtained by compiling the Triple-Speed Ethernet MegaCore function using the Quartus II software targeting a Stratix V GX (5SGXMA7N3F45C3) device with speed grade -3.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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C-2

ToD Clock Parameter Setting

Table C-2: Stratix V Performance and Resource Utilization

MegaCore Function Settings FIFO Buffer

Size (Bits)

Combina‐ tional ALUTs

TOD Clock Default 0 378

Logic

Registers

1,120

Memory

(M20K Blocks/

MLAB Bits)

0/0

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ToD Clock Parameter Setting

The ToD Clock is part of the reference design components in the Quartus II software. You can enable this module from the IP Catalog and in Qsys (Interface Protocols > Ethernet > Reference Design

Components).

Table C-3: ToD Clock Configuration Parameters

Name

DEFAULT_NSEC_

PERIOD

DEFAULT_FNSEC_

PERIOD

DEFAULT_NSEC_

ADJPERIOD

DEFAULT_FNSEC_

ADJPERIOD

Value

Between 0 and 0x000F

Between 0 and 0xFFFF

Between 0 and 0x000F

Between 0 and 0xFFFF

Description

4-bit value that defines the reset value for

PERIOD_

NS

. For Triple-Speed Ethernet MegaCore function, set the value to 0x0008.

The default value is 0x0006.

16-bit value that defines the reset value for

PERIOD_

FNS

. For Triple-Speed Ethernet MegaCore function, set the value to 0x0000.

The default value is 0x6666.

4-bit value that defines the reset value for

ADJPERIOD_NS

.

The default value is 0x0006.

16-bit value that defines the reset value for

PERIOD_

FNS

.

The default value is 0x6666.

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ToD Clock Interface Signals

Figure C-1: Time-of-Day Clock Interface Signals

Avalon-MM

Control

Interface

Signals

Avalon-ST

Transmit

Interface

Signals

ToD Clock Interface Signals

ToD Clock

4

32 csr_address[] csr_read csr_write csr_writedata[] clk rst_n csr_readdata[]

32

96

64 period_clk time_of_day_96b_load_valid time_of_day_96b_load_data[] time_of_day_64b_load_valid time_of_day_64b_load_data[] time_of_day_96[] time_of_day_64[] csr_readdata[]

96

64

32

C-3

ToD Clock Avalon-MM Control Interface Signals

Table C-4: Avalon-MM Control Interface Signals for ToD Clock

Signal

csr_address[] csr_read csr_readdata[] csr_write csr_writedata[] clk rst_n

Direction

Input

Input

Output

Input

Input

Input

Input

2

1

1

1

32

1

32

Width Description

Use this bus to specify the register address you want to read from or write to.

Assert this signal to request a read.

Carries the data read from the specified register.

Assert this signal to request a write.

Carries the data to be written to the specified register.

Register access reference clock.

Assert this active low signal to reset the ToD clock.

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C-4

ToD Clock Avalon-ST Transmit Interface Signals

ToD Clock Avalon-ST Transmit Interface Signals

Table C-5: Avalon-ST Transmit Interface Signals for ToD Clock

Signal

time_of_day_64b[] time_of_day_96b[]

Direction

Output 64

Width

time_of_day_96b_load_valid

Input time_of_day_96b_load_data[]

Input time_of_day_64b_load_valid

Input time_of_day_64b_load_data[]

Input period_clk

Output

Input

96

1

96

1

64

1

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Description

Timestamp from the ToD clock

• Bits 0 to 15: 16-bit fractional nanosecond field

• Bits 16 to 63: 48-bit nanosecond field

Timestamp from the ToD clock

• Bits 0 to 15: 16-bit fractional nanosecond field

• Bits 16 to 47: 32-bit nanosecond field

• Bits 48 to 95: 48-bit second field

Indicates that the synchronized ToD is valid.

Every time you assert this signal, the synchronized ToD is loaded into the ToD clock. Assert this signal for only one clock cycle.

Loads 96-bit synchronized ToD from master

ToD clock to slave ToD clock within 1 clock cycle.

• Bits 0 to 15: 16-bit fractional nanosecond field

• Bits 16 to 63: 32-bit nanosecond field

• Bits 64 to 95: 48-bit second field

Indicates that the synchronized ToD is valid.

Every time you assert this signal, the synchronized ToD is loaded into the ToD clock. Assert this signal for only one clock cycle.

Loads 64-bit synchronized ToD from master

ToD clock to slave ToD clock within 1 clock cycle.

• Bits 0 to 15: 16-bit fractional nanosecond field

• Bits 16 to 63: 48-bit nanosecond field

Clock for the ToD clock. The clock must be in the same clock domain as tx_time_of_day and rx_time_of_day

in the MAC function.

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Signal

period_rst_n

Direction

Input 1

Width

ToD Clock Configuration Register Space

Description

Assert this signal to reset period_clk

to the same clock domain as tx_time_of_day

and rx_time_of_day

in the MAC function.

C-5

ToD Clock Configuration Register Space

Table C-6: ToD Clock Registers

Dword

Offset

Name

0x00

SecondsH

R/W

RW

0x01

SecondsL

0x02

NanoSec

0x03 Reserved

0x04

Period

0x05 AdjustPeriod

0x06 AdjustCount

RW

RW

RW

RW

RW

Description HW Reset

• Bits 0 to 15: High-order 16-bit second field.

• Bits 16 to 31: Not used.

Bits 0 to 32: Low-order 32-bit second field.

Bits 0 to 32: 32-bit nanosecond field.

Reserved for future use

The period for the frequency adjustment.

• Bits 0 to 15: Period in fractional nanosecond (

PERIOD_

FNS

).

• Bits 16 to 24: Period in nanosecond (

PERIOD_NS

).

• Bits 25 to 31: Not used.

The default value for the period depends on the f the MAC function. For example, if f

MAX

MAX

of

= 125-MHz, the period is 8-ns (

PERIOD_NS

= 0x0008 and

PERIOD_FNS

=

0x0000).

0x0

— n

0x0

0x0

The period for the offset adjustment.

• Bits 0 to 15: Period in fractional nanosecond

(

ADJPERIOD_FNS

).

• Bits 16 to 24: Period in nanosecond (

ADJPERIOD_NS

).

• Bits 25 to 31: Not used.

Bits 0 to 19: The number of AdjustPeriod clock cycles used during offset adjustment.

Bits 20 to 31: Not used.

0x0

0x06

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C-6

Dword

Offset

Using ToD Clock SecondsH, SecondsL, and NanoSec Registers

Name

0x07

DriftAdjust

R/W

RW

0x08

DriftAdjustRate

RW

Description

The drift of ToD adjusted periodically by adding a correction value as configured in this register space.

• Bits 0 to 15: Adjustment value in fractional nanosecond (

DRIFT_ADJUST_FNS

). This value is added into the current ToD during the adjustment. The default value is 0.

• Bits 16 to 19: Adjustment value in nanosecond

(

DRIFT_ADJUST_NS

). This value is added into the current ToD during the adjustment. The default value is 0.

• Bits 20 to 32: Not used.

The count of clock cycles for each ToD’s drift adjustment to take effect.

• Bits 0 to 15: The number of clock cycles (

ADJUST_

RATE

). The ToD adjustment happens once after every period in number of clock cycles as indicated by this register space.

• Bits 16 to 32: Not used.

0x0

0x0

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HW Reset

Using ToD Clock SecondsH, SecondsL, and NanoSec Registers

To avoid data integrity issue, follow these sequence to read from or write to the

SecondsH

,

SecondsL

, and

NanoSec

registers:

Read: Read from

NanoSec

, then

SecondsL

, and followed by

SecondsH

.

Write: Write to

SecondsH

, then

SecondsL

, and followed by

NanoSec

.

Adjusting ToD Clock Drift

You can use the

DriftAdjust

and

DriftAdjustRate

registers to correct any drift in the ToD clock.

In the case of a ToD for 10G with period of 6.4ns, the nanosecond field is converted directly to

PERIOD_NS while the fractional nanosecond need to be multiplied with 216 or 65536 in order to convert to

PERIOD_FNS

. This results in 0x6

PERIOD_NS

and 0x6666.4

PERIOD_FNS

.

PERIOD_NS

only accepts 0x6666 and ignores 0x0000.4, which in turn would cause some inaccuracy in the configured period. This inaccuracy causes the ToD to drift from the actual time as much as 953.67 ns after a period of 1 second. You would notice that after every 5 cycles, 0x0000.4 accumulates to 0x0002. If the

TOD is able to add 0x0002 of fractional nanosecond into the ToD once after every period of 5 cycles, then it will correct the drift.

Therefore, for the 10G case,

DRIFT_ADJUST_NS

is now configured to 0x0,

DRIFT_ADJUST_FNS

is configured to 0x0002 and

ADJUST_RATE

is configured to 0x5.

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ToD Synchronizer

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The ToD Synchronizer provides a high accuracy synchronization of time of day from a master ToD clock to a slave ToD clock. This synchronizer provides more user flexibility for your design.

The IEEE 1588v2 specifies multiple type of PTP devices, which include the following clocks:

• ordinary clock

• boundary clock

• transparent clock

• peer to peer transparent clock

Some of these PTP devices, boundary clock for example, consists of multiple ports that act as master or slave in the IEEE 1588v2 system. All these ports may share a common system clock or have its own individual clock. If every port has an individual ToD running on its own clock, then you must implement a method to instantiate one ToD clock as the master and the rest of the ToD clocks synchronized to this master ToD clock.

For this purpose, Altera provides the ToD synchronizer module. This module synchronizes a master ToD and a slave ToD in the following conditions:

• Master and slave ToD clock are in the same frequency (within 125 MHz to 312.5 MHz) but different phase.

• Master and slave ToD clock are in the same frequency (within 125 MHz to 312.5 MHz) but different

PPM.

• Master and slave ToD clock are in different frequencies of either 125 MHz or 156.25 MHz.

• Master and slave ToD clock are in different frequencies of either 125 MHz or 312.5 MHz.

• Master and slave ToD clock are in different frequencies of either 156.25 MHz or 312.5 MHz.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

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ISO

9001:2008

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ToD Synchronizer Block

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ToD Synchronizer Block

Figure D-1: Connection between ToD Synchronizer, Master ToD, Slave ToD, and Sampling Clock PLL

Master reset

Master clock period_rst_n period_clk

Master ToD

1’b1 time_of_day_96b

Master ToD start_tod_sync tod_master_data reset_master clk_master

ToD Synchronizer

Slave ToD tod_slave_valid

Synchronization valid tod_slave_data

Synchronization ToD time_of_day_96b_load_valid time_of_day_96b_load_data reset_slave clk_slave period_rst_n period_clk

Slave reset

Slave clock

PLL

Sampling clock clk_sampling

The components:

• Master TOD clock domain—consists of three interfaces: clk_master

, reset_master

, and tod_master_data

.

• Slave TOD clock domain—consists of five interfaces: clk_slave

, reset_slave

, tod_slave_valid

, tod_slave_data

, and start_tod_sync

.

• Sampling clock PLL—consists of the clk_domain

interface.

The Tod synchronizer module synchronizes the master ToD clock domain with the slave ToD clock domain. The dual-clock FIFO in the Tod synchronizer block takes in the time of day from the master ToD clock domain and transfers it to the slave ToD clock domain. The slave ToD then will load the synchron‐ ized time of day into its own internal counter, which then increments based on the new value.

As the ToD transfer is in progress, the master ToD domain keeps incrementing. When the ToD reaches the slave ToD clock domain and is ready to be loaded, it is much slower than the master ToD. To achieve high accuracy synchronization, the latency caused by the transfer must be reflected in the synchronized

ToD.

The sampling clock PLL ( clk_sampling

) samples the FIFO fill level and calculates the latency through the

FIFO. For better accuracy, the sampling clock must be derived from the master ( clk_master

) or slave

( clk_slave

) clock domain using a PLL.

If you use the recommended sampling clock frequency, the Tod synchronizer module takes 64 clock cycles of sampling clock for every newly synchronized ToDto be valid at the output port.

Altera recommends that you use the following sampling clock frequencies:

• 1G master and slave—(64/63)*125 MHz

• 10G master and slave—(64/63)*156.25 MHz

• 1G master and 10G slave—(16/63)*125 MHz or (64/315)*156.25 MHz

• 10G master and 1G slave—(16/63)*125 MHz or (64/315)*156.25 MHz

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ToD Synchronizer Parameter Settings

D-3

• 10G (312.5 Mhz) master and slave—(64/63)*312.5 MHz

• 1G master and 10G (312.5 Mhz) slave—(32/63)*125 MHz or (64/315)*312.5 MHz

• 10G (156.25 MHz) master and 10G (312.5 Mhz) slave—(64/63)*156.25 MHz or (32/63)*312.5 MHz

Table D-1: Settings to Achieve The Recommended Factors for Stratix V PLL

Settings

M-Counter

N-Counter

C-Counter

64

21

03

64/63

16

03

21

16/63

64

21

15

64/315

32

03

21

32/63

ToD Synchronizer Parameter Settings

The ToD Synchronizer is part of the reference design components in the Quartus II software. You can enable this module from the IP Catalog and in Qsys (Interface Protocols > Ethernet > Reference Design

Components).

Table D-2: ToD Synchronizer Configuration Parameters

Name

TOD_MODE

Value

Between 0 and 1

Description

Value that defines the time of day format that this block is synchronizing.

The default value is 1.

• 1: 96-bits format (32 bits seconds, 48 bits nanosecond and

16 bits fractional nanosecond)

• 0: 64-bits format (48 bits nanosecond and 16 bits fractional nanoseconds).

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ToD Synchronizer Signals

Name

SYNC_MODE

PERIOD_NSEC

PERIOD_FNSEC

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Value

Between 0 and 6

Description

Value that defines types of synchronization.

The default value is 1.

• 0: Master clock frequency is 125MHz (1G) while slave is

156.25MHz (10G).

• 1: Master clock frequency is 156.25MHz (10G) while slave is

125MHz (1G).

• 2: Master and slave are same in the same frequency; can be in different ppm or phase. When you select this mode, specify the period of master and slave through the

PERIOD_

NSEC

and

PERIOD_FNSEC

parameters.

• 3: Master clock frequency is 156.25MHz (10G) while slave is

312.5MHz (10G).

• 4: Master clock frequency is 312.5MHz (10G) while slave is

156.25MHz (10G).

• 5: Master clock frequency is 125MHz (1G) while slave is

312.5MHz (10G).

• 6: Master clock frequency is 312.5MHz (10G) while slave is

125MHz (1G).

Between 0 and 4’hF A 4-bit value that defines the reset value for a nanosecond of period.

The default value is 4'h6 to capture 6.4ns for 156.25 MHz frequency. For 125 MHz frequency (1G), set this parameter to

4'h8.

Between 0 and

16’hFFFF

A 4-bit value that defines the reset value for a fractional nanosecond of period.

The default value is 16'h6666 to capture 0.4ns of 6.4ns for

156.25 MHz frequency. For 125 MHz frequency (1G), set this parameter to 16'h0.

ToD Synchronizer Signals

ToD Synchronizer Common Clock and Reset Signals

Table D-3: Clock and Reset Signals for the ToD Synchronizer

Signal

clk_master reset_master

Direction

Input

Input

1

1

Width Description

Clock from master ToD domain.

Reset signal that is synchronized to the master ToD clock domain.

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Signal

clk_slave reset_slave clk_sampling

Direction

Input

Input

1

1

Width

Input 1

ToD Synchronizer Interface Signals

D-5

Description

Clock from slave ToD domain.

Reset signal that is synchronized to the slave

ToD clock domain.

Sampling clock to measure the latency across the ToD Synchronizer.

ToD Synchronizer Interface Signals

Table D-4: Interface Signals for the ToD Synchronizer

Signal

start_tod_sync

Direction

Input 1

Width

tod_master_data tod_slave_valid tod_slave_data[n-1:0]

Input

Input

1

1

Description

Assert this signal to start the ToD synchroni‐ zation process. When this signal is asserted, the synchronization process continues and the time of day from the master ToD clock domain will be repeatedly synchronized with the slave ToD clock domain.

This signal carries the 64-bit or 96-bit format data for the time of day from the master ToD.

The width of this signal is determined by the

TOD_MODE

parameter.

This signal indicates that the tod_data_ slave

signal is valid and ready to be loaded into the slave ToD clock in the following cycle.

This signal will only be high for 1 cycle every time a new time of day is successfully synchronized to the slave clock domain.

This signal carries the 64-bit or 96-bit format synchronized time of day that is ready to be loaded into the slave clock domain. The width of this signal is determined by the

TOD_

MODE

parameter.

The synchronized time of day will be 1 slave clock period bigger than the master ToD because it takes 1 slave clock cycle to load this data into the slave ToD.

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The Packet Classifier decodes the packet types of incoming PTP packets and returns the decoded information aligned with SOP to the Triple-Speed Ethernet MAC with IEEE 1588v2 feature.

Packet Classifier Block

Figure E-1: Packet Classifier Block Diagram

Packet Classifier

Avalon-ST DataIn

(Sink)

Data Pipeline FIFO Packets

Ingress Control

Input Signals

FIFO Insert

Control

Decoding

FIFO Request

Control

Avalon-ST DataOut

(Source)

Control Signals to

Inserter

Timestamp Field

Location

Ingress Control

Output Signals

E

The components:

• Data Pipeline—holds the data frame up to a specified number of cycles. The number of cycles is determined by the largest length type field.

• FIFO Packets—holds the Avalon-ST frame data.

• FIFO Insert Control—the ingress control input bus that includes the signals required for decoding logics and signals to the MAC that is required to be aligned with SOP.

• FIFO Request Control—contains decoded data such as control signals to inserter and timestamp field locations.

• Decoding—Decodes packet types of incoming PTP packets and returns the decoded data to be stored in the FIFO request control block.

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Packet Classifier Signals

Packet Classifier Signals

Packet Classifier Common Clock and Reset Signals

Table E-1: Clock and Reset Signals for the Packet Classifier

clk reset

Signal Direction Width

Input 1

Input 1

Description

156.25-MHz register access reference clock.

Assert this signal to reset the clock.

Packet Classifier Avalon-ST Interface Signals

Table E-2: Avalon-ST DataIn Interface Signals for the Packet Classifier

Signal

data_sink_sop data_sink_eop data_sink_valid data_sink_ready data_sink_data data_sink_empty data_sink_error

Direction Width

Input

Input

Input 1

Output 1

1

1

Input

Input

Input

64

3

1

Description

The Avalon-ST input frames.

Table E-3: Avalon-ST DataOut (Source) Interface Signals for the Packet Classifier

Signal

data_src_sop data_src_eop data_src_valid data_src_ready data_src_data data_src_empty data_src_error

Direction Width

Input

Input

Input

Output 1

Input 64

Input

Input

3

1

1

1

1

Description

The Avalon-ST output frames.

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Packet Classifier Ingress Control Signals

Table E-4: Ingress Control Signals for the Packet Classifier

Packet Classifier Ingress Control Signals

Signal

tx_etstamp_ins_ctrl_in_ingress_ timestamp_96b

Direction Width

Input 96 tx_etstamp_ins_ctrl_in_ingress_ timestamp_64b tx_etstamp_ins_ctrl_out_ ingress_timestamp_96b tx_etstamp_ins_ctrl_out_ ingress_timestamp_64b tx_egress_timestamp_request_in_ valid tx_egress_timestamp_request_in_ fingerprint tx_egress_timestamp_request_ out_valid tx_egress_timestamp_request_ out_fingerprint clock mode

Input

Output

Output

Input

Input

Output

Output

Input

64

96

64

1

4

1

4

2

Description

96-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.

64-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.

96-bit format of ingress timestamp that holds data so that the output can align with the start of an outgoing packet.

64-bit format of ingress timestamp that holds data so that the output can align with the start of an outgoing packet.

Assert this signal when timestamp is required for the particular frame.

This signal must be aligned to the start of an incoming packet.

A width-configurable fingerprint that correlates timestamps for incoming packets.

Assert this signal when timestamp is required for the particular frame.

This signal must be aligned to the start of an outgoing packet.

A width-configurable fingerprint that correlates timestamps for outgoing packets.

Determines the clock mode.

• 00: Ordinary clock

• 01: Boundary clock

• 10: End-to-end transparent clock

• 11: Peer-to-peer transparent clock

E-3

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Packet Classifier Control Insert Signals

pkt_with_crc

Signal

tx_etstamp_ins_ctrl_in_ residence_time_update tx_etstamp_ins_ctrl_in_ residence_time_calc_format tx_etstamp_ins_ctrl_out_ residence_time_calc_format

Direction Width

Input 1

Input

Input

Output

1

1

1

Description

Indicates whether or not a packet contains CRC.

• 1: Packet contains CRC

• 0: Packet does not contain CRC

Indicates the update for residence time.

• 1: Allows update for residence time based on decoded results.

• 0: Prevents update for residence time. When this signal is deasserted, tx_etstamp_ins_ ctrl_out_residence_time_ update also gets deasserted.

Format of the timestamp to be used for calculating residence time. This signal must be aligned to the start of an incoming packet.

• 1: 64-bit timestamp format

• 0: 96-bit timestamp format

Format of the timestamp to be used for calculating residence time. This signal must be aligned to the start of an outgoing packet.

• 1: 64-bit timestamp format

• 0: 96-bit timestamp format

Packet Classifier Control Insert Signals

These signals must be aligned to the start of a packet.

Table E-5: Control Insert Signals for the Packet Classifier

Signal

tx_etstamp_ins_ctrl_out_ checksum_zero tx_etstamp_ins_ctrl_out_ checksum_correct tx_etstamp_ins_ctrl_out_ timestamp_format

Direction Width

Output 1

Output

Output

1

1

Description

Assert this signal to set the checksum field.

Assert this signal to correct the packet checksum by updating the checksum correction specified by tx_etstamp_ins_ctrl_out_ offset_checksum_correction

.

The timestamp format of the frame where the timestamp is inserted.

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Signal

tx_etstamp_ins_ctrl_out_ timestamp_insert tx_etstamp_ins_ctrl_out_ residence_time_update

Packet Classifier Timestamp Field Location Signals

Direction Width

Output 1

Output 1

Description

Assert this signal to insert timestamp into the associated frame.

Assert this signal to add the residence time into the correction field of the PTP frame.

Packet Classifier Timestamp Field Location Signals

These signals must be aligned to the start of a packet.

Table E-6: Timestamp Field Location Signals for the Packet Classifier

Signal

tx_etstamp_ins_ctrl_out_offset_ timestamp

Direction Width

Output 16 tx_etstamp_ins_ctrl_out_offset_ correction_field

Output 16 tx_etstamp_ins_ctrl_out_offset_ checksum_field

Output 16 tx_etstamp_ins_ctrl_out_offset_ checksum_correction

Output 16

Description

Indicates the location of the timestamp field.

Indicates the location of the correction field.

Indicates the location of the checksum field.

Indicates the location of the checksum corrector field.

E-5

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F

©

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

www.altera.com

101 Innovation Drive, San Jose, CA 95134

ISO

9001:2008

Registered

F-2

Triple-Speed Ethernet IP Core Document Revision History

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Triple-Speed Ethernet IP Core Document Revision History

Date

June 2015

Version

2015.06.15

Changes

• Added a new parameter, Use clock enable for MAC, in the Core

Configuration Parameters table.

• Added description for new signals— tx_clkena

, rx_clkena

, and led_panel_link

.

• Added Qsys-equivalent signal names for the following signals:

• control_port_clock_connection: clk

• pcs_mac_tx_clock_connection: tx_clk

• pcs_mac_rx_clock_connection: rx_clk

• receive_clock_connection: ff_rx_clk

• transmit_clock_connection: ff_tx_clk

• Revised the

Command_config

register field descriptions for bits 0, 1, and 13.

• Corrected the

Command_config

register setting for Enable MAC

Transmit and Receive Datapath register initialization sequence from 0x00802223 to 0x00800223.

• Corrected the bit width for pkt_class_data

signal in the following timing diagrams:

• Receive Operation—MAC Without Internal FIFO Buffers.

• Invalid Length Error During Receive Operation—MAC Without

Internal FIFO Buffers.

• Updated the following sections to indicate that the reconfiguration signals are not present in variations targeting Arria 10, Stratix V,

Arria V, and Cyclone V devices with GX transceivers.

• note in

Figure F-5

• SERDES control signals description in

Table F-27

.

• note in

Figure F-6

Sharing Transceiver Quads

on page 8-7

• Updated the description for Extended Statistics Counters (0x3C –

0x3E) to state the specific order for reading counters.

• Removed "10/100/1000-Mbps MAC with 1000BASE-X/SGMII PCS" configuration from the list of supported configurations in IEEE

1588v2 feature.

• Added a new topic -

Using ToD Clock SecondsH, SecondsL, and

NanoSec Registers

on page 14-6.

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Triple-Speed Ethernet IP Core Document Revision History

F-3

Changes

• Added a link to the Altera website that provides the latest device support information for Altera IP.

• Added a note in

PCS/Transceiver Options

on page 3-5—You must

configure the Arria 10 Transceiver ATX PLL output clock frequency to 1250.0 MHz when using the Arria 10 Transceiver

Native PHY with the Triple-Speed Ethernet IP core.

• Added

MAC Error Correction Code

on page 4-20 section.

• Added new support configuration for IEEE 1588v2 feature.

• Updated the tx_period

and rx_period

register bits in

IEEE

1588v2 Feature (Dword Offset 0xD0 – 0xD6)

on page 6-16.

• Updated the timing adjustment for the IEEE 1588v2 feature PMA delay in

IEEE 1588v2 Feature PMA Delay

on page 6-17.

• Revised the control interface signal names to reg_rd

, reg_data_in

, reg_wr

, reg_busy

, and reg_addr

in

MAC Control Interface

Signals

on page 7-3.

• Added ECC status signals in

ECC Status Signals

on page 7-12 and

ECC Status Signals

on page 7-21.

• Added Arria 10 Transceiver Native PHY signals in

Arria 10

Transceiver Native PHY Signals

on page 7-20.

• Added Transceiver Native PHY signal in

Transceiver Native PHY

Signal

on page 7-25.

• Updated the following the signal diagrams:

• 10/100/1000 Ethernet MAC Signals

• 1000BASE-X/SGMII PCS Function Signals

• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS

Signals

• 10/100/1000 Multiport Ethernet MAC Function without

Internal FIFO Buffers, with IEEE 1588v2, 1000BASE-X/SGMII

PCS and Embedded PMA Signals

• Added IEEE 1588v2 feature PHY path delay interface signals in

IEEE 1588v2 PHY Path Delay Interface Signals

on page 7-35.

• Updated the

Period

and

AdjustPeriod

register bits in

ToD Clock

Configuration Register Space

on page 14-5.

• Added two new conditions that the ToD synchronizer module supports in

ToD Synchronizer

chapter.

• Added three new recommended sampling clock frequencies in

ToD

Synchronizer

chapter.

• Added a new setting of 32/63 in

ToD Synchronizer Block

on page

15-2.

• Updated the

SYNC_MODE

parameter value and description in

ToD

Synchronizer Parameter Settings

on page 15-3.

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Triple-Speed Ethernet IP Core Document Revision History

Date

December

2013

13.1

Version Changes

• Added support for Arria 10 device.

• Added device family support list for IEEE 1588v2 variant.

• Updated the PCS/Transceiver options parameters in

PCS/

Transceiver Options

on page 3-5.

• Updated the bit order in

Table F-16

,

Table F-17

and

Table F-19

.

• Added information on how to view all the signal names when implementing the IP in Qsys in

Interface Signals

.

• Added a section about exposed ports in the new user interface in

Design Considerations

.

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Version

Triple-Speed Ethernet IP Core Document Revision History

F-5

Changes

• Updated the MegaWizard Plug-In Manager flow in

Getting Started with Altera IP Cores

.

• Added information about generating a design example and

simulation testbench in

Generating a Design Example or

Simulation Model

on page 2-2.

• Updated the list of Quartus II generated files.

• Added information about the recommended pin assignments in

Design Constraint File No Longer Generated

on page 2-4.

• Updated the MegaCore parameter names and description in

Parameter Settings

.

• Updated the IEEE 1588v2 feature list in

Functional Description

.

• Updated the SGMII auto-negotiation description in

Functional

Description

.

• Added information about the IEEE 1588v2 feature PMA delay in

IEEE 1588v2 Feature PMA Delay

on page 6-17.

• Updated the Multiport Ethernet MAC with IEEE 1588v2,

1000BASE-X/SGMII PCS and Embedded PMA Signals.

• Updated the IEEE 1588v2 timestamp signal names.

• Added timing diagrams for IEEE 1588v2 timestamp signals.

• Added a section about migrating existing design to the Quartus II software new MegaCore user interface in

Design Considerations

.

• Updated

Timing Constraints

chapter, to describe the new timing constraint files and the recommended clock input frequency for each MegaCore Function variant.

• Added information about the simulation model files generated

using IEEE simulation encryption in

Simulation Model Files

on

page 10-5.

• Updated the jumbo frames file directory in

Using Jumbo Frames

on page 11-4.

• Updated the ToD configuration parameters in

ToD Clock

Parameter Setting

on page 14-2 and ToD interface signals in

ToD

Clock Interface Signals

,

ToD Clock Avalon-ST Transmit

Interface Signals

on page 14-4 and

ToD Clock Avalon-MM

Control Interface Signals

on page 14-3.

• Added information to describe the ToD’s drift adjustment in

Adjusting ToD Clock Drift

on page 14-6.

• Added

ToD Synchronizer

and

Packet Classifier

chapters.

• Removed SOPC Builder information.

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Triple-Speed Ethernet IP Core Document Revision History

Date

January 2013 12.1

Version

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Changes

• Added Altera IEEE 1588v2 Feature section in Chapter 4.

• Added information for the following GUI parameters: Enable timestamping, Enable PTP 1-step clock, and Timestamp fingerprint width in “Timestamp Options”.

• Added MAC registers with IEEE 1588v2 feature.

• Added IEEE 1588v2 feature signals tables.

• Added Triple-Speed Ethernet with IEEE 1588v2 Design Example section.

• Added Time-of-Day Clock section.

June 2012 12.0

• Added support for Cyclone V.

• Updated the Congestion and Flow Control section in Chapter 4.

• Added Register Initialization section in Chapter 5.

• Added holdoff_quant

register description.

• Added

UNIDIRECTIONAL_ENABLE

bit description.

• Revised and moved the section on Timing Constraint to a new chapter.

• Added information about how to customize the SDC file in Chapter

8.

• Added Pause Frame Generation section.

November

2011

11.1

• Added support for Arria V.

• Revised the Device Family Support section in Chapter 1.

• Added disable_read_timeout

and read_timeout registers at address 0x15 and 0x16.

June 2011 11.0

• Updated support for Cyclone IV GX, Cyclone III LS, Aria II GZ,

HardCopy IV GX/E and HardCopy III E devices.

• Revised Performance and Resource Utilization section in Chapter 1.

• Updated Chapter 3 to include Qsys System Integration Tool Design

Flow.

• Added Transmit and Receive Latencies section in Chapter 4.

• Updated all MAC register address to dbyte addressing.

December

2010

10.1

• Added support for Arria II GZ.

• Added a new parameter, Starting Channel Number.

• Streamlined the contents and document organization.

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Version

November

2009

March 2009

November

2008

May 2008

9.1

9.0

8.1

8.0

October 2007 7.2

May 2007

March 2007

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7.0

Triple-Speed Ethernet IP Core Document Revision History

F-7

Changes

• Added support for Stratix V.

• Revised the nomenclature of device support types.

• Added chapter 5, Design Considerations. Moved the Clock

Distribution section to this chapter and renamed it to Optimizing

Clock Resources in Multiport MAC and PCS with Embedded PMA.

Added sections on PLL Sharing and Transceiver Quad Sharing.

• Updated the description of Enable transceiver dynamic reconfigura‐ tion.

• Added support for Cyclone IV, Hardcopy III, and Hardcopy IV, and updated support for Hardcopy II to full.

• Updated chapter 1 to include a feature comparison between 10/100/

1000 Ethernet MAC and small MAC.

• Updated chapter 4 to revise the 10/100/1000 Ethernet MAC description, Length checking, Reset, and Control Interface sections.

• Added support for Arria II GX.

• Updated chapter 3 to include a new parameter that enables wider statistics counters.

• Updated chapter 4 to reflect support for different speed in multiport

MACs and gated clocks elimination.

• Updated chapter 6 to reflect enhancements made on the device drivers.

• Updated Chapters 3 and 4 to add description on dynamic reconfi‐ guration.

• Updated Chapter 6 to include a procedure to add unsupported

PHYs.

• Revised the performance tables and device support.

• Updated Chapters 3 and 4 to include information on MAC with multi ports and without internal FIFOs.

• Revised the clock distribution section in Chapter 4.

• Reorganized Chapter 5 to remove redundant information and to include the new testbench architecture.

• Updated Chapter 6 to include new public APIs.

• Updated Chapter 1 to reflect new device support.

• Updated Chapters 3 and 4 to include information on Small MAC.

• Added Chapters 2, 3, 5 and 6.

• Updated contents to reflect changes and enhancements in the current version.

Updated signal names and description.

Altera Corporation

F-8

How to Contact Altera

Date

December

2006

6.1

Version

December

2006

6.1

How to Contact Altera

Table F-1: Altera Contact Information

Contact

(5)

Technical support

Technical training

Product literature

Nontechnical support

General

Software licensing

Related Information

www.altera.com/support

www.altera.com/training

www.altera.com/literature

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Changes

• Global terminology changes: 1000BASE-X PCS/SGMII to

1000BASE-X/SGMII PCS, host side or client side to internal system side, HD to half-duplex.

• Initial release of document on Web.

Initial release of document on DVD.

Contact Method

Website

Website

Email

Website

Email

Email

Address

www.altera.com/support www.altera.com/training [email protected]

www.altera.com/literature [email protected]

[email protected]

(5) You can also contact your local Altera sales office or sales representative.

Altera Corporation

Additional Information

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