Zilog Z80 CPU User’s Manual

2

Z80 CPU

User’s Manual

13

CPU and

System

Control

Signals

I n

Inst.

Register

CPU

Control

Data Bus

Control

Internal Data Bus

CPU

Registers

Address

Control

+5V GND CLK

Figure 1.

Z80 CPU Block Diagram

16-Bit

Address Bus

ALU

UM008003-1202 Overview

Z80 CPU

User’s Manual

7

System

Control

CPU

Control

CPU

Bus

Control

M1

MREQ

IORQ

RD

WR

RFSH

HALT

WAIT

INT

NMI

RESET

BUSRQ

BUSACK

CLK

+5V

GND

27

19

20

21

22

28

18

24

16

17

26

25

23

6

11

29

Z80 CPU

3

4

5

37

38

39

40

1

2

30

31

32

33

34

35

36

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

Address

Bus

14

15

12

8

10

13

7

9

D0

D1

D2

D3

D4

D5

D6

D7

Data

Bus

Figure 3.

Z80 I/O Pin Configuration

UM008003-1202 Overview

12

Z80 CPU

User’s Manual

T Cycle

CLK

T1 T2 T3

Machine Cycle

M1

(Opcode Fetch)

T1 T2 T3 T1 T2 T3

M2

(Memory Read)

Instruction Cycle

M3

(Memory Write)

Figure 4.

Basic CPU Timing Example

Instruction Fetch

Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is placed on the address bus at the beginning of the M1 cycle. One half clock cycle later the MREQ signal goes active. At this time the address to the memory has had time to stabilize so that the falling edge of MREQ can be used directly as a chip enable clock to dynamic memories. The RD line also goes active to indicate that the memory read data should be enabled onto the

CPU data bus. The CPU samples the data from the memory on the data bus with the rising edge of the clock of state T3 and this same edge is used by the CPU to turn off the RD and MREQ signals. Thus, the data has already been sampled by the CPU before the RD signal becomes inactive. Clock state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The

CPU uses this time to decode and execute the fetched instruction so that no other operation could be performed at this time.

During T3 and T4, the lower seven bits of the address bus contain a memory refresh address and the RFSH signal becomes active tindicating that a refresh read of all dynamic memories must be accomplished. An RD signal is not generated during refresh time to prevent data from different memory

UM008003-1202 Overview

Z80 CPU

User’s Manual

CLK

A

15

— A

0

MREQ

RD

WAIT

M1

D

7

— D

0

RFSH segments from being gated onto the data bus. The MREQ signal during refresh time should be used to perform a refresh read of all memory elements. The refresh signal can not be used by itself because the refresh address is only guaranteed to be stable during MREQ time.

M1 Cycle

T

1

T

2

T

3

T

4

T

1

PC

IN

Refresh Address

Figure 5.

Instruction Op Code Fetch

Memory Read Or Write

Figure 6 illustrates the timing of memory read or write cycles other than an

Op Code fetch cycle. These cycles are generally three clock periods long unless wait states are requested by the memory through the WAIT signal.

The MREQ signal and the RD signal are used the same as in the fetch cycle.

In a memory write cycle, the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memories. The WR line is active when data on the data bus is stable so that

UM008003-1202 Overview

13

14

Z80 CPU

User’s Manual

CLK

A

15

— A

0

MREQ it can be used directly as a R/W pulse to virtually any type of semiconductor memory. Furthermore, the WR signal goes inactive one-half T state before the address and data bus contents are changed so that the overlap requirements for almost any type of semiconductor memory type is met.

Memory Write Cycle

Memory Read Cycle

T

2

T

3

T

1

T

2

T

3

Memory Address Memory Address

RD

WR

D

7

— D

0

WAIT

In

Data Out

Figure 6.

Memory Read or Write Cycle

Input or Output Cycles

Figure 7 illustrates an I/O read or I/O write operation. During I/O operations a single wait state is automatically inserted. The reason is that during I/O operations, the time from when the IORQ signal goes active until the CPU must sample the WAIT line is very short. Without this extra state, sufficient time does not exist for an I/O port to decode its address and activate the

WAIT line if a wait is required. Also, without this wait state, it is difficult to design MOS I/O devices that can operate at full CPU speed. During this wait state time, the WAIT request signal is sampled.

During a read I/O operation, the RD line is used to enable the addressed port onto the data bus just as in the case of a memory read. For I/O write operations, the WR line is used as a clock to the I/O port.

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Z80 CPU

User’s Manual

15

T

1

T

2

TW* T

3

T

1

CLK

A

15

— A

0

IORQ

RD

D

7

— D

0

WAIT

Port Address

In

Read

Cycle

WR

D

7

— D

0

*Automatically inserted WAIT state

Figure 7.

Input or Output Cycles

Out

Write

Cycle

Bus Request/Acknowledge Cycle

Figure 8 illustrates the timing for a Bus Request/Acknowledge cycle. The

BUSREQ signal is sampled by the CPU with the rising edge of the last clock period of any machine cycle. If the BUSREQ signal is active, the CPU sets its address, data, and tristate control signals to the high-impedance state with the rising edge of the next clock pulse. At that time, any external device can control the buses to transfer data between memory and I/O devices. (This operation is generally known as Direct Memory Access [DMA] using cycle stealing.) The maximum time for the CPU to respond to a bus request is the length of a machine cycle and the external controller can maintain control of the bus for as many clock cycles as is required. If very long DMA cycles are used, and dynamic memories are used, the external controller also performs the refresh function. This situation only occurs if very large blocks of data

UM008003-1202 Overview

16

Z80 CPU

User’s Manual

are transferred under DMA control. During a bus request cycle, the CPU cannot be interrupted by either an NMI or an INT signal.

Any M Cycle Bus Available Status

Last T State

T

X

T

X

CLK

BUSREQ

BUSACK

A

15

— A

0

D

7

— D

0

MREQ, RD

WR. IORQ,

RFSH

Sample

Sample

Floating

Figure 8.

Bus Request/Acknowledge Cycle

T

X

T

1

Interrupt Request/Acknowledge Cycle

Figure 9 illustrates the timing associated with an interrupt cycle. The CPU samples the interrupt signal (INT) with the rising edge of the last clock at the end of any instruction. The signal is not accepted if the internal CPU software controlled interrupt enable flip-flop is not set or if the BUSREQ signal is active. When the signal is accepted, a special M1 cycle is generated. During this special M1 cycle, the IORQ signal becomes active

(instead of the normal MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. Two wait states are automatically added to this cycle. These states are added so that a ripple priority interrupt scheme can be easily implemented. The two wait states allow sufficient time for the ripple signals to stabilize and identify which

I/O device must insert the response vector. Refer to Chapter 6 for details on how the interrupt response vector is utilized by the CPU.

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Z80 CPU

User’s Manual

17

Last M Cycle of Instruction

M1

Last T State

T

1

T

2

T

W*

CLK

INT

A

15

— A

0

PC

M1

MREQ

IORQ

D

7

— D

0

WAIT

RD

Figure 9.

Interrupt Request/Acknowledge Cycle

T

W*

In

T

3

Refresh

Non-Maskable Interrupt Response

Figure 10 illustrates the request/acknowledge cycle for the non-maskable interrupt. This signal is sampled at the same time as the interrupt line, but this line takes priority over the normal interrupt and it can not be disabled under software control. Its usual function is to provide immediate response to important signals such as an impending power failure. The CPU response to a non-maskable interrupt is similar to a normal memory read operation.

The only difference is that the content of the data bus is ignored while the processor automatically stores the PC in the external stack and jumps to location

0066H

. The service routine for the non-maskable interrupt must begin at this location if this interrupt is used.

UM008003-1202 Overview

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Z80 CPU

User’s Manual

Last M Cycle

Last T State

T

1

T

2

M1

T

3

T

4

CLK

NMI

A

15

— A

0

M1

MREQ

RD

RFSH

PC Refresh

Figure 10. Non-Maskable Interrupt Request Operation

T

1

HALT Exit

Whenever a software HALT instruction is executed, the CPU executes

NOPs until an interrupt is received (either a non-maskable or a maskable interrupt while the interrupt flip-flop is enabled). The two interrupt lines are sampled with the rising clock edge during each T4 state as depicted in

Figure 11. If a non-maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable flip-flop is set, then the

HALT state is exited on the next rising clock edge. The following cycle is an interrupt acknowledge cycle corresponding to the type of interrupt that was received. If both are received at this time, then the non-maskable one is acknowledged since it has highest priority. The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active. Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data received from the memory is ignored and a NOP instruction is forced internally to the CPU. The HALT acknowledge signal is active during this time indicating that the processor is in the HALT state.

UM008003-1202 Overview

Main Register Set Alternate Register Set

Accumulator

A

B

D

H

Interrupt Vector

I

Index Register

Index Register

Stack Pointer

Program Counter

Flags

F

C

E

L

Accumulator

A '

B '

D '

H '

Memory Refresh

R

IX

IY

SP

PC

Special

Purpose

Registers

Flags

F '

B '

E '

L '

Figure 2.

Z80 CPU Register Configuration

General

Purpose

Registers

Z80 CPU

User’s Manual

3

UM008003-1202 Overview

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Z80 CPU

User’s Manual

Z80 Status Indicator Flags

The flag registers (F and F') supply information to the user about the status of the Z80 at any given time. The bit positions for each flag is listed below:

7

S

6

Z

5

X

4

N

3

X

2

P/V

1

N

0

C

Symbol Field Name

S

X

H

Z

C Carry Flag

N Add/Subtract

P/V Parity/Overflow Flag

Half Carry Flag

Zero Flag

Sign Flag

Not Used

Each of the two flag registers contains 6 bits of status information that are set or cleared by CPU operations. (Bits 3 and 5 are not used.) Four of these bits (C, P/V, Z, and S) may be tested for use with conditional

JUMP

,

CALL

, or

RETURN

instructions. Two flags may not be tested (H, N) and are used for BCD arithmetic.

Carry Flag

The Carry Flag (C) is set or cleared depending on the operation performed.

For

ADD

instructions that generate a Carry, and

SUB

instructions that generate a Borrow, the Carry Flag sets. The Carry Flag is reset by an

ADD instruction that does not generate a Carry, and by a

SUB

instruction that does not generate a Borrow. This saved Carry facilitates software routines

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User’s Manual

51

Table 2. 8-Bit Load Group LD t our

Destination

Register A

Reg

Indirect

B

C

D

E

H

L

(HL)

Source

I

Implied Register

ED

57

R A

ED

5F

7F

47

4F

57

5F

67

6F

77

Reg Indirect 11indexed

B C D E F L (HL)

78 79 7A 7B 7C 7D 7E 0A 1A FD

7E d

40 41 42 43 44 45 46 DD

46 d

48 49 4A 4B 4C 4D 4E

50 51 52 53 54 55 56

DD

4E d

DD

56 d

58 59 5A 5B 5C 5D 5E

60

68

61

69

62 63 64 65 66

6A 6B 6C 6D 6E

DD

5E d

DD

66 d

DD

6E d

70 71 72 73 74 75

FD

5E d

FD

66 d

FD

6E d

FD

4E d

FD

56 d

DD

7E d

FD

46 d

(BC)

(DE)

INDEXED (IX+d)

(IY+d)

EXT,

ADDR

(nn)

IMPLIED I

R

02

12

DD

77 d

DD

70 d

DD

71 d

DD

72 d

DD

73 d

DD

74 d

DD

75 d

FD

77 d

FD

70 d

FD

71 d

FD

72 d

FD

73 d

FD

74 d

FD

75 d

32 n n

ED

47

ED

4F

.

Ext Addr.

FD

3A nn d n

FD

36 d n

DD

36

Imme.

DD

2B n

DD

36 n

DD

1B n

DD

1E n

DD

78

D

DD

D5 n

DD

DE n n

FD

2E n

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User’s Manual

55

Register

Table 3. 16-Bit Load Group LD t our , PUSH op and POP op

AF

BC

DE

HL

SP

IX

IY

Register

AF BC DE HL SP IX

F9 DD

F9

EXT

ADDR.

(nn) n n

ED

43 n n

ED

53

22 n n n n

ED

73 n n

DD

22

PUSH

Instructions

®

REG.

IND.

(SP) F6 C6 D6 E6

NOTE: The Push & Pop instruction adjust the SP after every execution.

DD

E6

Source

n n

FD

22

FD

E6

Imm. Ext.

Ext. Addr.

Reg. Indir.

IY nn

FD

F9

01 n n

11 n n

21 n n

31 n n

DD

21 n n

FD

21 n n

(nn)

ED

4B n n n n

ED

5B n n

FD

2A n n

DD

2A

2A n n n n

ED

7B

(SP)

P1

C1

D1

E1

DD

E1

FD

E1

¦

POP

Instructions

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Z80 CPU

User’s Manual

Table 5. Block Transfer Group

Destination

Reg. Indir.

(DE)

Source

Reg. Indir.

(HL)

(ED)

A0

(ED)

B0

(ED)

A8

(ED)

B8

LDI - Load (DE)

® (HL)

Inc HL and DE, Dec BC

LDIR, - Load (DE)

®(HL)

Inc HL and DE, Dec BC, Repeat until BC = 0

LDD - Load (DE)

® (HL)

Inc HL and DE, Dec BC

LDDR - Load (DE)

® (HL)

Dec HL and DE, Dec BC, Repeat until BC = 0

Note:

Reg HL points to source

Reg DE points to destination

Reg BC is byte counter

Table 6. Block Search Group

Search

Location

Reg. Indir.

(HL)

(ED)

A1

(ED)

B1

(ED)

A9

(ED)

B9

CPI

Inc HL, Dec BC

CPRI. Inc HL, Dec BC

Repeat until) BC = 0 or find match

WD Dec HL and BC

CPDR Dec HL and BC

Repeat until BC = 0 or find match

Note: HL points to location in memory to be compared with accumulator contents

BC Is byte counter

UM008003-1202

Arithmetic and Logical

Table 7 lists all the 8-bit arithmetic operations that can be performed with the accumulator, also listed are the increment (

INC

) and decrement (

DEC

)

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User’s Manual

Five general-purpose arithmetic instructions operate on the accumulator or carry flag. These five are listed in Table 8. The decimal adjust instruction can adjust for subtraction as well as addition, making BCD arithmetic operations simple. Note that to allow for this operation the flag

N is used. This flag is set if the last arithmetic operation was a subtract.

The negate accumulator (

NEG

) instruction forms the two’s complement of the number in the accumulator. Finally, notice that a reset carry instruction is not included in the Z80 because this operation can be easily achieved through other instructions such as a logical AND of the accumulator with itself.

Table 9 lists all the 16-bit arithmetic operations between 16-bit registers.

There are five groups of instructions including add with carry and subtract with carry.

ADC

and

SBC

affect all the flags. These two groups simplify address calculation operations or other 16-bit arithmetic operations.

Table 7. 8-Bit Arithmetic and Logic

ADD

Source

Register Addressing Reg Indir.

A B C D E F L (HL)

87 80 81 82 83 84 85 88

ADD W CARRY

ADC

8F 88 89 8A 8B 8C 8D 8E

97 90 91 92 93 94 95 96 SUBTRACT

SUB

SUB w CARR

SBC

AND

9F 98 99 9A 9B 9C 9D 9E

A7 A0 A1 A2 A3 A4 A5 A6

XOR AF A8 A9 AA AB AC AD AE

Indexed

DD

9E d

DD

A6 d

DD

AE d

DD

8E d

DD

96 d

(IX+d)

DD

86 d

FD

9E d

FD

A6 d

FD

AE d

FD

8E d

FD

96 d

(lY+d)

FD

86 d

DE n

E6 n

EE n

CE n

D6 n

Immed.

n

C6 n

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User’s Manual

61

Table 7. 8-Bit Arithmetic and Logic

OR

Source

Register Addressing Reg Indir.

B7 B0 B1 B2 B3 B4 B5 B6

COMPARE

CP

INCREMENT

INC

DECREMENT

DEC

BF B8 B9 BA BB BC BD BE

3C 04 0C 14 1C 24 2C 34

3D 05 0D 15 1D 25 2D 35

Indexed

DD

34 d

DD

35 d

DD

B6 d

DD

BE d

FD

34 d

FD

35 d

FD

B6 d

FD

BE d

Table 8. General-Purpose AF Operation

Decimal Adjust Acc, DAA

Complement Acc, CPL

Negate Acc, NEG

(2’s complement

Complement Carry Flag, CCF

Set Carry Flag, SCF

27

2F

ED

44

3F

37

Immed.

F6 n

FE n

Table 9. 16-Bit Arithmetic

Source

BC DE HL SP IX IY

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62

Z80 CPU

User’s Manual

Table 9. 16-Bit Arithmetic

Destination

ADD

ADD with carry and set flags ADC

SUB with carry and set flags SBC

Increment INC

Decrement DEC

Source

HL 09

IX DD

09

IY FD

09

HL ED

4A

HL ED

42

03

19

DD

19

FD

19

ED

5A

ED

52

13

DB 1B

29

ED

6A

ED

62

23

2B

39

DD

39

FD

39

ED

7A

ED

72

33

DD

29

3B

FD

29

DD

23

DD

2B

FD

23

FD

2B

Rotate and Shift

A major feature of the Z80 is to rotate or shift data in the accumulator, any general-purpose register, or any memory location. All the rotate and shift

Op Codes are depicted in Figure 10. Also included in the Z80 are arithmetic and logical shift operations. These operations are useful in a wide range of applications including integer multiplication and division.

Two BCD digit rotate instructions (

RRD

and

RLD

) allow a digit in the accumulator to be rotated with the two digits in a memory location pointed to by register pair HL (See Figure 10). These instructions allow for efficient BCD arithmetic.

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User’s Manual

63

Table 10. Rotates and Shifts

Source

Type of

Rotate

Shift

A B C D E F L (HL) (IX+d) (lY+d)

RCL CB

07

RRC CB

0F

CB

00

CB

08

CB

01

CB

09

CB

02

CB

0A

CB

03

CB

06

CB

04

CB

0C

CB

06

CB

0E

CB

0D

CB

0E

DD

CB d

06

DD

CB d

0E

FD

CB d

06

FD

CB d

0E

RL CB

17

CB

10

CB

11

CB

12

CB

13

CB

14

CB

15

CB

16

RR

SLA

SRA

SRL

CB

1F

CB

27

CB

2F

CB

3F

CB

18

CB

20

CB

28

CB

38

CB

19

CB

21

CB

29

CB

39

CB

1A

CB

22

CB

2A

CB

3A

CB

1B

CB

23

CB

2B

CB

3B

CB

1C

CB

24

CB

2C

CB

3C

CB

1D

CB

25

CB

2D

CB

3D

CB

1E

CB

26

CB

2E

CB

3E

DD

CB d

26

DD

CB d

2E

DD

CB d

16

DD

CB d

1E

DD

CB d

3E

FD

CB d

2E

FD

CB d

26

FD

CB d

3E

FD

CB d

1E

FD

CB d

16

ED

6F

ED

67

A

RLCA D7

RRCA 0F

RLA 17

RRA 1F

CY b

7

CY

0

ACC b

0

Rotate

Left Circular

Rotate

Right Circular

Rotate

Left

Rotate

Right

Shift

Left Arithmetic

Shift

Right Arithmetic

Shift

Right Logical b

3

-b

0

ACC b

7

-b

4 b

3

-b

0

(HL)

Rotate

Digit

Left

(HL)

Rotate

Digit

Right

Bit Manipulation

The ability to set, reset, and test individual bits in a register or memory location is needed in almost every program. These bits may be flags in a general-purpose software routine, indications of external control

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Test

Bit

Table 11. Bit Manipulation Group (Continued)

0

Register Addressing

C8

47

C8

40

C8

41

C8

42

C8

43

C8

44

C8

45

1

2

3

4

5

6

7

C8

4F

C8

57

C8

5F

C8

67

C8

6F

C8

77

C8

7F

C8

48

C8

50

C8

58

C8

60

C8

68

C8

70

C8

78

C8

49

C8

51

C8

59

C8

61

C8

69

C8

71

C8

79

C8

4A

C8

52

C8

5A

C8

62

C8

6A

C8

72

C8

7A

C8

48

C8

53

C8

5B

C8

63

C8

68

C8

73

C8

78

C8

4C

C8

54

C8

5C

C8

64

C8

6C

C8

74

C8

7C

C8

4D

C8

55

C8

5D

C8

65

C8

6D

C8

75

CS

7D

Reg. Indir.

Indexed

C8

46

C8

4E

C8

56

C8

5E

C8

66

C8

6E

C8

76

C8

7E

C8 d

46

C8 d

76

DD

C8 d

6E

DD

C8 d

66

DD

C8 d

46

DD

C8 d

56

DD

C8 d

4E

DD

C8 d

46

DD

C8 d

46

C8 d

76

DD

C8 d

6E

FD

C8 d

66

FD

C8 d

46

FD

C8 d

56

FD

C8 d

4E

FD

C8 d

46

FD

UM008003-1202 Z80 CPU Instruction Description

Z80 CPU

User’s Manual

Rest

Bit

RES

Table 11. Bit Manipulation Group (Continued)

Register Addressing

0

1

2

3

4

5

6

7

C8

87

C8

8F

C8

97

C8

9F

C8

A7

C8

AF

C8

B7

C8

BF

C8

80

C8

88

C8

90

C8

98

C8

AO

C8

A8

C8

B0

C8

B8

C8

81

C8

89

CS

91

C8

99

C8

AI

C8

A9

C8

B1

C8

89

C8

82

C8

8A

C8

92

C8

9A

C8

A2

C8

AA

C8

82

C8

8A

C8

83

C8

88

C8

93

CS

98

C6

A3

08

AB

C8

B3

C8

B8

C8

84

C8

8C

C8

94

C8

90

C8

A4

C8

AC

C8

B4

C8

8C

C8

85

C8

8D

C8

95

C8

90

C8

A5

C8

AD

C8

B5

C8

BD

Reg. Indir.

Indexed

C8

86

C8

8E

C8

96

C8

9E

C8

A6

C8

AE

C8

B6

C8

9E

DD

C8 d

BE

DD

C8 d

B6

DD

C8 d

AE

DD

C8 d

A6

DD

C8 d

9E

DD

C8 d

96

DD

C8 d

8E

DD

C8 d

86

DD

C8 d

BE

FD

C8 d

B6

FD

C8 d

AE

FD

C8 d

A6

FD

C8 d

9E

FD

C8 d

96

FD

C8 d

8E

FD

C8 d

86

UM008003-1202 Z80 CPU Instruction Description

67

68

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User’s Manual

Set

Bit

SET

Table 11. Bit Manipulation Group (Continued)

Register Addressing

0

1

2

3

4

5

6

7

C8

C7

C8

CF

C8

D7

C8

DF

C8

E7

C8

EF

C8

F7

C8

FF

C8

C0

C8

C8

C8

DO

C8

D8

C8

E0

C8

E8

C8

FO

C8

F8

C8

C1

C8

C9

C8

D1

C8

09

C8

E1

C8

E9

C8

F1

C8

F9

C8

C2

C8

CA

C8

D2

C8

DA

C8

E2

C8

EA

C8

F2

C8

FA

C8

C3

C8

C8

C8

D3

C8

DS

C8

E3

C8

EB

C8

F3

C8

FB

C8

C4

C8

CC

C8

D4

C8

DC

C8

E4

C8

EC

C8

F4

C8

FC

C8

C5

C8

CD

C8

DS

C8

DD

C8

E5

C8

ED

C8

FS

C8

FD

Reg. Indir.

Indexed

C8

C6

C8

CE

C8

D6

C8

DE

C8

E6

C8

EE

C8

F6

C8

FE

DD

C8 d

FE

DD

C8 d

F6

DD

C8 d

EE

DD

C8 d

E6

DD

C8 d

DE

DD

C8 d

D6

DD

C8 d

CE

DD

C8 d

C6

FD

C8 d

FE

FD

C8 d

F6

FD

C8 d

EE

FD

C8 d

E6

FD

C8 d

DE

FD

C8 d

D6

FD

C8 d

CE

FD

C8 d

C6

UM008003-1202 Z80 CPU Instruction Description

Z80 CPU

User’s Manual

69

Table 12. Jump, Call, and Return Group

JUMP JP

JUMP JR

JUMP JP

CALL

IMMED.

EXT.

nn

RELATIVE PC+e 18 e-2

Register

INDIR.

(HL)

(IX)

EB

DD

E9

(IY)

IMMED.

EXT.

nn

FD

E9

CD n n

RELATIVE PC+e

Un-

Cond.

C3 n n

Decrement B, Jump

If Non Zero DJNZ

Return RE

Return From

INT RETI

Return From

Non Maskable

INT RETN

REGISTER

INDIR.

(SP)

(SP+1)

C9

ED

4D

ED

45

Condition

Carry Non

Carry

D8 n n

38 e-2

D2 n n

30 e-2

DC n n

D8

D4 n n

D0

Zero Non

Zero

CA n n

28 e-2

C2 n n

20 e-2

CC n n

C8

C4 n n

C0

Parity

Even

EA n n

Parity

Odd

E2 n n

Sign

Neg

FA n n

EC n n

E8

E4 n n

E0

FC n n

F8

Sign

Pos

F2 n n

Reg

B

¹0

F4 n n

F0

10 e-2

The instruction

DJNZ

is used to facilitate program loop control. This two byte, relative jump instruction decrements the B register and the jump occurs if the B register has not been decremented to zero. The relative displacement is expressed as a signed two’s complement number. A simple example of its use is:

Address

N, N+1

N+2 to N+9

N+10,N+11

N + 12

Instruction

LD B, 7

(Perform a sequence of instructions)

DJNZ -8

(Next Instruction)

Comments

: set B register to count of 7

: loop to be performed 7 times

: to jump from N+12 to N+2

UM008003-1202 Z80 CPU Instruction Description

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User’s Manual

UM008003-1202

Table 13 lists the eight Op Codes for the restart instruction. This instruction is a single byte call to any of the eight addresses listed. The simple mnemonic for these eight calls is also listed. This instruction is useful for frequently-used routines because memory consumption is minimized.

Table 13. Restart Group

CALL Address 0000H

0008H

0010H

0018H

0020H

0028H

0030H

0038H

Op

Code

E7

EF

F7

FF

C7

CF

D7

DF

RST 0

RST 8

RST 16

RST 24

RST 32

RST 40

RST 48

RST 56

Input/Output

The Z80 has an extensive set of input and output instructions as shown in

Table 14 and Table 15. The addressing of the input or output device can be either absolute or register indirect, using the C register. In the register indirect addressing mode, data can be transferred between the I/O devices and any of the internal registers. In addition, eight block transfer instructions have been implemented. These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to the memory source (output commands) or destination (input commands) while register B is used as a byte counter. Register C holds the address of the port for which the input or output command is required.

Because register B is eight bits in length, the I/O block transfer command handles up to 256 bytes.

In the instructions

IN A

, and

OUT n

,

A

, the I/O device address n appears in the lower half of the address bus (A7-A0) while the accumulator content

Z80 CPU Instruction Description

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Z80 CPU

User’s Manual

Table 14. Input Group

Input

Destination

Input IN

INI - input & inc HL, Dec B

INIR - INP, Inc HL,

Dec B, repeat IF B

¹0

IND - input & Inc

Dec HL, Dec B

INDR - input, Dec HL,

Dec B, repeat IF B

¹0

Register

Address

Register

Indir

E

H

L

(HL)

C

D

A

B

Immed.

(n)

DB n

ED

68

ED

A2

ED

58

ED

60

ED

48

ED

50

ED

7B

ED

40

ED

B2

ED

AA

ED

BA

Register

Indir.

(c)

Block

Input

Commands

UM008003-1202 Z80 CPU Instruction Description

Z80 CPU

User’s Manual

73

Table 15.

Output group

Source

OUT

OUT - output inc HL, dec B

OUT - output dec B, repeat if B ¹0

OUT - output dec HL and B

OUTDR - output, dec HL and B, repeat IF B ¹0

A B

Immed.

(n) D3 n

Reg

Ind.

(c) ED

79

ED

41

C D E

ED

49

ED

51

H

ED

59

ED

61

L

ED

69

(HL)

ED

AB

ED

BB

ED

A3

ED

B3

Port

Destination

Address

Table 16. Miscellaneous CPU Control

NOP

HALT

Disable INT (EI)

Enable INT (EI)

Set INT mode 0

IM0

Set INT mode 1

IM1

Set INT mode 2

IM2

ED

46

ED

56

ED

5E

00

76

F3

FB

8080A mode

Call to location 0038H indirect call using register I and B bits from INTER device as a pointer

Block

Output

Command

UM008003-1202 Z80 CPU Instruction Description