Marvell - Storage - 88SE9345 Datasheet

88SE9345 R3.3
Four-Lane PCIe 2.0 to Four-Port
SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Doc No. MV-S109418-00 Rev. A
April 21, 2015
Document Classification: Proprietary
Marvell. Moving Forward Faster
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
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ii
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Ordering Information
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SE9345 part. For complete
ordering information, contact your Marvell FAE or sales representative.
Sample Ordering Part Number
88XXXXX - XX - XXX - C000 - XXXX
Part Number
Custom Code
(optional )
Extended Part Number
Custom Code
Product Revision
Temperature Code
C = Commercial
I = Industrial
Custom Code
Package Code
Environmental Code
3-character
alphabetic code
such as BCC, TEH
+ = RoHS 0/6
– = RoHS 5/6
1 = RoHS 6/6
2 = Green)
The standard ordering part numbers for the respective solutions are indicated in the following table.
Ordering Part Numbers
Part Number
88SE9345C3-BMJ2C000
Description
481-Ball TFBGA 19 × 19 mm
This product does not support Marvell RAID stack.
The next figure shows a typical Marvell package marking.
88SE9345 Package Marking and Pin 1 Location
Marvell Logo
Country of origin
(contained in the mold ID or
marked as the last line on
the package)
Pin 1 location
88XXXXX-AAAe
Lot Number
YYWW xx@
Country of Origin
Part number, package code, environmental code e
XXXXX = Part number
AAA = Package code
e = Environmental code
(+ = RoHS 0/6, no code = RoHS 5/6,
1 = RoHS 6/6, 2 = Green)
Date code, custom code, assembly plant code
YYWW = Date code (YY = year, WW = Work Week)
xx = Custom code or die revision
@ = Assembly plant code
iii
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
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iv
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Change History
CHANGE HISTORY
The following table identifies the document change history for Rev. A.
Document Changes *
Location
Type
Description
Date
Page 1-1
Update
Updated the description for chapter 1, Overview:
December 8, 2014
from
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a
one- or four-lane PCIe 2.0 host interface, and supports advanced RAID
topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does not
support the Marvell RAID stack.
to
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a
one-, two-, or four-lane PCIe 2.0 host interface, and supports advanced
RAID topologies. The 88SE9xx5 is similar to the 88SE9xx0, but does
not support the Marvell RAID stack.
Page 2-2
Update
Updated the description for section 2.1, General.
December 5, 2014
Page 3-5
Update
Updated Table 3-1, Signal Type Definitions.
December 8, 2014
Page 3-8
Update
Updated the description for PIN_TEST[9:8] in Table 3-2, General
Purpose I/O Signals:
January 14, 2015
from
PIN_TEST[9:8]–PCIe maximum lane width
0h:
1h:
2h:
3h:
to
x8
x1
x4
x8
PIN_TEST[9:8]–PCIe maximum lane width
0h:
x8
Note: Always use 0h.
Page 4-2
Update
Added notes for the following schematics in section 4.1, 88SE9345
Board Schematics:
•
•
•
•
June 27, 2014
88SE9345 Example Board Schematic (1 of 4)
88SE9345 Example Board Schematic (2 of 4)
88SE9345 Example Board Schematic (3 of 4)
88SE9345 Example Board Schematic (4 of 4)
v
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Document Changes * (continued)
Location
Type
Description
Date
Page 5-4
Parameter Updated Table 5-3, DC Electrical Characteristics:
December 18, 2014
•
•
•
•
•
Updated Analog Power for PCIe PHY 1.8V.
Updated Analog Power for SATA PHY 2.5V, Chip PLL.
Updated Digital Core Power.
Updated Digital I/O Power.
Corrected the Maximum value of Input Low Voltage of Digital I/O from
0.8 to 0.3 × VDDOx.
• Corrected the Minimum value of Input High Voltage of Digital I/O from
2.0 to 0.7 × VDDOx.
• Corrected the Maximum value of Input High Voltage of Digital I/O
from 3.6 to VDDOx + 0.4.
• Corrected the Typical value of Output High Voltage of Digital I/O from
VDDO1/VDDO2 to VDDOx.
Page 5-5
Update
December 4, 2014
Updated the description for section 5.4, Thermal Data:
from
Table 5-5 shows the values for the package thermal parameters for the
484-pin TFBGA mounted on a 4-layer PCB.
to
Table 5-5 shows the values for the package thermal parameters for the
481-ball TFBGA mounted on a 4-layer PCB.
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision
change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
vi
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Contents
CONTENTS
1
OVERVIEW ........................................................................................................................................................ 1-1
2
FEATURES ........................................................................................................................................................
2.1
GENERAL ..................................................................................................................................................
2.2
PCIE .........................................................................................................................................................
2.3
SATA ......................................................................................................................................................
2.4
XOR ENGINE ............................................................................................................................................
2.5
PERIPHERALS ............................................................................................................................................
2-1
2-2
2-3
2-4
2-5
2-6
3
PACKAGE .........................................................................................................................................................
3.1
BALL DIAGRAM ..........................................................................................................................................
3.2
MECHANICAL DIMENSIONS .........................................................................................................................
3.3
SIGNAL DESCRIPTIONS ...............................................................................................................................
3.3.1
Signal Definitions ......................................................................................................................
3.3.2
Signal Descriptions ...................................................................................................................
3-1
3-2
3-3
3-5
3-5
3-6
4
LAYOUT GUIDELINES ...................................................................................................................................... 4-1
4.1
88SE9345 BOARD SCHEMATICS ................................................................................................................ 4-2
4.2
LAYER STACK-UP ...................................................................................................................................... 4-7
4.2.1
Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes ................... 4-7
4.2.2
Layer 2–Solid Ground Plane ..................................................................................................... 4-7
4.2.3
Layer 3–Power Plane and Low Speed Signals ......................................................................... 4-7
4.2.4
Layer 4–Power Plane ................................................................................................................ 4-7
4.2.5
Layer 5–Solid Ground Plane ..................................................................................................... 4-7
4.2.6
Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes .................... 4-8
4.3
POWER SUPPLY ........................................................................................................................................ 4-9
4.3.1
VDD Power (1.0V) ..................................................................................................................... 4-9
4.3.2
PCIe Analog Power Supply (1.8V) ............................................................................................ 4-9
4.3.3
SATA Analog Power Supply (2.5V) ........................................................................................... 4-9
4.3.4
General I/O Power (3.3V) .......................................................................................................... 4-9
4.3.5
Bias Current Resistor (RSET) ................................................................................................. 4-10
4.4
PCB TRACE ROUTING ............................................................................................................................. 4-11
4.5
RECOMMENDED LAYOUT .......................................................................................................................... 4-12
5
ELECTRICAL SPECIFICATIONS ......................................................................................................................
5.1
ABSOLUTE MAXIMUM RATINGS ..................................................................................................................
5.2
RECOMMENDED OPERATING CONDITIONS ...................................................................................................
5.3
DC ELECTRICAL CHARACTERISTICS ...........................................................................................................
5.4
THERMAL DATA .........................................................................................................................................
5.5
AC TIMING ................................................................................................................................................
5.5.1
SATA .........................................................................................................................................
5.5.2
PCIe ..........................................................................................................................................
5.5.3
Parallel Flash and NVSRAM .....................................................................................................
5-1
5-2
5-3
5-4
5-5
5-6
5-6
5-6
5-6
vii
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
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viii
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Overview
1
OVERVIEW
The 88SE9345 is a four-port, 6.0 Gbps SATA controller that provides a one-, two-, or
four-lane PCIe 2.0 host interface, and supports advanced RAID topologies. The 88SE9xx5
is similar to the 88SE9xx0, but does not support the Marvell RAID stack.
The 88SE9345 controller brings a high-performance, low-cost 6.0 Gbps per port SATA
solution to HBA, workstation, and server designs utilizing a one- or four-lane PCIe 2.0
interface. The 88SE9345 integrates four high-performance SATA PHYs and a
self-configuring four-lane PCIe core. Each of the four PHYs is capable of 1.5 Gbps, 3.0 Gbps,
and 6.0 Gbps SATA link rates. The controller supports the SATA protocol defined in the
Serial ATA, Revision 3.0 Specification.
Figure 1-1 shows the system block diagram.
Figure 1-1 88SE9345 (4-Port SATA) Block
Config, Interrupts ,
and Timers
GPPs, UART, and
TWSI
XOR
x2
AHB Bus
Comm
PBSRAM
MXI Bus
FLASH
NVSRAM
PCIExpress
x4
SATA
x4
1-1
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April 21, 2015
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Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
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1-2
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
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Part 1: Chip Overview
Features
2
FEATURES
The chapter contains the following sections:

General

PCIe

SATA

XOR Engine

Peripherals
2-1
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
2.1
General

Four SATA ports.

Choice of x1, x2, or x4 lane PCIe 2.0 host interface.

Supports three Serial Device Bus (I2C) controllers for communicating with hardware
monitoring ICs.

Supports two industry standard 57600 UARTs.

Supports two SFF-8485 compliant SGPIO ports.

Up to 2048 concurrent I/O operations.

Up to 64 concurrent SATA Devices.

No hardware limit on the number of SAS devices supported.

55 nm CMOS process, 1.0V digital core, 2.5V analog power supply, and 3.3V I/O supply.

Estimated power (4-port):

Minimum = 3.0W

Typical = 3.93W

Maximum = 5.7W

Up to 34 LED/GPIO ports.

Supports hardware RAID 5 and RAID 6 acceleration.

Supports Data Path Parity Protection (DPP).
2-2
Copyright © 2015 Marvell
April 21, 2015
General
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Document Classification: Proprietary
Part 1: Chip Overview
Features
2.2
PCIe

Supports x1, x2, or x4 lane PCIe 2.0 Interface (5.0 Gbps).

Supports four fully independent PCIe functions.

Supports independent interrupt mechanisms for each PCIe function.

Supports Message Signal Interrupts (MSI).

All registers memory mapped.

Supports PCIe Power Management: D0, D1, D3COLD, D3HOT.
PCIe
Copyright © 2015 Marvell
April 21, 2015
2-3
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
2.3
SATA

Serial ATA Revision 3.0 (6 Gbps) compliant, with speed negotiation to 3.0 Gbps and
1.5 Gbps.

Supports programmable SATA signaling levels, including Gen1x, Gen2i, and Gen2x.

Supports ATA and ATAPI commands.

Supports Native Command Queuing (NCQ).


Non-zero offset and non-sequential data delivery.

32 outstanding commands per device.
Supports Port Multiplier.

FIS based Switching on NCQ and legacy commands.

Supports Host mode and Device mode of operation.

Supports hardware assisted Scatter-Gather.
2-4
Copyright © 2015 Marvell
April 21, 2015
SATA
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Part 1: Chip Overview
Features
2.4
XOR Engine

Supports Advanced RAID features including:

Dual XOR RAID 6.

P + Q + Copy, or Q + Q + Q RAID 6.

Memory Block Fill.

Zero Result Check.

Generates up to 3 checksums concurrently, including any combination of P and Q.

Independent GF Multiply coefficient for each of 3 concurrent Q checksum calculations.

Supports rebuilding three failed drives simultaneously with a single read of remaining good
drives.

Supports chained XOR Descriptor Tables, with up to 32 operations in each table.

Supports Scatter-Gather transfers using a common PRD format.

Supports CRC32 checksum generation and checking.
XOR Engine
Copyright © 2015 Marvell
April 21, 2015
2-5
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Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
2.5
Peripherals

Supports up to 4 MB of external NVSRAM memory (x8/x16).

Supports up to 4 MB of external PBSRAM memory (x32).

Supports up to 8 MB of external Parallel Flash memory (x8/x16).

Supports up to 16 MB of external SPI Flash memory.
2-6
Copyright © 2015 Marvell
April 21, 2015
Peripherals
Doc No. MV-S109418-00 Rev. A
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Part 1: Chip Overview
Package
3
PACKAGE
This chapter contains the following sections:

Ball Diagram

Mechanical Dimensions

Signal Descriptions
3-1
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
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April 21, 2015
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S
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S
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2]
3]
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[1
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[2
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PI
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03]
VA
VA
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]
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P
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D N_P AD N_P A N_
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D N _ P D A N_ P DA _ P D N _ P
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[7 TA _ [4 TA
[
A
3
2
]
]
]
]
PI
P
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P
N
D N_P D I N_ D I N_
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[1 A [1 TA _[1 TA _ [ TA _
3]
6]
1]
2]
PI
PI
P
PI
N
D N_P D IN_
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AT _ A P DA _P
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4]
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]
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[0
PI
]
PI ]
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[6 DR _ 1_ P_ _N _W
]
[2
N
PI
]
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S
[2 DR _
S
0]
PI
PI
N
N
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VS
_
XN
[0 RX
S
P
]
[0
]
PI
N
VS
_T
VS
[0 X
S
S
] N
PI
PI
N
N
VS
_
_
[1 RX [1 RX
S
P
]
] N
PI
N
VS
VS
_
[1 TX
S
S
] N
PI
PI
N
N
_
_R
VS
[2 RX
S
P [2] XN
]
PI
N
_T
VS
VS
[2 X
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$
S
3.1
VS
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Ball Diagram
The 481-pin TFBGA ball diagram is illustrated in Figure 3-1.
Figure 3-1 Ball Diagram
'
(
)
*
+
-
.
/
0
1
3
5
7
8
:
<
$$
$%
$&
Ball Diagram
Doc No. MV-S109418-00 Rev. A
Part 1: Chip Overview
Package
3.2
Mechanical Dimensions
The package mechanical drawing is shown in Figure 3-2 and the mechanical dimensions are
shown in Figure 3-2.
Figure 3-2 Package Mechanical Drawing (BMJ)
Mechanical Dimensions
Copyright © 2015 Marvell
April 21, 2015
3-3
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Figure 3-3 Package Mechanical Dimensions (BMJ)
3-4
Copyright © 2015 Marvell
April 21, 2015
Mechanical Dimensions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Package
3.3
Signal Descriptions
This section includes information on signal definitions and descriptions:
3.3.1

Signal Definitions

Signal Descriptions
Signal Definitions
Signal type definitions are shown in Table 3-1.
Table 3-1 Signal Type Definitions
Signal Type Definition
I/O
Input and output
I
Input only
O
Output only
OC
Open Collector
OD
Open-Drain pad
Ground
Ground
Power
Power
NC
No Connect*
DNC
Do Not Connect†
N/A
Not Applicable
* Pin is floating and is not connected
internally to any active circuitry nor has
any electrical continuity to any other
pin
† Device pin to which there may or may
not be an internal connection, but to
which no external connections are
allowed.
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
3.3.2
Signal Descriptions
This section outlines the 88SE9345 signal descriptions. Signals ending with the letter “N”
are active-low signals.
Table 3-2 General Purpose I/O Signals
Signal Name
Signal
Number
Type
Description
PIN_ACT[8]
L21
I/O, OC
Activity LED.
PIN_ACT[7]
M22
Active low.
PIN_ACT[6]
M23
PIN_ACT[5]
N23
PIN_ACT is active when SATA PHY is transmitting or
receiving.
PIN_ACT[4]
N22
These pins can be used as GPIO.
PIN_ACT[3]
M21
PIN_ACT[3:0]–SATA PHY[3:0] activity.
PIN_ACT[2]
P23
PIN_ACT[7:4]—Not used.
PIN_ACT[1]
P22
PIN_ACT[8]–Global Activity. Enabled when any SATA
PIN_ACT[0]
N21
PHY is active.
3-6
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
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Part 1: Chip Overview
Package
Table 3-2 General Purpose I/O Signals (continued)
Signal Name
Signal
Number
Type
Description
PIN_FLT[8]
H23
I/O, OC
Fault LED.
PIN_FLT[7]
J21
Active low signals.
PIN_FLT[6]
J22
PIN_FLT[5]
J23
PIN_FLT[4]
K21
PIN_FLT is active when PHY is not ready or when PHY
is ready and there is any PHY related error or
connection error.
PIN_FLT[3]
K22
PIN_FLT[2]
K23
These pins can be used as GPIO, SGPIO, I2C, or
FLT_LED. See GPIO_FLT_CFG (R10080h [7:0]) and
I2C_SGPIO_FLT_PAD_SEL (R10104h [9:8]).
PIN_FLT[1]
L22
Pins used as Fault LED:
PIN_FLT[0]
L23
• PIN_FLT[8]: Global Fault indication. The indicator is
on when any SATA_PHY has a fault.
• PIN_FLT[3:0] corresponds to SATA_PHY3 through
PHY0.
Note: When PHY is not ready, PIN_FLT[7:0] is always on.
After the PHY is ready, a fault occurs.
Pins used as SGPIO:
• PIN_FLT[8]: Same as FLT mode.
• PIN_FLT[7:4]: SGPIO1 SCLK, SLOAD, SDOUT,
SDIN
• PIN_FLT[3:0]: SGPIO0
SCLK,SLOAD,SDOUT,SDIN
Used as I2C:
•
•
•
•
•
PIN_FLT[8]: Same as FLT Mode
PIN_FLT[7:6]: I2C2 CLK, DATA
PIN_FLT[5:4]: Not used
PIN_FLT[3:2]: I2C1 CLK, DATA
PIN_FLT[1:0]: Not used
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Table 3-2 General Purpose I/O Signals (continued)
Signal Name
Signal
Number
Type
Description
PIN_TEST[15]
C22
I/O
Configuration and test pins.
PIN_TEST[14]
D22
These pins can be used as GPIO.
PIN_TEST[13]
B23
PIN_TEST[15]-PCIe power-up disable
PIN_TEST[12]
E21
PIN_TEST[11]
E22
PIN_TEST[10]
C23
PIN_TEST[9]
E23
0h: Enable PCIe after power-up
1h: Disable PCIe after power-up
Not applicable to this chip. This signal needs
pull-down.
PIN_TEST[8]
D23
PIN_TEST[7]
F22
PIN_TEST[6]
F21
PIN_TEST[5]
G21
0h:
1h:
2h:
3h:
PIN_TEST[4]
F23
PIN_TEST[12:11]–Reserved
PIN_TEST[3]
G22
PIN_TEST[10]–PCIe ROM location
PIN_TEST[2]
H21
PIN_TEST[1]
G23
0h:
1h:
PIN_TEST[0]
H22
PIN_TEST[14:13]–Chip reference clock selection
20 MHz
50 MHz
100 MHz
75 MHz
Parallel Flash
Serial Flash
PIN_TEST[9:8]–PCIe maximum lane width
0h:
x8
Always use 0h.PIN_TEST[7:6]–Reserved
PIN_TEST[5]—PCIe configuration access enable.
0h:
1h:
PCIe responds to configuration access.
PCIe returns a retry configuration access.
Not applicable to this chip. This signal needs pull-down.
PIN_TEST[4]–Parallel Flash x8/x16
0h:
1h:
Byte mode
Word mode
PIN_TEST[3:2]–Reserved
PIN_TEST[1]–UART baudrate
0h:
1h:
57600
Reserved
PIN_TEST[0]–UART mode
0h:
1h:
Reserved
Terminal mode
Table 3-3 Clock and Reset Signals
Signal Name
Signal
Type
Number
Description
PIN_REFCLK
AB22
Reference clock input.
I
2.5V, ± 350 ppm.
PIN_RESET_N
V21
I
Power-on reset.
3-8
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
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Part 1: Chip Overview
Package
Table 3-3 Clock and Reset Signals (continued)
Signal Name
Signal
Type
Number
Description
PIN_PRESET_N
AA22
I
PCIe Reset
PIN_TP
AC22
O
SATA analog test port.
Table 3-4 I2C Signals
Signal Name
Signal
Type
Number
PIN_SCL[2]
R23
PIN_SCL[1]
R22
PIN_SCL[0]
P21
PIN_SDA[2]
T23
PIN_SDA[1]
T22
PIN_SDA[0]
R21
Description
I/O, OC I2C clock.
I/O, OC I2C data.
Table 3-5 UART Signals
Signal Name
Signal
Type
Number
Description
PIN_UAI[1]
U23
I
UART input.
PIN_UAI[0]
U22
PIN_UAO[1]
V23
O
UART output.
PIN_UAO[0]
T21
.
Table 3-6 Parallel Flash Signals
Signal Name
Signal
Type
Number
Description
PIN_F_BYTE_N
B3
O
Parallel flash Byte mode.
PIN_F_CE_N
E4
O
Parallel flash chip select.
PIN_F_OE_N
F4
O
Parallel flash output enable.
PIN_F_READY
D3
I
Parallel flash ready signal.
Requires external pull-up resistor.
PIN_F_RESET_N
C3
O
Parallel flash reset.
PIN_F_WE_N
A3
O
Parallel flash write enable.
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
3-9
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Table 3-6 Parallel Flash Signals (continued)
Signal Name
Signal
Type
Number
PIN_P_ADDR[21]
AC5
PIN_P_ADDR[20]
AB5
Shared address bus for parallel flash, NVSRAM and
PBSRAM.
PIN_P_ADDR[19]
J1
For Parallel Flash, signals are word addresses.
PIN_P_ADDR[18]
K1
For NVSRAM, signals are WORD addresses.
PIN_P_ADDR[17]
M3
For PBSRAM, signals are Dword addresses.
PIN_P_ADDR[16]
N2
PIN_P_ADDR[15]
N1
PIN_P_ADDR[14]
N3
PIN_P_ADDR[13]
M2
PIN_P_ADDR[12]
M1
PIN_P_ADDR[11]
L2
PIN_P_ADDR[10]
L1
PIN_P_ADDR[9]
AA1
PIN_P_ADDR[8]
AB1
PIN_P_ADDR[7]
AC4
PIN_P_ADDR[6]
AB4
PIN_P_ADDR[5]
K3
PIN_P_ADDR[4]
L3
PIN_P_ADDR[3]
F1
PIN_P_ADDR[2]
G1
PIN_P_ADDR[1]]
H1
PIN_P_ADDR[0]
K2
O
Description
3-10
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Package
Table 3-6 Parallel Flash Signals (continued)
Signal Name
Signal
Type
Number
PIN_P_DATA[35]
J2
PIN_P_DATA[34]
F3
For Parallel Flash, DATA[15:0] are used.
PIN_P_DATA[33]
Y2
PIN_P_DATA[32]
P1
In Byte mode, DATA[15] is address bit 0. DATA[7:0] are
data.
PIN_P_DATA[31]
E1
In Word mode, DATA[15:0] are data.
PIN_P_DATA[30]
D1
For NVSRAM, DATA[15:0] are used.
PIN_P_DATA[29]
C1
For PBSRAM, DATA[35:0] are used.
PIN_P_DATA[28]
J3
DATA[35] is parity for Byte 3.
PIN_P_DATA[27]
E2
DATA[34] is parity for Byte 2.
PIN_P_DATA[26]
B1
DATA[33] is parity for Byte 1.
PIN_P_DATA[25]
C2
DATA[32] is parity for Byte 0.
PIN_P_DATA[24]
D2
PIN_P_DATA[23]
H2
PIN_P_DATA[22]
H3
PIN_P_DATA[21]
G2
PIN_P_DATA[20]
A2
PIN_P_DATA[19]
B2
PIN_P_DATA[18]
E3
PIN_P_DATA[17]
F2
PIN_P_DATA[16]
G3
PIN_P_DATA[15]
W2
PIN_P_DATA[14]
U3
PIN_P_DATA[13]
V2
PIN_P_DATA[12]
T2
PIN_P_DATA[11]
U2
PIN_P_DATA[10]
T3
PIN_P_DATA[9]
Y1
PIN_P_DATA[8]
W1
PIN_P_DATA[7]
V1
PIN_P_DATA[6]
R2
PIN_P_DATA[5]
R3
PIN_P_DATA[4]
U1
PIN_P_DATA[3]
T1
PIN_P_DATA[2]
R1
PIN_P_DATA[1]]
P3
PIN_P_DATA[0]
P2
I/O
Description
Shared Data Bus for Parallel Flash/NVSRAM/PBSRAM.
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
3-11
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88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Table 3-7 NVSRAM Signals
Signal Name
Signal
Type
Number
Description
PIN_N_CE_N
C4
O
nvSRAM chip select.
PIN_N_OE_N
G4
O
nvSRAM output enable.
PIN_N_WE_N
D4
O
nvSRAM write enable.
Table 3-8 PBSRAM Signals
Signal Name
Signal
Type
Number
Description
PIN_P_ADSC_N
AB2
O
PBSRAM ASDC mode.
PIN_P_ADV_N
AA2
O
PBSRAM address advance.
PIN_P_BW_N
AC2
O
PBSRAM BW.
PIN_P_CS1_N
AA4
O
PBSRAM chip select.
PIN_P_GW_N
V3
O
PBSRAM global write enable.
PIN_P_OE_N
AC3
O
PBSRAM output enable.
PIN_P_OUT_CLK
AB3
O
PBSRAM clock.
PIN_P_WE_N[3]
AA3
O
PBSRAM write enable.
PIN_P_WE_N[2]
Y4
PIN_P_WE_N[1]
W3
PIN_P_WE_N[0]
Y3
Table 3-9 System Interface Signals
Signal Name
Signal
Type
Number
PIN_CNFG[1]
W22
PIN_CNFG[0]
Y22
REFCLKP
A13
I
Description
Configuration.
00: Normal Functional mode.
Others:Test Mode.
I
PCIe reference clock input.
100MHz ± 300ppm.No internal clock termination.
REFCLKN
B13
I
PCIe reference clock input.
100MHz ± 300ppm.No internal clock termination.
3-12
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Package
Table 3-10 SPI Interface Signals
Signal Name
Signal
Type
Number
Description
PIN_SPI_DI
V22
I
SPI data input.
PIN_SPI_CLK
Y23
O
SPI clock.
PIN_SPI_CS_N
W23
O
SPI chip select.
PIN_SPI_DO
U21
O
SPI data output.
Table 3-11 PCIe Interface Signals
Signal Name
Signal
Type
Number
Description
ISET
W21
Reference Current for PCI-Express PHY.
I/O
This pin must be connected to an external 6.04 kΩ, 1%
resistor to ground.
PIN_ISET
F12
I
Chip reference resistor 5 kΩ.
PTP
E15
O
Analog test port for PCIe.
PIN_M_CLK
AB23
I
PCIe debugging MDIO interface, clock.
PIN_M_DATA
AA23
I/O
PCIe debugging MDIO interface, data.
Table 3-12 SATA Transmitter and Receiver Interface Signals
Signal Name
Signal
Type
Number
PIN_RXP[3]
AA12
PIN_RXP[2]
AA10
PIN_RXP[1]
AA8
PIN_RXP[0]
AA6
PIN_RXN[3]
Y12
PIN_RXN[2]
Y10
PIN_RXN[1]
Y8
PIN_RXN[0]
Y6
Description
I
PIN_RXP[3:0]–SATA PHY 3–0 Receiver Differential
Signal.
I
PIN_RXN[3:0]–SATA PHY 3–0 Receiver Differential
Signals.
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
3-13
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Table 3-12 SATA Transmitter and Receiver Interface Signals (continued)
Signal Name
Signal
Type
Number
PIN_TXP[3]
AC13
PIN_TXP[2]
AC11
PIN_TXP[1]
AC9
PIN_TXP[0]
AC7
PIN_TXN[7]
–
PIN_TXN[6]
–
PIN_TXN[5]
–
PIN_TXN[4]
–
PIN_TXN[3]
AB13
PIN_TXN[2]
AB11
PIN_TXN[1]
AB9
PIN_TXN[0]
AB7
Description
O
PIN_TXP[3:0]–SATA PHY 3–0 Transmitter Differential
Signals.
O
PIN_TXN[3:0]–SATA PHY 3–0 Transmitter Differential
Signals.
Table 3-13 PCIe Transmitter and Receiver Interface Signals
Signal Name
Signal
Type
Number
PRXP[3]
A15
PRXP[2]
A17
PRXP[1]
A19
PRXP[0]
A21
PRXN[3]
B15
PRXN[2]
B17
PRXN[1]
B19
PRXN[0]
B21
PTXP[3]
C14
PTXP[2]
C16
PTXP[1]
C18
PTXP[0]
C20
PTXN[3]
D14
PTXN[2]
D16
PTXN[1]
D18
PTXN[0]
D20
Description
I
PRXP[3:0]–PCI-Express Lane 3–0 Receiver Differential
Signal (PCI-Express RX +/-).
I
PRXN[3:0]–PCI-Express Lane 3–0 Receiver Differential
Signals (PCI-Express RX +/-).
O
PTXP[3:0]–PCI-Express Lane 3–0 Transmitter
Differential Signals (PCI-Express TX -/+).
O
PTXN[3:0]–PCI-Express Lane 3–0 Transmitter
Differential Signals (PCI-Express TX -/+).
3-14
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Package
Table 3-14 Power Interface Signals
Signal Name
Signal
Number
Type
Description
AVDD25_0
F7
Power, I
I/O Pad Power 2.5V.
AVDD25_1
F18
Power, I
I/O Pad Power 2.5V.
AVDD[8]-1
F14, F15, Power, I
F16. H13,
H14, H15,
H16
1.8V analog power for PCI-Express PHY.
F9, F10, Power, I
F11, H9,
H10, H11,
H12
1.8V analog power for PCI-Express PHY.
AVDD[8]-2
AVDD[8] is for PLL and the current source.
AVDD[8] is for PLL and the current source.
VAA[0-3]
V7, V8,
V9, V10,
V11
Power, I
2.5V analog power for SATA PHY.
VAA[4-7]
V12, V13, Power, I
V14, V15,
V16
2.5V analog power for SATA PHY.
VAA_ANA
U20
2.5V analog power for PLL.
VDD
H6, H7,
Power, I
H8, H17,
H18, J6,
J18, K6,
K18, L6,
L18, M6,
M18, N6,
N18, P6,
P18, R6,
R18, T6,
T7, T8,
T9, T10,
T11, T12,
T13, T14,
T15, T16,
T17, T18
1.0V digital core power.
VDDO1
H20, J20, Power, I
K20, L20,
M20, N20,
P20, R20,
T20
Digital Power.
VDDO2
Power, I
3.3V I/O Power to supply digital and I/Os.
F5, H4,
J4, K4,
L4, M4,
N4, P4,
R4, T4,
U4
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
3-15
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Table 3-14 Power Interface Signals (continued)
Signal Name
VSS
Signal
Number
Type
A1, A4,
Ground
A6, A8,
A10, A12,
A14, A16,
A18, A20,
A22, A23,
B4, B6,
B8, B10,
B12, B14,
B16, B18,
B20, B22,
C5, C7,
C9, C11,
C13, C15,
C17, C19,
C21, D5,
D7, D9,
D11, D13,
D15, D17,
D19, D21,
E5–E14,
E16–E20,
F6, F8,
F13, F17,
F19, F20,
G20,
J7–J17,
K7–K17,
L7–L17,
M7– M17,
N7–N17,
P7–P17,
R7–R17,
V4–V6,
V17–
V20,
W4–W20,
Y5, Y7,
Y9, Y11,
Y13, Y15,
Y17, Y19,
Y21, AA5,
AA7, AA9,
AA11,
AA13,
AA15,
AA17,
AA19,
AA21,
Description
Ground.
3-16
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Package
Table 3-14 Power Interface Signals (continued)
Signal
Number
Signal Name
VSS
Type
AB6, AB8, Ground
AB10,
AB12,
AB14,
AB16,
AB18,
AB20,
AC1,
AC6,
AC8,
AC10,
AC12,
AC14,
AC16,
AC18,
AC20,
AC23
Description
Ground.
Table 3-15 No Connect Signals
Signal
Type
Number
Signal Name
NC
–
A5, A7, N/A
A9, A11,
B5, B7,
B9, B11,
C6, C8,
C10,
C12, D6,
D8, D10,
D12,
Y14,
Y16,
Y18,
Y20,
AA14,
AA16,
AA18,
AA20,
AB15,
AB17,
AB19,
AB21,
AC15,
AC17,
AC19,
AC21
Description
No Connect
Signal Descriptions
Copyright © 2015 Marvell
April 21, 2015
3-17
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
THIS PAGE LEFT INTENTIONALLY BLANK
3-18
Copyright © 2015 Marvell
April 21, 2015
Signal Descriptions
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Layout Guidelines
4
LAYOUT GUIDELINES
This chapter describes the system recommendations from the Marvell Semiconductor
design and application engineers who work with the 88SE9345. It is written for those who are
designing schematics and printed circuit boards for an 88SE9345-based system. Whenever
possible, the PCB designer should try to follow the suggestions provided in this chapter.
The information in this chapter is preliminary. Please consult with Marvell Semiconductor
design and application engineers before starting your PCB design.
The chapter contains the following sections:

88SE9345 Board Schematics

Layer Stack-Up

Power Supply

PCB Trace Routing

Recommended Layout
Refer to Chapter 3, Package, for package information.
4-1
Copyright © 2015 Marvell
April 21, 2015
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
4.1
88SE9345 Board Schematics
This section contains the following example board schematics:

Figure 4-1, 88SE9345 Example Board Schematic (1 of 4)

Figure 4-2, 88SE9345 Example Board Schematic (2 of 4)

Figure 4-3, 88SE9345 Example Board Schematic (3 of 4)

Figure 4-4, 88SE9345 Example Board Schematic (4 of 4)
4-2
Copyright © 2015 Marvell
April 21, 2015
88SE9345 Board Schematics
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Layout Guidelines

Figure 4-4, 88SE9345 Example Board Schematic (4 of 4)
Figure 4-1 88SE9345 Example Board Schematic (1 of 4)
U1A
RSTn
REFCLK+
REFCLKSMDAT
A16
A17 HSI_0+
HSI_0-
PTXP1
PTXN1
C118 100nF
C119 100nF
A21
A22 HSI_1+
HSI_1-
PTXP2
PTXN2
C111 100nF
C110 100nF
A25
A26 HSI_2+
HSI_2A29
A30 HSI_3+
HSI_3-
C113 100nF
C112 100nF
A32
A19
B12
B30
B3
B32
B29
B26
B25
B22
B21
B18
B16
B13
B7
B4
SMCLK
TCK
TDI
TMS
TRST
TDO
B7
A7 PRXN[6]
PRXP[6]
SRXP0
B11
A11
A13
PCLKP
A14
PCLKN
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
3.3VAux
D12
C12 PRXN[4]
PRXP[4]
B6
B5
A5
JT_TCK
A6
JT_TDI
A8
JT_TMS
B9
JT_TRSTn
A7
JT_TDO
A9
3V3a A10
3V3b B8
3V3c
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
A9
B9 PRXN[5]
PRXP[5]
B10 PCIE_12V_IN
3V3
PRXN3
PRXP3
B15
A15 PRXN[3]
PRXP[3]
PRXN2
PRXP2
B17
A17 PRXN[2]
PRXP[2]
PRXN1
PRXP1
B19
A19 PRXN[1]
PRXP[1]
PRXN0
PRXP0
B21
A21 PRXN[0]
PRXP[0]
+ C33
S_RXP1 0.01U C19 SRXP1
Y6 S_RXN0
PIN_RXN[0] AA6 S_RXP0
PIN_RXP[0]
AC9 S_TXP1
PIN_TXP[1] AB9 S_TXN1
PIN_TXN[1]
S_TXP2 0.01U C9
Y8 S_RXN1
PIN_RXN[1] AA8 S_RXP1
PIN_RXP[1]
S_RXN2 0.01U C10 SRXN2
S_RXP2 0.01U C11 SRXP2
AC11 S_TXP2
PIN_TXP[2] AB11 S_TXN2
PIN_TXN[2]
Y10 S_RXN2
PIN_RXN[2] AA10 S_RXP2
PIN_RXP[2]
S_TXP3 0.01U C25 STXP3
AC13 S_TXP3
PIN_TXP[3] AB13 S_TXN3
PIN_TXN[3]
S_RXN3 0.01U C29 SRXN3
S_TXN3 0.01U C27 STXN3
S_RXP3 0.01U C30 SRXP3
Y12 S_RXN3
PIN_RXN[3] AA12 S_RXP3
PIN_RXP[3]
J1
SRXP0
SRXN0
SRXP1
SRXN1
D8
C8 PTXN[6]
PTXP[6]
A12
A28
A27
A24
A23
A20
A18
A15
A4
A31
D10
C10 PTXN[5]
PTXP[5]
B11
A11 PTXN[4]
PTXP[4]
PTXN3
PTXP3
D14
C14 PTXN[3]
PTXP[3]
PTXN2
PTXP2
D16
C16 PTXN[2]
PTXP[2]
GOLD FINGER
Vanir Lite: PCIE X 4 ONLY!
PTXN1
PTXP1
D18
C18 PTXN[1]
PTXP[1]
PTXN0
PTXP0
D20
C20 PTXN[0]
PTXP[0]
R77
3 I2C_SDA
3 I2C_SCL
3 S_CLK0
3 S_LOAD0
S_CLK0
S_LOAD0
3 S_DOUT0
3 S_DIN0
S_DOUT0 R75
S_DIN0 R76
R78
R73
R74
AA22
PIN_PRESET_N
PIN_RESET_N
PCLKN
B13
R2
100R_X
A13
REFCLKN
PIN_ISET
W21
R4
6.04K
1
AC22
STXP1
STXN1
B5
B6 TX+1
TX-1
B13
B14 TX+2
TX-2
22R
22R
3V3
R_CFG0_3
10K_X
1K-5%_X
GND1
GND2
GND3
GND4
GND5
GND6
P1
P2
A1
A4
A7
A12
A15
A18
B16
B17 TX+3
TX-3
B8
B9
B10
A9
A10
A11
B11
A8
22R
SB0-SCLK GND7
SB1-SLOD GND8
SB2-GND GND9
SB3
GND10
SB4_SDO GND11
SB5_SDI GND12
SB6
SB7
B1
B4
B7
B12
B15
B18
iPASS_0.8mm_36
CONN-SAS-36pin-TS
R_CFG0_4
3V3
TP1
PTP
ISET
PIN_REFCLK
AB22
CNFG0
R_CFG0_1
R_CFG0_2
10K_X
1K-5%
CNFG1
R_CFG1_1
R_CFG1_2
10K_X
1K-5%
SOC_RESET# 3
3V3
(INTERNAL TEST MODE SELECTION)
CNFG[1:0]
*00: Normal
01:
10:
11:
FB1
1
Y1
2
1
GND OUT
OE
Vcc
50MHZ_8W50000002
3
2
2V5
FB_1A
4
C39
0.1U
C40
1U
C148
4.7uF
10V
C0805
C59
1U
88SE9345 Board Schematics
Copyright © 2015 Marvell
April 21, 2015
B2
B3 TX+0
TX-0
PEG2
R3
F12
U10
1
5
2 A VCC
3 B
4
GND Y
SN74LVC1G08
AND
STXP0
STXN0
PEG1
S1
S2
S3
S4
S5
S6
V21
R68 DNP_0R
5 REG_PGOOD
A16
A17 RX+3
RX-3
MTH1
MTH2
MTH3
MTH4
MTH5
MTH6
4.99K
PIN_TP
1 E15
SRXP3
SRXN3
STXP3
STXN3
REFCLKP
PCLKP
TP2
A13
A14 RX+2
RX-2
22R
Y22
PIN_CNFG[0] W22
PIN_CNFG[1]
A2
A3 RX+0
RX-0
A5
A6 RX+1
RX-1
SRXP2
SRXN2
STXP2
STXN2
22R_X
22R_X
CLOCK & RESET
PCIE_RESET_N
STXP2
S_TXN2 0.01U C21 STXN2
D6
C6 PTXN[7]
PTXP[7]
100uF/16V
A3
+12Va A2
+12Vb B1
+12Vc B2
+12Vd
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND21
GND22
S_RXN1 0.01U C16 SRXN1
C38
WAKE#
B31
C37
B27
B28 HSO_3+
HSO_3-
PTXP3
PTXN3
SRXN0
S_RXP0 0.01U C4
S_TXN1 0.01U C14 STXN1
AC7 S_TXP0
PIN_TXP[0] AB7 S_TXN0
PIN_TXN[0]
C36
PRXP3
PRXN3
PRSNT#2b
B17
C35
B23
B24 HSO_2+
HSO_2-
B5
A5 PRXN[7]
PRXP[7]
P0_PRSNTX2
1000pF_X
PRXP2
PRXN2
PRSNT#2a
A1
1000pF_X
B19
B20 HSO_1+
HSO_1-
PRSNT#1
SAS/SATA
1000pF_X
PRXP1
PRXN1
PEX
1000pF_X
B14
B15 HSO_0+
HSO_0-
C114 100nF
C116 100nF
STXN0
S_RXN0 0.01U C3
S_TXP1 0.01U C13 STXP1
PEX 4x
PTXP0
PTXN0
STXP0
S_TXN0 0.01U C2
VanirLite_88SE9440
P1
PRXP0
PRXN0
S_TXP0 0.01U C1
4-3
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest
schematics.
Figure 4-2 88SE9345 Example Board Schematic (2 of 4)
VanirLite_88SE9440
U1B
P_ADDR0
P_ADDR1
P_ADDR2
P_ADDR3
P_ADDR4
P_ADDR5
P_ADDR6
P_ADDR7
P_ADDR8
P_ADDR9
P_ADDR10
P_ADDR11
P_ADDR12
P_ADDR13
P_ADDR14
P_ADDR15
P_ADDR16
TP39 1
TP41 1
TP43 1
TP45 1
TP46 1
2 I2C_SDA
Y3
W3 PIN_P_WE_N[0]
Y4 PIN_P_WE_N[1]
AA3 PIN_P_WE_N[2]
PIN_P_WE_N[3]
K2
H1
G1
F1
L3
K3
AB4
AC4
AB1
AA1
L1
L2
M1
M2
N3
N1
N2
M3
K1
J1
AB5
AC5
PIN_P_ADDR[0]
PIN_P_ADDR[1]
PIN_P_ADDR[2]
PIN_P_ADDR[3]
PIN_P_ADDR[4]
PIN_P_ADDR[5]
PIN_P_ADDR[6]
PIN_P_ADDR[7]
PIN_P_ADDR[8]
PIN_P_ADDR[9]
PIN_P_ADDR[10]
PIN_P_ADDR[11]
PIN_P_ADDR[12]
PIN_P_ADDR[13]
PIN_P_ADDR[14]
PIN_P_ADDR[15]
PIN_P_ADDR[16]
PIN_P_ADDR[17]
PIN_P_ADDR[18]
PIN_P_ADDR[19]
PIN_P_ADDR[20]
PIN_P_ADDR[21]
NVSRAM/FLASH
D4
C4 PIN_N_WE_N
G4 PIN_N_CE_N
PIN_N_OE_N
N_WE_N
N_CE_N
N_OE_N
PIN_F_RESET_N
PIN_F_CE_N
PIN_F_READY
PIN_F_WE_N
PIN_F_OE_N
PIN_F_BYTE_N
R51 R52
10K 10K
3V3
1
1
1
1
1
1
C3
E4
D3
A3
F4
B3
R5 R6
UAO_0
UAI_0
TP8
TP14
TP10
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP40
TP42
TP44
SMCLK
I2C_SCL
1
100R
1
1
1
1
DNP_SJ-3523
AUDIO-JACK-SJ-3523-SMT
P21
R22 PIN_SCL[0]
R23 PIN_SCL[1]
PIN_SCL[2]
ACT0
ACT1
ACT2
ACT3
ACT4
ACT5
ACT6
ACT7
ACT8
Gnd
SPI_DI
1 2
SPI_DI
SPI_DO
SPI_CLK
SPI_CS_N
T21 UAO_0
PIN_UAO[0] V23
PIN_UAO[1] U22 UAI_0
PIN_UAI[0] U23
PIN_UAI[1]
SPI FLASH - AT26F004 JP3
4Mb
SOIC8-50-212
N21
P22
P23
M21
N22
N23
M23
M22
L21
PIN_ACT[0]
PIN_ACT[1]
PIN_ACT[2]
PIN_ACT[3]
PIN_ACT[4]
PIN_ACT[5]
PIN_ACT[6]
PIN_ACT[7]
PIN_ACT[8]
2
3V3
R55 R56
10K 10K
1
R14
4.7K-5%
R0603
R57 R63
10K 10K
UAO_1
TEST[2]
1 2
JP2
UAI_1
3 I2C_SCL
2
P_DATA6
N_OE_N
P_ADDR10
N_CE_N
P_DATA7
P_DATA5
P_DATA4
P_DATA3
3V3
C48
0.1U
C58
0.1U
DNP_AT24C02B
1 I2C_SDA
3V3
3V3
Serial EEPROM for I2C
4
FDC640PCT 1
Q1
6
U6
C50
0.1U
I2C connector
BUZZ1
1
2
2 SOC_RESET#
SOC_RESET#
1
2
3
4
5
6
7
NC1
NC2
NC3
VCC
NC4
NC5
RST
NC7
NC6
GND_A
GND
SDA2
SDA1
SCL
14
13
12
11
10
9
8
R16
R17
10K_X 10K_X
SMDAT
SMCLK
BUZZER_3VDC
U3,U5,U6 ARE OPTIONAL.
LED SILKSCREEN
3V3
3V3
3V3
J3
(ACTIVITY LED)
4 HEADER
L23
L22
K23
K22
K21
J23
J22
J21
H23
Encryption key
2 S_DIN0
2 S_DOUT0
2 S_LOAD0
2 S_CLK0
TEST[0]_D
TEST[1]_D
TEST[3]_D
TEST[4]_D
3V3
S_DIN0
S_DOUT0
S_LOAD0
S_CLK0
S_DIN1
S_DOUT1
S_LOAD1
S_CLK1
FLT8
Top - Activity (Green)
Bottom - Fault (Yellow)
3V3
LED1
GREEN/YELLOW
led_bi_smd4
Item 25.
ACT0
ACT1
ACT2
ACT3
R34
R43
100R
R18
R19
R20
R22
10R
10R
10R
10R
ACT1
ACT2
ACT3
ACT4
GREEN
GREEN
GREEN
GREEN
1
3
5
7
9
1
3
5
7
9
2
4
6
8
10
2
4
6
8
10
ACT0_D
ACT1_D
ACT2_D
ACT3_D
SH_2x5_2.54
10K
3V3
TEST[0]
TEST[1]
TEST[0]_D
TEST[1]_D
TEST[3]_D
TEST[4]_D
R44
1K-5%
R36
R37
R38
R40
10R
10R
10R
10R
FLT1
FLT2
FLT3
FLT4
C57
0.1U
Amber
Amber
Amber
Amber
(DRIVE FAULT LED)
2
4 DA0
6 DA1
8 DA2
DA3
ACT0
ACT1
ACT2
ACT3
17
15 DB0
13 DB1
11 DB2
DB3
TEST[14] R50
1K-5%
19
1 OEB
OEA
18 TEST[0]_D
OA0 16 TEST[1]_D
OA1 14 TEST[3]_D
OA2 12 TEST[4]_D
OA3
3
OB0 5
OB1 7
OB2 9
OB3
10
Install R34, 10K and R44, 1K for debug purposes (UART)
PIN_TEST[15:0]
Configuration and Test pins, GPIO.
0
PIN_TEST[15] => Must tie low
PIN_TEST[14:13] => Chip reference clock selection => 00: 20MHz, 01: 50MHz(default), 10: 100MHz, 11: 75MHz
PIN_TEST[12:11] => RSVD
PIN_TEST[10] => PCIE ROM Location => 0: Parallel Flash, 1: Serial Flash
PIN_TEST[9:8] => RSVD
00 or 11
PIN_TEST[7:5] => RSVD Must tie low
000
3V3
PIN_TEST[4] => Parallel Flash x8/x16 => 0: Byte Mode, 1: Word Mode
PIN_TEST[3:2] => RSVD
R48
PIN_TEST[1] => UART Baud Rate =>
0: 57600, 1: RSVD
10K
PIN_TEST[0] => UART Mode =>
0: RSVD, 1: Terminal Mode
TEST[13]
U12
TEST[0]
TEST[1]
TEST[3]_FLT2
TEST[4]_FLT3
R46
ACT0_D
ACT1_D
ACT2_D
ACT3_D
PI74FCT241/SO
Drive Fault/ Activity LED headers
3V3
R49
10K
TEST[10]
4-4
Copyright © 2015 Marvell
April 21, 2015
P_ADDR11
3V3
U5
8
1
7 VCC A0 2
6 WP A1 3
5 SCL A2 4
SDA GND
22-05-5035
3
M_CLK
M_DATA
1
2
3
4
PIN_FLT[0]
PIN_FLT[1]
PIN_FLT[2]
PIN_FLT[3]
PIN_FLT[4]
PIN_FLT[5]
PIN_FLT[6]
PIN_FLT[7]
PIN_FLT[8]
C44
0.1U
DNP_ARC100_16P_X
J5
LED
10K
NVRAM 128KB
pin 2: A16, pin47: A15
3
BUZZER
AB23
PIN_M_CLK AA23
PIN_M_DATA
PIN_TEST[0]
PIN_TEST[1]
PIN_TEST[2]
PIN_TEST[3]
PIN_TEST[4]
PIN_TEST[5]
PIN_TEST[6]
PIN_TEST[7]
PIN_TEST[8]
PIN_TEST[9]
PIN_TEST[10]
PIN_TEST[11]
PIN_TEST[12]
PIN_TEST[13]
PIN_TEST[14]
PIN_TEST[15]
R7
N_WE_N
P_ADDR13
P_ADDR8
P_ADDR9
NVRAM 32KB
pin 2: NC, pin47: NC
SPI_DO
2
SO
P_ADDR15
DNP_CY14B256L-SP35XCT
SPI_CS_N
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
2.0K
H22
G23
H21
G22
F23
G21
F21
F22
D23
E23
C23
E22
E21
B23
D22
C22
P_DATA0
P_ADDR3
P_ADDR2
P_ADDR1
P_ADDR0
P_DATA1
P_DATA2
48
Vcap VCC2 47
A16
A15 46
A14 HSB# 45
A12
WE# 44
A7
A13 43
A6
A8 42
A5
A9 41
NC1 NC14 40
A4
A11 39
NC2 NC13 38
NC3 NC12 37
NC4 NC11 36
VSS1 VSS2 35
NC5 NC10 34
NC6 NC9 33
DQ0 DQ6 32
A3
OE# 31
A2
A10 30
A1
CE# 29
A0
DQ7 28
DQ1 DQ5 27
DQ2 DQ4 26
NC7 DQ3 25
NC8 VCC1
SPI_CLK
R9 0R
R0603
3V3
56R
56R
56R
56R
P_ADDR4
UART
3V3
V22 R11
PIN_SPI_DI U21 R12
PIN_SPI_DO Y23 R13
PIN_SPI_CLK W23 R15
PIN_SPI_CS_N
A2
C2
A1
C1
TP56
TP57
TP58
TP59
100uF/16V
4
C45
100nF
C0402
C47
100nF
C0402
4
3
2
1
(ACTIVITY LED)
GND J4
3V3
R23
R24
R25
R26
R27
R28
R29
R30
TEST[0]
TEST[1]
TEST[2]
TEST[3]_FLT2
TEST[4]_FLT3
TEST[5]
1K-5%
TEST[6]_FLT4
1K-5%
TEST[7]_FLT5
1K-5%
TEST[8]
1K-5%
TEST[9]
1K-5%
TP60 1 TEST[10]
TP61 1 TEST[11]_FLT6
TP66 1 TEST[12]_FLT7
TEST[13]
TEST[14]
TEST[15]
1K-5%
(DRIVE FAULT LED)
R69
+ C41
RXO
P_ADDR16
P_ADDR14
P_ADDR12
P_ADDR7
P_ADDR6
P_ADDR5
SPI FLASH, 4MBit
CONFIG/TEST/RSVD
R72
R79
R80
R71
R70
3V3
C43
100nF
C0402
5
SI
4
2
5
TP55
1
5
3V3
TP47
TP48
TP49
TP50
TP51
TP52
SERIAL INTERFACE
2 I2C_SCL
2
TXI J5
R8 10K
U4
3
6
7 WP SCLK
1
8 HOLD
VCC CS
C49
100nF
10V
C0402
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
J2
3
ADM0_TX
ADM0_RX
I2C0
SMDAT R21
I2C_SDA T22 PIN_SDA[0]
TP53 1 T23 PIN_SDA[1]
PIN_SDA[2]
R53 R54
10K 10K
U2
11
14
12 Tx1IN Tx1OUT 13
9 Rx1OUT Rx1IN 8
Rx2OUT
Rx2IN
10
7
Tx2IN Tx2OUT
1
16
C1+
3.3V 2
C42
V+
100nF
C0402 3
4 C1C2+
C46
6
100nF
V- 15
C0402 5
C2GND
ADM3202ARN
3V3
3V3
U3
10K 10K
20
1
1
1
1
TP9
TP16
TP11
TP12
P_DATA0
P_DATA1
P_DATA2
P_DATA3
P_DATA4
P_DATA5
P_DATA6
P_DATA7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCC
1 AC3
1 AA4 PIN_P_OE_N
PIN_P_CS1_N
TP7
TP15
PIN_P_DATA[0]
PIN_P_DATA[1]
PIN_P_DATA[2]
PIN_P_DATA[3]
PIN_P_DATA[4]
PIN_P_DATA[5]
PIN_P_DATA[6]
PIN_P_DATA[7]
PIN_P_DATA[8]
PIN_P_DATA[9]
PIN_P_DATA[10]
PIN_P_DATA[11]
PIN_P_DATA[12]
PIN_P_DATA[13]
PIN_P_DATA[14]
PIN_P_DATA[15]
PIN_P_DATA[16]
PIN_P_DATA[17]
PIN_P_DATA[18]
PIN_P_DATA[19]
PIN_P_DATA[20]
PIN_P_DATA[21]
PIN_P_DATA[22]
PIN_P_DATA[23]
PIN_P_DATA[24]
PIN_P_DATA[25]
PIN_P_DATA[26]
PIN_P_DATA[27]
PIN_P_DATA[28]
PIN_P_DATA[29]
PIN_P_DATA[30]
PIN_P_DATA[31]
PIN_P_DATA[32]
PIN_P_DATA[33]
PIN_P_DATA[34]
PIN_P_DATA[35]
P2
P3
R1
T1
U1
R3
R2
V1
W1
Y1
T3
U2
T2
V2
U3
W2
G3
F2
E3
B2
A2
G2
H3
H2
D2
C2
B1
E2
J3
C1
D1
E1
P1
Y2
F3
J2
GND
TP4
TP5
TP6
3V3
3V3 3V3
PBSRAM
1 AC2
1 AB3 PIN_P_BW_N
PIN_P_OUT_CLK
1 V3
1 AB2 PIN_P_GW_N
1 AA2 PIN_P_ADSC_N
PIN_P_ADV_N
TP13
TP3
88SE9345 Board Schematics
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Layout Guidelines
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest
schematics.
Figure 4-3 88SE9345 Example Board Schematic (3 of 4)
U1C
VanirLite_88SE9440
J6
AVDD_25
VAA_0_3
VAA_4_7
VDDO1
VDDO2
1V0_core
F9
H9
F10
H10
F11
H11
H12
F7
F18
VAA_ANA U20
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
H20
J20
K20
L20
M20
N20
P20
R20
T20
H4
J4
K4
L4
M4
N4
P4
R4
T4
U4
F5
H6
J6
K6
L6
M6
N6
P6
R6
T6
H7
T7
H8
T8
T9
T10
T11
T12
T13
T14
T15
T16
H17
T17
H18
J18
K18
L18
M18
N18
P18
R18
T18
AVDD[8]-2_0
AVDD[8]-2_1
AVDD[8]-2_2
AVDD[8]-2_3
AVDD[8]-2_4
AVDD[8]-2_5
AVDD[8]-2_6
AVDD25_0
AVDD25_1
VAA_ANA
VAA[0_3]_0
VAA[0_3]_1
VAA[0_3]_2
VAA[0_3]_3
VAA[0_3]_4
VAA[4_7]_0
VAA[4_7]_1
VAA[4_7]_2
VAA[4_7]_3
VAA[4_7]_4
VDDO1_0
VDDO1_1
VDDO1_2
VDDO1_3
VDDO1_4
VDDO1_5
VDDO1_6
VDDO1_7
VDDO1_8
VDDO2_0
VDDO2_1
VDDO2_2
VDDO2_3
VDDO2_4
VDDO2_5
VDDO2_6
VDDO2_7
VDDO2_8
VDDO2_9
VDDO2_10
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
A1
AC1
A4
B4
V4
W4
C5
D5
E5
V5
W5
Y5
AA5
A6
B6
E6
F6
V6
W6
AB6
AC6
C7
D7
E7
J7
K7
L7
M7
N7
P7
R7
W7
Y7
AA7
A8
B8
E8
F8
J8
K8
L8
M8
N8
P8
R8
W8
AB8
AC8
C9
D9
E9
J9
K9
L9
M9
N9
P9
R9
W9
Y9
AA9
A10
B10
E10
J10
K10
L10
M10
N10
P10
R10
W10
AB10
AC10
C11
D11
E11
J11
K11
L11
M11
N11
P11
R11
W11
Y11
AA11
A12
B12
E12
J12
K12
L12
M12
N12
P12
R12
W12
AB12
AC12
C13
D13
E13
F13
J13
K13
L13
M13
N13
P13
R13
W13
Y13
AA13
A14
B14
E14
J14
K14
L14
M14
N14
P14
R14
W14
AB14
AC14
C15
D15
J15
K15
L15
M15
N15
P15
1V8
2V5
Banana Plug_WHITE
FB2
R207
0.1-1%
R0805
FB3
1
2
VAA_ANA
FB_1A
C51
C52
0.1U
0.01U
R205
0.1-1%
R0805
1
2
AVDD[8]-1
FB_2A
C53
C54
C55
C56
2.2U
0.1U
0.01U
1000P
C65
C66
C67
C68
2.2U
0.1U
0.01U
1000P
J4
2V5
Banana Plug_YELLOW
FB4
R206
1
0.1-1%
R0805
2
VAA_0_3
FB_1A
C61
C62
C63
C64
2.2U
0.1U
0.01U
1000P
FB5
1
2
AVDD[8]-2
TP63 TP64
FB_2A
FB6
1
2
VAA_4_7
FB_1A
C69
C70
C71
C72
2.2U
0.1U
0.01U
1000P
2V5
C77
J8
10U_10V
GND
2V5
FB7
R208
0.1-1%
R0805
1
2
AVDD_25
FB_1A
C78
C79
0.1U
0.01U
J10
1V0
Banana Plug_Blue
3V3
FB8
J7
R209
FB9
0.1-1%
R0805
1
2
FB_4A
Banana Plug_RED
R210
0.1-1%
R0805
1
2
1V0_core
C80
C81
C82
C83
C84
C85
C86
C87
C88
10U_10V
0.1U
0.1U
0.1U
0.01U
0.01U
0.01U
0.01U
0.01U
C94
C95
C96
C97
C98
C99
C100
C101
C102
10U_10V
0.1U
0.1U
0.1U
0.01U
0.01U
0.01U
0.01U
0.01U
VDDO1
FB_1A
C89
C90
C91
C92
C93
10U_10V
0.1U
0.1U
0.01U
0.01U
1V0_core
FB10
1
2
FB_1A
VDDO2
C103
C104
10U_10V 0.1U
C105 C106
C107 C108 C109
0.1U
0.01U 0.01U 0.01U
0.1U
R15
W15
Y15
AA15
A16
B16
E16
J16
K16
L16
M16
N16
P16
R16
W16
AB16
AC16
C17
D17
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
E17
F17
J17
K17
L17
M17
N17
P17
R17
V17
W17
Y17
AA17
A18
B18
E18
V18
W18
AB18
AC18
C19
D19
E19
F19
V19
W19
Y19
AA19
A20
B20
E20
F20
G20
V20
W20
AB20
AC20
C21
D21
Y21
AA21
A22
B22
A23
AC23
AVDD[8]-1_0
AVDD[8]-1_1
AVDD[8]-1_2
AVDD[8]-1_3
AVDD[8]-1_4
AVDD[8]-1_5
AVDD[8]-1_6
1
AVDD[8]-2
H13
F14
H14
F15
H15
F16
H16
1
POWER/GND
AVDD[8]-1
88SE9345 Board Schematics
Copyright © 2015 Marvell
April 21, 2015
4-5
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
88SE9345 R3.3 Four-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAID I/O Controller
Preliminary Datasheet
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest
schematics.
Figure 4-4 88SE9345 Example Board Schematic (4 of 4)
SYSTEM 1.0V/ 3A
3V3
MTH1
1
Hole
3V3
R67
100K
13
2 REG_PGOOD
17
16
2
SGND
POR
SW1
SW2
SW3
SW4
SDI
EN
SFB
PSET
C130
PVIN
PVIN
PVIN
PGND
PGND
PGND
VBS
18
0.1U
R158
1K-5%
1
R62
100K
SVIN
7
6
5
9
10
11
3
+ C142
22uF
6V3
C0805
C147
47nF C0603
4
8
12
19
L6
+ C143
22uF
6V3
C0805
C144
22uF
6V3
C0805
C145
22uF
6V3
C0805
1.0uH
FDV0630-1R0
3.1A
14
Hole
C146
4.7uF
10V
C0805
1V0
VSET
15
C141
100nF
10V
C0402
MTH2
1
88PG877
+
U9
+
R148
R0402
10
R64
0R
NORMAL:5A
PEAK:7.5A
R65
18.7K-1%
R0402
3V3
1K-5% R0402
GREEN
+
R66
LED2
3V3
R58
100K
C131
0.1U
R59
2
20
18
L2
2.0uH
2V5
C121
0.1U
C123 C124
22U
22U
17
3V3
C125
C126
22U
22U
L3
2.0uH
3V3
0.1U
C128
22U
EN
SVIN
SGND
PVIN2
POR2
5
C127
SW2_1
SW2_0
SDI
19
1V8
SFB2
7
9
10
PGND2
POR1
SFB1
PSET2
SW1_1
SW1_0
VSET2
PSET1
PVIN1
VSET1
C129
3V3
10R
U8
1
C122
3
0.1U
4
6 SDI
R60
16
10K
11
R61
100K
REG_PGOOD
15 PSET2
14 VSET2
12 PSET1
13 VSET1
R-VSET1
165K
R_PSET1
0R
22U
8
PGND1
R_VSET2
88PG8237
97.6K
R_PSET2
0R
Note: This diagram is for reference only. Contact your Marvell field applications engineer for the latest
schematics.
4-6
Copyright © 2015 Marvell
April 21, 2015
88SE9345 Board Schematics
Doc No. MV-S109418-00 Rev. A
Document Classification: Proprietary
Part 1: Chip Overview
Layout Guidelines
4.2
Layer Stack-Up
The following layer stack up is recommended

Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power Routes

Layer 2–Solid Ground Plane

Layer 3–Power Plane and Low Speed Signals

Layer 4–Power Plane

Layer 5–Solid Ground Plane

Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes
5 mil traces and 5 mil spacing are the recommended minimum requirements.
4.2.1
Layer 1–Topside, Parts, Low and High-Speed Signal Routes, and Power
Routes
All active parts are to be placed on the topside. Some of the differential pairs for SATA and
PCIe are routed on the top layer, differential 100 ohm impedance needs to be maintained for
those high-speed signals.
4.2.2
Layer 2–Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer
should be a minimum distance below the top layer in order to reduce the amount of crosstalk
and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is
recommended.
4.2.3
Layer 3–Power Plane and Low Speed Signals
Use solid planes on layer 3 to supply power to the ICs on the PCB. Avoid narrow traces and
necks on this plane.
4.2.4
Layer 4–Power Plane
Use solid planes on layer 4 to supply power to the ICs on the PCB. Avoid narrow traces and
necks on this plane.
4.2.5
Layer 5–Solid Ground Plane
A solid ground plane should be located directly below the top layer of the PCB. This layer
should be a minimum distance below the top layer in order to reduce the amount of crosstalk
and EMI. There should be no cutouts in the ground plane. Use of 1 ounce copper is
recommended.
Layer Stack-Up
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4.2.6
Layer 6–Bottom Layer, Low and High-Speed Signal Routes, and Power Routes
Some of the differential pairs for SATA and PCIe are routed on the top layer, differential 100Ω
impedance needs to be maintained for those high speed signals.
4-8
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Layout Guidelines
4.3
Power Supply
The 88SE9345 operates using the following power supplies:
4.3.1

VDD Power (1.0V) for the digital core

PCIe Analog Power Supply (1.8V)

SATA Analog Power Supply (2.5V)

General I/O Power (3.3V)
VDD Power (1.0V)
All digital power pins (VDD pins) must be connected directly to a VDD plane in the power
layer with short and wide traces to minimize digital power-trace inductances.
Use vias close to the VDD pins to connect to this plane and avoid using the traces on the top
layer. Marvell recommends placing capacitors around the three sides of the PCB near VDD
pins with the following dimensions:

0.001 µF (1 capacitor)

0.1 µF (2 capacitors)

2.2 µF (1 ceramic capacitor)
The combinations of small capacitors are used to suppress switching noise at various
frequency ranges. The 2.2 µF ceramic decoupling capacitor is required to filter the lower
frequency power-supply noise.
To reduce system noise, place high-frequency surface-mount monolithic ceramic bypass
capacitors as close as possible to the channel VDD pins. Place at least one decoupling
capacitor on each side of the IC package.
4.3.2
PCIe Analog Power Supply (1.8V)
The analog supply provides power for the PCIe link’s high speed serial signals. To ensure
high speed link operation, use a series of bypass capacitors for the supplies. A typical
capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.3
SATA Analog Power Supply (2.5V)
The analog supply provides power for the SATA link’s high speed serial signals. To ensure
high speed link operation, use a series of bypass capacitors for the supplies. A typical
capacitor value combination is 1 nF, 0.1µF, and 2.2 µF.
4.3.4
General I/O Power (3.3V)
A general I/O power supply provides power to the GPIO, flash and I2C blocks. A stable and
clean power source is desired. Use proper bypass capacitors to provide a clean power
source with good stability. A typical capacitor value combination is 0.1µF, and 2.2 µF.
Power Supply
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4.3.5
Bias Current Resistor (RSET)
Connect a 6.04KΩ (1%) resistor between the ISET pin and the adjacent top ground plane.
This resistor should lie as close as possible to the ISET pin. Avoid routing noisy signals close
to the ISET pin.
4-10
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Power Supply
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Layout Guidelines
4.4
PCB Trace Routing
The stack-up parameters for the reference board are shown in Table 4-1.
Table 4-1 PCB Board Stack-up Parameters
Layer
Layer
Description
Copper Weight
(oz)
Target Impedance
(±10%)
1
Signal
0.5
50
2
GND
1
N/A
3
Power and
Signal
1
50
4
Power
1
N/A
5
GND
1
N/A
6
Signal
0.5
50
PCB Trace Routing
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4.5
Recommended Layout
High-speed designs must consist of a good board stack-up and careful consideration of the
power planes. For the 88SE9345, the following power planes are required:

VDDIO_C, VDDIO_D, and VDDIO_P power plane (3.3V power source for the digital I/O pins)

VDD (1.0V power source for the core and digital circuitry)

VAA (2.5V power source for SATA analog)

AVDD (1.8V power source for PCIe analog)
Solid ground planes are recommended. However, special care should be taken when routing
VAA, AVDD, and VSS pins.
The following general tips describe what should be considered when determining your
stack-up and board routing. These tips are not meant to substitute for consulting with a
signal-integrity expert or doing your own simulations.
Note: Specific numbers or rules-of-thumb are not used here because they might not be applicable in
every situation.

Do not split ground planes.
Keep good spacing between possible sensitive analog circuitry on your board and the digital
signals to sufficiently isolate noise. A solid ground plane is necessary to provide a good return
path for routing layers. Try to provide at least one ground plane adjacent to all routing layers
(see Figure 4-5).

Keep trace layers as close as possible to the adjacent ground or power planes.
This helps minimize crosstalk and improve noise control on the planes.
Figure 4-5 Trace Has At Least One Solid Plane For Return Path
GND
V2
V1

When routing adjacent to only a power plane, do not cross splits.
Route traces only over the power plane that supplies both the driver and the load. Otherwise,
provide a decoupling capacitor near the trace at the end that is not supplied by the adjacent
power plane.

Critical signals should avoid running parallel and close to or directly over a gap.
This would change the impedance of the trace.

Separate analog powers onto opposing planes.
This helps minimize the coupling area that an analog plane has with an adjacent digital plane.
4-12
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Recommended Layout
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Layout Guidelines

For dual strip-line routing, traces should only cross at 90 degrees.
Avoid more than two routing layers in a row to minimize tandem crosstalk and to better control
impedance.

Planes should be evenly distributed in order to minimize warping.

Calculating or modeling impedance should be made prior to routing.
This helps ensure that a reasonable trace thickness is used and that the desired board
thickness is available. Consult with your board fabricator for accurate impedance.

Allow good separation between fast signals to avoid crosstalk.
Crosstalk increases as the parallel traces get longer.

When packages become smaller, route traces over a split power plane
Smaller packages force vias to become smaller, thereby reducing board thickness and layer
counts, which might create the need to route traces over a split power plane. Some
alternatives to provide return path for these signals are listed below.
Caution must be used when applying these techniques. Digital traces should not cross over
analog planes, and vice-versa. All of these rules must be followed closely to prevent noise
contamination problems that might arise due to routing over the wrong plane.
By tightly controlling the return path, control noise on the power and ground planes can be
controlled.

Place a ground layer close enough to the split power plane in order to couple enough to
provide buried capacitance, such as SIG-PWR-GND (see Figure 4-6). Return signals that
encounter splits in this situation simply jumps to the ground plane, over the split, and back
to the other power plane. Buried capacitance provides the benefit of adding low
inductance decoupling to your board. Your fabricator may charge for a special license fee
and special materials. To determine the amount of capacitance your planes provide, use
the following equation:
C = 1.249 • 10
– 13
• Er • L • W ⁄ H
Where ER is the dielectric coefficient, L • W represents the area of copper, and H is the
separation between planes.

Provide return-path capacitors that connect to both power planes and jumps the split.
Place them close to the traces so that there is one capacitor for every four or five traces.
The capacitors would then provide the return path (see Figure 4-7).

Allow only static or slow signals on layers where they are adjacent to split planes.
Figure 4-6 shows the ground layer close to the split power plane.
Figure 4-6 Close Power and Ground Planes Provide Coupling For Good Return Path
V2 PLANE
H
V1 PLANE
GND PLANE
Recommended Layout
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Figure 4-7 shows the thermal ground plane in relation to the return-path capacitor.
Figure 4-7 Suggested Thermal Ground Plane On Opposite Side of Chip
V2
V1
4-14
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Electrical Specifications
5
ELECTRICAL SPECIFICATIONS
This chapter contains the following sections:

Absolute Maximum Ratings

Recommended Operating Conditions

DC Electrical Characteristics

Thermal Data

AC Timing
5-1
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Preliminary Datasheet
5.1
Absolute Maximum Ratings
Table 5-1 Absolute Maximum Ratings
Parameter
Symbol
Minimum
Typical
Maximum
Units
Absolute Analog Power for PCIe PHY
AVDD[8:0]
1.62
1.8
1.98
V
Absolute Analog Power for SATA PHY, VAA[7:0],
Chip PLL
VAA_ANA
2.25
2.5
2.75
V
Absolute Power for Digital Core
VDD
0.9
1.0
1.1
V
Absolute Digital I/O Power
VDDO1/VDDO2 3
3.3
3.6
V
CAUTION: Exposure to conditions at or beyond the maximum rating may damage the device.
Operation beyond the recommended operating conditions (Table 5-2) is neither recommended
nor guaranteed.
Note: Before designing a system, it is recommended that you read application note AN-63: Thermal
Management for Marvell Technology Products. This application note presents basic concepts of
thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating
conditions for Marvell Technology's products.
5-2
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Electrical Specifications
5.2
Recommended Operating Conditions
Table 5-2 Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
Analog Power for PCIe PHY
AVDD[8:0]
1.71
1.8
1.89
V
Analog Power for SATA PHY, Chip
PLL
VAA[7:0],
VAA_ANA
2.38
2.5
2.63
V
Digital Core Power
VDD
0.95
1.0
1.05
V
Digital I/O Power
VDDO1/VDDO2 3.14
3.3
3.47
V
Internal Bias Reference
ISET, PIN_ISET 5.74
6.04
6.34
KΩ
Ambient Operating Temperature
TA
0
N/A
70
°C
Junction Operating Temperature
TJ
0
N/A
125
°C
CAUTION: Operation beyond the recommended operating conditions is neither recommended
nor guaranteed.
Recommended Operating Conditions
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5.3
DC Electrical Characteristics
Table 5-3 DC Electrical Characteristics
Parameter
Symbol Minimum
Typical
Maximum
Units
Analog Power for PCIe PHY 1.8V
IAVDD
0.19
0.215
0.24
A
Analog Power for SATA PHY 2.5V, Chip IVAA
PLL
0.55
0.62
0.69
A
Digital Core Power
IVDD
1.5
1.94
2.93
A
mA
Digital I/O Power
IVDDO
9.2
10.5
11.6
Input Low Voltage of Digital I/O
VIL
-0.4
N/A
0.3 × VDDOx V
Input High Voltage of Digital I/O
VIH
0.7 × VDDOx N/A
VDDOx + 0.4 V
Output Low Voltage of Digital I/O
VOL
N/A
0.13
N/A
V
Output High Voltage of Digital I/O
VOH
2.0
VDDOx*
N/A
V
* VDDOx: VDDO1/VDDO2.
CAUTION: Operation beyond the recommended operating conditions is neither recommended
nor guaranteed.
Table 5-4 shows the internal pull-up and pull-down strength.
Table 5-4 Internal Pull-Up and Pull-Down Strength
Specifications
Condition
Minimum
Nominal
Maximum Unit
Pull-Up Strength
V(PAD) = 0.5 × VDDO
10
N/A
50
µA
V(PAD) = 0
10
N/A
65
µA
V(PAD) = 0.5 × VDDO
10
N/A
50
µA
Pull-Down Strength
5-4
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Electrical Specifications
5.4
Thermal Data
It is recommended to read application note AN-63 Thermal Management for Selected
Marvell® Products (Document Number MV-S300281-00) and the ThetaJC, ThetaJA, and
Temperature Calculations White Paper, available from Marvell, before designing a system.
These documents describe the basic understanding of thermal management of integrated
circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products.
Table 5-5 provides the thermal data for the 88SE9345. The simulation was performed
according to JEDEC standards. The heat sink is 25.4 mm × 25.4 mm × 25 mm.
Table 5-5 shows the values for the package thermal parameters for the 481-ball TFBGA
mounted on a 4-layer PCB.
Table 5-5 Package Thermal Data, 4-Layer PCB*
Airflow Value
Parameter
Definition
0 m/s
1 m/s
2 m/s
3 m/s
θJA
Thermal resistance: junction to
ambient (no heat sink)
16.2 C/W
13.9 C/W
13.0 C/W
12.6 C/W
θJA
Thermal resistance: junction to
ambient (with heat sink)
11.7 C/W
8.4 C/W
7.8 C/W
7.6 C/W
θJC
Thermal resistance: junction to
case
5.30 C/W
N/A
N/A
N/A
* All data is based on parts mounted on a 4” x 4.5” JEDEC 4L PCB.
Thermal Data
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5.5
AC Timing
This section discusses the following topics:
5.5.1

SATA

PCIe

Parallel Flash and NVSRAM
SATA
This product conforms to AC timing requirements as specified in the Serial ATA Revision 3.0
Specification (www.sata-io.org).
5.5.2
PCIe
This product conforms to AC timing requirements as specified in the PCIe® Base 2.0
specification (www.pcisig.com/).
5.5.3
Parallel Flash and NVSRAM
This section describes the timing for Parallel Flash and NVSRAM.
5-6
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Electrical Specifications
Figure 5-1 illustrates the Parallel Flash and NVSRAM Read timing, and Table 5-6 provides
parameter information for the timing diagram.
Figure 5-1 Parallel Flash / NVSRAM Read Timing
tRC
P_ADDR
Address Valid
tRCEH
CE_N
tRCEL
tOEH
OE_N
tOEL
P_DATA
Input Data Valid
tACC
Table 5-6 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing
Parameter
Description
tRC
Read Cycle Time
tRCEL
Read CE Assert Time
NVSRAM
Parallel Flash
Unit
ns
(NV_RD_CYCLE_TM
(FLSH_RD_CYCLE_TM
(R0C968h [7:0]) + 2) ×
Tclk
(R0C978h [7:0]) + 2) × Tclk
(NV_RD_CE_ASSRT_TM
(FLSH_RD_CE_ASSRT_TM
ns
(R0C96Ch [23:16]) + 1) × (R0C97Ch [23:16]) + 1) × Tclk
Tclk
tRCEH
Read CE Deassert Time
(NV_RD_CE_DEASSRT_T (FLSH_RD_CE_DEASSRT_TM ns
M (R0C96Ch [31:24]) + 2) (R0C97Ch [31:24]) + 2) × Tclk
× Tclk
tOEL
Read OE Assert Time
(NV_RD_OE_ASSRT_TM
(FLSH_RD_OE_ASSRT_TM
(R0C96Ch [7:0]) + 1) ×
Tclk
(R0C97Ch [7:0]) + 1) × Tclk
ns
tOEH
Read OE Deassert Time (NV_RD_OE_DEASSRT_T (FLSH_RD_OE_DEASSRT_TM ns
M (R0C96Ch [15:8]) + 2) × (R0C97Ch [15:8]) + 2) × Tclk
Tclk
tACC
Read Data Latch Time
(NV_RD_DATA_LTCH_TM (FLSH_RD_DATA_LTCH_TM
(R0C968h [15:8]) + 1) ×
Tclk - 20
ns
(R0C978h [15:8]) + 1) × Tclk 20
Note: Tclk—Internal system clock cycle, default value is 3.33ns.
AC Timing
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Figure 5-2 illustrates the Parallel Flash and NVSRAM Write timing, and Table 5-7 provides
parameter information for the timing diagram.
Figure 5-2 Parallel Flash / NVSRAM Write Timing
tWC
P_ADDR
Address Valid
tWCEH
CE_N
tWCEL
tWEH
WE_N
tWEL
P_DATA
Output Data Valid
tDL
tDH
Table 5-7 Timing Parameters for Figure 5-1, Parallel Flash / NVSRAM Read Timing
Parameter
Description
tWC
Write Cycle Time
tWCEL
tWCEH
NVSRAM
Write CE Assert Time
Write CE Deassert Time
Parallel Flash
Unit
ns
(NV_WRT_CYCLE_TM
(FLSH_WRT_CYCLE_TM
(R0C960h [7:0]) + 2) ×
Tclk
(R0C970h [7:0]) + 2) × Tclk
ns
(NV_CE_ASSRT_TM
(FLSH_CE_ASSRT_TM
(R0C960h [15:8]) + 1) ×
Tclk
(R0C970h [15:8]) + 1) × Tclk
(NV_CE_DEASSRT_TM
(FLSH_CE_DEASSRT_TM
ns
(R0C960h [23:16]) + 2) × (R0C970h [23:16]) + 2) × Tclk
Tclk
ns
tWEL
Write WE Assert Time
tWEH
Read WE Deassert Time (NV_WRT_WE_DEASSRT (FLSH_WRT_WE_DEASSRT_T ns
_TM (R0C964h [15:8]) + M (R0C974h [15:8]) + 2) × Tclk
2) × Tclk
tDL
Write Data IO Enable
Time
(NV_WRT_WE_ASSRT_T (FLSH_WRT_WE_ASSRT_TM
M (R0C964h [7:0]) + 1) × (R0C974h [7:0]) + 1) × Tclk
Tclk
(NV_WRT_DATA_IO_EN_ (FLSH_WRT_DATA_IO_EN_TM ns
TM (R0C964h [23:16]) + (R0C974h [23:16]) + 1) × Tclk
1) × Tclk
tDH
Write Data IO Disable
Time
(NV_WRT_DATA_IO_DSB (FLSH_WRT_DATA_IO_DSBL_ ns
L_TM (R0C964h [31:24]) TM (R0C974h [31:24]) + 2) ×
+ 2) × Tclk
5-8
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