Stratix IV GX FPGA Development Kit User Guide

Stratix IV GX FPGA Development Kit User Guide

Stratix IV GX FPGA Development Kit

User Guide

101 Innovation Drive

San Jose, CA 95134 www.altera.com

Document Version:

Document Date:

1.0

May 2009

Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services

.

UG-01061-1.0

Contents

Chapter 1. About This Kit

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Chapter 2. Getting Started

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Before You Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Inspect the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Quartus II Programmer System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Chapter 3. Software Installation

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Altera Complete Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Licensing Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1

Installing the Stratix IV GX Development Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2

Installing the USB-Blaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3

Chapter 4. Development Board Setup

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Chapter 5. Board Update Portal

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Connecting to the Board Update Portal Web Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Using the Board Update Portal to Update User Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2

Chapter 6. Board Test System

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1

Preparing the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3

Launching the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

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Using the Board Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

The Configure Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4

The Config Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

MAX-II Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Board Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5

The GPIO Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

User Dipswitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6

User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

Pushbutton Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

The SRAM&Flash Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

The DDR3 Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Number of addresses to write / read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

R/W control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

The QDRII+ Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10

Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Number of addresses to write / read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

The HSMC Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12

Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13

Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

Performance Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14

The Video Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

HDMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15

SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

Error Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

The Power Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17

MAX II Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–18

Temperature Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Power Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

12V Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Power Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Graph Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Calculating Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Configuring the FPGA Using Quartus II Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20

Appendix A. Programming the Flash Memory Device

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

CFI Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1

Preparing Design Files for Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Creating Flash Files Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2

Programming Flash Memory Using the Board Update Portal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Programming Flash Memory Using the Nios II EDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3

Restoring the Factory Design to the Flash Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

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© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

vi

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

1. About This Kit

Introduction

The Altera

®

Stratix

®

IV GX FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Stratix IV GX

FPGA designs. The PCI-SIG-compliant board and a one-year license for the

Quartus ® II software provide everything you need to begin prototyping for

Stratix IV GX FPGAs. The following list describes what you can accomplish with the development kit:

■ Develop and test PCI Express 2.0 designs using the PCI-SIG-compliant development board

Develop and test memory subsystems consisting of DDR3 and QDR II+ memory

Build designs capable of migrating to Altera’s low-cost HardCopy ® IV ASICs

Take advantage of the modular and scalable design by using the high-speed mezzanine card (HSMC) connectors to interface to one of over 20 different HSMCs provided by Altera partners, supporting protocols such as Serial RapidIO

®

,

10 Gigabit Ethernet, SONET, Common Public Radio Interface (CPRI), Open Base

Station Architecture Initiative (OBSAI) and others.

Kit Features

This section briefly describes the Stratix IV GX FPGA Development Kit contents.

Hardware

■ Stratix IV GX EP4SGX230 FPGA Development Board—A development platform that allows you to develop and prototype hardware designs running on the

Stratix IV GX FPGA.

f

For detailed information about board components and interfaces, refer to the

Stratix IV GX FPGA Development Board Reference Manual

.

Power Supply and Cables—The development kit includes the following items:

Power supply and AC adapters for North America, Japan, Europe, and the

United Kingdom

USB cable

Ethernet cable

SMB cable

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

1–2 Chapter 1: About This Kit

Kit Features

Software

■ Altera Complete Design Suite DVD—A DVD that includes the following items:

Quartus II Software—The Quartus II software, including the SOPC Builder system development tool, provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software integrates into nearly any design environment and provides interfaces to industry-standard EDA tools.

f

The kit includes a development kit edition (DKE) license for the Quartus II software (Windows platform only). This license entitles you to all the features of the subscription edition for a period of one year. After the year, you must purchase a renewal subscription to continue using the software.

For more information, refer to the Altera website ( www.altera.com

).

MegaCore ® IP Library—A library that contains Altera IP MegaCore functions.

You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following:

Simulate behavior of a MegaCore function within your system

Verify functionality of your design, and quickly and easily evaluate its size and speed

Generate time-limited device programming files for designs that include

MegaCore functions

Program a device and verify your design in hardware

1

The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only. You must purchase a license to use a MegaCore function in production.

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For more information about OpenCore Plus, refer to

AN 320: OpenCore

Plus Evaluation of Megafunctions

.

Nios ® II Embedded Design Suite (EDS)—A full-featured set of tools that allow you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs.

Stratix IV GX FPGA Development Kit CD-ROM—A CD-ROM that includes all the documentation and design examples for the kit.

f

Use the following links to check the Altera website to ensure you have the latest software versions:

For the Altera Complete Design Suite, refer to the Quartus II Subscription Edition

Download page.

For the Stratix IV GX FPGA Development Kit, refer to the Stratix IV GX FPGA

Development Kit page.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

2. Getting Started

Introduction

This user guide guides you through the Stratix IV GX development board setup.

Using this user guide, you can take the following actions:

Inspect the contents of the kit

Install the Altera Complete Design Suite DVD software

Set up, power up, and verify correct operation of the development board

Configure the Stratix IV GX FPGA

Run the Board Test System software and use the test designs f

For complete information about the development board, refer to the

Stratix IV GX

FPGA Development Board Reference Manual

.

Before You Begin

Before using the kit or installing the software, check the kit contents and inspect the board to verify that you received all of the items listed in this section. If any of the items are missing, contact Altera before you proceed.

Inspect the Board

To inspect the board, perform the following steps:

1. Place the board on an anti-static surface and inspect it to ensure that it has not been damaged during shipment.

c

Without proper anti-static handling, the Stratix IV GX development board can be damaged.

2. Verify that all components are on the board and appear intact.

1

In typical applications with the Stratix IV GX development board, a heat sink is not necessary. However, under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines. You can perform power consumption and thermal modeling to determine whether your application requires additional cooling.

f

For more information about power consumption and thermal modeling, refer to

AN 358: Thermal Management for FPGAs

.

Hardware Requirements

The kit provides all the hardware you need to use the board.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

2–2 Chapter 2: Getting Started

References

Software Requirements

The kit requires the following software:

Windows XP operating system

Quartus II Programmer (which can be installed from the Altera Complete Design

Suite DVD)

Quartus II Programmer System Requirements

The Quartus II Programmer has some minimum system requirements.

f

For Quartus II Programmer system requirements, refer to the Quartus II Web Edition

Software page on the Altera website.

References

Use the following links to check the Altera website for the following other related information:

For the latest board design files and reference designs, refer to the Stratix IV GX

FPGA Development Kit page.

For additional daughter cards available for purchase, refer to the Development

Board Daughtercards page.

For the Stratix IV device documentation, refer to the Literature: Stratix IV Devices page.

To purchase devices from the eStore, refer to the Devices page.

For Stratix IV GX OrCAD symbols, refer to the Capture CIS Symbols page.

For Nios II 32-bit embedded processor solutions, refer to the Embedded

Processing page.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

3. Software Installation

Introduction

This section explains how to install the following software:

Altera Complete Design Suite

Stratix IV GX Development Kit

■ USB-Blaster

driver

Before starting the installation, verify that you meet the conditions described in

“Software Requirements” on page 2–2

.

Installing the Altera Complete Design Suite

The Altera Complete Design Suite provides the necessary tools used for developing hardware and software for Altera FPGAs. Included in the Altera Complete Design

Suite DVD are the Quartus II software and the Nios II EDS installations. The

Quartus II software (including SOPC Builder) and the Nios II EDS are the primary

FPGA development tools used to create the reference designs in this development kit.

Although running this kit and the included example designs requires only the

Quartus II Programmer, creating new designs requires additional Altera software tools. To install the Altera software tools, perform the following steps:

1. Insert the Altera Complete Design Suite DVD into your computer.

2. Follow the installer instructions to complete the installation process.

f

If you have difficulty installing the Quartus II software, refer to the

Quartus II

Installation & Licensing for Windows and Linux Workstations

.

Licensing Considerations

Before using the Quartus II software, you must request a license file from the Altera

Licensing page on the Altera website and install it on your computer. When you request a license file, Altera emails you a

license.dat

file that enables the software.

To license the Quartus II software, you need your network interface card (NIC) ID, which is a 12-digit hexadecimal number that identifies your computer. On the computer you’ll use to run the Quartus II software, type ipconfig /all

at a command prompt to determine the NIC ID for your computer. Your NIC ID is the number on the physical address line, without the dashes.

To obtain a license, perform the following steps.

1. Go to the Get My Altera License page on the Altera website.

2. Under

Development Kit Licenses Request

, click

Licenses for RoHS-Compliant

Kits

.

3. Follow the on-screen instructions to request your license. You will receive a license file through email.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

3–2 Chapter 3: Software Installation

Installing the Stratix IV GX Development Kit

4. To install your license, refer to

Specifying the License File

in

Quartus II Installation &

Licensing for Windows and Linux Workstations

.

Installing the Stratix IV GX Development Kit

To install the Stratix IV GX Development Kit, perform the following steps:

1. Insert the Stratix IV GX Development Kit CD-ROM into your computer.

1

The CD-ROM should start an auto-install process. If it does not, browse to the CD-ROM drive and double-click on the

setup.exe

file.

2. Follow the on-screen instructions to complete the installation process.

The installation program creates the directory structure for the Stratix IV GX FPGA

Development Kit files shown in

Figure 3–1 .

Figure 3–1.

Stratix IV GX FPGA Kit Installed Directory Structure

<install dir>

The default Windows installation directory is

C:\altera\

<version>

\kits

.

stratixIVGX_4sgx230es_fpga board_design_files demos documents examples factory_recovery

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 3: Software Installation

Installing the USB-Blaster Driver

3–3

Table 3–1

lists the file directory names and a description of their contents.

Table 3–1.

Installed Directory Contents

Directory Name board_design_files demos documents examples factory_recovery

Description of Contents

Contains schematic, layout, assembly, and bill of material board design files. Use these files as a starting point for a new prototype board design.

Contains demonstration applications.

Contains the development kit documentation.

Contains the sample design files for the Stratix IV GX FPGA Development Kit.

Contains the original data programmed onto the board before shipment. Use this data to restore the board with its original factory contents.

Installing the USB-Blaster Driver

The Stratix IV GX FPGA board includes integrated USB-Blaster circuitry for FPGA programming. However, for the host computer and board to communicate, you must install the USB-Blaster driver on the host computer. To install the driver, follow the instructions on the USB-Blaster Driver for Windows XP page of the Altera website.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

3–4 Chapter 3: Software Installation

Installing the USB-Blaster Driver

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

4. Development Board Setup

Introduction

The instructions in this chapter explain how to set up the Stratix IV GX FPGA development board.

Powering Up the Board

To power up the board, perform the following steps:

1. Verify the rotary switch (SW2) is set to the 0 position.

2. Verify the settings for the JTAG DIP switch bank (SW6), located on the back of the

board, match Table 4–1 . These settings determine the devices to include in the

JTAG chain.

Table 4–1.

SW6 Dip Switch Settings

Switch Position

3

4

1

2

Off

On

On

On f

For more information about DIP switch settings on the board, refer to the

Stratix IV GX FPGA Development Board Reference Manual

.

3. Connect the DC adapter (+16 V, 3.75 A) to the DC power jack (J4) on the board and plug the cord into a power outlet.

c

Use only the supplied 16-V power supply. Power regulation circuitry on the board could be damaged by supplies greater than 16 V.

4. Set the POWER switch (SW1) to the ON position. When power is supplied to the board, a blue LED (D24) illuminates indicating that the board has power.

The development board ships with example designs stored in the flash memory device. The MAX II device on the board contains a parallel flash loader (PFL) megafunction. When the board powers up, the PFL reads one of two designs from flash memory and configures the FPGA. The rotary switch (SW2) controls which design to load. When the switch is in the 0 position, the PFL loads the design from the factory portion of flash memory. When the switch is in the 1 position, the PFL loads the design from the user portion of flash memory.

1

The development kit includes the MAX II configuration design in the <

install dir

>

\stratixIVGX_4sgx230es_fpga\examples\max2

directory.

When complete, the CONF DONE LED (D5) illuminates, signaling that the

Stratix IV GX device configured successfully.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

4–2 Chapter 4: Development Board Setup

Powering Up the Board f

For more information about the PFL megafunction, refer to

AN 386: Using the Parallel

Flash Loader with the Quartus II Software

.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

5. Board Update Portal

Introduction

The Stratix IV GX FPGA Development Kit ships with the Board Update Portal example design stored in the factory portion of the flash memory on the board. The design consists of a Nios II embedded processor, an Ethernet MAC, and an HTML web server.

When you power up the board with the rotary switch (SW2) set to the 0 position, the

Stratix IV GX FPGA configures with the Board Update Portal example design. The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network. The web page allows you to upload new FPGA designs to the user portion of flash memory, and provides links to useful information on the Altera website, including links to kit-specific and design resources.

1

After successfully updating the flash memory user design, you can load the user design from flash memory into the FPGA. To do so, set the rotary switch (SW2) to the

1 position and power cycle the board.

The source code for the Board Update Portal design resides in the <

install dir

>

\stratixIVGX_4sgx230es_fpga\examples

directory. If the Board Update Portal is corrupted or deleted from the flash memory, refer to

“Restoring the Factory Design to the Flash Device” on page A–4

to restore the board with its original factory contents.

Connecting to the Board Update Portal Web Page

This section provides instructions to connect to the Board Update Portal web page.

1

Before you proceed, ensure that you have the following:

A PC with a connection to a working Ethernet port on a DHCP enabled network.

A separate working Ethernet port connected to the same network for the board.

The Ethernet and power cables that are included in the kit.

To connect to the Board Update Portal web page, perform the following steps:

1. With the board powered down, set the rotary switch (SW2) to the 0 position.

2. Attach the Ethernet cable from the board to your LAN.

3. Power up the board. The board connects to the LAN’s gateway router, and obtains an IP address. The LCD on the board displays the IP address.

4. Launch a web browser on a PC that is connected to the same network, and enter the IP address from the LCD into the browser address bar. The Board Update

Portal web page appears in the browser.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

5–2 Chapter 5: Board Update Portal

Using the Board Update Portal to Update User Designs

5. Click

Stratix IV GX FPGA Development Kit

on the Board Update Portal web page and verify that you have the latest version of the development kit software

(the software version also appears on the CD-ROM).

1

If you download new software, double-click the downloaded

.exe

file to begin the installation process.

6. Visit the Board Update Portal web page occasionally for documentation updates and additional new designs not included on the CD-ROM.

f

If the Board Update Portal does not connect, refer to the Stratix IV GX FPGA

Development Kit page on the Altera website to determine if you have the latest kit software.

Using the Board Update Portal to Update User Designs

The Board Update Portal allows you to write new designs to the user portion of flash memory. Designs must be in the Nios II Flash Programmer File (

.flash

) format.

1

Design files available from the Stratix IV GX FPGA Development Kit page on the

Altera website include

.flash

files. You can also create

.flash

files from your own

custom design. Refer to “Preparing Design Files for Flash Programming” on page A–2

for information about preparing your own design for upload.

To upload a design over the network into the user portion of flash memory on your board, perform the following steps:

1. Perform the steps in

“Connecting to the Board Update Portal Web Page”

to access the Board Update Portal web page.

2. In the

Hardware File Name

field specify the

.flash

file that you either downloaded from the Altera website or created on your own. If there is a software component to the design, specify it in the same manner using the

Software File Name

field, otherwise leave the

Software File Name

field blank.

3. Click

Upload

. The progress bar indicates the percent complete.

4. To configure the FPGA with the new design after the flash memory upload process is complete, set the rotary switch (SW2) to the 1 position and power cycle the board (or press the CONFIGN button (S1) on the board).

1

As long as you don’t overwrite the factory image in the flash memory device, you can continue to use the Board Update Portal to write new designs to the user portion of flash memory. If you do overwrite the factory image, you can restore it by following

the instructions in “Restoring the Factory Design to the Flash Device” on page A–4

.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

6. Board Test System

Introduction

The kit includes an example design and application called the Board Test System to test the functionality of the Stratix IV GX FPGA development board. The application provides an easy-to-use interface to alter functional settings and observe the results.

You can use the application to test board components, modify functional parameters, observe performance, and measure power usage. The application is also useful as a reference for designing systems. To install the application, follow the steps in

“Installing the Stratix IV GX Development Kit” on page 3–2

.

The application provides access to the following Stratix IV GX FPGA Development

Board features:

General purpose I/O (GPIO)

SRAM

Flash memory

DDR3 memory

QDR II+ memory

High-speed mezzanine connectors (HSMC)

■ High-definition multimedia interface (HDMI) and serial digital interface (SDI) video

The application allows you to exercise most of the board components. While using the application, you reconfigure the FPGA several times with test designs specific to the functionality you are testing.

A GUI runs on the PC which communicates over the JTAG bus to a test design running in the Stratix IV GX device.

Figure 6–1

shows the initial GUI for a board that is in the factory configuration.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–2

Figure 6–1.

Board Test System Graphical User Interface

Chapter 6: Board Test System

Introduction

Several designs are needed for a complete test. Each design provides data for one or more tabs in the application. The Configure menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears and allows you to exercise the related board features. The components you are exercising highlight in the board picture in the GUI.

The

Power Tool

button starts the Power Monitor application that measures and reports current power and temperature information for the board. Because the tool communicates over the JTAG bus to the MAX II device, you can measure the power of any design in the FPGA, including your own design.

1

Both the Board Test System and Power Monitor applications take control of the JTAG bus. The Quartus II software cannot access the JTAG chain while these applications are in use. Be sure to close the applications before attempting to reconfigure the FPGA through the Quartus II Programmer or use the SignalTap ® II Embedded Logic

Analyzer.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Preparing the Board

6–3

Preparing the Board

With the power to the board off, perform the following steps:

1. Connect the USB cable to the board.

2. Set the rotary switch (SW2) to the 1 position.

3. Verify the settings for the board settings DIP switch bank (SW4) match Table 6–1 .

Table 6–1.

SW4 Dip Switch Settings

Switch Position

6

7

4

5

1

2

3

8

Off

On

On

On

Off

Off

On

On

4. Verify the settings for the JTAG DIP switch bank (SW6), located on the back of the

board, match Table 6–2 .

Table 6–2.

SW6 Dip Switch Settings

Switch Position

1

2

3

4

Off

On

On

On f

For more information about the board’s DIP switch settings, refer to the

Stratix IV GX FPGA Development Board Reference Manual

.

5. Turn the power to the board on. The board loads the design stored in the user portion of flash memory into the FPGA. If your board is still in the factory configuration or if you have downloaded a new version of the Board Test System to flash memory through the Board Update Portal, the design that tests the GPIO,

SRAM, and flash memory loads. c

To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application. The application cannot run correctly unless the USB cable is attached and the board is on.

© May 2009 Altera Corporation

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6–4 Chapter 6: Board Test System

Launching the Board Test System

Launching the Board Test System

To run the application, navigate to the <

install dir

>

\stratixIVGX_4sgx230es_fpga\examples\board_test_system

directory and launch the

BoardTestSystem.exe

application. A GUI appears, displaying the application tab that corresponds to the design running in the FPGA. The Stratix IV GX

FPGA development board’s flash memory ships preconfigured with the design that corresponds to the

Config

,

GPIO

, and

SRAM&Flash

tabs.

1

If you power up your board with the rotary switch (SW2) in a position other than the

1 position, or if you load your own design into the FPGA with the Quartus II

Programmer, you receive a message prompting you to configure your board with a valid Board Test System design. Refer to

“The Configure Menu”

for information about configuring your board.

Using the Board Test System

This section describes each menu, tab, and button in the Board Test System application.

The Configure Menu

Each test design tests different functionality and corresponds to one or more application tabs. Use the Configure menu to select the design you want to use.

Figure 6–2

shows the Configure menu.

Figure 6–2.

The Configure Menu

To configure the FPGA with a test system design, perform the following steps:

1. On the Configure menu, click the configure command that corresponds to the functionality you wish to test.

2. In the dialog box that appears, click

Configure

to download the corresponding design’s SRAM Object File (

.sof

) to the FPGA. The download process usually takes about a minute.

3. When configuration finishes, click

Close

to complete the configuration process and run the design in the FPGA. A corresponding application tab appears in the

GUI that interfaces with the design in the FPGA.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

6–5

The Config Tab

The

Config

tab shows information about the board’s current configuration.

Figure 6–1 on page 6–2 shows the

Config

tab. The tab displays the contents of the

MAX II registers, the MAX II code version, the JTAG chain, the board’s MAC address, and the flash memory map.

The following sections describe the controls on the

Config

tab.

MAX-II Registers

This control allows you to view and change the current MAX II register values as described in

Table 6–3

.

Table 6–3.

MAX II Registers

Register Name

Software Reset

(SRST)

Page Select Register

(PSR)

Page Select Override

(PSO)

Page Select Switch

(PSS)

Read/Write

Capability

Write only

Description

Set to 0 to initiate an FPGA reconfiguration.

Read / Write Determines the page of flash memory to use for FPGA reconfiguration.

Read / Write When set to 0, the PSR determines the page of flash memory to use for FPGA reconfiguration. When set to 1, the rotary switch (SW2) determines the page of flash memory to use for FPGA reconfiguration.

Read only Holds the current value of the rotary switch (SW2).

1

Because the

Config

tab requires that a specific design is running in the FPGA, writing a 0 to SRST might cause the application to stop running.

JTAG Chain

This control shows all the devices currently in the JTAG chain. The Stratix IV GX device is always the first device in the chain.

1

Putting DIP switch SW6.1 in the ON position removes the MAX II device from the

JTAG chain.

Board Information

MAX-II rev

—Indicates the version of MAX II code currently running on the board.

The MAX II code resides in the <

install dir

>

\stratixIVGX_4sgx230es_fpga\examples

directory. Newer revisions of this code might be available on the Stratix IV GX FPGA

Development Kit page of the Altera website.

MAC

—Indicates the MAC address of the board.

Flash Memory Map

This control shows the memory map of the flash memory device on your board.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–6 Chapter 6: Board Test System

Using the Board Test System

The GPIO Tab

The

GPIO

tab allows you to interact with all the general purpose user I/O components on your board. You can write to the LCD, read DIP switch settings, turn

LEDs on or off, and detect push button presses. Figure 6–3

shows the

GPIO

tab.

Figure 6–3.

The GPIO Tab

The following sections describe the controls on the

GPIO

tab.

LCD

This control allows you to display text strings on the LCD on your board. Type text in the text boxes and then click

Write

.

1

If you exceed the 16 character display limit on either line, a warning message appears.

User Dipswitch

This read-only control displays the current positions of the eight switches in the user

DIP switch bank (SW3). Change the switches on the board to see the graphical display change accordingly.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

6–7

User LEDs

This control displays the current state of the user LEDs. Click on the graphical representation of the LEDs to turn the board LEDs on and off.

Pushbutton Switches

This control displays the current state of the board push buttons. Depress a push button on the board to see the graphical display change accordingly.

The SRAM&Flash Tab

The

SRAM&Flash

tab allows you to read and write SRAM and flash memory on your

board. Figure 6–4

shows the

SRAM&Flash

tab.

Figure 6–4.

The SRAM&Flash Tab

The following sections describe the controls on the

SRAM&Flash

tab.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–8 Chapter 6: Board Test System

Using the Board Test System

SRAM

This control allows you to read and write the SRAM on your board. Type a starting address in the text box and click

Read

. Values starting at the specified address appear in the table. The SRAM addresses display in the format the Nios II processor within the FPGA uses, that is, each SRAM address is offset by 0x00400000. Thus, the first location in SRAM appears as 0x00400000 in the GUI.

1

If you enter an address outside of the 0x00400000 to 0x005FFFFF SRAM address space, a warning message identifies the valid SRAM address range.

To update the SRAM contents, change values in the table and click

Write

. The application writes the new values to SRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

Flash

This control allows you to read and write the flash memory on your board. Type a starting address in the text box and click

Read

. Values starting at the specified address appear in the table. The flash memory addresses display in the format the Nios II processor within the FPGA uses, that is, each flash memory address is offset by

0x04000000. Thus, the first location in flash memory appears as 0x04000000 in the

GUI.

1

If you enter an address outside of the 0x04000000 - 0x07FFFFFF flash memory address space, a warning message identifies the valid flash memory address range.

To update the flash memory contents, change values in the table and click

Write

. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

1

To prevent overwriting the dedicated portions of flash memory, the application limits the writable flash memory address range to 0x07FE0000 - 0x07FFFFFF (which corresponds to the unused flash memory address range of 0x03FE0000 - 0x03FFFFFF

shown in Figure 6–1 on page 6–2 and

Table A–1 on page A–1

.

The DDR3 Tab

The

DDR3

tab allows you to read and write the DDR3 memory on your board.

Figure 6–5

shows the

DDR3

tab.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

Figure 6–5.

The DDR3 Tab

6–9

The following sections describe the controls on the

DDR3

tab.

Port

This control directs communication to one of two DDR3 memory ports on your board.

A 16-bit interface connects to the top bank of the Stratix IV GX FPGA and a 64-bit interface connects to the bottom banks of the FPGA.

Start

This control initiates DDR3 memory transaction performance analysis.

Stop

This control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last pressed

Start

.

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6–10 Chapter 6: Board Test System

Using the Board Test System

Write

,

Read

, and

Total

performance bars—Show the percentage of maximum data rate that the requested transactions are able to achieve.

Write(MBytes/s)

,

Read(MBytes/s)

, and

Total(MBytes/s)

—Show the number of bytes of data analyzed per second.

Error Control

These controls track transaction errors detected during analysis.

Detected Errors

—Displays the number of transaction errors detected in the hardware.

Inserted Errors

—Displays the number of errors inserted into the transaction stream.

Insert Error

—Inserts a one-word error into the transaction stream each time you click the button.

Insert Error

is only enabled during transaction performance analysis.

Clear

—Resets the

Detected Errors

and

Inserted Errors

counters to zeros.

Number of addresses to write / read

This control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 2 to 524,288.

Data type

This control specifies the type of data contained in the transactions. The following data types are available for analysis:

PRBS

—Selects pseudo-random bit sequences.

Memory

—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

Math

—Selects data generated from a simple math function within the FPGA fabric.

R/W control

This control specifies the type of transactions to analyze. The following transaction types are available for analysis:

Read/Write

—Selects read and write transactions for analysis.

Read Only

—Selects read transactions for analysis.

Write Only

—Selects write transactions for analysis.

The QDRII+ Tab

The

QDRII+

tab allows you to independently test each QDR II+ port on your board.

Figure 6–6

shows the

QDRII+

tab.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

Figure 6–6.

The QDRII+ Tab

6–11

The following sections describe the controls on the

QDRII+

tab.

Port

This control directs communication to one of two QDR II+ ports on your board.

Start

This control initiates QDR II+ port transaction performance analysis.

Stop

This control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last pressed

Start

.

Write

and

Read

performance bars—Show the percentage of maximum data rate that the requested transactions are able to achieve.

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Using the Board Test System

Write(MBytes/s)

and

Read(MBytes/s)

—Show the number of bytes of data analyzed per second.

Error Control

These controls track transaction errors detected during analysis.

Detected Errors

—Displays the number of transaction errors detected in the hardware.

Inserted Errors

—Displays the number of errors inserted into the transaction stream.

Insert Error

—Inserts a one-word error into the transaction stream each time you click the button.

Insert Error

is only enabled during transaction performance analysis.

Clear

—Resets the

Detected Errors

and

Inserted Errors

counters to zeros.

Number of addresses to write / read

This control determines the number of addresses to use in each iteration of reads and writes. Valid values range from 2 to 524,288.

Data type

This control specifies the type of data contained in the transactions. The following data types are available for analysis:

PRBS

—Selects pseudo-random bit sequences.

Memory

—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

Math

—Selects data generated from a simple math function within the FPGA fabric.

The HSMC Tab

The

HSMC

tab allows you to perform loopback tests on the HSMC A and HSMC B.

Figure 6–7

shows the

HSMC

tab.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

Figure 6–7.

The HSMC Tab

6–13

1

You must have the loopback HSMC installed on the HSMC connector that you are testing for this test to succeed.

The following sections describe the controls on the

HSMC

tab.

Status

This control displays status information during the loopback test.

PLL Lock

—Shows the PLL locked or unlocked state.

Channel Lock

—Shows the channel locked or unlocked state. When locked, all lanes are aligned and bonded.

Pattern Sync

—Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.

Port

This control allows you to specify the type of test to run on the HSMC ports. The following HSMC port tests are available:

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–14 Chapter 6: Board Test System

Using the Board Test System

HSMA x4 Tranceivers [0..3]

HSMA x4 Tranceivers [4..7]

HSMB x4 Tranceivers [0..3]

HSMB x2 Tranceivers [4..5]

HSMA x17 LVDS SERDES

HSMB x17 LVDS SERDES

HSMA x3 Single Ended Loopback

HSMB x3 Single Ended Loopback

Data type

This control specifies the type of data contained in the transactions. The following data types are available for analysis:

PRBS

—Selects pseudo-random bit sequences.

Memory

—Selects a generic data pattern stored in the on chip memory of the

Stratix IV GX device.

Math

—Selects data generated from a simple math function within the FPGA fabric.

Error Control

These controls track transaction errors detected during analysis.

Detected Errors

—Displays the number of transaction errors detected in the hardware.

Inserted Errors

—Displays the number of errors inserted into the transaction stream.

Insert Error

—Inserts a one-word error into the transaction stream each time you click the button.

Insert Error

is only enabled during transaction performance analysis.

Clear

—Resets the

Detected Errors

and

Inserted Errors

counters to zeros.

Start

This control initiates HSMC transaction performance analysis.

Stop

This control terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last pressed

Start

.

TX

and

RX

performance bars—Show the percentage of maximum data rate that the requested transactions are able to achieve.

Tx(MBytes/s)

and

Rx(MBytes/s)

—Show the number of bytes of data analyzed per second.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

Using the Board Test System

6–15

The Video Tab

The

Video

tab allows you to test the HDMI and SDI video interfaces on your board.

Figure 6–8

shows the

Video

tab.

Figure 6–8.

The Video Tab

The following sections describe the controls on the

Video

tab.

HDMI

Testing the HDMI requires connecting a monitor with at least UXGA (1600 × 1200) resolution to your board. Once connected, the following controls define the output to the monitor.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–16 Chapter 6: Board Test System

Using the Board Test System

Color Bar Test Pattern

—Specifies the test pattern to output to the monitor. The following choices are available:

Color Bar

Red

Green

Blue

Table 6–4

shows the color bar test pattern and corresponding color names and RGB values.

Table 6–4.

HDMI Color Bar Test Pattern

Color Bars Color

White/Grey

Yellow

Cyan

Green

Magenta

Red

Blue

Black

RGB Values

180,180,180

180,180,16

16,180,180

16,180,16

180,16,180

180,16,16

16,16,180

16,16,16

Resolution

—Specifies the resolution to output to the monitor. The following choices are available:

1080p (1920 × 1080 progressive)

720p (1280 × 720 progressive)

Start

—Initiates the test.

Stop

—Terminates the test.

Get EDID

—Reads the extended display information data (EDID) from the monitor and displays the results.

SDI

Testing the SDI requires connecting a SMB loopback cable as shown in

Figure 6–9

.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

The Power Monitor

Figure 6–9.

Board with SMB Loopback Cable

6–17

Once connected, the following controls are available.

Reset

This control restarts the test.

Load

This control passes a new seed value to the PRBS generator on the device.

Status

These controls display status information during the loopback test.

Tx PLL

—Shows whether the Tx PLL is locked or unlocked.

Rx PLL

—Shows whether the Rx PLL is locked or unlocked.

Error Status

—Shows “No Error Detected” when the test is running correctly; otherwise shows pertinent error.

Error Control

These controls track transaction errors detected during analysis.

Errors

—Displays the number of errors detected in the hardware.

Insert Error

—Inserts a one-word error into the transaction stream each time you click the button.

Clear

—Resets the

Errors

counter to zero.

The Power Monitor

The Power Monitor measures and reports current power and temperature information for the board. To start the tool, click

Power Tool

in the Board Test System application.

1

You can also run this tool as a stand-alone application.

PowerTool.exe

resides in the

<

install dir

>

\stratixIVGX_4sgx230es_fpga\examples\board_test_system

directory.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–18 Chapter 6: Board Test System

The Power Monitor

The Power Monitor communicates to the MAX II device on the board through the

JTAG bus. A power monitor circuit attached to the MAX II device allows you to measure the power that the Stratix IV GX FPGA device is consuming no matter what

design is currently running. Figure 6–10 shows the Power Monitor.

Figure 6–10.

The Power Monitor

The following sections describe the Power Monitor controls.

MAX II Information

These controls display information about the MAX II device.

MAX II Version

—Indicates the version of MAX II code currently running on the board. The MAX II code resides in the <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery

directory. Newer revisions of this code might be available on the Stratix IV GX FPGA Development Kit page of the

Altera website.

Power Rail

—Indicates the currently-selected power rail. The rotary switch (SW2) on your board controls which rail to measure. After setting the switch for the desired rail, click

Reset

to refresh the screen with new board readings.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter 6: Board Test System

The Power Monitor

6–19

f

A table of the power rail switch positions is available in the

Stratix IV GX

FPGA Development Board Reference Manual

.

Temperature Information

These controls display temperature readings for the board and the FPGA on the board.

FPGA

—Indicates the temperature of the FPGA device.

Board

—Indicates the overall board temperature.

Power Information

This control displays current, maximum, and minimum power readings for the following units:

■ mVolts mAmps mWatts

12V Power Consumption

This control displays 12V power consumption readings for the following units:

■ mAmps mWatts

Power Graph

This control displays the mWatt power consumption of your board over time. The green line indicates the current value. The red line indicates the maximum value read since the last reset. Yellow line indicates the minimum value read since last reset.

Graph Setting

These controls allow you to define the look and feel of the power graph.

Scale Select

—Specifies the amount to scale the power graph. Select a smaller number to zoom in to see finer detail. Select a larger number to zoom out to see the entire range of recorded values.

Update Speed

—Specifies how often to refresh the graph.

Reset

This control clears the graph, resets the minimum and maximum values, and restarts the Power Monitor.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

6–20 Chapter 6: Board Test System

Calculating Power

Calculating Power

The Power Monitor calculates power by measuring two different voltages with the

LT2418 A/D and applying the equation

P

=

V

×

I

to determine the power consumption. The LT2418 measures the voltage after the appropriate sense resistor

(

Vsense

) and the voltage drop across that sense resistor (

Vdif

). The current (

I

) is calculated by dividing the measured voltage drop across the resistor by the value of the sense resistor (

I

=

Vdif

/

R

). Through substitution, the equation for calculating power becomes

P

=

V

×

I

=

Vsense

× (

Vdif

/

R

) = (

Vsense

) × (

Vdif

) × (1/.003).

You can verify the power numbers shown in the Power Monitor with a digital multimeter that is capable of measuring microvolts to ensure you have enough significant digits for an accurate calculation. Measure the voltage on one side of the resistor (the side opposite the power source) and then measure the voltage on the other side. The first measurement is

Vsense

and the difference between the two measurements is

Vdif

. Plug the values into the equation to determine the power consumption.

Configuring the FPGA Using Quartus II Programmer

You can use the Quartus II Programmer to configure the FPGA with a specific

.sof

.

Before configuring the FPGA, ensure that the Quartus II Programmer and the

USB-Blaster driver are installed on the host computer, the USB cable is connected to the development board, power to the board is on, and no applications that use the

JTAG chain are running.

To configure the Stratix IV GX FPGA, perform the following steps:

1. Start the Quartus II Programmer.

2. Click

Add File

and select the path to the desired

.sof

.

3. Turn on the

Program/Configure

option for the added file.

4. Click

Start

to download the selected file to the FPGA. The FPGA is configured when the progress bar reaches 100%.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

A. Programming the Flash Memory

Device

Introduction

As you develop your own project using the Altera tools, you can program the flash memory device so that your own user design loads from flash memory into the FPGA on power up. This appendix describes the preprogrammed contents of the common flash interface (CFI) flash memory device on the Stratix IV GX FPGA Development

Board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device.

The Stratix IV GX FPGA Development Board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board

Update Portal example design and a default user configuration for running the Board

Test System demonstration. There are several other factory software files written to the CFI flash device to support the Board Update Portal. These software files were created using the Nios II EDS, just as the hardware design was created using the

Quartus II software.

f

For more information about Altera development tools, refer to the Design Software page on the Altera website.

CFI Flash Memory Map

Table A–1 shows the default memory contents of the CFI flash device. This memory

map must be maintained for the Board Update Portal to run correctly and to update designs in the user memory.

Table A–1.

Byte Address Flash Memory Map—512-Mbit (64-MByte) Flash Intel PC48F4400P0VB00

Block Description

Unused

Unused

Unused

Unused

User software

Factory software zipfs (html, web content)

User hardware

Factory hardware

PFL option bits

Board information

Ethernet option bits

User design reset vector

Size

32 KB

32 KB

32 KB

32 KB

24,320 KB

8,192 KB

8,192 KB

12,288 KB

12,288 KB

32 KB

32 KB

32 KB

32 KB

Address Range

0x03FF8000 - 0x03FFFFFF

0x03FF0000 - 0x03FF7FFF

0x03FE8000 - 0x03FEFFFF

0x03FE0000 - 0x03FE7FFF

0x02820000 - 0x03FDFFFF

0x02020000 - 0x0281FFFF

0x01820000 - 0x0201FFFF

0x00C20000 - 0x0181FFFF

0x00020000 - 0x00C1FFFF

0x00018000 - 0x0001FFFF

0x00000000 - 0x00017FFF

0x00008000 - 0x0000FFFF

0x00000000 - 0x00007FFF

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

A–2

Preparing Design Files for Flash Programming c

Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools or deliberately overwriting the factory design. If you unintentionally overwrite the factory hardware or factory software image, refer to

“Restoring the Factory Design to the Flash Device” on page A–4

.

Preparing Design Files for Flash Programming

You can obtain designs containing prepared

.flash

files from the Stratix IV GX FPGA

Development Kit page on the Altera website or create

.flash

files from your own custom design.

The Nios II EDS

sof2flash

command line utility converts your Quartus II-compiled

.sof

into the

.flash

format necessary for the flash device. Similarly, the Nios II EDS

elf2flash

command line utility converts your compiled and linked Executable and

Linking Format File (

.elf

) software design to

.flash

. After your design files are in the

.flash

format, use the Board Update Portal or the Nios II EDS

nios2-flashprogrammer

utility to write the

.flash

files to the user hardware and user software locations of the flash memory.

f

For more information about Nios II EDS software tools and practices, refer to the

Embedded Software Development page on the Altera website.

Creating Flash Files Using the Nios II EDS

If you have an FPGA design developed using the Quartus II software, and software developed using the Nios II EDS, follow these instructions:

1. On the Windows Start menu, click

All Programs

>

Altera

>

Nios II EDS

>

Nios II

Command Shell

.

2. In the Nios II command shell, navigate to the directory where your design files reside and type the following Nios II EDS commands:

For Quartus II

.sof

files: sof2flash --input=yourfile_hw.sof --output=yourfile_hw.flash --offset=0xC20000 r

For Nios II

.elf

files: elf2flash --base=0x0A000000 --end=0x0BFFFFFF --reset=0x0A820000 --input=yourfile_sw.elf

-–output=yourfile_sw.flash -boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec r

The resulting

.flash

files are ready for flash device programming. If your design uses additional files such as image data or files used by the runtime program, you must first convert the files to

.flash

format and concatenate them into one

.flash

file before using the Board Update Portal to upload them.

1

The Board Update Portal standard

.flash

format conventionally uses either

<

filename

>

_hw.flash

for hardware design files or <

filename

>

_sw.flash

for software design files.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Chapter :

Programming Flash Memory Using the Board Update Portal

A–3

Programming Flash Memory Using the Board Update Portal

Once you have the necessary

.flash

files, you can use the Board Update Portal to reprogram the flash memory. Refer to

“Using the Board Update Portal to Update User

Designs” on page 5–2

for more information.

1

If you have generated a

.sof

using the Quartus II software that operates without a software design file, you can still use the Board Update Portal to upload your design.

In this case, leave the

Software File Name

field blank.

Programming Flash Memory Using the Nios II EDS

The Nios II EDS offers a

nios2-flash-programmer

utility to program the flash memory directly. To program the

.flash

files or any compatible S-Record File (

.srec

) to the board using

nios2-flash-programmer

, perform the following steps:

1. Set the rotary switch (SW2) to the 0 position to load the Board Update Portal design from flash memory on power up.

2. Attach the USB-Blaster cable and power up the board.

3. If the board has powered up and the LCD displays either "Connecting..." or a valid

IP address (such as 152.198.231.75), proceed to step 8. If no output appears on the

LCD is seen or if the CONF DONE LED (D5) does not illuminate, continue to step

4 to load the FPGA with a flash-writing design.

4. Launch the Quartus II Programmer to configure the FPGA with a

.sof

capable of flash programming. Refer to

“Configuring the FPGA Using Quartus II

Programmer” on page 6–20

for more information.

5. Click

Add File

and select <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery\stratixIVGX_4sgx230es_de v_bup.sof

.

6. Turn on the

Program/Configure

option for the added file.

7. Click

Start

to download the selected configuration file to the FPGA. Configuration is complete when the progress bar reaches 100% and the CONF DONE LED (D5) and the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is ready for programming.

8. On the Windows Start menu, click

All Programs

>

Altera

>

Nios II EDS

>

Nios II

Command Shell

.

9. In the Nios II command shell, navigate to the <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery

directory (or to the directory of the

.flash

files you created in

“Creating Flash Files Using the Nios II EDS” on page A–2 ) and type the following Nios II EDS command:

nios2-flash-programmer --base=0x08000000 yourfile_hw.flash r

10. After programming completes, if you have a software file to program, type the following Nios II EDS command: nios2-flash-programmer --base=0x0A000000 yourfile_sw.flash r

11. Set the rotary switch (SW2) to the 1 position and power cycle the board to load and run the new user design.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

A–4

Restoring the Factory Design to the Flash Device

Programming the board is now complete.

f

For more information about the

nios2-flash-programmer

utility, refer to the

Nios II

Flash Programmer User Guide

.

Restoring the Factory Design to the Flash Device

To restore the flash memory device on the development board with its original factory contents, reprogram the contents using the following instructions. Make sure you have the Nios II EDS installed, and perform the instructions in this section.

1. Launch the Quartus II Programmer to configure the FPGA with a

.sof

capable of flash programming. Refer to

“Configuring the FPGA Using Quartus II

Programmer” on page 6–20

for more information.

2. Click

Add File

and select <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery\stratixIVGX_4sgx230es_de v_bup.sof

.

3. Turn on the

Program/Configure

option for the added file.

4. Click

Start

to download the selected configuration file to FPGA. The FPGA is configured when the progress bar reaches 100% and the CONF DONE LED (D5) and the eight lower user LEDs (D16-D23) illuminate indicating that the flash device is ready for programming.

5. On the Windows Start menu, click

All Programs

>

Altera

>

Nios II EDS

>

Nios II

Command Shell

.

6. In the Nios II command shell, navigate to the <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery

directory and type the following command to run the restore script:

./restore.sh r

Restoring the flash memory might take several minutes.

7. After all flash programming completes, cycle the POWER switch (SW1) OFF then

ON.

8. Using the Quartus II Programmer, click

Add File

and select <

install dir

>

\stratixIVGX_4sgx230es_fpga\factory_recovery\stratixIVGX_4sgx230es_de v_bup.sof

.

9. Turn on the

Program/Configure

option for the added file.

10. Click

Start

to download the selected configuration file to FPGA. The FPGA is configured when the progress bar reaches 100% and the CONF DONE LED (D5) and the eight lower user LEDs (D16-D23) illuminate indicating the flash memory device is now restored with the factory contents.

11. Cycle the POWER switch (SW1) OFF then ON to load and run the restored factory design.

f

To ensure that you have the most up-to-date factory restore files and information about this product, refer to the Altera Development Kits page on the Altera website.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

Additional Information

Revision History

The following table displays the revision history for this user guide.

Date & Document

Version

May 2009 v1.0

Initial release.

Changes Made Summary of Changes

How to Contact Altera

For the most up-to-date information about Altera products, refer to the following table.

Contact

(Note 1)

Contact

Method

Technical support

Technical training

Website

Website

Email

Product literature Website

Non-technical support (General) Email

(Software Licensing) Email

Address

www.altera.com/support www.altera.com/training [email protected]

www.altera.com/literature [email protected]

[email protected]

Note to Table:

(1) You can also contact your local Altera sales office or sales representative.

Typographic Conventions

This document uses the typographic conventions shown in the following table.

Visual Cue Meaning

Bold Type with Initial Capital

Letters bold type

Indicates command names, dialog box titles, dialog box options, and other GUI labels. For example,

Save As

dialog box.

Indicates directory names, project names, disk drive names, file names, file name extensions, and software utility names. For example,

\qdesigns

directory,

d:

drive, and

chiptrip.gdf

file.

Italic Type with Initial Capital Letters

Indicates document titles. For example,

AN 519: Stratix IV Design Guidelines.

Italic type

Indicates variables. For example,

n

+ 1.

Initial Capital Letters

Variable names are enclosed in angle brackets (< >). For example,

<file name>

and

<project name>

.pof

file.

Indicates keyboard keys and menu names. For example, Delete key and the Options menu.

© May 2009 Altera Corporation

Stratix IV GX FPGA Development Kit User Guide

Info–2

Visual Cue

“Subheading Title”

Courier type

1., 2., 3., and a., b., c., and so on.

1 c w r f

Additional Information

Typographic Conventions

Meaning

Quotation marks indicate references to sections within a document and titles of

Quartus II Help topics. For example, “Typographic Conventions.”

Indicates signal, port, register, bit, block, and primitive names. For example, data1

, tdi

, and input

. Active-low signals are denoted by suffix n

. For example, resetn

.

Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf

.

Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword

SUBDESIGN

), and logic function names (for example,

TRI

).

Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.

Bullets indicate a list of items when the sequence of the items is not important.

The hand points to information that requires special attention.

A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.

A warning calls attention to a condition or possible situation that can cause you injury.

The angled arrow instructs you to press Enter.

The feet direct you to more information about a particular topic.

Stratix IV GX FPGA Development Kit User Guide

© May 2009 Altera Corporation

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