DSP56311 User's Manual

DSP56311 User's Manual
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
DSP56311 User’s Manual
24-Bit Digital Signal Processor
DSP56311UM/D
Revision 1.0, October 1999
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
OnCEÉ and Mfax are trademarks of Motorola, Inc. Intel“ is a registered trademark of the Intel Corporation. All other
trademarks are those of their respective owners.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function, or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use
as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain
life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and
suitability of its product or products for the use intended. Motorola and
are registered trademarks of Motorola, Inc.
Motorola, Inc. is an Equal Employment Opportunity /Affirmative Action Employer.
How to reach us:
USA/Europe/Locations Not Listed:
Motorola Literature Distribution
P.O. Box 5405
Denver, Colorado 80217
1 (800) 441-2447
1 (303) 675-2140
Asia/Pacific:
Motorola Semiconductors H.K. Ltd.
8B Tai Ping Industrial Park
51 Ting Kok Road
Tai Po, N.T., Hong Kong
852-26629298
Japan:
Nippon Motorola Ltd
SPD, Strategic Planning Office141
4-32-1, Nishi-Gotanda
Shinagawa-ku, Japan
81-3-5487-8488
Motorola Fax Back System (Mfax™):
TOUCHTONE (602) 244-6609
1 (800) 774-1848
[email protected]
Technical Resource Center:
1 (800) 521-6274
Internet:
http://www.motorola-dsp.com/
DSP Helpline
[email protected]
È
For More Information On This Product,
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MOTOROLA INC., 1999
Freescale Semiconductor, Inc.
Contents
Freescale Semiconductor, Inc...
Chapter 1
Overview
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.1.1
1.5.1.2
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.6
1.7
1.8
1.9
1.9.1
1.9.2
1.9.3
1.9.4
1.9.5
1.9.6
Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
DSP56300 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
PLL and Clock Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Off-Chip Memory Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
GPIO Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
HI08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
EFCOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Chapter 2
Signals/Connections
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.7
Motorola
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
External Memory Expansion Port (Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
External Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
HI08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
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2.8
2.9
2.10
2.11
2.12
Enhanced Synchronous Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced Synchronous Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG and OnCE Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-14
2-17
2-19
2-19
2-20
Freescale Semiconductor, Inc...
Chapter 3
Memory Configuration
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
3.5
3.6
Program Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Switch Modes—Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
X Data Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Switch Modes—X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal X I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Y Data Memory Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Switch Modes—Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Y I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Y I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sixteen-Bit Compatibility Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-1
3-2
3-3
3-3
3-3
3-3
3-4
3-5
3-5
3-5
3-6
3-7
3-7
3-7
3-8
3-8
Chapter 4
Core Configuration
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Motorola
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Interrupt Sources and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Interrupt Priority Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
DMA Request Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Status Register (SR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Device Identification Register (IDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Address Attribute Registers (AAR0–AAR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
JTAG Boundary Scan Register (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
DSP56311 User’s Manual
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Freescale Semiconductor, Inc...
Chapter 5
Programming the Peripherals
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Peripheral Initialization Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mapping the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reading Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advantages and Disadvantages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port D Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple Timer Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-2
5-2
5-3
5-3
5-3
5-5
5-6
5-6
5-6
5-7
5-8
5-8
5-9
Chapter 6
Host Interface (HI08)
6.1
6.1.1
6.1.2
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.7
6.7.1
6.7.2
Motorola
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
DSP Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Host Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Software Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Core Interrupts and Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Core DMA Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Host Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Boot-up Using the HI08 Host Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
DSP Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Host Control Register (HCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Host Data Direction Register (HDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Host Base Address Register (HBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Host Port Control Register (HPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Host Transmit Data Register (HTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Host Receive Data Register (HRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
DSP-Side Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Host Programmer’s Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Command Vector Register (CVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Contents
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6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.8
Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Byte Registers (RXH: RXM: RXL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-28
6-30
6-30
6-30
6-31
6-32
Freescale Semiconductor, Inc...
Chapter 7
Enhanced Synchronous Serial Interface (ESSI)
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.6
7.6.1
7.6.2
7.6.3
Motorola
ESSI Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
ESSI Data and Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Serial Transmit Data Signal (STD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Serial Receive Data Signal (SRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Serial Control Signal (SC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Serial Control Signal (SC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Serial Control Signal (SC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
ESSI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
Operating Modes: Normal, Network, and On-Demand. . . . . . . . . . . . . . . . . . . . . . . 7-10
Normal/Network/On-Demand Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Synchronous/Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Frame Sync Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
Frame Sync Length for Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Word Length Frame Sync and Data Word Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Frame Sync Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Byte Format (LSB/MSB) for the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
ESSI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
ESSI Receive Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
ESSI Receive Data Register (RX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
ESSI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
ESSI Transmit Data Registers (TX[2 – 0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
ESSI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Receive Slot Mask Registers (RSMA, RSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
GPIO Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Port Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Port Direction Register (PRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Port Data Register (PDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
DSP56311 User’s Manual
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Freescale Semiconductor, Inc...
Chapter 8
Serial Communication Interface (SCI)
8.1
8.1.1
8.1.2
8.1.3
8.1.3.1
8.1.3.2
8.1.3.3
8.1.3.4
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.4.1
8.4.2
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.4.1
8.6.4.2
8.7
8.7.1
8.7.2
8.7.3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Transmitting Data and Address Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Wired-OR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Idle Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Address Mode Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Receive Data (RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Transmit Data (TXD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI Serial Clock (SCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Preamble, Break, and Data Transmission Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Bootstrap Loading Through the SCI (Operating Mode 6). . . . . . . . . . . . . . . . . . . . . . 8-7
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
SCI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
SCI Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
SCI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
SCI Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
SCI Receive Register (SRX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
SCI Transmit Register (STX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
GPIO Signals and Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Port E Data Register (PDRE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Chapter 9
Triple Timer Module
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
9.3.1.4
Motorola
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Timer After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Timer Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Timer Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Triple Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Timer GPIO (Mode 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Timer Pulse (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Timer Toggle (Mode 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Timer Event Counter (Mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Contents
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9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.3.3
9.3.4
9.3.4.1
9.3.4.2
9.3.4.3
9.3.5
9.3.6
9.4
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
Signal Measurement Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulse Width Modulation (PWM, Mode 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Toggle (Mode 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple Timer Module Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prescalar Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Prescalar Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Prescalar Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-11
9-12
9-13
9-15
9-16
9-18
9-19
9-20
9-21
9-21
9-21
9-21
9-21
9-23
9-24
9-24
9-29
9-30
9-30
Chapter 10
Enhanced Filter Coprocessor (EFCOP)
10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2
Architecture Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.2.1 PMB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.2 EFCOP Memory Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.2.3 Filter Multiplier and Accumulator (FMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3
EFCOP Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.3.1 Filter Data Input Register (FDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.2 Filter Data Output Register (FDOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.3 Filter K-Constant Input Register (FKIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.4 Filter Count (FCNT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.3.5 EFCOP Control Status Register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.3.6 EFCOP ALU Control Register (FACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.3.7 EFCOP Data Base Address (FDBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.3.8 EFCOP Coefficient Base Address (FCBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.3.9 Decimation/Channel Count Register (FDCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.3.10 EFCOP Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.4
EFCOP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5
Operation Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.1 FIR Filter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
10.5.1.1 Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.1.1.1
Adaptive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.1.1.2
Multichannel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17
10.5.1.1.3
Complex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
Motorola
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10.5.1.1.4
Alternating Complex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.1.1.5
Magnitude Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.1.1.6
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.1.1.7
Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.5.2 IIR Filter Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6
Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7
Examples of Use in Different Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.1 Real FIR Filter: Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.1.1 DMA Input/DMA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.1.2 DMA Input/Polling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.1.3 DMA Input/Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.2 Real FIR Filter With Decimation by M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.3 Adaptive FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.3.1 Implementation Using Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.7.3.2 Implementation Using DMA Input and Interrupt Output . . . . . . . . . . . . . . . . . . .
10.7.3.3 Updating an FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8
Verification For All Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.1 Input Sequence (input.asm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.2 Filter Coefficients (coefs.asm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.3 Output Sequence for Examples D-1, D-2, and D-3 . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.4 Desired Signal for Example D-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.8.5 Output Sequence for Example D-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-18
10-19
10-19
10-19
10-20
10-21
10-22
10-22
10-23
10-26
10-28
10-30
10-31
10-33
10-34
10-34
10-37
10-37
10-38
10-39
10-39
10-40
Appendix A
Bootstrap Program
A.1
A.2
A.3
Bootstrap Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Internal I/O Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
Interrupt Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
Appendix B
Programming Reference
B.1
B.2
B.3
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Interrupt Sources and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
INDEX
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Contents
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DSP56311 User’s Manual
For More Information On This Product,
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x
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Figures
Figure1-1.
Figure 2-1.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 3-14.
Figure 3-15.
Figure 3-16.
Figure 3-17.
Figure 3-18.
Figure 3-19.
Figure 3-20.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Motorola
DSP56311 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Signals Identified by Functional Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Memory Switch Off, Cache Off, 24-Bit Mode (Default) . . . . . . . . . . . . . . . . 3-9
Memory Switch Off, Cache On, 24-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . 3-10
Memory Switch On (MSW = 00), Cache Off, 24-Bit Mode . . . . . . . . . . . . 3-11
Memory Switch On (MSW = 00), Cache On, 24-Bit Mode . . . . . . . . . . . . . 3-12
Memory Switch On (MSW = 01), Cache Off, 24-Bit Mode . . . . . . . . . . . . 3-13
Memory Switch On (MSW = 01), Cache On, 24-Bit Mode . . . . . . . . . . . . . 3-14
Memory Switch On (MSW = 10), Cache Off, 24-Bit Mode . . . . . . . . . . . . 3-15
Memory Switch On (MSW = 10), Cache On, 24-Bit Mode . . . . . . . . . . . . . 3-16
Memory Switch On (MSW = 11), Cache Off, 24-Bit Mode . . . . . . . . . . . . 3-17
Memory Switch On (MSW = 11), Cache On, 24-Bit Mode . . . . . . . . . . . . . 3-18
Memory Switch Off, Cache Off, 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . 3-19
Memory Switch Off, Cache On, 16-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . 3-20
Memory Switch On (MSW = 00), Cache Off, 16-Bit Mode . . . . . . . . . . . . 3-21
Memory Switch On (MSW = 00), Cache On, 16-Bit Mode . . . . . . . . . . . . . 3-22
Memory Switch On (MSW = 01), Cache Off, 16-Bit Mode . . . . . . . . . . . . 3-23
Memory Switch On (MSW = 01), Cache On, 16-Bit Mode . . . . . . . . . . . . . 3-24
Memory Switch On (MSW = 10), Cache Off, 16-Bit Mode . . . . . . . . . . . . 3-25
Memory Switch On (MSW = 10), Cache On, 16-Bit Mode . . . . . . . . . . . . . 3-26
Memory Switch On (MSW = 11), Cache Off, 16-Bit Mode . . . . . . . . . . . . 3-27
Memory Switch On (MSW = 11), Cache On, 16-Bit Mode . . . . . . . . . . . . . 3-28
Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . . . . . . . . . . . 4-7
Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . . . . . . . . . . . 4-7
DSP56311 Operating Mode Register (OMR) Format . . . . . . . . . . . . . . . . . . 4-11
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Identification Register Configuration (Revision 0) . . . . . . . . . . . . . . . . . . . . 4-22
Address Attribute Registers (AAR0–AAR3)
(X:$FFFFF9–$FFFFF6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
JTAG Identification Register Configuration (Revision 0). . . . . . . . . . . . . . . 4-25
Memory Mapping of Peripherals Control Registers . . . . . . . . . . . . . . . . . . . . 5-2
Port B Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Port C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
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Figures
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 6-7.
Figure 6-8.
Figure 6-9.
Figure 6-10.
Figure 6-11.
Figure 6-12.
Figure 6-13.
Figure 6-14.
Figure 6-15.
Figure 6-16.
Figure 6-17.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 7-7.
Figure 7-8.
Figure 7-9.
Figure 7-10.
Figure 7-11.
Figure 7-12.
Figure 7-13.
Figure 7-14.
Figure 7-15.
Figure 7-16.
Figure 7-17.
Motorola
Port D Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Port E Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Triple Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
HI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
HI08 Core Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
HI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
HI08 Read and Write Operations in Little Endian Mode . . . . . . . . . . . . . . . 6-11
HI08 Read and Write Operations in Big Endian Mode . . . . . . . . . . . . . . . . . 6-12
Host Control Register (HCR) (X:$FFFFC2) . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Host Status Register (HSR) (X:$FFFFC3) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Host Data Direction Register (HDDR) (X:$FFFFC8). . . . . . . . . . . . . . . . . . 6-16
Host Base Address Register (HBAR) (X:$FFFFC5). . . . . . . . . . . . . . . . . . . 6-17
Self Chip-Select Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . . . . . . . . . . 6-18
Single-Strobe Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Dual-Strobe Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Command Vector Register (CVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Interface Status Registe (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Interrupt Vector Register (IVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
ESSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
ESSI Control Register A(CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . . . . . 7-17
ESSI Frame Sync Generator Functional Block Diagram . . . . . . . . . . . . . . . 7-18
ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
CRB FSL0 and FSL1 Bit Operation (FSR = 0) . . . . . . . . . . . . . . . . . . . . . . . 7-25
CRB SYN Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
CRB MOD Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) . . . . . . . . . . 7-28
Network Mode, External Frame Sync (8 Bit, 2 Words in Frame). . . . . . . . . 7-28
ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
ESSI Data Path Programming Model (SHFD = 0) . . . . . . . . . . . . . . . . . . . . 7-32
ESSI Data Path Programming Model (SHFD = 1) . . . . . . . . . . . . . . . . . . . . 7-33
ESSI Transmit Slot Mask Register A (TSMA) . . . . . . . . . . . . . . . . . . . . . . . 7-34
ESSI Transmit Slot Mask Register B (TSMB) . . . . . . . . . . . . . . . . . . . . . . . 7-35
ESSI Receive Slot Mask Register A (RSMA). . . . . . . . . . . . . . . . . . . . . . . . 7-35
ESSI Receive Slot Mask Register B (RSMB) . . . . . . . . . . . . . . . . . . . . . . . . 7-36
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Figures
Figure 7-18.
Figure 7-19.
Freescale Semiconductor, Inc...
Figure 7-20.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 8-8.
Figure 8-9.
Figure 8-10.
Figure 8-11.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 9-7.
Figure 9-8.
Figure 9-9.
Figure 9-10.
Figure 9-11.
Figure 9-12.
Figure 9-13.
Figure 9-14.
Figure 9-15.
Figure 9-16.
Figure 9-17.
Figure 9-18.
Figure 9-19.
Figure 9-20.
Figure 9-21.
Port Control Register (PCR) (PCRC X:$FFFFBF)
(PCRD X:$FFFAF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Port Direction Register (PRR)(PRRC X:$FFFFBE)
(PRRD X: $FFFFAE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37
Port Data Register (PDR) (PDRC X:$FFFFBD)
(PDRD X: $FFFFAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38
SCI Data Word Formats (SSFTD = 1), 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
SCI Data Word Formats (SSFTD = 0), 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
SCI Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
16 x Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
SCI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
SCI Programming Model - Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Port E Data Register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Triple Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Timer Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Timer Mode (TRM = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Timer Mode (TRM = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Pulse Mode (TRM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Pulse Mode (TRM = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Toggle Mode, TRM = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Toggle Mode, TRM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
Event Counter Mode, TRM = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Event Counter Mode, TRM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
Pulse Width Measurement Mode, TRM = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Pulse Width Measurement Mode, TRM = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Period Measurement Mode, TRM = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Period Measurement Mode, TRM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Capture Measurement Mode, TRM = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Pulse Width Modulation Toggle Mode, TRM = 1 . . . . . . . . . . . . . . . . . . . . 9-17
Pulse Width Modulation Toggle Mode, TRM = 0 . . . . . . . . . . . . . . . . . . . . 9-18
Watchdog Pulse Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Watchdog Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Timer Module Programmer’s Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
Timer Prescalar Load Register (TPLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Motorola
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Figures
Figure 9-22.
Figure 9-23.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 10-6.
Figure 10-7.
Figure 10-8.
Figure 10-9.
Figure 10-11.
Figure 10-10.
Figure 10-12.
Figure 10-13.
Figure B-1.
Figure B-2.
Figure B-3.
Figure B-4.
Figure B-5.
Figure B-6.
Figure B-7.
Figure B-8.
Figure B-9.
Figure B-10.
Figure B-11.
Figure B-12.
Figure B-13.
Figure B-14.
Figure B-15.
Figure B-16.
Figure B-17.
Figure B-18.
Figure B-19.
Figure B-20.
Figure B-21.
Figure B-22.
Figure B-23.
Motorola
Timer Prescalar Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
EFCOP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Storage of Filter Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
EFCOP Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Filter Count (FCNT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
EFCOP ALU Control Register (FACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Decimation/Channel Count Register (FDCH) . . . . . . . . . . . . . . . . . . . . . . . 10-13
FIR Filter Type Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16
IIR Filter Type Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20
Real FIR Filter Data stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Adaptive FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31
Real FIR Filter Data Stream With Decimation by M . . . . . . . . . . . . . . . . . 10-31
Adaptive FIR Filter Using Polling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
Adaptive FIR Filter Using DMA Input and Interrupt Output . . . . . . . . . . . 10-34
Status Register (SR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
Operating Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
Address Attribute Registers (AAR3 - AAR0) . . . . . . . . . . . . . . . . . . . . . . . . B-15
Bus Control Register (BCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16
DMA Control Register (DCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
Interrupt Priority Register–Core (IPR–C) . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
Interrupt Priority Register – Peripherals (IPR–P) . . . . . . . . . . . . . . . . . . . . . B-19
Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . B-20
Host Receive and Host Transmit Data Registers. . . . . . . . . . . . . . . . . . . . . . B-21
Host Control and Host Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22
Host Base Address and Host Port Control Registers . . . . . . . . . . . . . . . . . . . B-23
Interrupt Control and Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . B-24
Interrupt Vector and Command Vector Registers . . . . . . . . . . . . . . . . . . . . . B-25
Host Receive and Host Transmit Data Registers. . . . . . . . . . . . . . . . . . . . . . B-26
ESSI Control Register A (CRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27
ESSI Control Register B (CRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
ESSI Status Register (SSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
ESSR Transmit and Receive Slot Mask Registers (TSM, RSM) . . . . . . . . . B-30
SCI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31
SCI Status and Clock Control Registers (SSR, SCCR) . . . . . . . . . . . . . . . . . B-32
SCI Receive and Transmit Data Registers (SRX, TRX) . . . . . . . . . . . . . . . . B-33
Timer Prescaler Load/Count Register (TPLR, TPCR) . . . . . . . . . . . . . . . . . B-34
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-35
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Figures
Figure B-24.
Figure B-25.
Figure B-26.
Figure B-27.
Figure B-28.
Figure B-29.
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Figure B-30.
Timer Load, Compare, Count Registers (TLR, TCPR, TCR). . . . . . . . . . . . B-36
Host Data Direction and Host Data Registers (HDDR, HDR) . . . . . . . . . . . B-37
Port C Registers (PCRC, PRRC, PDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Port D Registers (PCRD, PRRD, PDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . B-39
Port E Registers (PCRE, PRRE, PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . B-40
EFCOP Counter and Control Status Registers
(FCNT and FCSR)B-41
EFCOP FACR, FDBA, FCBA, and FDCH Registers. . . . . . . . . . . . . . . . . . B-42
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Figures
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Tables
Table 1-1.
Table 1-2.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 5-1.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 6-10.
Table 6-11.
Table 6-12.
Table 6-13.
Table 6-14.
Table 6-15.
Table 6-16.
Table 6-17.
Table 6-18.
Table 6-19.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Motorola
High True/Low True Signal Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
DSP56311 Switch Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
DSP56311 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Operating Mode Register (OMR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . 4-11
Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
PLL Control Register (PCTL) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Address Attribute Registers (AAR0–AAR3) Bit Definitions . . . . . . . . . . . . . . 4-23
DMA-Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
HI08 Signal Definitions for Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08 Data Strobe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HI08 Host Request Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0) . . . . . . . . 6-10
HTRQ and HRRQ Pin Operation In Double Request Mode
(ICR[2]=HDRQ=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Host Control Register (HCR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Host Status Register (HSR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Host Base Address Register (HBAR) Bit Definitions. . . . . . . . . . . . . . . . . . . . 6-17
Host Port Control Register (HPCR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . 6-18
DSP-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Host-Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Interface Control Register (ICR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . 6-25
Command Vector Register (CVR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . 6-27
Interface Status Register (ISR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Host-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
HI08 Programming Model, DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
HI08 Programming Model: Host Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
ESSI Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Mode and Signal Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
ESSI Control Register A (CRA) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . 7-14
ESSI Control Register B (CRB) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . 7-19
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Tables
Table 7-5.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-8.
Table 10-9.
Table 10-10.
Table 10-11.
Table B-1.
Table B-2.
Table B-3.
Table B-4.
Table B-5.
Motorola
ESSI Status Register (SSISR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
SCI Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
SCI Control Register (SCR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
SCI Status Register (SSR) Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
SCI Clock Control Register (SCCR) Bit Definitions . . . . . . . . . . . . . . . . . . . . 8-21
Port Control Register and Port Direction Register Bits . . . . . . . . . . . . . . . . . . 8-26
Timer Prescalar Load Register (TPLR) Bit Definitions . . . . . . . . . . . . . . . . . . 9-23
Timer Prescalar Count Register (TPCR) Bit Definitions . . . . . . . . . . . . . . . . . 9-24
Timer Control/Status Register (TCSR) Bit Definitions . . . . . . . . . . . . . . . . . . 9-24
Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28
EFCOP Registers Accessible Through the PMB . . . . . . . . . . . . . . . . . . . . . . . 10-4
EFCOP Registers and Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Filter Count FCNT Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
FCSR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
EFCOP ALU Control Register (FACR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Decimation/Channel Count Register (FDCH) Bits. . . . . . . . . . . . . . . . . . . . . 10-14
EFCOP Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
EFCOP DMA Request Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
EFCOP Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
DMA Channel 0 Regisister Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
DMA Channel 1 Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24
Guide to Programming Sheets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Internal X I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Internal Y I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Interrupt Source Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
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Chapter 1
Overview
This manual describes the DSP56311 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56311 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.
Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD),
which describes the CPU, core programming models, and instruction set. The DSP56311
Technical Data (DSP56311/D)—referred to as the data sheet—provides DSP56311
electrical specifications, timing, pinout, and packaging descriptions.
You can obtain these documents—and the Motorola DSP development tools—through a
local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest
information on this DSP, access the Motorola DSP home page at the address given on the
back cover of this document.
1.1 Manual Organization
This manual contains the following sections and appendices:
■
Chapter 1, Overview — Features list and block diagram, related documentation,
organization of this manual, and the notational conventions used.
■
Chapter 2, Signals/Connections — DSP56311 signals and their functional
groupings.
■
Chapter 3, Memory Configuration — DSP56311 memory spaces, RAM
configuration, memory configuration bit settings, memory configurations, and
memory maps.
■
Chapter 4, Core Configuration — Registers for configuring the DSP56300 core
when programming the DSP56311, in particular the interrupt vector locations and
the operation of the interrupt priority registers; operating modes and how they
affect the processor’s program and data memories.
■
Chapter 5, Programming the Peripherals — Guidelines on initializing the
DSP56311 peripherals, including mapping control registers, specifying a method of
transferring data, and configuring for general-purpose input/output (GPIO).
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Manual Conventions
■
Chapter 6, Host Interface (HI08) — Features, signals, architecture, programming
model, reset, interrupts, external host programming model, initialization, and a
quick reference to the HI08 programming model.
■
Chapter 7, Enhanced Synchronous Serial Interface (ESSI) — Enhancements, data
and control signals, programming model, operating modes, initialization,
exceptions, and GPIO.
■
Chapter 8, Serial Communication Interface (SCI) — Signals, programming
model, operating modes, reset, initialization, and GPIO.
■
Chapter 9, Triple Timer Module — Architecture, programming model, and
operating modes of three identical timer devices available for use as internals or
event counters.
■
Chapter 10, Enhanced Filter Coprocessor (EFCOP) — Structure and function of
the EFCOP, including features, architecture, and programming model;
programming topics such as data transfer to and from the EFCOP, its use in
different modes, and examples of usage.
■
Appendix A, Bootstrap Code — Bootstrap code for the DSP56311.
■
Appendix B, Programming Reference — Peripheral addresses, interrupt addresses,
and interrupt priorities for the DSP56311; programming sheets listing the contents
of the major DSP56311 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
1-2
■
Bits within registers are always listed from most significant bit (MSB) to least
significant bit (LSB).
■
Bits within a register are indicated AA[n – m], n > m, when more than one bit is
involved in a description. For purposes of description, the bits are presented as if
they are contiguous within a register. However, this is not always the case. Refer to
the programming model diagrams or to the programmer’s sheets to see the exact
location of bits within a register.
■
When a bit is described as “set,” its value is 1. When a bit is described as “cleared,”
its value is 0.
■
The word “assert” means that a high true (active high) signal is pulled high to VCC
or that a low true (active low) signal is pulled low to ground. The word “deassert”
means that a high true signal is pulled low to ground or that a low true signal is
pulled high to VCC. See Table 1-1.
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Manual Conventions
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Table 1-1. High True/Low True Signal Conventions
1.
2.
3.
■
Signal/Symbol
Logic State
Signal State
Voltage
PIN1
True
Asserted
Ground2
PIN
False
Deasserted
VCC3
PIN
True
Asserted
VCC
PIN
False
Deasserted
Ground
PIN is a generic term for any pin on the chip.
Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable
low voltage levels (typically a TTL logic low).
VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).
Pins or signals that are asserted low (made active when pulled to ground) are
indicated like this in text:
— In text, they have an overbar: for example, RESET is asserted low.
— In code examples, they have a tilde in front of their names. In Example 1-1, line
3 refers to the SS0 signal (shown as ~SS0).
■
Sets of signals are indicated by the first and last signals in the set, for instance
HA1–HA8.
■
“Input/Output” indicates a bidirectional signal. “Input or Output” indicates a signal
that is exclusively one or the other.
■
Code examples are displayed in a monospaced font, as shown in Example 1-1.
Example 1-1. Sample Code Listing
BFSET
#$0007,X:PCC; Configure:
line 1
;
line 2
MISO0, MOSI0, SCK0 for SPI master
; ~SS0 as PC3 for GPIO
■
line 3
Hex values are indicated with a dollar sign ($) preceding the hex value, as follows:
$FFFFFF is the X memory address for the core interrupt priority register.
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Features
■
The word “reset” is used in four different contexts in this manual:
— the reset signal, written as RESET
— the reset instruction, written as RESET
— the reset operating state, written as Reset
— the reset function, written as reset
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1.3 Features
The Motorola DSP56311, a member of the DSP56300 core family of programmable
DSPs, supports wireless infrastructure applications with general filtering operations. The
on-chip EFCOP processes filter algorithms in parallel with core operation, thus increasing
overall DSP performance and efficiency. Like the other family members, the DSP56311
uses a high-performance, single-clock-cycle-per-instruction engine (code compatible with
Motorola's popular DSP56000 core family), a barrel shifter, 24-bit addressing, instruction
cache, and DMA controller. The DSP56311 offers 150 million instructions per second
(MIPS) performance (255 MIPS using the EFCOP in filtering applications) using an
internal 150 MHz clock with 1.8 V core and independent 3.3 V input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules.
The modules are chosen from a library of standard predesigned elements, such as
memories and peripherals. New modules can be added to the library to meet customer
specifications. A standard interface between the DSP56300 core and the on-chip memory
and peripherals supports a wide variety of memory and peripheral configurations. In
particular, the DSP56311 includes Motorola’s JTAG port and OnCE module.
The DSP56311, with its large on-chip memory array of 128K words and its EFCOP, is
well suited for high-end multichannel telecommunication applications, such as wireless
infrastructure, multi-line voice/data/FAX processing, video conferencing, and general
digital signal processing.
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DSP56300 Core
1.4 DSP56300 Core
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Core features are fully described in the DSP56300 Family Manual. (This manual, in
contrast, documents pinout, memory, and peripheral features.) Core features are as
follows:
■
150 MIPS (255 MIPS using the EFCOP in filtering applications) with a 150 MHz
clock at 1.8 V
■
Object code compatible with the DSP56000 core
■
Highly parallel instruction set
■
Large on-chip RAM memory of 128K words
■
EFCOP running concurrently with the core, capable of executing 100 million filter
taps per second at peak performance
■
Hardware debugging support
— JTAG test access port (TAP)
— OnCE module
— Address trace mode reflects internal accesses at the external port
■
Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate at 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.5 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
■
Data arithmetic logic unit (ALU)
■
Address generation unit
■
Program control unit
■
PLL and clock oscillator
■
JTAG TAP and OnCE module
■
Memory
In addition, the DSP56311 provides a set of on-chip peripherals, discussed in Section 1.9,
"Peripherals," on page 1-12.
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DSP56300 Core Functional Blocks
1.5.1 Data ALU
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The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
■
Fully pipelined 24 ™ 24-bit parallel multiplier-accumulator
■
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and
normalization; bit stream generation and parsing)
■
Conditional ALU instructions
■
Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
■
Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0
■
Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into
two general-purpose, 56-bit accumulators, A and B, accumulator shifters
■
Two data bus shifter/limiter circuits
1.5.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
32-bit operands. The source operands for the data ALU can be 16, 32, or 40 bits and
always originate from data ALU registers. The results of all data ALU operations are
stored in an accumulator. Data ALU operations are performed in two clock cycles in a
pipeline so that a new instruction can be initiated in every clock cycle, yielding an
effective execution rate of one instruction per clock cycle. The destination of every
arithmetic operation can be a source operand for the immediately following operation
without penalty.
1.5.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit
accepts as many as three input operands and outputs one 56-bit result of the following
form: extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit 24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is
right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit
result can be stored as a 24-bit operand. The LSP is either truncated or rounded into the
MSP. Rounding is performed if specified.
™
1-6
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DSP56300 Core Functional Blocks
1.5.2 Address Generation Unit (AGU)
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The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address
ALU has four sets of register triplets, and each register triplet includes an address register,
offset register, and modifier register. Each contains a 24-bit full adder (called an offset
adder). A second full adder (called a modulo adder) adds the summed result of the first full
adder to a modulo value that is stored in its respective modifier register. A third full adder
(called a reverse-carry adder) is also provided. The offset adder and the reverse-carry
adder work in parallel and share common inputs. The only difference between them is that
the carry propagates in opposite directions. Test logic determines which of the three
summed results of the full adders is output.
Each address ALU can update one address register from its own address register file
during one instruction cycle. The contents of the associated modifier register specify the
type of arithmetic used in the address register update calculation. The modifier value is
decoded in the address ALU.
1.5.3 Program Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the
DSP56300 core. The PCU consists of three hardware blocks:
■
Program decode controller — decodes the 24-bit instruction loaded into the
instruction latch and generates all signals for pipeline control.
■
Program address generator — contains all the hardware needed for program
address generation, system stack, and loop control.
■
Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI),
and generates the appropriate interrupt vector address.
PCU features include the following:
■
Position-independent code support
■
Addressing modes optimized for DSP applications (including immediate offsets)
■
On-chip instruction cache controller
Motorola
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DSP56300 Core Functional Blocks
■
On-chip memory-expandable hardware stack
■
Nested hardware DO loops
■
Fast auto-return interrupts
■
Hardware system stack
Freescale Semiconductor, Inc...
The PCU uses the following registers:
■
Program counter register
■
Status register
■
Loop address register
■
Loop counter register
■
Vector base address register
■
Size register
■
Stack pointer
■
Operating mode register
■
Stack counter register
1.5.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the
clock generator, which performs low-power division and clock pulse generation. These
features allow you to:
■
Change the low-power divide factor without losing the lock
■
Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
1-8
■
A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
■
The ability to oscillate at different frequencies reduces costs by eliminating the
need to add additional oscillators to a system.
DSP56311 User’s Manual
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Freescale Semiconductor, Inc.
DSP56300 Core Functional Blocks
1.5.5 JTAG TAP and OnCE Module
Freescale Semiconductor, Inc...
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems with
testing high-density circuit boards led to the development of this standard under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300
core implementation supports circuit-board test strategies based on this standard. The test
logic includes a TAP with four dedicated signals, a 16-state controller, and three test data
registers. A boundary scan register links all device signals into a single shift register. The
test logic, implemented utilizing static logic design, is independent of the device system
logic. For details on the JTAG port, consult the DSP56300 Family Manual.
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so
that you can examine registers, memory, or on-chip peripherals. This facilitates hardware
and software development on the DSP56300 core processor. OnCE module functions are
provided through the JTAG TAP signals. For details on the OnCE module, consult the
DSP56300 Family Manual.
1.5.6 On-Chip Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to
work with the two address ALUs and to feed two operands simultaneously to the data
ALU. Memory space includes internal RAM and ROM and can be expanded off-chip
under software control. There is an on-chip 192 x 24-bit bootstrap ROM. For details on
internal memory, see Chapter 3, Memory Configuration. Program RAM, instruction
cache, X data RAM, and Y data RAM size are programmable, as Table 1-2 shows.
Table 1-2. DSP56311 Switch Memory Configuration
Program RAM
Size
32 K
™
24-bit
31 K
™
24-bit
96 K
™
24-bit
95 K
™
24-bit
80 K
™
24-bit
79 K
™
24-bit
64 K
™
24-bit
63 K
™
24-bit
48 K
™
24-bit
47 K
™
24-bit
*Includes 10 K
Motorola
Instruction
Cache Size
0
1024
™
24-bit
0
1024
™
24-bit
0
1024
™
24-bit
0
1024
™
24-bit
0
1024
™
™
24-bit
X Data RAM
Size*
Y Data RAM
Size*
48 K
™
24-bit
48 K
™
24-bit
Instruction
Switch
MSW1 MSW0
Cache (CE) Mode (MS)
disabled
disabled
0/1
0/1
48 K
™
24-bit
48 K
™
24-bit
enabled
disabled
0/1
0/1
16 K
™
24-bit
16 K
™
24-bit
disabled
enabled
0
0
16 K
™
24-bit
16 K
™
24-bit
enabled
enabled
0
0
24 K
™
24-bit
24 K
™
24-bit
disabled
enabled
0
1
24 K
™
24-bit
24 K
™
24-bit
enabled
enabled
0
1
32 K
™
24-bit
32 K
™
24-bit
disabled
enabled
1
0
32 K
™
24-bit
32 K
™
24-bit
enabled
enabled
1
0
40 K
™
24-bit
40 K
™
24-bit
disabled
enabled
1
1
40 K
™
24-bit
40 K
™
24-bit
enabled
enabled
1
1
24-bit shared memory (i.e., memory shared by the core and the EFCOP)
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Internal Buses
1.5.7 Off-Chip Memory Expansion
Freescale Semiconductor, Inc...
Memory can be expanded off chip to the following capacities:
■
Data memory expansion to two 256K ™ 24-bit word memory spaces (or up to two
4M x 24-bit word memory spaces by using the Address Attribute AA0 – AA3
signals)
■
Program memory expansion to one 256K ™ 24-bit word memory space (or up to
one 4M x 24-bit word memory spaces by using the Address Attribute AA0 – AA3
signals)
Further features of off-chip memory include the following:
■
External memory expansion port
■
Simultaneous glueless interface to static RAM (SRAM) and dynamic RAM
(DRAM)
1.6 Internal Buses
To provide data exchange between the blocks, the DSP56311 implements the following
buses:
■
Peripheral I/O expansion bus to peripherals
■
Program memory expansion bus to program ROM
■
X memory expansion bus to X memory
■
Y memory expansion bus to Y memory
■
Global data bus between PCU and other core structures
■
Program data bus for carrying program data throughout the core
■
X memory data bus for carrying X data throughout the core
■
Y memory data bus for carrying Y data throughout the core
■
Program address bus for carrying program memory addresses throughout the core
■
X memory address bus for carrying X memory addresses throughout the core
■
Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components.
1-10
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Block Diagram
1.7 Block Diagram
All internal buses on the DSP56300 family members are 24-bit buses. The program data
bus is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56311.
3
16
6
6
Memory Expansion Area
Peripheral
Expansion Area
Address
Generation
Unit
Six Channel
DMA Unit
X Data
RAM
48K ™ 24
YAB
XAB
PAB
DAB
Y Data
RAM
48K ™ 24
YM_EB
EFCOP
Program
RAM
32K ™ 24 or
(Program
RAM
31K ™ 24 and
Instruction
Cache
1024 ™ 24)
XM_EB
Enhanced
Filter
Coprocessor
PM_EB
Host
ESSI
Interface Interface
HI08
Triple
Timer
PIO_EB
Freescale Semiconductor, Inc...
SCI
Interface
24-Bit
Bootstrap
ROM
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
Clock
Generator
EXTAL
XTAL
RESET
PINIT/NMI
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Mngmnt.
Program
Interrupt
Controller
PLL
2
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 ™ 24+56“56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
18
Address
13
Control
24
Data
5
JTAG
OnCE™
DE
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure1-1. DSP56311 Block Diagram
Note:
Motorola
See Section 1.5.6, “On-Chip Memory,” on page 1-9 for details on memory size.
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DMA
1.8 DMA
The DMA block has the following features:
■
Six DMA channels supporting internal and external accesses
■
One-, two-, and three-dimensional transfers (including circular buffering)
■
End-of-block-transfer interrupts
■
Triggering from interrupt lines and all peripherals
Freescale Semiconductor, Inc...
1.9 Peripherals
In addition to the core features, the DSP56311 provides the following peripherals:
■
As many as 34 user-configurable GPIO signals
■
HI08 to external hosts
■
Dual ESSI
■
SCI
■
Triple timer module
■
Memory switch mode
■
Four external interrupt/mode control lines
1.9.1 GPIO Functionality
The GPIO port consists of up to 34 programmable signals, also used by the peripherals
(HI08, ESSI, SCI, and timer). There are no dedicated GPIO signals. After a reset, the
signals are automatically configured as GPIO. Three memory-mapped registers per
peripheral control GPIO functionality. Programming techniques for these registers to
control GPIO functionality are detailed in Chapter 5, Programming the Peripherals.
1.9.2 HI08
The HI08 is a byte-wide, full-duplex, double-buffered parallel port that can connect
directly to the data bus of a host processor. The HI08 supports a variety of buses and
provides connection with a number of industry-standard DSPs, microcomputers, and
microprocessors without requiring any additional logic. The DSP core treats the HI08 as a
memory-mapped peripheral occupying eight 24-bit words in data memory space. The DSP
can use the HI08 as a memory-mapped peripheral, using either standard polled or interrupt
programming techniques. Separate double-buffered transmit and receive data registers
allow the DSP and host processor to transfer data efficiently at high speed. Memory
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Peripherals
mapping allows you to program DSP core communication with the HI08 registers using
standard instructions and addressing modes.
1.9.3 ESSI
Freescale Semiconductor, Inc...
The DSP56311 provides two independent and identical ESSIs. Each ESSI has a
full-duplex serial port for communication with a variety of serial devices, including one or
more industry-standard codecs, other DSPs, microprocessors, and peripherals that
implement the Motorola SPI. The ESSI consists of independent transmitter and receiver
sections and a common ESSI clock generator. ESSI capabilities include the following:
■
Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs
■
Normal mode operation using frame sync
■
Network mode operation with as many as 32 time slots
■
Programmable word length (8, 12, or 16 bits)
■
Program options for frame synchronization and clock generation
■
One receiver and three transmitters per ESSI
1.9.4 SCI
The SCI provides a full-duplex port for serial communication with other DSPs,
microprocessors, or peripherals such as modems. The SCI interfaces without additional
logic to peripherals that use TTL-level signals. With a small amount of additional logic,
the SCI can connect to peripheral interfaces that have non-TTL level signals, such as the
RS-232C, RS-422, etc. This interface uses three dedicated signals: transmit data, receive
data, and SCI serial clock. It supports industry-standard asynchronous bit rates and
protocols, as well as high-speed synchronous data transmission (up to 12.5 Mbps for a
100 MHz clock). SCI asynchronous protocols include a multidrop mode for master/slave
operation with wakeup on idle line and wakeup on address bit capability. This mode
allows the DSP56311 to share a single serial line efficiently with other peripherals.
Separate SCI transmit and receive sections can operate asynchronously with respect to
each other. A programmable baud-rate generator provides the transmit and receive clocks.
An enable vector and an interrupt vector allow the baud-rate generator to function as a
general-purpose timer when the SCI is not using it or when the interrupt timing is the same
as that used by the SCI.
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Peripherals
1.9.5 Timer Module
Freescale Semiconductor, Inc...
The triple timer module is composed of a common 21-bit prescaler and three independent
and identical general-purpose 24-bit timer/event counters, each with its own
memory-mapped register set. Each timer has the following properties:
■
A single signal that can function as a GPIO signal or as a timer signal
■
Uses internal or external clocking and can interrupt the DSP after a specified
number of events (clocks) or signal an external device after counting internal
events
■
Connection to the external world through one bidirectional signal. When this signal
is configured as an input, the timer functions as an external event counter or
measures external pulse width/signal period. When the signal is used as an output,
the timer functions as either a timer, a watchdog, or a pulse width modulator.
1.9.6 EFCOP
The EFCOP interfaces with the DSP core via the peripheral module bus. It is a
general-purpose, fully programmable coprocessor that performs filtering tasks
concurrently with the DSP core, with minimum core overhead. The DSP core and the
EFCOP can share data via an 8K-word shared data memory. DMA channels shuttle input
and output data between the DSP core and the EFCOP. The EFCOP supports a variety of
filter modes, some of which are optimized for cellular base station applications:
■
Real finite impulse response (FIR) with real taps
■
Complex FIR with complex taps
■
Complex FIR generating pure real or pure imaginary outputs alternately
■
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
■
Direct form 1 (DFI) infinite impulse response (IIR) filter
■
Direct form 2 (DFII) IIR filter
■
Four scaling factors (1, 4, 8, 16) for IIR output
■
Adaptive FIR filter with true least mean square (LMS) coefficient updates
■
Adaptive FIR filter with delayed LMS coefficient updates
The EFCOP supports up to 10K taps and 10K coefficients in any combination of number
and length of filters (e.g., eight filters of length 512, or 16 filters of length 256). It
performs either 24-bit or 16-bit precision arithmetic with full support for saturation
arithmetic. A cost-effective and power-efficient coprocessor, the EFCOP accelerates
filtering tasks, such as echo cancellation or correlation, concurrently with software
running on the DSP core.
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Chapter 2
Signals/Connections
Freescale Semiconductor, Inc...
The DSP56311 input and output signals are organized into functional groups, as shown in
Table 2-1 and illustrated in Figure 2-1.
Table 2-1.
DSP56311 Functional Signal Groupings
Number of Signals
Functional Group
Description
Power (VCC)
20
Table 2-2
Ground (GND)
19
Table 2-3
Clock
2
Table 2-4
PLL
3
Table 2-5
18
Table 2-6
24
Table 2-7
Bus control
13
Table 2-8
Interrupt and mode control
5
Table 2-9
Address bus
Port A
Data bus
1
HI08
Port B2
16
Table 2-10
ESSI
Ports C and D 3
12
Table 2-11
Table 2-12
Port E4
3
Table 2-13
Timer5
3
Table 2-14
OnCE/JTAG Port
6
Table 2-15
SCI
NOTES:
1.
2.
3.
4.
5.
Motorola
Port A signals define the external memory interface port, including the external address bus, data
bus, and control signals. The data bus lines have internal keepers.
Port B signals are the HI08 port signals multiplexed with the GPIO signals. All Port B signals have
keepers.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. All Port C and
D signals have keepers.
Port E signals are the SCI port signals multiplexed with the GPIO signals. All Port C signals have
keepers.
All timer signals have keepers.
Signals/Connections
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The Clock Output (CLKOUT) is not functional in the DSP56311. The CLKOUT
output pin provides a 50 percent duty cycle output clock synchronized to the
internal processor clock when the Phase Lock Loop (PLL) is enabled and
locked. At 150 MHz and above, CLKOUT produces a low-amplitude waveform
that is not usable externally by other devices. Several alternatives to using
CLKOUT exist, such as enabling bus arbitration by setting the Asynchronous Bus
Arbitration Enable Bit (ABE) in the Operating Mode register. When set, the
ABE bit eliminates the setup and hold time requirements with respect to
CLKOUT for BB and BG.
Freescale Semiconductor, Inc...
Note:
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During Rese
MODA
MODB
MODC
MODD
RESET
DSP56311
Freescale Semiconductor, Inc...
VCCP
V CCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
GNDP
GNDP1
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
Power Inputs:
PLL
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
4
3
3
4
2
2
Grounds:
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
4
4
4
2
2
EXTAL
XTAL
Clock
PLL
PCAP
After
Reset
NMI
During
Reset
PINIT
Port A
A0–A17
D0–D23
AA0–AA3/
RAS0–RAS3
RD
WR
TA
BR
BG
BB
CAS
NOTES: 1.
2.
3.
18
24
4
External
Address Bus
External
Data Bus
External
Bus
Control
Interrupt/Mode
Control
8
Host
Interface
(HI08) Port1
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)2
3
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)2
3
Serial
Communications
Interface (SCI) Port2
Timers3
OnCE/JTAG
Port
t
Non-Multiplexed
Bus
After Reset
IRQA
IRQB
IRQC
IRQD
RESET
Multiplexed
Bus
H0–H7
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
HAD0–HAD7
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
zDouble HR
HTRQ/HTRQ
HRRQ/HRRQ
SC00–SC02
SCK0
SRD0
STD0
Port C GPIO
PC0–PC2
PC3
PC4
PC5
SC10–SC12
SCK1
SRD1
STD1
Port D GPIO
PD0–PD2
PD3
PD4
PD5
RXD
TXD
SCLK
Port E GPIO
PE0
PE1
PE2
TIO0
TIO1
TIO2
Port B
GPIO
PB0–PB7
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Timer GPIO
TIO0
TIO1
TIO2
TCK
TDI
TDO
TMS
TRST
DE
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and
single or double Host Request (HR) configurations. Since each of these modes is configured
independently, any combination of these modes is possible. These HI08 signals can also be configured
alternately as GPIO signals (PB0–PB15). Signals with dual designations (e.g., HAS/HAS) have
configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed: ESSI0 with the Port C GPIO signals (PC0–PC5),
ESSI1 with Port D GPIO signals (PD0–PD5), and SCI with Port E GPIO signals (PE0–PE2).
TIO0–TIO2 can be configured as GPIO signals.
Figure 2-1. Signals Identified by Functional Group
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Power
2.1 Power
Table 2-2.
Freescale Semiconductor, Inc...
Power Name
Power Inputs
Description
VCCP
PLL Power—VCC dedicated for PLL use. The voltage should be well-regulated and the input
should be provided with an extremely low impedance path to the VCC power rail.
VCCQL
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must
be isolated externally from all other chip power inputs. The user must provide adequate
external decoupling capacitors.
VCCQH
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied
externally to all other chip power inputs, except V CCQL. The user must provide adequate
decoupling capacitors.
VCCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This
input must be tied externally to all other chip power inputs, except VCCQL. The user must
provide adequate external decoupling capacitors.
VCCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must
be tied externally to all other chip power inputs, except VCCQL. The user must provide
adequate external decoupling capacitors.
VCCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be
tied externally to all other chip power inputs, except VCCQL. The user must provide adequate
external decoupling capacitors.
VCCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to
all other chip power inputs, except VCCQL. The user must provide adequate external
decoupling capacitors.
VCCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers.
This input must be tied externally to all other chip power inputs, except VCCQL. The user must
provide adequate external decoupling capacitors.
2.2 Ground
Table 2-3. Ground Signals
Ground
Name
Description
GNDP
PLL Ground— A ground dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground. V CCP should be bypassed to GNDP by a 0.47 mF capacitor located as
close as possible to the chip package.
GNDP1
PLL Ground 1—A ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground.
GNDQ
Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
GNDA
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are four GND A connections.
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Clock
Table 2-3.
Ground (Continued)Signals
Freescale Semiconductor, Inc...
Ground
Name
Description
GNDD
Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors.
GNDC
Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
GNDH
Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally to
all other chip ground connections. The user must provide adequate external decoupling capacitors.
GNDS
ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors.
2.3 Clock
Table 2-4.
Signal
Name
Type
State During
Reset
Clock Signals
Signal Description
EXTAL
Input
Input
External Clock/Crystal Input—EXTAL interfaces the internal crystal
oscillator input to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—XTAL connects the internal crystal oscillator output
to an external crystal. If an external clock is used, leave XTAL
unconnected.
Note:
Motorola
The Clock Output (CLKOUT) is not functional in the DSP56311. The CLKOUT
output pin provides a 50 percent duty cycle output clock synchronized to the
internal processor clock when the Phase Lock Loop (PLL) is enabled and
locked. At 150 MHz and above, CLKOUT produces a low-amplitude waveform
that is not usable externally by other devices. Several alternatives to using
CLKOUT exist, such as enabling bus arbitration by setting the Asynchronous Bus
Arbitration Enable Bit (ABE) in the Operating Mode register. When set, the
ABE bit eliminates the setup and hold time requirements with respect to
CLKOUT for BB and BG.
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PLL
2.4 PLL
Table 2-5.
Signal Name
PCAP
Type
Input
Phase-Locked Loop Signals
State During
Reset
Signal Description
Input
PLL Capacitor—PCAP is an input connecting an off-chip
capacitor to the PLL filter. Connect one capacitor terminal to
PCAP and the other terminal to VCCP.
Freescale Semiconductor, Inc...
If the PLL is not used, PCAP may be tied to VCC, GND, or left
floating.
PINIT
Input
NMI
Input
Input
PLL Initial—During assertion of RESET, the value of PINIT is
written into the PLL enable (PEN) bit of the PLL control (PCTL)
register, determining whether the PLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during
normal instruction processing, this Schmitt-trigger input is the
negative-edge-triggered NMI request internally synchronized to
the internal clock.
2.5 External Memory Expansion Port (Port A)
When the DSP56311 enters a low-power standby mode (stop or wait), it releases bus
mastership and tri-states the relevant Port A signals: A0–A17, D0–D23, AA0/RAS0–AA3/RAS3,
RD, WR, BB, CAS.
2.5.1 External Address Bus
Table 2-6.
Signal Name
A0–A17
2-6
Type
Output
External Address Bus Signals
State During
Reset
Tri-stated
Signal Description
Address Bus—When the DSP is the bus master, A0–A17 are
active-high outputs that specify the address for external
program and data memory accesses. Otherwise, the signals
are tri-stated. To minimize power dissipation, A0–A17 do not
change state when external memory spaces are not being
accessed.
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External Memory Expansion Port (Port A)
2.5.2 External Data Bus
Table 2-7.
Signal Name
Freescale Semiconductor, Inc...
D0–D23
External Data Bus Signals
State During
Reset
Type
Input/ Output
Tri-stated
Signal Description
Data Bus—When the DSP is the bus master, D0–D23 are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D0–D23 are tri-stated. These lines have
weak keepers to maintain the last state even if all drivers are
tri-stated.
2.5.3 External Bus Control
Table 2-8.
Signal Name
AA0–AA3
Type
Output
State During
Reset
Tri-stated
External Bus Control Signals
Signal Description
Address Attribute—When defined as AA, these signals can be
used as chip selects or additional address lines. The default use
defines a priority scheme under which only one AA signal can be
asserted at a time. Setting the AA priority disable (APD) bit (Bit 14) of
the OMR, the priority mechanism is disabled and the lines can be
used together as four external lines that can be decoded externally
into 16 chip select signals.
Row Address Strobe—When defined as RAS, these signals can be
used as RAS for DRAM interface. These signals are tri-statable
outputs with programmable polarity.
RAS0–RAS3
Output
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is an
active-low output that is asserted to read external memory on the
data bus (D0–D23). Otherwise, RD is tri-stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is an
active-low output that is asserted to write external memory on the
data bus (D0–D23). Otherwise, the signals are tri-stated.
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External Memory Expansion Port (Port A)
Table 2-8. External Bus Control Signals (Continued)
Signal Name
Freescale Semiconductor, Inc...
TA
Type
Input
State During
Reset
Ignored Input
Signal Description
Transfer Acknowledge—If the DSP56311 is the bus master and
there is no external bus activity, or the DSP56311 is not the bus
master, the TA input is ignored. The TA input is a data transfer
acknowledge (DTACK) function that can extend an external bus
cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be
added to the wait states inserted by the bus control register (BCR) by
keeping TA deasserted. In typical operation, TA is deasserted at the
start of a bus cycle, is asserted to enable completion of the bus
cycle, and is deasserted before the next bus cycle. The current bus
cycle completes one clock period after TA is asserted synchronous
to the internal clock. The number of wait states is determined by the
TA input or by the BCR, whichever is longer. The BCR can be used
to set the minimum number of wait states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion; otherwise, improper operation may result. TA can
operate synchronously or asynchronously depending on the setting
of the OMR[TAS] bit.
TA functionality must not be used while DRAM accesses are
performed; otherwise, improper operation may result.
BR
2-8
Output
Output
(deasserted)
Bus Request—An active-low output, never tri-stated. BR is asserted
when the DSP requests bus mastership. BR is deasserted when the
DSP no longer needs the bus. BR may be asserted or deasserted
independently of whether the DSP56311 is a bus master or a bus
slave. Bus “parking” allows BR to be deasserted even though the
DSP56311 is the bus master. (See the description of bus “parking” in
the BB signal description.) The bus request hole (BRH) bit in the
BCR allows BR to be asserted under software control even though
the DSP does not need the bus. BR is typically sent to an external
bus arbitrator that controls the priority, parking, and tenure of each
master on the same external bus. BR is only affected by DSP
requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the
bus slave state.
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Interrupt and Mode Control
Table 2-8.
Signal Name
Freescale Semiconductor, Inc...
BG
Type
Input
External Bus Control Signals (Continued)
State During
Reset
Ignored Input
Signal Description
Bus Grant—An active-low input. BG must be asserted/deasserted
synchronous to the internal clock for proper operation. BG is
asserted by an external bus arbitration circuit when the DSP56311
becomes the next bus master. When BG is asserted, the DSP56311
must wait until BB is deasserted before taking bus mastership. When
BG is deasserted, bus mastership is typically given up at the end of
the current bus cycle. This may occur in the middle of an instruction
that requires more than one external bus cycle for execution.
The default operation of this bit requires a setup and hold time as
specified in DSP56311 Technical Data (the data sheet). An alternate
mode can be invoked: set the asynchronous bus arbitration enable
(ABE) bit (Bit 13) in the OMR. When this bit is set, BG and BB are
synchronized internally. This eliminates the respective setup and
hold time requirements but adds a required delay between the
deassertion of an initial BG input and the assertion of a subsequent
BG input.
BB
Input/
Output
Input
Bus Busy—A bidirectional active-low input/output. Must be asserted
and deasserted synchronous to the internal clock. BB indicates that
the bus is active. Only after BB is deasserted can the pending bus
master become the bus master (and then assert the signal again).
The bus master may keep BB asserted after ceasing bus activity
regardless of whether BR is asserted or deasserted. Called “bus
parking,” this allows the current bus master to reuse the bus without
rearbitration until another device requires the bus. The deassertion
of BB is done by an “active pull-up” method (i.e., BB is driven high
and then released and held high by an external pull-up resistor).
The default operation of this bit requires a setup and hold time as
specified in the DSP56311 Technical Data sheet. An alternate mode
can be invoked: set the ABE bit (Bit 13) in the OMR. When this bit is
set, BG and BB are synchronized internally. See BG for additional
information.
NOTE: BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe—When the DSP is the bus master, CAS
is an active-low output used by DRAM to strobe the column address.
Otherwise, if the bus mastership enable (BME) bit in the DRAM
control register is cleared, the signal is tri-stated.
2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request
lines.
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Interrupt and Mode Control
Table 2-9.
Freescale Semiconductor, Inc...
Signal Name
Type
Interrupt and Mode Control
State During
Reset
Signal Description
RESET
Input
Input
Reset—An active-low, Schmitt-trigger input. Deassertion of
RESET is internally synchronized to the internal clock. When
asserted, the chip is placed in the Reset state and the internal
phase generator is reset. The Schmitt-trigger input allows a slowly
rising input (such as a capacitor charging) to reset the chip reliably.
If RESET is deasserted synchronous to the internal clock, exact
start-up timing is guaranteed, allowing multiple processors to start
synchronously and operate together in “lock-step.” When the
RESET signal is deasserted, the initial chip operating mode is
latched from the MODA, MODB, MODC, and MODD inputs. The
RESET signal must be asserted after power up.
MODA
Input
Input
Mode Select A—An active-low Schmitt-trigger input, internally
synchronized to the internal clock. MODA, MODB, MODC, and
MODD select one of 16 initial chip operating modes, latched into
the OMR when the RESET signal is deasserted.
IRQA
Input
MODB
Input
IRQB
Input
MODC
Input
IRQC
Input
2-10
External Interrupt Request A—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If IRQA is
asserted synchronous to the internal clock, multiple processors
can be resynchronized using the WAIT instruction and asserting
IRQA to exit the wait state. If the processor is in the stop standby
state and IRQA is asserted, the processor will exit the stop state.
Input
Mode Select B—An active-low Schmitt-trigger input, internally
synchronized to the internal clock. MODA, MODB, MODC, and
MODD select one of 16 initial chip operating modes, latched into
the OMR when the RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If IRQB is
asserted synchronous to the internal clock, multiple processors
can be resynchronized using the WAIT instruction and asserting
IRQB to exit the wait state. If the processor is in the stop standby
state and IRQB is asserted, the processor will exit the stop state.
Input
Mode Select C—An active-low Schmitt-trigger input, internally
synchronized to the internal clock. MODA, MODB, MODC, and
MODD select one of 16 initial chip operating modes, latched into
the OMR when the RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If IRQC is
asserted synchronous to the internal clock, multiple processors
can be resynchronized using the WAIT instruction and asserting
IRQC to exit the wait state. If the processor is in the stop standby
state and IRQC is asserted, the processor will exit the stop state.
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HI08
Table 2-9.
Freescale Semiconductor, Inc...
Signal Name
Type
MODD
Input
IRQD
Input
Interrupt and Mode Control (Continued)
State During
Reset
Input
Signal Description
Mode Select D—An active-low Schmitt-trigger input, internally
synchronized to the internal clock. MODA, MODB, MODC, and
MODD select one of 16 initial chip operating modes, latched into
the OMR when the RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a
level-sensitive or negative-edge-triggered, maskable interrupt
request input during normal instruction processing. If IRQD is
asserted synchronous to the internal clock, multiple processors
can be resynchronized using the WAIT instruction and asserting
IRQD to exit the wait state. If the processor is in the stop standby
state and IRQD is asserted, the processor will exit the stop state.
2.7 HI08
The HI08 provides a fast parallel-data-to-8-bit port that connects directly to the host bus.
The HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
Table 2-10.
Signal Name
Type
H0–H7
Input/
Output
HAD0–HAD7
Input/
Output
PB0–PB7
Input or
Output
State During
Reset
Tri-stated
Host Interface
Signal Description
Host Data—When the HI08 is programmed to interface a
nonmultiplexed host bus and the HI function is selected, these
signals are lines 0–7 of the data bidirectional, tri-state bus.
Host Address—When HI08 is programmed to interface a
multiplexed host bus and the HI function is selected, these
signals are lines 0–7 of the address/data bidirectional,
multiplexed, tri-state bus.
Port B 0–7—When the HI08 is configured as GPIO through the
host port control register (HPCR), these signals are individually
programmed as inputs or outputs through the HI08 data direction
register (HDDR).
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
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HI08
Table 2-10. Host Interface (Continued)
Freescale Semiconductor, Inc...
Signal Name
Type
HA0
Input
HAS/HAS
Input
PB8
State During
Reset
Input
Signal Description
Host Address Input 0—When the HI08 is programmed to
interface a nonmultiplexed host bus and the HI function is
selected, this signal is line 0 of the host address input bus.
Host Address Strobe—When HI08 is programmed to interface
a multiplexed host bus and the HI function is selected, this signal
is the host address strobe (HAS) Schmitt-trigger input. The
polarity of the address strobe is programmable but is configured
active-low (HAS) following reset.
Port B 8—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
Input or
Output
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
HA1
Input
HA8
Input
PB9
Input
Host Address Input 1—When the HI08 is programmed to
interface a nonmultiplexed host bus and the HI function is
selected, this signal is line 1 of the host address (HA1) input bus.
Host Address 8—When HI08 is programmed to interface a
multiplexed host bus and the HI function is selected, this signal is
line 8 of the host address (HA8) input bus.
Port B 9—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
Input or
Output
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
HA2
Input
HA9
Input
PB10
Input or
Output
Input
Host Address Input 2—When the HI08 is programmed to
interface a nonmultiplexed host bus and the HI function is
selected, this signal is line 2 of the host address (HA2) input bus.
Host Address 9—When HI08 is programmed to interface a
multiplexed host bus and the HI function is selected, this signal is
line 9 of the host address (HA9) input bus.
Port B 10—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
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HI08
Table 2-10.
Freescale Semiconductor, Inc...
Signal Name
Type
HRW
Input
HRD/HRD
Input
PB11
State During
Reset
Input
Host Interface (Continued)
Signal Description
Host Read/Write—When HI08 is programmed to interface a
single-data-strobe host bus and the HI function is selected, this
signal is the Host Read/Write (HRW) input.
Host Read Data—When HI08 is programmed to interface a
double-data-strobe host bus and the HI function is selected, this
signal is the HRD strobe Schmitt-trigger input. The polarity of the
data strobe is programmable, but is configured as active-low
(HRD) after reset.
Port B 11—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
Input or
Output
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
HDS/HDS
Input
HWR/HWR
Input
PB12
Input
Host Data Strobe—When HI08 is programmed to interface a
single-data-strobe host bus and the HI function is selected, this
signal is the host data strobe (HDS) Schmitt-trigger input. The
polarity of the data strobe is programmable, but is configured as
active-low (HDS) following reset.
Host Write Data—When HI08 is programmed to interface a
double-data-strobe host bus and the HI function is selected, this
signal is the host write data strobe (HWR) Schmitt-trigger input.
The polarity of the data strobe is programmable, but is configured
as active-low (HWR) following reset.
Port B 12—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
Input or
Output
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
HCS
Input
HA10
Input
PB13
Input or
Output
Input
Host Chip Select—When HI08 is programmed to interface a
nonmultiplexed host bus and the HI function is selected, this
signal is the host chip select (HCS) input. The polarity of the chip
select is programmable, but is configured active-low (HCS) after
reset.
Host Address 10—When HI08 is programmed to interface a
multiplexed host bus and the HI function is selected, this signal is
line 10 of the host address (HA10) input bus.
Port B 13—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
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Enhanced Synchronous Serial Interface 0
Table 2-10. Host Interface (Continued)
Freescale Semiconductor, Inc...
Signal Name
Type
HREQ/HREQ
Output
HTRQ/HTRQ
Output
PB14
State During
Reset
Input
Signal Description
Host Request—When HI08 is programmed to interface a single
host request host bus and the HI function is selected, this signal
is the host request (HREQ) output. The polarity of the host
request is programmable, but is configured as active-low (HREQ)
following reset. The host request may be programmed as a
driven or open-drain output.
Transmit Host Request—When HI08 is programmed to
interface a double host request host bus and the HI function is
selected, this signal is the transmit host request (HTRQ) output.
The polarity of the host request is programmable, but is
configured as active-low (HTRQ) following reset. The host
request may be programmed as a driven or open-drain output.
Port B 14—When the HI08 is programmed to interface a
multiplexed host bus and the signal is configured as GPIO
through the HPCR, this signal is individually programmed as an
input or output through the HDDR.
Input or
Output
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
HACK/
Input
HACK
HRRQ/
Output
HRRQ
PB15
Input or
Output
Input
Host Acknowledge—When HI08 is programmed to interface a
single host request host bus and the HI function is selected, this
signal is the host acknowledge (HACK) Schmitt-trigger input. The
polarity of the host acknowledge is programmable, but is
configured as active-low (HACK) after reset.
Receive Host Request—When HI08 is programmed to interface
a double host request host bus and the HI function is selected,
this signal is the receive host request (HRRQ) output. The
polarity of the host request is programmable, but is configured as
active-low (HRRQ) after reset. The host request may be
programmed as a driven or open-drain output.
Port B 15—When the HI08 is configured as GPIO through the
HPCR, this signal is individually programmed as an input or
output through the HDDR.
NOTE: This signal has a weak keeper to maintain the last state
even if all drivers are tri-stated.
2.8 Enhanced Synchronous Serial Interface 0
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement
the Motorola serial peripheral interface (SPI).
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Enhanced Synchronous Serial Interface 0
Table 2-11. Enhanced Synchronous Serial Interface 0
Signal Name
SC00
State During
Reset
Type
Input or Output
Input
Serial Control 0—The function of SC00 is determined by
the selection of either synchronous or asynchronous
mode. For asynchronous mode, this signal will be used for
the receive clock I/O (Schmitt-trigger input). For
synchronous mode, this signal is used either for transmitter
1 output or for serial I/O flag 0.
Port C 0—The default configuration following reset is
GPIO input PC0. When configured as PC0, signal direction
is controlled through the port directions register (PRR0).
The signal can be configured as ESSI signal SC00 through
the port control register (PCR0).
PC0
Freescale Semiconductor, Inc...
Signal Description
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
SC01
PC1
Input/
Output
Input
Serial Control 1—The function of this signal is determined
by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this signal is the receiver
frame sync I/O. For synchronous mode, this signal is used
either for transmitter 2 output or for serial I/O flag 1.
Port C 1—The default configuration following reset is
GPIO input PC1. When configured as PC1, signal direction
is controlled through PRR0. The signal can be configured
as an ESSI signal SC01 through PCR0.
Input or Output
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
SC02
Input/
Output
PC2
Input or Output
Serial Control Signal 2—Used for frame sync I/O. SC02
is the frame sync for both the transmitter and receiver in
synchronous mode, and for the transmitter only in
asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When
configured as an input, this signal receives an external
frame sync signal for the transmitter (and the receiver in
synchronous operation).
Port C 2—The default configuration following reset is
GPIO input PC2. When configured as PC2, signal direction
is controlled through PRR0. The signal can be configured
as an ESSI signal SC02 through PCR0.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
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Enhanced Synchronous Serial Interface 0
Table 2-11.
Signal Name
Freescale Semiconductor, Inc...
SCK0
Enhanced Synchronous Serial Interface 0 (Continued)
State During
Reset
Type
Input/
Output
Input
Signal Description
Serial Clock—A bidirectional Schmitt-trigger input signal
providing the serial bit rate clock for the ESSI. The SCK0 is
a clock input or output, used by both the transmitter and
receiver in synchronous modes or by the transmitter in
asynchronous modes.
Although an external serial clock can be independent of
and asynchronous to the DSP system clock, it must
exceed the minimum clock cycle time of 6T (i.e., the
system clock frequency must be at least three times the
external ESSI clock frequency). The ESSI needs at least
three DSP phases inside each half of the serial clock.
PC3
Port C 3—The default configuration following reset is
GPIO input PC3. When configured as PC3, signal direction
is controlled through PRR0. The signal can be configured
as an ESSI signal SCK0 through PCR0.
Input or Output
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
SRD0
Input/
Output
PC4
Input or Output
Serial Receive Data—Receives serial data and transfers
the data to the ESSI receive shift register. SRD0 is an input
when data is being received.
Port C 4—The default configuration following reset is
GPIO input PC4. When configured as PC4, signal direction
is controlled through PRR0. The signal can be configured
as an ESSI signal SRD0 through PCR0.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
STD0
Input/
Output
PC5
Input or Output
Serial Transmit Data—Transmits data from the serial
transmit shift register. STD0 is an output when data is
transmitted.
Port C 5—The default configuration following reset is
GPIO input PC5. When configured as PC5, signal direction
is controlled through PRR0. The signal can be configured
as an ESSI signal STD0 through PCR0.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
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Enhanced Synchronous Serial Interface 1
2.9 Enhanced Synchronous Serial Interface 1
Table 2-12. Enhanced Serial Synchronous Interface 1
Signal Name
SC10
State During
Reset
Type
Input or Output
Input
Serial Control 0—The function of SC10 is determined by
the selection of either synchronous or asynchronous
mode. For asynchronous mode, this signal will be used for
the receive clock I/O (Schmitt-trigger input). For
synchronous mode, this signal is used either for transmitter
1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is
GPIO input PD0. When configured as PD0, signal direction
is controlled through the port directions register (PRR1).
The signal can be configured as an ESSI signal SC10
through the port control register (PCR1).
Input or Output
Freescale Semiconductor, Inc...
Signal Description
PD0
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
SC11
PD1
Input/
Output
Input
Serial Control 1—The function of this signal is determined
by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this signal is the receiver
frame sync I/O. For synchronous mode, this signal is used
either for Transmitter 2 output or for Serial I/O Flag 1.
Port D 1—The default configuration following reset is
GPIO input PD1. When configured as PD1, signal direction
is controlled through PRR1. The signal can be configured
as an ESSI signal SC11 through PCR1.
Input or Output
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
SC12
Input/
Output
PD2
Input or Output
Serial Control Signal 2—For frame sync I/O. SC12 is the
frame sync for both the transmitter and receiver in
synchronous mode, and for the transmitter only in
asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When
configured as an input, this signal receives an external
frame sync signal for the transmitter (and the receiver in
synchronous operation).
Port D 2—The default configuration following reset is
GPIO input PD2. When configured as PD2, signal direction
is controlled through PRR1. The signal can be configured
as an ESSI signal SC12 through PCR1.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
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Enhanced Synchronous Serial Interface 1
Table 2-12.
Signal Name
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SCK1
Enhanced Serial Synchronous Interface 1 (Continued)
State During
Reset
Type
Input/
Output
Input
Signal Description
Serial Clock—A bidirectional Schmitt-trigger input signal
providing the serial bit rate clock for the ESSI. The SCK1 is
a clock input or output used by both the transmitter and
receiver in synchronous modes, or by the transmitter in
asynchronous modes.
Although an external serial clock can be independent of
and asynchronous to the DSP system clock, it must
exceed the minimum clock cycle time of 6T (i.e., the
system clock frequency must be at least three times the
external ESSI clock frequency). The ESSI needs at least
three DSP phases inside each half of the serial clock.
PD3
Port D 3—The default configuration following reset is
GPIO input PD3. When configured as PD3, signal direction
is controlled through PRR1. The signal can be configured
as an ESSI signal SCK1 through PCR1.
Input or Output
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
SRD1
Input/
Output
PD4
Input or Output
Serial Receive Data—Receives serial data and transfers
the data to the ESSI receive shift register. SRD1 is an input
when data is being received.
Port D 4—The default configuration following reset is
GPIO input PD4. When configured as PD4, signal direction
is controlled through PRR1. The signal can be configured
as an ESSI signal SRD1 through PCR1.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
Input
STD1
Input/
Output
PD5
Input or Output
Serial Transmit Data—Transmits data from the serial
transmit shift register. STD1 is an output when data is
being transmitted.
Port D 5—The default configuration following reset is
GPIO input PD5. When configured as PD5, signal direction
is controlled through PRR1. The signal can be configured
as an ESSI signal STD1 through PCR1.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
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SCI
2.10 SCI
The SCI provides a full duplex port for serial communication with other DSPs,
microprocessors, or peripherals such as modems.
Table 2-13.
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Signal Name
Serial Communication Interface
State During
Reset
Type
RXD
Input
Input
PE0
Input or Output
Signal Description
Serial Receive Data—Receives byte oriented serial data
and transfers it to the SCI receive shift register.
Port E 0—The default configuration following reset is
GPIO input PE0. When configured as PE0, signal direction
is controlled through the SCI port directions register (PRR).
The signal can be configured as an SCI signal RXD
through the SCI port control register (PCR).
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
TXD
Output
Input
PE1
Input or Output
Serial Transmit Data—Transmits data from the SCI
transmit data register.
Port E 1—The default configuration following reset is
GPIO input PE1. When configured as PE1, signal direction
is controlled through the SCI PRR. The signal can be
configured as an SCI signal TXD through the SCI PCR.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
SCLK
Input/ Output
Input
PE2
Input or Output
Serial Clock—The bidirectional Schmitt-trigger input
signal providing the input or output clock used by the
transmitter and/or the receiver.
Port E 2—The default configuration following reset is
GPIO input PE2. When configured as PE2, signal direction
is controlled through the SCI PRR. The signal can be
configured as an SCI signal SCLK through the SCI PCR.
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
2.11 Timers
The DSP56311 has three identical and independent timers. Each timer can use internal or
external clocking and either interrupt the DSP56311 after a specified number of events
(clocks) or signal an external device after counting a specific number of internal events.
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JTAG and OnCE Interface
Table 2-14.
Signal Name
TIO0
Triple Timer Signals
State During
Reset
Type
Input or Output
Input
Signal Description
Timer 0 Schmitt-Trigger Input/Output— When Timer 0
functions as an external event counter or in measurement
mode, TIO0 is used as input. When Timer 0 functions in
watchdog, timer, or pulse modulation mode, TIO0 is used
as output.
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The default mode after reset is GPIO input. This can be
changed to output or configured as a timer I/O through the
timer 0 control/status register (TCSR0).
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
TIO1
Input or Output
Input
Timer 1 Schmitt-Trigger Input/Output— When Timer 1
functions as an external event counter or in measurement
mode, TIO1 is used as input. When Timer 1 functions in
watchdog, timer, or pulse modulation mode, TIO1 is used
as output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a timer I/O through the
timer 1 control/status register (TCSR1).
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
TIO2
Input or Output
Input
Timer 2 Schmitt-Trigger Input/Output— When timer 2
functions as an external event counter or in measurement
mode, TIO2 is used as input. When timer 2 functions in
watchdog, timer, or pulse modulation mode, TIO2 is used
as output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a timer I/O through the
timer 2 control/status register (TCSR2).
NOTE: This signal has a weak keeper to maintain the last
state even if all drivers are tri-stated.
2.12 JTAG and OnCE Interface
The DSP56300 family and in particular the DSP56311 support circuit-board test strategies
based on the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture, the
industry standard developed under the sponsorship of the Test Technology Committee of
IEEE and the JTAG.
The OnCE module interfaces nonintrusively with the DSP56300 core and its peripherals
so that you can examine registers, memory, or on-chip peripherals. Functions of the OnCE
module are provided through the JTAG TAP signals.
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JTAG and OnCE Interface
Table 2-15.
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Signal Name
Type
OnCE/JTAG Interface
State During
Reset
Signal Description
TCK
Input
Input
Test Clock—A test clock input signal to synchronize the
JTAG test logic.
TDI
Input
Input
Test Data Input—A test data serial input signal used for
test instructions and data. TDI is sampled on the rising
edge of TCK and has an internal pull-up resistor.
TDO
Output
Tri-stated
Test Data Output—A test data serial output signal used
for test instructions and data. TDO is tri-statable and is
actively driven in the shift-IR and shift-DR controller states.
TDO changes on the falling edge of TCK.
TMS
Input
Input
Test Mode Select—An input signal to sequence the test
controller’s state machine. TMS is sampled on the rising
edge of TCK and has an internal pull-up resistor.
TRST
Input
Input
Test Reset—A Schmitt-trigger input signal to
asynchronously initialize the test controller. TRST has an
internal pull-up resistor. TRST must be asserted after
power up.
DE
Input/ Output
Input
Debug Event—An open-drain signal. As an input, enters
the Debug mode of operation from an external command
controller. As an output, acknowledges that the chip has
entered Debug mode. When asserted as an input, DE
causes the DSP56300 core to finish the executing
instruction, save the instruction pipeline information, enter
the Debug mode, and wait for commands to be entered
from the debug serial input line. This signal is asserted as
an output for three clock cycles when the chip enters
Debug mode as a result of a debug request or as a result
of meeting a breakpoint condition. The DE has an internal
pull-up resistor.
This is not a standard part of the JTAG TAP controller. The
signal connects directly to the OnCE module to initiate
Debug mode directly or to provide a direct external
indication that the chip has entered the debug mode. All
other interface with the OnCE module must occur through
the JTAG port.
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JTAG and OnCE Interface
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Chapter 3
Memory Configuration
Like all members of the DSP56300 core family, the DSP56311 can address three sets of
16 M ™ 24-bit memory internally: program, X data, and Y data. Each of these memory
spaces includes both on-chip and external memory (accessed through the external memory
interface). The DSP56311 is extremely flexible because it has several modes to allocate
on-chip memory between the program memory and the two data memory spaces. You can
also configure it to operate in a special sixteen-bit compatibility mode that allows the chip
to use DSP56000 object code without any change; this can result in higher performance of
existing code for applications that do not require a larger address space. This section
provides detailed information on each of these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
■
Internal program memory (program RAM, 32K by default, up to 96K)
■
(Optional) instruction cache (1K) formed from program RAM
■
Bootstrap program ROM (192 x 24-bit)
■
Optional off-chip memory expansion (as much as 128K in 16-bit mode or 256K in
24-bit mode using the 18 external address lines or 4 M using the external address
lines and the four address attribute lines). Refer to the DSP56300 Family Manual,
especially the Expansion Port chapter, for detailed information on using the
external memory interface to access external program memory.
Note:
Program memory space at locations $FF00C0 – $FFFFFF is reserved and
should not be accessed.
3.1.1 Internal Program Memory
The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM
occupying the lowest 32K locations ($0 – $7FFF) in program memory space. The on-chip
program RAM is organized in 32 banks with 1024 locations each. You can make
additional program memory available using the memory switch mode described in
Section 3.1.2, "Memory Switch Modes—Program Memory."
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Program Memory Space
3.1.2 Memory Switch Modes—Program Memory
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Memory switch mode allows reallocation of portions of X and Y data RAM as program
RAM. OMR[7] is the memory switch (MS) bit that controls this function, as follows:
■
When the MS bit is cleared, program memory consists of the default 32K ™ 24-bit
memory space described in the previous section. In this default mode, the lowest
external program memory location is $8000.
■
When the MS bit is set, a portion of the higher locations of the internal X and
Y data memory are switched to internal program memory. The memory switch
configuration (MSW[1:0]) bits (also called M1 and M0) in the OMR select one of
the following options:
— MSW[1:0] = 00—The 32K higher locations ($4000 – $BFFF) of the internal X
data memory and the 32K higher locations ($6000 – $BFFF) of the internal Y
data memory are switched to internal program memory. In such a case, the
on-chip program memory occupies the lowest 96K locations ($0 – $17FFF) in
the program memory space. The instruction cache, if enabled, occupies the
lowest 1K program words (locations $0 – $3FF). The lowest external program
memory location in this mode is $18000.
— MSW[1:0] = 01—The 24K higher locations ($6000 – $BFFF) of the internal X
data memory and the 24K higher locations ($6000 – $BFFF) of the internal Y
data memory are switched to internal program memory. In such a case, the
on-chip program memory occupies the lowest 80K locations ($0 – $13FFF) in
the program memory space. The instruction cache, if enabled, occupies the
lowest 1K program words (locations $0 – $3FF). The lowest external program
memory location in this mode is $18000, while program memory locations
$14000 – $17FFF are considered reserved and should not be accessed.
— MSW[1:0] = 10—The 16K higher locations ($8000 – $BFFF) of the internal X
data memory and the 16K higher locations ($8000 – $BFFF) of the internal Y
data memory are switched to internal program memory. In such a case, the
on-chip program memory occupies the lowest 64K locations ($0 – $FFFF) in
the program memory space. The instruction cache, if enabled, occupies the
lowest 1K program words (locations $0 – $3FF). The lowest external program
memory location in this mode is $18000, while program memory locations
$10000 – $17FFF are considered reserved and should not be accessed.
— MSW[1:0] = 11—The 8K higher locations ($A000 – $BFFF) of the internal
X memory and the 8K higher locations ($A000 – $BFFF) of the internal
Y memory are switched to internal program memory. In such a case, the
on-chip program memory occupies the lowest 48K locations ($0 – $BFFF) in
the program memory space. The instruction cache, if enabled, occupies the
3-2
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X Data Memory Space
lowest 1 K program words (locations $0 – $3FF). The lowest external program
memory location in this mode is $18000, while program memory locations
$C000-$17FFF are considered reserved and should not be accessed.
3.1.3 Instruction Cache
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In program memory space, the lowest 1024 (1K) program words (at locations $0 – $3FF)
function as an internal instruction cache. When the instruction cache is enabled (that is, the
CE bit in the SR is set), the lowest 1K program words are reserved for the instruction
cache and should not be accessed for other purposes.
Note:
When using an enabled instruction cache, you must assign a valid value for the
vector address bus so that interrupts can be handled properly outside P:$0 –
$3FF. (See the memory diagrams, starting with Figure 3-2, "Memory Switch
Off, Cache On, 24-Bit Mode," on page 3-10.)
3.1.4 Program Bootstrap ROM
The program memory space occupying locations $FF0000 – $FF00BF includes the
internal bootstrap ROM. This ROM contains the 192-word DSP56311 bootstrap program.
3.2 X Data Memory Space
The X data memory space consists of the following:
■
Internal X data memory (48K by default down to 8K)
■
Internal X I/O space (upper 128 locations)
■
Optional off-chip memory expansion (as much as 128K in 16-bit mode, or 256K in
24-bit mode using the 18 external address lines, or 4 M using the external address
lines and the four address attribute lines). Refer to the DSP56300 Family Manual,
especially Section 2, Expansion Port, for details on using the external memory
interface to access external X data memory.
Note:
The X memory space at locations $FF0000 – $FFEFFF is reserved and should
not be accessed.
3.2.1 Internal X Data Memory
The default on-chip X data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 48 K locations ($0 – $BFFF) in X memory space. The on-chip X data RAM is
organized into 48 banks with 1024 locations each. Available X data memory space is
reduced and reallocated to program memory using the memory switch mode described in
the next section.
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X Data Memory Space
3.2.2 Memory Switch Modes—X Data Memory
Memory switch mode reallocates of portions of X and Y data RAM as program RAM. Bit
7 in the OMR is the MS bit that controls this function, as follows:
When the MS bit is cleared, the X data memory consists of the default 48K ™ 24-bit
memory space described in the previous section. In this default mode, the lowest
external X data memory location is $6000.
■
When the MS bit is set, a portion of the higher locations of the internal X memory
is switched to internal program memory. The memory switch (MSW[1:0])
configuration bits in the OMR select one of the following options:
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■
— MSW[1:0] = 00—The 32K higher locations ($4000 – $BFFF) of the internal
X memory are switched to internal program memory, and therefore the highest
internal X memory location is $3FFF. The X memory space at the switched
locations ($4000 – $BFFF) becomes reserved and should not be accessed. The
lowest external X memory location is $C000.
— MSW[1:0] = 01—The 24K higher locations ($6000 – $BFFF) of the internal
X memory are switched to internal program memory, and therefore the highest
internal X memory location is $5FFF. The X memory space at the switched
locations ($6000 – $BFFF) becomes reserved and should not be accessed. The
lowest external X memory location is $C000.
— MSW[1:0] = 10—The 16K higher locations ($8000 – $BFFF) of the internal
X memory are switched to internal program memory, and therefore the highest
internal X memory location is $7FFF. The X memory space at the switched
locations ($8000 – $BFFF) becomes reserved and should not be accessed. The
lowest external X memory location is $C000.
— MSW[1:0] = 11—The 8K higher locations ($A000 – $BFFF) of the internal
X memory are switched to internal program memory, and therefore the highest
internal X memory location is $9FFF. The X memory space at the switched
locations ($A000 – $BFFF) becomes reserved and should not be accessed. The
lowest external X memory location is $C000.
Note:
3-4
The 10K lowest locations ($0 – $27FF) of the internal X memory are shared
memory, which is accessible to both the core and the EFCOP. The EFCOP
connects to the shared memory instead of the DMA bus, so there is no DMA
accessibility to shared memory. Simultaneous accesses by the core and the
EFCOP to the same memory bank (1024 locations) of the shared memory are
not permitted. It is the programmer’s responsibility to prevent such
simultaneous accesses.
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Y Data Memory Space
3.2.3 Internal X I/O Space
One part of the on-chip peripheral registers and some of the DSP56311 core registers
occupy the top 128 locations of the X data memory ($FFFF80 – $FFFFFF). This area is
referred to as the internal X I/O space and it can be accessed by MOVE, MOVEP
instructions and by bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR,
BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and JSSET). The contents of the internal
X I/O memory space are listed in Appendix A.
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3.3 Y Data Memory Space
The Y data memory space consists of the following:
■
Internal Y data memory (48K by default down to 16K)
■
Internal Y I/O space (16 locations—$FFFF80 – $FFFF8F)
■
External Y I/O space (upper 112 locations)
■
Optional off-chip memory expansion (as much as 128K in 16-bit mode or 256K in
24-bit mode using the 18 external address lines or 4 M using the external address
lines and the four address attribute lines). Refer to the DSP56300 Family Manual
for details on using the external memory interface to access external Y data
memory.
Note:
The Y memory space at locations $FF0000 – $FFEFFF is reserved and should
not be accessed.
3.3.1 Internal Y Data Memory
The default on-chip Y data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 48K locations ($0 – $BFFF) in Y memory space. The on-chip Y data RAM is
organized in 48 banks, 1024 locations each. Available Y data memory space is reduced
and reallocated to program memory by using the memory switch mode described in the
following paragraphs.
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Y Data Memory Space
3.3.2 Memory Switch Modes—Y Data Memory
Memory switch mode reallocates of portions of X and Y data RAM as program RAM. Bit
7 in the OMR is the MS bit that controls this function, as follows:
When the MS bit is cleared, the Y data memory consists of the default 48K ™ 24-bit
memory space described in the previous section. In this default mode, the lowest
external Y data memory location is $6000.
■
When MS mode bit in the OMR is set, a portion of the higher locations of the
internal Y memory are switched to internal program memory. The memory switch
configuration (MSW[1:0]) bits in the OMR select one of the following options:
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■
— MSW[1:0] = 00—The 32K higher locations ($4000 – $BFFF) of the internal
Y memory are switched to internal program memory, and therefore the highest
internal Y memory location is $3FFF. The Y memory space at the switched
locations ($4000 – $BFFF) becomes reserved and should not be accessed. The
lowest external Y memory location is $C000.
— MSW[1:0] = 01—The 24K higher locations ($6000 – $BFFF) of the internal
Y memory are switched to internal program memory, and therefore the highest
internal Y memory location is $5FFF. The Y memory space at the switched
locations ($6000 – $BFFF) becomes reserved and should not be accessed. The
lowest external Y memory location is $C000.
— MSW[1:0] = 10—The 8K higher locations ($8000 – $BFFF) of the internal
Y memory are switched to internal program memory, and therefore the highest
internal Y memory location is $7FFF. The Y memory space at the switched
locations ($8000 – $BFFF) becomes reserved and should not be accessed. The
lowest external Y memory location is $C000.
— MSW[1:0] = 11—The 4K higher locations ($A000 – $BFFF) of the internal
Y memory are switched to internal program memory, and therefore the highest
internal Y memory location is $9FFF. The Y memory space at the switched
locations ($A000-$BFFF) becomes reserved and should not be accessed. The
lowest external Y memory location is $C000.
Note:
3-6
The 10K lowest locations ($0-$27FF) of the internal Y memory are shared
memory, which is accessible both to the core and the EFCOP. The EFCOP
connects to the shared memory in place of the DMA bus. Therefore, DMA
cannot access the shared memory, and simultaneous accesses by the core and
EFCOP to the same memory bank (of 256 locations) of the shared memory are
not permitted. It is your responsibility to prevent such simultaneous accesses.
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Dynamic Memory Configuration Switching
3.3.3 Internal Y I/O Space
The second part of the on-chip peripheral registers occupies 16 locations ($FFFF80 –
$FFFF8F) of the Y data memory. This area is the internal Y I/O space, and it can be
accessed by MOVE, MOVEP instructions and by bit-oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR and
JSSET). The contents of the internal Y I/O memory space are listed in Appendix A.
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3.3.4 External Y I/O Space
Off-chip peripheral registers should be mapped into the top 112 locations ($FFFF90 –
$FFFFFF) to take advantage of the move peripheral data (MOVEP) instruction and the
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR,
BSSET, JCLR, JSET, JSCLR and JSSET). This area is the external Y I/O space.
3.4 Dynamic Memory Configuration Switching
When the internal memory configuration is altered by remapping RAM modules from X
and Y data memories into program memory space and vice versa, data contents of the
switched RAM modules are preserved. Any sequence that complies with the switch
condition is valid. For example, if the program flow executes in the address range that is
not affected by the switch, the switch condition can be met very easily. A switch can be
accomplished just by changing the OMR[MS/MSW] bits in the regular program flow,
assuming no accesses to the affected address ranges of the data memory occur up to three
instructions after the instruction that changes the OMR bits.
CAUTION
To ensure that dynamic switching is trouble-free, do not allow any
accesses (including instruction fetches) to or from the affected
address ranges in program and data memories during the switch cycle.
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Sixteen-Bit Compatibility Mode Configuration
Because an interrupt could cause the DSP to fetch instructions out of sequence and might
violate the switch condition, special care should be taken in relation to the interrupt vector
routines.
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CAUTION
Pay special attention when executing a memory switch routine using
the OnCE port. Running the switch routine in trace mode, for
example, can cause the switch to complete after the MS/MSW bits
change while the DSP is in Debug mode. As a result, subsequent
instructions may be fetched according to the new memory
configuration (after the switch) and thus may execute improperly.
3.5 Sixteen-Bit Compatibility Mode Configuration
The sixteen-bit compatibility (SC) mode allows the DSP56311 to use DSP56000 object
code without change. The SC bit (Bit 13 in the SR) is used to switch from the default
24-bit mode to this special 16-bit mode. SC is cleared by reset. You must set this bit to
select the SC mode. The address ranges described in the previous sections apply in the SC
mode with regard to the reallocation of X and Y data memory to program memory in MS
mode, but the maximum addressing ranges are limited to $FFFF, and all data and program
code are 16 bits wide.
3.6 Memory Maps
The following figures illustrate each of the memory space and RAM configurations
defined by the settings of the MS (and MSW[1:0]), CE, and SC bits. The figures show the
configuration and describe the bit settings, memory sizes, and memory locations.
Note:
3-8
In 16-bit mode, if the MS mode bit in the Operating Mode Register (OMR) is
set, external program memory is not accessible, so enabling the instruction
cache is of little benefit. In addition, certain 16-bit modes prevent you from
accessing the entire internal DSP56311 memory space.
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Memory Maps
Default
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
Internal
Reserved
$FFF000
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$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
External
$FFF000
Internal
Reserved
External I/O
Internal I/O
External
Internal
Reserved
$FF0000
External
External
$00C000
$00C000
$008000
Internal
Program RAM
32K
$000000
Internal
X data RAM
48K
MS
0
MSW
[1:0]
any
value
$000000
$000000
Bit Settings
Internal
Y data RAM
48K
Memory Configuration
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
0
0
32K
$0000 – $7FFF
48K
$0000 – $BFFF
48K
$0000 – $BFFF
None
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-1. Memory Switch Off, Cache Off, 24-Bit Mode (Default)
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-9
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
$FFF000
Internal
Reserved
Freescale Semiconductor, Inc...
$FFF000
Internal
Reserved
$FF00C0
$FF0000
External
Bootstrap ROM
Internal I/O
External
Internal
Reserved
$FF0000
External
External I/O
$FF0000
External
External
$00C000
$00C000
$008000
Internal
Program RAM
31K
$000400
Reserved
$000000
$000000
Bit Settings
MS
0
MSW
[1:0]
any
value
Internal
X data RAM
48K
Internal
Y data RAM
48K
$000000
Memory Configuration
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
0
31K
$0400 – $7FFF
48K
$0000 – $BFFF
48K
$0000 – $BFFF
Enabled
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-2. Memory Switch Off, Cache On, 24-Bit Mode
3-10
DSP56311 User’s Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
$FFF000
Internal
Reserved
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM
External
$FFF000
Internal
Reserved
External
$FF0000
External
External
$00C000
Internal
Program RAM
96 K
$000000
$004000
$00C000
Internal
Reserved
$004000
Internal X data
RAM 16K
$000000
Bit Settings
Internal I/O
External
Internal
Reserved
$FF0000
$018000
External I/O
$000000
Internal
Reserved
Internal Y data
RAM 16K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
00
0
0
96K
$0000 –
$17FFF
16K
$0000 – $3FFF
16K
$0000 – $3FFF
None
16 M
*
Lowest 10K of X data RAM and 410K of Y data RAM are shared memory that can be accessed by the core
and the EFCOP but not by the DMA controller.
Figure 3-3. Memory Switch On (MSW = 00), Cache Off, 24-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-11
Freescale Semiconductor, Inc.
Memory Maps
Program
$FFFFFF
X Data
Y Data
$FFFFFF
Internal I/O
$FFFF80
Internal
Reserved
$FFF000
External
$FFF000
Internal
Reserved
$FF00C0
Freescale Semiconductor, Inc...
$FF0000 Bootstrap ROM $FF0000
External
$00C000
Internal
Program RAM
95K
$004000
Reserved
Internal I/O
External
$FF0000
External
$00C000
Internal
Reserved
Internal X data
RAM 16K
$000000
Bit Settings
External I/O
Internal
Reserved
External
$018000
$000400
$000000
$FFFFFF
$FFFFC0
$FFFF80
$004000
Internal
Reserved
Internal Y data
RAM 16K
$000000
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
00
1
0
95K
$0400 – $BFFF
16K
$0000 – $3FFF
16K
$0000 – $3FFF
Enabled
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-4. Memory Switch On (MSW = 00), Cache On, 24-Bit Mode
3-12
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
Internal
Reserved
$FFF000
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
$018000
$014000
External
$FFF000
Internal
Reserved
External I/O
Internal I/O
External
Internal
Reserved
$FF0000
External
External
Reserved
$00C000
$00C000
Internal
Reserved
Internal
$006000
Program RAM
Internal X data
80K
RAM 24K
$000000
$000000
Bit Settings
$006000
$000000
Internal
Reserved
Internal Y data
RAM 24K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
01
0
0
80K
$0000 –
$13FFF
24K
$0000 – $5FFF
24K
$0000 – $5FFF
None
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-5. Memory Switch On (MSW = 01), Cache Off, 24-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-13
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
$FFF000
Internal
Reserved
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
$018000
$014000
External
$FFF000
Internal
Reserved
$000000
Internal I/O
External
Internal
Reserved
$FF0000
External
External
Reserved
$00C000
$000400
External I/O
Internal
Program RAM
79K
Reserved
$006000
$00C000
Internal
Reserved
$006000
Internal X data
RAM 24K
$000000
Bit Settings
$000000
Internal
Reserved
Internal Y data
RAM 24K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
01
1
0
79K
$0400 –
$13FFF
24K
$0000 – $5FFF
24K
$0000 – $5FFF
Enabled
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-6. Memory Switch On (MSW = 01), Cache On, 24-Bit Mode
3-14
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
Internal
Reserved
$FFF000
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
$FFF000
Internal
Reserved
Internal I/O
External
Internal
Reserved
$FF0000
External
$180000
$010000
External
External I/O
External
Reserved
$00C000
$00C000
Reserved
Reserved
$008000
Internal
Program RAM
Internal X data
64K
RAM 32K
$000000
$000000
Bit Settings
$008000
Internal Y data
RAM 32K
$000000
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
10
0
0
64K
$0000 – $FFFF
32K
$0000 – $7FFF
32K
$0000 – $7FFF
None
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-7. Memory Switch On (MSW = 10), Cache Off, 24-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
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3-15
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
$FFF000
Internal
Reserved
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
$000400
$000000
$FFF000
Internal
Reserved
Internal I/O
External
Internal
Reserved
$FF0000
External
$018000
$010000
External
External I/O
External
Reserved
$00C000
Internal
Program RAM
63K
Reserved
$008000
$00C000
Reserved
$008000
Internal X data
RAM 32K
$000000
Bit Settings
$000000
Reserved
Internal Y data
RAM 32K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
10
1
0
63K
$0400 – $FFFF
32K
$0000 – $7FFF
32K
$0000 – $7FFF
Enabled
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-8. Memory Switch On (MSW = 10), Cache On, 24-Bit Mode
3-16
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
Internal
Reserved
External
$FFF000
Internal
Reserved
$FF00C0
$FF0000 Bootstrap ROM $FF0000
Freescale Semiconductor, Inc...
$FFF000
External I/O
Internal I/O
External
Internal
Reserved
$FF0000
External
External
$018000
External
Reserved
$00C000
$00C000
$00C000
Reserved
$00A000
Internal
Program RAM
48K
$000000
$00A000
Internal Y data
RAM 40K
Internal X data
RAM 40K
$000000
$000000
Bit Settings
Reserved
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
11
0
0
48K
$0000 – $BFFF
40K
$0000 – $9FFF
40K
$0000 – $9FFF
None
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-9. Memory Switch On (MSW = 11), Cache Off, 24-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
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3-17
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFFFF
$FFFFFF
$FFFFFF
$FFFFC0
$FFFF80
Internal I/O
$FFFF80
Internal
Reserved
$FFF000
Freescale Semiconductor, Inc...
$FF00C0
$FF0000 Bootstrap ROM $FF0000
External
External
$FFF000
Internal
Reserved
Internal I/O
External
Internal
Reserved
$FF0000
External
$018000
External I/O
External
Reserved
$00C000
$000400
$000000
$00C000
Internal
$00A000
Program RAM
47K
Reserved
$00C000
Reserved
$00A000
Internal X data
RAM 40K
$000000
Bit Settings
$000000
Reserved
Internal Y data
RAM 40K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
11
1
0
47K
$0400 – $BFFF
40K
$0000 – $9FFF
40K
$0000 – $9FFF
Enabled
16 M
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-10. Memory Switch On (MSW = 11), Cache On, 24-Bit Mode
3-18
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FFFF
Internal I/O
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
External
External I/O
Internal I/O
External
$C000
$C000
$8000
Internal
Program RAM
32K
$0000
$0000
Bit Settings
MS
0
MSW
[1:0]
any
value
Internal
Y data RAM
48K
Internal
X data RAM
48K
$0000
Memory Configuration
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
0
1
32K
$0000 – $3FFF
48K
$0000 – $BFFF
48K
$0000 – $BFFF
None
64K
*Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and the
EFCOP but not by the DMA controller.
Figure 3-11. Memory Switch Off, Cache Off, 16-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-19
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
$FFFF
$FFFF
$FFFF
Internal I/O
$FF80
Freescale Semiconductor, Inc...
External
Y Data
External I/O
$FFC0
$FF80
Internal I/O
External
$C000
External
$C000
$8000
Internal
Program RAM
31K
$0400
$0000
Reserved
$0000
Bit Settings
MS
0
MSW
[1:0]
any
value
Internal
Y data RAM
48K
Internal
X data RAM
48K
$0000
Memory Configuration
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
1
31K
$0400 – $7FFF
48K
$0000 – $BFFF
48K
$0000 – $BFFF
Enabled
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-12. Memory Switch Off, Cache On, 16-Bit Mode
3-20
DSP56311 User’s Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FFFF
Internal I/O
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
Internal
Program RAM
64K
$C000
$C000
Reserved
$4000
$4000
Internal X data
RAM 16K
$0000
$0000
Bit Settings
Internal I/O
External
Reserved
$0000
External I/O
Internal Y data
RAM 16K
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
00
0
1
64K
$0000 – $FFFF
16K
$0000 – $3FFF
16K
$0000 – $3FFF
None
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-13. Memory Switch On (MSW = 00), Cache Off, 16-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
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3-21
Freescale Semiconductor, Inc.
Memory Maps
Program
$FFFF
X Data
Y Data
$FFFF
$FFFF
External I/O
Internal I/O
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
Internal
Program RAM
63K
External
$C000
$C000
Reserved
$0400
$0000
Reserved
Internal I/O
Reserved
$4000
$4000
Internal X data
RAM 16K
$0000
Internal Y data
RAM 16K
$0000
Bit Settings
Memory Configuration
MS
MSW
[1:0]
CE
SC
1
00
1
1
Program RAM
X Data RAM*
Y Data RAM*
Cache
63K
16K
$0400 – $FFFF $0000 – $3FFF
16K
$0000 – $3FFF
Enabled
Addressable
Memory Size
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-14. Memory Switch On (MSW = 00), Cache On, 16-Bit Mode
3-22
DSP56311 User’s Manual
For More Information On This Product,
Go to: www.freescale.com
Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
$FFFF
Y Data
$FFFF
$FFFF
Internal I/O
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
Internal
Program RAM
64K
Internal I/O
External
$C000
$C000
Reserved
Reserved
$6000
$6000
Internal Y data
RAM 24K
Internal X data
RAM 24K
$0000
$0000
External I/O
Bit Settings
$0000
Memory Configuration
MS
MSW
[1:0]
CE
SC
1
01
0
1
Program RAM
X Data RAM*
Y Data RAM*
64K
24K
$0000 – $FFFF $0000 – $5FFF
24K
$0000 – $5FFF
Cache
None
Addressable
Memory Size
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-15. Memory Switch On (MSW = 01), Cache Off, 16-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-23
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
$FFFF
$FFFF
Internal I/O
$FF80
Freescale Semiconductor, Inc...
Y Data
$FFFF
External I/O
$FFC0
$FF80
Internal I/O
External
Internal
Program RAM
63K
$C000
External
$C000
Reserved
$6000
$0400
$0000
Reserved
Reserved
$6000
Internal Y data
RAM 24K
Internal X data
RAM 24K
$0000
Bit Settings
$0000
Memory Configuration
MS
MSW
[1:0]
CE
SC
1
01
1
1
Program RAM
X Data RAM*
Y Data RAM*
Cache
63K
24K
$0400 – $FFFF $0000 – $5FFF
24K
$0000 – $5FFF
Enabled
Addressable
Memory Size
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-16. Memory Switch On (MSW = 01), Cache On, 16-Bit Mode
3-24
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FFFF
Internal I/O
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
$C000
Reserved
Reserved
$8000
$0000
$0000
Internal I/O
External
$C000
Internal
Program RAM
64K
External I/O
$8000
Internal X data
RAM 32K
Bit Settings
$0000
Internal Y data
RAM 32K
Memory Configuration
MS
MSW
[1:0]
CE
SC
1
10
0
1
Program RAM
X Data RAM*
Y Data RAM*
64K
32K
$0000 – $FFFF $0000 – $7FFF
32K
$0000 – $7FFF
Cache
None
Addressable
Memory Size
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-17. Memory Switch On (MSW = 10), Cache Off, 16-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
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3-25
Freescale Semiconductor, Inc.
Memory Maps
Program
$FFFF
X Data
$FFFF
Internal I/O
$FF80
Freescale Semiconductor, Inc...
Y Data
$FFFF
External I/O
$FFC0
$FF80
Internal I/O
External
Internal
Program RAM
63K
$C000
External
$C000
Reserved
$A000
$0400
$0000
Reserved
$0000
Bit Settings
Reserved
$A000
Internal X data
RAM 24K
$0000
Internal Y data
RAM 24K
Memory Configuration
MS
MSW
[1:0]
CE
SC
1
10
1
1
Program RAM
X Data RAM*
Y Data RAM*
Cache
63K
24K
$0400 – $FFFF $0000 – $9FFF
24K
$0000 – $9FFF
Enabled
Addressable
Memory Size
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-18. Memory Switch On (MSW = 10), Cache On, 16-Bit Mode
3-26
DSP56311 User’s Manual
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Go to: www.freescale.com
Motorola
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
Y Data
$FFFF
$FFFF
$FFFF
Internal I/O
Reserved
$FFC0
$FF80
$FF80
Freescale Semiconductor, Inc...
External
$C000
$A000
$C000
Internal
Program RAM
48K
$C000
$A000
Reserved
Reserved
Internal Y data
RAM 40K
Internal X data
RAM 40K
Bit Settings
Internal I/O
External
$0000
$0000
External I/O
$0000
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
11
0
1
48K
$0000 – $BFFF
40K
$0000 – $9FFF
40K
$0000 – $9FFF
None
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-19. Memory Switch On (MSW = 11), Cache Off, 16-Bit Mode
Motorola
Memory Configuration
For More Information On This Product,
Go to: www.freescale.com
3-27
Freescale Semiconductor, Inc.
Memory Maps
Program
X Data
$FFFF
$FFFF
Internal I/O
Reserved
Y Data
$FFFF
$FF80
External I/O
$FFC0
$FF80
Internal I/O
Freescale Semiconductor, Inc...
External
$C000
$A000
$C000
Internal
Program RAM
47K
$0400
$0000
Reserved
Reserved
External
$C000
$A000
Internal Y data
RAM 40K
Internal X data
RAM 40K
$0000
Bit Settings
Reserved
$0000
Memory Configuration
MS
MSW
[1:0]
CE
SC
Program RAM
X Data RAM*
Y Data RAM*
Cache
Addressable
Memory Size
1
11
1
1
47K
$0400 – $BFFF
40K
$0000 – $9FFF
40K
$0000 – $9FFF
Enabled
64K
*
Lowest 10K of X data RAM and 10K of Y data RAM are shared memory that can be accessed by the core and
the EFCOP but not by the DMA controller.
Figure 3-20. Memory Switch On (MSW = 11), Cache On, 16-Bit Mode
3-28
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Chapter 4
Core Configuration
Freescale Semiconductor, Inc...
This chapter presents DSP56300 core configuration details specific to the DSP56311.
These configuration details include the following:
■
Operating modes
■
Bootstrap program
■
Interrupt sources and priorities
■
DMA request sources
■
OMR
■
PLL control register
■
AA control registers
■
JTAG boundary scan register
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.
4.1 Operating Modes
The DSP56311 begins operation by leaving the Reset state and going into one of eight
operating modes. As the DSP56311 exits the Reset state, it loads the values of MODA,
MODB, MODC, and MODD into bits MA, MB, MC, and MD of the OMR. These bit
settings determine the chip’s operating mode, which in turn determines the bootstrap
program option the chip uses to start up.
Software can also directly set the OMR[MA–MD] bits. A jump directly to the bootstrap
program entry point ($FF0000) after the OMR bits are set causes the DSP56311 to execute
the specified bootstrap program option (except modes 0 and 8). Table 4-1 shows the
DSP56311 bootstrap operation modes, the corresponding settings of the external
operational mode signal lines (the OMR[MA–MD] bits), and the reset vector address to
which the DSP56311 jumps once it leaves the Reset state.
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Operating Modes
Table 4-1. DSP56311 Operating Modes
Reset
Vector
MODD
MODC
MODB
MODA
0
0
0
0
0
$C00000
Expanded mode
Bypasses the bootstrap ROM, and the DSP56311
starts fetching instructions beginning at address
$C00000. Memory accesses are performed using
SRAM memory access type with 31 wait states
and no address attributes selected (default).
Address $C00000 is reflected as address $00000
on Port A signals A0–A17.
1
0
0
0
1
$FF0000
Reserved
2
0
0
1
0
$FF0000
Reserved
3
0
0
1
1
$FF0000
Reserved
4
0
1
0
0
$FF0000
Reserved
5
0
1
0
1
$FF0000
Reserved
6
0
1
1
0
$FF0000
Reserved
7
0
1
1
1
$FF0000
Reserved
8
1
0
0
0
$008000
Expanded mode
Bypasses the bootstrap ROM, and the DSP56311
starts fetching instructions beginning at address
$008000. Memory accesses are performed using
SRAM memory access type with 31 wait states
and no address attributes selected.
9
1
0
0
1
$FF0000
Bootstrap from byte-wide memory
The bootstrap program loads instructions through
Port A from external byte-wide memory, starting at
P:$D00000. The SRAM memory access type is
selected by the values in address attribute register
1 (AAR1). Thirty-one wait states are inserted
between each memory access. Address $D00000
is reflected as address $00000 on Port A signals
A0–A17. The boot program concatenates every 3
bytes read from the external memory into a 24-bit
wide DSP56311 word.
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Mode
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Operating Modes
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Table 4-1. DSP56311 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
A
1
0
1
0
$FF0000
Bootstrap through SCI
Instructions are loaded through the SCI. The
bootstrap program sets the SCI to operate in 10-bit
asynchronous mode, with 1 start bit, 8 data bits, 1
stop bit, and no parity. Data is received in this
order: start bit, 8 data bits (LSB first), and one stop
bit. Data is aligned in the SCI receive data register
with the LSB of the least significant byte of the
received data appearing at Bit 0.The user must
provide an external clock source with a frequency
at least 16 times the transmission data rate. Each
byte received by the SCI is echoed back through
the SCI transmitter to the external transmitter. The
boot program concatenates every 3 bytes read
from the SCI into a 24-bit wide DSP56311 word.
B
1
0
1
1
$FF0000
Reserved
C
1
1
0
0
$FF0000
HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to interface with an ISA bus
or with the memory expansion port of a master
DSP563xx processor through the HI08. The HI08
pin configuration is optimized for connection to the
ISA bus or memory expansion port of a master
DSP based on the DSP56300 core.
D
1
1
0
1
$FF0000
HI08 bootstrap in HC11 nonmultiplexed mode
The bootstrap program sets the host interface to
interface with the Motorola HC11 microcontroller
through the HI08. The HI08 pin configuration is
optimized for connection to the Motorola HC11
nonmultiplexed bus.
E
1
1
1
0
$FF0000
HI08 bootstrap in 8051 multiplexed bus mode
The bootstrap program sets the host interface to
interface with the Intel 8051 bus through the HI08.
The program stored in this location, after testing
MODA, MODB, MODC, and MODD, bootstraps
through HI08. The HI08 pin configuration is
optimized for connection to the Intel 8051
multiplexed bus.
F
1
1
1
1
$FF0000
HI08 bootstrap in MC68302 bus mode
The bootstrap program sets the host interface to
interface with the Motorola MC68302 or MC68360
bus through the HI08. The HI08 pin configuration is
optimized for connection to a Motorola MC68302
or MC68360 bus.
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Bootstrap Program
4.2 Bootstrap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap
ROM located in program memory space at locations $FF0000–$FF00BF. The bootstrap
program can load any program RAM segment from an external byte-wide EPROM, the
SCI, or the host port. The bootstrap program code is listed in Appendix A.
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Upon exiting the Reset state, the DSP56311 samples the MODA-MODD signal lines and
loads their values into OMR[MA - MD]. The mode input signals (MODA–MODD) and
the resulting MA, MB, MC, and MD bits determine which bootstrap mode the DSP56311
enters (see Table 4-1).
Note:
To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0).
The loaded user program begins executing from the specified starting address.
You can invoke the bootstrap program options (except modes 0 and 8) at any time by
setting the MA, MB, MC, and MD bits in the OMR and jumping to the bootstrap program
entry point, $FF0000. Software can directly set the mode selection bits in the OMR.
Bootstrap modes 0 and 8 are the normal DSP56311 functioning modes. Bootstrap modes
9, A, and C–F select different specific bootstrap loading source devices. In these modes,
the bootstrap program expects the following data sequence when downloading the user
program through an external port:
1. Three bytes that specify the number of (24-bit) program words to be loaded
2. Three bytes that specify the (24-bit) start address where the user program loads in
the DSP56311 program memory
3. The user program (three bytes for each 24-bit program word)
Note:
The three bytes for each data sequence are loaded least significant byte first.
When the bootstrap program finishes loading the specified number of words, it jumps to
the specified starting address and executes the loaded program.
4.3 Interrupt Sources and Priorities
DSP56311 interrupt handling, like that for all DSP56300 family members, is optimized
for DSP applications. Refer to the chapter on interrupts in the DSP56300 Family Manual.
The interrupt table resides in the 256 locations of program memory to which the PCU
vector base address (VBA) register points.
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Interrupt Sources and Priorities
4.3.1 Interrupt Sources
Each interrupt is allocated two instructions in the table, resulting in 128 table entries for
interrupt handling. Table 4-2 shows the table entry address for each interrupt source. The
DSP56311 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56311, only some of the 128 vector addresses
are used for specific interrupt sources. The remaining interrupt vectors are reserved and
can be used for host NMI (IPL = 3) or for host command interrupt (IPL = 2). Unused
interrupt vector locations can be used for program or data storage.
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Table 4-2. Interrupt Sources
Interrupt
Starting Address
Interrupt
Priority Level
Range
VBA:$00
3
Hardware RESET
VBA:$02
3
Stack error
VBA:$04
3
Illegal instruction
VBA:$06
3
Debug request interrupt
VBA:$08
3
Trap
VBA:$0A
3
Nonmaskable interrupt (NMI)
VBA:$0C
3
Reserved
VBA:$0E
3
Reserved
VBA:$10
0–2
IRQA
VBA:$12
0–2
IRQB
VBA:$14
0–2
IRQC
VBA:$16
0–2
IRQD
VBA:$18
0–2
DMA channel 0
VBA:$1A
0–2
DMA channel 1
VBA:$1C
0–2
DMA channel 2
VBA:$1E
0–2
DMA channel 3
VBA:$20
0–2
DMA channel 4
VBA:$22
0–2
DMA channel 5
VBA:$24
0–2
TIMER 0 compare
VBA:$26
0–2
TIMER 0 overflow
VBA:$28
0–2
TIMER 1 compare
VBA:$2A
0–2
TIMER 1 overflow
VBA:$2C
0–2
TIMER 2 compare
VBA:$2E
0–2
TIMER 2 overflow
VBA:$30
0–2
ESSI0 receive data
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Interrupt Sources and Priorities
Table 4-2. Interrupt Sources (Continued)
Interrupt
Priority Level
Range
VBA:$32
0–2
ESSI0 receive data with exception status
VBA:$34
0–2
ESSI0 receive last slot
VBA:$36
0–2
ESSI0 transmit data
VBA:$38
0–2
ESSI0 transmit data with exception status
VBA:$3A
0–2
ESSI0 transmit last slot
VBA:$3C
0–2
Reserved
VBA:$3E
0–2
Reserved
VBA:$40
0–2
ESSI1 receive data
VBA:$42
0–2
ESSI1 receive data with exception status
VBA:$44
0–2
ESSI1 receive last slot
VBA:$46
0–2
ESSI1 transmit data
VBA:$48
0–2
ESSI1 transmit data with exception status
VBA:$4A
0–2
ESSI1 transmit last slot
VBA:$4C
0–2
Reserved
VBA:$4E
0–2
Reserved
VBA:$50
0–2
SCI receive data
VBA:$52
0–2
SCI receive data with exception status
VBA:$54
0–2
SCI transmit data
VBA:$56
0–2
SCI idle line
VBA:$58
0–2
SCI timer
VBA:$5A
0–2
Reserved
VBA:$5C
0–2
Reserved
VBA:$5E
0–2
Reserved
VBA:$60
0–2
Host receive data full
VBA:$62
0–2
Host transmit data empty
VBA:$64
0–2
Host command (default)
VBA:$66
0–2
Reserved
VBA:$68
0-2
EFCOP data input buffer empty
VBA:$6A
0-2
EFCOP data output buffer full
VBA:$6C
0-2
Reserved
VBA:$6E
0-2
Reserved
:
:
VBA:$FE
0–2
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Interrupt
Starting Address
4-6
Interrupt Source
:
Reserved
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Interrupt Sources and Priorities
4.3.2 Interrupt Priority Levels
There are two interrupt priority registers in the DSP56311. The IPR–C (Figure 4-1) is
dedicated to DSP56300 core interrupt sources, and IPR–P (Figure 4-2) is dedicated to
DSP56311 peripheral interrupt sources.
23
22
21
20
19
18
17
D5L1
D5L0
D4L1
D4L0
D3L1
D3L0
D2L1
16
15
D2L0 D1L1
14
13
12
D1L0
D0L1
D0L0
DMA0 IPL
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DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
11
10
9
8
7
6
5
IDL2
IDL1
IDL0
ICL2
ICL1
ICL0
IBL2
4
3
IBL1
IBL0
2
1
0
IAL2
IAL1
IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
Figure 4-1. Interrupt Priority Register C (IPR-C) (X:$FFFFFF)
23
22
21
20
19
18
17
16
15
14
13
12
reserved
11
FCL1
10
FCL0
9
8
T0L1 T0L0
7
6
5
SCL1 SCL0 S1L1
4
S1L0
3
2
S0L1
S0L0
1
0
HPL1 HPL0
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
EFCOP IPL
Figure 4-2. Interrupt Priority Register P (IPR-P) (X:$FFFFFE)
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Interrupt Sources and Priorities
.
Table 4-3. Interrupt Priority Level Bits
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IPL bits
Interrupts Enabled
Interrupts Masked
Interrupt Priority Level
0
No
—
0
0
1
Yes
0
1
1
0
Yes
0, 1
2
1
1
Yes
0, 1, 2
3
xxL1
xxL0
0
4.3.3 Interrupt Source Priorities Within an IPL
If more than one interrupt request is pending when an instruction executes, the interrupt
source with the highest IPL is serviced first. When several interrupt requests with the same
IPL are pending, another fixed-priority structure within that IPL determines which
interrupt source is serviced first. Table 4-4 shows this fixed-priority list of interrupt
sources within an IPL, from highest to lowest at each level The interrupt mask bits in the
Status Register (I[1:0]) can be programmed to ignore low priority level interrupt requests.
Table 4-4. Interrupt Source Priorities Within an IPL
Priority
Interrupt Source
Level 3 (nonmaskable)
Highest
Hardware RESET
Stack error
Illegal instruction
Debug request interrupt
Trap
Lowest
Nonmaskable interrupt
Levels 0, 1, 2 (maskable)
Highest
IRQA (external interrupt)
IRQB (external interrupt)
IRQC (external interrupt)
IRQD (external interrupt)
DMA channel 0 interrupt
DMA channel 1 interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
DMA channel 4 interrupt
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Interrupt Sources and Priorities
Table 4-4. Interrupt Source Priorities Within an IPL (Continued)
Priority
Interrupt Source
DMA channel 5 interrupt
Highest
Host command interrupt
Host transmit data empty
Host receive data full
ESSI0 RX data with exception interrupt
ESSI0 RX data interrupt
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ESSI0 receive last slot interrupt
ESSI0 TX data with exception interrupt
ESSI0 transmit last slot interrupt
ESSI0 TX data interrupt
ESSI1 RX data with exception interrupt
ESSI1 RX data interrupt
ESSI1 receive last slot interrupt
ESSI1 TX data with exception interrupt
ESSI1 transmit last slot interrupt
ESSI1 TX data interrupt
SCI receive data with exception interrupt
SCI receive data
SCI transmit data
SCI idle line
SCI timer
TIMER0 overflow interrupt
TIMER0 compare interrupt
TIMER1 overflow interrupt
TIMER1 compare interrupt
TIMER2 overflow interrupt
TIMER2 compare interrupt
EFCOP data input buffer empty
Lowest
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EFCOP data output buffer full
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Interrupt Sources and Priorities
4.3.4 DMA Request Sources
The DMA request source bits (DRS[4:0]) in the DMA control/status registers) encode the
source of DMA requests that trigger DMA transfers. The DMA request sources may be
internal peripherals or external devices requesting service through the IRQA, IRQB, IRQC, or
IRQD signals. Table 4-5 shows the values of the DRS bits.
Table 4-5. DMA Request Sources
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DMA Request Source Bits
DRS4 . . . DRS0
00000
External (IRQA signal)
00001
External (IRQB signal)
00010
External (IRQC signal)
00011
External (IRQD signal)
00100
Transfer done from DMA channel 0
00101
Transfer done from DMA channel 1
00110
Transfer done from DMA channel 2
00111
Transfer done from DMA channel 3
01000
Transfer done from DMA channel 4
01001
Transfer done from DMA channel 5
01010
ESSI0 receive data (RDF0 = 1)
01011
ESSI0 transmit data (TDE0 = 1)
01100
ESSI1 receive data (RDF1 = 1)
01101
ESSI1 transmit data (TDE1 = 1)
01110
SCI receive data (RDRF = 1)
01111
SCI transmit data (TDRE = 1)
10000
Timer0 (TCF0 = 1)
10001
Timer1 (TCF1 = 1)
10010
Timer2 (TCF2 = 1)
10011
Host receive data full (HRDF = 1)
10100
Host transmit data empty (HTDE = 1)
10101
EFCOP input buffer empty (FDIBE=1)
10110
EFCOP output buffer full (FDOBF=1)
10111–11111
Note:
4-10
Requesting Device
Reserved
The lowest 10K of X data RAM and 10K of Y data RAM are shared memory
that can be accessed by the core and the EFCOP but not by the DMA controller.
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Operating Mode Register (OMR)
4.4 Operating Mode Register (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes
(EOM and COM) control the chip’s operating mode. The high byte (SCS) controls and
monitors the stack extension. The OMR control bits are shown in Figure 4-3.
SCS
23
22
21
20
19
EOM
18
17
16
15
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MSW[1:0] SEN WRPEOVEUN XYS
MSW1–
MSW0 Memory Switch Configuration
14
13
12
11
COM
10
9
8
7
6
APD ABE BRT TAS BE CDP1:0 MS SD
APD
Address Attribute Priority
Disable
5
4
3
2
1
0
EBD MD MC MB MA
MS
Memory Switch Mode
SD
Stop Delay
SEN
Stack Extension Enable
ABE
Async. Bus Arbitration Enable
EBD
External Bus Disable
WRP
Stack Extension Wrap Flag
BRT
Bus Release Timing
MD
Chip Operating Mode D
EOV
Stack Extension Overflow Flag
TAS
TA Synchronize Select
MC
Chip Operating Mode C
EUN
Stack Extension Underflow
Flag
BE
Cache Burst Mode Enable
MB
Chip Operating Mode B
XYS
Stack Extension Space Select
MA
Chip Operating Mode A
CDP1 Core-DMA Priority 1
CDP0 Core-DMA Priority 0
- Reserved bit; read as zero; should be written with zero for future compatibility
Figure 4-3. DSP56311 Operating Mode Register (OMR) Format
The EOM and COM bytes are affected only by processor reset and by instructions directly
referencing the OMR (i.e., ANDI, ORI, and other instructions, such as MOVEC, that
specify OMR as a destination). The SCS byte is referenced implicitly by some
instructions, such as DO, JSR, and RTI, or directly by the MOVEC instruction. During
processor reset, the chip operating mode bits (MD, MC, MB, and MA) are loaded from the
external mode select pins MODD, MODC, MODB, and MODA respectively. Table 4-6
defines the DSP56311 OMR bits.
Table 4-6. Operating Mode Register (OMR) Bit Definitions
Bit Number
Bit Name
23
22 – 21
Motorola
MSW[1 –0]
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
0
Memory Switch Configuration
Reallocate portions of X and Y data RAM as program RAM. Memory
Switch Mode is enabled when the Memory Switch bit, OMR[7] is set.
The Memory Switch Configuration (MSW) bits determine what portion of
the higher locations of internal X and Y data memory are switched to
internal program memory when the Memory Switch Mode is enabled.
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Operating Mode Register (OMR)
Table 4-6. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Name
Reset Value
20
SEN
0
Stack Extension Enable
Enables/disables the stack extension in data memory. If the SEN bit is
set, the extension is enabled. Hardware reset clears this bit, so the
default out of reset is a disabled stack extension.
19
WRP
0
Stack Extension Wrap Flag
Set when copying from the on-chip hardware stack (System Stack
Register file) to the stack extension memory begins. You can use this
flag during the debugging phase of the software development to
evaluate and increase the speed of software-implemented algorithms.
The WRP flag is a sticky bit (i.e., cleared only by hardware reset or by
an explicit MOVEC operation to the OMR).
18
EOV
0
Stack Extension Overflow Flag
Set when a stack overflow occurs in Stack Extended mode. Extended
stack overflow is recognized when a push operation is requested while
SP = SZ (Stack Size register), and the Extended mode is enabled by
the SEN bit. The EOV flag is a sticky bit (i.e., cleared only by hardware
reset or by an explicit MOVEC operation to the OMR). The transition of
the EOV flag from zero to one causes a Priority Level 3 (Non-maskable)
stack error exception.
17
EUN
0
Stack Extension Underflow Flag
Set when a stack underflow occurs in Extended Stack mode. Extended
stack underflow is recognized when a pull operation is requested, SP =
0, and the SEN bit enables Extended mode. The EUN flag is a sticky bit
(i.e., cleared only by hardware reset or by an explicit MOVEC operation
to the OMR). Transition of the EUN flag from zero to one causes a
Priority Level 3 (Non-maskable) stack error exception.
NOTE: While the chip is in Extended Stack mode, the UF bit in the SP
acts like a normal counter bit.
16
XYS
0
Stack Extension XY Select
Determines whether the stack extension is mapped onto X or Y memory
space. If the bit is clear, then the stack extension is mapped onto the X
memory space. If the XYS bit is set, the stack extension is mapped to
the Y memory space.
0
Reserved. Set to 0 for future compatibility.
0
Address Attribute Priority Disable
Disables the priority assigned to the Address Attribute signals
(AA0-AA3). When APD = 0 (default setting), the four Address Attribute
signals each have a certain priority: AA3 has the highest priority, AA0
has the lowest priority. Therefore, only one AA signal can be active at
one time. This allows continuous partitioning of external memory;
however, certain functions, such as using the AA signals as additional
address lines, require the use of additional interface hardware. When
APD is set, the priority mechanism is disabled, allowing more than one
AA signal to be active simultaneously. Therefore, the AA signals can be
used as additional address lines without the need for additional
interface hardware. For details on the Address Attribute Registers, see
Section 4.8, "Address Attribute Registers (AAR0–AAR3)," on page
4-22.
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Bit Number
15
14
4-12
APD
Description
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Operating Mode Register (OMR)
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Table 4-6. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
13
ABE
0
Asynchronous Bus Arbitration Enable
Eliminates the setup and hold time requirements for BB and BG, and
substitutes a required non-overlap interval between the deassertion of
one BG input to a DSP56300 family device and the assertion of a
second BG input to a second DSP56300 family device on the same bus.
When the ABE bit is set, the BG and BB inputs are synchronized. This
synchronization causes a delay between a change in BG or BB until this
change is actually accepted by the receiving device.
12
BRT
0
Bus Release Timing
Selects between fast or slow bus release. If BRT is cleared, a Fast Bus
Release mode is selected (i.e., no additional cycles are added to the
access and BB is not guaranteed to be the last Port A pin that is
tri-stated at the end of the access). If BRT is set, a Slow Bus Release
mode is selected (i.e., an additional cycle is added to the access, and
BB is the last Port A pin that is tri-stated at the end of the access).
11
TAS
0
TA Synchronize Select
Selects the synchronization method for the input Port A pin—TA
(Transfer Acknowledge). If TAS is cleared, you are responsible for
asserting the TA pin in synchrony with the chip clock, as described in
the technical data sheet. If TAS is set, the TA input pin is synchronized
inside the chip, thus eliminating the need for an off-chip synchronizer.
Note that the TAS bit has no effect when the TA pin is deasserted: you
are responsible for deasserting the TA pin in synchrony with the chip
clock, regardless of the value of TAS.
10
BE
0
Cache Burst Mode Enable
Enables/disables Burst mode in the memory expansion port during an
instruction cache miss. If the bit is cleared, Burst mode is disabled and
only one program word is fetched from the external memory when an
instruction cache miss condition is detected. If the bit is set, Burst mode
is enabled, and up to four program words are fetched from the external
memory when an instruction cache miss is detected.
9–8
CDP
11
Core-DMA Priority
Specify the priority of core and DMA accesses to the external bus.
Motorola
00
Determined by comparing status register CP[1:0] to the
active DMA channel priority
01
DMA accesses have higher priority than core accesses
10
DMA accesses have the same priority as the core
accesses
11
DMA accesses have lower priority than the core accesses
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Operating Mode Register (OMR)
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Table 4-6. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
7
MS
0
Memory Switch Mode
Allows some internal data memory (X, Y, or both) to become part of the
chip internal Program RAM.
Notes:
1. Program data placed in the Program RAM/Instruction Cache
area changes its placement after the MS bit is set (i.e., the
Instruction Cache always uses the lowest internal Program RAM
addresses).
2. To ensure proper operation, place six NOP instructions after the
instruction that changes the MS bit.
3. To ensure proper operation, do not set the MS bit while the
Instruction Cache is enabled (CE bit is set in SR).
6
SD
0
Stop Delay Mode
Determines the length of the delay invoked when the core exits the Stop
state. The STOP instruction suspends core processing indefinitely until
a defined event occurs to restart it. If SD is cleared, a 128K clock cycle
delay is invoked before a STOP instruction cycle continues. However, if
SD is set, the delay before the instruction cycle continues is 16 clock
cycles. The long delay allows a clock stabilization period for the internal
clock to begin oscillating and to stabilize. When a stable external clock
is used, the shorter delay allows faster start-up of the DSP56300 core.
0
Reserved. Write to zero for future compatibility.
5
4
EBD
0
External Bus Disable
Disables the external bus controller to reduce power consumption when
external memories are not used. When EBD is set, the external bus
controller is disabled and external memory cannot be accessed. When
EBD is cleared, the external bus controller is enabled and external
access can be performed. Hardware reset clears the EBD bit.
3–0
MD – MA
*
Chip Operating Mode
Indicate the operating mode of the DSP56300 core. On hardware reset,
these bits are loaded from the external mode select pins, MODD,
MODC, MODB, and MODA, respectively. After the DSP56300 core
leaves the Reset state, MD, MC, MB, and MA can be changed under
program control.
* The MD – MA bits reflect the corresponding value of the mode input (i.e., MODD, MODC, MODB, or MODA),
respectively.
4-14
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Status Register (SR)
4.5 Status Register (SR)
Freescale Semiconductor, Inc...
The Status Register (SR) (Figure 4-4) is a 24-bit register that indicates the current system
state of the processor and the results of previous arithmetic computations. The SR is
pushed onto the system stack when program looping is initialized or a JSR is performed,
including long interrupts. The SR consists of the following three special-purpose 8-bit
control registers:
■
Extended Mode Register (EMR) (SR[23:16]) and Mode Register (MR) (SR[15:8])
—Define the current system state of the processor. The bits in both registers are
affected by hardware reset, exception processing, ENDDO (end current DO loop)
instructions, RTI (return from interrupt) instructions, and TRAP instructions. In
addition, the EMR bits are affected by instructions that specify SR as their
destination, DO FOREVER instructions, BRKcc instructions, and instructions that
specify SR as a destination (e.g., MOVEC). During hardware reset, all EMR bits
are cleared. The MR register bits are affected by DO instructions, and instructions
that directly reference the MR (e.g., ANDI, ORI, or instructions, such as MOVEC,
that specify SR as the destination). During processor reset, the interrupt mask bits
are set and all other bits are cleared.
■
Condition Code Register (CCR) (SR[7:0])—Defines the results of previous
arithmetic computations. The CCR bits are affected by Data Arithmetic Logic Unit
(Data ALU) operations, parallel move operations, instructions that directly
reference the CCR (ORI and ANDI), and instructions that specify SR as a
destination (e.g., MOVEC). Parallel move operations affect only the S and L bits of
the CCR. During processor reset, all CCR bits are cleared.
The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Motorola DSPs. Bit definitions in the following paragraphs
identify the bits within the SR and not within the subregister.
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Status Register (SR)
Extended Mode Register (EMR)
23
22
CP1:0
21
20
19
18
17
16
Mode Register (MR)
15
14
13
12
SA FV LF DM SC
RM SM CE
11
10
S1:0
Condition Code Register (CCR)
9
8
I1:0
7
6
5
4
3
2
1
0
S
L
E
U
N
Z
V
C
0
0
0
0
0
0
0
0
Reserved bit. Read as zero. Write with zero for future compatibility
Values after reset:
Freescale Semiconductor, Inc...
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
CP1
Core Priority Bit 1
LF
DO-Loop Flag
S
Scaling Flag
CP0
Core Priority Bit 0
DM
Double Precision Multiply
L
Limit Flag
RM
Rounding Mode
SC
Sixteen-bit Compatibility
E
Extension Flag
SM
Arithmetic Saturation Mode
S1
Scaling Mode Bit 1
U
Unnormalized Flag
CE
Instruction Cache Enable
S0
Scaling Mode Bit 0
N
Negative Flag
SA
Sixteen-Bit Arithmetic
I1
Interrupt Mask Bit 1
Z
Zero Flag
FV
DO-Forever Flag
I0
Interrupt Mask Bit 0
V
Overflow Flag
C
Carry Flag
Figure 4-4. Status Register
Table 4-7. Status Register Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23 – 22
CP[1 – 0]
11
Core Priority
Under control of the CDP[1:0] bits in the OMR, the CP bits specify the
priority of core accesses to external memory. These bits are compared
against the priority bits of the active DMA channel. If the core priority is
greater than the DMA priority, the DMA waits for a free time slot on the
external bus. If the core priority is less than the DMA priority, the core waits
for a free time slot on the external bus. If the core priority equals the DMA
priority, the core and DMA access the external bus in a round robin pattern
(e.g., ... P, X, Y, DMA, P, X, Y, ...).
Priority
Mode
Dynamic
Static
4-16
Core
Priority
DMA
Priority
OMR
(CDP[1-0])
SR (CP[1 - 0])
0
Determined
(Lowest) by DCRn
(DPR[1:0])
1
for active
DMA
2
channel
3
(Highest)
00
00
00
01
00
10
00
11
core < DMA
01
xx
core = DMA
10
xx
core > DMA
11
xx
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Status Register (SR)
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Table 4-7. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
21
RM
0
Rounding Mode
Selects the type of rounding performed by the Data ALU during arithmetic
operations. If RM is cleared, convergent rounding is selected. If RM is set,
two’s-complement rounding is selected.
20
SM
0
Arithmetic Saturation Mode
Selects automatic saturation on 48 bits for the results going to the
accumulator. This saturation is performed by a special circuit inside the
MAC unit. The purpose of this bit is to provide an Arithmetic Saturation
mode for algorithms that do not recognize or cannot take advantage of the
extension accumulator.
19
CE
0
Cache Enable
Enables/disables the instruction cache controller. If CE is set, the cache is
enabled, and instructions are cached into and fetched from the internal
Program RAM. If CE is cleared, the cache is disabled and the DSP56300
core fetches instructions from external or internal program memory,
according to the memory space table of the specific DSP56300 core-based
device.
NOTE: To ensure proper operation, do not clear Cache Enable mode while
Burst mode is enabled (OMR[BE] is set).
0
Reserved. Write to zero for future compatibility.
18
17
SA
0
Sixteen-Bit Arithmetic Mode
Affects data width functionality, enabling the Sixteen-bit Arithmetic mode of
operation. When SA is set, the core uses 16-bit operations instead of 24-bit
operations. In this mode, 16-bit data is right-aligned in the 24-bit memory
locations, registers, and 24-bit register portions. Shifting, limiting, rounding,
arithmetic instructions, and moves are performed accordingly. For details
on Sixteen-Bit Arithmetic mode, consult the DSP56300 Family Manual.
16
FV
0
DO FOREVER Flag
Set when a DO FOREVER loop executes. The FV flag, like the LF flag, is
restored from the stack when a DO FOREVER loop terminates. Stacking
and restoring the FV flag when initiating and exiting a DO FOREVER loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the system stack is pulled and the
value of the FV bit is restored.
15
LF
0
Do Loop Flag
When a program loop is in progress, enables the detection of the end of the
loop. The LF is restored from stack when a program loop terminates.
Stacking and restoring the LF when initiating and exiting a program loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the System Stack is pulled and the LF
bit value is restored.
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Status Register (SR)
Table 4-7. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
14
DM
0
Description
Double-Precision Multiply Mode
Enables four multiply/MAC operations to implement a double-precision
algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing
the DM bit disables the mode.
Freescale Semiconductor, Inc...
NOTE: The Double-Precision Multiply mode is supported to maintain object
code compatibility with devices in the DSP56000 family. For a more
efficient way of executing double precision multiply, refer to the chapter on
the Data Arithmetic Logic Unit in the DSP56300 Family Manual.
In Double-Precision Multiply mode, the behavior of the four specific
operations listed in the double-precision algorithm is modified. Therefore,
do not use these operations (with those specific register combinations) in
Double-Precision Multiply mode for any purpose other than the double
precision multiply algorithm. All other Data ALU operations (or the four
listed operations, but with other register combinations) can be used.
The double-precision multiply algorithm uses the Y0 Register at all stages.
Therefore, do not change Y0 when running the double-precision multiply
algorithm. If the Data ALU must be used in an interrupt service routine, Y0
should be saved with other Data ALU registers to be used and restored
before the interrupt routine terminates.
13
SC
0
Sixteen-bit Compatibility mode
Affects addressing functionality, enabling full compatibility with object code
written for the DSP56000 family. When SC is set, MOVE operations to/from
any of the following PCU registers clear the eight MSBs of the destination:
LA, LC, SP, SSL, SSH, EP, SZ, VBA and SC. If the source is either the SR
or OMR, then the eight MSBs of the destination are also cleared. If the
destination is either the SR or OMR, then the eight MSBs of the destination
are left unchanged. To change the value of one of the eight MSBs of the
SR or OMR, clear SC.
SC also affects the contents of the Loop Counter Register. If SC is cleared
(normal operation), then a loop count value of zero causes the loop body to
be skipped, and a loop count value of $FFFFFF causes the loop to execute
the maximum number of 224 – 1 times. If the SC bit is set, a loop count
value of zero causes the loop to execute 216 times, and a loop count value
of $FFFFFF causes the loop to execute 216 – 1 times.
NOTE: Due to pipelining, a change in the SC bit takes effect only after
three instruction cycles. Insert three NOP instructions after the instruction
that changes the value of this bit to ensure proper operation.
12
4-18
0
Reserved. Set to 0 for future compatibility.
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Status Register (SR)
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Table 4-7. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
11 – 10
S1/S0
0
Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling
mode affects data read from the A or B accumulator registers out to the
X-data bus (XDB) and Y-data bus (YDB). Different scaling modes can be
used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point arithmetic.
The scaling mode also affects the MAC rounding position to maintain
proper rounding when different portions of the accumulator registers are
read out to the XDB and YDB. Scaling mode bits are cleared at the start of
a long Interrupt Service Routine and during a hardware reset.
9–8
I1/I0
11
Interrupt Mask
Reflect the current Interrupt Priority Level (IPL) of the processor and
indicate the IPL needed for an interrupt source to interrupt the processor.
The current IPL of the processor can be changed under software control.
The interrupt mask bits are set during hardware reset, but not during
software reset.
Priority
Lowest
Highest
Exceptions
Permitted
I1
I0
Exceptions Masked
0
0
IPL 0, 1, 2, 3
None
0
1
IPL 1, 2, 3
IPL 0
1
0
IPL 2, 3
IPL 0, 1
1
1
IPL 3
IPL 0, 1, 2
7
S
0
Scaling
Set when a result moves from accumulator A or B to the XDB or YDB
buses (during an accumulator to memory or accumulator to register move)
and remains set until explicitly cleared; that is, the S bit is a sticky bit. The
logical equations of this bit are dependent on the Scaling mode. The
scaling bit is set if the absolute value in the accumulator, before scaling, is
> 0.25 or < 0.75.
6
L
0
Limit
Set if the overflow bit is set or if the data shifter/limiter circuits perform a
limiting operation. In Arithmetic Saturation mode, the L bit is also set when
an arithmetic saturation occurs in the Data ALU result; otherwise, it is not
affected. The L bit is cleared only by a processor reset or by an instruction
that specifically clears it (i.e., a sticky bit); this allows the L bit to be used as
a latching overflow bit. The L bit is affected by data movement operations
that read the A or B accumulator registers.
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Status Register (SR)
Table 4-7. Status Register Bit Definitions (Continued)
Bit Name
Reset Value
Description
5
E
1
Extension
Cleared if all the bits of the integer portion of the 56-bit result are all ones or
all zeros; otherwise, this bit is set. The Scaling mode defines the integer
portion. If the E bit is cleared, then the low-order fraction portion contains all
the significant bits; the high-order integer portion is sign extension. In this
case, the accumulator extension register can be ignored. If the E bit is set,
it indicates that the accumulator extension register is in use.
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Bit Number
4
4-20
U
0
S1
S0
Scaling Mode
Integer Portion
0
0
No Scaling
Bits
55,54..............48,47
0
1
Scale Down
Bits
55,54..............49,48
1
0
Scale Up
Bits
55,54..............47,46
Unnormalized
Set if the two MSBs of the Most Significant Portion (MSP) of the result are
identical; otherwise, this bit is cleared. The MSP portion of the A or B
accumulators is defined by the Scaling mode.
S1
S0
Scaling Mode
Integer Portion
0
0
No Scaling
U = (Bit 47 xor Bit 46)
0
1
Scale Down
U = (Bit 48 xor Bit 47)
1
0
Scale Up
U = (Bit 46 xor Bit 45)
3
N
0
Negative
Set if the MSB of the result is set; otherwise, this bit is cleared.
2
Z
0
Zero
Set if the result equals zero; otherwise, this bit is cleared.
1
V
0
Overflow
Set if an arithmetic overflow occurs in the 56-bit result; otherwise, this bit is
cleared. V indicates that the result cannot be represented in the
accumulator register (i.e., the register overflowed). In Arithmetic Saturation
mode, an arithmetic overflow occurs if the Data ALU result is not
representable in the accumulator without the extension part (i.e., 48-bit
accumulator or the 32-bit accumulator in Arithmetic Sixteen-bit mode).
0
C
0
Carry
Set if a carry is generated by the MSB resulting from an addition operation.
This bit is also set if a borrow is generated in a subtraction operation;
otherwise, this bit is cleared. The carry or borrow is generated from Bit 55
of the result. The C bit is also affected by bit manipulation, rotate, and shift
instructions.
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PLL Control Register (PCTL)
4.6 PLL Control Register (PCTL)
The PCTL is an X-I/O mapped, read/write register that directs the operation of the on-chip
PLL. (See Figure 4-5.)
23
22
21
20
19
18
17
16
15
14
13
12
PD3
PD2
PD1
PD0
COD
PEN
PSTP
XTLD
XTLR
DF2
DF1
DF0
11
10
9
8
7
6
5
4
3
2
1
0
MF11
MF10
MF9
MF8
MF7
MF6
MF5
MF4
MF3
MF2
MF1
MF0
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Figure 4-5. PLL Control Register (PCTL)
Table 4-8 defines the DSP56311 PCTL bits.
Table 4-8. PLL Control Register (PCTL) Bit Definitions
Bit Number
Bit Name
Reset Value
23 – 20
PD[3 – 0]
0
19
COD
Clock Output Disable
Controls the output buffer of the clock at the CLKOUT pin. When
COD is set, the CLKOUT output is pulled high. When COD is
cleared, the CLKOUT pin provides a 50 percent duty cycle clock.
18
PEN
PLL Enable
Enables PLL operation.
17
PSTP
PLL Stop State
Controls PLL and on-chip crystal oscillator behavior during the
stop processing state.
16
XTLD
XTAL Disable
Controls the on-chip crystal oscillator XTAL output. The XTLD bit
is cleared during DSP56311 hardware reset, so the XTAL output
signal is active, permitting normal operation of the crystal
oscillator.
15
XTLR
14–12
DF
0
Description
Predivider Factor Bits
Define the predivision factor (PDF) to be applied to the PLL input
frequency. The PD[3:0] bits are cleared during DSP56311
hardware reset, which corresponds to a PDF of one.
Crystal Range
Controls the on-chip crystal oscillator transconductance. The
XTLR bit is set to a predetermined value during hardware reset. In
the DSP56311, this value is zero.
Division Factor
Define the DF of the low-power divider. These bits specify the DF
as a power of two in the range from 20 to 27.
11–0
Motorola
MF[1 –0]
0
PLL Multiplication Factor
Define the multiplication factor that is applied to the PLL input
frequency. The MF bits are cleared during DSP56311 hardware
reset and thus correspond to an MF of one.
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Device Identification Register (IDR)
4.7 Device Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family
members. It specifies the derivative number and revision number of the device. This
information is used in testing or by software. Figure 4-6 shows the contents of the IDR.
Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on.
Changing the following bits may cause the PLL to lose lock and re-lock according to their
new value: PD[3 – 0], PEN, XTLR, and MF.
.
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23
16
15
12
11
0
Reserved
Revision Number
Derivative Number
$00
$0
$311
Figure 4-6. Identification Register Configuration (Revision 0)
4.8 Address Attribute Registers (AAR0–AAR3)
The Address Attribute Registers (AAR0–AAR3) are read/write registers that control the
activity of the AA0–AA3/RAS0–RAS3 pins. The associated AAn/RASn pin is asserted if the
address defined by the BAC bits in the associated AAR matches the exact number of
external address bits defined by the BNC bits, and the external address space (X data, Y
data, or program) is enabled by the AAR. Figure 4-7 shows an AAR register; Table 4-9
lists the bit definitions. Note that the DSP56311 does not support address multiplexing.
4-22
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Address Attribute Registers (AAR0–AAR3)
23
22
21
20
19
18
17
16
15
14
13
12
BAC11BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0
Address to Compare
11
10
9
8
7
6
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BNC3 BNC2 BNC1 BNC0 BPAC
5
4
3
2
1
0
BYEN BXEN BPEN BAAP BAT1 BAT0
External Access Type
AA pin polarity
Program space Enable
X data space Enable
Y data space Enable
Reserved
Packing Enable
Number of Address bit to
compare
- Reserved Bit. Write to zero for future compatibility.
Figure 4-7. Address Attribute Registers (AAR0–AAR3)
(X:$FFFFF9–$FFFFF6)
Table 4-9. Address Attribute Registers (AAR0–AAR3) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23 – 12
BAC[11 – 0]
0
Bus Address to Compare
Read/write control bits that define the upper 12 bits of the 24-bit address
with which to compare the external address to determine whether to assert
the corresponding AA/RAS signal. This is also true of 16-bit compatibility
mode. The BNC[3:0] bits define the number of address bits to compare.
11 – 8
BNC[3 – 0]
0
Bus Number of Address Bits to Compare
Specify the number of bits (from the BAC bits) that are compared to the
external address. The BAC bits are always compared with the Most
Significant Portion of the external address (e.g., if BNC[3:0] = 0011, then
the BAC[11:9] bits are compared to the 3 MSBs of the external address). If
no bits are specified (i.e., BNC[3:0] = 0000), the AA signal is activated for
the entire 16 M-word space identified by the space enable bits (BPEN,
BXEN, BYEN), but only when the address is external to the internal
memory map. The combinations BNC[3:0] = 1111, 1110, 1101 are
reserved.
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Address Attribute Registers (AAR0–AAR3)
Table 4-9. Address Attribute Registers (AAR0–AAR3) Bit Definitions
Bit Name
Reset Value
Description
7
BPAC
0
Bus Packing Enable
Enables/disables the internal packing/unpacking logic. When BPAC is set,
packing is enabled. In this mode each DMA external access initiates three
external accesses to an 8-bit wide external memory (the addresses for
these accesses are DAB, then DAB + 1 and then DAB + 2). Packing to a
24-bit word (or unpacking from a 24-bit word to three 8-bit words) is done
automatically by the expansion port control hardware. The external memory
should reside in the eight Least Significant Bits (LSBs) of the external data
bus, and the packing (or unpacking for external write accesses) occurs in
“Little Endian” order (i.e., the low byte is stored in the lowest of the three
memory locations and is transferred first; the middle byte is
stored/transferred next; and the high byte is stored/transferred last). When
this bit is cleared, the expansion port control logic assumes a 24-bit wide
external memory.
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Bit Number
NOTES:
1. BPAC is used only for DMA accesses and not core accesses.
2. To ensure sequential external accesses, the DMA address should
advance three steps at a time in two-dimensional mode with a row
length of one and an offset size of three. For details, refer to
Motorola application note, APR23/D, Using the DSP56300 Direct
Memory Access Controller.
3. To prevent improper operation, DMA address + 1 and DMA
address + 2 should not cross the AAR bank borders.
4. Arbitration is not allowed during the packing access (i.e., the three
accesses are treated as one access with respect to arbitration, and
the bus mastership is not released during these accesses).
6
Reserved. Set to 0 for future compatibility.
5
BYEN
0
Bus Y Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during
external Y data space accesses. When set, BYEN enables the comparison
of the external address to the BAC bits during external Y data space
accesses. If BYEN is cleared, no address comparison is performed.
4
BXEN
0
Bus X Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during
external X data space accesses. When set, BXEN enables the comparison
of the external address to the BAC bits during external X data space
accesses. If BXEN is cleared, no address comparison is performed.
3
BPEN
0
Bus Program Memory Enable
A read/write control bit that enables/disables the AA/RAS pin and logic
during external program space accesses. When set, BPEN enables the
comparison of the external address to the BAC bits during external program
space accesses. If BPEN is cleared, no address comparison is performed.
2
4-24
0
BAAP
0
Bus Address Attribute Polarity
A read/write Bus Address Attribute Polarity (BAAP) control bit that defines
whether the AA/RAS signal is active low or active high. When BAAP is
cleared, the AA/RAS signal is active low (useful for enabling memory
modules or for DRAM Row Address Strobe). If BAAP is set, the appropriate
AA/RAS signal is active high (useful as an additional address bit).
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JTAG Boundary Scan Register (BSR)
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Table 4-9. Address Attribute Registers (AAR0–AAR3) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
1-0
BAT
0
Bus Access Type
Read/write bits that define the type of external memory (DRAM or SRAM)
to access for the area defined by the BAC[11:0],BYEN, BXEN, and BPEN
bits. The encoding of BAT[1:0] is:
00 = Reserved
01 = SRAM access
10 = DRAM access
11 = Reserved
When the external access type is defined as a DRAM access (BAT[1:0] =
10), AA/RAS acts as a Row Address Strobe (RAS) signal. Otherwise, it acts
as an Address Attribute signal. External accesses to the default area
always execute as if BAT[1:0] = 01 (i.e., SRAM access).
4.9 JTAG Identification (ID) Register
The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes
the component on a board according to the IEEE 1149.1 standard. Figure 4-8 shows the
JTAG ID register configuration. Version information corresponds to the revision number
($0 for revision 0, $1 for revision A, etc.).
I)
31
28
27
22
21
12
11
1
0
Version Information
Design Center
Number
Sequence
Number
Manufacturer
Identity
1
0000
000110
0000001011
00000001110
1
Figure 4-8. JTAG Identification Register Configuration (Revision 0)
4.10 JTAG Boundary Scan Register (BSR)
The BSR in the DSP56311 JTAG implementation contains bits for all device signals,
clock pins, and their associated control signals. All DSP56311 bidirectional pins have a
corresponding register bit in the BSR for pin data and are controlled by an associated
control bit in the BSR. For details on the BSR, consult the DSP56300 Family Manual.
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JTAG Boundary Scan Register (BSR)
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Chapter 5
Programming the Peripherals
When peripherals are programmed in a given application, a number of possible modes and
options are available for use. Chapters 6 through 10 describe in detail the possible modes
and configurations for peripheral registers and ports. This chapter presents general
guidelines for initializing the peripherals. These guidelines include a description of how
the control registers are mapped in the DSP56311, data transfer methods that are available
when the various peripherals are used, and information on General-Purpose Input/Output
(GPIO) configuration.
5.1 Peripheral Initialization Steps
Each peripheral has its own initialization process. However, all four peripherals share
some common steps, which follow:
1. Determine the Register values to be programmed.
— Find the peripheral register descriptions in the manual.
— Choose the appropriate modes to configure for a given application.
— Determine the bit settings for programming those modes.
2. Make sure the peripheral is in individual reset state or disabled.
— Peripheral registers should not be modified while the peripheral is active.
3. Configure the registers by writing the predetermined values to them.
— Write the register values determined in step 1 into the appropriate register
locations.
4. Enable the peripheral.
— Once the peripheral is enabled, it operates according the programmed modes
determined in step 1.
For detailed initialization procedures unique to each peripheral, consult the initialization
section within each peripheral’s chapter.
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Mapping the Control Registers
5.2 Mapping the Control Registers
The I/O peripherals are controlled through registers mapped to the top 128 words of
X-data memory ($FFFF80 - $FFFFFF). Referred to as the internal I/O space, the control
registers are accessed by move (MOVE, MOVEP) instructions and bit-oriented
instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR,
JSET, JSCLR, and JSSET). The contents of the internal X I/O memory space are listed in
Appendix B, Programming Reference, Table B-2.
X-Data Memory
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$FFFFFF
Internal I/O
Peripherals Control Registers
Memory Space
$FFFF80
External
$FFF000
Internal
Reserved
$FF0000
External
$00C000
Internal
X-Data RAM
48K (default)
$000000
Figure 5-1. Memory Mapping of Peripherals Control Registers
5.3 Reading Status Registers
Each peripheral has a read-only status register that indicate the state of the peripheral at a
given time. The HI08, ESSI, and SCI have dedicated status registers. The triple timer has
status bits embedded within a control/status register. Changes in the status bits can
generate interrupt conditions. For example, the HI08 has a host status register with two
host flag bits that can be encoded by the host to generate an interrupt in the DSP.
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Data Transfer Methods
5.4 Data Transfer Methods
Peripheral I/O on the DSP56311 can be accomplished in three ways:
■
Polling
■
Interrupts
■
DMA
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5.4.1 Polling
Polling is the easiest method for data transfers. When polling is chosen, the DSP56311
core continuously checks a specified register flag waiting for an event to happen. One
example would be setting an overflow flag in one of the Timers. Once the event occurs,
the DSP56311 is free to continue with its next task. However, while it is waiting for the
event to occur, the DSP56311 core is not executing any other code. Polling is the easiest
transfer method since it does not require register initializations, but it is also the least
efficient use of the DSP core.
Each peripheral has its own set of flags which may be polled to determine when data is
ready to be transferred. For example, the ESSI control registers provide bits that tell the
core when data is ready to be transferred to or from the peripheral. The core polls these
bits to determine when to interact with the peripheral. Similar flags exist for each
peripheral.
Example 5-1 shows software polling programmed in an application using the HI08.
Example 5-1. Software Polling
jclr
move
#1,x:M_HSR,*
y:(TBUFF_PTR)+,x1
; loop if HSR[1]:HTDE=0
; move data to x1
In this example, the core waits until the Host Status Register’s (HSR) Host Transmit Data
Empty (HTDE) flag is set. When the flag is set, the core moves data from Y memory to
the X1 register.
5.4.2 Interrupts
Interrupts are more efficient than polling, but interrupts also require additional register
initializations. Polling requires the core to remain busy checking a flag in a specified
control register and therefore does not allow the core to execute other code at the same
time. For interrupts, you can initialize the interrupt so it is triggered off one of the same
flags that can also be polled. Then the core does not have to continuously check a flag.
Once the interrupt is initialized and the flag is set, the core is notified to execute a data
transfer. Until the flag is set, the core can remain busy executing other sections of code.
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Data Transfer Methods
When an interrupt occurs, the core execution flow jumps to the interrupt start address
defined in Table B-4 in Appendix B, Programming Reference. It executes code starting
at the interrupt address. If it is a short interrupt (i.e., the service routine is two opcodes
long), the code automatically returns to the original program flow after executing two
opcodes with no impact to the pipeline. Otherwise, if a longer service routine is required
the programmer can place a jump-to-subroutine (JSR) instruction at the interrupt service
address. In this case, the program executes that service routine and continues until a
return-from-interrupt (RTI) instruction executes. The execution flow then resumes from
the position the program counter was in before the interrupt was triggered.
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Configuring interrupts requires two steps:
1. Setting up the interrupt routine
— The interrupt handler is located at the interrupt starting address.
— The interrupt routines can be short (only two opcodes long) or long (more than
two opcodes and requiring a JSR instruction).
2. Enabling the interrupts
a. Set the corresponding bits in the applicable peripheral control register.
b. Enable peripheral interrupts in the Interrupt Priority Register (IPRP).
c. Enable global interrupts in the Mode Register (MR) portion of the Status Register
(SR).
Events that change bits in the peripheral control registers can then trigger the interrupt.
Depending on the peripheral, from two to six peripheral interrupt sources are available to
the programmer.
Example 5-2 shows a short interrupt programmed for the HI08. The main program
enables the Host Receive Interrupt in the Host Control Register (HCR). When the
interrupt is triggered during code execution, the core processing jumps to the Host
Receive Interrupt routine location at p:$60 and executes the code there. Since this is a
short interrupt, the core returns to normal code execution after executing the two move
instructions, and an RTI instruction is not necessary.
Example 5-2. Interrupts
bset
#M_HRIE,x:M_HCR; enable host receive interrupt
; Short Interrupt Routine
org
P:$60
movep x:M_HRX,x1
; HI08 Receive Data Full interrupt
move
x1,y:(r0)+
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Data Transfer Methods
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5.4.3 DMA
The Direct Memory Access (DMA) controller permits data transfers between
internal/external memory and/or internal/external I/O in any combination without the
intervention of the DSP56311 core. Dedicated DMA address and data buses and internal
memory partitioning ensure that a high level of isolation is achieved so the DMA
operation does not interfere with the core operation or slow it down. The DMA moves
data to/from the peripheral transmit/receive registers. The programmer may use the DMA
control registers to configure sources and destinations of data transfers. Depending on the
peripheral, you will find one to four peripheral request sources available. This is the most
efficient method of data transfer available. Core intervention is not required after the
DMA channel is initialized.
Table 5-1. DMA-Accessible Registers
DMA
Block
ESSI
SCI
EFCOP
HI08
Register
Read
Write
TX0
No
Yes
TX1
No
Yes
TX2
No
Yes
RX
Yes
No
SRX
Yes
No
STX
No
Yes
FDIR
No
Yes
FDOR
Yes
No
HTX
No
Yes
HRX
Yes
No
Timer
Example 5-3 shows a DMA configuration for transferring data to the Host Transmit
register of the HI08.
Example 5-3. DMA Transfers
bclr
bclr
movep
movep
movep
movep
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#M_D1L0,x:M_IPRC
#M_D1L1,x:M_IPRC
#TBUFF_START,x:M_DSR1
#M_HTX,x:M_DDR1
#TBUFF_SIZE-1,x:M_DCO1
#INIT_DCR1,x:M_DCR1
; disable DMA1 interrupts
;
;
;
;
DMA1 source is transmit buffer
DMA1 destination is HTX
DMA1 count is the full buffer
init. DMA1 control register
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General-Purpose Input/Output (GPIO)
DMA requires more initialization code and consideration of DMA modes. However, it is
the most efficient use of core resources. Once these registers are programmed, the user
must enable the DMA by triggering a DMA request off one of the peripheral control flags
or enabling it in normal program flow or an interrupt service routine.
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5.4.4 Advantages and Disadvantages
Polling is the easiest method to implement, but it requires a large amount of DSP56311
core processing power. The core cannot be involved in other processing activities while it
is polling receive and transmit ready bits. Interrupts require more code, but the core can
process other routines while waiting for data I/O. An interrupt is generated when data is
ready to be transferred to or from the peripheral device. DMA requires even less core
intervention, and the setup code is minimal, but the DMA channels must be available.
Note:
Do not interrupt requests and DMA requests simultaneously.
5.5 General-Purpose Input/Output (GPIO)
The DSP56311 provides 34 bidirectional signals that can be configured as GPIO signals or
as peripheral dedicated signals. No dedicated GPIO signals are provided. All of these
signals are GPIO by default after reset. The control register settings of the DSP56311
peripherals determine whether these signals function as GPIO or as peripheral dedicated
signals. This section tells how signals can be used as GPIO.
Chapter 2, Signals/Connections details the special uses of the 34 bidirectional signals.
These signals fall into five groups and are controlled separately or as a group:
■
Port B: 16 GPIO signals (shared with the HI08 signals)
■
Port C: six GPIO signals (shared with the ESSI0 signals)
■
Port D: six GPIO signals (shared with the ESSI1 signals)
■
Port E: three GPIO signals (shared with the SCI signals)
■
Timers: three GPIO signals (shared with the triple timer signals)
5.5.1 Port B Signals and Registers
Each of the 16 Port B signals not used as an HI08 signal can be configured as a GPIO
signal. Three registers control the GPIO functionality of Port B: host control register
(HCR), host port GPIO data register (HDR), and host port GPIO direction register
(HDDR). Chapter 6, Host Interface (HI08) discusses these registers.
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General-Purpose Input/Output (GPIO)
DSP56311
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Host Interface
(HI08) Port
Non-Multiplexed
Bus
Multiplexed
Bus
Port B GPIO
H0 - H7
HAD0 - HAD7
PB0 - PB7
HA0
HAS/HAS
PB8
HA1
HA8
PB9
HA2
HA9
PB10
HCS/HCS
HA10
PB13
Single DS
HRW
Double DS
HRD/HRD
PB11
HDS/HDS
HWR/HWR
PB12
Single HR
HREQ/HREQ
HACK/HACK
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
PB14
PB15
Figure 5-2. Port B Signals
5.5.2 Port C Signals and Registers
Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO
signal. Three registers control the GPIO functionality of Port C: Port C control register
(PCRC), Port C direction register (PRRC), and Port C data register (PDRC).
Chapter 7, Enhanced Synchronous Serial Interface (ESSI) discusses these registers.
Port C GPIO
DSP56311
SC00-SC02
Enhanced Synchronous
Serial Interface Port 1
(ESSI0)
SCK0
PC0 - PC2
PC3
SRD0
PC4
STD0
PC5
Figure 5-3. Port C Signals
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General-Purpose Input/Output (GPIO)
5.5.3 Port D Signals and Registers
Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPIO
signal. Three registers control the GPIO functionality of Port D: Port D control register
(PCRD), Port D direction register (PRRD), and Port D data register (PDRD).
Chapter 7, Enhanced Synchronous Serial Interface (ESSI) discusses these registers.
Port C GPIO
DSP56311
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SC10-SC02
Enhanced Synchronous
Serial Interface Port 1
(ESSI1)
SCK1
PD0 - PD2
PD3
SRD1
PD4
STD1
PD5
Figure 5-4. Port D Signals
5.5.4 Port E Signals and Registers
Each of the three Port E signals not used as an SCI signal can be configured as a GPIO
signal. Three registers control the GPIO functionality of Port E: Port E control register
(PCRE), Port E direction register (PRRE), and Port E data register (PDRE).
Chapter 8, Serial Communication Interface (SCI) discusses these registers.
DSP56311
Port E GPIO
RXD
Serial
Communications
Interface (SCI) Port
TXD
PE0
PE1
SCLK
PE2
Figure 5-5. Port E Signals
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General-Purpose Input/Output (GPIO)
5.5.5 Triple Timer Signals and Registers
Each of the three triple timer interface signals (TIO0–TIO2) not used as a timer signal can
be configured as a GPIO signal. Each signal is controlled by the appropriate timer control
status register (TCSR0–TCSR2). Chapter 9, Triple Timer Module discusses these
registers.
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Timer GPIO
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TIO0
TIMERS
TIO1
TIO0
TIO1
TIO2
TIO2
Figure 5-6. Triple Timer Signals
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General-Purpose Input/Output (GPIO)
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Chapter 6
Host Interface (HI08)
The host interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that
can connect directly to the data bus of a host processor. The HI08 supports a variety of
buses and provides glueless connection with a number of industry-standard
microcomputers, microprocessors, and DSPs. The HI08 signals not used to interface to the
host can be configured as GPIO signals, up to a total of 16.
6.1 Features
The HI08 host is a slave device that operates asynchronously to the DSP core and host
clocks. Thus, the HI08 peripheral has a host processor interface and a DSP core interface.
This section lists the features of the host processor and DSP core interfaces.
6.1.1 DSP Core Interface
■
Mapping:
— Registers are directly mapped into eight internal X data memory locations.
■
Data word:
— DSP56311 24-bit (native) data words are supported, as are 8-bit and 16-bit
words.
■
Handshaking protocols:
— Software polled
— Interrupt driven
— Core DMA accesses
■
Instructions:
— Memory-mapped registers allow the standard MOVE instruction to transfer
data between the DSP56311 and external hosts.
— A special MOVEP instruction for I/O service capability using fast interrupts.
— Bit addressing instructions (for example, BCHG, BCLR, BSET, BTST, JCLR,
JSCLR, JSET, JSSET) simplify I/O service routines.
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Features
6.1.2 Host Processor Interface
■
Sixteen signals support nonmultiplexed or multiplexed buses:
— H0–H7/HAD0–HAD7 host data bus (H0–H7) or host multiplexed address/data
bus (HAD0–HAD7)
— HAS/HA0 address strobe (HAS) or host address line (HA0)
— HA8/HA1 host address line (HA8) or host address line (HA1)
— HA9/HA2 host address line (HA9) or host address line (HA2)
— HRW/HRD read/write select (HRW) or read strobe (HRD)
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— HDS/HWR data strobe (HDS) or write strobe (HWR)
— HCS/HA10 host chip select (HCS) or host address line (HA10)
— HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ)
— HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ)
■
Mapping:
— HI08 registers are mapped into eight consecutive locations in the host’s external
bus address space.
— The HI08 acts as a memory or I/O-mapped peripheral for microprocessors,
microcontrollers, etc.
■
Transfer modes:
— Mixed 8-bit, 16-bit, and 24-bit data transfers
— DSP-to-host
— Host-to-DSP
— Host command
■
Handshaking protocols:
— Software polled
— Interrupt-driven (Interrupts are compatible with most processors, including the
MC68000, 8051, HC11, and Hitachi H8.)
■
Data word: 8 bits
■
Dedicated interrupts:
–
Separate request lines for each interrupt source
–
Special host commands force DSP core interrupts under host processor control. These
commands are useful for
— Real-time production diagnostics
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Host Port Signals
— Creation of a debugging window for program development
— Host control protocols
■
Interface capabilities:
— Glueless interface (no external logic required) to
— Motorola HC11
— Hitachi H8
— 8051 family
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— Thomson P6 family
— Minimal glue-logic (pull-ups, pull-downs) required to interface to
— ISA bus
— Motorola 68K family
— Intel X86 family
6.2 Host Port Signals
The host port signals are discussed in Chapter 2, Signals/Connections. Each host port
signal can be programmed as a host port signal or as a GPIO signal, PB0–PB15. See
Table 6-1 through Table 6-3.
Table 6-1. HI08 Signal Definitions for Operational Modes
HI08 Port Signal
Multiplexed Address/Data Bus
Mode
Nonmultiplexed Bus Mode
GPIO Mode
HAD0–HAD7
HAD0–HAD7
H0–H7
PB0–PB7
HAS/HA0
HAS/HAS
HA0
PB8
HA8/HA1
HA8
HA1
PB9
HA9/HA2
HA9
HA2
PB10
HCS/HA10
HA10
HCS/HCS
PB13
Table 6-2. HI08 Data Strobe Signals
HI08 Port
Signal
Single Strobe Bus
Dual Strobe Bus
GPIO Mode
HRW/HRD
HRW
HRD/HRD
PB11
HDS/HWR
HDS/HDS
HWR/HWR
PB12
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Overview
Table 6-3. HI08 Host Request Signals
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HI08 Port
Signal
Vector Required
No Vector Required
GPIO Mode
HREQ/
HTRQ
HREQ/HREQ
HTRQ/HTRQ
PB14
HACK/
HRRQ
HACK/HACK
HRRQ/HRRQ
PB15
The HI08 port can operate in multiplexed or non-multiplexed mode. In multiplexed mode
(HPCR[11]:HMUX=1), the lower eight address signals multiplex with the eight data lines.
In non-multiplexed mode (HPCR[11]:HMUX=0), the HI08 requires a chip select signal
and three address lines to select one of the eight registers accessible to the host. Eight lines
are used for data. The HI08 port can also be programmed to use a single or dual read/write
data strobe and single or double host request line.
Software and hardware resets clear all DSP-side control registers and configure the HI08
as GPIO with all 16 signals disconnected. To select GPIO functions, clear HPCR bits 6
through 1; to select other HI08 functions, set those same bits. If the HI08 is in GPIO mode,
the HDDR configures each corresponding signal in the HDR as an input signal if the
HDDR bit is cleared or as an output signal if the HDDR bit is set. For details, see Section
6.6.3, "Host Data Direction Register (HDDR)," on page 6-16 and Section 6.6.4, "Host
Data Register (HDR)," on page 6-16.
6.3 Overview
The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side
register bank is accessible only to the host, and the DSP-side register bank is accessible
only to the DSP core. For the host, the HI08 appears as eight byte-wide locations mapped
in its external address space. The DSP-side registers appear to the DSP core as six 24-bit
registers mapped into internal I/O X memory space and therefore accessible via standard
DSP56300 instructions and addressing modes. In GPIO mode, two additional registers
(HDDR and HDR) are related to the HI08 peripheral.
The separate receive and transmit data paths are double buffered for efficient, high speed
asynchronous transfers. The host-side transmit data path (host writes) is also the DSP-side
receive path; the host-side receive data path (host reads) is also the DSP-side transmit
path. The Receive (RXH:M:L) and Transmit Data Registers (TXH:M:L) use the same host
address. During host writes to these addresses, the data is transferred to the Transmit Data
Registers while reads are performed from the Receive Data Registers.
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Overview
DSP-Side Registers
Control Registers
Data Registers
HCR = Host Control Register
HSR = Host Status Register
HPCR = Host Port Control Register
HBAR = Host Base Address Register
HTX = Host Transmit Register
HRX = Host Receive Register
HDDR = Host Data Direction Register
HDR = Host Data Register
Core DMA Data Bus
DSP Peripheral Data Bus
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24
HCR
24
HSR
24
HDDR
24
HDR
24
24
HBAR
8
24
HPCR
24 24
HTX
Address
Comparator
24
DSP
Side
HRX
24
24
5
3
ISR
8
ICR
8
CVR
IVR
8
Latch
8
8
RXH RXM RXL
3
8
8
8
TXH TXM TXL
8
8
Host
Side
8
HOST Bus
Host-Side Registers
Control Registers
Data Registers
ISR = Interface Status Register
ICR = Interface Control Register
CVR = Command Vector Register
IVR = Interrupt Vector Register
RXH = Receive Register High
RXM = Receive Register Middle
RXL = Receive Register Low
TXH = Transmit Register High
TXM = Transmit Register Middle
TXL = Transmit Register Low
Figure 6-1. HI08 Block Diagram
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Operation
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6.4 Operation
The HI08 is a slave-only device, so the host is the master of all bus transfers. In
host-to-DSP transfers, the host writes data to the Transmit Byte Registers (TXH:M:L). In
DSP-to-host transfers the host reads data from the Receive Byte Registers (RXH:M:L).
The DSP side has access only to the Host Receive Data Register (HRX) and the Host
Transmit Data Register (HTX). Data automatically moves between the host-side data
registers and the DSP-side data registers when it is available. This double-buffered
mechanism allows for fast data transfers but creates a “pipeline” that can either stall
communication (if the pipeline is either full or empty) or cause erroneous data transfers
(new data to be overwritten or old data to be read twice). The HI08 port has several
handshaking mechanisms to counter these buffering effects.
Suppose the host is writing several pieces of data to the HI08 port. The host first uses one
of the handshaking protocols to determine whether any data previously written to the
Transmit Byte Registers (TXH:M:L) has successfully transferred to the DSP side. If the
host-side Transmit Byte Registers (TXH:M:L) are empty, the host writes the data to these
registers. The transfer to the DSP-side Host Receive Data Register (HRX) occurs only if
HRX is empty (that is, the DSP has read it). The DSP core then uses an appropriate
handshaking protocol to move data from the HRX to the receiving buffer or register.
Without handshaking, the host might overwrite data not transferred to the DSP side or the
DSP might receive stale data.
Similarly, when the host performs multiple reads from the HI08 port Receive Byte
Registers (RXH:M:L), the DSP side uses an appropriate handshaking protocol to
determine whether any data previously written to the Host Transmit Register (HTX) has
successfully transferred to the host-side registers. If HTX is empty, the DSP writes the
data to this register. Data transfers to the host-side Receive Byte Registers (RXH:M:L)
occur only if they are empty (that is, the host has read them). The host can then use any of
the available handshaking protocols to determine whether more data is ready to be read.
The DSP56311 HI08 port offers the following handshaking protocols for data transfers
with the host:
■
Software polling
■
Interrupts
■
Core DMA access
■
Host requests
The choice of which protocol to use is based on such system constraints as the amount of
data to be transferred, the timing requirements for the transfer, and the availability of such
resources as processing bandwidth and DMA channels. All of these constraints are
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Operation
discussed in the following sections. The transfers described here occur asynchronously
between the host and the DSP; each transferring data at its own pace. However, use of the
appropriate handshaking protocol allows data transfers to occur at optimum rates.
6.4.1 Software Polling
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Software polling is the simplest data transfer method to use, but it demands the greatest
amount of the core’s processing power. Status bits are provided for the host or the DSP
core to test and determine if the data registers are empty or full. However, the DSP core
cannot be involved in other processing activities while it is polling these status bits.
On the DSP side, for transfers from the DSP to the host (host reads), the DSP core must
determine the state of Host Transmit Data register (HTX). In transfers from the host to the
DSP (host writes), the DSP side should determine the state of the Host Receive Data
Register (HRX). Thus, two bits are provided to the core for polling:
■
the Host Transmit Data Empty bit in the Host Status register (HSR[1]:HTDE)
■
the Host Receive Data Full bit in the Host Status register (HSR[0]:HRDF)
A similar mechanism is available on the host-side to determine the state of the Transmit
Registers (TXH:TXM:TXL) and Receive Registers (RXH:RHM:RHL). Two bits are
provided to the host for polling:
■
the Transmit Data Empty bit in the Interface Status Register (ISR[1]:TXDE)
■
the Receive Data Full bit in the Interface Status Register (ISR[0]:RXDF)
The HI08 also offers four general-purpose flags for communication between the host and
the DSP. The DSP-side uses the HSR Host Flag bits (HCR[4 – 3]=HF3:HF2) to pass
application-specific information to the host. The status of HF3:HF2 is reflected in the
host-side ISR Host Flag bits (ISR[4 – 3]=HF3:HF2). Similarly, the host side can use the
ICR Host Flag bits (ICR[4 – 3]=HF1:HF0) to pass application-specific information to the
DSP. The status of HF1:HF0 is reflected in the DSP-side HSR Host Flag bits
(HSR[4 – 3]=HF1:HF0).
6.4.2 Core Interrupts and Host Commands
The HI08 can request interrupt service from the DSP56311 core. The DSP56311 core
interrupts are internal and do not require the use of an external interrupt signal. When the
appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host
interface sets the appropriate bit in the HSR, generating an interrupt request to the
DSP56311 interrupt controller (see Figure 6-2). The DSP56311 acknowledges interrupts
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by jumping to the appropriate interrupt service routine. The following DSP core interrupts
are possible from the HI08 peripheral:
■
Host command
■
Transmit data register empty
■
Receive data register full
These interrupts are maskable via the Host Receive Interrupt Enable bit (HCR[0]=HRIE),
the Host Transmit Interrupt Enable bit (HCR[1]=HTIE), and the Host Command Interrupt
Enable bit (HCR[2]=HCIE), respectively. Receive Data Full and Transmit Data Empty
interrupts move data to/from the HTX and HRX data registers. The DSP interrupt service
routine must read or write the appropriate HI08 data register (HRX or HTX) to clear the
interrupt condition.
Enable
15
X:HCR
HF3
HF2
0
HCIE HTIE HRIE HCR
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
15
X:HSR
0
HF1
HF0
HCP HTDE HRDF HSR
Status
Figure 6-2. HI08 Core Interrupt Operation
Host commands allow the host to issue command requests to the DSP by selecting any of
128 DSP interrupt routines for execution. For example, the host may issue a command via
the HI08 that sets up and enables a DMA transfer. The DSP56311 processor has reserved
interrupt vector addresses for application-specific service routines. However, this
flexibility is independent of the data transfer mechanisms in the HI08 and allows the host
to force execution of any interrupt handler (for example, SSI, SCI, IRQx, and so on).
To enable Host Command interrupts, the HCR[2]=HCIE bit is set on the DSP side. The
host then uses the Command Vector Register (CVR) to start an interrupt routine. The host
sets the Host Command bit (CVR[7]=HC) to request the command interrupt and the seven
Host Vector bits CVR[6 – 0]=HV6:HV0 to select the interrupt address to be used. When
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Operation
the DSP core recognizes the host command interrupt, the address of the interrupt taken is
2xHV. For host command interrupts, the interrupt acknowledge from the DSP56311
program controller clears the pending interrupt condition.
Note:
When the DSP enters Stop mode, the HI08 pins are electrically disconnected
internally, thus disabling the HI08 until the core leaves Stop mode. Do not issue
a STOP command via the HI08 unless some other mechanism for exiting this
mode is provided.
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6.4.3 Core DMA Access
The DSP56300 family Direct Memory Access (DMA) controller permits transfers
between internal or external memory and I/O without any core intervention. A DMA
channel can be set up to transfer data to/from the HTX and HRX data registers, freeing the
core to use its processing power on functions other than polling or interrupt routines for
the HI08. DMA may well be the best method to use for data transfers, but it requires that
one of the six DMA channels be available for use. Two HI08 DMA sources are possible,
as Table 6-4 shows. Refer to the DSP56300 Family Manual to learn about DMA accesses.
Table 6-4. DMA Request Sources
Requesting Device
DCRx[15 – 11]=DRS4 – DRS0
Host Receive Data Full (HRDF=1)
10011
Host Transmit Data Empty (HTDE=1)
10100
Note that DMA transfers do not access the host bus. The host must determine when data is
available in the host-side data registers using an appropriate polling mechanism.
6.4.4 Host Requests
A set of signal lines allow the HI08 to request service from the host. The request signal
lines normally connect to the host interrupt request pins (IRQx) and indicate to the host
when the DSP HI08 port requires service. The HI08 can be configured to use either a
single Host Request (HREQ) line for both receive and transmit requests or two signal
lines, a Host Transmit Request (HTRQ) and a Host Receive Request (HRRQ), for each
type of transfer.
Host requests are enabled on both the DSP-side and host-side. On the DSP side, the HPCR
Host Request Enable bit (HPCR[4]=HREN) is set to enable host requests. On the host
side, clearing the ICR Double Host Request bit (ICR[2]=HDRQ) configures the HI08 to
use a single request line (HREQ). Setting the ICR[2]=HDRQ bit enables both transmit and
request lines to be used. Further, the host uses the ICR Receive Request Enable bit
(ICR[0]=RREQ) and the ICR Transmit Request Enable bit (ICR[1]=TREQ) to enable
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Operation
receive and transmit requests, respectively.When host requests are enabled, the host
request pins operate as shown in Figure 6-3.
Status
7
$2 HREQ
0
0
HF3
HF2
TRDY
0
TXDE RXDF ISR
Host Request
Signals
Host Request
Asserted
HRRQ
HREQ
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HTRQ
7
$0
0
INIT
0
0
HF1
HF0 HLEND TREQ RREQ ICR
Enable
Figure 6-3. HI08 Host Request Structure
Table 6-5 shows the operation of the HREQ pin when a single request line is used. The
host can test these ICR bits to determine the interrupt source.
Table 6-5. HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0)
ICR[1]=TREQ
ICR[0]=RREQ
HREQ Pin
0
0
No interrupts
0
1
RXDF request enabled
1
0
TXDE Request enabled
1
1
RXDF and TXDE request enabled
Table 6-6 shows the operation of the transmit request (HTRQ) and receive request
(HRRQ) lines with dual host requests enabled.
Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode
(ICR[2]=HDRQ=1)
6-10
ICR[1]=TREQ
ICR[0]=RREQ
HTRQ Pin
HRRQ Pin
0
0
No interrupts
No interrupts
0
1
No interrupts
RXDF request enabled
1
0
TXDE Request enabled
No interrupts
1
1
TXDE Request enabled
RXDF request enabled
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Operation
6.4.5 Endian Modes
The Host Little Endian bit in the host-side Interface Control Register (ICR[5]=HLEND)
allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In
Little Endian mode (HLEND=1), a host transfer occurs as shown in the Figure 6-4.
HTX/HRX Bit Number: 23
0
aa
bb
cc
DSP side
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Host side
Host 32-bit
internal register
Low Byte
cc
bb
aa
Host bus address:
$5
$6
$7
cc
bb
aa
xx
High Byte
(read/write last!)
Figure 6-4. HI08 Read and Write Operations in Little Endian Mode
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three
store (or load) byte operations, ensuring that the data byte at host bus address $7 is written
last since this causes the transfer of the data to the DSP-side HRX. However, the host bus
controller may be sophisticated enough that the host can transfer all bytes in a single
operation (instruction). For example, in the Power PC MPC860 processor, the GeneralPurpose Controller Module (GPCM) in the memory controller can be programmed so that
the host can execute a single read (load word, LDW) or write (store word, STW)
instruction to the HI08 port and cause four byte transfers to occur on the host bus. The
32-bit datum transfer shown in Figure 6-4 has byte data xx written to HI08 address $4,
byte aa to address $5, byte bb to address $6 and byte cc to address $7 (this assumes the
24-bit datum is contained in the lower 24 bits of the host’s 32-bit data register as shown).
A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing
the Host Little Endian bit (ICR[5]=HLEND). Big Endian mode is depicted in Figure 6-5.
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Boot-up Using the HI08 Host Port
HTX/HRX Register: 23
0
aa
bb
cc
DSP side
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Host side
High Byte
aa
bb
cc
Host bus address:
$5
$6
$7
aa
bb
cc
Host 32-bit
internal register
xx
Low Byte
(read/write last!)
Figure 6-5. HI08 Read and Write Operations in Big Endian Mode
6.5 Boot-up Using the HI08 Host Port
The DSP56300 core has eight bootstrap operating modes to start up after reset. As the
processor exits the Reset state the value at the external mode pins MODA/IRQA,
MODB/IRQB, MODC/IRQC and MODD/IRQD are loaded into the Chip Operating Mode
bits (MA, MB, MC and MD) of the Operating Mode Register (OMR). These bits
determine the bootstrap operating mode. Modes C, D, E and F use the HI08 host port to
bootstrap the application code to the DSP. The following table describes these modes.
Mode
MODD
MODC
MODB
MODA
HI08 Bootstrap Description
C
1
1
0
0
ISA/DSP5630x mode
D
1
1
0
1
HC11 non-multiplexed bus mode
E
1
1
1
0
8051 multiplexed bus mode
F
1
1
1
1
MC68302 bus mode
The bootstrap program is factory-programmed into an internal 192-word by 24-bit
bootstrap ROM at locations $FF0000 to $FF00BF of P memory. This program can load
program RAM segment from the HI08 host port. When any of the modes in the preceding
table are used, the core begins executing the bootstrap program and configures the HI08
based on the OMR mode bits. The bootstrap program then expects the following data
sequence when the user program is downloaded from the HI08:
1. Three bytes (least significant byte first) indicating the number of 24-bit program
words to be loaded.
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2. Three bytes (least significant byte first) indicating the 24-bit starting address in
P-memory to load the user’s program.
3. The user’s program (three bytes, least significant byte first, for each program word).
Once the bootstrap program finishes loading the specified number of words, it jumps to
the specified starting address and executes the loaded program.
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6.6 DSP Core Programming Model
The DSP56300 core treats the HI08 as a memory-mapped peripheral occupying eight
24-bit words in X data memory space. The DSP can use the HI08 as a normal
memory-mapped peripheral, employing either standard polled or interrupt-driven
programming techniques. Separate transmit and receive data registers are double-buffered
to allow the DSP and host processor to transfer data efficiently at high speed. Direct
memory mapping allows the DSP56311 core to communicate with the HI08 registers
using standard instructions and addressing modes. In addition, the MOVEP instruction
allows direct data transfers between DSP56311 internal memory and the HI08 registers or
vice versa.
There are two types of host processor registers, data and control, with eight registers in all.
The DSP core can access all eight registers, but the external host cannot.The following
data registers are 24-bit registers used for high-speed data transfer to and from the DSP.
■
Host data receive register (HRX), on page 6-22
■
Host data transmit register (HTX), on page 6-21
The DSP-side control registers are 16-bit registers that control HI08 functionality:
■
Host control register (HCR), on page 6-14
■
Host status register (HSR), on page 6-15
■
Host GPIO data direction register (HDDR), on page 6-16
■
Host GPIO data register (HDR), on page 6-16
■
Host base address register (HBAR), on page 6-17
■
Host port control register (HPCR), on page 6-17
Both hardware and software resets disable the HI08. After a reset, the HI08 signals are
configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left
floating).
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6.6.1 Host Control Register (HCR)
This read/write register controls the HI08 interrupt operation. Initialization values for
HCR bits are presented in Section 6.6.9, "DSP-Side Registers After Reset," on page 6-22.
15
14
13
12
11
10
9
8
7
6
5
4
3
HF3
HF2
2
1
0
HCIE HTIE HRIE
—Reserved bit; read as 0; should be written with 0 for future compatibility.
Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)
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Table 6-7. Host Control Register (HCR) Bit Definitions
Bit Number
Bit Name
15 – 5
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
4–3
HF[3 –2]
0
Host Flags 2, 3
General-purpose flags for DSP-to-host communication. The DSP core
can set or clear HF[3 – 2]. The values of HF[3 – 2] are reflected in the
interface status register (ISR); that is, if they are modified by the DSP
software, the host processor can read the modified values by reading
the ISR. These two general-purpose flags can be used individually or as
encoded pairs in a simple DSP-to-host communication protocol,
implemented in both the DSP and the host processor software. The bit
value is indeterminate after an individual reset.
2
HCIE
0
Host Command Interrupt Enable
Generates a host command interrupt request if the host command
pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP
interrupts are disabled. The interrupt address is determined by the host
command vector register (CVR).
NOTE: If more than one interrupt request source is asserted and
enabled (for example, HRDF is set, HCP is set, HRIE is set, and HCIE is
set), the HI08 generates interrupt requests according to priorities shown
here. The bit value is indeterminate after an individual reset.
Priority
Interrupt Source
Highest
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Lowest
1
6-14
HTIE
0
Receive Data (HRDF = 1)
Host Transmit Interrupt Enable
Generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is
transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is
cleared, HTDE interrupts are disabled. The bit value is indeterminate
after an individual reset.
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Table 6-7. Host Control Register (HCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
0
HRIE
0
Host Receive Interrupt Enable
Generates a host receive data interrupt request if the host receive data
full (HRDF) bit in the host status register (HSR, Bit 0) is set. The HRDF
bit is set when data is transferred to the HRX from the TXH, TXM, or
TXL registers. If HRIE is cleared, HRDF interrupts are disabled. The bit
value is indeterminate after an individual reset.
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6.6.2 Host Status Register (HSR)
The HSR is a 16-bit read-only status register by which the reads the HIO8 status and flags.
The host processor cannot access it directly. The initialization values for the HSR bits are
discussed in Section 6.6.9, "DSP-Side Registers After Reset," on page 6-22.
15
14
13
12
11
10
9
8
7
6
5
4
3
HF1
HF0
2
1
0
HCP HTDE HRDF
—Reserved bit; read as 0; should be written with 0 for future compatibility.
Figure 6-7. Host Status Register (HSR) (X:$FFFFC3)
Table 6-8. Host Status Register (HSR) Bit Definitions
Bit Number
Bit Name
15 – 5
4–3
HF[1 – 0]
2
1
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HTDE
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
0
Host Flags 0, 1
General-purpose flags for host-to-DSP communication. These bits
reflect the status of host flags HF[1 – 0] in the ICR on the host side.
These two general-purpose flags can be used individually or as
encoded pairs in a simple host-to-DSP communication protocol,
implemented in both the DSP and the host processor software.
0
Host Command Pending
Reflects the status of the CVR[HC] bit. When set, it indicates that a host
command interrupt is pending. HI08 hardware clears HC and HCP when
the DSP core services the interrupt request. If the host clears HC, HCP
is also cleared.
0
Host Transmit Data Empty
Indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is
transferred to the RXH:RXM:RXL registers. The host processor can also
set HTDE using the initialize function. HTDE is cleared when the DSP
core writes to HTX.
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Table 6-8. Host Status Register (HSR) Bit Definitions
Bit Number
Bit Name
Reset Value
0
HRDF
0
Description
Host Receive Data Full
Indicates that the host receive data register (HRX) contains data from
the host processor. HRDF is set when data is transferred from the
TXH:TXM:TXL registers to the HRX register. The host processor can
also clear HRDF using the initialize function.
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6.6.3 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured
as GPIO. Even when the HI08 functions as the host interface, its unused signals can be
configured as GPIO signals. For information on the HI08 GPIO configuration options, see
Section 6.2, "Host Port Signals," on page 6-3. If Bit DRxx is set, the corresponding HI08
signal is configured as an output signal. If Bit DRxx is cleared, the corresponding HI08
signal is configured as an input signal. Hardware and software reset clear the HDDR bits.
15
14
13
12
11
10
DR15 DR14 DR13 DR12 DR11 DR10
9
8
7
6
5
4
3
2
1
0
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
6.6.4 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals
configured as GPIO signals. The functionality of Dxx depends on the corresponding
HDDR bit (that is, DRxx).
Table 6-9. HDR and HDDR Functionality
HDDR
HDR
Dxx
DRxx
GPIO Signal1
Non-GPIO Signala
0
Read-only bit—The value read is the binary value
of the signal. The corresponding signal is
configured as an input.
Read-only bit—Does not contain significant data.
1
Read/write bit— The value written is the value
read. The corresponding signal is configured as an
output and is driven with the data written to Dxx.
Read/write bit— The value written is the value
read.
1. Defined by the selected configuration.
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6.6.5 Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers
are mapped into the host bus address space. The address from the host bus is compared
with the base address as programmed in the Base Address Register. An internal chip select
is generated if a match is found. Figure 6-10 shows how the chip-select logic uses HBAR.
15
14
13
12
11
10
9
8
7
6
BA10 BA9
5
4
3
2
1
0
BA8
BA7
BA6
BA5
BA4
BA3
Figure 6-9. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-10. Host Base Address Register (HBAR) Bit Definitions
Bit Number
Bit Name
Reset Value
0
15 – 8
7–0
BA[10 – 3]
$80
Description
Reserved. Set to 0 for future compatibility.
Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
HAD[0–7]
Latch
HAS
A[3:7]
HA[8:10]
DSP Peripheral
Data Bus
Base
Address
Register
8 bits
Comparator
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—Reserved bit, read as 0, should be written with 0 for future compatibility.
Chip select
Figure 6-10. Self Chip-Select Logic
6.6.6 Host Port Control Register (HPCR)
The HPCR is a read/write control register that controls the HI08 operating mode. HPCR
bit initialization values s are discussed in Section 6.6.9, "DSP-Side Registers After Reset,"
on page 6-22. Hardware and software reset clear the HPCR bits.
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15
14
HAP
13
12
11
10
9
8
HRP HCSP HDDS HMUX HASP HDSP HROD
7
6
5
4
3
2
1
0
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
—Reserved bit, read as 0, should be written with 0 for future compatibility.
Figure 6-11. Host Port Control Register (HPCR) (X:$FFFFC4)
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Note:
To assure proper operation of the DSP56311, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed
only if HEN is cleared. Similarly, the HPCR bits HAP, HRP, HCSP, HDDS,
HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN
should not be set when HEN is set nor at the time HEN is set.
Table 6-11. Host Port Control Register (HPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
15
HAP
0
Host Acknowledge Polarity
If HAP is cleared, the host acknowledge (HACK) signal is configured as
an active low input. The HI08 drives the contents of the IVR onto the
host bus when the HACK signal is low. If the HAP bit is set, the HACK
signal is configured as an active high input. The HI08 outputs the
contents of the IVR when the HACK signal is high.
14
HRP
0
Host Request Polarity
Controls the polarity of the host request signals. In single host request
mode (that is, when HDRQ is cleared in the ICR), if HRP is cleared and
host requests are enabled (that is, if HREN is set and HEN is set), then
the HREQ signal is an active low output. If HRP is set and host requests
are enabled, the HREQ signal is an active high output. In the double
host request mode (that is, when HDRQ is set in the ICR), if HRP is
cleared and host requests are enabled (that is, if HREN is set and HEN
is set), then the HTRQ and HRRQ signals are active low outputs. If HRP
is set and host requests are enabled, the HTRQ and HRRQ signals are
active high outputs.
13
HCSP
0
Host Chip Select Polarity
If the HCSP bit is cleared, the host chip select (HCS) signal is
configured as an active low input and the HI08 is selected when the
HCS signal is low. If the HCSP signal is set, HCS is configured as an
active high input and the HI08 is selected when the HCS signal is high.
12
HDDS
0
Host Dual Data Strobe
If the HDDS bit is cleared, the HI08 operates in single strobe bus mode.
In this mode, the bus has a single data strobe signal for both reads and
writes. If the HDDS bit is set, the HI08 operates in dual strobe bus
mode. In this mode, the bus has two separate data strobes: one for data
reads, the other for data writes. See Figure 6-12 on page 6-21 and
Figure 6-13 on page 6-21 for more information on dual and single
strobe modes.
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Table 6-11. Host Port Control Register (HPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
11
HMUX
0
Host Multiplexed Bus
If HMUX is set, the HI08 operates in multiplex mode, latching the lower
portion of a multiplexed address/data bus. In this mode the internal
address line values of the host registers are taken from the internal
latch. If HMUX is cleared, it indicates that the HI08 is connected to a
nonmultiplexed type of bus. The values of the address lines are then
taken from the HI08-dedicated address signals.
10
HASP
0
Host Address Strobe Polarity
If HASP is cleared, the host address strobe (HAS) signal is an active low
input, and the address on the host address/data bus is sampled when
the HAS signal is low. If HASP is set, HAS is an active-high address
strobe input, and the address on the host address or data bus is
sampled when the HAS signal is high.
9
HDSP
0
Host Data Strobe Polarity
If HDSP is cleared, the data strobe signals are configured as active low
inputs, and data is transferred when the data strobe is low. If HDSP is
set, the data strobe signals are configured as active high inputs, and
data is transferred when the data strobe is high. The data strobe signals
are either HDS by itself or both HRD and HWR together.
8
HROD
0
Host Request Open Drain
Controls the output drive of the host request signals. In the single host
request mode (that is, when HDRQ is cleared in ICR), if HROD is
cleared and host requests are enabled (that is, if HREN is set and HEN
is set in the host port control register (HPCR)), then the HREQ signal is
always driven by the HI08. If HROD is set and host requests are
enabled, the HREQ signal is an open drain output. In the double host
request mode (that is, when HDRQ is set in the ICR), if HROD is cleared
and host requests are enabled (that is, if HREN is set and HEN is set in
the HPCR), then the HTRQ and HRRQ signals are always driven. If
HROD is set and host requests are enabled, the HTRQ and HRRQ
signals are open drain outputs.
0
Reserved. Set to 0 for future compatibility.
7
6
HEN
0
Host Enable
If HEN is set, the HI08 operates as the host interface. If HEN is cleared,
the HI08 is not active, and all the HI08 signals are configured as GPIO
signals according to the value of the HDDR and HDR.
5
HAEN
0
Host Acknowledge Enable
Controls the HACK signal. In the single host request mode (HDRQ is
cleared in the ICR), if HAEN and HREN are both set, HACK/HRRQ is
configured as the host acknowledge (HACK) input. If HAEN or HREN is
cleared, HACK/HRRQ is configured as a GPIO signal according to the
value of the HDDR and HDR. In the double host request mode (HDRQ
is set in the ICR), HAEN is ignored.
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Table 6-11. Host Port Control Register (HPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
4
HREN
0
Host Request Enable
Controls the host request signals. If HREN is set and the HI08 is in the
single host request mode (that is, if HDRQ is cleared in the host
interface control register (ICR)), then HREQ/HTRQ is configured as the
host request (HREQ) output. If HREN is cleared, HREQ/HTRQ and
HACK/HRRQ are configured as GPIO signals according to the value of
the HDDR and HDR.
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If HREN is set in the double host request mode (that is, if HDRQ is set in
the ICR), HREQ/HTRQ is configured as the host transmit request
(HTRQ) output and HACK/HRRQ as the host receive request (HRRQ)
output. If HREN is cleared, HREQ/HTRQ and HACK/HRRQ are
configured as GPIO signals according to the value of the HDDR and
HDR.
3
HCSEN
0
Host Chip Select Enable
If the HCSEN bit is set, HCS/HA10 is a host chip select (HCS) in the
non-multiplexed bus mode (that is, when HMUX is cleared) and host
address line 10 (HA10) in the multiplexed bus mode (that is, when
HMUX is set). If this bit is cleared, HCS/HA10 is configured as a GPIO
signal according to the value of the HDDR and HDR.
2
HA9EN
0
Host Address Line 9 Enable
If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2
is host address line 9 (HA9). If this bit is cleared and the HI08 is in
multiplexed bus mode, then HA9/HA2 is configured as a GPIO signal
according to the value of the HDDR and HDR.
NOTE: HA9EN is ignored when the HI08 is not in the multiplexed bus
mode (that is, when HMUX is cleared).
1
HA8EN
0
Host Address Line 8 Enable
If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 is
host address line 8 (HA8). If this bit is cleared and the HI08 is in
multiplexed bus mode, then HA8/HA1 is a GPIO signal according to the
value of the HDDR and HDR.
NOTE: HA8EN is ignored when the HI08 is not in the multiplexed bus
mode (that is, when HMUX is cleared).
0
6-20
HGEN
0
Host GPIO Port Enable
Enables/disables signals configured as GPIO. If this bit is cleared,
signals configured as GPIO are disconnected: outputs are high
impedance, inputs are electrically disconnected. Signals configured as
HI08 are not affected by the value of HGEN.
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HRW
HDS
In a single-strobe bus, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write)
signal specifies the direction of the access.
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Figure 6-12. Single-Strobe Bus
Data
Write Data In
HWR
Write Cycle
Data
Read Data Out
HRD
Read Cycle
In dual-strobe bus, separate HRD and HWR signals specify the access as a read or write
access, respectively.
Figure 6-13. Dual-Strobe Bus
6.6.7 Host Transmit Data Register (HTX)
The HTX register performs DSP-to-host data transfers. The DSP56311 views it as a 24-bit
write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host
transfer data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register
are transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both
HSR[HTDE] and receive data full (ISR[RXDF]) on the host-side bits are cleared. This
transfer operation sets the ISR[RXDF] and HSR[HTDE] bits. The DSP56311 can set the
HCR[HTIE] bit to cause a host transmit data interrupt when HSR[HTDE] is set. To
prevent the previous data from being overwritten, data should not be written to the HTX
until HSR[HTDE] is set.
Note:
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When data is written to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of the
status bits within the next two cycles, the bit does not reflect its current status.
For details, see the DSP56300 Family Manual, “Appendix B, Polling a
Peripheral Device for Write.”
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6.6.8 Host Receive Data Register (HRX)
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The HRX register performs host-to-DSP data transfers.The DSP56311 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the
transmit data registers (TXH:TXM:TXL on the host side) when both the transmit data
register empty (ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on
the DSP side are cleared. The transfer operation sets both ISR[TXDE] and HSR[HRDF].
When the HSR[HRDF] is set, the HRX register contains valid data. The DSP56311 can set
the HCR[HRIE] to cause a host receive data interrupt when HSR[HRDF] is set. When the
DSP56311 reads the HRX register, the HSR[HRDF] bit is cleared.
6.6.9 DSP-Side Registers After Reset
Table 6-12 shows the results of the four reset types on the bits in each of the HI08
registers accessible to the DSP56311. The hardware reset (HW) is caused by the RESET
signal. The software reset (SW) is caused by execution of the RESET instruction. The
individual reset (IR) occurs when HPCR[HEN] is cleared. The stop reset (ST) occurs
when the STOP instruction executes.
Table 6-12. DSP-Side Registers After Reset
Reset Type
Register
Name
Register
Data
HCR
HW
Reset
SW
Reset
IR
Reset
ST
Reset
All bits
0
0
—1
—
HPCR
All bits
0
0
—
—
HSR
HF[1 – 0]
0
0
—
—
HCP
0
0
0
0
HTDE
1
1
1
1
HRDF
0
0
0
0
HBAR
BA[10 – 3]
$80
$80
—
—
HDDR
DR[15 – 0]
0
0
—
—
HDR
D[15 – 0]
—
—
—
—
HRX
HRX [23 – 0]
empty
empty
empty
empty
HTX
HTX [23 – 0]
empty
empty
empty
empty
1. The bit value is indeterminate after reset
6-22
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Host Programmer’s Model
6.7 Host Programmer’s Model
The HI08 provides a simple, high-speed interface to a host processor. To the host bus, the
HI08 appears to be eight byte-wide registers. Separate transmit and receive data paths are
double-buffered to allow the DSP core and host processor to transfer data efficiently at
high speed. The host can access the HI08 asynchronously using polling techniques or
interrupt-based techniques. The HI08 appears to the host processor as a memory-mapped
peripheral occupying eight bytes in the host processor address space. (See Table 6-13.)
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The eight HI08 registers include the following:
■
A control register (ICR), on page 6-24
■
A status register (ISR), on page 6-28
■
Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), on page 6-30
■
Two vector registers (CVR and IVR), on page 6-27 and page 6-30
To transfer data between itself and the HI08, the host processor bus performs the
following steps:
1. Asserts the HI08 address and strobes to select the register to be read or written.
(Chip select in non-multiplexed mode, the address strobe in multiplexed mode.)
2. Selects the direction of the data transfer. If it is writing, the host processor sources
the data on the bus. Otherwise, the HI08 places the data on the bus.
3. Strobes the data transfer.
Host processors can use standard host processor instructions (for example, byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are aligned
so that 8-bit host processors can use 8-, 16-, or 24-bit load and store instructions for data
transfers. The HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled
or interrupt-driven data transfers with the host processor. Because of the speed of the
DSP56311 interrupt response, most host microprocessors can load or store data at their
maximum programmed I/O instruction rate without testing the handshake flags for each
transfer. If full handshake is not needed, the host processor can treat the DSP56311 as a
fast device, and data can be transferred between the host processor and the DSP56311 at
the fastest data rate of the host processor.
One of the most innovative features of the host interface is the host command feature.
With this feature, the host processor can issue vectored interrupt requests to the
DSP56311. The host can select any of 128 DSP interrupt routines for execution by writing
a vector address register in the HI08. This flexibility allows the host processor to execute
up to 128 pre-programmed functions inside the DSP56311. For example, the DSP56311
host interrupts allow the host processor to read or write DSP registers (X, Y, or program
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memory locations), force interrupt handlers (for example, SSI, SCI, IRQA, IRQB interrupt
routines), and perform control or debugging operations.
Note:
When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the
HI08 configuration remains unchanged in Stop mode, the core cannot be
restarted via the HI08 interface. Do not issue a STOP command to the DSP via
the HI08 unless you provide some other mechanism to exit stop mode.
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Table 6-13. Host-Side Register Map
Host
Address
Big Endian
HLEND = 0
Little Endian
HLEND = 1
0
ICR
ICR
Interface Control
1
CVR
CVR
Command Vector
2
ISR
ISR
Interface Status
3
IVR
IVR
Interrupt Vector
4
00000000
00000000
Unused
5
RXH/TXH
RXL/TXL
6
RXM/TXM
RXM/TXM
7
RXL/TXL
RXH/TXH
Receive/Transmit
Bytes
6.7.1 Interface Control Register (ICR)
The ICR is an 8-bit read/write control register by which the host processor controls the
HI08 interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write
register, which allows the use of bit manipulation instructions on control register bits.
Hardware and software reset clear the ICR bits.
7
INIT
6
5
4
3
HLEND
HF1
HF0
2
1
0
HDRQ TREQ RREQ
—Reserved bit; read as 0; should be written with 0 for future compatibility.
Figure 6-14. Interface Control Register (ICR)
6-24
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Table 6-14. Interface Control Register (ICR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
7
INIT
0
Initialize
The host processor uses the INIT bit to force initialization of the HI08
hardware. During initialization, the HI08 transmit and receive control bits
are configured. Whether it is necessary to use the INIT bit to initialize
the HI08 hardware depends on the software design of the interface.
The type of initialization when the INIT bit is set depends on the state of
TREQ and RREQ in the HI08. The INIT command, which is local to the
HI08, configures the HI08 into the desired data transfer mode. When the
host sets the INIT bit, the HI08 hardware executes the INIT command.
The interface hardware clears the INIT bit after the command executes.
6
TREQ
PREQ
After INIT
Execution
Transfer Direction
Initialized
0
0
INIT = 0
None
0
1
INIT = 0;
RXDF = 0;
HTDE = 1
DSP to host
1
0
INIT = 0;
TXDE = 1;
HRDF = 0
Host to DSP
1
1
INIT = 0;
RXDF = 0;
HTDE = 1;
TXDE = 1;
HRDF = 0
Host to/from DSP
0
Reserved. Write to 0 for future compatibility.
5
HLEND
0
Host Little Endian
If the HLEND bit is cleared, the host can access the HI08 in Big-Endian
byte order. If set, the host can access the HI08 in Little-Endian byte
order. If the HLEND bit is cleared the RXH/TXH register is located at
address $5, the RXM/TXM register at $6, and the RXL/TXL register at
$7. If the HLEND bit is set, the RXH/TXH register is located at address
$7, the RXM/TXM register at $6, and the RXL/TXL register at $5.
4
HF1
0
Host Flag 1
A general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF1, and the DSP56311cannot change it.
HF1 is reflected in the HSR on the DSP side of the HI08.
3
HF0
0
Host Flag 0
A general-purpose flag for host-to-DSP communication. The host
processor can set or clear, and the DSP56311 cannot change it. HF0 is
reflected in the HSR on the DSP side of the HI08.
2
HDRQ
0
Double Host Request
If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as
HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is
configured as HTRQ, and HACK/HRRQ is configured as HRRQ.
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Table 6-14. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
1
TREQ
0
Description
Transmit Request Enable
Enables host requests via the host request (HREQ or HTRQ) signal
when the transmit data register empty (TXDE) status bit in the ISR is
set. If TREQ is cleared, TXDE interrupts are disabled. If TREQ and
TXDE are set, the host request signal is asserted.
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TREQ and RREQ modes (HDRQ = 0)
TREQ
RREQ
HREQ Signal
0
0
No interrupts (polling)
0
1
RXDF request (interrupt)
1
0
TXDE request (interrupt)
1
1
RXDF and TXDE request (interrupts)
TREQ and RREQ modes (HDRQ = 1)
0
6-26
RREQ
0
TREQ
RREQ
HTRQ Signal
HRRQ Signal
0
0
No interrupts
(polling)
No interrupts (polling)
0
1
No interrupts
(polling)
RXDF request
(interrupt)
1
0
TXDE request
(interrupt)
No interrupts (polling)
1
1
TXDE request
(interrupt)
RXDF request
(interrupt)
Receive Request Enable
Controls the HREQ signal for host receive data transfers. RREQ
enables host requests via the host request (HREQ or HRRQ) signal
when the receive data register full (RXDF) status bit in the ISR is set. If
RREQ is cleared, RXDF interrupts are disabled. If RREQ and RXDF are
set, the host request signal (HREQ or HRRQ) is asserted.
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6.7.2 Command Vector Register (CVR)
The host processor uses the CVR to cause the DSP56311 to execute an interrupt. The host
command feature is independent of any of the data transfer mechanisms in the HI08. It can
cause execution of any of the 128 possible interrupt routines in the DSP core. Hardware,
software, individual, and stop resets clear the CVR bits.
7
6
5
4
3
2
1
0
HC
HV6
HV5
HV4
HV3
HV2
HV1
HV0
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Figure 6-15. Command Vector Register (CVR)
Table 6-15. Command Vector Register (CVR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
7
HC
0
Host Command
The host processor uses the HC bit to handshake the execution of host
command interrupts. Normally, the host processor sets HC to request a
host command interrupt from the DSP56311. When the DSP56311
acknowledges the host command interrupt, HIO8 hardware clears the
HC bit. The host processor can read the state of HC to determine when
the host command has been accepted. After setting HC, the host must
not write to the CVR again until the HIO8 hardware clears the HC.
Setting the HC bit causes host command pending (HCP) to be set in the
HSR. The host can write to the HC and HV bits in the same write cycle.
6–0
HV[6 – 0]
0
Host Vector
Select the host command interrupt address for use by the host
command interrupt logic. When the DSP interrupt control logic
recognizes the host command interrupt, the address of the interrupt
routine taken is 2 ™ HV. The host can write HC and HV in the same write
cycle.
The host processor can select any of the 128 possible interrupt routine
starting addresses in the DSP by writing the interrupt routine address
divided by 2 into the HV bits. This means that the host processor can
force any interrupt handler (SSI, SCI, IRQA, IRQB, etc.) and can use
any reserved or otherwise unused addresses (if have been
pre-programmed in the DSP). HV is set to $32 (vector location $0064)
by hardware, software, individual, and stop resets.
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6.7.3 Interface Status Register (ISR)
The host processor uses the ISR, an 8-bit read-only status register, to interrogate the HI08
status and flags. The host processor can write to this address without affecting the internal
state of the HI08. The DSP core cannot access the ISR.
7
6
5
HREQ
4
3
2
1
0
HF3
HF2
TRDY
TXDE
RXDF
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—Reserved bit; read as 0; should be written with 0 for future compatibility.
Figure 6-16. Interface Status Registe (ISR)
Table 6-16. Interface Status Register (ISR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
7
HREQ
0 (Hardware
and Software
reset)
1 (Individual
reset and
TREQ is set)
1 (Stop reset
and TREQ is
set)
Host Request
If HDRQ is set, the HREQ bit indicates the status of the external
transmit and receive request output signals (HTRQ and HRRQ). If
HDRQ is cleared, HREQ indicates the status of the external host
request output signal (HREQ). The HREQ bit is set from either or both of
two conditions— the receive byte registers are full or the transmit byte
registers are empty. These conditions are indicated by status bits: ISR
RXDF indicates that the receive byte registers are full, and ISR TXDE
indicates that the transmit byte registers are empty. If the interrupt
source is enabled by the associated request enable bit in the ICR,
HREQ is set if one or more of the two enabled interrupt sources is set.
6–5
6-28
HDRQ
HREQ
Effect
0
0
HREQ is cleared; no host processor
interrupts are requested.
0
1
HREQ is set; an interrupt is requested.
1
0
HTRQ and HRRQ are cleared, no host
processor interrupts are requested.
1
1
HTRQ or HRRQ are set; an interrupt is
requested.
0
Reserved. Set to 0 for future compatibility.
4
HF3
0
Host Flag 3
Indicates the state of HF3 in the HCR on the DSP side. HF3 can be
changed only by the DSP56311. Hardware and software reset clear
HF3.
3
HF2
0
Host Flag 2
Indicates the state of HF2 in the HCR on the DSP side. HF2 can be
changed only by the DSP56311. Hardware and software reset clear
HF2.
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Table 6-16. Interface Status Register (ISR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
2
TRDY
1
Transmitter Ready
Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY
is set, the data that the host processor writes to TXH:TXM:TXL is
immediately transferred to the DSP side of the HI08. This feature has
many applications. For example, if the host processor issues a host
command that causes the DSP56311 to read the HRX, the host
processor can be guaranteed that the data it just transferred to the HI08
is that being received by the DSP56311. Hardware, software, individual,
and stop resets all set TRDY.
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CAUTION
TRDY = TXDE and HRDF
1
TXDE
1
Transmit Data Register Empty
Indicates that the transmit byte registers (TXH:TXM:TXL) are empty and
can be written by the host processor. TXDE is set when the contents of
the transmit byte registers are transferred to the HRX register. TXDE is
cleared when the transmit register (TXL or TXH according to HLEND bit)
is written by the host processor. The host processor can set TXDE using
the initialize function. TXDE can assert the external HTRQ signal if the
TREQ bit is set. Regardless of whether the TXDE interrupt is enabled,
TXDE indicates whether the TX registers are full and data can be
latched in (so that polling techniques may be used by the host
processor). Hardware, software, individual, and stop resets all set
TXDE.
0
RXDF
0
Receive Data Register Full
Indicates that the receive byte registers (RXH:RXM:RXL) contain data
from the DSP56311 to be read by the host processor. RXDF is set when
the HTX is transferred to the receive byte registers. RXDF is cleared
when the host processor reads the receive data register (RXL or RXH
according to HLEND bit). The host processor can clear RXDF using the
initialize function. RXDF can assert the external HREQ signal if the
RREQ bit is set. Regardless of whether the RXDF interrupt is enabled,
RXDF indicates whether the RX registers are full and data can be
latched out (so that the host processor can use polling techniques).
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6.7.4 Interrupt Vector Register (IVR)
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The IVR is an 8-bit read/write register that typically contains the interrupt vector number
used with MC68000 family processor vectored interrupts. Only the host processor can
read and write this register. The contents of the IVR are placed on the host data bus, H[7 –
0], when both the HREQ and HACK signals are asserted. The contents of this register are
initialized to $0F by a hardware or software reset. This value corresponds to the
uninitialized interrupt vector in the MC68000 family. The hardware and software reset
value of the IVR is $0F.
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Figure 6-17. Interrupt Vector Register (IVR)
6.7.5 Receive Byte Registers (RXH: RXM: RXL)
The host processor views the receive byte registers as three 8-bit read-only registers: the
receive high register (RXH), the receive middle register (RXM), and the receive low
register (RXL). They receive data from the high, middle, and low bytes, respectively, of
the HTX register and are selected by the external host address inputs (HA[2 – 0]) during a
host processor read operation. The memory address of the receive byte registers are set by
ICR[HLEND]. If ICR[HLEND] is set, the RXH is located at address $7, RXM at $6, and
RXL at $5. If ICR[HLEND] is cleared, the RXH is located at address $5, RXM at $6, and
RXL at $7.
When data is transferred from the HTX register to the receive byte register at host address
$7, the ISR Receive Data Register Full (RXDF) bit is set. The host processor can program
the RREQ bit to assert the external HREQ signal when ISR[RXDF] is set. This indicates
that the HI08 has a full word (either 8, 16, or 24 bits) for the host processor. The host
processor can program the RREQ bit to assert the external HREQ signal when
ISR[RXDF] is set. Assertion of the HREQ signal informs the host processor that the
receive byte registers have data to be read. When the host reads the receive byte register at
host address $7, the ISR[RXDF] bit is cleared.
6.7.6 Transmit Byte Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit write-only registers.
These registers are the transmit high register (TXH), the transmit middle register (TXM),
and the transmit low register (TXL). These registers send data to the high, middle, and low
bytes, respectively, of the HRX register and are selected by the external host address
inputs, HA[2 – 0], during a host processor write operation.
6-30
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Host Programmer’s Model
If ICR[HLEND] is set, the TXH register is located at address $7, the TXM register at $6,
and the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is
located at address $5, the TXM register at $6, and the TXL register at $7.
Freescale Semiconductor, Inc...
Data can be written into the transmit byte registers when the ISR transmit data register
empty (TXDE) bit is set. The host processor can program the ICR[TREQ] bit to assert the
external HREQ/HTRQ signal when ISR[TXDE] is set. This informs the host processor
that the transmit byte registers are empty. Writing to the data register at host address $7
clears the ISR[TXDE] bit. The contents of the transmit byte registers are transferred as
24-bit data to the HRX register when both ISR[TXDE] and HSR[HRDF] are cleared. This
transfer operation sets HSR[TXDE] and HSR[HRDF].
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit will not reflect its current
status. For details, see the DSP56300 Family Manual, “Appendix B, Polling a
Peripheral Device for Write.”
6.7.7 Host-Side Registers After Reset
Table 6-17 shows the result of the four kinds of reset on bits in each of the HI08 registers
seen by the host processor. To cause a hardware reset, assert the RESET signal. To cause a
software reset, execute the RESET instruction. To reset the HEN bit individually, clear the
HPCR[HEN] bit. To cause a stop reset, execute the STOP instruction.
Table 6-17. Host-Side Registers After Reset
Reset Type
Register
Name
Register
Data
ICR
CVR
HW
Reset
SW
Reset
IR
Reset
ST
Reset
All bits
0
0
—
—
HC
0
0
0
0
HV[0 – 6]
$32
$32
—
—
HREQ
0
0
1 if TREQ is set;
0 otherwise
1 if TREQ is set;
0 otherwise
HF3 -HF2
0
0
—
—
TRDY
1
1
1
1
TXDE
1
1
1
1
RXDF
0
0
0
0
IVR
IV[0 – 7]
$0F
$0F
—
—
RX
RXH: RXM:RXL
empty
empty
empty
empty
TX
TXH: TXM:TXL
empty
empty
empty
empty
ISR
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Programming Model Quick Reference
6.8 Programming Model Quick Reference
Table 6-18 summarizes the HI08 programming model.
Table 6-18. HI08 Programming Model, DSP Side
Bit
Reset Type
Reg
#
Freescale Semiconductor, Inc...
HCR
HPCR
Motorola
Name
Value
Function
HW/
SW
IR
ST
0
HRIE
Receive
Interrupt
Enable
0
1
HRRQ interrupt disabled
HRRQ interrupt enabled
0
—
—
1
HTIE
Transmit
Interrupt
Enable
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
—
—
2
HCIE
Host Command
Interrupt
Enable
0
1
HCP interrupt disabled
HCP interrupt enabled
0
—
—
3
HF2
Host Flag 2
0
4
HF3
Host Flag 3
0
—
—
0
HGEN
Host GPIO
Enable
0
1
GPIO signal disconnected
GPIO signals active
0
—
—
1
HA8EN
Host Address
Line 8 Enable
0
1
HA8/A1 = GPIO
HA8/A1 = HA8
0
—
—
2
HA9EN
Host Address
Line 9 Enable
0
1
HA9/A2 = GPIO
HA9/A2 = HA9
0
—
—
3
HCSEN
Host Chip
Select Enable
0
1
HCS/A10 = GPIO
HCS/A10 = HCS
0
—
—
Host Interface (HI08)
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Programming Model Quick Reference
Table 6-18. HI08 Programming Model, DSP Side (Continued)
Bit
Reset Type
Reg
#
HPCR
4
Name
HREN
Value
Host Request
Enable
0
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1
5
HAEN
Host
Acknowledge
Enable
0
1
HPCR
Motorola
HW/
SW
IR
ST
HDRQ = 0
HDRQ = 1
HREQ/HTRQ = GPIO
HREQ/HTRQ
HACK/HRRQ = GPIO
HREQ/HTRQ =
HREQ,HREQ/HTRQ
HACK/HRRQ = HTRQ, HRRQ
0
—
—
HDRQ = 0
HDRQ=1
HACK/HRRQ
HREQ/HTRQ
HACK/HRRQ
HACK/HRRQ
HREQ/HTRQ
HACK/HRRQ
0
—
—
—
—
Function
= GPIO
= GPIO
= HACK
= HTRQ, HRRQ
6
HEN
Host Enable
0
1
Host Port = GPIO
Host Port Active
0
8
HROD
Host Request
Open Drain
0
1
HREQ/HTRQ/HRRQ = driven
HREQ/HTRQ/HRRQ = open
drain
0
9
HDSP
Host Data
Strobe Polarity
0
1
HDS/HRD/HWR active low
HDS/HRD/HWR active high
0
—
—
10
HASP
Host Address
Strobe Polarity
0
1
HAS active low
HAS active high
0
—
—
11
HMUX
Host
Multiplexed Bus
0
1
Separate address and data
lines
Multiplexed address/data
0
—
—
12
HDDS
Host Dual Data
Strobe
0
1
Single Data Strobe (HDS)
Double Data Strobe (HWR,
HRD)
0
—
—
13
HCSP
Host Chip
Select Polarity
0
1
HCS active low
HCS active high
0
—
—
14
HRP
Host Request
Polarity
0
1
HREQ/HTRQ/HRRQ active low
HREQ/HTRQ/HRRQ active
high
0
—
—
15
HAP
Host
Acknowledge
Polarity
0
1
HACK active low
HACK active high
0
—
—
Host Interface (HI08)
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Programming Model Quick Reference
Table 6-18. HI08 Programming Model, DSP Side (Continued)
Bit
Reset Type
Reg
#
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HSR
Name
Value
Function
HW/
SW
IR
ST
0
HRDF
Host Receive
Data Full
0
1
no receive data to be read
Receive Data Register is full
0
0
0
1
HTDE
Host Transmit
Data Empty
1
0
The Transmit Data Register is
empty.
The Transmit Data Register is
not empty.
1
1
1
2
HCP
Host Command
Pending
0
1
no host command pending
host command pending
0
0
0
3
HF0
Host Flag 0
0
—
—
4
HF1
Host Flag 1
0
—
—
BA10-B
A3
Host Base
Address
Register
$80
HBAR
7-0
HRX
23-0
DSP Receive
Data Register
empty
HTX
23-0
DSP Transmit
Data Register
empty
HDR
16-0
D16D0
GPIO signal
Data
$0000
—
—
HDRR
16-0
DR16-D
R0
GPIO signal
Direction
$0000
—
—
6-34
[0]
[1]
Input
Output
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Programming Model Quick Reference
Table 6-19. HI08 Programming Model: Host Side
Bit
Reset Type
Reg
#
Freescale Semiconductor, Inc...
ICR
Name
Value
HW/
SW
IR
S
T
0
RREQ
Receive Request Enable
0
1
HRRQ interrupt disabled
HRRQ interrupt enabled
0
—
—
1
TREQ
Transmit Request Enable
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
—
—
2
HDRQ
Double Host Request
0
HREQ/HTRQ = HREQ,
HACK/HRRQ = HACK
HREQ/HTRQ = HTRQ,
HACK/HRRQ = HRRQ
0
—
—
1
ISR
Function
3
HF0
Host Flag 0
0
—
—
4
HF1
Host Flag 1
0
—
—
5
HLEND
Host Little Endian
0
1
Big Endian order
Little Endian order
0
—
—
7
INIT
Initialize
1
Reset data paths according to
TREQ and RREQ
0
—
—
0
RXDF
Receive Data Register Full
0
1
Host Receive Register is empty
Host Receive Register is full
0
0
0
1
TXDE
Transmit Data Register
Empty
1
0
Host Transmit Register is empty
Host Transmit Register is full
1
1
1
2
TRDY
Transmitter Ready
1
0
transmit FIFO (6 deep) is empty
transmit FIFO is not empty
1
1
1
3
HF2
Host Flag 2
0
—
—
4
HF3
Host Flag 3
0
—
—
7
HREQ
Host Request
0
0
0
HV6-HV0
Host Command Vector
$32
—
—
HC
Host Command
0
0
0
—
—
0
1
HREQ signal is deasserted
HREQ signal is asserted (if
enabled)
CVR
6-0
CVR
7
RXH
/M/L
7-0
Host Receive Data
Register
empty
TXH
/M/L
7-0
Host Transmit Data
Register
empty
IVR
7-0
Motorola
IV7-IV0
Interrupt Register
0
1
no host command pending
host command pending
68000 family vector register
Host Interface (HI08)
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Programming Model Quick Reference
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Chapter 7
Enhanced Synchronous Serial
Interface (ESSI)
The ESSI provides a full-duplex serial port for serial communication with a variety of
serial devices, including one or more industry-standard CODECs, other DSPs,
microprocessors, and peripherals. The ESSI consists of independent transmitter and
receiver sections and a common ESSI clock generator. There are two independent and
identical ESSIs in the DSP56311: ESSI0 and ESSI1. For simplicity, a single generic ESSI
is described here. The ESSI block diagram is shown in Figure 7-1. This interface is
synchronous because all serial transfers are synchronized to one clock.
Note:
This synchronous interface should not be confused with the asynchronous
channels mode of the ESSI, in which separate clocks are used for the receiver
and transmitter. In that mode, the ESSI is still a synchronous device because all
transfers are synchronized to these clocks.
Pin notations for the generic ESSI refer to the analogous pin of ESSI0 (PCx)
and ESSI1 (PDx).
Additional synchronization signals delineate the word frames. The Normal mode of
operation transfers data at a periodic rate, one word per period. The Network mode is
similar in that it is also for periodic transfers; however, it supports up to 32 words (time
slots) per period. The Network mode can be used to build time division multiplexed
(TDM) networks. In contrast, the On-Demand mode is for nonperiodic transfers of data.
This mode, which offers a subset of the Motorola Serial Peripheral Interface (SPI)
protocol, can transfer data serially at high speed when the data become available. Since
each ESSI unit can be configured with one receiver and three transmitters, the two units
can be used together for surround sound applications (which need two digital input
channels and six digital output channels).
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Enhanced Synchronous Serial Interface (ESSI)
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ESSI Enhancements
7.1 ESSI Enhancements
The DSP56000 SSI is enhanced in the following ways to make the ESSI:
■
Network enhancements
— Time slot mask registers (receive and transmit)
— End-of-frame interrupt
— Drive enable signal (to be used with transmitter 0)
Freescale Semiconductor, Inc...
GDB DDB
RCLK
RX SHIFT REG
RSMA
SRD
RSMB
RX
TSMA
TCLK
TX0 SHIFT REG
STD
TSMB
TX0
CRA
TX1 SHIFT REG
CRB
SC0
TX1
TSR
TX2 SHIFT REG
SSISR
SC1
TX2
Interrupts
Clock/Frame Sync Generators and Control Logic
SC2
SCK
Figure 7-1. ESSI Block Diagram
7-2
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ESSI Data and Control Signals
■
Audio enhancements
— Three transmitters per ESSI (for six-channel surround sound)
■
General enhancements
— Can trigger DMA interrupts (receive or transmit)
— Separate exception enable bits
■
Other changes
— One divide-by-2 removed from the internal clock source chain
Freescale Semiconductor, Inc...
— Control register A prescaler range (CRA[PSR]) bit definition is reversed
— Gated clock mode not available
7.2 ESSI Data and Control Signals
Three to six signals are required for ESSI operation, depending on the operating mode
selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are
fully synchronized to the clock if they are programmed as transmit-data signals.
7.2.1 Serial Transmit Data Signal (STD)
The STD signal transmits data from the serial transmit shift register. STD is an output when
data is transmitted from the TX0 shift register. With an internally-generated bit clock, the
STD signal becomes a high impedance output signal for a full clock period after the last
data bit is transmitted if another data word does not follow immediately. If sequential data
words are transmitted, the STD signal does not assume a high-impedance state. The STD
signal can be programmed as a GPIO signal (P5) when the ESSI STD function is not in
use.
7.2.2 Serial Receive Data Signal (SRD)
The SRD signal receives serial data and transfers the data to the receive shift register. SRD
can be programmed as a GPIO signal (P4) when the SRD function is not in use.
7.2.3 Serial Clock (SCK)
The SCK signal is a bidirectional signal providing the serial bit rate clock for the ESSI
interface. The SCK signal is a clock input or output used by all the enabled transmitters
and receivers in synchronous modes or by all the enabled transmitters in Asynchronous
modes. See Table 7-1 for details. SCK can be programmed as a GPIO signal (P3) when the
ESSI SCK function is not in use.
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ESSI Data and Control Signals
Table 7-1. ESSI Clock Sources
SYN
SCKD
SCD0
RX Clock Source
RX Clock
Out
TX Clock Source
TX Clock Out
EXT, SCK
EXT, SCK
INT
INT
—
—
SCK
SCK
EXT, SCK
INT
—
SCK
Asynchronous
0
0
0
0
0
0
1
1
0
1
0
1
EXT, SC0
INT
EXT, SC0
INT
—
SC0
—
SC0
Synchronous
Freescale Semiconductor, Inc...
1
1
Note:
0
1
0/1
0/1
EXT, SCK
INT
—
SCK
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, the external ESSI clock frequency must not exceed
Fcore/3, and each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles.
The internally sourced ESSI clock frequency must not exceed Fcore/4.
7.2.4 Serial Control Signal (SC0)
ESSI0: SC00; ESSI1: SC10
To determine the function of the SC0 signal, select either Synchronous or Asynchronous
mode, according to Table 7-2. In Asynchronous mode, this signal is used for the receive
clock I/O. In Synchronous mode, this signal is the transmitter data out signal for transmit
shift register TX1 or for serial flag I/O. A typical application of serial flag I/O would be
multiple device selection for addressing in CODEC systems.
If SC0 is configured as a serial flag signal or receive clock signal, its direction is
determined by the serial control direction 0 (SCD0) bit in ESSI control register B (CRB).
When configured as an output, SC0 functions as the serial output flag 0 (OF0) or as a
receive shift register clock output. If SC0 is used as the serial output flag 0, its value is
determined by the value of the serial output flag 0 (OF0) bit in the CRB. If SC0 is an input,
it functions as either serial Input Flag 0 or a receive shift register clock input. As serial
input flag 0, SC0 controls the state of the serial input flag 0 (IF0) bit in the ESSI status
register (SSISR).
When SC0 is configured as a transmit data signal, it is always an output signal, regardless
of the SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD
and SC1). SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is
not in use.
Note:
7-4
The ESSI can operate with more than one active transmitter only in
Synchronous mode.
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ESSI Data and Control Signals
7.2.5 Serial Control Signal (SC1)
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ESSI0:SC01; ESSI1: SCI11
To determine the function of SC1, select either Synchronous or Asynchronous mode,
according to Table 7-2. In Asynchronous mode (as for a single CODEC with
asynchronous transmit and receive), SC1 is the receiver frame sync I/O. In Synchronous
mode, SC1 is the transmitter data out signal of transmit shift register TX2, for the
transmitter 0 drive-enabled signal, or for serial flag I/O. As serial flag I/O, SC1 operates
like SC0. SC0 and SC1are independent flags but can be used together for multiple serial
device selection; they can be unencoded to select up to two CODECs or decoded
externally to select up to four CODECs. If SC1 is configured as a serial flag or receive
frame sync signal, the Serial Control Direction 1 CRB[SCD1] bit determines its direction.
Table 7-2. Mode and Signal Definitions
Control Bits
ESSI Signals
SYN
TE0
TE1
TE2
RE
SC0
SC1
SC2
SCK
STD
SRD
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
U
RXC
U
RXC
U
F0/U
F0/U
F0/U
TD1
TD1
TD1
TD1
F0/U
F0/U
F0/U
F0/U
TD1
TD1
TD1
TD1
U
FSR
U
FSR
U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
U
U
FST
FST
U
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
U
U
TXC
TXC
U
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
U
U
TD0
TD0
U
U
U
U
U
U
U
U
TD0
TD0
TD0
TD0
TD0
TD0
TD0
TD0
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
TXC
RXC
XC
FST
FSR
FS
TD0
TD1
TD2
T0D
RD
F0
F1
U
X
Motorola
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Transmitter clock
Receiver clock
Transmitter/receiver clock (synchronous operation)
Transmitter frame sync
Receiver frame sync
Transmitter/receiver frame sync (synchronous operation)
Transmit data signal 0
Transmit data signal 1
Transmit data signal 2
Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1
Receive data
Flag 0
Flag 1 if SSC1 = 0
Unused (can be used as GPIO signal)
Indeterminate
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Operation
When configured as an output, the SC1 signal functions as a serial output flag, as the
transmitter 0 drive-enabled signal, or as the receive frame sync signal output. If SC1 is
used as serial output flag 1, its value is determined by the value of the serial output flag 1
(OF1) bit in the CRB. When configured as an input, this signal can receive frame sync
signals from an external source, or it acts as a serial input flag. As a serial input flag,
SC1controls status bit IF1 in the SSISR.
Freescale Semiconductor, Inc...
When SC1 is configured as a transmit data signal, it is always an output signal, regardless
of the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit
data signals (STD and SC0). SC1 can be programmed as a GPIO signal (P1) when the ESSI
SC1 function is not in use.
7.2.6 Serial Control Signal (SC2)
ESSI0:SC02; ESSI1:SC12
SC2 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode
and for the transmitter only in Asynchronous mode. The direction of this signal is
determined by the SCD2 bit in the CRB. When configured as an output, this signal outputs
the internally generated frame sync signal. When configured as an input, this signal
receives an external frame sync signal for the transmitter in Asynchronous mode and for
both the transmitter and receiver when in Synchronous mode. SC2 can be programmed as
a GPIO signal (P2) when the ESSI SC2 function is not in use.
7.3 Operation
This section discusses ESSI basics: reset state, initialization, and exceptions.
7.3.1 ESSI After Reset
A hardware RESET signal or software RESET instruction clears the port control register
and the port direction control register, thus configuring all the ESSI signals as GPIO. The
ESSI is in the reset state while all ESSI signals are programmed as GPIO; it is active only
if at least one of the ESSI I/O signals is programmed as an ESSI signal.
7.3.2 Initialization
To initialize the ESSI, do the following:
1. Send a reset: hardware RESET signal, software RESET instruction, ESSI individual
reset, or STOP instruction reset.
2. Program the ESSI control and time slot registers.
3. Write data to all the enabled transmitters.
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Operation
4. Configure at least one signal as ESSI signal.
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5. If an external frame sync is used, from the moment the ESSI is activated, at least
five (5) serial clocks are needed before the first external frame sync is supplied.
Otherwise, improper operation may result.
When the PC[5 – 0] bits in the GPIO Port Control Register (PCR) are cleared during
program execution, the ESSI stops serial activity and enters the individual reset state. All
status bits of the interface are set to their reset state. The contents of CRA and CRB are not
affected. The ESSI individual reset allows a program to reset each interface separately
from the other internal peripherals. During ESSI individual reset, internal DMA accesses
to the data registers of the ESSI are not valid, and data read there are undefined. To ensure
proper operation of the ESSI, use an ESSI individual reset when you change the ESSI
control registers (except for bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and
RE). Here is an example of how to initialize the ESSI.
1. Put the ESSI in its individual reset state by clearing the PCR bits.
2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2 – 0] and RE bits. Set the interrupt
enable bits for the operating mode chosen.
3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be
used.
4. Write initial data to the transmitters that are in use during operation. This step is
needed even if DMA services the transmitters.
5. Enable the transmitters and receiver to be used.
Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI is enabled
(Step 3), operation starts as follows:
1. For internally generated clock and frame sync, these signals start activity
immediately after the ESSI is enabled.
2. The ESSI receives data after a frame sync signal (either internally or externally
generated) only when the receive enable (RE) bit is set.
3. Data is transmitted after a frame sync signal (either internally or externally
generated) only when the transmitter enable (TE[2 – 0]) bit is set.
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Operation
7.3.3 Exceptions
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The ESSI can generate six different exceptions. They are discussed in the following
paragraphs (ordered from the highest to the lowest exception priority):
■
ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data register is
full, and a receiver overrun error has occurred. This exception sets the ROE bit.
The ROE bit is cleared when you first read the SSISR and then read the Receive
Data Register (RX).
■
ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum overhead.
■
ESSI receive last slot interrupt:
Occurs when the ESSI is in Network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The
receive last slot interrupt can signal that the receive mask slot register can be reset,
the DMA channels can be reconfigured, and data memory pointers can be
reassigned. Using the receive last slot interrupt guarantees that the previous frame
is serviced with the previous setting and the new frame is serviced with the new
setting without synchronization problems.
Note:
7-8
The maximum time it takes to service a receive last slot interrupt should not
exceed N – 1 ESSI bits service time (where N is the number of bits the ESSI can
transmit per time slot).
■
ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit data
register of the enabled transmitters is empty, and a transmitter underrun error has
occurred. This exception sets the TUE bit. The TUE bit is cleared when you first
read the SSISR and then write to all the transmit data registers of the enabled
transmitters, or when you write to TSR to clear the pending interrupt.
■
ESSI transmit last slot interrupt:
Occurs when the ESSI is in Network mode at the start of the last slot of the frame.
This exception occurs regardless of the transmit mask register setting. The transmit
last slot interrupt can signal that the transmit mask slot register can be reset, the
DMA channels can be reconfigured, and data memory pointers can be reassigned.
Using the Transmit Last Slot interrupt guarantees that the previous frame is
serviced with the previous frame settings and the new frame is serviced with the
new frame settings without synchronization problems.
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Operation
Note:
■
The maximum transmit last slot interrupt service time should not exceed
N – 1 ESSI bits service time (where N is the number of bits in a slot).
ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit
data registers is empty, and no transmitter error conditions exist. Write to all the
enabled TX registers or to the TSR to clear this interrupt. This error-free interrupt
uses a fast interrupt service routine for minimum overhead (if no more than two
transmitters are used).
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To configure an ESSI exception, perform the following steps:
1. Configure the interrupt service routine (ISR):
a. Load vector base address register
VBA (b23:8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined, I_VEC
must be defined for the assembler before the interrupt equate file is included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
p:I_SI0TD
2. Configure interrupt trigger; preload transmit data
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (S0L1:0)
b.
c.
d.
e.
f.
Note:
Write data to all enabled transmit registers.
Enable a peripheral interrupt-generating function.
Enable a specific peripheral interrupt.
Enable peripheral and associated signals.
Unmask interrupts at the global level.
TX00
CRB (TE0)
CRB0 (TIE)
PCRC (PC[5 – 0])
SR (I1 – 0)
The example material to the right of the steps shows register settings for
configuring an ESSI0 transmit interrupt using transmitter 0. The order of the
steps is optional except that the interrupt trigger configuration must not be
completed until the ISR configuration is complete. Since step c may cause an
immediate transmit without generating an interrupt, perform the transmit data
preload in step b before step c to ensure that valid data is sent in the first
transmission.
After the first transmit, subsequent transmit values are typically loaded into
TXnn by the ISR (one value per register per interrupt). Therefore, if N items are
to be sent from a particular TXnn, the ISR needs to load the transmit register (N
– 1) times. Steps, c, and d can be performed in step a as a single instruction. If
an interrupt trigger event occurs before all interrupt trigger configuration steps
are performed, the event is ignored and not queued. If interrupts derived from
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Operating Modes: Normal, Network, and On-Demand
the core or other peripherals need to be enabled at the same time as ESSI
interrupts, step g should be performed last.
7.4 Operating Modes: Normal, Network, and On-Demand
The ESSI has three basic operating modes and several data and operation formats. These
modes are programmed via the ESSI control registers. The data and operation formats
available to the ESSI are selected when you set or clear control bits in the CRA and CRB.
These control bits are WL[2 – 1], MOD, SYN, FSL[1 – 0], FSR, FSP, CKP, and SHFD.
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7.4.1 Normal/Network/On-Demand Mode Selection
To select either Normal mode or Network mode, clear or set CRB[MOD]. In Normal
mode, the ESSI sends or receives one data word per frame (per enabled receiver or
transmitter). In Network mode, 2 to 32 time slots per frame can be selected. During each
frame, 0 to 32 data words are received or transmitted (from each enabled receiver or
transmitter). In either case, the transfers are periodic.
The Normal mode typically transfers data to or from a single device. Network mode is
typically used in time division multiplexed networks of CODECs or DSPs with multiple
words per frame.
Network mode has a submode called On-Demand mode. Set the CRB[MOD] for Network
mode, and set the frame rate divider to 0 (DC = $00000) to select On-Demand mode. This
submode does not generate a periodic frame sync. A frame sync pulse is generated only
when data is available to transmit. The frame sync signal indicates the first time slot in the
frame. On-Demand mode requires that the transmit frame sync be internal (output) and the
receive frame sync be external (input). For simplex operation, Synchronous mode could
be used; however, for full-duplex operation, Asynchronous mode must be used. You can
enable data transmission that is data-driven by writing data into each TX. Although the
ESSI is double-buffered, only one word can be written to each TX, even if the transmit
shift register is empty. The receive and transmit interrupts function normally, using TDE
and RDF; however, transmit underruns are impossible for On-Demand transmission and
are disabled. This mode is useful for interfacing with CODECs requiring a continuous
clock.
Note:
7-10
When the ESSI transmits data in On-Demand mode (that is, MOD = 1 in the
CRB and DC[4 – 0]=$00000 in the CRA) with WL[2 – 0] = 100, the
transmission does not work properly. To ensure correct operation, do not use
On-Demand mode with the WL[2 – 0] = 100 32-bit word length mode.
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Operating Modes: Normal, Network, and On-Demand
7.4.2 Synchronous/Asynchronous Operating Modes
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The transmit and receive sections of the ESSI interface are synchronous or asynchronous.
The transmitter and receiver use common clock and synchronization signals in
Synchronous mode; they use separate clock and sync signals in Asynchronous mode. The
SYN bit in CRB selects synchronous or asynchronous operation. When the SYN bit is
cleared, the ESSI TX and RX clocks and frame sync sources are independent. If the SYN
bit is set, the ESSI TX and RX clocks and frame sync are driven by the same source (either
external or internal). Since the ESSI operates either synchronously or asynchronously,
separate receive and transmit interrupts are provided.
Transmitter 1 and transmitter 2 operate only in Synchronous mode. Data clock and frame
sync signals are generated internally by the DSP or obtained from external sources. If
clocks are internally generated, the ESSI clock generator derives bit clock and frame sync
signals from the DSP internal system clock. The ESSI clock generator consists of a
selectable fixed prescaler with a programmable prescaler for bit rate clock generation and
a programmable frame-rate divider with a word-length divider for frame-rate sync-signal
generation.
7.4.3 Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either a
bit-long or word-long frame-sync signal format, and the receiver can have the same or
another format. The selection is made by programming the CRB FSL[1 – 0], FSR, and
FSP bits.
7.4.4 Frame Sync Signal Format
CRB[FSL1] controls the frame sync signal format.
■
If CRB[FSL1] is cleared, the RX frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola CODECs,
serial peripherals that conform to the Motorola SPI, serial A/D and D/A converters,
shift registers, and telecommunication pulse code modulation serial I/O.
■
If CRB[FSL1] is set, the RX frame sync pulses active for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel·1
and National Semiconductor Corporation components, CODECs, and
telecommunication pulse code modulation serial I/O.
1. Intel
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Operating Modes: Normal, Network, and On-Demand
7.4.5 Frame Sync Length for Multiple Devices
The ability to mix frame sync lengths is useful to configure systems in which data is
received from one type of device (for example, CODEC) and transmitted to a different
type of device. CRB[FSL0] controls whether RX and TX have the same frame sync
length.
■
If CRB[FSL0] is cleared, both RX and TX have the same frame sync length.
■
If CRB[FSL0] is set, RX and TX have different frame sync lengths.
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CRB[FSL0] is ignored when CRB[SYN] is set.
7.4.6 Word Length Frame Sync and Data Word Timing
The CRB[FSR] bit controls the relative timing of the word length frame sync relative to
the data word timing.
■
When CRB[FSR] is cleared, the word length frame sync is generated (or expected)
with the first bit of the data word.
■
When CRB[FSR] is set, the word length frame sync is generated (or expected) with
the last bit of the previous word.
CRB[FSR] is ignored when a bit length frame sync is selected.
7.4.7 Frame Sync Polarity
The CRB[FSP] bit controls the polarity of the frame sync.
■
When CRB[FSP] is cleared, the polarity of the frame sync is positive; that is, the
frame sync signal is asserted high. The ESSI synchronizes on the leading edge of
the frame sync signal.
■
When CRB[FSP] is set, the polarity of the frame sync is negative; that is, the frame
sync is asserted low. The ESSI synchronizes on the trailing edge of the frame sync
signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if CRB[FSP] is
cleared, trailing edge if FSP is set) only when the previous frame is completed. If the
frame sync is asserted before the frame is completed (or before the last bit of the frame is
received in the case of a bit frame sync or a word-length frame sync with CRB[FSR] set),
the current frame sync is not recognized, and the receiver is internally disabled until the
next frame sync.
Frames do not have to be adjacent; that is, a new frame sync does not have to follow the
previous frame immediately. Gaps of arbitrary periods can occur between frames. All the
enabled transmitters are tri-stated during these gaps.
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Operating Modes: Normal, Network, and On-Demand
7.4.8 Byte Format (LSB/MSB) for the Transmitter
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Some devices, such as CODECs, require a MSB-first data format. Other devices, such as
those that use the AES – EBU digital audio format, require the LSB first. To be
compatible with all formats, the shift registers in the ESSI are bidirectional. You select
either MSB or LSB by programming CRB[SHFD].
■
If CRB[SHFD] is cleared, data is shifted into the receive shift register MSB first
and shifted out of the transmit shift register MSB first.
■
If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and
shifted out of the transmit shift register LSB first.
7.4.9 Flags
Two ESSI signals (SC[1 – 0]) are available for use as serial I/O flags. Their operation is
controlled by the SYN, SCD[1 – 0], SSC1, and TE[2 – 1] bits in the CRB/CRA.The
control bits OF[1 – 0] and status bits IF[1 – 0] are double-buffered to and from SC[1 – 0].
Double-buffering the flags keeps the flags in sync with TX and RX.
The SC[1 – 0] flags are available in Synchronous mode only. Each flag can be separately
programmed. The SC0 flag is enabled when transmitter 1 is disabled (TE1 = 0). The flag’s
direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output.
When SCD0 is cleared, SC0 is configured as input. Similarly, the SC1 flag is enabled
when transmitter 2 is disabled (TE2 = 0), and the SC1 signal is not configured as the
transmitter 0 drive-enabled signal (Bit SSC1 = 0). The direction of SC1 is determined by
the SCD1 bit. When SCD1 is set, SC1 is an output flag. When SCD1 is cleared, SC1 is an
input flag.
When programmed as input flags, the value of the SC[1 – 0] bits is latched at the same
time as the first bit of the received data word is sampled. Once the input is latched, the
signal on the input flag signal (SC0 and SC1) can change without affecting the input flag.
The value of SC[1 – 0] does not change until the first bit of the next data word is received.
When the received data word is latched by RX, the latched values of SC[1 – 0] are latched
by the SSISR IF[1 – 0] bits, respectively, and can be read by software.
When they are programmed as output flags, the value of the SC[1 – 0] bits is taken from
the value of the OF[1 – 0] bits. The value of OF[1 – 0] is latched when the contents of TX
transfer to the transmit shift register. The value on SC[1 – 0] is stable from the time the
first bit of the transmit data word transmits until the first bit of the next transmit data word
transmits. Software can directly set the OF[1 – 0] values, allowing the DSP56311 to
control data transmission by indirectly controlling the value of the SC[1 – 0] flags.
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ESSI Programming Model
7.5 ESSI Programming Model
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The ESSI is composed of the following registers:
■
Two control registers (CRA, CRB), page 7-14 and page 7-18
■
One status register (SSISR), page 7-29
■
One Receive Shift Register, page 7-31
■
One Receive Data Register (RX), page 7-31
■
Three Transmit Shift Registers, page 7-31
■
Three Transmit Data Registers (TX0, TX1, TX2), page 7-31
■
One special-purpose Time Slot Register (TSR), page 7-34
■
Two Transmit Slot Mask Registers (TSMA, TSMB), page 7-34
■
Two Receive Slot Mask Registers (RSMA, RSMB), page 7-35
This section discusses the ESSI registers and describes their bits. Section 7.6, "GPIO
Signals and Registers," on page 7-36 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that
direct the operation of the ESSI. CRA controls the ESSI clock generator bit and frame
sync rates, word length, and number of words per frame for serial data.
23
22
21
20
19
18
SSC1
WL2
WL1
WL0
ALC
10
9
8
7
6
5
PM7
PM6
PM5
11
PSR
17
16
15
14
13
12
DC4
DC3
DC2
DC1
DC0
4
3
2
1
0
PM4
PM3
PM2
PM1
PM0
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
Figure 7-2. ESSI Control Register A(CRA)
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
Bit Number
23
7-14
Bit Name
Reset Value
0
Description
Reserved. Write to 0 for future compatibility.
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ESSI Programming Model
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Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
22
SSC1
0
Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
21 – 19
WL[2 – 0]
0
Word Length Control
Select the length of the data words transferred via the ESSI. Word lengths
of 8-, 12-, 16-, 24-, or 32-bits can be selected. The ESSI data path
programming model in Figure 7-12 and Figure 7-13 shows additional
information on how to select different lengths for data words. The ESSI data
registers are 24 bits long. The ESSI transmits 32-bit words in one of two
ways:
■
■
by duplicating the last bit 8 times when WL[2 – 0] = 100
by duplicating the first bit 8 times when WL[2 – 0] = 101.
NOTE: When WL[2 – 0] = 100, the ESSI is designed to duplicate the last bit
of the 24-bit transmission eight times to fill the 32-bit shifter. Instead, after
the 24-bit word is shifted correctly, eight zeros (0s) are shifted.
ESSI Word Length Selection
WL2
WL1
WL0
Number of Bits/Word
0
0
0
8
0
0
1
12
0
1
0
16
0
1
1
24
1
0
0
32
(valid data in the first 24
bits)
1
0
1
32
(valid data in the last 24
bits)
1
1
0
Reserved
1
1
1
Reserved
NOTE: When the ESSI transmits data in On-Demand mode (that is, MOD =
1 in the CRB and DC[4 – 0]=00000 in the CRA) with WL[2 – 0] = 100, the
transmission does not work properly. To ensure correct operation, do not
use On-Demand mode with the WL[2 – 0] = 100 32-bit word length mode.
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ESSI Programming Model
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Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
18
ALC
0
Alignment Control
The ESSI handles 24-bit fractional data. Shorter data words are left-aligned
to the MSB, bit 23. For applications that use 16-bit fractional data, shorter
data words are left-aligned to bit 15. The ALC bit supports shorter data
words. If ALC is set, received words are left-aligned to bit 15 in the receive
shift register. Transmitted words must be left-aligned to bit 15 in the transmit
shift register. If the ALC bit is cleared, received words are left-aligned to bit
23 in the receive shift register. Transmitted words must be left-aligned to bit
23 in the transmit shift register.
NOTE: If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use
of 24- or 32-bit words leads to unpredictable results.
17
Reserved. Set to 0 for future compatibility.
16 – 12
DC[4 – 0]
0
Frame Rate Divider Control
Control the divide ratio for the programmable frame rate dividers that
generate the frame clocks. In Network mode, this ratio is the number of
words per frame minus one. In Normal mode, this ratio determines the word
transfer rate. The divide ratio ranges from 1 to 32 (DC = 00000 to 11111) for
Normal mode and 2 to 32 (DC = 00001 to 11111) for Network mode. A
divide ratio of one (DC = 00000) in Network mode is a special case known
as On-Demand mode. In Normal mode, a divide ratio of one (DC = 00000)
provides continuous periodic data word transfers. A bit-length frame sync
must be used in this case; you select it by setting the FSL[1 – 0] bits in the
CRA to (01). Figure 7-4 shows the ESSI frame sync generator functional
block diagram.
11
PSR
0
Prescaler Range
Controls a fixed divide-by-eight prescaler in series with the variable
prescaler. This bit extends the range of the prescaler when a slower bit
clock is needed. When PSR is set, the fixed prescaler is bypassed. When
PSR is cleared, the fixed divide-by-eight prescaler is operational, as in
Figure 7-3. This definition is reversed from that of the SSI in other
DSP56000 family members. The maximum allowed internally generated bit
clock frequency is the internal DSP56311 clock frequency divided by 4; the
minimum possible internally generated bit clock frequency is the DSP56311
internal clock frequency divided by 4096.
NOTE: The combination PSR = 1 and PM[7 – 0] = $00 (dividing Fcore by 2)
can cause synchronization problems and thus should not be used.
10 – 8
7-16
0
Reserved. Set to 0 for future compatibility.
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Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
7–0
PM
0
Prescale Modulus Select
Specify the divide ratio of the prescale divider in the ESSI clock generator. A
divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive
clock (SC0) signal of the DSP. The bit clock output is also available
internally for use as the bit clock to shift the transmit and receive shift
registers. Figure 7-3 shows the ESSI clock generator functional block
diagram. Fcore is the DSP56311 core clock frequency (the same frequency
as the enabled CLKOUT signal). Careful choice of the crystal oscillator
frequency and the prescaler modulus can generate the industry-standard
CODEC master clock frequencies of 2.048 MHz, 1.544 MHz, and
1.536 MHz.
TX 1 or Flag0 Out
Flag0 In
CRB(TE1) CRB(OF0) SSISR(IF0)
(Sync Mode)
(Sync Mode)
CRA(WL2 – 0)
/8, /12, /16, /24,
SCD0 = 0
SYN = 0
CRB(SYN) =
SCn0
Sync:
TX 1, or
Flag0
Async:
CRB(SCD0)
RX clk
FCORE
1
2
3 4,5
RX Shift Register
SYN = 0
SCD0 = 1
RCLOCK
SYN = 1
TCLOCK
Internal Bit Clock
SCKn
Sync:
TX/RX clk
Async:
CRB(SCKD)
TX clk
/2
0
RX
Word
Clock
CRA(WL2 – 0)
/8, /12, /16, /24,
0 1
2
3 4,5
TX
Word
Clock
TX Shift Register
CRA(PSR)
CRA(PM7:0)
/1 or /8
/1 to /256
1
0
(Opposite
from SSI)
0
255
Note:1. FCORE is the DSP56300 core
internal clock frequency.
2. ESSI internal clock range:
min = FOSC/4096
max = FOSC/4
3. ‘n’ in signal name is ESSI # (0 or 1)
Figure 7-3. ESSI Clock Generator Functional Block Diagram
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ESSI Programming Model
CRB(FSL1)
CRB(FSR)
RX
Word
CRA(DC4:0)
SyncType
/1 to /32
0
Internal Rx Frame Sync
CRB(SCD1)
31
CRB(SCD1) = 1
SYN = 0
CRB(SYN) = 0
Receive
Receive
Control
Logic
Frame Sync
SCD1 =
SCn1
Sync:
TX 2 Flag1,
or drive enb.
Async:
RX F.S.
SYN = 1
SYN =
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These signals are
identical in sync mode.
Flag1 In
TX 2, Flag1 Out, or drive enb.
SSISR(IF1) CRB(TE2) CRB(OF1) CRA(SSC1)
(Sync Mode)
(Sync Mode)
CRB(FSL[1 – 0])
CRB(FSR)
TX Word
Clock
CRB(SCD2)
CRA(DC4 – 0)
Sync
Type
/1 to /32
0
31
Transmit
Control
Logic
Internal TX Frame Sync
SCn2
Sync:
TX/RX F.S.
Async:
TX F.S.
Transmit
Frame Sync
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
7.5.2 ESSI Control Register B (CRB)
Control Register B (CRB) is one of two read/write control registers that direct the
operation of the ESSI (see Figure 7-5). The CRB bit definitions are presented in Table
7-4. CRB controls the ESSI multifunction signals, SC[2 – 0], which can be used as clock
inputs or outputs, frame synchronization signals, transmit data signals, or serial I/O flag
signals.
23
22
21
20
19
18
17
16
15
14
13
12
REIE
TEIE
RLIE
TLIE
RIE
TIE
RE
TE0
TE1
TE2
MOD
SYN
11
10
9
8
7
6
5
4
3
2
1
0
CKP
FSP
FSR
FSL1
FSL0
SHFD
SCKD
SCD2
SCD1
SCD0
OF1
OF0
(ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)
Figure 7-5. ESSI Control Register B (CRB)
The CRB contains the serial output flag control bits and the direction control bits for the
serial control signals. Also in the CRB are interrupt enable bits for the receiver and the
transmitter. Bit settings of the CRB determines how many transmitters are enabled: 0, 1, 2,
7-18
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ESSI Programming Model
or 3. The CRB settings also determine the ESSI operating mode. Either a hardware RESET
signal or a software RESET instruction clears all the bits in the CRB. Table 7-2, “Mode
and Signal Definitions,” on page 7-5 summarizes the relationship between the ESSI
signals SC[2 – 0], SCK, and the CRB bits.
The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence follows for
setting output flags when transmitting data (by transmitter 0 through the STD signal only).
1. Wait for TDE (TX0 empty) to be set.
2. Write the flags.
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3. Write the transmit data to the TX register.
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals
when the TX data is transferred to the transmit shift register. The flag bit values are
synchronized with the data transfer.
Note:
The timing of the optional serial output signals SC[2 – 0] is controlled by the
frame timing and is not affected by the settings of TE2, TE1, TE0, or the
receive enable (RE) bit of the CRB.
The ESSI has three transmit enable bits (TE[2 – 0]), one for each data transmitter. The
process of transmitting data from TX1 and TX2 is the same. TX0 differs from these two
bits in that it can also operate in Asynchronous mode. The normal transmit enable
sequence is to write data to one or more transmit data registers (or the time slot register
(TSR)) before you set the TE bit. The normal transmit disable sequence is to set the
transmit data empty (TDE) bit and then to clear the TE, transmit interrupt enable (TIE),
and transmit exception interrupt enable (TEIE) bits. In Network mode, if you clear the
appropriate TE bit and set it again, then you disable the corresponding transmitter (0, 1, or
2) after transmission of the current data word. The transmitter remains disabled until the
beginning of the next frame. During that time period, the corresponding SC (or STD in the
case of TX0) signal remains in a high-impedance state. The CRB bits are cleared by either
a hardware RESET signal or a software RESET instruction.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23
REIE
0
Receive Exception Interrupt Enable
When the REIE bit is set, the DSP is interrupted when both RDF and
ROE in the ESSI status register are set. When REIE is cleared, this
interrupt is disabled. The receive interrupt is documented in Section
7.3.3, "Exceptions," on page 7-8. A read of the status register followed
by a read of the receive data register clears both ROE and the pending
interrupt.
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ESSI Programming Model
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Name
Reset Value
22
TEIE
0
Transmit Exception Interrupt Enable
When the TEIE bit is set, the DSP is interrupted when both TDE and
TUE in the ESSI status register are set. When TEIE is cleared, this
interrupt is disabled. The use of the transmit interrupt is documented
in Section 7.3.3, "Exceptions," on page 7-8. A read of the status
register, followed by a write to all the data registers of the enabled
transmitters, clears both TUE and the pending interrupt.
21
RLIE
0
Receive Last Slot Interrupt Enable
Enables/disables an interrupt after the last slot of a frame ends when
the ESSI is in Network mode. When RLIE is set, the DSP is interrupted
after the last slot in a frame ends regardless of the receive mask register
setting. When RLIE is cleared, the receive last slot interrupt is disabled.
The use of the receive last slot interrupt is documented in Section
7.3.3, "Exceptions," on page 7-8. RLIE is disabled when the ESSI is in
On-Demand mode (DC = $0).
20
TLIE
0
Transmit Last Slot Interrupt Enable
Enables/disables an interrupt at the beginning of the last slot of a frame
when the ESSI is in Network mode. When TLIE is set, the DSP is
interrupted at the start of the last slot in a frame regardless of the
transmit mask register setting. When TLIE is cleared, the transmit last
slot interrupt is disabled. The transmit last slot interrupt is documented
in Section 7.3.3, "Exceptions," on page 7-8. TLIE is disabled when the
ESSI is in On-Demand mode (DC = $0).
19
RIE
0
Receive Interrupt Enable
Enables/disables a DSP receive data interrupt; the interrupt is
generated when both the RIE and receive data register full (RDF) bit (in
the SSISR) are set. When RIE is cleared, this interrupt is disabled. The
receive interrupt is documented in Section 7.3.3, "Exceptions," on page
7-8. When the receive data register is read, it clears RDF and the
pending interrupt. Receive interrupts with exception have higher priority
than normal receive data interrupts. If the receiver overrun error (ROE)
bit is set (signaling that an exception has occurred) and the REIE bit is
set, the ESSI requests an SSI receive data with exception interrupt from
the interrupt controller.
18
TIE
0
Transmit Interrupt Enable
Enables/disables a DSP transmit interrupt; the interrupt is generated
when both the TIE and the TDE bits in the ESSI status register are set.
When TIE is cleared, the transmit interrupt is disabled. The transmit
interrupt is documented in Section 7.3.3. When data is written to the
data registers of the enabled transmitters or to the TSR, it clears TDE
and also clears the interrupt. Transmit interrupts with exception
conditions have higher priority than normal transmit data interrupts. If
the transmitter underrun error (TUE) bit is set (signaling that an
exception has occurred) and the TEIE bit is set, the ESSI requests an
SSI transmit data with exception interrupt from the interrupt controller.
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Bit Number
7-20
Description
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
17
RE
0
Receive Enable
Enables/disables the receive portion of the ESSI. When RE is cleared,
the receiver is disabled: data transfer into RX is inhibited. If data is being
received while this bit is cleared, the remainder of the word is shifted in
and transferred to the ESSI receive data register. RE must be set in
both Normal and On-Demand modes for the ESSI to receive data. In
Network mode, clearing RE and setting it again disables the receiver
after reception of the current data word. The receiver remains disabled
until the beginning of the next data frame.
NOTE: The setting of the RE bit does not affect the generation of a
frame sync.
16
TE0
0
Transmit 0 Enable
Enables the transfer of data from TX1 to Transmit Shift Register 0. TE0
is functional when the ESSI is in either synchronous or Asynchronous
mode. When TE0 is set and a frame sync is detected, the transmitter 0
is enabled for that frame.
When TE0 is cleared, transmitter 0 is disabled after the transmission of
data currently in the ESSI transmit shift register. The STD output is
tri-stated, and any data present in TX0 is not transmitted. In other
words, data can be written to TX0 with TE0 cleared; the TDE bit is
cleared, but data is not transferred to the transmit shift register 0. The
transmit enable sequence in On-Demand mode can be the same as in
Normal mode, or TE0 can be left enabled.
NOTE: Transmitter 0 is the only transmitter that can operate in
Asynchronous mode (SYN = 0). The setting of the TE0 bit does not
affect the generation of frame sync or output flags.
15
TE1
0
Transmit 1 Enable
Enables the transfer of data from TX1 to Transmit Shift Register 1. TE1
is functional only when the ESSI is in Synchronous mode and is ignored
when the ESSI is in Asynchronous mode. When TE1 is set and a frame
sync is detected, transmitter 1 is enabled for that frame.
When TE1 is cleared, transmitter 1 is disabled after completing
transmission of data currently in the ESSI transmit shift register. Any
data present in TX1 is not transmitted. If TE1 is cleared, data can be
written to TX1; the TDE bit is cleared, but data is not transferred to
transmit shift register 1. If the TE1 bit is kept cleared until the start of the
next frame, it causes the SC0 signal to act as serial I/O flag from the
start of the frame in both Normal and Network mode. The transmit
enable sequence in On-Demand mode can be the same as in Normal
mode, or the TE1 bit can be left enabled.
NOTE: The setting of the TE1 bit does not affect the generation of frame
sync or output flags.
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
14
TE2
0
Transmit 2 Enable
Enables the transfer of data from TX2 to Transmit Shift Register 2. TE2
is functional only when the ESSI is in Synchronous mode and is ignored
when the ESSI is in Asynchronous mode. When TE2 is set and a frame
sync is detected, transmitter 2 is enabled for that frame.
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When TE2 is cleared, transmitter 2 is disabled after completing
transmission of data currently in the ESSI transmit shift register. Any
data present in TX2 is not transmitted. If TE2 is cleared, data can be
written to TX2; the TDE bit is cleared, but data is not transferred to
transmit shift register 2. If the TE2 bit is kept cleared until the start of the
next frame, it causes the SC1 signal to act as a serial I/O flag from the
start of the frame in both Normal mode and Network mode. The transmit
enable sequence in On-Demand mode can be the same as in Normal
mode, or the TE2 bit can be left enabled.
NOTE: The setting of the TE2 bit does not affect the generation of frame
sync or output flags.
7-22
13
MOD
0
Mode Select
Selects the operational mode of the ESSI, as in Figure 7-8 on page
7-27, Figure 7-9 on page 7-28, and Figure 7-10 on page 7-28. When
MOD is cleared, the Normal mode is selected; when MOD is set, the
Network mode is selected. In Normal mode, the frame rate divider
determines the word transfer rate: one word is transferred per frame
sync during the frame sync time slot. In Network mode, a word can be
transferred every time slot. For details, see Section 7.3.
12
SYN
0
Synchronous/Asynchronous
Controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other. (See
Figure 7-7 on page 7-26.) When SYN is cleared, the ESSI is in
Asynchronous mode, and separate clock and frame sync signals are
used for the transmit and receive sections. When SYN is set, the ESSI
is in Synchronous mode, and the transmit and receive sections use
common clock and frame sync signals. Only in Synchronous mode can
more than one transmitter be enabled.
11
CKP
0
Clock Polarity
Controls which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked
out on the rising edge of the transmit bit clock and latched in on the
falling edge of the receive bit clock. If CKP is set, the data and the frame
sync are clocked out on the falling edge of the transmit bit clock and
latched in on the rising edge of the receive bit clock.
10
FSP
0
Frame Sync Polarity
Determines the polarity of the receive and transmit frame sync signals.
When FSP is cleared, the frame sync signal polarity is positive; that is,
the frame start is indicated by the frame sync signal going high. When
FSP is set, the frame sync signal polarity is negative; that is, the frame
start is indicated by the frame sync signal going low.
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
9
FSR
0
Frame Sync Relative Timing
Determines the relative timing of the receive and transmit frame sync
signal in reference to the serial data lines for word length frame sync
only. When FSR is cleared, the word length frame sync occurs together
with the first bit of the data word of the first slot. When FSR is set, the
word length frame sync occurs one serial clock cycle earlier (that is,
simultaneously with the last bit of the previous data word).
7–8
FSL[1 – 0]
0
Frame Sync Length
Selects the length of frame sync to be generated or recognized, as in
Figure 7-6 on page 7-25, Figure 7-9 on page 7-28, and Figure 7-10 on
page 7-28.
Frame Sync Length
FSL1
FSL0
RX
TX
0
0
word
word
0
1
word
bit
1
0
bit
bit
1
1
bit
word
6
SHFD
0
Shift Direction
Determines the shift direction of the transmit or receive shift register. If
SHFD is set, data is shifted in and out with the LSB first. If SHFD is
cleared, data is shifted in and out with the MSB first, as in Figure 7-12
on page 7-32 and Figure 7-13 on page 7-33.
5
SCKD
0
Clock Source Direction
Selects the source of the clock signal that clocks the transmit shift
register in Asynchronous mode and both the transmit and receive shift
registers in Synchronous mode. If SCKD is set and the ESSI is in
Synchronous mode, the internal clock is the source of the clock signal
used for all the transmit shift registers and the receive shift register. If
SCKD is set and the ESSI is in Asynchronous mode, the internal clock
source becomes the bit clock for the transmit shift register and word
length divider. The internal clock is output on the SCK signal. When
SCKD is cleared, the external clock source is selected. The internal
clock generator is disconnected from the SCK signal, and an external
clock source may drive this signal.
4
SCD2
0
Serial Control Direction 2
Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is
an output; when SCD2 is cleared, SC2 is an input.
NOTE: Programming the ESSI to use an internal frame sync (that is,
SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be programmed
as outputs. However, if the corresponding multiplexed pins are
programmed by the Port Control Register (PCR) to be GPIOs, the GPIO
Port Direction Register (PRR) chooses their direction. The ESSI uses
an external frame sync if GPIO is selected. To assure correct operation,
either program the GPIO pins as outputs or configure the pins in the
PCR as ESSI signals. The default selection for these signals after reset
is GPIO. This note applies to both ESSI0 and ESSI1.
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Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Name
Reset Value
Description
3
SCD1
0
Serial Control Direction 1
In Synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 =
0), or in Asynchronous mode (SYN = 0), SCD1 controls the direction of
the SC1 I/O signal. When SCD1 is set, SC1 is an output; when SCD1 is
cleared, SC1 is an input. When TE2 is set, the value of SCD1 is ignored
and the SC1 signal is always an output.
2
SCD0
0
Serial Control Direction 0
In Synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 =
0), or in Asynchronous mode (SYN = 0), SCD0 controls the direction of
the SC0 I/O signal. When SCD0 is set, SC0 is an output; when SCD0 is
cleared, SC0 is an input. When TE1 is set, the value of SCD0 is ignored
and the SC0 signal is always an output.
1
OF1
0
Serial Output Flag 1
In Synchronous mode (SYN = 1), when transmitter 2 is disabled (TE2 =
0), the SC1 signal is configured as ESSI flag 1. When SCD1 is set, SC1
is an output. Data present in bit OF1 is written to SC1 at the beginning of
the frame in Normal mode or at the beginning of the next time slot in
Network mode.
0
OF0
0
Serial Output Flag 0
In Synchronous mode (SYN = 1), when transmitter 1 is disabled (TE1 =
0), the SC0 signal is configured as ESSI flag 0. When SCD0 is set, the
SC0 signal is an output. Data present in Bit OF0 is written to SC0 at the
beginning of the frame in Normal mode or at the beginning of the next
time slot in Network mode.
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Bit Number
7-24
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Word Length: FSL1 = 0, FSL0 = 0
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
Data
Data
NOTE: Frame sync occurs while data is valid.
One Bit Length: FSL1 = 1, FSL0 = 0
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Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
Data
Data
NOTE: Frame sync occurs for one bit time preceding the data.
Mixed Frame Length: FSL1 = 0, FSL0 = 1
Serial Clock
RX Frame Sync
RXSerial Data
Data
Data
Data
Data
TX Frame SYNC
TX Serial Data
Mixed Frame Length: FSL1 = 1, FSL0 = 1
Serial Clock
RX Frame SYNC
RX Serial Data
Data
Data
TX Frame SYNC
TX Serial Data
Data
Data
Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0)
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Asynchronous (SYN = 0)
Transmitter
Clock
SCK
ESSI Bit
Clock
SC0
External Transmit Clock
External Transmit Frame
Internal Clock
Internal Frame SYNC
External Receive Clock
External Receive Frame
Clock
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STD
Frame
SYNC
Frame
SYNC
SC2
SC1
SR
Receiver
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN = 1)
Transmitter
Clock
SCK
ESSI Bit
Clock
ST
Frame
SYNC
External Clock
External Frame SYNC
Internal Clock
Internal Frame SYNC
Clock
Frame
SYNC
SC2
SRD
Receiver
NOTE: Transmitter and receiver may have the same clock frame syncs.
Figure 7-7. CRB SYN Bit Operation
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Slot 1
Slot 2
Slot 1
Receiver Interrupt (or DMA Request) and Flags Set
Slot 3
Transmitter Interrupts (or DMA Request) and
Network Mode (MOD = 1)
NOTE: Interrupts occur every time slot and a word may be transferred.
Serial Data
Frame SYNC
Serial Clock
Data
Receiver Interrupt (or DMA Request) and Flags
Transmitter Interrupt (or DMA Request) and
NOTE: Interrupts occur and data is transferred once per frame sync.
Serial Data
Frame SYNC
Serial Clock
Normal Mode (MOD = 0)
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Slot 2
SSI Control Register B (CRB)
(READ/WRITE)
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ESSI Programming Model
Figure 7-8. CRB MOD Bit Operation
7-27
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ESSI Programming Model
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data Out
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Flags
Slot 0
Wait
Slot 0
Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data
Flags
SLOT 0
SLOT 1
SLOT 0
SLOT 1
Figure 7-10. Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)
7-28
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7.5.3 ESSI Status Register (SSISR)
The SSISR is a 24-bit read-only status register by which the DSP reads the ESSI status
and serial input flags.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDF
TDE
ROE
TUE
RFS
TFS
IF1
IF0
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(ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)
Figure 7-11. ESSI Status Register (SSISR)
Table 7-5. ESSI Status Register (SSISR) Bit Definitions
Bit Number
Bit Name
23 – 8
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
7
RDF
0
Receive Data Register Full
Set when the contents of the receive shift register transfer to the receive
data register. RDF is cleared when the DSP reads the receive data
register. If RIE is set, a DSP receive data interrupt request is issued
when RDF is set.
6
TDE
0
Transmit Data Register Empty
Set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a
TSR disabled time slot period in Network mode (as if data were being
transmitted after the TSR has been written). When TDE is set, TDE data
is written to all the TX registers of the enabled transmitters or to the
TSR. The TDE bit is cleared when the DSP writes to all the transmit
data registers of the enabled transmitters, or when the DSP writes to the
TSR to disable transmission of the next time slot. If the TIE bit is set, a
DSP transmit data interrupt request is issued when TDE is set.
5
ROE
0
Receiver Overrun Error Flag
Set when the serial receive shift register is filled and ready to transfer to
the receive data register (RX) but RX is already full (that is, the RDF bit
is set). If the REIE bit is set, a DSP receiver overrun error interrupt
request is issued when the ROE bit is set. The programmer clears ROE
by reading the SSISR with the ROE bit set and then reading the RX.
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Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
Bit Name
Reset Value
Description
4
TUE
0
Transmitter Underrun Error Flag
TUE is set when at least one of the enabled serial transmit shift registers
is empty (that is, there is no new data to be transmitted) and a transmit
time slot occurs. When a transmit underrun error occurs, the previous
data (which is still present in the TX registers not written) is
retransmitted. In Normal mode, there is only one transmit time slot per
frame. In Network mode, there can be up to 32 transmit time slots per
frame. If the TEIE bit is set, a DSP transmit underrun error interrupt
request is issued when the TUE bit is set. The programmer can also
clear TUE by first reading the SSISR with the TUE bit set, then writing to
all the enabled transmit data registers or to the TSR.
3
RFS
0
Receive Frame Sync Flag
When set, the RFS bit indicates that a receive frame sync occurred
during the reception of a word in the serial receive data register. In other
words, the data word is from the first time slot in the frame. When the
RFS bit is cleared and a word is received, it indicates (only in Network
mode) that the frame sync did not occur during reception of that word.
RFS is valid only if the receiver is enabled (that is , if the RE bit is set).
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Bit Number
NOTE: In Normal mode, RFS is always read as 1 when data is read
because there is only one time slot per frame, the frame sync time slot.
2
TFS
0
Transmit Frame Sync Flag
When set, TFS indicates that a transmit frame sync occurred in the
current time slot. TFS is set at the start of the first time slot in the frame
and cleared during all other time slots. If the transmitter is enabled, data
written to a transmit data register during the time slot when TFS is set is
transmitted (in Network mode) during the second time slot in the frame.
TFS is useful in Network mode to identify the start of a frame. TFS is
valid only if at least one transmitter is enabled that is, when TE0, TE1, or
TE2 is set).
NOTE: In Normal mode, TFS is always read as 1 when data is being
transmitted because there is only one time slot per frame, the frame
sync time slot.
7-30
1
IF1
0
Serial Input Flag 1
The ESSI latches any data on the SC1 signal during reception of the
first received bit after the frame sync is detected. IF1 is updated with this
data when the data in the receive shift register transfers into the receive
data register. IF1 is enabled only when SC1 is an input flag and
Synchronous mode is selected; that is, when SC1 is programmed as
ESSI in the port control register (PCR), the SYN bit is set, and the TE2
and SCD1 bits are cleared. If it is not enabled, IF1 is cleared.
0
IF0
0
Serial Input Flag 0
The ESSI latches any data on the SC0 signal during reception of the
first received bit after the frame sync is detected. The IF0 bit is updated
with this data when the data in the receive shift register transfers into the
receive data register. IF0 is enabled only when SC0 is an input flag and
the Synchronous mode is selected; that is, when SC0 is programmed as
ESSI in the port control register (PCR), the SYN bit is set, and the TE1
and SCD0 bits are cleared. If it is not enabled, the IF0 bit is cleared.
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7.5.4 ESSI Receive Shift Register
The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives incoming
data from the serial receive data signal. The selected (internal/external) bit clock shifts
data in when the associated frame sync I/O is asserted. Data is received MSB first if SHFD
is cleared and LSB first if SHFD is set. Data transfers to the ESSI receive data register
after 8, 12, 16, 24, or 32 serial clock cycles are counted, depending on the word length
control bits in the CRA.
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7.5.5 ESSI Receive Data Register (RX)
The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the
receive shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The
data read is aligned according to the value of the ALC bit. When the ALC bit is cleared,
the MSB is bit 23, and the least significant byte is unused. When the ALC bit is set, the
MSB is bit 15, and the most significant byte is unused. Unused bits are read as 0. If the
associated interrupt is enabled, the DSP is interrupted whenever the RX register becomes
full.
7.5.6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted, as in Figure
7-12 and Figure 7-13. Data is shifted out to the serial transmit data signals by the selected
(whether internal or external) bit clock when the associated frame sync I/O is asserted.
The word-length control bits in CRA determine the number of bits that must be shifted out
before the shift registers are considered empty and can be written again. Depending on the
setting of the CRA, the number of bits to be shifted out can be 8, 12, 16, 24, or 32.
Transmitted data is aligned according to the value of the ALC bit. When ALC is cleared,
the MSB is Bit 23 and the least significant byte is unused. When ALC is set, the MSB is
Bit 15 and the most significant byte is unused. Unused bits are read as 0. Data shifts out of
these registers MSB first if the SHFD bit is cleared and LSB first if SHFD is set.
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ESSI Programming Model
23
87
16 15
Receive High Byte
7
Receive Middle Byte
0 7
0
ESSI Receive Data
Register
Receive Low Byte
07
0
16 15
87
Serial 23
Receive
Receive High Byte
Receive Middle Byte
Receive Low Byte
Shift
0 7
07
Register 7
0
0
24 Bit
Freescale Semiconductor, Inc...
16 Bit
12 Bit
8 Bit
WL1, WL0
MSB
MSB
8-bit Data
LSB
0
0
SRD
Least Significant
Zero Fill
0
LSB
12-bit Data
LSB
MSB
16-bit Data
MSB
LSB
24-bit Data
NOTES:
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
(a) Receive Registers
23
16 15
Transmit High Byte
8 7
Transmit Middle Byte
0
ESSI Transmit Data
Register
Transmit Low Byte
7
0 7
0 7
0
23
16 15
0 7
0
Transmit High Byte
STD
7
Transmit Middle Byte
0 7
MSB
MSB
MSB
8-bit Data
07
LSB
0
ESSI Transmit
Shift Register
Transmit Low Byte
0
0
Least Significant
Zero Fill
0
LSB
12-bit Data
LSB
16-bit Data
MSB
LSB
24-bit Data
(b) Transmit Registers
NOTES:
Data is transmitted MSB first if
SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
Figure 7-12. ESSI Data Path Programming Model (SHFD = 0)
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ESSI Programming Model
23
8 7
16 15
Receive High Byte
Receive Middle Byte
ESSI Receive Data
Register (Read Only)
Receive Low Byte
7
0 7
0 7
0
23
16 15
0 7
0
Receive High Byte
SR
7
Receive Middle Byte
0 7
MSB
8-bit Data
LSB
0
ESSI Receive
Shift Register
Receive Low Byte
0 7
MSB
0
0
Least Significant
Zero Fill
0
LSB
12-bit Data
LSB
MSB
Freescale Semiconductor, Inc...
0
16-bit Data
MSB
LSB
24-bit Data
NOTES:
(a) Receive Registers
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
23
16 15
87
0
ESSI Transmit Data
Register
Transmit High Byte
Transmit Middle Byte
Transmit Low Byte
(Write Only)
7
0 7
0
07
23
16 15
Transmit High Byte
7
07
Transmit Middle Byte
0 7
0
Transmit Low Byte
07
0
ESSI Transmit Shift
Register
24 Bit
16 Bit
12 Bit
8 Bit
MSB
8-bit Data
LSB
MSB
12-bit Data
MSB
0
0
ST
0
WL1, WL0
Least Significant
Zero Fill
LSB
LSB
16-bit Data
MSB
24-bit Data
(b) Transmit Registers
LSB
NOTES:
Data is received MSB first if SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
Figure 7-13. ESSI Data Path Programming Model (SHFD = 1)
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ESSI Programming Model
7.5.7 ESSI Transmit Data Registers (TX[2 – 0])
ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01
TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers
automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.)
The data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC
bit. When the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15.
If the transmit data register empty interrupt has been enabled, the DSP is interrupted
whenever a transmit data register becomes empty.
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Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
while any status bits affected by this operation are updated. If any of those
status bits are read during the two-cycle delay, the status bit may not reflect the
current status. For details, see the DSP56300 Family Manual, “Appendix B,
Polling a Peripheral Device for Write.”
7.5.8 ESSI Time Slot Register (TSR)
TSR is effectively a write-only null data register that prevents data transmission in the
current transmit time slot. For timing purposes, TSR is a write-only register that behaves
as an alternative transmit data register, except that, rather than transmitting data, the
transmit data signals of all the enabled transmitters are in the high-impedance state for the
current time slot.
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)
Both transmit slot mask registers are read/write registers. When the TSMA or TSMB is
read to the internal data bus, the register contents occupy the two low-order bytes of the
data bus, and the high-order byte is filled by 0. In Network mode the transmitter(s) use
these registers to determine which action to take in the current transmission slot.
Depending on the bit settings, the transmitter(s) either tri-state the transmitter(s) data
signal(s) or transmit a data word and generate a transmitter empty condition.
23
22
21
11
10
9
TS11
TS10
TS9
20
8
19
7
18
6
17
5
16
4
TS8
TS7
TS6
TS5
TS4
(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)
15
14
13
12
TS15
TS14
TS13
TS12
3
2
1
0
TS3
TS2
TS1
TS0
Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA)
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ESSI Programming Model
23
22
21
11
10
9
TS27
TS26
TS25
20
8
19
7
18
6
17
5
16
4
TS24
TS23
TS22
TS21
TS20
(ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)
15
14
13
12
TS31
TS30
TS29
TS28
3
2
1
0
TS19
TS18
TS17
TS16
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Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB)
TSMA and TSMB (as in Figure 7-12 and Figure 7-13) can be seen as a single 32-bit
register, TSM. Bit n in TSM (TSn) is an enable/disable control bit for transmission in slot
number N. When TSn is cleared, all the data signals of the enabled transmitters are
tri-stated during transmit time slot number N. The data still transfers from the enabled
transmit data register(s) to the transmit shift register. However, the TDE and the TUE
flags are not set. Consequently, during a disabled slot, no transmitter empty interrupt is
generated. The DSP is interrupted only for enabled slots. Data written to the transmit data
register when the transmitter empty interrupt request is serviced transmits in the next
enabled transmit time slot. When TSn is set, the transmit sequence proceeds normally.
Data transfers from the TX register to the shift register during slot number N, and the TDE
flag is set.
The TSM slot mask does not conflict with the TSR. Even if a slot is enabled in the TSM,
you can chose to write to the TSR to tri-state the signals of the enabled transmitters during
the next transmission slot. Setting the bits in the TSM affects the next frame transmission.
The frame being transmitted is not affected by the new TSM setting. If the TSM is read, it
shows the current setting.
After a hardware RESET signal or software RESET instruction, the TSM register is reset to
$FFFFFFFF, enabling all 32 slots for data transmission.
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
Both receive slot mask registers are read/write registers. In Network mode, the receiver(s)
use these registers to determine which action to take in the current time slot. Depending on
the setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive
a data word and generate a receiver full condition.
23
22
21
11
10
9
RS11
RS10
RS9
20
8
19
7
18
6
17
5
16
4
RS8
RS7
RS6
RS5
RS4
(ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)
15
14
13
12
RS15
RS14
RS13
RS12
3
2
1
0
RS3
RS2
RS1
RS0
Figure 7-16. ESSI Receive Slot Mask Register A (RSMA)
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GPIO Signals and Registers
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
11
10
9
8
7
6
5
4
3
2
1
0
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
– Reserved. Read as zero. Write with zero for future compatibility.
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
Freescale Semiconductor, Inc...
Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)
RSMA and RSMB (as in Figure 7-12 and Figure 7-13) can be seen as one 32-bit register,
RSM. Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When
RSn is cleared, all the data signals of the enabled receivers are tri-stated during time slot
number N. Data transfers from the receive data register(s) to the receive shift register(s),
but the RDF and ROE flags are not set. Consequently, during a disabled slot, no receiver
full interrupt is generated. The DSP is interrupted only for enabled slots. When RSn is set,
the receive sequence proceeds normally. Data is received during slot number N, and the
RDF flag is set.
When the bits in the RSM are set, their setting affects the next frame transmission. The
frame being transmitted is not affected by the new RSM setting. If the RSM is read, it
shows the current setting.
When RSMA or RSMB is read by the internal data bus, the register contents occupy the
two low-order bytes of the data bus, and the high-order byte is filled by 0.
After a hardware RESET signal or a software RESET instruction, the RSM register is reset
to $FFFFFFFF, enabling all 32 time slots for data transmission.
7.6 GPIO Signals and Registers
The GPIO functionality of an ESSI port (whether C or D) is controlled by three registers:
port control register (PCRC, PCRD), port direction register (PRRC, PRRD), and port data
register (PDRC, PDRD).
7.6.1 Port Control Register (PCR)
The read/write 24-bit PCR controls the functionality of the ESSI GPIO signals. Each of
the PC[5 – 0] bits controls the functionality of the corresponding port signal. When a PC[i]
bit is set, the corresponding port signal is configured as an ESSI signal. When a PC[i] bit
is cleared, the corresponding port signal is configured as a GPIO signal. Either a hardware
RESET signal or a software RESET instruction clears all PCR bits.
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GPIO Signals and Registers
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC5
PC4
PC3
PC2
PC1
PC0
STDn SRDn SCKn SCn2 SCn1
0 = GPIO, 1 = ESSI
SCn0
PRCR: ESSI0, PCRD: ESSI1
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Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-18. Port Control Register (PCR) (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
7.6.2 Port Direction Register (PRR)
The read/write 24-bit PRR controls the data direction of the ESSI GPIO signals. When
PRR[i] is set, the corresponding signal is an output signal. When PRR[i] is cleared, the
corresponding signal is an input signal. Either a hardware RESET signal or a software
RESET instruction clears all PRR bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
0 = Input, 1 = Output
STDn
PRRC: ESSI0, PRRD: ESSI1
SRDn SCKn SCn2 SCn1
SCn0
Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-19. Port Direction Register (PRR)(PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
The following table shows the port signal configurations.
PC[i]
PDC[i]
Port Signal[i] Function
1
X
ESSI
0
0
GPIO input
0
1
GPIO output
X: The signal setting is irrelevant to the Port Signal[i] function.
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GPIO Signals and Registers
7.6.3 Port Data Register (PDR)
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The read/write 24-bit PDR reads or writes data to and from the ESSI GPIO signals. The
PD[5 – 0] bits read or write data from and to the corresponding port signals if they are
configured as GPIO signals. If a port signal [i] is configured as a GPIO input, the
corresponding PD[i] bit reflects the value present on this signal. If a port signal [i] is
configured as a GPIO output, the value written into the corresponding PD[i] bit is
reflected on this signal. Either a hardware RESET signal or a software RESET instruction
clears all PDR bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD5
PD4
PD3
PD2
PD1
PD0
STDn
SRDn SCKn SCn2 SCn1
SCn0
PDRC: ESSI0, PDRD: ESSI1
Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-20. Port Data Register (PDR) (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)
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Chapter 8
Serial Communication Interface (SCI)
The DSP56311 Serial Communication Interface (SCI) provides a full-duplex port for
serial communication with other DSPs, microprocessors, or peripherals such as modems.
The SCI interfaces without additional logic to peripherals that use TTL-level signals. With
a small amount of additional logic, the SCI can connect to peripheral interfaces that have
non-TTL level signals, such as RS232C, RS422, and so on. This interface uses three
dedicated signals: transmit data, receive data, and SCI serial clock. It supports
industry-standard asynchronous bit rates and protocols, as well as high-speed synchronous
data transmission (up to 8.25 Mbps for a 66 MHz clock). SCI asynchronous protocols
include a multidrop mode for master/slave operation with wake-up on idle line and
wake-up on address bit capability. This mode allows the DSP56311 to share a single serial
line efficiently with other peripherals.
The SCI consists of separate transmit and receive sections that can operate asynchronously
with respect to each other. A programmable baud rate generator supplies the transmit and
receive clocks. An enable vector and an interrupt vector are included so that the baud-rate
generator can function as a general-purpose timer when the SCI is not using it, or when the
interrupt timing is the same as that used by the SCI.
8.1 Operating Modes
The operating modes for the DSP56311 SCI are as follows:
■
8-bit synchronous (shift register mode)
■
10-bit asynchronous (1 start, 8 data, 1 stop)
■
11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)
■
11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)
■
11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)
This mode is used for master/slave operation with wake-up on idle line and wakeup
on address bit capability. It allows the DSP56311 to share a single serial line
efficiently with other peripherals.
These modes are selected by the SCR WD[0 – 2] bits. Synchronous data mode is
essentially a high-speed shift register for I/O expansion and stream-mode channel
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Operating Modes
interfaces. A gated transmit and receive clock compatible with the Intel 8051 serial
interface mode 0 synchronizes data. Asynchronous modes are compatible with most
UART-type serial devices. Standard RS232C communication links are supported by these
modes. Multidrop Asynchronous mode is compatible with the MC68681 DUART, the
M68HC11 SCI interface, and the Intel 8051 serial interface.
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8.1.1 Synchronous Mode
Synchronous mode (WDS=0, Shift Register mode) handles serial-to-parallel and
parallel-to-serial conversions. In Synchronous mode, the clock is always common to the
transmit and receive shift registers. As a controller (synchronous master), the DSP puts out
a clock on the SCLK pin. To select master mode, choose the internal transmit and receive
clocks (set TCM and RCM=0).
As a peripheral (synchronous slave), the DSP accepts an input clock from the SCLK pin. To
select the slave mode, choose the external transmit and receive clocks (TCM and
RCM=1). Since there is no frame signal, if a clock is missed because of noise or any other
reason, the receiver loses synchronization with the data without any error signal being
generated. You can detect an error of this type with an error detecting protocol or with
external circuitry such as a watchdog timer. The simplest way to recover synchronization
is to reset the SCI.
8.1.2 Asynchronous Mode
Asynchronous data uses a data format with embedded word sync, which allows an
unsynchronized data clock to be synchronized with the word if the clock rate and number
of bits per word is known. Thus, the clock can be generated by the receiver rather than
requiring a separate clock signal. The transmitter and receiver both use an internal clock
that is 16 ™ the data rate to allow the SCI to synchronize the data. The data format requires
that each data byte have an additional start bit and stop bit. Also, two of the word formats
have a parity bit. The Multidrop mode used when SCIs are on a common bus has an
additional data type bit. The SCI can operate in full-duplex or half-duplex modes since the
transmitter and receiver are independent.
8.1.3 Multidrop Mode
Multidrop is a special case of asynchronous data transfer. The key difference is that a
protocol allows networking transmitters and receivers on a single data-transmission line.
Inter-processor messages in a multidrop network typically begin with a destination
address. All receivers check for an address match at the start of each message. Receivers
with no address match can ignore the remainder of the message and use a wakeup mode to
enable the receiver at the start of the next message. Receivers with an address match can
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I/O Signals
receive the message and optionally transmit an acknowledgment to the sender. The
particular message format and protocol used are determined by the user’s software.
8.1.3.1 Transmitting Data and Address Characters
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To send data, the 8-bit data character must be written to the STX register. Writing the data
character to the STX register sets the ninth bit in the frame to zero, which indicates that
this frame contains data. To send an 8-bit address, the address data is written to the STXA
register, and the ninth bit in the frame is set to one, indicating that this frame contains an
address.
8.1.3.2 Wired-OR Mode
Building a multidrop bus network requires connecting multiple transmitters to a common
wire. The Wired-OR mode allows this to be done without damaging the transmitters when
the transmitters are not in use. A protocol is still needed to prevent two transmitters from
simultaneously driving the bus. The SCI multidrop word format provides an address field
to support this protocol.
8.1.3.3 Idle Line Wakeup
A wakeup mode frees a DSP from reading messages intended for other processors. The
usual operational procedure is for each DSP to suspend SCI reception (the DSP can
continue processing) until the beginning of a message. Each DSP compares the address in
the message header with the DSP’s address. If the addresses do not match, the SCI again
suspends reception until the next address. If the address matches, the DSP reads and
processes the message and then suspends reception until the next address. The Idle Line
Wakeup mode wakes up the SCI to read a message before the first character arrives.
8.1.3.4 Address Mode Wakeup
The purpose and basic operational procedure for Address Mode Wakeup is the same as for
Idle Line Wakeup. The difference is that Address Mode Wakeup re-enables the SCI when
the ninth bit in a character is set to one (if cleared, this bit marks a character as data; if set,
an address). As a result, an idle line is not needed, which eliminates the dead time between
messages.
8.2 I/O Signals
Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO
signal or as a specific SCI signal. Each signal is independent of the others. For example, if
only the TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO.
However, at least one of the three signals must be selected as an SCI signal to release the
SCI from reset.
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SCI After Reset
To enable SCI interrupts, program the SCI control registers before any of the SCI signals
are programmed as SCI functions. In this case, only one transmit interrupt can be
generated because the Transmit Data Register is empty. The timer and timer interrupt
operate regardless of how the SCI pins are configured, either as SCI or GPIO.
8.2.1 Receive Data (RXD)
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This input signal receives byte-oriented serial data and transfers the data to the SCI receive
shift register. Asynchronous input data is sampled on the positive edge of the receive
clock (1 ™ SCLK) if the SCI Clock Polarity (SCKP) bit is cleared. RXD can be configured as
a GPIO signal (PE0) when the SCI RXD function is not in use.
8.2.2 Transmit Data (TXD)
This output signal transmits serial data from the SCI transmit shift register. Data changes
on the negative edge of the asynchronous transmit clock (SCLK) if SCKP is cleared. This
output is stable on the positive edge of the transmit clock. TXD can be programmed as a
GPIO signal (PE1) when the SCI TXD function is not in use.
8.2.3 SCI Serial Clock (SCLK)
This bidirectional signal provides an input or output clock from which the transmit and/or
receive baud rate is derived in Asynchronous mode and from which data is transferred in
Synchronous mode. SCLK can be programmed as a GPIO signal (PE2) when the SCI SCLK
function is not in use. This signal can be programmed as PE2 when data is being
transmitted on TXD, since the clock does not need to be transmitted in Asynchronous
mode. Because SCLK is independent of SCI data I/O, there is no connection between
programming the PE2 signal as SCLK and data coming out the TXD signal.
8.3 SCI After Reset
There are several different ways to reset the SCI:
8-4
■
Hardware RESET signal
■
Software RESET instruction:
Both hardware and software resets clear the port control register bits, which
configure all I/O as GPIO input. The SCI remains in the Reset state as long as all
SCI signals are programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI
becomes active only when at least one of the SCI I/O signals is not programmed as
GPIO.
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SCI After Reset
■
Individual reset:
During program execution, the PC2, PC1, and PC0 bits can all be cleared (that is,
individually reset), causing the SCI to stop serial activity and enter the Reset state.
All SCI status bits are set to their reset state. However, the contents of the SCR
remain unaffected so the DSP program can reset the SCI separately from the other
internal peripherals. During individual reset, internal DMA accesses to the data
registers of the SCI are not valid, and the data is unknown.
■
Stop processing state reset (that is, the STOP instruction)
Executing the STOP instruction halts operation of the SCI until the DSP is
restarted, causing the SCI Status Register (SSR) to be reset. No other SCI registers
are affected by the STOP instruction.
Table 8-1 illustrates how each type of reset affects each register in the SCI.
Table 8-1. SCI Registers After Reset
Reset Type
Register
SCR
SSR
SCCR
SRX
STX
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Bit Mnemonic
REIE
SCKP
STIR
TMIE
TIE
RIE
ILIE
TE
RE
WOMS
RWU
WAKE
SBK
SSFTD
WDS[2 – 0]
R8
FE
PE
OR
IDLE
RDRF
TDRE
TRNE
TCM
RCM
SCP
COD
CD[11 – 0]
SRX [23 – 0]
STX[23 – 0]
Bit Number
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2–0
7
6
5
4
3
2
1
0
15
14
13
12
11–0
23–16, 15–8, 7–0
23–0
HW Reset
SW Reset
IR Reset
ST Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
1
1
—
—
—
—
—
—
—
Serial Communication Interface (SCI)
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SCI Initialization
Table 8-1. SCI Registers After Reset (Continued)
Reset Type
Register
Bit Mnemonic
Bit Number
HW Reset
SW Reset
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SRSH
SRS[8 – 0]
8–0
—
—
STSH
STS[8 – 0]
8–0
—
—
SRSH SCI receive shift register, STSH — SCI transmit shift register
HW
Hardware reset is caused by asserting the external RESET signal.
SW
Software reset is caused by executing the RESET instruction.
IR
Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO).
ST
Stop reset is caused by executing the STOP instruction.
1
The bit is set during this reset.
0
The bit is cleared during this reset.
—
The bit is not changed during this reset.
IR Reset
ST Reset
—
—
—
–
8.4 SCI Initialization
The SCI is initialized as follows:
1. Ensure that the SCI is in its individual reset state (PCRE = $0). Use a hardware
RESET signal or software RESET instruction.
2. Program the SCI control registers.
3. Configure at least one SCI signal as and SCI signal.
If interrupts are to be used, the signals must be selected, and global interrupts must be
enabled and unmasked before the SCI can operate. The order does not matter; any one of
these three requirements for interrupts can enable the SCI, but the interrupts should be
unmasked last (that is, I[1 – 0] bits in the Status Register (SR) should be changed last).
Synchronous applications usually require exact frequencies, so the crystal frequency must
be chosen carefully. An alternative to selecting the system clock to accommodate the SCI
requirements is to provide an external clock to the SCI. When the SCI is configured in
Synchronous mode, internal clock, and all the SCI pins are simultaneously enabled, an
extra pulse of one DSP clock length is provided on the SCLK pin. There are two
workarounds for this issue:
■
Enable an SCI pin other than SCLK.
■
In the next instruction, enable the remaining SCI pins, including the SCLK pin.
Following is an example of one way to initialize the SCI:
1. Ensure that the SCI is in its individual reset state (PCRE = $0).
2. Configure the control registers (SCR, SCCR) according to the operating mode, but
do not enable transmitter (TE = 0) or receiver (RE = 0).
It is now possible to set the interrupts enable bits that are used during the operation.
No interrupt occurs yet.
8-6
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SCI Initialization
3. Enable the SCI by setting the PCRE bits according to which signals are used during
operation.
4. If transmit interrupt is not used, write data to the transmitter.
If transmitter interrupt enable is set, an interrupt is issued and the interrupt handler
should write data into the transmitter. The DMA channel services the SCI transmit
request if it is programmed to service the SCI transmitter.
5. Enable transmitters (TE = 1) and receiver (RE = 1) according to use.
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Operation starts as follows:
■
For an internally-generated clock, the SCLK signal starts operation immediately
after the SCI is enabled (Step 3 above) for Asynchronous modes. In Synchronous
mode, the SCLK signal is active only while transmitting (that is, a gated clock).
■
Data is received only when the receiver is enabled (RE = 1) and after the
occurrence of the SCI receive sequence on the RXD signal, as defined by the
operating mode (that is, idle line sequence).
■
Data is transmitted only after the transmitter is enabled (TE = 1), and after the
initialization sequence has been transmitted (depending on the operating mode).
8.4.1 Preamble, Break, and Data Transmission Priority
Two or three transmission commands can be set simultaneously:
■
A preamble (TE is set.)
■
A break (SBK is set or is cleared.)
■
An indication that there is data for transmission (TDRE is cleared.)
After the current character transmission, if two or more of these commands are set, the
transmitter executes them in the following order: preamble, break, data.
8.4.2 Bootstrap Loading Through the SCI (Operating Mode 6)
When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA
pins and sets the corresponding mode bits in the Operating Mode Register (OMR). If the
mode bits are set to 1010, respectively, the DSP loads the program RAM from the SCI.
Appendix A, Bootstrap Program shows the complete bootstrap code. This program (1)
configures the SCI, (2) loads the program size, (3) loads the location where the program
begins loading in program memory, and (4) loads the program.
First, the SCI Control Register is set to $0302, which enables the transmitter and receiver
and configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit,
and no parity. Next, the SCI Clock Control Register is set to $C000, which configures the
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Exceptions
SCI to use external receive and transmit clocks on the SCLK pin. This clock must be 16
times the serial data rate.
The next step is to receive the program size and then the starting address to load the
program. These two numbers are three bytes each loaded least significant byte first. Each
byte is echoed back as it is received. After both numbers are loaded, the program size is in
A0 and the starting address is in A1.
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The program is then loaded one byte at a time, least significant byte first. After the
program is loaded, the operating mode is set to zero, the CCR is cleared, and the DSP
begins execution with the first instruction loaded
8.5 Exceptions
The SCI can cause five different exceptions in the DSP, discussed here from the highest to
the lowest priority:
1. SCI receive data with exception status occurs when the receive data register is full
with a receiver error (parity, framing, or overrun error). To clear the pending
interrupt, read the SCI status register; then read SRX. Use a long interrupt service
routine to handle the error condition. This interrupt is enabled by SCR[16] (REIE).
2. SCI receive data occurs when the receive data register is full. Read SRX to clear
the pending interrupt. This error-free interrupt can use a fast interrupt service
routine for minimum overhead. This interrupt is enabled by SCR[11] (RIE).
3. SCI transmit data occurs when the transmit data register is empty. Write STX to
clear the pending interrupt. This error-free interrupt can use a fast interrupt service
routine for minimum overhead. This interrupt is enabled by SCR[12] (TIE).
4. SCI idle line occurs when the receive line enters the idle state (10 or 11 bits
of ones). This interrupt is latched and then automatically reset when the interrupt is
accepted. This interrupt is enabled by SCR[10] (ILIE).
5. SCI timer occurs when the baud rate counter reaches zero. This interrupt is
automatically reset when the interrupt is accepted. This interrupt is enabled by
SCR[13] (TMIE).
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SCI Programming Model
8.6 SCI Programming Model
The SCI programming model can be viewed as three types of registers:
■
Control
— SCI Control Register (SCR) in Figure 8-3
— SCI Clock Control Register (SCCR) in Figure 8-5
■
Status
— SCI Status Register (SSR) in Figure 8-4
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■
Data transfer
— SCI Receive Data Registers (SRX) in Figure 8-8
— SCI Transmit Data Registers (STX) in Figure 8-8
— SCI Transmit Data Address Register (STXA) in Figure 8-8
The SCI includes the GPIO functions described in Section 8.7, "GPIO Signals and
Registers," on page 8-25. The next subsections describe the registers and their bits.
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SCI Programming Model
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
D7
D6
D5
D4
D3
D2
D1
D0
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
WDS2 WDS1 WDS0
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TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Data
Type
Stop
Bit
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Even
Data
Parity
Type
Stop
Bit
Mode 5
1
0
1
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Odd
Data
Parity
Type
Stop
Bit
Mode 6
1
1
0
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
Data Type: 1 = Address Byte
0 = Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Data
Type
Stop
Bit
Note: 1.Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB
3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if
SSFTD = 1
Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1
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SCI Programming Model
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
D0
D1
D2
D3
D4
D5
D6
D7
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
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WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7 or
Data
Type
Stop
Bit
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D7 or
Even
Data
Parity
Type
D6
Stop
Bit
Mode 5
1
0
1
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7 or
Odd
Data
Parity
Type
Stop
Bit
Mode 6
1
1
0
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
Data Type: 1 = Address Byte
0 = Data Byte
D1
D2
D3
D4
D5
D6
D7
Data
Type
Stop
Bit
Note: 1.Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB.
3. Data is transmitted and received LSB first if SSFTD = 0,
or MSB first if SSFTD = 1.
Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2
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SCI Programming Model
8.6.1 SCI Control Register (SCR)
The SCR is a read/write register that controls the serial interface operation. Seventeen of
its 24 bits are defined.
.
23
22
21
20
19
18
17
16
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REIE
15
14
13
12
11
10
9
8
SCKP
STIR
TMIE
TIE
RIE
ILIE
TE
RE
7
6
5
4
3
2
1
0
WOMS
RWU
WAKE
SBK
SSFTD
WDS2
WDS1
WDS0
Figure 8-3. SCI Control Register (SCR)
Table 8-2. SCI Control Register (SCR) Bit Definitions
Bit Number
Bit Name
23 – 17
8-12
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
16
REIE
0
Receive with Exception Interrupt Enable
Enables/disables the SCI receive data with exception interrupt. If REIE
is cleared, the receive data with exception interrupt is disabled. If both
REIE and RDRF are set, and PE, FE, and OR are not all cleared, the
SCI requests an SCI receive data with exception interrupt from the
interrupt controller. Either a hardware RESET signal or a software
RESET instruction clears REIE.
15
SCKP
0
SCI Clock Polarity
Controls the clock polarity sourced or received on the clock signal
(SCLK), eliminating the need for an external inverter. When SCKP is
cleared, the clock polarity is positive; when SCKP is set, the clock
polarity is negative. In Synchronous mode, positive polarity means that
the clock is normally positive and transitions negative during valid data.
Negative polarity means that the clock is normally negative and
transitions positive during valid data. In Asynchronous mode, positive
polarity means that the rising edge of the clock occurs in the center of
the period that data is valid. Negative polarity means that the falling
edge of the clock occurs during the center of the period that data is
valid. Either a hardware RESET signal or a software RESET instruction
clears SCKP.
14
STIR
0
Timer Interrupt Rate
Controls a divide-by-32 in the SCI Timer interrupt generator. When
STIR is cleared, the divide-by-32 is inserted in the chain. When STIR is
set, the divide-by-32 is bypassed, thereby increasing timer resolution by
a factor of 32. Either a hardware RESET signal or a software RESET
instruction clears this bit. To ensure proper operation of the timer, STIR
must not be changed during timer operation (that is, if TMIE = 1).
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SCI Programming Model
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Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
13
TMIE
0
Timer Interrupt Enable
Enables/disables the SCI timer interrupt. If TMIE is set, timer interrupt
requests are sent to the interrupt controller at the rate set by the SCI
clock register. The timer interrupt is automatically cleared by the timer
interrupt acknowledge from the interrupt controller. This feature allows
DSP programmers to use the SCI baud rate generator as a simple
periodic interrupt generator if the SCI is not in use, if external clocks are
used for the SCI, or if periodic interrupts are needed at the SCI baud
rate. The SCI internal clock is divided by 16 (to match the 1 ™ SCI baud
rate) for timer interrupt generation. This timer does not require that any
SCI signals be configured for SCI use to operate. Either a hardware
RESET signal or a software RESET instruction clears TMIE.
12
TIE
0
SCI Transmit Interrupt Enable
Enables/disables the SCI transmit data interrupt. If TIE is cleared,
transmit data interrupts are disabled, and the transmit data register
empty (TDRE) bit in the SCI status register must be polled to determine
whether the transmit data register is empty. If both TIE and TDRE are
set, the SCI requests an SCI transmit data interrupt from the interrupt
controller. Either a hardware RESET signal or a software RESET
instruction clears TIE.
11
RIE
0
SCI Receive Interrupt Enable
Enables/disables the SCI receive data interrupt. If RIE is cleared, the
receive data interrupt is disabled, and the RDRF bit in the SCI status
register must be polled to determine whether the receive data register is
full. If both RIE and RDRF are set, the SCI requests an SCI receive
data interrupt from the interrupt controller. Receive interrupts with
exception have higher priority than normal receive data interrupts.
Therefore, if an exception occurs (that is, if PE, FE, or OR are set) and
REIE is set, the SCI requests an SCI receive data with exception
interrupt from the interrupt controller. Either a hardware RESET signal
or a software RESET instruction clears RIE.
10
ILIE
0
Idle Line Interrupt Enable
When ILIE is set, the SCI interrupt occurs when IDLE (SCI status
register bit 3) is set. When ILIE is cleared, the IDLE interrupt is disabled.
Either a hardware RESET signal or a software RESET instruction
clears ILIE. An internal flag, the shift register idle interrupt (SRIINT) flag,
is the interrupt request to the interrupt controller. SRIINT is not directly
accessible to the user. When a valid start bit is received, an idle
interrupt is generated if both IDLE and ILIE are set. The idle interrupt
acknowledge from the interrupt controller clears this interrupt request.
The idle interrupt is not asserted again until at least one character has
been received. The results are as follows:
■ The IDLE bit shows the real status of the receive line at all times.
■ An idle interrupt is generated once for each idle state, no matter
how long the idle state lasts.
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SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
9
TE
0
Transmitter Enable
When TE is set, the transmitter is enabled. When TE is cleared, the
transmitter completes transmission of data in the SCI transmit data shift
register, and then the serial output is forced high (that is, idle). Data
present in the SCI transmit data register (STX) is not transmitted. STX
can be written and TDRE cleared, but the data is not transferred into the
shift register. TE does not inhibit TDRE or transmit interrupts. Either a
hardware RESET signal or a software RESET instruction clears TE.
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Setting TE causes the transmitter to send a preamble of 10 or 11
consecutive ones (depending on WDS), giving you a convenient way to
ensure that the line goes idle before a new message starts. To force
this separation of messages by the minimum idle line time, we
recommend the following sequence:
1. Write the last byte of the first message to STX.
2.
Wait for TDRE to go high, indicating the last byte has been
transferred to the transmit shift register.
3.
Clear TE and set TE to queue an idle line preamble to follow
immediately the transmission of the last character of the
message (including the stop bit).
4.
Write the first byte of the second message to STX.
In this sequence, if the first byte of the second message is not
transferred to STX prior to the finish of the preamble transmission, the
transmit data line remains idle until STX is finally written.
8-14
8
RE
0
Receiver Enable
When RE is set, the receiver is enabled. When RE is cleared, the
receiver is disabled, and data transfer from the receive shift register to
the receive data register (SRX) is inhibited. If RE is cleared while a
character is being received, the reception of the character completes
before the receiver is disabled. RE does not inhibit RDRF or receive
interrupts. Either a hardware RESET signal or a software RESET
instruction clears RE.
7
WOMS
0
Wired-OR Mode Select
When WOMS is set, the SCI TXD driver is programmed to function as
an open-drain output and can be wired together with other TXD signals
in an appropriate bus configuration, such as a master-slave multidrop
configuration. An external pullup resistor is required on the bus. When
WOMS is cleared, the TXD signal uses an active internal pullup. Either
a hardware RESET signal or a software RESET instruction clears
WOMS.
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SCI Programming Model
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Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
6
RWU
0
Receiver Wakeup Enable
When RWU is set and the SCI is in Asynchronous mode, the wakeup
function is enabled; i. e., the SCI is asleep and can be awakened by the
event defined by the WAKE bit. In Sleep state, all interrupts and all
receive flags except IDLE are disabled. When the receiver wakes up,
RWU is cleared by the wakeup hardware. You can also clear the RWU
bit to wake up the receiver. You can use RWU to ignore messages that
are for other devices on a multidrop serial network. Wakeup on idle line
(i. e., WAKE is cleared) or wakeup on address bit (i. e., WAKE is set)
must be chosen. When WAKE is cleared and RWU is set, the receiver
does not respond to data on the data line until an idle line is detected.
When WAKE is set and RWU is set, the receiver does not respond to
data on the data line until a data frame with Bit 9 set is detected.
When the receiver wakes up, the RWU bit is cleared, and the first frame
of data is received. If interrupts are enabled, the CPU is interrupted and
the interrupt routine reads the message header to determine whether
the message is intended for this DSP. If the message is for this DSP,
the message is received, and RWU is set to wait for the next message.
If the message is not for this DSP, the DSP immediately sets RWU.
Setting RWU causes the DSP to ignore the remainder of the message
and wait for the next message. Either a hardware RESET signal or a
software RESET instruction clears RWU. RWU is ignored in
Synchronous mode.
5
WAKE
0
Wakeup Mode Select
When WAKE is cleared, the wakeup on Idle Line mode is selected. In
the wakeup on idle line mode, the SCI receiver is re-enabled by an idle
string of at least 10 or 11 (depending on WDS mode) consecutive ones.
The transmitter’s software must provide this idle string between
consecutive messages. The idle string cannot occur within a valid
message because each word frame there contains a start bit that is 0.
When WAKE is set, the wakeup on address bit mode is selected. In the
wakeup on address bit mode, the SCI receiver is re-enabled when the
last (eighth or ninth) data bit received in a character (frame) is 1. The
ninth data bit is the address bit (R8) in the 11-bit multidrop mode; the
eighth data bit is the address bit in the 10-bit asynchronous and 11-bit
asynchronous with parity modes. Thus, the received character is an
address that has to be processed by all sleeping processors—that is,
each processor has to compare the received character with its own
address and decide whether to receive or ignore all following
characters.
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SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit Name
Reset Value
Description
4
SBK
0
Send Break
A break is an all-zero word frame—a start bit 0, characters of all zeros
(including any parity), and a stop bit 0 (that is, ten or eleven zeros,
depending on the mode selected). If SBK is set and then cleared, the
transmitter finishes transmitting the current frame, sends 10 or 11 0s,
and reverts to idle or sending data. If SBK remains set, the transmitter
continually sends whole frames of 0s (10 or 11 bits with no stop bit). At
the end of the break code, the transmitter sends at least one high (set)
bit before transmitting any data to guarantee recognition of a valid start
bit. Break can signal an unusual condition, message, and so on, by
forcing a frame error; the frame error is caused by a missing stop bit.
3
SSFTD
0
SCI Shift Direction
Determines the order in which the SCI data shift registers shift data in or
out: MSB first when set, LSB first when cleared. The parity and data
type bits do not change their position in the frame, and they remain
adjacent to the stop bit.
2–0
WDS[2 – 0]
0
Word Select
Select the format of transmitted and received data. Asynchronous
modes are compatible with most UART-type serial devices, and they
support standard RS232C communication links. Multidrop
Asynchronous mode is compatible with the MC68681 DUART, the
M68HC11 SCI interface, and the Intel 8051 serial interface.
Synchronous data mode is essentially a high-speed shift register for I/O
expansion and stream-mode channel interfaces. You can synchronize
data by using a gated transmit and receive clock compatible with the
Intel 8051 serial interface mode 0. When odd parity is selected, the
transmitter counts the number of ones in the data word. If the total is not
an odd number, the parity bit is set, thus producing an odd number. If
the receiver counts an even number of ones, an error in transmission
has occurred. When even parity is selected, an even number must
result from the calculation performed at both ends of the line, or an error
in transmission has occurred.
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Bit Number
8-16
WDS2
WDS1
WDS0
Mode
Word Formats
0
0
0
0
8-Bit Synchronous Data (shift
register mode)
0
0
1
1
Reserved
0
1
0
2
10-Bit Asynchronous (1 start, 8 data,
1 stop)
1
1
1
3
Reserved
1
0
0
4
11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1
0
1
5
11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
1
1
0
6
11-Bit Multidrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
0
1
1
7
Reserved
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SCI Programming Model
8.6.2 SCI Status Register (SSR)
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The SSR is a 24-bit read-only register that indicates the status of the SCI.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R8
FE
PE
OR
IDLE
RDRF
TDRE
TRNE
Figure 8-4. SCI Status Register
Table 8-3. SCI Status Register (SSR) Bit Definitions
Bit Number
Bit Name
23 – 8
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
7
R8
0
Received Bit 8
In 11-bit Asynchronous Multidrop mode, the R8 bit indicates whether
the received byte is an address or data. R8 is set for addresses and is
cleared for data. R8 is not affected by reads of the SRX or SCI status
register. A hardware RESET signal, a software RESET instruction, an
SCI individual reset, or a STOP instruction clears R8.
6
FE
0
Framing Error Flag
In Asynchronous mode, FE is set when no stop bit is detected in the
data string received. FE and RDRE are set simultaneously when the
received word is transferred to the SRX. However, the FE flag inhibits
further transfer of data into the SRX until it is cleared. FE is cleared
when the SCI status register is read followed by a read of the SRX. A
hardware RESET signal, a software RESET instruction, an SCI
individual reset, or a STOP instruction clears FE. In 8-bit Synchronous
mode, FE is always cleared. If the byte received causes both framing
and overrun errors, the SCI receiver recognizes only the overrun error.
5
PE
0
Parity Error
In 11-bit Asynchronous modes, PE is set when an incorrect parity bit is
detected in the received character. PE and RDRF are set
simultaneously when the received word is transferred to the SRX. If PE
is set, further data transfer into the SRX is not inhibited. PE is cleared
when the SCI status register is read, followed by a read of SRX. A
hardware RESET signal, a software RESET instruction, an SCI
individual reset, or a STOP instruction also clears PE. In 10-bit
Asynchronous mode, 11-bit multidrop mode, and 8-bit Synchronous
mode, the PE bit is always cleared since there is no parity bit in these
modes. If the byte received causes both parity and overrun errors, the
SCI receiver recognizes only the overrun error.
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SCI Programming Model
Table 8-3. SCI Status Register (SSR) Bit Definitions (Continued)
Bit Name
Reset Value
Description
4
OR
0
Overrun Error Flag
Set when a byte is ready to be transferred from the receive shift register
to the receive data register (SRX) that is already full (RDRF = 1). The
receive shift register data is not transferred to the SRX. The OR flag
indicates that character(s) in the received data stream may have been
lost. The only valid data is located in the SRX. OR is cleared when the
SCI status register is read, followed by a read of SRX. The OR bit
clears the FE and PE bits; that is, overrun error has higher priority than
FE or PE. A hardware RESET signal, a software RESET instruction, an
SCI individual reset, or a STOP instruction clears OR.
3
IDLE
0
Idle Line Flag
Set when 10 (or 11) consecutive ones are received. IDLE is cleared by
a start-bit detection. The IDLE status bit represents the status of the
receive line. The transition of IDLE from 0 to 1 can cause an IDLE
interrupt (ILIE).
2
RDRF
0
Receive Data Register Full
Set when a valid character is transferred to the SCI receive data
register from the SCI receive shift register (regardless of the error bits
condition). RDRF is cleared when the SCI receive data register is read.
1
TDRE
1
Transmit Data Register Empty
Set when the SCI transmit data register is empty. When TDRE is set,
new data can be written to one of the SCI transmit data registers (STX)
or the transmit data address register (STXA). TDRE is cleared when the
SCI transmit data register is written. Either a hardware RESET signal, a
software RESET instruction, an SCI individual reset, or a STOP
instruction sets TDRE.
Freescale Semiconductor, Inc...
Bit Number
In Synchronous mode, when the internal SCI clock is in use, there is a
delay of up to 5.5 serial clock cycles between the time that STX is
written until TDRE is set, indicating the data has been transferred from
the STX to the transmit shift register. There is a delay of 2 to 4 serial
clock cycles between writing STX and loading the transmit shift register;
in addition, TDRE is set in the middle of transmitting the second bit.
When using an external serial transmit clock, if the clock stops, the SCI
transmitter stops. TDRE is not set until the middle of the second bit
transmitted after the external clock starts. Gating the external clock off
after the first bit has been transmitted delays TDRE indefinitely.
In Asynchronous mode, the TDRE flag is not set immediately after a
word is transferred from the STX or STXA to the transmit shift register
nor when the word first begins to be shifted out. TDRE is set 2 cycles (of
the 16 ™ clock) after the start bit; that is, 2 (16 ™ clock) cycles into the
transmission time of the first data bit.
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Table 8-3. SCI Status Register (SSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
0
TRNE
1
Transmitter Empty
This flag bit is set when both the transmit shift register and transmit data
register (STX) are empty, indicating that there is no data in the
transmitter. When TRNE is set, data written to one of the three STX
locations or to the transmit data address register (STXA) is transferred
to the transmit shift register and is the first data transmitted. TRNE is
cleared when a write into STX or STXA clears TDRE or when an idle,
preamble, or break is transmitted. When set, TRNE indicates that the
transmitter is empty; therefore, the data written to STX or STXA is
transmitted next. That is, there is no word in the transmit shift register
being transmitted. This procedure is useful when initiating the transfer
of a message (that is, a string of characters).
8.6.3 SCI Clock Control Register (SCCR)
The SCCR is a 24-bit read/write register that controls the selection of clock modes and
baud rates for the transmit and receive sections of the SCI interface. The SCCR is cleared
by a hardware RESET signal.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TCM
RCM
SCP
COD
CD11
CD10
CD9
CD8
7
6
5
4
3
2
1
0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
Reserved. Read as 0. Write with 0 for future compatibility.
Figure 8-5. SCI Clock Control Register (SCCR)
The basic features of the clock generator, as shown in Figure 8-6 and Figure 8-7, follow:
■
■
■
The SCI logic always uses a 16 ™ internal clock in Asynchronous mode and always
uses a 2 ™ internal clock in Synchronous mode. The maximum internal clock
available to the SCI peripheral block is the oscillator frequency divided by 4. These
maximum rates are the same for internally or externally supplied clocks.
The 16 ™ clock is necessary for Asynchronous modes to synchronize the SCI to the
incoming data (as shown in Figure 8-6).
For Asynchronous modes, you must provide a 16 ™ clock if you want to use an
external baud rate generator (that is, SCLK input).
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■
■
When SCKP is cleared, the transmitted data on the TXD signal changes on the
negative edge of the 1 ™ serial clock and is stable on the positive edge. When SCKP
is set, the data changes on the positive edge and is stable on the negative edge.
■
The received data on the RXD signal is sampled on the positive edge (if SCKP = 0)
or on the negative edge (if SCKP = 1) of the 1 ™ serial clock.
■
For Asynchronous mode, the output clock is continuous.
■
Freescale Semiconductor, Inc...
For Asynchronous modes, you can select either 1 ™ or 16 ™ for the output clock
when using internal TX and RX clocks (TCM = 0 and RCM = 0).
For Synchronous mode, a 1 ™ clock is used for the output or input baud rate. The
maximum 1 ™ clock is the crystal frequency divided by 8.
■
For Synchronous mode, the clock is gated.
■
For Synchronous mode, the transmitter and receiver are synchronous with each
other.
Select 8-or 9-bit Words
0
Idle Line
1
2
3
4
5
6
7
8
RX, TX Data
(SSFTD = 0)
Start
Stop
Start
x1 Clock
x16 Clock
(SCKP = 0)
Figure 8-6. 16 x Serial Clock
The SCI clock determines the data transmission rate and can also establish a periodic
interrupt that can act as an event timer or be used in any other timing function. Bits CD11–
CD0, SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1
when the periodic time-out occurs, the SCI timer interrupt is recognized and pending. The
SCI timer interrupt is automatically cleared when the interrupt is serviced. This interrupt
occurs every time the periodic timer times out.
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SCI Programming Model
Table 8-4. SCI Clock Control Register (SCCR) Bit Definitions
Bit Number
Bit Name
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23 – 16
Reset Value
Description
0
Reserved. Set to 0 for future compatibility.
15
TCM
0
Transmit Clock Source
Selects whether an internal or external clock is used for the transmitter. If
TCM is cleared, the internal clock is used. If TCM is set, the external clock
(from the SCLK signal) is used.
14
RCM
0
Receive Clock Mode Source
Selects whether an internal or external clock is used for the receiver. If RCM
is cleared, the internal clock is used. If RCM is set, the external clock (from
the SCLK signal) is used.
TCM
RCM
TX
Clock
RX
Clock
SCLK
Signal
Mode
0
0
Internal Internal
0
1
Internal External Input
Asynchronous only
1
0
External Internal Input
Asynchronous only
1
1
External External Input
Synchronous/asynchronous
Output Synchronous/asynchronous
13
SCP
0
Clock Prescaler
Selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler
for the clock divider. The output of the prescaler is further divided by 2 to
form the SCI clock.
12
COD
0
Clock Out Divider
The clock output divider is controlled by COD and the SCI mode. If the SCI
mode is synchronous, the output divider is fixed at divide by 2. If the SCI
mode is asynchronous, either:
■ If COD is cleared and SCLK is an output (that is, TCM and RCM are
both cleared), then the SCI clock is divided by 16 before being output
to the SCLK signal. Thus, the SCLK output is a 1 clock.
■ If COD is set and SCLK is an output, the SCI clock is fed directly out
to the SCLK signal. Thus, the SCLK output is a 16 baud clock.
™
™
11 – 0
Motorola
CD[11 – 0]
0
Clock Divider
Specifies the divide ratio of the prescale divider in the SCI clock generator. A
divide ratio from 1 to 4096 (CD[11 – 0] = $000 to $FFF) can be selected.
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SCI Programming Model
Fcore
Divide
By 2
12-bit Counter
Divide
By 2
Prescaler:
Divide by
1 or 8
CD[11 – 0]
SCP
Freescale Semiconductor, Inc...
Internal Clock
Divide
by 16
SCI Core Logic
Uses Divide by 16 for
Asynchronous
Uses Divide by 2 for
Synchronous
STIR
Timer
Interrupt
(STMINT)
COD
If Asynchronous
Divide by 1 or 16
If Synchronous
Divide By 2
Fcore
BPS = 64 x (7(SCP) + 1) x CD + 1)
where: SCP = 0 or 1
CD = $000 to $FFF
SCKP
SCKP = 0 +
SCKP = 1 -
TO SCLK
Figure 8-7. SCI Baud Rate Generator
8.6.4 SCI Data Registers
The SCI data registers are divided into two groups: receive and transmit, as shown in
Figure 8-8. There are two receive registers: a receive data register (SRX) and a
serial-to-parallel receive shift register. There are also two transmit registers: a transmit
data register (called either STX or STXA) and a parallel-to-serial transmit shift register.
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SCI Programming Model
23
16 15
8 7
0
SCI Receive Data Register High (Read Only)
SRX
SRX
SCI Receive Data Register Middle (Read Only)
SRX
SCI Receive Data Register Low (Read Only)
SCI Receive Data Shift Register
RXD
Note: SRX is the same register decoded at three different addresses.
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(a) Receive Data Register
23
16 15
8 7
0
STX
SCI Transmit Data Register High (Write Only)
STX
SCI Transmit Data Register Middle (Write Only)
STX
SCI Transmit Data Register Low (Write Only)
SCI Transmit Data Shift Register
23
16 15
TXD
8 7
0
STXA
SCI Transmit Data Address Register (Write Only)
Note: Bytes are masked on the fly.
1. STX is the same register decoded at four different addresses.
(b) Transmit Data Register
Figure 8-8. SCI Programming Model - Data Registers
8.6.4.1 SCI Receive Register (SRX)
Data bits received on the RXD signal are shifted into the SCI receive shift register. When
a complete word is received, the data portion of the word is transferred to the byte-wide
SRX. This process converts serial data to parallel data and provides double buffering.
Double buffering promotes flexibility and increased throughput since the programmer can
save (and process) the previous word while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is
read, the contents of the SRX are placed in the lower byte of the data bus and the
remaining bits on the data bus are read as zeros. Similarly, when SRXM is read, the
contents of SRX are placed into the middle byte of the bus, and when SRXH is read, the
contents of SRX are placed into the high byte with the remaining bits are read as 0s. This
way of mapping SRX efficiently packs three bytes into one 24-bit word by ORing three
data bytes read from the three addresses.
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The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial
word. The SCR receive clock mode (RCM) defines the clock source.
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In Synchronous mode, the start bit, the eight data bits, the address/data indicator bit or the
parity bit, and the stop bit are received, respectively. Data bits are sent LSB first if SSFTD
is cleared, and MSB first if SSFTD is set. In Synchronous mode, a gated clock provides
synchronization. In either synchronous or Asynchronous mode, when a complete word is
clocked in, the contents of the shift register can be transferred to the SRX and the flags;
RDRF, FE, PE, and OR are changed appropriately. Because the operation of the receive
shift register is transparent to the DSP, the contents of this register are not directly
accessible to the programmer.
8.6.4.2 SCI Transmit Register (STX)
The transmit data register is a one-byte-wide register mapped into four addresses as
STXL, STXM, STXH, and STXA. In Asynchronous mode, when data is to be transmitted,
STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it
easy for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA
should be written in 11-bit asynchronous multidrop mode when the data is an address and
the programmer wants to set the ninth bit (the address bit). When STXA is written, the
data from the low byte on the data bus is stored in it. The address data bit is cleared in
11-bit asynchronous multidrop mode when any of STXL, STXM, or STXH is written.
When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically,
but not immediately, after the last bit from the previous word is shifted out; that is, the
transmit shift register is empty. Like the receiver, the transmitter is double-buffered.
However, a delay of two to four serial clock cycles occurs between when the data is
transferred from either STX or STXA to the transmit shift register and when the first bit
appears on the TXD signal. (A serial clock cycle is the time required to transmit one data
bit.)
The transmit shift register is not directly addressable, and there is no dedicated flag for this
register. Because of this fact and the two- to four-cycle delay, two bytes cannot be written
consecutively to STX or STXA without polling, because the second byte might overwrite
the first byte. Thus, you should always poll the TDRE flag prior to writing STX or STXA
to prevent overruns unless transmit interrupts are enabled. Either STX or STXA is usually
written as part of the interrupt service routine. An interrupt is generated only if TDRE is
set. The transmit shift register is indirectly visible via the SSR[TRNE] bit.
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GPIO Signals and Registers
In Synchronous mode, data is synchronized with the transmit clock. That clock can have
either an internal or external source, as defined by the TCM bit in the SCCR. The length
and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in
the SCR. In Asynchronous mode, the start bit, the eight data bits (with the LSB first if
SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit,
and the stop bit are transmitted in that order.
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The data to be transmitted can be written to any one of the three STX addresses. If SCKP
is set and SSHTD is set, SCI Synchronous mode is equivalent to the SSI operation in 8-bit
data on-demand mode.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by this operation are updated. If you read any of
those status bits within the next two cycles, the bit does not reflect its current
status. For details see the DSP56300 Family Manual.
8.7 GPIO Signals and Registers
Three registers control the GPIO functionality of port SCI: Port E control register (PCRE),
Port E direction register (PRRE) and Port E data register (PDRE).
8.7.1 Port E Control Register (PCRE)
The read/write PCRE controls the functionality of SCI GPIO signals. Each of PC[2 – 0]
bits controls the functionality of the corresponding port signal. When a PC[i] bit is set, the
corresponding port signal is configured as an SCI signal. When a PC[i] bit is cleared, the
corresponding port signal is configured as a GPIO signal. A hardware RESET signal or a
software RESET instruction clears all PCR bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PC2 PC1 PC0
Port Control Bits: 1 = SCI
0 = GPIO
Reserved. Read as 0. Write with 0 for future compatibility.
Figure 8-9. Port E Control Register (PCRE)
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GPIO Signals and Registers
8.7.2 Port E Direction Register (PRRE)
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The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is
configured as GPIO, PDC[i] controls the port signal direction. When PDC[i] is set, the
GPIO port signal[i] is configured as output. When PDC[i] is cleared, the GPIO port
signal[i] is configured as input. A hardware RESET signal or a software RESET instruction
clears all PRR bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PDC2 PDC1 PDC0
Direction Control Bits: 1 = Output
0 = Input
Reserved. Read as 0. Write with 0 for future compatibility
Figure 8-10. Port E Direction Register (PRRE)
Table 8-5 shows the port signal configurations.
.
Table 8-5. Port Control Register and Port Direction Register Bits
PC[i]
PDC[i]
Port Signal[i] Function
1
1 or 0
SCI
0
0
GPIO input
0
1
GPIO output
8.7.3 Port E Data Register (PDRE)
The read/write PDRE reads or writes data to or from SCI GPIO signals. Bits PD[2 – 0]
read or write data to or from the corresponding port signals if they are configured as
GPIO. If a port signal [i] is configured as a GPIO input, then the corresponding PD[i] bit
reflects the value of this signal. If a port signal [i] is configured as a GPIO output, then the
value of the corresponding PD[i] bit is reflected on this signal. A hardware RESET signal
or a software RESET instruction clears all PDRE bits.
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GPIO Signals and Registers
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PD2 PD1 PD0
Reserved. Read as 0. Write with 0 for future compatibility
Freescale Semiconductor, Inc...
Figure 8-11. Port E Data Register (PDRE)
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GPIO Signals and Registers
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Chapter 9
Triple Timer Module
The timers in the DSP56311 internal triple timer module act as timed pulse generators or
as pulse-width modulators. Each timer has a single signal that can function as a GPIO
signal or as a timer signal. Each timer can also function as an event counter to capture an
event or to measure the width or period of a signal.
9.1 Overview
The timer module contains a common 21-bit prescalar and three independent and identical
general-purpose 24-bit timer/event counters, each with its own register set. Each timer has
the following capabilities:
■
uses internal or external clocking
■
interrupts the DSP56311 after a specified number of events (clocks) or signals an
external device after counting internal events
■
triggers DMA transfers after a specified number of events (clocks) occurs
■
connects to the external world through one bidirectional signal, designated
TIO[0– 2] for timers 0–2.
When the TIO signal is configured as input, the timer functions as an external event
counter or measures external pulse width/signal period. When the TIO signal is configured
as an output, the timer functions as a timer, a watchdog timer, or a pulse-width modulator.
When the timer is not using the TIO signal, TIO can be used as a GPIO signal (also called
TIO[0 – 2]).
Figure 9-1 shows a block diagram of the triple timer module. Notice the 24-bit timer
Prescalar Load Register (TPLR) and the 24-bit Timer Prescalar Count Register (TPCR).
Each of the three timers can use the prescalar clock as its clock source. The timer block
diagram in Figure 9-2 shows the structure of a timer module. The DSP56311 treats each
timer as a memory-mapped peripheral with four registers occupying four 24-bit words in
the X data memory space. The three timers are identical in structure and function. Either
standard polled or interrupt programming techniques can be used to service the timers. A
single, generic timer is discussed in this chapter.
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Operation
The timer includes a 24-bit counter, a 24-bit read/write Timer Control and Status Register
(TCSR), a 24-bit read-only Timer Count Register (TCR), a 24-bit write-only Timer Load
Register (TLR), a 24-bit read/write Timer Compare Register (TCPR), and logic for clock
selection and interrupt/DMA trigger generation.
GDB
24
24
24
TPLR
TPCR
24
Freescale Semiconductor, Inc...
Timer Prescalar
Load Register
Timer Prescalar
Count Register
Timer 0
Timer 1
24-bit Counter
Timer 2
CLK/2
TIO0 TIO1 TIO2
Figure 9-1. Triple Timer Module Block Diagram
The timer mode is controlled by the TC[3 – 0] bits of the Timer Control/Status Register
(TCSR). For a listing of the timer modes and descriptions of their operations, see Section
9.3, "Operating Modes," on page 9-4.
9.2 Operation
This section discusses timer basics: reset state, initialization, and exceptions.
9.2.1 Timer After Reset
A hardware RESET signal or software RESET instruction clears the Timer Control
Register, thus configuring the timer as GPIO. A timer is active only if TCSR[TE] is set.
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Operation
GDB
24
24
24
TCSR
Control/Status
Register
Load
Register
Compare
Register
24
24
2
TIO
TCPR
Count
Register
24
Timer Control
Logic
24
TCR
TLR
9
Freescale Semiconductor, Inc...
24
24
Counter
CLK/2 Prescalar CLK
=
Timer interrupt/DMA request
Figure 9-2. Timer Module Block Diagram
9.2.2 Timer Initialization
To initialize a timer, do the following:
1. Ensure that the timer is not active either by sending a reset or clearing the
TCSR[TE] bit.
2. Configure the control register (TCSR) to set the timer operating mode. Set the
interrupt enable bits as needed for the application.
3. Configure other registers: Prescalar Load Register (TPLR), Load register (TLR),
and Compare register (TCPR) as needed for the application.
4. Enable the timer by setting the TCSR[TE] bit.
9.2.3 Timer Exceptions
Each timer can generate two different exceptions:
■
Timer Overflow (highest priority) — Occurs when the timer counter reaches the
overflow value. This exception sets the TOF bit. TOF is cleared when a value of
one is written to it or when the timer overflow exception is serviced.
■
Timer Compare (lowest priority) — Occurs when the timer counter reaches the
value given in the Timer Compare Register (TCPR) for all modes except
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Operating Modes
measurement modes. In measurement modes, 4 – 6, a compare exception occurs
when the appropriate transition occurs on the TIO signal. The Compare exception
sets the TCF bit. TCF is cleared when a value of one is written to it or when the
timer compare interrupt is serviced.
To configure a timer exception, perform the following steps. The example at the right of
each step shows the register settings for configuring a Timer 0 compare interrupt. The
order of the steps is optional except that the timer should not be enabled (step 2e) until all
other exception configuration is complete:
Freescale Semiconductor, Inc...
1. Configure the interrupt service routine (ISR):
a. Load vector base address register
VBA (b23 – 8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch
to subroutine (long interrupt).
p:TIM0C
2. Configure the interrupt trigger:
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (TOL[1 – 0])
b. Enable a specific peripheral interrupt.
TCSR0 (TCIE)
c. Unmask interrupts at the global level.
SR (I[1 – 0])
d. Configure a peripheral interrupt-generating function.
TCSR0 (TC[7 – 4])
e. Enable peripheral and associated signals.
TCSR0 (TE)
9.3 Operating Modes
Each timer has operating modes that meet a variety of system requirements, as follows:
■
Timer
— GPIO, mode 0: Internal timer interrupt generated by the internal clock
— Pulse, mode 1: External timer pulse generated by the internal clock
— Toggle, mode 2: Output timing signal toggled by the internal clock
— Event counter, mode 3: Internal timer interrupt generated by an external clock
9-4
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Operating Modes
■
Measurement
— Input width, mode 4: Input pulse width measurement
— Input pulse, mode 5: Input signal period measurement
— Capture, mode 6: Capture external signal
■
PWM, mode 7: Pulse width modulation
■
Watchdog
— Pulse, mode 9: Output pulse, internal clock
Freescale Semiconductor, Inc...
— Toggle, mode 10: Output toggle, internal clock
Note:
To ensure proper operation, the TCSR TC[3 – 0] bits should be changed only
when the timer is disabled (that is, when TCSR[TE] is cleared).
9.3.1 Triple Timer Modes
For all triple timer modes, the following points are true:
■
The TCSR[TE] bit is set to clear the counter and enable the timer. Clearing
TCSR[TE] disables the timer.
■
The value to which the timer is to count is loaded into the TCPR. (This is true for
all modes except the measurement modes (modes 4 through 6).
■
The counter is loaded with the TLR value on the first clock.
■
If the counter overflows, TCSR[TOF] is set, and if TCSR[TOIE] is set, an overflow
interrupt is generated.
■
You can read the counter contents at any time from the Timer Count Register
(TCR).
9.3.1.1 Timer GPIO (Mode 0)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
0
0
0
GPIO
Timer
GPIO
Internal
In Mode 0, the timer generates an internal interrupt when a counter value is reached, if the
timer compare interrupt is enabled (see Figure 9-3 and Figure 9-4). When the counter
equals the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is reloaded with the TLR
value at the next timer clock and the count is resumed. If TCSR[TRM] is cleared, the
counter continues to increment on each timer clock signal. This process repeats until the
timer is disabled.
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Operating Modes
Mode 0 (internal clock, no timer output): TRM = 1
N = write preload
M = write compare
first event
last event
TE
Clock
(CLK/2 or prescale CLK)
Freescale Semiconductor, Inc...
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
Figure 9-3. Timer Mode (TRM = 1)
Mode 0 (internal clock, no timer output): TRM = 0
N = write preload
M = write compare
first event
last event
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-4. Timer Mode (TRM = 0)
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Operating Modes
9.3.1.2 Timer Pulse (Mode 1)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
0
1
1
Timer Pulse
Timer
Output
Internal
In Mode 1, the timer generates an external pulse on its TIO signal when the timer count
reaches a pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit.
When the counter matches the TCPR value, TCSR[TCF] is set and a compare interrupt is
generated if the TCSR[TCIE] bit is set. The polarity of the TIO signal is inverted for one
timer clock period. If TCSR[TRM] is set, the counter is loaded with the TLR value on the
next timer clock and the count is resumed. If TCSR[TRM] is cleared, the counter
continues to increment on each timer clock. This process repeats until TCSR[TE] is
cleared (disabling the timer).
The TLR value in the TCPR sets the delay between starting the timer and generating the
output pulse. To generate successive output pulses with a delay of X clock cycles between
signals, set the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until
the timer is disabled.
Mode 1 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
timer clock
period
TIO pin (INV = 1)
Figure 9-5. Pulse Mode (TRM = 1)
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Operating Modes
Mode 1 (internal clock): TRM = 0
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
N
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TLR
0
Counter (TCR)
N
N+1
M
M+1
0
1
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
timer clock
period
TIO pin (INV = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-6. Pulse Mode (TRM = 0)
9.3.1.3 Timer Toggle (Mode 2)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
1
0
2
Toggle
Timer
Output
Internal
In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is
enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter
value matches the value in the TCPR, the polarity of the TIO output signal is inverted.
TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If
the TCSR[TRM] bit is set, the counter is loaded with the value of the TLR when the next
timer clock is received, and the count resumes. If the TRM bit is cleared, the counter
continues to increment on each timer clock. This process repeats until the timer is cleared
(disabling the timer). The TCPR[TLR] value sets the delay between starting the timer and
toggling the TIO signal. To generate output signals with a delay of X clock cycles between
toggles, set the TLR value to X/2, and set the TCSR[TRM] bit. This process repeats until
the timer is disabled (that is, TCSR[TE] is cleared).
9-8
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Operating Modes
Mode 2 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
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TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
M - N clock
periods
TIO pin (INV = 1)
Figure 9-7. Toggle Mode, TRM = 1
Mode 2 (internal clock): TRM = 0
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
First toggle = M - N clock periods
Second and later toggles = 2 24 clock periods
TIO pin (INV = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-8. Toggle Mode, TRM = 0
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Operating Modes
9.3.1.4 Timer Event Counter (Mode 3)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
1
1
3
Event Counter
Timer
Input
External
In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits
are set) when the timer counts a preset number of events. The timer clock signal can be
taken from either the TIO input signal or the prescalar clock output. If an external clock is
used, it must be internally synchronized to the internal clock, and its frequency must be
less than the DSP56311 internal operating frequency divided by 4. The value of the
TCSR[INV] bit determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0)
transitions increment the counter. If the INV bit is set, high-to-low transitions increment
the counter. If the INV bit is cleared, low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, TCSR[TCF] is set and a
compare interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set,
the counter is loaded with the value of the TLR when the next timer clock is received, and
the count is resumed. If the TCSR[TRM] bit is cleared, the counter continues to increment
on each timer clock. This process repeats until the timer is disabled.
Mode 3 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
if clock source
is from TIO pin,
TIO < CPUCLK + 4
Clock
(TIO pin or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
interrupts every
M - N clock
periods
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
Figure 9-9. Event Counter Mode, TRM = 1
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Operating Modes
Mode 3 (internal clock): TRM = 0
N = write preload
M = write compare
if clock source is from TIO pin,
TIO < CPUCLK + 4
first event
TE
Clock
(TIO pin or prescale CLK)
Freescale Semiconductor, Inc...
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TCIE = 1)
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
Figure 9-10. Event Counter Mode, TRM = 0
9.3.2 Signal Measurement Modes
The following signal measurement and pulse width modulation modes are provided:
■
Measurement input width (Mode 4)
■
Measurement input period (Mode 5)
■
Measurement capture (Mode 6)
■
Pulse width modulation mode (Mode 7)
The external signal synchronizes with the internal clock that increments the counter. This
synchronization process can cause the number of clocks measured for the selected signal
value to vary from the actual signal value by plus or minus one counter clock cycle.
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Operating Modes
9.3.2.1 Measurement Input Width (Mode 4)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
0
0
4
Input width
Measurement
Input
Internal
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an
input signal. After the first appropriate transition (as determined by the TCSR[INV] bit)
occurs on the TIO input signal, the counter is loaded with the TLR value. If TCSR[INV] is
set, the timer starts on the first high-to-low (1 to 0) signal transition on the TIO signal. If
the INV bit is cleared, the timer starts on the first low-to-high (that is, 0 to 1) transition on
the TIO signal. When the first transition opposite in polarity to the INV bit setting occurs
on the TIO signal, the counter stops. TCSR[TCF] is set and a compare interrupt is
generated if the TCSR[TCIE] bit is set. The value of the counter (which measures the
width of the TIO pulse) is loaded into the TCR, which can be read to determine the
external signal pulse width. If the TCSR[TRM] bit is set, the counter is loaded with the
TLR value on the first timer clock received following the next valid transition on the TIO
input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to
increment on each timer clock. This process repeats until the timer is disabled.
Mode 4 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
M
N+1
M
TCR
Next 0-to-1 edge
on TIO loads
counter and
process repeats
width being measured
TIO pin
Interrupt Service
reads TCR; width
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Figure 9-11. Pulse Width Measurement Mode, TRM = 1
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Operating Modes
Mode 4 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
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Counter
N
N+1
M
Next 0-to-1
N + 1edge
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1).
M
TCR
width being measured
TIO pin
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Interrupt Service
reads TCR for
accumulated width
of M - N clock periods.
Figure 9-12. Pulse Width Measurement Mode, TRM = 0
9.3.2.2 Measurement Input Period (Mode 5)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
0
1
5
Input period
Measurement
Input
Internal
In Mode 5, the timer counts the period between the reception of signal edges of the same
polarity across the TIO signal. The value of the INV bit determines whether the period is
measured between consecutive low-to-high (0 to 1) transitions of TIO or between
consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal
transitions are selected. If INV is cleared, low-to-high signal transitions are selected. After
the first appropriate transition occurs on the TIO input signal, the counter is loaded with
the TLR value. On the next signal transition of the same polarity that occurs on TIO,
TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. The
contents of the counter load into the TCR. The TCR then contains the value of the time
that elapsed between the two signal transitions on the TIO signal. After the second signal
transition, if the TCSR[TRM] bit is set, the TCSR[TE] bit is set to clear the counter and
enable the timer. The counter is repeatedly loaded and incremented until the timer is
disabled. If the TCSR[TRM] bit is cleared, the counter continues to increment until it
overflows.
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Operating Modes
Mode 5 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
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Counter
N
N+1
M
N
Counter continues
counting,
N +does
1
not stop
M
TCR
period being measured
TIO pin
Interrupt Service
reads TCR; period
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
loads TCR with count and the counter with N.
Figure 9-13. Period Measurement Mode, TRM = 1
Mode 5 (internal clock): TRM = 0
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
M+1
M
TCR
TIO pin
M
Counter continues
counting,
N +does
1
not stop. Overflow
may occur (TOF=1).
period being measured
Interrupt Service
reads TCR; period
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
loads TCR with count and the counter with N.
Figure 9-14. Period Measurement Mode, TRM = 0
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Operating Modes
9.3.2.3 Measurement Capture (Mode 6)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
1
0
6
Capture
Measurement
Input
Internal
In Mode 6, the timer counts the number of clocks that elapse between when the timer
starts and when an external signal is received. At the first appropriate transition of the
external clock detected on the TIO signal, TCSR[TCF] is set and, if the TCSR[TCIE] bit is
set, a compare interrupt is generated. The counter halts. The contents of the counter are
loaded into the TCR. The value of the TCR represents the delay between the setting of the
TCSR[TE] bit and the detection of the first clock edge signal on the TIO signal. The value
of the INV bit determines whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition
of the external clock signals the end of the timing period. If the INV bit is set, a
high-to-low transition signals the end of the timing period. If INV is cleared, a low-to-high
transition signals the end of the timing period.
Mode 6 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
N
Counter stops
counting;
N +overflow
1
may occur before
capture (TOF = 1)
M
TCR
TIO pin
M
delay being measured
TCF (Compare Interrupt if TCIE = 1)
Interrupt Service
reads TCR; delay
= M - N clock
periods
NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and stops the counter.
Figure 9-15. Capture Measurement Mode, TRM = 0
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Operating Modes
9.3.3 Pulse Width Modulation (PWM, Mode 7)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
1
1
7
Pulse width modulation
PWM
Output
Internal
Freescale Semiconductor, Inc...
In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals
the value in the TCPR, the TIO output signal is toggled and TCSR[TCF] is set. The
contents of the counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare
interrupt is generated. The counter continues to increment on each timer clock.
If counter overflow occurs, the TIO output signal is toggled, TCSR[TOF] is set, and an
overflow interrupt is generated if the TCSR[TOIE] bit is set. If the TCSR[TRM] bit is set,
the counter is loaded with the TLR value on the next timer clock and the count resumes. If
the TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock.
This process repeats until the timer is disabled.
When the TCSR[TE] bit is set and the counter starts, the TIO signal assumes the value of
INV. On each subsequent toggle of the TIO signal, the polarity of the TIO signal is
reversed. For example, if the INV bit is set, the TIO signal generates the following signal:
1010. If the INV bit is cleared, the TIO signal generates the following signal: 0101.
The value of the TLR determines the output period ($FFFFFF - TLR + 1). The timer
counter increments the initial TLR value and toggles the TIO signal when the counter
value exceeds $FFFFFF. The duty cycle of the TIO signal is determined by the value in
the TCPR. When the value in the TLR increments to a value equal to the value in the
TCPR, the TIO signal is toggled. The duty cycle is equal to ($FFFFFF – TCPR) divided
by ($FFFFFF - TLR + 1). For a 50 percent duty cycle, the value of TCPR is equal to
($FFFFFF + TLR + 1)/2.
Note:
9-16
The value in TCPR must be greater than the value in TLR.
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Operating Modes
Period = $FFFFFF - TLR + 1
Duty cycle = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
Mode 7 (internal clock): TRM = 1
N = write preload
M = write compare
first event
TE
Freescale Semiconductor, Inc...
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
M
M+1
0
N
N+1
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TCF (Overflow Interrupt if TDIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
Pulse width
Period
Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1
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Operating Modes
Period = $FFFFFF - TLR + 1
Duty cycle = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
Mode 7 (internal clock): TRM = 0
N = write preload
M = write compare
first event
TE
Freescale Semiconductor, Inc...
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
M
M+1
0
1
2
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TCF (Overflow Interrupt if TDIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
Pulse width
Period
NOTE: On overflow, TCR is loaded with the value of TLR.
Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0
9.3.4 Watchdog Modes
The following watchdog timer modes are provided:
■
Watchdog Pulse
■
Watchdog Toggle
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Operating Modes
9.3.4.1 Watchdog Pulse (Mode 9)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
1
0
0
1
9
Pulse
Watchdog
Output
Internal
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal
to the period of one timer clock. After the counter reaches the value in the TCPR, if the
TCSR[TRM] bit is set, the counter is loaded with the TLR value on the next timer clock
and the count resumes. Therefore TRM = 1 is not useful for watchdog functions. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each subsequent timer
clock. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). If the
counter overflows, a pulse is output on the TIO signal with a pulse width equal to the timer
clock period. If the INV bit is set, the pulse polarity is high (logical 1). If INV is cleared,
the pulse polarity is low (logical 0). The counter reloads when the TLR is written with a
new value while the TCSR[TE] bit is set. In Mode 9, internal logic preserves the TIO
value and direction for an additional 2.5 internal clock cycles after the hardware RESET
signal is asserted. This convention ensures that a valid RESET signal is generated when the
TIO signal resets the DSP56311.
Mode 9 (internal clock): TRM = 0
N = write preload
M = write compare
(Software does not reset watchdog timer; watchdog times out)
first event
TRM = 1 is not useful for watchdog function
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
N+1
M
M+1
0
1
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
TIO pin (INV = 0)
float
TIO pin (INV = 1)
low
pulse width
= timer
clock period
high
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Figure 9-18. Watchdog Pulse Mode
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Operating Modes
9.3.4.2 Watchdog Toggle (Mode 10)
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Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
1
0
1
0
10
Toggle
Watchdog
Output
Internal
In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set
to the value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is
set, and a compare interrupt is generated if the TCSR[TCIE] bit is also set. If the
TCSR[TRM] bit is set, the counter loads with the TLR value on the next timer clock and
the count resumes. Therefore, TRM = 1 is not useful for watchdog functions. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each subsequent timer
clock. When a counter overflow occurs, the polarity of the TIO output signal is inverted.
The counter is reloaded whenever the TLR is written with a new value while the
TCSR[TE] bit is set. This process repeats until the timer is disabled. In Mode 10, internal
logic preserves the TIO value and direction for an additional 2.5 internal clock cycles after
the hardware RESET signal is asserted. This convention ensures that a valid reset signal is
generated when the TIO signal resets the DSP56311.
Mode 10 (internal clock): TRM = 0
TRM = 1 is not useful for watchdog function
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
N+1
M
M+1
0
1
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
TIO pin (INV = 0)
float
low
high
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Figure 9-19. Watchdog Toggle Mode
9-20
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Triple Timer Module Programming Model
9.3.4.3 Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
9.3.5 Special Cases
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The following special cases apply during wait and stop state.
■
Timer behavior during wait — Timer clocks are active during the execution of the
WAIT instruction and timer activity is undisturbed. If a timer interrupt is generated,
the DSP56311 leaves the wait state and services the interrupt.
■
Timer behavior during stop — During execution of the STOP instruction, the timer
clocks are disabled, timer activity stops, and the TIO signals are disconnected. Any
external changes that happen to the TIO signals are ignored when the DSP56311 is
in stop state. To ensure correct operation, disable the timers before the DSP56311
is placed in stop state.
9.3.6 DMA Trigger
Each timer can also trigger DMA transfers if a DMA channel is programmed to be
triggered by a timer event. The timer issues a DMA trigger on every event in all modes of
operation. To ensure that all DMA triggers are serviced, provide for the preceding DMA
trigger to be serviced before the DMA channel receives the next trigger.
9.4 Triple Timer Module Programming Model
The timer programmer’s model in Figure 9-20 shows the structure of the timer registers.
9.4.1 Prescalar Counter
The prescalar counter is a 21-bit counter that decrements on the rising edge of the
prescalar input clock. The counter is enabled when at least one of the three timers is
enabled (that is, one or more of the timer enable bits are set) and is using the prescalar
output as its source (that is, one or more of the PCE bits are set).
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Triple Timer Module Programming Model
23
0
Timer Prescalar Load
Register (TPLR)
TPLR = $FFFF83
23
0
Timer Prescalar Count
Register (TPCR)
TPLR = $FFFF82
23
22
21
20
19
18
17
16
Timer Control/Status
Register (TCSR)
TCF TOF
15
14
Freescale Semiconductor, Inc...
PCE
13
12
11
DO
DI
DIR
5
4
3
10
9
8
TCSR0 = $FFFF8F
TRM
INV
TCSR1 = $FFFF8B
1
0
TCSR2 = $FFFF87
7
6
TC3
TC2 TC1 TC0
23
2
TCIE TOIE
TE
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
23
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
23
0
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
Reserved bit. Read as 0. Write with 0 for future compatibility
Figure 9-20. Timer Module Programmer’s Model
9-22
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Triple Timer Module Programming Model
9.4.2 Timer Prescalar Load Register (TPLR)
The TPLR is a read/write register that controls the prescalar divide factor (i. e., the number
that the prescalar counter loads and begins counting from) and the source for the prescalar
input clock.
Freescale Semiconductor, Inc...
23
22
21
20
19
18
17
16
15
14
13
12
PS1
PS0
PL20
PL19
PL18
PL17
PL16
PL15
PL14
PL13
PL12
11
10
9
8
7
6
5
4
3
2
1
0
PL11
PL10
PL9
PL8
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
— Reserved bit. Read as 0. Write with 0 for future compatibility
Figure 9-21. Timer Prescalar Load Register (TPLR)
Table 9-1. Timer Prescalar Load Register (TPLR) Bit Definitions
Bit Number
Bit Name
23
22 – 21
PS[1 – 0]
Reset Value
Description
0
Reserved. Write to zero for future compatibility.
0
Prescalar Source
Control the source of the prescalar clock. The prescalar’s use of a TIO
signal is not affected by the TCSR settings of the timer of the
corresponding TIO signal. If the prescalar source clock is external, the
prescalar counter is incremented by signal transitions on the TIO signal.
The external clock is internally synchronized to the internal clock. The
external clock frequency must be lower than the DSP56311 internal
operating frequency divided by 4 (that is, CLK/4).
NOTE: To ensure proper operation, change the PS[1 – 0] bits only
when the prescalar counter is disabled. Disable the prescalar counter
by clearing TCSR[TE] of each of three timers.
20 – 0
Motorola
PL[20 – 0]
0
PS1
0
PS0
0
Prescalar Clock Source
0
1
TIO0
1
0
TIO1
1
1
TIO2
Internal CLK/2
Prescalar Preload Value
Contains the prescalar preload value, which is loaded into the prescalar
counter when the counter value reaches 0 or the counter switches state
from disabled to enabled. If PL[20 – 0] = N, then the prescalar counts
N+1 source clock cycles before generating a prescalar clock pulse.
Therefore, the prescalar divide factor = (preload value) + 1.
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9.4.3 Timer Prescalar Count Register (TPCR)
The TPCR is a read-only register that reflects the current value in the prescalar counter.
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23
22
21
20
19
18
17
16
15
14
13
12
PC20
PC19
PC18
PC17
PC16
PC15
PC14
PC13
PC12
11
10
9
8
7
6
5
4
3
2
1
0
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reserved bit; read as 0; should be written with 0 for future compatibility
Figure 9-22. Timer Prescalar Count Register (TPCR)
Table 9-2. Timer Prescalar Count Register (TPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
23 – 21
20 – 0
PC[20 – 0]
Description
0
Reserved. Write to zero for future compatibility.
0
Prescalar Counter Value
Contain the current value of the prescalar counter.
9.4.4 Timer Control/Status Register (TCSR)
The TCSR is a read/write register controlling the timer and reflecting its status.
23
22
11
10
DIR
21
20
19
18
17
16
TCF
TOF
9
8
7
6
5
4
TRM
INV
TC3
TC2
TC1
TC0
15
14
13
12
DO
DI
2
1
0
TCIE
TOIE
TE
PCE
3
Reserved. Read as 0. Write with 0 for future compatibility
Figure 9-23. Timer Control/Status Register (TCSR)
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions
Bit Number
23 – 22
9-24
Bit Name
Reset Value
0
Description
Reserved. Write to zero for future compatibility.
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Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
21
TCF
0
Timer Compare Flag
Indicate that the event count is complete. In timer, PWM, and watchdog
modes, the TCF bit is set after (M – N + 1) events are counted. (M is the
value in the compare register and N is the TLR value.) In measurement
modes, the TCF bit is set when the measurement completes. Writing a
one to the TCF bit clears it. A zero written to the TCF bit has no effect.
The bit is also cleared when the timer compare interrupt is serviced. The
TCF bit is cleared by a hardware RESET signal, a software RESET
instruction, the STOP instruction, or by clearing the TCSR[TE] bit to
disable the timer.
NOTE: The TOF and TCF bits are cleared by a 1 written to the specific
bit. To ensure that only the target bit is cleared, do not use the BSET
command. The proper way to clear these bits is to write 1, using a
MOVEP instruction, to the flag to be cleared and 0 to the other flag.
20
TOF
0
Timer Overflow Flag
Indicates that a counter overflow has occurred. This bit is cleared by a
one written to the TOF bit. A zero written to TOF has no effect. The bit is
also cleared when the timer overflow interrupt is serviced. The TOF bit is
cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TCSR[TE] bit to disable the timer.
19 – 16
15
PCE
14
0
Reserved. Write to zero for future compatibility.
0
Prescalar Clock Enable
Selects the prescalar clock as the timer source clock. When PCE is
cleared, the timer uses either an internal (CLK/2) signal or an external
(TIO) signal as its source clock. When PCE is set, the prescalar output is
the timer source clock for the counter, regardless of the timer operating
mode. To ensure proper operation, the PCE bit is changed only when the
timer is disabled. The PS[1 – 0] bits of the TPLR determine which source
clock is used for the prescalar. A timer can be clocked by a prescalar
clock that is derived from the TIO of another timer.
0
Reserved. Write to zero for future compatibility.
13
DO
0
Data Output
The source of the TIO value when it is a data output signal. The TIO
signal is a data output when the GPIO mode is enabled and DIR is set. A
value written to the DO bit is written to the TIO signal. If the INV bit is set,
the value of the DO bit is inverted when written to the TIO signal. When
the INV bit is cleared, the value of the DO bit is written directly to the TIO
signal. When GPIO mode is disabled, writing to the DO bit has no effect.
12
DI
0
Data Input
Reflects the value of the TIO signal. If the INV bit is set, the value of the
TIO signal is inverted before it is written to the DI bit. If the INV bit is
cleared, the value of the TIO signal is written directly to the DI bit.
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Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
11
DIR
0
Direction
Determines the behavior of the TIO signal when it functions as a GPIO
signal. When DIR is set, the TIO signal is an output; when DIR is cleared,
the TIO signal is an input. The TIO signal functions as a GPIO signal only
when the TC[3 – 0] bits are cleared. If any of the TC[3 – 0] bits are set,
then the GPIO function is disabled, and the DIR bit has no effect.
0
Reserved. Write to zero for future compatibility.
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10
9
TRM
0
Timer Reload Mode
Controls the counter preload operation. In timer (0–3) and watchdog
(9–10) modes, the counter is preloaded with the TLR value after the
TCSR[TE] bit is set and the first internal or external clock signal is
received. If the TRM bit is set, the counter is reloaded each time after it
reaches the value contained by the TCR. In PWM mode (7), the counter
is reloaded each time counter overflow occurs. In measurement (4–5)
modes, if the TRM and the TCSR[TE] bits are set, the counter is
preloaded with the TLR value on each appropriate edge of the input
signal. If the TRM bit is cleared, the counter operates as a free running
counter and is incremented on each incoming event.
8
INV
0
Inverter
Affects the polarity definition of the incoming signal on the TIO signal
when TIO is programmed as input. It also affects the polarity of the
output pulse generated on the TIO signal when TIO is programmed as
output. See Table 9-4, “Inverter (INV) Bit Operation,” on page 9-28. The
INV bit does not affect the polarity of the prescalar source when the TIO
is input to the prescalar.
NOTE: The INV bit affects both the timer and GPIO modes of operation.
To ensure correct operation, change this bit only when one or both of the
following conditions is true: the timer is disabled (the TCSR[TE] bit is
cleared). The timer is in GPIO mode.
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Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
7–4
TC[3 – 0]
0
Timer Control
Control the source of the timer clock, the behavior of the TIO signal, and
the Timer mode of operation. Section 9.3, "Operating Modes," on page
9-4 describes the timer operating modes in detail.
NOTE: To ensure proper operation, the TC[3 – 0] bits should be changed
only when the timer is disabled (that is, when the TCSR[TE] bit is
cleared)
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NOTE: If the clock is external, the counter is incremented by the
transitions on the TIO signal. The external clock is internally
synchronized to the internal clock, and its frequency should be lower
than the internal operating frequency divided by 4 (that is, CLK/4).
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Number
Mode
Function
0
0
0
0
0
Timer and
GPIO
GPIO 1 Internal
0
0
0
1
1
Timer pulse
Output Internal
0
0
1
0
2
Timer toggle Output Internal
0
0
1
1
3
Event counter
Input External
0
1
0
0
4
Input width
measurement
Input
Internal
0
1
0
1
5
Input period
measurement
Input
Internal
0
1
1
0
6
Capture event Input
Internal
0
1
1
1
7
Pulse width
modulation
1
0
0
0
8
Reserved
—
1
0
0
1
9
Watchdog
pulse
Output Internal
1
0
1
0
10
Watchdog
Toggle
Output Internal
1
0
1
1
11
Reserved
—
—
1
1
0
0
12
Reserved
—
—
1
1
0
1
13
Reserved
—
—
1
1
1
0
14
Reserved
—
—
1
1
1
1
15
Reserved
—
—
TIO
Clock
Output Internal
—
Note 1 : The GPIO function is enabled only if all of the TC[3 – 0] bits are
0.
3
Motorola
0
Reserved. Write to zero for future compatibility.
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Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
2
TCIE
0
Timer Compare Interrupt Enable
Enables/disables the timer compare interrupts. When set, TCIE enables
the compare interrupts. In the timer, pulse width modulation (PWM), or
watchdog modes, a compare interrupt is generated after the counter
value matches the value of the TCPR. The counter starts counting up
from the number loaded from the TLR and if the TCPR value is M, an
interrupt occurs after (M – N + 1) events, where N is the value of TLR.
When cleared, the TCSR[TCIE] bit disables the compare interrupts.
1
TOIE
0
Timer Overflow Interrupt Enable
Enables timer overflow interrupts. When set, TOIE enables overflow
interrupt generation. The timer counter can hold a maximum value of
$FFFFFF. When the counter value is at the maximum value and a new
event causes the counter to be incremented to $000000, the timer
generates an overflow interrupt. When cleared, the TOIE bit disables
overflow interrupt generation.
0
TE
0
Timer Enable
Enables/disables the timer. When set, TE enables the timer and clears
the timer counter. The counter starts counting according to the mode
selected by the timer control (TC[3 – 0]) bit values. When clear, TE bit
disables the timer.
NOTE: When all three timers are disabled and the signals are not in
GPIO mode, all three TIO signals are tri-stated. To prevent undesired
spikes on the TIO signals when you switch from tri-state into active state,
these signals should be tied to the high or low signal state by pull-up or
pull-down resistors.
Table 9-4. Inverter (INV) Bit Operation
TIO Programmed as Input
TIO Programmed as Output
Mode
INV = 0
INV = 1
0
GPIO signal on the TIO
signal read directly.
GPIO signal on the TIO
signal inverted.
1
Counter is incremented on
the rising edge of the
signal from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
2
Counter is incremented on
the rising edge of the
signal from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
3
Counter is incremented on
the rising edge of the
signal from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
9-28
INV = 0
Bit written to GPIO
put on TIO signal
directly.
—
Initial output put on
TIO signal directly.
—
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INV = 1
Bit written to GPIO
inverted and put on
TIO signal.
—
Initial output inverted
and put on TIO signal.
—
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Triple Timer Module Programming Model
Table 9-4. Inverter (INV) Bit Operation (Continued)
TIO Programmed as Input
TIO Programmed as Output
Mode
INV = 0
4
5
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6
INV = 1
Width of the high input
pulse is measured.
Width of the low input
pulse is measured.
Period is measured
between the rising edges
of the input signal.
Period is measured
between the falling edges
of the input signal.
Event is captured on the
rising edge of the signal
from the TIO signal.
Event is captured on the
falling edge of the signal
from the TIO signal.
7
INV = 0
INV = 1
—
—
—
—
—
—
Pulse generated by
the timer has
negative polarity.
—
—
Pulse generated by
the timer has
positive polarity.
—
—
Pulse generated by
the timer has
positive polarity.
Pulse generated by
the timer has
negative polarity.
—
—
Pulse generated by
the timer has
positive polarity.
Pulse generated by
the timer has
negative polarity.
9
10
9.4.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the
TLR value after the TCSR[TE] bit is set and a first event occurs.
■
In timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after
it reaches the value contained by the timer compare register and the new event
occurs.
■
In measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is
reloaded with the value in the TLR on each appropriate edge of the input signal.
■
In PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it
overflows and the new event occurs.
■
In watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event
occurs. In this mode, the counter is also reloaded whenever the TLR is written with
a new value while TCSR[TE] is set.
■
In all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a
free-running counter.
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9.4.6 Timer Compare Register (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the
counter value. These two values are compared every timer clock after TCSR[TE] is set.
When the values match, the timer compare flag bit is set and an interrupt is generated if
interrupts are enabled (that is, the timer compare interrupt enable bit in the TCSR is set).
The TCPR is ignored in measurement modes.
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9.4.7 Timer Count Register (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the contents of the
counter can be read at any time from the TCR register. In measurement modes, the TCR is
loaded with the current value of the counter on the appropriate edge of the input signal,
and its value can be read to determine the width, period, or delay of the leading edge of the
input signal. When the timer is in measurement mode, the TIO signal is used for the input
signal.
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Chapter 10
Enhanced Filter Coprocessor (EFCOP)
The EFCOP peripheral module functions as a general-purpose, fully programmable filter.
It has optimized modes of operation to perform real and complex finite impulse response
(FIR) filtering, infinite impulse response (IIR) filtering, adaptive FIR filtering, and
multichannel FIR filtering. EFCOP filter operations complete concurrently with
DSP56300 core operations, with minimal CPU intervention. For optimal performance, the
EFCOP has one dedicated Filter Multiplier Accumulator (FMAC) unit. Thus, for filtering,
the combination Core/EFCOP offers dual MAC capabilities. Its dedicated modes make the
EFCOP a very flexible filter coprocessor with operations optimized for cellular base
station applications. The EFCOP architecture also allows adaptive FIR filtering in which
the filter coefficient update is performed using any fixed-point standard or non-standard
adaptive algorithms—for example, the well-known Least Mean Square (LMS) algorithm,
the Normalized LMS, and customized update algorithms. In a transceiver base station, the
EFCOP can perform complex matched filtering to maximize the signal-to-noise ratio
(SNR) within an equalizer. In a transcoder base station or a mobile switching center, the
EFCOP can perform all types of FIR and IIR filtering within a vocoder, as well as
LMS-type echo cancellation.
The first half of this chapter describes the structure and function of the EFCOP, examining
its features, architecture, and programming model. The remainder of the chapter covers
programming topics, such as transferring data to and from the EFCOP, using it in different
modes, and examples of usage.
10.1 Features
■
Fully programmable real/complex filter machine with 24-bit resolution
■
FIR filter options
— Four modes of operation with optimized performance:
— Mode 0, FIR machine with real taps
— Mode 1, FIR machine with complex taps
— Mode 2, Complex FIR machine generating pure real/imaginary outputs
alternately
— Mode 3—Magnitude (calculate the square of each input sample)
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Features
— 4-bit decimation factor in FIR filters providing up to 1:16 decimation ratio
— Easy to use adaptive mode supporting true or delayed LMS-type algorithms
— K-constant input register for coefficient updates (in adaptive mode)
■
IIR filter options:
— Direct form 1 (DFI) and direct form 2 (DFII) configurations1
Freescale Semiconductor, Inc...
— Three optional output scaling factors (1, 8, or 16)
■
Multichannel mode to process multiple, equal-length filter channels (up to 64)
simultaneously with minimal core intervention
■
Optional input scaling for both FIR and IIR filters
■
Two filter initialization modes
— No initialization
— Data initialization
■
Sixteen-bit arithmetic mode support
■
Three rounding options available:
— No rounding
— Convergent rounding
— Two’s complement rounding
■
Arithmetic saturation mode support for bit-exact applications
■
Sticky saturation status bit indication
■
Sticky data/coefficient transfer contention status bit
■
4-word deep input data buffer for maximum performance
■
EFCOP-shared and core-shared 10K-word filter data memory bank and 10K-word
filter coefficient memory bank
■
Two memory bank base address pointers, one for data memory (shared with
X memory) and one for coefficient memory (shared with Y memory)
■
I/O data transfers via core or DMA with minimal core intervention
■
Core-concurrent operation with minimal core intervention
1. For details on DFI and DFII modes, refer to the Motorola application note entitled Implementing IIR/FIR
Filters with Motorola’s DSP56000/DSP56001 (APR7/D).
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Architecture Overview
10.2 Architecture Overview
As Figure 10-1 shows, the EFCOP comprises these main functional blocks:
■
Peripheral module bus (PMB) interface, including:
— Data input buffer
— Constant input buffer
— Output buffer
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— Filter counter
■
Filter data memory (FDM) bank
■
Filter coefficient memory (FCM) bank
■
Filter multiplier accumulator (FMAC) machine
■
Address generator
■
Control logic
DMA BUS
PMB
Interface
GDB BUS
FDIR
Control
Logic
X Memory
Shared
RAM
FKIR
Filter Constant
4-Word
Data Input Buffer
FDM
DATA
Memory Bank
24-bit
FCNT
Filter Count
FCBA
Coeff. Base Ad.
FDBA
Data Base Ad.
Address
Generator
Y Memory
Shared
RAM
FCM
COEFFICIENT
Memory Bank
24-bit
FMAC
24x24 -> 56-bit
Rounding & Limiting
Output Buffer
FDOR
Figure 10-1. EFCOP Block Diagram
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10.2.1 PMB Interface
The PMB interface block contains control and status registers, buffers the internal bus
from the PMB, decodes and generates addresses, and controls the handshake signals
required for DMA and interrupt operations. The block generates interrupt and DMA
trigger signals for data transfers. The interface registers accessible to the DSP56300 core
through the PMB are summarized in Table 10-1.
Table 10-1. EFCOP Registers Accessible Through the PMB
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Register Name
Description
Filter Data Input
Register (FDIR)
A 4-word-deep 24-bit-wide FIFO used for DSP-to-EFCOP data transfers. Data from the
FDIR is transferred to the FDM for filter processing.
Filter Data Output
Register (FDOR)
A 24-bit-wide register used for EFCOP-to-DSP data transfers. Data is transferred to
FDOR after processing of all filter taps is completed for a specific set of input samples.
Filter K-Constant Input
Register (FKIR)
A 24-bit register for DSP-to-EFCOP constant transfers.
Filter Count (FCNT)
Register
A 24-bit register that specifies the number of filter taps. The count stored in the FCNT
register is used by the EFCOP address generation logic to generate correct addressing
to the FDM and FCM.
EFCOP Control Status
Register (FCSR)
A 24-bit read/write register used by the DSP56300 core to program the EFCOP and to
examine the status of the EFCOP module.
EFCOP ALU Control
Register (FACR)
A 24-bit read/write register used by the DSP56300 core to program the EFCOP data
ALU operating modes.
EFCOP Data Buffer
Base Address (FDBA)
A 16-bit read/write register used by the DSP56300 core to indicate the EFCOP the data
buffer base start address pointer in FDM RAM.
EFCOP Coefficient
Buffer Base Address
(FCBA)
A 16-bit read/write register by which the DSP56300 core indicates the EFCOP
coefficient buffer base start address pointer in FCM RAM.
Decimation/
Channel Count
Register (FDCH)
A 24-bit register that sets the number of channels in multichannel mode and the filter
decimation ratio. The EFCOP address generation logic uses this information to supply
the correct addressing to the FDM and FCM.
10.2.2 EFCOP Memory Banks
The EFCOP contains two memory banks:
■
Filter Data Memory (FDM)—This 24-bit-wide memory bank is mapped as X
memory and stores input data samples for EFCOP filter processing. The FDM is
written via a 4-word FIFO (FDIR), and its addressing is generated by the EFCOP
address generation logic. The input data samples are read sequentially from the
FDM into the MAC. The FDM is accessible for writes by the core, and the DMA
controller and is shared with the 10K lowest locations ($0–$2800) of the on-chip
internal X memory.
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■
Filter Coefficient Memory (FCM)—This 24-bit-wide memory bank is mapped as
Y memory and stores filter coefficients for EFCOP filter processing. The FCM is
written via the DSP56300 core, and the EFCOP address generation logic generates
its addressing. The filter coefficients are read sequentially from the FCM into the
MAC. The FCM is accessible for writes only by the core. The FCM is shared with
the 10K lowest locations ($0–$2800 of the on-chip internal Y memory.
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Note:
The filter coefficients, H(n), are stored in “reverse order,” where H(N-1) is
stored at the lowest address of the FCM register as shown in Figure 10-2.
Data
Memory
Bank
(FDM)
D(0)
H(N - 1)
D(1)
D(2)
D(3)
D(4)
D(5)
-
H(N - 2)
H(1)
Coefficient
Memory
Bank
(FCM)
H(0)
Figure 10-2. Storage of Filter Coefficients
The EFCOP connects to the shared memory in place of the DMA bus. Simultaneous core
and EFCOP accesses to the same memory module block (256 locations) of shared memory
are not permitted. It is your responsibility to prevent such simultaneous accesses. Figure
10-3 illustrates the memory shared between the core and the EFCOP.
.
X RAM
Data
(FDM)
Y RAM
Coefficients
(FCM)
X RAM
Y RAM
P RAM
YDB
PDB
XDB
FDB
CDB
DDB
EFCOP
GDB
CORE
Figure 10-3. EFCOP Memory Organization
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10.2.3 Filter Multiplier and Accumulator (FMAC)
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The FMAC machine can perform a 24-bit ™ 24-bit multiplication with accumulation in a
56-bit accumulator. The FMAC operates a pipeline: the multiplication is performed in one
clock cycle, and the accumulation occurs in the following clock cycle. Throughput is one
MAC result per clock cycle. The two MAC operands are read from the FDM and from the
FCM. The full 56-bit width of the accumulator is used for intermediate results during the
filter calculations.
For operations in which saturation mode is disabled, the final result is rounded according
to the selected rounding mode and limited to the most positive number ($7FFFFF, if
overflow occurred) or most negative number ($800000, if underflow occurred) after
processing of all filter taps is completed. In saturation mode, the result is limited to the
most positive number ($7FFFFF, if overflow occurred), or the most negative number
($800000, if underflow occurred) after each MAC operation. The 24-bit result from the
FMAC is stored in the EFCOP output buffer, FDOR.
Operating in sixteen-bit arithmetic mode, the FMAC performs a 16-bit ™ 16-bit
multiplication with accumulation into a 40-bit accumulator. As with 24-bit operations, if
saturation mode is disabled, the result is rounded according to the selected rounding mode
and limited to the most positive number ($7FFF, if overflow occurred) or the most
negative number ($8000, if underflow occurred) after processing of all filter taps is
completed. In saturation mode, the result is limited to the most positive number ($7FFF, if
overflow occurred) or the most negative number ($8000, if underflow occurred) after
every MAC operation. The 16-bit result from the FMAC is stored in the EFCOP output
buffer, FDOR.
10.3 EFCOP Programming Model
This section documents the registers for configuring and operating the EFCOP. The
EFCOP registers available to the DSP programmer are listed in Table 10-2. The following
paragraphs describe these registers in detail.
Table 10-2. EFCOP Registers and Base Addresses
Motorola
Address
EFCOP Register Name
Y:$FFFFB0
Filter data input register (FDIR)
Y:$FFFFB1
Filter data output register (FDOR)
Y:$FFFFB2
Filter K-constant register (FKIR)
Y:$FFFFB3
Filter count register (FCNT)
Y:$FFFFB4
Filter control status register (FCSR)
Y:$FFFFB5
Filter ALU control register (FACR)
Y:$FFFFB6
Filter data buffer base address (FDBA)
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Table 10-2. EFCOP Registers and Base Addresses (Continued)
Address
EFCOP Register Name
Y:$FFFFB7
Filter coefficient base address (FCBA)
Y:$FFFFB8
Filter decimation/channel register (FDCH)
NOTE: The EFCOP registers are mapped onto Y data memory space.
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10.3.1 Filter Data Input Register (FDIR)
The FDIR is a 4-word deep, 24-bit wide FIFO for DSP-to-EFCOP data transfers. Up to
four data samples can be written into the FDIR at the same address. Data from the FDIR is
transferred to the FDM for filter processing. For proper operation, write data to the FDIR
only if the FDIBE status bit is set, indicating that the FIFO is empty. A write to the FDIR
clears the FDIBE bit. Data transfers can be triggered by an interrupt request (for core
transfers) or a DMA request (for DMA transfers). The FDIR is accessible for writes by the
DSP56300 core and the DMA controller.
10.3.2 Filter Data Output Register (FDOR)
The FDOR is a 24-bit read-only register for EFCOP-to-DSP data transfers. The result of
the filter processing is transferred from the FMAC to the FDOR. For proper operation,
read data from the FDOR only if the FDOBF status bit is set, indicating that the FDOR
contains data. A read from the FDOR clears the FDOBF bit. Data transfers can be
triggered by an interrupt request (for core transfers) or a DMA request (DMA transfers).
The FDOR is accessible for reads by the DSP56300 core and the DMA controller.
10.3.3 Filter K-Constant Input Register (FKIR)
The Filter K-Constant Input Register (FKIR) is a 24-bit write-only register for
DSP-to-EFCOP data transfers in adaptive mode where the value stored in FKIR represents
the weight update multiplier. FKIR is accessible only to the DSP core for reads or writes.
When adaptive mode is enabled, the EFCOP immediately starts the coefficient update if a
K-Constant value is written to FKIR. If no value is written to FKIR for the current data
sample, the EFCOP halts processing until the K-Constant is written to FKIR. After the
weight update multiplier is written to FKIR, the EFCOP transfers it to the FMAC unit and
starts updating the filter coefficients according to the following equation:
New_coefficients = Old_coefficients + FKIR * Input_buffer
10.3.4 Filter Count (FCNT) Register
The FCNT register is a read/write register that selects the filter length (number of filter
taps). Always write the initial count into the FCNT register before you enable the EFCOP
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(that is, before you set FEN). The number stored in FCNT is used to generate the correct
addressing for the FDM and for the FCM.
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Note:
To ensure correct operation, never change the contents of the FCNT register
unless the EFCOP is in the individual reset state (that is, FEN = 0). In the
individual reset state (that is, FEN = 0), the EFCOP module is inactive, but the
contents of the FCNT register are preserved.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCNT8
FCNT7
FCNT6
FCNT5
FCNT4
FCNT3
FCNT2
FCNT1
FCNT0
FCNT11 FCNT10 FCNT9
=
Reserved bit; read as 0; should be written with 0 for future compatibility
Figure 10-4. Filter Count (FCNT) Register
Table 10-3. Filter Count FCNT Register Bits
Bit #
Abbr.
23–12
11–0
Description
These bits are reserved and unused. They are read as 0 and should be written with 0 for
future compatibility.
FCNT
Filter Count—The actual value written to the FCNT register must be the number of coefficient
values minus one. The number of coefficient values is the number of locations used in the
FCM. For a real FIR filter, the number of coefficient values is identical to the number of filter
taps. For a complex FIR filter, the number of coefficient values is twice the number of filter
taps.
10.3.5 EFCOP Control Status Register (FCSR)
The FCSR is a 24-bit read/write register by which the DSP56300 core controls the main
operation modes of the EFCOP and monitors the EFCOP status.
23
22
11
10
FDOIE
FDIIE
=
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21
9
20
19
18
17
16
15
14
13
12
FDOBF
FDIBE
FCONT
FSAT
8
7
6
5
4
3
2
1
0
FSCO
FPRC
FMLC
FOM1
FOM0
FUPD
FADP
FLT
FEN
Reserved bit; read as 0; should be written with 0 for future compatibility
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Table 10-4. FCSR Bits
Bit
Number
Bit Name
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23–16
Reset
Value
Description
0
These bits are reserved and unused. They are read as 0 and should be written
with 0 for future compatibility.
15
FDOBF
0
Filter Data Output Buffer Full— When set, this read-only status bit indicates
that the FDOR is full and the DSP can read data from the FDOR. The FDOBF bit
is set when a result from FMAC is transferred to the FDOR. For proper operation,
read data from the FDOR only if the FDOBF status bit is set. When FDOBF is
set, the EFCOP generates an FDOBF interrupt request to the DSP56300 core if
that interrupt is enabled (that is, FDOIE = 1). A DMA request is always generated
when the FDOBF bit is set, but a DMA transfer takes place only if a DMA channel
is activated and triggered by this event. A read from the FDOR clears the FDOBF
bit.
14
FDIBE
0
Filter Data Input Buffer Empty—When set, this read-only status bit indicates
that the FDIR is empty and the DSP can write data to the FDIR. The FDIBE bit is
set when all four FDIR locations are empty. For proper operation, write data to
the FDIR only if FDIBE is set. After the EFCOP is enabled by setting FEN, FDIBE
is set, indicating that the FDIR is empty. When FDIBE is set, the EFCOP
generates an FDIR empty interrupt request to the DSP56300 core, if enabled
(that is, FDIIE = 1). A DMA request is always generated when the FDIBE bit is
set, but a DMA transfer takes place only if a DMA channel is activated and
triggered by this event. A write to the FDIR clears the FDIBE bit.
13
FCONT
0
Filter Contention—When set, this read-only status bit indicates an attempt by
both the DSP56300 core and the EFCOP to access the same 256-word bank in
either the shared FDM or FCM. A dual access could result in faulty data output in
the FDOR. Once set, the FCONT bit is a sticky bit that can only be cleared by a
hardware RESET signal, a software RESET instruction, or an individual reset.
12
FSAT
0
Filter Saturation—When set, this read-only status bit indicates that an overflow
or underflow occurred in the MAC result. When an overflow occurs, the FSAT bit
is set, and the result is saturated to the most positive number (that is, $7FFFFF).
When an underflow occurs, the FSAT bit is set, and the result is saturated to the
most negative number (that is, $800000). FSAT is a sticky status bit that is set by
hardware and can be cleared only by a hardware RESET signal, a software
RESET instruction, or an individual reset.
11
FDOIE
0
Filter Data Output Interrupt Enable—This read/write control bit enables the
filter data output interrupt. If FDOIE is cleared, the filter data output interrupt is
disabled, and the FDOBF status bit should be polled to determine whether the
FDOR is full. If both FDOIE and FDOBF are set, the EFCOP requests a data
output buffer full interrupt service from the DSP56300 core. A DMA transfer is
enabled if a DMA channel is activated and triggered by this event.
NOTE: For proper operation, enable the interrupt service routine and the
corresponding interrupt for core processing or enable the DMA transfer and
configure the proper trigger for the selected channel. Never enable both
simultaneously.
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Table 10-4. FCSR Bits (Continued)
Bit
Number
Bit Name
Reset
Value
10
FDIIE
0
Description
Filter Data Input Interrupt Enable—This read/write control bit enables the data
input buffer empty interrupt. If FDIIE is cleared, the data input buffer empty
interrupt is disabled, and the FDIBE status bit should be polled to determine
whether the FDIR is empty. If both FDIIE and FDIBE are set, the EFCOP
requests a data input buffer empty interrupt service from the DSP56300 core.
DMA transfer is enabled if a DMA channel is activated and triggered by this
event.
NOTE: For proper operation, enable the interrupt service routine and the
corresponding interrupt for core processing or enable the DMA transfer and
configure the proper trigger for the selected channel. Never enable both
simultaneously.
9
8
FSCO
0
Reserved. It is read as 0 and should be written with 0 for future compatibility.
0
Filter Shared Coefficients Mode—This read/write control bit is valid only when
the EFCOP is operating in multichannel mode (that is, FMLC is set). When
FSCO is set, the EFCOP uses the coefficients in the same memory area (that is,
the same coefficients) to implement the filter for each channel. This mode is used
when several channels are filtered through the same filter. When the FSCO bit is
cleared, the EFCOP filter coefficients are stored sequentially in memory for each
channel.
NOTE: To ensure proper operation, never change the FSCO bit unless the
EFCOP is in individual reset state (that is, FEN = 0).
7
FPRC
0
Filter Processing (FPRC) State Initialization Mode—This read/write control bit
defines the EFCOP processing initialization mode. When this bit is cleared, the
EFCOP starts processing after a state initialization. (The EFCOP machine starts
computing once the FDM bank contains N input samples for an N tap filter).
When this bit is set, the EFCOP starts processing with no state initialization. (The
EFCOP machine starts computing as soon as the first data sample is available in
the input buffer.)
NOTE: To ensure proper operation, never change the FPRC bit unless the
EFCOP is in individual reset state (that is, FEN = 0).
6
FMLC
0
Filter Multichannel (FMLC) Mode—This read/write control bit enables
multichannel mode, allowing the EFCOP to process several filters (defined by
FCHL[5:0] bits in FDCH register) concurrently by sequentially entering a different
sample to each filter. If FMLC is cleared, multichannel mode is disabled, and the
EFCOP operates in single filter mode.
NOTE: To ensure proper operation, never change the FMLC bit unless the
EFCOP is in individual reset state (that is, FEN = 0).
5–4
FOM
0
Filter Operation Mode—This pair of read/write control bits defines one of four
operation modes if the FIR filter is selected (that is, FLT is cleared):
FOM = 00—Mode 0: Real FIR filter
FOM = 01—Mode 1: Full complex FIR filter
FOM = 10—Mode 2: Complex FIR filter with alternate real and imaginary outputs
FOM = 11—Mode 3: Magnitude
NOTE: To ensure proper operation, never change the FOM bits unless the
EFCOP is in the individual reset state (that is, FEN = 0).
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Table 10-4. FCSR Bits (Continued)
Bit
Number
Bit Name
Reset
Value
3
FUPD
0
Filter Update—This read/write control/status bit enables the EFCOP to start a
single coefficient update session. Upon completion of the session, the FUPD bit
is automatically cleared. FUPD is automatically set when the EFCOP is in
adaptive mode (that is, FADP = 1).
2
FADP
0
Filter Adaptive (FADP) Mode—This read/write control bit enables adaptive
mode. Adaptive mode is an efficient way to implement a LMS-type filter, and
therefore it is used when the EFCOP operates in FIR filter mode (FLT = 0). In
adaptive mode, processing of every input data sample consists of FIR
processing followed by a coefficient update. When FADP is set, the EFCOP
completes the FIR processing on the current data sample and immediately starts
the coefficient update assuming that a K-constant value is written to the FKIR. If
no value is written to the FKIR for the current data sample, the EFCOP halts
processing until the K-constant is written to the FKIR. During the coefficient
update, the FUPD bit is automatically set to indicate an update session. After
completion of the update, the EFCOP starts processing the next data sample.
1
FLT
0
Filter (FLT) Type—This read/write control bit selects one of two available filter
types:
FLT = 0—FIR filter
FLT = 1—IIR filter
Description
NOTE: To ensure proper operation, never change the FLT bit unless the EFCOP
is in the individual reset state (that is, FEN = 0).
0
FEN
0
Filter Enable—This read/write control bit enables the operation of the EFCOP.
When FEN is cleared, operation is disabled and the EFCOP is in the individual
reset state.
In the individual reset state, the EFCOP is inactive; internal logic and status bits
assume the same state as that produced by a hardware RESET signal or a
software RESET instruction; the contents of the FCNT, FDBA, and FCBA
registers are preserved; and the control bits in FCSR and FACR remain
unchanged.
10.3.6 EFCOP ALU Control Register (FACR)
The FACR is a read/write register by which the DSP56300 core controls the main
operation modes of the EFCOP ALU.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FISL
FSA
FSM
FRM1
FRM0
FSCL1
FSCL0
=
Reserved bit; read as 0; should be written with 0 for future compatibility
=
Reserved for internal use; read as 0; should be written with 0 for proper use.
Figure 10-5. EFCOP ALU Control Register (FACR)
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Table 10-5. EFCOP ALU Control Register (FACR) Bits
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Bit
Number
Bit
Name
Reset
Value
Description
23–16
0
Reserved. They are read as 0 and should be written with 0 for future compatibility.
15–12
0
Reserved for internal use. Written as 0 for proper operation.
11–7
0
Reserved and unused. They are read as 0 and should be written with 0 for future
compatibility.
6
FISL
0
Filter Input Scale—When set, this read/write control bit directs the EFCOP ALU
to scale the IIR feedback terms but not the IIR input. When cleared, the EFCOP
ALU scales both the IIR feedback terms and the IIR input. The scaling value in
both cases is determined by the FSCL[1:0] bits.
5
FSA
0
Filter Sixteen-bit Arithmetic (FSA) Mode—When set, this read/write control bit
enables FSA mode. In this mode, the rounding of the arithmetic operation is
performed on Bit 31 of the 56-accumulator instead of the usual bit 23 of the 56-bit
accumulator. The scaling of the EFCOP data ALU is affected accordingly.
4
FSM
0
Filter Saturation Mode—When set, this read/write control bit selects automatic
saturation on 48 bits for the results going to the accumulator. A special circuit
inside the EFCOP MAC unit then saturates those results. The purpose of this bit is
to provide arithmetic saturation mode for algorithms that do not recognize or
cannot take advantage of the extension accumulator.
3–2
FRM
0
Filter Rounding Mode—These read/write control bits select the type of rounding
performed by the EFCOP data ALU during arithmetic operation:
FRM = 00—Convergent rounding
FRM = 01—Two’s complement rounding
FRM = 10—Truncation (no rounding)
FRM = 11—Reserved for future expansion
These bits affect operation of the EFCOP data ALU.
1–0
FSCL
0
Filter Scaling (FSCL)—These read/write control bits select the scaling factor of
the FMAC result:
FSCL = 00—Scaling factor = 1 (no shift)
FSCL = 01—Scaling factor = 8 (3-bit arithmetic left shift)
FSCL = 10—Scaling factor = 16 (4-bit arithmetic left shift)
FSCL = 11—Reserved for future expansion
To ensure proper operation, never change the FSCL bits unless the EFCOP is in
the individual reset state (that is, FEN = 0).
10.3.7 EFCOP Data Base Address (FDBA)
The FDBA is a 16-bit read/write counter register used as an address pointer to the EFCOP
FDM bank. FDBA points to the location to write the next data sample. The FDBA points
to a modulo delay buffer of size M, defined by the filter length (M = FCNT[11:0] + 1).
The address range of this modulo delay buffer is defined by lower and upper address
boundaries. The lower address boundary is the FDBA value with 0 in the k-LSBs, where
±
2 k ˜ M ˜ 2 k 1 ; it therefore must be a multiple of 2k. The upper boundary is equal to the
lower boundary plus (M – 1). Since M ˆ 2 k , once M has been chosen (that is, FCNT has
been assigned), a sequential series of data memory blocks (each of length 2k) will be
created where multiple circular buffers for multichannel filtering can be located. If M < 2 k ,
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there will be a space between sequential circular buffers of 2 k ± M . The address pointer is
not required to start at the lower address boundary or to end on the upper address
boundary. It can point anywhere within the defined modulo address range. If the data
address pointer (FDBA) increments and reaches the upper boundary of the modulo buffer,
it will wrap around to the lower boundary.
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10.3.8 EFCOP Coefficient Base Address (FCBA)
The FCBA is a 16-bit read/write counter register used as an address pointer to the EFCOP
FCM bank. FCBA points to the first location of the coefficient table. The FCBA points to
a modulo buffer of size M, defined by the filter length (M = FCNT[11:0] + 1). The
address range of this modulo buffer is defined by lower and upper address boundaries. The
lower address boundary is the FCBA value with 0 in the k-LSBs, where 2 k ˜ M ˜ 2 k ± 1 ; it
therefore must be a multiple of 2k. The upper boundary is equal to the lower boundary plus
(M – 1). Since M ˆ 2k , once M has been chosen (that is, FCNT has been assigned), a
sequential series of coefficient memory blocks (each of length 2k) is created where
multiple circular buffers for multichannel filtering can be located. If M < 2k , there will be
a space between sequential circular buffers of 2 k ± M . The FCBA address pointer must be
assigned to the lower address boundary (that is, it must have 0 in its k-LSBs). In a
compute session, the coefficient address pointer always starts at the lower boundary and
ends at the upper address boundary. Therefore, a FCBA read always gives the value of the
lower address boundary.
10.3.9 Decimation/Channel Count Register (FDCH)
The FDCH is a read/write register that sets the number of channels used in multichannel
mode (FCHL) and sets the decimation ratio in FIR filter mode. FDCH must be written
before the FEN enables the EFCOP. FDCH should be changed only when the EFCOP is in
individual reset state (FEN = 0); otherwise, improper operation may result. The number
stored in FCHL is used by the EFCOP address generation logic to generate the correct
address for the FDM bank and for the FCM bank in multichannel mode. When the EFCOP
enable bit (FEN) is cleared, the EFCOP is in individual reset state. In this state, the
EFCOP is inactive, and the contents of FDCH register are preserved.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCHL5
FCHL4
FCHL3
FCHL2
FCHL1
FCHL0
FDCM3 FDCM2 FDCM1 FDCM0
=
Reserved bit; read as 0; should be written with 0 for future compatibility
Figure 10-6. Decimation/Channel Count Register (FDCH)
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EFCOP Programming
Table 10-6. Decimation/Channel Count Register (FDCH) Bits
Bit
Number
Bit
Name
Reset
Value
23–12
11–8
FDCM
Description
0
These bits are reserved and unused. They are read as 0 and should be written
with 0 for future compatibility.
0
Filter Decimation—These read/write control bits select the decimation function.
There are 16 decimation factor options (from 1 to 16).
NOTE: To ensure proper operation, never change the FDCM bits unless the
EFCOP is in the individual reset state (FEN = 0).
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7–6
5–0
FCHL
0
Reserved and unused. They are read as 0 and should be written with 0 for future
compatibility.
0
Filter Channels—These read/write control bits determine the number of filter
channels to process simultaneously (from 1 to 64) in multichannel mode. The
number represented by the FCHL bits is one less than the number of channels to
be processed; that is, if FCHL = 0, then 1 channel is processed; if FCHL =1, then
2 channels are processed; and so on.
NOTE: To ensure proper operation, never change the FCHL bits unless the
EFCOP is in the individual reset state (FEN = 0).
10.3.10 EFCOP Interrupt Vectors
Table 10-7 shows the EFCOP interrupt vectors, and Table 10-8 shows the DMA request
sources.
Table 10-7. EFCOP Interrupt Vectors
Interrupt
Address
VBA + $68
VBA + $6A
Interrupt Vector
Data input buffer empty
Data output buffer full
Priority
Highest
Lowest
Interrupt
Enable
Interrupt
Conditions
FDIIE
FDOIE
FDIBE = 1
FDOBF = 1
Table 10-8. EFCOP DMA Request Sources
Requesting Device Number
EFCOP input buffer empty
EFCOP output buffer full
Request Conditions
Peripheral Request
MDRQ
FDIBE = 1
FDOBF = 1
MDRQ11
MDRQ12
10.4 EFCOP Programming
The DSP56311 Enhanced Filter Coprocessor (EFCOP) supports both Finite Impulse
Response (FIR) filters and Infinite Impulse Response (IIR) filters.1 This section discusses
the different ways data can be transferred in and out of the EFCOP and presents some
programming examples in which such transfers are performed for FIR and IIR filters.
1. For details on FIR and IIR filters, refer to the Motorola application note entitled Implementing IIR/FIR
Filters with Motorola’s DSP56000/DSP56001 (APR7/D).
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EFCOP Programming
EFCOP operation is determined by the control bits in the EFCOP Control/Status Register
(FCSR), described in Section 10.3.5. Further filtering operations are enabled via the
appropriate bits in the FACR and FDCH registers. After the FCSR is configured to the
mode of choice, enable the EFCOP by setting FCSR[FEN]. To ensure proper EFCOP
operation, most FCSR bits must not be changed while the EFCOP is enabled. Table 10-9
summarizes the EFCOP operating modes.
Table 10-9. EFCOP Operating Modes
FCSR Bits
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Mode Description
3
3
2
FADP2
1
FLT
0
FEN
x
x
x
0
00
0
0
0
1
0
00
0
1
0
1
FIR, Real, coeff. update, single channel
0
00
1
0
0
1
FIR, Real, adaptive + coeff. update,
single channel
0
00
1
1
0
1
FIR, Real, multichannel
1
00
0
0
0
1
FIR, Real, adaptive, multichannel
1
00
0
1
0
1
FIR, Real, coeff. update, multichannel
1
00
1
0
0
1
FIR, Real, adaptive + coeff. update,
multichannel
1
00
1
1
0
1
FIR, Full Complex, single channel
0
01
0
0
0
1
6
FMLC
5–4
FOM
FUPD
EFCOP Disabled1
x
x
FIR, Real, single channel
0
FIR, Real, adaptive, single channel
2
FIR, Complex Alternating, single channel
0
10
0
0
0
1
FIR, Magnitude, single channel
0
11
0
0
0
1
IIR, Real, single channel
0
00
0
0
1
1
IIR, Real, multichannel
1
00
0
0
1
1
NOTES:
1. An x indicates that the specified value can be 1 or 0.
2. If the user sets the FUPD bit, the EFCOP updates the coefficients and clears the FUPD bit. The adaptive mode
(that is, FADP = 1) sets the FUPD bit, which causes the EFCOP to update the coefficients and then automatically
clear the FUPD bit. Therefore, the value assigned to the FUPD bit in this table refers only to its initial setting and
not its dynamic state during operation.
3. All bit combinations not defined by this table are reserved for future development.
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Operation Summary
10.5 Operation Summary
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The EFCOP is very easy to use. To define the type of filtering to perform, you need only
set the following registers (the settings in the FDCH and FACR are optional) and then
enable the EFCOP by setting FCSR[FEN]:
■
FCNT
■
FDBA
■
FCBA
■
FCSR
Polling, DMA, or interrupts can then be used to write data to the FDIR and read data from
the FDOR. As Table 10-9 shows, the EFCOP operates in many different modes based on
the settings of the control registers. However, the EFCOP performs only two basic types
of processing, FIR filter type and IIR filter type processing. Various sub-options are
available with each filter type, as described in the following sections.
10.5.1 FIR Filter Type
To select the FIR filter type clear FCSR[FLT] and perform the processing shown in
Figure 10-7 based on the equation shown below. The EFCOP takes an input, x(n), from
N
w(n )
Ê Bi x ( n ± i )
i
0
the FDIR, saves the input while shifting the previous inputs down in the FDM, multiplies
each input in the FDM by the corresponding coefficient, Bi, stored in the FCM,
accumulates the multiplication results, and places accumulation result, w(n), in the FDOR.
This is done for each sample input to the FDIR.
FDIR
FDM
FCM
x(n)
B0
x(n-1)
B1
x(n-2)
B2
x(n-N)
BN
FDOR
Figure 10-7. FIR Filter Type Processing
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Operation Summary
There are four operating modes available with the FIR filter type: real, complex,
alternating complex, and magnitude mode.
10.5.1.1 Real Mode
Real mode performs FIR type filtering with real data and is selected by clearing both FOM
bits in the FCSR. One sample, the real input, is written to the FDIR, and the EFCOP
processes the data. Then one sample, the real output, is read from the FDOR. Two other
options are available with the real FIR filter type: adaptive and multichannel modes. These
modes can be used individually or together.
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10.5.1.1.1 Adaptive Mode
Adaptive mode provides a way to update the coefficients based on filter input, x(n), using
the following equation,
hn 1 ( i )
hn ( i ) Ke ( n ) x ( n ± i )
where hn(i) is the ith coefficient at time n. The coefficients are updated when
FSCR[FUPD] is set. The EFCOP checks to see if a value has been written to the FKIR. If
no value is written, the EFCOP halts processing until a value is written to the FKIR. When
a value is written to the FKIR, the EFCOP updates all the coefficients based on the above
equation using the value in the FKIR for Ke(n). The EFCOP automatically clears
FSCR[FUPD] when the coefficient update is complete.
If the coefficients are to be updated after every input sample, Adaptive mode is enabled by
setting the FCSR[FADP]. In Adaptive mode, the EFCOP automatically sets the FUDP bit
after each input sample is processed. This allows for continuous processing using
interrupts that includes a filter session and a coefficient update session with minimal core
intervention.
10.5.1.1.2 Multichannel Mode
Multichannel mode allows several channels of data to be processed concurrently and is
selected by setting the FCSR[FMLC]. The number of channels to process is one plus the
number in the FDCH[FDCM] bits. For each time period, the EFCOP expects to receive
the samples for each channel sequentially. This is repeated for consecutive time periods.
Filtering can be done with the same filter or different filters for each channel by using the
FCSR[FSCO] bit. If FCSR[FSCO] is set, the same set of coefficients are used for all
channels. If FSCO is clear, the coefficients for each filter are stored sequentially in
memory for each channel.
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Operation Summary
10.5.1.1.3 Complex Mode
Complex mode performs FIR type filtering with complex data based on the following
equations:
N±1
Ê Re( H ( i )) ¼ Re ( D( n ± i) ) ± Im( H ( i )) ¼ Im( D( n ± i) )
Re ( F ( n ) )
i ± 01
N
Ê Re (H ( i ) ) ¼ Im ( D ( n ± i ) ) Im ( H ( i ) ) ¼ Re (D ( n ± i ) )
Im ( F ( n ) )
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i
0
where H(n) is the coefficients, D(n) is the input data, and F(n) is the output data at time n.
Two samples, the real part then the imaginary part of the input, are written to the FDIR.
The EFCOP processes the data, and then two samples—the real and then the imaginary
part of the output—are read from the FDOR.
Complex mode is selected by setting the FCSR[FOM] bits to 01. In Complex mode, the
number written to the FCNT register should be twice the number of filter coefficients.
Also, the coefficients are stored in the FCM with the real part of the coefficient in the
memory location preceding the memory location holding the imaginary part of the
coefficient.
10.5.1.1.4 Alternating Complex Mode
Alternating Complex mode performs FIR type filtering with complex data, providing
alternating real and complex results based on the following equations
N±1
Re ( F ( n
even
Ê Re ( H ( i ) ) ¼ Re( D( n ± i ) ) ± Im ( H ( i ) ) ¼ Im( D( n ± i ) )
))
i 0
N±1
Im ( F ( n
odd
Ê Re ( H ( i ) ) ¼ Im ( D ( n ± i ) ) Im( H( i ) ) ¼ Re ( D ( n ± i ) )
))
i
0
where H(n) is the coefficients, D(n) is the input data, and F(n) is the output data at time n.
Two samples, the real part then the imaginary part of the input, are written to the FDIR.
The EFCOP processes the data. Then one sample, alternating between the real part and the
imaginary part of the output, is read from the FDOR.
Alternating Complex mode is selected by setting the FCSR[FOM] bits to 10. In
Alternating Complex mode, the number written to the FCNT register should be twice the
number of filter coefficients. Also, the coefficients should be stored in the FCM with the
real part of the coefficient in the memory location preceding the memory location holding
the imaginary part of the coefficient.
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Operation Summary
10.5.1.1.5 Magnitude Mode
Magnitude mode calculates the magnitude of an input signal based on the following
equation:
N±1
Ê D(n ± i)
F( n)
i
2
0
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where D(n) is the input data and F(n) is the output data at time n. One sample, the real
input, is written to the FDIR. The EFCOP processes the data. Then one sample, the real
magnitude of the input signal, is read from the FDOR. Magnitude mode is selected by
setting both the FCSR[FOM] bits.
10.5.1.1.6 Initialization
Before the first sample is processed, the EFCOP filter must be initialized; that is, the input
samples for times before n = 0 (assuming that time starts at 0) must be loaded into the
FDM. The number of samples needed to initialize the filter is the number of filter
coefficients minus one. To select Initialization mode, clear the FCSR[FPRC] bit. If
FCSR[FPRC] is set, initialization is disabled and the EFCOP assumes that the core wrote
the initial input values to the FDM before the EFCOP was enabled. Thus, the first value
written to FDIR is the first sample to be filtered.
If FCSR[FPRC] is clear, initialization mode is enabled and the EFCOP initializes the
FDM by receiving the number of coefficients minus one samples through the FDIR. After
samples are loaded, the next value written to the FDIR is the first sample to be filtered.
10.5.1.1.7 Decimation
Decimation is another option that can be used with any four of the modes available with
the FIR filter type. Decimation cannot be used in conjunction with Adaptive and
Multichannel modes. Decimation decreases (downsamples) the sampling rate. The
decimation ratio defines the number of input samples per output sample. The decimation
ratio is one plus the number in the FDCH[FDCM] bits. The decimation ratio can be
programmed from 1 to 16.
For Real and Magnitude modes the decimation ratio number of samples must be written to
the FDIR before an output sample is read from the FDOR. For Complex mode, two times
the decimation ratio number of samples (one for the real part and one for the imaginary
part of the input) must be written to the FDIR before two output samples (one for the real
part and one for the imaginary part of the output) can be read from the FDOR. For
Alternating Complex mode, two times the decimation ratio number of samples must be
written to the FDIR (one for the real part and one for the imaginary part of the input)
before one output sample (alternating between the real part and the imaginary part of the
output) can be read from the FDOR.
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Operation Summary
10.5.2 IIR Filter Type
To select the IIR filter type, set the FCSR[FLT] bit and perform the processing shown in
Figure 10-8 based on the equation shown here. The EFCOP multiplies each previous
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y(n )
Ë
S ÌÌ w ( n )
Í
M
Ê Aj y ( n ±
j
1
Û
j )ÜÜ
Ý
output value in the FDM by the corresponding coefficient, A, stored in the FCM;
accumulates the multiplication results; adds the input, w(n), from the FDIR (which is
optionally not scaled by S, depending on the FACR[FISL] bit setting); places the
accumulation result, y(n), in the FDOR; and saves the output while shifting the previous
outputs down in the FDM. This is done for each sample input to the FDIR. To process a
complete IIR filter, a FIR filter type session followed by an IIR filter type session is
needed.
FDM
FCM
y(n-1)
A0
y(n-2)
A1
y(n-3)
A2
FDOR
FDIR
y(n-N)
AN
Figure 10-8. IIR Filter Type Processing
Real mode is one of two operating modes available with the IIR filter type. Thus, the
FCSR[FOM] bits are ignored when the IIR filter type is in use. Real mode performs IIR
type filtering with real data. One sample, the real input, is written to the FDIR, and the
EFCOP processes the data. Then one sample, the real output, is read from the FDOR.
Another option available for the IIR filter type is Multichannel mode. Multichannel mode
for IIR filter type works exactly the same as it does for FIR filter type, as explained in
Section 10.5.1.1.2, "Multichannel Mode," on page 10-17. Decimation and Adaptive
modes are not available with the IIR filter type. Initialization is always disabled with the
IIR filter type, and the FCSR[FPRC] bit is ignored. Thus, the DSP56300 core must write
the initial input values before the EFCOP is enabled. The first value written to FDIR is
always the first sample to be filtered.
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Data Transfer
10.6 Data Transfer
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This section describes how to transfer data to and from the EFCOP using an FIR filter
configuration. Here, we provide background information to help you understand the
examples in Section 10.7, "Examples of Use in Different Modes," on page 10-22. The
examples employ the following notations:
■
D(n): Data sample at time n
■
H(n): Filter coefficient at time n
■
F(n): Output result at time n
■
#filter_count: Number of coefficient values in the coefficient memory bank FCM;
it is equal to the initial value written to the FCNT register plus 1.
■
Compute: Perform all calculations to determine one filter output F(n) for a specific
set of input data samples
To transfer data to/from the EFCOP input/output registers, the Filter Data Input Register
(FDIR) and the Filter Data Output Register (FDOR) are triggered by three different
methods:
■
Direct Memory Access (DMA)
■
Interrupts
■
Polling
Two FCSR bits (FDIBE and FDOBF) indicate the status of the FDIR and the FDOR,
respectively. All three data transfer methods use these two FCSR bits as their control
mechanism. If FDIBE is set, the input buffer is empty; if FDOBF is set, the output buffer
is full. Because these bits come into full operation only when the EFCOP is enabled
(FCSR:FEN is set), the polling, DMA, or interrupt methods can be initialized either before
or after the EFCOP is enabled. No service request is issued until the EFCOP is enabled,
since FDIBE and FDOBF are cleared while the EFCOP is in the Individual Reset state.
The most straightforward EFCOP data transfer method uses the core processor to poll the
status flags, monitoring for input/output service requests. The disadvantage of this
approach is that it demands large amounts of (if not all of) the core’s processing time. The
interrupt and DMA methods are more efficient in their use of the core processor.
Interrupts intervene on the core processor infrequently to service input/output data.
DMA can operate concurrently with the processor core and demands only minimal core
resource for setup. DMA transfers are recommended when the EFCOP is in FIR/IIR
filtering mode since the core can operate independently of the EFCOP while DMA
transfers data to the FDIR and from the FDOR. Since the EFCOP input buffer (FDIR) is
four words deep, the DMA can input in blocks of up to four words. A combination of
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Examples of Use in Different Modes
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DMA transfer for input and an interrupt request for processing the output is recommended
for adaptive FIR mode. This combination gives the following benefits:
■
Input data transfers to the FDIR can occur independently of the core.
■
There is minimal intervention of the core while the weight update multiplier is
updated.
If the initialization mode is enabled (that is, if the FCSR[FPRC] bit is cleared), the core
can initialize the coefficient bank while the DMA controller concurrently transfers initial
data values to the data bank. The EFCOP state machine starts computation as soon as
#filter_count data samples are input. If no initialization mode is used (the FCSR[FPRC]
bit is set), the EFCOP starts computation as soon as the first data sample is available in the
input buffer. The filter coefficient bank must therefore be initialized before an input data
transfer starts. The DMA input channel can continue transferring data whenever the input
FIFO becomes empty, while the EFCOP state machine takes data words from the FIFO
whenever required.
10.7 Examples of Use in Different Modes
The following sections provide examples of how to use the EFCOP in Real FIR Filter
(Mode 0) and Adaptive FIR filter mode.
10.7.1 Real FIR Filter: Mode 0
In this example, an N tap FIR filter is represented as follows:
N±1
ÊHi
F(n)
( )¼
i
D( n ± i )
0
The filter is implemented with three different data transfers using the EFCOP in data
initialization mode:
1. DMA input/DMA output
2. DMA input/Polling output
3. DMA input/Interrupt output
This transfer combination is only one of many possible combinations.1
1.For information on DMA transfers, refer to the Motorola application note entitled Using the DSP56300
Direct Memory Access Controller (APR23/D).
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Examples of Use in Different Modes
10.7.1.1 DMA Input/DMA Output
A 20-tap FIR filter using a 28-input sample signal is implemented in the following stages:
Setup:
1. Set the filter count register (FCNT) to the length of the filter coefficients –1 (i.e
N-1).
2. Set the Data and Coefficient Base Address pointers (FDBA, FCBA).
3. Set the operation mode (FCSR[5:4] = FOM[00]).
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4. Set Initialization mode (FCSR[7] = FPRC = 0).
5. Set DMA registers:
DMA input: A two-dimensional (2D) DMA transfer fills up the FDM bank via
channel 0. The DMA input control registers are initialized as shown in Table
10-10.
Table 10-10. DMA Channel 0 Regisister Initialization
Register Setting
DCR0 bit values are as follows:
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Description
DMA Control Register 0
DIE = 0
Disables end-of-transfer interrupt.
DTM = 2
Chooses line transfer triggered by request; DE auto clear
on end of transfer.
DPR = 2
Priority 2
DCON = 0
Disables continuous mode.
DRS = $15
Chooses DMA to trigger on EFCOP input buffer empty.
D3D = 0
Chooses non-3D mode.
DAM = $20
Sets the following DMA Address Mode:
■ source address - 2D
■ counter mode B
■ offset DOR0
■ destination address - no update, no offset
DDS = 1
Destination in Y memory space (because the EFCOP is in
Y memory).
DSS = 0
Source in X memory space.
DOR0=1
DMA Offset Register 0
DCO0= $006003
DMA Counter Register 0
Gives transfer of 7 * 4 = 28 items (input sequence length).
DSR0 = Address of source data
DMA Source Address Register 0
DDR0 = $FFFFB0
DMA Destination Address Register for Channel 0
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Examples of Use in Different Modes
■
DMA output: Channel 1 is used, with a configuration similar to that of the DMA
input channel, except for a 1D transfer. The DMA output control registers are
initialized as shown in Table 10-11.
Table 10-11. DMA Channel 1 Register Initialization
Register Setting
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DCR1 bit values are as follows:
Note:
Description
DMA Control Register 1
DIE = 0
Disables end-of-transfer interrupt.
DTM = 1
Chooses word transfer triggered by request, DE auto clear
on end of transfer.
DPR = 3
Priority 3.
DCON = 0
Disables continuous mode.
DRS = $16
Chooses DMA to trigger on EFCOP output buffer full.
D3D = 0
Chooses non-3D mode.
DAM = $2C
Sets the following DMA address mode
■ source address - no update, no offset
■ destination address - 1D, post-increment by 1, no
offset.
DDS = 0
Destination in X memory space.
DSS = 1
Source in Y memory space (because EFCOP is in Y
memory).
DCO1 = $12
DMA Counter Register 1
Gives transfer of 9 items.
DSR1 = address of FDOR =
$FFFFFB1
DMA Source Address Register 1
DDR1 = address of destination
memory space
DMA Destination Address Register 1
Setting the DCO0 and DCO1 must be considered carefully. These registers
must be loaded with one less than the number of items to be transferred. Also,
the following equality must hold: DCO1=input length - filter length.
6. Initialization:
— Enable DMA channel 1 (output) DCR1[23] DE=1
— Enable EFCOP FCSR[0] FEN=1
— Enable DMA channel 0. (input) DCR0[23] DE=1
7. Processing:
— Whenever the Input Data Buffer (FDIR) is empty (that is, FDIBE = 1), the
EFCOP triggers DMA input to transfer up to four new data words to FDIR.
— Compute F(n); The result is stored in FDOR, and this triggers the DMA for an
output data transfer.
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Examples of Use in Different Modes
Note:
The filter coefficients are stored in “reverse order,” as Figure 10-9 shows.
D(0)
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Data
Memory
Bank
(FDM)
D(1)
D(2)
D(3)
D(4)
D(5)
-
H(N - 1)
Output Data
Stream
F(0)
F(1)
F(2)
F(3)
F(4)
F(5)
-
H(N - 2)
H(1)
H(0)
Coefficient
Memory
Bank
(FCM)
Figure 10-9. Real FIR Filter Data stream
Example 10-1. Real FIR Filter Using DMA Input/DMA Output
INCLUDE ’ioequ.asm’
;;******************************************************************
; equates
;;******************************************************************
Start
equ
$00100
; main program starting address
FCON
equ
$001
; EFCOP FSCR register contents:
; enable the EFCOP
FIR_LEN
equ
20
; EFCOP FIR length
SRC_ADDRS
equ
$3040;
; DMA source address point to DATA bank
DST_ADDRS
equ
$3000
; address at which to begin output
SRC_COUNT
equ
$006003
; DMA0 count (7*4 word transfers)
DST_COUNT
equ
8
; number of outputs generated.
FDBA_ADDRS
equ
0
; Input samples Start Address x:$0
FCBA_ADDRS
equ
0
; Coeff. Start Address y:$0
;;******************************************************************
; main program
;;******************************************************************
ORG
p:Start
move
#FDBA_ADDRS,r0
; FDM memory area
move
#0,x0
rep
#DST_COUNT
move
x0,x:(r0)+
; clear FDM memory area
; ** DMA channel 1 initialisation - output from EFCOP **
movep
#M_FDOR,x:M_DSR1
; DMA source address points to the EFCOP FDIR
movep
#DST_ADDRS,x:M_DDR1 ; Init DMA destination address.
movep
#DST_COUNT,x:M_DCO1 ; Init DMA count.
movep
#$8EB2C1,x:M_DCR1
; Start DMA 1 with FDOBF request.
; ** EFCOP initialisation **
movep
#FIR_LEN-1,y:M_FCNT ; FIR length
movep
#FDBA_ADDRS,y:M_FDBA ; FIR input samples Start Address
movep
#FCBA_ADDRS,y:M_FCBA ; FIR Coeff. Start Address
movep
#FCON,y:M_FCSR
; Enable EFCOP
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Examples of Use in Different Modes
; ** DMA channel 0 initialisation - input to EFCOP **
movep
#SRC_ADDRS,x:M_DSR0 ; DMA source address points to the DATA bank.
movep
#M_FDIR,x:M_DDR0
; Init DMA destination address.
movep
#SRC_COUNT,x:M_DCO0 ; Init DMA count to line mode.
movep
#$1,x:M_DOR0
; DMA offset reg. is 1.
movep
#$94AA04,x:M_DCR0
; Init DMA control reg to line mode FDIBE
request.
nop
nop
;;******************************************************************
jclr #0,x:M_DSTR,*
jclr #1,x:M_DSTR,*
nop
nop
stop_label
nop
jmp stop_label
org x:SRC_ADDRS
INCLUDE ‘input.asm’
org y:FCBA_ADDRS
INCLUDE ‘coefs.asm’
10.7.1.2 DMA Input/Polling Output
The different stages of input/polling are as follows:
1. Setup:
— Set the filter count register (FCNT) to the length of the filter coefficients –1 (i.e
N-1).
— Set the data and coefficient base address pointers (FDBA, FCBA).
— Set the operation mode (FCSR[5:4] = FOM[00],), = 1).
— Set the initialization mode (FCSR[7] = FPRC = 0).
— Set DMA registers: DMA input: as per channel 0 in Section 10.7.1.1
2. Initialization:
— Enable EFCOP FCSR[0] FEN=1.
— Enable DMA input channel, DCR0[23] DE=1.
3. Processing:
— Whenever the Input Data Buffer (FDIR) is empty (that is, FDIBE = 1), the
EFCOP triggers DMA input to transfer up to four new data words to FDM via
FDIR.
— Compute F(n); the result is stored in FDOR.
— The core keeps polling the FCSR[FDOBF] bit and stores the data in memory.
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Example 10-2. Real FIR Filtering using DMA input/Polling output
INCLUDE ’ioequ.asm’
;;******************************************************************
; equates
;;******************************************************************
Start
equ
$00100
; main program starting address
FCON
equ
$001
; EFCOP FSCR register contents:
; enable the EFCOP
FIR_LEN
equ
20
; EFCOP FIR length
SRC_ADDRS
equ
$3040 ; DMA source address point to DATA bank
DST_ADDRS
equ
$3000 ; address at which to begin output
SRC_COUNT
equ
$006003 ; DMA0 count (7*4 word transfers)
DST_COUNT
equ
8
; number of outputs generated.
FDBA_ADDRS
equ
0
; Input samples Start Address x:$0
FCBA_ADDRS
equ
0
; Coeff. Start Address y:$0
;;******************************************************************
; main program
;;******************************************************************
ORG
p:Start
move
#0,b
move
#0,a
move
#DST_COUNT,b0
move
#FDBA_ADDRS,r0
move
#0,x0
rep
#DST_COUNT
move
x0,x:(r0)+
move
#DST_ADDRS,r0
; ** EFCOP initialisation **
movep
#FIR_LEN-1,y:M_FCNT
movep
#FDBA_ADDRS,y:M_FDBA
movep
#FCBA_ADDRS,y:M_FCBA
movep
#FCON,y:M_FCSR
; counter for output interrupt
; FDM memory area
; clear FDM memory area
; Destination address
;
;
;
;
FIR length
FIR input samples Start Address
FIR Coeff. Start Address
Enable EFCOP
; ** DMA channel 0 initialisation - input to EFCOP **
movep
#SRC_ADDRS,x:M_DSR0 ; DMA source address points to the DATA bank.
movep
#M_FDIR,x:M_DDR0
; Init DMA destination address.
movep
#SRC_COUNT,x:M_DCO0 ; Init DMA count to line mode.
movep
#$1,x:M_DOR0
; DMA offset reg. is 1.
movep
#$94AA04,x:M_DCR0
; Init DMA control reg to line mode FDIBE
request.
nop
nop
;;******************************************************************
do
#DST_COUNT,endd
nop
jclr #15,y:M_FCSR,*
movep y:M_FDOR,x:(r0)+
endd
nop
nop
stop_label
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Examples of Use in Different Modes
nop
jmp stop_label
org x:SRC_ADDRS
INCLUDE ‘input.asm’
org y:FCBA_ADDRS
INCLUDE ‘coefs.asm’
10.7.1.3 DMA Input/Interrupt Output
The different stages of DMA input and interrupt output are as follows:
Freescale Semiconductor, Inc...
1. Setup:
— Set the filter count register (FCNT) to the length of the filter coefficients –1 (i.e
N-1).
— Set the Data and Coefficient Base Address pointers (FDBA, FCBA).
— Set the operation mode (FCSR[5:4] = FOM[00],).
— Set Initialization mode (FCSR[7] = FPRC = 0).
— Set Filter Data Output Interrupt Enable FSCR[11]=FDOIE=1.
— Set DMA register with DMA input as per channel 0 in Section 10.7.1.1.
2. Initialization:
— Enable interrupts in the Interrupt Priority Register IPRP[10:11]=E0L=11.
–
–
–
Enable interrupts in the Status Register SR[8:9]=00.
Enable EFCOP FCSR[0]=FEN=1.
Enable the DMA input channel, DCR0[23]=DE=1.
3. Processing:
— Whenever the Input Data Buffer (FDIR) is empty (that is, FDIBE = 1), the
EFCOP triggers DMA, which loads the next input into the FDIR.
— Compute F(n); the result is stored in FDOR; The core is interrupted when
FDOBF is set and stores the data in memory.
Example 10-3. Real FIR Filter DMA Input/Interrupt Output
INCLUDE ’ioequ.asm’
;;******************************************************************
; equates
;;******************************************************************
Start
equ
$00100
; main program starting address
FCON
equ
$801
; EFCOP FSCR register contents:
; enable output interrupt
; enable the EFCOP
FIR_LEN
equ
20
; EFCOP FIR length
SRC_ADDRS equ
$3040
; DMA source address point to DATA bank
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DST_ADDRS equ
$3000
; address at which to begin output
SRC_COUNT equ
$006003
; DMA0 count (7*4 word transfers)
DST_COUNT equ
8
; number of outputs generated.
FDBA_ADDRS equ
0
; Input samples Start Address x:$0
FCBA_ADDRS equ
0
; Coeff. Start Address y:$0
;;******************************************************************
org P:$0
jmp
Start
ORG
p:$6a
jsr
>kdo
nop
nop
;;******************************************************************
; main program
;;******************************************************************
ORG
p:Start
; ** interrupt initialisation **
bset
#10,x:M_IPRP
bset
#11,x:M_IPRP
bclr
#8,SR
bclr
#9,SR
move
#0,b
move
#0,a
move
#DST_COUNT,b0
move
#FDBA_ADDRS,r0
move
#0,x0
rep
#DST_COUNT
move
x0,x:(r0)+
move
#DST_ADDRS,r0
; ** EFCOP initialisation **
movep
#FIR_LEN-1,y:M_FCNT
movep
#FDBA_ADDRS,y:M_FDBA
movep
#FCBA_ADDRS,y:M_FCBA
movep
#FCON,y:M_FCSR
;
; enable EFCOP interrupts in IPRP
;
; enable interrupts in SR
; counter for output interrupt
; FDM memory area
; clear FDM memory area
; Destination address
;
;
;
;
FIR length
FIR input samples Start Address
FIR Coeff. Start Address
Enable EFCOP
; ** DMA channel 0 initialisation - input to EFCOP **
movep
#SRC_ADDRS,x:M_DSR0 ; DMA source address points to the DATA bank.
movep
#M_FDIR,x:M_DDR0
; Init DMA destination address.
movep
#SRC_COUNT,x:M_DCO0 ; Init DMA count to line mode.
movep
#$1,x:M_DOR0
; DMA offset reg. is 1.
movep
#$94AA04,x:M_DCR0
; Init DMA control reg to line mode FDIBE
request.
nop
nop
;;******************************************************************
wait1
jset
#11,y:M_FCSR,*
; Wait until FDOIE is cleared.
do
#40,endd
nop
endd
nop
nop
stop_label
nop
jmp stop_label
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Examples of Use in Different Modes
;;******************************************************************
kdo
; Interrupt handler for EFCOP output
movep
y:M_FDOR,x:(r0)+ ; Get y(k) from FDOR
; Store in destination memory space.
nop
dec
b
jne
cont
nop
bclr
#11,y:M_FCSR
; Disable output interrupt
cont
rti
nop
nop
nop
org
x:SRC_ADDRS
INCLUDE
‘input.asm’
org
INCLUDE
y:FCBA_ADDRS
‘coefs.asm’
10.7.2 Real FIR Filter With Decimation by M
An N tap real FIR filter with decimation by M of a sequence of real numbers is
represented by,
N±1
F(n
Ê H(i)
)
M
i
¼
D(n ± i)
0
A DMA data transfer occurs in the following stages for both input and output.The stages
are the similar to the ones described in Section 10.7.1.1. The difference is: set
FDCH[11:8] = FDCM =M.
Processing:
1. Whenever the Input Data Buffer (FDIR) is empty (that is, FDIBE = 1), the EFCOP
triggers DMA input to transfer up to four new data words to FDM via FDIR.
2. Compute F(n); the result is stored in FDOR; the EFCOP triggers DMA output for
an output data transfer.
3. Repeat M times:
{
Get new data word; EFCOP increments data memory pointer.
}
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D(0)
Freescale Semiconductor, Inc...
Data
Memory
Bank
(FDM)
H(N - 1)
Output Data
Stream
D(1)
D(2)
D(3)
D(4)
D(5)
-
H(N - 2)
H(1)
H(0)
F(0)
F(M)
F(2M)
F(3M)
F(4M)
-
Coefficient
Memory
Bank
(FCM)
Figure 10-10. Real FIR Filter Data Stream With Decimation by M
10.7.3 Adaptive FIR Filter
An adaptive FIR filter is represented in Figure 10-11. The goal of the FIR filter is to
adjust the filter coefficients so that the output, F(n), becomes as close as possible to the
desired signal, R(n)—that is, E(n) -> 0.
R(n)
D(n)
F(n)
Adaptive
FIR Filter
Filter Update
E(n)
Figure 10-11. Adaptive FIR Filter
The adaptive FIR filter typically comprises four stages, which are performed for each
input sample at time n:
■
Stage 1. The FIR filter output value is calculated for the EFCOP FIR session
according to this equation:
N±1
Ê Hn i D n ± i
F( n)
( )
i
(
)
0
where Hn(i) are the filter coefficients at time n, D(n) is the input signal and F(n) is
the filter output at time n. This stage requires N MAC operations, calculated by the
EFCOP FMAC unit.
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■
Stage 2. The core calculates the error signal, E(n), in software according to the
following equation:
E( n)
R( n ) ± F( n)
where R(n) is the desired signal at time n. This stage requires a single arithmetic
operation.
Freescale Semiconductor, Inc...
■
Stage 3. The core calculates the weight multiplier, Ke(n), in software according to
the following equation:
Ke(n) = K * E(n)
where K is the convergence factor of the algorithm. After calculating the weight
multiplier, Ke, the core must write it into the FKIR.
■
Stage 4. The coefficients are updated by the EFCOP update session:
Hn 1 ( i )
H n ( i ) Ke D ( n ± i )
where Hn+1(i) are the adaptive filter coefficients at time n+1, Ke(n) is the weight
multiplier at time n, and D(n) is the input signal. This stage starts immediately after
Ke(n) is written in the FKIR (if Adaptive mode is enabled).
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Examples of Use in Different Modes
10.7.3.1 Implementation Using Polling
Figure 10-12 shows a flowchart for an adaptive FIR filter that uses polling to transfer
data.
Freescale Semiconductor, Inc...
Start
Set FCNT=N-1
Set FDBA, FCBA
Calculate Ke
Enable EFCOP
(ADP) Real FIR Mode
Write Ke to FKIR
Write next x(n)
Set FUPD = 1
No
(opt.)
Automatically
Done in ADP Mode
Output Buffer
Full?
Yes
Read y(n)
Block
Done?
No
Yes
End
Figure 10-12. Adaptive FIR Filter Using Polling
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Examples of Use in Different Modes
10.7.3.2 Implementation Using DMA Input and Interrupt Output
Figure 10-13 shows a flowchart for an adaptive FIR filter that uses DMA and an interrupt
to transfer data.
Start
Output Buffer
Full
Interrupt
Set DMA/Int for input
on FDIBE
Freescale Semiconductor, Inc...
Set FCNT=L-1
Set FDBA, FCBA
Read y(n)
Enable EFCOP
ADP Real FIR Mode
Calculate Ke
Block
Done?
No
Write Ke to FKIR
Yes
Set FUPD = 1
End
(opt.)
Automatically
Done in ADP Mode
RTI
Figure 10-13. Adaptive FIR Filter Using DMA Input and Interrupt Output
10.7.3.3 Updating an FIR Filter
The following example shows an FIR adaptive filter that is updated using the LMS
algorithm.
Example 10-4. FIR Adaptive Filter Update Using the LMS Algorithm
TITLE ’ADAPTIVE’
INCLUDE ’ioequ.asm’
;;**************************************************************************************
; equates
;;**************************************************************************************
Start
equ
$00100
; main program starting address
FCON
equ
$805
; EFCOP FSCR register contents:
; enable output interrupt
; Choose adaptive real FIR mode
; enable the EFCOP
FIR_LEN
Motorola
equ
20
; EFCOP FIR length
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DES_ADDRS
SRC_ADDRS
DST_ADDRS
SRC_COUNT
DST_COUNT
MU2
FDBA_ADDRS
FCBA_ADDRS
equ
equ
equ
equ
equ
equ
equ
equ
$3200
$3100
$3000
$06003
8
$100000
0
0
;
;
;
;
;
;
;
;
Desired signal R(n)
Reference signal D(n)
address at which to begin output (signal F(n))
DMA0 count (7*4 word transfers)
number of outputs generated.
stepsize mu = 0.0625 (that is 2mu = 0.125)
Input samples Start Address x:$0
Coeff. Start Address y:$0
;;**************************************************************************************
org p:$0
jmp
Start
Freescale Semiconductor, Inc...
ORG p:$6a
jsr
nop
nop
>kdo
;;**************************************************************************************
; main program
;;**************************************************************************************
ORG p:Start
; ** interrupt initialisation **
bset
bset
#10,x:M_IPRP
#11,x:M_IPRP
;
; enable EFCOP interrupts in IPRP
bclr
bclr
#8,SR
#9,SR
;
; enable interrupts in SR
move
move
move
#0,b
#0,a
#DST_COUNT,b0
; counter for output interrupt
; ** FDM memory initialisation **
move
move
rep
move
#FDBA_ADDRS,r0
#0,x0
#FIR_LEN
x0,x:(r0)+
; FDM memory area
; clear FDM memory area
; ** address register initialisation **
move
move
#DST_ADDRS,r0
#DES_ADDRS,r1
; Destination address
; Desired signal address
rep
move
#FIR_LEN-1
(r1)+
; Set reference pointer correctly
; ** EFCOP initialisation **
movep
movep
movep
Motorola
#FIR_LEN-1,y:M_FCNT
#FDBA_ADDRS,y:M_FDBA
#FCBA_ADDRS,y:M_FCBA
; FIR length
; FIR input samples Start Address
; FIR Coeff. Start Address
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Examples of Use in Different Modes
movep
#FCON,y:M_FCSR
; Enable EFCOP
; ** DMA channel 0 initialisation - input to EFCOP **
movep
movep
movep
movep
movep
#SRC_ADDRS,x:M_DSR0
#M_FDIR,x:M_DDR0
#SRC_COUNT,x:M_DCO0
#$1,x:M_DOR0
#$94AA04,x:M_DCR0
;
;
;
;
;
DMA source address points to the DATA bank.
Init DMA destination address.
Init DMA count to line mode.
DMA offset reg. is 1.
Init DMA control reg to line mode FDIBE
request.
Freescale Semiconductor, Inc...
nop
nop
;;******************************************************************
wait1
jset
#11,y:M_FCSR,*
; Wait until FDOIE is cleared.
do
#40,endd
nop
endd
nop
nop
stop_label
nop
jmp stop_label
;;******************************************************************
kdo
; Interrupt handler for EFCOP output
movep
y:M_FDOR,x:(r0)
; Get F(n) from FDOR
; Store in destination memory space.
;******* Calculate Ke *********
move
x:(r1)+,a
; Retrieve desired value R(n)
move
sub
x:(r0)+,y0
y0,a
;
; calculate E(n) = R(n) - F(n)
move
move
mpy
#MU2,y0
a,y1
y0,y1,a
;
;
; calculate Ke = mu * 2 * E(n)
;******************************
movep
a1,y:M_FKIR
dec
jne
nop
bclr
; store Ke in FKIR
b
cont
#11,y:M_FCSR
; Disable output interrupt
cont
rti
nop
nop
nop
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;;******************************************************************
;;******************************************************************
ORG y:FCBA_ADDRS
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
dc
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
$000000
ORG x:SRC_ADDRS
INCLUDE ’input.asm’; Reference signal D(n)
ORG x:DES_ADDRS
INCLUDE ’desired.asm’; Desired signal R(n)
10.8 Verification For All Exercises
10.8.1 Input Sequence (input.asm)
dc
$000000
dc
$37cc8a
dc
$343fae
dc
$0b63b1
dc
$0595b4
dc
$38f46e
dc
$6a4ea2
dc
$5e8562
dc
$2beda5
dc
$1b3cd0
dc
$42f452
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Verification For All Exercises
dc
$684ca0
dc
$5093b0
dc
$128ab8
dc
$f74ee1
dc
$15c13a
dc
$336e48
dc
$15e98e
dc
$d428d2
dc
$b76af5
dc
$d69eb3
dc
$f749b6
dc
$dee460
dc
$a43601
dc
$903d59
dc
$b9999a
dc
$e5744e
10.8.2 Filter Coefficients (coefs.asm)
dc
$F8125C
dc
$F77839
dc
$F4E9EE
dc
$F29373
dc
$F2DC9A
dc
$F51D6E
dc
$F688CE
dc
$F6087E
dc
$F5B5D3
dc
$F7E65E
dc
$FBE0F8
dc
$FEC8B7
dc
$FF79F5
dc
$000342
dc
$02B24F
dc
$06C977
dc
$096ADD
dc
$097556
dc
$08FD54
dc
$0A59A5
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Verification For All Exercises
10.8.3
Output Sequence for Examples D-1, D-2, and D-3
$d69ea9
$ccae36
$c48f2a
$be8b28
$bad8c5
$b9998c
$bad8cb
$be8b2d
Freescale Semiconductor, Inc...
$c7b906
10.8.4 Desired Signal for Example D-4
dc
$000000
dc
$0D310F
dc
$19EA7C
dc
$25B8E2
dc
$30312E
dc
$38F46D
dc
$3FB327
dc
$443031
dc
$4642D6
dc
$45D849
dc
$42F452
dc
$3DB126
dc
$363E7F
dc
$2CDFE8
dc
$21EA5B
dc
$15C13A
dc
$08D2CE
dc
$FB945D
dc
$EE7E02
dc
$E2066F
dc
$D69EB2
dc
$CCAE3C
dc
$C48F2F
dc
$BE8B32
dc
$BAD8D3
dc
$B99999
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Verification For All Exercises
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Appendix B
Programming Reference
This reference for programmers includes a table showing the addresses of all DSP
memory-mapped peripherals, an exception priority table, and programming sheets for the
major programmable DSP registers. The programming sheets are grouped in the following
order: central processor, Phase Lock Loop, (PLL), Host Interface (HI08), Enhanced
Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer,
GPIO, and EFCOP. Each sheet provides room to write in the value of each bit and the
hexadecimal value for each register. You can photocopy these sheets and reuse them for
each application development project. For details on the instruction set of the DSP56300
family of DSPs, see the DSP56300 Family Manual.
■
Table B-2, “Internal X I/O Memory Map,” on page B-2 and Table B-3, “Internal
Y I/O Memory Map,” on page B-7 list the memory addresses of all on-chip
peripherals.
■
Table B-4, “Interrupt Sources,” on page B-8 lists the interrupt starting addresses
and sources.
■
Table B-5, “Interrupt Source Priorities Within an IPL,” on page B-10 lists the
priorities of specific interrupts within interrupt priority levels.
■
The programming sheets appear in this manual as figures (listed in Table B-1);
they show the major programmable registers on the DSP56311.
Table B-1. Guide to Programming Sheets
Module
Central
Processor
PLL
Motorola
Programming Sheet
Page
Figure B-1, "Status Register (SR)"
page B-12
Figure B-2, "Operating Mode Register"
page B-13
Figure B-3, "Address Attribute Registers (AAR3 - AAR0)"
page B-14
Figure B-4, "Bus Control Register (BCR)"
page B-15
Figure B-5, "DMA Control Register (DCR)"
page B-16
Figure B-6, "Interrupt Priority Register–Core (IPR–C)"
page B-17
Figure B-7, "Interrupt Priority Register – Peripherals (IPR–P)"
page B-18
Figure B-8, "Phase Lock Loop Control Register (PCTL)"
page B-19
Programming Reference
For More Information On This Product,
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B-1
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Table B-1. Guide to Programming Sheets
HI08
Freescale Semiconductor, Inc...
ESSI
SCI
Timers
GPIO
EFCOP
Figure B-9, "Host Receive and Host Transmit Data Registers"
page B-20
Figure B-10, "Host Control and Host Status Registers"
page B-21
Figure B-11, "Host Base Address and Host Port Control Registers"
page B-22
Figure B-12, "Interrupt Control and Interrupt Status Registers"
page B-23
Figure B-13, "Interrupt Vector and Command Vector Registers"
page B-24
Figure B-14, "Host Receive and Host Transmit Data Registers"
page B-25
Figure B-15, "ESSI Control Register A (CRA)"
page B-26
Figure B-16, "ESSI Control Register B (CRB)"
page B-27
Figure B-17, "ESSI Status Register (SSISR)"
page B-28
Figure B-18, "ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)"
page B-29
Figure B-19, "SCI Control Register (SCR)"
page B-30
Figure B-20, "SCI Status and Clock Control Registers (SSR, SCCR)"
page B-31
Figure B-21, "SCI Receive and Transmit Data Registers (SRX, TRX)"
page B-32
Figure B-22, "Timer Prescaler Load/Count Register (TPLR, TPCR)"
page B-33
Figure B-23, "Timer Control/Status Register (TCSR)"
page B-34
Figure B-24, "Timer Load, Compare, Count Registers (TLR, TCPR, TCR)"
page B-35
Figure B-25, "Host Data Direction and Host Data Registers (HDDR, HDR)"
page B-36
Figure B-26, "Port C Registers (PCRC, PRRC, PDRC)"
page B-37
Figure B-27, "Port D Registers (PCRD, PRRD, PDRD)"
page B-38
Figure B-28, "Port E Registers (PCRE, PRRE, PDRE)"
page B-39
Figure B-29, "EFCOP Counter and Control Status Registers (FCNT and FCSR)"
page B-40
Figure B-30, "EFCOP FACR, FDBA, FCBA, and FDCH Registers"
page B-41
B.1 Internal I/O Memory Map
Table B-2. Internal X I/O Memory Map
Peripheral
16-Bit Address
24-Bit Address
IPR
$FFFF
$FFFFFF
Interrupt Priority Register Core (IPR-C)
$FFFE
$FFFFFE
Interrupt Priority Register Peripheral (IPR-P)
PLL
$FFFD
$FFFFFD
PLL Control Register (PCTL)
OnCE
$FFFC
$FFFFFC
OnCE GDB Register (OGDB)
B-2
Register Name
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Freescale Semiconductor, Inc...
Table B-2. Internal X I/O Memory Map (Continued)
Peripheral
16-Bit Address
24-Bit Address
BIU
$FFFB
$FFFFFB
Bus Control Register (BCR)
$FFFA
$FFFFFA
DRAM Control Register (DCR)
$FFF9
$FFFFF9
Address Attribute Register 0 (AAR0)
$FFF8
$FFFFF8
Address Attribute Register 1 (AAR1)
$FFF7
$FFFFF7
Address Attribute Register 2 (AAR2)
$FFF6
$FFFFF6
Address Attribute Register 3 (AAR3)
$FFF5
$FFFFF5
ID Register (IDR)
$FFF4
$FFFFF4
DMA Status Register (DSTR)
$FFF3
$FFFFF3
DMA Offset Register 0 (DOR0)
$FFF2
$FFFFF2
DMA Offset Register 1 (DOR1)
$FFF1
$FFFFF1
DMA Offset Register 2 (DOR2)
$FFF0
$FFFFF0
DMA Offset Register 3 (DOR3)
$FFEF
$FFFFEF
DMA Source Address Register (DSR0)
$FFEE
$FFFFEE
DMA Destination Address Register (DDR0)
$FFED
$FFFFED
DMA Counter (DCO0)
$FFEC
$FFFFEC
DMA Control Register (DCR0)
$FFEB
$FFFFEB
DMA Source Address Register (DSR1)
$FFEA
$FFFFEA
DMA Destination Address Register (DDR1)
$FFE9
$FFFFE9
DMA Counter (DCO1)
$FFE8
$FFFFE8
DMA Control Register (DCR1)
$FFE7
$FFFFE7
DMA Source Address Register (DSR2)
$FFE6
$FFFFE6
DMA Destination Address Register (DDR2)
$FFE5
$FFFFE5
DMA Counter (DCO2)
$FFE4
$FFFFE4
DMA Control Register (DCR2)
$FFE3
$FFFFE3
DMA Source Address Register (DSR3)
$FFE2
$FFFFE2
DMA Destination Address Register (DDR3)
$FFE1
$FFFFE1
DMA Counter (DCO3)
$FFE0
$FFFFE0
DMA Control Register (DCR3)
DMA
DMA0
DMA1
DMA2
DMA3
Motorola
Register Name
Programming Reference
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B-3
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Table B-2. Internal X I/O Memory Map (Continued)
Peripheral
16-Bit Address
24-Bit Address
DMA4
$FFDF
$FFFFDF
DMA Source Address Register (DSR4)
$FFDE
$FFFFDE
DMA Destination Address Register (DDR4)
$FFDD
$FFFFDD
DMA Counter (DCO4)
$FFDC
$FFFFDC
DMA Control Register (DCR4)
$FFDB
$FFFFDB
DMA Source Address Register (DSR5)
$FFDA
$FFFFDA
DMA Destination Address Register (DDR5)
$FFD9
$FFFFD9
DMA Counter (DCO5)
$FFD8
$FFFFD8
DMA Control Register (DCR5)
$FFD7
$FFFFD7
Reserved
$FFD6
$FFFFD6
Reserved
$FFD5
$FFFFD5
Reserved
$FFD4
$FFFFD4
Reserved
$FFD3
$FFFFD3
Reserved
$FFD2
$FFFFD2
Reserved
$FFD1
$FFFFD1
Reserved
$FFD0
$FFFFD0
Reserved
$FFCF
$FFFFCF
Reserved
$FFCE
$FFFFCE
Reserved
$FFCD
$FFFFCD
Reserved
$FFCC
$FFFFCC
Reserved
$FFCB
$FFFFCB
Reserved
$FFCA
$FFFFCA
Reserved
$FFC9
$FFFFC9
Host Port GPIO Data Register (HDR)
$FFC8
$FFFFC8
Host Port GPIO Direction Register (HDDR)
$FFC7
$FFFFC7
Host Transmit Register (HTX)
$FFC6
$FFFFC6
Host Receive Register (HRX)
$FFC5
$FFFFC5
Host Base Address Register (HBAR)
$FFC4
$FFFFC4
Host Port Control Register (HPCR)
$FFC3
$FFFFC3
Host Status Register (HSR)
$FFC2
$FFFFC2
Host Control Register (HCR)
Freescale Semiconductor, Inc...
DMA5
Port B
HI08
B-4
Register Name
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Table B-2. Internal X I/O Memory Map (Continued)
Peripheral
Port C
Freescale Semiconductor, Inc...
ESSI 0
Port D
Motorola
16-Bit Address
24-Bit Address
Register Name
$FFC1
$FFFFC1
Reserved
$FFC0
$FFFFC0
Reserved
$FFBF
$FFFFBF
Port C Control Register (PCRC)
$FFBE
$FFFFBE
Port C Direction Register (PRRC)
$FFBD
$FFFFBD
Port C GPIO Data Register (PDRC)
$FFBC
$FFFFBC
ESSI 0 Transmit Data Register 0 (TX00)
$FFBB
$FFFFBB
ESSI 0 Transmit Data Register 1 (TX01)
$FFBA
$FFFFBA
ESSI 0 Transmit Data Register 2 (TX02)
$FFB9
$FFFFB9
ESSI 0 Time Slot Register (TSR0)
$FFB8
$FFFFB8
ESSI 0 Receive Data Register (RX0)
$FFB7
$FFFFB7
ESSI 0 Status Register (SSISR0)
$FFB6
$FFFFB6
ESSI 0 Control Register B (CRB0)
$FFB5
$FFFFB5
ESSI 0 Control Register A (CRA0)
$FFB4
$FFFFB4
ESSI 0 Transmit Slot Mask Register A
(TSMA0)
$FFB3
$FFFFB3
ESSI 0 Transmit Slot Mask Register B
(TSMB0)
$FFB2
$FFFFB2
ESSI 0 Receive Slot Mask Register A
(RSMA0)
$FFB1
$FFFFB1
ESSI 0 Receive Slot Mask Register B
(RSMB0)
$FFB0
$FFFFB0
Reserved
$FFAF
$FFFFAF
Port D Control Register (PCRD)
$FFAE
$FFFFAE
Port D Direction Register (PRRD)
$FFAD
$FFFFAD
Port D GPIO Data Register (PDRD)
Programming Reference
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B-5
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Table B-2. Internal X I/O Memory Map (Continued)
16-Bit Address
24-Bit Address
ESSI 1
$FFAC
$FFFFAC
ESSI 1 Transmit Data Register 0 (TX10)
$FFAB
$FFFFAB
ESSI 1 Transmit Data Register 1 (TX11)
$FFAA
$FFFFAA
ESSI 1 Transmit Data Register 2 (TX12)
$FFA9
$FFFFA9
ESSI 1 Time Slot Register (TSR1)
$FFA8
$FFFFA8
ESSI 1 Receive Data Register (RX1)
$FFA7
$FFFFA7
ESSI 1 Status Register (SSISR1)
$FFA6
$FFFFA6
ESSI 1 Control Register B (CRB1)
$FFA5
$FFFFA5
ESSI 1 Control Register A (CRA1)
$FFA4
$FFFFA4
ESSI 1 Transmit Slot Mask Register A
(TSMA1)
$FFA3
$FFFFA3
ESSI 1 Transmit Slot Mask Register B
(TSMB1)
$FFA2
$FFFFA2
ESSI 1 Receive Slot Mask Register A
(RSMA1)
$FFA1
$FFFFA1
ESSI 1 Receive Slot Mask Register B
(RSMB1)
$FFA0
$FFFFA0
Reserved
$FF9F
$FFFF9F
Port E Control Register (PCRE)
$FF9E
$FFFF9E
Port E Direction Register (PRRE)
$FF9D
$FFFF9D
Port E GPIO Data Register (PDRE)
$FF9C
$FFFF9C
SCI Control Register (SCR)
$FF9B
$FFFF9B
SCI Clock Control Register (SCCR)
$FF9A
$FFFF9A
SCI Receive Data Register - High (SRXH)
$FF99
$FFFF99
SCI Receive Data Register - Middle (SRXM)
$FF98
$FFFF98
SCI Recieve Data Register - Low (SRXL)
$FF97
$FFFF97
SCI Transmit Data Register - High (STXH)
$FF96
$FFFF96
SCI Transmit Data Register - Middle (STXM)
$FF95
$FFFF95
SCI Transmit Data Register - Low (STXL)
$FF94
$FFFF94
SCI Transmit Address Register (STXA)
$FF93
$FFFF93
SCI Status Register (SSR)
$FF92
$FFFF92
Reserved
$FF91
$FFFF91
Reserved
$FF90
$FFFF90
Reserved
Freescale Semiconductor, Inc...
Peripheral
Port E
SCI
B-6
Register Name
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Internal I/O Memory Map
Freescale Semiconductor, Inc...
Table B-2. Internal X I/O Memory Map (Continued)
Peripheral
16-Bit Address
24-Bit Address
Register Name
Triple Timer
$FF8F
$FFFF8F
Timer 0 Control/Status Register (TCSR0)
$FF8E
$FFFF8E
Timer 0 Load Register (TLR0)
$FF8D
$FFFF8D
Timer 0 Compare Register (TCPR0)
$FF8C
$FFFF8C
Timer 0 Count Register (TCR0)
$FF8B
$FFFF8B
Timer 1 Control/Status Register (TCSR1)
$FF8A
$FFFF8A
Timer 1 Load Register (TLR1)
$FF89
$FFFF89
Timer 1 Compare Register (TCPR1)
$FF88
$FFFF88
Timer 1 Count Register (TCR1)
$FF87
$FFFF87
Timer 2 Control/Status Register (TCSR2)
$FF86
$FFFF86
Timer 2 Load Register (TLR2)
$FF85
$FFFF85
Timer 2 Compare Register (TCPR2)
$FF84
$FFFF84
Timer 2 Count Register (TCR2)
$FF83
$FFFF83
Timer Prescaler Load Register (TPLR)
$FF82
$FFFF82
Timer Prescaler Count Register (TPCR)
$FF81
$FFFF81
Reserved
$FF80
$FFFF80
Reserved
Table B-3. Internal Y I/O Memory Map
Peripheral
Motorola
16-Bit
Address
24-Bit
Address
Register Name
$FFBF
$FFFFBF
Reserved
$FFBE
$FFFFBE
Reserved
$FFBD
$FFFFBD
Reserved
$FFBC
$FFFFBC
Reserved
$FFBB
$FFFFBB
Reserved
$FFBA
$FFFFBA
Reserved
$FFB9
$FFFFB9
Reserved
Programming Reference
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B-7
Freescale Semiconductor, Inc.
Interrupt Sources and Priorities
Table B-3. Internal Y I/O Memory Map
16-Bit
Address
Peripheral
Freescale Semiconductor, Inc...
Enhanced Filter
Coprocessor
(EFCOP)
24-Bit
Address
Register Name
$FFB8
$FFFFB8
EFCOP Decimation/Channel (FDCH) Register
$FFB7
$FFFFB7
EFCOP Coefficient Base Address (FCBA)
$FFB6
$FFFFB6
EFCOP Data Base Address (FDBA)
$FFB5
$FFFFB5
EFCOP ALU Control Register (FACR)
$FFB4
$FFFFB4
EFCOP Control Status Register (FCSR)
$FFB3
$FFFFB3
EFCOP Filter Count (FCNT) Register
$FFB2
$FFFFB2
EFCOP K-Constant Register (FKIR)
$FFB1
$FFFFB1
EFCOP Data Output Register (FDOR)
$FFB0
$FFFFB0
EFCOP Data Input Register (FDIR)
$FFAF–
$FF80
$FFFFAF–
$FFFF80
Reserved
B.2 Interrupt Sources and Priorities
Table B-4. Interrupt Sources
Interrupt
Starting Address
Interrupt
Priority
Level Range
VBA:$00
3
Hardware RESET
VBA:$02
3
Stack Error
VBA:$04
3
Illegal Instruction
VBA:$06
3
Debug Request Interrupt
VBA:$08
3
Trap
VBA:$0A
3
Non-Maskable Interrupt (NMI)
VBA:$0C
3
Reserved
VBA:$0E
3
Reserved
VBA:$10
0–2
IRQA
VBA:$12
0–2
IRQB
VBA:$14
0–2
IRQC
VBA:$16
0–2
IRQD
VBA:$18
0–2
DMA Channel 0
VBA:$1A
0–2
DMA Channel 1
VBA:$1C
0–2
DMA Channel 2
B-8
Interrupt Source
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Interrupt Sources and Priorities
Freescale Semiconductor, Inc...
Table B-4. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority
Level Range
VBA:$1E
0–2
DMA Channel 3
VBA:$20
0–2
DMA Channel 4
VBA:$22
0–2
DMA Channel 5
VBA:$24
0–2
Timer 0 Compare
VBA:$26
0–2
Timer 0 Overflow
VBA:$28
0–2
Timer 1 Compare
VBA:$2A
0–2
Timer 1 Overflow
VBA:$2C
0–2
Timer 2 Compare
VBA:$2E
0–2
Timer 2 Overflow
VBA:$30
0–2
ESSI0 Receive Data
VBA:$32
0–2
ESSI0 Receive Data With Exception Status
VBA:$34
0–2
ESSI0 Receive Last Slot
VBA:$36
0–2
ESSI0 Transmit Data
VBA:$38
0–2
ESSI0 Transmit Data With Exception Status
VBA:$3A
0–2
ESSI0 Transmit Last Slot
VBA:$3C
0–2
Reserved
VBA:$3E
0–2
Reserved
VBA:$40
0–2
ESSI1 Receive Data
VBA:$42
0–2
ESSI1 Receive Data With Exception Status
VBA:$44
0–2
ESSI1 Receive Last Slot
VBA:$46
0–2
ESSI1 Transmit Data
VBA:$48
0–2
ESSI1 Transmit Data With Exception Status
VBA:$4A
0–2
ESSI1 Transmit Last Slot
VBA:$4C
0–2
Reserved
VBA:$4E
0–2
Reserved
VBA:$50
0–2
SCI Receive Data
VBA:$52
0–2
SCI Receive Data With Exception Status
VBA:$54
0–2
SCI Transmit Data
VBA:$56
0–2
SCI Idle Line
VBA:$58
0–2
SCI Timer
VBA:$5A
0–2
Reserved
VBA:$5C
0–2
Reserved
VBA:$5E
0–2
Reserved
Motorola
Interrupt Source
Programming Reference
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B-9
Freescale Semiconductor, Inc.
Interrupt Sources and Priorities
Table B-4. Interrupt Sources (Continued)
Interrupt
Priority
Level Range
VBA:$60
0–2
Host Receive Data Full
VBA:$62
0–2
Host Transmit Data Empty
VBA:$64
0–2
Host Command (Default)
VBA:$66
0–2
Reserved
VBA:$68
0–2
EFCOP Data Input Buffer Empty
VBA:$6A
0–2
EFCOP Data Output Buffer Full
VBA:$6C
0–2
Reserved
VBA:$6E
0–2
Reserved
:
:
VBA:$FE
0–2
Freescale Semiconductor, Inc...
Interrupt
Starting Address
Interrupt Source
:
Reserved
Table B-5. Interrupt Source Priorities Within an IPL
Priority
Interrupt Source
Level 3 (Nonmaskable)
Highest
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
B-10
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Interrupt Sources and Priorities
Table B-5. Interrupt Source Priorities Within an IPL (Continued)
Priority
Interrupt Source
DMA Channel 5 Interrupt
Host Command Interrupt
Host Transmit Data Empty
Host Receive Data Full
ESSI0 RX Data with Exception Interrupt
ESSI0 RX Data Interrupt
Freescale Semiconductor, Inc...
ESSI0 Receive Last Slot Interrupt
ESSI0 TX Data With Exception Interrupt
ESSI0 Transmit Last Slot Interrupt
ESSI0 TX Data Interrupt
ESSI1 RX Data With Exception Interrupt
ESSI1 RX Data Interrupt
ESSI1 Receive Last Slot Interrupt
ESSI1 TX Data With Exception Interrupt
ESSI1 Transmit Last Slot Interrupt
ESSI1 TX Data Interrupt
SCI Receive Data With Exception Interrupt
Lowest
SCI Receive Data
Highest
SCI Transmit Data
SCI Idle Line
SCI Timer
Timer0 Overflow Interrupt
Timer0 Compare Interrupt
Timer1 Overflow Interrupt
Timer1 Compare Interrupt
Timer2 Overflow Interrupt
Timer2 Compare Interrupt
EFCOP Data Input Buffer Empty
Lowest
Motorola
EFCOP Data Output Buffer Full
Programming Reference
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B-11
Freescale Semiconductor, Inc.
Programming Sheets
B.3 Programming Sheets
Central Processor
Carry
Over?ow
Zero
Negative
Freescale Semiconductor, Inc...
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
I(1:0)
00
01
10
11
Scaling Mode
S(1:0) Scaling Mode
00 No scaling
01 Scale down
10 Scale up
11 Reserved
Interrupt Mask
Exceptions Masked
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Reserved
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteenth-Bit Arithmetic
Reserved
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
Core Priority
CP(1:0) Core Priority
00
0 (lowest)
01
1
10
2
11
3 (highest)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CP1 CP0 RM SM
I0
S
L
E
U
N
Z
V
C
CE
*0
SA
FV
Extended Mode Register (MR)
LF
DM
SC
*0
S1
S0
I1
Mode Register (MR)
Status Register (SR)
Read/Write
Reset = $C00300
Condition Code Register (CCR)
* = Reserved, Program as 0
Figure B-1. Status Register (SR)
B-12
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Programming Sheets
Central Processor
Chip Operating Mode, Bits 3 – 0
Refer to the operating modes
table in Chapter 4.
Asynchronous Bus Arbitration Enable, Bit 13
0 = Synchronization disabled
1 = Synchronization enabled
Stop Delay Mode, Bit 6
0 = Delay is 128K clock cycles
1 = Delay is 16 clock cycless
Freescale Semiconductor, Inc...
Address Attribute Priority Disable, Bit 14
0 = Priority mechanism enabled
1 = Priority mechanism disabled
Memory Switch Mode, Bit 7
0 = Memory switching disabled
1 = Memory switching enabled
Stack Extension X Y Select, Bit 16
0 = Mapped to X memory
1 = Mapped to Y memory
Stack Extension Underflow Flag, Bit 17
0 = No stack underflow
1 = Stack underflow
Core-DMA Priority, Bits 9 – 8
CPD[1:0]
Description
00
Compare SR[CP] to
active DMA channel
priority
01
DMA has higher
priority than core
10
DMA has same
priority as core
11
DMA has lower
priority than core
Stack Extension Overflow Flag, Bit 18
0 = No stack overflow
1 = Stack overflow
Stack Extension Wrap Flag, Bit 19
0 = No stack extension wrap
1 = Stack extension wrap (sticky bit)
Stack Extension Enable, Bit 20
0 = Stack extension disabled
1 = Stack extension enabled
Memory Switch Configuration, Bits 22 – 21
MSW[1 – 0]
00
01
10
11
23
*0
22
X
Y
X
Y
X
Y
X
Y
Program Memory
Memory: $4000 - $BFFF
Memory: $4000 - $BFFF
Memory: $6000 - $BFFF
Memory: $6000 - $BFFF
Memory: $8000 - $BFFF
Memory: $8000 - $BFFF
Memory: $A000 - $BFFF
Memory: $A000 - $BFFF
Cache Burst Mode Enable, Bit 10
0 = Burst Mode disabled
1 = Burst Mode enabled
TA Synchronize Select, Bit 11
0 = Not synchronized
1 = Synchronized
Bus Release Timing, Bit 12
0 = Fast Bus Release mode
1 = Slow Bus Release mode
21 20 19 18 17 16 15 14 13 12 11 10 9
MSW1 MSW0 SEN WRP EOV EUN XYS
Operating Mode Register
Reset = $000300
External Bus Disable, Bit 4
0 = Enables external bus
1 = Disables external bus
*0
8
7
APD ABE BRT TAS BE CPD1 CPD0 MS
6
5
SD
*0
4
3
2
EBD MD MC
1
0
MB
MA
* = Reserved, Program as 0
Figure B-2. Operating Mode Register
Motorola
Programming Reference
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B-13
Freescale Semiconductor, Inc.
Programming Sheets
Central Processor
Bus Packing Enable, Bit 7
0 = Disable internal packing/unpacking logic
1 = Enable internal packing/unpacking logic
Freescale Semiconductor, Inc...
Bus Y Data Memory Enable, Bit 5
0 = Disable AA pin and logic during
external Y data space accesses
1 = Enable AA pin and logic during
external Y data space accesses
Bus X Data Memory Enable, Bit 4
0 = Disable AA pin and logic during
external X data space accesses
1 = Enable AA pin and logic during
external X data space accesses
Bus Program Memory Enable, Bit 3
0 = Disable AA pin and logic during
external program space accesses
1 = Enable AA pin and logic during
external program space accesses
Bus Address Attribute Polarity, Bit 2
0 = AA/RAS signal is active low
1 = AA/RAS signal is active high
Bus Number of Address Bits to Compare, Bits 11 – 8
BNC[3 –0] = number of bits (from BAC bits) that are
compared to the external address
Bus Access Type, Bits 1 – 0
(Combinations BNC[3 – 0] = 1111, 1110, 1101 are
reserved.)
Bus Address to Compare, Bits 23 – 12
BAC[11 – 0] = address to compare to the
external address in order to decide
whether to assert the AA pin
23
BAC
11
22 21 20 19 18 17 16 15 14 13 12 11 10 9
BAC
10
BAT[1 – 0]
00
01
10
11
8
7
6
BAC BAC BAC BAC BAC BAC BAC BAC BAC BAC BNC BNC BNC BNC BPAC
3
2
1
0
9
8
7
6
5
4
3
2
1
0
Address Attribute Registers (AAR3 - AAR0)
Reset = $000000
Encoding
Reserved
SRAM access
DRAM access
Reserved
*0
5
4
3
2
1
0
BYEN BXENBPEN BAAP BAT BAT
1
0
* = Reserved, Program as 0
Figure B-3. Address Attribute Registers (AAR3 - AAR0)
B-14
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Programming Sheets
Central Processor
NOTE: All BCR bits are read/write control bits.
Bus State, Bit 21
0 = DSP is not bus master
1 = DSP is bus master
Default Area Wait Control, Bits 20 –16
Freescale Semiconductor, Inc...
Area 3 Wait Control, Bits 15 – 13
Area 2 Wait Control, Bits 12 – 10
Area 1 Wait Control, Bits 9 – 5
Area 0 Wait Control, Bits 4– 0
These read/write control bits define
the number of wait states inserted
into each external SRAM access to
the designated area. The value of
these bits should not be programmed
as zero.
Number of wait states:
Bus Lock Hold, Bit 22
0 = BL pin is asserted only for attempted readwrite modify external access
BDFW[20 – 16]
0 – 31
BA3W[15 – 13]
0–7
BA2W[12 – 10]
0–7
BA1W[9 – 5]
0 – 31
BA0W[4 – 0]
0 – 31
1 = BL pin is always asserted
Bus Request Hold, Bit 23
0 = BR pin is asserted only for attempted
or pending access
1 = BR pin is always asserted
23
22
BRH
BLH
21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BBS BDFWBDFW BDFWBDFWBDFWBA3W BA3W BA3WBA2W BA2W BA2W BA1W BA2WBA1W BA1WBA1W BA0W BA0W BA0WBA0W BA0W
4
3
2
1
0
2
1
0
2
1
0
4
3
2
1
0
4
3
2
1
0
Bus Control Register (BCR)
Reset = $1FFFFF
Figure B-4. Bus Control Register (BCR)
Motorola
Programming Reference
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B-15
Freescale Semiconductor, Inc.
Programming Sheets
Central Processor
Three-Dimensional Mode, Bit 10
0 = Three-Dimensional mode disabled
1 = Three-Dimensional mode enabled
Freescale Semiconductor, Inc...
DMA Request Source, Bits 15 – 11
DRS[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
...
10111 11111
Requesting Device
External( IRQA Pin)
External (IRQB pin)
External (IRQC pin)
External (IRQD pin)
Transfer done from channel 0
Transfer done from channel 1
Transfer done from channel 2
Transfer done from channel 3
Transfer done from channel 4
Transfer done from channel 5
ESSI 0 Receive Data
...
Reserved
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
Channel Priority
Priority level 0 (lowest)
Priority level 1
Priority level 2
Priority level 3 (highest)
DMA Transfer Mode, Bits 21 – 19
DTM[2:0]
000
001
010
011
100
101
110
111
Triggered By
request
request
request
DE
request
request
reserved
reserved
DE Cleared
yes
yes
yes
yes
no
no
DAM[2 – 0] = source
DAM[5 – 3] = Destination
DAM[5:3]
Addressing
Counter
DAM[2:0]
Mode
Mode
000
2D
B
001
2D
B
010
2D
B
011
2D
B
100
No update
A
101
PostincrementA
by-1
110
reserved
111
reserved
Offset Register
Selection
DOR0
DOR1
DOR2
DOR3
None
None
Three-Dimensional Addressing Modes (D3D= 1)
DMA Channel Priority, Bits 18 – 17
DPR[1:0]
00
01
10
11
DMA Address Mode, Bits 9 – 4
Non-Three-Dimensional Addressing Modes (D3D=0)
Transfer Mode
block transfer
word transfer
line transfer
block transfer
block transfer
word transfer
DAM[5:3] Addressing Mode
000
2D
001
2D
010
2D
011
2D
100
No update
101
Postincrement-by1
110
3D
111
3D
Offset Selection
DOR0
DOR1
DOR2
DOR3
None
None
DOR0: DOR1
DOR2: DOR3
DMA Destination Space, Bits 3 – 2
DSS[1:0]
00
01
10
11
DMA Destination Memory
X Memory Space
Y Memory Space
P Memory Space
Reserved
DMA Source Space, Bits 1 – 0
DMA Interrupt Enable, Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
DSS[1:0]
00
01
10
11
DMA Channel Enable, Bit 23
0 = Disables channel operation
1 = Enables channel operation
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
DMA Source Memory
X Memory Space
Y Memory Space
P Memory Space
Reserved
5
4
3
2
1
0
DE DIE DTM DTM DTM DPR DPR DCON DRS DRS DRS DRS DRS D3D DAM DAM DAM DAM DAM DAM DDS DDS DSS DSS
2
1
0
1
0
4
3
2
1
0
5
4
3
2
1
0
1
0
1
0
DMA Control Registers (DCR5 – DCR0)
Reset = $000000
Figure B-5. DMA Control Register (DCR)
B-16
DSP56311 User’s Manual
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Motorola
Motorola
Programming Reference
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Interrupt Priority
Register (IPR–C)
X:$FFFFFF Read/Write
Reset = $000000
IPL
0
1
2
3
Trigger
Level
Neg. Edge
IDL2
0
1
Trigger
Level
Neg. Edge
IRQD Mode
IBL2
0
1
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
IDL2 IDL1
8
7
IBL1
IDL1
0
0
1
1
6
IBL0
IDL0
0
1
0
1
5
4
No
Yes
Yes
Yes
Enabled
3
0
1
2
3
2
IPL
IAL1 IAL0 I Enabled
ICL1 ICL0
0
0
No
0
1
Yes
1
0
Yes
1
1
Yes
1
0
1
2
3
IPL
0
IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
9
Trigger
Level
Neg. Edge
IRQB Mode
ICL2
0
1
IRQC Mode
Trigger
Level
Neg. Edge
IRQA Mode
IAL2
0
1
23 22 21 20 19 18 17 16 15 14 13 12 11 10
XXL1 XXL0 Enabled
0
0
No
0
1
Yes
1
0
Yes
1
1
Yes
DMA IPL
Central Processor
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Programming Sheets
Figure B-6. Interrupt Priority Register–Core (IPR–C)
B-17
B-18
DSP56311 User’s Manual
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Interrupt Priority
Register (IPR–P)
X:$FFFF Read/Write
Reset = $000000
Enabled
No
Yes
Yes
Yes
SCI IPL
SCL0
0
1
0
1
IPL
—
0
1
2
Enabled
No
Yes
Yes
Yes
ESSI1 IPL
S1L1 S1L0
0
0
0
1
1
0
1
1
IPL
—
0
1
2
$0
* = Reserved, Program as 0
$0
$0
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
SCL1
0
0
1
1
Central Processor
8
7
ESSI0 IPL
6
5
4
3
S0L0 Enabled
0
No
1
Yes
0
Yes
1
Yes
2
IPL
—
0
1
2
1
IPL
—
0
1
2
0
T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 SOL1 S0L0 HPL1 HPL0
9
S0L1
0
0
1
1
HPL1 HPL0 Enabled
0
0
No
0
1
Yes
1
0
Yes
1
1
Yes
Host IPL
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Programming Sheets
Figure B-7. Interrupt Priority Register – Peripherals (IPR–P)
Motorola
Motorola
Programming Reference
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PLL Control
Register (PCTL)
X:$FFFFFD Read/Write
Reset = $000000
PD3 PD2
PD1
PD0 COD PEN PSTP XTLD XTLR DF2
DF1
1 = EXTAL Driven From
An External Source
0 = Enable XTALOscillator
XTAL Disable Bit (XTLD)
8
DF0 MF11 MF10 MF9 MF8
7
5
4
3
2
MF7 MF6 MF5 MF4 MF3 MF2
6
0
MF1 MF0
1
Multiplication Factor Bits MF0 – MF11
MF11 – MF0 Multiplication Factor MF
$000
1
$001
2
$002
3
•
•
•
•
•
•
$FFF
4095
$FFF
4096
1 = External Xtal Freq < 200KHz
Crystal Range Bit (XTLR)
0 = External Xtal Freq> 200KHz
Division Factor Bits (DF0 – DF2)
DF2 – DF0
Division Factor DF
$0
20
$1
21
$2
22
•
•
•
•
•
•
27
$7
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Predivision Factor Bits (PD0 – PD3)
PD3 – PD0 Predivision Factor PDF
$0
1
$1
2
$2
3
•
•
•
•
•
•
$F
16
1 = Pin Held In High State
0 = 50% Duty Cycle Clock
Clock Output Disable (COD)
PSTP and PEN Relationship
Operation During STOP
PSTP PEN
PLL
Oscillator
0
1 Disabled
Disabled
1
0 Disabled
Enabled
1
1 Enabled
Enabled
PLL
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Programming Sheets
Figure B-8. Phase Lock Loop Control Register (PCTL)
B-19
Freescale Semiconductor, Inc.
Programming Sheets
HOST
Host Receive Data (usually Read by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Freescale Semiconductor, Inc...
Receive High Byte
8
7
6
Receive Middle Byte
5
4
3
2
1
0
1
0
Receive Low Byte
Host Receive Data Register (HRX)
X:$FFEC6 Read Only
Reset = empty
Host Transmit Data (usually Loaded by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Transmit High Byte
8
7
6
Transmit Middle Byte
5
4
3
2
Transmit Low Byte
Host Transmit Data Register (HTX)
X:$FFEC7 Write Only
Reset = empty
Figure B-9. Host Receive and Host Transmit Data Registers
B-20
DSP56311 User’s Manual
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Motorola
Freescale Semiconductor, Inc.
Programming Sheets
HOST
Host Receive Interrupt Enable
0 = Disable 1 = Enable if HRDF = 1
Host Transmit Interrupt Enable
0 = Disable 1 = Enable if HTDE = 1
Freescale Semiconductor, Inc...
Host Command Interrupt Enable
0 = Disable 1 = Enable if HCP = 1
Host Flag 2
Host Flag 3
15 7
Host Control Register (HCR)
X:$FFFFC2 Read /Write
Reset = $0
6
5
*0 *0 *0 *0
4
3
HF3
HF2
2
1
HCIE HTIE
0
HRIE
DSP Side
Host Receive Data Full
0 = ³ Wait
1 = ³ Read
Host Transmit Data Empty
0 = ³ Wait
1 = ³ Write
Host Command Pending
0 = ³ Wait
1 = ³ Ready
Host Flags
Read Only
15 7
Host Staus Register (HSR)
X:$FFFFC3 Read Only
Reset = $2
6
5
*0 *0 *0 *0
4
3
HF1
HF0
2
1
0
HCP HTDE HRDF
* = Reserved, Program as 0
Figure B-10. Host Control and Host Status Registers
Motorola
Programming Reference
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B-21
Freescale Semiconductor, Inc.
Programming Sheets
HOST
15
*0 *0
Host Base Address Register (HBAR)
X:$FFFFC5
Reset = $80
Freescale Semiconductor, Inc...
8
7
Host Request Open Drain
HDRQ
HROD
HREN/HEW
0
0
1
0
1
1
1
0
1
1
1
1
BA9
5
4
3
2
1
0
BA8
BA7
BA6
BA5
BA4
BA3
Host GPIO Port Enable
0 = GPIO Pins Disable, 1 = GPIO Pin Enable
Host Address Line 8 Enable
0 “ HA8 = GPIO, 1 Æ HA8 = HA8
Host Address Line 9 Enable
0 “ HA9 = GPIO, 1 Æ HA9 = HA9
Host Data Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Chip Select Enable
0 “ HCS/HAI0 = GPIO,
1 “ HCS/HA10 = HC8, if HMUX = 0
1 “ HCS/HA10 = HC10, if HMUX = 1
Host Address Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Multiplexed Bus
0 = Nonmultiplexed, 1 = Multiplexed
Host Request Enable
0 “ HREQ/HACK = GPIO,
1 “ HREQ = HREQ, if HDRQ = 0
Host Dual Data Strobe
0 = Single Strobe, 1 = Dual Strobe
Host Chip Select Polarity
0 = HCS Active Low
HTRQ & HRRQ Enable
1 = HCS Active High
HDRQ
0
0
1
1
6
BA10
Host Acknowledge Enable
0 “ HACK = GPIO
If HDRQ & HREN = 1,
HACK = HACK
Host Request Polarity
HRP
0
HREQ Active Low
1
HREQ Active High
0
HTRQ,HRRQ Active Low
1
HTRQ,HRRQ Active High
Host Enable
0 “ HI08 Disable
Pins = GPIO
1 “ HI08 Enable
Host Acknowledge Polarity
0 = HACK Active Low, 1 = HACK Active High
15
Host Port Control
Register (HPCR)
X:$FFFFC4
Read/Write
Reset = $0
HAP
14
13
12
HRP
HCSP
HDDS HMUX
11
10
HASP
9
8
7
6
5
HDSP
HROD
*0
HEN
HAEN
4
3
2
1
0
HREN HCSEN HA9EN HA8EN HGEN
* = Reserved, Program as 0
Figure B-11. Host Base Address and Host Port Control Registers
B-22
DSP56311 User’s Manual
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Freescale Semiconductor, Inc.
Programming Sheets
Processor Side
Freescale Semiconductor, Inc...
HOST
Receive Request Enable
DMA Off
0 =  Interrupts Disabled
DMA On
0 = Host “ DSP
1 = Interrupts Enabled
1 = DSP “ Host
Transmit Request Enable
DMA Off
0 = Interrupts Disabled
DMA On
0 = DSP “ Host
1 = Interrupts Enabled
1 = Host “ DSP
HDRQ HREQ/HTRQ HACK/HRRQ
0
HREQ
HACK
1
HTRQ
HRRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 =  No Action 1 =  Initialize DMA
7
6
INIT
*0
7
6
Interrupt Control Register (ICR)
X:$
Read/Write
Reset = $0
5
4
HLEND HF1
3
2
1
0
HF0 HDRQ TREQ RREQ
Receive Data Register Full
0 = Wait
1 = Read
Transmit Data Register Empty
0 = Wait
1 = Write
Transmitter Ready
0 = Data in HI 1 = Data Not in HI
Host Flags
Read Only
DMA Status
0 = ³ DMA Disabled
1 =  DMA Enabled
Host Request
0 = ³ HREQ Deasserted 1 =  HREQ Asserted
HREQ DMA
Interrupt Status Register (ISR)
$2 Read/Write
Reset = $06
Figure B-12.
Motorola
5
4
*0
HF3
3
2
1
0
HF2 TRDY TXDE RXDF
= Reserved, Program as 0
*
Interrupt Control and Interrupt Status Registers
Programming Reference
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B-23
Freescale Semiconductor, Inc.
Programming Sheets
Freescale Semiconductor, Inc...
HOST
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
1
0
Interrupt Vector Register (IVR)
Reset = $0F
Contains the interruptvectoror number
Host Vector
Contains Host Command Interrupt Address ³ 2
Host Command
Handshakes Executing Host Command Interrupts
7
6
5
4
3
2
HC7 HC6 HC5 HC4 HC3 HC2 HC1 HC0
Command Vector Register (CVR)
Reset = $2A
Contains the host command interrupt addressr
Figure B-13. Interrupt Vector and Command Vector Registers
B-24
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Freescale Semiconductor, Inc.
Programming Sheets
HOST
Processor Side
Host Receive Data (usually Read by program)
7
0 7
Freescale Semiconductor, Inc...
Receive Low Byte
0 7
Receive Middle Byte
0 7
Not Used
0
$7
0
Receive High Byte
$6
0
0
0
$5
0
0
0
0
$4
Receive Byte Registers
$7, $6, $5, $4 Read Only
Reset = $00
Receive Byte Registers
Host Transmit Data (usually loaded by program)
7
0 7
Transmit Low Byte
0 7
Transmit Middle Byte
0 7
Not Used
0
$7
$6
0
Transmit High Byte
$5
0
0
0
0
0
0
0
$4
Transmit Byte Registers
$7, $6, $5, $4 Write Only
Reset = $00
Figure B-14. Host Receive and Host Transmit Data Registers
Motorola
Programming Reference
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B-25
B-26
Frame Rate Divider Control
DC4:0 = $00-$1F (1 to 32)
Divide ratio for Normal mode
# of time slots for Network
Prescaler Range
0= 8 1= 1
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*0
* = Reserved, Program as 0
*0
WL0 ALC
DC4
DC3 DC2
DC1
DC0
PSR
8
*0 *0 *0
9

WL1
6
PM7 PM6
7

SSC1 WL2
4
3
2
1
PM5 PM4 PM3 PM2 PM1
5
0
PM0
Prescale Modulus Select
PM7:0 = $00-$FF ( 1 to 256)
PSR = 1 and PM[7:0] = $00 is forbidden
Alignment Control
0 = 16-bit data left aligned to bit 23
1 = 16-bit data left aligned to bit 15
ESSI
Control Register A (CRAx)
ESSI0 :$FFFFB5 Read/Write
ESSI1 :$FFFFA5 Read/Write
Reset = $000000


23 22 21 20 19 18 17 16 15 14 13 12 11 10
Select SC1 as Tx#0
drive enable
0 = SC1 functions as
serial I/O flag
1 = functions as driver
enable of Tx#0
external buffer
Word Length Control
WL2 WL1 WL0
Number of bits/word
0
0
0 8
0
0
1 12
0
1
0 16
0
1
1 24
1
0
0 32 (data in first 24 bits)
1
0
1 32 (data in last 24 bits)
1
1
0 Reserved
1
1
1 Reserved
ESSI
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Freescale Semiconductor, Inc.
Programming Sheets
Figure B-15. ESSI Control Register A (CRA)
Motorola
Motorola
1 = Network
Programming Reference
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ESSI
Control Register B (CRBx)
ESSI0 :$FFFFB6 Read/Write
ESSI1 :$FFFFA6 Read/Write
Reset = $000000
REIE TEIE RLIE TLIE
RIE
TIE
RE
TE0
TE1
TE2 MOD SYN CKP FSP
1 = Output
7
6
5
4
3
2
0
FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0
8
Clock Source Direction
0 = External Clock 1 = Internal Clock
1 = LSB First
0 = Input
1
Output Flag x
If SYN = 1 and SCD1 = 1
SCx Pin
OFx
Frame Sync Length
TX
RX
Word
Word
Bit
Word
Bit
Bit
Word
Bit
Serial Control Direction Bits
0
1
0
1
Shift Direction
0 = MSB First
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Receive Exception Interrupt Enable
0 = Disable
1 = Enable
Transmit Exception Interrupt Enable
0 = Disable
1 = Enable
Receive Last Slot Interrupt Enable
0 = Disable
1 = Enable
Transmit Last Slot Interrupt Enable
0 = Disable
1 = Enable
Receive Interrupt Enable
0 = Disable
1 = Enable
Transmit Interrupt Enable
0 = Disable
1 = Enable
Receiver Enable
0 = Disable
1 = Enable
Transmit 0 Enable
0 = Disable
1 = Enable
Transmit 1 Enable (SYN=1 only)
0 = Disable
1 = Enable
0
0
1
1
FSL1 FSL0
“
Transmit 2 Enable (SYN=1 only)
0 = Disable
1 = Enable
Mode Select
0 = Normal
Sync/Async Control (Tx & Rx transfer together or not)
0 = Asynchronous 1 = Synchronous
Clock Polarity (clk edge data & Frame Sync clocked out/in)
0 = out on rising / in on falling 1 = in on rising / out on falling
1 = low level (negative)
Frame Sync Relative Timing (WL Frame Sync only)
0 = with 1st data bit
1 = 1 clock cycle earlier than 1st data bit
Frame Sync Polarity
0 = high level (positive)
ESSI
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Freescale Semiconductor, Inc.
Programming Sheets
Figure B-16. ESSI Control Register B (CRB)
B-27
Freescale Semiconductor, Inc.
Programming Sheets
ESSI
Freescale Semiconductor, Inc...
Serial Input Flag 0
If SCD0 = 0, SYN = 1, & TE1 = 0
latch SC0 on FS
Serial Input Flag 1
If SCD1 = 0, SYN = 1, & TE2 = 0
latch SC0 on FS
Transmit Frame Sync
0 = Sync Inactive
1 = Sync Active
Receive Frame Sync
0 = Wait
1 = Frame Sync Occurred
Transmitter Underrun Error Flag
0 = OK
1 = Error
Receiver Overrun Error Flag
0 = OK
1 = Error
Transmit Data Register Empty
0 = Wait
1 = Write
Receive Data Register Full
1 = Read
0 = Wait
ESSI Status Register (SSISRx)
ESSI0: $FFFFB7 (Read)
ESSI1: $FFFFA7 (Read)
23
7
*0
RDF
6
5
TDE ROE
4
3
2
1
0
TUE
RFS
TFS
IF1
IF0
SSI Status Bits
* = Reserved, program as 0
Figure B-17. ESSI Status Register (SSISR)
B-28
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Programming Sheets
ESSI
ESSI Transmit Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
Freescale Semiconductor, Inc...
23
ESSI Transmit Slot Mask A
TSMAx
ESSI0: $FFFFB4 Read/Write
ESSI1: $FFFFA4 Read/Write
Reset = $FFFF
16 15 14 13 12 11 10
*0 *0
9
TS15 TS14 TS13 TS12 TS11 TS10 TS9
8
7
6
5
4
3
2
1
0
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
ESSI Transmit Slot Mask A
* = Reserved, Program as 0
ESSI Transmit Slot Mask
0 = Ignore Time Slot
1 = Activ e Time Slot
23
ESSI Transmit Slot Mask B
TSMBx
ESSI0: $FFFFB3 Read/Write
ESSI1: $FFFFA3 Read/Write
Reset = $FFFF
16 15 14 13 12 11 10
*0 *0
9
8
7
6
5
4
3
2
1
0
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask B
* = Reserved, Program as 0
ESSI Receive Slot Mask
0 = Ignore Time Slot
1 = Activ e Time Slot
23
ESSI Receive Slot Mask A
RSMAx
ESSI0: $FFFFB2 Read/Write
ESSI1: $FFFFA2 Read/Write
Reset = $FFFF
16 15 14 13 12 11 10
*0 *0
9
RS15 RS14 RS13 RS12 RS11 RS10 RS9
8
7
6
5
4
3
2
1
0
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
ESSI Receive Slot Mask A
* = Reserved, Program as 0
ESSI Receive Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
ESSI Receive Slot Mask B
RSMBx
ESSI0: $FFFFB1 Read/Write
ESSI1: $FFFFA1 Read/Write
Reset = $FFFF
23
16 15 14 13 12 11 10
*0 *0
9
8
7
6
5
4
3
2
1
0
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
ESSI Receive Slot Mask B
Figure B-18.
Motorola
= Reserved, Program as 0
*
ESSR Transmit and Receive Slot Mask Registers (TSM, RSM)
Programming Reference
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B-29
Freescale Semiconductor, Inc.
Programming Sheets
Port E Pin Control
0 = General-Purpose I/O Pin
1 = SCI pin
SCI
15 14 13 12 11 10
Freescale Semiconductor, Inc...
Port E
Control Register (PCRE)
X:$FFFF9F Read/Write
Reset = $000000
9
8
7
6
5
4
3
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
$0
$0
2
1
0
PC2
PC1
PC0
$0
Port E Control Register (PCRE)
* = Reserved, Program as 0
Word Select Bits
0 0 0 = 8-bit Synchronous Data (Shift Register Mode)
0 0 1 = Reserved
0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
0 1 1 = Reserved
1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)
1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)
1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)
1 1 1 = Reserved
Transmitter Enable
0 = Transmitter Disable
1 = Transmitter Enable
Idle Line Interrupt Enable
0 = Idle Line Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receive Interrupt Enable
0 = Receive Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receiver Wakeup Enable
0 = receiver has awakened
1 = Wakeup function enabled
Transmit Interrupt Enable
0 = Transmit Interrupts Disabled
1 = Transmit Interrupts Enabled
Wired-Or Mode Select
1 = Multidrop
0 = Point to Point
Timer Interrupt Enable
0 = Timer Interrupts Disabled
1 = Timer Interrupts Enabled
Send Break
0 = Send break, then revert
1 = Continually send breaks
Receiver Enable
0 = Receiver Disabled
1 = Receiver Enabled
SCI Timer Interrupt Rate
0 =  32, 1 = ³ 1
SCI Shift Direction
0 = LSB First
1 = MSB First
Wakeup Mode Select
0 = Idle Line Wakeup
1 = Address Bit Wakeup
SCI Clock Polarity
0 = Clock Polarity is Positive
1 = Clock Polarity is Negative
SCI Receive Exception Inerrupt
0 = Receive Interrupt Disable
1 = Receive Interrupt Enable
23
SCI Control
Register (SCR)
Address X:$FFFF9C
Read/Write
*0
16 15 14 13 12 11 10 9
REIE SCKP STIR TMIE
TIE
RIE
ILIE
TE
8
RE
7
6
5
4
3
2
1
0
WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0
SCI Control Register (SCR)
* = Reserved, Program as 0
Figure B-19. SCI Control Register (SCR)
B-30
DSP56311 User’s Manual
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Freescale Semiconductor, Inc.
Programming Sheets
Freescale Semiconductor, Inc...
SCI
Overrun Error Flag
0 = No error
1 = Overrun detected
Idle Line Flag
0 = Idle not detected
1 = Idle State
Parity Error Flag
0 = No error
1 = Incorrect Parity detected
Receive Data Register Full
0 = Receive Data Register Full
1 = Receive Data Register Empty
Framing Error Flag
0 = No error
1 = No Stop Bit detected
Transmitter Data Register Empty
0 = Transmitter Data Register full
1 = Transmitter Data Register empty
Received Bit 8
0 = Data
1 = Address
Transmitter Empty
0 = Transmitter full
1 = Transmitter empty
SCI Status Register (SSR)
Address X:$FFFF93
Read Only
Reset = $000003
23
7
6
5
*0
R8
FE
PE
4
3
2
1
0
OR IDLE RDRFTDRETRNE
$0
$3
= Reserved, Program as 0
*
SCI Status Register (SSR)
Clock Divider Bits CD11 – CD0)
CD11 – CD0
Icyc Rate
$000
Icyc/1
$001
Icyc/2
$002
Icyc/3
•
•
•
•
•
•
$FFE
Icyc/4095
$FFF
Icyc/4096
Clock Divider Bits CD11 – CD0)
TCM RCM TX Clock RX Clock SCLK Pin
Mode
0
0
Internal
Internal
Output
Synchronous/Asynchronous
0
1
Internal External
Input
Asynchronous only
1
0
External Internal
Input
Asynchronous only
1
1
External External
Input
Synchronous/Asynchronous
Transmitter Clock Mode/Source
0 = Internal clock for Transmitter
1 = External clock from SCLK
Receiver Clock Mode/Source
0 = Internal clock for Receiver
1 = External clock from SCLK
Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK
SCI Clock Prescaler
0 = 1 1 =  8
23
15 14 13 12 11 10
*0
TCM RCM
SCP
9
COD CD11 CD10 CD9
8
7
6
5
4
3
2
1
0
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
SCI Clock Control Register (SCCR)
* = Reserved, Program as 0
Figure B-20. SCI Status and Clock Control Registers (SSR, SCCR)
Motorola
Programming Reference
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B-31
Freescale Semiconductor, Inc.
Programming Sheets
SCI
“A”
X0
Unpacking
16 15
Freescale Semiconductor, Inc...
23
SCI Transmit Data Registers
Address X:$FFFF95 – X:$FFFF97
Write
Reset = xxxxxx
X:$FFFF97
“B”
“C”
87
0
STX
X:$FFFF96
STX
X:$FFFF95
STX
NOTE: STX is the same register decoded at four different addresses
SCI Transmit SR
TXD
SCI Transmit Data Registers
X:$FFFF94
STXA
RXD
SCI Receive SR
23
SCI Receive Data Registers
Address X:$FFFF98 – X:$FFFF9A
Read
Reset = xxxxxx
16 15
87
X:$FFFF9A
SRX
X:$FFFF99
X:$FFFF98
0
SRX
SRX
Packing
“A”
“B”
“C”
NOTE: STX is the same register decoded at three different addresses
SCI Receive Data Registers
Figure B-21. SCI Receive and Transmit Data Registers (SRX, TRX)
B-32
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Freescale Semiconductor, Inc.
Programming Sheets
Freescale Semiconductor, Inc...
Timers
PS (1:0)
00
01
10
11
Prescaler Clock Source
Internal CLK/2
TIO0
TIO1
TIO2
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0
PS1
8
7
6
5
4
3
2
1
0
PS0
Prescaler Preload Value (PL [0:20])
Timer Prescaler Load Register
TPLR:$FFFF83 Read/Write
Reset = $000000
* = Reserved, Program as 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0 *0
8
7
6
5
4
3
2
1
0
Current Value of Prescaler Counter (PC [0:20])
Timer Prescaler Count Register
TPCR:$FFFF82 Read Only
Reset = $000000
* = Reserved, Program as 0
Figure B-22. Timer Prescaler Load/Count Register (TPLR, TPCR)
Motorola
Programming Reference
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Freescale Semiconductor, Inc.
Programming Sheets
Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
or high pulse width measured, or high pulse output on TIO
Timers
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO
Timer Reload Mode Bit 9
0 = Timer operates as a free
running counter
TC (3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Freescale Semiconductor, Inc...
1 = Timer is reloaded when
selected condition occurs
Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Timer Control Bits 4 – 7 (TC0 – TC3)
TIO
Clock
Mode
GPIO Internal Timer
Output Internal Timer Pulse
Output Internal Timer Toggle
Input External Event Counter
Input
Internal Input Width
Input
Internal Input Period
Input
Internal Capture
Output Internal Pulse Width Modulation
–
–
Reserved
Output Internal Watchdog Pulse
Output Internal Watchdog Toggle
–
–
Reserved
–
–
Reserved
–
–
Reserved
–
–
Reserved
–
–
Reserved
Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Enabled
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output
Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Timer Compare Flag Bit 21
0 = “1” has been written to TCSR(TCF),
or timer compare interrupt serviced
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
1 = Timer Compare has occurred
Timer Overflow Flag Bit 20
0 = “1” has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0
TCF
TOF
*0 *0 *0 *0
PCE
*0
DO
DI
DIR
*0
8
TRM INV
Timer Control/Status Register
TCSR0:$FFFF8F Read/Write
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
Reset = $000000
7
6
5
4
3
TC3
TC2
TC1
TC0
*0
2
1
TCIE TQIE
0
TE
* = Reserved, Program as 0
Figure B-23. Timer Control/Status Register (TCSR)
B-34
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Freescale Semiconductor, Inc.
Programming Sheets
Timers
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Freescale Semiconductor, Inc...
Timer Reload Value
Timer Load Register
TLR0:$FFFF8E Write Only
TLR1:$FFFF8A Write Only
TLR2:$FFFF86 Write Only
Reset = $000000
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Value Compared to Counter Value
Timer Compare Register
TCPR0:$FFFF8D Read/Write
TCPR1:$FFFF89 Read/Write
TCPR2:$FFFF85 Read/Write
Reset = $000000
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
Timer Count Value
Timer Count Register
TCR0:$FFFF8C Read Only
TCR1:$FFFF88 Read Only
TCR2:$FFFF84 Read Only
Reset = $000000
Figure B-24. Timer Load, Compare, Count Registers (TLR, TCPR, TCR)
Motorola
Programming Reference
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B-35
Freescale Semiconductor, Inc.
Programming Sheets
GPIO
Port B (HI08)
Host Data Direction Register
15
14
13
12
11
10
9
Freescale Semiconductor, Inc...
DR15 DR14 DR13 DR12 DR11 DR10 DR9
8
7
6
5
4
3
2
1
0
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
X:$FFFFC8
Write
Reset = $0
DRn = 1
“
DRx = 0 “ HIx is Input
HIx is Output
Host Data Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X:$FFFFC9
Write
Reset = Undefined
DRn holds value of corresponding HI08 GPIO pin.
Function depends on HDDR.
Figure B-25. Host Data Direction and Host Data Registers (HDDR, HDR)
B-36
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Freescale Semiconductor, Inc.
Programming Sheets
GPIO
Port C (ESSI0)
STD0 SRD0 SCK0 SC02 SC01 SC00
Freescale Semiconductor, Inc...
Port C Control Register
(PCRC)
X:$FFFFBF
ReadWrite
Reset = $0
23
6
*0 *0
PCn = 1
PCn = 0
Port C Direction Register
(PRRC)
X:$FFFFBE
ReadWrite
Reset = $0
23
6
*0 *0
“
“
5
4
3
2
1
0
PC5
PC4
PC3
PC2
PC1
PC0
Port Pin configured as ESSI
Port Pin configured as GPIO
5
4
3
2
1
0
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn = 1 “ Port Pin is Output
PDCn = 0 “ Port Pin is Input
23
Port C GPIO Data Register
(PDRC)
X:$FFFFBD
ReadWrite
Reset = $0
6
*0 *0
5
4
3
2
1
0
PD5
PD4
PD3
PD2
PD1
PD0
If port pin n is GPIO input, then PDn reflects the
value on port pin n.
If port pin n is GPIO output, then value written to
PDn is reflected on port pin n.
* = Reserved, Program as 0
Figure B-26. Port C Registers (PCRC, PRRC, PDRC)
Motorola
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Freescale Semiconductor, Inc.
Programming Sheets
GPIO
Port D (ESSI1)
STD1 SRD1 SCK1 SC12 SC11 SC10
Freescale Semiconductor, Inc...
Port D Control Register
(PCRD)
X:$FFFFAF
ReadWrite
Reset = $0
23
6
*0 *0
PCn = 1
PCn = 0
23
Port D Direction Register
(PRRD)
X:$FFFFAE
ReadWrite
Reset = $0
6
*0 *0
“
“
5
4
3
2
1
0
PC5
PC4
PC3
PC2
PC1
PC0
Port Pin configured as ESSI
Port Pin configured as GPIO
5
4
3
2
1
0
PDC5
PDC4
PDC3
PDC2
PDC1
PDC0
PDCn = 1 “ Port Pin is Output
PDCn = 0 “ Port Pin is Input
23
Port D GPIO Data Register
(PDRD)
X:$FFFFAD
ReadWrite
Reset = $0
6
*0 *0
5
4
3
2
1
0
PD5
PD4
PD3
PD2
PD1
PD0
If port pin n is GPIO input, then PDn reflects the
value on port pin n.
If port pin n is GPIO output, then value written to
PDn is reflected on port pin n.
* = Reserved, Program as 0
Figure B-27. Port D Registers (PCRD, PRRD, PDRD)
B-38
DSP56311 User’s Manual
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Freescale Semiconductor, Inc.
Programming Sheets
GPIO
Port E (SCI)
SCLK TXD RXD
Freescale Semiconductor, Inc...
Port E Control Register
(PCRE)
X:$FFFF9F
ReadWrite
Reset = $0
23
6
4
3
*0 *0 *0 *0 *0
PCn = 1
PCn = 0
Port E Direction Register
(PRRE)
X:$FFFF9E
ReadWrite
Reset = $0
5
23
6
“
“
2
1
0
PC2
PC1
PC0
Port Pin configured as SCI
Port Pin configured as GPIO
5
4
3
*0 *0 *0 *0 *0
2
1
0
PDC2
PDC1
PDC0
PDCn = 1 “ Port Pin is Output
PDCn = 0 “ Port Pin is Input
23
Port E GPIO Data Register
(PDRE)
X:$FFFF9D
ReadWrite
Reset = $0
6
5
4
3
*0 *0 *0 *0 *0
2
1
0
PD2
PD1
PD0
If port pin n is GPIO input, then PDn reflects the
value on port pin n.
If port pin n is GPIO output, then value written to
PDn is reflected on port pin n.
* = Reserved, Program as 0
Figure B-28.
Motorola
Port E Registers (PCRE, PRRE, PDRE)
Programming Reference
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B-39
Freescale Semiconductor, Inc.
Programming Sheets
EFCOP
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
7
6
5
2
1
0
* = Reserved, Program as 0
Filter Enable Bit 0
0 = EFCOP Disabled
1 = EFCOP Enabled
FilterData Input Interrupt Enable Bit 10
(Read/write control bit)
0 = Interrupt disabled
1 = Interrupt enabled
Freescale Semiconductor, Inc...
3
Filter Count Value
Filter Count Register (FCNT)
Y:$FFFFB3 Read/Write
Reset = $000000
Filter Type Bit 1
0 = FIR
1 = IIR
FilterData Output Interrupt Enable Bit 11
(Read/write control bit)
0 = Interrupt disabled
1 = Interrupt enabled
Adaptive Mode Enable Bit 2
0 = Adaptive Mode Disabled
1 = Adaptive Mode Enabled
Update Mode Enable Bit 3
0 = Update Mode Disabled
1 = Update Mode Enabled
FilterSaturation Bit 12
(Read only status bit)
0 = No FMAC underflow/overflow
1 = FMAC underflow/overflow occurred
Filter Operating ModeBits 5–4
00 = Real
10 = Alt. Complex
01 = Complex 11 = Magnitude
FilterContention Bit 13
(Read only status bit)
0 = No dual access occurred
1 = Core and EFCOP tried to access
the same bank in FDM or FCM
Channels Bit 6
0 = Single channel
1 = Multichannel
Initialization Bit 7
0 = Preprocess initialization
1 = No initialization
Filter Data Input Buffer Empty Bit 14
(Read only status bit)
0 = FDIR is not empty
1 = FDIR is empty
Coefficients Bit 8
0 = Not shared
1 = Shared
Filter Data Output Buffer Full Bit 15
(Read only status bit)
0 = FDOR is not full
1 = FDOR is full
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0 *0 *0 *0 *0 *0 *0
4
FD FD
F
FSAT FDOE FDIE
OBF IBE CONT
*0
EFCOP Control Status Register (FCSR)
Y:$FFFFB4 Read/Write
Reset = $000000
8
7
6
5
4
3
2
1
0
FSCO FPCR FMLC FOM1FOM0 FUPD FADP FLT
FEN
* = Reserved, Program as 0
Figure B-29. EFCOP Counter and Control Status Registers
(FCNT and FCSR)
B-40
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Freescale Semiconductor, Inc.
Programming Sheets
EFCOP
Saturation Mode Bit 4
0 = Disabled 1 = Enabled
Sixteen-bit Arithmetic Mode Bit 5
0 = Disabled 1 = Enabled
Filter Rounding Mode Bits 3–2
00 = Convergent
01 = Two’s complement
10 = Truncation
11 = Reserved
Filter Scaling Bits 1–0
00 = ™ 1 10 = ™ 16
01 = ™ 8 11 = Reserved
Freescale Semiconductor, Inc...
Filter Input Scaling Bit 6
0 = Not used 1 = Used
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
EFCOP ALU Control Register (FACR)
Y:$FFFFB5 Read/Write
15 14 13 12 11 10 9
Reset = $000000
8
5
4
FISL FSA FSM
3
2
Rounding
Mode
1
0
Filter
Scaling
= Reserved, Program as 0
*
7 6 5 4 3 2 1 0
Data Base Address (FDM Pointer)
EFCOP Data Base Address (FDBA)
Y:$FFFFB6 Read/Write
Reset = $000000
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
2
1
0
Coefficient Base Address (FDM Pointer)
EFCOP Coefficient Base Address (FCBA)
Y:$FFFFB7 Read/Write
Reset = $000000
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
Filter Deci0 0 0 0 0 0 0 0 0 0 0 0 mation Value
************
EFCOP Decimation/Channel Count Register (FDCH)
Y:$FFFFB8 Read/Write
Reset = $000000
7
6
*0 *0
5
4
3
Filter Channels Value
* = Reserved, Program as 0
Figure B-30. EFCOP FACR, FDBA, FCBA, and FDCH Registers
Motorola
Programming Reference
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B-41
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Programming Sheets
B-42
DSP56311 User’s Manual
For More Information On This Product,
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Motorola
Freescale Semiconductor, Inc.
Index
Freescale Semiconductor, Inc...
A
AAR see Address Attribute Registers
adaptive filter 10-1
adder
modulo 1-7
offset 1-7
reverse-carry 1-7
Address Arithmetic Logic Unit (Address ALU) 1-7
Address Attribute Registers (AAR1-AAR4) 4-22
Address Generation Unit 1-7
Address Mode Wakeup 8-3
addressing modes 1-7
AGU see Address Generation Unit
ALC bit 7-16
Alignment Control bit (ALC) 7-16
ALU
see Address Arithmetic Logic Unit
see Data Arithmetic Logic Unit
asynchronous data transfer 8-2
Asynchronous mode 7-10, 8-2, 8-15, 8-17, 8-18, 8-19,
8-20
Asynchronous modes 8-19
Asynchronous Multidrop mode 8-17
B
barrel shifter 1-6
BCHG 5-2
BCLR 5-2
bit 6-15, 6-30, 6-31
bit, sticky 10-2
bit-oriented instructions (BCHG, BCLR, BSET, BTST,
BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET,
JSCLR, AND JSSET) 5-2
bootstrap 3-1, 3-3, 4-4
program 4-4
program options, invoking 4-4
bootstrap code 8-7
Bootstrap mode 7 4-3
Boundary Scan Register (BSR) 4-25
BRCLR 5-2
break 8-16
BRSET 5-2
BSCLR 5-2
BSET 5-2
BSR see Boundary Scan Register
BSSET 5-2
Motorola
BTST 5-2
bus
address 2-3
data 2-3
external address 2-6
external data 2-6
internal 1-10
multiplexed 2-3
non-multiplexed 2-3
C
Capture Measurement mode 9-15
cellular base station 10-1
Central Processing Unit (CPU) 1-1
chip select signal 6-4
Chip-Select logic 6-17
clock 1-5, 2-5
Clock Generator (CLKGEN) 1-8
clock generator features 8-19
clock generator, ESSI 7-11
Clock Out Divider bit (COD) 8-21
CMOS 1-5
COD bit 8-21
code
compatible 1-5
real FIR filter with polling 10-25
codec systems 7-4
codecs 7-10, 7-13
Command Vector Register (CVR) 6-27
Compare register (TCPR) 9-3
configure an ESSI exception 7-9
configure interrupt trigger 9-4
configuring a timer exception 9-4
control HI08 operating mode 6-17
Control Register A 7-14
bit 18—Alignment Control bit (ALC) 7-16
see also ESSI
Control Register B 7-18
see also ESSI
counter overflow 9-25
counter preload operation 9-26
CRA see Control Register A
CRB see Control Register B
cross-correlation filtering 10-1
crystal frequency 8-6
CVR see Command Vector Register
DSP56311 User’s Manual
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Index-1
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
D
data and control host processor registers 6-13
Data Arithmetic Logic Unit 1-6
Multiplier-Accumulator (MAC) 1-6
registers 1-6
data strobe 6-4
data transfer methods 5-3
interrupts 5-3
polling 5-3
data/coefficient transfer contention bit 10-2
Debug mode
entering 2-21
external indication 2-21
warning 3-8
decimation 10-1, 10-4, 10-7, 10-13, 10-14
example (sequence of even real numbers) 10-30
Decimation/Channel Count Register 10-13, 10-14
DFI 10-2
DFII 10-2
Direct Form 1 10-2
Direct Form 2 10-2
Direct Memory Access (DMA) 6-9
EFCOP and 10-2
Request Source bits (DRS4-DRS0) 4-10
restrictions on EFCOP 10-5
triggered by timer 9-21
DMA 6-6
DMA see Direct Memory Access
DMA transfers and host bus 6-9
DO loop 1-8
Double Data Strobe 2-3
Double Host Request bit (HDRQ) 6-25
DRAM 1-10
DS 2-3
DSP core programming model 6-13
DSP transmit interrupt 7-20
DSP56300 core 1-1
DSP56300 Family Manual 1-1 , 1-5, 6-9, 6-21, 6-31
DSP56307 Technical Data 1-1
DSP-to-host transfers 6-6
dual host requests enabled 6-10
dynamic memory configuration switching 3-7
E
echo cancellation 10-1
echo cancellation filter 10-31
EFCOP 1-2, 1-14
control and status registers 10-4
core transfers 10-2
DMA restrictions 10-4
DMA transfers 10-2
FACR 10-11, 10-12
Index-2
FCBA 10-13
FCM 10-4
FCNT 10-7
FCSR 10-8
FDBA 10-12
FDCH 10-13, 10-14
FDIR 10-7
FDM 10-4
FDOR 10-7
Filter Coefficient Memory bank 10-2
Filter Data Memory 10-2
FKIR 10-7
FMAC 10-6
initialization 10-2
input data buffer 10-2
interrupt vector table 10-6
memory bank base address pointers 10-2
memory banks 10-4
memory organization 10-4
PMB 10-4
programming model 10-6
Saturation mode 10-6
Sixteen-bit Arithmetic mode 10-6
enable/disable receive portion of ESSI 7-21
enable/disablesan interrupt at beginning of last slot of a
frame when ESSI is in Network mode 7-20
Enhanced Filter Coprocessor (EFCOP) 1-4, 1-14
Enhanced Synchronous Serial Interface (ESSI) 2-15,
2-17, 7-1
see also ESSI
ensure proper operation of the ESSI 7-7
equalization 10-1
ESSI 1-13, 2-3, 2-15, 2-17, 5-2, 7-1
after reset 7-6
Asynchronous mode 7-21
Asynchronous modes 7-11
asynchronous operating mode 7-11
audio enhancements 7-3
byte format 7-13
Clock Generator 7-17
clock generator 7-11
Clock Sources 7-4
codecs 7-13
configure an ESSI exception 7-9
control and time slot registers 7-6
control direction of SC2 I/O signal 7-23
control divide ratio for programmable frame rate
dividers 7-16
control fixed divide-by-eight prescaler in series
with variable prescaler 7-16
Control functionality of SC1 signal 7-15
Control Register A 7-14
Control Register A (CRA)
Alignment Control 7-16
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Frame Rate Divider Control 7-16
Prescale Modulus Select 7-17
Prescaler Range 7-16
Select SC1 7-15
Word Length Control 7-15
Control Register A (CRA) bit definitions 7-14
Control Register B 7-18
Control Register B (CRB)
Clock Polarity 7-22
Clock Source Direction 7-23
Frame Sync Length 7-23
Frame Sync Polarity 7-22
Frame Sync Relative Timing 7-23
Mode Select 7-22
Receive Enable 7-21
Receive Exception Interrupt Enable 7-19
Receive Interrupt Enable 7-20
Receive Last Slot Interrupt Enable 7-20
Serial Control Direction 0 7-24
Serial Control Direction 1 7-24
Serial Control Direction 2 7-23
Serial Output Flag 0 7-24
Serial Output Flag 1 7-24
Shift Direction 7-23
Synchronous/Asynchronous 7-22
Transmit 0 Enable 7-21
Transmit 1 Enable 7-21
Transmit 2 Enable 7-22
Transmit Exception Interrupt Enable 7-20
Transmit Interrupt Enable 7-20
Transmit Last Slot Interrupt Enable 7-20
Control Register B bit definitions 7-19
control whether the receive and transmit functions
occur synchronously or asynchronously with
respect to each other 7-22
control which bit clock edge data and frame sync
are clocked out and latched i 7-22
CRA and CRB 7-10
data and control signals 7-3
determine polarity of the receive and transmit frame
sync signals 7-22
determine relative timing of the receive and
transmit frame sync signal 7-23
determine shift direction of the transmit or receive
shift register 7-23
DMA services the transmitters 7-7
DSP receive data interrupt request 7-29
enable transfer of data from TX1 to Transmit Shift
Register 0 7-21
enable transfer of data from TX1 to Transmit Shift
Register 1 7-21
enable transfer of data from TX2 to Transmit Shift
Register 2 7-22
enable/disable a DSP transmit interrupt 7-20
Motorola
enable/disable DSP receive data interrupt 7-20
enable/disable receive portion 7-21
exceptions 7-8
receive data 7-8
receive data with exception status 7-8
receive last slot interrupt 7-8
transmit data 7-9
transmit data with exception status 7-8
transmit last slot interrupt 7-8
flags 7-13
frame rate divider 7-10
Frame Sync Generator 7-18
frame sync I/O signal 7-6
frame sync length 7-12
frame sync polarity 7-12
frame sync selection 7-11
frame sync signal 7-7, 7-10
frame sync signal format 7-11
frame sync word length 7-12
frame synchronization signals 7-18
Gated clock mode 7-3
GPIO 7-6
GPIO functionality 7-36
handle 24-bit fractional data 7-16
initialization 7-6
initialization example 7-7
internally generated clock and frame sync 7-7
interrupt service routine 7-9
interrupt trigger 7-9
interrupt trigger event 7-9
interrupts 7-8
multiple serial device selection 7-5
Network enhancements 7-2
Network mode 7-1, 7-8, 7-10, 7-22
Normal and Network mode 7-21
Normal and On-Demand modes 7-21
Normal mode 7-1, 7-10
On-Demand mode 7-10, 7-15, 7-21
operating modes 7-6, 7-10
polling, interrupts, DMA 7-7
Port Control Register (PCR) 7-7, 7-36
Port Control Registers (C and D) 7-36
Port Data Register (PDR) 7-38
Port Data Registers (C and D) 7-38
Port Direction Register (PRR) 7-37
Port Direction Registers (C and D) 7-37
programming model 7-14
receive and transmit interrupts 7-11
Receive Data Register 7-31
receive frame sync edge 7-12
receive frame sync occurred during reception of
word in serial receive data register 7-30
Receive Shift Register 7-31
Receive Slot Mask Registers 7-14, 7-35
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Received Data Register 7-14
reset 7-6
RX frame sync 7-11
RX frame sync pulses active 7-11
SC0 7-4
SC1 7-5
SC2 7-6
SCD2 bit in the CRB 7-6
SCK 7-3
select length of data words transferred via
ESSI 7-15
select length of frame sync to be generated or
recognized, 7-23
select source of clock signal 7-23
Serial Control Direction 1 bit 7-5
serial flag signal or receive clock signal 7-4
serial output flag 0 (OF0) bit in the CRB 7-4
single codec with asynchronous transmit and
receive 7-5
specify divide ratio of prescale divider in ESSI
clock generator 7-17
SPI protocol 7-1
SRD 7-3
SSISR 7-6
Status Register 7-29
status register 7-14
Status Register (SSISR)
Receive Data Register Full 7-29
Receive Frame Sync Flag 7-30
Receiver Overrun Error Flag 7-29
Serial Input Flag 0 7-31
Serial Input Flag 1 7-30
Transmit Data Register Empty 7-29
Transmit Frame Sync Flag 7-30
Transmitter Underrun Error Flag 7-30
STD 7-3
SYN bit 7-11
Synchronous mode 7-13
synchronous mode, multiple active transmitters 7-4
Synchronous modes 7-11
synchronous operating mode 7-11
synchronous or asynchronous mode 7-4, 7-5
TE bit 7-19
Time Slot Register 7-34
Transmit Data Registers 7-34
transmit data signal 7-4
transmit enable bits 7-19
transmit enable sequence in On-Demand
mode 7-22
transmit interrupt is enabled 7-9
Transmit Shift Registers 7-31
Transmit Slot Mask Registers 7-14, 7-34
transmitter data out signal of transmit shift register
TX2 7-5
Index-4
TSR 7-9
TX and RX clocks 7-11
variable prescaler 7-16
word length frame sync 7-12
word length frame sync timing 7-12
ESSI Control Register A (CRA) 7-14
ESSI Control Registers 7-14
see also Control Register A, B
ESSI data and control signals
SC0 7-4
SCK 7-3
SRD 7-3
STD 7-3
ESSI programming model 7-14
ESSI Receive Data Register (RX) 7-31
ESSI Receive Exception Interrupt Enable bit
(REIE) 7-19
ESSI Receive Shift Register 7-31
ESSI Receive Slot Mask Registers (RSMA,
RSMB) 7-35
ESSI Status Register (SSISR) 7-29
ESSI Status Register (SSISR) bit definitions 7-29
ESSI Time Slot Register (TSR) 7-34
ESSI Transmit Data Registers 7-14
ESSI Transmit Data registers (TX2, TX1, TX0) 7-34
ESSI Transmit Exception Interrupt Enable bit
(TEIE) 7-20
ESSI Transmit Shift Registers 7-31
ESSI Transmit Slot Mask Registers (TSMA,
TSMB) 7-34
ESSI0 (GPIO) 5-7
ESSI1 (GPIO) 5-8
ESSI-related
program the GPIO pins as outputs or configure the
pins in the PCR as ESSI signals 7-23
Programming the ESSI to use an internal frame
sync 7-23
example of how to initialize the ESSI 7-7
expansion memory 3-1
external address bus 2-6
external bus control 2-6, 2-8, 2-9
external data bus 2-6
external memory expansion port 2-6
external Y I/O space 3-7
F
FCM 10-2
FDM 10-2
features of clock generator 8-19
filter
adaptive 10-1
cross-correlation 10-1
echo cancellation 10-31
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FIR 10-1
IIR 10-1, 10-2
multichannel 10-1
Filter ALU Control Register 10-11, 10-12
Filter Coefficient Base Address 10-13
Filter Coefficient Memory 10-2
Filter Control Status Register 10-8
Filter Count Register 10-7
Filter Data Base Address 10-12
Filter Data Input Register 10-7
Filter Data Memory bank 10-2
Filter Data Output Register 10-7
Filter K-Constant Input Register 10-7
Filter Multiplier and Accumulator 10-6
Finite Impulse Response filter 10-1
FIR
decimation by 2 10-30
filter 10-1
mode 10-1
no decimation 10-22
no decimation/polling 10-25
Real mode (0) 10-22, 10-25, 10-30
single channel
Adaptive mode
no decimation 10-31
DMA and interrupts 10-34
polling 10-33
single channel 10-22, 10-25, 10-30
frame rate divider 7-10
frame sync I/O signal 7-6
frame sync length, ESSI 7-12
frame sync selection
ESSI 7-11
frame sync signal 7-7, 7-10
frame sync signal format, ESSI 7-11
frame synchronization signals, ESSI 7-18
frequency
operation 1-5
functional groups 2-3
G
Global Data Bus 1-10
GPIO 1-12, 2-3
Timers 2-3
GPIO (ESSI0, Port C) 5-7
GPIO (ESSI1, Port D) 5-8
GPIO (HI08, Port B) 5-6
GPIO (SCI, Port E) 5-8
GPIO (Timer) 5-9
GPIO functionality
on ESSI 7-36
GPIO functions 6-4
Motorola
GPIO Port Direction Register (PRR) 7-23
Ground 2-4
PLL 2-4
H
HA8EN bit 6-20
HA9EN bit 6-20
handshaking mechanisms, HI08 6-6
hardware stack 1-8
HASP bit 6-19
CVR 6-15
HI08
HSR
Reflect status of the CVR 6-15
HCSEN bit 6-20
HCSP bit 6-18
HDDR 6-4
HDDS bit 6-18
HDR and HDDR Functionality 6-16
HDR register 6-16
HDRQ bit 6-25
HDSP bit 6-19
HEN bit 6-19
HI08 1-12, 2-3, 2-11, 2-12, 2-13, 2-14, 5-2, 6-1
(GPIO) 5-6
cause the chip to execute an interrupt 6-27
CAUTION 6-29
Chip-Select logic 6-17
Command Vector Register (CVR) 6-8
configuring for host requests 6-9
control HI08 operating mode 6-17
control host request signals 6-20
control HREQ signal for host receive data
transfers 6-26
control output drive of host request signals 6-19
control polarity of host request signals 6-18
control register (ICR) 6-23
controls direction of data flow for each HI08 signal
configured as GPIO 6-16
core communication with HI08 registers 6-13
core interrupts
host command 6-8
receive data register full 6-8
transmit data empty 6-8
CVR
Host Command 6-27
Host Vector 6-27
data registers (RXH/TXH, RXM/TXM, and
RXL/TXL) 6-23
data strobe 6-4
Direct Memory Access (DMA) 6-9
DMA transfers and host bus 6-9
double-buffered mechanism 6-6
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DSP core 6-6
DSP core interrupts 6-7
DSP interrupt routines 6-23
DSP side control registers 6-13
DSP side data registers 6-13
DSP side registers after reset 6-22
DSP to host
data word 6-2
handshaking protocols 6-2
interrupts 6-2
mapping 6-2
transfer modes 6-2
DSP-side conrol registers
Host status register (HSR) 6-13
DSP-side control registers
Host base address register (HBAR) 6-13
Host control register (HCR) 6-13
Host GPIO data direction register
(HDDR) 6-13
Host GPIO data register (HDR) 6-13
Host Port Control Register (HPCR) 6-13
DSP-side registers after reset 6-22
DSP-to-host data transfers 6-21
DSP-to-host transfers 6-6
dual host requests enabled 6-10
dual-strobe bus 6-21
enable host requests via host request (HREQ or
HTRQ) signal 6-26
enable/disable signals configured as GPIO 6-20
enabling host requests 6-9
external host address inputs 6-30
external host programmer’s model 6-23
force execution of any interrupt handler 6-8
force initialization of HI08 hardware 6-25
four kinds of reset 6-31
four reset types 6-22
free core to use its processing power on functions
other than polling or interrupt routines 6-9
general-purpose flag for host-to-DSP
communication 6-25
general-purpose flags for communication between
the host and the DSP 6-7
GPIO configuration options 6-16
HACK signal 6-19
HACK/HRRQ handshake flags 6-23
handshake the execution of host command
interrupts 6-27
handshaking mechanisms 6-6
handshaking protocol 6-6
handshaking protocols 6-6
Core DMA access 6-6
host requests 6-6
software polling 6-6
handshaking protocols, choosing 6-6
Index-6
handshaking protocols, pros and cons of polling 6-7
hardware reset 6-22, 6-31
HBAR
Base Address 6-17
HCR
General-purpose flags for DSP-to-host
communication 6-14
Generate a host command interrupt
request 6-14
Generate a host receive data interrupt
request 6-15
Generate a host transmit data interrupt
request 6-14
Host Receive Interrupt Enable 6-15
HDDR 6-4
HDDR and HDR, GPIO mode 6-4
HDR and HDDR functionality 6-16
HI08 to DSP core interface 6-1
HI08 to host processor interface 6-2
hold data value of corresponding bits of HI08
signals configured as GPIO signals 6-16
Host Base Address Register (HBAR) 6-17
host can access the HI08 in Big-Endian byte
order 6-25
host can access the HI08 in Little-Endian byte
order 6-25
host command 6-23
host commands 6-8
Host Control Register
Host Command Interrupt Enable 6-14
Host control Register
Host Transmit Interrupt Enable 6-14
Host Control Register (HCR)
Host Flags 2, 3 6-14
Host Data Direction Register (HDDR) 6-16
Host Data Register (HDR) 6-16
host interrupt request pins (IRQx) 6-9
host issues command requests to DSP 6-8
host issues vectored interrupt requests 6-23
host performs multiple reads from the HI08 port
Receive Byte Registers 6-6
Host Port Control Register (HPCR) 2-11, 2-12,
2-13, 2-14, 6-17, 6-22, 6-32, 6-33, B-4, B-23
host processor registers 6-13
Host Receive Data Register (HRX) 6-6, 6-22
Host Receive Request (HRRQ 6-9
host request line 6-4
host request pins 6-10
host side
Command Vector Register (CVR) 6-27
Interface Control Register (ICR) 6-24
Interface Status Register (ISR) 6-28
Interface Vector Register (IVR) 6-30
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Receive Byte Registers (RXH, RXM,
RXL) 6-30
registers after reset 6-31
Transmit Byte Registers (TXH, TXM,
TXL) 6-30
Host Status Register (HSR) 6-15
host to DSP
data word 6-1
handshaking protocols 6-1
instructions 6-1
mapping 6-1
Host Transmit Data Register (HTX) 6-21
Host Transmit Data register (HTX) 6-7
host-side register map 6-24
host-to-DSP data transfers 6-6, 6-22
HPCR 6-4
Host Acknowledge Enable 6-19
Host Acknowledge Polarity 6-18
Host Address Line 8 Enable 6-20
Host Address Line 9 Enable 6-20
Host Address Strobe Polarity 6-19
Host Chip Select Enable 6-20
Host Chip Select Polarity 6-18
Host Data Strobe Polarity 6-19
Host Dual Data Strobe 6-18
Host Enable 6-19
Host GPIO Port Enable 6-20
Host Multiplexed Bus 6-19
Host Request Enable 6-20
Host Request Open Drain 6-19
Host Request Polarity 6-18
HREQ pin when a single request line is used 6-10
HREQ/HTRQ handshake flags 6-23
HSR
General-purpose flags for host-to-DSP
communication 6-15
Host Command Pending 6-15
Host Flags 0, 1 6-15
Host Receive Data Full 6-16
Host Transmit Data Empty 6-15
indicate that host transmit data register (HTX)
is empty and can be written by DSP
core 6-15
indicates that host receive data register (HRX)
contains data from host processor 6-16
HTX register 6-30
ICR
Double Host Request 6-25
Host Flag 0 6-25
Host Flag 1 6-25
Host Little Endian 6-25
Initialize 6-25
Receive Request Enable 6-26
Transmit Request Enable 6-26
Motorola
ICR Double Host Request bit 6-9
indicate state of HF2 in the HCR on DSP side 6-28
indicate that TXH
TXM
TXL
and HRX
empty 6-29
registers
are
instructions and addressing modes. 6-4
Interface Control Register (ICR) 6-24
Interface Status Registe (ISR) 6-28
interrupt routines 6-8
interrupt vector number used with MC68000 family
processor vectored interrupts 6-30
Interrupt Vector Register (IVR) 6-30
interrupt-based techniques 6-23
ISR
Host Flag 2 6-28
Host Flag 3 6-28
Host Request 6-28
Receive Data Register Full 6-29
Transmit Data Register Empty 6-29
Transmitter Ready 6-29
masking interrupts 6-8
MOVEP instruction 6-13
multiplexed bus mode 6-20
multiplexed bus modes 6-17
multiplexed mode 6-4
non-multiplexed bus mode 6-20
non-multiplexed mode 6-4
pipeline 6-6
polling techniques 6-23, 6-29
receive and transmit data paths 6-4
Receive Byte Registers 6-6
Receive Byte Registers (RXH
RXM
RXL) 6-30
receive byte registers (RXH
RXM
RXL) contain data from DSP to be
read by host processor 6-29
Receive Data Full bit in the Interface Status
Register 6-7
Receive Data Registers 6-4
Receive Registers (RXH
RHM
RHL) 6-7
register banks 6-4
request service from host 6-9
reserved interrupt vector addresses for
application-specific service routines 6-8
resets, hardware and software 6-4, 6-13
RREQ and RXDF 6-26
select host command interrupt address for use by
host command interrupt logic 6-27
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select the interrupt address to be used 6-8
software polling 6-7
software reset 6-31
status register (ISR) 6-23
STOP command 6-24
STOP instruction 6-31
Stop mode 6-24
timing requirements 6-6
Transmit Byte Registers 6-6
Transmit Byte Registers (TXH
TXM
TXL) 6-30
transmit byte registers (TXH
TXM
TXL) are empty and can be written
by host processor 6-29
Transmit Data Empty bit in the Interface Status
Register 6-7
Transmit Data Registers 6-4
Transmit Registers (TXH
TXM
TXL) 6-7
TRDY 6-29
vector registers (CVR and IVR) 6-23
HI08 GPIO functions 6-4
HI08
ICR 6-30, 6-31
HLEND bit 6-25
HMUX bit 6-19
Host Address Line 8 Enable bit (HA8EN) 6-20
Host Address Line 9 Enable bit (HA9EN) 6-20
Host Address Strobe Polarity bit (HASP) 6-19
Host Base Address Register (HBAR) 6-17
Host base address register (HBAR) 6-13
Host Chip Select Enable 6-20
Host Chip Select Enable bit (HCSEN) 6-20
Host Chip Select Polarity bit (HCSP) 6-18
Host Control Register (HCR) 6-14
Host control register (HCR) 6-13
Host Data Direction Register (HDDR) 6-16
Host data receive register (HRX) 6-13
Host Data Register (HDR) 6-16
Host Data Strobe Polarity bit (HDSP) 6-19
Host data transmit register (HTX) 6-13
Host Dual Data Strobe bit (HDDS) 6-18
Host Enable bit (HEN) 6-19
Host GPIO data direction register (HDDR) 6-13
Host GPIO data register (HDR) 6-13
Host Interface 2-3, 2-11, 2-12, 2-13, 2-14, 6-1
Host Little Endian bit (HLEND) 6-25
Host Multiplexed Bus bit (HMUX) 6-19
Host Port Control Register (HPCR) 2-11, 2-12, 2-13,
2-14, 6-13, 6-17, 6-22, 6-32, 6-33, B-4, B-23
Index-8
host processor address space 6-23
Host Receive Data Full bit 6-7
Host Receive Data Register (HRX) 6-6, 6-22
Host Receive Request (HRRQ 6-9
Host Request
Double 2-3
Single 2-3
host request line 6-4
host request pins 6-10
host requests 6-6
host requests, enabling 6-9
Host Status Register (HSR) 6-15
Host status register (HSR) 6-13
Host Transmit Data Empty bit 6-7
Host Transmit Data Register (HTX) 6-21
Host Transmit Data register (HTX) 6-7
host-to-DSP transfers 6-6
HPCR 6-4
HPCR register 2-11-2-14, ??-6-22, 6-32, 6-33, B-4,
B-23
HR 2-3
HREQ bit 6-28
HREQ signal 6-26
HRX register 6-22
HSR register 6-15
HTX register 6-21
I
I/O space
external Y data Memory 3-7
X data Memory 3-5
Y data Memory 3-7
ICR Double Host Request bit 6-9
ICR register 6-24
Idle Line Interrupt Enable bit (ILIE) 8-13
Idle Line Wakeup mode 8-3
IF0 bit 7-31
IIR
filter 10-1, 10-2
scaling 10-2
ILIE bit 8-13
Indicate state of HF3 in HCR on DSP side 6-28
Infinite Impulse Response filter 10-1
INIT bit 6-25
initialization
EFCOP 10-2
Initialize bit (INIT) 6-25
initializing the timer 9-2, 9-3
Instruction Cache 3-3
instruction cache 3-1
instruction set 1-5
Interface Control Register (ICR) 6-24
Interface Status Register (ISR) 6-28
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Interface Vector Register (IVR) 6-30
internal buses 1-10
internal program memory 3-1
internal Y data Memory 3-5
Internal Y I/O space 3-7
interrupt 1-8
ESSI 7-8
HI08 6-7
priority levels 4-7
sources 4-4, 4-5
interrupt and mode control 2-9
interrupt conditions 5-2
interrupt control 2-9
interrupt DSP after last slot in frame ends regardless of
receive mask register setting 7-20
interrupt handler, forcing execution 6-8
Interrupt Priority Levels 4-7
Interrupt Priority Register P (IPR—P) 4-7
interrupt routines, HI08 6-8
interrupt service routine 7-9
interrupt service routine (ISR) 9-4
Interrupt Source Priorities 4-8
Interrupt Sources 4-5
interrupt trigger event 7-9
interrupt trigger, configuring 7-9
interrupts 5-3
interrupts, HI08
HI08
handshaking protocols
interrupts 6-6
interrupts, receive and transmit 7-11
IPR—P 4-7
ISR Host Request bit (HREQ) 6-28
ISR register 6-28
IVR register 6-30
J
JCLR 5-2
Joint Test Action Group (JTAG) 1-5, 1-9
BSR 4-25
interface 2-20
JSCLR 5-2
JSET 5-2
JSSET 5-2
JTAG 1-9
K
K-constant 10-1
L
LA register 1-8
Motorola
LC register 1-8
Load register (TLR) 9-3
logic 1-5
Loop Address register (LA) 1-8
Loop Counter register (LC) 1-8
M
M68HC11 SCI interface 8-16
MAC 1-6
Manual Conventions 1-2
mapping control registers 5-2
MC68000 family 6-30
MC68681 DUART 8-16
Measurement 9-11
Measurement capture (Mode 6) 9-11
Measurement input period (Mode 5) 9-11
Measurement input width (Mode 4) 9-11
memory
allocation switching 3-2
configuration 3-7
dynamic switching 3-7
expansion 1-10, 3-1
external expansion port 1-10
maps 3-8
off-chip 1-10
on-chip 1-9
shared 10-2
memory maps 3-8, 3-9, 3-10, 3-11, 3-12, 3-13, 3-14,
3-15, 3-16, 3-17, 3-18, 3-19, 3-20, 3-21, 3-22,
3-23, 3-24, 3-25, 3-26, 3-27, 3-28
Memory Switch mode 3-2
X data Memory 3-4
Y data Memory 3-6
MIPS 1-5
mobile switching center 10-1
MODD, MODC, MODB, and MODA 8-7
mode control 2-9
modulo adder 1-7
move (MOVE, MOVEP) instructions 5-2
MOVEP instruction 6-13
multichannel filter 10-1
Multidrop mode 8-2
multiple serial device selection 7-5
multiplexed bus 2-3
multiplexed bus mode 6-20
multiplexed bus modes 6-17
multiplexed mode 6-4
Multiplier-Accumulator (MAC) 1-6
N
network enhancements to ESSI 7-2
Network mode 7-8
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Index-9
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Network mode interrupt, ESSI 7-20
non-multiplexed bus 2-3
non-multiplexed mode 6-4
Freescale Semiconductor, Inc...
O
OF0–OF1 bits 7-19
off-chip memory expansion 3-1
offset adder 1-7
OMR 1-8, 4-11
OnCE 1-5
OnCE module 1-9
interface 2-20
OnCE/JTAG 2-3
On-Chip Emulation (OnCE) module 1-9
on-chip memory 1-9
On-Demand mode 7-10
Operating 4-1
operating mode 4-1 , 4-2
ESSI 7-10
synchronous, ESSI 7-11
Operating Mode Register 4-11
Operating Mode Register (OMR) 1-8
operating mode, HI08 6-17
operating modes 4-1
operational mode select, ESSI 7-22
P
PAB 1-10
PAG 1-7
Parity Error bit (PE) 8-17
PC register 1-8
PCRC register 7-36
PCRD register 7-36
PCRE register 8-25
PCTL 4-21
PCTL register 4-21
PCU 1-7
PDB 1-10
PDC 1-7
PDRC register 7-38
PDRD register 7-38
PDRE register 8-26
PE bit 8-17
Peripheral I/O Expansion Bus 1-10
peripherals programming
bit-oriented instructions 5-2
data transfer methods 5-3
individual reset state 5-1
initializat steps 5-1
interrupts 5-3
mapping control registers 5-2
move (MOVE, MOVEP) instructions 5-2
Index-10
polling 5-3
reading status registers 5-2
peripherals programming, guidelines 5-1
PIC 1-7
PLL 1-8, 2-5
PLL Control Register 4-21
PLL control register (PCTL) 4-21
PMB 10-4
pointers
EFCOP memory bank base address 10-2
polling 5-3
Port A 2-6
Port B 2-3, 2-13, 5-6
Port C 2-3, 2-15, 5-7
Port C and D control registers 7-36
Port C Control Register (PCRC) 7-36
Port C Data Register (PDRC) 7-38
Port C Direction Register (PRRC) 7-37
Port Control Register 7-23
Port D 2-3, 2-17, 5-8
Port D Control Register (PCRD) 7-36
Port D Data Register (PDRD) 7-38
Port D Direction Register (PRRD) 7-37
Port E 5-8
Port E Control Register (PCRE) 8-25
Port E Data Register (PDRE) 8-26
Port E Direction Register (PRRE) 8-26
position independent code 1-7
power 2-4
low 1-5
management 1-5
standby modes 1-5
prescale divider, ESSI 7-17
Prescaler Counter 9-21
Prescaler Load Register (TPLR) 9-3
Program Address Bus (PAB) 1-10
Program Address Generator (PAG) 1-7
Program Control Unit (PCU) 1-7
Program Counter register (PC) 1-8
Program Data Bus (PDB) 1-10
Program Decode Controller (PDC) 1-7
Program Interrupt Controller (PIC) 1-7
Program Memory Expansion Bus 1-10
Program RAM 3-1
Program ROM
bootstrap 3-1
programming model
EFCOP 10-6
ESSI 7-14
SCI 8-9
PRRC register 7-37
PRRD register 7-37
PRRE register 8-26
ESSI
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CRA 7-3
Pulse width modulation mode (Mode 7) 9-11
Freescale Semiconductor, Inc...
R
R8 bit 8-17
RAM
Program 3-1
RCM bit 8-21
RE bit 8-14
reading status registers 5-2
receive and transmit data paths 6-4
Receive Byte Registers 6-6
Receive Byte Registers (RXH, RXM, RXL) 6-30
Receive Clock Mode Source bit (RCM) 8-21
Receive Data Register (RX) 7-31
Receive Data signal (RXD) 8-4
Receive Exception Interrupt Enable bit (REIE) 7-19
Receive Exception Interrupt, enable 7-19
receive frame sync edge, ESSI 7-12
Receive Frame Sync Flag bit (RFS) 7-30
Receive Shift Register 7-31
Receive Slot Mask Registers (RSMA, RSMB) 7-35
Received Bit 8 Address bit (R8) 8-17
Receiver Enable bit (RE) 8-14
Receiver Wakeup Enable bit (SBK) 8-15
register banks 6-4
REIE bit 7-19
RESET 2-10
reset
bus signals 2-6, 2-7
clock signals 2-5
essi signals 2-15, 2-17
host interface signals 2-11
interrupt signals 2-10
JTAG signals 2-21
mode control 2-10
OnCE signals 2-21
phase lock loop signals 2-6
sci signals 2-19
timers 2-20
resets, hardware and software 6-4
reverse-carry adder 1-7
RFS bit 7-30
ROM
bootstrap 3-1, 3-3
RSMA and RSMB 7-14, 7-35
RSMA, RSMB registers 7-35
RWU bit 8-15
RX 7-14, 7-31
RX register 7-31
RXD 8-4
RXD signal 8-4
RXH, RXM, RXL registers 6-30
Motorola
S
saturation status bit 10-2
SBK bit 8-16
SC register 1-8
SC0 7-4
SC0 signal 7-4, 7-5
SC1 7-5
SC2 7-6
SC2 and SC1 signals programmed as outputs 7-23
SCCR 8-19
SCD0 bit 7-24
SCD1 bit 7-24
SCI 1-13, 2-3, 2-19, 5-2, 8-9
Clock Control Register 8-19
Control Register 8-12
data registers 8-22
exceptions 8-8
Idle Line 8-8
Receive Data 8-8
Receive Data with Exception Status 8-8
Timer 8-8
Transmit Data 8-8
GPIO functionality 8-25
I/O signals 8-3
initialization 8-6
operating mode
Asynchronous 8-1
Synchronous 8-1
operating modes 8-1
Asynchronous 8-1
programming model 8-9
Receive Data 8-4
Receive Register 8-23
reset 8-4
state after reset 8-5
Serial Clock 8-4
Status Register 8-17
transmission priority
preamble, break, and data 8-7
Transmit Data 8-4
Transmit Register 8-24
SCI (GPIO) 5-8
SCI Clock Control Register 8-7
SCI Clock Control Register (SCCR) 8-9, 8-19
Clock Divider 8-21
Clock Out Divider 8-21
Receive Clock Mode Source 8-21
Transmit Clock Source 8-21
SCI Clock Control register (SCCR)
Clock Prescaler 8-21
SCI Clock Control Register (SCCR) Bit
Definitions 8-21
SCI Control Register 8-7
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Index-11
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Freescale Semiconductor, Inc.
SCI Control Register (SCR) 8-9, 8-12
Idle Line Interrupt Enable 8-13
Receive with Exception Interrupt Enable 8-12
Receiver Wakeup Enable 8-15
SCI Clock Polarity 8-12
SCI Receive Interrupt Enable 8-13
SCI Shift Direction 8-16
SCI Transmit Interrupt Enable 8-13
Send Break 8-16
Timer Interrupt Enable 8-13
Timer Interrupt Rate 8-12
Transmitter Enable 8-14
Wakeup Mode Select 8-15
Word Select 8-16
SCI Control Register (SCR) Bit Definitions 8-12
SCI Data Registers 8-22
SCI Data Word Formats 8-10
SCI exceptions
Receive Data 8-8
SCI pins
RXD, TXD, SCLK 8-3
SCI Programming Model - Data Registers 8-23
SCI Receive Data Registers (SRX) 8-9
SCI Receive Register (SRX) 8-23
SCI Serial Clock signal (SCLK) 8-4
SCI Status Register (SSR) 8-9, 8-17
Idle Line Flag 8-18
Overrun Error Flag 8-18
Parity Error 8-17
Receive Data Register Full 8-18
Received Bit 8 8-17
Transmit Data Register Empty 8-18
Transmitter Empty 8-19
SCI Status Register (SSR) Bit Definitions 8-17
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Registers (STX) 8-9
SCI Transmit Register (STX)
STX register 8-24
SCK 7-3
SCK signal 7-3
SCLK 8-4
SCLK pin 8-2, 8-6
SCLK signal 8-4
SCR 8-12
SCR Control Register (SCR)
Receiver Enable 8-14
SCR register 8-12
select operational mode of the ESSI 7-22
Send Break bit (SBK) 8-16
Serial Clock 7-3
Serial Clock signal (SCK) 7-3
Serial Communicaiton Interface (SCI)
indicate whether received byte is an address or
data 8-17
Index-12
Serial Communication Interface 2-19
Asynchronous mode 8-2
enable/disable SCI timer interrupt 8-13
Serial Communication Interface (SCI)
Address Mode Wakeup 8-3
bootstrap loading 8-7
byte is ready to transfer from receive shift register
to receive data register 8-18
clock generator features 8-19
control clock polarity sourced or received on the
clock signal (SCLK) 8-12
control divide-by-32 in the SCI Timer interrupt
generator 8-12
crystal frequency 8-6
determine order in which SCI data shift registers
shift data in or out 8-16
empty SCI transmit data register 8-18
enable receiver 8-14
enable transmitter 8-14
enable wakeup function 8-15
enable/disable SCI receive data interrupt 8-13
enable/disable SCI receive data with exception
interrupt 8-12
enable/disables SCI transmit data interrupt. 8-13
establish a periodic interrupt 8-20
Idle Line Wakeup mode 8-3
incorrect parity bit is detected in received
character 8-17
individual reset state (PCR = $0) 8-6
Inter-processor messages 8-2
interrupts 8-6
maximum internal clock 8-19
Multidrop mode 8-2
recover synchronization 8-2
SCR, SCCR 8-6
select format of transmitted and received data 8-16
select wakeup on idle line mode 8-15
select whether internal or external clock is used for
transmitter 8-21
Serial Clock 8-20
STX or STXA 8-22
transmit and receive shift registers 8-2
Wired-OR mode 8-3
Serial Communications Interface (SCI) 1-13, 8-1
Synchronous mode 8-2
Serial Control 0 7-4
Serial Control 0 Direction bit (SCD0) 7-24
serial control 0 signal (SC0) 7-4, 7-5
Serial Control 1 7-5
Serial Control 1 Direction bit (SCD1) 7-24
Serial Control 2 7-6
serial flag signal or receive clock signal 7-4
Serial Input Flag 0 bit (IF0) 7-31
Serial Output Flag bits (OF0–OF1) 7-19
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Freescale Semiconductor, Inc.
Serial Receive Data 7-3
Serial Receive Data signal (SRD) 7-3
serial receive shift register is filled and ready to transfer
to receive data register (RX) but RX is full 7-29
Serial Transmit Data 7-3
Serial Transmit Data signal (STD) 7-3
set timer operating mode 9-3
shared memory 10-2
signal measurement modes 9-11
signals
ESSI data and control 7-3
functional grouping 2-3
Single Data Strobe 2-3
single-strobe bus 6-21
Sixteen-bit Compatibility mode 3-8
Size register (SZ) 1-8
software polling 6-6
SP 1-8
SR register 1-8
SRAM
interfacing 1-10
SRD 7-3
SRD signal 7-3
SRX 8-23
read as SRXL, SRXM, SRXH 8-23
SRX register 8-23
SSISR 7-6, 7-14, 7-29
SSISR register 7-29
SSR 8-17
SSR register 8-17
Stack Counter register (SC) 1-8
Stack Pointer (SP) 1-8
standby
mode
Stop 1-5
Wait 1-5
Status Register (SR) 1-8
status registers, reading 5-2
STD 7-3
STD signal 7-3
sticky bits 10-2
stop
standby mode 1-5
STOP instruction 6-22, 8-6
STX 8-24
STX register
read as STXL, STXM. STXH, and STXA 8-24
switching memory configuration dynamically 3-7
switching memory sizes 3-2
Synchronous mod 8-19
Synchronous mode 7-10, 7-11, 7-13, 8-2, 8-18
synchronous mode 7-4
SZ register 1-8
Motorola
T
TAP 1-9
TCPR register 9-30
TCR register 9-30
TCSR register 9-24
TE bit 8-14, 9-24
TEIE bit 7-20
Test Access Port (TAP) 1-9
TFS bit 7-30
Time Slot Register (TSR) 7-34
timer
control counter preload operation 9-26
control timer clock source, behavior of TIO signal,
and timer mode of operation 9-27
indicate a counter overflow 9-25
indicate that event count is complete 9-25
operating modes 9-4
polarity definition of the incoming signal on the
TIO signal 9-26
reflect value of TIO signal 9-25
select prescalar clock as the timer source clock 9-25
source of TIO value when it is a data output
signal 9-25
special cases 9-21
timer compare interrupts, enable 9-28
Timer (GPIO) 5-9
timer after Reset 9-2
Timer Compare exception 9-3
Timer Compare Register (TCPR) 9-3, 9-30
Timer Control Register 9-2
Timer Control/Status Register (TCSR) 9-24
Data Input 9-25
Data Output 9-25
Direction 9-26
Inverter 9-26
Prescalar Clock Enable 9-25
Timer Compare Flag 9-25
Timer Compare Interrupt Enable 9-28
Timer Control 9-27
Timer Enable 9-28
Timer Overflow Flag 9-25
Timer Overflow Interrupt Enable 9-28
Timer Reload Mode 9-26
Timer Control/Status Register (TCSR) bit
definitions 9-24
Timer Count Register (TCR) 9-30
Timer Enable bit (TE) 9-24
timer exception, configuring 9-4
timer exceptions 9-3
Timer GPIO (Mode 0) 9-5
timer initialization 9-2, 9-3
Timer Load Register (TLR) 9-29
timer mode
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Index-13
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
mode 5—measurement input period 9-13
mode 6—measurement capture 9-15
mode 7—pulse width modulation 9-16
mode 8—reserved 9-19
mode 9—watchdog pulse 9-19
mode 10—measurement toggle 9-20
modes 11–15—reserved 9-21
Timer module 1-14
architecture 9-1
timer block diagram 9-1
timer opeating modes
PWM, mode 7 9-5
timer operating mode, setting 9-3
timer operating modes
Event Counter (Mode 3) 9-10
Event counter, mode 3 9-4
GPIO (Mode 0) 9-5
GPIO, mode 0 9-4
Input pulse, mode 5 9-5
Input width, mode 4 9-5
Measurement Capture (Mode 6) 9-15
Measurement Input Width (Mode 4) 9-12
overview 9-5
Pulse (Mode 1) 9-7
Pulse Width Modulation (PWM, Mode 7) 9-16
Pulse, mode 1 9-4
Pulse, mode 9 9-5
reserved modes 9-20, 9-21
signal measurement modes 9-11
Toggle (Mode 2) 9-8
Toggle, mode 10 9-5
Toggle, mode 2
9-4
Watchdog 9-5
Watchdog modes 9-18
Watchdog Pulse 9-18
Watchdog Pulse (Mode 9) 9-19
Watchdog Pulse mode 9-19
Watchdog Toggle 9-18
Watchdog Toggle (Mode 10) 9-20
Timer Overflow exception 9-3
Timer Prescalar Count Register (TPCR)
Prescalar Counter Value 9-24
Timer Prescaler Count Register (TPCR) 9-24
Timer Prescaler Count Register (TPCR) bit
definitions 9-24
Timer Prescaler Load Register (TPLR) 9-23
Prescaler Preload Value 9-23
Timer Prescaler Load Register (TPLR) bit
definitions 9-23
timer, enabling 9-3
Timers 2-3, 2-19
TLR register 9-29
TPCR register 9-24
Index-14
TPLR register 9-23
transcoder basestation 10-1
Transmit Byte Registers 6-6
Transmit Byte Registers (TXH, TXM, TXL) 6-30
Transmit Data signal (TXD) 8-4
transmit data signal, ESSI 7-4
Transmit Exception Interrupt Enable bit (TEIE) 7-20
Transmit Frame Sync Flag bit (TFS) 7-30
transmit interrupt enable, ESSI 7-20
Transmit Shift Registers 7-31
Transmit Slot Mask Registers (TSMA, TSMB) 7-34
Transmitter Enable bit (TE) 8-14
HI08
ICR 6-31
triple timer 5-2
triple timer module 1-14
TSMA and TSMB 7-14, 7-34
TSMA, TSMB registers 7-34
TSR 7-34
TSR register 7-34
TX0–TX2 7-14, 7-34
TX2, TX1, TX0 registers 7-34
TXD 8-4
TXD signal 8-4
HI08
HSR 6-31
TXH, TXM, TXL registers 6-30
V
VBA register 1-8
Vector Base Address register (VBA) 1-8
vocoder 10-1
W
wait standby mode 1-5
see also reset
WAKE bit 8-15
Wakeup Mode Select bit (WAKE) 8-15
Watchdog pulse 9-18
Watchdog Pulse mode 9-19
Watchdog Toggle 9-18
Wired-OR Select bit (WOMS) 8-14
WOMS bit 8-14
word length frame sync 7-12
X
X data memory 3-3
X I/O space 3-5
X Memory Address Bus (XAB) 1-10
X Memory Data Bus (XDB) 1-10
X Memory Expansion Bus 1-10
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Freescale Semiconductor, Inc.
XAB 1-10
XDB 1-10
Y
Freescale Semiconductor, Inc...
Y data Memory 3-5
internal 3-5
Y I/O space 3-7
Y Memory Address Bus (YAB) 1-10
Y Memory Data Bus (YDB) 1-10
Y Memory Expansion Bus 1-10
YAB 1-10
YDB 1-10
Motorola
DSP56311 User’s Manual
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Index-15
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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