LMS1485 5V Low Power RS-485 Differential Bus - tyro

LMS1485 5V Low Power RS-485 Differential Bus - tyro
LMS1485
LMS1485 5V Low Power RS-485 Differential Bus Transceiver
Literature Number: SNOSA29E
LMS1485
October 12, 2011
5V Low Power RS-485 Differential Bus Transceiver
General Description
Features
The LMS1485 is a low power differential bus/line transceiver
designed for high speed bidirectional data communication on
multipoint bus transmission lines. It is designed for balanced
transmission lines. It meets ANSI Standards TIA/EIA RS422B, TIA/EIA RS485-A and ITU recommendation and V.11 and
X.27.
The LMS1485 combines a TRI-STATE® differential line driver
and differential input receiver, both of which operate from a
single 5.0V power supply. The driver and receiver have an
active high and active low, respectively, that can be externally
connected to function as a direction control. The driver and
receiver differential inputs are internally connected to form
differential input/output (I/O) bus ports that are designed to
offer minimum loading to bus whenever the driver is disabled
or when VCC = 0V. These ports feature wide positive and
negative common mode voltage ranges, making the device
suitable for multipoint applications in noisy environments.
The LMS1485 is build with National’s advanced BiCMOS process and is available in a 8-Pin SOIC package. It is a drop-in
socket replacement to ADI’s ADM1485 and LTC’s LT1485.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Meet ANSI standard RS-485-A and RS-422-B
Data rate 30Mbps
Single supply voltage operation, 5V
Wide input and output voltage range
Thermal shutdown protection
Short circuit protection
Driver propagation delay 10ns
Receiver propagation delay 25ns
High impedance outputs with power off
Open circuit fail-safe for receiver
Extended operating temperature range −40°C to 85°C
ESD rating 8kV HBM
Drop-in replacement to ADM1485 and LT1485
Available in 8-pin SOIC
Low supply current, ICC = 1mA
Applications
■
■
■
■
■
■
■
■
Low power RS-485 systems
Network hubs, bridges, and routers
Point of sales equipment (ATM, barcode scanners,…)
Local area networks (LAN)
Integrated service digital network (ISDN)
Industrial programmable logic controllers
High speed parallel and serial applications
Multipoint applications with noisy environment
Typical Application
20048801
A typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable.
Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all
drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
200488
200488 Version 6 Revision 2
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LMS1485 5V Low Power RS-485 Differential Bus Transceiver
OBSOLETE
LMS1485
Connection Diagram
8-Pin SOIC
20048802
Top View
Ordering Information
Package
Part Number
LMS1485M
LMS1485MX
8-Pin SOIC
LMS1485IM
LMS1485IMX
Package Marking
LMS1485M
LMS1485IM
Transport Media
NSC Drawing
95 Units/Rail
2.5k Units Tape and Reel
95 Units/Rail
M08A
2.5k Units Tape and Reel
Pin Descriptions
Pin #
I/O
Name
Function
1
O
RO
Receiver Output: If A > B by 200 mV, RO will be high; If A < B by 200mV, RO will be low. RO will be
high also if the inputs (A and B) are open (non-terminated)
2
I
RE
Receiver Output Enable: RO is enabled when RE is low; RO is in TRI-STATE when RE is high
3
I
DE
Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in TRISTATE when DE is low. Pins A and B also function as the receiver input pins (see below)
4
I
DI
Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low when
the driver is enabled
5
N/A
GND
Ground
6
I/O
A
Non-inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling
levels
7
I/O
B
Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling
levels
8
N/A
VCC
Power Supply: 4.75V ≤ VCC ≤ 5.25V
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LMS1485
Truth Table
DRIVER SECTION
RE
DE
DI
A
B
X
H
H
H
L
X
H
L
L
H
X
L
X
Z
Z
RECEIVER SECTION
RE
DE
A-B
RO
L
L
H
L
L
≥ +0.2V
≤ −0.2V
H
X
X
Z
L
L
OPEN *
H
L
Note: * = Non Terminated, Open Input only
X = Irrelevant
Z = TRI-STATE
H = High level
L = Low level
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LMS1485
ESD Rating (Note 4, Note 8)
ESD Rating (Note 4, Note 9)
Soldering Information
Infrared or Convection (20 sec.)
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage, VCC (Note 2)
Input Voltage, VIN (DI, DE, or RE)
Voltage Range at Any Bus Terminal
(AB)
Receiver Outputs
7V
−0.3V to VCC+ 0.3V
235°C
Operating Ratings
Supply Voltage, VCC
Voltage at any Bus Terminal
(Separately or Common Mode)
VIN or VIC
High-Level Input Voltage, VIH
(Note 5)
Low-Level Input Voltage, VIL
(Note 5)
Differential Input Voltage, VID
(Note 6)
−7V to 12V
−0.3V to VCC + 0.3V
Package Thermal Impedance, θJA
SOIC (Note 3)
Junction Temperature (Note 3)
Operating Free-Air Temperature
Range, TA
Commercial
Industrial
Storage Temperature Range
8kV
2kV
125°C/W
150°C
0°C to 70°C
−40°C to 85°C
−65°C to 150°C
Min Nom Max
4.75 5.0 5.25
−7
12
2
V
V
V
0.8
V
±12
V
Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5
V
Driver Section
VOD
Differential Output Voltage
R = ∞ (Figure 1)
VOD1
Differential Output Voltage
R = 50Ω (Figure 1), RS-422
2
5
V
VOD2
Differential Output Voltage
R = 27Ω (Figure 1), RS-485
1.5
5
V
VOD3
Differential Output Voltage
VTEST = −7V to + 12V (Figure 2)
1.5
5
V
ΔVOD
Change in Magnitude of
Differential Output Voltage
R = 27Ω or 50Ω (Figure 1 ), (Note 7)
−0.2
0.2
V
VOC
Common-Mode Output Voltage R = 27Ω or 50Ω (Figure 1), (Note 7)
3
V
ΔVOC
Change in Magnitude of
R = 27Ω or 50Ω (Figure 1), (Note 7)
Common-Mode Output Voltage
−0.2
0.2
V
IOSD
Short-Circuit Output Current
VO = High, −7V≤VCM ≤+12V
−250
250
VO = Low, −7V ≤VCM ≤+12V
−250
250
0.8
mA
VINL
CMOS Input Logic Threshold
Low
DE, DI, RE
V
VINH
CMOS Input Logic Threshold
High
DE, DI, RE
2
IIN
Logic Input Current
DE, DI
−1
1
μA
−0.2
+0.2
V
V
Receiver Section
VTH
Differential Input Threshold
Voltage
−7V ≤ VCM ≤ + 12V
ΔVTH
Input Hysteresis Voltage
(VTH+ − VTH−)
VCM = 0
RIN
Input Resistance
−7V ≤ VCM ≤ + 12V
IIN
Input Current (A, B)
VIN = 12V
70
12
−0.8
IRE
Logic Enable Input Current
RE
VOL
CMOS Low-Level Output
Voltage
IOL = 4mA
VOH
CMOS High-Level Output
Voltage
IOH = −4mA
4
IOSR
Short-Circuit Output Current
VO = GND or VCC
7
−1
4
200488 Version 6 Revision 2
kΩ
1
VIN = −7V
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mV
Print Date/Time: 2011/10/12 09:50:35
mA
1
μA
0.4
V
V
85
mA
IOZ
Parameter
Conditions
0.4V ≤VO ≤+2.4V
Tristate Output Leakage
Current
Min
Typ
−1
Max
Units
1
μA
Power Supply Current
ICC
Supply Current
Driver Enabled, Output = No Load,
Digital Inputs = GND or VCC
1.1
2.2
mA
Driver Disabled, Output = No Load,
Digital Inputs = GND or VCC
1
2.2
mA
20
ns
Switching Characteristics
Driver
TPLH,
TPHL
Propagation Delay Input to
Output
RL = 54Ω, CL = 100pF
(Figure 3, Figure 7)
11
TSKEW
Driver Output Skew
RL = 54Ω, CL = 100pF
(Figure 3, Figure 7)
1
TR,
TF
Driver Rise and Fall Time
RL = 100Ω, CL = 100pF
(Figure 3, Figure 7)
5
10
ns
TENABLE
Driver Enable to Ouput Valid
Time
(Figure 4, Figure 8)
18
32
ns
TDISABLE
Output Disable Time
(Figure 4, Figure 8)
20
40
ns
TPLH,
TPHL
Propagation Delay Input to
Output
CL = 15pF
(Figure 5, Figure 7)
33
55
ns
TSKEW
Receiver Output Skew
(Figure 5, Figure 7)
2
TENABLE
Receiver Enable Time
(Figure 6, Figure 10)
6
25
ns
TDISABLE
Receiver Disable Time
(Figure 6, Figure 10)
15
25
ns
ns
Receiver
18
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics
Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ
(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ.
Note 5: Voltage limits apply to DI, DE, RE pins.
Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B.
Note 7: |ΔVOD| and |ΔVOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels.
Note 8: ESD rating applies to pins 6 and 7
Note 9: ESD rating applies to pins 1, 2, 3, 4, 5 and 8
5
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LMS1485
Symbol
LMS1485
Typical Performance Characteristics
Receiver Output Low Voltage vs. Output Current
Receiver Output High Voltage vs. Output Current
20048813
20048814
Receiver Output High Voltage vs. Temperature
Receiver Output Low Voltage vs. Temperature
20048815
20048816
Driver Differential Output Voltage vs. Output Current
Driver Differential Output Voltage vs. Temperature
RL = 54Ω
20048817
20048818
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Driver Output High Voltage vs. Output Current
20048820
20048819
Supply Current vs. Temperature
Receiver Skew vs. Temperature
20048822
20048821
Driver Skew vs. Temperature
20048823
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LMS1485
Driver Output Low Voltage vs. Output Current
LMS1485
Parameter Measuring Information
20048803
FIGURE 1. Test Circuit for VOD and VOC
20048804
FIGURE 2. Test Circuit for VOD3
20048805
FIGURE 3. Test Circuit for Driver Propagation Delay
20048806
FIGURE 4. Test Circuit for Driver Enable / Disable
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LMS1485
20048807
FIGURE 5. Test Circuit for Receiver Propagation Delay
20048808
FIGURE 6. Test Circuit for Receiver Enable / Disable
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LMS1485
Switching Characteristics
20048811
FIGURE 9. Receiver Propagation Delay
20048809
FIGURE 7. Driver Propagation Delay, Rise / Fall Time
20048812
FIGURE 10. Receiver Enable / Disable Time
20048810
FIGURE 8. Driver Enable / Disable Time
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POWER LINE NOISE FILTERING
A factor to consider in designing power and ground is noise
filtering. A noise filtering circuit is designed to prevent noise
generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method
is to place by-pass capacitors (Cbp) between the power and
ground lines.
Placing a by-pass capacitor (Cbp) with the correct value at the
proper location solves many power supply noise problems.
Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not ideal, they
20048824
FIGURE 11. Placement of by-pass Capacitors, Cbp
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LMS1485
may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may
be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10μF, between the power supply pin and ground to filter out low
frequencies and a 0.1μF to filter out high frequencies.
By pass-capacitors must be mounted as close as possible to
the IC to be effective. Long leads produce higher impedance
at higher frequencies due to stray inductance. Thus, this will
reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because they have
lower inductance.
Application Information
LMS1485
Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
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LMS1485
Notes
13
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LMS1485 5V Low Power RS-485 Differential Bus Transceiver
Notes
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