HCS12 V1.5 Core User Guide Version 1.2

HCS12 V1.5 Core User Guide Version 1.2

Freescale Semiconductor, Inc.

DOCUMENT NUMBER

S12CPU15UG/D

HCS12 V1.5 Core

User Guide

Version 1.2

Original Release Date: 12 May 2000

Revised: 17 August 2000

For More Information On This Product,

Go to: www.freescale.com

Revision History

Revision History

Freescale Semiconductor, Inc.

Release Number

1.2

1.2

1.1

1.0

Date

17 August 2000

13 October 2000

21 July 2000

12 May 2000

Author Summary of Changes

Update allocated RAM space table.

Security enhancements, add core_exp_t2, core_per_t2 outputs and peri_clk2, peri_clk4, and ram_fmts inputs.

Correct access detail for LSL instruction in appendix B

Original draft. Distributed only within Motorola

Version 1.2 — 17 August 2000

For More Information On This Product,

Go to: www.freescale.com

HCS12 V1.5 Core

Table of Contents

Section 1 Introduction

1.1

Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

1.3

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

1.4

Architectural Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

1.5

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

1.6

Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

1.6.1

1.6.2

Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Memory Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

1.7

Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

1.8

Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

1.8.1

1.8.2

Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

1.8.3

1.8.4

1.8.5

1.8.6

1.8.7

Operation Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Access Detail Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Condition Code State Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Section 2 Nomenclature

2.1

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.2

Units and Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.3

Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.4

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Section 3 Core Registers

3.1

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.1.1

Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.1.2

3.1.3

Index Registers (X and Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

3.1.4

3.1.5

Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

3.2

Core Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

For More Information On This Product,

Go to: www.freescale.com

Section 4 Instructions

4.1

Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.2

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.2.1

4.2.2

Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Inherent Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

4.2.3

4.2.4

4.2.5

4.2.6

Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Direct Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

4.2.7

4.2.8

Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Instructions Using Multiple Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

4.3

Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.1

Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

4.3.2

4.3.3

4.3.4

4.3.5

Transfer and Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Add and Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Binary Coded Decimal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.3.6

4.3.7

4.3.8

4.3.9

Decrement and Increment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Compare and Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Boolean Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Clear, Complement, and Negate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.3.10

Multiply and Divide Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.3.11

Bit Test and Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.3.12

Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

4.3.13

Fuzzy Logic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.3.14

Maximum and Minimum Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

4.3.15

Multiply and Accumulate Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.3.16

Table Interpolation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

4.3.17

Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

4.3.18

Jump and Subroutine Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4.3.19

Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

4.3.20

Index Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

4.3.21

Stacking Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

4.3.22

Load Effective Address Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

4.3.23

Condition Code Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

4.3.24

STOP and WAI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

For More Information On This Product,

Go to: www.freescale.com

4.3.25

Background Mode and Null Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .91

4.4

High-Level Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

4.4.1

4.4.2

Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Parameters and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

4.4.3

4.4.4

4.4.5

4.4.6

Increment and Decrement Operators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Higher Math Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Conditional If Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Case and Switch Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4.4.7

4.4.8

Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4.4.9

Instruction Set Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4.5

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

4.6

Transfer and Exchange Postbyte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

4.7

Loop Primitive Postbyte (lb) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

4.8

Indexed Addressing Postbyte (xb) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Section 5 Instruction Execution

5.1

Normal Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

5.2

Execution Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

5.2.1

5.2.2

No Movement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Advance and Load from Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

5.3

Changes of Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.3.1

Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.3.2

5.3.3

Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.3.4

Jumps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.4

Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

5.4.1

5.4.2

Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

5.4.3

5.4.4

5.4.5

5.4.6

Operation Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Access Detail Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.4.7

Condition Code State Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.5

External Visibility Of Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.5.1

Instruction Queue Status Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

For More Information On This Product,

Go to: www.freescale.com

5.5.2

5.5.3

5.5.4

5.5.5

5.5.6

No Movement (0:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

ALD — Advance and Load from Data Bus (1:0) . . . . . . . . . . . . . . . . . . . . . . . . . . .128

INT — Start Interrupt (0:1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

SEV — Start Even Instruction (1:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

SOD — Start Odd Instruction (1:1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

Section 6 Exception Processing

6.1

Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

6.1.1

Reset Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

6.1.2

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

6.2

Exception Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

6.3

Exception Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

6.3.1

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

6.3.2

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Section 7 Core Interface

7.1

Core Interface Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

7.1.1

Signal Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

7.2

Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

7.2.1

Internal Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

7.2.2

7.2.3

7.2.4

7.2.5

External Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Vector Request/Acknowledge Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Stop and Wait Mode Control/Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

7.2.6

7.2.7

Background Debug Mode (BDM) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . .151

Memory Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

7.2.8

Scan Control Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

7.3

Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155

Multiplexed External Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158

General Internal Read Visibility Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161

Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

Section 8 Core Clock and Reset Connections

8.1

Clocking Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

For More Information On This Product,

Go to: www.freescale.com

8.1.1

8.1.2

8.1.3

8.1.4

Basic Clock Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

Reset Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Phase-Locked Loop Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

HCS12 CPU Wait and Stop Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

8.2

Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

8.3

Detailed Clock and Reset Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

8.3.1

8.3.2

Clock and Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167

Stop and Wait Mode Control/Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Section 9 Core Power Connections

9.1

Power Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

9.1.1

Power and Ground Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Section 10 Interrupt (INT)

10.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

10.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

10.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

10.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172

10.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.3.1

Interrupt Test Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.3.2

Interrupt Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

10.3.3

Highest Priority I Interrupt (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

10.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

10.4.1

Interrupt Exception Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

10.4.2

Reset Exception Requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

10.4.3

Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

10.5

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.5.1

Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.5.2

Special Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.5.3

Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.6

Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.6.1

Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.6.2

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.6.3

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

10.7

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

Section 11 Module Mapping Control (MMC)

For More Information On This Product,

Go to: www.freescale.com

11.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

11.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

11.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

11.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

11.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

11.3.1

Initialization of Internal RAM Position Register (INITRM) . . . . . . . . . . . . . . . . . . . .182

11.3.2

Initialization of Internal Registers Position Register (INITRG) . . . . . . . . . . . . . . . . .182

11.3.3

Initialization of Internal EEPROM Position Register (INITEE) . . . . . . . . . . . . . . . . .183

11.3.4

Miscellaneous System Control Register (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . .184

11.3.5

Reserved Test Register Zero (MTST0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.3.6

Reserved Test Register One (MTST1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

11.3.7

Memory Size Register Zero (MEMSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

11.3.8

Memory Size Register One (MEMSIZ1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

11.3.9

Program Page Index Register (PPAGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

11.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

11.4.1

Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

11.4.2

Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

11.4.3

Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

11.5

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

11.5.1

Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

11.5.2

MMC Bus Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

Section 12 Multiplexed External Bus Interface (MEBI)

12.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

12.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

12.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

12.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

12.2.1

MEBI Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

12.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

12.3.1

Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

12.3.2

Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

12.3.3

Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

12.3.4

Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

12.3.5

Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211

12.3.6

Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

12.3.7

Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

For More Information On This Product,

Go to: www.freescale.com

12.3.8

MODE Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

12.3.9

Pullup Control Register (PUCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

12.3.10 Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219

12.3.11 External Bus Interface Control Register (EBICTL) . . . . . . . . . . . . . . . . . . . . . . . . . .220

12.3.12 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

12.3.13 Reserved Registers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

12.3.14 Port K Data Register (PORTK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

12.3.15 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223

12.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

12.4.1

External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

12.4.2

External Data Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

12.4.3

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

12.4.4

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

12.4.5

External System Pin Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

12.4.6

Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

12.4.7

Stretched Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

12.4.8

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

12.4.9

Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

12.4.10 Secure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.5

Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.5.1

Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.5.2

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.5.3

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.6

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.6.1

Peripheral Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

12.6.2

Special Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233

Section 13 Breakpoint (BKP)

13.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

13.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235

13.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

13.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

13.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

13.3.1

Breakpoint Control Register 0 (BKPCT0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

13.3.2

Breakpoint Control Register 1 (BKPCT1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

13.3.3

Breakpoint First Address Expansion Register (BKP0X). . . . . . . . . . . . . . . . . . . . . .242

For More Information On This Product,

Go to: www.freescale.com

13.3.4

Breakpoint First Address High Byte Register (BKP0H) . . . . . . . . . . . . . . . . . . . . . .243

13.3.5

Breakpoint First Address Low Byte Register (BKP0L) . . . . . . . . . . . . . . . . . . . . . . .243

13.3.6

Breakpoint Second Address Expansion Register (BKP1X) . . . . . . . . . . . . . . . . . . .243

13.3.7

Breakpoint Data (Second Address) High Byte Register (BKP1H) . . . . . . . . . . . . . .244

13.3.8

Breakpoint Data (Second Address) Low Byte Register (BKP1L) . . . . . . . . . . . . . . .244

13.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

13.4.1

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

13.4.2

Breakpoint Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

13.5

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Section 14 Background Debug Mode (BDM)

14.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

14.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

14.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

14.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

14.2.1

Background Interface Pin (BKGD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

14.2.2

High Byte Instruction Tagging Pin (TAGHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

14.2.3

Low Byte Instruction Tagging Pin (TAGLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

14.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

14.3.1

BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

14.3.2

BDM CCR Holding Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

14.3.3

BDM Internal Register Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

14.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

14.4.1

Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

14.4.2

Enabling and Activating BDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

14.4.3

BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

14.4.4

Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

14.4.5

BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

14.4.6

BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

14.4.7

Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

14.4.8

Instruction Tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

14.5

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

14.5.1

Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

14.5.2

Special Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.5.3

Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.6

Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

For More Information On This Product,

Go to: www.freescale.com

14.6.1

Run Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.6.2

Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.6.3

Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.7

Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.8

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262

14.8.1

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

14.8.2

BDM Instruction Register (Hardware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

14.8.3

BDM Instruction Register (Firmware) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

14.8.4

BDM Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266

14.8.5

BDM Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

14.8.6

BDM Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

14.8.7

Special Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

14.8.8

Standard BDM Firmware Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

14.8.9

Secured Mode BDM Firmware Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

Section 15 Secured Mode of Operation

15.1

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

15.1.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279

15.1.2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

15.2

Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

15.3

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

15.4

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

15.4.1

Normal Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

15.4.2

Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

15.4.3

Unsecuring The System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

15.5

Motorola Internal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

15.5.1

BDM Secured Mode Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

Appendix A Instruction Set and Commands

A.1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

A.2

Glossary Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

A.2.1

Condition Code State Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

A.2.2

Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286

A.2.3

Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

A.2.4

Operator Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

A.2.5

Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

For More Information On This Product,

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A.2.6

Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

A.2.7

CPU Cycles Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289

A.3

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292

Appendix B Fuzzy Logic Support

B.1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503

B.2

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503

B.3

Fuzzy Logic Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503

B.3.1

Fuzzification (MEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .505

B.3.2

Rule Evaluation (REV and REVW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .506

B.3.3

Defuzzification (WAV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508

B.4

Example Inference Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .508

B.5

MEM Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510

B.5.1

Membership Function Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510

B.5.2

Abnormal Membership Function Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511

B.6

REV, REVW Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514

B.6.1

Unweighted Rule Evaluation (REV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .514

B.6.2

Weighted Rule Evaluation (REVW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .518

B.7

WAV Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523

B.7.1

Initialization Prior to Executing WAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523

B.7.2

WAV Interrupt Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523

B.7.3

Cycle-by-Cycle Details for WAV and wavr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .524

B.8

Custom Fuzzy Logic Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527

B.8.1

Fuzzification Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527

B.8.2

Rule Evaluation Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .529

B.8.3

Defuzzification Variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530

Appendix C M68HC11 to HCS12 Upgrade

C.1

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531

C.2

Source Code Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .531

C.3

Programmer’s Model and Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533

C.4

True 16-Bit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533

C.4.1

Bus Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533

C.4.2

Instruction Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533

C.4.3

Stack Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534

C.5

Improved Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535

For More Information On This Product,

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C.5.1

Constant Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536

C.5.2

Autoincrement/Autodecrement Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537

C.5.3

Accumulator Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537

C.5.4

Indirect Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538

C.6

Improved Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538

C.6.1

Reduced Cycle Counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538

C.6.2

Fast Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538

C.6.3

Code Size Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539

C.7

Additional Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540

C.7.1

New Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540

C.7.2

Memory-to-Memory Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542

C.7.3

Universal Transfer and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542

C.7.4

Loop Construct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542

C.7.5

Long Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542

C.7.6

Minimum and Maximum Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .543

C.7.7

Fuzzy Logic Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .543

C.7.8

Table Lookup and Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544

C.7.9

Extended Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544

C.7.10

Push and Pull D and CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544

C.7.11

Compare SP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544

C.7.12

Support for Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544

For More Information On This Product,

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For More Information On This Product,

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List of Figures

Figure 1-1 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 1-2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 3-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 3-2 Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 3-3 Accumulator B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 3-4 Index Register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 3-5 Index Register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 3-6 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 3-7 Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 3-8 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 3-9 Core Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 5-1 Queue Status Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . 127

Figure 7-1 Core Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Figure 7-2 Basic 8-bit Peripheral Read Timing . . . . . . . . . . . . . . . . . . . . 153

Figure 7-3 Basic 16-bit Peripheral Read Timing . . . . . . . . . . . . . . . . . . . 153

Figure 7-4 Basic 8-bit Memory Read Timing. . . . . . . . . . . . . . . . . . . . . . 154

Figure 7-5 Basic 16-bit Memory Read Timing. . . . . . . . . . . . . . . . . . . . . 154

Figure 7-6 Basic 8-bit Core Register Read Timing . . . . . . . . . . . . . . . . . 155

Figure 7-7 Basic 16-bit Core Register Read Timing . . . . . . . . . . . . . . . . 155

Figure 7-8 Basic 8-bit Peripheral Write Timing . . . . . . . . . . . . . . . . . . . . 156

Figure 7-9 Basic 16-bit Peripheral Write Timing . . . . . . . . . . . . . . . . . . . 156

Figure 7-10 Basic 8-bit Memory Write Timing. . . . . . . . . . . . . . . . . . . . . . 157

Figure 7-11 Basic 16-bit Memory Write Timing. . . . . . . . . . . . . . . . . . . . . 157

Figure 7-12 Basic 8-bit Core Register Write Timing . . . . . . . . . . . . . . . . . 158

Figure 7-13 Basic 16-bit Core Register Write Timing . . . . . . . . . . . . . . . . 158

Figure 7-14 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 7-15 General Internal Read Visibility Timing . . . . . . . . . . . . . . . . . 161

Figure 8-1 Core Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Figure 8-2 System Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 10-1 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 10-2 Interrupt Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 10-3 Interrupt Test Control Register (ITCR). . . . . . . . . . . . . . . . . . 173

Figure 10-4 Interrupt TEST Registers (ITEST) . . . . . . . . . . . . . . . . . . . . . 174

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Figure 10-5 Highest Priority I Interrupt Register (HPRIO). . . . . . . . . . . . . 175

Figure 11-1 Module Mapping Control Block Diagram . . . . . . . . . . . . . . . . 180

Figure 11-2 Module Mapping Control Register Summary. . . . . . . . . . . . . 181

Figure 11-3 INITRM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 11-4 INITRG Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Figure 11-5 INITEE Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

Figure 11-6 Miscellaneous System Control Register (MISC) . . . . . . . . . . 184

Figure 11-7 Reserved Test Register Zero (MTST0) . . . . . . . . . . . . . . . . . 185

Figure 11-8 Reserved Test Register One (MTST1) . . . . . . . . . . . . . . . . . 185

Figure 11-9 Memory Size Register Zero . . . . . . . . . . . . . . . . . . . . . . . . . . 186

Figure 11-10 Memory Size Register One . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Figure 11-11 Program Page Index Register (PPAGE) . . . . . . . . . . . . . . . . 188

Figure 11-13 Mapping Test Register Zero (MTST0) . . . . . . . . . . . . . . . . . . 196

Figure 11-14 Mapping Test Register One (MTST1) . . . . . . . . . . . . . . . . . . 197

Figure 12-1 MEBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 12-2 MEBI Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . 207

Figure 12-3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . 208

Figure 12-4 Data Direction Register A (DDRA). . . . . . . . . . . . . . . . . . . . . 209

Figure 12-5 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . 210

Figure 12-6 Data Direction Register B (DDRB). . . . . . . . . . . . . . . . . . . . . 210

Figure 12-7 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . 211

Figure 12-8 Data Direction Register E (DDRE). . . . . . . . . . . . . . . . . . . . . 212

Figure 12-9 Port E Assignment Register (PEAR) . . . . . . . . . . . . . . . . . . . 213

Figure 12-10 MODE Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

Figure 12-11 Pullup Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . 218

Figure 12-12 Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . 219

Figure 12-13 External Bus Interface Control Register (EBICTL) . . . . . . . . 220

Figure 12-14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . 220

Figure 12-15 Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 12-16 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . 222

Figure 12-17 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . 223

Figure 13-1 Breakpoint Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Figure 13-2 Breakpoint Register Summary. . . . . . . . . . . . . . . . . . . . . . . . 238

Figure 13-3 Breakpoint Control Register 0 (BKPCT0) . . . . . . . . . . . . . . . 239

Figure 13-4 Breakpoint Control Register 1 (BKPCT1) . . . . . . . . . . . . . . . 240

Figure 13-5 Breakpoint First Address Expansion Register (BKP0X) . . . . 242

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Figure 13-6 Breakpoint First Address High Byte Register (BKP0H) . . . . . 243

Figure 13-7 Breakpoint First Address Low Byte Register (BKP0L). . . . . . 243

Figure 13-8 Breakpoint Second Address Expansion Register (BKP1X) . . 244

Figure 13-9 Breakpoint Data High Byte Register (BKP1H). . . . . . . . . . . . 244

Figure 13-10 Breakpoint Data Low Byte Register (BKP1L) . . . . . . . . . . . . 245

Figure 14-1 BDM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Figure 14-2 BDM Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . 249

Figure 14-3 BDM Status Register (BDMSTS). . . . . . . . . . . . . . . . . . . . . . 250

Figure 14-4 BDM CCR Holding Register (BDMCCR) . . . . . . . . . . . . . . . . 252

Figure 14-5 BDM Internal Register Position (BDMINR) . . . . . . . . . . . . . . 253

Figure 14-11 BDM Instruction Register (BDMIST) . . . . . . . . . . . . . . . . . . . 264

Figure 14-12 BDM Instruction Register (BDMIST) . . . . . . . . . . . . . . . . . . . 265

Figure 14-13 BDM Shift Register (BDMSHTH) . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-14 BDM Shift Register (BDMSHTL) . . . . . . . . . . . . . . . . . . . . . . 267

Figure 14-15 BDM Address Register (BDMADDH). . . . . . . . . . . . . . . . . . . 268

Figure 14-16 BDM Address Register (BDMADDL) . . . . . . . . . . . . . . . . . . . 268

Figure 15-1 Security Implementation Block Diagram . . . . . . . . . . . . . . . . 280

Figure B-1 Block Diagram of a Fuzzy Logic System . . . . . . . . . . . . . . . . 504

Figure B-2 Fuzzification Using Membership Functions . . . . . . . . . . . . . . 506

Figure B-3 Fuzzy Inference Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

Figure B-4 Defining a Normal Membership Function . . . . . . . . . . . . . . . 511

Figure B-5 MEM Instruction Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . 512

Figure B-6 Abnormal Membership Function Case 1 . . . . . . . . . . . . . . . . 513

Figure B-7 Abnormal Membership Function Case 2 . . . . . . . . . . . . . . . . 514

Figure B-8 Abnormal Membership Function Case 3 . . . . . . . . . . . . . . . . 514

Figure B-9 REV Instruction Flow Diagram. . . . . . . . . . . . . . . . . . . . . . . . 517

Figure B-10 REVW Instruction Flow Diagram . . . . . . . . . . . . . . . . . . . . . . 522

Figure B-11 WAV and wavr Instruction Flow Diagram . . . . . . . . . . . . . . . 526

Figure B-12 Endpoint Table Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

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List of Tables

Table 1-1 Addressing Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 1-2 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 1-3 Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 1-4 Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 1-5 Operation Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 1-6 Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 1-7 Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 1-8 Access Detail Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 1-9 Condition Code State Notation . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 2-1 Symbols and Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 3-1 Core Register Map Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 4-1 Addressing Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 4-2 Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 4-3 Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 4-4 Transfer and Exchange Instructions . . . . . . . . . . . . . . . . . . . . . 74

Table 4-5 Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 4-6 Add and Subtract Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 4-7 BCD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 4-8 Decrement and Increment Instructions . . . . . . . . . . . . . . . . . . . 76

Table 4-9 Compare and Test Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 4-10 Boolean Logic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 4-11 Clear, Complement, and Negate Instructions . . . . . . . . . . . . . . 78

Table 4-12 Multiplication and Division Instructions . . . . . . . . . . . . . . . . . . . 79

Table 4-13 Bit Test and Bit Manipulation Instructions . . . . . . . . . . . . . . . . . 79

Table 4-14 Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 4-15 Fuzzy Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 4-16 Minimum and Maximum Instructions . . . . . . . . . . . . . . . . . . . . . 82

Table 4-17 Multiply and Accumulate Instruction . . . . . . . . . . . . . . . . . . . . . 83

Table 4-18 Table Interpolation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table 4-19 Short Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 4-20 Long Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 4-21 Bit Condition Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . 85

Table 4-22 Loop Primitive Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

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Table 4-23 Jump and Subroutine Instructions . . . . . . . . . . . . . . . . . . . . . . . 87

Table 4-24 Interrupt Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 4-25 Index Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 88

Table 4-26 Stacking Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 4-27 Load Effective Address Instructions. . . . . . . . . . . . . . . . . . . . . . 90

Table 4-28 Condition Code Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 4-29 STOP and WAI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 4-30 Background Mode and Null Operation Instructions . . . . . . . . . . 91

Table 5-1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 5-2 Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 5-3 Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 5-4 Operation Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 5-5 Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 5-6 Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 5-7 Access Detail Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 5-8 Condition Code State Notation . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 5-9 IPIPE[1:0] Decoding when E Clock is High . . . . . . . . . . . . . . . 127

Table 5-10 IPIPE[1:0] Decoding when E Clock is Low . . . . . . . . . . . . . . . 128

Table 6-1 Exception Vector Map and Priority. . . . . . . . . . . . . . . . . . . . . . 135

Table 6-2 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Table 6-3 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 7-1 Core Interface Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . 142

Table 7-2 Multiplexed Expansion Bus Timing - Preliminary Targets . . . . 160

Table 7-3 Expansion Bus Timing - Preliminary Targets. . . . . . . . . . . . . . 161

Table 7-4 Access Type vs. Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . 162

Table 8-1 Core Clock and Reset Interface Signals . . . . . . . . . . . . . . . . . 166

Table 10-1 Exception Vector Map and Priority. . . . . . . . . . . . . . . . . . . . . . 176

Table 11-1 External Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . 184

Table 11-2 Allocated EEPROM Memory Space . . . . . . . . . . . . . . . . . . . . 186

Table 11-3 Allocated RAM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 186

Table 11-4 Allocated Flash EEPROM/ROM Physical Memory Space. . . . 187

Table 11-5 Allocated Off-Chip Memory Options . . . . . . . . . . . . . . . . . . . . 188

Table 11-6 Program Page Index Register Bits. . . . . . . . . . . . . . . . . . . . . . 189

Table 11-7 Select Signal Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Table 11-8 Allocated Off-Chip Memory Options . . . . . . . . . . . . . . . . . . . . 191

Table 11-9 External/Internal Page Window Access . . . . . . . . . . . . . . . . . . 191

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Table 11-100K Byte Physical Flash/ROM Allocated . . . . . . . . . . . . . . . . . . 193

Table 11-1116K Byte Physical Flash/ROM Allocated . . . . . . . . . . . . . . . . . 193

Table 11-1248K Byte Physical Flash/ROM Allocated . . . . . . . . . . . . . . . . . 193

Table 11-1364K Byte Physical Flash/ROM Allocated . . . . . . . . . . . . . . . . . 194

Table 11-14Wide Bus Enable Signal Generation . . . . . . . . . . . . . . . . . . . . 198

Table 11-15Read Data Bus Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Table 12-1 MEBI Interface Signal Definitions . . . . . . . . . . . . . . . . . . . . . . 203

Table 12-2 MODC, MODB, MODA Write Capability . . . . . . . . . . . . . . . . . 216

Table 12-3 Mode Select and State of Mode Bits . . . . . . . . . . . . . . . . . . . . 216

Table 12-4 External System Pins Associated With MEBI . . . . . . . . . . . . . 225

Table 12-5 Access Type vs. Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . 227

Table 12-6 Mode Pin Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . 227

Table 12-7 Peripheral Mode Pin Configuration . . . . . . . . . . . . . . . . . . . . . 232

Table 13-1 Breakpoint Mask Bits for First Address . . . . . . . . . . . . . . . . . . 240

Table 13-2 Breakpoint Mask Bits for Second Address (Dual Mode) . . . . . 241

Table 13-3 Breakpoint Mask Bits for Data Breakpoints (Full Mode) . . . . . 241

Table 14-1 Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Table 14-2 Firmware Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 14-3 Tag Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Table 14-4 TTAGO Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Table 14-5 RNEXT Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

Table 15-1 Security Interface Signal Definitions . . . . . . . . . . . . . . . . . . . . 280

Table A-1 Condition Code State Notation . . . . . . . . . . . . . . . . . . . . . . . . 285

Table A-2 Register and Memory Notation . . . . . . . . . . . . . . . . . . . . . . . . 286

Table A-3 Address Mode Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table A-4 Operator Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Table A-5 Machine Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Table A-6 Source Form Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

Table A-7 CPU Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

Table C-1 Translated M68HC11 Mnemonics . . . . . . . . . . . . . . . . . . . . . . 531

Table C-2 Instructions with Smaller Object Code . . . . . . . . . . . . . . . . . . . 532

Table C-3 Comparison of Math Instruction Speeds . . . . . . . . . . . . . . . . . 539

Table C-4 New HCS12 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

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Section 1 Introduction

1.1 Core Overview

The HCS12 V1.5 Core is a 16-bit processing core using the 68HC12 instruction set architecture (ISA).

This makes the Core instruction set compatible with currently available Motorola 68HC12 based designs and allows for Motorola 68HC11 source code to be directly accepted by assemblers used for the HCS12

Central Processing Unit (CPU). In addition, the Core contains the Interrupt (INT), Module Mapping

Control (MMC), Multiplexed External Bus Interface (MEBI), Breakpoint (BKP) and Background Debug

Mode (BDM) sub-blocks providing a tightly coupled structure to maximize execution efficiency for integrating into a System-on-a-Chip (SoC) design. These sub-blocks handle all system interfacing with the

Core including interrupt and reset processing, register and memory mapping, memory and peripheral interfacing, external bus control and source code debug for code development. A complete functional description of each sub-block is included in later sections of this guide.

1.2 Features

The main features of the Core are:

• High-speed, 16-bit processing with the same programming model and instruction set as the

Motorola 68HC12 CPU

• Full 16-bit data paths for efficient arithmetic operation and high-speed mathematical execution

• Allows instructions with odd byte counts, including many single-byte instructions for more efficient use of program memory space

• Three stage instruction queue to buffer program information for more efficient CPU execution

• Extensive set of indexed addressing capabilities including:

– Using the stack pointer as an indexing register in all indexed operations

– Using the program counter as an indexing register in all but auto increment/decrement mode

– Accumulator offsets using A, B or D accumulators

– Automatic index pre-decrement, pre-increment, post-decrement and post-increment (by -8 to

+8)

– 5-bit, 9-bit or 16-bit signed constant offsets

– 16-bit offset indexed-indirect and accumulator D offset indexed-indirect addressing

• Provides 2 to 122 I bit maskable interrupt vectors, 1 X bit maskable interrupt vector, 2 nonmaskable

CPU interrupt vectors and 3 reset vectors

• Optional register configurable highest priority I bit maskable interrupt

• On-chip memory and peripheral block interfacing with internal memory expansion capability and external data chip select

• Configurable system memory and mapping options

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• External Bus Interface (8-bit or 16-bit, multiplexed or non-multiplexed)

• Multiple modes of operation

• Hardware breakpoint support for forced or tagged breakpoints with two modes of operation:

– Dual Address Mode to match on either of two addresses

– Full Breakpoint Mode to match on address and data combination

• Single-wire background debug system implemented in on-chip hardware

• Secured mode of operation

• Fully synthesizable design

• Single Core clock operation

• Full Mux-D scan test implementation

The HCS12 V1.5 Core is designed to interface with the system peripherals through the use of the I.P. Bus and its interface defined by the Motorola Semiconductor Reuse Standards (MSRS). The Core communicates with the on-chip memory blocks either directly through the Core interface signals or via the

STAR bus. Interfacing with memories external to the system is provided for through the MEBI sub-block of the Core and the corresponding port/pad logic it is connected to within the system.

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1.3 Block Diagram

A block diagram of the Core within a typical SoC system is given in

Figure 1-1

below. This diagram is a general representation of the Core, its sub-blocks and the interfaces to the rest of the blocks within the

SoC design. The signals related to BKGD, Port A, Port B, Port E and Port K are direct interfaces to port/pad logic at the top level of the overall system.

STAR Bus

Resets

Clocks

RAM

CPU

Central

Processing

Unit

MMC

Module

Mapping

Control EEPROM

BDM

BKGD

Pin

BDM

Background

Debug

Mode

MEBI

INT

Interrupt

BKP

Breakpoint

Multiplexed External Bus Interface

Port A

(8-bit)

Port B

(8-bit)

Port E

(8-bit)

Port K

(8-bit)

Flash

EEPROM

Figure 1-1 Core Block Diagram

SCI

SPI

. . .

. . .

Timer

I.P.Bus

The main sub-blocks of the Core are:

• Central Processing Unit (CPU) - 68HC12 ISA compatible

• Interrupt (INT)

• Module Mapping Control (MMC)

• Multiplexed External Bus Interface (MEBI)

• Breakpoint (BKP)

• Background Debug Mode (BDM)

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1.4 Architectural Summary

As briefly discussed previously, the Core consists of the HCS12 Central Processing Unit (CPU) along with the Interrupt (INT), Module Mapping Control (MMC), Multiplexed External Bus Interface (MEBI),

Breakpoint (BKP) and Background Debug Mode (BDM) sub-blocks. The CPU executes the 68HC12 CPU

ISA with a three-stage instruction queue to facilitate a high level of code execution efficiency. The INT sub-block interacts with the CPU to provide 2 to 122 I bit maskable (configured at system integration), 1

X bit maskable and 2 nonmaskable CPU interrupt vectors, 3 reset vectors and handles waking-up the system from wait or stop mode due to a serviceable interrupt. The MMC sub-block controls address space mapping and generates memory selects and a single peripheral select (to be decoded by the I.P. Bus) as well as multiplexing the address and data signals for proper interaction with the CPU. The MEBI sub-block functions as the external bus controller with four 8-bit ports (A, B, E and K) as well as handling mode decoding and initialization for the Core. The BKP sub-block serves to assist in debugging of software by providing for hardware breakpoints. The BKP supports dual address and full breakpoint modes for matching on either of two address or on an address and data combination, respectively, to initiate a Software Interrupt (SWI) or put the system into Background Debug Mode. The BKP also supports tagged or forced breakpoints for breaking just before a specific instruction or on the first instruction boundary after a match, respectively. The BDM sub-block provides for a single-wire background debug communication system implemented within the Core with on-chip hardware. The BDM allows for single-wire serial interfacing with a development system host.

The Core is a fully synthesizable single-clock design with full Mux-D scan test implementation. It is designed to be synthesized and timed together as a single block for optimizing speed of execution and minimizing area.

1.5 Programming Model

The HCS12 V1.5 Core CPU12 programming model, shown in

Figure 1-2

, is the same as that of the

68HC12 and 68HC11. For a detailed description of the programming model and associated registers please refer to

Section 3

of this guide.

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15

15

7

15

15

15

A

0

D

7

X

Y

SP

PC

B

0

0

8-BIT ACCUMULATORS A AND B

16-BIT DOUBLE ACCUMULATOR D (A : B)

0 INDEX REGISTER X

0 INDEX REGISTER Y

0 STACK POINTER

0 PROGRAM COUNTER

S X H I N Z V C

CONDITION CODE REGISTER

CARRY

OVERFLOW

ZERO

NEGATIVE

IRQ INTERRUPT MASK (DISABLE)

HALF-CARRY FOR BCD ARITHMETIC

XIRQ INTERRUPT MASK (DISABLE)

STOP DISABLE (IGNORE STOP INSTRUCTION)

Figure 1-2 Programming Model

1.6 Data Format Summary

Following is a discussion of the data types used and their organization in memory for the Core.

1.6.1 Data Types

The CPU uses the following types of data:

• Bits

• 5-bit signed integers

• 8-bit signed and unsigned integers

• 8-bit, 2-digit binary coded decimal numbers

• 9-bit signed integers

• 16-bit signed and unsigned integers

• 16-bit effective addresses

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• 32-bit signed and unsigned integers

NOTE:

Negative integers are represented in two’s complement form.

Five-bit and 9-bit signed integers are used only as offsets for indexed addressing modes. Sixteen-bit effective addresses are formed during addressing mode computations. Thirty-two-bit integer dividends are used by extended division instructions. Extended multiply and extended multiply-and-accumulate instructions produce 32-bit products.

1.6.2 Memory Organization

The standard HCS12 Core address space is 64K bytes. However, the CPU has special instructions to support paged memory expansion which increases the standard area by means of predefined windows

within the available address space. See Section 11 Module Mapping Control (MMC) for more

information.

Eight-bit values can be stored at any odd or even byte address in available memory. Sixteen-bit values occupy two consecutive memory locations; the high byte is in the lowest address, but does not have to be aligned to an even boundary. Thirty-two-bit values occupy four consecutive memory locations; the high byte is in the lowest address, but does not have to be aligned to an even boundary.

All I/O and all on-chip peripherals are memory-mapped. No special instruction syntax is required to access these addresses. On-chip register and memory mapping are determined at the SoC level and are configured during integration of the Core into the system.

1.7 Addressing modes

A summary of the addressing modes used by the Core is given in

Table 1-1

below. The operation of each of these modes is discussed in detail in

Section 4

of this guide.

Table 1-1 Addressing Mode Summary

Addressing Mode

Inherent

Immediate

Source Form

INST

(no externally supplied operands)

INST #opr8i or

INST #opr16i

Abbreviation

INH

IMM

Description

Operands (if any) are in CPU registers.

Operand is included in instruction stream; 8-bit or

16-bit size implied by context.

Direct

Extended

INST opr8a DIR

EXT

Operand is the lower 8-bits of an address in the range

$0000–$00FF.

Operand is a 16-bit address.

Relative

INST opr16a

INST rel8 or

INST rel16

REL

Effective address is the value in PC plus an 8-bit or

16-bit relative offset value.

Indexed

(5-bit offset)

Indexed

(predecrement)

INST oprx5,xysp

INST oprx3,–xys

IDX

IDX

Effective address is the value in X, Y, SP, or PC plus a

5-bit signed constant offset.

Effective address is the value in X, Y, or SP autodecremented by 1 to 8.

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Addressing Mode

Indexed

(preincrement)

Indexed

(postdecrement)

Indexed

(postincrement)

Indexed

(accumulator offset)

Indexed

(9-bit offset)

Indexed

(16-bit offset)

Indexed-indirect

(16-bit offset)

Indexed-indirect

(D accumulator offset)

Table 1-1 Addressing Mode Summary

Source Form

INST oprx3,+xys

INST oprx3,xys–

INST oprx3,xys+

INST abd,xysp

INST oprx9,xysp

INST oprx16,xysp

INST [oprx16,xysp]

INST [D,xysp]

Abbreviation

IDX

IDX

IDX

IDX

IDX1

IDX2

[IDX2]

[D,IDX]

Description

Effective address is the value in X, Y, or SP autoincremented by 1 to 8.

Effective address is the value in X, Y, or SP. The value is postdecremented by 1 to 8.

Effective address is the value in X, Y, or SP. The value is postincremented by 1 to 8.

Effective address is the value in X, Y, SP, or PC plus the value in A, B, or D.

Effective address is the value in X, Y, SP, or PC plus a

9-bit signed constant offset.

Effective address is the value in X, Y, SP, or PC plus a

16-bit constant offset.

The value in X, Y, SP, or PC plus a 16-bit constant offset points to the effective address.

The value in X, Y, SP, or PC plus the value in D points to the effective address.

1.8 Instruction Set Overview

All memory and I/O are mapped in a common 64K byte address space, allowing the same set of instructions to access memory, I/O, and control registers. Load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory and peripherals.

There are instructions for signed and unsigned addition, division and multiplication with 8-bit, 16-bit, and some larger operands.

Special arithmetic and logic instructions aid stacking operations, indexing, BCD calculation, and condition code register manipulation. There are also dedicated instructions for multiply and accumulate operations, table interpolation, and specialized mathematical calculations for fuzzy logic operations.

A summary of the CPU instruction set is given in

Table 1-2

below. A detailed overview of the entire instruction set is covered in

Section 4

of this guide along with an instruction-by-instruction detailed description in

Appendix A

.

Source Form

ABA

ABXSame as LEAX B,X

ABYSame as LEAY B,Y

ADCA # opr8i

ADCA opr8a

ADCA opr16a

ADCA oprx0_xysppc

ADCA oprx9,xysppc

ADCA oprx16,xysppc

ADCA [D, xysppc]

ADCA [ oprx16,xysppc]

Table 1-2 Instruction Set Summary

Operation

Add B to A; (A)+(B)

A

Add B to X; (X)+(B)

X

Add B to Y; (Y)+(B)

Y

Add with carry to A; (A)+(M)+C

A or (A)+imm+C

A

Address

Mode

INH

Machine

Coding (Hex)

18 06

IDX

IDX

1A E5

19 ED

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

89 ii

99 dd

B9 hh ll

A9 xb

A9 xb ff

A9 xb ee ff

A9 xb

A9 xb ee ff

OO

Pf

Access Detail

Pf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– –

∆ ∆ ∆ ∆

– – – – – – – –

– – – – – – – –

– –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

ADCB # opr8i

ADCB opr8a

ADCB opr16a

ADCB oprx0_xysppc

ADCB oprx9,xysppc

ADCB oprx16,xysppc

ADCB [D, xysppc]

ADCB [ oprx16,xysppc]

ADDA # opr8i

ADDA opr8a

ADDA opr16a

ADDA oprx0_xysppc

ADDA oprx9,xysppc

ADDA oprx16,xysppc

ADDA [D, xysppc]

ADDA [ oprx16,xysppc]

ADDB # opr8i

ADDB opr8a

ADDB opr16a

ADDB oprx0_xysppc

ADDB oprx9,xysppc

ADDB oprx16,xysppc

ADDB [D, xysppc]

ADDB [ oprx16,xysppc]

ADDD # opr16i

ADDD opr8a

ADDD opr16a

ADDD oprx0_xysppc

ADDD oprx9,xysppc

ADDD oprx16,xysppc

ADDD [D, xysppc]

ADDD [ oprx16,xysppc]

ANDA # opr8i

ANDA opr8a

ANDA opr16a

ANDA oprx0_xysppc

ANDA oprx9,xysppc

ANDA oprx16,xysppc

ANDA [D, xysppc]

ANDA [ oprx16,xysppc]

ANDB # opr8i

ANDB opr8a

ANDB opr16a

ANDB oprx0_xysppc

ANDB oprx9,xysppc

ANDB oprx16,xysppc

ANDB [D, xysppc]

ANDB [ oprx16,xysppc]

ANDCC # opr8i

ASL opr16aSame as LSL

ASL oprx0_xysp

ASL oprx9,xysppc

ASL oprx16,xysppc

ASL [D, xysppc]

ASL [ oprx16,xysppc]

ASLASame as LSLA

ASLBSame as LSLB

ASLDSame as LSLD

Operation

Add with carry to B; (B)+(M)+C

B or (B)+imm+C

B

Add to A; (A)+(M) or (A)+imm

Add to B; (B)+(M) or (B)+imm or (B)

• imm

B

Add to D; (A:B)+(M:M+1) or (A:B)+imm

AND with A; (A) or (A)

• imm

A

A

AND with B; (B)

B

A:B

(M)

(M)

A

B

A

B

AND with CCR; (CCR)

• imm

CCR

Arithmetic shift left M

C b7 b0

0

A:B

Arithmetic shift left A

Arithmetic shift left B

Arithmetic shift left D

C b7

• • •

A b0 b7

• • •

B b0

0

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Coding (Hex)

C9 ii

D9 dd

F9 hh ll

E9 xb

E9 xb ff

E9 xb ee ff

E9 xb

E9 xb ee ff

C3 jj kk

D3 dd

F3 hh ll

E3 xb

E3 xb ff

E3 xb ee ff

E3 xb

E3 xb ee ff

84 ii

94 dd

B4 hh ll

A4 xb

A4 xb ff

A4 xb ee ff

A4 xb

A4 xb ee ff

8B ii

9B dd

BB hh ll

AB xb

AB xb ff

AB xb ee ff

AB xb

AB xb ee ff

CB ii

DB dd

FB hh ll

EB xb

EB xb ff

EB xb ee ff

EB xb

EB xb ee ff

C4 ii

D4 dd

F4 hh ll

E4 xb

E4 xb ff

E4 xb ee ff

E4 xb

E4 xb ee ff

10 ii

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

48

58

59

Access Detail

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

S X H I N Z V C

– –

∆ ∆ ∆ ∆

– –

∆ ∆ ∆ ∆

– –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

ASR opr16a

ASR oprx0_xysppc

ASR oprx9,xysppc

ASR oprx16,xysppc

ASR [D, xysppc]

ASR [ oprx16,xysppc]

ASRA

ASRB

BCC rel8Same as BHS

BCLR opr8a, msk8

BCLR opr16a, msk8

BCLR oprx0_xysppc, msk8

BCLR oprx9,xysppc, msk8

BCLR oprx16,xysppc, msk8

BCS rel8Same as BLO

BEQ rel8

BGE rel8

BGND

BGT rel8

BHI rel8

BHS rel8Same as BCC

BITA # opr8i

BITA opr8a

BITA opr16a

BITA oprx0_xysppc

BITA oprx9,xysppc

BITA oprx16,xysppc

BITA [D, xysppc]

BITA [ oprx16,xysppc]

BITB # opr8i

BITB opr8a

BITB opr16a

BITB oprx0_xysppc

BITB oprx9,xysppc

BITB oprx16,xysppc

BITB [D, xysppc]

BITB [ oprx16,xysppc]

BLE rel8

BLO rel8Same as BCS

BLS rel8

BLT rel8

BMI rel8

BNE rel8

BPL rel8

BRA rel8 b7

Operation

Arithmetic shift right M b0 C

Arithmetic shift right A

Arithmetic shift right B

Branch if C clear; if C=0, then

(PC)+2+rel

PC

REL

Clear bit(s) in M; (M)

• mask byte

M

DIR

EXT

IDX

IDX1

IDX2

REL Branch if C set; if C=1, then

(PC)+2+rel

PC

Branch if equal; if Z=1, then

(PC)+2+rel

PC

Branch if

0, signed; if N

V=0, then

(PC)+2+rel

PC

Enter background debug mode

Branch if

>

0, signed; if Z | (N

V)=0, then (PC)+2+rel

PC

Branch if higher, unsigned; if

C | Z=0, then (PC)+2+rel

PC

Branchifhigherorsame,unsigned;if

C=0,then(PC)+2+rel

PC

Bit test A; (A)

(M) or (A)

• imm

REL

REL

INH

REL

REL

REL

Bit test B; (B) or (B)

• imm

(M)

Branch if

0,signed; if Z | (N

V)=1, then (PC)+2+rel

PC

Branch if lower, unsigned; if C=1, then (PC)+2+rel

PC

Branch if lower or same, unsigned; if

C | Z=1, then (PC)+2+rel

PC

Branch if

<

0, signed; if N

V=1, then

(PC)+2+rel

PC

Branch if minus; if N=1, then

(PC)+2+rel

PC

Branch if not equal to 0; if Z=0, then

(PC)+2+rel

PC

Branch if plus; if N=0, then

(PC)+2+rel

PC

Branch always

REL

REL

REL

REL

REL

REL

REL

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

REL

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

Machine

Coding (Hex)

77 hh ll

67 xb

67 xb ff

67 xb ee ff

67 xb

67 xb ee ff

47

57

24 rr

4D dd mm

1D hh ll mm

0D xb mm

0D xb ff mm

0D xb ee ff mm

25 rr

27 rr

2C rr

00

2E rr

22 rr

24 rr

85 ii

95 dd

B5 hh ll

A5 xb

A5 xb ff

A5 xb ee ff

A5 xb

A5 xb ee ff

C5 ii

D5 dd

F5 hh ll

E5 xb

E5 xb ff

E5 xb ee ff

E5 xb

E5 xb ee ff

2F rr

25 rr

23 rr

2D rr

2B rr

26 rr

2A rr

20 rr

Access Detail

rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

PPP

(branch)

P

(no branch) rPwO rPwP rPwO rPwP frPwPO

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

VfPPP

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

For More Information On This Product,

Go to: www.freescale.com

CALL opr16a, page

CALL oprx0_xysppc, page

CALL oprx9,xysppc, page

CALL oprx16,xysppc, page

CALL [D, xysppc]

CALL [ oprx16, xysppc]

CBA

CLCSame as ANDCC #$FE

CLISame as ANDCC #$EF

CLR opr16a

CLR oprx0_xysppc

CLR oprx9,xysppc

CLR oprx16,xysppc

CLR [D, xysppc]

CLR [ oprx16,xysppc]

CLRA

CLRB

CLVSame as ANDCC #$FD

CMPA # opr8i

CMPA opr8a

CMPA opr16a

CMPA oprx0_xysppc

CMPA oprx9,xysppc

CMPA oprx16,xysppc

CMPA [D, xysppc]

CMPA [ oprx16,xysppc]

CMPB # opr8i

CMPB opr8a

CMPB opr16a

CMPB oprx0_xysppc

CMPB oprx9,xysppc

CMPB oprx16,xysppc

CMPB [D, xysppc]

CMPB [ oprx16,xysppc]

Source Form

BRCLR opr8a, msk8, rel8

BRCLR opr16a, msk8, rel8

BRCLR oprx0_xysppc, msk8, rel8

BRCLR oprx9,xysppc, msk8, rel8

BRCLR oprx16,xysppc, msk8, rel8

BRN rel8

BRSET opr8, msk8, rel8

BRSET opr16a, msk8, rel8

BRSET oprx0_xysppc, msk8, rel8

BRSET oprx9,xysppc, msk8, rel8

BRSET oprx16,xysppc, msk8, rel8

BSET opr8, msk8

BSET opr16a, msk8

BSET oprx0_xysppc, msk8

BSET oprx9,xysppc, msk8

BSET oprx16,xysppc, msk8

BSR rel8

BVC

BVS rel8 rel8

Set bit(s) in M

Operation

Branch if bit(s) clear; if

(M)

(mask byte)=0, then

(PC)+2+rel

PC

Branch never

Branch if bit(s) set; if

(M)

(mask byte)=0, then

(PC)+2+rel

PC

(M) | mask byte

M

Branch to subroutine; (SP)–2

SP

RTN

H

:RTN

L

M

(PC)+2+rel

PC

SP

:M

SP+1

Branch if V clear; if V=0, then

(PC)+2+rel

PC

Branch if V set; if V=1, then

(PC)+2+rel

PC

Call subroutine in expanded memory

(SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

SP+1

(SP)–1

SP; (PPG)

M

SP pg

PPAGE register subroutine address

PC

Compare A to B; (A)–(B)

Clear C bit

Clear I bit

Clear M; $00

M

Clear A; $00

Clear B; $00

Clear V

Compare A

A

B

(A)–(M) or (A)–imm

Compare B

(B)–(M) or (B)–imm

REL

REL

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

IMM

IMM

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IMM

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

DIR

EXT

IDX

IDX1

IDX2

REL

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

Machine

Coding (Hex)

Access Detail

4F dd mm rr

1F hh ll mm rr

0F xb mm rr

0F xb ff mm rr

0F xb ee ff mm rr rPPP rfPPP rPPP rfPPP

PrfPPP

REL

21 rr P

4E dd mm rr

1E hh ll mm rr

0E xb mm rr

0E xb ff mm rr

0E xb ee ff mm rr

4C dd mm

1C hh ll mm

0C xb mm

0C xb ff mm

0C xb ee ff mm

07 rr rPPP rfPPP rPPP rfPPP

PrfPPP rPwO rPwP rPwO rPwP frPwPO

SPPP

28 rr

29 rr

4A hh ll pg

4B xb pg

4B xb ff pg

4B xb ee ff pg

4B xb

4B xb ee ff

18 17

10 FE

10 EF

79 hh ll

69 xb

69 xb ff

69 xb ee ff

69 xb

69 xb ee ff

87

C7

10 FD

81 ii

91 dd

B1 hh ll

A1 xb

A1 xb ff

A1 xb ee ff

A1 xb

A1 xb ee ff

C1 ii

D1 dd

F1 hh ll

E1 xb

E1 xb ff

E1 xb ee ff

E1 xb

E1 xb ee ff

P

P

PwO

Pw

PwO

PwP

PIfw

PIPw

O

O

P

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch) gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP

OO

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – – – – – 0

– – – 0 – – – –

– – – – 0 1 0 0

– – – – – – 0 –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

COM opr16a

COM oprx0_xysppc

COM oprx9,xysppc

COM oprx16,xysppc

COM [D, xysppc]

COM [ oprx16,xysppc]

COMA

COMB

CPD # opr16i

CPD opr8a

CPD opr16a

CPD oprx0_xysppc

CPD oprx9,xysppc

CPD oprx16,xysppc

CPD [D, xysppc]

CPD [ oprx16,xysppc]

CPS # opr16i

CPS opr8a

CPS opr16a

CPS oprx0_xysppc

CPS oprx9,xysppc

CPS oprx16,xysppc

CPS [D, xysppc]

CPS [ oprx16,xysppc]

CPX # opr16i

CPX opr8a

CPX opr16a

CPX oprx0_xysppc

CPX oprx9,xysppc

CPX oprx16,xysppc

CPX [D, xysppc]

CPX [ oprx16,xysppc]

CPY # opr16i

CPY opr8a

CPY opr16a

CPY oprx0_xysppc

CPY oprx9,xysppc

CPY oprx16,xysppc

CPY [D, xysppc]

CPY [ oprx16,xysppc]

DAA

DBEQ abdxysp, rel9

DBNE abdxysp, rel9

DEC opr16a

DEC oprx0_xysppc

DEC oprx9,xysppc

DEC oprx16,xysppc

DEC [D, xysppc]

DEC [ oprx16,xysppc]

DECA

DECB

DESSame as LEAS –1,SP

DEX

DEY

EDIV

Compare D or (A:B)–imm

Compare SP or (SP)–imm

Compare X

(X)–(M:M+1) or (X)–imm

Compare Y

(Y)–(M:M+1) or (Y)–imm

Operation

Complement M; (M)=$FF–(M)

Complement A; (A)=$FF–(A)

Complement B; (B)=$FF–(B)

(A:B)–(M:M+1)

(SP)–(M:M+1)

Decimal adjust A for BCD

A

B

M

Decrement and branch if equal to 0

(counter)–1

⇒ counter if (counter)=0, then branch

REL

(9-bit)

Decrement and branch if not equal to 0;

(counter)–1

⇒ counter; if (counter)

0, then branch

Decrement M; (M)–1

M

REL

(9-bit)

Decrement A; (A)–1

Decrement B; (B)–1

A

B

Decrement SP; (SP)–1

SP

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IDX

Decrement X; (X)–1

X

Decrement Y; (Y)–1

Y

INH

INH

Extended divide, unsigned; 32 by 16 to 16-bit; (Y:D)

÷

(X)

Y; remainder

D

INH

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

Machine

Coding (Hex)

71 hh ll

61 xb

61 xb ff

61 xb ee ff

61 xb

61 xb ee ff

41

51

8C jj kk

9C dd

BC hh ll

AC xb

AC xb ff

AC xb ee ff

AC xb

AC xb ee ff

8F jj kk

9F dd

BF hh ll

AF xb

AF xb ff

AF xb ee ff

AF xb

AF xb ee ff

8E jj kk

9E dd

BE hh ll

AE xb

AE xb ff

AE xb ee ff

AE xb

AE xb ee ff

8D jj kk

9D dd

BD hh ll

AD xb

AD xb ff

AD xb ee ff

AD xb

AD xb ee ff

18 07

04 lb rr

04 lb rr

73 hh ll

63 xb

63 xb ff

63 xb ee ff

63 xb

63 xb ee ff

43

53

1B 9F

09

03

11

PPP

(branch)

PPO

(no branch)

Access Detail

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

OfO

PPP

(branch)

PPO

(no branch)

O

O rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

Pf ffffffffffO

S X H I N Z V C

– – – –

∆ ∆

0 1

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

?

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆

– – – – – – – –

– – – – –

– –

– – – – –

– –

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

EDIVS

EMACS

EMAXD

EMAXD

EMAXD

EMIND [

Source Form

opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMAXD [D,

EMAXD [

EMAXM

EMAXM

EMAXM oprx16,xysppc] oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMAXM [D,

EMAXM [

EMIND

EMIND

EMIND

EMIND [D, xysppc] xysppc] oprx16,xysppc] oprx0_xysppc oprx9,xysppc oprx16,xysppc xysppc] oprx16,xysppc]

Operation

Address

Mode

Machine

Coding (Hex)

Extended divide,signed; 32 by 16 to

16-bit; (Y:D)

÷

(X)

Y remainder

D

Extended multiply and accumulate, signed; (M

X

:M

X+1

)

×

(M

Y

:M

Y+1

)

+

(M~M+3)

M~M+3; 16 by 16 to 32-bit

INH

Special

Extended maximum in D; put larger of

2 unsigned 16-bit values in D

MAX[(D), (M:M+1)]

D

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 14

18 12 hh ll

18 1A xb

18 1A xb ff

18 1A xb ee ff

18 1A xb

18 1A xb ee ff

Extended maximum in M; put larger of

2 unsigned 16-bit values in M

MAX[(D), (M:M+1)]

M:M+1

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Extended minimum in D; put smaller of

2 unsigned 16-bit values in D

MIN[(D), (M:M+1)]

D

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 1E xb

18 1E xb ff

18 1E xb ee ff

18 1E xb

18 1E xb ee ff

18 1B xb

18 1B xb ff

18 1B xb ee ff

18 1B xb

18 1B xb ee ff

Access Detail

OffffffffffO

ORROfffRRfWWP

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

EMINM

EMINM

EMINM oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMINM [D,

EMINM [

EMUL xysppc] oprx16,xysppc]

Extended minimum in M; put smaller of

2 unsigned 16-bit values in M

MIN[(D), (M:M+1)]

M:M+1

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Extended multiply, unsigned

(D)

×

(Y)

Y:D; 16 by 16 to 32-bit

Extended multiply, signed

(D)

×

(Y)

Y:D; 16 by 16 to 32-bit

INH

INH

18 1F xb

18 1F xb ff

18 1F xb ee ff

18 1F xb

18 1F xb ee ff

13

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW ffO

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

EMULS

18 13 OfO

OffO

(if followed by page 2 instruction)

– – – –

∆ ∆

EORA # opr8i

EORA opr8a

EORA opr16a

EORA oprx0_xysppc

EORA oprx9,xysppc

EORA oprx16,xysppc

EORA [D, xysppc]

EORA [ oprx16,xysppc]

EORB #

EORB

EORB

EORB

EORB

EORB opr8i opr8a opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc

EORB [D,

EORB [ xysppc] oprx16,xysppc]

Exclusive OR A

(A)

(B)

(M) or (A) or (B)

(M)

A imm

B imm

A

Exclusive OR B

B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

88 ii

98 dd

B8 hh ll

A8 xb

A8 xb ff

A8 xb ee ff

A8 xb

A8 xb ee ff

C8 ii

D8 dd

F8 hh ll

E8 xb

E8 xb ff

E8 xb ee ff

E8 xb

E8 xb ee ff

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

ETBL oprx0_xysppc

Extended table lookup and interpolate,

16-bit; (M:M+1)+

[(B)

×

((M+2:M+3)–(M:M+1))]

D

IDX

18 3F xb ORRffffffP

– – – –

∆ ∆

Before executing ETBL, initialize B with fractional part of lookup value; initialize index register to point to first table entry (M:M+1). No extensions or indirect addressing allowed.

EXG abcdxysp,abcdxysp

FDIV

Exchange register contents

(r1)

(r2) r1 and r2 same size

$00:(r1)

⇒ r2r1=8-bit; r2=16-bit

(r1

L

)

(r2)r1=16-bit; r2=8-bit

Fractional divide; (D)

÷

(X)

X remainder

D; 16 by 16-bit

INH

INH

B7 eb

18 11

P

OffffffffffO

– – – – – – – –

– – – – –

∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

IBEQ abdxysp, rel9

IBNE abdxysp, rel9

IDIV

IDIVS

INC opr16a

INC oprx0_xysppc

INC oprx9,xysppc

INC oprx16,xysppc

INC [D, xysppc]

INC [ oprx16,xysppc]

INCA

INCB

INSSame as LEAS 1,SP

INX

INY

JMP opr16a

JMP oprx0_xysppc

JMP oprx9,xysppc

JMP oprx16,xysppc

JMP [D, xysppc]

JMP [ oprx16,xysppc]

JSR opr8a

JSR opr16a

JSR oprx0_xysppc

JSR oprx9,xysppc

JSR oprx16,xysppc

JSR [D, xysppc]

JSR [ oprx16,xysppc]

LBCC rel16Same as LBHS

LBCS rel16Same as LBLO

LBEQ rel16

LBGE rel16

LBGT rel16

LBHI rel16

LBHS rel16Same as LBCC

LBLE rel16

LBLO rel16Same as LBCS

LBLS rel16

LBLT rel16

Operation

Increment and branch if equal to 0

(counter)+1

⇒ counter

If (counter)=0, then branch

Increment and branch if not equal to 0

(counter)+1

⇒ counter

If (counter)

0, then branch

Integer divide, unsigned; (D)

÷

(X)

X

Remainder

D; 16 by 16-bit

Integer divide, signed; (D)

÷

(X)

X

Remainder

D; 16 by 16-bit

Increment M; (M)+1

M

Address

Mode

REL

(9-bit)

Machine

Coding (Hex)

04 lb rr

REL

(9-bit)

INH

INH

04 lb rr

18 10

18 15

Increment A; (A)+1

Increment B; (B)+1

A

B

Increment SP; (SP)+1

Increment X; (X)+1

X

Increment Y; (Y)+1

Y

SP

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IDX

INH

INH

72 hh ll

62 xb

62 xb ff

62 xb ee ff

62 xb

62 xb ee ff

42

52

1B 81

08

02

Jump

Subroutine address

Jump to subroutine

(SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

PC

SP+1

Subroutine address

PC

Long branch if C clear; if C=0, then

(PC)+4+rel

PC

Long branch if C set; if C=1, then

(PC)+4+rel

PC

Long branch if equal; if Z=1, then

(PC)+4+rel

PC

Long branch if

0, signed

If N

V=0, then (PC)+4+rel

PC

Long branch if

>

0, signed

If Z | (N

V)=0, then (PC)+4+rel

PC

Long branch if higher, unsigned

If C | Z=0, then (PC)+4+rel

PC

Long branch if higher or same, unsigned; If C=0, (PC)+4+rel

PC

Long branch if

0, signed; if

Z | (N

V)=1, then (PC)+4+rel

PC

Long branch if lower, unsigned; if

C=1, then (PC)+4+rel

PC

Long branch if lower or same, unsigned; If C | Z=1, then

(PC)+4+rel

PC

Long branch if

<

0, signed

If N

V=1, then (PC)+4+rel

PC

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

REL

REL

REL

REL

REL

REL

REL

REL

REL

REL

REL

06 hh ll

05 xb

05 xb ff

05 xb ee ff

05 xb

05 xb ee ff

17 dd

16 hh ll

15 xb

15 xb ff

15 xb ee ff

15 xb

15 xb ee ff

18 24 qq rr

18 25 qq rr

18 27 qq rr

18 2C qq rr

18 2E qq rr

18 22 qq rr

18 24 qq rr

18 2F qq rr

18 25 qq rr

18 23 qq rr

18 2D qq rr

Access Detail

PPP

(branch)

PPO

(no branch)

PPP

(branch)

PPO

(no branch)

OffffffffffO

OffffffffffO

OPPP

OPO

(branch)

(no branch)

O

O rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

Pf

PPP

PPP

PPP fPPP fIfPPP fIfPPP

SPPP

SPPP

PPPS

PPPS fPPPS fIfPPPS fIfPPPS

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – –

0

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆

– – – – – – – –

– – – – –

– –

– – – – –

– –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

For More Information On This Product,

Go to: www.freescale.com

LBMI rel16

Source Form

LBNE rel16

LBPL rel16

LBRA rel16

LBRN rel16

LBVC rel16

LBVS rel16

LDAA # opr8i

LDAA opr8a

LDAA opr16a

LDAA oprx0_xysppc

LDAA oprx9,xysppc

LDAA oprx16,xysppc

LDAA [D, xysppc]

LDAA [ oprx16,xysppc]

LDAB # opr8i

LDAB opr8a

LDAB opr16a

LDAB oprx0_xysppc

LDAB oprx9,xysppc

LDAB oprx16,xysppc

LDAB [D, xysppc]

LDAB [ oprx16,xysppc]

LDD # opr16i

LDD opr8a

LDD opr16a

LDD oprx0_xysppc

LDD oprx9,xysppc

LDD oprx16,xysppc

LDD [D, xysppc]

LDD [ oprx16,xysppc]

LDS # opr16i

LDS opr8a

LDS opr16a

LDS oprx0_xysppc

LDS oprx9,xysppc

LDS oprx16,xysppc

LDS [D, xysppc]

LDS [ oprx16,xysppc]

LDX # opr16i

LDX opr8a

LDX opr16a

LDX oprx0_xysppc

LDX oprx9,xysppc

LDX oprx16,xysppc

LDX [D, xysppc]

LDX [ oprx16,xysppc]

LDY # opr16i

LDY opr8a

LDY opr16a

LDY oprx0_xysppc

LDY oprx9,xysppc

LDY oprx16,xysppc

LDY [D, xysppc]

LDY [ oprx16,xysppc]

Operation

Long branch if minus

If N=1, then (PC)+4+rel

PC

Long branch if not equal to 0

If Z=0, then (PC)+4+rel

PC

Long branch if plus

If N=0, then (PC)+4+rel

PC

Long branch always

Long branch never

Long branch if V clear

If V=0,then (PC)+4+rel

PC

Long branch if V set

If V=1,then (PC)+4+rel

PC

Load A

(M)

A or imm

A

Load B

(M)

B or imm

B

Load D

(M:M+1)

A:B or imm

A:B

Load SP

(M:M+1)

SP or imm

SP

Load X

(M:M+1)

X or imm

X

Load Y

(M:M+1)

Y or imm

Y

CC jj kk

DC dd

FC hh ll

EC xb

EC xb ff

EC xb ee ff

EC xb

EC xb ee ff

CF jj kk

DF dd

FF hh ll

EF xb

EF xb ff

EF xb ee ff

EF xb

EF xb ee ff

86 ii

96 dd

B6 hh ll

A6 xb

A6 xb ff

A6 xb ee ff

A6 xb

A6 xb ee ff

C6 ii

D6 dd

F6 hh ll

E6 xb

E6 xb ff

E6 xb ee ff

E6 xb

E6 xb ee ff

CE jj kk

DE dd

FE hh ll

EE xb

EE xb ff

EE xb ee ff

EE xb

EE xb ee ff

CD jj kk

DD dd

FD hh ll

ED xb

ED xb ff

ED xb ee ff

ED xb

ED xb ee ff

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Address

Mode

REL

Machine

Coding (Hex)

18 2B qq rr

REL

REL

REL

REL

REL

REL

18 26 qq rr

18 2A qq rr

18 20 qq rr

18 21 qq rr

18 28 qq rr

18 29 qq rr

Access Detail

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

OPO

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

For More Information On This Product,

Go to: www.freescale.com

Source Form

LEAS oprx0_xysppc

LEAS oprx9,xysppc

LEAS oprx16,xysppc

LEAX oprx0_xysppc

LEAX oprx9,xysppc

LEAX oprx16,xysppc

LEAY oprx0_xysppc

LEAY oprx9,xysppc

LEAY oprx16,xysppc

LSL opr16aSame as ASL

LSL oprx0_xysppc

LSL oprx9,xysppc

LSL oprx16,xysppc

LSL [D, xysppc]

LSL [ oprx16,xysppc]

LSLASame as ASLA

LSLBSame as ASLB

LSLDSame as ASLD

LSR opr16a

LSR oprx0_xysppc

LSR oprx9,xysppc

LSR oprx16,xysppc

LSR [D, xysppc]

LSR [ oprx16,xysppc]

LSRA

LSRB

LSRD

MAXA oprx0_xysppc

MAXA oprx9,xysppc

MAXA oprx16,xysppc

MAXA [D, xysppc]

MAXA [ oprx16,xysppc]

MAXM oprx0_xysppc

MAXM oprx9,xysppc

MAXM oprx16,xysppc

MAXM [D, xysppc]

MAXM [ oprx16,xysppc]

MEM

MINA oprx0_xysppc

MINA oprx9,xysppc

MINA oprx16,xysppc

MINA [D, xysppc]

MINA [ oprx16,xysppc]

MINM oprx0_xysppc

MINM oprx9,xysppc

MINM oprx16,xysppc

MINM [D, xysppc]

MINM [ oprx16,xysppc]

Load effective address into SP

EA

EA

SP

Load effective address into X

X

Load effective address into Y

EA

Y

Operation

Logical shift left M

C b7 b0

0

Address

Mode

IDX

IDX1

IDX2

Machine

Coding (Hex)

1B xb

1B xb ff

1B xb ee ff

IDX

IDX1

IDX2

IDX

IDX1

IDX2

1A xb

1A xb ff

1A xb ee ff

19 xb

19 xb ff

19 xb ee ff

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

48

58

59

Logical shift left A

Logical shift left B

Logical shift left D

C b7

• • •

A b0 b7

• • •

B b0

0

Logical shift right M

0 b7 b0

Logical shift right A

Logical shift right B

Logical shift right D

0 b7 A b0 b7

C

B b0 C

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

74 hh ll

64 xb

64 xb ff

64 xb ee ff

64 xb

64 xb ee ff

44

54

49

Maximum in A; put larger of 2 unsigned 8-bit values in A

MAX[(A), (M)]

A

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 18 xb

18 18 xb ff

18 18 xb ee ff

18 18 xb

18 18 xb ee ff

Maximum in M; put larger of 2 unsigned 8-bit values in M

MAX[(A), (M)]

M

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Determine grade of membership;

µ

(grade)

M

Y

; (X)+4

X; (Y)+1

Y

If (A)<P1 or (A)>P2, then

µ

=0; else

µ

=

MIN[((A)–P1)

×

S1, (P2–(A))

×

S2, $FF]

(A)=current crisp input value; X points at 4 data bytes (P1, P2, S1, S2) of a trapezoidal membership function; Y points at fuzzy input (RAM location)

Special

01

18 1C xb

18 1C xb ff

18 1C xb ee ff

18 1C xb

18 1C xb ee ff

Minimum in A; put smaller of 2 unsigned 8-bit values in A

MIN[(A), (M)]

A

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

Minimum in N; put smaller of two unsigned 8-bit values in M

MIN[(A), (M)]

M

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 19 xb

18 19 xb ff

18 19 xb ee ff

18 19 xb

18 19 xb ee ff

18 1D xb

18 1D xb ff

18 1D xb ee ff

18 1D xb

18 1D xb ee ff rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

RRfOw

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

Access Detail

Pf

PO

PP

Pf

PO

PP

Pf

PO

PP rOPw rPw rPOw frPPw fIfrPw fIPrPw

O

O

O

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – – 0

∆ ∆ ∆

– – – – 0

∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – ? – ? ? ? ?

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

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Source Form Operation

MOVB # opr8, opr16a

MOVB # opr8i, oprx0_xysppc

MOVB opr16a, opr16a

MOVB opr16a, oprx0_xysppc

MOVB oprx0_xysppc, opr16a

MOVB oprx0_xysppc, oprx0_xysppc

Move byte

Memory-to-memory 8-bit byte-move

(M

1

)

M

2

First operand specifies byte to move

MOVW # oprx16, opr16a

MOVW # opr16i, oprx0_xysppc

MOVW opr16a, opr16a

MOVW opr16a, oprx0_xysppc

MOVW oprx0_xysppc, opr16a

MOVW oprx0_xysppc, oprx0_xysppc

Move word

Memory-to-memory 16-bit word-move

(M

1

:M

1

+1)

M

2

:M

2

+1

First operand specifies word to move

MUL Multiply, unsigned

(A)

×

(B)

A:B; 8 by 8-bit

Negate M; 0–(M)

M or (M)+1

M NEG opr16a

NEG oprx0_xysppc

NEG oprx9,xysppc

NEG oprx16,xysppc

NEG [D, xysppc]

NEG [ oprx16,xysppc]

NEGA

NEGB

NOP

Negate A; 0–(A)

Negate B; 0–(B)

No operation

A or (A)+1

B or (B)+1

A

B

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

Address

Mode

Machine

Coding (Hex)

Access Detail

IMM-EXT

IMM-IDX

EXT-EXT

EXT-IDX

IDX-EXT

IDX-IDX

18 0B ii hh ll

18 08 xb ii

18 0C hh ll hh ll

18 09 xb hh ll

18 0D xb hh ll

18 0A xb xb

OPwP

OPwO

OrPwPO

OPrPw

OrPwP

OrPwO

IMM-EXT

IMM-IDX

EXT-EXT

EXT-IDX

IDX-EXT

IDX-IDX

18 03 jj kk hh ll

18 00 xb jj kk

18 04 hh ll hh ll

18 01 xb hh ll

18 05 xb hh ll

18 02 xb xb

OPWPO

OPPW

ORPWPO

OPRPW

ORPWP

ORPWO

INH

12 O

70 hh ll

60 xb

60 xb ff

60 xb ee ff

60 xb

60 xb ee ff

40

50

A7 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

ORAA # opr8i

ORAA opr8a

ORAA opr16a

ORAA oprx0_xysppc

ORAA oprx9,xysppc

ORAA oprx16,xysppc

ORAA [D, xysppc]

ORAA [ oprx16,xysppc]

ORAB # opr8i

ORAB opr8a

ORAB opr16a

ORAB oprx0_xysppc

ORAB oprx9,xysppc

ORAB oprx16,xysppc

ORAB [D, xysppc]

ORAB [ oprx16,xysppc]

ORCC # opr8i

PSHA

PSHB

PSHC

PSHD

PSHX

PSHY

PULA

PULB

PULC

PULD

OR accumulator A

(A) | (M)

A or (A) | imm

A

OR accumulator B

(B) | (M)

B or (B) | imm

B

OR CCR; (CCR) | imm

CCR

Push A; (SP)–1

SP; (A)

M

SP

Push B; (SP)–1

SP; (B)

M

SP

Push CCR; (SP)–1

SP;

(CCR)

M

SP

Push D

(SP)–2

SP; (A:B)

M

SP

:M

SP+1

Push X

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

Push Y

(SP)–2

SP; (Y

H

:Y

L

)

M

SP

:M

SP+1

Pull A

(M

SP

)

A; (SP)+1

SP

Pull B

(M

SP

)

B; (SP)+1

SP

Pull CCR

(M

SP

)

CCR; (SP)+1

SP

Pull D

(M

SP

:M

SP+1

)

A:B; (SP)+2

SP

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

INH

INH

INH

INH

INH

INH

INH

INH

INH

INH

8A ii

9A dd

BA hh ll

AA xb

AA xb ff

AA xb ee ff

AA xb

AA xb ee ff

CA ii

DA dd

FA hh ll

EA xb

EA xb ff

EA xb ee ff

EA xb

EA xb ee ff

14 ii

36

37

39

3B

34

35

32

33

38

3A

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

Os

Os

Os

OS

OS

OS ufO ufO ufO

UfO

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

⇑ ⇑ ⇑ ⇑ ⇑ ⇑

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

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Source Form Operation

Address

Mode

INH

30

Machine

Coding (Hex)

Access Detail

PULX

PULY

REV

Pull X

(M

SP

:M

SP+1

)

X

H

:X

L

; (SP)+2

SP

Pull Y

(M

SP

:M

SP+1

)

Y

H

:Y

L

; (SP)+2

SP

Rule evaluation, unweighted; find smallest rule input; store to rule outputs unless fuzzy output is larger

INH

Special

31

18 3A

UfO

UfO

Orf(t^tx)O* ff+Orft^**

*The t^tx loop is executed once for each element in the rule list. The

^

denotes a check for pending interrupt requests.

**These are additional cycles caused by an interrupt: ff is the exit sequence and

Orft^

is the re-entry sequence.

REVW Special

18 3B

Rule evaluation, weighted; rule weights optional; find smallest rule input; store to rule outputs unless fuzzy output is larger

ORf(t^Tx)O* or

ORf(r^ffRf)O** ffff+ORft^*** ffff+ORfr^****

SBCA # opr8i

SBCA opr8a

SBCA opr16a

SBCA oprx0_xysppc

SBCA oprx9,xysppc

SBCA oprx16,xysppc

SBCA [D, xysppc]

SBCA [ oprx16,xysppc]

Subtract with carry from A

(A)–(M)–C

A or (A)–imm–C

A

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

82 ii

92 dd

B2 hh ll

A2 xb

A2 xb ff

A2 xb ee ff

A2 xb

A2 xb ee ff

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – ? – ? ?

?

– – ? – ? ?

!

*With weighting not enabled, the t^Tx loop is executed once for each element in the rule list. The

^

denotes a check for pending interrupt requests.

**With weighting enabled, the t^Tx

loop is replaced by r^ffRf

.

***Additional cycles caused by an interrupt when weighting is not enabled: ffff

is the exit sequence and

ORft^

is the re-entry sequence.

**** Additional cycles caused by an interrupt when weighting is enabled: ffff

is the exit sequence and

ORfr^

is the re-entry sequence.

Rotate left M

– – – –

∆ ∆ ∆ ∆

ROL opr16a

ROL oprx0_xysppc

ROL oprx9,xysppc

ROL oprx16,xysppc

ROL [D, xysppc]

ROL [ oprx16,xysppc]

ROLA

ROLB

C b7

Rotate left A

Rotate left B b0

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

75 hh ll

65 xb

65 xb ff

65 xb ee ff

65 xb

65 xb ee ff

45

55 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

ROR opr16a

ROR oprx0_xysppc

ROR oprx9,xysppc

ROR oprx16,xysppc

ROR [D, xysppc]

ROR [ oprx16,xysppc]

RORA

RORB

RTC

RTI

RTS

SBA

Rotate right M b0 b7

C

Rotate right A

Rotate right B

Return from call; (M

SP

)

PPAGE

(SP)+1

SP;

(M

SP

:M

SP+1

(SP)+2

SP

)

PC

H

:PC

L

Return from interrupt

(M

SP

)

CCR; (SP)+1

SP

(M

SP

:M

SP+1

(M

SP

:M

SP+1

(M

(M

SP

SP

:M

:M

SP+1

SP+1

)

B:A;(SP)+2

SP

)

X

)

PC

)

Y

H

H

:X

:Y

L

;(SP)+4

SP

H

:PC

L

;(SP)+2

SP

L

;(SP)+4

SP

*RTI takes 11 cycles if an interrupt is pending.

Return from subroutine

(M

SP

:M

SP+1

(SP)+2

SP

)

PC

H

:PC

L

;

Subtract B from A; (A)–(B)

A

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

INH

INH

INH

76 hh ll

66 xb

66 xb ff

66 xb ee ff

66 xb

66 xb ee ff

46

56

0A

0B

3D

18 16 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O uUnfPPP uUUUUPPP or uUUUUfVfPPP*

UfPPP

OO

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

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Source Form

SBCB # opr8i

SBCB opr8a

SBCB opr16a

SBCB oprx0_xysppc

SBCB oprx9,xysppc

SBCB oprx16,xysppc

SBCB [D, xysppc]

SBCB [ oprx16,xysppc]

SECSame as ORCC #$01

Operation

Subtract with carry from B

(B)–(M)–C

B or (B)–imm–C

B

SEISame as ORCC #$10

SEVSame as ORCC #$02

Set C bit

Set I bit

Set V bit

SEX abc,dxyspSame as TFR r1, r2 Sign extend; 8-bit r1 to 16-bit r2

$00:(r1)

⇒ r2 if bit 7 of r1 is 0

$FF:(r1)

⇒ r2 if bit 7 of r1 is 1

STAA opr8a

STAA opr16a

STAA oprx0_xysppc

STAA oprx9,xysppc

STAA oprx16,xysppc

STAA [D, xysppc]

STAA [ oprx16,xysppc]

Store accumulator A

(A)

M

Store accumulator B

(B)

M

STAB opr8a

STAB opr16a

STAB oprx0_xysppc

STAB oprx9,xysppc

STAB oprx16,xysppc

STAB [D, xysppc]

STAB [ oprx16,xysppc]

STD opr8a

STD opr16a

STD oprx0_xysppc

STD oprx9,xysppc

STD oprx16,xysppc

STD [D, xysppc]

STD [ oprx16,xysppc]

STOP

Store D

(A:B)

M:M+1

Stop processing; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

Stop all clocks

STS opr8a

STS opr16a

STS oprx0_xysppc

STS oprx9,xysppc

STS oprx16,xysppc

STS [D, xysppc]

STS [ oprx16,xysppc]

STX opr8a

STX opr16a

STX oprx0_xysppc

STX oprx9,xysppc

STX oprx16,xysppc

STX [D, xysppc]

STX [ oprx16,xysppc]

Store SP

(SP

H

:SP

L

)

M:M+1

Store X

(X

H

:X

L

)

M:M+1

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

IMM

IMM

INH

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

Machine

Coding (Hex)

C2 ii

D2 dd

F2 hh ll

E2 xb

E2 xb ff

E2 xb ee ff

E2 xb

E2 xb ee ff

14 01

14 10

14 02

B7 eb

5A dd

7A hh ll

6A xb

6A xb ff

6A xb ee ff

6A xb

6A xb ee ff

5B dd

7B hh ll

6B xb

6B xb ff

6B xb ee ff

6B xb

6B xb ee ff

5C dd

7C hh ll

6C xb

6C xb ff

6C xb ee ff

6C xb

6C xb ee ff

18 3E

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5F dd

7F hh ll

6F xb

6F xb ff

6F xb ee ff

6F xb

6F xb ee ff

5E dd

7E hh ll

6E xb

6E xb ff

6E xb ee ff

6E xb

6E xb ee ff

P

P

Access Detail

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

P

Pw

PwO

Pw

PwO

PwP

PIfw

PIPw

Pw

PwO

Pw

PwO

PwP

PIfw

PIPw

PW

PWO

PW

PWO

PWP

PIfW

PIPW

OOSSSSsf

(enter stop mode) fVfPPP

(exit stop mode) ff

(continue stop mode)

OO

(if stop mode disabled by S=1)

PW

PWO

PW

PWO

PWP

PIfW

PIPW

PW

PWO

PW

PWO

PWP

PIfW

PIPW

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – – – – – 1

– – – 1 – – – –

– – – – – – 1 –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

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SUBA #

SUBA

SUBA

SUBA

SUBA

SUBA

SUBA [D,

SUBA [

Source Form

STY opr8a

STY opr16a

STY oprx0_xysppc

STY oprx9,xysppc

STY oprx16,xysppc

STY [D, xysppc]

STY [ oprx16,xysppc] opr8i opr8a opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc xysppc] oprx16,xysppc]

SUBB # opr8i

SUBB opr8a

SUBB opr16a

SUBB oprx0_xysppc

SUBB oprx9,xysppc

SUBB oprx16,xysppc

SUBB [D, xysppc]

SUBB [ oprx16,xysppc]

Store Y

(Y

H

:Y

L

)

(A)–(M) or (A)–imm

Operation

Subtract from B

(B)–(M)

M:M+1

Subtract from A

A

B or (B)–imm

A

B

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Coding (Hex)

5D dd

7D hh ll

6D xb

6D xb ff

6D xb ee ff

6D xb

6D xb ee ff

80 ii

90 dd

B0 hh ll

A0 xb

A0 xb ff

A0 xb ee ff

A0 xb

A0 xb ee ff

C0 ii

D0 dd

F0 hh ll

E0 xb

E0 xb ff

E0 xb ee ff

E0 xb

E0 xb ee ff

SUBD # opr16i

SUBD opr8a

SUBD opr16a

SUBD oprx0_xysppc

SUBD oprx9,xysppc

SUBD oprx16,xysppc

SUBD [D, xysppc]

SUBD [ oprx16,xysppc]

Subtract from D

(A:B)–(M:M+1) or (A:B)–imm

A:B

A:B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

83 jj kk

93 dd

B3 hh ll

A3 xb

A3 xb ff

A3 xb ee ff

A3 xb

A3 xb ee ff

SWI Software interrupt; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

(SWI vector)

PC

;1

I

INH

3F

*The CPU also uses

VSPSSPSsP

for hardware interrupts and unimplemented opcode traps.

TAB Transfer A to B; (A)

B INH

18 0E

TAP

TBA

Transfer A to CCR; (A)

CCR

Assembled as TFR A, CCR

Transfer B to A; (B)

A

INH

INH

B7 02

18 0F

TBEQ abdxysp,rel9

04 lb rr

TBL

TFR oprx0_xysppc

TBNE abdxysp,rel9 abcdxysp,abcdxysp

TPASame as TFR CCR ,A

Test and branch if equal to 0

If (counter)=0, then (PC)

+

2

+ rel

PC

Table lookup and interpolate, 8-bit

(M)+[(B)

×

((M+1)–(M))]

A

Test and branch if not equal to 0

If (counter)

0, then (PC)

+

2

+ rel

PC

Transfer from register to register

(r1)

⇒ r2r1 and r2 same size

$00:(r1)

⇒ r2r1=8-bit; r2=16-bit

(r1

L

)

⇒ r2r1=16-bit; r2=8-bit

Transfer CCR to A; (CCR)

A

REL

(9-bit)

IDX

REL

(9-bit)

INH

INH

18 3D xb

04 lb rr

B7 eb

B7 20

OO

PPP

(branch)

PPO

(no branch)

ORfffP

PPP

(branch)

PPO

(no branch)

P

P

Access Detail

PW

PWO

PW

PWO

PWP

PIfW

PIPW

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

VSPSSPSsP*

OO

P

S X H I N Z V C

– – – –

∆ ∆

0 –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – 1 – – – –

– – – –

∆ ∆

0 –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – –

∆ ∆

0 –

– – – – – – – –

– – – –

∆ ∆

– – – – – – – –

– – – – – – – – or

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

For More Information On This Product,

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Source Form

TRAP trapnum

TST opr16a

TST oprx0_xysppc

TST oprx9,xysppc

TST oprx16,xysppc

TST [D, xysppc]

TST [ oprx16,xysppc]

TSTA

TSTB

TSXSame as TFR SP,X

TSYSame as TFR SP,Y

TXSSame as TFR X,SP

TYSSame as TFR Y,SP

WAI

WAV

Operation

Trap unimplemented opcode;

(SP)–2

SP

RTN

H

:RTN

L

M

SP

(SP)–2

SP; (Y

H

:Y

:M

SP+1

L

)

M

SP

(SP)–2

SP; (X

H

:X

L

)

M

SP

(SP)–1

SP; (CCR)

M

SP

1

I; (trap vector)

PC

:M

SP+1

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

Test M; (M)–0

Address

Mode

INH

Machine

Coding (Hex)

18 tn tn = $30–$39 or tn = $40–$FF

Test A; (A)–0

Test B; (B)–0

Transfer SP to X; (SP)

X

Transfer SP to Y; (SP)

Y

Transfer X to SP; (X)

SP

Transfer Y to SP; (Y)

SP

Wait for interrupt; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

Calculate weighted average; sum of products (SOP) and sum of weights

(SOW)*

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

INH

INH

INH

INH

F7 hh ll

E7 xb

E7 xb ff

E7 xb ee ff

E7 xb

E7 xb ee ff

97

D7

B7 75

B7 76

B7 57

B7 67

3E

Special

18 3C

OVSPSSPSsP rPO rPf rPO frPP fIfrPf fIPrPf

O

O

P

P

P

P

Access Detail

OSSSSsf

(before interrupt) fVfPPP

(after interrupt)

S X H I N Z V C

– – – 1 – – – –

– – – –

∆ ∆

0 0

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – – or

– – – 1 – – – – or

– 1 – 1 – – – –

Of(frr^ffff)O**

SSS+UUUrr^***

– – ? – ?

? ?

B

∑ i = 1

S i

F i

B

F i

X i = 1

Y:D

*Initialize B, X, and Y: B=number of elements; X points at first element in S i list; Y points at first element in F i list. All S i and F i elements are 8-bit values.

**The frr^ffff

sequence is the loop for one iteration of SOP and SOW accumulation. The

^

denotes a check for pending interrupt requests.

***Additional cycles caused by an interrupt:

SSS is the exit sequence and

UUUrr^ is the re-entry sequence. Intermediate values use six stack bytes.

wavr* Resume executing interrupted WAV Special

3C UUUrr^ffff(frr^ ffff)O**

SSS+UUUrr^***

– – ? – ?

? ?

*wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0.

**The frr^ffff

sequence is the loop for one iteration of SOP and SOW recovery. The

^

denotes a check for pending interrupt requests.

***These are additional cycles caused by an interrupt:

SSS

is the exit sequence and

UUUrr^

is the re-entry sequence.

XGDXSame as EXG D, X Exchange D with X; (D)

(X) INH

B7 C5 P

– – – – – – – –

XGDYSame as EXG D, Y Exchange D with Y; (D)

(Y) INH

B7 C6 P

– – – – – – – –

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1.8.1 Register and Memory Notation

Table 1-3 Register and Memory Notation

A or a Accumulator A

An Bit n of accumulator A

B or b Accumulator B

Bn Bit n of accumulator B

D or d Accumulator D

Dn Bit n of accumulator D

X or x Index register X

X

H

High byte of index register X

X

L

Low byte of index register X

Xn Bit n of index register X

Y or y Index register Y

Y

H

High byte of index register Y

Y

L

Low byte of index register Y

Yn Bit n of index register Y

SP or sp Stack pointer

SPn Bit n of stack pointer

PC or pc Program counter

PC

H

High byte of program counter

PC

L

Low byte of program counter

CCR or c Condition code register

M Address of 8-bit memory location

Mn Bit n of byte at memory location M

Rn Bit n of the result of an arithmetic or logical operation

In Bit n of the intermediate result of an arithmetic or logical operation

RTN

H

High byte of return address

RTN

L

Low byte of return address

( ) Contents of

1.8.2 Source Form Notation

The Source Form column of the summary in

Table 1-2

gives essential information about assembler

source forms. For complete information about writing source files for a particular assembler, refer to the documentation provided by the assembler vendor.

Everything in the Source Form column, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, square brackets ( [ or ] ), plus signs

(+), minus signs (–), and the register designation (A, B, D), are literal characters.

The groups of italic characters shown in

Table 1-4

represent variable information to be supplied by the

programmer. These groups can include any alphanumeric character or the underscore character, but cannot

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include a space or comma. For example, the groups xysppc and oprx0_xysppc are both valid, but the two groups oprx0 xysppc are not valid because there is a space between them.

Table 1-4 Source Form Notation

abc abcdxysp abd abdxysp dxysp

Register designator for A, B, or CCR

Register designator for A, B, CCR, D, X, Y, or SP

Register designator for A, B, or D

Register designator for A, B, D, X, Y, or SP msk8

Register designator for D, X, Y, or SP

8-bit mask value

Some assemblers require the # symbol before the mask value.

opr8i opr16i opr8a opr16a page

8-bit immediate value

16-bit immediate value

8-bit address value used with direct address mode

16-bit address value oprx0_xysp Indexed addressing postbyte code: oprx3,–xysp — Predecrement X , Y, or SP by 1–8 oprx3,+xysp — Preincrement X , Y, or SP by 1–8 oprx3,xysp– — Postdecrement X, Y, or SP by 1–8 oprx3,xysp+ — Postincrement X, Y, or SP by 1–8 oprx5,xysppc — 5-bit constant offset from X, Y, SP, or PC abd,xysppc — Accumulator A, B, or D offset from X, Y, SP, or PC oprx3 oprx5

Any positive integer from 1 to 8 for pre/post increment/decrement

Any integer from –16 to +15 oprx9 oprx16

Any integer from –256 to +255

Any integer from –32,768 to +65,535

8-bit value for PPAGE register

Some assemblers require the # symbol before this value.

rel8 rel9 rel16 trapnum xysp xysppc

Label of branch destination within –256 to +255 locations

Label of branch destination within –512 to +511 locations

Any label within the 64-Kbyte memory space

Any 8-bit integer from $30 to $39 or from $40 to $FF

Register designator for X or Y or SP

Register designator for X or Y or SP or PC

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1.8.3 Operation Notation

Table 1-5 Operation Notation

+ Add

– Subtract

AND

| OR

Exclusive OR

×

Multiply

÷

Divide

: Concatenate

Transfer

Exchange

1.8.4 Address Mode Notation

Table 1-6 Address Mode Notation

INH Inherent; no operands in instruction stream

IMM Immediate; operand immediate value in instruction stream

DIR Direct; operand is lower byte of address from $0000 to $00FF

EXT Operand is a 16-bit address

REL Two’s complement relative offset; for branch instructions

IDX Indexed (no extension bytes); includes:

5-bit constant offset from X, Y, SP or PC

Pre/post increment/decrement by 1–8

Accumulator A, B, or D offset

IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte

IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes

[IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC

[D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC

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1.8.5 Machine Code Notation

In the Machine Code (Hex) column of the summary in

Table 1-2

, digits 0–9 and upper case letters A–F represent hexadecimal values. Pairs of lower-case letters represent 8-bit values as shown in

Table 1-7

.

Table 1-7 Machine Code Notation

dd

8-bit direct address from $0000 to $00FF; high byte is $00 ee

High byte of a 16-bit constant offset for indexed addressing eb

Exchange/transfer postbyte ff

Low eight bits of a 9-bit signed constant offset in indexed addressing, or low byte of a 16-bit constant offset in indexed addressing hh

High byte of a 16-bit extended address ii

8-bit immediate data value jj

High byte of a 16-bit immediate data value kk

Low byte of a 16-bit immediate data value lb

Loop primitive (DBNE) postbyte ll

Low byte of a 16-bit extended address mm

8-bit immediate mask value for bit manipulation instructions; bits that are set indicate bits to be affected pg

Program page or bank number used in CALL instruction qq

High byte of a 16-bit relative offset for long branches tn

Trap number from $30 to $39 or from $40 to $FF rr

Signed relative offset $80 (–128) to $7F (

+

127) relative to the byte following the relative offset byte, or low byte of a 16-bit relative offset for long branches xb

Indexed addressing postbyte

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1.8.6 Access Detail Notation

A single-letter code in the Access Detail column of

Table 1-2

represents a single CPU access cycle. An upper-case letter indicates a 16-bit access.

Table 1-8 Access Detail Notation

f

Free cycle. During an f

cycle, the CPU does not use the bus. An f

cycle is always one cycle of the system bus clock. An f cycle can be used by a queue controller or the background debug system to perform a single-cycle access without disturbing the CPU.

g

Read PPAGE register. A g

cycle is used only in CALL instructions and is not visible on the external bus. Since PPAGE is an internal 8-bit register, a g

cycle is never stretched.

I

Read indirect pointer. Indexed-indirect instructions use the 16-bit indirect pointer from memory to address the instruction operand. An

I

cycle is a 16-bit read that can be aligned or misaligned. An

I cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An

I

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

i

Read indirect PPAGE value. An i

cycle is used only in indexed-indirect CALL instructions. The 8-bit

PPAGE value for the CALL destination is fetched from an indirect memory location. An i

cycle is stretched only when controlled by a chip-select circuit that is programmed for slow memory.

n

Write PPAGE register. An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus. Since the PPAGE register is an internal 8-bit register, an n

cycle is never stretched.

O

Optional cycle. An

O cycle adjusts instruction alignment in the instruction queue. An

O cycle can be a free cycle ( f

) or a program word access cycle (

P

). When the first byte of an instruction with an odd number of bytes is misaligned, the

O

cycle becomes a

P

cycle to maintain queue order. If the first byte is aligned, the

O

cycle is an f

cycle.

The $18 prebyte for a page-two opcode is treated as a special one-byte instruction. If the prebyte is misaligned, the

O

cycle at the beginning of the instruction becomes a

P

cycle to maintain queue order. If the prebyte is aligned, the

O

cycle is an f

cycle. If the instruction has an odd number of bytes, it has a second

O

cycle at the end. If the first

O

cycle is a

P

cycle (prebyte misaligned), the second

O cycle is an f cycle. If the first

O cycle is an f cycle (prebyte aligned), the second

O cycle is a

P

cycle.

An

O cycle that becomes a

P cycle can be extended to two bus cycles if the MCU is operating with an

8-bit external data bus and the program is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

O

cycle that becomes an f

cycle is never stretched.

P

Program word access. Program information is fetched as aligned 16-bit words. A

P cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

r

8-bit data read. An r cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

R

16-bit data read. An

R

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

R

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

s

Stack 8-bit data. An s cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

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Table 1-8 Access Detail Notation (Continued)

S

Stack 16-bit data. An

S

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching if the address space is assigned to a chip-select circuit programmed for slow memory. An

S

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single cycle misaligned word access.

w

8-bit data write. A w

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

W

16-bit data write. A

W

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

A

W cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

u

Unstack 8-bit data. A

W

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

U

Unstack 16-bit data. A

U

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word access.

V

16-bit vector fetch. Vectors are always aligned 16-bit words. A

V

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

t

8-bit conditional read. A t cycle is either a data read cycle or a free cycle, depending on the data and flow of the REVW instruction. A t

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

T

16-bit conditional read. A

T

cycle is either a data read cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. A

T

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

x

8-bit conditional write. An x

cycle is either a data write cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. An x

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

Special Notation for Branch Taken/Not Taken

PPP/P

A short branch requires three cycles if taken, one cycle if not taken. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the queue advances, another program word fetch is made, and execution continues with the next instruction. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

OPPP/OPO

A long branch requires four cycles if taken, three cycles if not taken. An

O

cycle is required because all long branches are page two opcodes and thus include the $18 prebyte. The prebyte is treated as a one-byte instruction. If the prebyte is misaligned, the

O

cycle is a

P

cycle; if the prebyte is aligned, the

O

cycle is an f

cycle. As a result, both the taken and not-taken cases use one

O

cycle for the prebyte. In the not-taken case, the queue must advance so that execution can continue with the next instruction, and another

O

cycle is required to maintain the queue. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

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1.8.7 Condition Code State Notation

Table 1-9 Condition Code State Notation

– Not changed by operation

0 Cleared by operation

1 Set by operation

Set or cleared by operation

May be cleared or remain set, but not set by operation

May be set or remain cleared, but not cleared by operation

? May be changed by operation but final state not defined

! Used for a special purpose

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Section 2 Nomenclature

This section describes the conventions and notation used to describe the Core operation.

2.1 References

This document uses the Sematech Official Dictionary and the JEDEC/EIA Reference Guide to Letter

Symbols for Semiconductor Devices as references for terminology and symbology.

2.2 Units and Measures

SIU units and abbreviations are used throughout this guide.

2.3 Symbology

The symbols and operators used throughout this guide are shown in

Table 2-1

.

Table 2-1 Symbols and Operators

+

NOT

:

Symbol

+

/

>

-

*

<

=

0b0011

0x0F

Function

Addition

Subtraction (two’s complement) or negation

Multiplication

Division

Greater

Less

Equal

Equal or greater

Equal or less

Not equal

AND

Inclusive OR (OR)

Exclusive OR (EOR)

Complementation

Concatenation

Transferred

Exchanged

Tolerance

Binary value

Hexadecimal value

2.4 Terminology

Logic level one is a voltage that corresponds to Boolean true (1) state.

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Logic level zero is a voltage that corresponds to Boolean false (0) state.

To set a bit or bits means to establish logic level one on them.

To clear a bit or bits means to establish logic level zero on them.

A signal is an electronic construct whose state or changes in state convey information.

A pin is an external physical connection. The same pin can be used to connect a number of signals.

Asserted means that a discrete signal is in active logic state.

Active low signals change from logic level one to logic level zero.

Active high signals change from logic level zero to logic level one.

Negated means that an asserted discrete signal changes logic state.

Active low signals change from logic level zero to logic level one.

Active high signals change from logic level one to logic level zero.

LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes or words are spelled out.

Memory and registers use big-endian ordering. The most significant byte (byte 0) of word 0 is located at address 0. Bits within a word are numbered downward from the MSB, bit 15.

Signal, bit field, and control bit mnemonics follow a general numbering scheme:

• A range of mnemonics is referred to by mnemonic and numbers that define the range, from highest to lowest. For example, p_addr[4:0] are lines four to zero of an address bus.

• A single mnemonic stands alone or includes a single numeric designator when appropriate. For example, m_rst is a unique mnemonic, while p_addr15 represents line 15 of an address bus.

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Section 3 Core Registers

This section provides detailed descriptions of the Core programming model, registers and accumulators.

In addition, a general description of the complete Core register map which includes all Core sub-blocks is included.

3.1 Programming Model

The Core CPU12 programming model, shown in

Figure 3-1

, is the same as that of the 68HC12 and

68HC11. The register set and data types used in the model are covered in the subsections that follow.

7

15

15

15

15

15

A

0

D

7

X

Y

SP

PC

B

0

0

8-BIT ACCUMULATORS A AND B

16-BIT DOUBLE ACCUMULATOR D (A: B)

0 INDEX REGISTER X

0 INDEX REGISTER Y

0 STACK POINTER

0 PROGRAM COUNTER

S X H I N Z V C

CONDITION CODE REGISTER

CARRY

OVERFLOW

ZERO

NEGATIVE

IRQ INTERRUPT MASK (DISABLE)

HALF-CARRY FOR BCD ARITHMETIC

XIRQ INTERRUPT MASK (DISABLE)

STOP DISABLE (IGNORE STOP INSTRUCTION)

Figure 3-1 Programming Model

3.1.1 Accumulators

General-purpose 8-bit accumulators A and B hold operands and results of operations. Some instructions use the combined 8-bit accumulators, A:B, as a 16-bit double accumulator, D, with the most significant byte in A.

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7

Read:

Write:

Reset: 0

6 5 4 3 2 1

0 0 0 0

Figure 3-2 Accumulator A

0 0

0

0

7

Read:

Write:

Reset: 0

6 5 4 3 2 1 0

0 0 0 0

Figure 3-3 Accumulator B

0 0 0

Most operations can use accumulator A or B interchangeably. However, there are a few exceptions. Add, subtract, and compare instructions involving both A and B (ABA, SBA, and CBA) only operate in one direction, so it is important to verify that the correct operand is in the correct accumulator. The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations.

There is no equivalent instruction to adjust accumulator B.

3.1.2 Index Registers (X and Y)

16-bit index registers X and Y are used for indexed addressing. In indexed addressing, the contents of an index register are added to a 5-bit, 9-bit, or 16-bit constant or to the contents of an accumulator to form the effective address of the instruction operand. Having two index registers is especially useful for moves and in cases where operands from two separate tables are used in a calculation.

15 14 13 12 11 10

Read:

Write:

Reset: 0 0 0 0 0 0

9 8 7 6 5

0 0 0 0

Figure 3-4 Index Register X

0

4 3 2 1 0

0 0 0 0 0

15 14 13 12 11 10 9 8 7 6

Figure 3-5 Index Register Y

5 4 3 2 1 0

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Read:

Write:

Reset: 0 0 0 0 0 0 0 0 0 0

Figure 3-5 Index Register Y

0 0 0 0 0 0

3.1.3 Stack Pointer (SP)

The stack stores system context during subroutine calls and interrupts, and can also be used for temporary data storage. It can be located anywhere in the standard 64K byte address space and can grow to any size up to the total amount of memory available in the system.

SP holds the 16-bit address of the last stack location used. Normally, SP is initialized by one of the first instructions in an application program. The stack grows downward from the address pointed to by SP.

Each time a byte is pushed onto the stack, the stack pointer is automatically decremented, and each time a byte is pulled from the stack, the stack pointer is automatically incremented.

When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return from subroutine (RTS) is executed at the end of a subroutine. The return instruction loads the program counter with the previously stacked return address and execution continues at that address.

15 14 13 12 11 10

Read:

Write:

Reset: 0 0 0

9 8 7 6 5

0 0 0 0 0 1 1 1

Figure 3-6 Stack Pointer (SP)

4

1

3 2 1

1 1 1

0

1

When an interrupt occurs, the CPU:

• Completes execution of the current instruction

• Calculates the address of the next instruction and pushes it onto the stack

• Pushes the contents of all the CPU registers onto the stack

• Loads the program counter with the address pointed to by the interrupt vector, and begins execution at that address

The stacked CPU registers are referred to as an interrupt stack frame. The Core stack frame is the same as that of the CPU.

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3.1.4 Program Counter (PC)

PC is a 16-bit register that holds the address of the next instruction to be executed. The address in PC is automatically incremented each time an instruction is executed.

15 14 13 12 11 10

Read:

Write:

Reset: 0

0 0

9 8 7 6 5 4

0 0 0 0 0 0 0 0

Figure 3-7 Program Counter (PC)

0

3 2 1

0 0 0

0

0

3.1.5 Condition Code Register (CCR)

CCR has five status bits, two interrupt mask bits, and a STOP instruction mask bit. It is named for the five conditions indicated by the status bits.

The status bits reflect the results of CPU operations. The five status bits are half-carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry bit is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a CPU operation.

Most instructions automatically update condition codes, so it is rarely necessary to execute extra instructions to load and test a variable. The condition codes affected by each instruction are shown in

Appendix A

of this guide.

The following paragraphs describe common uses of the condition codes. There are other, more specialized uses. For instance, the C status bit is used to enable weighted fuzzy logic rule evaluation. Specialized usages are described in the relevant portions of this guide and in

Appendix A

.

Read:

Write:

Reset:

Bit 7

S

6

X

5

H

4

I

3

N

2

Z

1

V

1 1 0 1 0 0

Figure 3-8 Condition Code Register (CCR)

0

Bit 0

C

0

S — STOP Mask Bit

Clearing the S bit enables the STOP instruction. Execution of a STOP instruction causes the on-chip oscillator to stop. This may be undesirable in some applications. When the S bit is set, the CPU treats the STOP instruction as a no-operation (NOP) instruction and continues on to the next instruction.

Reset sets the S bit.

1 = STOP instruction disabled

0 = STOP instruction enabled

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X — XIRQ Mask Bit

Clearing the X bit enables interrupt requests on the XIRQ pin. The XIRQ input is an updated version of the nonmaskable interrupt (NMI) input found on earlier generations of Motorola microcontroller units (MCUs). Nonmaskable interrupts are typically used to deal with major system failures such as loss of power. However, enabling nonmaskable interrupts before a system is fully powered and initialized can lead to spurious interrupts. The X bit provides a mechanism for masking nonmaskable interrupts until the system is stable.

Reset sets the X bit. As long as the X bit remains set, interrupt service requests made via the XIRQ pin are not recognized. Software must clear the X bit to enable interrupt service requests from the XIRQ pin. Once software clears the X bit, enabling XIRQ interrupt requests, only a reset can set it again. The

X bit does not affect I bit maskable interrupt requests.

When the X bit is clear and an XIRQ interrupt request occurs, the CPU stacks the cleared X bit. It then automatically sets the X and I bits in the CCR to disable XIRQ and maskable interrupt requests during the XIRQ interrupt service routine.

An RTI instruction at the end of the interrupt service routine restores the cleared X bit to the CCR, re-enabling XIRQ interrupt requests.

1 = XIRQ interrupt requests disabled

0 = XIRQ interrupt requests enabled

H — Half-Carry Bit

The H bit indicates a carry from bit 3 of the result during an addition operation. The DAA instruction uses the value of the H bit to adjust the result in accumulator A to BCD format. ABA, ADD, and ADC are the only instructions that update the H bit.

1 = Carry from bit 3 after ABA, ADD, or ADC instruction

0 = No carry from bit 3 after ABA, ADD, or ADC instruction

I — Interrupt Mask Bit

Clearing the I bit enables maskable interrupt sources. Reset sets the I bit. To enable maskable interrupt requests, software must clear the I bit. Maskable interrupt requests that occur while the I bit is set remain pending until the I bit is cleared.

When the I bit is clear and a maskable interrupt request occurs, the CPU stacks the cleared I bit. It then automatically sets the I bit in the CCR to prevent other maskable interrupt requests during the interrupt service routine.

An RTI instruction at the end of the interrupt service routine restores the cleared I bit to the CCR, reenabling maskable interrupt requests. The I bit can be cleared within the service routine, but implementing a nested interrupt scheme requires great care, and seldom improves system performance.

1 = Maskable interrupt requests disabled

0 = Maskable interrupt requests enabled

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N — Negative Bit

The N bit is set when the MSB of the result is set. N is most commonly used in two’s complement arithmetic, where the MSB of a negative number is one and the MSB of a positive number is zero, but it has other uses. For instance, if the MSB of a register or memory location is used as a status bit, the user can test the bit by loading an accumulator.

1 = MSB of result set

0 = MSB of result clear

Z — Zero Bit

The Z bit is set when all the bits of the result are zeros. Compare instructions perform an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. The

INX, DEX, INY, and DEY instructions affect the Z bit and no other condition bits. These operations can only determine = and

.

1 = Result all zeros

0 = Result not all zeros

V — Overflow Bit

The V bit is set when a two’s complement overflow occurs as a result of an operation.

1 = Overflow

0 = No overflow

C — Carry Bit

The C bit is set when a carry occurs during addition or a borrow occurs during subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate through the C bit to facilitate multiple-word shifts.

1 = Carry or borrow

0 = No carry or borrow

3.2 Core Register Map

The Core registers are those that are part of the sub-blocks that support the CPU to makeup the entire Core block. In addition to the registers contributed by the Core sub-blocks, sections of the Core space are reserved for registers contributed by the system peripherals and memory sub-blocks. These registers are configured at integration of the Core into the SoC design. The Core register map summary is shown in

Figure 3-9

below.

The Core registers, with the exception of those associated with the BDM sub-block (addresses $FF00 through $FF07), can be mapped to any 2K byte block within the first 32K byte space of the standard 64K byte address area by configuring the INITRG register.

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For detailed descriptions of the Core register and bit functionality please refer to Core sub-block description sections of this guide. To assist in locating this more detailed information,

Table 3-1

below

lists the Core registers, the sub-block they are associated with and a brief description of function.

Address

$0000

$0001

$0002

$0003

Name

PORTA

PORTB

DDRA

DDRB

$0004 Reserved

$0005 Reserved

$0006 Reserved

$0007 Reserved

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F Reserved

$0010

$0011

$0012

$0013

$0014 Reserved

$0015

PORTE

DDRE

PEAR

MODE

PUCR

RDRIV

EBICTL

INITRM

INITRG

INITEE

MISC

ITCR

Bit 7 6 5 4 3 2 1 Bit 0

read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write

Bit 7

Bit 7

Bit 7

Bit 7

0

0

0

0

Bit 7

Bit 7

NOACCE

MODC

PUPKE

RDPK

0

0

RAM15

0

EE15

0

0

0

6

6

6

6

0

0

0

0

6

6

0

MODB

0

0

0

0

RAM14

REG14

EE14

0

0

0

5

5

5

5

0

0

0

0

5

5

PIPOE

MODA

0

0

0

0

RAM13

REG13

EE13

0

0

0

4

4

4

4

0

0

0

0

4

4

NECLK

0

PUPEE

RDPE

0

0

RAM12

REG12

EE12

0

0

WRTINT

3

3

3

3

0

0

0

0

3

3

LSTRE

IVIS

0

0

0

0

RAM11

REG11

EE11

2

2

2

2

0

0

0

0

2

2

RDWE

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

0

0

EMK

PUPBE

RDPB

0

0

0

0

0

EXSTR1 EXSTR0 ROMHM

0

ADR3

0

ADR2

0

ADR1

Bit 0

Bit 0

Bit 0

Bit 0

0

0

0

0

Bit 0

0

0

EME

PUPAE

RDPA

ESTR

0

RAMHAL

0

EEON

ROMON

0

ADR0

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$0016

$0017

$0018 to

$001B

$0020 to

$0027

Reserved

$001C MEMSIZ0

$001D MEMSIZ1

$001E

$001F

IRQCR

HPRIO read reg_sw0 write

0 read rom_sw1 rom_sw0 write read write read write

IRQE

PSEL7

IRQEN

PSEL6 eeo_sw1 eep_sw0

0

0

PSEL5

0

0

PSEL4

0

0

0

PSEL3 ram_sw2 ram_sw1 ram_sw0

0

0

PSEL2 pag_sw1 pag_sw0

0

PSEL1

0

0

Reserved

Reserved for Peripheral Block Registers

Reserved for Peripheral Block Registers

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0031

$0032

$0033

ITEST

Reserved

BKPCT0

BKPCT1

BKP0X

BKP0H

BKP0L

BKP1X

BKP1H

BKP1L

PPAGE

Reserved

PORTK

DDRK read write read write write read write read write read write read read write read write read write read write read write read write read write read write

INTE

0

BKEN BKFULL BKBDM BKTAG

0 0 0 0

BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW

0

Bit 15

Bit 7

0

Bit 15

Bit 7

0

0

Bit 7

Bit 7

INTC

0

0

14

6

0

14

6

0

0

6

6

INTA

0

BK0V5

13

5

BK1V5

13

5

PIX5

0

5

5

INT8

0

BK0V4

12

4

BK1V4

12

4

PIX4

0

4

4

INT6

0

BK0V3

11

3

BK1V3

11

3

PIX3

0

3

3

INT4

0

BK0V2

10

2

BK1V2

10

2

PIX2

0

2

2

INT2

0

BK0V1

9

1

BK1V1

9

1

PIX1

0

1

1

INT0

0

BK0V0

Bit 8

Bit 0

BK1V0

Bit 8

Bit 0

PIX0

0

Bit 0

Bit 0

$0034 to

$00FF

$0100 to

$010F

Reserved

Reserved

Reserved for Peripheral Block Registers

Reserved for Flash EEPROM or ROM Registers

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$0110 to

$011B

$011C to

$011F

$0120 to

$07FF

Reserved

Reserved

Reserved

Reserved for EEPROM Registers

Reserved for RAM Registers

Reserved for Peripheral Block Registers

$FF00

$FF01

$FF02

$FF03

$FF04

$FF05

$FF06 BDMCCR

$FF07

Reserved

BDMSTS

Reserved

Reserved

Reserved

Reserved

BDMINR read write read write read write read

X X X

ENBDM BDMACT ENTAG

X X X

X

SDV

X

X

TRACE

X

X

CLKSW

X

0

UNSEC

X

X X X X X X X write read write read

X X X X X X X

X X X X X X X write read

CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 write read REG15 REG14 REG13 REG12 REG11 0 0 write

0

CORE

X

X

X

X

CCR0

0

= Unimplemented X = Indeterminate

Figure 3-9 Core Register Map Summary

Table 3-1 Core Register Map Reference

Address Name Sub-block

$0000 PORTA MEBI

$0001

$0002

$0003

$0008

$0009

PORTB

DDRA

DDRB

PORTE

DDRE

MEBI

MEBI

MEBI

MEBI

MEBI

Description

Port A 8-bit Data Register

Port B 8-bit Data Register

Port A 8-bit Data Direction Register

Port B 8-bit Data Direction Register

$000A

$000B

$000C

PEAR

MODE

PUCR

MEBI

MEBI

MEBI

Port E 8-bit Data Register

Port E 8-bit Data Direction Register

Port E Assignment Register - configures functionality of Port E as general purpose I/O and/or alternate functions

Used to establish mode of operation of the Core and configure other miscellaneous functions

Pullup Control Register to configure state of pullups on Ports A, B,

E and K

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Table 3-1 Core Register Map Reference

Address Name Sub-block

$000D RDRIV MEBI

Description

Reduced Drive Register to configure drive strength of pins associated with Ports A, B, E and K

$000E

$0010

$0011

$0012

$0013

$0015

$0016

$001C

$001D

$001E

$001F

$0028

$0029

$002A

$002B

$002C

$002D

$002E

$002F

$0030

$0032

$0033

$FF01

$FF06

$FF07

EBICTL

INITRM

INITRG

INITEE

MISC

ITCR

ITEST

IRQCR

HPRIO

BKP0X

BKP0H

BKP0L

BKP1X

BKP1H

BKP1L

PPAGE

MEBI

MMC

MMC

MMC

MMC

INT

INT

MEMSIZ0 MMC

MEMSIZ1 MMC

MEBI

INT

BKPCT0 BKP

BKPCT1 BKP

BKP

BKP

BKP

BKP

BKP

BKP

MMC

PORTK

DDRK

MEBI

MEBI

BDMSTS BDM

BDMCCR BDM

BDMINR BDM

External Bus Interface Control Register to configure functionality of external E-clock signal

Initialization of Internal RAM Position Register

Initialization of Internal Registers Position Register

Initialization of Internal EEPROM Registers Position Register

Miscellaneous Register to configure various system functions

Interrupt Test Control Register used in special modes of operation for testing interrupt logic

Interrupt Test Register used in special modes of operation testing interrupt logic

Memory Size Register 0 to allow capability to read the state of the system memory configuration switches

Memory Size Register 1 to allow capability to read the state of the system memory configuration switches

IRQ Control Register to configure IRQ pin functionality

Highest Priority I Interrupt Register (optional)

Breakpoint Control Register 0 to configure mode of operation of breakpoint functions

Breakpoint Control Register 1 to configure mode of operation of breakpoint functions

First Address Memory Expansion Breakpoint Register to assign first address match value for expanded addresses

First Address High Byte Breakpoint Register to assign high byte of first address within system memory space to be matched

First Address Low Byte Breakpoint Register to assign low byte of first address within system memory space to be matched

Second Address Memory Expansion Breakpoint Register to assign second address match value for expanded addresses

Second Address High Byte Breakpoint Register to assign high byte of first address within system memory space to be matched

Second Address Low Byte Breakpoint Register to assign low byte of first address within system memory space to be matched

Program Page Index Register to configure the active memory page viewed through the program page window from $8000-$BFFF

Port K 8-bit Data Register

Port K 8-bit Data Direction Register

BDM Status Register

BDM CCR Holding Register for interaction of BDM with CPU

BDM Internal Register Position Register to configure BDM register mapping

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Section 4 Instructions

This section describes the instruction set of the Core. This discussion includes descriptions of instructions grouped by type, the addressing modes used and the opcode map. Please refer to

Appendix A

of this

guide for a detailed instruction-by-instruction description of each opcode.

4.1 Instruction Types

All memory and I/O are mapped in a common 64K byte address space, allowing the same set of instructions to access memory, I/O, and control registers. Load, store, transfer, exchange, and move instructions facilitate movement of data to and from memory and peripherals.

There are instructions for signed and unsigned addition, division and multiplication with 8-bit, 16-bit, and some larger operands.

Special arithmetic and logic instructions aid stacking operations, indexing, BCD calculation, and condition code register manipulation. There are also dedicated instructions for multiply and accumulate operations, table interpolation, and specialized mathematical calculations for fuzzy logic operations.

4.2 Addressing Modes

A summary of the addressing modes used by the Core is given in

Table 4-1

below. The operation of each of these modes is discussed in the subsections that follow.

Table 4-1 Addressing Mode Summary

Addressing Mode

Inherent

Immediate

Source Form

INST

(no externally supplied operands)

INST #opr8i or

INST #opr16i

Abbreviation

INH

IMM

Description

Operands (if any) are in CPU registers.

Operand is included in instruction stream; 8-bit or

16-bit size implied by context.

Direct

Extended

INST opr8a DIR

EXT

Operand is the lower 8-bits of an address in the range

$0000–$00FF.

Operand is a 16-bit address.

Relative

INST opr16a

INST rel8 or

INST rel16

REL

Effective address is the value in PC plus an 8-bit or

16-bit relative offset value.

Indexed

(5-bit offset)

Indexed

(predecrement)

Indexed

(preincrement)

Indexed

(postdecrement)

INST oprx5,xysp

INST oprx3,–xys

INST oprx3,+xys

INST oprx3,xys–

IDX

IDX

IDX

IDX

Effective address is the value in X, Y, SP, or PC plus a

5-bit signed constant offset.

Effective address is the value in X, Y, or SP autodecremented by 1 to 8.

Effective address is the value in X, Y, or SP autoincremented by 1 to 8.

Effective address is the value in X, Y, or SP. The value is postdecremented by 1 to 8.

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Addressing Mode

Indexed

(postincrement)

Indexed

(accumulator offset)

Indexed

(9-bit offset)

Indexed

(16-bit offset)

Indexed-indirect

(16-bit offset)

Indexed-indirect

(D accumulator offset)

Table 4-1 Addressing Mode Summary

Source Form

INST oprx3,xys+

INST abd,xysp

INST oprx9,xysp

INST oprx16,xysp

INST [oprx16,xysp]

INST [D,xysp]

Abbreviation

IDX

IDX

IDX1

IDX2

[IDX2]

[D,IDX]

Description

Effective address is the value in X, Y, or SP. The value is postincremented by 1 to 8.

Effective address is the value in X, Y, SP, or PC plus the value in A, B, or D.

Effective address is the value in X, Y, SP, or PC plus a

9-bit signed constant offset.

Effective address is the value in X, Y, SP, or PC plus a

16-bit constant offset.

The value in X, Y, SP, or PC plus a 16-bit constant offset points to the effective address.

The value in X, Y, SP, or PC plus the value in D points to the effective address.

4.2.1 Effective Address

Every addressing mode except inherent mode generates a 16-bit effective address. The effective address is the address of the memory location that the instruction acts on. Effective address computations do not require extra execution cycles.

4.2.2 Inherent Addressing Mode

Instructions that use this addressing mode either have no operands or all operands are in internal CPU registers. In either case, the CPU does not need to access any memory locations to complete the instruction.

NOP

INX

;this instruction has no operands

;operand is a CPU register

4.2.3 Immediate Addressing Mode

Operands for immediate mode instructions are included in the instruction and are fetched into the instruction queue one 16-bit word at a time during normal program fetch cycles. Since program data is read into the instruction queue several cycles before it is needed, when an immediate addressing mode operand is called for by an instruction, it is already present in the instruction queue.

The pound symbol (#) is used to indicate an immediate addressing mode operand. One very common programming error is to accidentally omit the # symbol. This causes the assembler to misinterpret the following expression as an address rather than explicitly provided data. For example LDAA #$55 means to load the immediate value $55 into the A accumulator, while LDAA $55 means to load the value from address $0055 into the A accumulator. Without the # symbol the instruction is erroneously interpreted as a direct addressing instruction.

LDAA #$55

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LDX #$1234

LDY #$67

The size of the immediate operand is implied by the instruction context. In the third example, the instruction implies a 16-bit immediate value but only an 8-bit value is supplied. In this case the assembler generates the 16-bit value $0067 because the CPU expects a 16-bit value in the instruction stream.

BRSET FOO,#$03,THERE

In this example, extended addressing is used to access the operand FOO, immediate addressing is used to access the mask value $03, and relative addressing is used to identify the destination address of a branch in case the branch-taken conditions are met. BRSET is listed as an extended mode instruction even though immediate and relative modes are also used.

4.2.4 Direct Addressing Mode

This addressing mode is sometimes called zero-page addressing because it accesses operands in the address range $0000 through $00FF. Since these addresses always begin with $00, only the low byte of the address needs to be included in the instruction, which saves program space and execution time. A system can be optimized by placing the most commonly accessed data in this area of memory. The low byte of the operand address is supplied with the instruction and the high byte of the address is assumed to be zero.

LDAA $55

The value $55 is taken to be the low byte of an address in the range $0000 through $00FF. The high byte of the address is assumed to be zero. During execution, the CPU combines the value $55 from the instruction with the assumed value of $00 to form the address $0055, which is then used to access the data to be loaded into accumulator A.

LDX $20

In this example, the value $20 is combined with the assumed value of $00 to form the address $0020. Since the LDX instruction requires a 16-bit value, a 16-bit word of data is read from addresses $0020 and $0021.

After execution, the X index register has the value from address $0020 in its high byte and the value from address $0021 in its low byte.

4.2.5 Extended Addressing Mode

In extended addressing, the full 16-bit address of the memory location to be operated on is provided in the instruction. Extended addressing can access any location in the 64K byte memory map.

LDAA $F03B

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The value from address $F03B is loaded into the A accumulator.

4.2.6 Relative Addressing Mode

Relative addressing is for branch instructions only. Relative addressing determines the branch destination.

The short and long versions of conditional branch instructions use relative addressing exclusively. The branching bit-condition instructions, BRSET and BRCLR, use multiple addressing modes, including relative mode.

A conditional branch instruction tests a status bit in the condition code register. If the bit tests true, execution begins at the destination formed by adding an offset to the address of the memory location after the offset. If the bit does not test true, execution continues with the instruction that follows the branch instruction.

A short conditional branch instruction has an 8-bit opcode and a signed 8-bit relative offset in the byte that follows the opcode. A long conditional branch instruction has an 8-bit prebyte, an 8-bit opcode and a signed 16-bit relative offset in the two bytes that follow the opcode.

A branching bit-condition instruction, BRCLR or BRSET, tests the state of one or more bits in a memory byte. Direct, extended, or indexed addressing can determine the location of the memory byte. The instruction includes an immediate 8-bit mask operand to test the bits and an 8-bit relative offset. If the bits test true, execution begins at the destination formed by adding the 8-bit offset to the address of the memory location after the offset. If the bits do not test true, execution continues with the instruction that follows the branch instruction.

Both 8-bit and 16-bit offsets are signed two’s complement numbers to support branching upward and downward in memory. The numeric range of short branch offset values is $80 (–128) to $7F (127). The numeric range of long branch offset values is $8000 (–32768) to $7FFF (32767). If the offset is zero, the

CPU executes the instruction that follows the branch instruction.

Since the offset is at the end of a branch instruction, using a negative offset value can cause the PC to point to the opcode and initiate a loop. For instance, a branch always (BRA) instruction consists of two bytes, so using an offset of $FE sets up an infinite loop; the same is true of a long branch always (LBRA) instruction with an offset of $FFFC.

An offset that points to the opcode can cause a branching bit-condition instruction to repeat execution until the specified bit condition is satisfied. Since branching bit-condition instructions can consist of four, five, or six bytes depending on the addressing mode used, the offset value that sets up a loop can vary. For instance, an offset of $FC in a 4-byte BRCLR instruction sets up a loop that executes until all the bits in the tested memory byte are clear.

4.2.7 Indexed Addressing Modes

There are seven indexed addressing modes:

• 5-bit constant offset

• Autodecrement/increment

• 9-bit constant offset

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• 16-bit constant offset

• 16-bit constant offset indexed-indirect

• Accumulator offset

• Accumulator D offset indexed-indirect

Features of indexed addressing include:

• The stack pointer can be used as an indexing register in all indexed operations

• The program counter can be used as an indexing register in all but autoincrement and autodecrement modes

• A, B, or D accumulators can be used for accumulator offsets

• Automatic pre- or postincrement or pre- or postdecrement by –8 to +8

• A choice of 5-, 9-, or 16-bit signed constant offsets

• Two indexed-indirect modes:

– Indexed-indirect mode with 16-bit offset

– Indexed-indirect mode with accumulator D offset

4.2.7.1 Indexed Addressing Postbyte

A postbyte follows all indexed addressing opcodes. There may be 0, 1, or 2 extension bytes after the postbyte. The postbyte and extensions do the following tasks:

1.

Select a register for indexing (X, Y, SP, PC, A, B, or D)

2.

Enable automatic pre- or postincrementing or decrementing of X, Y, or SP and select the pre- or postincrement value

3.

Select 5-bit, 9-bit, or 16-bit signed constant offsets

Table 4-2

shows how the postbyte enhances indexed addressing capabilities.

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Table 4-2 Summary of Indexed Operations

5-bit constant offset indexed addressing (IDX)

Postbyte:

7 rr

1

6 5

0

4 3 2 1

5-bit signed offset

0

Effective address = 5-bit signed offset + (X, Y, SP, or PC)

Accumulator offset addressing (IDX)

7

Postbyte: 1

6

1

5

1

4

rr

1

3 2

1

1 aa

2

0

Effective address = (X, Y, SP, or PC) + (A, B, or D)

Autodecrement/autoincrement) indexed addressing (IDX)

7 6 5 4 3 2 1 0

Postbyte:

rr

1,3

1 p

4

4-bit inc/dec value

Effective address = (X, Y, or SP)

±

1 to 8

5

9-bit constant offset indexed addressing (IDX1)

7

Postbyte: 1

6

1

5

1

4

rr

1

3 2

0

1 0

0 s

6

Effective address = s:(offset extension byte) + (X, Y, SP, or PC)

16-bit constant offset indexed addressing (IDX2)

Postbyte:

7

1

6

1

5

1

4

rr

1

3 2

0

1

1

0

0

Effective address = (two offset extension bytes) + (X, Y, SP, or PC)

16-bit constant offset indexed-indirect addressing ([IDX2])

7 6 5 4 3 2 1 0

Postbyte: 1 1 1

rr

1

0 1 1

(two offset extension bytes) + (X, Y, SP, or PC) is address of pointer to effective address

Accumulator D offset indexed-indirect addressing ([D,IDX])

Postbyte:

7

1

6

1

5

1

4

rr

1

3 2

1

1

1

0

1

(X, Y, SP, or PC) + (D) is address of pointer to effective address

NOTES:

1. rr selects X (00), Y (01), SP (10), or PC (11).

2. aa selects A (00), B (01), or D (10).

3. In autoincrement/decrement indexed addressing, PC is not a valid selection.

4. p selects pre- (0) or post- (1) increment/decrement.

5. Increment values range from 0000 (+1) to 0111 (+8). Decrement values range from 1111 (–1) to 1000 (–8).

6. s is the sign bit of the offset extension byte.

All indexed addressing modes use a 16-bit CPU register and additional information to create an indexed address. In most cases the indexed address is the effective address of the instruction, that is, the address of the memory location that the instruction acts on. In indexed-indirect addressing, the indexed address is the location of a value that points to the effective address.

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PC offsets are calculated from the location immediately following the current instruction.

1000 18 09 C2 20 00 MOVB $2000 2,PC

1005 A7 NOP

This example moves a byte of data from $2000 to $1007.

4.2.7.2 5-Bit Constant Offset Indexed Addressing

This addressing mode calculates the effective address by adding a 5-bit signed offset in the postbyte to the indexing register (X, Y, SP, or PC). The value in the indexing register does not change. The 5-bit signed offset gives a range of

16 through +15 from the value in the indexing register. The majority of indexed instructions use offsets that fit in the 5-bit offset range.

For these examples, assume X contains $1000 and Y contains $2000:

LDAA 0,X

The value at address $1000 is loaded into A.

STAB –8,Y

The value in B is stored at address $2000 – $8, or $1FF8.

4.2.7.3 9-Bit Constant Offset Indexed Addressing

This addressing mode calculates the effective address by adding a 9-bit signed offset in an extension byte to the indexing register (X, Y, SP, or PC). The value in the indexing register does not change. The sign bit of the offset is in the postbyte. The 9-bit offset gives a range of

256 through +255 from the value in the indexing register.

For these examples assume X contains $1000 and Y contains $2000:

LDAA $FF,X

The value at address $10FF is loaded into A.

LDAB –20,Y

The value at address $2000 – $14, or $1FEC, is loaded into B.

4.2.7.4 16-Bit Constant Offset Indexed Addressing

This addressing mode calculates the effective address by adding a 16-bit offset in two extension bytes to the indexing register (X, Y, SP, or PC). The value in the indexing register does not change. The 16-bit offset allows access to any address in the 64K byte address space. The address bus and the offset are both

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16 bits, so it does not matter whether the offset is considered to be signed or unsigned ($FFFF may be thought of as +65,535 or as

1).

4.2.7.5 16-Bit Constant Indexed-Indirect Addressing

This addressing mode calculates the address of a pointer to the effective address. It adds a 16-bit offset in two extension bytes to the indexing register (X, Y, SP, or PC). The value in the indexing register does not change. The square brackets distinguish this addressing mode from 16-bit constant offset indexed addressng.

For this example, assume X contains $1000 and the value at address $100A is $2000:

LDAA [10,X]

The value 10 is added to the value in X to form the address $100A. The CPU fetches the effective address pointer, $2000, from address $100A and loads the value at address $2000 into A.

4.2.7.6 Autodecrement/Autoincrement Indexed Addressing

This addressing mode calculates the effective address by adding an integer value between –8 and –1 or between 1 and 8 to the indexing register (X, Y, or SP). The indexing register retains its changed value.

NOTE:

Autodecrementing and autoincrementing do not apply to the program counter.

When predecremented or preincremented, the indexing register changes before indexing takes place.

When postdecremented or postincremented, the indexing register changes after indexing takes place.

This addressing mode adjusts the indexing value without increasing execution time by using an additional instruction.

In this example, the instruction compares X with the value that X points to and then increments X by one:

CPX 1,X+

The next two examples are equivalent to common push instructions. In the first example, the instruction predecrements the stack pointer by one and then stores A to the address contained in the stack pointer:

STAA

STX

1,–SP ;equivalent to PSHA

2,–SP ;equivalent to PSHX

The next two examples are equivalent to common pull instructions. In the first example, the instruction loads X from the address in the stack pointer and then postincrements the stack pointer by two:

LDX

LDAA

2,SP+ ;equivalent to PULX

1,SP+ ;equivalent to PULA

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The next example demonstrates how to work with data structures larger than bytes and words. With this instruction in a program loop, it is possible to move words of data from a list having one word per entry into a second table that has four bytes per table element. The instruction postincrements the source pointer after reading the data from memory and preincrements the destination pointer before accessing memory:

MOVW 2,X+,4,+Y

Using a predecrement/increment version of LEAS, LEAX, or LEAY when SP, X, or Y is the respective indexing register changes the value in the indexing register. Using a postdecrement/increment version of

LEAS, LEAX, LEAY when SP, X, or Y is the respective indexing register has no effect.

4.2.7.7 Accumulator Offset Indexed Addressing

This addressing mode calculates the effective address by adding the value in the indexing register to an unsigned offset value in one of the accumulators. The value in the indexing register is not changed. The indexing register can be X, Y, SP, or PC, and the accumulator can be A, B, or D.

Example:

LDAA B,X

This instruction adds B to X to form the address from which A will be loaded. B and X are not changed by this instruction. This example is similar to the following two-instruction combination in an M68HC11.

4.2.7.8 Accumulator D Indexed-Indirect Addressing

This addressing mode calculates address of a pointer to the effective address. It adds the value in D to the value in the indexing register (X, Y, SP, or PC) The value in the indexing register does not change. The square brackets distinguish this addressing mode from D accumulator offset indexing.

In this example, accumulator D indexed-indirect addressing is used in a computed GOTO:

JMP

GO1

GO2

GO3

[D,PC]

DC.W

DC.W

DC.W

PLACE1

PLACE2

PLACE3

The values beginning at GO1 are addresses of potential destinations of the jump instruction. At the time the JMP [D,PC] instruction is executed, PC points to the address GO1, and D holds one of the values

$0000, $0002, or $0004, determined by the program some time before the JMP.

Assume that the value in D is $0002. The JMP instruction adds the values in D and PC to form the address of GO2. Next the CPU reads the address PLACE2 from memory at GO2 and jumps to PLACE2. The locations of PLACE1 through PLACE3 were known at the time of program assembly but the destination of the JMP depends upon the value in D computed during program execution.

4.2.8 Instructions Using Multiple Modes

Several instructions use more than one addressing mode in the course of execution.

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4.2.8.1 Move Instructions

Move instructions can use one addressing mode to access the source of the move and another addressing mode to access the destination. There are move variations for most combinations of immediate, extended, and indexed addressing modes.

The only combinations of addressing modes that are not allowed are those with an immediate mode destination; the operand of an immediate instruction is data, not an address. For indexed moves, the indexing register can be X, Y, SP, or PC.

Move instructions do not have indirect modes, or 9-bit or 16-bit offset modes.

4.2.8.2 Bit Manipulation Instructions

Bit manipulation instructions use a combination of two or three addressing modes.

A BCLR or BSET instruction has an 8-bit mask to clear or set bits in a memory byte. The mask is an immediate value supplied with the instruction. Direct, extended, or indexed addressing determines the location of the memory byte.

A BRCLR or BRSET instruction has an 8-bit mask to test the states of bits in a memory byte. The mask is an immediate value supplied with the instruction. Direct, extended, or indexed addressing determines the location of the memory byte. Relative addressing determines the branch address. A signed 8-bit offset must be supplied with the instruction.

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4.3 Instruction Descriptions

A brief discussion of the CPU instructions group by type is given in the subsections below. For a detailed instruction-by-instruction description please consult

Appendix A

of this guide.

4.3.1 Load and Store Instructions

Load instructions copy a value in memory or an immediate value into a CPU register. The value in memory is not changed by the operation. Load instructions (except LEAS, LEAX, and LEAY) affect condition code bits so no separate test instructions are needed to check the loaded values for negative or zero conditions.

Store instructions copy the value in a CPU register to memory. The CPU register value is not changed by the operation. Store instructions automatically update the N and Z condition code bits, which can eliminate the need for a separate test instruction in some programs.

A summary of the load and store instructions is given in

Table 4-3

.

Table 4-3 Load and Store Instructions

Mnemonic

LDAA

LDAB

LDD

LDS

LDX

LDY

LEAS

LEAX

LEAY

STAA

STAB

STD

STS

STX

STY

Function

Load A from memory

Load A with immediate value

Load B from memory

Load B with immediate value

Load D from memory

Load D with immediate value

Load SP from memory

Load SP with immediate value

Load X from memory

Load X with immediate value

Load Y from memory

Load Y with immediate value

Load effective address into SP

Load effective address into X

Load effective address into Y

Store A in memory

Store B in memory

Store D in memory

Store SP in memory

Store X in memory

Store Y in memory

Operation

(M)

A imm

A

(M)

B imm

B

(M)

A, (M + 1)

B imm

H

A, imm

L

B

(M)

SP

H

, (M + 1)

SP

L imm

H

SP

H

, imm

L

SP

L

(M)

X

H

, (M + 1)

X

L imm

H

X

H

, imm

L

X

L

(M)

Y

H

, (M + 1)

Y

L imm

H

Y

H

, imm

L

Y

L

Effective address

SP

Effective address

X

Effective address

Y

(A)

M

(B)

M

(A)

M, (B)

M + 1

(SP

H

)

M, (SP

L

)

M + 1

(X

H

)

M, (X

L

)

M + 1

(Y

H

)

M, (Y

L

)

M + 1

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4.3.2 Transfer and Exchange Instructions

Transfer instructions copy the value in a CPU register into another CPU register. The source value is not changed by the operation. TFR is a universal transfer instruction, but other mnemonics are accepted for compatibility with the M68HC12. The TAB and TBA instructions affect the N, Z, and V condition code bits in the same way as M68HC12 instructions. The TFR instruction does not affect the condition code bits.

Exchange instructions exchange the values in pairs of CPU registers.

The sign-extend instruction, SEX, is a special case of the universal transfer instruction. It adds a sign extension to an 8-bit two’s complement number so that the number can be used in 16-bit operations. The

8-bit number is copied from accumulator A, B, or the condition code register to accumulator D, the X index register, the Y index register, or the stack pointer. All the bits in the upper byte of the 16-bit result are given the value of the MSB of the 8-bit number.

A summary of the transfer and exchange instructions is given in

Table 4-4

.

Table 4-4 Transfer and Exchange Instructions

Mnemonic Function

TAB

TAP

TBA

TFR

TPA

TSX

TSY

TXS

TYS

EXG

XGDX

XGDY

SEX

Transfer A to B

Transfer A to CCR

Transfer B to A

Transfer register

Transfer CCR to A

Transfer SP to X

Transfer SP to Y

Transfer X to SP

Transfer Y to SP

Exchange registers

Exchange D with X

Exchange D with Y

Sign-extend 8-bit operand

Operation

(A)

B

(A)

CCR

(B)

A

(A, B, CCR, D, X, Y, or SP)

A, B, CCR, D, X, Y, or SP

(CCR)

A

(SP)

X

(SP)

Y

(X)

SP

(Y)

SP

(A, B, CCR, D, X, Y, or SP)

(A, B, CCR, D, X, Y, or SP)

(D)

(X)

(D)

(Y)

00:(A, B, or CCR) or FF:(A, B, or CCR)

D, X, Y, or SP

4.3.3 Move Instructions

These instructions move bytes or words from a source in memory, M

1

or M

1

:M

1

+ 1, to a destination in memory, M

2 or M

2

:M

2

+ 1. Six combinations of immediate, extended, and indexed addressing can specify source and destination addresses: IMM/EXT, IMM/IDX, EXT/EXT, EXT/IDX, IDX/EXT, and IDX/IDX.

A summary of the move instructions is given in

Table 4-5

.

Table 4-5 Move Instructions

Mnemonic

MOVB

MOVW

Function

Move byte (8-bit)

Move word (16-bit)

Operation

(M

1

)

M

2

(M

1

):(M

1

+ 1)

M

2

:M

2

+ 1

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4.3.4 Add and Subtract Instructions

Signed and unsigned 8-bit and 16-bit addition and subtraction can be performed on CPU registers, on a

CPU register and memory, or on a CPU register and an immediate value. Special instructions support index calculation. Instructions that add or subtract the carry bit, C, in the CCR facilitate multiple precision computation. A summary of the add and subtract instructions is given in

Table 4-6

.

Table 4-6 Add and Subtract Instructions

Mnemonic Function

ABA

ABX

ABY

ADCA

ADCB

ADDA

ADDB

ADDD

SBA

SBCA

SBCB

SUBA

SUBB

SUBD

Add A to B

Add B to X

Add B to Y

Add memory and carry to A

Add immediate value and carry to A

Add memory and carry to B

Add immediate value and carry to B

Add memory to A

Add immediate value to A

Add memory to B

Add immediate value to B

Add memory to D

Add immediate value to D

Subtract B from A

Subtract memory and carry from A

Subtract immediate value and carry from A

Subtract memory and carry from B

Subtract immediate value and carry from B

Subtract memory from A

Subtract immediate value from A

Subtract memory from B

Subtract immediate value from B

Subtract memory from D

Subtract immediate value from D

Operation

(A) + (B)

A

(B) + (X)

X

(B) + (Y)

Y

(A) + (M) + C

A

(A) + imm + C

A

(B) + (M) + C

B

(B) + imm + C

B

(A) + (M)

A

(A) + imm

A

(B) + (M)

B

(B) + imm

B

(A):(B) + (M):(M + 1)

A:B

(A):(B) + imm

A:B

(A) – (B)

A

(A) – (M) – C

A

(A) – imm – C

A

(B) – (M) – C

B

(B) – imm – C

B

(A) – (M)

A

(A) – imm

A

(B) – (M)

B

(B) – imm

B

(A):(B) – (M):(M + 1)

A:B

(A):(B) – imm

A:B

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4.3.5 Binary Coded Decimal Instructions

To add binary coded decimal (BCD) operands, use addition instructions that set the half-carry bit, H, in the CCR. Then adjust the result with the DAA instruction. A summary of the BCD instructions is given in

Table 4-7

.

Table 4-7 BCD Instructions

Mnemonic

ABA

ADCA

ADCB

ADDA

ADDB

DAA

Function

Add B to A

Add memory and carry to A

Add immediate value and carry to A

Add memory and carry to B

Add immediate value and carry to B

Add memory to A

Add immediate value to A

Add memory to B

Add immediate value to B

Decimal adjust A

Operation

(A) + (B)

A

(A) + (M) + C

A

(A) + imm + C

A

(B) + (M) + C

B

(B) + imm + C

B

(A) + (M)

A

(A) + imm

A

(B) + (M)

B

(B) + imm

B

(A)10

A

4.3.6 Decrement and Increment Instructions

These instructions are optimized 8-bit and 16-bit addition and subtraction operations. They are used to implement counters. Because they do not affect the carry bit, C, in the CCR, they are particularly well

suited for loop counters in multiple-precision computation routines. See 4.3.17.4 Loop Primitive

Instructions for information concerning automatic counter branches. A summary of the decrement and

increment instructions is given in Table 4-8 Decrement and Increment Instructions.

Table 4-8 Decrement and Increment Instructions

Mnemonic

DEC

DECA

DECB

DES

DEX

DEY

INC

INCA

INCB

INS

INX

INY

Function

Decrement memory

Decrement A

Decrement B

Decrement SP

Decrement X

Decrement Y

Increment memory

Increment A

Increment B

Increment SP

Increment X

Increment Y

Operation

(M) – $01

M

(A) – $01

A

(B) – $01

B

(SP) – $0001

SP

(X) – $0001

X

(Y) – $0001

Y

(M) + $01

M

(A) + $01

A

(B) + $01

B

(SP) + $0001

SP

(X) + $0001

X

(Y) + $0001

Y

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4.3.7 Compare and Test Instructions

Compare and test instructions perform subtraction on a pair of CPU registers, on a CPU register and memory, or on a CPU register and an immediate value. The result is not stored, but the operation can affect condition codes in the CCR. These instructions are used to establish conditions for branch instructions.

However, most instructions update condition codes automatically, so it is often unnecessary to include separate compare or test instructions. A summary of the compare and test instructions is given in

Table

4-9

.

Table 4-9 Compare and Test Instructions

Mnemonic Function

CBA

CMPA

CMPB

CPD

CPS

CPX

CPY

TST

TSTA

TSTB

Compare A to B

Compare A to memory

Compare A to immediate value

Compare B to memory

Compare B to immediate value

Compare D to memory

Compare D to immediate value

Compare SP to memory

Compare SP to immediate value

Compare X to memory

Compare X to immediate value

Compare Y to memory

Compare Y to immediate value

Test memory for zero or minus

Test A for zero or minus

Test B for zero or minus

Operation

(A) – (B)

(A) – (M)

(A) – imm

(B) – (M)

(B) – imm

(A):(B) – (M):(M + 1)

(A):(B) – imm

(SP) – (M):(M + 1)

(SP) – imm

(X) – (M):(M + 1)

(X) – imm

(Y) – (M):(M + 1)

(Y) – imm

(M) – $00

(A) – $00

(B) – $00

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4.3.8 Boolean Logic Instructions

These instructions perform a logic operation on the A or B accumulator and a memory value or immediate value, or on the CCR and an immediate value. A summary of the boolean logic instructions is given in

Table 4-10

.

Table 4-10 Boolean Logic Instructions

Mnemonic Function

ANDA

ANDB

ANDCC

EORA

EORB

ORAA

ORAB

ORCC

AND A with memory

AND A with immediate value

AND B with memory

AND B with immediate value

AND CCR with immediate value (to clear CCR bits)

Exclusive OR A with memory

Exclusive OR A with immediate value

Exclusive OR B with memory

Exclusive OR B with immediate value

OR A with memory

OR A with immediate value

OR B with memory

OR B with immediate value

OR CCR with immediate value (to set CCR bits)

Operation

(A)

(M)

A

(A)

• imm

A

(B)

(M)

B

(B)

• imm

B

(CCR)

• imm

CCR

(A)

(M)

A

(A)

⊕ imm

A

(B)

(M)

B

(B)

⊕ imm

B

(A) + (M)

A

(A) + imm

A

(B) + (M)

B

(B) + imm

B

(CCR) + imm

CCR

4.3.9 Clear, Complement, and Negate Instructions

These instructions perform binary operations on values in an accumulator or in memory. Clear operations clear the value, complement operations replace the value with its one’s complement, and negate operations replace the value with its two’s complement. A summary of the clear, complement and negate instructions is given in

Table 4-11

.

Table 4-11 Clear, Complement, and Negate Instructions

Mnemonic

CLC

CLI

CLR

CLRA

CLRB

CLV

COM

COMA

COMB

NEG

NEGA

NEGB

Function

Clear C bit in CCR

Clear I bit in CCR

Clear memory

Clear A

Clear B

Clear V bit in CCR

One’s complement memory

One’s complement A

One’s complement B

Two’s complement memory

Two’s complement A

Two’s complement B

Operation

0

C

0

I

$00

M

$00

A

$00

B

0

V

$FF – (M)

M or (M)

M

$FF – (A)

A or (A)

A

$FF – (B)

B or (B)

B

$00 – (M)

M or (M) + 1

M

$00 – (A)

A or (A) + 1

A

$00 – (B)

B or (B) + 1

B

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4.3.10 Multiply and Divide Instructions

The multiply instructions perform signed and unsigned, 8-bit and 16-bit multiplication. An 8-bit multiplication gives a 16-bit product. A 16-bit multiplication gives a 32-bit product.

An integer divide or fractional divide instruction has a 16-bit dividend, divisor, quotient, and remainder.

Extended divide instructions use a 32-bit dividend and a 16-bit divisor to produce a 16-bit quotient and a

16-bit remainder.

A summary of the multiply and divide instructions is given in

Table 4-12

.

Table 4-12 Multiplication and Division Instructions

Mnemonic Function

EMUL

EMULS

MUL

16 by 16 multiply (unsigned)

16 by 16 multiply (signed)

8 by 8 multiply (unsigned)

EDIV 32 by 16 divide (unsigned)

EDIVS

FDIV

IDIV

IDIVS

32 by 16 divide (signed)

16 by 16 fractional divide (unsigned)

16 by 16 integer divide (unsigned)

16 by 16 integer divide (signed)

Operation

(Y)

×

(D)

Y:D

(Y)

×

(D)

Y:D

(A)

×

(B)

A:B

(Y):(D)

÷

(X), quotient

Y, remainder

D

(Y):(D)

(D)

÷

(X), quotient

Y, remainder

D

÷

(X)

X, remainder

D

(D)

÷

(X)

X, remainder

D

(D)

÷

(X)

X, remainder

D

4.3.11 Bit Test and Bit Manipulation Instructions

These operations use a mask value to test or change the value of individual bits in an accumulator or in memory. BITA and BITB provide a convenient means of testing bits without altering the value of either operand. A summary of the bit test and bit manipulation instructions is given in

Table 4-13

.

Table 4-13 Bit Test and Bit Manipulation Instructions

Mnemonic

BCLR

BITA

BITB

BSET

Function

Clear bit(s) in memory

Bit test A

Bit test B

Set bits in memory

Operation

(M)

• mask byte

M

(A)

(M)

(B)

(M)

(M) + mask byte

M

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4.3.12 Shift and Rotate Instructions

There are shifts and rotates for accumulators and memory bytes. For multiple-byte operations, all shifts and rotates pass the shifted-out bit through the carry bit, C. Because logical and arithmetic left shifts are identical, there are no separate logical left shift operations. LSL mnemonics are assembled as ASL operations. A summary of the shift and rotate instructions is given in

Table 4-14

.

Table 4-14 Shift and Rotate Instructions

Mnemonic Function

LSL

LSLA

LSLB

Logic shift left memory

Logic shift left A

Logic shift left B

Operation

C 7 0

0

0

LSLD Logic shift left D

C 7 A 0 7 B 0

LSR

LSRA

LSRB

Logic shift right memory

Logic shift right A

Logic shift right B

0

7 0 C

0

LSRD Logic shift right D

7 A 0 7 B 0 C

ASL

ASLA

ASLB

Arithmetic shift left memory

Arithmetic shift left A

Arithmetic shift left B

C 7 0

0

0

ASLD Arithmetic shift left D

C 7 A 0 7 B 0

ASR

ASRA

ASRB

ROL

ROLA

ROLB

ROR

RORA

RORB

Arithmetic shift right memory

Arithmetic shift right A

Arithmetic shift right B

Rotate left memory

Rotate left A

Rotate left B

Rotate right memory

Rotate right A

Rotate right B

7

C

0

7

0

7

C

0

C

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4.3.13 Fuzzy Logic Instructions

The instruction set supports efficient processing of fuzzy logic operations. A summary of the fuzzy logic instructions is given in

Table 4-15

.

Table 4-15 Fuzzy Logic Instructions

Mnemonic Function

MEM

REV

REVW

WAV

Membership evaluation

MIN-MAX rule evaluation

Weighted

MIN-MAX rule evaluation

Weighted average calculation

Operation

µ

(grade)

M

(Y)

, (X) + 4

X, (Y) + 1

Y, A unchanged

If (A) < P1 or (A) > P2, then

µ

= 0, else

µ

= MIN [((A) – P1)

×

S1, (P2 – (A))

×

S2, $FF]

A contains current crisp input value.

X points to 4-byte data structure describing trapezoidal membership function as base intercept points and slopes (P1, P2, S1, S2).

Y points to fuzzy input (RAM location).

Find smallest rule input (MIN).

Store to rule outputs unless fuzzy output is larger (MAX). Rules are unweighted.

Each rule input is 8-bit offset from base address in Y.

Each rule output is 8-bit offset from base address in Y.

$FE separates rule inputs from rule outputs. $FF terminates rule list.

REV can be interrupted.

Find smallest rule input (MIN). Multiply by rule-weighting factor (optional).

Store to rule outputs unless fuzzy output is larger (MAX).

Each rule input is 16-bit address of a fuzzy input.

Each rule output is 16-bit address of fuzzy output.

Address $FFFE separates rule inputs from rule outputs. $FFFF terminates rule list.

Weights are 8-bit values in separate table.

REVW can be interrupted.

Calculate numerator (sum of products) and denominator (sum of weights).

B

S i

F i

⇒ i

B

1

F i

X

Y:D i = 1

Put results in correct CPU registers for EDIV immediately after WAV.

wavr

Return to interrupted

WAV instruction

Recover intermediate results from stack rather than initializing to zero.

4.3.14 Maximum and Minimum Instructions

4.3.14.1 Fuzzy Logic Membership Instruction

The MEM instruction is used during the fuzzification process. During fuzzification, current system input values are compared to stored input membership functions to determine the degree to which each label of each system input is true. This is accomplished by finding the y value for the current input on a trapezoidal membership function for each label of each system input. The MEM instruction performs this calculation for one label of one system input. To perform the complete fuzzification task for a system, several MEM instructions must be executed, usually in a program loop structure.

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4.3.14.2 Fuzzy Logic Rule Evaluation Instructions

The REV and REVW instructions perform MIN-MAX rule evaluations that are central elements of a fuzzy logic inference program. Fuzzy input values are processed using a list of rules from the knowledge base to produce a list of fuzzy outputs. The REV instruction treats all rules as equally important. The REVW instruction allows each rule to have a separate weighting factor. REV and REVW also differ in the way rules are encoded into the knowledge base.

Because they require a number of cycles to execute, rule evaluation instructions can be interrupted. Once the interrupt has been serviced, instruction execution resumes at the point the interrupt occurred.

4.3.14.3 Fuzzy Logic Averaging Instruction

The WAV instruction calculates weighted averages. In order to be usable, the fuzzy outputs produced by rule evaluation must be defuzzified to produce a single output value which represents the combined effect of all of the fuzzy outputs. Fuzzy outputs correspond to the labels of a system output and each is defined by a membership function in the knowledge base. The CPU typically uses singletons for output membership functions rather than the trapezoidal shapes used for inputs. As with inputs, the x-axis represents the range of possible values for a system output. Singleton membership functions consist of the x-axis position for a label of the system output. Fuzzy outputs correspond to the y-axis height of the corresponding output membership function. The WAV instruction calculates the numerator and denominator sums for a weighted average of the fuzzy outputs.

Because WAV requires a number of cycles to execute, it can be interrupted. The wavr pseudoinstruction causes execution to resume at the point where it was interrupted.

These instructions make comparisons between an accumulator and a memory location. They can be used for linear programming operations such as Simplex-method optimization or for fuzzification.

MAX and MIN instructions use accumulator A to perform 8-bit comparisons, while EMAX and EMIN instructions use accumulator D to perform 16-bit comparisons. The result (maximum or minimum value) can be stored in the accumulator or in the memory location. A summary of the minimum and maximum instructions is given in

Table 4-16

.

Table 4-16 Minimum and Maximum Instructions

Mnemonic Function

EMIND

EMINM

MINA

MINM

EMAXD

EMAXM

MAXA

MAXM

Put smaller of two unsigned 16-bit values in D

Put smaller of two unsigned 16-bit values in memory

Put smaller of two unsigned 8-bit values in A

Put smaller of two unsigned 8-bit values in memory

Put larger of two unsigned 16-bit values in D

Put larger of two unsigned 16-bit values in memory

Put larger of two unsigned 8-bit values in A

Put larger of two unsigned 8-bit values in memory

Operation

MIN [(D), (M):(M + 1)]

D

MIN [(D), (M):(M + 1)]

M:M + 1

MIN [(A), (M)]

A

MIN [(A), (M)]

M

MAX [(D), (M):(M + 1)]

D

MAX [(D), (M):(M + 1)]

M:M + 1

MAX [(A), (M)]

A

MAX[(A), (M)]

M

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4.3.15 Multiply and Accumulate Instruction

The EMACS instruction multiplies two 16-bit operands stored in memory and accumulates the 32-bit result in a third memory location. EMACS can be used to implement simple digital filters and defuzzification routines that use 16-bit operands. The WAV instruction incorporates an 8-bit to 16-bit multiply and accumulate operation that obtains a numerator for the weighted average calculation. The

EMACS instruction can automate this portion of the averaging operation when 16-bit operands are used.

A summary of the multiply and accumulate instructions is given in

Table 4-17

.

Table 4-17 Multiply and Accumulate Instruction

Mnemonic Function

EMACS

Multiply and accumulate

(signed)

16

×

16 bit

32 bit

Operation

(M

X

):(M

X + 1

)

×

(M

Y

):M

Y + 1

) + (M):(M + 1):(M + 2):(M + 3)

M:M + 1:M + 2:M + 3

4.3.16 Table Interpolation Instructions

The TBL and ETBL instructions interpolate values from tables stored in memory. Any function that can be represented as a series of linear equations can be represented by a table. Interpolation can be used for many purposes, including tabular fuzzy logic membership functions. TBL uses 8-bit table entries and returns an 8-bit result; ETBL uses 16-bit table entries and returns a 16-bit result. Indexed addressing modes provide flexibility in structuring tables.

Consider each of the successive values stored in a table as y-values for the endpoint of a line segment. The value in the B accumulator before instruction execution begins represents change in x from the beginning of the line segment to the lookup point divided by total change in x from the beginning to the end of the line segment. B is treated as an 8-bit binary fraction with radix point left of the MSB, so each line segment is effectively divided into 256 smaller segments. During instruction execution, the change in y between the beginning and end of the segment (a signed byte for TBL or a signed word for ETBL) is multiplied by the value in B to obtain an intermediate delta-y term. The result (stored in the A accumulator by TBL, in the D accumulator by ETBL) is the y-value of the beginning point plus the signed intermediate delta-y value.

A summary of the table interpolation instructions is given in

Table 4-18

.

Table 4-18 Table Interpolation Instructions

Mnemonic Function

ETBL

TBL

16-bit table lookup and interpolate

(indirect addressing not allowed)

8-bit table lookup and interpolate

(indirect addressing not allowed)

Operation

(M):(M + 1) + [(B)

×

[(M + 2):(M + 3) – (M):(M + 1)]]

D

Initialize B, and index before ETBL.

Effective address points to the first 16-bit table entry (M):(M + 1)

B is fractional part of lookup value

(M) + [(B)

×

[(M + 1) – (M)]]

A

Initialize B, and index before TBL.

Effective address points to the first 8-bit table entry (M)

B is fractional part of lookup value.

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4.3.17 Branch Instructions

A branch instruction causes a program sequence change when specific conditions exist. There are three types of branch instructions: short, long, and bit-conditional.

Branch instructions can also be classified by the type of condition that must be satisfied in order for a branch to be taken:

• Unary branch instructions are always executed

• Simple branch instructions are executed when a specific bit in the condition code register is in a specific state as a result of a previous operation

• Unsigned branch instructions are executed when a comparison or test of unsigned quantities results in a specific combination of bit states in the condition code register

• Signed branch instructions are executed when a comparison or test of signed quantities results in a specific combination of bit states in the condition code register

Some branch instructions belong to more than one type.

4.3.17.1 Short Branch Instructions

When a specified condition is met, a short branch instruction adds a signed 8-bit offset to the value in the program counter. Program execution continues at the new address. The numeric range of short branch offset values is $80 (–128) to $7F (127) from the address of the next memory location after the offset value.

A summary of the short branch instructions is given in

Table 4-19

.

Table 4-19 Short Branch Instructions

Mnemonic Type

BVC

BVS

BHI

BHS

BLO

BLS

BGE

BGT

BLE

BLT

BRA

BRN

BCC

BCS

BEQ

BMI

BNE

BPL

Unary

Simple

Unsigned

Signed

Function

Branch always

Branch never

Branch if carry clear

Branch if carry set

Branch if equal

Branch if minus

Branch if not equal

Branch if plus

Branch if overflow clear

Branch if overflow set

Branch if higher (R

>

M)

Branch if higher or same (R

M)

Branch if lower (R

<

M)

Branch if lower or same (R

M)

Branch if greater than or equal (R

M)

Branch if greater than (R

>

M)

Branch if less than or equal (R

M)

Branch if less than (R

<

M)

Condition Equation

1 = 1

1 = 0

C = 0

C = 1

Z = 1

N = 1

Z = 0

N = 0

V = 0

V = 1

C + Z = 0

C = 0

C = 1

C + Z = 1

N

V = 0

Z + (N

V) = 0

Z + (N

V) = 1

N

V = 1

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4.3.17.2 Long Branch Instructions

When a specified condition is met, a long branch instruction adds a signed 16-bit offset to the value in the program counter. Program execution continues at the new address. Long branches are used when large displacements between decision-making steps are necessary. The numeric range of long branch offset values is $8000 (–32,768) to $7FFF (32,767) from the address of the next memory location after the offset value. This permits branching from any location in the standard 64K byte address map to any other location in the map. A summary of the long branch instructions is given in

Table 4-20

.

Table 4-20 Long Branch Instructions

Mnemonic Class

LBVC

LBVS

LBHI

LBHS

LBLO

LBLS

LBGE

LBGT

LBLE

LBLT

LBRA

LBRN

LBCC

LBCS

LBEQ

LBMI

LBNE

LBPL

Unary

Simple

Unsigned

Signed

Function

Long branch always

Long branch never

Long branch if carry clear

Long branch if carry set

Long branch if equal

Long branch if minus

Long branch if not equal

Long branch if plus

Long branch if overflow clear

Long branch if overflow set

Long branch if higher (R

>

M)

Long branch if higher or same (R

M)

Long branch if lower (R

<

M)

Long branch if lower or same (R

M)

Long branch if greater than or equal (R

M)

Long branch if greater than (R

>

M)

Long branch if less than or equal (R

M)

Long branch if less than (R

<

M)

Condition Equation

1 = 1

1 = 0

C = 0

C = 1

Z = 1

N = 1

Z = 0

N = 0

V = 0

V = 1

C + Z = 0

C = 0

Z = 1

C + Z = 1

N

V = 0

Z + (N

V) = 0

Z + (N

V) = 1

N

V = 1

4.3.17.3 Bit Condition Branch Instructions

Bit condition branches are taken when bits in a memory byte are in a specific state. A mask operand is used to test the location. If all bits in that location that correspond to ones in the mask are set (BRSET) or cleared

(BRCLR), the branch is taken. The numeric range of 8-bit offset values is $80 (

128) to $7F (127) from the address of the next memory location after the offset value. A summary of the bit condition branch instructions is given in

Table 4-21

.

Table 4-21 Bit Condition Branch Instructions

Mnemonic

BRCLR

BRSET

Function

Branch if selected bits clear

Branch if selected bits set

Condition Equation

(M)

(mm) = 0

(M)

(mm) = 0

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4.3.17.4 Loop Primitive Instructions

Loop primitive instructions test a counter value in a CPU register (A, B, D, X, Y, or SP) for a zero or nonzero value as a branch condition. There are predecrement, preincrement and test-only versions of these instructions. The numeric range of 9-bit offset values is –256 to +255 from the address of the next memory location after the offset value. A summary of the loop primitive instructions is given in

Table 4-22

.

Table 4-22 Loop Primitive Instructions

Mnemonic Function

DBEQ

DBNE

IBEQ

IBNE

TBEQ

TBNE

Decrement counter and branch if zero

Decrement counter and branch if not zero

Increment counter and branch if zero

Increment counter and branch if not zero

Test counter and branch if zero

Test counter and branch if not zero

Operation

(counter) – 1

⇒ counter

If (counter) = 0, then branch, else continue to next instruction

(counter) – 1

⇒ counter

If (counter)

0, then branch, else continue to next instruction

(counter) + 1

⇒ counter

If (counter) = 0, then branch, else continue to next instruction

(counter) + 1

⇒ counter

If (counter)

0, then branch, else continue to next instruction

If (counter) = 0, then branch, else continue to next instruction

If (counter)

0, then branch, else continue to next instruction

4.3.18 Jump and Subroutine Instructions

Jump instructions cause immediate changes in program sequence. The JMP instruction loads the PC with an address in the 64K byte memory map, and program execution continues at that address. The address can be provided as an absolute 16-bit address or determined by various forms of indexed addressing.

Subroutine instructions transfer control to a code segment that performs a particular task. A short branch to subroutine (BSR), a jump to subroutine (JSR), or an expanded-memory call (CALL) can be used to initiate subroutines. There is no long branch to subroutine instruction (LBSR), but a PC-relative JSR performs the same function. A return address is stacked, then execution begins at the subroutine address.

Subroutines in the normal 64K byte address space are terminated with an RTS instruction. RTS unstacks the return address so that execution resumes with the instruction after BSR or JSR.

The CALL instruction is intended for use with expanded memory. CALL stacks the value in the PPAGE register and the return address, then writes a new value to PPAGE to select the memory page where the subroutine resides. The page value is an immediate operand in all addressing modes except indexed indirect modes; in these modes, an operand points to locations in memory where the new page value and subroutine address are stored. The RTC instruction ends subroutines in expanded memory. RTC unstacks the PPAGE value and the return address so that execution resumes with the next instruction after CALL.

For software compatibility, CALL and RTC operate correctly on devices that do not have expanded addressing capability.

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A summary of the jump and subroutine instructions is given in

Table 4-23

.

Table 4-23 Jump and Subroutine Instructions

Mnemonic Function

BSR Branch to subroutine

CALL

JMP

JSR

Call subroutine in expanded memory

Jump

Jump to subroutine

RTS

RTC

Return from subroutine

Return from call

Operation

(SP) – $0002

SP, RTN

H

:RTN

L

M

SP

:M

SP + 1

, subroutine address

PC

(SP) – $0002

SP, RTN

H

(PPAGE)

M

SP

:RTN

L

M

SP

:M

SP + 1

,(SP) – $0001

, page

PPAGE, subroutine address

PC

SP,

Subroutine address

PC

(SP) – $0002

SP, RTN

H

:RTN

L

M

SP

:M

SP + 1

, subroutine address

PC

(M

SP

)

PPAGE, (SP) + $0001

SP, (M

SP

):(M

SP + 1

(SP) + $0002

SP

)

PC

H

:PC

L

,

(M

SP

):(M

SP + 1

)

PC

H

:PC

L

, (SP) + $0002

SP

4.3.19 Interrupt Instructions

Interrupt instructions handle transfer of control to and from interrupt service routines.

The SWI instruction initiates a software interrupt. It stacks the return address and the values in the CPU registers. Then execution begins at the address pointed to by the SWI vector.

The SWI instruction causes an interrupt without an interrupt request. The global mask bits I and X in the

CCR do not inhibit SWI. SWI sets the I bit, inhibiting maskable interrupts until the I bit is cleared.

The TRAP instruction The CPU uses the software interrupt for unimplemented opcode trapping. There are opcodes in all 256 positions in the page 1 opcode map, but only 54 of the 256 positions on page 2 of the opcode map are used. If the CPU attempts to execute one of the unimplemented opcodes on page 2, an opcode trap interrupt occurs. Traps are essentially interrupts that share the $FFF8:$FFF9 interrupt vector.

The RTI instruction is used to terminate all exception handlers, including interrupt service routines. RTI first restores the CCR, B:A, X, Y, and the return address from the stack. If no other interrupt is pending, normal execution resumes with the instruction following the last instruction that executed prior to interrupt. A summary of the interrupt instructions is given in

Table 4-24

.

Table 4-24 Interrupt Instructions

Mnemonic Function

RTI

SWI

TRAP

Return from interrupt

Software interrupt

Operation

(M

SP

)

CCR, (SP) + $0001

SP

(M

(M

(M

(M

SP

SP

SP

SP

):(M

SP + 1

)

B:A, (SP) + $0002

SP

):(M

SP + 1

)

X

H

):(M

SP + 1

)

PC

H

):(M

SP + 1

)

Y

H

:X

L

, (SP) + $0004

SP

:Y

:PC

L

L

, (SP) + $0002

SP

, (SP) + $0004

SP

(SP) – $0002

(SP) – $0002

SP, RTN

SP, (Y

H

H

:RTN

):(Y

L

(SP) – $0002

SP, (X

H

):(X

L

L

M

SP

)

M

SP

)

M

SP

(SP) – $0002

SP, (B):(A)

M

SP

(SP) – $0001

SP, (CCR)

M

SP,

:M

1

:M

SP + 1

:M

SP + 1

:M

SP + 1

SP + 1

I

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4.3.20 Index Manipulation Instructions

Index manipulation instructions perform 8-bit and 16-bit operations on CPU registers or memory. A summary of the index manipulation instructions is given in

Table 4-25

.

Mnemonic Function

LEAS

LEAX

LEAY

STS

STX

STY

TFR

TSX

ABX

ABY

CPS

CPX

CPY

LDS

LDX

LDY

TSY

TXS

TYS

EXG

XGDX

XGDY

Add B to X

Add B to Y

Compare SP to memory

Compare X to memory

Compare Y to memory

Load SP from memory

Load X from memory

Load Y from memory

Load effective address into SP

Load effective address into X

Load effective address into Y

Store SP in memory

Store X in memory

Store Y in memory

Transfer registers

Transfer SP to X

Transfer SP to Y

Transfer X to SP

Transfer Y to SP

Exchange registers

Exchange D with X

Exchange D with Y

Table 4-25 Index Manipulation Instructions

Operation

(B) + (X)

X

(B) + (Y)

Y

(SP) – (M):(M + 1)

(X) – (M):(M + 1)

(Y) – (M):(M + 1)

(M):(M + 1)

SP

(M):(M + 1)

X

(M):(M + 1)

Y

Effective address

SP

Effective address

X

Effective address

Y

(SP)

M:M + 1

(X)

M:M + 1

(Y)

M:M + 1

(A, B, CCR, D, X, Y, or SP)

A, B, CCR, D, X, Y, or SP

(SP)

X

(SP)

Y

(X)

SP

(Y)

SP

(A, B, CCR, D, X, Y, or SP)

(A, B, CCR, D, X, Y, or SP)

(D)

(X)

(D)

(Y)

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4.3.21 Stacking Instructions

There are two types of stacking instructions:

• Stack pointer manipulation

• Stack operation (saving and retrieving CPU register contents)

A summary of the stacking instructions is given in

Table 4-26

.

PSHB

PSHC

PSHD

PSHX

PSHY

PULA

PULB

PULC

PULD

PULX

PULY

Mnemonic Type

CPS

DES

INS

LDS

LEAS

STS

TSX

TSY

TXS

TYS

Stack pointer manipulation

PSHA

Stack operation

Table 4-26 Stacking Instructions

Push B

Push CCR

Push D

Push X

Push Y

Pull A

Pull B

Pull CCR

Pull D

Pull X

Pull Y

Function

Compare SP to memory

Decrement SP

Increment SP

Load SP

Load effective address into SP

Store SP

Transfer SP to X

Transfer SP to Y

Transfer X to SP

Transfer Y to SP

Push A

Operation

(SP) – (M):(M + 1)

(SP) – $0001

SP

(SP) + $0001

SP

(M):(M + 1)

SP

Effective address

SP

(SP)

M:M + 1

(SP)

X

(SP)

Y

(X)

SP

(Y)

SP

(SP) – $0001

SP, (A)

M

SP

(SP) – $0001

SP, (B)

M

SP

(SP) – $0001

SP, (CCR)

M

SP

(SP) – $0002

SP, (A):(B)

M

SP

:M

SP + 1

(SP) – $0002

SP, (X)

M

SP

:M

SP + 1

(SP) – $0002

SP, (Y)

M

SP

:M

SP + 1

(M

SP

)

A, (SP) + 1

SP

(M

SP

)

B, (SP) + 1

SP

(M

SP

)

CCR, (SP) + 1

SP

(M

SP

):(M

SP + 1

)

A:B, (SP) + 2

SP

(M

SP

):(M

SP + 1

)

X, (SP) + 2

SP

(M

SP

):(M

SP + 1

)

Y, (SP) + 2

SP

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4.3.22 Load Effective Address Instructions

Load effective address instructions add a constant or the value in an accumulator to the value in an index register, the stack pointer, or the program counter. The constant can be a 5-, 8-, or 16-bit value. The accumulator can be A, B, or D. A summary of the load effective address instructions is given in

Table

4-27

.

Table 4-27 Load Effective Address Instructions

Mnemonic Function

LEAS

LEAX

LEAY

Load effective address into SP

Load effective address into X

Load effective address into Y

Operation

(X), (Y), (SP), or (PC)

±

constant

SP

(X, (Y), (SP), or (PC) + (A, B, or D)

SP

(X), (Y), (SP), or (PC)

±

constant

X

(X), (Y), (SP), or (PC) + (A, B, or D)

X

(X), (Y), (SP), or (PC)

±

constant

Y

(R) + (A), (B), or (D)

Y

4.3.23 Condition Code Instructions

A summary of the condition code instructions is given in

Table 4-28

.

Table 4-28 Condition Code Instructions

Mnemonic Function

ANDCC

CLC

CLI

CLV

ORCC

Logical AND CCR with immediate value

Clear C bit

Clear I bit

Clear V bit

Logical OR CCR with immediate value

PSHC Push CCR onto stack

PULC

SEC

SEI

SEV

TAP

TPA

Pull CCR from stack

Set C bit

Set I bit

Set V bit

Transfer A to CCR

Transfer CCR to A

Operation

(CCR)

• imm

CCR

0

C

0

I

0

V

(CCR) + imm

CCR

(SP) – $0001

SP, (CCR)

M

SP

(M

SP

)

CCR, (SP) + $0001

SP

1

C

1

I

1

V

(A)

CCR

(CCR)

A

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4.3.24 STOP and WAI Instructions

The STOP and WAI instructions put the MCU in a standby state to reduce power consumption.

The STOP instruction stacks a return address and the values in the CPU registers, then stops all system clocks, halting program execution. A reset or an external interrupt request recovers the stacked values and restarts the system clocks, and program execution resumes.

The WAI instruction stacks a return address and the values in the CPU registers, then stops the CPU clocks, halting program execution. A reset or any enabled interrupt request recovers the stacked values and restarts the CPU clocks, and program execution resumes.

Although recovery from STOP or WAI takes the same number of clock cycles, restarting after STOP requires extra time for the oscillator to reach operating speed.

A summary of the STOP and WAI instructions is given in

Table 4-29

.

Table 4-29 STOP and WAI Instructions

Mnemonic

STOP

WAI

Function

Stop

Wait for interrupt

Operation

(SP) – $0002

SP, RTN

H

:RTN

L

(SP) – $0002

SP, (Y

H

(SP) – $0002

SP, (X

H

):(Y

L

):(X

L

M

)

M

SP

)

M

SP

(SP) – $0002

SP, (B):(A)

M

SP

:M

SP + 1

:M

SP + 1

:M

SP + 1

SP

:M

SP + 1

(SP) – $0001

SP, (CCR)

M

SP

Stop all clocks

(SP) – $0002

SP, RTN

(SP) – $0002

SP, (Y

H

(SP) – $0002

SP, (X

H

H

:RTN

):(Y

):(X

L

L

)

L

(SP) – $0002

SP, (B):(A)

M

M

SP

:M

SP + 1

)

M

SP

M

SP

(SP) – $0001

SP, (CCR)

M

SP

SP

:M

:M

:M

SP + 1

SP + 1

SP + 1

Stop CPU clocks

4.3.25 Background Mode and Null Operation Instructions

Executing the BGND instruction when BDM is enabled puts the MCU in background debug mode for system development and debugging.

Null operations are often used to replace other instructions during software debugging. Replacing conditional branch instructions with BRN, for instance, permits testing a decision-making routine without actually taking the branches.

A summary of the background mode and null operation instructions is given in

Table 4-30

.

Table 4-30 Background Mode and Null Operation Instructions

Mnemonic Function

BGND

BRN

LBRN

NOP

Enter background debug mode

Branch never

Long branch never

Null operation

Operation

If BDM enabled, enter BDM, else resume normal processing

Does not branch

Does not branch

Does nothing

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4.4 High-Level Language Support

Many programmers are turning to high-level languages such as C as an alternative to coding in native assembly languages. High-level language (HLL) programming can improve productivity and produce code that is more easily maintained than assembly language programs. Historically, the most serious drawback to the use of HLL in microcontrollers has been the relatively large size of programs written in

HLL. Larger program memory space size requirements translate into increased system costs.

Motorola solicited the cooperation of third-party software developers to assure that the HCS12 instruction set would meet the needs of a more efficient generation of compilers. Several features of the HCS12 were specifically designed to improve the efficiency of compiled HLL, and thus minimize cost.

This subsection identifies HCS12 instructions and addressing modes that provide improved support for high-level language. C language examples are provided to demonstrate how these features support efficient HLL structures and concepts. Since the HCS12 instruction set is a superset of the M68HC11 instruction set, some of the discussions use the M68HC11 as a basis for comparison.

4.4.1 Data Types

The HCS12 CPU supports the bit-sized data type with bit-manipulation instructions that are available in extended, direct, and indexed variations. The char data type is a simple 8-bit value that is commonly used to specify variables in a small microcontroller system because it requires less memory space than a 16-bit integer (provided the variable has a range small enough to fit into eight bits). The 16-bit HCS12 CPU can easily handle 16-bit integer types and the set of conditional branches, including long branches, allows branching based on signed or unsigned arithmetic results. Some of the higher math functions allow for division and multiplication involving 32-bit values, although it is somewhat less common to use such long values in a microcontroller system.

Special sign-extension instructions allow easy type-casting from smaller data types to larger ones, such as from char to integer. This sign extension is automatically performed when an 8-bit value is transferred to a 16-bit register.

4.4.2 Parameters and Variables

High-level languages make extensive use of the stack, both to pass variables and for temporary and local storage. It follows that there should be easy ways to push and pull all CPU registers, that stack pointer-based indexing should be allowed, and that direct arithmetic manipulation of the stack pointer value should be allowed. The HCS12 instruction set provides for all of these needs with improved indexed addressing, the addition of an LEAS instruction, and the addition of push and pull instructions for the D accumulator and the CCR.

4.4.2.1 Register Pushes and Pulls

The M68HC11 has push and pull instructions for A, B, X, and Y, but requires separate 8-bit pushes and pulls of accumulators A and B to stack or unstack the 16-bit D accumulator (the concatenated combination

A:B). The PSHD and PULD instructions allow directly stacking the D accumulator in the expected 16-bit order.

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Adding PSHC and PULC improved orthogonality by completing the set of stacking instructions so that any of the CPU registers can be pushed or pulled. These instructions are also useful for preserving the CCR value during a function call subroutine.

4.4.2.2 Allocating and Deallocating Stack Space

The LEAS instruction can be used to allocate or deallocate space on the stack for temporary variables:

LEAS –10,S ;Allocate space for 5 16-bit integers

LEAS 10,S ;Deallocate space for 5 16-bit ints

The (de)allocation can even be combined with a register push or pull as in the following example:

LDX 8,S+ ;Load return value and deallocate

X is loaded with the 16-bit integer value at the top of the stack, and the stack pointer is adjusted up by eight to deallocate space for eight bytes’ worth of temporary storage. Postincrement indexed addressing is used in this example, but all four combinations of pre/post increment/decrement are available (offsets from –8 to +8 inclusive, from X, Y, or SP). This form of indexing can often be used to get an index or stack pointer adjustment for free during an indexed operation: the instruction requires no more code space or cycles than a zero-offset indexed instruction.

4.4.2.3 Frame Pointer

In the C language, it is common to have a frame pointer in addition to the CPU stack pointer. The frame is an area of memory within the system stack which is used for parameters and local storage of variables used within a function subroutine. The following is a description of how a frame pointer can be set up and used.

First, parameters (typically values in CPU registers) are pushed onto the system stack prior to using a JSR or CALL to get to the function subroutine. At the beginning of the called subroutine, the frame pointer of the calling program is pushed onto the stack. Typically, an index register, such as X, is used as the frame pointer, so a PSHX instruction would save the frame pointer from the calling program.

Next, the called subroutine establishes a new frame pointer by executing a TFR S,X. Space is allocated for local variables by executing an LEAS –n,S, where n is the number of bytes needed for local variables.

Notice that parameters are at positive offsets from the frame pointer while locals are at negative offsets.

In the M68HC11, the indexed addressing mode uses only positive offsets, so the frame pointer always points to the lowest address of any parameter or local. After the function subroutine finishes, calculations are required to restore the stack pointer to the midframe position between the locals and the parameters before returning to the calling program. The HCS12 CPU requires only the execution of TFR X,S to deallocate the local storage and return.

The concept of a frame pointer is supported in the HCS12 through a combination of improved indexed addressing, universal transfer/exchange, and the LEA instruction. These instructions work together to achieve more efficient handling of frame pointers. It is important to consider the complete instruction set as a complex system with subtle interrelationships rather than simply examining individual instructions when trying to improve an instruction set. Adding or removing a single instruction can have unexpected consequences.

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4.4.3 Increment and Decrement Operators

In C, the notation

+ + i or i – – is often used to form loop counters. Within limited constraints, the HCS12 loop primitives can speed up the loop-count-and-branch function.

The HCS12 includes a set of six basic loop-control instructions that decrement, increment, or test a loop-count register and then branch if the register is either equal to zero or not equal to zero. The loop-count register can be A, B, D, X, Y, or SP. A or B could be used if the loop count fits in an 8-bit char variable; the other choices are all 16-bit registers. The relative offset for the loop branch is a 9-bit signed value, so these instructions can be used with loops as long as 256 bytes.

In some cases, the pre- or postincrement operation can be combined with an indexed instruction to eliminate the cost of the increment operation. This is typically done by postcompile optimization because the indexed instruction that could absorb the increment/decrement operation may not be apparent at compile time.

4.4.4 Higher Math Functions

In the HCS12 CPU, subtle characteristics of higher math operations such as IDIVS and EMUL are arranged so a compiler can handle inputs and outputs more efficiently.

The most apparent case is the IDIVS instruction, which divides two 16-bit signed numbers to produce a

16-bit result. While the same function can be accomplished with the EDIVS instruction (a 32 by 16 divide), doing so is much less efficient because extra steps are required to prepare inputs to the EDIVS, and because EDIVS uses the Y index register. EDIVS uses a 32-bit signed numerator and the C compiler would typically want to use a 16-bit value (the size of an integer data type). The 16-bit C value would need to be sign-extended into the upper 16-bits of the 32-bit EDIVS numerator before the divide operation.

Operand size is also a potential problem in the extended multiply operations but the difficulty can be minimized by putting the results in CPU registers. Having higher-precision math instructions is not necessarily a requirement for supporting high-level language because these functions can be performed as library functions. However, if an application requires these functions, the code is much more efficient if the CPU can use native instructions instead of relatively large, slow routines.

4.4.5 Conditional If Constructs

In the HCS12 instruction set, most arithmetic and data manipulation instructions automatically update the condition code register, unlike other architectures that only change condition codes during a few specific compare instructions. The HCS12 includes branch instructions that perform conditional branching based on the state of the indicators in the condition code register. Short branches use a single byte-relative offset that allows branching to a destination within about

±

128 locations from the branch. Long branches use a

16-bit relative offset that allows conditional branching to any location in the 64K byte map.

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4.4.6 Case and Switch Statements

Case and switch statements (and computed GOTOs) can use PC-relative indexed-indirect addressing to determine which path to take. Depending upon the situation, cases can use either the constant offset variation or the accumulator D offset variation of indexed-indirect addressing.

4.4.7 Pointers

The HCS12 supports pointers with direct arithmetic operations on the 16-bit index registers (LEAS,

LEAX, and LEAY instructions) and with indexed-indirect addressing modes.

4.4.8 Function Calls

Bank switching is a common way of adapting a CPU with a 16-bit address bus to accommodate more than

64K bytes of program memory space. One of the most significant drawbacks of this technique is the requirement of masking interrupts while the bank page value is being changed. Another problem is that the physical location of the bank page register can change from one system to another or even due to a change to mapping controls by a user program. In these situations, an operating system program has to keep track of the physical location of the page register. The HCS12 addresses both of these problems with the uninterruptible CALL and return from call (RTC) instructions.

The CALL instruction is similar to a JSR instruction, except that the programmer supplies a destination page value as part of the instruction. When CALL executes, the old page value is saved on the stack and the new page value is written to the bank page register. Since the CALL instruction is uninterruptible, this eliminates the need to separately mask off interrupts during the context switch.

The HCS12 has dedicated signal lines that allow the CPU to access the bank page register without having to use an address in the normal 64K byte address space. This eliminates the need for the program to know where the page register is physically located.

The RTC instruction is similar to the RTS instruction, except that RTC uses the byte of information that was saved on the stack by the corresponding CALL instruction to restore the bank page register to its old value. A CALL/RTC pair can be used to access any function subroutine on any page. But when the called subroutine is on the current page or in an area of memory that is always visible, it is more efficient to access it with JSR/RTS instructions.

Push and pull instructions can be used to stack some or all the CPU registers during a function call. The

HCS12 CPU can push and pull any of the CPU registers A, B, D, CCR, X, Y, or SP.

4.4.9 Instruction Set Orthogonality

One very helpful aspect of the HCS12 instruction set, orthogonality, is difficult to quantify in terms of direct benefit to an HLL compiler. Orthogonality refers to the regularity of the instruction set. A completely orthogonal instruction set would allow any instruction to operate in any addressing mode, would have identical code sizes and execution times for similar operations, and would include both signed and unsigned versions of all mathematical instructions. Greater regularity of the instruction set makes it

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possible to implement compilers more efficiently because operation is more consistent, and fewer special cases must be handled.

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98

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4.6 Transfer and Exchange Postbyte Encoding

0

1

2

LS MS

A

A

A

0

A

B

CCR B

B

B

1

A

B

CCR

CCR

CCR

CCR

2

A

B

CCR

Transfers

3

TMP3

TMP3

TMP3

L

L

L

A

B

CCR B

B

B

4

A

B

CCR

5

X

L

A

X

L

B

X

L

CCR Y

L

Y

L

Y

L

6

A

B

CCR

SP

L

SP

L

SP

L

7

A

B

CCR

3

4

5

6

7

LS MS

0

1

2

3

4

5

6

7 sex:A

TMP2 sex:B

TMP2 sex:CCR

TMP2 TMP3

TMP2 sex:A

D

SEX A,D sex:A

X

SEX A,X sex:A

Y

SEX A,Y sex:A

SP

SEX A,SP sex:B sex:B sex:B sex:B

D

SEX B,D

X

SEX B,X

Y

SEX B,Y

SP

SEX B,SP sex:CCR

D

SEX CCR,D sex:CCR

X

SEX CCR,X sex:CCR

Y

SEX CCR,Y sex:CCR

SP

SEX CCR,SP

TMP3

TMP3

TMP3

TMP3

D

X

Y

SP

A

A

A

8

A

B

CCR B

B

B

9

A

B

CCR

CCR

CCR

CCR

A

A

B

CCR

D

D

D

D

D

TMP2

D

X

Y

SP

X

X

X

X

X

TMP2

D

X

Y

SP

Y

Y

Y

Y

Y

TMP2

D

X

Y

SP

SP

SP

SP

SP

SP

TMP2

D

X

Y

SP

Exchanges

B

TMP3

L

A

$00:A

TMP3

TMP3

L

B

$FF:B

TMP3

TMP3

L

CCR

$FF:CCR

TMP3

C D

B

A

A

B

B

B

$FF

A

B

CCR

$FF:CCR

D

X

L

A

$00:A

X

X

L

B

$FF:B

X

X

L

CCR

$FF:CCR

X

E

Y

L

A

$00:A

Y

Y

L

B

$FF:B

Y

Y

L

CCR

$FF:CCR

Y

F

SP

L

A

$00:A

SP

SP

L

B

$FF:B

SP

SP

L

CCR

$FF:CCR

SP

$00:A

TMP2

TMP2

L

A

$00:B

TMP2

TMP2

L

B

$00:A

X

A

D

$00:A

Y

Y

A

$00:A

SP

L

L

L

$00:A

X

SP

A

$00:B

$00:B

X

X

Y

SP

L

$00:B

Y

L

$00:B

L

B

B

SP

B

D

$00:CCR

TMP2

TMP2

L

CCR

$00:CCR

D

B

CCR

$00:CCR

X

X

L

CCR

$00:CCR

Y

Y

L

CCR

$00:CCR

SP

SP

L

CCR

TMP3

TMP3

TMP3

TMP3

TMP3

TMP2

D

X

Y

SP

D

D

D

D

D

TMP2

D

X

Y

SP

X

X

X

X

X

TMP2

D

X

Y

SP

Y

Y

Y

Y

Y

TMP2

D

X

Y

SP

SP

SP

SP

SP

SP

TMP2

D

X

Y

SP

TMP2 and TMP3 registers are for factory use only.

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4.7 Loop Primitive Postbyte (lb) Encoding

00

DBEQ

A

(+)

01

DBEQ

B

(+)

02

10

DBEQ

A

(–)

11

DBEQ

B

(–)

12

20

DBNE

A

(+)

21

DBNE

B

(+)

22

30

DBNE

A

(–)

31

DBNE

B

(–)

32

40

TBEQ

A

(+)

41

TBEQ

B

(+)

42

50

TBEQ

A

(–)

51

TBEQ

B

(–)

52

60

TBNE

(+)

A

61

TBNE

(+)

B

62

70

TBNE

(–)

A

71

TBNE

(–)

B

72

80

IBEQ

(+)

81

IBEQ

(+)

82

A

B

90

IBEQ

(–)

91

IBEQ

(–)

92

A

B

A0

IBNE

(+)

A1

IBNE

(+)

A2

A

B

B0

IBNE

(–)

B1

IBNE

(–)

B2

A

B

03

13

23

33

43

53

63

73

83

93

A3

B3

04

DBEQ

D

(+)

05

DBEQ

X

(+)

06

DBEQ

Y

(+)

07

DBEQ

SP

(+)

14

DBEQ

D

(–)

15

DBEQ

X

(–)

16

DBEQ

Y

(–)

17

DBEQ

SP

(–)

24

DBNE

D

(+)

25

DBNE

X

(+)

26

DBNE

Y

(+)

27

DBNE

SP

(+)

34

DBNE

D

(–)

35

DBNE

X

(–)

36

DBNE

Y

(–)

37

DBNE

SP

(–)

44

TBEQ

D

(+)

45

TBEQ

X

(+)

46

TBEQ

Y

(+)

47

TBEQ

SP

(+)

54

TBEQ

D

(–)

55

TBEQ

X

(–)

56

TBEQ

Y

(–)

57

TBEQ

SP

(–)

64

TBNE

(+)

D

65

TBNE

X

(+)

66

TBNE

Y

(+)

67

TBNE

SP

(+)

74

TBNE

(–)

D

75

TBNE

X

(–)

76

TBNE

Y

(–)

77

TBNE

SP

(–)

84

IBEQ

(+)

85

IBEQ

(+)

86

IBEQ

D

X

Y

(+)

87

IBEQ

SP

(+)

94

IBEQ

(–)

95

IBEQ

(–)

96

IBEQ

D

X

Y

(–)

97

IBEQ

SP

(–)

A4

IBNE

(+)

A5

IBNE

(+)

A6

IBNE

D

X

Y

(+)

A7

IBNE

SP

(+)

B4

IBNE

(–)

B5

IBNE

(–)

B6

IBNE

D

X

Y

(–)

B7

IBNE

SP

(–)

Hex postbyte (bit 3 is don’t care)

Mnemonic

00

DBEQ

(+)

A

Counter

Sign of 9-bit relative branch offset

(lower eight bits are an extension byte following postbyte)

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Section 5 Instruction Execution

The CPU uses a three-stage instruction queue to facilitate instruction fetching and increase execution speed. This section provides a general description of the instruction queue during normal program execution and during changes in execution flow. Operation of the queue is automatic and generally transparent to the user.

5.1 Normal Instruction Execution

Queue logic prefetches program information and positions it for sequential execution, one instruction at a time. The relationship between bus cycles and execution cycles is straightforward and facilitates tracking and debugging.

There are three 16-bit stages in the instruction queue. Instructions enter the queue at stage1 and roll out after stage 3. Each byte in the queue is selectable. An opcode-prediction algorithm determines the location of the next opcode in the instruction queue.

Each instruction refills the queue by fetching the same number of bytes that the instruction uses. Program information is fetched in aligned 16-bit words. Each program fetch indicates that two bytes need to be replaced in the instruction queue. Each optional fetch indicates that only one byte needs to be replaced.

For example, an instruction composed of five bytes does two program fetches and one optional fetch. If the first byte of the five-byte instruction was even-aligned, the optional fetch is converted into a free cycle.

If the first byte was odd-aligned, the optional fetch is executed as a program fetch.

Two external pins, IPIPE[1:0], provide time-multiplexed information about instruction execution and data movement in the queue. Decoding and using the IPIPE signals is discussed in.

5.2 Execution Sequence

All queue operations are defined by two basic queue movement cycles. Queue movement cycles are only one factor in instruction execution time and should not be confused with bus cycles.

5.2.1 No Movement

There is no data movement in the instruction queue during the cycle. This occurs during execution of instructions that must perform a number of internal operations, such as division instructions.

5.2.2 Advance and Load from Data Bus

The content of queue stage 1 advances to stage 2, stage 2 advances to stage 3, and stage 1 is loaded with a word of program information from the data bus.

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5.3 Changes of Flow

Most of the time, the instruction queue operates in a continuous sequence of queue movement cycles.

When program flow changes because of an exception, subroutine call, branch, or jump, the queue automatically adjusts its movement sequence to accommodate the change in program flow.

5.3.1 Exceptions

Exceptions include three types of reset, an unimplemented opcode trap, a software interrupt instruction, X bit maskable interrupts, and I bit maskable interrupts.

To minimize the effect of queue operation on exception handling:

• The exception vector fetch is the first part of exception processing.

• Fetches to refill the queue from the new address are interleaved with the context-stacking operations, so that program access time does not delay the switch.

Please see

Section 6

of this guide for more detailed information on exception processing.

5.3.2 Subroutines

The CPU can branch to (BSR), jump to (JSR), or CALL subroutines. The BSR and JSR instructions are for accessing subroutines in the normal 64K byte address space. The CALL instruction is for accessing subroutines in expanded memory.

BSR uses relative addressing mode to generate the effective address of the subroutine, while JSR can use other addressing modes. Both instructions calculate a return address, stack the address, then do three program word fetches to refill the queue.

A subroutine in the normal 64K byte address space ends with a return from subroutine instruction (RTS).

RTS unstacks the return address and does three program word fetches from that address to refill the queue.

CALL is similar to JSR. MCUs with expanded memory treat the 16K bytes of addresses from $8000 to

$BFFF as an expanded memory window. An 8-bit PPAGE register switches the memory pages in the window. CALL calculates and stacks a return address along with the current PPAGE value and writes a new instruction-supplied value to PPAGE. Then it calculates the subroutine address and fetches three program words from that address to refill the queue.

A subroutine in expanded memory ends with a return from call instruction (RTC). RTC unstacks the

PPAGE value and the return address and does three program word fetches from that address to refill the queue.

5.3.3 Branches

A branch instruction changes the execution flow when a specific condition exists. There are short conditional branches, long conditional branches, and bit-condition branches. All branch instructions affect the queue similarly, but there are differences in cycle counts between the various types. Loop primitive instructions are a special type of branch instruction for implementing counter-based loops.

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A branch instruction has two execution cases. Either the branch condition is satisfied, and a change of flow takes place, or the condition is not satisfied, and no change of flow occurs.

5.3.3.1 Short Branches

The branch-not-taken case for a short branch is simple. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the queue advances, the CPU fetches another program word, and execution continues with the next instruction.

The branch-taken case for a short branch requires that the queue be refilled so that execution can begin at a new address. First, the CPU calculates the effective address of the destination using the relative offset in the instruction. Then it loads the address into the program counter, and performs three program word fetches at the new address to refill the queue.

5.3.3.2 Long Branches

The branch-not-taken case for a long branch requires three cycles, while the branch-taken case requires four cycles. This is due to differences in the amount of program information needed to fill the queue.

A long branch instruction begins with a $18 prebyte which indicates that the opcode is on page 2 of the opcode map. The CPU treats the prebyte as a special one-byte instruction. To maintain alignment in the two-byte queue, the first cycle of a long branch instruction is an optional cycle. If the prebyte is not aligned, the CPU does a program word access; if the prebyte is aligned, the first cycle is a free cycle.

Optional cycles align byte-sized and misaligned instructions with aligned word-length instructions.

Program information is always fetched as aligned 16-bit words. When an instruction has an odd number of bytes, and the first byte is not aligned with an even byte boundary, the optional cycle makes an additional program word access that maintains queue order. In all other cases, the optional cycle is a free cycle. In the branch-not-taken case, the queue advances so that execution can continue with the next instruction. The CPU does one program fetch and one optional fetch to refill the queue.

In the branch-taken case, the CPU calculates the effective address of the branch using the 16-bit relative offset contained in the second word of the instruction. It loads the address into the program counter and then does three program word fetches at the new address to refill the queue.

5.3.3.3 Bit Condition Branches

A bit-condition branch instruction reads a location in memory and branches if the bits in that location are in a certain state. It can use direct, extended, or indexed addressing mode. Indexed operations require varying amounts of information to determine the effective address, so instruction length varies with the addressing mode. The amount of program information fetched also varies with instruction length. To shorten execution time, the CPU does one program word fetch in anticipation of the branch-taken case.

The data from this fetch is ignored if the branch is not taken, and the CPU refills the queue according to the instruction length. If the branch is taken, the CPU refills the queue from the new address according to the instruction length.

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5.3.3.4 Loop Primitive Instructions

A loop primitive instruction tests a counter value in a register or accumulator. If the test condition is met, the CPU branches to an address specified by a 9-bit relative offset contained in the instruction. There are autoincrement and autodecrement versions of the instructions. The test and increment/decrement operations are performed on internal CPU registers, and require no additional program information. To shorten execution time, the CPU does one program word fetch in anticipation of the branch-taken case.

The data from this fetch is ignored if the branch is not taken, and the CPU does one program fetch and one optional fetch to refill the queue. If the branch is taken, the CPU refills the queue with two additional program word fetches at the new address.

5.3.4 Jumps

JMP is the simplest change-of-flow instruction. JMP can use extended or indexed addressing. Indexed operations require varying amounts of information to determine the effective address, so instruction length varies with the addressing mode. The amount of program information fetched also varies with instruction length. In all forms of JMP, the CPU refills the queue with three program word fetches at the new address.

5.4 Instruction Timing

The Access Detail column of the summary in

Table 5-1

shows how many bytes of information the CPU accesses while executing an instruction. With this information and knowledge of the type and speed of memory in the system, you can determine the execution time for any instruction in any system. Simply count the code letters to determine the execution time of an instruction in a best-case system. An example of a best-case system is a single-chip 16-bit system with no 16-bit off-boundary data accesses to any locations other than on-chip RAM.

A description of the notation used in each column of the table is given in the subsections that follow including that of the Access Detail column. This information as well as the summary in

Table 5-1

is

repeated from

Section 1

of this guide for completeness.

Source Form

ABA

ABXSame as LEAX B,X

ABYSame as LEAY B,Y

ADCA # opr8i

ADCA opr8a

ADCA opr16a

ADCA oprx0_xysppc

ADCA oprx9,xysppc

ADCA oprx16,xysppc

ADCA [D, xysppc]

ADCA [ oprx16,xysppc]

Table 5-1 Instruction Set Summary

Operation

Add B to A; (A)+(B)

A

Add B to X; (X)+(B)

X

Add B to Y; (Y)+(B)

Y

Add with carry to A; (A)+(M)+C

A or (A)+imm+C

A

Address

Mode

INH

Machine

Coding (Hex)

18 06

IDX

IDX

1A E5

19 ED

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

89 ii

99 dd

B9 hh ll

A9 xb

A9 xb ff

A9 xb ee ff

A9 xb

A9 xb ee ff

OO

Pf

Access Detail

Pf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– –

∆ ∆ ∆ ∆

– – – – – – – –

– – – – – – – –

– –

∆ ∆ ∆ ∆

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Source Form

ADCB # opr8i

ADCB opr8a

ADCB opr16a

ADCB oprx0_xysppc

ADCB oprx9,xysppc

ADCB oprx16,xysppc

ADCB [D, xysppc]

ADCB [ oprx16,xysppc]

ADDA # opr8i

ADDA opr8a

ADDA opr16a

ADDA oprx0_xysppc

ADDA oprx9,xysppc

ADDA oprx16,xysppc

ADDA [D, xysppc]

ADDA [ oprx16,xysppc]

ADDB # opr8i

ADDB opr8a

ADDB opr16a

ADDB oprx0_xysppc

ADDB oprx9,xysppc

ADDB oprx16,xysppc

ADDB [D, xysppc]

ADDB [ oprx16,xysppc]

ADDD # opr16i

ADDD opr8a

ADDD opr16a

ADDD oprx0_xysppc

ADDD oprx9,xysppc

ADDD oprx16,xysppc

ADDD [D, xysppc]

ADDD [ oprx16,xysppc]

ANDA # opr8i

ANDA opr8a

ANDA opr16a

ANDA oprx0_xysppc

ANDA oprx9,xysppc

ANDA oprx16,xysppc

ANDA [D, xysppc]

ANDA [ oprx16,xysppc]

ANDB # opr8i

ANDB opr8a

ANDB opr16a

ANDB oprx0_xysppc

ANDB oprx9,xysppc

ANDB oprx16,xysppc

ANDB [D, xysppc]

ANDB [ oprx16,xysppc]

ANDCC # opr8i

ASL opr16aSame as LSL

ASL oprx0_xysp

ASL oprx9,xysppc

ASL oprx16,xysppc

ASL [D, xysppc]

ASL [ oprx16,xysppc]

ASLASame as LSLA

ASLBSame as LSLB

ASLDSame as LSLD

Operation

Add with carry to B; (B)+(M)+C

B or (B)+imm+C

B

Add to A; (A)+(M) or (A)+imm

Add to B; (B)+(M) or (B)+imm or (B)

• imm

B

Add to D; (A:B)+(M:M+1) or (A:B)+imm

AND with A; (A) or (A)

• imm

A

A

AND with B; (B)

B

A:B

(M)

(M)

A

B

A

B

AND with CCR; (CCR)

• imm

CCR

Arithmetic shift left M

C b7 b0

0

A:B

Arithmetic shift left A

Arithmetic shift left B

Arithmetic shift left D

C b7

• • •

A b0 b7

• • •

B b0

0

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Coding (Hex)

C9 ii

D9 dd

F9 hh ll

E9 xb

E9 xb ff

E9 xb ee ff

E9 xb

E9 xb ee ff

C3 jj kk

D3 dd

F3 hh ll

E3 xb

E3 xb ff

E3 xb ee ff

E3 xb

E3 xb ee ff

84 ii

94 dd

B4 hh ll

A4 xb

A4 xb ff

A4 xb ee ff

A4 xb

A4 xb ee ff

8B ii

9B dd

BB hh ll

AB xb

AB xb ff

AB xb ee ff

AB xb

AB xb ee ff

CB ii

DB dd

FB hh ll

EB xb

EB xb ff

EB xb ee ff

EB xb

EB xb ee ff

C4 ii

D4 dd

F4 hh ll

E4 xb

E4 xb ff

E4 xb ee ff

E4 xb

E4 xb ee ff

10 ii

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

48

58

59

Access Detail

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

S X H I N Z V C

– –

∆ ∆ ∆ ∆

– –

∆ ∆ ∆ ∆

– –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

ASR opr16a

ASR oprx0_xysppc

ASR oprx9,xysppc

ASR oprx16,xysppc

ASR [D, xysppc]

ASR [ oprx16,xysppc]

ASRA

ASRB

BCC rel8Same as BHS

BCLR opr8a, msk8

BCLR opr16a, msk8

BCLR oprx0_xysppc, msk8

BCLR oprx9,xysppc, msk8

BCLR oprx16,xysppc, msk8

BCS rel8Same as BLO

BEQ rel8

BGE rel8

BGND

BGT rel8

BHI rel8

BHS rel8Same as BCC

BITA # opr8i

BITA opr8a

BITA opr16a

BITA oprx0_xysppc

BITA oprx9,xysppc

BITA oprx16,xysppc

BITA [D, xysppc]

BITA [ oprx16,xysppc]

BITB # opr8i

BITB opr8a

BITB opr16a

BITB oprx0_xysppc

BITB oprx9,xysppc

BITB oprx16,xysppc

BITB [D, xysppc]

BITB [ oprx16,xysppc]

BLE rel8

BLO rel8Same as BCS

BLS rel8

BLT rel8

BMI rel8

BNE rel8

BPL rel8

BRA rel8 b7

Operation

Arithmetic shift right M b0 C

Arithmetic shift right A

Arithmetic shift right B

Branch if C clear; if C=0, then

(PC)+2+rel

PC

REL

Clear bit(s) in M; (M)

• mask byte

M

DIR

EXT

IDX

IDX1

IDX2

REL Branch if C set; if C=1, then

(PC)+2+rel

PC

Branch if equal; if Z=1, then

(PC)+2+rel

PC

Branch if

0, signed; if N

V=0, then

(PC)+2+rel

PC

Enter background debug mode

Branch if

>

0, signed; if Z | (N

V)=0, then (PC)+2+rel

PC

Branch if higher, unsigned; if

C | Z=0, then (PC)+2+rel

PC

Branchifhigherorsame,unsigned;if

C=0,then(PC)+2+rel

PC

Bit test A; (A)

(M) or (A)

• imm

REL

REL

INH

REL

REL

REL

Bit test B; (B) or (B)

• imm

(M)

Branch if

0,signed; if Z | (N

V)=1, then (PC)+2+rel

PC

Branch if lower, unsigned; if C=1, then (PC)+2+rel

PC

Branch if lower or same, unsigned; if

C | Z=1, then (PC)+2+rel

PC

Branch if

<

0, signed; if N

V=1, then

(PC)+2+rel

PC

Branch if minus; if N=1, then

(PC)+2+rel

PC

Branch if not equal to 0; if Z=0, then

(PC)+2+rel

PC

Branch if plus; if N=0, then

(PC)+2+rel

PC

Branch always

REL

REL

REL

REL

REL

REL

REL

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

REL

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

Machine

Coding (Hex)

77 hh ll

67 xb

67 xb ff

67 xb ee ff

67 xb

67 xb ee ff

47

57

24 rr

4D dd mm

1D hh ll mm

0D xb mm

0D xb ff mm

0D xb ee ff mm

25 rr

27 rr

2C rr

00

2E rr

22 rr

24 rr

85 ii

95 dd

B5 hh ll

A5 xb

A5 xb ff

A5 xb ee ff

A5 xb

A5 xb ee ff

C5 ii

D5 dd

F5 hh ll

E5 xb

E5 xb ff

E5 xb ee ff

E5 xb

E5 xb ee ff

2F rr

25 rr

23 rr

2D rr

2B rr

26 rr

2A rr

20 rr

Access Detail

rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

PPP

(branch)

P

(no branch) rPwO rPwP rPwO rPwP frPwPO

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

VfPPP

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch)

PPP

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

For More Information On This Product,

Go to: www.freescale.com

CALL opr16a, page

CALL oprx0_xysppc, page

CALL oprx9,xysppc, page

CALL oprx16,xysppc, page

CALL [D, xysppc]

CALL [ oprx16, xysppc]

CBA

CLCSame as ANDCC #$FE

CLISame as ANDCC #$EF

CLR opr16a

CLR oprx0_xysppc

CLR oprx9,xysppc

CLR oprx16,xysppc

CLR [D, xysppc]

CLR [ oprx16,xysppc]

CLRA

CLRB

CLVSame as ANDCC #$FD

CMPA # opr8i

CMPA opr8a

CMPA opr16a

CMPA oprx0_xysppc

CMPA oprx9,xysppc

CMPA oprx16,xysppc

CMPA [D, xysppc]

CMPA [ oprx16,xysppc]

CMPB # opr8i

CMPB opr8a

CMPB opr16a

CMPB oprx0_xysppc

CMPB oprx9,xysppc

CMPB oprx16,xysppc

CMPB [D, xysppc]

CMPB [ oprx16,xysppc]

Source Form

BRCLR opr8a, msk8, rel8

BRCLR opr16a, msk8, rel8

BRCLR oprx0_xysppc, msk8, rel8

BRCLR oprx9,xysppc, msk8, rel8

BRCLR oprx16,xysppc, msk8, rel8

BRN rel8

BRSET opr8, msk8, rel8

BRSET opr16a, msk8, rel8

BRSET oprx0_xysppc, msk8, rel8

BRSET oprx9,xysppc, msk8, rel8

BRSET oprx16,xysppc, msk8, rel8

BSET opr8, msk8

BSET opr16a, msk8

BSET oprx0_xysppc, msk8

BSET oprx9,xysppc, msk8

BSET oprx16,xysppc, msk8

BSR rel8

BVC

BVS rel8 rel8

Set bit(s) in M

Operation

Branch if bit(s) clear; if

(M)

(mask byte)=0, then

(PC)+2+rel

PC

Branch never

Branch if bit(s) set; if

(M)

(mask byte)=0, then

(PC)+2+rel

PC

(M) | mask byte

M

Branch to subroutine; (SP)–2

SP

RTN

H

:RTN

L

M

(PC)+2+rel

PC

SP

:M

SP+1

Branch if V clear; if V=0, then

(PC)+2+rel

PC

Branch if V set; if V=1, then

(PC)+2+rel

PC

Call subroutine in expanded memory

(SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

SP+1

(SP)–1

SP; (PPG)

M

SP pg

PPAGE register subroutine address

PC

Compare A to B; (A)–(B)

Clear C bit

Clear I bit

Clear M; $00

M

Clear A; $00

Clear B; $00

Clear V

Compare A

A

B

(A)–(M) or (A)–imm

Compare B

(B)–(M) or (B)–imm

REL

REL

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

IMM

IMM

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IMM

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

DIR

EXT

IDX

IDX1

IDX2

REL

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

Machine

Coding (Hex)

Access Detail

4F dd mm rr

1F hh ll mm rr

0F xb mm rr

0F xb ff mm rr

0F xb ee ff mm rr rPPP rfPPP rPPP rfPPP

PrfPPP

REL

21 rr P

4E dd mm rr

1E hh ll mm rr

0E xb mm rr

0E xb ff mm rr

0E xb ee ff mm rr

4C dd mm

1C hh ll mm

0C xb mm

0C xb ff mm

0C xb ee ff mm

07 rr rPPP rfPPP rPPP rfPPP

PrfPPP rPwO rPwP rPwO rPwP frPwPO

SPPP

28 rr

29 rr

4A hh ll pg

4B xb pg

4B xb ff pg

4B xb ee ff pg

4B xb

4B xb ee ff

18 17

10 FE

10 EF

79 hh ll

69 xb

69 xb ff

69 xb ee ff

69 xb

69 xb ee ff

87

C7

10 FD

81 ii

91 dd

B1 hh ll

A1 xb

A1 xb ff

A1 xb ee ff

A1 xb

A1 xb ee ff

C1 ii

D1 dd

F1 hh ll

E1 xb

E1 xb ff

E1 xb ee ff

E1 xb

E1 xb ee ff

P

P

PwO

Pw

PwO

PwP

PIfw

PIPw

O

O

P

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PPP

(branch)

P

(no branch)

PPP

(branch)

P

(no branch) gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP

OO

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – – – – – 0

– – – 0 – – – –

– – – – 0 1 0 0

– – – – – – 0 –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

COM opr16a

COM oprx0_xysppc

COM oprx9,xysppc

COM oprx16,xysppc

COM [D, xysppc]

COM [ oprx16,xysppc]

COMA

COMB

CPD # opr16i

CPD opr8a

CPD opr16a

CPD oprx0_xysppc

CPD oprx9,xysppc

CPD oprx16,xysppc

CPD [D, xysppc]

CPD [ oprx16,xysppc]

CPS # opr16i

CPS opr8a

CPS opr16a

CPS oprx0_xysppc

CPS oprx9,xysppc

CPS oprx16,xysppc

CPS [D, xysppc]

CPS [ oprx16,xysppc]

CPX # opr16i

CPX opr8a

CPX opr16a

CPX oprx0_xysppc

CPX oprx9,xysppc

CPX oprx16,xysppc

CPX [D, xysppc]

CPX [ oprx16,xysppc]

CPY # opr16i

CPY opr8a

CPY opr16a

CPY oprx0_xysppc

CPY oprx9,xysppc

CPY oprx16,xysppc

CPY [D, xysppc]

CPY [ oprx16,xysppc]

DAA

DBEQ abdxysp, rel9

DBNE abdxysp, rel9

DEC opr16a

DEC oprx0_xysppc

DEC oprx9,xysppc

DEC oprx16,xysppc

DEC [D, xysppc]

DEC [ oprx16,xysppc]

DECA

DECB

DESSame as LEAS –1,SP

DEX

DEY

EDIV

Compare D or (A:B)–imm

Compare SP or (SP)–imm

Compare X

(X)–(M:M+1) or (X)–imm

Compare Y

(Y)–(M:M+1) or (Y)–imm

Operation

Complement M; (M)=$FF–(M)

Complement A; (A)=$FF–(A)

Complement B; (B)=$FF–(B)

(A:B)–(M:M+1)

(SP)–(M:M+1)

Decimal adjust A for BCD

A

B

M

Decrement and branch if equal to 0

(counter)–1

⇒ counter if (counter)=0, then branch

REL

(9-bit)

Decrement and branch if not equal to 0;

(counter)–1

⇒ counter; if (counter)

0, then branch

Decrement M; (M)–1

M

REL

(9-bit)

Decrement A; (A)–1

Decrement B; (B)–1

A

B

Decrement SP; (SP)–1

SP

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IDX

Decrement X; (X)–1

X

Decrement Y; (Y)–1

Y

INH

INH

Extended divide, unsigned; 32 by 16 to 16-bit; (Y:D)

÷

(X)

Y; remainder

D

INH

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

Machine

Coding (Hex)

71 hh ll

61 xb

61 xb ff

61 xb ee ff

61 xb

61 xb ee ff

41

51

8C jj kk

9C dd

BC hh ll

AC xb

AC xb ff

AC xb ee ff

AC xb

AC xb ee ff

8F jj kk

9F dd

BF hh ll

AF xb

AF xb ff

AF xb ee ff

AF xb

AF xb ee ff

8E jj kk

9E dd

BE hh ll

AE xb

AE xb ff

AE xb ee ff

AE xb

AE xb ee ff

8D jj kk

9D dd

BD hh ll

AD xb

AD xb ff

AD xb ee ff

AD xb

AD xb ee ff

18 07

04 lb rr

04 lb rr

73 hh ll

63 xb

63 xb ff

63 xb ee ff

63 xb

63 xb ee ff

43

53

1B 9F

09

03

11

PPP

(branch)

PPO

(no branch)

Access Detail

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

OfO

PPP

(branch)

PPO

(no branch)

O

O rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

Pf ffffffffffO

S X H I N Z V C

– – – –

∆ ∆

0 1

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

?

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆

– – – – – – – –

– – – – –

– –

– – – – –

– –

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

EDIVS

EMACS

EMAXD

EMAXD

EMAXD

EMIND [

Source Form

opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMAXD [D,

EMAXD [

EMAXM

EMAXM

EMAXM oprx16,xysppc] oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMAXM [D,

EMAXM [

EMIND

EMIND

EMIND

EMIND [D, xysppc] xysppc] oprx16,xysppc] oprx0_xysppc oprx9,xysppc oprx16,xysppc xysppc] oprx16,xysppc]

Operation

Address

Mode

Machine

Coding (Hex)

Extended divide,signed; 32 by 16 to

16-bit; (Y:D)

÷

(X)

Y remainder

D

Extended multiply and accumulate, signed; (M

X

:M

X+1

)

×

(M

Y

:M

Y+1

)

+

(M~M+3)

M~M+3; 16 by 16 to 32-bit

INH

Special

Extended maximum in D; put larger of

2 unsigned 16-bit values in D

MAX[(D), (M:M+1)]

D

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 14

18 12 hh ll

18 1A xb

18 1A xb ff

18 1A xb ee ff

18 1A xb

18 1A xb ee ff

Extended maximum in M; put larger of

2 unsigned 16-bit values in M

MAX[(D), (M:M+1)]

M:M+1

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Extended minimum in D; put smaller of

2 unsigned 16-bit values in D

MIN[(D), (M:M+1)]

D

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 1E xb

18 1E xb ff

18 1E xb ee ff

18 1E xb

18 1E xb ee ff

18 1B xb

18 1B xb ff

18 1B xb ee ff

18 1B xb

18 1B xb ee ff

Access Detail

OffffffffffO

ORROfffRRfWWP

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

EMINM

EMINM

EMINM oprx0_xysppc oprx9,xysppc oprx16,xysppc

EMINM [D,

EMINM [

EMUL xysppc] oprx16,xysppc]

Extended minimum in M; put smaller of

2 unsigned 16-bit values in M

MIN[(D), (M:M+1)]

M:M+1

N, Z, V, C bits reflect result of internal compare [(D)–(M:M+1)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Extended multiply, unsigned

(D)

×

(Y)

Y:D; 16 by 16 to 32-bit

Extended multiply, signed

(D)

×

(Y)

Y:D; 16 by 16 to 32-bit

INH

INH

18 1F xb

18 1F xb ff

18 1F xb ee ff

18 1F xb

18 1F xb ee ff

13

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW ffO

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆

EMULS

18 13 OfO

OffO

(if followed by page 2 instruction)

– – – –

∆ ∆

EORA # opr8i

EORA opr8a

EORA opr16a

EORA oprx0_xysppc

EORA oprx9,xysppc

EORA oprx16,xysppc

EORA [D, xysppc]

EORA [ oprx16,xysppc]

EORB #

EORB

EORB

EORB

EORB

EORB opr8i opr8a opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc

EORB [D,

EORB [ xysppc] oprx16,xysppc]

Exclusive OR A

(A)

(B)

(M) or (A) or (B)

(M)

A imm

B imm

A

Exclusive OR B

B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

88 ii

98 dd

B8 hh ll

A8 xb

A8 xb ff

A8 xb ee ff

A8 xb

A8 xb ee ff

C8 ii

D8 dd

F8 hh ll

E8 xb

E8 xb ff

E8 xb ee ff

E8 xb

E8 xb ee ff

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

ETBL oprx0_xysppc

Extended table lookup and interpolate,

16-bit; (M:M+1)+

[(B)

×

((M+2:M+3)–(M:M+1))]

D

IDX

18 3F xb ORRffffffP

– – – –

∆ ∆

Before executing ETBL, initialize B with fractional part of lookup value; initialize index register to point to first table entry (M:M+1). No extensions or indirect addressing allowed.

EXG abcdxysp,abcdxysp

FDIV

Exchange register contents

(r1)

(r2) r1 and r2 same size

$00:(r1)

⇒ r2r1=8-bit; r2=16-bit

(r1

L

)

(r2)r1=16-bit; r2=8-bit

Fractional divide; (D)

÷

(X)

X remainder

D; 16 by 16-bit

INH

INH

B7 eb

18 11

P

OffffffffffO

– – – – – – – –

– – – – –

∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form

IBEQ abdxysp, rel9

IBNE abdxysp, rel9

IDIV

IDIVS

INC opr16a

INC oprx0_xysppc

INC oprx9,xysppc

INC oprx16,xysppc

INC [D, xysppc]

INC [ oprx16,xysppc]

INCA

INCB

INSSame as LEAS 1,SP

INX

INY

JMP opr16a

JMP oprx0_xysppc

JMP oprx9,xysppc

JMP oprx16,xysppc

JMP [D, xysppc]

JMP [ oprx16,xysppc]

JSR opr8a

JSR opr16a

JSR oprx0_xysppc

JSR oprx9,xysppc

JSR oprx16,xysppc

JSR [D, xysppc]

JSR [ oprx16,xysppc]

LBCC rel16Same as LBHS

LBCS rel16Same as LBLO

LBEQ rel16

LBGE rel16

LBGT rel16

LBHI rel16

LBHS rel16Same as LBCC

LBLE rel16

LBLO rel16Same as LBCS

LBLS rel16

LBLT rel16

Operation

Increment and branch if equal to 0

(counter)+1

⇒ counter

If (counter)=0, then branch

Increment and branch if not equal to 0

(counter)+1

⇒ counter

If (counter)

0, then branch

Integer divide, unsigned; (D)

÷

(X)

X

Remainder

D; 16 by 16-bit

Integer divide, signed; (D)

÷

(X)

X

Remainder

D; 16 by 16-bit

Increment M; (M)+1

M

Address

Mode

REL

(9-bit)

Machine

Coding (Hex)

04 lb rr

REL

(9-bit)

INH

INH

04 lb rr

18 10

18 15

Increment A; (A)+1

Increment B; (B)+1

A

B

Increment SP; (SP)+1

Increment X; (X)+1

X

Increment Y; (Y)+1

Y

SP

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

IDX

INH

INH

72 hh ll

62 xb

62 xb ff

62 xb ee ff

62 xb

62 xb ee ff

42

52

1B 81

08

02

Jump

Subroutine address

Jump to subroutine

(SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

PC

SP+1

Subroutine address

PC

Long branch if C clear; if C=0, then

(PC)+4+rel

PC

Long branch if C set; if C=1, then

(PC)+4+rel

PC

Long branch if equal; if Z=1, then

(PC)+4+rel

PC

Long branch if

0, signed

If N

V=0, then (PC)+4+rel

PC

Long branch if

>

0, signed

If Z | (N

V)=0, then (PC)+4+rel

PC

Long branch if higher, unsigned

If C | Z=0, then (PC)+4+rel

PC

Long branch if higher or same, unsigned; If C=0, (PC)+4+rel

PC

Long branch if

0, signed; if

Z | (N

V)=1, then (PC)+4+rel

PC

Long branch if lower, unsigned; if

C=1, then (PC)+4+rel

PC

Long branch if lower or same, unsigned; If C | Z=1, then

(PC)+4+rel

PC

Long branch if

<

0, signed

If N

V=1, then (PC)+4+rel

PC

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

REL

REL

REL

REL

REL

REL

REL

REL

REL

REL

REL

06 hh ll

05 xb

05 xb ff

05 xb ee ff

05 xb

05 xb ee ff

17 dd

16 hh ll

15 xb

15 xb ff

15 xb ee ff

15 xb

15 xb ee ff

18 24 qq rr

18 25 qq rr

18 27 qq rr

18 2C qq rr

18 2E qq rr

18 22 qq rr

18 24 qq rr

18 2F qq rr

18 25 qq rr

18 23 qq rr

18 2D qq rr

Access Detail

PPP

(branch)

PPO

(no branch)

PPP

(branch)

PPO

(no branch)

OffffffffffO

OffffffffffO

OPPP

OPO

(branch)

(no branch)

O

O rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

Pf

PPP

PPP

PPP fPPP fIfPPP fIfPPP

SPPP

SPPP

PPPS

PPPS fPPPS fIfPPPS fIfPPPS

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – –

0

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆

– – – – – – – –

– – – – –

– –

– – – – –

– –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

For More Information On This Product,

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LBMI rel16

Source Form

LBNE rel16

LBPL rel16

LBRA rel16

LBRN rel16

LBVC rel16

LBVS rel16

LDAA # opr8i

LDAA opr8a

LDAA opr16a

LDAA oprx0_xysppc

LDAA oprx9,xysppc

LDAA oprx16,xysppc

LDAA [D, xysppc]

LDAA [ oprx16,xysppc]

LDAB # opr8i

LDAB opr8a

LDAB opr16a

LDAB oprx0_xysppc

LDAB oprx9,xysppc

LDAB oprx16,xysppc

LDAB [D, xysppc]

LDAB [ oprx16,xysppc]

LDD # opr16i

LDD opr8a

LDD opr16a

LDD oprx0_xysppc

LDD oprx9,xysppc

LDD oprx16,xysppc

LDD [D, xysppc]

LDD [ oprx16,xysppc]

LDS # opr16i

LDS opr8a

LDS opr16a

LDS oprx0_xysppc

LDS oprx9,xysppc

LDS oprx16,xysppc

LDS [D, xysppc]

LDS [ oprx16,xysppc]

LDX # opr16i

LDX opr8a

LDX opr16a

LDX oprx0_xysppc

LDX oprx9,xysppc

LDX oprx16,xysppc

LDX [D, xysppc]

LDX [ oprx16,xysppc]

LDY # opr16i

LDY opr8a

LDY opr16a

LDY oprx0_xysppc

LDY oprx9,xysppc

LDY oprx16,xysppc

LDY [D, xysppc]

LDY [ oprx16,xysppc]

Operation

Long branch if minus

If N=1, then (PC)+4+rel

PC

Long branch if not equal to 0

If Z=0, then (PC)+4+rel

PC

Long branch if plus

If N=0, then (PC)+4+rel

PC

Long branch always

Long branch never

Long branch if V clear

If V=0,then (PC)+4+rel

PC

Long branch if V set

If V=1,then (PC)+4+rel

PC

Load A

(M)

A or imm

A

Load B

(M)

B or imm

B

Load D

(M:M+1)

A:B or imm

A:B

Load SP

(M:M+1)

SP or imm

SP

Load X

(M:M+1)

X or imm

X

Load Y

(M:M+1)

Y or imm

Y

CC jj kk

DC dd

FC hh ll

EC xb

EC xb ff

EC xb ee ff

EC xb

EC xb ee ff

CF jj kk

DF dd

FF hh ll

EF xb

EF xb ff

EF xb ee ff

EF xb

EF xb ee ff

86 ii

96 dd

B6 hh ll

A6 xb

A6 xb ff

A6 xb ee ff

A6 xb

A6 xb ee ff

C6 ii

D6 dd

F6 hh ll

E6 xb

E6 xb ff

E6 xb ee ff

E6 xb

E6 xb ee ff

CE jj kk

DE dd

FE hh ll

EE xb

EE xb ff

EE xb ee ff

EE xb

EE xb ee ff

CD jj kk

DD dd

FD hh ll

ED xb

ED xb ff

ED xb ee ff

ED xb

ED xb ee ff

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Address

Mode

REL

Machine

Coding (Hex)

18 2B qq rr

REL

REL

REL

REL

REL

REL

18 26 qq rr

18 2A qq rr

18 20 qq rr

18 21 qq rr

18 28 qq rr

18 29 qq rr

Access Detail

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

OPPP

OPO

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

OPPP

(branch)

OPO

(no branch)

OPPP

(branch)

OPO

(no branch)

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

For More Information On This Product,

Go to: www.freescale.com

Source Form

LEAS oprx0_xysppc

LEAS oprx9,xysppc

LEAS oprx16,xysppc

LEAX oprx0_xysppc

LEAX oprx9,xysppc

LEAX oprx16,xysppc

LEAY oprx0_xysppc

LEAY oprx9,xysppc

LEAY oprx16,xysppc

LSL opr16aSame as ASL

LSL oprx0_xysppc

LSL oprx9,xysppc

LSL oprx16,xysppc

LSL [D, xysppc]

LSL [ oprx16,xysppc]

LSLASame as ASLA

LSLBSame as ASLB

LSLDSame as ASLD

LSR opr16a

LSR oprx0_xysppc

LSR oprx9,xysppc

LSR oprx16,xysppc

LSR [D, xysppc]

LSR [ oprx16,xysppc]

LSRA

LSRB

LSRD

MAXA oprx0_xysppc

MAXA oprx9,xysppc

MAXA oprx16,xysppc

MAXA [D, xysppc]

MAXA [ oprx16,xysppc]

MAXM oprx0_xysppc

MAXM oprx9,xysppc

MAXM oprx16,xysppc

MAXM [D, xysppc]

MAXM [ oprx16,xysppc]

MEM

MINA oprx0_xysppc

MINA oprx9,xysppc

MINA oprx16,xysppc

MINA [D, xysppc]

MINA [ oprx16,xysppc]

MINM oprx0_xysppc

MINM oprx9,xysppc

MINM oprx16,xysppc

MINM [D, xysppc]

MINM [ oprx16,xysppc]

Load effective address into SP

EA

EA

SP

Load effective address into X

X

Load effective address into Y

EA

Y

Operation

Logical shift left M

C b7 b0

0

Address

Mode

IDX

IDX1

IDX2

Machine

Coding (Hex)

1B xb

1B xb ff

1B xb ee ff

IDX

IDX1

IDX2

IDX

IDX1

IDX2

1A xb

1A xb ff

1A xb ee ff

19 xb

19 xb ff

19 xb ee ff

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

48

58

59

Logical shift left A

Logical shift left B

Logical shift left D

C b7

• • •

A b0 b7

• • •

B b0

0

Logical shift right M

0 b7 b0

Logical shift right A

Logical shift right B

Logical shift right D

0 b7 A b0 b7

C

B b0 C

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

74 hh ll

64 xb

64 xb ff

64 xb ee ff

64 xb

64 xb ee ff

44

54

49

Maximum in A; put larger of 2 unsigned 8-bit values in A

MAX[(A), (M)]

A

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 18 xb

18 18 xb ff

18 18 xb ee ff

18 18 xb

18 18 xb ee ff

Maximum in M; put larger of 2 unsigned 8-bit values in M

MAX[(A), (M)]

M

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Determine grade of membership;

µ

(grade)

M

Y

; (X)+4

X; (Y)+1

Y

If (A)<P1 or (A)>P2, then

µ

=0; else

µ

=

MIN[((A)–P1)

×

S1, (P2–(A))

×

S2, $FF]

(A)=current crisp input value; X points at 4 data bytes (P1, P2, S1, S2) of a trapezoidal membership function; Y points at fuzzy input (RAM location)

Special

01

18 1C xb

18 1C xb ff

18 1C xb ee ff

18 1C xb

18 1C xb ee ff

Minimum in A; put smaller of 2 unsigned 8-bit values in A

MIN[(A), (M)]

A

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

Minimum in N; put smaller of two unsigned 8-bit values in M

MIN[(A), (M)]

M

N, Z, V, C bits reflect result of internal compare [(A)–(M)]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

18 19 xb

18 19 xb ff

18 19 xb ee ff

18 19 xb

18 19 xb ee ff

18 1D xb

18 1D xb ff

18 1D xb ee ff

18 1D xb

18 1D xb ee ff rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

RRfOw

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

Access Detail

Pf

PO

PP

Pf

PO

PP

Pf

PO

PP rOPw rPw rPOw frPPw fIfrPw fIPrPw

O

O

O

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – – 0

∆ ∆ ∆

– – – – 0

∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – ? – ? ? ? ?

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

For More Information On This Product,

Go to: www.freescale.com

Source Form Operation

MOVB # opr8, opr16a

MOVB # opr8i, oprx0_xysppc

MOVB opr16a, opr16a

MOVB opr16a, oprx0_xysppc

MOVB oprx0_xysppc, opr16a

MOVB oprx0_xysppc, oprx0_xysppc

Move byte

Memory-to-memory 8-bit byte-move

(M

1

)

M

2

First operand specifies byte to move

MOVW # oprx16, opr16a

MOVW # opr16i, oprx0_xysppc

MOVW opr16a, opr16a

MOVW opr16a, oprx0_xysppc

MOVW oprx0_xysppc, opr16a

MOVW oprx0_xysppc, oprx0_xysppc

Move word

Memory-to-memory 16-bit word-move

(M

1

:M

1

+1)

M

2

:M

2

+1

First operand specifies word to move

MUL Multiply, unsigned

(A)

×

(B)

A:B; 8 by 8-bit

Negate M; 0–(M)

M or (M)+1

M NEG opr16a

NEG oprx0_xysppc

NEG oprx9,xysppc

NEG oprx16,xysppc

NEG [D, xysppc]

NEG [ oprx16,xysppc]

NEGA

NEGB

NOP

Negate A; 0–(A)

Negate B; 0–(B)

No operation

A or (A)+1

B or (B)+1

A

B

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

Address

Mode

Machine

Coding (Hex)

Access Detail

IMM-EXT

IMM-IDX

EXT-EXT

EXT-IDX

IDX-EXT

IDX-IDX

18 0B ii hh ll

18 08 xb ii

18 0C hh ll hh ll

18 09 xb hh ll

18 0D xb hh ll

18 0A xb xb

OPwP

OPwO

OrPwPO

OPrPw

OrPwP

OrPwO

IMM-EXT

IMM-IDX

EXT-EXT

EXT-IDX

IDX-EXT

IDX-IDX

18 03 jj kk hh ll

18 00 xb jj kk

18 04 hh ll hh ll

18 01 xb hh ll

18 05 xb hh ll

18 02 xb xb

OPWPO

OPPW

ORPWPO

OPRPW

ORPWP

ORPWO

INH

12 O

70 hh ll

60 xb

60 xb ff

60 xb ee ff

60 xb

60 xb ee ff

40

50

A7 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

O

ORAA # opr8i

ORAA opr8a

ORAA opr16a

ORAA oprx0_xysppc

ORAA oprx9,xysppc

ORAA oprx16,xysppc

ORAA [D, xysppc]

ORAA [ oprx16,xysppc]

ORAB # opr8i

ORAB opr8a

ORAB opr16a

ORAB oprx0_xysppc

ORAB oprx9,xysppc

ORAB oprx16,xysppc

ORAB [D, xysppc]

ORAB [ oprx16,xysppc]

ORCC # opr8i

PSHA

PSHB

PSHC

PSHD

PSHX

PSHY

PULA

PULB

PULC

PULD

OR accumulator A

(A) | (M)

A or (A) | imm

A

OR accumulator B

(B) | (M)

B or (B) | imm

B

OR CCR; (CCR) | imm

CCR

Push A; (SP)–1

SP; (A)

M

SP

Push B; (SP)–1

SP; (B)

M

SP

Push CCR; (SP)–1

SP;

(CCR)

M

SP

Push D

(SP)–2

SP; (A:B)

M

SP

:M

SP+1

Push X

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

Push Y

(SP)–2

SP; (Y

H

:Y

L

)

M

SP

:M

SP+1

Pull A

(M

SP

)

A; (SP)+1

SP

Pull B

(M

SP

)

B; (SP)+1

SP

Pull CCR

(M

SP

)

CCR; (SP)+1

SP

Pull D

(M

SP

:M

SP+1

)

A:B; (SP)+2

SP

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

INH

INH

INH

INH

INH

INH

INH

INH

INH

INH

8A ii

9A dd

BA hh ll

AA xb

AA xb ff

AA xb ee ff

AA xb

AA xb ee ff

CA ii

DA dd

FA hh ll

EA xb

EA xb ff

EA xb ee ff

EA xb

EA xb ee ff

14 ii

36

37

39

3B

34

35

32

33

38

3A

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

Os

Os

Os

OS

OS

OS ufO ufO ufO

UfO

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

⇑ ⇑ ⇑ ⇑ ⇑ ⇑

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

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Source Form Operation

Address

Mode

INH

30

Machine

Coding (Hex)

Access Detail

PULX

PULY

REV

Pull X

(M

SP

:M

SP+1

)

X

H

:X

L

; (SP)+2

SP

Pull Y

(M

SP

:M

SP+1

)

Y

H

:Y

L

; (SP)+2

SP

Rule evaluation, unweighted; find smallest rule input; store to rule outputs unless fuzzy output is larger

INH

Special

31

18 3A

UfO

UfO

Orf(t^tx)O* ff+Orft^**

*The t^tx loop is executed once for each element in the rule list. The

^

denotes a check for pending interrupt requests.

**These are additional cycles caused by an interrupt: ff is the exit sequence and

Orft^

is the re-entry sequence.

REVW Special

18 3B

Rule evaluation, weighted; rule weights optional; find smallest rule input; store to rule outputs unless fuzzy output is larger

ORf(t^Tx)O* or

ORf(r^ffRf)O** ffff+ORft^*** ffff+ORfr^****

SBCA # opr8i

SBCA opr8a

SBCA opr16a

SBCA oprx0_xysppc

SBCA oprx9,xysppc

SBCA oprx16,xysppc

SBCA [D, xysppc]

SBCA [ oprx16,xysppc]

Subtract with carry from A

(A)–(M)–C

A or (A)–imm–C

A

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

82 ii

92 dd

B2 hh ll

A2 xb

A2 xb ff

A2 xb ee ff

A2 xb

A2 xb ee ff

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

S X H I N Z V C

– – – – – – – –

– – – – – – – –

– – ? – ? ?

?

– – ? – ? ?

!

*With weighting not enabled, the t^Tx loop is executed once for each element in the rule list. The

^

denotes a check for pending interrupt requests.

**With weighting enabled, the t^Tx

loop is replaced by r^ffRf

.

***Additional cycles caused by an interrupt when weighting is not enabled: ffff

is the exit sequence and

ORft^

is the re-entry sequence.

**** Additional cycles caused by an interrupt when weighting is enabled: ffff

is the exit sequence and

ORfr^

is the re-entry sequence.

Rotate left M

– – – –

∆ ∆ ∆ ∆

ROL opr16a

ROL oprx0_xysppc

ROL oprx9,xysppc

ROL oprx16,xysppc

ROL [D, xysppc]

ROL [ oprx16,xysppc]

ROLA

ROLB

C b7

Rotate left A

Rotate left B b0

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

75 hh ll

65 xb

65 xb ff

65 xb ee ff

65 xb

65 xb ee ff

45

55 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O

ROR opr16a

ROR oprx0_xysppc

ROR oprx9,xysppc

ROR oprx16,xysppc

ROR [D, xysppc]

ROR [ oprx16,xysppc]

RORA

RORB

RTC

RTI

RTS

SBA

Rotate right M b0 b7

C

Rotate right A

Rotate right B

Return from call; (M

SP

)

PPAGE

(SP)+1

SP;

(M

SP

:M

SP+1

(SP)+2

SP

)

PC

H

:PC

L

Return from interrupt

(M

SP

)

CCR; (SP)+1

SP

(M

SP

:M

SP+1

(M

SP

:M

SP+1

(M

(M

SP

SP

:M

:M

SP+1

SP+1

)

B:A;(SP)+2

SP

)

X

)

PC

)

Y

H

H

:X

:Y

L

;(SP)+4

SP

H

:PC

L

;(SP)+2

SP

L

;(SP)+4

SP

*RTI takes 11 cycles if an interrupt is pending.

Return from subroutine

(M

SP

:M

SP+1

(SP)+2

SP

)

PC

H

:PC

L

;

Subtract B from A; (A)–(B)

A

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

INH

INH

INH

76 hh ll

66 xb

66 xb ff

66 xb ee ff

66 xb

66 xb ee ff

46

56

0A

0B

3D

18 16 rPwO rPw rPwO frPwP fIfrPw fIPrPw

O

O uUnfPPP uUUUUPPP or uUUUUfVfPPP*

UfPPP

OO

– – – –

∆ ∆ ∆ ∆

– – – – – – – –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

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Source Form

SBCB # opr8i

SBCB opr8a

SBCB opr16a

SBCB oprx0_xysppc

SBCB oprx9,xysppc

SBCB oprx16,xysppc

SBCB [D, xysppc]

SBCB [ oprx16,xysppc]

SECSame as ORCC #$01

Operation

Subtract with carry from B

(B)–(M)–C

B or (B)–imm–C

B

SEISame as ORCC #$10

SEVSame as ORCC #$02

Set C bit

Set I bit

Set V bit

SEX abc,dxyspSame as TFR r1, r2 Sign extend; 8-bit r1 to 16-bit r2

$00:(r1)

⇒ r2 if bit 7 of r1 is 0

$FF:(r1)

⇒ r2 if bit 7 of r1 is 1

STAA opr8a

STAA opr16a

STAA oprx0_xysppc

STAA oprx9,xysppc

STAA oprx16,xysppc

STAA [D, xysppc]

STAA [ oprx16,xysppc]

Store accumulator A

(A)

M

Store accumulator B

(B)

M

STAB opr8a

STAB opr16a

STAB oprx0_xysppc

STAB oprx9,xysppc

STAB oprx16,xysppc

STAB [D, xysppc]

STAB [ oprx16,xysppc]

STD opr8a

STD opr16a

STD oprx0_xysppc

STD oprx9,xysppc

STD oprx16,xysppc

STD [D, xysppc]

STD [ oprx16,xysppc]

STOP

Store D

(A:B)

M:M+1

Stop processing; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

Stop all clocks

STS opr8a

STS opr16a

STS oprx0_xysppc

STS oprx9,xysppc

STS oprx16,xysppc

STS [D, xysppc]

STS [ oprx16,xysppc]

STX opr8a

STX opr16a

STX oprx0_xysppc

STX oprx9,xysppc

STX oprx16,xysppc

STX [D, xysppc]

STX [ oprx16,xysppc]

Store SP

(SP

H

:SP

L

)

M:M+1

Store X

(X

H

:X

L

)

M:M+1

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

IMM

IMM

INH

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

Machine

Coding (Hex)

C2 ii

D2 dd

F2 hh ll

E2 xb

E2 xb ff

E2 xb ee ff

E2 xb

E2 xb ee ff

14 01

14 10

14 02

B7 eb

5A dd

7A hh ll

6A xb

6A xb ff

6A xb ee ff

6A xb

6A xb ee ff

5B dd

7B hh ll

6B xb

6B xb ff

6B xb ee ff

6B xb

6B xb ee ff

5C dd

7C hh ll

6C xb

6C xb ff

6C xb ee ff

6C xb

6C xb ee ff

18 3E

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

5F dd

7F hh ll

6F xb

6F xb ff

6F xb ee ff

6F xb

6F xb ee ff

5E dd

7E hh ll

6E xb

6E xb ff

6E xb ee ff

6E xb

6E xb ee ff

P

P

Access Detail

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P

P

Pw

PwO

Pw

PwO

PwP

PIfw

PIPw

Pw

PwO

Pw

PwO

PwP

PIfw

PIPw

PW

PWO

PW

PWO

PWP

PIfW

PIPW

OOSSSSsf

(enter stop mode) fVfPPP

(exit stop mode) ff

(continue stop mode)

OO

(if stop mode disabled by S=1)

PW

PWO

PW

PWO

PWP

PIfW

PIPW

PW

PWO

PW

PWO

PWP

PIfW

PIPW

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

– – – – – – – 1

– – – 1 – – – –

– – – – – – 1 –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

– – – – – – – –

– – – –

∆ ∆

0 –

– – – –

∆ ∆

0 –

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SUBA #

SUBA

SUBA

SUBA

SUBA

SUBA

SUBA [D,

SUBA [

Source Form

STY opr8a

STY opr16a

STY oprx0_xysppc

STY oprx9,xysppc

STY oprx16,xysppc

STY [D, xysppc]

STY [ oprx16,xysppc] opr8i opr8a opr16a oprx0_xysppc oprx9,xysppc oprx16,xysppc xysppc] oprx16,xysppc]

SUBB # opr8i

SUBB opr8a

SUBB opr16a

SUBB oprx0_xysppc

SUBB oprx9,xysppc

SUBB oprx16,xysppc

SUBB [D, xysppc]

SUBB [ oprx16,xysppc]

Store Y

(Y

H

:Y

L

)

(A)–(M) or (A)–imm

Operation

Subtract from B

(B)–(M)

M:M+1

Subtract from A

A

B or (B)–imm

A

B

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Coding (Hex)

5D dd

7D hh ll

6D xb

6D xb ff

6D xb ee ff

6D xb

6D xb ee ff

80 ii

90 dd

B0 hh ll

A0 xb

A0 xb ff

A0 xb ee ff

A0 xb

A0 xb ee ff

C0 ii

D0 dd

F0 hh ll

E0 xb

E0 xb ff

E0 xb ee ff

E0 xb

E0 xb ee ff

SUBD # opr16i

SUBD opr8a

SUBD opr16a

SUBD oprx0_xysppc

SUBD oprx9,xysppc

SUBD oprx16,xysppc

SUBD [D, xysppc]

SUBD [ oprx16,xysppc]

Subtract from D

(A:B)–(M:M+1) or (A:B)–imm

A:B

A:B

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

83 jj kk

93 dd

B3 hh ll

A3 xb

A3 xb ff

A3 xb ee ff

A3 xb

A3 xb ee ff

SWI Software interrupt; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

(SWI vector)

PC

;1

I

INH

3F

*The CPU also uses

VSPSSPSsP

for hardware interrupts and unimplemented opcode traps.

TAB Transfer A to B; (A)

B INH

18 0E

TAP

TBA

Transfer A to CCR; (A)

CCR

Assembled as TFR A, CCR

Transfer B to A; (B)

A

INH

INH

B7 02

18 0F

TBEQ abdxysp,rel9

04 lb rr

TBL

TFR oprx0_xysppc

TBNE abdxysp,rel9 abcdxysp,abcdxysp

TPASame as TFR CCR ,A

Test and branch if equal to 0

If (counter)=0, then (PC)

+

2

+ rel

PC

Table lookup and interpolate, 8-bit

(M)+[(B)

×

((M+1)–(M))]

A

Test and branch if not equal to 0

If (counter)

0, then (PC)

+

2

+ rel

PC

Transfer from register to register

(r1)

⇒ r2r1 and r2 same size

$00:(r1)

⇒ r2r1=8-bit; r2=16-bit

(r1

L

)

⇒ r2r1=16-bit; r2=8-bit

Transfer CCR to A; (CCR)

A

REL

(9-bit)

IDX

REL

(9-bit)

INH

INH

18 3D xb

04 lb rr

B7 eb

B7 20

OO

PPP

(branch)

PPO

(no branch)

ORfffP

PPP

(branch)

PPO

(no branch)

P

P

Access Detail

PW

PWO

PW

PWO

PWP

PIfW

PIPW

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

VSPSSPSsP*

OO

P

S X H I N Z V C

– – – –

∆ ∆

0 –

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – –

∆ ∆ ∆ ∆

– – – 1 – – – –

– – – –

∆ ∆

0 –

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – –

∆ ∆

0 –

– – – – – – – –

– – – –

∆ ∆

– – – – – – – –

– – – – – – – – or

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

– – – – – – – –

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Source Form

TRAP trapnum

TST opr16a

TST oprx0_xysppc

TST oprx9,xysppc

TST oprx16,xysppc

TST [D, xysppc]

TST [ oprx16,xysppc]

TSTA

TSTB

TSXSame as TFR SP,X

TSYSame as TFR SP,Y

TXSSame as TFR X,SP

TYSSame as TFR Y,SP

WAI

WAV

Operation

Trap unimplemented opcode;

(SP)–2

SP

RTN

H

:RTN

L

M

SP

(SP)–2

SP; (Y

H

:Y

:M

SP+1

L

)

M

SP

(SP)–2

SP; (X

H

:X

L

)

M

SP

(SP)–1

SP; (CCR)

M

SP

1

I; (trap vector)

PC

:M

SP+1

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

Test M; (M)–0

Address

Mode

INH

Machine

Coding (Hex)

18 tn tn = $30–$39 or tn = $40–$FF

Test A; (A)–0

Test B; (B)–0

Transfer SP to X; (SP)

X

Transfer SP to Y; (SP)

Y

Transfer X to SP; (X)

SP

Transfer Y to SP; (Y)

SP

Wait for interrupt; (SP)–2

SP

RTN

H

:RTN

L

M

SP

:M

(SP)–2

SP; (Y

H

:Y

L

SP+1

)

M

SP

:M

SP+1

(SP)–2

SP; (X

H

:X

L

)

M

SP

:M

SP+1

(SP)–2

SP; (B:A)

M

SP

:M

SP+1

(SP)–1

SP; (CCR)

M

SP

Calculate weighted average; sum of products (SOP) and sum of weights

(SOW)*

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

INH

INH

INH

INH

INH

INH

INH

F7 hh ll

E7 xb

E7 xb ff

E7 xb ee ff

E7 xb

E7 xb ee ff

97

D7

B7 75

B7 76

B7 57

B7 67

3E

Special

18 3C

OVSPSSPSsP rPO rPf rPO frPP fIfrPf fIPrPf

O

O

P

P

P

P

Access Detail

OSSSSsf

(before interrupt) fVfPPP

(after interrupt)

S X H I N Z V C

– – – 1 – – – –

– – – –

∆ ∆

0 0

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – – or

– – – 1 – – – – or

– 1 – 1 – – – –

Of(frr^ffff)O**

SSS+UUUrr^***

– – ? – ?

? ?

B

∑ i = 1

S i

F i

B

F i

X i = 1

Y:D

*Initialize B, X, and Y: B=number of elements; X points at first element in S i list; Y points at first element in F i list. All S i and F i elements are 8-bit values.

**The frr^ffff

sequence is the loop for one iteration of SOP and SOW accumulation. The

^

denotes a check for pending interrupt requests.

***Additional cycles caused by an interrupt:

SSS is the exit sequence and

UUUrr^ is the re-entry sequence. Intermediate values use six stack bytes.

wavr* Resume executing interrupted WAV Special

3C UUUrr^ffff(frr^ ffff)O**

SSS+UUUrr^***

– – ? – ?

? ?

*wavr is a pseudoinstruction that recovers intermediate results from the stack rather than initializing them to 0.

**The frr^ffff

sequence is the loop for one iteration of SOP and SOW recovery. The

^

denotes a check for pending interrupt requests.

***These are additional cycles caused by an interrupt:

SSS

is the exit sequence and

UUUrr^

is the re-entry sequence.

XGDXSame as EXG D, X Exchange D with X; (D)

(X) INH

B7 C5 P

– – – – – – – –

XGDYSame as EXG D, Y Exchange D with Y; (D)

(Y) INH

B7 C6 P

– – – – – – – –

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5.4.1 Register and Memory Notation

Table 5-2 Register and Memory Notation

A or a Accumulator A

An Bit n of accumulator A

B or b Accumulator B

Bn Bit n of accumulator B

D or d Accumulator D

Dn Bit n of accumulator D

X or x Index register X

X

H

High byte of index register X

X

L

Low byte of index register X

Xn Bit n of index register X

Y or y Index register Y

Y

H

High byte of index register Y

Y

L

Low byte of index register Y

Yn Bit n of index register Y

SP or sp Stack pointer

SPn Bit n of stack pointer

PC or pc Program counter

PC

H

High byte of program counter

PC

L

Low byte of program counter

CCR or c Condition code register

M Address of 8-bit memory location

Mn Bit n of byte at memory location M

Rn Bit n of the result of an arithmetic or logical operation

In Bit n of the intermediate result of an arithmetic or logical operation

RTN

H

High byte of return address

RTN

L

Low byte of return address

( ) Contents of

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5.4.2 Source Form Notation

The Source Form column of the summary in

Table 5-1

gives essential information about assembler

source forms. For complete information about writing source files for a particular assembler, refer to the documentation provided by the assembler vendor.

Everything in the Source Form column, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, square brackets ( [ or ] ), plus signs

(+), minus signs (–), and the register designation (A, B, D), are literal characters.

The groups of italic characters shown in

Table 5-3

represent variable information to be supplied by the

programmer. These groups can include any alphanumeric character or the underscore character, but cannot include a space or comma. For example, the groups xysppc and oprx0_xysppc are both valid, but the two groups oprx0 xysppc are not valid because there is a space between them.

Table 5-3 Source Form Notation

abc abcdxysp abd abdxysp dxysp

Register designator for A, B, or CCR

Register designator for A, B, CCR, D, X, Y, or SP

Register designator for A, B, or D

Register designator for A, B, D, X, Y, or SP msk8

Register designator for D, X, Y, or SP

8-bit mask value

Some assemblers require the # symbol before the mask value.

opr8i opr16i opr8a opr16a page

8-bit immediate value

16-bit immediate value

8-bit address value used with direct address mode

16-bit address value oprx0_xysp Indexed addressing postbyte code: oprx3,–xysp — Predecrement X , Y, or SP by 1–8 oprx3,+xysp — Preincrement X , Y, or SP by 1–8 oprx3,xysp– — Postdecrement X, Y, or SP by 1–8 oprx3,xysp+ — Postincrement X, Y, or SP by 1–8 oprx5,xysppc — 5-bit constant offset from X, Y, SP, or PC abd,xysppc — Accumulator A, B, or D offset from X, Y, SP, or PC oprx3 oprx5

Any positive integer from 1 to 8 for pre/post increment/decrement

Any integer from –16 to +15 oprx9 oprx16

Any integer from –256 to +255

Any integer from –32,768 to +65,535

8-bit value for PPAGE register

Some assemblers require the # symbol before this value.

rel8 rel9 rel16 trapnum xysp xysppc

Label of branch destination within –256 to +255 locations

Label of branch destination within –512 to +511 locations

Any label within the 64K byte memory space

Any 8-bit integer from $30 to $39 or from $40 to $FF

Register designator for X or Y or SP

Register designator for X or Y or SP or PC

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5.4.3 Operation Notation

Table 5-4 Operation Notation

+ Add

– Subtract

AND

| OR

Exclusive OR

×

Multiply

÷

Divide

: Concatenate

Transfer

Exchange

5.4.4 Address Mode Notation

Table 5-5 Address Mode Notation

INH Inherent; no operands in instruction stream

IMM Immediate; operand immediate value in instruction stream

DIR Direct; operand is lower byte of address from $0000 to $00FF

EXT Operand is a 16-bit address

REL Two’s complement relative offset; for branch instructions

IDX Indexed (no extension bytes); includes:

5-bit constant offset from X, Y, SP or PC

Pre/post increment/decrement by 1–8

Accumulator A, B, or D offset

IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte

IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes

[IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC

[D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC

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5.4.5 Machine Code Notation

In the Machine Code (Hex) column of the summary in

Table 5-1

, digits 0–9 and upper case letters A–F represent hexadecimal values. Pairs of lower-case letters represent 8-bit values as shown in

Table 5-6

.

Table 5-6 Machine Code Notation

dd

8-bit direct address from $0000 to $00FF; high byte is $00 ee

High byte of a 16-bit constant offset for indexed addressing eb

Exchange/transfer postbyte ff

Low eight bits of a 9-bit signed constant offset in indexed addressing, or low byte of a 16-bit constant offset in indexed addressing hh

High byte of a 16-bit extended address ii

8-bit immediate data value jj

High byte of a 16-bit immediate data value kk

Low byte of a 16-bit immediate data value lb

Loop primitive (DBNE) postbyte ll

Low byte of a 16-bit extended address mm

8-bit immediate mask value for bit manipulation instructions; bits that are set indicate bits to be affected pg

Program page or bank number used in CALL instruction qq

High byte of a 16-bit relative offset for long branches tn

Trap number from $30 to $39 or from $40 to $FF rr

Signed relative offset $80 (–128) to $7F (

+

127) relative to the byte following the relative offset byte, or low byte of a 16-bit relative offset for long branches xb

Indexed addressing postbyte

5.4.6 Access Detail Notation

A single-letter code in the Access Detail column of

Table 5-1

represents a single CPU access cycle. An upper-case letter indicates a 16-bit access.

Table 5-7 Access Detail Notation

f

Free cycle. During an f

cycle, the CPU does not use the bus. An f

cycle is always one cycle of the system bus clock. An f cycle can be used by a queue controller or the background debug system to perform a single-cycle access without disturbing the CPU.

g

Read PPAGE register. A g

cycle is used only in CALL instructions and is not visible on the external bus. Since PPAGE is an internal 8-bit register, a g

cycle is never stretched.

I

Read indirect pointer. Indexed-indirect instructions use the 16-bit indirect pointer from memory to address the instruction operand. An

I

cycle is a 16-bit read that can be aligned or misaligned. An

I cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An

I

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

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Table 5-7 Access Detail Notation (Continued)

i

Read indirect PPAGE value. An i

cycle is used only in indexed-indirect CALL instructions. The 8-bit

PPAGE value for the CALL destination is fetched from an indirect memory location. An i

cycle is stretched only when controlled by a chip-select circuit that is programmed for slow memory.

n

Write PPAGE register. An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus. Since the PPAGE register is an internal 8-bit register, an n

cycle is never stretched.

O

Optional cycle. An

O cycle adjusts instruction alignment in the instruction queue. An

O cycle can be a free cycle ( f

) or a program word access cycle (

P

). When the first byte of an instruction with an odd number of bytes is misaligned, the

O

cycle becomes a

P

cycle to maintain queue order. If the first byte is aligned, the

O

cycle is an f

cycle.

The $18 prebyte for a page-two opcode is treated as a special one-byte instruction. If the prebyte is misaligned, the

O

cycle at the beginning of the instruction becomes a

P

cycle to maintain queue order. If the prebyte is aligned, the

O

cycle is an f

cycle. If the instruction has an odd number of bytes, it has a second

O

cycle at the end. If the first

O

cycle is a

P

cycle (prebyte misaligned), the second

O cycle is an f cycle. If the first

O cycle is an f cycle (prebyte aligned), the second

O cycle is a

P

cycle.

An

O cycle that becomes a

P cycle can be extended to two bus cycles if the MCU is operating with an

8-bit external data bus and the program is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

O

cycle that becomes an f

cycle is never stretched.

P

Program word access. Program information is fetched as aligned 16-bit words. A

P cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

r

8-bit data read. An r cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

R

16-bit data read. An

R

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

R

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

s

Stack 8-bit data. An s cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

S

Stack 16-bit data. An

S

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching if the address space is assigned to a chip-select circuit programmed for slow memory. An

S

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single cycle misaligned word access.

w

8-bit data write. A w

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

W

16-bit data write. A

W

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

A

W cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

u

Unstack 8-bit data. A

W

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

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Table 5-7 Access Detail Notation (Continued)

U

Unstack 16-bit data. A

U

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word access.

V

16-bit vector fetch. Vectors are always aligned 16-bit words. A

V

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

t

8-bit conditional read. A t cycle is either a data read cycle or a free cycle, depending on the data and flow of the REVW instruction. A t

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

T

16-bit conditional read. A

T

cycle is either a data read cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. A

T

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

x

8-bit conditional write. An x

cycle is either a data write cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. An x

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

Special Notation for Branch Taken/Not Taken

PPP/P

A short branch requires three cycles if taken, one cycle if not taken. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the queue advances, another program word fetch is made, and execution continues with the next instruction. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

OPPP/OPO

A long branch requires four cycles if taken, three cycles if not taken. An

O

cycle is required because all long branches are page two opcodes and thus include the $18 prebyte. The prebyte is treated as a one-byte instruction. If the prebyte is misaligned, the

O

cycle is a

P

cycle; if the prebyte is aligned, the

O

cycle is an f

cycle. As a result, both the taken and not-taken cases use one

O

cycle for the prebyte. In the not-taken case, the queue must advance so that execution can continue with the next instruction, and another

O

cycle is required to maintain the queue. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

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5.4.7 Condition Code State Notation

Table 5-8 Condition Code State Notation

– Not changed by operation

0 Cleared by operation

1 Set by operation

Set or cleared by operation

May be cleared or remain set, but not set by operation

May be set or remain cleared, but not cleared by operation

? May be changed by operation but final state not defined

! Used for a special purpose

5.5 External Visibility Of Instruction Queue

The instruction queue buffers program information and increases instruction throughput. The queue consists of three 16-bit stages. Program information is always fetched in aligned 16-bit words. Normally, at least three bytes of program information are available to the CPU when instruction execution begins.

Program information is fetched and queued a few cycles before it is used by the CPU. In order to monitor cycle-by-cycle CPU activity, it is necessary to externally reconstruct what is happening in the instruction queue.

Two external pins, IPIPE[1:0], provide time-multiplexed information about data movement in the queue and instruction execution. To complete the picture for system debugging, it is also necessary to include program information and associated addresses in the reconstructed queue.

The instruction queue and cycle-by-cycle activity can be reconstructed in real time or from trace history captured by a logic analyzer. However, neither scheme can be used to stop the CPU at a specific instruction. By the time an operation is visible outside the system, the instruction has already begun execution. A separate instruction tagging mechanism is provided for this purpose. A tag follows the information in the queue as the queue is advanced. During debugging, the CPU enters active background debug mode when a tagged instruction reaches the head of the queue, rather than executing the tagged

instruction. For more information about tagging, refer to 14.4.8 Instruction Tagging.

5.5.1 Instruction Queue Status Signals

The IPIPE[1:0] signals carry time-multiplexed information about data movement and instruction execution during normal operation. The signals are available on two multifunctional device pins. During reset, the pins are mode-select inputs MODA and MODB. After reset, information on the pins does not become valid until an instruction reaches stage two of the queue.

To reconstruct the queue, the information carried by the status signals must be captured externally. In general, data-movement and execution-start information are considered to be distinct two-bit values, with the low bit on IPIPE0 and the high bit on IPIPE1. Data-movement information is available when E clock is high or on falling edges of the E clock; execution-start information is available when E clock is low or on rising edges of the E clock, as shown in

Figure 5-1

. Data-movement information refers to data on the

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bus. Execution-start information is delayed one bus cycle to guarantee the indicated opcode is in stage three.

Table 5-9

summarizes the information encoded on the IPIPE[1:0] pins.

CPU CLOCK T4 T2 T4 T2 T4 T2

E CLOCK

PIPE[1:0]

EX

00

NONE

DM

10

ALD

A

EX

10

SEV

B

DM

00

NONE

EX

11

SOD

C

DATA[15:0] PROGRAM DATA OPERAND OR FREE CYCLE

STAGE THREE

STAGE TWO

STAGE ONE

B C

A

ALD — Advance and load data

SEV — Start even instruction

SOD — Start odd instruction

A

Figure 5-1 Queue Status Signal Timing

PROGRAM DATA

DM

10

ALD

Data movement status is valid when the E clock is high and is represented by two states:

• No movement — There is no data shifting in the queue.

• Advance and load from data bus — The queue shifts up one stage with stage one being filled with the data on the read data bus.

Execution start status is valid when the E clock is low and is represented by four states:

• No start — Execution of the current instruction continues.

• Start interrupt — An interrupt sequence has begun.

NOTE:

The start-interrupt state is indicated when an interrupt request or tagged instruction alters program flow. SWI and TRAP instructions are part of normal program flow and are indicated as start even or start odd depending on their alignment. Since they are present in the queue, they can be tracked in an external queue rebuild. An external event that interrupts program flow is indeterministic.

Program data is not present in the queue until after the vector jump.

• Start even instruction — The current opcode is in the high byte of stage three of the queue.

• Start odd instruction — The current opcode is in the low byte of stage three of the queue.

Table 5-9 IPIPE[1:0] Decoding when E Clock is High

Data Movement

(capture at E fall)

0:0

Mnemonic

— No movement

Meaning

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Table 5-9 IPIPE[1:0] Decoding when E Clock is High

Data Movement

(capture at E fall)

0:1

1:0

1:1

Mnemonic

ALD

Meaning

Reserved

Advance queue and load from bus

Reserved

Table 5-10 IPIPE[1:0] Decoding when E Clock is Low

Execution Start

(capture at E rise)

0:0

0:1

1:0

1:1

Mnemonic

INT

SEV

SOD

Meaning

No start

Start interrupt sequence

Start even instruction

Start odd instruction

The execution-start status signals are delayed by one E clock cycle to allow a lagging program fetch and queue advance. Therefore the execution-start status always refers to the data in stage three of the queue.

The advance and load from bus signal can be used as a load-enable to capture the instruction word on the data bus. This signal is effectively the queue advance signal inside the CPU. Program data is registered into stage one on the rising edge of t4 when queue advance is asserted.

5.5.2 No Movement (0:0)

The 0:0 state at the falling edge of E indicates that there is no data movement in the instruction queue during the current cycle. The 0:0 state at the rising edge of E indicates continuation of an instruction or interrupt sequence during the previous cycle.

5.5.3 ALD — Advance and Load from Data Bus (1:0)

The three-stage instruction queue is advanced by one word and stage one is refilled with a word of program information from the data bus. The CPU requested the information two bus cycles earlier but, due to access delays, the information was not available until the E cycle immediately prior to the ALD.

5.5.4 INT — Start Interrupt (0:1)

This state indicates program flow has changed to an interrupt sequence. Normally this cycle is a read of the interrupt vector. However, in systems that have interrupt vectors in external memory and an 8-bit data bus, this cycle reads only the lower byte of the 16-bit interrupt vector.

5.5.5 SEV — Start Even Instruction (1:0)

This state indicates that the instruction is in the even (high) half of the word in stage three of the instruction queue. The queue treats the $18 prebyte of an instruction on page two of the opcode map as a special

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one-byte, one-cycle instruction. However, interrupts are not recognized at the boundary between the prebyte and the rest of the instruction.

5.5.6 SOD — Start Odd Instruction (1:1)

This state indicates that the instruction in the odd (low) half of the word in stage three of the instruction queue. The queue treats the $18 prebyte of an instruction on page two of the opcode map as a special one-byte, one-cycle instruction. However, interrupts are not recognized at the boundary between the prebyte and the rest of the instruction.

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Section 6 Exception Processing

Exceptions are events that require a change in the sequence of instruction execution. This section describes the exceptions supported by the Core and their functionality.

6.1 Exception Processing Overview

The Core supports two basic types of exceptions; those from resets and those from interrupt requests.

Regardless of the source, the first cycle in exception processing is a vector fetch cycle. The exception processing flow is shown in

Figure 6-1

below. Relevant points within the flow are detailed in the paragraphs that follow.

1.0-V

During the vector fetch cycle, the CPU indicates to the system that it is requesting that the vector address of the pending exception having the highest priority be driven onto the address bus. The CPU does not provide this address.

The vector points to the address where the exception service routine begins. Exception vectors are stored in a table at the top of the memory map ($FFB6–$FFFF). The CPU begins using the vector to fetch instructions in the third cycle of the exception processing sequence.

After the vector fetch, the CPU selects one of the three processing paths based on the source of the exception:

• Reset

• X bit maskable and I bit maskable interrupt request

• SWI and TRAP

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START

1.0-V Fetch vector

2.0-f No bus access

Set S, X, and I bits and clear all other bits in programmer’s model

Yes

Reset?

No

SWI or TRAP?

No

2.1-S Push return address

Address of next instruction that would have been executed

Yes

2.2-S Push return address

Address of instruction after SWI or unimplemented opcode

3.0-P Fetch program word

Start filling instruction queue

4.0-P Fetch program word

Continue filling instruction queue

5.0-P Fetch program word

Finish filling instruction queue

END

3.1-P

4.1-S

Fetch program word

Start filling instruction queue

Push Y

5.1-S Push X

6.1-P Fetch program word

Continue filling instruction queue

7.1-S Push B:A

XIRQ interrupt?

No

8.1-s Push CCR (byte)

Set I bit

Yes

8.2-s Push CCR (byte)

Set X and I bits

9.1-P Fetch program word

Finish filling instruction queue

END

Figure 6-1 Exception Processing Flow

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6.1.1 Reset Processing

2.0-f

This cycle sets the S, X and I bits.

3.0-P

through

5.0-P

These cycles are program word fetches that refill the instruction queue. Fetches start at the address pointed to by the reset vector. When the fetches are completed, reset processing ends, and the CPU starts executing the instruction at the head of the instruction queue.

6.1.2 Interrupt Processing

The SWI and TRAP interrupts have no mask or interrupt request and are always recognized. An XIRQ interrupt request is recognized any time after the X bit is cleared. An enabled I bit maskable interrupt request is recognized any time after the I bit is cleared. The CPU responds to an interrupt after it completes the execution of its current instruction. Interrupt latency depends on the number of cycles required to complete the instruction.

After the vector fetch, the CPU calculates a return address. The return address depends on the type of exception:

• When an X bit maskable or I bit maskable interrupt causes the exception, the return address points to the next instruction that would have been executed had processing not been interrupted.

• When an SWI opcode or TRAP causes the exception, the return address points to the next address after the SWI opcode or to the next address after the unimplemented opcode.

2.1-S

and

2.2-S

These are both S cycles (16-bit writes) that push the return address onto the stack.

3.1-P

This cycle is the first of three program word fetches to refill the instruction queue. Instructions are fetched from the address pointed to by the vector.

4.1-S

This cycle pushes Y onto the stack.

5.1-S

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This cycle pushes X onto the stack.

6.1-P

This cycle is the second of three program word fetches to refill the instruction queue. During this cycle, the contents of the A and B accumulators are concatenated in the order B:A, making register order in the stack frame the same as that of the M68HC11, M6801, and the M6800.

7.1-S

This cycle pushes the 16-bit word containing B:A onto the stack.

8.1-s

and

8.2-s

These are both s cycles (8-bit writes) that push the 8-bit CCR onto the stack and then update the X and I mask bits:

• When an XIRQ interrupt causes the exception, both X and I are set to inhibit further interrupts during exception processing.

• When any other interrupt causes the exception, the I bit is set to inhibit further I bit maskable interrupts during exception processing, but the X bit is not changed.

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9.1-P

This cycle is the third of three program word fetches to refill the instruction queue. It is the last cycle of exception processing. After this cycle the CPU begins the interrupt service routine by executing the instruction at the head of the instruction queue.

At the end of the interrupt service routine, an RTI instruction restores the stacked registers, and the CPU returns to the return address. RTI is an 8-cycle instruction when no other interrupt is pending, and an

11-cycle instruction when another interrupt is pending. In either case, the first five cycles are used to pull the CCR, B:A, X, Y, and the return address from the stack.

If no other interrupt is pending at this point, three program words are fetched to refill the instruction queue from the area of the return address and processing proceeds from there.

If another interrupt is pending after registers are restored, a new vector is fetched, and the stack pointer is adjusted to point at the CCR value that was just recovered (SP = SP – 9). This makes it appear that the registers have been stacked again. After the SP is adjusted, three program words are fetched to refill the instruction queue, starting at the address the vector points to. Processing then continues with execution of the instruction at the head of the queue.

6.2 Exception Vectors

Each exception has a 16-bit vector that points to the memory location where the routine that handles the exception is located. Vectors are stored in the upper 128 bytes of the standard 64K byte address map and are prioritized as shown in

Table 6-1

below from highest (system reset) to lowest (lowest priority I maskable interrupt).

Table 6-1 Exception Vector Map and Priority

Vector Address

$FFFE–$FFFF

$FFFC–$FFFD

$FFFA–$FFFB

$FFF8–$FFF9

$FFF6–$FFF7

$FFF4–$FFF5

$FFF2–$FFF3

$FFF0–$FF00

Source

System reset

Crystal Monitor reset

COP reset

Unimplemented opcode trap

Software interrupt instruction (SWI) or BDM vector request

XIRQ signal

IRQ signal

Device-specific I bit maskable interrupt sources (priority in descending order)

The six highest vector addresses are used for resets and nonmaskable interrupt sources. The remaining vectors are used for maskable interrupts. All vectors must be programmed to point to the address of the appropriate service routine.

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6.3 Exception Types

As stated previously, the Core supports exceptions from resets within the system as well as interrupt requests. Each of these exception types are discussed in the subsections that follow.

6.3.1 Resets

A block (or blocks) within the SoC design must evaluate any/all reset sources and request the proper reset vector from the Core. The CPU then fetches a vector determined by the source of the reset, configures the

CPU registers to their reset states and fills the instruction queue from the address pointed to by the vector.

There are three reset sources supported by the Core:

• System reset

• Crystal Monitor reset

• COP Watchdog reset

The priority and vector addresses assigned to these reset sources are shown in

Table 6-2

below. Please note that the inclusion of Crystal Monitor and COP reset requests is based upon the two most common and predominately used requests historically implemented in HC12 based systems. (It is assumed that all systems will have a system reset). Each SoC integration of the Core will determine whether the system contains both requests, one or the other or neither request. Each source is described in the subsections that follow.

Table 6-2 Reset Sources

Reset

Source

System reset

Crystal Monitor block

Computer Operating Properly (COP) block

Exception

Priority

1

2

3

Vector

Address

$FFFE–$FFFF

$FFFC–$FFFD

$FFFA–$FFFB

6.3.1.1 System reset

All systems generally have a block or sub-block within the system that determines the validity and priority of all possible sources of a system reset request. When a valid system reset request becomes active, the block or sub-block will request the appropriate reset vector from the Core. The Core will then acknowledge the request and provide the vector.

6.3.1.2 Crystal Monitor Reset

A Crystal Monitor sub-block typically contains a mechanism to determine whether or not the system clock frequency is above a predetermined limit. If the clock frequency falls below the limit when the Crystal

Monitor is enabled, the sub-block will typically request the reset vector that is associated with this function from the Core.

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6.3.1.3 COP Reset

A Computer Operating Properly (COP) sub-block helps protect against software failures. When the COP is enabled, software might, for example, write a particular code sequence to a specific address in order to keep a watchdog timer from timing out. If software fails to execute the sequence properly, the sub-block will typically then request a reset vector from the Core.

6.3.2 Interrupts

The Core supports the following types of interrupt sources:

• nonmaskable interrupt requests

– Unimplemented Opcode Trap

– Software Interrupt instruction

– XIRQ pin interrupt request

• Maskable interrupt requests

– Optional highest priority maskable interrupt (defaults to IRQ pin)

– IRQ pin interrupt request

– System peripheral block I bit maskable interrupt requests

A block (or blocks) within the SoC design must evaluate the system peripheral block I bit maskable interrupt sources and request the proper interrupt vector from the Core. All other interrupt requests are handled within the Core. Once the CPU receives the request it then fetches the vector to the proper interrupt service routine. The CPU will then calculate and stack a return address and the contents of the

CPU registers. Finally, it will set the I bit (and the X bit if XIRQ is the source) and fill the instruction queue from the address pointed to by the vector. The vector mapping for all interrupt sources is shown in

Table

6-3

below with detailed descriptions given in the sub-sections that follow.

Table 6-3 Interrupt Sources

Interrupt

Source

Unimplemented opcode trap (TRAP)

Software interrupt instruction (SWI)

Nonmaskable external interrupt pin (XIRQ pin)

Highest priority I-Maskable interrupt (defaults to IRQ pin)

Maskable external interrupt pin (IRQ pin)

System peripheral block interrupt requests

Exception

Priority

4

4

5

6

6 or 7

8

Mask

Vector

Address

None $FFF8–$FFF9

None $FFF6–$FFF7

X bit $FFF4–$FFF5

I bit

I bit

I bit

$FFxx-$FFxx+1

$FFF2–$FFF3

$FFF0–$FF00

Interrupts can be classified according to their maskability. TRAP and SWI are nonmaskable. The XIRQ pin is masked at reset by the X bit, but once software clears the X bit, the XIRQ pin is nonmaskable until another reset occurs. The remaining interrupt sources can be masked by the I bit. I bit maskable interrupt

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requests come from the IRQ pin and peripheral blocks within the system such as timers and serial ports.

These I bit maskable sources have default priorities that follow the address order of the interrupt vectors: the higher the address, the higher the priority of the interrupt request. The IRQ pin is initially assigned the highest I bit maskable interrupt priority. The system can give one I bit maskable source priority over other

I bit maskable sources configured at integration of the Core into the SoC design. The documentation for each system should provide more information.

6.3.2.1 Unimplemented Opcode Trap (TRAP)

Only 54 of the 256 positions on page 2 of the opcode map are used. Attempting to execute one of the 202 unused opcodes on page 2 causes a nonmaskable interrupt without an interrupt request. All 202 unused opcodes share the same interrupt vector, $FFF8:$FFF9.

TRAP processing stacks the CCR and then sets the I bit to prevent other interrupts during the TRAP service routine. An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state.

The CPU uses the next address after an unimplemented page 2 opcode as a return address. This differs from the M68HC11 illegal opcode interrupt, which uses the address of an illegal opcode as the return address. The stacked return address can be used to calculate the address of the unimplemented opcode for software-controlled traps.

6.3.2.2 Software Interrupt Instruction (SWI)

Execution of the SWI instruction causes a nonmaskable interrupt without an interrupt request.

SWI processing stacks the CCR and then sets the I bit to prevent other interrupts during the SWI service routine. An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state.

NOTE:

CPU processing of a TRAP or SWI cannot be interrupted. Also, TRAP and SWI are mutually exclusive instructions with no relative priority.

6.3.2.3 Nonmaskable External Interrupt Request Pin (XIRQ)

Driving the XIRQ pin low generates an external interrupt request, subject initially to masking by the X bit.

Reset sets the X bit, masking XIRQ interrupt requests. Software can unmask XIRQ interrupt requests once after reset by clearing the X bit with an instruction such as ANDCC #$BF. After the X bit has been cleared, it cannot be set and XIRQ interrupt requests are nonmaskable until another reset occurs.

XIRQ interrupt request processing stacks the CCR and then sets both the X and I bits to prevent other interrupts during the XIRQ service routine. An RTI instruction at the end of the service routine restores the X and I bits to their preinterrupt states.

6.3.2.4 Maskable External Interrupt Request Pin (IRQ)

Driving the IRQ pin low generates an external interrupt request, subject to masking by the I bit. IRQ interrupt request processing stacks the CCR and then sets the I bit to prevent other interrupts during the

IRQ service routine. An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state.

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The Interrupt sub-block of the Core (INT) also has a control bit to disconnect the IRQ input. Please see

Section 10

of this guide for a more detailed description.

6.3.2.5 System Peripheral Block Interrupt Requests

Some system peripheral blocks can generate interrupt requests that are subject to masking by the I bit.

Processing of an interrupt request from one of these sources stacks the CCR and then sets the I bit to prevent other interrupts during the service routine. An RTI instruction at the end of the service routine restores the I bit to its preinterrupt state.

Interrupt requests from a system peripheral block may also be subject to masking by interrupt enable bits in control registers. In addition, there may be interrupt flags with register read-write sequences required for flag clearing. The documentation for the system peripheral block should provide a detailed functional description.

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Section 7 Core Interface

This section provides a brief description of the Core interface to the rest of the SoC design. Detailed information on the Core interface, such as more complete descriptions of all signals and timing information, is provided in the HCS12 V1.5 Core Integration Guide.

7.1 Core Interface Overview

The Core is designed to be integrated into a SoC design as a fully synthesizable block. The Core interface is shown in

Figure 7-1

below with the interface signals grouped by function. All signals related to the

internal and I.P. bus interfacing appear on the right side of the Core block in the diagram. In addition to bus interfacing, the Core receives reset and clock inputs from the system and provides signals for interacting with the CPU for vector request and acknowledge and for functional operation of the stop and wait modes. The Core interacts with the external blocks of the overall system through the port/pad logic for Ports A, B, E (which include the physical IRQ and XIRQ pins) and K and the BDM BKGD pin interfaces. The memory configuration switches shown in the diagram are inputs to the Core block that are tied to a constant logic state at the time of integration into the SoC design to correctly define the on-chip memory configuration for proper Core operation within the system.

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.

Memory Configuration Switches

Resets peri_reset_ta4 reset_pin_ind

Clocks

ECLK

Control

Vector

Request/

Acknowledge

Stop and

Wait Mode

Control/

Status

PLL

BDM

BKGD

Pin

Interface peri_clk2 peri_clk4 peri_clk24 peri_clk34 peri_clk23 peri_phase_oscdX core_eclk_load core_neclk_t2 core_vector_fetch_t4 peri_rstv_request peri_xmonv_request peri_copv_request core_stop_t24 core_wait_t24 core_wakeup_ta peri_cwai_t3 peri_syswai_t3 peri_test_clk_enable peri_test_clk peri_pllsel_t3 bkgd_ind core_bkgd_dout_t4 core_bkgd_obe core_bkgd_ibe_t2 core_bkgdpue_t2

CPU

Central

Processing

Unit

MMC

Module

Mapping

Control

BDM

Background

Debug

Mode

MEBI

Multiplexed External Bus Interface

INT

Interrupt

BKP

Breakpoint core_ramregsel_t2 core_ramarraysel_t2 core_ramhal_t2 ram_rdb_L12[15:0] core_eeregsel_t2 core_eearraysel_t2

On-Chip

RAM

Interface

On-Chip

EEPROM

Interface ee_rdb_L12[15:0] ee_hold_t1 core_feeregsel_t2 core_feearraysel_t2 fee_rdb_L12[15:0] fee_hold_t1

On-Chip

Flash

EEPROM

Interface core_ab_t2[19:0] core_wdb_t4[15:0] core_rw_t2 core_sz8_t2

Common Bus

Interface

Signals

(Memory and

Peripherals) core_exp_t2 core_per_t2 core_smod_t2 core_perisel_t2 core_bdmact_t4 ipt_scan_mode core_secure_t2 secreq peri_rdb_L12[15:0] peri_ffxx_t3 peri_rtifff0i_t3

Scan Control

Security

Peripheral

Bus Only

Interface

Signals

Port A[7:0]

Interface

Port B[7:0]

Interface

Port E[7:0]

Interface

Figure 7-1 Core Interface Signals

Port K[7:0]

Interface

7.1.1 Signal Summary

A brief summary of the Core interface signals is given in

Table 7-1

below. For detailed descriptions and timing information please consult the HCS12 V1.5 Core Integration Guide.

Table 7-1 Core Interface Signal Definitions

Signal Name

core_ab_t2[19:0] peri_rdb_L12[15:0] ram_rdb_L12[15:0] ee_rdb_L12[15:0] fee_rdb_L12[15:0] core_wdb_t4[15:0] core_rw_t2

Type Functional Description

Internal Bus Interface Signals

O Core 16-bit Address Bus [19:0]

I

I

I 16-bit Read Data Bus data from Peripheral block

I 16-bit Read Data Bus data from on-chip RAM array

16-bit Read Data Bus data from on-chip EEPROM array

16-bit Read Data Bus data from on-chip Flash EEPROM or ROM array

O Core 16-bit Write Data Bus [15:0]

O Core Read/Write signal - active low Write

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Signal Name

core_sz8_t2 core_exp_t2 core_per_t2 core_smod_t2 core_secure_t2 core_perisel_t2 core_ramregsel_t2 core_ramarraysel_t2 core_ramhal_t2 core_eeregsel_t2 core_eearraysel_t2 core_feeregsel_t2 core_feearraysel_t2 ee_hold_t1 fee_hold_t1 secreq peri_ffxx_t3 peri_rtifff0i_t3 core_bdmact_t4 core_paind[7:0] core_pado[7:0] core_paobe[7:0] core_paibe_t2 core_papue_t2 core_padse_t2 core_pbind[7:0] core_pbdo[7:0] core_pbobe[7:0] core_pbibe_t2 core_pbpue_t2 core_pbdse_t2 core_peind[7:0] core_pedo[7:0] core_peobe[7:0] core_peibe_t2 core_pepue_t2 core_mdrste core_pedse_t2

Table 7-1 Core Interface Signal Definitions

Type

O

Functional Description

Core bus data size requested signal

0 - 16-bit access

1 - 8-bit access

O Expanded Mode selected signal

O Peripheral Test Mode selected signal

O Special Mode selected signal

O Core secure mode signal

O Core peripheral select to I.P. Bus Interface

O On-chip RAM Register select from Core to memory and/or bus

O On-chip RAM Array select from Core to memory and /or bus

O On-chip RAM Array align signal from Core to memory and/or bus

O On-chip EEPROM Register select from Core to memory and/or bus

O On-chip EEPROM Array select from Core to memory and/or bus

O

O

On-chip Flash EEPROM Register select from Core to memory and/or bus

On-chip Flash EEPROM Array select from Core to memory and/or bus

I

I

I

I On-chip EEPROM signal to Core to suspend CPU operation

On-chip Flash EEPROM signal to Core to suspend CPU operation

Security mode request from applicable memory

Interrupt Bus from I.P. Bus Interface

I Real Time Interrupt signal

O Core BDM active signal for I.P. Bus Interface (freeze signal)

External Bus Interface Signals

I Port A input data [7:0]

O Port A data output [7:0]

O Port A output buffer enable [7:0]

O Port A input buffer enable

O Port A pullup enable

O Port A drive strength enable

I Port B input data [7:0]

O Port B data output [7:0]

O Port B output buffer enable [7:0]

O Port B input buffer enable

O Port B pullup enable

O Port B drive strength enable

I

Port E input data [7:0]

NOTE: PE1 is IRQ pin input; PE0 is XIRQ pin input.

O Port E data output [7:0]

O Port E output buffer enable [7:0]

O Port E input buffer enable

O Port E pullup enable

O Enable signal for EBI Mode pin pullups at the pad

O Port E drive strength enable

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Table 7-1 Core Interface Signal Definitions

Signal Name

core_pkind[7:0] core_pkdo[7:0] core_pkobe[7:0] core_pkibe_t2 core_pkpue_t2 core_pkdse_t2 core_vector_fetch_t4 peri_rstv_request peri_xmonv_request peri_copv_request

Type

I

Functional Description

Port K input data [7:0]

O Port K data output [7:0]

O Port K output buffer enable [7:0]

O Port K input buffer enable

O Port K pullup enable

O Port K drive strength enable

Clock and Reset Signals

See Section 8 of this guide.

Vector Request/Acknowledge Signals

O Core CPU vector request

I

I System level reset vector request

I System level Crystal Monitor reset vector request

System level COP Watchdog reset vector request

Stop and Wait Mode Control/Status Signals

See Section 8 of this guide.

bkgd_ind core_bkgd_dout_t4 core_bkgd_obe core_bkgd_ibe_t2 core_bkgdpue_t2

Background Debug Mode (BDM) Interface Signals

I BDM BKGD pin input data

O Data output for BDM BKGD pin

O BDM BKGD pin output buffer enable

O BDM BKGD pin input buffer enable

O BDM BKGD pin pullup enable reg_sw0 pag_sw1 pag_sw0 ram_fmts ram_sw2 ram_sw1 ram_sw0 eep_sw1 eep_sw0 rom_sw1 rom_sw0 I

I

I

I

I

I

I

I

I

I

I

Memory Configuration Signals

Register space size select switch to be tied to the appropriate logic level at system integration:

0 - 1K byte register space aligned to lower address

1 - 2K byte register space.

On-chip memory size select switch bit 1 to be tied to the appropriate logic level at system integration.

On-chip memory size select switch bit 0 to be tied to the appropriate logic level at system integration.

On-chip RAM fast memory transfer select to be tied to the appropriate logic level at system integration.

On-chip RAM size select switch bit 2 to be tied to the appropriate logic level at system integration.

On-chip RAM size select switch bit 1 to be tied to the appropriate logic level at system integration.

On-chip RAM size select switch bit 0 to be tied to the appropriate logic level at system integration.

On-chip EEPROM size select switch bit 1 to be tied to the appropriate logic level at system integration.

On-chip EEPROM size select switch bit 0 to be tied to the appropriate logic level at system integration.

On-chip Flash EEPROM or ROM size select switch bit 1 to be tied to the appropriate logic level at system integration.

On-chip Flash EEPROM or ROM size select switch bit 0 to be tied to the appropriate logic level at system integration.

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Signal Name

romon_exp_state ipt_scan_mode

Table 7-1 Core Interface Signal Definitions

Type Functional Description

Reset state of the ROMON bit in the MISC Register to be tied to the appropriate literal logic level at system integration (i.e. tied level is the state out of reset and not inverted).

I

Scan Control Interface Signals

Scan mode select signal

7.2 Signal Descriptions

General descriptions of the Core interface signals are given in the subsections below. The clock, reset and wait and stop mode signals are discussed in

Section 8

of this guide. For detailed descriptions of these

signals including timing information please consult the HCS12 V1.5 Core Integration Guide.

7.2.1 Internal Bus Interface Signals

These descriptions apply to the Core signals that interface with the on-chip memories either directly or through the Core bus and with the system peripheral blocks through the I.P. Bus Interface.

7.2.1.1 Core 20-bit Address Bus (core_ab_t2[19:0])

This 20-bit wide Core output provides the Core Address Bus to the system memory and peripheral blocks.

7.2.1.2 16-bit Read Data Bus from system peripheral blocks (peri_rdb_L12[15:0])

16-bit wide Read Data Bus input to the Core from the system peripherals via the I.P. Bus Interface block.

7.2.1.3 16-bit Read Data Bus from on-chip RAM (ram_rdb_L12[15:0])

16-bit wide Read Data Bus input to the Core from the on-chip RAM memory block.

7.2.1.4 16-bit Read Data Bus from on-chip EEPROM (ee_rdb_L12[15:0])

16-bit wide Read Data Bus input to the Core from the on-chip EEPROM memory block.

7.2.1.5 16-bit Read Data Bus from on-chip Flash EEPROM or ROM (fee_rdb_L12[15:0])

16-bit wide Read Data Bus input to the Core from the on-chip Flash EEPROM or ROM memory block.

7.2.1.6 Core 16-bit Write Data Bus (core_wdb_t4[15:0])

This 16-bit wide Core output provides the Core Write Data Bus to the system memory and peripheral blocks.

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7.2.1.7 Core Read/Write signal (core_rw_t2)

This single bit Core output indicates the direction of bus access (read or write with write being active low) by the Core.

7.2.1.8 Core bus data size request indicator (core_sz8_t2)

This single bit Core output indicates the size of data (8-bit or 16-bit when high or low, respectively) being read/written by a Core bus access.

7.2.1.9 Core Expanded Mode indicator (core_exp_t2)

This single bit Core output indicates that the Core is in Expanded Mode (i.e. the Core has been configured in one of the expanded modes via the MODE pins)

7.2.1.10 Core Peripheral Test Mode indicator (core_per_t2)

This single bit Core output indicates that the Core is in Peripheral Test Mode. In this mode, the cpu is disabled and the direction of the bus interface is switched such that the on-chip peripherals can be addressed directly. This mode is used for factory test only.

7.2.1.11 Core Special Mode indicator (core_smod_t2)

This single bit Core output indicates that the Core is in Special Mode (i.e. the Core has been configured in

Special Mode via the MODE pins)

7.2.1.12 Core Secure Mode indicator (core_secure_t2)

This single bit Core output indicates that the Core is operating in secured mode. Please see

Section 15

of this guide for functional details.

7.2.1.13 Peripheral select signal (core_perisel_t2)

This single bit Core output indicates that the Core is accessing an address within the peripheral space of the system memory map.

7.2.1.14 On-Chip RAM register space select signal (core_ramregsel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip RAM register space of the system memory map.

7.2.1.15 On-Chip RAM array select signal (core_ramarraysel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip RAM array space of the system memory map.

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7.2.1.16 On-Chip RAM array align signal (core_ramhal_t2)

This single bit Core output reflects the state of the RAMHAL bit in the INITRAM register within the

Module Mapping Control (MMC) sub-block of the Core. Please see

Section 11

of this guide for further functional details.

7.2.1.17 On-Chip EEPROM register select signal (core_eeregsel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip EEPROM register space of the system memory map.

7.2.1.18 On-Chip EEPROM array select signal (core_eearraysel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip EEPROM array space of the system memory map.

7.2.1.19 On-Chip Flash EEPROM register select signal (core_feeregsel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip Flash

EEPROM register space of the system memory map.

7.2.1.20 On-Chip Flash EEPROM array select signal (core_feearraysel_t2)

This single bit Core output indicates that the Core is accessing an address within the on-chip Flash

EEPROM array space of the system memory map.

7.2.1.21 On-Chip EEPROM hold signal to Core (ee_hold_t1)

This single bit input to the Core is used to suspend operation of the CPU when needed for functions of the on-chip EEPROM memory block.

7.2.1.22 On-Chip Flash EEPROM hold signal to Core (fee_hold_t1)

This single bit input to the Core is used to suspend operation of the CPU when needed for functions of the on-chip Flash EEPROM memory block.

7.2.1.23 Core Security Request (secreq)

This single bit input indicates to the Core that the system memory is in a secured state and that the Core should operate in secured mode. Please see

Section 15

for functional details.

7.2.1.24 56-bit Interrupt request signals from peripheral block to Core (peri_ffxx_t3)

This 56-bit wide input to the Core provides the Core with the Interrupt request signals from all the system interrupt sources via the I.P. Bus Interface.

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7.2.1.25 System Real Time Interrupt request (peri_rtifff0i_t3)

This input signal indicates to the Core that the system is requesting the interrupt vector for a Real Time

Interrupt (RTI) from the Core.

7.2.1.26 Background Debug Mode active indicator (core_bdmact_t4)

This single bit output from the Core indicates that the Background Debug Mode (BDM) is active.

7.2.2 External Bus Interface Signals

These descriptions apply to the interface signals between the Core and the system External Bus Interface pad logic. Please see

Section 12

of this guide for further functional details of the External Bus Interface.

7.2.2.1 Port A Input Data to Core (core_paind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port A.

7.2.2.2 Port A Output Data from Core (core_pado[7:0])

This 8-bit wide output from the Core provides the Port A data output to the system port/pad logic for Port

A.

7.2.2.3 Port A output buffer enable from Core (core_paobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port A.

7.2.2.4 Port A input buffer enable from Core (core_paibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port A.

7.2.2.5 Port A pullup enable from Core (core_papue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port A should be enabled for all Port A pins.

7.2.2.6 Port A drive strength enable from Core (core_padse_t2)

This single bit output from the Core indicates whether all Port A pins will operate with full or reduced drive strength.

7.2.2.7 Port B Input Data to Core (core_pbind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port B.

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7.2.2.8 Port B Output Data from Core (core_pbdo[7:0])

This 8-bit wide output from the Core provides the Port B data output to the system port/pad logic for Port

B.

7.2.2.9 Port B output buffer enable from Core (core_pbobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port B.

7.2.2.10 Port B input buffer enable from Core (core_pbibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port B.

7.2.2.11 Port B pullup enable from Core (core_pbpue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port B should be enabled for all Port B pins.

7.2.2.12 Port B drive strength enable from Core (core_pbdse_t2)

This single bit output from the Core indicates whether all Port B pins will operate with full or reduced drive strength.

7.2.2.13 Port E Input Data to Core (core_peind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port E. When the system has an external IRQ pin implemented, the input signal from the IRQ pin pad logic must be tied to Port E Input Data Bit 1. Likewise, when the system has an external XIRQ pin implemented, the input signal from the XIRQ pin pad logic must be tied to Port E Input Data Bit 0. Both the IRQ and

XIRQ signals are active low (i.e. their asserted state is logic 0).

7.2.2.14 Port E Output Data from Core (core_pedo[7:0])

This 8-bit wide output from the Core provides the Port E data output to the system port/pad logic for Port E.

7.2.2.15 Port E output buffer enable from Core (core_peobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port E.

7.2.2.16 Port E input buffer enable from Core (core_peibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port E.

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7.2.2.17 Port E pullup enable from Core (core_pepue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port E should be enabled for all Port E pins except the MODA (PE5) and MODB (PE6) pins.

7.2.2.18 Port E MODE pin pullup enable from Core (core_mdrste)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for the MODA (PE5) and MODB (PE6) pins within Port E should be enabled.

7.2.2.19 Port E drive strength enable from Core (core_pedse_t2)

This single bit output from the Core indicates whether all Port E pins will operate with full or reduced drive strength.

7.2.2.20 Port K Input Data to Core (core_pkind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port K.

7.2.2.21 Port K Output Data from Core (core_pkdo[7:0])

This 8-bit wide output from the Core provides the Port K data output to the system port/pad logic for Port

K.

7.2.2.22 Port K output buffer enable from Core (core_pkobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port K.

7.2.2.23 Port K input buffer enable from Core (core_pkibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port K.

7.2.2.24 Port K pullup enable from Core (core_pkpue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port K should be enabled for all Port K pins.

7.2.2.25 Port K drive strength enable from Core (core_pkdse_t2)

This single bit output from the Core indicates whether all Port K pins will operate with full or reduced drive strength.

7.2.3 Clock and Reset Signals

Please see

Section 8

of this guide.

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7.2.4 Vector Request/Acknowledge Signals

These descriptions apply to signals that provide for vector requesting to and corresponding acknowledgment from the Core.

7.2.4.1 CPU vector fetch (core_vector_fetch_t4)

This Core output signal indicates that the CPU is executing a vector fetch as a result of a reset or interrupt sequence.

7.2.4.2 System level reset vector request (peri_rstv_request)

This input signal indicates to the Core that the system is requesting the external reset vector from the Core.

7.2.4.3 System level Crystal Monitor reset vector request (peri_xmonv_request)

This input signal indicates to the Core that the system is requesting the Crystal Monitor reset vector from the Core.

7.2.4.4 System level COP Watchdog reset vector request (peri_copv_request)

This input signal indicates to the Core that the system is requesting the COP Watchdog reset vector from the Core.

7.2.5 Stop and Wait Mode Control/Status Signals

Please see

Section 8

of this guide.

7.2.6 Background Debug Mode (BDM) Interface Signals

These descriptions apply to the Core BDM sub-block interface with the system BKGD pad logic. Please see

Section 14

of this guide for further functional details of the BDM.

7.2.6.1 BKGD pin Input Data to Core (bkgd_ind)

This single bit input to the Core provides the Core with the input data from the system port/pad logic for

BDM BKGD pin.

7.2.6.2 BKGD pin Output Data from Core (core_bkgd_dout_t4)

This single bit output from the Core provides the BKGD pin data output to the system port/pad logic for the BDM BKGD pin.

7.2.6.3 BKGD pin output buffer enable from Core (core_bkgd_obe)

This single bit output from the Core provides the output buffer enable signal to the system port/pad logic for the BDM BKGD pin.

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7.2.6.4 BKGD pin input buffer enable from Core (core_bkgd_ibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for the BDM BKGD pin.

7.2.6.5 BKGD pin pullup enable from Core (core_bkgdpue_t2)

This single bit output from the Core indicates that the pullup device within the system port/pad logic for the BKGD pin should be enabled for the BKGD pin.

7.2.7 Memory Configuration Signals

These input signals to the Core establish the system memory configuration. Each of these signals is to be tied off to the appropriate logic state at integration of the Core into the SoC design in order to configure the Core memory partitioning according to the needs of the system. Please consult the HCS12 V1.5 Core

Integration Guide for details on defining the states of these signals.

7.2.8 Scan Control Interface Signals

These descriptions apply to the Core Scan test control signals.

7.2.8.1 Scan mode enable(ipt_scan_mode)

This single bit input indicates to the Core that the system is in Scan test mode and all logic within the Core that needs special conditions for Scan test mode will be handled appropriately.

7.3 Interface Operation

The subsections below give general descriptions of basic read and write operations of the Core. These operations include interfacing with system peripheral registers, on-chip memory registers and array elements, internal Core registers and external bus interface. For more detailed descriptions and timing information please consult the HCS12 V1.5 Core Integration Guide.

7.3.1 Read Operations

All read data coming into the Core is implemented by multiplexing the various input read data buses

(peri_rdb_L12[15:0], ram_rdb_L12[15:0], ee_rdb_L12[15:0] and fee_rdb_L12[15:0]) onto the main internal Core read data bus. The active input read data bus is defined by the select signal that is active during the Core read cycle. The subsections below briefly discuss each of peripheral, on-chip memory register and array element and internal core register reads. In each of the figures used in these subsections, the read sequences are separated by write sequences to better illustrate the timing edges.

7.3.1.1 Peripheral Reads

The Core supports both 8-bit and 16-bit reads of peripheral registers. The timing relationship for a basic

8-bit read of a peripheral register is shown in

Figure 7-2

and that of a basic 16-bit read in

Figure 7-3

.

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The Core clock (peri_clk24) provides the timing reference within the Core for all data transfers with the peripherals. The peripheral clock (peri_clk34) is the timing reference for all peripherals within the system tied to the I.P. Bus.

peri_clk24 core_ab_t2 addr0

T2 T3 T4 T1 T2 addr1 data0 peri_rdb_L12 core_perisel_t2 core_rw_t2 core_sz8_t2 peri_clk34

8_BIT data1 addr2

8_BIT data2 addr3 data3

Figure 7-2 Basic 8-bit Peripheral Read Timing

8_BIT peri_clk24 core_ab_t2 addr0

T2 T3 T4 T1 T2 addr1 data0 peri_rdb_L12 core_perisel_t2 core_rw_t2 core_sz8_t2 peri_clk34

16_BIT data1 addr2

16_BIT data2 addr3 data3

16_BIT

Figure 7-3 Basic 16-bit Peripheral Read Timing

7.3.1.2 Memory Reads

The timing relationship for a basic 8-bit read of a on-chip memory register or array byte by the Core is shown in below in

Figure 7-4

and that of a basic 16-bit read in

Figure 7-5

. In the diagrams, the

MEM_rdb_L12 signal represents any of the on-chip memory read data bus signals (ram_rdb_L12,

ee_rdb_L12 or fee_rdb_L12) and core_MSEL_t2 represents any of the on-chip memory register or array selects (such as core_ramregsel_t2 or core_ramarraysel_t2 for the RAM and likewise for the EEPROM and Flash EEPROM).

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peri_clk24 core_ab_t2 addr0

T2 T3 T4 T1 T2 addr1 data0 MEM_rdb_L12 core_MSEL_t2 core_rw_t2 core_sz8_t2 peri_clk34

8_BIT data1 addr2

8_BIT data2 addr3 data3

Figure 7-4 Basic 8-bit Memory Read Timing

8_BIT peri_clk24 core_ab_t2 addr0

T2 T3 T4 T1 T2 addr1 data0 MEM_rdb_L12 core_MSEL_t2 core_rw_t2 core_sz8_t2 peri_clk34

16_BIT data1 addr2

16_BIT data2 addr3 data3

16_BIT

Figure 7-5 Basic 16-bit Memory Read Timing

7.3.1.3 Internal Core Register Reads

The timing for basic 8-bit and 16-bit reads of internal Core registers are shown in

Figure 7-6

and

Figure

7-7

, respectively.

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peri_clk24 core_ab_t2 addr0

T2 T3 T4 T1 T2 addr1 rdb_t4 core_RSEL_t4 data0 data1 core_rw_t2 core_sz8_t2 addr2 data2

Figure 7-6 Basic 8-bit Core Register Read Timing

addr3 data3 peri_clk24 T2 T3 T4 T1 T2 core_ab_t2 addr0 rdb_t4 data0 addr1 data1 core_RSEL_t4 core_rw_t2 core_sz8_t2 addr2 data2 addr3 data3

Figure 7-7 Basic 16-bit Core Register Read Timing

7.3.2 Write Operations

All write data exits the Core via the Core write data bus (core_wdb_t4[15:0]). The subsections below briefly discuss each of peripheral, on-chip memory register and array element and internal core register writes. In each of the figures used in these subsections, the write sequences are separated by read sequences to better illustrate the timing edges.

7.3.2.1 Peripheral Writes

The Core supports both 8-bit and 16-bit writes of peripheral registers. The timing relationship for a basic

8-bit write of a peripheral register is shown in

Figure 7-8

and that of a basic 16-bit write in

Figure 7-9

.

An example of the I.P. Bus read data bus timing is provided in the figures for further illustration purposes.

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peri_clk24 core_ab_t2 core_wdb_t4 ipb_rdb core_perisel_t2 core_rw_t2 core_sz8_t2 peri_clk34

T2 T3 T4 T1 T2 addr1 data1 data1 addr2 data2 data2 addr3 data3 data3

8_BIT 8_BIT

Figure 7-8 Basic 8-bit Peripheral Write Timing

peri_clk24 core_ab_t2 core_wdb_t4 ipb_rdb core_perisel_t2 core_rw_t2 core_sz8_t2 peri_clk34

T2 T3 T4 T1 T2 addr1 data1 data1 addr2 data2 data2 addr3 data3 data3

16_BIT 16_BIT

Figure 7-9 Basic 16-bit Peripheral Write Timing

7.3.2.2 Memory Writes

The timing relationship for a basic 8-bit write of a on-chip memory register or array byte by the Core is shown in below in

Figure 7-10

and that of a basic 16-bit write in

Figure 7-11

. As before, the

MEM_rdb_L12 signal represents any of the on-chip memory read data bus signals (ram_rdb_L12,

ee_rdb_L12 or fee_rdb_L12) and core_MSEL_t2 represents any of the on-chip memory register or array selects (such as core_ramregsel_t2 or core_ramarraysel_t2 for the RAM and likewise for the EEPROM and Flash EEPROM).

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peri_clk24 core_ab_t2 core_wdb_t4 core_MSEL_t2 core_rw_t2 core_sz8_t2 peri_clk34

T2 T3 T4 T1 T2 addr1

8_BIT data1 addr2 data2

8_BIT

Figure 7-10 Basic 8-bit Memory Write Timing

addr3 data3 peri_clk24 core_ab_t2 core_wdb_t4 core_MSEL_t2 core_rw_t2 core_sz8_t2 peri_clk34

T2 T3 T4 T1 T2 addr1 data1

16_BIT addr2 data2

16_BIT addr3 data3

Figure 7-11 Basic 16-bit Memory Write Timing

7.3.2.3 Internal Core Register Writes

The timing for basic 8-bit and 16-bit writes of internal Core registers are shown in

Figure 7-12

and

Figure 7-13

, respectively.

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peri_clk24 core_ab_t2 core_wdb_t4 core_RSEL_t4 core_rw_t2 core_sz8_t2

T2 T3 T4 T1 T2 addr1 data1 addr2 data2 addr3 data3

Figure 7-12 Basic 8-bit Core Register Write Timing

peri_clk24 core_ab_t2 core_wdb_t4 core_RSEL_t2 core_rw_t2 core_sz8_t2

T2 T3 T4 T1 T2 addr1 data1 addr2 data2 addr3 data3

Figure 7-13 Basic 16-bit Core Register Write Timing

7.3.3 Multiplexed External Bus Interface

A timing diagram of the multiplexed external bus is shown in . Major bus signals are included in the

diagram. While both a data write and data read cycle are shown, only one would occur on a particular bus

cycle. Table 7-2 gives the preliminary timing characteristics for the signals illustrated in .

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ECLK

5

10

Addr/Data

(read) data

Addr/Data

(write) data

16

2

1

3

7 addr

22

8

23

9 addr

13

17

11 data data

15

R/W

19 20

LSTRB

26 27

12

14

18

21

28 29

CS

Figure 7-14 General External Bus Timing

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10

11

12

13

14

8

9

5

6

7

16

17

18

19

20

21

Num

28

29

1

2

3

15

22

23

26

27

Table 7-2 Multiplexed Expansion Bus Timing - Preliminary Targets

Characteristic

1 2 3

Symbol

Frequency of operation (E-clock)

Cycle time

Pulse width, E low

Pulse width, E high

Address delay time n/a

4

Address valid time to E rise (PW

Muxed address hold time

Address hold to data valid

Data hold to address

Read data setup time

Read data hold time

Write data delay time

Write data hold time

EL

-T

AD

) t

DSR t

DHR t

DDW t

DHW t

AV t

MAH t

AHDS t

DHA

Write data setup time

4

(PW

EH

-t

DDW

) t

DSW

Read/write delay time t

RWD

Read/write valid time to E rise (PW

EL

-t

RWD

) t

RWV

Read/write hold time

Low strobe delay time

Low strobe valid time to E rise (PW

Low strobe hold time

EL

-t

LSD

) t

RWH t

LSD t

LSV t

LSH

Address access time

4

(t cyc

-t

AD

-t

DSR

)

E high access time

4

(PW

EH

-t

DSR

)

Chip select delay time t t t

ACCA

ACCE

CSD

Chip select access time

4

(t cyc

-t

CSD

-t

DSR

) t

ACCS

Chip select hold time

Chip select negated time t

CSH t

CSN f o t cyc

PW

EL

PW

EH t

AD n/a

16 MHz

Min Max

20 MHz

Min Max

25 MHz

Min Max

D.C.

16.0

D.C.

20.0

D.C.

25.0

62

28

50

22

40

18

28

16

2

4

14

0

2

16

16

2

16

2

36

14

26

12

12

5

12

12

12

22

1

22

12

2

3

10

0

2

12

12

2

12

2

30

12

22

10

10

4

10

10

10

18

1

18

10

1

2

10

1

10

1

8

0

1

10

24

10

17

8

8

3

8

8

8

15

1

Unit

ns ns ns ns ns ns ns ns

MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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NOTES:

1. Crystal input is required to be within 45% to 55% duty.

2. Reduced drive must be off to meet these timings.

3. Unequal loading of pins will affect relative timing numbers.

4. Affected by clock stretch: add N x t cyc

where N=0,1,2 or 3, depending on the number of clock stretches.

7.3.4 General Internal Read Visibility Timing

Internal writes have the same timing as external writes. Internal read visibility is shown in Figure 7-15 and Table 7-3 shows the associated timing numbers.

1

2 3

ECLK

ADDR

31

Muxed

Addr/Data

(read) data addr

32

IVIS data

Figure 7-15 General Internal Read Visibility Timing

Num

Table 7-3 Expansion Bus Timing - Preliminary Targets

Characteristic

1 2 3

Symbol

Frequency of operation (E-clock)

Cycle time 1

2 Pulse width, E low

3

Pulse width, E high

4

31RG IVIS read data set-up time - Registers

31RM IVIS read data set-up time - RAM

31EE

IVIS read data set-up time -

EEPROM

31FL

IVIS read data set-up time - FLASH

5 f o t cyc

PW

EL

PW

EH

62

28

28

11

11

16 MHz 20 MHz 25 MHz

Min Max Min Max Min Max

Unit

D.C.

16.0

D.C.

20.0

D.C.

25.0

MHz

50

22

22

5

5

40

18

18

2

2 ns ns ns ns ns

11

6

5

0

2

0 ns ns

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Table 7-3 Expansion Bus Timing - Preliminary Targets

Num

Characteristic

1 2 3

Symbol 16 MHz 20 MHz 25 MHz

32 IVIS read data hold time (all) 2 2 1

NOTES:

1. Crystal input is required to be within 45% to 55% duty.

2. Reduced drive must be off to meet these timings.

3. Unequal loading of pins will affect relative timing numbers.

4. Affected by clock stretch: add N x t cyc

where N=0,1,2 or 3, depending on the number of clock stretches.

5. Timing is tighter than other memories due to larger array size.

7.3.5 Detecting Access Type from External Signals

Unit

ns

The external signals LSTRB, R/W, and A0 indicate the type of bus access that is taking place. Accesses to the internal RAM are the only type of access that would produce LSTRB=A0=1 because the internal

RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases, the data for the address that was accessed is on the low half of the data bus and the data for address+1 is on the high half of the data bus. This operation only occurs when internal visibility is on.

Table 7-4 shows the relationship between these signals and the type of access.

Table 7-4 Access Type vs. Bus Control Pins

LSTRB

1

0

1

0

0

1

0

1

0

1

0

A0

0

1

1

0

1

0

0

1

R/W

1

1

1

0

0

Type of Access

8-bit read of an even address

8-bit read of an odd address

8-bit write of an even address

8-bit write of an odd address

16-bit read of an even address

16-bit read of an odd address

(low/high data swapped)

16-bit write to an even address

16-bit write to an odd address

(low/high data swapped)

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Section 8 Core Clock and Reset Connections

This section details the HCS12 V1.5 Core external clock connections. In addition, this section will discuss the reset timing needs of the Core since this is associated very closely with the external clocking requirements.

8.1 Clocking Overview

The HCS12 V1.5 Core is implemented as a single clock source design with complete Mux-D scan test implementation. Since the Core is compatible with the feature set of the MHC12 microcontroller product family, many signal and timing requirements exist for the system clock and reset generation block(s) to support these features. Many of these requirements are driven by the interaction of the Core with the clock and reset generation block(s) in the system due to CPU wait and stop mode functionality and the various time based reset and interrupt functions (such as Crystal Monitor and COP Watchdog resets and Real Time

Interrupt functions) available on the HCS12 family of products. A diagram of the Core interface signals is given in

Figure 8-1

below.

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Memory Configuration Switches

Resets peri_reset_ta4 reset_pin_ind

Clocks

ECLK

Control

Vector

Request/

Acknowledge

Stop and

Wait Mode

Control/

Status

PLL

BDM

BKGD

Pin

Interface peri_clk2 peri_clk4 peri_clk24 peri_clk34 peri_clk23 peri_phase_oscdX core_eclk_load core_neclk_t2 core_vector_fetch_t4 peri_rstv_request peri_xmonv_request peri_copv_request core_stop_t24 core_wait_t24 core_wakeup_ta peri_cwai_t3 peri_syswai_t3 peri_test_clk_enable peri_test_clk peri_pllsel_t3 bkgd_ind core_bkgd_dout_t4 core_bkgd_obe core_bkgd_ibe_t2 core_bkgdpue_t2

CPU

Central

Processing

Unit

MMC

Module

Mapping

Control

BDM

Background

Debug

Mode

MEBI

Multiplexed External Bus Interface

INT

Interrupt

BKP

Breakpoint core_ramregsel_t2 core_ramarraysel_t2 core_ramhal_t2 ram_rdb_L12[15:0] core_eeregsel_t2 core_eearraysel_t2

On-Chip

RAM

Interface

On-Chip

EEPROM

Interface ee_rdb_L12[15:0] ee_hold_t1 core_feeregsel_t2 core_feearraysel_t2 fee_rdb_L12[15:0] fee_hold_t1

On-Chip

Flash

EEPROM

Interface core_ab_t2[19:0] core_wdb_t4[15:0] core_rw_t2 core_sz8_t2

Common Bus

Interface

Signals

(Memory and

Peripherals) core_exp_t2 core_per_t2 core_smod_t2 core_perisel_t2 core_bdmact_t4 ipt_scan_mode core_secure_t2 secreq peri_rdb_L12[15:0] peri_ffxx_t3 peri_rtifff0i_t3

Scan Control

Security

Peripheral

Bus Only

Interface

Signals

Port A[7:0]

Interface

Port B[7:0]

Interface

Port E[7:0]

Interface

Figure 8-1 Core Interface Signals

Port K[7:0]

Interface

The Core interfaces with the system clock and reset generation block(s) in order to synchronize the actions of the HCS12 CPU with the rest of the system. Through the interface signals, the Core supports the use of a system Phase-Locked Loop (PLL), Crystal Monitor, COP Watchdog and Real Time Interrupt as well as clocking options during CPU wait and stop modes. Each of these aspects are discussed in the subsections that follow.

8.1.1 Basic Clock Relationship

The basic system clock timing in shown in

Figure 8-2

below. The system clock generation block is required to provide the main Core clocks (peri_clk24, peri_clk2, and peri_clk4), the main peripheral clock

(peri_clk34) and the system clk23 (peri_clk23) to the Core (the Core uses peri_clk23 to generate the ECLK signal). The method of clock generation (i.e. crystal, PLL, etc.) is left up to the system integrator as long as the clocks provided meet the phase relationship shown in the figure.

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peri_clk24 peri_clk34 peri_clk23 peri_clk2 peri_clk4

T2 T3 T4 T1 T2

T3 T4

T3T4 T1T2

T2T3 T4T1

T2 T2

T4 T4

Figure 8-2 System Clock Timing Diagram

The remaining clock input to the Core, peri_phase_oscdX, is the same frequency as the peri_clk34 as derived directly from the oscillator. When using the PLL for the system clocks, the BDM sub-block must maintain a constant rate clock and cannot depend upon the use of the PLL generated clock. Because of this, this signal operates at the same frequency as peri_clk34 prior to engaging the PLL (or as derived directly from the oscillator). Once the PLL is engaged, this clock must maintain the pre-PLL frequency in order to keep the BDM synchronized.

8.1.2 Reset Relationship

The Core depends upon the use of two input signals, reset_pin_ind and peri_reset_ta4, for controlling the reset conditions of all logic within the Core. The active low reset_pin_ind signal timing follows that of the physical system reset pin indicating immediately when a system reset is requested (for example when the

RESET pin is pulled low externally). This signal is used as a load enable on the MODE pins of the MEBI sub-block to ensure that the Core mode of operation is known and set up immediately upon a system reset request. The peri_reset_ta4 signal will generally be asserted (logic 1) asynchronously by the reset generation block at the time that a system reset is requested. Further, the assumption is that this signal will stay asserted until such time that the clock generation block has determined that the clocks to the Core are stable and that the Core should proceed with a system reset sequence.

8.1.3 Phase-Locked Loop Interface

The Core allows for the implementation of a on-chip Phase-Locked Loop (PLL) and interacts with it through the peri_pllsel_t3, peri_test_clk_enable and peri_test_clk input signals. If a PLL is implemented, the Core assumes it will operate on the peripheral clock (peri_clk34) and thus the peri_pllsel_t3 signal must be asserted (logic 1) on the phase three rising edge of this clock when the PLL is first engaged and to be negated (logic 0) when the PLL is disabled. The peri_test_clk and peri_test_clk_enable signals are provided in order to facilitate test features for the PLL. When the peri_test_clk_enable signal is asserted

(logic 1), the Core will register the signal on the phase four rising edge of peri_clk24 and will then output the clock signal being input on peri_test_clk directly on Port E Bit 6 of the system. This test feature is only valid in Special modes and setting of the PIPOE bit in the PEAR register overrides the clock output.

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8.1.4 HCS12 CPU Wait and Stop Modes

The Core inputs peri_cwai_t3 and peri_syswai_t3 indicate to the Core what the state of the system clocks will be during CPU wait mode with the former reflecting the Core clock (peri_clk24) state and the latter the state of all system clocks. These inputs typically come from the clock and reset generation block(s) and could either be hard-wired to a given logic value or reflect the state of software bits controlling the clock functionality. The Core assumes that the asserted (logic 1) state indicates that the clock(s) will cease during wait mode and that the negated (logic 0) state indicates that the clock(s) will run during wait mode.

The Core will reflect the CPU mode through the state of the core_wait_t24 and core_stop_t24 signals. The

core_wait_t24 or core_stop_t24 signal will assert when the CPU executes a WAI or STOP instruction, respectively, and both will remain negated (logic 0) during normal operation. In the case of exit from either wait or stop mode due to a valid interrupt, the core_wakeup_ta signal will assert (logic 1) asynchronously upon receiving the valid interrupt request. This signal will then negate (logic 0) asynchronously once the interrupt source is negated (indicating that the interrupt has been serviced and is no longer being requested).

8.2 Signal Summary

Each of the Core I/O signals that interface with the system clock and reset generation block(s) are listed in

Table 8-1

below with the signal type and a brief functional description for completeness.

Table 8-1 Core Clock and Reset Interface Signals

Signal Name

peri_reset_ta4 reset_pin_ind peri_clk2 peri_clk4 peri_clk24 peri_clk34 peri_clk23 peri_phase_oscdX peri_test_clk_enable peri_test_clk peri_pllsel_t3 core_eclk_load core_neclk_t2 core_stop_t24 core_wait_t24 core_wakeup_ta peri_cwai_t3 peri_syswai_t3

Type Functional Description

I

I

Clock and Reset Signals

System reset signal

I

I

System level reset pin input data

System clock clk2 for Core

I

I

System clock clk4 for Core

System clock clk24 for Core

I

I

System clock clk34 for peripherals on I.P. Bus Interface

System clock clk23 used by Core to generate ECLK

I

I

Oscillator Clock divided by ‘X’

PLL test feature clock enable signal

I

PLL test feature clock signal

PLL selected signal

O External clock load enable signal

O External clock disable signal

Stop and Wait Mode Control/Status Signals

O Core CPU stop mode signal

O Core CPU wait mode signal

O Core wakeup from stop or wait mode due to interrupt

I

Core wait signal: controls whether clk24 runs during CPU wait mode. 0 clk24 runs during wait, 1 - clk24 ceases during wait.

I

System level wait signal: controls whether system clocks run during CPU wait mode. 0 - all clocks run during wait, 1 - no clocks run during wait.

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8.3 Detailed Clock and Reset Signal Descriptions

General descriptions of the Core clock and reset interface signals are given in the subsections below. Also included are the stop and wait mode signals due to the necessary interaction with the clock and reset requirements. For detailed descriptions of these signals including timing information please consult the

HCS12 V1.5 Core Integration Guide.

8.3.1 Clock and Reset Signals

These descriptions apply to system level clock and reset signals needed by the Core.

8.3.1.1 System Reset signal (peri_reset_ta4)

This single bit asynchronous input to the Core indicates the system reset condition.

8.3.1.2 System level reset input data (reset_pin_ind)

This active-low single bit input is used within the Core as a load enable for the MODE pin logic on Port

E of the system.

8.3.1.3 System level clock for the Core (peri_clk2)

This clock input is one of the main clocks for the Core.

8.3.1.4 System level clock for the Core (peri_clk4)

This clock input is one of the main clocks for the Core.

8.3.1.5 System level clock for the Core (peri_clk24)

This clock input is one of the main clocks for the Core.

8.3.1.6 System level clock for peripheral blocks (peri_clk34)

This clock input is the main clock source for all peripheral blocks integrated in the system and accessed by the Core through the I.P. Bus Interface.

8.3.1.7 System ECLK clock (peri_clk23)

This clock input is the main clock source used by the Core to generate the system ECLK.

8.3.1.8 Divided Down System Oscillator Clock (peri_phase_oscdX)

This clock input to the Core is used within the Core by the Background Debug Mode sub-block to keep the BDM synchronized.

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8.3.1.9 System Test Clock enable (peri_test_clk_enable)

This single bit input to the Core indicates that the phase-locked loop (PLL) test clock should be output on the system Port E bit 6 pin when the PIPOE bit is zero.

8.3.1.10 System Test Clock (peri_test_clk)

This clock input to the Core is the PLL test clock.

8.3.1.11 System clock source select signal (peri_pllsel_t3)

This single bit input to the Core indicates whether clocks within the system are derived from the crystal or

PLL.

8.3.1.12 ECLK load enable signal (core_eclk_load)

This single bit output from the Core is the load enable signal for the system external clock, ECLK.

8.3.1.13 ECLK disable signal (core_neclk_t2)

This single bit output from the Core is the disable signal for the system external clock, ECLK.

8.3.2 Stop and Wait Mode Control/Status Signals

These descriptions apply to signals that provide for controlling some of the functionality and status indication of CPU stop and wait modes.

8.3.2.1 CPU stop mode indicator (core_stop_t24)

This Core output signal indicates whether the CPU is in stop mode.

8.3.2.2 CPU wait mode indicator (core_wait_t24)

This Core output signal indicates whether the CPU is in wait mode.

8.3.2.3 Core wakeup indicator for wait and stop mode (core_wakeup_ta)

This asynchronous Core output signal indicates that the CPU has received an interrupt request and is ready to resume normal operation.

8.3.2.4 Core wait signal from system clock generation block (peri_cwai_t3)

This Core input signal indicates to the CPU whether the main Core clock, peri_clk24, will run during CPU wait mode.

8.3.2.5 System level wait signal (peri_syswai_t3)

This Core input signal indicates to the Core whether all system clocks will run during CPU wait mode.

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Section 9 Core Power Connections

This section details the HCS12 V1.5 Core power connections.

9.1 Power Overview

The HCS12 V1.5 Core operates from a single power and a single ground connection.

9.1.1 Power and Ground Summary

The Core requires a single power (typically termed VDD) and a single ground (typically termed VSS) connection that is implicit when integrating into a synthesized design. There are no signals at the Core interface for power and ground.

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Section 10 Interrupt (INT)

This section describes the functionality of the Interrupt (INT) sub-block of the Core.

10.1 Overview

The Interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a nonmaskable Unimplemented Opcode Trap, a nonmaskable software interrupt (SWI) or Background

Debug Mode request, and three system reset vector requests. All interrupt related exception requests are handled by the Interrupt.

10.1.1 Features

• Provides 2 to 122 I bit maskable interrupt vectors ($FF00-$FFF2)

• Provides 1 X bit maskable interrupt vector ($FFF4)

• Provides a nonmaskable Unimplemented Opcode Trap (TRAP) vector ($FFF8)

• Provides a nonmaskable software interrupt (SWI) or Background Debug Mode request vector

($FFF6)

• Provides 3 system reset vectors ($FFFA-$FFFE)

• Determines the appropriate vector and drives it onto the address bus at the appropriate time

• Signals the CPU that interrupts are pending

• Provides control registers which allow testing of interrupts

• Provides additional input signals which prevents requests for servicing I and X interrupts

• Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active, even if XIRQ is masked

• Provides asynchronous path for all I and X interrupts, ($FF00–$FFF4)

• (Optional) Selects and stores the highest priority I interrupt based on the value written into the

HPRIO register

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10.1.2 Block Diagram

A block diagram of the Interrupt sub-block is shown in

Figure 10-1

below.

INT

HPRIO (OPTIONAL)

WRITE DATA BUS

HIGHEST PRIORITY

I-INTERRUPT

INTERRUPTS

XMASK

IMASK

INTERRUPT INPUT REGISTERS

AND CONTROL REGISTERS

READ DATA BUS

WAKEUP

QUALIFIED

INTERRUPTS

RESET FLAGS

VECTOR REQUEST

PRIORITY DECODER

INTERRUPT

PENDING

VECTOR

ADDRESS

Figure 10-1 Interrupt Block Diagram

10.2 Interface Signals

All interfacing with the Interrupt sub-block is done within the Core. The Interrupt does however receive direct input from the Multiplexed External Bus Interface (MEBI) sub-block of the Core for the IRQ and

XIRQ pin data.

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10.3 Registers

A summary of the registers associated with the Interrupt sub-block is shown in

Figure 10-2

below.

Detailed descriptions of the registers and associated bits are given in the subsections that follow.

Address Name

$0015 ITCR read write

Bit 7

0

6

0

5

0

4 3 2 1 Bit 0

WRTINT ADR3 ADR2 ADR1 ADR0

$0016 ITEST read write

INTE INTC INTA INT8 INT6 INT4 INT2

$001F HPRIO read write

PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1

= Unimplemented X = Indeterminate

INT0

0

Figure 10-2 Interrupt Register Summary

10.3.1 Interrupt Test Control Register

Address:$0015

Bit 7

Read:

Write:

0

Reset: 0

6

0

5

0

4 3 2 1

0 0 0 1 1 1

Figure 10-3 Interrupt Test Control Register (ITCR)

Bit 0

WRTINT ADR3 ADR2 ADR1 ADR0

1

Read: see individual bit descriptions

Write: see individual bit descriptions

WRTINT - Write to the Interrupt Test Registers

Read: anytime

Write: only in special modes and with I bit mask and X bit mask set.

1 = Disconnect the interrupt inputs from the priority decoder and use the values written into the

ITEST registers instead.

0 = Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs.

NOTE:

Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten.

ADR3 - ADR0 - Test register select bits

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Read: anytime

Write: anytime

These bits determine which test register is selected on a read or write. The hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects. That is, an “F” written into ADR3 - ADR0 will select vectors $FFFE - $FFF0 while a “7” written to ADR3 - ADR0 will select vectors $FF7E - $FF70.

10.3.2 Interrupt Test Registers

Address:$0016

Bit 7

Read:

Write:

Reset:

INTE

0

6

INTC

5

INTA

4

INT8

3

INT6

2

INT4

1

INT2

0 0 0 0 0

Figure 10-4 Interrupt TEST Registers (ITEST)

0

Bit 0

INT0

0

Read: Only in special modes. Reads will return either the state of the interrupt inputs of the

Interrupt sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT

= 1). Reads will always return zeroes in normal modes.

Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.

INTE - INT0 - Interrupt TEST bits

These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic one state. Bits are named with INTE through INT0 to indicate vectors $FFxE through $FFx0. These bits can be written only in special modes and only with the WRTINT bit set (logic one) in the Interrupt Test

Control Register (ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines to the Interrupt sub-block will be disconnected and interrupt requests will be generated only by this register. These bits can also be read in special modes to view that an interrupt requested by a system block (such as a peripheral block) has reached the INT module.

There is a test register implemented for every 8 interrupts in the overall system. All of the test registers share the same address and are individually selected using the value stored in the ADR3 - ADR0 bits of the Interrupt Test Control Register (ITCR).

NOTE:

When ADR3-ADR0 have the value of $F, only bits 2-0 in the ITEST register will be accessible. That is, vectors higher than $FFF4 cannot be tested using the test registers and bits 7-3 will always read as a logic zero. If ADR3-ADR0 point to an unimplemented test register, writes will have no effect and reads will always return a logic zero value.

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10.3.3 Highest Priority I Interrupt (Optional)

Address:$001F

Bit 7

Read:

Write:

Reset:

PSEL7

1

6

PSEL6

1

5

PSEL5

1

4

PSEL4

1

3

PSEL3

0

2

PSEL2

0

1

PSEL1

1

Figure 10-5

Highest Priority I Interrupt

Register (HPRIO)

Bit 0

0

0

Read: anytime

Write: only if I mask in CCR = 1

PSEL7 - PSEL1 - Highest priority I interrupt select bits

The state of these bits determines which I bit maskable interrupt will be promoted to highest priority

(of the I bit maskable interrupts). To promote an interrupt, the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I bit masked vector address (value higher than $F2) is written, IRQ ($FFF2) will be the default highest priority interrupt.

10.4 Operation

The Interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.

10.4.1 Interrupt Exception Requests

As shown in

Figure 10-1

above, the INT mainly contains a register block to provide interrupt status and control, an optional Highest Priority I Interrupt (HPRIO) block and a priority decoder to evaluate whether pending interrupts are valid and assess their priority.

10.4.1.1 Interrupt Registers

The INT registers are accessible only in special modes of operation and function as described in

10.3.1

and

10.3.2

previously.

10.4.1.2 Highest Priority I bit Maskable Interrupt

When the optional HPRIO block is implemented, the user is allowed to promote a single I bit maskable interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active.

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10.4.1.3 Interrupt Priority Decoder

The priority decoder evaluates all interrupts pending and determines their validity and priority. When the

CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request.

NOTE:

Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed.

If for any reason the interrupt source is unknown (e.g. an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request), the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt vector when there has never been a pending interrupt request, the INT will provide the Software Interrupt

(SWI) vector address.

10.4.2 Reset Exception Requests

The INT supports three system reset exception request types: normal system reset or power-on-reset request, Crystal Monitor reset request and COP Watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the Core. The INT will then provide the service routine address for the type of reset requested.

10.4.3 Exception Priority

The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in

Table 10-1

below.

Table 10-1 Exception Vector Map and Priority

Vector Address

$FFFE–$FFFF

$FFFC–$FFFD

$FFFA–$FFFB

$FFF8–$FFF9

$FFF6–$FFF7

$FFF4–$FFF5

$FFF2–$FFF3

$FFF0–$FF00

Source

System reset

Crystal Monitor reset

COP reset

Unimplemented opcode trap

Software interrupt instruction (SWI) or BDM vector request

XIRQ signal

IRQ signal

Device-specific I bit maskable interrupt sources (priority in descending order)

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10.5 Modes of Operation

The functionality of the INT sub-block in various modes of operation is discussed in the subsections that follow.

10.5.1 Normal Operation

The INT operates the same in all normal modes of operation.

10.5.2 Special Operation

Interrupts may be tested in special modes through the use of the interrupt test registers as described in

10.3.1

and

10.3.2

previously.

10.5.3 Emulation Modes

The INT operates the same in emulation modes as in normal modes.

10.6 Low-Power Options

The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections.

10.6.1 Run Mode

The INT does not contain any options for reducing power in run mode.

10.6.2 Wait Mode

Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wakeup signal upon recognition of a valid interrupt or any XIRQ request.

10.6.3 Stop Mode

Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be used to generate the wakeup signal upon recognition of a valid interrupt or any XIRQ request.

10.7 Motorola Internal Information

The INT does not contain any functionality that is considered to be for Motorola internal use only.

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Section 11 Module Mapping Control (MMC)

This section describes the functionality of the Module Mapping Control (MMC) sub-block of the Core.

11.1 Overview

The Module Mapping Control (MMC) sub-block of the Core performs all mapping and select operations for the on-chip and external memory blocks. The MMC also handles mapping functions for the system peripheral blocks and provides a global peripheral select to be decoded by the Motorola I.P. Bus when the

Core is addressing a portion of the peripheral register map space. All bus-related data flow and multiplexing for the Core is handled within the MMC as well. Finally, the MMC contains logic to determine the state of system security.

11.1.1 Features

• Registers for mapping of address space for on-chip RAM, EEPROM, and Flash EEPROM (or

ROM) memory blocks and associated registers

• Memory mapping control and selection based upon address decode and system operating mode

• Core Address Bus control

• Core Data Bus control and multiplexing

• Core Security state decoding

• Emulation Chip Select signal generation (ECS)

• External Chip Select signal generation (XCS)

• Internal memory expansion

• Miscellaneous system control functions via the MISC register

• Reserved registers for test purposes

• Configurable system memory options defined at integration of Core into the System-on-a-Chip

(SOC).

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11.1.2 Block Diagram

The block diagram of the MMC is shown in

Figure 11-1

below.

secure bdm_unsecure

Stop, Wait

MMC

SECURITY

Read & Write Enables

Clocks, Reset

Mode Information

EBI Alternate Address bus

EBI Alternate Write data bus

EBI Alternate Read data bus

CPU Address bus

CPU Read Data bus

CPU Write Data bus

CPU Control

REGISTERS

BUS CONTROL mmc_secure

ADDRESS DECODE

INTERNAL MEMORY

EXPANSION

Port K Interface

memory space select(s)

peripheral select

Core select (s)

Alternate Address bus (BDM)

Alternate Write data bus (BDM)

Alternate Read data bus (BDM)

Figure 11-1 Module Mapping Control Block Diagram

11.2 Interface Signals

All interfacing with the MMC sub-block is done within the Core.

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11.3 Registers

A summary of the registers associated with the MMC sub-block is shown in

Figure 11-2

below. Detailed descriptions of the registers and bits are given in the subsections that follow.

Address Name

$0010 INITRM read write

Bit 7 6 5 4 3

RAM15 RAM14 RAM13 RAM12 RAM11

2

0

1

0

Bit 0

RAMHAL

$0011

$0012

INITRG read write

INITEE read write

0

EE15

0

$0013 MISC read write

$0014 Reserved read write

$0017 Reserved read write

Bit 7

Bit 7

REG14

EE14

0

6

6

REG13

EE13

0

5

5

REG12

EE12

0

4

4

REG11

EE11

EXSTR1

3

3

0

0

EXSTR0

2

2

0

0

ROMHM

1

1

0

EEON

ROMON

Bit 0

Bit 0

$001C MEMSIZ0 read reg_sw0 write

0

$001D MEMSIZ1 read rom_sw1 rom_sw0 write

0 0

$0030 PPAGE read write eep_sw1 eep_sw0

0

PIX5

0

PIX4

$0031 Reserved read write

0 0 0 0

= Unimplemented

0

0

PIX3

0

X = Indeterminate ram_sw2 ram_sw1 ram_sw0

0

PIX2

0 pag_sw1

PIX1

0 pag_sw0

PIX0

0

Figure 11-2 Module Mapping Control Register Summary

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11.3.1 Initialization of Internal RAM Position Register (INITRM)

Address: Base + $10

Bit 7 6 5 4 3

Read:

Write:

Reset:

RAM15 RAM14 RAM13 RAM12 RAM11

0 0 0

= Unimplemented

0 1

Figure 11-3 INITRM Register

0

2

0

1

0

0

Bit 0

RAM-

HAL

1

Read: Anytime

Write: Once in Normal and Emulation Modes, anytime in Special Modes

NOTE:

Writes to this register take one cycle to go into effect.

This register initializes the position of the internal RAM within the on-chip system memory map.

RAM15 - RAM11 - Internal RAM Map Position

These bits determine the upper five bits of the base address for the system’s internal RAM array.

RAMHAL - RAM High-align

RAMHAL specifies the alignment of the internal RAM array.

0 = Aligns the RAM to the lowest address ($0000) of the mappable space

1 = Aligns the RAM to the higher address ($FFFF) of the mappable space

11.3.2 Initialization of Internal Registers Position Register (INITRG)

Address:

Read:

Write:

Reset:

Base + $11

6 Bit 7

0

5 4 3

REG14 REG13 REG12 REG11

0 0 0 0 0

= Unimplemented

Figure 11-4 INITRG Register

0

2

0

1

0

0

Bit 0

0

0

Read: Anytime

Write: Once in Normal and Emulation modes and anytime in Special modes

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This register initializes the position of the internal registers within the on-chip system memory map. The registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first

32K bytes of the system’s address space.

REG14 - REG11 - Internal Register Map Position

These four bits in combination with the leading zero supplied by bit 7 of INITRG determine the upper five bits of the base address for the system’s internal registers (i.e. the minimum base address is $0000 and the maximum is $7FFF).

11.3.3 Initialization of Internal EEPROM Position Register (INITEE)

Address: Base + $12

Bit 7 6

Read:

Write:

Reset:

EE15

0

EE14

5

EE13

4

EE12

3

EE11

0 0 0 0

= Unimplemented

Figure 11-5 INITEE Register

0

2

0

1

0

0

Bit 0

EEON

1

Read: Anytime

Write: Once in Normal and Emulation modes with the exception of the EEON bit which can be written anytime and write anytime in Special modes

NOTE:

Writes to this register take one cycle to go into effect.

This register initializes the position of the internal EEPROM within the on-chip system memory map.

EE15 - EE11 - Internal EEPROM map position

These bits determine the upper five bits of the base address for the system’s internal EEPROM array.

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11.3.4 Miscellaneous System Control Register (MISC)

Address: Base + $13

Bit 7

Read:

Write:

0

Expanded

Reset:

Peripheral or Single

Chip Reset

0

0

6

0

0

0

5

0

0

0

4

0

0

0

3 Bit 0

EXSTR1 EXSTR0 ROMHM ROMON

1

1

2

1

1

1

0

0

= Unimplemented

Figure 11-6 Miscellaneous System Control Register (MISC)

NOTES:

1. The reset state of this bit is determined at the chip integration level.

1

1

Read: Anytime

Write: As stated in each bit description below

NOTE:

Writes to this register take one cycle to go into effect

This register initializes miscellaneous control functions.

EXSTR1,0 - External Access Stretch Bits 1 & 0

Write: Once in Normal and Emulation modes and anytime in Special modes

This two bit field determines the amount of clock stretch on accesses to the external address space as shown in

Table 11-1

below. In Single Chip and Peripheral modes these bits have no meaning or effect.

Table 11-1 External Stretch Bit Definition

Stretch bit EXSTR1 Stretch bit EXSTR0 Number of E Clocks Stretched

0

0

0

1

0

1

1

1

0

1

2

3

ROMHM - Flash EEPROM or ROM only in second half of memory map

Write: Once in Normal and Emulation modes and anytime in Special modes

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1 = Disables direct access to the Flash EEPROM or ROM in the lower half of the memory map.

These physical locations of the Flash EEPROM or ROM can still be accessed through the

Program Page window.

0 = The fixed page(s) of Flash EEPROM or ROM in the lower half of the memory map can be accessed.

ROMON - Enable Flash EEPROM or ROM

Write: Once in Normal and Emulation modes and anytime in Special modes

This bit is used to enable the Flash EEPROM or ROM memory in the memory map.

1 = Enables the Flash EEPROM or ROM in the memory map.

0 = Disables the Flash EEPROM or ROM from the memory map.

11.3.5 Reserved Test Register Zero (MTST0)

Address:

Read:

Write:

Reset:

Base + $17

0 0 0 0 0 0 0

0 0 0

= Unimplemented

0 0 0 0

Figure 11-7 Reserved Test Register Zero (MTST0)

0

0

Read: Anytime

Write: No effect - this register location is used for internal test purposes.

11.3.6 Reserved Test Register One (MTST1)

Address:

Read:

Write:

Reset:

Base + $14

0 0 0 0 0 0 0

0 0 0

= Unimplemented

1 0 0 0

Figure 11-8 Reserved Test Register One (MTST1)

Read: Anytime

Write: No effect - this register location is used for internal test purposes.

0

0

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11.3.7 Memory Size Register Zero (MEMSIZ0)

Address: Base + $1C

Read: reg_sw0 0

Write:

Reset: eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0

-

= Unimplemented

Figure 11-9 Memory Size Register Zero

-

Read: Anytime

Write: Writes have no effect

The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration switches at the Core boundary which are configured at system integration. This register allows read visibility to the state of these switches.

reg_sw0 - Allocated System Register Space

1 = Allocated system register space size is 2K byte

0 = Allocated system register space size is 1K byte eep_sw1:eep_sw0 - Allocated System EEPROM Memory Space

The allocated system EEPROM memory space size is as given in

Table 11-2

below.

Table 11-2 Allocated EEPROM Memory Space eep_sw1:eep_sw0 Allocated EEPROM Space

00

01

10

11

0K byte

2K byte

4K byte

8K byte ram_sw2:ram_sw0 - Allocated System RAM Memory Space

The allocated system RAM memory space size is as given in

Table 11-3

below.

Table 11-3 Allocated RAM Memory Space ram_sw2:ram_sw0 Allocated RAM Space RAM mappable region

000 2k Byte 2k Byte

001 4k Byte

010

011

100

6k Byte

8k Byte

10k Byte

4k Byte

8k Byte

1

8k Byte

16k Byte

1

INITRM bits used

RAM15-RAM11

RAM15-RAM12

RAM15-RAM13

RAM15-RAM13

RAM15-RAM14

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Table 11-3 Allocated RAM Memory Space ram_sw2:ram_sw0 Allocated RAM Space RAM mappable region

101 12k Byte

16k Byte

1

110

111

14k Byte

16k Byte

16k Byte

1

16k Byte

INITRM bits used

RAM15-RAM14

RAM15-RAM14

RAM15-RAM14

NOTES:

1. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of

RAMHAL.

NOTE:

As stated, the bits in this register provide read visibility to the system physical memory space allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the chip-level documentation for actual sizes.

11.3.8 Memory Size Register One (MEMSIZ1)

Address: Base + $1D

Read: rom_sw1 rom-sw0

Write:

Reset: -

0 0 0 0

-

= Unimplemented

Figure 11-10 Memory Size Register One

pag_sw1 pag_sw0

-

Read: Anytime

Write: Writes have no effect

The MEMSIZ1 register reflects the state of the Flash EEPROM or ROM physical memory space and paging switches at the Core boundary which are configured at system integration. This register allows read visibility to the state of these switches.

rom_sw1:rom_sw0 - Allocated System Flash EEPROM or ROM Physical Memory Space

The allocated system Flash EEPROM or ROM physical memory space is as given in

Table 11-4

below.

Table 11-4 Allocated Flash EEPROM/ROM Physical Memory Space rom_sw1:rom_sw0

00

01

10

11

Allocated Flash or ROM Space

0K byte

16K byte

48K byte

1

64K byte

1

1 The ROMHM software bit in the MISC register determines the accessibility of the Flash EEPROM/ROM memory space.

Please refer to 11.3.4 for a detailed functional description of the ROMHM bit.

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pag_sw1:pag_sw0 - Allocated Off-Chip Flash EEPROM or ROM Memory Space

The allocated off-chip Flash EEPROM or ROM memory space size is as given in

Table 11-5

below.

Table 11-5 Allocated Off-Chip Memory Options pag_sw1:pag_sw0 Off-Chip Space On-Chip Space

00 876K byte 128K byte

01

10

11

768K byte

512K byte

0K byte

256K byte

512K byte

1M byte

NOTE:

As stated, the bits in this register provide read visibility to the system memory space and on-chip/off-chip partitioning allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the chip-level documentation for actual sizes.

11.3.9 Program Page Index Register (PPAGE)

Address: Base + $30

Bit 7 6

0 0

5 4 3 2 1

Read:

Write:

Reset:

PIX5 PIX4 PIX3 PIX2 PIX1

0 0 0

= Unimplemented

0 0 0 0

Figure 11-11 Program Page Index Register (PPAGE)

Bit 0

PIX0

0

Read: Anytime

Write: Anytime

The HCS12 Core architecture limits the physical address space available to 64K bytes. The Program Page

Index Register allows for integrating up to 1M byte of Flash EEPROM or ROM into the system by using the six page index bits to page 16K byte blocks into the Program Page Window located from $8000 to

$BFFF as defined in

Table 11-6

below. CALL and RTC instructions have a special single wire mechanism to read and write this register without using the address bus.

NOTE:

Normal writes to this register take one cycle to go into effect. Writes to this register using the special single wire mechanism of the CALL and RTC instructions will be complete before the end of the associated instruction.

PIX5 - PIX0 - Program Page Index Bits 5-0

These six page index bits are used to select which of the 64 Flash EEPROM or ROM array pages is to be accessed in the Program Page Window as shown in

Table 11-6

.

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Table 11-6 Program Page Index Register Bits

1

1

.

.

.

.

.

1

1

PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 Program Space Selected

0

0

0

0

0

0

0

0

0

0

0

1

16K page 0

16K page 1

0

0

0

0

0

0

0

0

1

1

0

1

16K page 2

16K page 3

.

.

.

.

.

1

1

1

1

.

.

.

.

1

1

1

1

1

1

.

.

.

.

.

1

1

0

0

.

.

.

.

.

1

1

0

1

.

.

.

.

.

0

1

16K page 60

16K page 61

16K page 62

16K page 63

.

.

.

.

.

11.4 Operation

The MMC sub-block performs four basic functions of the Core operation: bus control, address decoding and select signal generation, memory expansion and security decoding for the system. Each aspect is described in the subsections following.

11.4.1 Bus Control

The MMC controls the address bus and data buses that interface the Core with the rest of the system. This includes the multiplexing of the input data buses to the Core onto the main CPU read data bus and control of data flow from the CPU to the output address and data buses of the Core. In addition, the MMC handles all CPU read data bus swapping operations.

11.4.2 Address Decoding

As data flows on the Core address bus, the MMC decodes the address information, determines whether the internal Core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal. This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select.

The MMC also generates two external chip select signals, Emulation Chip Select (ECS) and External Chip

Select (XCS).

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11.4.2.1 Select Priority and Mode Considerations

Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers, vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in

Table 11-7

below. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active. An example of this is if the registers and the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority. This means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers.

Table 11-7 Select Signal Priority

Priority

Highest

...

...

...

...

Lowest

Address Space

BDM (internal to Core) firmware or register space

Internal register space

RAM memory block

EEPROM memory block

On-chip Flash EEPROM or ROM

Remaining external space

In expanded modes, all address space not used by internal resources is by default external memory space.

The data registers and data directions registers for Ports A and B are removed from the on-chip memory map and become external accesses. If the EME bit in the MODE register (see

12.3.8

) is set, the data and data direction registers for Port E are also removed from the on-chip memory map and become external accesses.

In Special Peripheral mode, the first 16 registers associated with bus expansion are removed from the on-chip memory map (PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, MODE, PUCR,

RDRIV and the EBI reserved registers).

In emulation modes, if the EMK bit in the MODE register (see

12.3.8

) is set, the data and data direction

registers for Port K are removed from the on-chip memory map and become external accesses.

11.4.2.2 Emulation Chip Select Signal

When the EMK bit in the MODE register (see

12.3.8

) is set, Port K bit 7 is used as an active-low emulation chip select signal, ECS. This signal is active when the system is in Emulation mode, the EMK bit is set and the Flash EEPROM or ROM space is being addressed subject to the conditions outlined in

11.4.3.2

below. When the EMK bit is clear, this pin is used for general purpose I/O.

11.4.2.3 External Chip Select Signal

When the EMK bit in the MODE register (see

12.3.8

) is set, Port K bit 6 is used as an active-low external

chip select signal, XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to unimplemented locations within the

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register space or to locations that are removed from the map (i.e. Ports A and B in Expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O.

11.4.3 Memory Expansion

The HCS12 Core architecture limits the physical address space available to 64K bytes. The Program Page

Index Register allows for integrating up to 1M byte of Flash EEPROM or ROM into the system by using the six page index bits to page 16K byte blocks into the Program Page Window located from $8000 to

$BFFF in the physical memory space. The paged memory space can consist of solely on-chip memory or a combination of on-chip and off-chip memory. This partitioning is configured at system integration through the use of the paging configuration switches (pag_sw1:pag_sw0) at the Core boundary. The options available to the integrator are as given in

Table 11-8

below (this table matches

Table 11-5

but

is repeated here for easy reference).

Table 11-8 Allocated Off-Chip Memory Options pag_sw1:pag_sw0 Off-Chip Space On-Chip Space

00 876K byte 128K byte

01

10

11

768K byte

512K byte

0K byte

256K byte

512K byte

1M byte

Based upon the system configuration, the Program Page Window will consider its access to be either internal or external as defined in

Table 11-9

below.

Table 11-9 External/Internal Page Window Access pag_sw1:pag_sw0 Partitioning PIX5:0 Value Page Window Access

00

01

10

11

876K off-Chip,

128K on-Chip

768K off-chip,

256K on-chip

512K off-chip,

512K on-chip

0K off-chip,

1M on-chip

$00 - $37

$38 - $3F

$00 - $2F

$30 - $3F

$00 - $1F

$20 - $3F n/a

$00 - $3F external internal external internal external internal external internal

NOTE:

The partitioning as defined in

Table 11-9

above applies only to the allocated memory space and the actual memory sizes implemented in the system may differ.

Please refer to the chip-level documentation for actual sizes.

The PPAGE register holds the page select value for the Program Page WIndow. The value of the PPAGE register can be manipulated by normal read and write instructions as well as the CALL and RTC instructions.

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Control registers, vector spaces and a portion of on-chip memory are located in unpaged portions of the

64K byte physical address space. The stack and I/O addresses should also be in unpaged memory to make them accessible from any page.

The starting address of a service routine must be located in unpaged memory because the 16-bit exception vectors cannot point to addresses in paged memory. However, a service routine can call other routines that are in paged memory. The upper 16K byte block of memory space ($C000-$FFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area.

11.4.3.1 CALL and Return from Call Instructions

CALL and RTC are uninterruptable instructions that automate page switching in the program expansion window. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program expansion memory. CALL calculates and stacks a return address, stacks the current PPAGE value, and writes a new instruction-supplied value to

PPAGE. The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map. Execution then begins at the address of the called subroutine.

During the execution of a CALL instruction, the CPU:

• Writes the old PPAGE value into an internal temporary register and writes the new instruction-supplied PPAGE value into the PPAGE register.

• Calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack.

• Pushes the old PPAGE value onto the stack.

• Calculates the effective address of the subroutine, refills the queue, and begins execution at the new address on the selected page of the expansion window.

This sequence is uninterruptable; there is no need to inhibit interrupts during CALL execution. A CALL can be performed from any address in memory to any other address.

The PPAGE value supplied by the instruction is part of the effective address. For all addressing mode variations except indexed-indirect modes, the new page value is provided by an immediate operand in the instruction. In indexed-indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows values calculated at run time rather than immediate values that must be known at the time of assembly.

The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the

CALL.

During the execution of an RTC instruction, the CPU:

• Pulls the old PPAGE value from the stack

• Pulls the 16-bit return address from the stack and loads it into the PC

• Writes the old PPAGE value into the PPAGE register

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• Refills the queue and resumes execution at the return address

This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window.

The CALL and RTC instructions behave like JSR and RTS, except they use more execution cycles.

Therefore, routinely substituting CALL/RTC for JSR/RTS is not recommended. JSR and RTS can be used to access subroutines that are on the same page in expanded memory. However, a subroutine in expanded memory that can be called from other pages must be terminated with an RTC. And the RTC unstacks a

PPAGE value. So any access to the subroutine, even from the same page, must use a CALL instruction so that the correct PPAGE value is in the stack.

11.4.3.2 Extended Address (XAB19:14) and ECS Signal Functionality

If the EMK bit in the MODE register is set (see

12.3.8

) the PIX5:0 values will be output on XAB19:14 respectively (Port K bits 5:0) when the system is addressing within the physical Program Page Window address space ($8000 - $BFFF) and is in an expanded mode. When addressing anywhere else within the physical address space (outside of the paging space), the XAB19:14 signals will be assigned a constant value based upon the physical address space selected. In addition, the active-low emulation chip select signal, ECS, will likewise function based upon the assigned memory allocation. In the cases of 48K byte and 64K byte allocated physical Flash/ROM space, the operation of the ECS signal will additionally depend upon the state of the ROMHM bit (see

11.3.4

) in the MISC register.

Table 11-10

,

Table 11-11

,

Table 11-12

and

Table 11-13

below summarize the functionality of these signals based upon the allocated memory configuration. Again, this signal information is only available externally when the EMK bit is set and the system is in an expanded mode.

Table 11-10 0K Byte Physical Flash/ROM Allocated

Address Space Page Window Access ROMHM ECS XAB19:14

$0000 - $3FFF n/a n/a 1 $3D

$4000 - $7FFF

$8000 - $BFFF

$C000 - $FFFF n/a n/a n/a n/a n/a n/a

1

0

0

$3E

PIX5:0

$3F

Table 11-11 16K Byte Physical Flash/ROM Allocated

Address Space Page Window Access ROMHM ECS XAB19:14

$0000 - $3FFF

$4000 - $7FFF

$8000 - $BFFF

$C000 - $FFFF n/a n/a n/a n/a n/a n/a n/a n/a

1

0

1

1

$3D

$3E

PIX5:0

$3F

Table 11-12 48K Byte Physical Flash/ROM Allocated

Address Space Page Window Access ROMHM ECS XAB19:14

$0000 - $3FFF n/a n/a 1 $3D

$4000 - $7FFF n/a

0

1

0

1

$3E

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Table 11-12 48K Byte Physical Flash/ROM Allocated

Address Space Page Window Access ROMHM ECS XAB19:14

external 1

$8000 - $BFFF n/a PIX5:0 internal 0

$C000 - $FFFF n/a n/a 0 $3F

Table 11-13 64K Byte Physical Flash/ROM Allocated

Address Space Page Window Access ROMHM ECS XAB19:14

$0000 - $3FFF

$4000 - $7FFF

$8000 - $BFFF

$C000 - $FFFF n/a n/a external internal n/a n/a n/a n/a

0

1

0

1

1

0

0

0

1

0

1

$3D

$3E

PIX5:0

$3F

A graphical example of a memory paging for a system configured as 1M byte on-chip Flash/ROM with

64K allocated physical space is given in

Figure 11-12

below for illustration.

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$0000

61

16K FLASH

(Unpaged)*

$4000

62

16K FLASH

(Unpaged)*

$8000

One 16K FLASH/ROM Page accessible at a time (selected by PPAGE = 0 to 6

3)

0

1 2

3

59 60 61 62 63

16K FLASH

(Paged)

$C000

63

*

These 16K FLASH/ROM pages accessible from $0000 to $7FFF if selected by the

ROMHM bit in the MISC register.

16K FLASH

(Unpaged)

$FF00

VECTORS

$FFFF

NORMAL

SINGLE CHIP

Figure 11-12 Memory Paging Example: 1M Byte On-Chip Flash/ROM, 64K Allocation

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11.5 Motorola Internal Information

The subsection aspects of the MMC that are considered to be for Motorola internal use only.

11.5.1 Test Registers

There are two test registers for the MMC, MTST[1:0]. These registers are used for internal test purposes to gain visibility into the module select logic.

In all modes, if the FLAGSE bit in MTST1 is set, accesses to internal registers or memory will cause the associated flag to assert. For example, an access into the RAM array will cause the MT01 bit (Bit 1in

MTST0 - RAM Array bit) to set. These registers can be read in any mode. If the FLAGSE bit is set, reading the register will cause it to be cleared. A write will have no effect in all modes.

11.5.1.1 Mapping Test Register 0 (MTST0)

Address:

Read:

Write:

Reset:

Base + $14

MT07 MT06 MT05 MT04 MT03 MT02 MT01

0 0 0 0 0 0 0

= Unimplemented

Figure 11-13 Mapping Test Register Zero (MTST0)

MT00

0

Read: Anytime

Write: No effect

MT0 7-0 - Mapping Test 0

The individual bits are assigned as follows:

MT07 - Core*

MT06 - Peripheral

MT05 - EE Array

MT04 - EE Register

MT03 - Flash Array

MT02 - Flash Register

MT01 - RAM Array

MT00 - RAM Register

* This flag bit will not get set when you are accessing any of the MTST registers

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11.5.1.2 Mapping Test Register 1 (MTST1)

Address:

Read:

Write:

Reset:

Base + $17

MT17 MT16 MT15 MT14

PNORME FLAGSE BKGDPUE

0 0 0

= Unimplemented

1

MT13

0

MT12

0

Figure 11-14 Mapping Test Register One (MTST1)

MT11

0

MT10

0

Read: Anytime

Write: See individual bit descriptions

MT17 - Unimplemented (reads back zero)

MT16 - Mapping Test Register 1 Bit 6 (PNORME).

Normally, the system will enter peripheral mode and be in a special mode. Setting this bit will put the system into normal peripheral mode. This is so that testing of register normal mode read/write conditions can be performed while in peripheral mode.

Normal, Special & Emulation: Write never.

Peripheral: Write anytime.

1 = The system operates in normal peripheral mode.

0 = The system operates in special peripheral mode.

MT15 — Mapping Test Register 1 Bit 5 (FLAGSE).

This bit is used to enable the select signal flag function of the MTST registers. When asserted, the

MTST registers that have an associated block select signal flag bit will act as flag registers, where an access to the block causes the flag bit to assert. When unasserted, the MTST registers will not act as flag bits.

Normal & Emulation: Write never.

Special: Write anytime.

1 = The MTST registers act as flag bits for the block select signals.

0 = The MTST registers do not act as flag bits for the block select signals.

MT14 - Mapping Test Register 3 Bit 4 (BKGDPUE)

This bit used to enable/disable the pull-up on the BKGD pin.

Normal & Emulation: Write never

Special: Write anytime

1 = The pull-up on the BKGD pin is enabled.

0 = The pull-up on the BKGD pin is disabled.

MT 13-10 — Mapping Test Register 1 Bits 3:0

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11.5.2 MMC Bus Control

This subsection discusses aspects of the bus control/multiplexing performed by the MMC.

11.5.2.1 Address Bus

The MMC multiplexes the EBI Alternate Address Bus, BDM Alternate Address Bus, and the CPU

Address Bus to form the main address bus for the Core. The EBI Alternate Address Bus is the address bus source in peripheral mode. The BDM Alternate Address Bus is the address bus source whenever the BDM is driving the bus. The CPU Address Bus is the address bus source whenever the CPU has a valid address, the BDM is not driving the bus and the system is not operating in peripheral mode.

11.5.2.2 Write Data Bus

The CPU Write Data bus, EBI Alternate Write Data bus or BDM Alternate Write Data bus supply data to the master bus. The CPU Write Data bus is the write data source unless the cycle is a BDM access or the system is operating in peripheral mode. The BDM Alternate Write Data bus is the write data source only when the BDM is driving the bus. The EBI Alternate Write Data bus is the write data source in peripheral mode.

11.5.2.3 Read Data Bus

The MMC provides the control to split 16-bit accesses into two cycle operations, when needed. The CPU is paused during the second cycle of the two cycle access. For reads, the MMC takes care of swapping and holding the read data bus so that the CPU will receive the data on the correct location of its read data bus.

An access may also take two cycles when the Interrupt or BDM is driving the address bus, if the system is in a narrow mode and the 16-bit access is to external memory space. In these cases, AB[0] will be forced high during the second cycle.

The MMC will also force those accesses that would normally be two cycle operations into a single cycle operation based upon the Wide Bus Enable signal. This signal will assert when performing a 16-bit access

in narrow mode to those locations that are removed from the memory map, as summarized by Table 11-14.

Table 11-14 Wide Bus Enable Signal Generation

Address

$0000 -

$0003

$0008 -

$0009

$000A -

$000D

Register

Names

PORTA

PORTB

DDRA

DDRB

PORTE

DDRE

PEAR

MODE

PUCR

RDRIV

Conditions initrg[4:0] == mmc_ab_t2[15:11] & ebi_emul_t2 & ebi_narrow_t2 initrg[4:0] == mmc_ab_t2[15:11] & ebi_emul_t2 & ebi_narrow_t2 & ebi_eme_t2 initrg[4:0] == mmc_ab_t2[15:11] & ebi_emul_t2 & ebi_narrow_t2 mmc_widebuse_t2

1

1

1

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$0032 -

$0033

All Others

PORTK

DDRK

initrg[4:0] == mmc_ab_t2[15:11] & ebi_emul_t2 & ebi_narrow_t2 & ebi_emk_t2

-

1

0

Table 11-15 summarizes the different access types, where the data is on the internal or external read data

bus and where the CPU is expecting the data. The source of the CPU’s read data bus for external accesses is the ebi_extrdb and for internal accesses is the rdb_t2.

IMS refers to the Internal Memory Select signal (1 = Internal, 0 = External). FMTS refers to the Fast

Memory Transfer Select signal, which asserts anytime an access is made to the RAM except for the last byte of the array.

Table 11-15 Read Data Bus Swapping

MODE

X 1 X 0 0

Single Chip

X

X

X

X

1

1

1

1

0 0

X

X

1

1

1 0

1

0

1

1

Normal

Expanded

Narrow

X 0 X 0 0

X

X

X

X

0 X

0

0

X

X

1 X

0

1

1

0

1

0

1

0

X

X

X

X

1

1

1

1

0 0

X

X

1

1

1 0

1

0

1

1

2

1

1

1

2

1

1

1

1

2

1

1

1

2

CYCLES

Read Data Bus

(Internal or External)

-> CPU Read Data Bus

rdbh -> core_rdbh rdbl -> core_rdbl

1. rdbl -> core_rdbh

2. rdbh -> core_rdbl rdbh -> core_rdbl rdbl -> core_rdbl rdbl -> core_rdbh rdbh -> core_rdbl

1. extrdbh -> core_rdbh

2. extrdbl -> core_rdbl

1. extrdbl -> core_rdbh

2. extrdbh -> core_rdbl extrdbh -> core_rdbl extrdbl -> core_rdbl rdbh -> core_rdbh rdbl -> core_rdbl

1. rdbl -> core_rdbh

2. rdbh -> core_rdbl rdbh -> core_rdbl rdbl -> core_rdbl rdbl -> core_rdbh rdbh -> core_rdbl

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Table 11-15 Read Data Bus Swapping

MODE

Emulation

Expanded

Narrow

Expanded

Wide

0 0 X 0 0

X

0 X 0 1

1 0 X 0 0

X

0 X 1 0

X

0 X 1 1

X

1 X 0 0

X

1 0 0 1

X

1 X 1 0

X

1 X 1 1

X

1 1 0 1

X X X 0 0

X

X 0 0 1

X

X X 1 0

X

X X 1 1

X

X 1 0 1

2

1

1

1

1

1

1

1

1

2

1

1

1

2

2

CYCLES

Read Data Bus

(Internal or External)

-> CPU Read Data Bus

1. extrdbh -> core_rdbh

2. extrdbl -> core_rdbl

1. extrdbl -> core_rdbh

2. extrdbh -> core_rdbl

extrdbh -> core_rdbh extrdbl -> core_rdbl extrdbh -> core_rdbl extrdbl -> core_rdbl rdbh -> core_rdbh rdbl -> core_rdbl

1. rdbl -> core_rdbh

2. rdbh -> core_rdbl rdbh -> core_rdbl rdbl -> core_rdbl rdbl -> core_rdbh rdbh -> core_rdbl

(ext)rdbh -> core_rdbh

(ext)rdbl -> core_rdbl

1. (ext)rdbl -> core_rdbh

2. (ext)rdbh -> core_rdbl

(ext)rdbh -> core_rdbl

(ext)rdbl -> core_rdbl

(ext)rdbl -> core_rdbh

(ext)rdbh -> core_rdbl

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Section 12 Multiplexed External Bus Interface (MEBI)

This section describes the functionality of the Multiplexed External Bus Interface (MEBI) sub-block of the Core.

12.1 Overview

The MEBI sub-block of the Core serves to provide access and/or visibility to internal Core data manipulation operations including timing reference information at the external boundary of the Core and/or system. Depending upon the system operating mode and the state of bits within the control registers of the MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses externally. Using control information from other blocks within the system, the MEBI will determine the appropriate type of data access to be generated.

12.1.1 Features

• External bus controller with four 8-bit ports (A,B, E and K)

• Data and data direction registers for ports A, B E and K when used as general purpose I/O

• Control register to enable/disable alternate functions on Port E and Port K

• Mode control register

• Control register to enable/disable pullups on Ports A, B, E and K

• Control register to enable/disable reduced output drive on Ports A, B, E and K

• Control register to configure external clock behavior

• Control register to configure IRQ pin operation

• Logic to capture and synchronize external interrupt pin inputs

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12.1.2 Block Diagram

The block diagram of the MEBI sub-block is shown in

Figure 12-1

below.

altab[15:0]

16

16

8

8

8

8 altwdb[15:0] altrdb[15:0]

16

16 db[15:0] clock reg_select reset

16

External

Data Bus

Interface

16 data

8

8

8

8 mdrste ab[15:0] int_mem_sel rw sz8 cpu_pipe[1:0]

16

2 altsz8 altrw irq_t4 xirq_t4

External

Bus Control sync/capture

Registers

8

PA7-PA0/

A15-A08/

D15-D8/

D7-D0

8

PB7-PB0/

A7-A0/

D7-D0

6

PE7-PE2/

(bus sigs)

PE1/IRQ

PE0/XIRQ

BKGD/...

extbdm mmccs.../ mmcxa...

8 Port K

Control

8

8

PK7-PK0/

CS.../XA...

Figure 12-1 MEBI Block Diagram

In the figure, the signals on the right hand side represent pins that are accessible externally to the Core and/or system.

12.2 Interface Signals

Much of the interfacing with the MEBI sub-block is done within the Core; however, many of the MEBI signals pass through the Core boundary and interface with the system port/pad logic for Ports A, B, E and

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K. The Core interface signals associated with the MEBI are shown in

Table 12-1

below. The functional descriptions of the signals are provided below for completeness.

Table 12-1 MEBI Interface Signal Definitions

Signal Name

core_paind[7:0] core_pado[7:0] core_paobe[7:0] core_paibe_t2 core_papue_t2 core_padse_t2 core_pbind[7:0] core_pbdo[7:0] core_pbobe[7:0] core_pbibe_t2 core_pbpue_t2 core_pbdse_t2 core_peind[7:0] core_pedo[7:0] core_peobe[7:0] core_peibe_t2 core_pepue_t2 core_mdrste core_pedse_t2 core_pkind[7:0] core_pkdo[7:0] core_pkobe[7:0] core_pkibe_t2 core_pkpue_t2 core_pkdse_t2

Type Functional Description

External Bus Interface Signals

I Port A input data [7:0]

O Port A data output [7:0]

O Port A output buffer enable [7:0]

O Port A input buffer enable

O Port A pullup enable

O Port A drive strength enable

I Port B input data [7:0]

O Port B data output [7:0]

O Port B output buffer enable [7:0]

O Port B input buffer enable

O Port B pullup enable

O Port B drive strength enable

I

Port E input data [7:0]

NOTE: PE1 is IRQ pin input; PE0 is XIRQ pin input.

O Port E data output [7:0]

O Port E output buffer enable [7:0]

O Port E input buffer enable

O Port E pullup enable

O Enable signal for EBI Mode pin pullups at the pad

O Port E drive strength enable

I Port K input data [7:0]

O Port K data output [7:0]

O Port K output buffer enable [7:0]

O Port K input buffer enable

O Port K pullup enable

O Port K drive strength enable

12.2.1 MEBI Signal Descriptions

These descriptions apply to the MEBI signals that pass through the Core boundary and interface with the system External Bus Interface port/pad logic.

12.2.1.1 Port A Input Data to Core (core_paind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port A.

12.2.1.2 Port A Output Data from Core (core_pado[7:0])

This 8-bit wide output from the Core provides the Port A data output to the system port/pad logic for Port

A.

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12.2.1.3 Port A output buffer enable from Core (core_paobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port A.

12.2.1.4 Port A input buffer enable from Core (core_paibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port A.

12.2.1.5 Port A pullup enable from Core (core_papue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port A should be enabled for all Port A pins.

12.2.1.6 Port A drive strength enable from Core (core_padse_t2)

This single bit output from the Core indicates whether all Port A pins will operate with full or reduced drive strength.

12.2.1.7 Port B Input Data to Core (core_pbind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port B.

12.2.1.8 Port B Output Data from Core (core_pbdo[7:0])

This 8-bit wide output from the Core provides the Port B data output to the system port/pad logic for Port

B.

12.2.1.9 Port B output buffer enable from Core (core_pbobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port B.

12.2.1.10 Port B input buffer enable from Core (core_pbibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port B.

12.2.1.11 Port B pullup enable from Core (core_pbpue_t2)

When asserted (logic 1), this single bit output from the Core indicates that the pullup devices within the system port/pad logic for Port B should be enabled for all Port B pins.

12.2.1.12 Port B drive strength enable from Core (core_pbdse_t2)

This single bit output from the Core indicates whether all Port B pins will operate with full or reduced drive strength.

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12.2.1.13 Port E Input Data to Core (core_peind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port E. When the system has an external IRQ pin implemented, the input signal from the IRQ pin pad logic must be tied to Port E Input Data Bit 1. Likewise, when the system has an external XIRQ pin implemented, the input signal from the XIRQ pin pad logic must be tied to Port E Input Data Bit 0. Both the IRQ and

XIRQ signals are active low (i.e. their asserted state is logic 0).

12.2.1.14 Port E Output Data from Core (core_pedo[7:0])

This 8-bit wide output from the Core provides the Port E data output to the system port/pad logic for Port E.

12.2.1.15 Port E output buffer enable from Core (core_peobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port E.

12.2.1.16 Port E input buffer enable from Core (core_peibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port E.

12.2.1.17 Port E pullup enable from Core (core_pepue_t2)

This single bit output from the Core indicates whether or not the pullup devices within the system port/pad logic for Port E should be enabled for all Port E pins except the MODA (PE5) and MODB (PE6) pins.

12.2.1.18 Port E MODE pin pullup enable from Core (core_mdrste)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for the MODA (PE5) and MODB (PE6) pins within Port E should be enabled.

12.2.1.19 Port E drive strength enable from Core (core_pedse_t2)

This single bit output from the Core indicates whether all Port E pins will operate with full or reduced drive strength.

12.2.1.20 Port K Input Data to Core (core_pkind[7:0])

This 8-bit wide input to the Core provides the Core with the input data from the system port/pad logic for

Port K.

12.2.1.21 Port K Output Data from Core (core_pkdo[7:0])

This 8-bit wide output from the Core provides the Port K data output to the system port/pad logic for Port

K.

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12.2.1.22 Port K output buffer enable from Core (core_pkobe[7:0])

This 8-bit wide output from the Core provides the bit-by-bit output buffer enable signal to the system port/pad logic for Port K.

12.2.1.23 Port K input buffer enable from Core (core_pkibe_t2)

This single bit output from the Core provides the input buffer enable signal to the system port/pad logic for Port K.

12.2.1.24 Port K pullup enable from Core (core_pkpue_t2)

This single bit output from the Core indicates that the pullup devices within the system port/pad logic for

Port K should be enabled for all Port K pins.

12.2.1.25 Port K drive strength enable from Core (core_pkdse_t2)

This single bit output from the Core indicates whether all Port K pins will operate with full or reduced drive strength.

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12.3 Registers

A summary of the registers associated with the MEBI sub-block is shown in

Figure 12-2

below. Detailed descriptions of the registers and bits are given in the subsections that follow.

Address Name Bit 7

$0000

$0001

$0002

$0003

PORTA

PORTB

DDRA

DDRB

$0004 Reserved

$0005 Reserved

$0006 Reserved

$0007 Reserved

$0008

$0009

$000A

$000B

$000C

$000D

$000E

PORTE

DDRE

PEAR

MODE

PUCR

RDRIV

EBICTL

$000F Reserved

$001E

$0032

$0033

IRQCR

PORTK

DDRK read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write read write

Bit 7

Bit 7

Bit 7

Bit 7

0

0

0

0

Bit 7

Bit 7

NOACCE

MODC

PUPKE

RDPK

0

0

IRQE

Bit 7

Bit 7

6

6

6

6

0

0

0

6

6

0

6

0

MODB

0

0

0

0

IRQEN

6

6

5

5

5

5

= Unimplemented

0

0

0

5

5

5

0

5

5

PIPOE

MODA

0

0

0

0

0

0

0

0

3

3

3

0

3

3

0

0

0

4

4

4

0

4

4

4

4

NECLK

0

PUPEE

RDPE

0

0

0

4

4

3

3

LSTRE

IVIS

0

0

0

0

0

3

3

X = Indeterminate

Figure 12-2 MEBI Register Map Summary

0

0

0

0

0

2

2

RDWE

0

2

2

0

0

0

2

2

2

0

2

2

EMK

PUPBE

RDPB

0

0

0

EME

PUPAE

RDPA

ESTR

0

0

1

1

Bit 0

Bit 0

0

1

0

0

0

0

1

1

1

0

1

1

Bit 0

Bit 0

0

0

0

Bit 0

Bit 0

Bit 0

Bit 0

0

0

0

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12.3.1 Port A Data Register (PORTA)

Address: Base + $___0

BIT 7 6 5 4 3 2

Read:

Write:

Reset:

Single Chip:

Exp Wide, Emul. Nar with IVIS & Periph:

Expanded Narrow:

Bit 7 6 5 4 3 2

-

PA7

AB/

DB15

-

PA6

AB/

DB14

-

PA5

AB/

DB13

-

PA4

AB/

DB12

-

PA3

AB/

DB11

-

PA2

AB/

DB10

AB15 &

DB15/

DB7

AB14 &

DB14/

DB6

AB13 &

DB13/

DB5

AB12 &

DB12/

DB4

AB11 &

DB11/

DB3

AB10 &

DB10/

DB2

Figure 12-3 Port A Data Register (PORTA)

1

1

-

PA1

AB/

DB9

AB9 &

DB9/

DB1

BIT 0

Bit 0

-

PA0

AB/

DB8

AB8 &

DB8/

DB0

Read: anytime when register is in the map

Write: anytime when register is in the map

Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general purpose I/O.

Data Direction Register A (DDRA) determines the primary direction of each pin. DDRA also determines the source of data for a read of PORTA.

This register is not in the on-chip memory map in expanded and peripheral modes.

CAUTION:

To ensure that you read the value present on the PORTA pins, always wait at least one cycle after writing to the DDRA register before reading from the PORTA register.

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12.3.2 Data Direction Register A (DDRA)

Read:

Write:

Reset:

Address: Base + $___2

BIT 7 6

Bit 7 6

5

5

4

4

3

3

2

2

0 0 0 0 0 0

Figure 12-4 Data Direction Register A (DDRA)

1

1

0

BIT 0

Bit 0

0

Read: anytime when register is in the map

Write: anytime when register is in the map

This register controls the data direction for Port A. When Port A is operating as a general purpose I/O port,

DDRA determines the primary direction for each Port A pin. A “1” causes the associated port pin to be an output and a “0” causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTA register. If the DDR bit is zero (input) the buffered pin input state is read. If the DDR bit is one (output) the associated port data register bit state is read.

This register is not in the on-chip map in expanded and peripheral modes. It is reset to $00 so the DDR does not override the three-state control signals.

DDRA7-0 — Data Direction Port A

1 = Configure the corresponding I/O pin as an output

0 = Configure the corresponding I/O pin as an input

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12.3.3 Port B Data Register (PORTB)

Address: Base + $___1

BIT 7 6 5 4 3 2 1 BIT 0

Read:

Write:

Reset:

Single Chip:

Bit 7

-

PB7

6

-

PB6

5

-

PB5

4

-

PB4

3

-

PB3

2

-

PB2

1

-

PB1

Bit 0

-

PB0

Exp Wide, Emul. Nar with IVIS & Periph:

Expanded Narrow:

AB/DB7 AB/DB6 AB/DB5 AB/DB4 AB/DB3 AB/DB2 AB/DB1 AB/DB0

AB7 AB6 AB5 AB4 AB3 AB2

Figure 12-5 Port B Data Register (PORTB)

AB1 AB0

Read: anytime when register is in the map

Write: anytime when register is in the map Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively. When this port is not used for external addresses, such as in single-chip mode, these pins can be used as general purpose I/O. Data Direction

Register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB.

This register is not in the on-chip map in expanded and peripheral modes

CAUTION:

To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register.

12.3.4 Data Direction Register B (DDRB)

Read:

Write:

Reset:

Address: Base + $___3

BIT 7 6

Bit 7 6

5

5

4

4

3

3

2

2

0 0 0 0 0 0

Figure 12-6 Data Direction Register B (DDRB)

1

1

0

Read: anytime when register is in the map

Write: anytime when register is in the map

BIT 0

Bit 0

0

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This register controls the data direction for Port B. When Port B is operating as a general purpose I/O port,

DDRB determines the primary direction for each Port B pin. A “1” causes the associated port pin to be an output and a “0” causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTB register. If the DDR bit is zero (input) the buffered pin input state is read. If the DDR bit is one (output) the associated port data register bit state is read.

This register is not in the on-chip map in expanded and peripheral modes. It is reset to $00 so the DDR does not override the three-state control signals.

DDRB7-0 — Data Direction Port B

1 = Configure the corresponding I/O pin as an output

0 = Configure the corresponding I/O pin as an input

12.3.5 Port E Data Register (PORTE)

Read:

Write:

Reset:

Address: Base + $___8

BIT 7 6

Bit 7 6

Alt. Pin Function:

5

5

4

4

3

3

2

2

-

NOACC

MODB or

IPIPE1 or

CLKTO

MODA or

IPIPE0

= Unimplemented

-

ECLK

-

LSTRB or TAG-

LO

-

R/W

Figure 12-7 Port E Data Register (PORTE)

1

Bit 1

BIT 0

Bit 0

-

IRQ XIRQ

Read: anytime when register is in the map

Write: anytime when register is in the map

Port E is associated with external bus control signals and interrupt inputs. These include mode select

(MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read / write (R/W), IRQ, and XIRQ.

When not used for one of these specific functions, Port E pins 7-2 can be used as general purpose I/O and pins 1-0 can be used as general purpose input. The Port E Assignment Register (PEAR) selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general purpose I/O. DDRE also determines the source of data for a read of PORTE.

Some of these pins have software selectable pullups (PE7, ECLK, LSTRB, R/W, IRQ and XIRQ). A single control bit enables the pullups for all of these pins when they are configured as inputs

This register is not in the on-chip map in peripheral mode or in expanded modes when the EME bit is set

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CAUTION:

It is unwise to write PORTE and DDRE as a word access. If you are changing Port E pins from being inputs to outputs, the data may have extra transitions during the write. It is best to initialize

PORTE before enabling as outputs.

CAUTION:

To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register

12.3.6 Data Direction Register E (DDRE)

Read:

Write:

Reset:

Address: Base + $___9

BIT 7 6

Bit 7 6

5

5

4

4

3

3

2

Bit 2

0 0 0

= Unimplemented

0 0 0

Figure 12-8 Data Direction Register E (DDRE)

1

0

0

BIT 0

0

0

Read: anytime when register is in the map

Write: anytime when register is in the map

Data Direction Register E is associated with Port E. For bits in Port E that are configured as general purpose I/O lines, DDRE determines the primary direction of each of these pins. A “1” causes the associated bit to be an output and a “0” causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register. If the DDR bit is zero (input) the buffered pin input state is read. If the DDR bit is one (output) the associated port data register bit state is read.

This register is not in the on-chip map in peripheral mode. It is also not in the map in expanded modes while the EME control bit is set.

DDRE7-2 — Data Direction Port E

1 = Configure the corresponding I/O pin as an output

0 = Configure the corresponding I/O pin as an input

CAUTION:

It is unwise to write PORTE and DDRE as a word access. If you are changing Port E pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize

PORTE before enabling as outputs.

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12.3.7 Port E Assignment Register (PEAR)

Address:

Read:

Write:

Base + $___A

BIT 7 6

0

NOACC

E

Reset: 0 0

Reset:

Reset:

Reset:

Reset:

Reset:

Reset:

Reset:

0

0

1

1

0

0

0

0

0

0

5 4 3 2

PIPOE NECLK LSTRE RDWE

0

1

0

1

1

0

0

0

0

0

0

1

0

1

0

1

1

0

0

1

0

1

1

0

0

0

0

0

1

0

0

0

BIT 0

0

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0

= Unimplemented

Figure 12-9 Port E Assignment Register (PEAR)

0

0

0

0

0

0

0

Special

Single

Chip

Special

Test

Peripheral

Emulation

Exp Nar

Emulation

Exp Wide

Normal

Single

Chip

Normal

Exp Nar

Normal

Exp Wide

Read: anytime (provided this register is in the map).

Write: each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages.Port E serves as general purpose I/O or as system and bus control signals. The PEAR register is used to choose between the general purpose I/O function and the alternate control functions. When an alternate control function is selected, the associated DDRE bits are overridden.

The reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in some modes. In normal single chip mode, no external bus control signals are needed so all of Port E is configured for general purpose I/O. In normal expanded modes, only the E clock is configured for its alternate bus control function and the other bits of Port E are configured for general purpose I/O. As the reset vector is located in external memory, the E clock is required for this access. R/W is only needed by the system when there are external writable resources. If the normal expanded system needs any other bus control signals, PEAR would need to be written before any access that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB and

R/W are configured out of reset as bus control signals

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This register is not in the on-chip map in emulation and peripheral modes.

NOACCE - CPU No Access Output Enable

Normal: write once

Emulation: write never

Special: write anytime

1 = The associated pin (Port E bit 7) is output and indicates whether the cycle is a CPU free cycle.

0 = The associated pin (Port E bit 7) is general purpose I/O.

This bit has no effect in single chip or peripheral modes.

PIPOE - Pipe Status Signal Output Enable

Normal: write once

Emulation: write never

Special: write anytime.

1 = The associated pins (Port E bits 6:5) are outputs and indicate the state of the instruction queue

0 = The associated pins (Port E bits 6:5) are general purpose I/O.

This bit has no effect in single chip or peripheral modes.

NECLK - No External E Clock

Normal and Special: write anytime

Emulation: write never

1 = The associated pin (Port E bit-4) is a general purpose I/O pin.

0 = The associated pin (Port E bit-4) is the external E clock pin. External E clock is free-running if

ESTR=0

External E clock is available as an output in all modes.

LSTRE - Low Strobe (LSTRB) Enable

Normal: write once

Emulation: write never

Special: write anytime.

1 = The associated pin (Port E bit-3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK.

0 = The associated pin (Port E bit-3) is a general purpose I/O pin.

This bit has no effect in single chip, peripheral or normal expanded narrow modes.

NOTE:

LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled to provide an extra I/O pin. If LSTRB is needed, it should be enabled before any external writes. External reads do not normally need LSTRB because all

16 data bits can be driven even if the system only needs 8 bits of data.

RDWE - Read / Write Enable

Normal: write once

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Emulation: write never

Special: write anytime

1 = The associated pin (Port E bit-2) is configured as the R/W pin

0 = The associated pin (Port E bit-2) is a general purpose I/O pin.

This bit has no effect in single chip or peripheral modes.

NOTE:

R/W is used for external writes. After reset in normal expanded mode, R/W is

disabled to provide an extra I/O pin. If R/W is needed it should be enabled before

any external writes.

12.3.8 MODE Register (MODE)

Address: Base + $___B

BIT 7 6

Read:

Write:

MODC MODB

5

MODA

Reset: 0 0 0

Reset:

Reset:

Reset:

0

0

0

0

1

1

1

0

1

Reset:

Reset:

Reset:

Reset:

1

1

1

1

0 0

0

0

0

0

4

0

0

3

IVIS

1

1

0

1

0

0

0

0

0

2

0

0

0

1

1

1

0

1

0

0

0

0

0

0

0

0

0

= Unimplemented

Figure 12-10 MODE Register (MODE)

0

0

0

0

1

0

1

1

EMK

0

BIT 0

EME

0

0

0

0

1

0

1

0

Special

Single chip

Emulation

Exp Nar

Special

Test

Emulation

Exp Wide

Normal

Single

Chip

Normal

Exp Nar

Peripheral

Normal

Exp Wide

Read: anytime (provided this register is in the map).

Write: each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages.

The MODE register is used to establish the operating mode and other miscellaneous functions (i.e. internal visibility and emulation of Port E and K).

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In peripheral modes, this register is not accessible but it is reset as shown to configure system features.

Changes to bits in the MODE register are delayed one cycle after the write.

This register is not in the on-chip map in emulation and peripheral modes.

MODC, MODB, MODA - Mode Select bits

These bits indicate the current operating mode.

If MODA=1, then MODC, MODB, MODA are write never.

If MODC=MODA=0, then MODC, MODB, MODA are write anytime except that you cannot change to or from peripheral mode

If MODC=1, MODB=0 and MODA=0, then MODC is write never, and MODB, MODA are write once, except that you cannot change to peripheral, special test, special single chip, or emulation modes.

Table 12-2 MODC, MODB, MODA Write Capability

1

MODC

0

MODB

0

MODA

0

Mode

Special Single Chip

MODx Write Capability

MODC, B, A write anytime but not to 110

2

0

0

0

1

1

0

Emulation Narrow

Special Test no write

MODC, B, A write anytime but not to 110

2

0

1

1

1

0

0

1

0

1

Emulation Wide

Normal Single Chip

Normal Expanded Narrow no write

MODC write never, MODB, A write once but not to 110 no write

1 1 0 Special Peripheral no write

1

NOTES:

1 1 Normal Expanded Wide no write

1. No writes to the MOD bits are allowed while operating in a SECURE mode. For more details refer to the security specification document.

2. If you are in a special single chip or special test mode and you write to this register, changing to normal single chip mode, then one allowed write to this register remains. If you write to normal expanded or emulation mode, then no writes remain.

Input

BKGD

& bit

MODC

0

0

Input

& bit

MODB

Table 12-3 Mode Select and State of Mode Bits

Input

& bit

MODA

Mode Description

0

0

0

1

Special Single Chip, BDM allowed and ACTIVE. BDM is “allowed” in all other modes but a serial command is required to make BDM “active”.

Emulation Expanded Narrow, BDM allowed

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Input

BKGD

& bit

MODC

0

0

1

1

1

1

Input

& bit

MODB

1

1

0

0

1

1

Table 12-3 Mode Select and State of Mode Bits

Input

& bit

MODA

0

1

0

1

0

1

Mode Description

Special Test (Expanded Wide), BDM allowed

Emulation Expanded Wide, BDM allowed

Normal Single Chip, BDM allowed

Normal Expanded Narrow, BDM allowed

Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used)

Normal Expanded Wide, BDM allowed

IVIS - Internal Visibility (for both read and write accesses)

This bit determines whether internal accesses generate a bus cycle that is visible on the external bus.

Normal: write once

Emulation: write never

Special: write anytime

1 = Internal bus operations are visible on external bus.

0 = No visibility of internal bus operations on external bus.

Reference Section 12.4.9 for mode availability of this bit.

EMK - Emulate Port K

Normal: write once

Emulation: write never

Special: write anytime

1 = If in any expanded mode, PORTK and DDRK are removed from the memory map.

0 = PORTK and DDRK are in the memory map so Port K can be used for general purpose I/O.

In single-chip modes, PORTK and DDRK are always in the map regardless of the state of this bit.

In peripheral modes, PORTK and DDRK are never in the map regardless of the state of this bit.

EME - Emulate Port E

Normal and Emulation: write never

Special: write anytime

1 = If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally.

0 = PORTE and DDRE are in the memory map so Port E can be used for general purpose I/O.

In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit.

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12.3.9 Pullup Control Register (PUCR)

Read:

Write:

Reset:

1

Address: Base + $___C

BIT 7 6

0

PUPKE

1

5

0

0 0

= Unimplemented

4

PUPEE

1

3

0

0

2

0

0

1

PUPBE PUPAE

0

BIT 0

0

Figure 12-11 Pullup Control Register (PUCR)

NOTES:

1. The reset state of this register may be controlled by an instantiation parameter as described in the

HCS12 V1.5 Core Integration Guide. The default value of this parameter is shown. Please refer to the specific device User’s Guide to determine the actual reset state of this register.

Read: anytime (provided this register is in the map).

Write: anytime (provided this register is in the map).

This register is used to select pullup resistors for the pins associated with the core ports. Pullups are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input.

This register is not in the on-chip map in emulation and peripheral modes.

NOTE:

These bits have no effect when the associated pin(s) are outputs. (The pullups are inactive.)

PUPKE - Pullup Port K Enable

1 = Enable pullup devices for Port K input pins.

0 = Port K pullups are disabled.

PUPEE - Pullup Port E Enable

1 = Enable pullup devices for Port E input pins bits 7, 4-0.

0 = Port E pullups on bit 7, 4-0 are disabled.

PUPBE - Pullup Port B Enable

1 = Enable pullup devices for all Port B input pins.

0 = Port B pullups are disabled.

PUPAE - Pullup Port A Enable

1 = Enable pullup devices for all Port A input pins.

0 = Port A pullups are disabled.

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12.3.10 Reduced Drive Register (RDRIV)

Read:

Write:

Reset:

Address: Base + $___D

BIT 7 6

0

RDPK

5

0

4

RDPE

3

0

2

0

0 0 0

= Unimplemented

0 0 0

Figure 12-12 Reduced Drive Register (RDRIV)

1

RDPB

0

BIT 0

RDPA

0

Read: anytime (provided this register is in the map)

Write: anytime (provided this register is in the map)

This register is used to select reduced drive for the pins associated with the core ports. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). This feature would be used on ports which have a light loading. The reduced drive function is independent of which function is being used on a particular port.

This register is not in the on-chip map in emulation and peripheral modes.

RDPK - Reduced Drive of Port K

1 = All Port K output pins have reduced drive enabled.

0 = All Port K output pins have full drive enabled.

RDPE - Reduced Drive of Port E

1 = All Port E output pins have reduced drive enabled.

0 = All Port E output pins have full drive enabled.

RDPB - Reduced Drive of Port B

1 = All Port B output pins have reduced drive enabled.

0 = All Port B output pins have full drive enabled.

RDPA - Reduced Drive of Ports A

1 = All Port A output pins have reduced drive enabled.

0 = All Port A output pins have full drive enabled.

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12.3.11

External Bus Interface Control Register (EBICTL)

Address:

BIT 7

0

Base + $___E

6 5

0 0

4

0

3

0

2

0

1

0

BIT 0

Read:

Write:

ESTR

Reset:

Reset:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

= Unimplemented

Figure 12-13 External Bus Interface Control Register (EBICTL)

Peripheral

All other modes

Read: anytime (provided this register is in the map)

Write: refer to individual bit descriptions below

The EBICTL register is used to control miscellaneous functions (i.e. stretching of external E clock).

This register is not in the on-chip map in peripheral mode.

ESTR - E clock Stretches

This control bit determines whether the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles.

Normal and Emulation: write once

Special: write anytime

1 = E stretches high during stretch cycles and low during non-visible internal accesses.

0 = E never stretches (always free running).

This bit has no effect in single chip modes.

12.3.12 IRQ Control Register (IRQCR)

Address Base + $__1E

Bit 7 6 5

0

4

0

3

0

2

0 Read:

Write:

Reset:

IRQE IRQEN

0 1 0 0 0 0

Figure 12-14 IRQ Control Register (IRQCR)

0

Read: see individual bit descriptions below

Write: see individual bit descriptions below

1

0

Bit 0

0

0

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IRQE - IRQ select edge sensitive only

Special: read or write anytime

Normal: read anytime, write once

Emulation: read anytime, write never

1 = IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt

(i.e. vector = $FFF2).

0 = IRQ configured for low level recognition

IRQEN - External IRQ enable

Normal, emulation, and special modes: read or write anytime

1 = External IRQ pin is connected to interrupt logic.

0 = External IRQ pin is disconnected from interrupt logic

NOTE:

In this state the edge detect latch is disabled.

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12.3.13 Reserved Registers.

Address:

Read:

Write:

Reset:

Address:

Read:

Write:

Reset:

BIT 7

Base + $___4 thru $___7

6 5

0 0 0

4

0

0

0

0

0

Base + $___F

0

0

0

0

0

3

0

0

0

2

0

0

0

0 0

= Unimplemented

0 0 0

Figure 12-15 Reserved Registers

1

0

0

0

0

BIT 0

0

0

0

0

These register locations are not used (reserved). All unused registers and bits in this block return logic zeros when read. Writes to these registers have no effect.

These registers are not in the on-chip map in peripheral mode.

12.3.14 Port K Data Register (PORTK).

Address: Base + $32

Bit 7 6

Read:

Write:

Alt. pin function

Reset:

Bit 7

ECS

6

XCS

5

5

4

4

3

3

2

2

1

1

Bit 0

Bit 0

XAB19 XAB18 XAB17 XAB16 XAB15 XAB14

-

= Unimplemented

Figure 12-16 Port K Data Register (PORTK)

-

Read: anytime

Write: anytime

This port is associated with the internal memory expansion emulation pins. When the port is not enabled to emulate the internal memory expansion, the port pins are used as general-purpose I/O. When Port K is operating as a general purpose I/O port, DDRK determines the primary direction for each Port K pin. A

“1” causes the associated port pin to be an output and a “0” causes the associated pin to be a

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high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding

PORTK register. If the DDR bit is zero (input) the buffered pin input is read. If the DDR bit is one (output) the output of the port data register is read.This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set.

When inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the

PUPKE bit in the PUCR register.

Bit 7- Port K bit 7.

This bit is used as an emulation chip select signal for the emulation of the internal memory expansion, or as general purpose I/O, depending upon the state of the EMK bit in the MODE register. While this bit is used as a chip select, the external bit will return to its de-asserted state (vdd) for approximately

1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0). See the HCS12v1.5 MMC spec for additional details on when this signal will be active.

Bit 6 — Port K bit 6.

This bit is used as an external chip select signal for most external accesses that are not selected by ECS

(see the MMC spec for more details), depending upon the state the of the EMK bit in the MODE register. While this bit is used as a chip select, the external pin will return to its de-asserted state (vdd) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0).

Bit 5 - Bit 0 — Port K bits 5 - 0.

These six bits are used to determine which Flash/ROM or external memory array page is being accessed. They can be viewed as expanded addresses XAB19 - XAB14 of the 20-bit address used to access up to1M byte internal Flash/ROM or external memory array. Alternatively, these bits can be used for general purpose I/O depending upon the state of the EMK bit in the MODE register.

12.3.15 Port K Data Direction Register (DDRK)

Address: Base + $33

Bit 7

Read:

Write:

Reset:

Bit 7

0

6

Bit 6

5

5

0 0

= Unimplemented

4

4

0

3

3

0

2

2

0

1

1

0

Figure 12-17 Port K Data Direction Register (DDRK)

Bit 0

Bit 0

0

Read: anytime.

Write: anytime.

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This register determines the primary direction for each port K pin configured as general-purpose I/O. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set.

DDRK 7-0 - The Data Direction Port K.

1 = Associated pin is an output

0 = Associated pin is a high-impedance input

CAUTION:

It is unwise to write PORTK and DDRK as a word access. If you are changing Port K pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize

PORTK before enabling as outputs.

CAUTION:

To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing to the DDRK register before reading from the PORTK register.

12.4 Operation

There are four main sub-blocks within the MEBI: external bus control, external data bus interface, control and registers.

12.4.1 External Bus Control

The external bus control generates the miscellaneous control functions (pipe signals, ECLK, LSTRB and

R/W) that will be sent external on Port E, bits 6-2. It also generates the external addresses.

12.4.2 External Data Bus Interface

The external data bus interface block manages data transfers from/to the external pins to/from the internal read and write data buses. This block selectively couples 8-bit or 16-bit data to the internal data bus to implement a variety of data transfers including 8-bit, 16-bit, 16-bit swapped and 8-bit external to 16-bit internal accesses. Modes, addresses, chip selects, etc. affect the type of accesses performed during each bus cycle.

12.4.3 Control

The control block generates the register read/write control signals and miscellaneous port control signals.

12.4.4 Registers

The register block includes the fourteen 8-bit registers and five reserved register locations associated with the MEBI sub-block.

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12.4.5 External System Pin Functional Descriptions

In typical SoC implementations, the MEBI sub-block of the Core interfaces directly with external system pins.

Table 12-4

below outlines the pin names and functions and gives a brief description of their

operation.

Pin Name

PA7/A15/D15/D7 thru

PA0/A8/D8/D0

PB7/A7/D7 thru

PB0/A0/D0

PE7/

NOACC

PE6/IPIPE1/

MODB/CLKTO

PE5/IPIPE0/

MODA

PE4/ECLK

Table 12-4 External System Pins Associated With MEBI

Pin Functions

PA7 - PA0

A15 - A8

D15 - D8

D15/D7 thru

D8/D0

PB7 - PB0

A7 - A0

D7 - D0

PE7

NOACC

MODB

PE6

IPIPE1

CLKTO

MODA

PE5

IPIPE0

PE4

ECLK

Description

General purpose I/O pins, see PORTA and DDRA registers.

High-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system.

High-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, peripheral mode & visible internal accesses (IVIS=1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W.

Alternate high-order and low-order bytes of the bidirectional data lines multiplexed during ECLK high in expanded narrow modes and narrow accesses in wide modes. Direction of data transfer is generally indicated by R/W.

General purpose I/O pins, see PORTB and DDRB registers.

Low-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system.

Low-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, peripheral mode & visible internal accesses (with IVIS=1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W.

General purpose I/O pin, see PORTE and DDRE registers.

CPU No Access output. Indicates whether the current cycle is a free cycle. Only available in expanded modes.

At the rising edge of RESET, the state of this pin is registered into the MODB bit to set the mode.

General purpose I/O pin, see PORTE and DDRE registers.

Instruction pipe status bit 1, enabled by PIPOE bit in PEAR.

System Clock Test Output. Only available in special modes. PIPOE=1 overrides this function. The enable for this function is in the clock module.

At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode.

General purpose I/O pin, see PORTE and DDRE registers.

Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.

General purpose I/O pin, see PORTE and DDRE registers.

Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses. ECLK is controlled by the NECLK bit in

PEAR, the IVIS bit in MODE and the ESTR bit in EBICTL.

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Pin Name

PE3/LSTRB/

TAGLO

PE2/R/W

PE1/IRQ

PE0/XIRQ

PK7/ECS

PK6/XCS

PK5/X19 thru

PK0/X14

BKGD/MODC/

TAGHI

PE1

IRQ

PE0

XIRQ

PK7

ECS

PK6

XCS

PK5 - PK0

X19 - X14

Table 12-4 External System Pins Associated With MEBI

Pin Functions

PE3

LSTRB

SZ8

TAGLO

PE2

R/W

MODC

BKGD

TAGHI

Description

General purpose I/O pin, see PORTE and DDRE registers.

Low strobe bar, 0 indicates valid data on D7-D0.

In peripheral mode, this pin is an input indicating the size of the data transfer

(0=16-bit; 1=8-bit).

In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue.

General purpose I/O pin, see PORTE and DDRE registers.

Read/write, indicates the direction of internal data transfers. This is an output except in peripheral mode where it is an input.

General purpose input-only pin, can be read even if IRQ enabled.

Maskable interrupt request, can be level sensitive or edge sensitive.

General purpose input-only pin.

Non-maskable interrupt input.

General purpose I/O pin, see PORTK and DDRK registers.

emulation chip select

General purpose I/O pin, see PORTK and DDRK registers.

external data chip select

General purpose I/O pins, see PORTK and DDRK registers.

Memory expansion addresses

At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.)

Pseudo-open-drain communication pin for the single-wire background debug mode. There is an internal pullup resistor on this pin.

When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue.

12.4.6 Detecting Access Type from External Signals

The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that would produce LSTRB=AB0=1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases

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the data for the address that was accessed is on the low half of the data bus and the data for address+1 is on the high half of the data bus.

Table 12-5 Access Type vs. Bus Control Pins

LSTRB

1

0

1

0

0

1

0

1

0

1

0

AB0

0

1

1

0

1

0

0

1

R/W

1

1

1

0

0

Type of Access

8-bit read of an even address

8-bit read of an odd address

8-bit write of an even address

8-bit write of an odd address

16-bit read of an even address

16-bit read of an odd address

(low/high data swapped)

16-bit write to an even address

16-bit write to an odd address

(low/high data swapped)

12.4.7 Stretched Bus Cycles

In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the

HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block of the Core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle, write data would already be driven onto the data bus so the length of time write data is valid is extended in the case of a stretched bus cycle Read data would not be captured by the system until the E clock falling edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the falling edge of the stretched E clock. The external address, chip selects, and R/W signals remain valid during the period of stretching (throughout the stretched E high time)

12.4.8 Modes of Operation

The MEBI sub-block controls the mode of the Core operation through the use of the BKGD, MODB and

MODA external system pins which are captured into the MODC, MODB and MODA controls bits, respectively, at the rising edge of the system RESET pin. The setup and hold times associated with these pins are given in

Table 12-6

below.

Table 12-6 Mode Pin Setup and Hold Timing

Characteristic

Mode programming setup time (time before reset is detected high that mode pins must hold their state to guarantee the proper state is entered)

Timing

2 bus clock cycles

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Table 12-6 Mode Pin Setup and Hold Timing

Characteristic

Mode programming hold (time after reset is detected high that mode pins must hold their state to guarantee the proper state is entered)

Timing

0 ns

The four 8-bit Ports (A, B, E and K) associated with the MEBI sub-block can serve as general purpose I/O pins or alternatively as the address, data and control signals for a multiplexed expansion bus. Address and data are multiplexed on Ports A and B. The control pin functions are dependent on the operating mode and the control registers PEAR and MODE. The initial state of bits in the PEAR and MODE registers are also established during reset to configure various aspects of the expansion bus. After the system is running, application software can access the PEAR and MODE registers to modify the expansion bus configuration.

Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU condition code register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup. Bit-0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ also can be enabled by bits in the CPU condition code register but it is inhibited at reset so this pin is initially configured as a simple input with a pullup. The ESTR bit in the

EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset.

The following subsections discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.

12.4.8.1 Special Single Chip Mode

When the system is reset in this mode, the background debug mode is enabled and “active”. The system does not fetch the reset vector and execute application code as it would in other modes. Instead, the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the system to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the system was reset.

There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional

I/O pins that are configured as high-impedance inputs with internal pullups enabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset.

All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with pullups enabled. PE4/ECLK is configured as the E clock output in this mode.

The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,

IPIPE0, LSTRB, and R/W, respectively, while the system is in single chip modes.The associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in this mode does not change the operation of the associated Port E pins.

Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically, the only use for an E clock output while the system is in single chip modes would be to get a constant speed clock for use in the external application system.

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12.4.8.2 Emulation Expanded Narrow Mode

Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR,

PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1.

Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data

D0 is associated with PB0.

The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,

PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted.

The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.

12.4.8.3 Peripheral Mode

This mode is intended for Motorola factory testing of the system. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole system acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the system into a different operating mode.

12.4.8.4 Emulation Expanded Wide Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the system. These signals can also be used by a logic analyzer to monitor the progress of application programs.

The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0,

PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted.

The main difference between emulation modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.

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12.4.8.5 Normal Single Chip Mode

There is no external expansion bus in this mode. All pins of Ports A, B and K are configured as general purpose I/O pins. Port E bits 1 and 0 are available as general purpose input only pins with internal pullups and the other remaining pins are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pullups enabled.

The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,

IPIPE0, LSTRB, and R/W while the system is in single chip modes. The associated control bits PIPOE,

LSTRE, and RDWE, respectively, are reset to zero. Writing the opposite state into them in this mode does not change the operation of the associated Port E pins.

In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.

Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically, the only use for an E clock output while the system is in single chip modes would be to get a constant speed clock for use in the external application system.

12.4.8.6 Normal Expanded Narrow Mode

This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices.

Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles.

Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write.

The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to “1” in this mode, the state of LSTRE is overridden and Port

E bit 3 cannot be reconfigured as the LSTRB output.

It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special test mode or occasionally emulation expanded narrow mode.

The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system.

The PE2/R/W pin is initially configured as a general purpose input with a pullup but this pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin.

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12.4.8.7 Special Test Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.

12.4.8.8 Normal Expanded Wide Mode

In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and

Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the system.

Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pullup resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the

PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose

I/O pins.

It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the emulation variation of this mode.

The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in

PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin.

The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications.

The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system.

12.4.9 Internal Visibility

Internal visibility is available when the system is operating in expanded wide modes, special test mode, or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes.

Internal visibility is enabled by setting the IVIS bit in the MODE register.

If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the

LSTRB pins will remain at their previous state.

When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external to prevent possible corruption of external devices. Specifically, during cycles when the BDM is selected,

R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated

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with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state.

12.4.10 Secure Mode

When the system is operating in a secure mode, internal visibility is not available (i.e. IVIS=1 has no effect). Also, the IPIPE signals will not be visible, regardless of operating mode. IPIPE1-IPIPE0 will display zeroes if they are enabled. In addition, the MOD bits in the MODE control register cannot be written.

12.5 Low-Power Options

The MEBI does not contain any user-controlled options for reducing power consumption. The operation of the MEBI in low-power modes is discussed in the following subsections.

12.5.1 Run Mode

The MEBI does not contain any options for reducing power in run mode; however, the external addresses are conditioned with expanded mode to reduce power in single chip modes.

12.5.2 Wait Mode

The MEBI does not contain any options for reducing power in wait mode.

12.5.3 Stop Mode

The MEBI will cease to function during execution of a CPU STOP instruction.

12.6 Motorola Internal Information

This subsection details information about the MEBI sub-block that is for Motorola use only and should not be published in any form outside of Motorola.

12.6.1 Peripheral Mode Operation

The only way to enter peripheral mode is via reset with the pins configured as shown in Table 12-7. The

only way to exit peripheral mode is to change the mode pin configuration and pull reset. It is not possible to enter/exit peripheral mode by writing the MODx bits in the MODE register.

Table 12-7 Peripheral Mode Pin Configuration

MODC (BKGD)

1

MODB (PE6)

1

MODA (PE5)

0

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Peripheral mode is a special mode immediately out of reset. It may be changed to a normal mode by writing the PNORME bit in the MTST1 register of the MMC sub-block to ‘1’.

In peripheral mode, the direction of the address and data buses is reversed compared to other modes of operation. Address, R/W and SZ8 all come from the external test system and drive the bus interface pins of Ports A, B and E of the system. The data bus is configured to pass data directly through Ports A and B to the internal data bus. Accesses are all initiated by the external test system.

The burden of deciding which port to access for 8-bit data or swapped data is the responsibility of the external test system. The MEBI does not modify peripheral mode accesses in any way. Misaligned 16-bit accesses are not allowed to blocks that require two cycles to complete such as system peripherals.

Misaligned 16-bit accesses are allowed to blocks that can handle fast transfers such as a RAM memory block.

12.6.2 Special Test Clock

When the peri_test_clk_enable signal at the Core interface is asserted in special modes, the peri_test_clk signal will be driven out on Port E, bit 6 when PIPOE=0.

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Section 13 Breakpoint (BKP)

This section describes the functionality of the Breakpoint (BKP) sub-block of the Core.

13.1 Overview

The Breakpoint sub-block of the Core provides for hardware breakpoints that are used to debug software on the CPU by comparing actual address and data values to predetermined data in setup registers. A successful comparison will place the CPU in Background Debug Mode or initiate a software interrupt

(SWI).

The Breakpoint sub-block contains two modes of operation:

• Dual Address Mode, where a match on either of two addresses will cause the system to enter

Background Debug Mode or initiate a Software Interrupt (SWI).

• Full Breakpoint Mode, where a match on address and data will cause the system to enter

Background Debug Mode or initiate a Software Interrupt (SWI).

There are two types of breakpoints, forced and tagged. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes. Tagged breakpoints will only occur on addresses. Tagging on data is not allowed; however, if this occurs nothing will happen within the BKP.

The BKP allows breaking within a 256 byte address range and/or within expanded memory. It allows matching of the data as well as the address and to match 8-bit or 16-bit data. Forced breakpoints can match on a read or a write cycle.

13.1.1 Features

• Full or Dual Breakpoint Mode

– Compare on address and data (Full)

– Compare on either of two addresses (Dual)

• BDM or SWI Breakpoint

– Enter BDM on breakpoint (BDM)

– Execute SWI on breakpoint (SWI)

• Tagged or Forced Breakpoint

– Break just before a specific instruction will begin execution (TAG)

– Break on the first instruction boundary after a match occurs (Force)

• Single, Range or Page address compares

– Compare on address (Single)

– Compare on address 256 byte (Range)

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– Compare on any 16K Page (Page)

• Compare address on read or write on forced breakpoints

• High and/or low byte data compares

13.1.2 Block Diagram

A block diagram of the Breakpoint sub-block is shown in

Figure 13-1

below. The Breakpoint contains

three main sub-blocks: the Register Block, the Compare Block and the Control Block. The Register Block consists of the eight registers that make up the Breakpoint register space. The Compare Block performs all required address and data signal comparisons. The Control Block generates the signals for the CPU for the tag high, tag low, force SWI and force BDM functions. In addition, it generates the register read and write signals and the comparator block enable signals.

NOTE:

There is a two cycle latency for address compares for forces, a two cycle latency for write data compares, and a three cycle latency for read data compares.

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Clocks and control signals

. . . . . .

CONTROL BLOCK

Breakpoint Modes and generation of SWI, force BDM & tags

BKP control signals

. . . . . .

EXPANSION

ADDRESS

ADDRESS

WRITE DATA

READ DATA

REGISTER BLOCK

BKPCT0

BKPCT1

BKP Read Data Bus

BKP0X

Write Data Bus

BKP0H

BKP0L

BKP1X

BKP1H

BKP1L

COMPARE BLOCK

Comparator

Comparator

Comparator

Comparator

Comparator

Comparator

Comparator

Comparator expansion addresses address high address low expansion addresses

Data/Address

High Mux

Data/Address

Low Mux

read data high data high address high data low address low read data low

Figure 13-1 Breakpoint Block Diagram

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13.2 Interface Signals

All interfacing with the Breakpoint sub-block is done within the Core.

13.3 Registers

A summary of the registers associated with the Breakpoint sub-block is shown in

Figure 13-2

below.

Detailed descriptions of the registers and bits are given in the subsections that follow.

Address Name

$0028 BKPCT0 read write

Bit 7 6 5 4

BKEN BKFULL BKBDM BKTAG

3

0

2

0

1

0

Bit 0

0

$0029 BKPCT1 read write

BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW

$002A BKP0X read write

0 0

BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0

$002B

$002C

BKP0H read write

Bit 15

BKP0L read write

Bit 7

14

6

13

5

12

4

11

3

10

2

9

1

Bit 8

Bit 0

$002D BKP1X read write

$002E

0

BKP1H read write

Bit 15

$002F BKP1L read write

Bit 7

0

14

6

BK1V5

13

5

BK1V4

12

4

BK1V3

11

3

BK1V2

10

2

BK1V1

9

1

BK1V0

Bit 8

Bit 0

= Unimplemented X = Indeterminate

Figure 13-2 Breakpoint Register Summary

13.3.1 Breakpoint Control Register 0 (BKPCT0)

Read: anytime

Write: anytime

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Address $0028

Bit 7

Read:

6 5 4

BKEN BKFULL BKBDM BKTAG

Write:

Reset: 0 0 0 0

3

0

2

0

1

0

0 0 0

= Reserved or unimplemented

Figure 13-3 Breakpoint Control Register 0 (BKPCT0)

Bit 0

0

0

This register is used to set the breakpoint modes.

BKEN - Breakpoint Enable

This bit enables the module

0 = Breakpoint module off

1 = Breakpoint module on

BKFULL - Full Breakpoint Mode Enable

This bit controls whether the breakpoint module is in Dual Mode or Full Mode

0 = Dual Address Mode enabled

1 = Full Breakpoint Mode enabled

BKBDM - Breakpoint Background Debug Mode Enable

This bit determines if the breakpoint causes the system to enter Background Debug Mode(BDM) or initiate a Software Interrupt (SWI)

0 = Go to Software Interrupt on a compare

1 = Go to BDM on a compare

BKTAG — Breakpoint on Tag

This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint

0 = On match, break at the next instruction boundary (force)

1 = On match, break if the match is an instruction that will be executed (tagged)

13.3.2 Breakpoint Control Register 1 (BKPCT1)

Read: anytime

Write: anytime

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Address $0029

Bit 7

Read:

Write:

Reset:

6 5 4

BK0MBH BK0MBL BK1MBH BK1MBL

0 0 0 0

3

BK0RW

E

0

2

BK0RW

BK1RW

E

BK1RW

0

1

0

Bit 0

0

Figure 13-4 Breakpoint Control Register 1 (BKPCT1)

This register is used to configure the functionality of the Breakpoint sub-block within the Core.

BK0MBH:BK0MBL - Breakpoint Mask High Byte and Low Byte for First Address

In Dual or Full Mode, these bits may be used to mask (disable) the comparison of the high and low bytes of the first address breakpoint. The functionality is as given in

Table 13-1

below

Table 13-1 Breakpoint Mask Bits for First Address

BK0MBH:BK0MBL

x:0

0:1

1:1

NOTES:

1. If page is selected.

Address Compare

Full Address Compare

256 byte Address Range

16K byte Address Range

BKP0X

Yes

1

Yes

(1)

Yes

(1)

BKP0H

Yes

Yes

No

BKP0L

Yes

No

No

The x:0 case is for a Full Address Compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are

{BKP0X[5:0],BKP0H[5:0],BKP0L[7:0]}. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are

{BKP0H[7:0],BKP0L[7:0]}.

The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the

BK0MBH control bit).

The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if

BKP0X compares.

BK1MBH:BK1MBL - Breakpoint Mask High Byte and Low Byte of Data (Second Address)

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In Dual Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in

Table 13-2

below.

Table 13-2 Breakpoint Mask Bits for Second Address (Dual Mode)

BK1MBH:BK1MBL

x:0

0:1

1:1

NOTES:

1. If page is selected.

Address Compare

Full Address Compare

256 byte Address Range

16K byte Address Range

BKP1X BKP1H

Yes

1

Yes

Yes

(1)

Yes

(1)

Yes

No

BKP1L

Yes

No

No

The x:0 case is for a Full Address Compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are

{BKP1X[5:0],BKP1H[5:0],BKP1L[7:0]}. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are

{BKP1H[7:0],BKP1L[7:0]}.

The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the

BK1MBH control bit).

The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if

BKP1X compares.

In Full Mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in

Table 13-3

below.

Table 13-3 Breakpoint Mask Bits for Data Breakpoints (Full Mode)

BKP1H BKP1L BK1MBH:BK1MBL

0:0

Data Compare

High and Low Byte

Compare

BKP1X

No

1

0:1

1:0

High Byte

Low Byte

No

(1)

No

(1)

1:1 No Compare

No

(1)

NOTES:

1. Expansion addresses for breakpoint 1 are not available in this mode.

Yes

Yes

No

No

Yes

No

Yes

No

BK0RWE - R/W Compare Enable

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Enables the comparison of the R/W signal for first address breakpoint. This bit is not useful in tagged breakpoints.

0 = R/W is not used in the comparisons

1 = R/W is used in comparisons

BK0RW - R/W Compare Value

When BK0RWE=1, this bit determines the type of bus cycle to match on first address breakpoint.

When BK0RWE=0, this bit has no effect.

0 = Write cycle will be matched

1 = Read cycle will be matched

BK1RWE - R/W Compare Enable

In Dual Mode, this bit enables the comparison of the R/W signal to further specify what causes a match for the second address breakpoint. This bit is not useful on tagged breakpoints or in Full Mode and is therefore a don’t care.

0 = R/W is not used in comparisons

1 = R/W is used in comparisons

BK1RW — R/W Compare Value

When BK1RWE=1, this bit determines the type of bus cycle to match on the second address breakpoint.When BK1RWE=0, this bit has no effect.

0 = Write cycle will be matched

1 = Read cycle will be matched

13.3.3 Breakpoint First Address Expansion Register (BKP0X)

Read: anytime

Write: anytime

Address $002A

Bit 7

0 Read:

Write:

Reset:

0

6

0

0

5 4

BK0V5 BK0V4

0 0

3 2 1

BK0V3 BK0V2 BK0V1

0 0 0

Bit 0

BK0V0

0

= Reserved or unimplemented

Figure 13-5 Breakpoint First Address Expansion Register (BKP0X)

This register contains the data to be matched against expansion address lines for the first address breakpoint when a page is selected.

BK0V[5:0] - Value of first breakpoint address to be matched in memory expansion space.

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13.3.4 Breakpoint First Address High Byte Register (BKP0H)

Read: anytime

Write: anytime

Address $002B

Bit 7 6 5 4 3 2 1 Bit 0

Read

:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:

0 0 0 0 0 0 0 0

Figure 13-6 Breakpoint First Address High Byte Register (BKP0H)

This register is used to set the breakpoint when compared against the high byte of the address.

13.3.5 Breakpoint First Address Low Byte Register (BKP0L)

Read: anytime

Write: anytime

Address $002C

Bit 7

Read

:

Write:

Bit 7

Reset:

0

6

6

0

5

5

0

4

4

0

3

3

0

2

2

0

1

1

0

Bit 0

Bit 0

0

Figure 13-7 Breakpoint First Address Low Byte Register (BKP0L)

This register is used to set the breakpoint when compared against the low byte of the address.

13.3.6 Breakpoint Second Address Expansion Register (BKP1X)

Read: anytime

Write: anytime

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Address $002D

Read:

Bit 7

0

Write:

Reset:

0

6

0

0

5

BK1V5

0

4

BK1V4

0

= Reserved or unimplemented

3

BK1V3

0

2

BK1V2

0

1

BK1V1

0

Bit 0

BK1V0

0

Figure 13-8 Breakpoint Second Address Expansion Register (BKP1X)

In Dual Mode, this register contains the data to be matched against expansion address lines for the second address breakpoint when a page is selected. In Full Mode, this register is not used.

BK1V[5:0] - Value of first breakpoint address to be matched in memory expansion space.

13.3.7 Breakpoint Data (Second Address) High Byte Register (BKP1H)

Read: anytime

Write: anytime

Address $002E

Bit 7 6 5 4 3 2 1 Bit 0

Read

:

Bit 15 14 13 12 11 10 9 Bit 8

Write:

Reset:

0 0 0 0 0 0 0

Figure 13-9 Breakpoint Data High Byte Register (BKP1H)

0

In Dual Mode, this register is used to compare against the high order address lines. In Full Mode, this register is used to compare against the high order data lines.

13.3.8 Breakpoint Data (Second Address) Low Byte Register (BKP1L)

Read: anytime

Write: anytime

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Address

$002F

Bit 7 6 5 4 3 2 1 Bit 0

Read:

Write:

Bit 7 6 5 4 3 2 1 Bit 0

Reset: 0 0 0 0 0 0 0

Figure 13-10 Breakpoint Data Low Byte Register (BKP1L)

0

In Dual Mode, this register is used to compare against the low order address lines. In Full Mode, this register is used to compare against the low order data lines.

13.4 Operation

The Breakpoint sub-block supports two modes of operation: Dual Address Mode and Full Breakpoint

Mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before a specific instruction executes. The action taken upon a successful match can be to either place the

CPU in Background Debug Mode or to initiate a software interrupt.

13.4.1 Modes of Operation

The Breakpoint can operate in Dual Address Mode or Full Breakpoint Mode. Each of these modes is discussed in the subsections below.

13.4.1.1 Dual Address Mode

When Dual Address Mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter Background Debug Mode or to initiate a software interrupt based upon the state of the

BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode.

The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is force or tag. The

BKxMBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The BKxRW and BKxRWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read, write, or both when performing forced breakpoints.

13.4.1.2 Full Breakpoint Mode

Full Breakpoint Mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter Background Debug Mode or initiate a software interrupt based upon the state of the BKBDM bit in the BKPCT0 Register being logic one or logic zero, respectively. BDM requests have a higher priority than SWI requests. R/W matches are also allowed in this mode.

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The BKTAG bit in the BKPCT0 register selects whether the breakpoint mode is forced or tagged. If the

BKTAG bit is set in BKPCT0, then only address is matched, and data is ignored. The BK0MBH:L bits in the BKPCT1 register select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BK1MBH:L bits in the BKPCT1 register select whether the data is matched on the high byte, low byte, or both bytes. The BK0RW and BK0RWE bits in the BKPCT1 register select whether the type of bus cycle to match is a read or a write when performing forced breakpoints. BK1RW and

BK1RWE bits in the BKPCT1 register are not used in Full Breakpoint Mode.

13.4.2 Breakpoint Priority

Breakpoint operation is first determined by the state of BDM. If BDM is already active, meaning the CPU is executing out of BDM firmware, Breakpoints are not allowed. In addition, while in BDM trace mode, tagging into BDM is not allowed. If BDM is not active, the Breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints.

In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block.

This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the

Breakpoint sub-block.

NOTE:

BDM should not be entered from a breakpoint unless the ENABLE bit is set in the

BDM. Even if the ENABLE bit in the BDM is negated, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if enable is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow.

There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled.

13.5 Motorola Internal Information

The Breakpoint sub-block does not contain any information that is considered to be for Motorola use only.

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Section 14 Background Debug Mode (BDM)

This section describes the functionality of the Background Debug Mode (BDM) sub-block of the Core.

14.1 Overview

The Background Debug Mode (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin.

14.1.1 Features

• Single-wire communication with host development system

• Active out of reset in special single-chip mode

• Nine hardware commands using free cycles, if available, for minimal CPU intervention

• Hardware commands not requiring active BDM

• 15 firmware commands execute from the standard BDM firmware lookup table

• Instruction tagging capability

• Software control of BDM operation during wait mode

• Software selectable clocks

• BDM disabled when secure feature is enabled

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14.1.2 Block Diagram

The block diagram of the BDM is shown in

Figure 14-1

below.

HOST

SYSTEM

BKGD

16-BIT SHIFT REGISTER

ENTAG

BDMACT

TRACE

INSTRUCTION DECODE

AND EXECUTION

BUS INTERFACE

AND

CONTROL LOGIC

ADDRESS

DATA

CLOCKS

SDV

ENBDM standard

BDM firmware

LOOKUP TABLE

CLKSW

Figure 14-1 BDM Block Diagram

14.2 Interface Signals

A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the Multiplexed External Bus Interface (MEBI) sub-block and all interfacing between the MEBI and BDM is done within the Core interface boundary. The functional descriptions of the pins are provided below for completeness.

• BKGD — Background interface pin

• TAGHI — High byte instruction tagging pin

• TAGLO — Low byte instruction tagging pin

BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin.

14.2.1 Background Interface Pin (BKGD)

Debugging control logic communicates with external devices serially via the single-wire background interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.

14.2.2 High Byte Instruction Tagging Pin (TAGHI)

This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue.

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14.2.3 Low Byte Instruction Tagging Pin (TAGLO)

This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue.

14.3 Registers

A summary of the registers associated with the BDM is shown in

Figure 14-2

below. Registers are

accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow.

Address

Register

Name

$FF00 Reserved

Read:

Write:

Bit 7

X

6

X

5

X

4

X

3

X

2

X

1

0

Bit 0

0

$FF01 BDMSTS

Read:

Write:

ENBDM BDMACT ENTAG SDV TRACE CLKSW

UNSEC

X X X X X X X

$FF02 Reserved

Read:

Write:

$FF03 Reserved

Read:

Write:

$FF04 Reserved

Read:

Write:

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

X

X

X

$FF05 Reserved

Read:

Write:

X X X X X X X X

$FF06 BDMCCR

Read:

Write:

CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

0 0 0

$FF07 BDMINR

Read: REG15 REG14 REG13 REG12 REG11

Write:

= Unimplemented X = Indeterminate

Figure 14-2 BDM Register Map Summary

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14.3.1 BDM Status Register

Address: $FF01

Bit 7 6 5 4 3 2 1

Read:

ENBDM BDMACT ENTAG SDV TRACE CLKSW

Write:

UNSEC

Reset:

Special single-chip mode:

0 1 0 0 0 0 0

Special peripheral mode:

0 1 0 0 0 0 0

All other modes:

0 0 0 0 0 0 0

= Unimplemented

Figure 14-3 BDM Status Register

(BDMSTS)

Bit 0

0

0

0

0

Read: All modes through BDM operation

Write: All modes but subject to the following:

– BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode.

– CLKSW can only be written via BDM hardware or standard BDM firmware write commands.

– All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution.

– ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in Special Single Chip Mode).

ENBDM - Enable BDM

This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed.

1 = BDM enabled

0 = BDM disabled

NOTE:

ENBDM is set by the firmware immediately out of reset in special single-chip mode.

In secure mode, this bit will not be set by the firmware until after the EEPROM and

FLASH erase verify tests are complete.

BDMACT - BDM active status

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This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map.

1 = BDM active

0 = BDM not active

ENTAG - Tagging enable

This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active.

1 = Tagging enabled

0 = Tagging not enabled, or BDM active

SDV - Shift data valid

This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution.

1 = Data phase of command is complete

0 = Data phase of command not complete

TRACE - TRACE1 BDM firmware command is being executed

This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized.

1 = TRACE1 command is being executed

0 = TRACE1 command is not being executed

CLKSW - Clock switch

The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware

BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active. The start of the next BDM command uses the new clock for timing subsequent BDM communications.

1 = BDM system operates with bus rate

0 = BDM system operates with alternate clock

WARNING:

The BDM will not operate with CLKSW = 0 if the frequency of the alternate clock source, peri_phase_oscdX, is greater than one half of the bus frequency. Please refer to the users guide for the clock generation module to determine if this condition can occur.

UNSEC - Unsecure

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This bit is only writable in special single chip mode from the BDM secure firmware and always gets reset to zero. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table.

The secure BDM firmware lookup table verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted.

1 = the system is in a unsecured mode

0 = the system is in a secured mode

WARNING:

When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that if the user does not change the state of the bits to "unsecured" mode, the system will be secured again when it is next taken out of reset.

14.3.2 BDM CCR Holding Register

Address: $FF06

Bit 7 6 5 4 3 2 1 Bit 0

Read:

CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

Write:

Reset: 0 0 0 0 0 0 0 0

Figure 14-4 BDM CCR Holding Register (BDMCCR)

Read: All modes

Write: All modes

NOTE:

When BDM is made active, the CPU stores the value of the CCR register in the

BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to $D8 and not $D0 which is the reset value of the CCR register.

When entering background debug mode, the BDM CCR holding register is used to save the contents of the condition code register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value.

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14.3.3 BDM Internal Register Position Register

Address: $FF07

Bit 7 6 5 4 3 2 1

Read: REG15 REG14 REG13 REG12 REG11

Write:

Reset: 0 0 0

= Unimplemented

0 0

0

0

0

0

Figure 14-5 BDM Internal Register Position (BDMINR)

Bit 0

0

0

Read: All modes

Write: Never

REG15–REG11 - Internal register map position

These five bits show the state of the upper five bits of the base address for the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space.

14.4 Operation

The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands.

Hardware commands are used to read and write target system memory locations and to enter active

background debug mode (see 14.4.3). Target system memory includes all memory that is accessible by the

CPU.

Firmware commands are used to read and write CPU resources and to exit from active background debug

mode (see 14.4.4). The CPU resources referred to are the accumulator (D), X index register (X), Y index

register (Y), stack pointer (SP), and program counter (PC).

Hardware commands can be executed at any time and in any mode excluding a few exceptions as

highlighted in 14.5 below. Firmware commands can only be executed when the system is in active

background debug mode (BDM).

14.4.1 Security

If the user resets into special single chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.

The secure BDM firmware verifies that the on-chip EEPROM and Flash EEPROM are erased. This being the case, the UNSEC bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off. If the EEPROM and FLASH do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This

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causes the BDM hardware commands to become enabled, but does not enable the software commands.

This allows the BDM hardware to be used to erase the EEPROM and FLASH.

14.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE.

After being enabled, BDM is activated by one of the following

1

:

• Hardware BACKGROUND command

• BDM external instruction tagging mechanism

• CPU BGND instruction

• Breakpoint sub-block’s force or tag mechanism

2

When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction.

NOTE:

If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed.

In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses

$FF00 to $FFFF. BDM registers are mapped to addresses $FF00 to $FF07. The BDM uses these registers which are readable anytime by the BDM. These registers are not, however, readable by user programs.

14.4.3 BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, Flash EEPROM, I/O and control registers, and all external memory.

Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,

NOTES:

1. BDM is enabled and active immediately out of special single-chip reset (see 14.5.2).

2. This method is only available on systems that have a a Breakpoint sub-block.

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if an operation requires multiple cycles, the CPU is frozen until the operation is complete, even though the

BDM found a free cycle.

The BDM hardware commands are listed in

Table 14-1

.

Table 14-1 Hardware Commands

Command

BACKGROUN

READ_BD_BYTE

READ_BD_WORD

READ_BYTE

READ_WORD

WRITE_BD_BYTE

WRITE_BD_WORD

WRITE_BYTE

WRITE_WORD

Opcode

(hex)

90

E4

EC

E0

E8

C4

CC

C0

C8

Data

None

16-bit address

16-bit data out

16-bit address

16-bit data out

16-bit address

16-bit data out

16-bit address

16-bit data out

16-bit address

16-bit data in

16-bit address

16-bit data in

16-bit address

16-bit data in

16-bit address

16-bit data in

Description

Enter background mode if firmware is enabled.

Read from memory with standard BDM firmware lookup table in map.

Odd address data on low byte; even address data on high byte

Read from memory with standard BDM firmware lookup table in map

.

Must be aligned access.

Read from memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte

Read from memory with standard BDM firmware lookup table out of map

.

Must be aligned access.

Write to memory with standard BDM firmware lookup table in map.

Odd address data on low byte; even address data on high byte

Write to memory with standard BDM firmware lookup table in map

.

Must be aligned access

Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte

Write to memory with standard BDM firmware lookup table out of map. Must be aligned access.

The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.

14.4.4 Standard BDM Firmware Commands

Firmware commands are used to access and manipulate CPU resources. The system must be in active

BDM to execute standard BDM firmware commands (see 14.4.2). Normal instruction execution is

suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.

As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at $FF00-$FFFF, and the CPU begins executing the standard BDM

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firmware. The standard BDM firmware watches for serial commands and executes them as they are

received. The firmware commands are shown in Table 14-2.

Table 14-2 Firmware Commands

Command

READ_NEXT

READ_PC

READ_D

READ_X

READ_Y

READ_SP

WRITE_NEXT

WRITE_PC

WRITE_D

WRITE_X

WRITE_Y

WRITE_SP

GO

TRACE1

TAGGO

42

46

47

08

10

18

43

44

45

Opcode

(hex)

62

63

64

65

66

67

Data

16-bit data out

16-bit data out

16-bit data out

16-bit data out

16-bit data out

16-bit data out

16-bit data in

16-bit data in

16-bit data in

16-bit data in

16-bit data in

16-bit data in none none none

Description

Increment X by 2 (X = X + 2), then read word X points to.

Read program counter.

Read D accumulator.

Read X index register.

Read Y index register.

Read stack pointer.

Increment X by 2 (X=X+2), then write word to location pointed to by X.

Write program counter.

Write D accumulator.

Write X index register.

Write Y index register.

Write stack pointer.

Go to user program.

Execute one user instruction then return to active BDM.

Enable tagging and go to user program.

14.4.5 BDM Command Structure

Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a

16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name.

NOTE:

8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB.

NOTE:

16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits.

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For hardware data read commands, the external host must wait 150 target clock cycles

1 after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the

BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 target clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 target clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle.

For firmware read commands, the external host must wait 32 target clock cycles after sending the command opcode before attempting to obtain the read data. This allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For firmware write commands, the external host must wait 32 target clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed.

The external host should wait 64 target clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table.

Figure 14-6 represents the BDM command structure. The command blocks illustrate a series of eight bit

times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8

×

16 target clock cycles.

HARDWARE

READ

8 BITS

AT ~16 TC/BIT

COMMAND

16 BITS

AT ~16 TC/BIT

ADDRESS

150-TC

DELAY

16 BITS

AT ~16 TC/BIT

DATA

NEXT

COMMAND

150-TC

DELAY

HARDWARE

WRITE

COMMAND

FIRMWARE

READ

COMMAND

32-TC

DELAY

ADDRESS

DATA

FIRMWARE

WRITE

GO,

TRACE

DATA

NEXT

COMMAND

COMMAND DATA

NEXT

COMMAND

32-TC

DELAY

NEXT

COMMAND

COMMAND

64-TC

DELAY

NEXT

COMMAND

Figure 14-6 BDM Command Structure

TC = TARGET CLOCK CYCLES

NOTES:

1. Target clock cycles are cycles measured using the target system’s serial clock rate. See 14.4.6 and 14.3.1 for information on

how serial clock rate is selected.

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14.4.6 BDM Serial Interface

The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM.

The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register (see

14.3.1). This clock will be referred to as the target clock in the following explanation.

The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host.

The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pullup and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases.

The timing for host-to-target is shown in Figure 14-7 and that of target-to-host in Figure 14-8 and Figure

14-9 below. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since

the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time.

Figure 14-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of

a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission.

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.

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CLOCK

TARGET SYSTEM

HOST

TRANSMIT 1

HOST

TRANSMIT 0

PERCEIVED

START OF BIT TIME

TARGET SENSES BIT

10 CYCLES

SYNCHRONIZATION

UNCERTAINTY

Figure 14-7 BDM Host-to-Target Serial Bit Timing

EARLIEST

START OF

NEXT BIT

The receive cases are more complicated. Figure 14-8 shows the host receiving a logic 1 from the target

system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the

BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.

CLOCK

TARGET SYSTEM

HOST

DRIVE TO

BKGD PIN

TARGET SYSTEM

SPEEDUP

PULSE

PERCEIVED

START OF BIT TIME

BKGD PIN

HIGH-IMPEDANCE

R-C RISE

HIGH-IMPEDANCE

HIGH-IMPEDANCE

10 CYCLES

10 CYCLES

HOST SAMPLES

BKGD PIN

Figure 14-8 BDM Target-to-Host Serial Bit Timing (Logic 1)

EARLIEST

START OF

NEXT BIT

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Figure 14-9 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,

there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.

CLOCK

TARGET SYS.

HOST

DRIVE TO

BKGD PIN

TARGET SYS.

DRIVE AND

SPEEDUP PULSE

PERCEIVED

START OF BIT TIME

BKGD PIN

HIGH-IMPEDANCE

SPEEDUP PULSE

10 CYCLES

10 CYCLES

EARLIEST

START OF

NEXT BIT

HOST SAMPLES

BKGD PIN

Figure 14-9 BDM Target-to-Host Serial Bit Timing (Logic 0)

14.4.7 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the

TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time.

If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.

14.4.8 Instruction Tagging

The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the

CPU at a specific instruction, because execution already has begun by the time an operation is visible outside the system. A separate instruction tagging mechanism is provided for this purpose.

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The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction.

NOTE:

Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active.

Executing the BDM TAGGO command configures two system pins for tagging. The TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal.

Table 14-3 shows the functions of the two tagging pins. The pins operate independently, that is, the state

of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. Low tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode).

Table 14-3 Tag Pin Function

TAGHI

1

1

0

0

TAGLO

1

0

1

0

Tag

No tag

Low byte

High byte

Both bytes

14.5 Modes of Operation

BDM is available in all operating modes but must be enabled before firmware commands are executed.

Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode.

In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory.

BDM is also active out of special peripheral mode reset and can be turned off by clearing the BDMACT bit in the BDM status (BDMSTS) register. This allows testing of the BDM memory space as well as the user’s memory space.

NOTE:

The BDM serial system should not be used in special peripheral mode since the

CPU, which in other modes interfaces with the BDM to relinquish control of the bus during a free cycle or a steal operation, is not operating in this mode.

14.5.1 Normal Operation

BDM operates the same in all normal modes.

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14.5.2 Special Operation

14.5.2.1 Special single-chip mode

BDM is enabled and active immediately out of reset. This allows programming a system with blank memory.

14.5.2.2 Special peripheral mode

BDM is enabled and active immediately out of reset. BDM can be disabled by clearing the BDMACT bit in the BDM status (BDMSTS) register. The BDM serial system should not be used in special peripheral mode.

14.5.3 Emulation Modes

In emulation modes, the BDM operates as in all normal modes.

14.6 Low-Power Options

14.6.1 Run Mode

The BDM does not include disable controls that would conserve power during run mode.

14.6.2 Wait Mode

The BDM cannot be used in wait mode if the system disables the clocks to the BDM.

14.6.3 Stop Mode

The BDM is completely shutdown in stop mode.

14.7 Interrupt Operation

The BDM does not generate interrupt requests.

14.8 Motorola Internal Information

This subsection details information about the BDM sub-block that is for Motorola use only and should not be published in any form outside of Motorola.

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14.8.1 Registers

This section gives detailed descriptions of all internally accessible registers and bits that are either not available or not disclosed to users external to Motorola. These registers were highlighted as being reserved

BDM registers previously in this section of the guide.

The BDM instruction (BDMIST) register is written by the BDM hardware as a result of a BDM command sent to the system via the BKGD pin. The individual bits decode into categories of BDM instruction. The two descriptions of the BDMIST below show the instruction decode when categorized as hardware or firmware instructions.

All of the BDM registers are readable and writable in special peripheral mode on the parallel bus until the

BDMACT bit in the BDMSTS register is cleared at which time the BDM resources are no longer accessible via the peripheral bus and require a reset to be restored.

A full summary of the registers associated with the BDM is shown in

Figure 14-10

below.

Address

$FF00

$FF01

$FF02

$FF03

$FF04 BDMADDH

$FF05

$FF06

$FF07

Name

BDMIST

BDMSTS

BDMSHTH

BDMSHTL

BDMADDL

BDMCCR

BDMINR read write read write read write read write

Bit 7

H/F

S15

S7

6

DATA

S14

S6

5

R/W

ENBDM BDMACT ENTAG

S13

S5

4

BKGND

SDV

S12

S4

3

W/B

TRACE

S11

S3

2

BD/U

CLKSW

S10

S2

1

0

UNSEC

S9

S1

Bit 0

0

0

S8

S0 read write read write

A15

A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

A9

A1

A8

A0 read write

CCR7 CCR6 CCR5 CCR4 CCR3 read REG15 REG14 REG13 REG12 REG11 write

CCR2

0

CCR1

0

CCR0

0

= Unimplemented X = Indeterminate

Figure 14-10 BDM Register Map

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14.8.2 BDM Instruction Register (Hardware)

Address: $FF00

Bit 7

Read:

Write:

Reset:

H/F

6

DATA

5 4 3

R/W BKGND W/B

2

BD/U

1

0

0 0 0 0 0 0 0

Figure 14-11 BDM Instruction Register (BDMIST)

Bit 0

0

0

Read: All modes

Write: All modes; BDM hardware writes this register when a BDM command is received.

Hardware clears the register if 512 BDM clock cycles occur between falling edges from the host. Firmware clears this register when exiting from BDM active mode.

H/F - Hardware/firmware flag

When the BDM is active, standard BDM firmware checks for this bit to be set by the BDM hardware as part of a BDM instruction load.

1 = Hardware command

0 = Firmware command

DATA - Data flag

Shows that data accompanies the command.

1 = Data follows the command

0 = No data

R/W - Read/write flag

1 = Read

0 = Write

BKGND - Enter active background mode

1 = Hardware background command

0 = Not a hardware background command

W/B - Word/byte transfer flag

1 = Word transfer

0 = Byte transfer

BD/U - BDM map/user map flag

Indicates whether BDM access is to BDM registers and standard BDM firmware lookup table mapped to addresses $FF00 to $FFFF or the user resources in this range. Used only by hardware read/write commands.

1 = standard BDM firmware lookup table and registers in map

0 = User resources in map.

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14.8.3 BDM Instruction Register (Firmware)

Address: $FF00

Bit 7

Read:

Write:

Reset:

H/F

6

DATA

5

R/W

4

TTAGO

3 2 1

RNEXT

0 0 0 0 0 0 0

Figure 14-12 BDM Instruction Register (BDMIST)

Bit 0

0

Read: All modes

Write: All modes; BDM hardware writes this register when a BDM command is received.

Hardware clears the register if 512 BDM clock cycles occur between falling edges from the host. Firmware clears this register when exiting from BDM active mode.

H/F - Hardware/firmware flag

When the BDM is active, standard BDM firmware checks for this bit to be set by the BDM hardware as part of a BDM instruction load.

1 = Hardware command

0 = Firmware command

DATA - Data flag

This bit indicates that data accompanies the command.

1 = Data follows the command

0 = No data

R/W - Read/write flag

1 = Read

0 = Write

TTAGO - Trace, tag, go bits.

The decoding of TTAGO is shown in

Table 14-4

below.

Table 14-4 TTAGO Decoding

TTAGO value

00

01

10

11

Instruction

GO

TRACE1

TAGGO

RNEXT - Register/next bits

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Indicates which register is being affected by a command. In the case of a READ_NEXT or

WRITE_NEXT command, index register X is pre-incremented by 2 and the word pointed to by X is then read or written. The decoding of RNEXT is shown in

Table 14-5

below.

Table 14-5 RNEXT Decoding

RNEXT value

000

001

010

011

100

101

110

111

Instruction

READ/WRITE NEXT

PC

D

X

Y

SP

14.8.4 BDM Status Register

The BDM status (BDMSTS) register is described in

14.3.1

. In addition, it is readable and writable in special peripheral mode on the parallel bus.

BDMACT - BDM active status

BDMACT is set by the BDM and is cleared in the exit sequence of the standard BDM firmware.

BDMACT can be written to in special peripheral mode via the peripheral bus. It cannot be written to via BDM hardware commands in any mode, that is, it cannot be written to if the H/F bit in the BDMIST register is set.

Clearing BDMACT causes the standard BDM firmware lookup table and registers to be removed from the memory map and BDM to become inactive.

Setting BDMACT in special peripheral mode via the peripheral bus causes BDM to become active but does not put the standard BDM firmware lookup table and registers into the memory map; therefore,

BDMACT should not be set in this manner but should instead be set by resetting the system.

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14.8.5 BDM Shift Register

Address: $FF02

Bit 15

Read:

Write:

Reset:

S15

14

S14

13

S13

12

S12

11

S11

10

S10 S9

Figure 14-13 BDM Shift Register (BDMSHTH)

9

Address: $FF03

Bit 7

Read:

Write:

Reset:

S7

6

S6

5

S5

4

S4

3

S3

2

S2 S1

Figure 14-14 BDM Shift Register (BDMSHTL)

1

Bit 8

S8

Bit 0

S0

Read: All modes

Write: All modes

The 16-bit BDM shift register contains data being received or transmitted via the serial interface. It is also used by the standard BDM firmware for temporary storage.

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14.8.6 BDM Address Register

Address: $FF04

Bit 15

Read:

Write:

Reset:

A15

14

A14

13

A13

12

A12

11

A11

10

A10

9

A9

Figure 14-15 BDM Address Register (BDMADDH)

Address: $FF05

Bit 7

Read:

Write:

Reset:

A7

6

A6

5

A5

4

A4

3

A3

2

A2

1

A1

Figure 14-16 BDM Address Register (BDMADDL)

Bit 8

A8

Bit 0

A0

Read: All modes

Write: Can only be written by BDM hardware

In secure mode, if the BDM hardware commands have been enabled by the secure firmware, the upper 5 bits of the address register will always be forced to the value from the BDMINR register. This restricts access of the hardware commands to the register space only.

The 16-bit address register is loaded with the address to be accessed by BDM hardware commands.

14.8.7 Special Peripheral Mode

In Special Peripheral Mode the BDM is enabled and active immediately out of reset. BDM can be disabled

by clearing the BDMACT bit in the BDM status (BDMSTS) register (see 14.8.4). This allows testing the

BDM memory space as well as the user’s program memory space. The BDM serial system should not be used in special peripheral mode since the CPU, which in other modes relinquishes control of the bus during a free cycle or a steal operation, is not operating in this mode.

14.8.8 Standard BDM Firmware Listing

;*******************************************************************************

;

; Copyright (C) 1997 by Motorola Inc.

; 6501 William Cannon Drive West

; Advanced MCU HC11 Group

; Austin, TX 78735-8598

;

; All rights reserved. No part of this software may be sold or distributed

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;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

; in any form or by any means without the prior written permission of

; Motorola, Inc.

;

; MOTOROLA CONFIDENTIAL PROPRIETARY INFORMATION

;

;*******************************************************************************

;===============================================================================

; VERSION HISTORY

;

; Started from UDR HC12 BDM ROM code

;

;===============================================================================

;

;

;

; Design Strategy:

-standard BDM firmware for M68HC12

-There are MANY traps that someone modifying this code MUST be aware of.

Those areas that have traps that we have fallen into and requiring special care have been marked with CAUTION. Here is a list of items to BEWARE of. Review this list after ANY ROM code changes.

CAUTION 1. There is an inherent cpudead cycle that we rely on in the

INST_LOOP loop when that ldaa instruction falls on an even address. For this reason, an ALIGN directive MUST be used at that location. See AR#156.

CAUTION 2. The first event that occurs in code that may interfere with user code is the saving of all internal registers. When this BDM code is entered, all the internal registers such as

CCR, PC, X, etc. MUST be saved so that they may be restored to the user's value upon an exit from this code.

CAUTION 3. DO NOT insert code that affects the user CCR value before it gets saved. The code that saves the user CCR should be one of the very first items that occur at the beginning of this code. See AR#166.

CAUTION 4. The PC value MUST be checked to see if it was a BDM (op=00) instruction that got us into BDM. If so, PC gets adjusted by 1.

This works only if the user enters BDM from locations $0000 thru $FEFF because locations $FF00-$FFFF are blocked out for the

BDM. So, the BDM ROM is in the map and not the user's code.

CAUTION 5. Any unused space should be set to $00 to ensure ROM is plugged and verified properly. Be careful to NOT OVERLAP vector space when filling unused space!!! Using the ZMB directive helps because the assembler version we used just hangs up when code OVERLAPs BUT some other assembler version may not catch this.

CAUTION 6. The ROM code size is limited in available space. Make sure that when instructions are added, the vector space is not overwritten.

CAUTION 7. The reset vector was INST_DONE. Added code so that after a reset, the ccr value at reset is saved because the exit sequence was changing the CCR to the value that was saved before the reset occurred. The user should really initialize the CCR, but we do it here to avoid confusion.

CAUTION 8. The ENBDM bit MUST be set out of reset, otherwise it won't pass the "brset STATUS $80 INST_LOOP" test and the user gets kicked out of background unintentionally.

CAUTION 9. The Dev. Tools PRU relies on the BDM entry point "START" being at location $FF24. They also rely on the exit point being at location $FF77 (the exit jump). Any changes to the start and exit points MUST be reviewed with them.

CAUTION 10. Be careful that the BDMACT bit in the STATUS register is

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;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

;

; not unintentionally changed from a 1 to a 0 during 16-bit manipulation of the INSTRUCTION register. This will cause a race condition because BDMACT=0 will disable the standard BDM firmware

ROM while the CPU is executing this firmware.

-This is a list of instructions which use the temp2 (t2) and temp3 (t3) instructions. List as of 7-27-94. Gotten from Tom Poterek's BDMcode.

temp2

===== bgnd emacs etbl mem revw stop tbl wai execution of BDM ROM temp3

===== emacs etbl mem puld pulx puly rtc rti rts tbl wav execution of BDM ROM

********************************************************************************

********************************************************************************

* EQUATES

BDMVEC equ$fff6 ;First BDM ROM vector.

fff6 ff00 ff00 INSTR org$ff00 ;Start of BDM map (registers) rmb1 ;Instruction (command) register

* s/w ! H/S ! DATA ! R/W ! TTAG : GO ! R2 ! R1 ! R0 !

* hdw ! H/S ! DATA ! R/W !BKGND : W/B !BD/USR! NEXT ! - !

* Reg codes: R2:R1:R0

* 0:0:0 - Illegal, command $00 is null command

* 0:0:1 - not used

* 0:1:0 - Next Word 2,+X pre inc X by 2 and r/w next word (,X)

* later r/w next will work from ADDRESS reg value not X

* 0:1:1 - PC

* 1:0:0 - D

* 1:0:1 - X

* 1:1:0 - Y

* 1:1:1 - SP

* TTAG:GO coding:

* 0:0 - No execution command

* 0:1 - Go to user program

* 1:0 - Trace one user instruction and return to BDM

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ff01 ff02 ff04 ff06

* 1:1 - Tag Go command (reconfigure BKGD pin for tagging in)

STATUS rmb1 ;Status/Control register

* ! enBDM!BDACTV! TAG ! VALID: TRACE! - ! - ! - !

* Exit conditions vs value written to STATUS on exit

* BDM not allowed - $00

* Trace 1 - $88

* Go - $80

* Tag Go - $A0

SHIFTER rmb2 ;For serial data in/out

ADDRESS rmb2 ;Address for some commands

* ADDRESS will be read-only on first parts but later it will

* be r/w so r/w next word doesn't need to use X

CCRSAVE rmb1 ;Save user CCR value while in BDM

* CCRSAVE also used briefly to hold exit value for status

* during exit sequence to return to user code ff20 ff20 1c ff 01 80 ff24 b7 b4 ff26 b7 20 ff28 7a ff 06 ff2b b7 d3 ff2d 8e ff 00 ff30 24 04 ff32 e7 00 ff34 26 01 ff36 08 ff37 b7 d3 ff39 1e ff 01 80 06 ff3e 87 ff3f 20 1c ff41 79 ff 00

AFTER_RST orgff20 ;BDM ROM start

;*****CAUTION 7. *****CAUTION 8.

bset STATUS $80;Set the ENBDM bit to pass the brset

;test below.

;CCR immediately after rst is

;SXHINZVC=11x1xxxx.

;CCR after this bset is

;SXHINZVC=11x1100x. This is o.k.

;because the SXI bits are not

;affected.

START

ROM_INC

;*****CAUTION 2. *****CAUTION 9.

exgt3 d ;Save D without affecting CCR.

;This "exg t3 d" instruction MUST

;occur before the following

;"tfr ccr a" instruction.

;*****CAUTION 3.

tfrccr a staaCCRSAVE;Save user CCR value exgx t2 ;pc into x. *****CAUTION 4.

cpx#$FF00 ;Check to see if user PC overlaps BDM

;ROM.

bhsROM_INC;If so, increment regardless.

tst0,x ;Test next opcode. This instruction

;affects CCR so it MUST occur AFTER

;saving the user's CCR.

bneRES_X_T2;if not $00, restore inx ;else inc, then restore. This

;instruction affects CCR so it MUST

;occur AFTER saving the user's CCR.

RES_X_T2 exgx t2 ;restore pc to temp 2 brsetSTATUS $80 INST_LOOP ;Check if BDM allowed clra ;Exit if BDM not allowed braEXIT_SEQ

* Above is 1 of 4 ways to exit BDM to user code.

INST_DONE clrINSTR ;clear INSTR then wait for new inst

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ff44 ff44 b6 ff 00 ff47 2f fb ff49 85 18 ff4b 27 2e ff4d 81 10 ff4f 27 06 ff51 2b 08 ff53 86 a0 ff55 20 06 ff57 86 88 ff59 20 02 ff5b 86 80

;CAUTION 10.

* Top of main loop to wait for a software instruction

;*****CAUTION 1.

ALIGN 1 ;Make sure the following loop

;starting with ldaa is ALWAYS on an

;even boundary.

;See AR# 156 for more details.

INST_LOOP ldaaINSTR ;Wait for non-zero non-hdw command bleINST_LOOP;$00 is null command

;MSB of A set (neg) is hdw command bita#$18 ;TAGGO,TRACE, or GO commands?

beqNOT_EXE;Branch if not execution command cmpa#$10 ;TRACE ---1:0--- ? tp 4/7/95 beqTRACE bmiGO ;If not GO it's TAG GO

* Fall through from TAG_GO is 4th of 4 ways to exit to user code.

ldaa#$A0 ;enBDM + TAG bits in STATUS braEXIT_SEQ;Controlled exit (3 of 4)

TRACE ldaa#$88 ;enBDM + TRACE bits in STATUS braEXIT_SEQ;Controlled exit (2 of 4)

GO ldaa#$80 ;enBDM bit only in STATUS

EXIT_SEQ ff5d 79 ff 00 ff60 f6 ff 06 ff63 7a ff 06 ff66 b7 d3 ff68 7e ff 02 ff6b b7 d3 ff6d b7 12 ff6f b7 b4 ff71 18 0c ff 06 ff 01

* Upon entry to EXIT_SEQ, A contains a value to be written

* to the STATUS register. Seq restores user info and

* resumes user program where it left to enter active BD mode

;CAUTION 10.

clrINSTR ;clear instruction tp 4/6/95 ldabCCRSAVE;re-entry value for CCR staaCCRSAVE;will use movb to store to STATUS exgx t2 ;Swap X to Temp2 and User PC to X stxSHIFTER;For later indirect jump exgx t2 ;Restore user X tfrb ccr ;Restore user CCR exgt3 d ;Restore user D reg movbCCRSAVE STATUS;[OrPwPO] write w/o chg to ccr ff77 05 fb ff 87

* Critical timing: cycle signature of above move is OrPwPO

* Exit timing referenced to the byte-write in cycle 4

* Cycle signatures of remaining instructions in exit seq

* are shown in the comments. ROM switch from BD ROM to

* user map should occur at f cycle before PPP in exit jump

* If TRACE, issue liufbdm at T4 of the second last P cycle

* of the exit jump

* O r P w P O f I f P P P

* ! ! !

jmp(SHIFTER-(*+4)),pc] ;[fIfPPP] Exit to user PC

* In this exit jump, the I cycle is a word read of the user PC

* from the SHIFTER register (BD map). The PPP cycles are word

* fetches of user program info to fill instruction queue from

* user's map. The ROM switch must occur between I and PPP

* See also *****CAUTION 9. concerning this exit jump.

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NOT_EXE ff7b b7 01 ff7d 84 07 ff7f 80 02 ff81 2b be ff83 c5 20 ff85 26 37 ff87 f7 ff 00 ff8a 27 b8 ff8c 1f ff 01 10 f6 ff91 c6 07 ff93 12 ff94 05 fd ff96 fc ff 02 ff99 6c 21 ff9b 20 a4

WAIT_DATA tstINSTR ;Check for new command beqINST_LOOP;Need escape if old command aborted brclrSTATUS $10 WAIT_DATA ;Wait for data ready ldab#7 mul ;B = 7*(reg_code - 1) jmpb,pc ;Calculated GOTO

* Each write command corresponding to reg code 2-7 takes

* exactly 7 bytes. For command 2 (write next word) the jump will

* GOTO 0,pc or the location immediately after the jump

* For command 7 (write SP) the jump will go to (5*7),pc

* Each command ends with a branch to the main command loop

W_NXT_WRD lddSHIFTER;Get data to write std2,+x ;pre-inc x by 2 and store word

INST_DONE1 braINST_DONE;Intermediate branch to loop top

WRITE_PC tfra b ;Duplicate command in B anda#$07 ;Strip all but 3-bit reg code suba#2 ;codes 0 & 1 illegal or unused bmiINST_DONE;branch if A now negative bitb#$20 ;Check R/W bit bne;COMP_GOTO;Go decode read command (was beq

;tp 3/30) ff9d fc ff 02 ffa0 b7 c3 ffa2 20 9d lddSHIFTER;Get data to write exgd t2 ;User PC in Temp2 reg braINST_DONE;Branch to loop top

WRITE_D ffa4 fc ff 02 ffa7 b7 b4 ffa9 20 96 lddSHIFTER;Get data to write exgt3 d ;User D in Temp3 reg (was exg d t2

;tp 3/28) braINST_DONE;Branch to loop top ffab fe ff 02 ffae 20 91 ffb0 a7 ffb1 a7 ffb2 fd ff 02 ffb5 20 8a ffb7 a7 ffb8 a7 ffb9 ff ff 02 ffbc 20 83 ffbe 48 ffbf 48 ffc0 05 fc

WRITE_X ldxSHIFTER;Update X register braINST_DONE;Branch to loop top nop nop

;Pad to make command take 7 bytes

WRITE_Y

WRITE_SP ldsSHIFTER;Update SP register braINST_DONE;Branch to loop top

* No need to pad last command since we don't index past it.

COMP_GOTO ldySHIFTER;Update Y register braINST_DONE;Branch to loop top nop nop

;Pad to make command take 7 bytes asla ;x2 asla ;A = (reg_code - 2)*4 jmpa,pc ;Calculated GOTO

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ffc2 ec 21 ffc4 20 12 ffc6 20 21 ffc8 a7 ffc9 a7 ffca b7 34 ffcc 20 0a

* Each read command corresponding to reg code 2-7 takes

* exactly 4 bytes. For command 2 (read next word) the jump will

* GOTO 0,pc or the location immediately after the jump

* For command 7 (read SP) the jump will go to (5*4),pc

* Each command ends with a branch to the main command loop

R_NXT_WRD ldd2,+x ;pre-inc X by 2 and read word braR_COMMON;D->SHIFTER and bra loop top

READ_PC braREAD_PC1;This command needs 4 bytes nop ;Pad to make command take 4 bytes nop

READ_D tfrt3 d ;User D was in Temp3 braR_COMMON;D->SHIFTER and bra loop top

READ_X tfrx d ;Requested data to D braR_COMMON;D->SHIFTER and bra loop top ffce b7 54 ffd0 20 06

READ_Y ffd2 b7 64 ffd4 20 02 tfry d ;Requested data to D braR_COMMON;D->SHIFTER and bra loop top

READ_SP ffd6 b7 74 ffd8 7c ff 02 ffdb f7 ff 00 ffde 18 27 ff 62 ffe2 1f ff 01 10 f4 ffe7 20 b2

R_COMMON

WAIT

READ_PC1 ffe9 b7 c3 ffeb 7c ff 02 ffee b7 c3 fff0 20 e9 fff2 1b 89 fff4 20 a5 fff6 fff6 fff6 ff 24 fff8 ff f2 tfrsp d ;Requested data to D stdSHIFTER;Requested data to SHIFTER tst INSTR ;Check for new command tp 3/30 lbeq INST_LOOP;Need escape if old command aborted

;tp 3/30 brclrSTATUS $10 WAIT ;Wait for data ready tp 3/30 braINST_DONE1;Back to loop top

SWIV

ILLOPV exgd t2 ;User PC to D, junk to Temp2 std SHIFTER;User PC to SHIFTER exg d t2 ;User PC to Temp2, junk to D bra WAIT ;D->SHIFTER and bra loop top

FIXSP leas 9,sp;Restore sp braINST_DONE1;And try to resume

;*****CAUTION 5.

zmbBDMVEC-*;All unused space must be set to

;zero.

*****

* All other normal vectors are blocked out when in BDM. The bdmact

* signal goes into INT module and blocks all I and X interrupts.

*****CAUTION 6.

orgBDMVEC ;BDM vectors start fdbSTART ;SWI vector (normal entry point) fdbFIXSP ;Illegal opcode vector

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fffa ff 24 fffc ff 24 fffe ff 20

COPV

CMONV

RESETV fdbSTART fdbSTART

;COP watchdog error vector

;Clock monitor error vector fdbAFTER_RST;Reset vector (Sgl chip special)

;*********** end **************************************************************

14.8.9 Secured Mode BDM Firmware Listing

;*******************************************************************************

;

; Copyright (C) 1999 by Motorola Inc.

; MTC S-CORE Design Group

; 7600-C Capitol of Texas Highway

; Austin, TX 78731

; All rights reserved

; No part of this software may be sold or distributed

; in any form or by any means without the prior written

; permission of Motorola, Inc.

;

; MOTOROLA CONFIDENTIAL PROPRIETARY INFORMATION

;

;*******************************************************************************

; File: secure_firm.s

; Target: HCS12 Version 1.5

; Author: [email protected]

; Creation date: June 28, 1999

; Comments: This code is contained in the secure ROM

; of the BDM.

;===============================================================================

; VERSION HISTORY

;

; Ver 000 John Langan orig July 02, 1999

; update bug found by Lloyd, EERPOM size

; spec changes Aug. 27, 1999

;

; Ver 001George Grimmer 26 July 2000

; Enable BDM hardware commands when NVM erase verify fails,

; BDM commands will remain disabled if Flash security bits = 01

;===============================================================================

;

; Design Strategy:

;

; This code determines if the FLASH and EEPROM are erased

; If they are both erased, the program releases security,

; else it hangs (branches to self).

;

********************************************************************************

* Equates here

********************************************************************************

001c MEMSIZ0 equ $001C

0030 PPAGE equ $0030

0012 INITEE equ $0012 ff01 BDMSTS equ $FF01 ff20 BDMSTAR equ $FF20 fff6 VECTORS equ $FFF6

********************************************************************************

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; Code starts here.

ff80 org $FF80 ff80 START equ *

; Verify the FLASH is erased (all ones)

; Initialization ff80 ce 00 00 ldx #$0000 ; needed for indexing ff83 86 3f ldaa #$3F ff85 5a 30 staa PPAGE ; start with last page ff87 cc bf fe ldd #$BFFE ; last word in page

; We check every 128th word then change Page ff8a ed e6 FLOOP ldy D,X ; read word from FLASH ff8c 02 iny ; erased will become $0000 ff8d 26 36 bne FAIL ; not blank -> done ff8f 83 00 80 subd #$0080 ; point to next word ff92 2b f6 bmi FLOOP ; until we go under $8000

; On each succesive Page, we start at a different point

; such that if we only had one array we would check the

; entire array ff94 c3 3f fe addd #$3FFE ; point toward end of next page ff97 73 00 30 dec PPAGE ; change to next lower page ff9a 2a ee bpl FLOOP ; until we go under $00

; Completed FLASH verify if we make it here

; Verify the EEPROM is erased (all ones)

; Move EEPROM to $7800

; This will be $7000 if the size is 4K

; This will be $6000 if the size is 8K ff9c 86 79 ldaa #$79 ;bit 0 is EEON ff9e 5a 12 staa INITEE

; First, determine the size of the EEPROM ffa0 d6 1c ldab MEMSIZ0 ; size is encoded in bits 5 & 4 ffa2 c4 30 andb #$30 ; just the bits we need ffa4 27 15 beq ECLEAR ; no EEPROM, we’re done!

ffa6 86 78 ldaa #$78 ; set up for 2K size ffa8 c0 10 SLOOP subb #$10 ; 2K if clear after 1st subtract, ffaa 27 03 beq EECHK ; 2nd sub. is 4K, 3rd is 8K ffac 48 lsla ; adjust for next size ffad 20 f9 bra SLOOP

; Finally the erase verify loop

; Every ninth word is verified

; Accumulator D has already been set to the array size

; note that X still = 0 from earlier routines

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ffaf 84 78 EECHK anda #$78 ; index D + X = last word ffb1 ed e6 ELOOP ldy D,X ; read word from EEPROM ffb3 02 iny ; erased will become $0000 ffb4 26 0f bne FAIL ; not blank -> done ffb6 c3 00 12 addd #$0012 ; point to next word ffb9 2a f6 bpl ELOOP ; until we get to or under $4000

; When we arrive here, all is clear ffbb 86 42 ECLEAR ldaa #$42 ; bit #1 is UNSEC ffbd ce ff 01 ldx #BDMSTS ffc0 6a 00 staa 0,X ; use instr that ends with write cycle ffc2 06 ff 20 jmp BDMSTAR

; Failures arrive here, forever.....

ffc5 18 0b 3f 00 30 FAIL movb #$3f,PPAGE ffca f6 bf 0f ldab $BF0F ffcd ca fc orab #$FC ffcf ce ff 01 ldx #BDMSTS ffd2 86 80 ldaa #$80 ffd4 aa 00 oraa 0,x ffd6 53 decb ffd7 27 03 beq BDMLOCK ffd9 6a 00 staa 0,x ffdb a7 align 1

BDMLOCK ffdc a7 nop ffdd 20 fd bra BDMLOCK

; Clear out space between here and the vectors ffdf 00 00 00 00 00 00 zmb VECTORS-*

00 00 00 00 00 00

00 00 00 00 00 00

00 00 00 00 00

; VECTORS HERE fff6 org VECTORS fff6 ff 24 fdb BDMSTAR+4 ; SWI fff8 ff c5 fdb FAIL ; TRAP fffa ff 80 fdb START ; COP fffc ff 80 fdb START ; CLK Monitor fffe ff 80 fdb START ; RESET

;*********** end **************************************************************

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Section 15 Secured Mode of Operation

This section provides a brief description of the secured mode of operation of the Core. Detailed information relating to integration issues is provided in the HCS12 V1.5 Core Integration Guide.

15.1 Overview

The implementation of the secured mode of operation for the Core provides for protecting the contents of internal (on-chip) memory arrays. While in secured mode the system can execute in single-chip mode or from an external memory block but the contents of the internal memory will not be accessible and all normal BDM functions will be blocked from execution. A mechanism is provided to release the system from the secured mode at which time normal operation will resume allowing the system to be reconfigured for unsecured mode.

15.1.1 Features

The secured mode of operation provides:

• Protection of internal (on-chip) Flash EEPROM contents

• Protection of internal (on-chip) EEPROM contents

• Operation in single-chip mode while secured

• Operation from external memory with internal Flash and EEPROM disabled while secured

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15.1.2 Block Diagram

A block diagram of the Core security implementation is given in

Figure 15-1

.

HCS12 V1.5 Core

MMC

Module

Mapping

Control secreq

System Memories

Security Register core_secure_t2

Flash

EEPROM

Bus Signals

BDM

BKGD

Pin

BDM

Background

Debug

Mode

BDM

Unsecure

Signal

Secure

Signal

MEBI

Multiplexed External Bus Interface

Bus Signals

Bus Signals

EEPROM

RAM

Figure 15-1 Security Implementation Block Diagram

This figure includes one example system implementation of the Core security feature. In this implementation, the Flash EEPROM block contains a security register that is programmed to the proper secured/un-secured state which generates a security request to the Core. See

15.4

for a complete

description of the operation of the secured mode.

15.2 Interface Signals

The Core interface signals associated with the secured mode of operation are shown in

Table 15-1

below.

The functional descriptions of the signals are provided below for completeness.

Table 15-1 Security Interface Signal Definitions

Signal Name

core_secure_t2 secreq

Type Functional Description

O Core secure mode signal

I Security mode request from applicable memory

15.2.0.1 Core Secure Mode indicator (core_secure_t2)

This single bit Core output indicates that the Core is operating in secured mode.

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15.2.0.2 Core Security Request (secreq)

This single bit input indicates to the Core that the system memory is in a secured state and that the Core should operate in secured mode.

15.3 Registers

There are no registers in the Core associated with the secured mode of operation. Typically, a non-volatile memory block in the system will contain a register for programming the state of system security. Please refer to the chip-level and/or memory block documentation for implementation details.

15.4 Operation

When the system is configured for secured mode of operation, it will normally operate in either normal single-chip mode or in an expanded mode executing from external memory. The conditions imposed by secured mode for each of these operating modes is discussed in the subsections that follow as well as a description of the method to unsecure the system.

15.4.1 Normal Single-Chip Mode

Normal single-chip mode will be the most common operation of a system configured for secured mode.

The system functionality will appear just as an unsecured system with the exception imposed that the BDM operation will not be allowed and will be blocked. This will prevent any access to the internal non-volatile memory block contents.

15.4.2 Expanded Mode

To operate in secured mode and execute from external memory space, the system should be correctly configured for secured mode and then reset into expanded mode. The internal (on-chip) Flash EEPROM and EEPROM blocks (if applicable) will be disabled and unavailable. All BDM operation will be blocked.

In addition, while in secured mode all internal visibility (IVIS) and CPU pipe (IPIPE) information will be blocked from output.

15.4.3 Unsecuring The System

To unsecure a system that is configured for secured mode, the internal (on-chip) Flash EEPROM and

EEPROM must be fully erased. This can be performed using one of the following methods:

1.

Reset the microcontroller into SPECIAL TEST mode, execute a program which writes the Mass

Erase command sequence into the Flash and EEPROM Command registers.

2.

Reset the microcontroller into SPECIAL SINGLE CHIP mode, delay while the erase test is performed by the BDM secure ROM. Send BDM commands to write the Mass Erase command sequence into the Flash and EEPROM Command registers.

3.

Reset the microcontroller into SPECIAL PERIPHERAL mode, using SPM commands write the

Mass Erase command sequence into the Flash and EEPROM Command registers.

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In all modes the mass erase command sequence must have the following steps: a.

Write FCLKDIV register to set the Flash clock for proper timing.

b.

Write $00 to FCNFG register to select Flash block 0.

c.

Write $10 to FTSTMOD register to set WRALL bit.

(with WRALL set, all of the following writes to banked Flash registers will affect all Flash blocks.) d.

Disable Flash protection by writing the FPROT register.

e.

Write any data to Flash memory space $C000-$FFFF f.

Write Mass Erase command($41) to FCMD register.

g.

Clear CBIEF (bit 7) it FSTAT register.

h.

Write ECLKDIV register to set the EEPROM clock for proper timing.

i.

Disable protection in EEPROM by writing the EPROT register.

j.

Write any data to EEPROM memory space.

k.

Write Mass Erase command($41) to ECMD register.

l.

Clear CBIEF (bit 7) it ESTAT register.

m. Wait until all CCIF flags are set to 1 again.

After all the CCIF flags are set to 1 again, the Flash and EEPROM have been erased. Reset the microcontroller into SPECIAL SINGLE CHIP mode. The BDM secure ROM will verify that the nonvolatile memories are erased, and then it will assert the UNSEC bit in the BDM Status register. This will cause the core_secure_t2 signal to de-assert, and the microcontroller will be unsecure. All BDM commands will be enabled and the Flash security byte may be programmed to the unsecure state by any of the following methods:

1.

Send BDM commands to write to the MODE register and change to SPECIAL TEST mode, send a

BDM WRITE_PC, followed by a BDM GO command to jump to a program at an external address.

This external program can then program the Flash security byte to the unsecure state.

2.

.Send BDM commands to directly program the Flash security byte.

In all modes programming the security byte must have the following steps: a.

Write FCLKDIV register to set the Flash clock for proper timing.

b.

Write $00 to FCNFG register to select Flash block 0.

c.

Disable Flash protection by writing the FPROT register.

d.

Write $FFFE to address $FF0E e.

Write Program command($20) to FCMD register.

f.

Clear CBIEF (bit 7) it FSTAT register.

g.

Wait until Flash CCIF flag is set to 1 again.

After this Flash programming sequence is complete, the microcontroller can be reset into any mode, the

Flash has been unsecured.

In normal modes, either SINGLE CHIP or EXPANDED, the microcontroller may only be unsecured by using the backdoor key access feature. This requires knowledge of the contents of the backdoor keys, which must be written to the Flash memory space at the appropriate addresses, in the correct order. In addition, in SINGLE CHIP mode the user code stored in the Flash must have a method of receiving the backdoor key from an external stimulus. This external stimulus would typically be through one of the on-chip serial ports. After the backdoor sequence has been correctly matched, the microcontroller will be

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unsecured, and all Flash commands will be enabled and the Flash security byte can be programmed to the unsecure state, if desired.

Please note that if the system goes through a reset condition prior to successful configuration of unsecured mode the system will reset back into secured mode operation.

15.5 Motorola Internal Information

This subsection details information about the Core secured mode of operation that is for Motorola use only and should not be published in any form outside of Motorola.

15.5.1 BDM Secured Mode Firmware

When the Core is operating in secured mode and the system is reset into special single-chip mode, alternate

BDM firmware is invoked in place of the standard BDM firmware. A listing of this secured mode firmware is given in

14.8.9

of this guide.

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Appendix A Instruction Set and Commands

A.1 General

This glossary contains entries for all assembler mnemonics in alphabetical order. Each entry describes the operation of the instruction, its effect on the condition code register, and its syntax.

A.2 Glossary Notation

A.2.1 Condition Code State Notation

Table A-1 Condition Code State Notation

– Not changed by operation

0 Cleared by operation

1 Set by operation

Set or cleared by operation

May be cleared or remain set, but not set by operation

May be set or remain cleared, but not cleared by operation

? May be changed by operation but final state not defined

! Used for a special purpose

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A.2.2 Register and Memory Notation

Table A-2 Register and Memory Notation

A or a Accumulator A

An Bit n of accumulator A

B or b Accumulator B

Bn Bit n of accumulator B

D or d Accumulator D

Dn Bit n of accumulator D

X or x Index register X

X

H

High byte of index register X

X

L

Low byte of index register X

Xn Bit n of index register X

Y or y Index register Y

Y

H

High byte of index register Y

Y

L

Low byte of index register Y

Yn Bit n of index register Y

SP or sp Stack pointer

SPn Bit n of stack pointer

PC or pc Program counter

PC

H

High byte of program counter

PC

L

Low byte of program counter

CCR or c Condition code register

M Address of 8-bit memory location

Mn Bit n of byte at memory location M

Rn Bit n of the result of an arithmetic or logical operation

In Bit n of the intermediate result of an arithmetic or logical operation

RTN

H

High byte of return address

RTN

L

Low byte of return address

( ) Contents of

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A.2.3 Address Mode Notation

Table A-3 Address Mode Notation

INH Inherent; no operands in instruction stream

IMM Immediate; operand immediate value in instruction stream

DIR Direct; operand is lower byte of address from $0000 to $00FF

EXT Operand is a 16-bit address

REL Two’s complement relative offset; for branch instructions

IDX Indexed (no extension bytes); includes:

5-bit constant offset from X, Y, SP or PC

Pre/post increment/decrement by 1–8

Accumulator A, B, or D offset

IDX1 9-bit signed offset from X, Y, SP, or PC; 1 extension byte

IDX2 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes

[IDX2] Indexed-indirect; 16-bit offset from X, Y, SP, or PC

[D, IDX] Indexed-indirect; accumulator D offset from X, Y, SP, or PC

A.2.4 Operator Notation

Table A-4 Operator Notation

+ Add

– Subtract

AND

| OR

Exclusive OR

×

Multiply

÷

Divide

: Concatenate

Transfer

Exchange

A.2.5 Machine Code Notation

In the Machine Code (Hex) column on the glossary pages, digits 0–9 and upper case letters A–F represent hexadecimal values. Pairs of lower-case letters represent 8-bit values as shown in

Table A-5

.

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Table A-5 Machine Code Notation

dd

8-bit direct address from $0000 to $00FF; high byte is $00 ee

High byte of a 16-bit constant offset for indexed addressing eb

Exchange/transfer postbyte ff

Low eight bits of a 9-bit signed constant offset in indexed addressing, or low byte of a 16-bit constant offset in indexed addressing hh

High byte of a 16-bit extended address ii

8-bit immediate data value jj

High byte of a 16-bit immediate data value kk

Low byte of a 16-bit immediate data value lb

Loop primitive (DBNE) postbyte ll

Low byte of a 16-bit extended address mm

8-bit immediate mask value for bit manipulation instructions; bits that are set indicate bits to be affected pg

Program page or bank number used in CALL instruction qq

High byte of a 16-bit relative offset for long branches tn

Trap number from $30 to $39 or from $40 to $FF rr

Signed relative offset $80 (–128) to $7F (

+

127) relative to the byte following the relative offset byte, or low byte of a 16-bit relative offset for long branches xb

Indexed addressing postbyte

A.2.6 Source Form Notation

The Source Form column on the glossary pages gives essential information about assembler source forms. For complete information about writing source files for a particular assembler, refer to the documentation provided by the assembler vendor.

Everything in the Source Form column, except expressions in italic characters, is literal information which must appear in the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic is always a literal expression. All commas, pound signs (#), parentheses, square brackets ( [ or ] ), plus signs

(+), minus signs (–), and the register designation (A, B, D), are literal characters.

The groups of italic characters shown in

Table A-6

represent variable information to be supplied by the

programmer. These groups can include any alphanumeric character or the underscore character, but cannot include a space or comma. For example, the groups xysppc and oprx0_xysppc are both valid, but the two groups oprx0 xysppc are not valid because there is a space between them.

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Table A-6 Source Form Notation

abc abcdxysp abd abdxysp dxysp

Register designator for A, B, or CCR

Register designator for A, B, CCR, D, X, Y, or SP

Register designator for A, B, or D

Register designator for A, B, D, X, Y, or SP msk8

Register designator for D, X, Y, or SP

8-bit mask value

Some assemblers require the # symbol before the mask value.

opr8i opr16i opr8a opr16a page

8-bit immediate value

16-bit immediate value

8-bit address value used with direct address mode

16-bit address value oprx0_xysp Indexed addressing postbyte code: oprx3,–xysp — Predecrement X , Y, or SP by 1–8 oprx3,+xysp — Preincrement X , Y, or SP by 1–8 oprx3,xysp– — Postdecrement X, Y, or SP by 1–8 oprx3,xysp+ — Postincrement X, Y, or SP by 1–8 oprx5,xysppc — 5-bit constant offset from X, Y, SP, or PC abd,xysppc — Accumulator A, B, or D offset from X, Y, SP, or PC oprx3 oprx5

Any positive integer from 1 to 8 for pre/post increment/decrement

Any integer from –16 to +15 oprx9 oprx16

Any integer from –256 to +255

Any integer from –32,768 to +65,535

8-bit value for PPAGE register

Some assemblers require the # symbol before this value.

rel8 rel9 rel16 trapnum xysp xysppc

Label of branch destination within –256 to +255 locations

Label of branch destination within –512 to +511 locations

Any label within the 64-Kbyte memory space

Any 8-bit integer from $30 to $39 or from $40 to $FF

Register designator for X or Y or SP

Register designator for X or Y or SP or PC

A.2.7 CPU Cycles Notation

The CPU Cycles column on the glossary pages shows how many bytes of information the CPU accesses while executing an instruction. With this information and knowledge of the type and speed of memory in the system, you can determine the execution time for any instruction in any system. Simply count the code letters to determine the execution time of an instruction in a best-case system. An example of a best-case system is a single-chip 16-bit system with no 16-bit off-boundary data accesses to any locations other than on-chip RAM.

A single-letter code in represents a single CPU access cycle. An upper-case letter indicates a 16-bit access.

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Table A-7 CPU Cycle Notation

f

Free cycle. During an f

cycle, the CPU does not use the bus. An f

cycle is always one cycle of the system bus clock. An f cycle can be used by a queue controller or the background debug system to perform a single-cycle access without disturbing the CPU.

g

Read PPAGE register. A g

cycle is used only in CALL instructions and is not visible on the external bus. Since PPAGE is an internal 8-bit register, a g

cycle is never stretched.

I

Read indirect pointer. Indexed-indirect instructions use the 16-bit indirect pointer from memory to address the instruction operand. An

I

cycle is a 16-bit read that can be aligned or misaligned. An

I cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. An

I

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

i

Read indirect PPAGE value. An i

cycle is used only in indexed-indirect CALL instructions. The 8-bit

PPAGE value for the CALL destination is fetched from an indirect memory location. An i

cycle is stretched only when controlled by a chip-select circuit that is programmed for slow memory.

n

Write PPAGE register. An n cycle is used only in CALL and RTC instructions to write the destination value of the PPAGE register and is not visible on the external bus. Since the PPAGE register is an internal 8-bit register, an n

cycle is never stretched.

O

Optional cycle. An

O cycle adjusts instruction alignment in the instruction queue. An

O cycle can be a free cycle ( f

) or a program word access cycle (

P

). When the first byte of an instruction with an odd number of bytes is misaligned, the

O

cycle becomes a

P

cycle to maintain queue order. If the first byte is aligned, the

O

cycle is an f

cycle.

The $18 prebyte for a page-two opcode is treated as a special one-byte instruction. If the prebyte is misaligned, the

O

cycle at the beginning of the instruction becomes a

P

cycle to maintain queue order. If the prebyte is aligned, the

O

cycle is an f

cycle. If the instruction has an odd number of bytes, it has a second

O

cycle at the end. If the first

O

cycle is a

P

cycle (prebyte misaligned), the second

O cycle is an f cycle. If the first

O cycle is an f cycle (prebyte aligned), the second

O cycle is a

P

cycle.

An

O cycle that becomes a

P cycle can be extended to two bus cycles if the MCU is operating with an

8-bit external data bus and the program is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

O

cycle that becomes an f

cycle is never stretched.

P

Program word access. Program information is fetched as aligned 16-bit words. A

P cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored externally. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

r

8-bit data read. An r cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

R

16-bit data read. An

R

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

An

R

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

s

Stack 8-bit data. An s cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

S

Stack 16-bit data. An

S

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching if the address space is assigned to a chip-select circuit programmed for slow memory. An

S

cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single cycle misaligned word access.

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Table A-7 CPU Cycle Notation (Continued)

w

8-bit data write. A w

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

W

16-bit data write. A

W

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

A

W cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

u

Unstack 8-bit data. A

W

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

U

Unstack 16-bit data. A

U

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the SP is pointing to external memory. There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

U cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access. The internal RAM is designed to allow single-cycle misaligned word access.

V

16-bit vector fetch. Vectors are always aligned 16-bit words. A

V

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the program is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory.

t

8-bit conditional read. A t cycle is either a data read cycle or a free cycle, depending on the data and flow of the REVW instruction. A t

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

T

16-bit conditional read. A

T

cycle is either a data read cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. A

T

cycle is extended to two bus cycles if the MCU is operating with an 8-bit external data bus and the corresponding data is stored in external memory.

There can be additional stretching when the address space is assigned to a chip-select circuit programmed for slow memory. A

T cycle is also stretched if it corresponds to a misaligned access to a memory that is not designed for single-cycle misaligned access.

x

8-bit conditional write. An x

cycle is either a data write cycle or a free cycle, depending on the data and flow of the REV or REVW instruction. An x

cycle is stretched only when controlled by a chip-select circuit programmed for slow memory.

Special Notation for Branch Taken/Not Taken

PPP/P

A short branch requires three cycles if taken, one cycle if not taken. Since the instruction consists of a single word containing both an opcode and an 8-bit offset, the not-taken case is simple — the queue advances, another program word fetch is made, and execution continues with the next instruction. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

OPPP/OPO

A long branch requires four cycles if taken, three cycles if not taken. An

O

cycle is required because all long branches are page two opcodes and thus include the $18 prebyte. The prebyte is treated as a one-byte instruction. If the prebyte is misaligned, the

O

cycle is a

P

cycle; if the prebyte is aligned, the

O

cycle is an f

cycle. As a result, both the taken and not-taken cases use one

O

cycle for the prebyte. In the not-taken case, the queue must advance so that execution can continue with the next instruction, and another

O

cycle is required to maintain the queue. The taken case requires that the queue be refilled so that execution can continue at a new address. First, the effective address of the destination is determined, then the CPU performs three program word fetches from that address.

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A.3 Glossary

ABA

Add B to A

ABA

Operation

(A) + (B)

A

Adds the value in B to the value in A and places the result in A. The value in B does not change. This instruction affects the H bit so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

CCR

Effects

S X H I N Z V C

– –

∆ ∆ ∆ ∆

H: A3

B3 | B3

R3 | R3

A3; set if there is a carry from bit 3; cleared otherwise

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

B7

R7 | A7

B7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

B7 | B7

R7 | R7

A7; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH

18 06

Machine

Code (Hex)

ABA

OO

CPU Cycles

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ABX

Add B to X

(same as LEAX B,X)

ABX

Operation

(X) + (B)

X

Adds the 8-bit unsigned value in B to the value in X considering the possible carry out of the low byte of X and places the result in X. The value in B does not change.

ABX assembles as LEAX B,X. The LEAX instruction allows A, B, D, or a constant to be added to X.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

IDX

1A E5

Machine

Code (Hex)

ABX

Pf

CPU Cycles

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ABY

Add B to Y

(same as LEAY B,Y)

ABY

Operation

(Y) + (B)

Y

Adds the 8-bit unsigned value in B to the value in Y considering the possible carry out of the low byte of Y and places the result in Y. The value in B does not change.

ABY assembles as LEAY B,Y. The LEAY instruction allows A, B, D, or a constant to be added to Y.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

IDX

19 ED

Machine

Code (Hex)

ABY

Pf

CPU Cycles

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ADCA

Add with Carry to A

ADCA

Operation

(A) + (M) + C

A or

(A) + imm + C

A

Adds either the value in M and the C bit or an immediate value and the C bit to the value in A. Puts the result in A. This instruction affects the H bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

CCR

Effects

S X H I N Z V C

– –

∆ ∆ ∆ ∆

H: A3

M3 | M3

R3 | R3

A3; set if there is a carry from bit 3; cleared otherwise

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

ADCA # opr8i

ADCA opr8a

ADCA opr16a

ADCA oprx0_xysppc

ADCA oprx9,xysppc

ADCA oprx16,xysppc

ADCA [D, xysppc]

ADCA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

89 ii

99 dd

B9 hh ll

A9 xb

A9 xb ff

A9 xb ee ff

A9 xb

A9 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ADCB

Add with Carry to B

ADCB

Operation

(B) + (M) + C

B or

(B) + imm + C

B

Adds either the value in M and the C bit or an immediate value and the C bit to the value in B. Puts the result in B. This instruction affects the H bit, so it is suitable for use in BCD arithmetic operations (see DAA instruction for additional information).

CCR

Effects

S X H I N Z V C

– –

∆ ∆ ∆ ∆

H: B3

M3 | M3

R3 | R3

B3; set if there is a carry from bit 3; cleared otherwise

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: B7

M7

R7 | B7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: B7

M7 | M7

R7 | R7

B7; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

ADCB # opr8i

ADCB opr8a

ADCB opr16a

ADCB oprx0_xysppc

ADCB oprx9,xysppc

ADCB oprx16,xysppc

ADCB [D, xysppc]

ADCB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine Code

(Hex)

C9 ii

D9 dd

F9 hh ll

E9 xb

E9 xb ff

E9 xb ee ff

E9 xb

E9 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ADDA

Add to A

ADDA

Operation

(A) + (M)

A or

(A) + imm

A

Adds either the value in M or an immediate value to the value in A and places the result in

A. This instruction affects the H bit, so it is suitable for use in BCD arithmetic operations

(see DAA instruction for additional information).

CCR

Effects

S X H I N Z V C

– –

∆ ∆ ∆ ∆

H: A3

M3 | M3

R3 | R3

A3; set if there is a carry from bit 3; cleared otherwise

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

ADDA # opr8i

ADDA opr8a

ADDA opr16a

ADDA oprx0_xysppc

ADDA oprx9,xysppc

ADDA oprx16,xysppc

ADDA [D, xysppc]

ADDA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine Code

(Hex)

8B ii

9B dd

BB hh ll

AB xb

AB xb ff

AB xb ee ff

AB xb

AB xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ADDB

Add to B

ADDB

Operation

(B) + (M)

B or

(B) + imm

B

Adds either the value in M or an immediate value to the value in B and places the result in

B. This instruction affects the H bit, so it is suitable for use in BCD arithmetic operations

(see DAA instruction for additional information).

CCR

Effects

S X H I N Z V C

– –

∆ ∆ ∆ ∆

H: B3

M3 | M3

R3 | R3

B3; set if there is a carry from bit 3; cleared otherwise

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: B7

M7

R7 | B7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: B7

M7 | M7

R7 | R7

B7; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

ADDB # opr8i

ADDB opr8a

ADDB opr16a

ADDB oprx0_xysppc

ADDB oprx9,xysppc

ADDB oprx16,xysppc

ADDB [D, xysppc]

ADDB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

CB ii

DB dd

FB hh ll

EB xb

EB xb ff

EB xb ee ff

EB xb

EB xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ADDD

Add to D

ADDD

Operation

(A):(B) + (M):(M + 1)

A:B or

(A):(B) + imm

A:B

Adds either the value in M concatenated with the value in M + 1 or an immediate value to the value in D. Puts the result in D. A is the high byte of D; B is the low byte.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if there is a carry from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

ADDD # opr16i

ADDD opr8a

ADDD opr16a

ADDD oprx0_xysppc

ADDD oprx9,xysppc

ADDD oprx16,xysppc

ADDD [D, xysppc]

ADDD [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C3 jj kk

D3 dd

F3 hh ll

E3 xb

E3 xb ff

E3 xb ee ff

E3 xb

E3 xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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ANDA

AND with A

ANDA

Operation

(A)

(M)

A or

(A)

imm

A

Performs a logical AND of either the value in M or an immediate value with the value in

A. Puts the result in A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

ANDA # opr8i

ANDA opr8a

ANDA opr16a

ANDA oprx0_xysppc

ANDA oprx9,xysppc

ANDA oprx16,xysppc

ANDA [D, xysppc]

ANDA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

84 ii

94 dd

B4 hh ll

A4 xb

A4 xb ff

A4 xb ee ff

A4 xb

A4 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ANDB

AND with B

ANDB

Operation

(B) or

(B)

(M)

B

imm

B

Performs a logical AND of either the value in M or an immediate value with the value in

B. Puts the result in B.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

ANDB # opr8i

ANDB opr8a

ANDB opr16a

ANDB oprx0_xysppc

ANDB oprx9,xysppc

ANDB oprx16,xysppc

ANDB [D, xysppc]

ANDB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C4 ii

D4 dd

F4 hh ll

E4 xb

E4 xb ff

E4 xb ee ff

E4 xb

E4 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ANDCC

AND with CCR

ANDCC

Operation

(CCR)

imm

CCR

Performs a logical AND of an immediate value and the value in the CCR. Puts the result in the CCR.

If the I mask bit is cleared, there is a one-cycle delay before the system allows interrupt requests. This prevents interrupts from occurring between instructions in the sequences

CLI, WAI and CLI, SEI (CLI is equivalent to ANDCC #$EF).

CCR

Effects

S X H I N Z V C

⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓ ⇓

All CCR bits: Clear if 0 before operation or if corresponding bit in mask is 0

Code and

CPU

Cycles

Source Form

ANDCC # opr8i

Address

Mode

IMM 10 ii

Machine

Code (Hex)

P

CPU Cycles

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ASL

Arithmetic Shift Left M

(same as LSL)

ASL

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

M

0

Shifts all bits of M one bit position to the left. Bit 0 is loaded with a 0. The C bit is loaded from the most significant bit of M.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: M7; set if the MSB of M was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

ASL opr16a

ASL oprx0_xysppc

ASL oprx9,xysppc

ASL oprx16,xysppc

ASL [D, xysppc]

ASL [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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ASLA

Arithmetic Shift Left A

(same as LSLA)

ASLA

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

A

0

Shifts all bits of A one bit position to the left. Bit 0 is loaded with a 0. The C bit is loaded from the most significant bit of A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: A7; set if the MSB of A was set before the shift; cleared otherwise

Code and

CPU

Cycles

ASLA

Source Form

Address

Mode

INH

48

Machine

Code (Hex)

O

CPU Cycles

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ASLB

Arithmetic Shift Left B

(same as LSLB)

ASLB

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

B

0

Shifts all bits of B one bit position to the left. Bit 0 is loaded with a 0. The C bit is loaded from the most significant bit of B.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: B7; set if the MSB of B was set before the shift; cleared otherwise

Code and

CPU

Cycles

ASLB

Source Form

Address

Mode

INH

58

Machine

Code (Hex)

O

CPU Cycles

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ASLD

Arithmetic Shift Left D

(same as LSLD)

ASLD

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

A b7 b6 b5 b4 b3 b2 b1 b0

B

0

Shifts all bits of D one bit position to the left. Bit 0 is loaded with a 0. The C bit is loaded from the most significant bit of D.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: D15; set if the MSB of D was set before the shift; cleared otherwise

Code and

CPU

Cycles

ASLD

Source Form

Address

Mode

INH 59

Machine

Code (Hex)

O

CPU Cycles

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ASR

Operation

Arithmetic Shift Right M

ASR

b7 b6 b5 b4 b3 b2 b1 b0 C

M

Shifts all bits of M one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: M0; set if the LSB of M was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

ASR opr16a

ASR oprx0_xysppc

ASR oprx9,xysppc

ASR oprx16,xysppc

ASR [D, xysppc]

ASR [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

77 hh ll

67 xb

67 xb ff

67 xb ee ff

67 xb

67 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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ASRA

Operation

Arithmetic Shift Right A

ASRA

b7 b6 b5 b4 b3 b2 b1 b0 C

A

Shifts all bits of A one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: A0; set if the LSB of A was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 47

Machine

Code (Hex)

ASRA O

CPU Cycles

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ASRB

Operation

Arithmetic Shift Right B

ASRB

b7 b6 b5 b4 b3 b2 b1 b0 C

B

Shifts all bits of B one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C bit. This operation effectively divides a two’s complement value by two without changing its sign. The carry bit can be used to round the result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C; set if:

N is set and C is cleared after the shift, or

N is cleared and C is set after the shift; cleared otherwise

C: B0; set if the LSB of B was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 57

Machine

Code (Hex)

ASRB O

CPU Cycles

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BCC

Branch if C Clear

(same as BHS)

BCC

Operation

If C = 0, then (PC) + $0002 + rel

PC

Tests the C bit and branches if C = 0.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

24 rr

REL BCC rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BCC/BHS 24

Test

(R)

(M) or

(B)

(A)

BGE 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Complementary Branch

Mnemonic Opcode

BCS/BLO 25

Test

(R)

<

(M) or

(B)

<

(A)

BLT 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Comment

Unsigned

Signed

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BCLR

Clear Bit(s) in M

BCLR

Operation

(M)

(mask byte)

M

Performs a logical AND of the value in M and the complement of a mask byte contained in the instruction. Puts the result in M. Bits in M that correspond to 1s in the mask byte are cleared. No other bits in M change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

Address

Mode

1

Machine

Code (Hex)

CPU Cycles

BCLR opr8a, msk8

BCLR opr16a, msk8

BCLR oprx0_xysppc, msk8

BCLR oprx9,xysppc, msk8

BCLR oprx16,xysppc, msk8

DIR

EXT

IDX

IDX1

IDX2

4D dd mm

1D hh ll mm

0D xb mm

0D xb ff mm

0D xb ee ff mm

NOTES:

1. Indirect forms of indexed addressing cannot be used with this instruction.

rPwO rPwP rPwO rPwP frPwPO

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BCS

Branch if C Set

(same as BLO)

BCS

Operation

If C = 1, then (PC) + $0002 + rel

PC

Tests the C bit and branches if C = 1.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

25 rr

REL BCS rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BCS/BLO 25

Test

(R)

<

(M) or

(B)

<

(A)

BLT 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Complementary Branch

Mnemonic Opcode

BCC/BHS 24

Test

(R)

(M) or

(B)

(A)

BGE 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Comment

Unsigned

Signed

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BEQ

Branch if Equal

BEQ

Operation

If Z = 1, then (PC) + $0002 + rel

PC

Tests the Z bit and branches if Z = 1.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

27 rr

REL BEQ rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BEQ 27

Test

(R) = (M) or

(R) = zero

Z = 1

Complementary Branch

Mnemonic Opcode

BNE 26

Test

(R)

(M) or

(R)

zero

Z = 0

Comment

Signed, unsigned or simple

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BGE

Branch if Greater Than or Equal to Zero

BGE

Operation

If N

V = 0, then (PC) + $0002 + rel

PC

BGE can be used to branch after comparing or subtracting signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is greater than or equal to the value in

M. After CBA or SBA, the branch occurs if the value in B is greater than or equal to the value in A.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

2C rr

REL BGE rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BGE

BHS/BCC

2C

24

Test

(R)

(M) or

(B)

(A)

N

V = 0

(R)

(M) or

(B)

(A)

C = 0

Complementary Branch

Mnemonic Opcode

BLT

BLO/BCS

2D

25

Test

(R)

<

(M) or

(B)

<

(A)

N

V = 1

(R)

<

(M) or

(B)

<

(A)

C = 1

Comment

Signed

Unsigned

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BGND

Enter Background Debug Mode

BGND

Operation

(PC)

TMP2

BDM vector

PC

BGND operates like a software interrupt, except that no registers are stacked. First, the current PC value is stored in internal CPU register TMP2. Next, the BDM ROM and background register block become active. The BDM ROM contains a substitute vector, mapped to the address of the software interrupt vector, which points to routines in the BDM

ROM that control background operation. The substitute vector is fetched, and execution continues from the address that it points to. Finally, the CPU checks the location that TMP2 points to. If the value stored in that location is $00 (the BGND opcode), TMP2 is incremented, so that the instruction that follows the BGND instruction is the first instruction executed when normal program execution resumes.

For all other types of BDM entry, the CPU performs the same sequence of operations as for a BGND instruction, but the value stored in TMP2 already points to the instruction that would have executed next had BDM not become active. If active BDM is triggered just as a BGND instruction is about to execute, the BDM firmware does increment TMP2, but the change does not affect resumption of normal execution.

While BDM is active, the CPU executes debugging commands received via a special single-wire serial interface. BDM is terminated by the execution of specific debugging commands. Upon exit from BDM, the background/boot ROM and registers are disabled, the instruction queue is refilled starting with the return address pointed to by TMP2, and normal processing resumes.

BDM is normally disabled to avoid accidental entry. While BDM is disabled, BGND executes as described, but the firmware causes execution to return to the user program.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

00

Machine

Code (Hex)

BGND

CPU Cycles

VfPPP

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BGT

Branch if Greater Than Zero

BGT

Operation

If Z | (N

V) = 0, then (PC) + $0002 + rel

PC

BGT can be used to branch after comparing or subtracting signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is greater than the value in M. After

CBA or SBA, the branch occurs if the value in B is greater than the value in A.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

2E rr

REL BGT rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BGT

BHI

2E

22

Test

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

(R)

>

(M) or

(B)

>

(A)

C | Z = 0

Complementary Branch

Mnemonic Opcode

BLE

BLS

2F

23

Test

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

(R)

(M) or

(B)

(A)

C | Z = 1

Comment

Signed

Unsigned

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BHI

Branch if Higher

BHI

Operation

If C | Z = 0, then (PC) + $0002 + rel

PC

BHI can be used to branch after comparing or subtracting unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than the value in M. After CBA or SBA, the branch occurs if the value in B is greater than the value in A. BHI is not for branching after instructions that do not affect the C bit, such as increment, decrement, load, store, test, clear, or complement.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

22 rr

REL BHI rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BHI 22

Test

(R)

>

(M) or

(B)

>

(A)

BGT 2E

C | Z = 0

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

Complementary Branch

Mnemonic Opcode

BLS 23

Test

(R)

(M) or

(B)

(A)

BLE 2F

C | Z = 1

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

Comment

Unsigned

Signed

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BHS

Branch if Higher or Same

(same as BCC)

BHS

Operation

If C = 0, then (PC) + $0002 + rel

PC

BHS can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is greater than or equal to the value in A. BHS is not for branching after instructions that do not affect the C bit, such as increment, decrement, load, store, test, clear, or complement.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

24 rr

REL BHS rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BHS/BCC 24

Test

(R)

(M) or

(B)

(A)

BGE 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Complementary Branch

Mnemonic Opcode

BLO/BCS 25

Test

(R)

<

(M) or

(B)

<

(A)

BLT 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Comment

Unsigned

Signed

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BITA

Bit Test A

BITA

Operation

(A)

(M) or

(A)

imm

Performs a logical AND of either the value in M or an immediate value with the value in

A. CCR bits reflect the result. The values in A and M do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

BITA # opr8i

BITA opr8a

BITA opr16a

BITA oprx0_xysppc

BITA oprx9,xysppc

BITA oprx16,xysppc

BITA [D, xysppc]

BITA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

85 ii

95 dd

B5 hh ll

A5 xb

A5 xb ff

A5 xb ee ff

A5 xb

A5 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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BITB

Bit Test B

BITB

Operation

(B) or

(B)

(M)

imm

Performs a logical AND of either the value in M or an immediate value with the value in

B. CCR bits reflect the result. The values in B and M do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

BITB # opr8i

BITB opr8a

BITB opr16a

BITB oprx0_xysppc

BITB oprx9,xysppc

BITB oprx16,xysppc

BITB [D, xysppc]

BITB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C5 ii

D5 dd

F5 hh ll

E5 xb

E5 xb ff

E5 xb ee ff

E5 xb

E5 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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BLE

Branch if Less Than or Equal to Zero

BLE

Operation

If Z | (N

V) = 1, then (PC) + $0002 + rel

PC

BLE can be used to branch after subtracting or comparing signed two’s complement values.

After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is less than or equal to the value in A.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

BLE rel8

Source Form

Address

Mode

Object Code

2F rr

REL

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BLE

BLS

2F

23

Test

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

(R)

(M) or

(B)

(A)

C | Z = 1

Complementary Branch

Mnemonic Opcode

BGT

BHI

2E

22

Test

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

(R)

>

(M) or

(B)

>

(A)

C | Z = 0

Comment

Signed

Unsigned

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BLO

Branch if Lower

(same as BCS)

BLO

Operation

If C = 1, then (PC) + $0002 + rel

PC

BLO can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than the value in M. After CBA or SBA, the branch occurs if the value in B is less than the value in A. BLO is not for branching after instructions that do not affect the C bit, such as increment, decrement, load, store, test, clear, or complement.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

25 rr

REL BLO rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BLO/BCS 25

Test

(R)

<

(M) or

(B)

<

(A)

BLT 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Complementary Branch

Mnemonic Opcode

BHS/BCC 24

Test

(R)

(M) or

(B)

(A)

BGE 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Comment

Unsigned

Signed

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BLS

Branch if Lower or Same

BLS

Operation

If C | Z = 1, then (PC) + $0002 + rel

PC

BLS can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is less than or equal to the value in A. BLS is not for branching after instructions that do not affect the C bit, such as increment, decrement, load, store, test, clear, or complement.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

BLS rel8

Source Form

Address

Mode

Machine

Code (Hex)

23 rr

REL

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BLS 23

Test

(R)

(M) or

(B)

(A)

BLE 2F

C | Z = 1

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

Complementary Branch

Mnemonic Opcode

BHI 22

Test

(R)

>

(M) or

(B)

>

(A)

BGT 2E

C | Z = 0

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

Comment

Unsigned

Signed

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BLT

Branch if Less Than Zero

BLT

Operation

If N

V = 1, then (PC) + $0002 + rel

PC

BLT can be used to branch after subtracting or comparing signed two’s complement values.

After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than the value in M. After CBA or SBA, the branch occurs if the value in B is less than the value in A.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

2D rr

REL BLT rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BLT

BLO/BCS

2D

25

Test

(R)

<

(M) or

(B)

<

(A)

N

V = 1

(R)

<

(M) or

(B)

<

(A)

C = 1

Complementary Branch

Mnemonic Opcode

BGE

BHS/BCC

2C

24

Test

(R)

(M) or

(B)

(A)

N

V = 0

(R)

(M) or

(B)

(A)

C = 0

Comment

Signed

Unsigned

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BMI

Branch if Minus

BMI

Operation

If N = 1, then (PC) + $0002 + rel

PC

Tests the N bit and branches if N = 1.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

2B rr

REL BMI rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode Test

Negative

BMI 2B

N = 1

Complementary Branch

Mnemonic Opcode Test

Positive

BPL 2A

N = 0

Comment

Simple

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BNE

Branch if Not Equal to Zero

BNE

Operation

If Z = 0, then (PC) + $0002 + rel

PC

Tests the Z bit and branches if Z = 0.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

26 rr

REL BNE rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BNE 26

Test

(R)

(M) or

(R)

zero

Z = 0

Complementary Branch

Mnemonic Opcode Test

BEQ 27

(R) = (M) or

(R) = zero

Z = 1

Comment

Signed, unsigned, or simple

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BPL

Branch if Plus

BPL

Operation

If N = 0, then (PC) + $0002 + rel

PC

Tests the N bit and branches if N = 0.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

2A rr

REL BPL rel8

Source Form

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode Test

Positive

BPL 2A

N = 0

Complementary Branch

Mnemonic Opcode Test

Negative

BMI 2B

N = 1

Comment

Simple

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BRA

Branch Always

BRA

Operation

(PC) + $0002 + rel

PC

Branches unconditionally.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

Execution time is longer when a conditional branch is taken than when it is not taken, because the instruction queue must be refilled before execution resumes at the new address.

Since the BRA branch condition is always satisfied, the branch is always taken, and the instruction queue must always be refilled.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

REL

20 rr

Machine

Code (Hex)

BRA rel8

CPU Cycles

PPP

Branch

Mnemonic Opcode

BRA 20

Test

Always

Complementary Branch

Mnemonic Opcode Test

BRN 21 Never

Comment

Simple

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BRCLR

Branch if Bit(s) Clear

BRCLR

Operation

If (M)

(mask byte) = 0, then (PC)

+

$0002 + rel

PC

Performs a logical AND of the value in M and the mask value supplied with the instruction.

Branches if all the 0s in M correspond to 1s in the mask byte.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

BRCLR opr8a, msk8, rel8

BRCLR opr16a, msk8, rel8

BRCLR oprx0_xysppc, msk8, rel8

BRCLR oprx9,xysppc, msk8, rel8

BRCLR oprx16,xysppc, msk8, rel8

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

Machine

Code (Hex)

CPU Cycles

4F dd mm rr

1F hh ll mm rr

0F xb mm rr

0F xb ff mm rr

0F xb ee ff mm rr rPPP rfPPP rPPP rfPPP

PrfPPP

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BRN

Branch Never

BRN

Operation

(PC) + $0002

PC

Never branches. BRN is effectively a 2-byte NOP that requires one cycle. BRN is included in the instruction set to provide a complement to the BRA instruction. BRN is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte. A complement for BRA is also useful in compiler implementations.

Execution time is longer when a conditional branch is taken than when it is not, because the instruction queue must be refilled before execution resumes at the new address. Since the BRN branch condition is never satisfied, the branch is never taken, and only a single program fetch is needed to update the instruction queue.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

REL

21 rr

Machine

Code (Hex)

CPU Cycles

BRN rel8

P

Branch

Mnemonic Opcode

BRN 21

Test

Never

Complementary Branch

Mnemonic Opcode Test

BRA 20

Comment

Always Simple

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BRSET

Branch if Bit(s) Set

BRSET

Operation

If (M)

(mask byte) = 0, then (PC) + $0002 + rel

PC

Performs a logical AND of the value of M and the mask value supplied with the instruction.

Branches if all the ones in M correspond to ones in the mask byte.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

BRSET opr8a, msk8, rel8

BRSET opr16a, msk8, rel8

BRSET oprx0_xysppc, msk8, rel8

BRSET oprx9,xysppc, msk8, rel8

BRSET oprx16,xysppc, msk8, rel8

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

Machine

Code (Hex)

CPU Cycles

4E dd mm rr

1E hh ll mm rr

0E xb mm rr

0E xb ff mm rr

0E xb ee ff mm rr rPPP rfPPP rPPP rfPPP

PrfPPP

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BSET

Set Bit(s) in M

BSET

Operation

(M) | (mask byte)

M

Performs a logical OR of the value in M and a mask byte contained in the instruction. Puts the result in M. Bits in M that correspond to 1s in the mask are set. No other bits in M change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

BSET opr8a, msk8

BSET opr16a, msk8

BSET oprx0_xysppc, msk8

BSET oprx9,xysppc, msk8

BSET oprx16,xysppc, msk8

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

Machine

Code (Hex)

4C dd mm

1C hh ll mm

0C xb mm

0C xb ff mm

0C xb ee ff mm

CPU Cycles

rPwO rPwP rPwO rPwP frPwPO

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BSR

Branch to Subroutine

BSR

Operation

(SP) – $0002

SP

RTN

H

:RTN

L

M

SP

:M

SP + 1

(PC) + $0002 + rel

PC

Sets up conditions to return to normal program flow, then transfers control to a subroutine.

Uses the address of the instruction after the BSR as a return address.

Decrements the SP by two, to allow the two bytes of the return address to be stacked.

Stacks the return address (the SP points to the high byte of the return address).

Branches to a location determined by the branch offset.

Subroutines are normally terminated with an RTS instruction, which restores the return address from the stack.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

REL

07 rr

Machine

Code (Hex)

BSR rel8

CPU Cycles

SPPP

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BVC

Branch if V Clear

BVC

Operation

If V = 0, then (PC) + $0002 + rel

PC

Tests the V bit and branches if V = 0. BVC causes a branch when a previous operation on two’s complement binary values does not cause an overflow. That is, when BVC follows a two’s complement operation, a branch occurs when the result of the operation is valid.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

28 rr

REL BVC rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BRN 21

Test

Never

Complementary Branch

Mnemonic Opcode Test

BRA 20

Comment

Always Simple

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BVS

Branch if V Set

BVS

Operation

If V = 1, then (PC) + $0002 + rel

PC

Tests the V bit and branches if V = 1. BVS causes a branch when a previous operation on two’s complement values causes an overflow. That is, when BVS follows a two’s complement operation, a branch occurs when the result of the operation is invalid.

Rel is an 8-bit two’s complement offset for branching forward or backward in memory.

Branching range is $80 to $7F (–128 to 127) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

29 rr

REL BVS rel8

CPU Cycles

PPP

(branch)

P

(no branch)

Branch

Mnemonic Opcode

BVS 29

Test

No overflow

V = 1

Complementary Branch

Mnemonic Opcode Test

Overflow

BVC 28

V = 1

Comment

Simple

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CALL

Call Subroutine in Expanded Memory

CALL

Operation

(SP) – $0002

SP

RTN

H

:RTN

L

M

SP

:M

SP + 1

(SP) – $0001

SP

(PPAGE)

M

SP new page value

PPAGE

Subroutine address

PC

Sets up conditions to return to normal program flow, then transfers control to a subroutine in expanded memory. Uses the address of the instruction following the CALL as a return address. For code compatibility, CALL also executes correctly in devices that do not have expanded memory capability.

Decrements SP by two, allowing the two return address bytes to be stacked.

Stacks the return address; SP points to the high byte of the return address.

Decrements SP by one, allowing the current PPAGE value to be stacked.

Stacks the value in PPAGE.

Writes a new page value supplied by the instruction to PPAGE.

Transfers control to the subroutine.

In indexed-indirect modes, the subroutine address and PPAGE value are fetched in the order M high byte, M low byte, and new PPAGE value.

Expanded-memory subroutines must be terminated by an RTC instruction, which restores the return address and PPAGE value from the stack.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

CALL opr16a, page

CALL oprx0_xysppc, page

CALL oprx9,xysppc, page

CALL oprx16,xysppc, page

CALL [D, xysppc]

CALL [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

4A hh ll pg

4B xb pg

4B xb ff pg

4B xb ee ff pg

4B xb

4B xb ee ff

CPU Cycles

gnSsPPP gnSsPPP gnSsPPP fgnSsPPP fIignSsPPP fIignSsPPP

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CBA

Compare B to A

CBA

Operation

(A) – (B)

Compares the value in A with the value in B. Condition code bits affected by the comparison can be used for conditional branches. The values in A and B do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

B7

R7 | A7

B7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

B7 | B7

R7 | R7 | A7; set if there is a borrow from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

CBA

Source Form

Address

Mode

INH

18 17

Machine

Code (Hex)

OO

CPU Cycles

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CLC

Clear C

(same as ANDCC #$FE)

CLC

Operation

0

C bit

Clears the C bit. CLC assembles as ANDCC #$FE.

CLC can be used to initialize the C bit prior to a shift or rotate instruction affecting the C bit.

CCR

Effects

S X H I N Z V C

– – – – – – – 0

C: Cleared

Code and

CPU

Cycles

CLC

Source Form

Address

Mode

IMM 10 FE

Machine

Code (Hex)

P

CPU Cycles

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CLI

Clear I

(same as ANDCC #$EF)

CLI

Operation

0

I bit

Clears the I bit. CLI assembles as ANDCC #$EF.

Clearing the I bit enables interrupts. There is a one-cycle bus clock delay in the clearing mechanism. If interrupts were previously disabled, the next instruction after a CLI is always executed, even if there was an interrupt pending prior to execution of the CLI instruction.

CCR

Effects

S X H I N Z V C

– – – 0 – – – –

I: Cleared

Code and

CPU

Cycles

CLI

Source Form

Address

Mode

IMM 10 EF

Machine

Code (Hex)

P

CPU Cycles

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CLR

Operation

$00

M

Clears all bits in M.

CCR

Effects

S X H I N Z V C

– – – – 0 1 0 0

Clear M

N: Cleared

Z: Set

V: Cleared

C: Cleared

Code and

CPU

Cycles

Source Form

CLR opr16a

CLR oprx0_xysppc

CLR oprx9,xysppc

CLR oprx16,xysppc

CLR [D, xysppc]

CLR [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

79 hh ll

69 xb

69 xb ff

69 xb ee ff

69 xb

69 xb ee ff

CPU Cycles

PwO

Pw

PwO

PwP

PIfw

PIPw

CLR

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CLRA

Operation

$00

A

Clears all bits in A.

CCR

Effects

S X H I N Z V C

– – – – 0 1 0 0

Clear A

N: Cleared

Z: Set

V: Cleared

C: Cleared

Code and

CPU

Cycles

CLRA

Source Form

Address

Mode

INH

87

Machine

Code (Hex)

CLRA

O

CPU Cycles

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CLRB

Operation

$00

B

Clears all bits in B.

CCR

Effects

S X H I N Z V C

– – – – 0 1 0 0

Clear B

N: Cleared

Z: Set

V: Cleared

C: Cleared

Code and

CPU

Cycles

CLRB

Source Form

Address

Mode

INH

C7

Machine

Code (Hex)

CLRB

O

CPU Cycles

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CLV

Clear V

(same as ANDCC #$FD)

Operation

0

V bit

Clears the V bit. CLV assembles as ANDCC #$FD.

CCR

Effects

S X H I N Z V C

– – – – – – 0 –

V: Cleared

Code and

CPU

Cycles

CLV

Source Form

Address

Mode

IMM 10 FD

Machine

Code (Hex)

P

CPU Cycles

CLV

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CMPA

Compare A

CMPA

Operation

(A) – (M) or

(A) – imm

Compares the value in A to either the value in M or an immediate value. CCR bits reflect the result. The values in A and M do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if there is a borrow from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

CMPA # opr8i

CMPA opr8a

CMPA opr16a

CMPA oprx0_xysppc

CMPA oprx9,xysppc

CMPA oprx16,xysppc

CMPA [D, xysppc]

CMPA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

81 ii

91 dd

B1 hh ll

A1 xb

A1 xb ff

A1 xb ee ff

A1 xb

A1 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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CMPB

Compare B

CMPB

Operation

(B) – (M) or

(B) – imm

Compares the value in B to either the value in M or an immediate value. CCR bits reflect the result. The values in B and M do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: B7

M7

R7 | B7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: B7

M7 | M7

R7 | R7

B7; set if there is a borrow from the MSB of the result; cleared otherwise

Code and

CPU

Cycles

Source Form

CMPB # opr8i

CMPB opr8a

CMPB opr16a

CMPB oprx0_xysppc

CMPB oprx9,xysppc

CMPB oprx16,xysppc

CMPB [D, xysppc]

CMPB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C1 ii

D1 dd

F1 hh ll

E1 xb

E1 xb ff

E1 xb ee ff

E1 xb

E1 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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COM

Complement M

COM

Operation

(M) = $FF – (M)

M

Replaces the value in M with its one’s complement. Immediately after a COM operation on unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. After operation on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 1

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

C: Set for M6800 compatibility

Code and

CPU

Cycles

Source Form

COM opr16a

COM oprx0_xysppc

COM oprx9,xysppc

COM oprx16,xysppc

COM [D, xysppc]

COM [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

71 hh ll

61 xb

61 xb ff

61 xb ee ff

61 xb

61 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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COMA

Complement A

COMA

Operation

(A) = $FF – (A)

A

Replaces the value in A with its one’s complement. Immediately after a COM operation on unsigned values, only the BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. After operation on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 1

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

C: Set for M6800 compatibility

Code and

CPU

Cycles

COMA

Source Form

Address

Mode

INH

41

Machine

Code (Hex)

O

CPU Cycles

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COMB

Complement B

COMB

Operation

(B) = $FF – (B)

B

Replaces the value in B with its one’s complement. Each bit of B is complemented.

Immediately after a COM operation on unsigned values, only the BEQ, BNE, LBEQ, and

LBNE branches can be expected to perform consistently. After operation on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 1

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

C: Set for M6800 compatibility

Code and

CPU

Cycles

COMB

Source Form

Address

Mode

INH

51

Machine

Code (Hex)

O

CPU Cycles

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CPD

Compare D

CPD

Operation

(A):(B) – (M):(M + 1) or

(A:B) – imm

Compares the value in D to either the value in M:M + 1 or an immediate value. CCR bits reflect the result. The values in D and M:M + 1 do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if the absolute value of (M:M + 1) is larger than the absolute value of (D); cleared otherwise

Code and

CPU

Cycles

Source Form

CPD # opr16i

CPD opr8a

CPD opr16a

CPD oprx0_xysppc

CPD oprx9,xysppc

CPD oprx16,xysppc

CPD [D, xysppc]

CPD [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

8C jj kk

9C dd

BC hh ll

AC xb

AC xb ff

AC xb ee ff

AC xb

AC xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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CPS

Compare SP

CPS

Operation

(SP) – (M):(M + 1) or

(SP) – imm

Compares the value in SP to either the value in M:M + 1 or an immediate value. CCR bits reflect the result. The values in SP and M:M + 1 do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: SP15

M15

R15 | SP15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: SP15

M15 | M15

R15 | R15

SP15; set if the absolute value of (M:M + 1) is larger than the absolute value of (SP); cleared otherwise

Code and

CPU

Cycles

Source Form

CPS # opr16i

CPS opr8a

CPS opr16a

CPS oprx0_xysppc

CPS oprx9,xysppc

CPS oprx16,xysppc

CPS [D, xysppc]

CPS [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

8F jj kk

9F dd

BF hh ll

AF xb

AF xb ff

AF xb ee ff

AF xb

AF xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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CPX

Compare X

CPX

Operation

(X) – (M):(M + 1) or

(X) – imm

Compares the value in X to either the value in M:M + 1 or an immediate value. CCR bits reflect the result. The values in X and M:M + 1 do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: X15

M15

R15 | X15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: X15

M15 | M15

R15 | R15

X15; set if the absolute value of (M:M + 1) is larger than the absolute value of (X); cleared otherwise

Code and

CPU

Cycles

Source Form

CPX # opr16i

CPX opr8a

CPX opr16a

CPX oprx0_xysppc

CPX oprx9,xysppc

CPX oprx16,xysppc

CPX [D, xysppc]

CPX [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

8E jj kk

9E dd

BE hh ll

AE xb

AE xb ff

AE xb ee ff

AE xb

AE xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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CPY

Compare Y

CPY

Operation

(Y) – (M):(M + 1) or

(Y) – imm

Compares the value in Y to either the value in M:M + 1 or an immediate value. CCR bits reflect the result. The values in Y and M:M + 1 do not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: Y15

M15

R15 | Y15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: Y15

M15 | M15

R15 | R15

Y15; set if the absolute value of (M:M + 1) is larger than the absolute value of (Y); cleared otherwise

Code and

CPU

Cycles

Source Form

CPY # opr16i

CPY opr8a

CPY opr16a

CPY oprx0_xysppc

CPY oprx9,xysppc

CPY oprx16,xysppc

CPY [D, xysppc]

CPY [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

8D jj kk

9D dd

BD hh ll

AD xb

AD xb ff

AD xb ee ff

AD xb

AD xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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DAA

Decimal Adjust A for BCD

DAA

Operation

DAA adjusts the value in A and the state of the C bit to represent the correct binary-coded-decimal (BCD) sum and the associated carry when a BCD calculation is performed. To execute DAA, the value in A, the state of the C bit, and the state of the H bit must all be the result of performing an ABA, ADD, or ADC on BCD operands, with or without an initial carry.

The table below shows DAA operation for all legal combinations of input operands. The first four columns represent the results of ABA, ADC, or ADD operations on BCD operands. The correction factor in the fifth column is added to the accumulator to restore the result of an operation on two BCD operands to a valid BCD value and to set or clear the

C bit. All values are in hexadecimal.

C Value A[7:6:5:4] Value H Value A[3:2:1:0] Value Correction Corrected C bit

0 0–9 0 0–9 00 0

1

1

0

1

0

0

0

0

0–8

0–9

A–F

9–F

A–F

0–2

0–2

0–3

0

1

1

0

0

0

0

1

A–F

0–3

0–9

A–F

0–3

0–9

A–F

0–3

66

60

66

66

06

06

60

66

1

1

1

1

1

1

0

0

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

C: Represents BCD carry

Code and

CPU

Cycles

DAA

Source Form

Address

Mode

INH

18 07

Machine

Code (Hex)

CPU Cycles

OfO

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DBEQ

Decrement and Branch if Equal to Zero

DBEQ

Operation

(counter) – 1

counter

If (counter) = 0, then (PC) + $0003 + rel

PC

Subtracts one from the counter register A, B, D, X, Y, or SP. Branches to a relative destination if the counter register reaches zero. Rel is a 9-bit two’s complement offset for branching forward or backward in memory. Branching range is $100 to $0FF (–256 to

+255) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

REL

(9-bit)

Machine

Code (Hex)

04 lb rr

DBEQ abdxysp, rel9

CPU Cycles

PPP

(branch)

PPO

(no branch)

Source

Form

DBEQ A, rel9

DBEQ B, rel9

DBEQ D, rel9

DBEQ X, rel9

DBEQ Y, rel9

DBEQ SP, rel9

Loop Primitive Postbyte ( lb

) Coding

Postbyte

1

Object

Code

Counter

Register

0000 X000

0000 X001

0000 X100

0000 X101

0000 X110

0000 X111

04 00 rr

04 01 rr

04 04 rr

04 05 rr

04 06 rr

04 07 rr

A

B

D

X

Y

SP

Offset

Positive

DBEQ A, rel9

DBEQ B, rel9

DBEQ D, rel9

DBEQ X, rel9

DBEQ Y, rel9

DBEQ SP, rel9

0001 X000

0001 X001

0001 X100

0001 X101

0001 X110

0001 X111

04 10 rr

04 11 rr

04 14 rr

04 15 rr

04 16 rr

04 17 rr

A

B

D

X

Y

SP

Negative

NOTES:

1. Bits 7:6:5 select DBEQ or DBNE; bit 4 is the offset sign bit: bit 3 is not used; bits 2:1:0 select the counter register.

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DBNE

Decrement and Branch if Not Equal to Zero

DBNE

Operation

(counter) – 1

counter

If (counter) not = 0, then (PC) + $0003 + rel

PC

Subtracts one from the counter register A, B, D, X, Y, or SP. Branches to a relative destination if the counter register does not reach zero. Rel is a 9-bit two’s complement offset for branching forward or backward in memory. Branching range is $100 to $0FF

(–256 to +255) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

REL

(9-bit)

Machine

Code (Hex)

04 lb rr

DBNE abdxysp, rel9

CPU Cycles

PPP

(branch)

PPO

(no branch)

Source

Form

DBNE A, rel9

DBNE B, rel9

DBNE D, rel9

DBNE X, rel9

DBNE Y, rel9

DBNE SP, rel9

Loop Primitive Postbyte ( lb

) Coding

Postbyte

1

Object

Code

Counter

Register

0010 X000

0010 X001

0010 X100

0010 X101

0010 X110

0010 X111

04 20 rr

04 21 rr

04 24 rr

04 25 rr

04 26 rr

04 27 rr

A

B

D

X

Y

SP

Offset

Positive

DBNE A, rel9

DBNE B, rel9

DBNE D, rel9

DBNE X, rel9

DBNE Y, rel9

DBNE SP, rel9

0011 X000

0011 X001

0011 X100

0011 X101

0011 X110

0011 X111

04 30 rr

04 31 rr

04 34 rr

04 35 rr

04 36 rr

04 37 rr

A

B

D

X

Y

SP

Negative

NOTES:

1. Bits 7:6:5 select DBEQ or DBNE; bit 4 is the offset sign bit: bit 3 is not used; bits 2:1:0 select the counter register.

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DEC

Decrement M

DEC

Operation

(M) – $01

M

Subtracts one from the value in M. The N, Z, and V bits are set or cleared by the operation.

The C bit is not affected by the operation, allowing the DEC instruction to be used as a loop counter in multiple-precision computations.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if operation produces a two’s complement overflow (if and only if (M) was $80 before the operation); cleared otherwise

Code and

CPU

Cycles

Source Form

DEC opr16a

DEC oprx0_xysppc

DEC oprx9,xysppc

DEC oprx16,xysppc

DEC [D, xysppc]

DEC [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

73 hh ll

63 xb

63 xb ff

63 xb ee ff

63 xb

63 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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DECA

Decrement A

DECA

Operation

(A) – $01

A

Subtracts one from the value in A. The N, Z, and V bits are set or cleared by the operation.

The C bit is not affected by the operation, allowing the DEC instruction to be used as a loop counter in multiple-precision computations.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if operation produces a two’s complement overflow (if and only if (A) was $80 before the operation); cleared otherwise

Code and

CPU

Cycles

DECA

Source Form

Address

Mode

INH

43

Machine

Code (Hex)

O

CPU Cycles

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DECB

Decrement B

DECB

Operation

(B) – $01

B

Subtracts one from the value in B. The N, Z, and V bits are set or cleared by the operation.

The C bit is not affected by the operation, allowing the DEC instruction to be used as a loop counter in multiple-precision computations.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if operation produces a two’s complement overflow (if and only if (B) was $80 before the operation); cleared otherwise

Code and

CPU

Cycles

DECB

Source Form

Address

Mode

INH

53

Machine

Code (Hex)

O

CPU Cycles

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DES

Decrement SP

(same as LEAS –1,SP)

DES

Operation

(SP) – $0001

SP

Subtracts one from SP. DES assembles as LEAS –1,SP. DES does not affect condition code bits as DEX and DEY do.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

IDX

1B 9F

Machine

Code (Hex)

DES

Pf

CPU Cycles

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DEX

Decrement X

DEX

Operation

(X) – $0001

X

Subtracts one from X. The Z bit reflects the result. The LEAX –1,X instruction does the same thing as DEX, but without affecting the Z bit.

CCR

Effects

S X H I N Z V C

– – – – –

– –

Z: Set if result is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 09

Machine

Code (Hex)

DEX O

CPU Cycles

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DEY

Decrement Y

DEY

Operation

(Y) – $0001

Y

Subtracts one from Y. The Z bit reflects the result. The LEAY –1,Y instruction does the same thing as DEY, but without affecting the Z bit.

CCR

Effects

S X H I N Z V C

– – – – –

– –

Z: Set if result is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 03

Machine

Code (Hex)

DEY O

CPU Cycles

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EDIV

Extended Divide, Unsigned

EDIV

Operation

(Y):(D)

÷

(X)

Y; remainder

D

Divides a 32-bit unsigned dividend by a 16-bit divisor, producing a 16-bit unsigned quotient and an unsigned 16-bit remainder. All operands and results are located in CPU registers. Division by zero has no effect, except that the states of the N, Z, and V bits are undefined.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise; undefined after overflow or division by 0

Z: Set if result is $0000; cleared otherwise; undefined after overflow or division by 0

V: Set if the result is greater than $FFFF; cleared otherwise; undefined after division by 0

C: Set if divisor is $0000; cleared otherwise

Code and

CPU

Cycles

EDIV

Source Form

Address

Mode

INH

11

Machine

Code (Hex)

CPU Cycles

ffffffffffO

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EDIVS

Extended Divide, Signed

EDIVS

Operation

(Y):(D)

÷

(X)

Y; remainder

D

Divides a signed 32-bit dividend by a 16-bit signed divisor, producing a signed 16-bit quotient and a signed 16-bit remainder. All operands and results are located in CPU registers. Division by zero has no effect, except that the C bit is set and the states of the N,

Z, and V bits are undefined.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise; undefined after overflow or division by 0

Z: Set if result is $0000; cleared otherwise; undefined after overflow or division by 0

V: Set if the result is greater than $7FFF or less than $8000; cleared otherwise; undefined after division by 0

C: Set if divisor is $0000; cleared otherwise; indicates division by 0

Code and

CPU

Cycles

EDIVS

Source Form

Address

Mode

INH

18 14

Machine

Code (Hex)

CPU Cycles

OffffffffffO

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EMACS

Extended Multiply and Accumulate,

Signed

EMACS

Operation

(M

X

):(M

X + 1

)

×

(M

Y

):(M

Y + 1

) + (M):(M + 1):(M + 2):(M + 3)

M + 1:M + 2:M + 3

Multiplies two 16-bit values. Adds the 32-bit product to the value in a 32-bit accumulator in memory. EMACS is a signed integer operation. All operands and results are located in memory. X must point to the high byte of the first source operand, and Y must point to the high byte of the second source operand. An extended address supplied with the instruction must point to the most significant byte of the 32-bit result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result, R31, is set; cleared otherwise

Z: Set if result is $00000000; cleared otherwise

V: M31

I31

R31 | M31

I31

R31; set if result is greater than $7FFFFFFF (+ overflow) or less than

$80000000 (– underflow); indicates two’s complement overflow

C: M15

I15 | I15

R15 | R15

M15; set if there is a carry from bit 15 of the result, R15; cleared otherwise; indicates a carry from low word to high word of the result

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

CPU Cycles

EMACS opr16a

1

Special

18 12 hh ll ORROfffRRfWWP

NOTES:

1.

opr16a is an extended address specification. Both X and Y point to source operands.

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EMAXD

Extended Maximum in D

EMAXD

Operation

MAX [(D), (M):(M + 1)]

D

Subtracts an unsigned 16-bit value in M:M + 1 from an unsigned 16-bit value in D to determine which is larger. Puts the larger value in D. If the values are equal, the Z bit is set.

If the value in M:M + 1 is larger, the C bit is set when the value in M:M + 1 replaces the value in D. If the value in D is larger, the C bit is cleared.

EMAXD accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate finding the largest value in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if (M):(M + 1) is larger than (D); cleared otherwise

Condition code bits reflect internal subtraction: R = (D) – (M):(M + 1).

Code and

CPU

Cycles

Source Form

EMAXD oprx0_xysppc

EMAXD oprx9,xysppc

EMAXD oprx16,xysppc

EMAXD [D, xysppc]

EMAXD [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1A xb

18 1A xb ff

18 1A xb ee ff

18 1A xb

18 1A xb ee ff

CPU Cycles

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

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EMAXM

Extended Maximum in M

EMAXM

Operation

MAX [(D), (M):(M + 1)]

M:M + 1

Subtracts an unsigned 16-bit value in M:M + 1 from an unsigned 16-bit value in D to determine which is larger. Puts the larger value in M:M + 1. If the values are equal, the Z bit is set. If the value in M:M + 1 is larger, the C bit is set. If the value in D is larger, the C bit is cleared when the value in D replaces the value in M:M + 1.

EMAXM accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate controlling the values in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if (M):(M + 1) is larger than (D); cleared otherwise

Condition code bits reflect internal subtraction: R = (D) – (M):(M + 1).

Code and

CPU

Cycles

Source Form

EMAXM oprx0_xysppc

EMAXM oprx9,xysppc

EMAXM oprx16,xysppc

EMAXM [D, xysppc]

EMAXM [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1E xb

18 1E xb ff

18 1E xb ee ff

18 1E xb

18 1E xb ee ff

CPU Cycles

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW

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EMIND

Extended Minimum in D

EMIND

Operation

MIN [(D), (M):(M + 1)]

D

Subtracts an unsigned 16-bit value in M:M + 1 from an unsigned 16-bit value in D to determine which is larger. Puts the smaller value in D. If the values are equal, the Z bit is set. If the value in M:M + 1 is larger, the C bit is set. If the value in D is larger, the C bit is cleared when the value in M:M + 1 replaces the value in D.

EMIND accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if (M):(M + 1) is larger than (D); cleared otherwise

Condition code bits reflect internal subtraction: R = (D) – (M):(M + 1).

Code and

CPU

Cycles

Source Form

EMIND oprx0_xysppc

EMIND oprx9,xysppc

EMIND oprx16,xysppc

EMIND [D, xysppc]

EMIND [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1B xb

18 1B xb ff

18 1B xb ee ff

18 1B xb

18 1B xb ee ff

CPU Cycles

ORPf

ORPO

OfRPP

OfIfRPf

OfIPRPf

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EMINM

Extended Minimum in M

EMINM

Operation

MIN [(D), (M):(M + 1)]

M:M + 1

Subtracts an unsigned 16-bit value in M:M + 1 from an unsigned 16-bit value in D to determine which is larger. Puts the smaller value in M:M + 1. If the values are equal, the Z bit is set. If the value in M:M + 1 is larger, the C bit is set when the value in D replaces the value in M:M + 1. If the value in D is larger, the C bit is cleared.

EMINM accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: D15

M15

R15 | D15

M15

R15; set if the operation produces a two’s complement overflow; cleared otherwise

C: D15

M15 | M15

R15 | R15

D15; set if (M):(M + 1) is larger than (D); cleared otherwise

Condition code bits reflect internal subtraction: R = (D) – (M):(M + 1).

Code and

CPU

Cycles

Source Form

EMINM oprx0_xysppc

EMINM oprx9,xysppc

EMINM oprx16,xysppc

EMINM [D, xysppc]

EMINM [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1F xb

18 1F xb ff

18 1F xb ee ff

18 1F xb

18 1F xb ee ff

CPU Cycles

ORPW

ORPWO

OfRPWP

OfIfRPW

OfIPRPW

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EMUL

Extended Multiply, Unsigned

EMUL

Operation

(D)

×

(Y)

Y:D

Multiplies an unsigned 16-bit value in D by an unsigned 16-bit value in Y. Puts the high

16-bits of the unsigned 32-bit result in Y and the low 16-bits of the result in D.

The C bit can be used to round the low 16 bits of the result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

N: Set if the MSB of the result is set; cleared otherwise

Z: Set if result is $00000000; cleared otherwise

C: Set if bit 15 of the result is set; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 13

Machine

Code (Hex)

EMUL

CPU Cycles

ffO

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EMULS

Extended Multiply, Signed

EMULS

Operation

(D)

×

(Y)

Y:D

Multiplies a signed 16-bit value in D by a signed 16-bit value in Y. Puts the high 16 bits of the 32-bit signed result in Y and the low 16 bits of the result in D.

The C bit can be used to round the low 16 bits of the result.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

N: Set if the MSB of the result is set; cleared otherwise

Z: Set if result is $00000000; cleared otherwise

C: Set if bit 15 of the result is set; cleared otherwise

Code and

CPU

Cycles

EMULS

Source Form

Address

Mode

Machine

Code (Hex)

18 13

INH

CPU Cycles

OfO

OffO

1

NOTES:

1. EMULS has an extra free cycle if it is followed by another page two instruction.

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EORA

Exclusive OR A

EORA

Operation

(A)

(M)

A or

(A)

imm

A

Performs a logical exclusive OR of the value in A and either the value in M or an immediate value. Puts the result in A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

EORA # opr8i

EORA opr8a

EORA opr16a

EORA oprx0_xysppc

EORA oprx9,xysppc

EORA oprx16,xysppc

EORA [D, xysppc]

EORA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

88 ii

98 dd

B8 hh ll

A8 xb

A8 xb ff

A8 xb ee ff

A8 xb

A8 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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EORB

Exclusive OR B with M

EORB

Operation

(B) or

(B)

(M)

B

imm

B

Performs a logical exclusive OR of the value in B and either the value in M or an immediate value. Puts the result in B.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

EORB # opr8i

EORB opr8a

EORB opr16a

EORB oprx0_xysppc

EORB oprx9,xysppc

EORB oprx16,xysppc

EORB [D, xysppc]

EORB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C8 ii

D8 dd

F8 hh ll

E8 xb

E8 xb ff

E8 xb ee ff

E8 xb

E8 xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ETBL

Extended Table Lookup and Interpolate

ETBL

Operation

(M):(M + 1) + [(B)

×

((M + 2):(M + 3) – (M):(M + 1))]

D

Linearly interpolates and stores in D one of 256 values between a pair of data entries, Y1 and Y2, in a lookup table. Data entries represent y coordinates of line segment endpoints.

Table entries and the interpolated results are 16-bit values.

Y2

YL

Before executing ETBL, point an indexing register at the Y1 value closest to but less than or equal to the Y value to interpolate. Point to

Y1 using any indexed addressing mode except indirect, 9-bit offset, and 16-bit offset. The next table entry after Y1 is Y2. Load B with a binary fraction (radix point to the left of the MSB) representing the

Y1

X1 XL

(XL – X1) ratio:

X2

÷

(X2 – X1) where

X1 = Y1 and X2 = Y2

XL is the x coordinate of the value to interpolate

The 16-bit unrounded result, YL, is calculated using the expression:

YL = Y1 + [(B)

×

(Y2 – Y1)] where

Y1 = 16-bit data entry pointed to by effective address

Y2 = 16-bit data entry pointed to by the effective address plus two

The 24-bit intermediate value (B)

×

(Y2 – Y1) has a radix point between bits 7 and 8.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

C: Set if result can be rounded up; cleared otherwise

Code and

CPU

Cycles

Source Form

ETBL oprx0_xysppc

Address

Mode

IDX

Machine

Code (Hex)

18 3F xb

CPU Cycles

ORRffffffP

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EXG

Exchange Register Contents

EXG

Operation

(r1)

(r2) when r1 and r2 are the same size

$00:(r1)

(r2) when r1 is 8 bits and r2 is 16 bits

(r1

L

)

(r2) when r1 is 16 bits and r2 is 8 bits

See the table on the next page.

Exchanges the values between a source register A, B, CCR, D, X, Y, or SP and a destination register A, B, CCR, D, X, Y, or SP. Exchanges involving TMP2 and TMP3 are reserved for

Motorola use.

CCR

Effects

S X H I N Z V C

– – – – – – – – or

S X H I N Z V C

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

CCR bits affected only when the CCR is the destination register. The X bit cannot change from 0 to 1.

Software can leave the X bit set, leave it cleared, or change it from 1 to 0, but X can only be set by a reset or by recognition of an XIRQ interrupt.

Code and

CPU

Cycles

Source Form

EXG abcdxysp,abcdxysp

Address

Mode

INH

B7 eb

Machine

Code (Hex)

P

CPU Cycles

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EXG

Exchange Register Contents

(continued)

EXG

Exchange Postbyte ( eb

) Coding

Source

Form

EXG A,A

EXG A,B

EXG A,CCR

EXG A,TMP2

EXG A,D

EXG A,X

EXG A,Y

EXG A,SP

EXG B,A

EXG B,B

EXG B,CCR

EXG B,TMP2

EXG B,D

EXG B,X

EXG B,Y

EXG B,SP

EXG CCR,A

EXG CCR,B

EXG CCR,CCR

EXG CCR,TMP2

EXG CCR,D

EXG CCR,X

EXG CCR,Y

EXG CCR,SP

EXG TMP3,A

EXG TMP3,B

EXG TMP3,CCR

EXG TMP3,TMP2

EXG TMP3,D

EXG TMP3,X

EXG TMP3,Y

EXG TMP3,SP

Postbyte

Object

Code

1000 X000

1000 X001

1000 X010

1000 X011

1000 X100

1000 X101

1000 X110

1000 X111

1001 X000

1001 X001

1001 X010

1001 X011

1001 X100

1001 X101

1001 X110

1001 X111

1010 X000

1010 X001

1010 X010

1010 X011

1010 X100

1010 X101

1010 X110

1010 X111

1011 X000

1011 X001

1011 X010

1011 X011

1011 X100

1011 X101

1011 X110

1011 X111

B7 80

B7 81

B7 82

B7 83

B7 84

B7 85

B7 86

B7 87

B7 90

B7 91

B7 92

B7 93

B7 94

B7 95

B7 96

B7 97

B7 A0

B7 A1

B7 A2

B7 A3

B7 A4

B7 A5

B7 A6

B7 A7

B7 B0

B7 B1

B7 B2

B7 B3

B7 B4

B7 B5

B7 B6

B7 B7

Exchange

Source

Form

Postbyte

Object

Code

A

A

A

B

A

CCR

$00:A

TMP2, TMP2

L

A

$00:A

D

$00:A

X, X

$00:A

Y, Y

L

L

A

$00:A

SP, SP

L

A

A

B

A

B

B

B

CCR

$00:B

TMP2, TMP2

L

B

$00:B

D

$00:B

X, X

$00:B

Y, Y

L

L

B

$00:B

SP, SP

L

B

B

CCR

A

CCR

B

CCR

CCR

$00:CCR

TMP2, TMP2

L

CCR

$00:CCR

D

$00:CCR

X, X

$00:CCR

Y, Y

L

L

CCR

$00:CCR

SP, SP

L

CCR

CCR

TMP3

L

TMP3

L

A, $00:A

TMP3

B, $FF:B

TMP3

CCR, $FF:CCR

TMP3 TMP3

L

TMP3

TMP2

TMP3

D

TMP3

X

TMP3

Y

TMP3

SP

EXG B,A

EXG B,B

EXG B,CCR

EXG D,TMP2

EXG D,D

EXG D,X

EXG D,Y

EXG D,SP

EXG X,A

EXG X,B

EXG X,CCR

EXG X,TMP2

EXG X,D

EXG X,X

EXG X,Y

EXG X,SP

EXG Y,A

EXG Y,B

EXG Y,CCR

EXG Y,TMP2

EXG Y,D

EXG Y,X

EXG Y,Y

EXG Y,SP

EXG SP,A

EXG SP,B

EXG SP,CCR

EXG SP,TMP2

EXG SP,D

EXG SP,X

EXG SP,Y

EXG SP,SP

1100 X000

1100 X001

1100 X010

1100 X011

1100 X100

1100 X101

1100 X110

1100 X111

1101 X000

1101 X001

1101 X010

1101 X011

1101 X100

1101 X101

1101 X110

1101 X111

1110 X000

1110 X001

1110 X010

1110 X011

1110 X100

1110 X101

1110 X110

1110 X111

1111 X000

1111 X001

1111 X010

1111 X011

1111 X100

1111 X101

1111 X110

1111 X111

B7 C0

B7 C1

B7 C2

B7 C3

B7 C4

B7 C5

B7 C6

B7 C7

B7 D0

B7 D1

B7 D2

B7 D3

B7 D4

B7 D5

B7 D6

B7 D7

B7 E0

B7 E1

B7 E2

B7 E3

B7 E4

B7 E5

B7 E6

B7 E7

B7 F0

B7 F1

B7 F2

B7 F3

B7 F4

B7 F5

B7 F6

B7 F7

Exchange

B

A, A

B

B

B, $FF

A

B

CCR, $FF:CCR

D

D

TMP2

D

D

D

X

D

Y

D

SP

X

L

A, $00:A

X

X

L

B, $FF:B

X

X

L

CCR, $FF:CCR

X

TMP2

X

D

X

X

X

X

Y

X

SP

Y

L

A, $00:A

Y

Y

L

B, $FF:B

Y

Y

L

CCR, $FF:CCR

Y

TMP2

Y

D

Y

Y

X

Y

Y

Y

SP

SP

L

A, $00:A

SP

SP

L

B, $FF:B

SP

SP

L

CCR, $FF:CCR

SP

TMP2

SP

D

SP

SP

X

SP

Y

SP

SP

For More Information On This Product,

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FDIV

Fractional Divide

FDIV

Operation

(D)

÷

(X)

X, remainder

D

Divides an unsigned 16-bit numerator in D by an unsigned 16-bit denominator in X. Puts the unsigned 16-bit quotient in X and the unsigned 16-bit remainder in D. If both the numerator and the denominator are assumed to have radix points in the same positions, the radix point of the quotient is to the left of bit 15. The numerator must be less than the denominator. In the case of overflow (denominator is less than or equal to the numerator) or division by 0, the quotient is set to $FFFF and the remainder is indeterminate.

FDIV is equivalent to multiplying the numerator by 2

16 and then performing 32 x 16-bit integer division. The result is interpreted as a binary-weighted fraction, which resulted from the division of a 16-bit integer by a larger 16-bit integer. A result of $0001 corresponds to 0.000015, and $FFFF corresponds to 0.9998. The remainder of an IDIV instruction can be resolved into a binary-weighted fraction by an FDIV instruction. The remainder of an FDIV instruction can be resolved into the next 16 bits of binary-weighted fraction by another FDIV instruction.

CCR

Effects

S X H I N Z V C

– – – – –

∆ ∆ ∆

Z: Set if quotient is $0000; cleared otherwise

V: Set if the denominator X is less than or equal to the numerator D; cleared otherwise

C: X15

X14

X13

X12

. . .

X3

X2

X1

X0; set if denominator is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 18 11

Machine

Code (Hex)

FDIV

CPU Cycles

OffffffffffO

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IBEQ

Increment and Branch if Equal to Zero

IBEQ

Operation

(counter) + 1

counter

If (counter) = 0, then (PC) + $0003 + rel

PC

Adds one to the counter register A, B, D, X, Y, or SP. Branches to a relative destination if the counter register reaches zero. Rel is a 9-bit two’s complement offset for branching forward or backward in memory. Branching range is $100 to $0FF (–256 to +255) from the address following the last byte of object code in the instruction.

CCR

Effects S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

04 lb rr

REL IBEQ abdxysp, rel9

CPU Cycles

PPP

(branch)

PPO

(no branch)

Source

Form

IBEQ A, rel9

IBEQ B, rel9

IBEQ D, rel9

IBEQ X, rel9

IBEQ Y, rel9

IBEQ SP, rel9

Loop Primitive Postbyte ( lb

) Coding

Postbyte

1

Object

Code

Counter

Register

1000 X000

1000 X001

1000 X100

1000 X101

1000 X110

1000 X111

04 80 rr

04 81 rr

04 84 rr

04 85 rr

04 86 rr

04 87 rr

A

B

D

X

Y

SP

Offset

Positive

IBEQ A, rel9

IBEQ B, rel9

IBEQ D, rel9

IBEQ X, rel9

IBEQ Y, rel9

IBEQ SP, rel9

1001 X000

1001 X001

1001 X100

1001 X101

1001 X110

1001 X111

04 90 rr

04 91 rr

04 94 rr

04 95 rr

04 96 rr

04 97 rr

A

B

D

X

Y

SP

Negative

NOTES:

1. Bits 7:6:5 select IBEQ or IBNE; bit 4 is the offset sign bit: bit 3 is not used; bits 2:1:0 select the counter register.

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IBNE

Increment and Branch if Not Equal to Zero

IBNE

Operation

(counter) + 1

counter

If (counter)

0, then (PC) + $0003 + rel

PC

Adds one to the counter register A, B, D, X, Y, or SP. Branches to a relative destination if the counter register does not reach zero.Rel is a 9-bit two’s complement offset for branching forward or backward in memory. Branching range is $100 to $0FF (–256 to

+255) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

04 lb rr

REL IBNE abdxysp, rel9

CPU Cycles

PPP

(branch)

PPO

(no branch)

Source

Form

IBNE A, rel9

IBNE B, rel9

IBNE D, rel9

IBNE X, rel9

IBNE Y, rel9

IBNE SP, rel9

Loop Primitive Postbyte ( lb

) Coding

Postbyte

1

Object

Code

Counter

Register

1010 X000

1010 X001

1010 X100

1010 X101

1010 X110

1010 X111

04 A0 rr

04 A1 rr

04 A4 rr

04 A5 rr

04 A6 rr

04 A7 rr

A

B

D

X

Y

SP

Offset

Positive

IBNE A, rel9

IBNE B, rel9

IBNE D, rel9

IBNE X, rel9

IBNE Y, rel9

IBNE SP, rel9

1011 X000

1011 X001

1011 X100

1011 X101

1011 X110

1011 X111

04 B0 rr

04 B1 rr

04 B4 rr

04 B5 rr

04 B6 rr

04 B7 rr

A

B

D

X

Y

SP

Negative

NOTES:

1. Bits 7:6:5 select IBEQ or IBNE; bit 4 is the offset sign bit: bit 3 is not used; bits 2:1:0 select the counter register.

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IDIV

Integer Divide, Unsigned

IDIV

Operation

(D)

÷

(X)

X; remainder

D

Divides an unsigned 16-bit dividend in D by an unsigned 16-bit divisor in X. Puts the unsigned 16-bit quotient in X and the unsigned 16-bit remainder in D. If both the divisor and the dividend are assumed to have radix points in the same positions, the radix point of the quotient is to the right of bit 0. In the case of division by 0, the quotient is set to $FFFF, and the remainder is indeterminate.

CCR

Effects

S X H I N Z V C

– – – – –

0

Z: Set if quotient is $0000; cleared otherwise

V: Cleared

C: X15

X14

X13

X12 ...

X3

X2

X1

X0; set if denominator is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 18 10

Machine

Code (Hex)

IDIV

CPU Cycles

OffffffffffO

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IDIVS

Integer Divide, Signed

IDIVS

Operation

(D)

÷

(X)

X; remainder

D

Divides a signed 16-bit dividend in D by a signed 16-bit divisor in X. Puts the signed 16-bit quotient in X and the signed 16-bit remainder in D. If division by 0 is attempted, the values in D and X do not change, but the N, Z, and V bits are undefined.

Other than division by 0, which is not legal and sets the C bit, the only overflow case is:

$8000

------------------

$FFFF

=

–32,768

+32,768

–1

=

But the highest positive value that can be represented in a 16-bit two’s complement number is 32,767 ($7FFFF).

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of quotient is set; cleared otherwise; undefined after overflow or division by 0

Z: Set if quotient is $0000; cleared otherwise; undefined after overflow or division by 0

V: Set if the quotient is greater than $7FFF or less than $8000; cleared otherwise; undefined after division by

0

C: X15

X14

X13

X12

...

X3

X2

X1

X0; set if denominator is $0000; cleared otherwise

Code and

CPU

Cycles

IDIVS

Source Form

Address

Mode

INH

18 15

Machine

Code (Hex)

CPU Cycles

OffffffffffO

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INC

Increment M

INC

Operation

(M) + $01

M

Adds one to the value in M. The N, Z, and V bits reflect the result of the operation. The C bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.

When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. When operating on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if the operation produces a two’s complement overflow (if and only if (M) was $7F before the operation); cleared otherwise

Code and

CPU

Cycles

Source Form

INC opr16a

INC oprx0_xysppc

INC oprx9,xysppc

INC oprx16,xysppc

INC [D, xysppc]

INC [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

72 hh ll

62 xb

62 xb ff

62 xb ee ff

62 xb

62 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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INCA

Increment A

INCA

Operation

(A) + $01

A

Adds one to the value in A. The N, Z and V bits reflect the result of the operation. The C bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.

When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. When operating on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if the operation produces a two’s complement overflow (if and only if (A) was $7F before the operation); cleared otherwise

Code and

CPU

Cycles

INCA

Source Form

Address

Mode

INH

42

Machine

Code (Hex)

O

CPU Cycles

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INCB

Increment B

INCB

Operation

(B) + $01

B

Adds one to the value in B. The N, Z and V bits reflect the result of the operation. The C bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations.

When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. When operating on two’s complement values, all signed branches are available.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if the operation produces a two’s complement overflow (if and only if (B) was $7F before the operation); cleared otherwise

Code and

CPU

Cycles

INCB

Source Form

Address

Mode

INH

52

Machine

Code (Hex)

O

CPU Cycles

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INS

Increment SP

(same as LEAS 1,SP)

INS

Operation

(SP) + $0001

SP

Adds one to SP. INS assembles as LEAS 1,SP. INS does not affect condition code bits as

INX and INY instructions do.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

IDX

1B 81

Machine

Code (Hex)

INS

Pf

CPU Cycles

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INX

Increment X

INX

Operation

(X) + $0001

X

Adds one to X. LEAX 1,X can produce the same result but LEAX does not affect the Z bit.

Although the LEAX instruction is more flexible, INX requires only one byte of object code.

CCR

Effects

S X H I N Z V C

– – – – –

– –

Z: Set if result is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 08

Machine

Code (Hex)

INX O

CPU Cycles

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INY

Increment Y

INY

Operation

(Y) + $0001

Y

Adds one to Y. LEAY 1,Y can produce the same result but LEAY does not affect the Z bit.

Although the LEAY instruction is more flexible, INY requires only one byte of object code.

CCR

Effects

S X H I N Z V C

– – – – –

– –

Z: Set if result is $0000; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 02

Machine

Code (Hex)

INY O

CPU Cycles

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JMP

Jump

JMP

Operation

Subroutine address

PC

Jumps to the instruction stored at the effective address. The effective address is obtained according to the rules for extended or indexed addressing.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

JMP opr16a

JMP oprx0_xysppc

JMP oprx9,xysppc

JMP oprx16,xysppc

JMP [D, xysppc]

JMP [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

06 hh ll

05 xb

05 xb ff

05 xb ee ff

05 xb

05 xb ee ff

CPU Cycles

PPP

PPP

PPP fPPP fIfPPP fIfPPP

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JSR

Jump to Subroutine

JSR

Operation

(SP) – $0002

SP

RTN

H

:RTN

L

(M

SP

):(M

SP + 1

)

Subroutine address

PC

Sets up conditions to return to normal program flow, then transfers control to a subroutine.

Uses the address of the instruction following the JSR as a return address.

Decrements SP by two, to allow the two bytes of the return address to be stacked.

Stacks the return address (SP points to the high byte of the return address).

Calculates an effective address according to the rules for extended, direct, or indexed addressing.

Jumps to the location determined by the effective address.

Subroutines are normally terminated with an RTS instruction, which restores the return address from the stack.

CCR

Effects S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

JSR opr8a

JSR opr16a

JSR oprx0_xysppc

JSR oprx9,xysppc

JSR oprx16,xysppc

JSR [D, xysppc]

JSR [ oprx16,xysppc]

Address

Mode

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

17 dd

16 hh ll

15 xb

15 xb ff

15 xb ee ff

15 xb

15 xb ee ff

CPU Cycles

SPPP

SPPP

PPPS

PPPS fPPPS fIfPPPS fIfPPPS

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LBCC

Long Branch if C Clear

(same as LBHS)

Operation

If C = 0, then (PC) + $0004 + rel

PC

Tests the C bit and branches if C = 0.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 24 qq rr

REL LBCC rel16

LBCC

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBCC/LBHS 18 24

Test

(R)

(M) or

(B)

(A)

LBGE 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Complementary Branch

Mnemonic Opcode

LBCS/LBLO 18 25

Test

(R)

<

(M) or

(B)

<

(A)

LBLT 18 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Comment

Unsigned

Signed

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LBCS

Long Branch if C Set

(same as LBLO)

Operation

If C = 1, then (PC) + $0004 + rel

PC

Tests the C bit and branches if C = 1.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 25 qq rr

REL LBCS rel16

LBCS

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBCS/LBLO 18 25

Test

(R)

<

(M) or

(B)

<

(A)

LBLT 18 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Complementary Branch

Mnemonic Opcode

LBCC/LBHS 18 24

Test

(R)

(M) or

(B)

(A)

LBGE 18 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Comment

Unsigned

Signed

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LBEQ

Long Branch if Equal

LBEQ

Operation

If Z = 1, (PC) + $0004 + rel

PC

Tests the Z bit and branches if Z = 1.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 27 qq rr

REL LBEQ rel16

CPU Cycles

OPPP

(no branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBEQ 18 27

Test

(R) = (M) or

(R) = zero

Z = 1

Complementary Branch

Mnemonic Opcode

LBNE 18 26

Test

(R)

(M) or

(R)

zero

Z = 0

Comment

Signed, unsigned or simple

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LBGE

Long Branch if Greater Than or Equal to

Zero

LBGE

Operation

If N

V = 0, (PC) + $0004 + rel

PC

LBGE can be used to branch after subtracting or comparing signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is greater than or equal to the value in

M. After CBA or SBA, the branch occurs if the value in B is greater than or equal to the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2C qq rr

REL LBGE rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBGE

LBHS/LBCC

18 2C

18 24

Test

(R)

(M) or

(B)

(A)

N

V = 0

(R)

(M) or

(B)

(A)

C = 0

Complementary Branch

Mnemonic Opcode

LBLT

LBLO/LBCS

18 2D

18 25

Test

(R)

<

(M) or

(B)

<

(A)

N

V = 1

(R)

<

(M) or

(B)

<

(A)

C = 1

Comment

Signed

Unsigned

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LBGT

Long Branch if Greater Than Zero

LBGT

Operation

If Z | (N

V) = 0, then (PC) + $0004 + rel

PC

LBGT can be used to branch after subtracting or comparing signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is greater than the value in M. After

CBA or SBA, the branch occurs if the value in B is greater than the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2E qq rr

REL LBGT rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBGT

LBHI

18 2E

18 22

Test

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

(R)

>

(M) or

(B)

>

(A)

C | Z = 0

Complementary Branch

Mnemonic Opcode

LBLE

LBLS

18 2F

18 23

Test

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

(R)

(M) or

(B)

(A)

C | Z = 1

Comment

Signed

Unsigned

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LBHI

Long Branch if Higher

LBHI

Operation

If C | Z = 0, then (PC) + $0004 + rel

PC

LBHI can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than the value in M. After CBA or SBA, the branch occurs if the value in B is greater than the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 22 qq rr

REL LBHI rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBHI 18 22

Test

(R)

>

(M) or

(B)

>

(A)

LBGT 18 2E

C | Z = 0

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

Complementary Branch

Mnemonic Opcode

LBLS 18 23

Test

(R)

(M) or

(B)

(A)

LBLE 18 2F

C | Z = 1

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

Comment

Unsigned

Signed

For More Information On This Product,

Go to: www.freescale.com

LBHS

Long Branch if Higher or Same

(same as LBCC)

LBHS

Operation

If C = 0, then (PC) + $0004 + rel

PC

LBHS can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is greater than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is greater than or equal to the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 24 qq rr

REL LBHS rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBHS/LBCC 18 24

Test

(R)

(M) or

(B)

(A)

LBGE 18 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Complementary Branch

Mnemonic Opcode

LBLO/LBCS 18 25

Test

(R)

<

(M) or

(B)

<

(A)

LBLT 18 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Comment

Unsigned

Signed

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LBLE

Long Branch if Less Than or Equal to Zero

LBLE

Operation

If Z | (N

V) = 1, then (PC) + $0004 + rel

PC

LBLE can be used to branch after subtracting or comparing signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is less than or equal to the value in M.

After CBA or SBA, the branch occurs if the value in B is less than or equal to the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2F qq rr

REL LBLE rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBLE

LBLS

18 2F

18 23

Test

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

(R)

(M) or

(B)

(A)

C | Z = 1

Complementary Branch

Mnemonic Opcode

LBGT

LBHI

18 2E

18 22

Test

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

(R)

>

(M) or

(B)

>

(A)

C | Z = 0

Comment

Signed

Unsigned

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LBLO

Long Branch if Lower

(same as LBCS)

LBLO

Operation

If C = 1, then (PC) + $0004 + rel

PC

LBLO can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than the value in M. After CBA or SBA, the branch occurs if the value in B is less than the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 25 qq rr

REL LBLO rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBLO/LBCS 18 25

Test

(R)

<

(M) or

(B)

<

(A)

LBLT 18 2D

C = 1

(R)

<

(M) or

(B)

<

(A)

N

V = 1

Complementary Branch

Mnemonic Opcode

LBHS/LBCC 18 24

Test

(R)

(M) or

(B)

(A)

LBGE 18 2C

C = 0

(R)

(M) or

(B)

(A)

N

V = 0

Comment

Unsigned

Signed

For More Information On This Product,

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LBLS

Long Branch if Lower or Same

LBLS

Operation

If C | Z = 1, then (PC) + $0004 + rel

PC

LBLS can be used to branch after subtracting or comparing unsigned values. After CMPA,

CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or SUBD, the branch occurs if the CPU register value is less than or equal to the value in M. After CBA or SBA, the branch occurs if the value in B is less than or equal to the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 23 qq rr

REL LBLS rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBLS 18 23

Test

(R)

(M) or

(B)

(A)

LBLE 18 2F

C | Z = 1

(R)

(M) or

(B)

(A)

Z | (N

V) = 1

Complementary Branch

Mnemonic Opcode

LBHI 18 22

Test

(R)

>

(M) or

(B)

>

(A)

LBGT 18 2E

C | Z = 0

(R)

>

(M) or

(B)

>

(A)

Z | (N

V) = 0

Comment

Unsigned

Signed

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LBLT

Long Branch if Less Than Zero

LBLT

Operation

If N

V = 1, (PC) + $0004 + rel

PC

LBLT can be used to branch after subtracting or comparing signed two’s complement values. After CMPA, CMPB, CPD, CPS, CPX, CPY, SBCA, SBCB, SUBA, SUBB, or

SUBD, the branch occurs if the CPU register value is less than the value in M. After CBA or SBA, the branch occurs if the value in B is less than the value in A.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2D qq rr

REL LBLT rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBLT

LBLO/LBCS

18 2D

18 25

Test

(R)

<

(M) or

(B)

<

(A)

N

V = 1

(R)

<

(M) or

(B)

<

(A)

C = 1

Complementary Branch

Mnemonic Opcode

LBGE

LBHS/LBCC

18 2C

18 24

Test

(R)

(M) or

(B)

(A)

N

V = 0

(R)

(M) or

(B)

(A)

C = 0

Comment

Signed

Unsigned

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LBMI

Long Branch if Minus

LBMI

Operation

If N = 1, then (PC) + $0004 + rel

PC

Tests the N bit and branches if N = 1.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2B qq rr

REL LBMI rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode Test

Negative

LBMI 18 2B

N = 1

Complementary Branch

Mnemonic Opcode Test

Positive

LBPL 18 2A

N = 0

Comment

Simple

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LBNE

Long Branch if Not Equal to Zero

LBNE

Operation

If Z = 0, then (PC) + $0004 + rel

PC

Tests the Z bit and branches if Z = 0.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 26 qq rr

REL LBNE rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBNE 18 26

Test

(R)

(M) or

(R)

zero

Z = 0

Complementary Branch

Mnemonic Opcode Test

LBEQ 18 27

(R) = (M) or

(R) = zero

Z = 1

Comment

Signed, unsigned, or simple

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LBPL

Long Branch if Plus

LBPL

Operation

If N = 0, then (PC) + $0004 + rel

PC

Tests the N bit and branches if N = 0.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 2A qq rr

REL LBPL rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode Test

Positive

LBPL 18 2A

N = 0

Complementary Branch

Mnemonic Opcode Test

Negative

LBMI 18 2B

N = 1

Comment

Simple

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LBRA

Long Branch Always

LBRA

Operation

(PC) + $0004 + rel

PC

Branches unconditionally.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

Execution time is longer when a conditional branch is taken than when it is not, because the instruction queue must be refilled before execution resumes at the new address. Since the LBRA branch condition is always satisfied, the branch is always taken, and the instruction queue must always be refilled.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

LBRA rel16

Source Form

Address

Mode

REL

Machine

Code (Hex)

18 20 qq rr

CPU Cycles

OPPP

Branch

Mnemonic Opcode

LBRA 18 20

Test

Always

Complementary Branch

Mnemonic Opcode Test

LBRN 18 21 Never

Comment

Simple

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LBRN

Long Branch Never

LBRN

Operation

(PC) + $0004

PC

Never branches. LBRN is effectively a 4-byte NOP that requires three cycles. LBRN is included in the instruction set to provide a complement to the LBRA instruction. LBRN is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte. A complement for LBRA is also useful in compiler implementations.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

LBRN rel16

Source Form

Address

Mode

REL

Machine

Code (Hex)

18 21 qq rr

CPU Cycles

OPO

Branch

Mnemonic Opcode

LBRN 18 21

Test

Never

Complementary Branch

Mnemonic Opcode Test

LBRA 18 20

Comment

Always Simple

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LBVC

Long Branch if V Clear

LBVC

Operation

If V = 0, then (PC) + $0004 + rel

PC

Tests the V bit and branches if V = 0. LBVC causes a branch when a previous operation on two’s complement binary values does not cause an overflow. That is, when LBVC follows a two’s complement operation, a branch occurs when the result of the operation is valid.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 28 qq rr

REL LBVC rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch

Mnemonic Opcode

LBVC 18 28

Test

No overflow

V = 0

Complementary Branch

Mnemonic Opcode Test

Overflow

LBVS 18 29

V = 1

Comment

Simple

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LBVS

Long Branch if V Set

LBVS

Operation

If V = 1, then (PC) + $0004 + rel

PC

Tests the V bit and branches if V = 1. LBVS causes a branch when a previous operation on two’s complement values causes an overflow. That is, when LBVS follows a two’s complement operation, a branch occurs when the result of the operation is invalid.

Rel is a 16-bit two’s complement offset for branching forward or backward in memory.

Branching range is $8000 to $7FFF (–32768 to 32767) from the address following the last byte of object code in the instruction.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

18 29 qq rr

REL LBVS rel16

CPU Cycles

OPPP

(branch)

OPO

(no branch)

Branch Complementary Branch

Mnemonic Opcode Test Mnemonic Opcode Test

Overflow No overflow

LBVS 18 29 LBVC 18 28

V = 1 V = 0

Comment

Simple

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LDAA

Load A

Operation

(M)

A or imm

A

Loads A with either the value in M or an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDAA # opr8i

LDAA opr8a

LDAA opr16a

LDAA oprx0_xysppc

LDAA oprx9,xysppc

LDAA oprx16,xysppc

LDAA [D, xysppc]

LDAA [ oprx16,xysppc

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

86 ii

96 dd

B6 hh ll

A6 xb

A6 xb ff

A6 xb ee ff

A6 xb

A6 xb ee ff

LDAA

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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LDAB

Load B

Operation

(M)

B or imm

B

Loads B with either the value in M or an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDAB # opr8i

LDAB opr8a

LDAB opr16a

LDAB oprx0_xysppc

LDAB oprx9,xysppc

LDAB oprx16,xysppc

LDAB [D, xysppc]

LDAB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

C6 ii

D6 dd

F6 hh ll

E6 xb

E6 xb ff

E6 xb ee ff

E6 xb

E6 xb ee ff

LDAB

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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LDD

Load D

LDD

Operation

(M):(M + 1)

A:B or imm

A:B

Loads A with the value in M and loads B with the value in M:M

+

1 or loads A:B with an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDD # opr16i

LDD opr8a

LDD opr16a

LDD oprx0_xysppc

LDD oprx9,xysppc

LDD oprx16,xysppc

LDD [D, xysppc]

LDD [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

CC jj kk

DC dd

FC hh ll

EC xb

EC xb ff

EC xb ee ff

EC xb

EC xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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LDS

Load SP

LDS

Operation

(M):(M + 1)

SP or imm

SP

Loads the high byte of SP with the value in M and the low byte with the value in M + 1 or loads SP with an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDS # opr16i

LDS opr8a

LDS opr16a

LDS oprx0_xysppc

LDS oprx9,xysppc

LDS oprx16,xysppc

LDS [D, xysppc]

LDS [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

CF jj kk

DF dd

FF hh ll

EF xb

EF xb ff

EF xb ee ff

EF xb

EF xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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LDX

Load X

LDX

Operation

(M):(M + 1)

X or imm

X

Loads the high byte of X with value in M and low byte with the value in M + 1 or loads X with an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDX # opr16i

LDX opr8a

LDX opr16a

LDX oprx0_xysppc

LDX oprx9,xysppc

LDX oprx16,xysppc

LDX [D, xysppc]

LDX [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

CE jj kk

DE dd

FE hh ll

EE xb

EE xb ff

EE xb ee ff

EE xb

EE xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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LDY

Load Y

LDY

Operation

(M):(M + 1)

Y or imm

Y

Loads the high byte of Y with the value in M and the low byte with the value in M + 1 or loads Y with an immediate value.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

LDY # opr16i

LDY opr8a

LDY opr16a

LDY oprx0_xysppc

LDY oprx9,xysppc

LDY oprx16,xysppc

LDY [D, xysppc]

LDY [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

CD jj kk

DD dd

FD hh ll

ED xb

ED xb ff

ED xb ee ff

ED xb

ED xb ee ff

CPU Cycles

PO

RPf

RPO

RPf

RPO fRPP fIfRPf fIPRPf

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LEAS

Load Effective Address into SP

LEAS

Operation

Effective address

SP

Loads the stack pointer with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address.

Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X, Y, SP, or PC.

LEAS does not alter condition code bits. This allows stack modification without disturbing

CCR bits changed by recent arithmetic operations.

When SP is the indexing register, a predecrement or preincrement LEAS loads SP with the changed value. A postdecrement or postincrement LEAS does not affect the value in SP.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

LEAS oprx0_xysppc

LEAS oprx9,xysppc

LEAS oprx16,xysppc

Address

Mode

IDX

IDX1

IDX2

Machine

Code (Hex)

1B xb

1B xb ff

1B xb ee ff

Pf

PO

PP

CPU Cycles

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LEAX

Load Effective Address into X

LEAX

Operation

Effective address

X

Loads X with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X, Y, SP, or PC.

When X is the indexing register, a predecrement or preincrement LEAX loads X with the changed value. A postdecrement or postincrement LEAX does not affect the value in X.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

LEAX oprx0_xysppc

LEAX oprx9,xysppc

LEAX oprx16,xysppc

Address

Mode

IDX

IDX1

IDX2

Machine

Code (Hex)

1A xb

1A xb ff

1A xb ee ff

Pf

PO

PP

CPU Cycles

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LEAY

Load Effective Address into Y

LEAY

Operation

Effective address

Y

Loads Y with an effective address specified by the program. The effective address can be any indexed addressing mode operand address except an indirect address. Indexed addressing mode operand addresses are formed by adding an optional constant supplied by the program or an accumulator value to the current value in X, Y, SP, or PC.

When Y is the indexing register, a predecrement or preincrement LEAY loads Y with the changed value. A postdecrement or postincrement LEAY does not affect the value in Y.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

LEAY oprx0_xysppc

LEAY oprx9,xysppc

LEAY oprx16,xysppc

Address

Mode

IDX

IDX1

IDX2

Machine

Code (Hex)

19 xb

19 xb ff

19 xb ee ff

Pf

PO

PP

CPU Cycles

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LSL

Logical Shift Left M

(same as ASL)

LSL

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

M

0

Shifts all bits of the M one place to the left. Loads bit 0 with 0. Loads the C bit from the most significant bit of M.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: M7; set if the LSB of M was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

LSL opr16a

LSL oprx0_xysppc

LSL oprx9,xysppc

LSL oprx16,xysppc

LSL [D, xysppc]

LSL [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

78 hh ll

68 xb

68 xb ff

68 xb ee ff

68 xb

68 xb ee ff

CPU Cycles

rPwO rPw rPwO frPPw fIfrPw fIPrPw

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LSLA

Logical Shift Left A

(same as ASLA)

LSLA

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

A

0

Shifts all bits of A one place to the left. Loads bit 0 with 0. Loads the C bit is from the most significant bit of A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: A7; set if the LSB of A was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 48

Machine

Code (Hex)

LSLA O

CPU Cycles

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LSLB

Logical Shift Left B

(same as ASLB)

LSLB

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

B

0

Shifts all bits of B one place to the left. Loads bit 0 with 0. Loads the C bit from the most significant bit of B.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: B7; set if the LSB of B was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 58

Machine

Code (Hex)

LSLB O

CPU Cycles

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LSLD

Logical Shift Left D

(same as ASLD)

LSLD

Operation

C b7 b6 b5 b4 b3 b2 b1 b0

A b7 b6 b5 b4 b3 b2 b1 b0

B

0

Shifts all bits of D one place to the left. Loads bit 0 with 0. Loads the C bit from the most significant bit of A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $0000; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: D15; set if the MSB of D was set before the shift; cleared otherwise

Code and

CPU

Cycles

LSLD

Source Form

Address

Mode

INH

59

Machine

Code (Hex)

O

CPU Cycles

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LSR

Logical Shift Right M

LSR

Operation

0 b7 b6 b5 b4 b3 b2 b1 b0

M

C

Shifts all bits of M one place to the right. Loads bit 7 with 0. Loads the C bit from the least significant bit of M.

CCR

Effects

S X H I N Z V C

– – – – 0

∆ ∆ ∆

N: Cleared

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: M0; set if the LSB of M was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

LSR opr16a

LSR oprx0_xysppc

LSR oprx9,xysppc

LSR oprx16,xysppc

LSR [D, xysppc]

LSR [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

74 hh ll

64 xb

64 xb ff

64 xb ee ff

64 xb

64 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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LSRA

Logical Shift Right A

LSRA

Operation

0 b7 b6 b5 b4 b3 b2 b1 b0

A

C

Shifts all bits of A one place to the right. Loads bit 7 with 0. Loads the C bit from the least significant bit of A.

CCR

Effects

S X H I N Z V C

– – – – 0

∆ ∆ ∆

N: Cleared

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: A0; set if the LSB of A was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 44

Machine

Code (Hex)

LSRA O

CPU Cycles

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LSRB

Logical Shift Right B

LSRB

Operation

0 b7 b6 b5 b4 b3 b2 b1 b0

B

C

Shifts all bits of B one place to the right. Loads bit 7 with 0. Loads the C bit from the least significant bit of B.

CCR

Effects

S X H I N Z V C

– – – – 0

∆ ∆ ∆

N: Cleared

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: B0; set if the LSB of B was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 54

Machine

Code (Hex)

LSRB O

CPU Cycles

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LSRD

Logical Shift Right D

LSRD

Operation

0 b7 b6 b5 b4 b3 b2 b1 b0

A b7 b6 b5 b4 b3 b2 b1 b0

B

C

Shifts all bits of D one place to the right. Loads D15 (A7) with 0. Loads the C bit from D0

(B0).

CCR

Effects

S X H I N Z V C

– – – – 0

∆ ∆ ∆

N: Cleared

Z: Set if result is $0000; cleared otherwise

V: D0; set if, after the shift operation, C is set; cleared otherwise

C: D0; set if the LSB of D was set before the shift; cleared otherwise

Code and

CPU

Cycles

LSRD

Source Form

Address

Mode

INH 49

Machine

Code (Hex)

O

CPU Cycles

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MAXA

Maximum in A

MAXA

Operation

MAX [(A), (M)]

A

Subtracts an unsigned 8-bit value in M from an unsigned 8-bit value in A to determine which is larger. Puts the larger value in A. If the values are equal, the Z bit is set. If the value in M is larger, the C bit is set when the value in M replaces the value in A. If the value in

A is larger, the C bit is cleared.

MAXA accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate finding the largest value in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if (M) is larger than (A); cleared otherwise

Condition code bits reflect internal subtraction: R = (A) – (M).

Code and

CPU

Cycles

Source Form

MAXA oprx0_xysppc

MAXA oprx9,xysppc

MAXA oprx16,xysppc

MAXA [D, xysppc]

MAXA [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 18 xb

18 18 xb ff

18 18 xb ee ff

18 18 xb

18 18 xb ee ff

CPU Cycles

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

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MAXM

Maximum in M

MAXM

Operation

MAX [(A), (M)]

M

Subtracts an unsigned 8-bit value in M from an unsigned 8-bit value in A to determine which is larger. Puts the larger value in M. If the values are equal, the Z bit is set. If the value in M is larger, the C bit is set. If the value in A is larger, the C bit is cleared when the value in A replaces the value in M.

MAXM accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate controlling the values in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produces a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if (M) is larger than (A); cleared otherwise

Condition code bits reflect internal subtraction: R = (A) – (M).

Code and

CPU

Cycles

Source Form

MAXM oprx0_xysppc

MAXM oprx9,xysppc

MAXM oprx16,xysppc

MAXM [D, xysppc]

MAXM [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1C xb

18 1C xb ff

18 1C xb ee ff

18 1C xb

18 1C xb ee ff

CPU Cycles

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

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MEM

Determine Grade of Membership

(Fuzzy Logic)

MEM

Operation

Grade of membership

M

Y

(Y) + $0001

Y

(X) + $0004

X

Before executing MEM, initialize A, X and Y. Load A with the current crisp value of a system input variable. Load Y with the fuzzy input RAM location where the grade of membership is to be stored. Load X with the first address of a 4-byte data structure that describes a trapezoidal membership function. The data structure consists of:

• Point_1 — The x-axis starting point for the leading side (at M

X

)

• Slope_1 — The slope of the leading side (at M

X + 1

)

• Point_2 — The x-axis position of the rightmost point (at M

X + 2

)

• Slope_2 — The slope of the trailing side (at M

X + 3

)

A slope_1 or slope_2 value of $00 is a special case in which the membership function either starts with a grade of $FF at input = point_1, or ends with a grade of $FF at input = point_2

(infinite slope).

During execution, the value of A remains the same. X is incremented by four and Y is incremented by one.

CCR

Effects

S X H I N Z V C

– – ?

– ?

?

?

?

Code and

CPU

Cycles

Source Form

Address

Mode

Special

01

Machine

Code (Hex)

MEM

CPU Cycles

RRfOw

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MINA

Minimum in A

MINA

Operation

MIN [(A), (M)]

A

Subtracts an unsigned 8-bit value in M from an unsigned 8-bit value in A to determine which is larger. Puts the smaller value in A. If the values are equal, the Z bit is set. If the value in M is larger, the C bit is set. If the value in A is larger, the C bit is cleared when the value in M replaces the value in A.

MINA accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate finding the smallest value in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produced a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if the value of the value in M is larger than the value in A; cleared otherwise

Condition codes reflect internal subtraction R = (A) – (M).

Code and

CPU

Cycles

Source Form

MINA oprx0_xysppc

MINA oprx9,xysppc

MINA oprx16,xysppc

MINA [D, xysppc]

MINA [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 19 xb

18 19 xb ff

18 19 xb ee ff

18 19 xb

18 19 xb ee ff

CPU Cycles

OrPf

OrPO

OfrPP

OfIfrPf

OfIPrPf

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MINM

Minimum in M

MINM

Operation

MIN [(A), (M)]

M

Subtracts an unsigned 8-bit value in M from an unsigned 8-bit value in A to determine which is larger. Puts the smaller value in M. If the values are equal, the Z bit is set. If the value in M is larger, the C bit is set when the value in A replaces the value in M. If the value in A is larger, the C bit is cleared.

MINM accesses memory with indexed addressing modes for flexibility in specifying operand addresses. Autoincrement and autodecrement functions can facilitate controlling the values in a list of values.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: A7

M7

R7 | A7

M7

R7; set if the operation produced a two’s complement overflow; cleared otherwise

C: A7

M7 | M7

R7 | R7

A7; set if the value in M is larger than the value in A; cleared otherwise

Condition codes reflect internal subtraction R = (A) – (M).

Code and

CPU

Cycles

Source Form

MINM oprx0_xysppc

MINM oprx9,xysppc

MINM oprx16,xysppc

MINM [D, xysppc]

MINM [ oprx16,xysppc]

Address

Mode

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

18 1D xb

18 1D xb ff

18 1D xb ee ff

18 1D xb

18 1D xb ee ff

CPU Cycles

OrPw

OrPwO

OfrPwP

OfIfrPw

OfIPrPw

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MOVB

Move Byte

MOVB

Operation

(M

1

)

M

2

Moves the value in one 8-bit memory location, M

1

The value in M

1

does not change.

, to another 8-bit memory location, M

2

.

Move instructions can use different addressing modes to access the source and destination of a move. Supported addressing mode combinations are: IMM–EXT, IMM–IDX,

EXT–EXT, EXT–IDX, IDX–EXT, and IDX–IDX. IDX operands allow indexed addressing mode specifications that fit in a single postbyte; including 5-bit constant, accumulator offsets, and autoincrement/decrement modes. Nine-bit and 16-bit constant offsets would require additional extension bytes and are not allowed. Indexed-indirect modes (for example [D,r]) are also not allowed.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

1

Address

Mode

Machine

Code (Hex)

CPU Cycles

MOVB # opr8, opr16a

MOVB # opr8i, oprx0_xysppc

MOVB opr16a, opr16a

MOVB opr16a, oprx0_xysppc

MOVB oprx0_xysppc, opr16a

MOVB oprx0_xysppc, oprx0_xysppc

IMM–EXT

IMM–IDX

EXT–EXT

EXT–IDX

IDX–EXT

IDX–IDX

18 0B ii hh ll

18 08 xb ii

18 0C hh ll hh ll

18 09 xb hh ll

18 0D xb hh ll

18 0A xb xb

OPwP

OPwO

OrPwPO

OPrPw

OrPwP

OrPwO

NOTES:

1. The first operand in the source code statement specifies the source for the move.

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MOVW

Move Word

MOVW

Operation

(M

1

):(M

1

+ 1)

M

2

:M

2

+ 1

Moves the value in one 16-bit memory location, M

1 location, M

2

:M

2

+ 1. The value in M

1

:M

1

:M

1

+ 1, to another 16-bit memory

+ 1 does not change.

Move instructions can use different addressing modes to access the source and destination of a move. These combinations of addressing modes are supported: IMM–EXT,

IMM–IDX, EXT–EXT, EXT–IDX, IDX–EXT, and IDX–IDX. IDX operands allow indexed addressing mode specifications that fit in a single postbyte; including 5-bit constant, accumulator offsets, and autoincrement/decrement modes. Nine-bit and 16-bit constant offsets would require additional extension bytes and are not allowed.

Indexed-indirect modes (for example [D,r]) are also not allowed.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

1

Address

Mode

Machine

Code (Hex)

CPU Cycles

MOVW # opr16i, opr16a

MOVW # opr16i, oprx0_xysppc

MOVW opr16a, opr16a

MOVW opr16a, oprx0_xysppc

MOVW oprx0_xysppc, opr16a

MOVW oprx0_xysppc, oprx0_xysppc

IMM–EXT

IMM–IDX

EXT–EXT

EXT–IDX

IDX–EXT

IDX–IDX

18 03 jj kk hh ll OPWPO

18 00 xb jj kk OPPW

18 04 hh ll hh ll ORPWPO

18 01 xb hh ll

18 05 xb hh ll

18 02 xb xb

OPRPW

ORPWP

ORPWO

NOTES:

1. The first operand in the source code statement specifies the source for the move.

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MUL

Multiply, Unsigned

MUL

Operation

(A)

×

(B)

A:B

Multiplies the 8-bit unsigned value in A by the 8-bit unsigned value in B and places the

16-bit unsigned result in D. The carry flag allows rounding the high byte of the result through the sequence: MUL, ADCA #0.

CCR

Effects

S X H I N Z V C

– – – – – – –

C: R7; set if bit 7 of the result is set; cleared otherwise

Code and

CPU

Cycles

Source Form

Address

Mode

INH 12

Machine

Code (Hex)

MUL O

CPU Cycles

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NEG

Negate M

NEG

Operation

0 – (M) = (M) + 1

M

Replaces the value in M with its two’s complement. A value of $80 does not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: R7

R6

R5

R4

R3

R2

R1

R0; set if there is a two’s complement overflow from the implied subtraction from 0; cleared otherwise; two’s complement overflow occurs if and only if (M) = $80

C: R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0; set if there is a borrow in the implied subtraction from 0; cleared otherwise; set in all cases except when (M) = $00

Code and

CPU

Cycles

Source Form

NEG opr16a

NEG oprx0_xysppc

NEG oprx9,xysppc

NEG oprx16,xysppc

NEG [D, xysppc]

NEG [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

70 hh ll

60 xb

60 xb ff

60 xb ee ff

60 xb

60 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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NEGA

Negate A

NEGA

Operation

0 – (A) = (A) + 1

A

Replaces the value in A with its two’s complement. A value of $80 does not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: R7

R6

R5

R4

R3

R2

R1

R0; set if there is a two’s complement overflow from the implied subtraction from 0; cleared otherwise; two’s complement overflow occurs if and only if (A) = $80

C: R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0; set if there is a borrow in the implied subtraction from 0; cleared otherwise; set in all cases except when (A) = $00

Code and

CPU

Cycles

NEGA

Source Form

Address

Mode

INH

40

Machine

Code (Hex)

O

CPU Cycles

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NEGB

Negate B

NEGB

Operation

0 – (B) = (B) + 1

B

Replaces the value in B with its two’s complement. A value of $80 does not change.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: R7

R6

R5

R4

R3

R2

R1

R0; set if there is a two’s complement overflow from the implied subtraction from 0; cleared otherwise; two’s complement overflow occurs if and only if (B) = $80

C: R7 | R6 | R5 | R4 | R3 | R2 | R1 | R0; set if there is a borrow in the implied subtraction from 0; cleared otherwise; set in all cases except when (B) = $00

Code and

CPU

Cycles

NEGB

Source Form

Address

Mode

INH

50

Machine

Code (Hex)

O

CPU Cycles

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NOP

Null Operation

NOP

Operation

No operation

This single-byte instruction increments the PC and does nothing else. No other CPU registers are affected. NOP typically is used to produce a time delay, although some software disciplines discourage CPU frequency-based time delays. During debug, NOP instructions are sometimes used to temporarily replace other machine code instructions, thus disabling the replaced instruction(s).

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

NOP

Source Form

Address

Mode

INH

A7

Machine

Code (Hex)

O

CPU Cycles

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ORAA

OR Accumulator A

ORAA

Operation

(A) | (M)

A or

(A) | imm

A

Performs logical inclusive OR of the value in A and either the value in M or an immediate value. Puts the result in A.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

ORAA # opr8i

ORAA opr8a

ORAA opr16a

ORAA oprx0_xysppc

ORAA oprx9,xysppc

ORAA oprx16,xysppc

ORAA [D, xysppc]

ORAA [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

8A ii

9A dd

BA hh ll

AA xb

AA xb ff

AA xb ee ff

AA xb

AA xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ORAB

OR Accumulator B

ORAB

Operation

(B) | (M)

B or

(B) | imm

B

Performs logical inclusive OR of the value in B and either the value in M or an immediate value. Puts the result in B.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆

0 –

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Cleared

Code and

CPU

Cycles

Source Form

ORAB # opr8i

ORAB opr8a

ORAB opr16a

ORAB oprx0_xysppc

ORAB oprx9,xysppc

ORAB oprx16,xysppc

ORAB [D, xysppc]

ORAB [ oprx16,xysppc]

Address

Mode

IMM

DIR

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine Coding

(Hex)

CA ii

DA dd

FA hh ll

EA xb

EA xb ff

EA xb ee ff

EA xb

EA xb ee ff

CPU Cycles

P rPf rPO rPf rPO frPP fIfrPf fIPrPf

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ORCC

OR CCR

ORCC

Operation

(CCR) | imm

CCR

Performs a logical inclusive OR of the value in the CCR and an immediate value. Puts the result in the CCR. CCR bits that correspond to 1s in M are set. No other CCR bits change.

NOTE:

The X bit cannot be set by any software instruction.

CCR

Effects

S X H I N Z V C

⇑ ⇑ ⇑ ⇑ ⇑ ⇑

A condition code bit is set if the corresponding bit was 1 before the operation or if the corresponding bit in the instruction-provided mask is 1. The X bit cannot be set by any software instruction.

Code and

CPU

Cycles

Source Form

ORCC # opr8i

Address

Mode

IMM

14 ii

Machine

Code (Hex)

P

CPU Cycles

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PSHA

Push A onto Stack

PSHA

Operation

(SP) – $0001

SP

(A)

M

SP

Decrements SP by one and loads the value in A into the address to which SP points.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved

CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

36

Machine

Code (Hex)

PSHA

Os

CPU Cycles

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PSHB

Push B onto Stack

PSHB

Operation

(SP) – $0001

SP

(B)

M

SP

Decrements SP by one and loads the value in B into the address to which SP points.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved

CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

37

Machine

Code (Hex)

PSHB

Os

CPU Cycles

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PSHC

Push CCR onto Stack

PSHC

Operation

(SP) – $0001

SP

(CCR)

M

SP

Decrements SP by one and loads the value in CCR into the address to which the SP points.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can be used to restore the saved

CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

39

Machine

Code (Hex)

PSHC

Os

CPU Cycles

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PSHD

Push D onto Stack

PSHD

Operation

(SP) – $0002

SP

(A):(B)

M

SP

:M

SP + 1

Decrements SP by two and loads the value in A into the address to which SP points. Loads the value in B into the address to which SP points plus one. After PSHD executes, SP points to the stacked value of A.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

3B

Machine

Code (Hex)

PSHD

OS

CPU Cycles

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PSHX

Push X onto Stack

PSHX

Operation

(SP) – $0002

SP

(X

H

):(X

L

)

M

SP

:M

SP + 1

Decrements SP by two and loads the high byte of X into the address to which SP points.

Loads the low byte of X into the address to which SP points plus one. After PSHX executes,

SP points to the stacked value of the high byte of X.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

34

Machine

Code (Hex)

PSHX

OS

CPU Cycles

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PSHY

Push Y onto Stack

PSHY

Operation

(SP) – $0002

SP

(Y

H

):(Y

L

)

M

SP

:M

SP + 1

Decrements SP by two and loads the high byte of Y into the address to which SP points.

Loads the low byte of Y into the address to which SP points plus one. After PSHY executes,

SP points to the stacked value of the high byte of Y.

Push instructions are commonly used to save the contents of one or more CPU registers at the start of a subroutine. Complementary pull instructions can restore the saved CPU registers just before returning from the subroutine.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

35

Machine

Code (Hex)

PSHY

OS

CPU Cycles

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PULA

Pull A from Stack

PULA

Operation

(M

SP

)

A

(SP) + $0001

SP

Loads A from the address to which SP points. Then increments SP by one.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

32

Machine

Code (Hex)

PULA

CPU Cycles

ufO

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PULB

Pull B from Stack

PULB

Operation

(M

SP

)

B

(SP) + $0001

SP

Loads B from the address to which SP points. Then increments SP by one.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

33

Machine

Code (Hex)

PULB

CPU Cycles

ufO

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PULC

Pull CCR from Stack

PULC

Operation

(M

SP

)

CCR

(SP) + $0001

SP

Loads CCR from the address to which SP points. Then increments SP by one.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

∆ ⇓ ∆ ∆ ∆ ∆ ∆ ∆

Condition codes take on the value pulled from the stack, except that the X mask bit cannot change from 0 to

1. Software can leave the X bit set, leave it cleared, or change it from 1 to 0, but it can only be set by a reset or by recognition of an XIRQ interrupt.

Code and

CPU

Cycles

Source Form

Address

Mode

INH 38

Machine

Code (Hex)

PULC

CPU Cycles

ufO

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PULD

Pull D from Stack

PULD

Operation

(M

SP

):(M

SP + 1

)

A:B

(SP) + $0002

SP

Loads the high byte of D from the address to which SP points. Loads the low byte of D from the address to which SP points plus one. Then increments SP by two.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

3A

Machine

Code (Hex)

PULD

CPU Cycles

UfO

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PULX

Pull X from Stack

PULX

Operation

(M

SP

):(M

SP + 1

)

X

H

(SP) + $0002

SP

:X

L

Loads the high byte of X from the address to which SP points. Loads the low byte of X from the address to which SP points plus one. Then increments SP by two.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

30

Machine

Code (Hex)

PULX

CPU Cycles

UfO

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PULY

Pull Y from Stack

PULY

Operation

(M

SP

):(M

SP + 1

)

Y

H

(SP) + $0002

SP

:Y

L

Loads the high byte of Y from the address to which SP points. Loads the low byte of Y from the address to which SP points plus one. Then increments SP by two.

Pull instructions are commonly used at the end of a subroutine to restore the contents of

CPU registers that were pushed onto the stack before subroutine execution.

CCR

Effects

S X H I N Z V C

– – – – – – – –

Code and

CPU

Cycles

Source Form

Address

Mode

INH

31

Machine

Code (Hex)

PULY

CPU Cycles

UfO

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REV

Fuzzy Logic Rule Evaluation

REV

Operation

MIN – MAX rule evaluation

Performs an unweighted evaluation of a list of rules, using fuzzy inputs to produce fuzzy outputs. REV can be interrupted, so it does not adversely affect interrupt latency.

REV uses an 8-bit unsigned offset from a base address stored in Y to determine the address of each fuzzy input and fuzzy output. Each rule in the knowledge base must consist of a table of 8-bit antecedent offsets followed by a table of 8-bit consequent offsets. The value

$FE marks boundaries between antecedents and consequents and between successive rules.

The value $FF marks the end of the rule list.

REV begins with the address pointed to by the first rule antecedent and evaluates successive fuzzy input values until it finds an $FE separator. Operation is similar to that of a MINA instruction. The smallest input value is the truth value of the rule. Then, beginning with the address pointed to by the first rule consequent, REV compares the truth value to successive fuzzy output values until it finds another $FE separator. If the truth value is greater than the current output value, REV writes it to the output. Operation is similar to that of a MAXM instruction. Rule processing continues up to the $FF terminator

Before executing REV, clear fuzzy outputs and initialize A, CCR, X, and Y. Load A with

$FF. Clear the V bit. Load X with the address of the first 8-bit rule element in the list. Load

Y with the base address for fuzzy inputs and fuzzy outputs.

X points to the element in the rule list that is being evaluated. REV updates X so that execution can resume correctly in case of an interrupt. After execution, X points to the address after the $FF separator at the end of the rule list.

Y points to the base address for the fuzzy inputs and fuzzy outputs. The value in Y does not change during execution.

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REV

Fuzzy Logic Rule Evaluation

(continued)

REV

A holds intermediate results. During antecedent processing, a MIN function compares each fuzzy input to the value in A and writes the smaller value to A. After evaluation of all antecedents, A contains the smallest input value. This is the truth value used during consequent processing. For subsequent rules, REV reinitializes A with $FF when it finds an $FE separator. After execution, A contains the truth value for the last rule.

The V bit signals whether antecedents (0) or consequents (1) are being processed. V must be initialized to 0 for processing to begin with the antecedents of the first rule. The value of V changes as $FE separators are encountered. After execution, V should equal 1, because the last element before the $FF terminator should be a rule consequent. If V is 0 at the end of execution, the rule list is incorrect.

CCR

Effects

S X H I N Z V C

– – ?

– ?

?

?

V: Set unless rule structure is incorrect

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

CPU Cycles

REV Special 18 3A

OrfttxO

1 ff + Orf

2

NOTES:

1. The 3-cycle ttx

loop is executed once for each element in the rule list.

2. These are additional cycles caused by an interrupt: ff is a 2-cycle exit sequence and

Orf is a 3-cycle re-entry sequence. Execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt.

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REVW

Fuzzy Logic Rule Evaluation, Weighted

REVW

Operation

MIN – MAX rule evaluation with optional rule weighting

Performs either weighted or unweighted evaluation of a list of rules, using fuzzy inputs to produce fuzzy outputs. REVW can be interrupted, so it does not adversely affect interrupt latency.

Each rule in the knowledge base must consist of a table of 16-bit antecedent pointers followed by a table of 16-bit consequent pointers. The value $FFFE marks boundaries between antecedents and consequents and between successive rules. The value $FFFF marks the end of the rule list.

In weighted evaluation, a table of 8-bit weighting factors, one per rule, must be stored in memory.

REVW begins with the address pointed to by the first rule antecedent, and evaluates successive fuzzy input values until it finds an $FFFE separator. Operation is similar to that of a MINA instruction. The smallest input value is the truth value of the rule. If weighted evaluation is enabled, the truth value is modified. Then, beginning with the address pointed to by the first consequent, REVW compares the truth value to successive fuzzy output values until it finds another $FFFE. If the truth value is greater than the current output value, REVW writes it to the output. Operation is similar to that of a MAXM instruction.

Rule processing continues up to the $FFFF terminator.

Before executing REVW, clear fuzzy outputs and initialize A, CCR, X, and Y. Load A with

$FF. Clear the V bit. Set or clear the C bit for weighted or unweighted evaluation. For weighted evaluation, load Y with the first item in a table of 8-bit weighting factors. Load

X with the address of the first 16-bit element in the list.

X points to the element in the list that is being evaluated. REVW updates X so that execution can resume after an interrupt. After execution, X points to the address after the

$FFFF separator at the end of the list.

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REVW

Fuzzy Logic Rule Evaluation, Weighted

(continued)

REVW

Y points to the current weighting factor. REVW updates Y so that execution can resume after an interrupt. After execution, Y points to the last weighting factor used. Y does not change in unweighted evaluation.

A holds intermediate results. During antecedent processing, a MIN function compares each fuzzy input to the value stored in A and writes the smaller value to A. After evaluation of all antecedents, A contains the smallest input value. In unweighted evaluation, this is the truth value for consequent processing. In weighted evaluation, it is multiplied by the quantity rule weight + 1, and the upper eight bits of the result replace the value in A. REVW reinitializes A with $FF when it finds an $FFFE separator. After execution, A holds the truth value for the last rule.

The V bit signals whether antecedents (0) or consequents (1) are being processed. V must be initialized to 0 for processing to begin with the antecedents of the first rule. The value of V changes as $FFFE separators are found. After execution, V should equal 1, because the last element before the $FF end marker should be a rule consequent. If V is equal to 0 at the end of execution, the rule list is incorrect.

CCR

Effects

S X H I N Z V C

– – ?

– ?

?

!

V: Set unless rule structure is incorrect

C: 1 selects weighted rule evaluation; 0 selects unweighted rule evaluation

Code and

CPU

Cycles

Source Form

Address

Mode

Machine

Code (Hex)

CPU Cycles

REVW Special 18 3B

ORftTxO

1 or

ORftTfRfO

2 ffff + ORf

3

NOTES:

1. Weighting not enabled; the 3-cycle tTx loop is executed once for each element in the rule list.

2. Weighting enabled; the 3-cycle tTx

loop expands to tTfRf

for separators.

3. These are additional cycles caused by an interrupt: ffff

is a 4-cycle exit sequence and

ORf

is a 3-cycle re-entry sequence. Execution resumes with a prefetch of the last antecedent or consequent being processed at the time of the interrupt.

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ROL

Operation

Rotate Left M

ROL

C b7 b6 b5 b4 b3 b2 b1 b0

M

Shifts all bits of M one place to the left. Bit 0 is loaded from the C bit. The C bit is loaded from the most significant bit of M. Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes. For example, to shift a 24-bit value one bit to the left, the sequence ASL LOW, ROL MID, ROL HIGH could be used where LOW, MID, and HIGH refer to the low, middle, and high bytes of the 24-bit value, respectively.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: M7; set if the MSB of M was set before the shift; cleared otherwise

Code and

CPU

Cycles

Source Form

ROL opr16a

ROL oprx0_xysppc

ROL oprx9,xysppc

ROL oprx16,xysppc

ROL [D, xysppc]

ROL [ oprx16,xysppc]

Address

Mode

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

Machine

Code (Hex)

75 hh ll

65 xb

65 xb ff

65 xb ee ff

65 xb

65 xb ee ff

CPU Cycles

rPwO rPw rPwO frPwP fIfrPw fIPrPw

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ROLA

Operation

Rotate Left A

ROLA

C b7 b6 b5 b4 b3 b2 b1 b0

A

Shifts all bits of A one place to the left. Bit 0 is loaded from the C bit. The C bit is loaded from the most significant bit of A. Rotate operations include the carry bit to allow extension of shift and rotate operations to multiple bytes. For example, to shift a 24-bit value one bit to the left, the sequence ASL LOW, ROL MID, ROL HIGH could be used where LOW,

MID and HIGH refer to the low, middle, and high bytes of the 24-bit value, respectively.

CCR

Effects

S X H I N Z V C

– – – –

∆ ∆ ∆ ∆

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: N

C = [N

C] | [N

C] (for N and C after the shift); set if (N is set and C is cleared) or (N is cleared and

C is set); cleared otherwise (for values of N and C after the shift)

C: A7; set if the MSB of A was set before the shift; cleared otherwise