Si4730/31
S i 4 7 3 0/31
B R O A D C A S T AM/FM R A D I O R E C E I V E R
Features
Worldwide FM band support
(76–108 MHz)
Worldwide AM band support
(520–1710 kHz)
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced AM/FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Integrated LDO regulator
Digital FM stereo decoder
Programmable de-emphasis
Adaptive noise suppression
AM/FM digital tuning
No manual alignment required
Programmable reference clock
Volume control
Soft mute control
RDS/RBDS processor (Si4731 only)
2-wire and 3-wire control interface
2.7 to 5.5 V supply voltage
Firmware upgradeable
Wide range of ferrite loop sticks and
air loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
Pb-free/RoHS compliant
Ordering Information:
See page 25.
Pin Assignments
Si4730/31-GM
Applications
NC
1
20 19 18 17 16
FMI 2
15 NC
RFGND 3
13 ROUT
6
7
8
9
RCLK
12 GND
SDIO
RST 5
SCLK
Functional Block Diagram
AMI 4
SEN
The Si4730/31 is the first digital CMOS AM/FM radio receiver IC that integrates
the complete tuner function from antenna input to audio output.
14 LOUT
GND
PAD
10 11 VDD
VIO
Description
NC
GPO3
GPO2/INT
GPO1
(Top View)
Cellular handsets
Modules
Clock radios
Mini HiFi
Entertainment systems
Car radios
NC
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Portable media players
Boom boxes
Si473x
AMI
LNA
RDS
(Si4731)
AGC
LOW-IF
ADC
LNA
AGC
2.7 - 5.5 V
ADC
AFC
RCLK
LDO
Preliminary Rev. 0.5 4/07
ROUT
DAC
LOUT
DSP
VDD
GND
DAC
CONTROL
INTERFACE
VIO
1.5-3.6V
Notes:
1. To ensure proper operation and
receiver performance, follow the
guidelines in “AN384: Si4730/31
AM/FM Receiver Layout Guide.”
Silicon Laboratories will evaluate
schematics and layouts for qualified
customers.
2. Place Si4730/31 as close as
possible to antenna jack and keep
the FMI and AMI traces as short as
possible.
RST
FMI
SEN
FM
ANT
Patents pending
SDIO
RFGND
SCLK
AM
ANT
Copyright © 2007 by Silicon Laboratories
Si4730/31
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Si4730/31
2
Preliminary Rev. 0.5
Si4730/31
TA B L E O F C O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. Operating Bands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.4. AM receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9. RDS/RBDS Processor (Si4731 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.16. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.17. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. Pin Descriptions: Si4730/31-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Package Outline: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9. PCB Land Pattern: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Preliminary Rev. 0.5
3
Si4730/31
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage
VDD
2.7
—
5.5
V
Interface Supply Voltage
VIO
1.5
—
3.6
V
TA
–20
25
85
°C
Ambient Temperature
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Supply Voltage
VDD
–0.5 to 5.8
V
Interface Supply Voltage
VIO
–0.5 to 3.9
V
Input Current3
IIN
10
mA
3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
°C
Storage Temperature
TSTG
–55 to 150
°C
0.4
VpK
Input Voltage
RF Input Level4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4730/31 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
Preliminary Rev. 0.5
Si4730/31
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
19.2
—
mA
FM Mode
Supply Current
Supply Current
IFM
1
RDS Supply Current
IFM
Low SNR level
—
19.8
—
mA
IFM
(Si4731 only)
—
19.9
—
mA
IA
—
16.8
—
mA
IIO
—
400
—
µA
IPD
—
10
20
µA
—
1
10
µA
AM Mode
Supply Current
Supplies and Interface
Interface Supply Current
Powerdown Current
2,3
2
Interface Powerdown Current
IIO
SCLK, RCLK inactive
4
VIH
0.7 x VIO
—
—
V
4
VIL
—
—
0.3 x VIO
V
4
IIH
VIN = VIO = 3.6 V
–10
—
10
µA
4
IIL
VIN = 0 V,
VIO = 3.6 V
–10
—
10
µA
High Level Output Voltage5
VOH
IOUT = 500 µA
0.8 x VIO
—
—
V
5
VOL
IOUT = –500 µA
—
—
0.2 x VIO
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Low Level Output Voltage
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. Refer to Section "4.16. Reset, Powerup, and Powerdown" on page 20.
4. For input pins SCLK, SEN, SDIO, RST, and RCLK.
5. For output pins SDIO, DFS, GPO1, GPO2, and GPO3.
Preliminary Rev. 0.5
5
Si4730/31
Table 4. Reset Timing Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
GPO1, GPO2 Input to RST ↑ Setup
tSRST
30
—
—
ns
GPO1, GPO2 Input to RST ↑ Hold
tHRST
Busmode Select
Method*
30
—
—
ns
*Note: In Busmode Select Method, GPIO3 may be left high-Z (minimum pullup 10 MΩ), be left floating, or pulled low to be
backwards compatible with Si4730/31 silicon revision A. If GPIO3 is pulled low then the minimum tSRST for RST↓,
GPIO3 input to RST↑ setup is only 30 nS. Do not force SCLK low during the rising edge of RST.
tSRST
RST
GPO1
GPO2
tHRST
70%
30%
70%
30%
70%
30%
Figure 1. Reset Timing Parameters for Busmode Select Method
6
Preliminary Rev. 0.5
Si4730/31
Table 5. 2-Wire Control Interface Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO ↓ Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO ↓ Hold
(START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK ↑ Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK ↓ Hold3,4
tHD:DAT
0
—
900
ns
SCLK input to SDIO ↑ Setup
(STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
20 + 01.Cb
—
250
ns
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
20 + 01.Cb
—
300
ns
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. Do not force SCLK low during the rising edge of RST.
3. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the 0 ns tHD:DAT
specification.
4. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated so long as all other timing parameters are met.
Preliminary Rev. 0.5
7
Si4730/31
SCLK
SDIO
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
70%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Preliminary Rev. 0.5
STOP
Si4730/31
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
—
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLK↑ Hold
tHSDIO
10
—
—
ns
SEN Input to SCLK↓ Hold
tHSEN
10
—
—
ns
SCLK↑ to SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLK↑ to SDIO Output High Z
tCDZ
Read
2
—
25
ns
10
ns
SDIO Input, SEN to SCLK↑ Setup
tR
tF
SCLK, SEN, SDIO, Rise/Fall time
SCLK
70%
30%
tS
SEN
SDIO
tR
tF
70%
t HSDIO
tHIGH
tLOW
t HSEN
tS
30%
70%
30%
A7
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
30%
tHSDIO
tS
SEN
70%
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Preliminary Rev. 0.5
9
Si4730/31
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
15
—
—
ns
SDIO Input to SCLK↑ Hold
tHSDIO
10
—
—
ns
SEN Input to SCLK↓ Hold
tHSEN
5
—
—
ns
SCLK↓ to SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLK↓ to SDIO Output High Z
tCDZ
Read
2
—
25
ns
10
ns
SDIO Input, SEN to SCLK↑ Setup
tR
tF
SCLK, SEN, SDIO, Rise/Fall time
SCLK
70%
30%
tHIGH
SEN
SDIO
tLOW
tHSDIO
tR
tF
tHSEN
70%
30%
70%
30%
tS
tS
C7
C6 –C1
C0
D7
Control Byte In
D6 –D1
D0
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
SCLK
70%
30%
tCDV
tS
SEN
70%
t HSEN
tHSDIO
tS
30%
tCDZ
SDIO
70%
C7
C6–C1
C0
D7
D6–D1
D0
30%
Control Byte In
Bus
Turnaround
16 Data Bytes Out
(SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters
10
Preliminary Rev. 0.5
Si4730/31
Table 8. FM Receiver Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Symbol
Parameter
Input Frequency
Test Condition
fRF
Min
Typ
Max
Unit
76
—
108
MHz
Sensitivity3,4,5,6,7
(S+N)/N = 26 dB
—
2.2
3.5
µV EMF
RDS Sensitivity
∆f = 2 kHz,
RDS BLER < 5%
—
15
—
µV EMF
3
4
5
kΩ
4
5
6
pF
—
105
—
dBµV EMF
m = 0.3
40
50
—
dB
±200 kHz
35
50
—
dB
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
Audio Output Voltage3,4,6
72
80
90
mVRMS
Audio Output L/R Imbalance3,6,8
—
—
1
dB
30
—
15k
Hz
25
—
—
dB
Audio S/N3,4,5,6
58
63
—
dB
Audio THD3,6,8
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
0.7
0.8
0.9
V
High-Z mode
—
0.5 x VIO
—
V
RL
Single-ended
10
—
—
kΩ
CL
Single-ended
—
—
50
pF
RCLK tolerance
= 100 ppm
—
—
60
ms/channel
From powerdown
—
—
110
ms
LNA Input Resistance6,10
LNA Input
Input IP3
Capacitance6,10
7,10
AM Suppression3,4,6,10
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
Audio Band Limits
Audio Stereo
10
3,6,9
±1.5 dB
Separation3,6,8
De-emphasis Time Constant
Audio Common Mode Voltage9
Audio Common Mode Voltage
9,10
Audio Output Load Resistance
Audio Output Load Capacitance
Seek/Tune Time
Powerup Time
10
9,10
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests. Tested at
Rf = 100 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. ∆f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Measured at VEMF = 1 mV, fRF = 76 to 108 MHz.
7. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4730/31-GM" on page 24.
8. ∆f = 75 kHz.
9. At LOUT and ROUT pins.
10. Guaranteed by characterization.
Preliminary Rev. 0.5
11
Si4730/31
Table 8. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Symbol
Parameter
RSSI Offset
Test Condition
Min
Input levels of 8 and
60 dBµV EMF
–3
Typ
Max
Unit
3
dB
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests. Tested at
Rf = 100 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. ∆f = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. Measured at VEMF = 1 mV, fRF = 76 to 108 MHz.
7. |f2 – f1| > 1 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4730/31-GM" on page 24.
8. ∆f = 75 kHz.
9. At LOUT and ROUT pins.
10. Guaranteed by characterization.
Table 9. AM Receiver Characteristics1
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Input Frequency
Min
Typ
Max
Unit
520
—
1710
kHz
(S+N)/N = 26 dB
—
38
—
µV EMF
THD < 8%
—
300
—
mVRMS
∆VDD = 100 mVRMS, 100 Hz
—
40
—
dB
54
60
66
mVRMS
—
58
—
dB
—
.1
.5
%
180
—
600
µH
—
60
—
ms/channel
—
—
110
ms
fRF
Sensitivity2,3
Large Signal Voltage Handling
Power Supply Rejection Ratio
Audio Output Voltage
Test Condition
4
2,5
Audio S/N2,3,5
2,3,5
Audio THD
Antenna Inductance4
Seek/Tune Time
Powerup Time
From powerdown
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. fRF = 1000 kHz, ∆f = 10 kHz.
4. Guaranteed by characterization.
5. VIN = 5 mVrms.
12
Preliminary Rev. 0.5
Si4730/31
Table 10. Reference Clock and Crystal Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
31,130
32,768
40,000
kHz
–100
—
100
ppm
Crystal Oscillator Frequency
—
32.768
—
kHz
Crystal Frequency Tolerance
–100
—
100
ppm
—
—
3.5
pF
Reference Clock
RCLK Supported Frequencies
RCLK Frequency Tolerance
Crystal Oscillator
Board Capacitance
Preliminary Rev. 0.5
13
Si4730/31
2. Typical Application Schematic
GPO1
NC
GPIO1
GPIO2
GPIO3
NC
20
19
18
17
16
GPO2/INT
GPO3
1
NC
2
FMI
3
RFGND
FMIP
L1
AM antenna
4
C5
5
U1
Si4730/31-GM
AMI
RST
15
NC
14
LOUT
13
ROUT
12
GND
11
VDD
LOUT
ROUT
VBATTERY
2.7 to 5.5 V
RST
6
7
8
9
10
SEN
SCLK
SDIO
RCLK
VIO
C1
X1
GPIO3
SEN
SCLK
SDIO
RCLK
VIO
1.5 to 3.6 V
C2
RCLK
C3
Optional: for crystal oscillator option
F2
RFGND
AMI
T1
C5
Optional: AM air loop antenna
Notes:
1. Place C1 close to VDD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4730/31 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
14
Preliminary Rev. 0.5
Si4730/31
3. Bill of Materials
Component(s)
Value/Description
Supplier
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
C5
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Murata
L1
Ferrite loop stick, 180–600 µH
Various
U1
Si4730/31 AM/FM Radio Tuner
Silicon Laboratories
Optional Components
T1
Transformer, 1–5 turns ratio
Various
L2
Air loop antenna, 10–20 µH
Various
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
C2, C3
X1
Preliminary Rev. 0.5
15
Si4730/31
4. Functional Description
4.1. Overview
Si473x
AMI
LNA
RDS
(Si4731)
AGC
LOW-IF
ADC
LNA
ADC
VDD
LDO
AFC
RCLK
GND
ROUT
DAC
LOUT
DSP
AGC
2.7 - 5.5 V
DAC
CONTROL
INTERFACE
VIO
1.5-3.6V
RST
FMI
SCLK
FM
ANT
SDIO
RFGND
SEN
AM
ANT
Figure 8. Functional Block Diagram
The Si4730/31 is the industry's first fully integrated,
100% CMOS AM/FM radio receiver IC. Offering
unmatched integration and PCB space savings, the
Si4730/31 requires only two external components and
less than 15 mm2 of board area, excluding the antenna
inputs. The Si4730/31 AM/FM radio provides the space
savings and low power consumption necessary for
portable devices while delivering the high performance
and design simplicity desired for all AM/FM solutions.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4730/31 delivers
superior RF performance and interference rejection in
both AM and FM bands. The high integration and
complete system production test simplifies design-in,
increases
system
quality,
and
improves
manufacturability.
The Si4730/31 is a feature-rich solution including
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, and FM stereo processing. In addition, the
Si4730/31 provides a programmable reference clock.
The device supports I2C-compatible 2-wire control
interface, and a Si4700/01 backwards-compatible 3wire control interface.
16
The Si4730/31 utilizes digital processing to achieve high
fidelity, optimal performance, and design flexibility. The
chip provides excellent pilot rejection, selectivity, and
unmatched audio performance, and offers both the
manufacturer
and
the
end-user
extensive
programmability and flexibility in listening experience.
The Si4731 incorporates a digital processor for the
European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS)
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using this feature, the Si4731 enables
broadcast data such as station identification and song
name to be displayed to the user.
4.2. Operating Bands
The Si4731 operates in either an FM receive or an AM
receive mode. In FM mode, radio signals are received
on FMI (pin 2) and processed by the FM front-end
circuitry. In AM mode, radio signals are received on AMI
(pin 4) and processed by the AM front-end circuitry. To
select either FM or AM band, use the “Powerup”
command (See Table 12 on page 21).
Preliminary Rev. 0.5
4.3. FM Receiver
The Si4730/31 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture allowing the elimination of external
components and factory adjustments. The Si4730/31
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers. For testing purposes, the AGC can be
disabled. Refer to Section "5. Commands and
Properties" on page 21 for additional programming and
configuration information. An image-reject mixer
downconverts the RF signal to low-IF. The quadrature
mixer output is amplified, filtered, and digitized with high
resolution analog-to-digital converters (ADCs). This
advanced architecture allows the Si4730/31 to perform
channel selection, FM demodulation, and stereo audio
processing to achieve superior performance compared
to traditional analog architectures.
4.4. AM receiver
The highly integrated Si4730/31 supports worldwide AM
band reception from 520 to 1710 kHz using a digital lowIF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering offering excellent selectivity and noise
suppression. The DSP also provides 9 or 10 kHz
channel selection, AM demodulation, soft mute, and
additional features such as adjustable channel
bandwidth settings. Similar to the FM receiver, the
integrated LNA and AGC optimize sensitivity and
rejection of strong interferers allowing better reception
of weak stations.
The Si4730/31 provides highly accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–600 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor the inductance is increased by 25x easily
supporting all typical AM air loop antennas which
generally vary between 10 and 20 µH.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 9 below.
17
Modulation Level
Si4730/31
Mono Audio
Left + Right
0
Stereo
Pilot
15 19 23
Stereo Audio
Left - Right
38
RDS/
RBDS
53
57
Frequency (kHz)
Figure 9. MPX Signal Spectrum
4.5.1. Stereo Decoder
The
Si4730/31's
integrated
stereo
decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4731 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
4.5.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
operation
can
be
forced
with
the
FM_BLEND_MONO_THRESHOLD property.
4.6. De-emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4730/31
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
4.7. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
Preliminary Rev. 0.5
Si4730/31
4.8. Soft Mute
4.10. Tuning
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION and
AM_SOFT_MUTE_MAX_ATTENUATION properties.
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop
during reception.
4.9. RDS/RBDS Processor (Si4731 only)
The Si4731 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4731 device provides an interrupt when RDS is
synchronized and RDS group data has been received
by the device. The interrupt is set regardless of RDS
block error levels in the data group. The device provides
interrupts every 1.1875 ms. If the device loses RDS
synchronization, RDS data decode and data capture
are not possible, and interrupts will not be set until RDS
synchronization is reestablished, and an RDS data
group has been received.
The Si4731 reports RDS decoder synchronization
status, and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors, or that the block
checkword contains errors.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
The tuning frequency can be directly programmed using
the
FM_TUNE_FREQ
and
AM_TUNE_FREQ
commands. The Si4730/31 supports channel spacing of
50, 100, or 200 kHz in FM mode and 9 or 10 kHz in AM
mode.
4.11. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated
using
the
FM_SEEK_START
and
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Table 13).
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
4.12. Reference Clock
The Si4730/31 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
voltage
levels
and
Table 8,
“FM
Receiver
Characteristics” on page 11 for frequency tolerance
information.
18
Preliminary Rev. 0.5
Si4730/31
4.13. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4730/31,
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, 3-wire
mode, or SPI mode. The Si4730/31 selects the bus
mode by sampling the state of the GPO1 and GPO2
pins on the rising edge of RST. The GPO1 pin includes
an internal pull-up resistor which is connected while
RST is low, and the GPO2 pin includes an internal pulldown resistor which is connected while RST is low.
Therefore, it is only necessary for the user to actively
drive pins which differ from these states:
Table 11. Bus Mode Select on Rising Edge of
RST
Bus Mode
GPO1
GPO2
2-Wire
1
0
SPI
1
1 (must drive)
3-Wire
0 (must drive)
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.14. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied. Do not force SCLK low during the
rising edge of RST.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
4.13.1. 2-Wire Control Interface Mode
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4730/31 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4730/31 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the seven-bit device
address is 0010001. When SEN = 1, the address is
1100011.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4730/31 acknowledges
19
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to 8
data bytes in a single 2-wire transaction. The first byte is
a command, and the next seven bytes are arguments.
For read operations, after the Si4730/31 has
acknowledged the control byte, it will drive an eight bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If a data byte is not
acknowledged, the transaction will end. The user may
read up to 16 data bytes in a single 2-wire transaction.
These bytes contain the response data from the
Si4730/31.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on
page 7, Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8 and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,”
on page 8.
4.13.2. 3-Wire Control Interface Mode
3-wire bus mode uses the SCLK, SDIO and SEN_ pins.
A transaction begins when the user drives SEN low.
Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a three-bit device
address (A7:A5 = 101), a read/write bit (read = 1, write
= 0), and a five-bit register address (A4:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4730/31 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9, Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
Preliminary Rev. 0.5
Si4730/31
4.13.3. SPI Control Interface Mode
4.14. GPO Outputs
SPI bus mode uses the SCLK, SDIO, and SEN pins for
read/write operations. For reads, the user can choose to
receive data from the device on either SDIO or GPO1. A
transaction begins when the user drives SEN low. The
user then pulses SCLK eight times while driving an 8-bit
control byte (MSB first) serially on SDIO. The device
captures the data on rising edges of SCLK. The control
byte must have one of these values:
GPO2 can be configured to provide interrupts for seek
and tune complete, receive signal quality, and RDS.
GPO1 and GPO3 are not available on Revision 1.0 of
the firmware.
0x48 = write 8 command/argument bytes (user will drive
write data on SDIO)
0x80 = read status byte (device will drive read data on
SDIO)
0xA0 = read status byte (device will drive read data on
GPO1)
0xC0 = read 16 response bytes (device will drive read
data on SDIO)
0xE0 = read 16 response bytes (device will drive read
data on GPO1)
When writing a command, after the control byte has
been written, the user must drive exactly 8 data bytes (a
command byte and 7 argument bytes) on SDIO. The
data will be captured by the device on the rising edges
of SCLK. After all 8 data bytes have been written, the
user raises SEN after the last falling edge of SCLK, to
end the transaction.
In SPI mode, the status byte is read by sending control
byte 0x80 or 0xA0, followed by reading a single byte on
SDIO or GPO1. The Si4730/31 will change the state of
SDIO or GPO1 after the falling edges of SCLK. Data
should be captured by the user on the rising edges of
SCLK. After the status byte has been read, the user
raises SEN after the last falling edge of SCLK to end the
transaction.
When reading a response, the user must read exactly
16 data bytes after sending the control byte. The user
must keep SEN low until all bytes transferred. After 16
bytes have been read, the user raises SEN after the last
falling edge of SCLK to end the transaction.
At the end of any SPI transaction, the user must drive
SEN high after the final falling edge of SCLK. At any
time during a transaction, if SEN is sampled high by the
device on a rising edge of SCLK, the transaction will be
aborted. When SEN is high, SCLK may toggle without
affecting the device.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
20
4.15. Firmware Upgrades
The Si4730/31 contains on-chip program RAM to
accommodate minor changes to the firmware. This
allows Silicon Labs to provide future firmware updates
to optimize the characteristics of new radio designs and
those already deployed in the field.
4.16. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
4.17. Programming with Commands
To ease development time and offer maximum
customization, the Si4730/31 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties and responses.
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control an action such
as power up the device, shut down the device, or tune
to a station. Arguments are specific to a given command
and are used to modify the command. A complete list of
commands is available in Table 12, “Si473x Command
Summary,” on page 21.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after power-up. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A complete list of
properties is available in Table 13, “Si473x Property
Summary,” on page 21.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a one-byte status update
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4730/31, see “AN385: Si4730/31
AM/FM Receiver Programming Guide.”
Preliminary Rev. 0.5
Si4730/31
5. Commands and Properties
Table 12. Si473x Command Summary
Cmd
Name
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
GET_REV
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
PATCH_DATA
FM_TUNE_FREQ
FM_SEEK_START
0x22
FM_TUNE_STATUS
0x23
FM_RSQ_STATUS
0x24
FM_RDS_STATUS
0x40
0x41
AM_TUNE_FREQ
AM_SEEK_START
0x42
AM_TUNE_STATUS
0x43
AM_RSQ_STATUS
Description
Power up device and mode selection. Modes include AM receive and FM
receive.
Returns revision information on the device.
Power down device.
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for firmware file downloads.
Reserved command used for firmware file downloads.
Selects the FM tuning frequency.
Begins searching for a valid frequency
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START
command.
Queries the status of the Received Signal Quality (RSQ) of the current channel
Returns RDS information for current channel and reads an entry from the
RDS FIFO.
Tunes to a given AM frequency.
Begins searching for a valid frequency.
Queries the status of the already issued AM_TUNE_FREQ or
AM_SEEK_START command.
Queries the status of the Received Signal Quality (RSQ) for the current
channel.
Table 13. Si473x Property Summary
Prop
Name
Description
Default
0x0001
GPO_IEN
0x0000
0x0201
RCLK_FREQ
0x0202
0x1100
RCLK_PRESCALE
FM_DEEMPHASIS
0x1105
FM_BLEND_STEREO_
THRESHOLD
0x1106
FM_BLEND_MONO_
THRESHOLD
Enables interrupt sources.
Sets frequency of reference clock in Hz. The range is 31130 to
34406 Hz, or 0 to disable the AFC. Default is 32768 Hz.
Sets the prescaler value for RCLK input.
Sets deemphasis time constant. Default is 75 us.
Sets RSSI threshold for stereo blend (Full stereo above threshold,
blend below threshold). To force stereo set this to 0. To force mono
set this to 127. Default value is 49 dBuV.
Sets RSSI threshold for mono blend (Full mono below threshold,
blend above threshold). To force stereo set this to 0. To force
mono set this to 127. Default value is 30 dBuV.
Sets the maximum freq error allowed before setting the AFC_RAIL
indicator. Default value is 30 kHz.
0x1108
0x1200
21
FM_MAX_TUNE_
ERROR
FM_RSQ_INT_
SOURCE
Configures interrupt related to Received Signal Quality metrics.
Preliminary Rev. 0.5
0x8000
0x0001
0x0002
0x0031
0x001E
0x001E
0x0000
Si4730/31
Table 13. Si473x Property Summary (Continued)
Prop
0x1201
0x1202
0x1203
0x1204
0x1207
0x1302
0x1303
0x1400
0x1401
0x1402
0x1403
0x1404
0x1500
0x1501
0x1502
0x3100
0x3102
0x3200
0x3201
0x3202
0x3203
0x3204
0x3300
0x3301
0x3302
22
Name
FM_RSQ_SNR_HI_
THRESHOLD
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
FM_SOFT_MUTE_
MAX_ATTENUATION
FM_SOFT_MUTE_
SNR_THRESHOLD
FM_SEEK_BAND_
BOTTOM
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
FM_SEEK_TUNE_
RSSI_TRESHOLD
RDS_INT_SOURCE
Description
Default
Sets high threshold for Audio SNR interrupt.
0x007F
Sets low threshold for Audio SNR interrupt.
0x0000
Sets high threshold for RSSI interrupt.
0x007F
Sets low threshold for RSSI interrupt.
0x0000
Sets the blend threshold for blend interrupt when boundary is
crossed.
Sets maximum attenuation during soft mute (dB). Set to 0 to disable soft mute. Default is 16 dB.
0x0081
0x0010
Sets SNR threshold to engage soft mute. Default is 4 dB.
0x0004
Sets the bottom of the FM band for seek. Default is 8750.
0x222E
Sets the top of the FM band for seek. Default is 10790.
0x2A26
Selects frequency spacing for FM seek.
0x000A
Sets the Audio SNR threshold for a valid FM Seek/Tune. Default
value is 3 dB.
Sets the RSSI threshold for a valid FM Seek/Tune. Default value is
20 dBuV.
Configures RDS interrupt behavior.
Sets the minimum number of RDS groups stored in the receive
RDS_INT_FIFO_COUNT
RDS FIFO required before RDS RECV is set.
RDS_CONFIG
Configures RDS setting.
Sets deemphasis time constant. Can be set to 50 us. Deemphasis
AM_DEEMPHASIS
is disabled by default.
Selects the bandwidth of the channel filter for AM reception. The
AM_CHANNEL_FILTER
choices are 6, 4, 3, or 2 (kHz). The default bandwidth is 2 kHz.
Configures interrupt related to Received Signal Quality metrics. All
AM_RSQ_INTERRUPTS
interrupts are disabled by default.
AM_RSQ_SNR_HIGH_
Sets high threshold for Audio SNR interrupt. The default is 0 dB.
THRESHOLD
AM_RSQ_SNR_LOW_
Sets low threshold for Audio SNR interrupt. The default is 0 dB.
THRESHOLD
AM_RSQ_RSSI_HIGH_
Sets high threshold for RSSI interrupt. The default is 0 dB.
THRESHOLD
AM_RSQ_RSSI_LOW_
Sets low threshold for RSSI interrupt. The default is 0 dB.
THRESHOLD
Sets the rate of attack when entering or leaving soft mute. The
AM_SOFT_MUTE_RATE
default is 274 dB/s.
Sets the AM soft mute slope. The bigger the number, the higher
AM_SOFT_MUTE_SLOPE
the max attenuation level. Default value is a slope of 2.
AM_SOFT_MUTE_MAX_ Sets maximum attenuation during soft mute (dB). Set to 0 to disATTENUATION
able soft mute. Default is 16 dB.
Preliminary Rev. 0.5
0x0003
0x0014
0x0000
0x0000
0x0000
0x0000
0x0004
0x0000
0x0000
0x0000
0x0000
0x0000
0x0040
0x0002
0x0010
Si4730/31
Table 13. Si473x Property Summary (Continued)
Prop
Name
AM_SOFT_MUTE_SNR_
THRESHOLD
AM_SEEK_BAND_
0x3400
BOTTOM
0x3401 AM_SEEK_BAND_TOP
AM_SEEK_FREQ_
0x3402
SPACING
0x3303
0x3403
AM_SEEK_SNR_
THRESHOLD
0x3404
AM_SEEK_RSSI_
THRESHOLD
0x4000
RX_VOLUME
0x4001
RX_HARD_MUTE
Description
Default
Sets SNR threshold to engage soft mute. Default is 10 dB.
0x0000
Sets the bottom of the AM band for seek. Default is 520.
0x000A
Sets the top of the AM band for seek. Default is 1710.
0x06AE
Selects frequency spacing for AM seek. Default is 10 kHz spacing. 0x000A
Sets the Audio SNR threshold for a valid AM Seek/Tune. If the
value is zero then SNR threshold is not considered when doing a
seek. Default value is 5 dB.
Sets the RSSI threshold for a valid AM Seek/Tune. If the value is
zero then RSSI threshold is not considered when doing a seek.
Default value is 25 dBuV.
Sets the output volume.
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
Preliminary Rev. 0.5
0x0005
0x0019
0x003F
0x0000
23
Si4730/31
GPO2/INT
GPO3
NC
1
GPO1
NC
NC
6. Pin Descriptions: Si4730/31-GM
20
19
18
17
16
FMI 2
15 NC
RFGND 3
14 LOUT
GND
PAD
AMI 4
13 ROUT
6
7
8
9
10
SCLK
SDIO
RCLK
VIO
12 GND
SEN
RST 5
11 VDD
Pin Number(s)
Name
1, 20
NC
No connect. Leave floating.
2
FMI
FM RF inputs. FMI should be connected to the antenna trace.
3
RFGND
4
AMI
AM RF input. AMI should be connected to the AM antenna.
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
External reference oscillator input.
10
VIO
I/O supply voltage.
11
VDD
Supply voltage. May be connected directly to battery.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
13
ROUT
Right audio line output.
14
LOUT
Left audio line output.
15, 16
NC
17
GPO3
18
19
24
Description
RF ground. Connect to ground plane on PCB.
No connect. Leave floating.
General purpose output.
GPO2/INT General purpose output or interrupt pin.
GPO1
General purpose output.
Preliminary Rev. 0.5
Si4730/31
7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4730-A10-GM
AM/FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 C
Si4731-A10-GM
AM/FM Broadcast Radio Receiver with RDS/RBDS
QFN
Pb-free
–20 to 85 C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
Preliminary Rev. 0.5
25
Si4730/31
8. Package Outline: Si4730/31 QFN
Figure 10 illustrates the package details for the Si4730/31. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 10. 20-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions
Symbol
Millimeters
Symbol
Min
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.20
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
D
D2
3.00 BSC
1.65
e
1.70
1.75
0.50 BSC
E
E2
3.00 BSC
1.65
1.70
Min
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
26
Millimeters
Preliminary Rev. 0.5
Nom
Max
2.53 BSC
Si4730/31
9. PCB Land Pattern: Si4730/31 QFN
Figure 11 illustrates the PCB land pattern details for the Si4730/31-GM. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 11. PCB Land Pattern
Preliminary Rev. 0.5
27
Si4730/31
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.71 REF
1.60
1.80
Min
Max
GE
2.10
—
W
—
0.34
—
e
0.50 BSC
X
E
2.71 REF
Y
E2
f
GD
1.60
1.80
2.53 BSC
2.10
Millimeters
0.28
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
28
Preliminary Rev. 0.5
Si4730/31
10. Additional Reference Resources
AN231: Si4700/01 Headphone and Antenna Interface
AN384: Si473x AM/FM Receiver Layout Guide
AN385: Si473x AM/FM Receiver Programming Guide
AN386: Si473x Ferrite Loop Stick Antenna Interface
AN387: Si473x Air Loop Antenna Interface
AN388: Si473x AM/FM Tuner Evaluation Board Test Procedure
AN389: Si473x EVB Quick-Start Guide
Si47xx Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to [email protected] Silicon Labs
recommends an all lower case user name.
Preliminary Rev. 0.5
29
Si4730/31
DOCUMENT CHANGE LIST
Revision 0.3 to Revision 0.5
Updated block diagram on page 1 and Figure 8 on
page 16.
Removed optional digital audio output and GPO
functionality. These features will be supported in
future firmware revisions.
Updated Table 3, “DC Characteristics,” on page 5.
Added SPI control interface timing diagrams,
Figure 6 and Figure 7.
Updated Table 8, “FM Receiver Characteristics1,2,”
on page 11.
Updated Table 9, “AM Receiver Characteristics1,” on
page 12.
Adjusted crystal frequency tolerance from +/– 200 ppm
to +/– 100 ppm.
Updated values for C5 and L2 in "3. Bill of Materials"
on page 15.
Updated “4. Functional Description” to include
appropriate commands and properties.
Updated Table 12, “Si473x Command Summary,” on
page 21.
Updated Table 13, “Si473x Property Summary,” on
page 21.
Updated "7. Ordering Guide" on page 25.
Updated "10. Additional Reference Resources" on
page 29.
Added instructions on gaining access to the secure
customer website on p.29.
30
Preliminary Rev. 0.5
Si4730/31
NOTES:
Preliminary Rev. 0.5
31
Si4730/31
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
32
Preliminary Rev. 0.5
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