AGM 0043W
SPECIFICATION
CUSTOMER
:
MODULE NO.:
AGM 0043W
APPROVED BY:
( FOR CUSTOMER USE ONLY )
PCB VERSION:
SALES BY
APPROVED BY
VERSION
DATE
0
2010.12.22
REVISED
PAGE NO.
DATA:
CHECKED BY
PREPARED BY
SUMMARY
First issue
MODLE NO:
DOC. FIRST ISSUE
RECORDS OF REVISION
VERSION
DATE
0
2010.12.22
REVISED
PAGE NO. SUMMARY
First issue
Contents
1. Module Classification Information
2. Block Diagram
3. Electrical Characteristics
4. Absolute Maximum Ratings
5. Interface Pin Function
6. DC Characteristics
7. AC Characteristics
8. Data transfer order Setting
9. Register Depiction
10. Optical Characteristics
11. Contour Drawing
12. RELIABILITY TEST
This product is composed of a TFT LCD panel, driver ICs,
FPC, Control Board and a backlight unit. The following table
described the features of
Item
AGM 0043W
Dimension
Unit
Dot Matrix
480 x RGBx 272(TFT)
dots
Module dimension
105.5x 67.2 x 6.7 (max)
mm
View area
95.04x 53.85
mm
Dot pitch
0.066(W) × 0.198(H) mm
mm
LCD type
TFT, Negative, Transmissive
View direction
6 o’clock
Backlight Type
LED,Normally White
Controller IC
SSD1963
*Expose the IC number blaze (Luminosity over than 1 cd) when using the LCM may cause IC operating
failure.
*Color tone slight changed by temperature and driving voltage.
TFT PANEL
480(R.G.B)X272
K
A
VDD
output 27.9V
/20mA
RBG 6/6/6
Backlight
circuit
,EN,CLK,DISP
TFT Controller
Control-Board
DISP ON
RES
CS
RD
WR
RS
B/L Enable
VDD
GND
8 Bits Data Bus
16 Bits Data Bus
(PANEL)
LED BACKUGHT
2.Block Diagram
3.Electrical Characteristics
Values
Item
Symbol
Unit
Min
TYP
max
Operating voltage
VDD
3.1
3.3
3.5
V
Input high voltage
VIH
0.8*VDD
-
VDD
V
Input low voltage
VIL
0
-
0.2*VDD
V
Output high voltage
VOH
VDD-0.3
VDD
V
Output low voltage
VOL
0
-
0.3
V
Current Consumption
IVCI
-
245
-
mA
Power Consumption
PLCD
-
808.5
-
mW
Remark
4.Absolute Maximum Ratings
Item
Values
Symbol
Unit
Remark
Min
max
VDD
-0.5
5.0
V
Logic input
-0.5
5.0
V
Topa
-20
70
。C
Note3,4
Storage Temperature
Tst
-30
80
。C
Note3,4
LED Reverse Voltage
Vr
-
1.2
V
Each LED Note2
LED Forward Current
IF
-
25
mA
Each LED
LED life time
--
20,000
--
--
Note5
Power Supply Voltages
Input signal voltage
Operating Temperature
Note 1: The absolute maximum rating values of this product are not allowed to be exceeded at any times.
A module should be used with any of the absolute maximum ratings exceeded, the characteristics of the
module may not be recovered, or in an extreme condition, the module may be permanently destroyed.
Note 2: VR Conditions: Zener Diode 20mA
Note 3: 90% RH Max. (Max wet temp. is 60℃)
Maximum wet-bulb temperature is at 60℃ or less. And No condensation (no drops of dew)
Note 4: In case of temperature below 0℃,the response time of liquid crystal (LC) becomes slower and the
color of panel darker than normal one.
Note 5: The “LED life time” is defined as the module brightness decrease to 50% original brightness
that the ambient temperature is 25℃ and IL =20mA. The LED lifetime could be decreased if operating
IL is lager than 20 mA.
5.Interface Pin Function
5-1 Pins Connection To Control Board
P/N
Symbol
8 B IT Function
Ground
1
GND
Power supply for Logic
2
VDD
3
B\L Enable Backlight control (H: ON L: OFF)
4
RS
Command/Data select
8080 family MPU interface : Write signal
5
WR
8080 family MPU interface: Read signal
6
RD
Data bus
7
DB0
8
DB1
9
DB2
10
DB3
11
DB4
12
DB5
13
DB6
14
DB7
Chip select
15
CS
16
RES
Reset
No
connection
17
NC
No connection
18
NC
19
DISP ON Display on
20
NC
No connection
6. DC CHARATERISTICS
Conditions:
Voltage referenced to VSS
VDDD, VDDPLL = 1.2V
VDDIO, VDDLCD = 3.3V
TA = 25°C
DC Characteristics
Symbol Parameter
PSTY
Quiescent Power
IIZ
Input leakage current
IOZ
Output leakage current
VOH
Output high voltage
VOL
Output low voltage
VIH
Input high voltage
VIL
Input low voltage
Test Condition
Min
-1
-1
0.8VDDIO
Typ
300
Max
500
1
1
0.2VDDIO
0.8VDDIO
VDDIO + 0.5
0.2VDDIO
Unit
uW
uA
uA
V
V
V
V
7. AC Characteristics
Conditions:
Voltage referenced to VSS
VDDD, VDDPLL = 1.2V
VDDIO, VDDLCD = 3.3V
TA = 25°C
CL = 50pF (Bus/CPU Interface)
CL = 0pF (LCD Panel Interface)
7.1 Clock Timing
Table 7-1:Clock Input Requirements for CLK (PLL-bypass)
Symbol
Parameter
Min
Max
FCLK
Input Clock Frequency (CLK)
110
TCLK
Input Clock period (CLK)
1/fCLK
Units
MHz
ns
Table 7-2:Clock Input Requirements for CLK
Symbol
Parameter
Min
FCLK
Input Clock Frequency (CLK)
2.5
TCLK
Input Clock period (CLK)
1/fCLK
Units
MHz
ns
Max
50
Table 7-3:Clock Input Requirements for crystal oscillator XTAL
Symbol
Parameter
Min
Max
Units
FXTAL
Input Clock Frequency
2.5
10
MHz
TXTAL
Input Clock period
1/fXTAL
ns
7.2 MCU Interface Timing
7.2.1 Parallel 6800-series Interface Timing
Table 7-4: Parallel 6800-series Interface Timing Characteristics (Use CS# as clock)
Symbol Parameter
Min
Typ
Max Unit
fMCLK System Clock Frequency*
1
110 MHz
1/
fMCLK
tMCLK System Clock Period*
ns
1.5* tMCLK
Control Pulse High Write
13
tPWCSH
ns
3.5* tMCLK
Width
Read
30
1.5* tMCLK
13
Control Pulse Low
Write (next write cycle)
9* tMCLK
80
tPWCSL Width
Write (next read cycle)
ns
9* tMCLK
80
Read
tAS
Address Setup Time
2
ns
tAH
Address Hold Time
2
ns
tDSW
Data Setup Time
4
ns
tDHW
Data Hold Time
1
ns
tPLW
Write Low Time
14
ns
tPHW
Write High Time
14
ns
tPLWR
Read Low Time
38
ns
tACC
Data Access Time
32
ns
tDHR
Output Hold time
1
ns
tR
Rise Time
0.5
ns
tF
Fall Time
0.5
ns
* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)
Figure 7-1: Parallel 6800-series Interface Timing Diagram (Use CS# as Clock)
Table 7-5: Parallel 6800-series Interface Timing Characteristics (Use E as clock)
Symbol
fMCLK
tMCLK
Parameter
Min
Typ
Max
Unit
System Clock Frequency*
1
110
MHz
1/ fMCLK
System Clock Period*
ns
13
Write (next write cycle)
1.5* tMCLK
Control Pulse Low
9* tMCLK
80
ns
Write (next read cycle)
tPWCSH
Width
9*
tMCLK
80
Read
Control Pulse High Write
13
1.5* tMCLK
tPWCSL
ns
3.5* tMCLK
Width
Read
30
tAS
Address Setup Time
2
ns
tAH
Address Hold Time
2
ns
tDSW
Data Setup Time
4
ns
tDHW
Data Hold Time
1
ns
tPLW
Write Low Time
14
ns
tPHW
Write High Time
14
ns
tPLWR
Read Low Time
38
ns
tACC
Data Access Time
32
ns
tDHR
Output Hold time
1
ns
tR
Rise Time
0.5
ns
tF
Fall Time
0.5
ns
* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)
Figure7-2: Parallel 6800-series Interface Timing Diagram (Use E as Clock)
7.2.2 Parallel 8080-series Interface Timing
Table 7-6: Parallel 8080-series Interface
Symbol
fMCLK
tMCLK
Parameter
Min
Typ
Max
Unit
System Clock Frequency*
1
110
MHz
1/ fMCLK
System Clock Period*
ns
Control Pulse High
Write
13
1.5* tMCLK
tPWCSL
ns
3.5* tMCLK
Width
Read
30
13
Write (next write cycle)
1.5* tMCLK
Control Pulse Low
9* tMCLK
80
Write (next read cycle)
tPWCSH
ns
Width
9*
tMCLK
80
Read
tAS
Address Setup Time
1
ns
tAH
Address Hold Time
2
ns
tDSW
Write Data Setup Time
4
ns
tDHW
Write Data Hold Time
1
ns
tPWLW Write Low Time
12
ns
tDHR
Read Data Hold Time
1
ns
tACC
Access Time
32
ns
tPWLR
Read Low Time
36
ns
tR
Rise Time
0.5
ns
tF
Fall Time
0.5
ns
tCS
Chip select setup time
2
ns
tCSH
Chip select hold time to read signal
3
ns
* System Clock denotes external input clock (PLL-bypass) or internal generated clock (PLL-enabled)
Figure 7-3: Parallel 8080-series Interface Timing Diagram (Write Cycle)
Figure 7-4: Parallel 8080-series Interface Timing Diagram (Read Cycle)
8. Data transfer order Setting
Pixel Data Format
Both 6800 and 8080 support 8-bit, 9-bit, 16-bit, 18-bit and 24-bit data bus. Depending on the width of the
data bus, the display data are packed into the data bus in different ways.
Table 8-1: Pixel Data Format
Cycle
D[23]
D[22]
D[21]
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
24 bits
1st
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
18 bits
16 bits
(565
format)
1st
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
1st
R5
R4
R3
R2
R1
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
1st
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
2nd
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
3rd
1st
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
1st
R5
R4
R3
R2
R1
R0
G5
G4
G3
2nd
G2
G1
G0
B5
B4
B3
B2
B1
B0
1st
R7
R6
R5
R4
R3
R2
R1
R0
2nd
G7
G6
G5
G4
G3
G2
G1
G0
3rd
B7
B6
B5
B4
B3
B2
B1
B0
Interface
16 bits
12 bits
9 bits
8 bits
2nd
9 Register Depiction
Please consult the spec of SSD1963 Version 1.2
10. OPTICAL CHARATERISTIC
105.5
98.7
95.04(AA)
5.23
6.70±0.3
2.90±0.15
66.9
19.5
11.00 P0.5*39=19.5
23.90
20.00
52.75
3.9±0.3
P1.0*21=21.00
P1.0*19=19.00
The non-specified tolerance of dimension is ±0.2mm.
CON2
CON1
42.45
36.05
40
53.85(AA)
31.15
67.20±0.2
57.5
4.225
11.Contour Drawing
12. RELIABILITY TEST
WIDE TEMPERATURE RELIABILITY TEST
N ITEM
CONDITION
O.
STANDARD
1
High Temp. Storage
80℃
240 Hrs
Appearance
without defect
2
Low Temp. Storage
-30℃
240 Hrs
Appearance
without defect
3
High Temp. & High
Humi. Storage
60 ℃
90%RH
240 Hrs
Appearance
without defect
4
High Temp.
Operating Display
70℃
240 Hrs
Appearance
without defect
5
Low Temp.
Operating Display
-20℃
240 Hrs
Appearance
without defect
6
Thermal Shock
-20 ℃, 30min. → 70℃, 30min.
Appearance
without defect
NOTE
10
cycles
Inspection Provision
1.Purpose
The AGT inspection provision provides outgoing inspection provision and its expected quality
level based on our outgoing inspection of AGT LCD produces.
2.Applicable Scope
The AGT inspection provision is applicable to the arrangement in regard to outgoing inspection and
quality assurance after outgoing.
3.Technical Terms
3-1 AGT Technical Terms
4.Outgoing Inspection
4-1 Inspection Method
MIL-STD-105E Level Ⅱ Regular inspection
4-2 Inspection Standard
AQL(%) Remarks
0.4
Faults which
substantially lower
the practicality and
the initial purpose
difficult to achieve
Cracks
Item
Opens
Shorts
Erroneous operation
Shorts
Loose
Display surface cracks
Dimensions
External from Dimensions
0.4
Inside the glass
Black spots
0.65
Polarizing plate
Dots
Scratches, foreign Matter,
air bubbles, and peeling
Pinhole, deformation
Color tone
Color unevenness
Solder appearance
Cold solder
Solder projections
Major Defect
Dots
Solder appearance
Minor Defect
Faults which appear
to pose almost no
obstacle to the
practicality,
effective use, and
operation
4-3 Inspection Provisions
*Viewing Area Definition
A : Zone Viewing Area
B : Zone Glass Plate Outline
*Inspection place to be 500 to 1000 lux illuminance uniformly without glaring.
The distance between luminous source(daylight fluorescent lamp and cool white fluorescent lamp)
and sample to be 30 cm to 50 cm.
*Test and measurement are performed under the following conditions, unless otherwise specified.
Temperature
20 ± 15℃
Humidity
65 ± 20%R.H.
Pressure
860~1060hPa(mmbar)
In case of doubtful judgment, it is performed under the following conditions.
Temperature
20 ± 2℃
Humidity
65 ±5%R.H.
Pressure
860~1060hPa(mmbar)
5.Specification for quality check
5-1-1 Electrical characteristics :
NO.
1
2
3
4
Item
Non operational
Miss operating
Contrast irregular
Response time
Criterion
Fail
Fail
Fail
Within Specified value
5-1-2 Components soldering :
Should be no defective soldering such as shorting, loose terminal cold solder, peeling of printed
circuit board pattern, improper mounting position, etc.
5-2 Inspection Standard for TFT panel
5-2-1 The environmental condition of inspection :
The environmental condition and visual inspection shall be conducted as below.
(1) Ambient temperature : 25±5℃
(2) Humidity : 25~75% RH
(3) External appearance inspection shall be conducted by using a single 20W fluorescent lamp or
equivalent illumination.
(4) Visual inspection on the operation condition for cosmetic shall be conducted at the distance
30cm or more between the LCD panels and eyes of inspector. The viewing angle shall be 90 degreeto the
front surface of display panel.
(5) Ambient Illumination : 300~500 Lux for external appearance inspection.
(6) Ambient Illumination : 100~200 Lux for light on inspection.
5-2-2 Inspection Criteria
(1) Definition of dot defect induced from the panel inside
a) The definition of dot : The size of a defective dot over 1/2 of whole dot is regarded as one defective dot
b) Bright dot : Dots appear bright and unchanged in size in which LCD panel is displaying under black
pattern.
c) Dark dot : Dots appear dark and unchanged in size in which LCD panel is displaying under pure red,
green, blue pattern.
d) 2 dot adjacent = 1 pair = 2 dots
Picture :
(2) Display Inspection
NO.
1
2
Item
Acceptable Count
N ≦ 2
Random
Bright Dot
N ≦ 0
2 dots adjacent
Dot defect
N ≦ 3
Random
Dark Dot
N ≦ 1
2 dots adjacent
N ≦ 4
Total bright and dark dot
Functional failure (V-line/ H-line/Cross line etc.)
Not allowable
It's OK if mura is slight visible through 6% ND filter. (Judged
Mura
by limit sample if it is necessary)
Newton
Orbicular of interference fringes is not allowed in the optimum
ring (touch
contrast within the active area under viewing angle.
panel)
(3) Appearance inspection
NO.
1
2
3
4
Item
Panel Crack
Broken CF Non -lead
Side of TFT
Broken Lead Side of
TFT
Broken Corner of TFT
at Lead Side
5
Burr of TFT / CF Edge
6
Foreign Black /
White/Bright Spot
7
Foreign Black /
White/Bright Line
8
Color irregular
Standards
Not allow. It is shown in Fig.1.
The broken in the area of W > 2mm is ignored, L is ignored. It
is shown in Fig.2.
FPC lead, electrical line or alignment mark can't be damaged.
It is shown in Fig.3.
FPC lead. electrical line or alignment mark can't be damaged.
It is shown in Fig.4.
The distance of burr from the edge of TFT / CF, W ≦
0.3mm. It is shown in Fig.5.
(1) 0.15 < D ≦ 0.5 mm, N≦ 4 ; (2) D ≦ 0.15mm, Ignore.
It is shown in Fig.6.
(1) 0.05<W≦ 0.1 mm, 0.3<L≦2 mm, N≦ 4.
(2) W ≦ 0.05mm and L≦ 0.3mm Ignore.
It is shown in Fig.7.
Not remarkable color irregular.
C rack
A ctiv e A rea
A ctive A rea
w
F ig 2.
Fig 1.
L
Fig 4.
w
w
L
Fig 3.
L ead A rea
BM
D ot A rea
Fig 6.
W
F ig 5.
b
BM
a
D =(a+ b)/2
L
F ig8.
R >90
w
Fig 7.
N otes
1.W :W idh
2.Lengh
3.D :A verage D iam eter
4.N :C ount
5.A ll the anhle of the
broken m ust be larger
than 90 ~.It is show n in
F ig.8.(R >90 ~)
NOTICE:
‧ SAFETY
1. If the LCD panel breaks, be careful not to get the liquid crystal to touch your skin.
2. If the liquid crystal touches your skin or clothes, please wash it off immediately by using soap and
water.
‧ HANDLING
1. Avoid static electricity which can damage the CMOS LSI.
2. Do not remove the panel or frame from the module.
3. The polarizing plate of the display is very fragile. So, please handle it very carefully.
4. Do not wipe the polarizing plate with a dry cloth, as it may easily scratch the surface of plate.
5. Do not use ketonics solvent & Aromatic solvent. Use a soft cloth soaked with a cleaning naphtha
solvent.
‧ STORAGE
1. Store the panel or module in a dark place where the temperature is 25±5℃ and the humidity is below
65% RH.
2. Do not place the module near organics solvents or corrosive gases.
3. Do not crush, shake, or jolt the module.
‧ TERMS OF WARRANT
1. Acceptance inspection period
The period is within one month after the arrival of contracted commodity at the buyer's factory site.
2. Applicable warrant period
The period is within twelve months since the date of shipping out under normal using and storage
conditions.
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