L6390 - Romstore
L6390
High-voltage high and low side driver
Features
■
High voltage rail up to 600 V
■
dV/dt immunity ± 50 V/nsec in full temperature
range
■
Driver current capability:
– 290 mA source,
– 430 mA sink
SO-16
DIP-16
■
Switching times 75/35 nsec rise/fall with
1 nF load
■
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Description
■
Integrated bootstrap diode
■
Operational amplifier for advanced current
sensing
■
Comparator for fault protections
The L6390 is a high-voltage device manufactured
with the BCD "OFF-LINE" technology. It is a
monolithic half-bridge gate driver for N-channel
Power MOSFET or IGBT.
■
Smart shut down function
■
Adjustable dead-time
■
Interlocking function
■
Compact and simplified layout
■
Bill of material reduction
■
Effective fault protection
■
Flexible, easy and fast design
The high side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
The IC embeds an operational amplifier suitable
for advanced current sensing in applications such
as field oriented motor control.
An integrated comparator is available for
protections against over-current,
over-temperature, etc.
Applications
Motor driver for home appliances, factory
automation, industrial drives. HID ballasts, power
supply units.
Table 1.
July 2008
Device summary
Order codes
Package
Packaging
L6390
DIP-16
Tube
L6390D
SO-16
Tube
L6390D013TR
SO-16
Tape and reel
Rev 3
1/22
www.st.com
22
Contents
L6390
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9.1
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Package mecanichal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/22
L6390
1
Block diagram
Block diagram
Figure 1.
Block diagram
BOOTSTRAP DRIVER
VCC
4
16
FLOATING STRUCTURE
from LVG
UV
DETECTION
UV
DETECTION
HVG
DRIVER
3
S
LEVEL
SHIFTER
HIN
15
R
HVG
LOGIC
5V
SHOOT
THROUGH
PREVENTION
LIN
BOOT
14
OUT
1
VCC
LVG
DRIVER
LVG
SD/OD
GND
2
8
11
SD
LATCH
5V
SMART
SD
COMPARATOR
10
+
CP+
+
VREF
DT
OPOUT
5
DEAD
VCC
TIME
7
OPAMP
+
9
-
OP+
OP-
6
3/22
Pin connection
2
L6390
Pin connection
Figure 2.
Table 2.
Pin connection (top view)
LIN
1
16
BOOT
SD/OD
2
15
HVG
HIN
3
14
OUT
VCC
4
13
NC
DT
5
12
NC
OP-
6
11
LVG
OPOUT
7
10
CP+
GND
8
9
OP+
Pin description
Pin n #
Pin name
Type
1
LIN
I
2
SD/OD (1)
I/O
3
HIN
I
High side driver logic input (active high)
4
VCC
P
Lower section supply voltage
5
DT
I
Dead time setting
6
OP-
I
Opamp inverting input
7
OPOUT
O
Opamp output
8
GND
P
Ground
9
OP+
I
Opamp non inverting input
10
CP+
I
Comparator input
O
Low side driver output
11
LVG
(1)
12, 13
NC
14
OUT
(1)
15
HVG
16
BOOT
Function
Low side driver logic input (active low)
Shut down logic input (active low)/open drain
(comparator output)
Not connected
P
High side (Floating) common voltage
O
High side driver output
P
Bootstrap supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows
omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/22
L6390
3
Truth table
Truth table
Table 3.
Truth table
Input
Note:
Output
SD
LIN
HIN
LVG
HVG
L
X
X
L
L
H
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
H
H
L
H
X: don't care
5/22
Electrical data
L6390
4
Electrical data
4.1
Absolute maximum ratings
Table 4.
Absolute maximum rating
Value
Symbol
Max
Supply voltage
- 0.3
21
V
Vout
Output voltage
Vboot - 21
Vboot + 0.3
V
Vboot
Bootstrap voltage
- 0.3
620
V
Vhvg
High side gate output voltage
Vout - 0.3
Vboot + 0.3
V
Vlvg
Low side gate output voltage
- 0.3
Vcc + 0.3
V
Vop+
OPAMP non-inverting input
- 0.3
Vcc + 0.3
V
Vop-
OPAMP inverting input
- 0.3
Vcc + 0.3
V
Vcp+
Comparator input voltage
- 0.3
Vcc + 0.3
V
Vi
Logic input voltage
- 0.3
15
V
Vod
Open drain voltage
- 0.3
15
V
Allowed output slew rate
50
V/ns
Ptot
Total power dissipation (TA = 25 °C)
800
mW
TJ
Junction temperature
150
°C
Tstg
Storage temperature
-50
150
°C
SO-16
DIP-16
Unit
155
100
°C/W
Thermal data
Table 5.
Symbol
Rth(JA)
6/22
Unit
Min
Vcc
dVout/dt
4.2
Parameter
Thermal data
Parameter
Thermal resistance junction to ambient
L6390
4.3
Electrical data
Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Pin
Vcc
4
VBO
(1)
Vout
16-14
14
Parameter
Test condition
Min
Max
Unit
Supply voltage
12.5
20
V
Floating supply voltage
12.4
20
V
580
V
800
kHz
125
°C
DC output voltage
fsw
Switching frequency
TJ
Junction temperature
-9
(2)
HVG, LVG load CL = 1 nF
-40
1. VBO = Vboot - Vout
2. LVG off. Vcc=12.5 V
Logic is operational if Vboot > 5 V
Refer to AN2378 for more details
7/22
Electrical characteristics
L6390
5
Electrical characteristics
5.1
AC operation
Table 7.
Symbol
ton
toff
tsd
AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Pin
Test condition
Comparator triggering to Measured applying a
high/low side driver turn- voltage step from 0 V to
off propagation delay
3.3 V to pin CP+.
MT
Delay matching, HS and
LS turn-on/off
5
MDT
tr
tf
Min
High/low side driver turn1 vs 11 on propagation delay
Vout = 0 V
3 vs 15 High/low side driver turn- Vboot = Vcc
CL = 1 nF
off propagation delay
V
i = 0 to 3.3 V
Shut down to high/low
2 vs
See Figure 3.
side driver propagation
11, 15
delay
tisd
dt
8/22
Parameter
Dead time setting range
Matching dead time
Typ
Max
Unit
125
200
ns
125
200
ns
125
200
ns
200
250
ns
40
ns
Rdt = 0, CL = 1 nF,
CDT = 100 nF
0.1
0.18
0.25
µs
Rdt = 37 kΩ, CL = 1 nF,
CDT = 100 nF
0.48
0.6
0.72
µs
Rdt = 136 kΩ, CL = 1 nF,
CDT = 100 nF
1.35
1.6
1.85
µs
Rdt = 260 kΩ, CL = 1 nF,
CDT = 100 nF
2.6
3.0
3.4
µs
Rdt = 0, CL = 1 nF,
CDT = 100 nF
60
ns
Rdt = 37 kΩ, CL = 1 nF,
CDT = 100 nF
100
ns
Rdt = 136 kΩ, CL = 1 nF,
CDT = 100 nF
240
ns
Rdt = 260 kΩ, CL = 1 nF,
CDT = 100 nF
350
ns
Rise time
CL = 1 nF
75
120
ns
Fall time
CL = 1 nF
35
70
ns
11, 15
L6390
Electrical characteristics
Figure 3.
Timing
LIN
50%
50%
tr
tf
90%
LVG
10%
10%
ton
HIN
90%
toff
50%
50%
tr
tf
90%
HVG
90%
10%
10%
ton
SD
toff
50%
50%
tr
tf
90%
90%
10%
10%
LVG/HVG
ton
toff
9/22
Electrical characteristics
L6390
5.2
DC operation
Table 8.
DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol
Pin
Parameter
Test condition
Min
Typ
Max
Unit
Vcc UV hysteresis
1200
1500
1800
mV
Vcc_thON
Vcc UV turn ON threshold
11.5
12
12.5
V
Vcc_thOFF
Vcc UV turn OFF threshold
10
10.5
11
V
Undervoltage quiescent
supply current
Vcc = 10 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
120
150
µA
Iqcc
Quiescent current
Vcc = 15 V
SD = 5 V; LIN = 5 V;
HIN = GND;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
720
1000
µA
Vref
Internal reference voltage
500
540
580
mV
VBO UV hysteresis
1200
1500
1800
mV
VBO_thON
VBO UV turn ON threshold
10.6
11.5
12.4
V
VBO_thOFF
VBO UV turn OFF threshold
9.1
10
10.9
V
VBO = 9 V
SD = 5 V; LIN and
Undervoltage VBO quiescent
HIN = 5 V;
current
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
70
110
µA
VBO = 15 V
SD = 5 V; LIN and
HIN = 5 V;
RDT = 0 Ω;
CP+=OP+=GND; OP-=5 V
150
210
µA
10
µA
Low supply voltage section
Vcc_hys
Iqccu
4
Bootstrapped supply voltage section
VBO_hys
IQBOU
16
(1)
VBO quiescent current
IQBO
High voltage leakage current Vhvg = Vout = Vboot = 600 V
ILK
Bootstrap driver on
resistance (2)
RDS(on)
LVG ON
120
Ω
Driving buffers section
Iso
Isi
10/22
11,
15
High/low side source short
circuit current
VIN = Vih (tp<10 µs)
200
290
mA
High/low side sink short
circuit current
VIN = Vil (tp<10 µs)
250
430
mA
L6390
Electrical characteristics
Table 8.
DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol
Pin
Parameter
Test condition
Min
Typ
Max
Unit
0.8
V
Logic inputs
Vil
Low logic level voltage
1, 2, 3
Vih
High logic level voltage
IHINh
HIN logic “1” input bias
current
HIN = 15 V
IHINl
HIN logic “0” input bias
current
HIN = 0 V
ILINl
LIN logic “0” input bias
current
LIN = 0 V
ILINh
LIN logic “1” input bias
current
LIN = 15 V
ISDh
SD logic “1” input bias
current
SD = 15 V
SD logic “0” input bias
current
SD = 0 V
2.25
V
175
260
µA
1
µA
20
µA
1
µA
100
µA
1
µA
3
6
1
40
2
ISDl
1. VBO = Vboot - Vout
2. RDSON is tested in the following way:
RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)]
where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
11/22
Electrical characteristics
Table 9.
Symbol
L6390
OPAMP characteristics (VCC = 15 V, TJ = +25 °C)
Pin
Parameter
Input bias current
Iib
6, 9
Test condition
Min
(1)
Typ
Max
Unit
100
200
nA
Vicm
Input common mode voltage
range
VOL
Low level output voltage
Vid = ± 1 V, RL = 10 kΩ to
VCC
75
mV
VOH
High level output voltage
Vid = ± 1 V, RL = 10 kΩ to
GND
14.7
V
0
V
7
Source,
Vid = ± 1; Vo = 0 V
16
30
mA
Sink,
Vid = ± 1; Vo = VCC
50
80
mA
Slew rate
Vi = 1 ÷ 4 V; RL = 2 kΩ;
CL = 100 pF; unity gain
2.5
3.8
V/µs
GBWP
Gain bandwidth product
Vo = 7.5 V; RL = 2 kΩ
12
MHz
Avd
Large signal voltage gain
75
85
dB
SVR
Supply voltage rejection ratio
60
70
dB
70
dB
Io
Output short circuit current
SR
Common mode rejection
ratio
CMRR
1. The direction of input current is out of the IC.
Table 10.
Sense comparator characteristics (VCC = 15 V, TJ = +25 °C)
Symbol
Pin
Iio
10
Input bias current
Vol
2
td_comp
SR
12/22
2
Parameter
Test conditions
Min
Typ
Max
Unit
VCP+ = 1 V
1
µA
Open drain low level output
voltage
Iod = - 3 mA
0.5
V
Comparator delay
SD/OD pulled to 5 V
through 100 kΩ resistor
90
130
ns
Slew rate
CL = 180 pF; Rpu = 5 kΩ
60
V/µsec
L6390
Waveforms definitions
Figure 4.
Dead time and interlocking waveforms definitions
HIN
INTE
R
LOC
KING
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
LOC
KING
LIN
INTE
R
6
Waveforms definitions
LVG
DT
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DT
DT
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DT
DT
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DT
DT
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
13/22
Smart shut down function
7
L6390
Smart shut down function
L6390 integrates a comparator committed to the fault sensing function. The comparator has
an internal voltage reference Vref connected to the inverting input, while the non-inverting
input is available on pin 10. The comparator input can be connected to an external shunt
resistor in order to implement a simple over-current detection function. The output signal of
the comparator is fed to an integrated MOSFET with the open drain output available on pin
2, shared with the SD input. When the comparator triggers, the device is set in shut down
state and both its outputs are set to low level leaving the half-bridge in tri-state.
Figure 5.
Smart shut down timing waveforms
comp
Vref
CP+
PROTECTION
HIN/LIN
HVG/LVG
SD/OD
upper
threshold
lower
threshold
1
2
open drain gate
(internal)
real disable time
Fast shut down:
the driver outputs are set in SD state
immediately after the comparator
triggering even if the SD signal
has not yet reach
the lower input threshold
TIME CONSTANTS
1
= (RON_OD // RSD)
CSD
2 = RSD
SHUT DOWN CIRCUIT
VBIAS
RSD
FROM/TO
CONTROLLER
SD/OD
CSD
14/22
RON_OD
SMART
SD
LOGIC
CSD
L6390
Smart shut down function
In common over-current protection architectures the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide a
mono-stable circuit, which implements a protection time that follows the fault condition.
Differently from the common fault detection systems, L6390 Smart shut down architecture
allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the
propagation delay between the fault detection event and the actual outputs switch-off. In fact
the time delay between the fault and the outputs turn off is no more dependent on the RC
value of the external network connected to the pin.In the Smart shut down circuitry, the fault
signal has a preferential path which directly switch off the outputs after the comparator
triggering. At the same time the internal logic turns on the open drain output and holds it on
until the SD voltage goes below the SD logic input lower threshold. The Smart shut down
system provides the possibility to increase the time constant of the external RC network
(that is the disable time after the fault event) up to very large values without increasing the
delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
15/22
Typical application diagram
8
L6390
Typical application diagram
Figure 6.
Application diagram
BOOTSTRAP DRIVER
VCC
VCC
4
16
FLOATING STRUCTURE
from LVG
UV
DETECTION
UV
DETECTION
FROM CONTROLLER
HIN
H.V.
3
S
LEVEL
SHIFTER
LIN
14
OUT
TO LOAD
1
VBIAS
GND
HVG
LOGIC
VCC
SD/OD
15
R
SHOOT
THROUGH
PREVENTION
FROM CONTROLLER
2
8
LVG
11
SD
LATCH
SMART
SD
LVG
DRIVER
5V
COMPARATOR
10
+
CP+
+
VBIAS
VREF
DT
5
DEAD
VCC
TIME
OPOUT
7
OPAMP
+
9
16/22
OP+
OP-
TO ADC
Cboot
HVG
DRIVER
5V
FROM/TO
CONTROLLER
BOOT
+
6
L6390
9
Bootstrap driver
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 7.a). In the L6390 a patented
integrated structure replaces the external diode. It is realized by a high voltage DMOS,
driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure
7.b.
An internal charge pump (Figure 7.b) provides the DMOS driving voltage.
9.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = ------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
CBOOT >>> CEXT
e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has
to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a voltage drop of 1V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value:
120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
17/22
Bootstrap driver
L6390
Equation 3
Q gate
V drop = I ch arg e R dson →V drop = ------------------ R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap
DMOS is about 1V, if the Tcharge is 5µs. In fact:
Equation 4
30nC
V drop = --------------- ⋅ 120Ω ∼0.7V
5µs
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 7.
Bootstrap driver
DBOOT
VCC
BOOT
BOOT
VCC
H.V.
H.V.
HVG
HVG
CBOOT
OUT
TO LOAD
TO LOAD
LVG
a
18/22
CBOOT
OUT
LVG
b
D99IN1067
L6390
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Figure 8.
DIP-16 mechanical data and package dimensions
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP16
Z
1.27
0.050
19/22
Package mechanical data
Figure 9.
L6390
SO-16 narrow mechanical data and package dimensions
mm
inch
DIM.
MIN.
TYP.
A
a1
b1
REF.
0.35 MIN.
A
c1
b
0.35
b1
0.19
9.8
5.8
c1
e
D
9.8
1.27
E
5.8
8.89
3.8
e3
G
F
4.60
3.8
G
4.6
0.4
M
M
S
S
0.010
0.004
0.008
0.020
1.65
0.013
45° 0.46(typ.)
10
0.25
0.064
0.018
0.007
0.010
0.386
16-LEAD SMALL OUTLINE
PACKAGE
0.394
0.019
0.244
10
0.385 0.050
0.393
6.2
0.228
0.244
1.27
0.350
Weight: not available
0.050
8.894.0
0.5
PACKAGE AND
PACKING INFORMATION
0.068
0.007
0.2
OUTLINE AND
MECHANICAL DATA
0.009
6.2 45°
0.228
(typ.)
F(1)
L
TYP. 0.018
MAX.
0.5
E
L
inch 0.063
TYP.
MAX.
MIN.
0.46
0.014
0.5
C
e
0.069
0.25
a2
MAX.
0.25 0.004
DIMENSIONS
mm1.6
0.1
C
e3
TYP.
1.75
0.19
a1
D(1)
MIN.
1.75
0.1
a2
b
MAX.
0.150
0.149
5.30 4.0 0.181
5.3
1.27
0.181
0.150
1.27
0.019
0.620.62
0.350 0.157
0.157
0.208
0.208
0.050
0.050
0.024
0.024
8° (max.)
8 ° (max.)
SO-16
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
20/22
L6390
11
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
29-Feb-2008
1
First release
09-Jul-2008
2
Updated: Cover page, Table 2 on page 4, Table 3 on page 5,
Section 4 on page 6, Section 5 on page 8, Section 9.1 on page 17
17-Jul-2008
3
Updated test condition values on Table 8 and Table 9
21/22
L6390
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