AHB-Lite Timer Datasheet

AHB-Lite Timer Datasheet
AHB-LiteTimer
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AHB-LiteTimer
Datasheet
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AHB-LiteTimer
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Introduction
TheRoaLogicAHB-LiteTimerIPisafullyparameterizedsoftIPimplementinga
user-defined number of timers and functions as specified by the RISC-V
Privileged1.9.1specification.
TheIPfeaturesanAHB-LiteSlaveinterface,withallsignalsdefinedintheAMBA
3 AHB-Lite v1.0 specifications fully supported, supporting a single AHB-Lite
based host connection. Bus address & data widths as well as the number of
timerssupportedarespecifiedviaparameters.
ThetimebaseofthetimersisderivedfromtheAHB-Litebusclock,scaleddown
byaprogrammablevalue.
The module features a single Interrupt output which is asserted whenever an
enabledtimeristriggered
Figure1:AHB-LiteTimer
Features
•
•
•
AHB-LiteInterfacewithprogrammableaddressanddatawidth
Userdefinednumberofcounters(Upto32)
ProgrammabletimebasederivedfromAHB-Litebusclock
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TableofContents
Introduction...........................................................................................................2
Features..................................................................................................................................................................2
1 GettingStarted.................................................................................................4
1.1 Deliverables..............................................................................................................................................4
1.2 Runningthetestbench.........................................................................................................................5
1.2.1 Self-checkingtestbench...................................................................................................................5
1.2.2 Makefilesetup......................................................................................................................................5
1.2.3 Makefilebackup..................................................................................................................................5
1.2.4 NoMakefile...........................................................................................................................................5
2 Specifications....................................................................................................6
2.1 FunctionalDescription.........................................................................................................................6
3 Configurations..................................................................................................7
3.1 Introduction..............................................................................................................................................7
3.1 CoreParameters.....................................................................................................................................7
3.1.1 TIMERS...................................................................................................................................................7
3.1.2 HADDR_SIZE.........................................................................................................................................7
3.1.3 HDATA_SIZE.........................................................................................................................................7
3.2 CoreRegisters..........................................................................................................................................7
3.2.1 PRESCALER...........................................................................................................................................7
3.2.2 IPENDING..............................................................................................................................................8
3.2.3 IENABLE.................................................................................................................................................8
3.2.4 TIME.........................................................................................................................................................8
3.2.5 TIMECMP[n].........................................................................................................................................9
4 Interfaces........................................................................................................10
4.1 AHB-LiteInterface...............................................................................................................................10
4.1.1 HRESETn..............................................................................................................................................10
4.1.2 HCLK......................................................................................................................................................10
4.1.3 HSEL.......................................................................................................................................................10
4.1.4 HTRANS................................................................................................................................................11
4.1.5 HADDR..................................................................................................................................................11
4.1.6 HWDATA..............................................................................................................................................11
4.1.7 HRDATA................................................................................................................................................11
4.1.8 HWRITE................................................................................................................................................11
4.1.9 HSIZE.....................................................................................................................................................11
4.1.10 HBURST..............................................................................................................................................11
4.1.11 HPROT................................................................................................................................................12
4.1.12 HREADYOUT....................................................................................................................................12
4.1.13 HREADY.............................................................................................................................................12
4.1.14 HRESP.................................................................................................................................................12
4.2 TimerInterface.....................................................................................................................................13
4.2.1 TIMER_INTERRUPT.........................................................................................................................13
5 Resources.......................................................................................................14
6 RevisionHistory..............................................................................................15
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1 GettingStarted
1.1 Deliverables
All IP is delivered as a zipped tarball, which can be unzipped with all common
compressiontools(likeunzip,winrar,tar,…).
Thetarballcontainsadirectorystructureasoutlinedbelow.
doc
rtl
verilog
sim
rtlsim
bin
run
bench
verilog
Figure1-1:IPDirectoryStructure
The doc directory contains relevant documents like user guides, application
notes,anddatasheets.
The rtl directory contains the actual IP design files. Depending on the license
agreement the AHB-Lite Timer is delivered as either encrypted Verilog-HDL or
asplainSystemVerilogsourcefiles.Encryptedfileshavetheextension“.enc.sv”,
plainsourcefileshavetheextension“.sv”.Thefilesareencryptionaccordingto
the IEEE-P1735 encryption standard. Encryption keys for Mentor Graphics
(Modelsim, Questasim, Precision), Synplicity (Synplify, Synplify-Pro), and Aldec
(Active-HDL, Riviera-Pro) are provided. As such there should be no issue
targetinganyexistingFPGAtechnology.
If any other synthesis or analysis tool is used then a plain source RTL delivery
may be needed. A separate license agreement and NDA is required for such a
delivery.
Thebenchdirectorycontainsthe(encrypted)sourcefilesforthetestbench.
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Thesimdirectorycontainsthefiles/structuretorunthesimulations.Section1.2
‘Runningthetestbench’providesforinstructionsonhowtousethemakefile.
1.2 Runningthetestbench
TheAHB-LiteTimerIPcomeswithadedicatedtestbenchthattestsallfeaturesof
the design and finally runs a full random test. The testbench is started from a
MakefilethatisprovidedwiththeIP.
The Makefile is located in the <install_dir>/sim/rtlsim/run directory. The
Makefile supports most commonly used simulators; Modelsim/Questasim,
Cadencencsim,AldecRiviera,andSynopsysVCS.
To start the simulation, enter the <install_dir>/sim/rtlsim/run directory and
type: make <simulator>. Where simulator is any of: msim (for
modelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec RivieraPro), or vcs (for Synopsys VCS). For example type make msim to start the
testbenchinModelsim/Questasim.
1.2.1 Self-checkingtestbench
The testbenches is a self-checking testbench intended to be executed from the
command line. There is no need for a GUI or a waveform viewer. Once the
testbenchcompletesitdisplaysasummaryandclosesthesimulator.
1.2.2 Makefilesetup
The simulator is executed in its associated directory. Inside this directory is
anotherMakefilethatcontainssimulatorspecificcommandstostartandexecute
the simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correct
directoryandcallsthesimulatorspecificMakefile.
For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msim
directory. Typing make msim loads the main Makefile, which then enters the
msimsub-directoryandcallsitsMakefile.ThisMakefilecontainscommandsto
compile the RTL and testbench sources with Modelsim, start the Modelsim
simulator,andrunthesimulation.
1.2.3 Makefilebackup
The <install_dir>/sim/rtlsim/bin directory contains backups of the original
Makefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletely
cleantherundirectory.Usethebackupstorestoretheoriginalsetup.
1.2.4 NoMakefile
For users unfamiliar with Makefiles or those on systems that do not natively
support make (e.g. Windows) a run.do file is provided that can be used with
Modelsim/QuestasimandRiviera-Pro.
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2 Specifications
2.1 FunctionalDescription
TheAHB-LiteTimerIPisafullyparameterisedTimer-tickcore,featuringasingle
AHB-LiteSlaveinterfaceandasinglemultiplexedInterruptoutputsignal.
TheTimerIPisintendedtogenerateCPUinterruptsatregulartimeintervals,for
timedeventssuchastimekeeping,task/contextswitches,andsleep().
The number of timers and Address & Data width of the AHB-Lite interface are
specifiedviaparametersdefinedatcompiletime.
Thetimebaseofthetimersiscommontoalltimersanddefinedatruntimeby
writingtothePRESCALERregister.Individualtimeralarmsmaythensetviathe
TIMECMP[n] registers. All timers are permanently enabled however a separate
IENABLEregisterallowsanytriggeredcounteroutputtobemasked.
The user may determine both the status of the TIMERS including which timer
hasgeneratedaninterruptviaareadoperationtotheAHB-Liteinterface.
Slave Interface
Master Interface
Figure2-1:AHB-LiteTimerSystemDiagram
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3 Configurations
3.1 Introduction
The size and implementation style of the timer module is defined via HDL
parametersasspecifiedbelow.
3.1 CoreParameters
Parameter
TIMERS
HADDR_SIZE
HDATA_SIZE
Type
Integer
Integer
Integer
Default
3
32
32
Description
NumberofTimers
WidthofAHB-LiteAddressBus
WidthofAHB-LiteDataBuses
Table3-1:CoreParameters
3.1.1 TIMERS
TheparameterTIMERSdefinesthenumberoftimerssupportedandtherebythe
number of TIMECMP registers implemented by the core. Values between 1 and
32aresupported,withthedefaultdefinedas‘3’.
3.1.2 HADDR_SIZE
The HADDR_SIZE parameter specifies the address bus size to connect to the
AHB-Litebasedhost.
3.1.3 HDATA_SIZE
TheHDATA_SIZEparameterspecifiesthedatabussizetoconnecttotheAHBLitebasedhost.Themaximumsizesupportedis64bits.
3.2 CoreRegisters
Register
Address
Size
Access
PRESCALER
Base+0x00
32bits Read/Write
IPENDING
Base+0x08
32bits ReadOnly
IENABLE
Base+0x0C
32bits Read/Write
TIME
Base+0x10
64bits Read/Write
TIMECMP[n] Base+0x18+8n 64bits Read/Write
Note:‘n’representsanintegerfor0toTIMERS-1.
Function
Timebase
InterruptPending
InterruptEnable
TimerRegister
CompareValue
3.2.1 PRESCALER
The Timer module operates synchronously with the AHB-Lite bus clock input
HCLK. A 32 bit PRESCALER register enables the time base for the timers to be
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less than that of HCLK by dividing this clock frequency by the value of
PRESCALER + 1.
Forexample:IfPRESCALER=3,thetimerwillincrementeveryPRESCALE+1=4
cyclesofHCLK,settingthetimebasetoHCLK/4Hz.
The default value of PRESCALER=0, thereby setting the timer clock frequency
equaltothebus(HCLK)frequency.TheTIMEcounterstartsincrementingonce
theregisterPRESCALERiswrittentoforthefirsttime(Seesection3.2.4).
Note: The value of PRESCALER value can only be defined once after the
peripheralisreleasedfromreset.
3.2.2 IPENDING
IPENDING is a 32-bit read-only register that indicates if a timer interrupt is
pending.
EachbitoftheIPENDINGregistercorrespondstoonetimerwiththepositionof
each bit indicating the associated timer. E.g. bit zero indicates the interrupt
status of Timer[0]. IPENDING bits associated with unimplemented timers are
tiedlow(‘0’)
AninterruptpendingbitissetwhenthevalueofTIMECMP[n]equalsthevalue
of TIME. It is cleared by a write to the associated TIMECMP[n] register, as
specifiedintheRISC-Vprivilegedspec1.9.1.
3.2.3 IENABLE
IENABLE is a 32-bit Read/Write register, where each bit of the register is a
dedicated 'Interrupt Enable' bit for each time. The bit position indicates the
associatedtimer.E.g.InterruptEnableforTimer[0]islocatedatbitposition0.
OnlyTIMERSbitsareimplementedwiththeremainingMSBsalwaysreadas'0'.
AwritetotheunusedMSBshasnoeffect.
An interrupt is generated when a bit of IPENDING is set and its associated
IENABLEbitisalsoset.Thisallowsthecoretobeusedin(1)purePOLLmode,
wheretheCPUpollsthestatusofthebitstodetermineifatimereventhappened,
(2)pureinterruptdrivenmode,whereeachtimercangenerateaninterrupt,or
(3)acombinationoftheabove.
3.2.4 TIME
The TIME register is a common 64-bit high-resolution time-keeping counter
usedbyalltimers.ItisthebasisfortheRDCYCLEinstructionasspecifiedinthe
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RISC-Vprivilegedspec1.9.1andmaybewrittentoalsoinaccordancewiththe
RISC-Vspecification.
The time base for the TIME register is derived from the AHB-Lite bus clock
HCLK,asdescribedinsection3.2.1,andisdefinedas:
FreqTIME = FreqHCLK / (PRESCALER+1)
ThecounterstartsincrementingoncetheregisterPRESCALERiswrittentofor
thefirsttime.
3.2.5 TIMECMP[n]
Foreachtimer(asdefinedbytheparameterTIMER)thereisadedicated64bit
TimeCompareregisterwhichdefineswhentheIPENDINGbitsareasserted
These registers are denoted as TIMECMP[n], where ‘n’ is an index from 0 to
TIMERS-1,andarelocatedconsecutivelyintheaddressspaceaccordingtothe
formula:
Base Address of TIMECMP[n] = 0x18 + 8n
For example, TIMECMP[0] is located at address 0x18, TIMECMP[1] at 0x20,
TIMECMP[1]at0x28etc.
TheIPENDINGbitassociatedwiththeTIMECMPregisterissetwhenthe
TIMECMP[n]valueequalsthevalueofTIME.
IPENDING[n] = (TIMECMP[n] == TIME)
WritingtheTIMECMP[n]registerclearsbit‘n’oftheIPENDINGregister.
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4 Interfaces
4.1 AHB-LiteInterface
TheAHB-LiteinterfaceisaregularAHB-Liteslaveport.Allsignalsaresupported.
SeetheAMBA3AHB-LiteSpecificationforacompletedescriptionofthesignals.
Port
HRESETn
HCLK
HSEL
HTRANS
HADDR
HWDATA
HRDATA
HWRITE
HSIZE
HBURST
HPROT
HREADYOUT
HREADY
HRESP
Size
1
1
1
2
HADDR_SIZE
HDATA_SIZE
HDATA_SIZE
1
3
3
4
1
1
1
Direction
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Input
Output
Input
Output
Description
Asynchronousactivelowreset
ClockInput
BusSelect
TransferType
AddressBus
WriteDataBus
ReadDataBus
WriteSelect
TransferSize
TransferBurstSize
TransferProtectionLevel
TransferReadyOutput
TransferReadyInput
TransferResponse
Table4-1:AHB-LiteInterfacePorts
4.1.1 HRESETn
WhentheactivelowasynchronousHRESETninputisasserted(‘0’),theinterface
isputintoitsinitialresetstate.
4.1.2 HCLK
HCLKistheinterfacesystemclock.AllinternallogicfortheAMB3-Liteinterface
operatesattherisingedgeofthissystemclockandAHBbustimingsarerelated
totherisingedgeofHCLK.
4.1.3 HSEL
The AHB-Lite interface only responds to other signals on its bus – with the
exception of the global asynchronous reset signal HRESETn – when HSEL is
asserted(‘1’).WhenHSELisnegated(‘0’)theinterfaceconsidersthebusIDLE. ©2017RoaLogic,Allrightsreserved
AHB-LiteTimer
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4.1.4 HTRANS
HTRANSindicatesthetypeofthecurrenttransfer.
HTRANS
00
01
10
11
Type
IDLE
BUSY
Description
Notransferrequired
Connectedmasterisnotreadytoacceptdata,but
intentstocontinuethecurrentburst.
NONSEQ Firsttransferofaburstorasingletransfer
SEQ
Remainingtransfersofaburst
Table4-2:AHB-LiteTransferType(HTRANS)
4.1.5 HADDR
HADDRistheaddressbus.ItssizeisdeterminedbytheHADDR_SIZEparameter
andisdriventotheconnectedperipheral.
4.1.6 HWDATA
HWDATA is the write data bus. Its size is determined by the HDATA_SIZE
parameterandisdriventotheconnectedperipheral.
4.1.7 HRDATA
HRDATAisthereaddatabus.ItssizeisdeterminedbyHDATA_SIZEparameter
andissourcedbytheAPB4peripheral.
4.1.8 HWRITE
HWRITE is the read/write signal. HWRITE asserted (‘1’) indicates a write
transfer.
4.1.9 HSIZE
HSIZEindicatesthesizeofthecurrenttransfer.
HSIZE
000
001
010
011
100
101
110
111
Size
8bit
16bit
32bit
64bits
128bit
256bit
512bit
1024bit
Description
Byte
HalfWord
Word
DoubleWord
Table4-3:TransferSizeValues(HSIZE)
4.1.10 HBURST
HBURSTindicatesthetransactionbursttype–asingletransferorpartofaburst.
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AHB-LiteTimer
HBURST
000
001
010
011
100
101
110
111
12
Type
SINGLE
INCR
WRAP4
INCR4
WRAP8
INCR8
WRAP16
INCR16
Description
Singleaccess
Continuousincrementalburst
4-beatwrappingburst
4-beatincrementingburst
8-beatwrappingburst
8-beatincrementingburst
16-beatwrappingburst
16-beatincrementingburst
Table4-4:AHB-LiteBurstTypes(HBURST)
4.1.11 HPROT
TheHPROTsignalsprovideadditionalinformationaboutthebustransferandare
intendedtoimplementalevelofprotection.
Bit#
3
2
1
0
Value
1
0
1
0
1
0
1
0
Description
Cacheableregionaddressed
Non-cacheableregionaddressed
Bufferable
Non-bufferable
PrivilegedAccess
UserAccess
DataAccess
Opcodefetch
Table4-5:AHB-LiteTransactionProtectionSignals(HPROT)
4.1.12 HREADYOUT
HREADYOUTindicatesthatthecurrenttransferhasfinished.Note,fortheAHBLiteTimerthissignalisconstantlyassertedasthecoreisalwaysreadyfordata
access.
4.1.13 HREADY
HREADYindicateswhetherornottheaddressedperipheralisreadytotransfer
data. When HREADY is negated (‘0’) the peripheral is not ready, forcing wait
states. When HREADY is asserted (‘1’) the peripheral is ready and the transfer
completed.
4.1.14 HRESP
HRESP is the instruction transfer response and indicates OKAY (‘0’) or ERROR
(‘1’).
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4.2 TimerInterface
4.2.1 TIMER_INTERRUPT
TIMER_INTERRUPT is a single output signal that is asserted the following
conditionsarebothmet:
1. AnybitoftheIPENDINGregisterisasserted
2. ThecorrespondingbitoftheIENABLEregisterisalsoasserted.
Thismayalsobewrittenas:
TIMER_INTERRUPT <= IPENDING & IENABLE
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5 Resources
Belowaresomeexampleimplementationsforvariousplatforms.
All implementations are push button, no effort has been undertaken to reduce
areaorimproveperformance.
Platform
DFF
Logic
Cells
Memory
Performance(MHz)
Table5-1:ResourceUtilizationExamples
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6 RevisionHistory
Date
Rev.
1.0
Comments
Table6-1:RevisionHistory
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