SN74HCU7204 - Texas Instruments

SN74HCU7204 - Texas Instruments
SN74HCU7204
DUAL INVERTERS
www.ti.com
SCLS700 – MAY 2006
FEATURES
•
•
•
•
•
•
•
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive up to 10 LSTTL Loads
Low Power Consumption, 20-µA Max ICC
Typical tpd = 7 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Unbuffered Outputs
PS OR PW PACKAGE
(TOP VIEW)
NC
1
8
VCC
1A
2
7
2A
1Y
3
6
2Y
GND
4
5
NC
DESCRIPTION/ORDERING INFORMATION
The SN74HCU7204 contains two independent unbuffered inverters. The device performs the Boolean function
Y = A in positive logic.
ORDERING INFORMATION
PACKAGE (1)
TA
SOP – PS
–40°C to 85°C
TSSOP – PW
(1)
ORDERABLE PART NUMBER
SN74HCU7204PS
Reel of 2000
SN74HCU7204PSR
Tube of 90
SN74HCU7204PW
Reel of 2000
SN74HCU7204PWR
Reel of 250
SN74HCU7204PWT
TOP-SIDE MARKING
HU7204
HU7204
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN74HCU7204
DUAL INVERTERS
www.ti.com
SCLS700 – MAY 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage range
IIK
Input clamp current (2)
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
PS package
TBD
PW package
TBD
–65
V
°C/W
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
MIN NOM MAX
VCC
Supply voltage
VIH
High-level input voltage
VIL
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
tt
TA
(1)
2
Low-level input voltage
Transition time
2
VCC = 2 V
1.7
VCC = 4.5 V
3.6
VCC = 6 V
4.8
5
0.3
VCC = 4.5 V
0.8
VCC = 6 V
1.1
0
0
V
VCC
V
mA
–5.2
VCC = 4.5 V
4
VCC = 6 V
mA
5.2
VCC = 2 V
0
1000
VCC = 4.5 V
0
500
VCC = 6 V
0
400
–40
85
Operating free-air temperature
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
V
VCC
–4
VCC = 6 V
V
V
VCC = 2 V
VCC = 4.5 V
UNIT
6
ns
°C
SN74HCU7204
DUAL INVERTERS
www.ti.com
SCLS700 – MAY 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
2V
IOH = –20 µA
VOH
IOH = –4 mA
IOH = –5.2 mA
VOL
ICC
VI = VCC or 0,
4
4
6V
5.5
5.5
4.5 V
3.86
3.76
6V
5.36
V
5.26
0.2
IOL = 20 µA
4.5 V
0.5
0.5
6V
0.5
0.5
IOL = 4 mA
4.5 V
0.32
0.37
IO = 0
V
6V
0.32
0.37
6V
±100
±1000
nA
2
20
µA
10
10
pF
6V
Ci
UNIT
1.8
0.2
IOL = 5.2 mA
VI = VCC or 0
MAX
2V
VI = VCC or GND
II
1.8
4.5 V
VI = VCC or GND
MIN
TYP MAX
2 V to 6 V
3
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
40
80
100
tpd
A
Y
4.5 V
8
16
20
6V
7
14
17
2V
38
75
95
4.5 V
8
15
19
6V
6
13
16
tr/tf
Y
MIN
TYP MAX
MIN
MAX
UNIT
ns
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per inverter
No load
Submit Documentation Feedback
TYP
20
UNIT
pF
3
SN74HCU7204
DUAL INVERTERS
www.ti.com
SCLS700 – MAY 2006
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
CL = 50 pF
(see Note A)
VCC
50%
50%
0V
tPLH
In-Phase
Output
LOAD CIRCUIT
tPHL
90%
50%
10%
90%
tr
tPHL
Input
50%
10%
90%
90%
tr
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
tPLH
50%
10%
tf
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74HCU7204PW
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TSSOP
PW
8
150
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
HU7204
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2015
Addendum-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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