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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
LMV98x-N Small, Low-Power, 1.8-V RRIO Operational Amplifiers With Shutdown
1 Features
1
• Ensured 1.8-V, 2.7-V, and 5-V Specifications
• Output Swing:
– 600-Ω Load: 80-mV from Rail
– 2-kΩ Load: 30-mV from Rail
• V
CM
200 mV Beyond Rails
• Supply Current (Per Channel): 100 µA
• Gain Bandwidth Product: 1.4 MHz
• Maximum V
OS
: 4 mV
• Gain with 600-Ω Load: 101 dB
• Ultra-Small Package: DSBGA 1.0 mm × 1.5 mm
• Turnon Time from Shutdown: 19 µs
• Independent Shutdown on Dual
• Temperature Range: −40°C to 125°C
2 Applications
• Industrial and Automotive
• Consumer Communication
• Fitness Trackers
• Wearables
• Mobile Phones
• Portable Audio
• Portable and Battery-Powered Electronic
Equipment
• Supply Current Monitoring
• Battery Monitoring
3 Description
LMV98x-N are low-voltage, low-power operational amplifiers. LMV98x-N operate from 1.8-V to 5-V supply voltages and have rail-to-rail input and output.
LMV98x-N input common mode voltage extends
200mV beyond the supplies which enables user enhanced functionality beyond the supply voltage range. The output can swing rail-to-rail unloaded and within 105 mV from the rail with 600-Ω load at 1.8-V supply. LMV98x-N are optimized to work at 1.8 V, which makes them ideal for portable two-cell battery powered systems and single cell Li-Ion systems.
LMV98x-N offer a shutdown pin that can be used to disable the device and reduce the supply current. The device is in shutdown when the SHDN pin is low. The output is high impedance in shutdown.
LMV98x-N exhibit excellent speed-power ratio, achieving 1.4-MHz gain bandwidth product at 1.8-V supply voltage with low supply current. LMV98x-N are capable of driving a 600-Ω load and up to 1000-pF capacitive load with minimal ringing. LMV98x-N have a high DC gain of 101 dB, making them suitable for low frequency applications.
PART NUMBER
PACKAGE
DSBGA (6)
BODY SIZE (NOM)
1.50 mm × 1.30 mm
LMV981-N
LMV982-N
SC70 (6)
SOT-23 (6)
VSSOP (10)
2.00 mm × 1.25 mm
2.90 mm × 1.60 mm
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application
V
+
R
1
2 NŸ
+
Simplified Schematic
-
R
SENSE
0.2 Ÿ
I
CHARGE
Load
R
2
2 NŸ
±
+
R
3
10 NŸ
Q1
2N3906
V
OUT
V
OUT
R
R
1 u
3 u I
CHARGE
: u I
CHARGE
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016 www.ti.com
1 Features ..................................................................
2 Applications ...........................................................
3 Description .............................................................
4 Revision History.....................................................
5 Description (continued).........................................
6 Pin Configuration and Functions .........................
7 Specifications.........................................................
7.1
Absolute Maximum Ratings ......................................
7.2
ESD Ratings..............................................................
7.3
Recommended Operating Conditions .......................
7.4
Thermal Information ..................................................
7.5
Electrical Characteristics – DC, 1.8 V.......................
7.6
Electrical Characteristics – AC, 1.8 V .......................
7.7
Electrical Characteristics – DC, 2.7 V.......................
7.8
Electrical Characteristics – AC, 2.7 V .......................
7.9
Electrical Characteristics – DC, 5 V........................
7.10
Electrical Characteristics – AC, 5 V ......................
7.11
Typical Characteristics ..........................................
8 Detailed Description ............................................
8.1
Overview .................................................................
Table of Contents
8.2
Functional Block Diagram .......................................
8.3
Feature Description.................................................
8.4
Device Functional Modes........................................
9 Application and Implementation ........................
9.1
Application Information............................................
9.2
Typical Applications ...............................................
9.3
Do's and Don'ts ......................................................
10 Power Supply Recommendations .....................
11 Layout...................................................................
11.1
Layout Guidelines .................................................
11.2
Layout Example ....................................................
12 Device and Documentation Support .................
12.1
Documentation Support ........................................
12.2
Related Links ........................................................
12.3
Receiving Notification of Documentation Updates
12.4
Community Resources..........................................
12.5
Trademarks ...........................................................
12.6
Electrostatic Discharge Caution ............................
12.7
Glossary ................................................................
13 Mechanical, Packaging, and Orderable
Information ...........................................................
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision L (March 2013) to Revision M Page
• Added Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ......................................................................................................................
• Changed R
θJA values for LMV981-N: YZR (DSBGA) From: 286 To: 138.2 ...........................................................................
• Changed R
θJA values for LMV981-N: DCK (SC70) From: 286 To: 229.1...............................................................................
• Changed R
θJA values for LMV981-N: DBV (SOT-23) From: 286 To: 209.9 ...........................................................................
• Changed R
θJA values for LMV982-N: DGS (VSSOP) From: 286 To: 182.8 ...........................................................................
Changes from Revision K (March 2013) to Revision L Page
• Changed layout of National Semiconductor Data Sheet to TI format ....................................................................................
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
5 Description (continued)
LMV981-N is offered in space-saving, 6-pin DSBGA, SC70, and SOT-23 packages. The 6-pin DSBGA package has only a 1.006 mm × 1.514 mm × 0.945 mm footprint. LMV982-N is offered in a space-saving, 10-pin VSSOP package. These small packages are ideal solutions for area constrained PCBs and portable electronics such as cellular phones and PDAs.
6 Pin Configuration and Functions
YZR Package
6-Pin DSBGA
Top View
V+ A1 A2 OUT
SHDN B1 B2 V-
DCK or DBV Package
6-Pin SC70 or SOT-23
Top View
+IN 1
V2
-IN 3
+
6 V+
5 SHDN
4 OUT
+IN C1 C2 -IN
NAME
+IN
–IN
OUT
SHDN
V+
V–
PIN
DSBGA
C1
C2
A2
B1
A1
B2
SC70, SOT-23
1
3
4
5
6
2
(1) I = Input, O = Output, P = Power
I
P
P
I
I
O
Pin Functions: LMV981-N
TYPE
(1)
DESCRIPTION
Noninverting input
Inverting input
Output
Shutdown input
Positive (highest) power supply
Negative (lowest) power supply
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
OUT A
-IN A
+IN A
V-
3
4
1
2
SHDN A 5
+
DGS Package
10-Pin VSSOP
Top View
+
10 V+
9 OUT B
8 -IN B
7 +IN B
6 SHDN B
Pin Functions: LMV982-N
PIN
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
SHDN A
SHDN B
V+
V–
VSSOP
3
7
2
8
1
9
5
6
10
4
(1) I = Input, O = Output, P = Power
TYPE
(1)
I
I
O
I
I
O
I
I
P
P
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
Output, channel B
Shutdown input, channel A
Shutdown input, channel B
Positive (highest) power supply
Negative (lowest) power supply
DESCRIPTION www.ti.com
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7 Specifications
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
Supply voltage (V
+
– V
−
)
Differential input voltage
Voltage at input/output pins
Junction temperature
(3)
Storage temperature, T stg
MIN MAX
5.5
±Supply voltage
V
+
+ 0.3
V
–
- 0.3
–65
150
150
UNIT
V
V
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) For soldering specifications, see TI application report, Absolute Maximum Ratings for Soldering (SNOA549).
(3) The maximum power dissipation is a function of T
J(MAX) temperature is P
D
= (T
J(MAX)
–T
A
)/R
θJA
, R
θJA
, and T
A
. The maximum allowable power dissipation at any ambient
. All numbers apply for packages soldered directly into a PCB.
7.2 ESD Ratings
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Machine model
(2)
VALUE
±2000
±200
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
UNIT
V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage
Temperature
MIN
1.8
–40
MAX
5
125
UNIT
V
°C
7.4 Thermal Information
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
THERMAL METRIC
(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
YZR
(DSBGA)
6 PINS
138.2
1.2
23.4
5
23.2
LMV981-N
DCK
(SC70)
6 PINS
229.1
116.1
53.3
8.8
52.7
DBV
(SOT-23)
6 PINS
209.9
181.2
53.2
55.5
52.6
LMV982-N
DGS
(VSSOP)
10 PINS
182.8
73.1
103.3
12.8
101.9
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016 www.ti.com
7.5 Electrical Characteristics – DC, 1.8 V
T
J
= 25°C, V + = 1.8 V, V – = 0 V, V
CM
PARAMETER
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted) (1)
TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
V
OS
Input offset voltage
LMV981-N (single)
LMV982-N (dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
1
1
4
6
5.5
7.5
TCV
OS
Input offset voltage average drift
5.5
I
B
I
OS
I
S
CMRR
PSRR
CMVR
Input bias current
Input offset current
Supply current
(per channel)
Common mode rejection ratio
Power supply rejection ratio
Input common-mode voltage
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
In shutdown
LMV981-N
(single)
LMV982-N
(dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
LMV981-N, 0 V ≤ V
1.4 V ≤ V
CM
≤ 1.8 V
CM
(4)
≤ 0.6 V,
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
LMV982, 0 V ≤ V
CM
1.4 V ≤ V
CM
≤ 1.8 V
≤ 0.6 V,
(4)
T
J
= –40°C to 125°C
–0.2 V ≤ V
CM
≤ 0 V, 1.8 V ≤ V
CM
≤ 2 V
1.8 V ≤ V
+
≤ 5 V
T
J
= 25°C
T
J
= –40°C to 125°C
For CMRR range ≥ 50 dB
T
A
= 25°C
50
50
75
70
V
−
− 0.2
60
55
55
15
13
103
0.156
0.178
78
76
72
100
–0.2
2.1
205
1
2
3.5
5
35
50
25
40
185
V
+
+ 0.2
V
+
V
+
− 0.2
A
V
Large signal voltage gain
LMV981-N (single)
Large signal voltage gain
LMV982-N (dual)
R
L
V
O
= 600 Ω to 0.9 V,
= 0.2 V to 1.6 V, V
CM
= 0.5 V
R
L
V
O
= 2 kΩ to 0.9 V,
= 0.2 V to 1.6 V, V
CM
= 0.5 V
R
L
V
O
= 600 Ω to 0.9 V,
= 0.2 V to 1.6 V, V
CM
= 0.5 V
R
L
V
O
= 2 kΩ to 0.9 V,
= 0.2 V to 1.6 V, V
CM
= 0.5 V
T
A
= –40°C to 85°C
T
A
= 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
V
−
V
−
+ 0.2
77
73
80
75
75
72
78
75
101
105
90
100
UNIT mV
µV/°C nA nA
µA dB dB
V dB dB
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) For ensured temperature ranges, see input common-mode voltage range specifications.
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Electrical Characteristics – DC, 1.8 V (continued)
T
J
= 25°C, V + = 1.8 V, V – = 0 V, V
CM
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
V
O
Output swing
R
L
V
IN
= 600 Ω to 0.9 V,
= ±100 mV
R
L
V
IN
= 2 kΩ to 0.9 V,
= ±100 mV
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
1.65
1.63
1.75
1.72
0.077
1.77
0.024
0.105
0.12
0.035
0.04
I
O
Output short circuit current
(5)
Sourcing, V
O
V
IN
= 100 mV
= 0 V,
Sinking, V
O
V
IN
= 1.8 V,
= –100 mV
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
1.74
4
3.3
7
5
8
9
Ton
V
SHDN
Turnon time from shutdown
Turnon voltage to enable part
Turnoff voltage
19
1
0.55
UNIT
V mA
µs
V
(5) Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability.
7.6 Electrical Characteristics – AC, 1.8 V
T
J
= 25°C, V
+
= 1.8 V, V
–
= 0 V, V
CM
PARAMETER
= V
+
/2, V
O
= V
+
/2, R
L
> 1 MΩ, and SHDN tied to V
+
TEST CONDITIONS MIN
(2)
(unless otherwise noted)
(1)
TYP
(3)
MAX
(2)
SR Slew rate
(4)
0.35
GBW
Φ m
G m e n i n
THD
Gain-bandwidth product
Phase margin
Gain margin
Input-referred voltage noise
Input-referred current noise
Total harmonic distortion f = 10 kHz, V
CM
= 0.5 V f = 10 kHz f = 1 kHz, A
V
V
IN
= 1 V
PP
= +1, R
L
= 600 Ω,
1.4
67
7
60
0.08
0.023%
Amp-to-amp isolation
(5)
123
UNIT
V/µs
MHz
° dB nV/ √Hz pA/ √Hz dB
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Connected as voltage follower with input step from V
−
(5) Input referred, R
V
O
= V
+
).
L
= 100 kΩ connected to V
+ to V
+
. Number specified is the slower of the positive and negative slew rates.
/ 2. Each amp excited in turn with 1 kHz to produce V
O
= 3 V
PP
(for supply voltages < 3 V,
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7.7 Electrical Characteristics – DC, 2.7 V
T
J
= 25°C, V + = 2.7 V, V – = 0 V, V
CM
PARAMETER
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted) (1)
TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
V
OS
Input offset voltage
LMV981-N (single)
LMV982-N (dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
1
1
4
6
6
7.5
TCV
OS
Input offset voltage average drift
5.5
I
I
B
OS
Input bias current
Input offset current
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
I
S
Supply current
(per channel)
In shutdown
LMV981-N
(single)
LMV982-N
(dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
LMV981-N, 0 V
2.3 V ≤ V
CM
≤ V
≤ 2.7 V
CM
(4)
≤ 1.5 V,
T
J
= 25°C
CMRR
Common mode rejection ratio
LMV982, 0 V ≤ V
CM
2.3 V ≤ V
−0.2 V ≤ V
CM
≤ 0 V, 2.7 V ≤ V
CM
≤ 2.9 V
PSRR Power supply rejection ratio 1.8 V ≤ V
CM
+
≤ 2.7 V
≤ 1.5 V,
(4)
≤ 5 V, V
CM
= 0.5 V
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
CMVR
Input common mode voltage
For CMRR Range ≥ 50 dB
T
A
= 25°C
50
50
75
70
V
−
− 0.2
60
55
55
15
8
105
0.061
0.101
81
80
74
100
–0.2
3
210
1
2
3.5
5
35
50
25
40
190
V
+
+ 0.2
V
+
V
+
− 0.2
A
V
Large signal voltage gain
LMV981-N (single)
Large signal voltage gain
LMV982-N (dual)
R
L
V
O
= 600 Ω to 1.35 V,
= 0.2 V to 2.5 V
R
L
V
O
= 2 kΩ to 1.35 V,
= 0.2 V to 2.5 V
R
L
V
O
= 600 Ω to 1.35 V,
= 0.2 V to 2.5 V
R
L
V
O
= 2 kΩ to 1.35 V,
= 0.2 V to 2.5 V
T
A
= −40°C to 85°C
T
A
= 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
V
−
V
−
+ 0.2
87
86
92
91
78
75
81
78
104
110
90
100
UNIT mV mV
µV/°C nA nA
µA dB dB
V dB
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) For ensured temperature ranges, see input common mode voltage range specifications.
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Electrical Characteristics – DC, 2.7 V (continued)
T
J
= 25°C, V + = 2.7 V, V – = 0 V, V
CM
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
V
O
Output swing
R
L
V
IN
= 600 Ω to 1.35 V,
= ±100 mV
R
L
V
IN
= 2 kΩ to 1.35 V,
= ±100 mV
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
2.55
2.53
2.65
2.62
0.083
2.675
0.025
0.11
0.13
0.04
0.045
I
O
Output short circuit current
(5)
Sourcing, V
O
V
IN
= 100 mV
= 0 V,
Sinking, V
O
V
IN
= 0 V,
= –100 mV
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
2.64
20
15
18
12
30
25
Ton
V
SHDN
Turnon time from shutdown
Turnon voltage to enable part
Turnoff voltage
12.5
1.9
0.8
UNIT
V mA
µs
V
(5) Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability.
7.8 Electrical Characteristics – AC, 2.7 V
T
J
= 25°C, V + = 2.7 V, V − = 0 V, V
CM
PARAMETER
= 1 V, V
O
= 1.35 V, R
L
> 1 MΩ, and SHDN tied to V +
TEST CONDITIONS MIN
(2)
(unless otherwise noted) (1)
TYP
(3)
MAX
(2)
SR Slew rate
(4)
0.4
GBW
Φ m
G m e n i n
THD
Gain-bandwidth product
Phase margin
Gain margin
Input-referred voltage noise
Input-referred current noise
Total harmonic distortion f = 10 kHz, V
CM
= 0.5 V f = 10 kHz f = 1 kHz, A
V
V
IN
= 1 V
PP
= +1, R
L
= 600 Ω,
1.4
70
7.5
57
0.08
0.022%
UNIT
V/µs
MHz
° dB nV/ √Hz pA/ √Hz
Amp-to-amp isolation
(5)
123 dB
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Connected as voltage follower with input step from V
−
(5) Input referred, R
V
O
= V
+
).
L
= 100 kΩ connected to V
+ to V
+
. Number specified is the slower of the positive and negative slew rates.
/2. Each amp excited in turn with 1 kHz to produce V
O
= 3 V
PP
(for supply voltages < 3 V,
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7.9 Electrical Characteristics – DC, 5 V
T
J
= 25°C, V + = 5 V, V
−
PARAMETER
= 0 V, V
CM
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted) (1)
TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
1 4
V
OS
Input offset voltage
LMV981-N (single)
LMV982-N (dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
1
6
5.5
7.5
TCV
OS
Input offset voltage average drift
5.5
I
B
I
OS
I
S
CMRR
PSRR
Input bias current
Input offset current
Supply current (per channel)
Common mode rejection ratio
(4)
Power supply rejection ratio
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
In shutdown
LMV981-N
(single)
LMV982-N
(dual)
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
0 V ≤ V
CM
4.6 V ≤ V
≤ 3.8 V,
CM
≤ 5 V
T
J
= 25°C
T
J
= –40°C to 125°C
−0.2 V ≤ V
CM
≤ 0 V, 5 V ≤ V
CM
≤ 5.2 V
1.8 V
V
CM
≤ V
+
≤ 5 V,
= 0.5 V
T
J
= 25°C
T
J
= –40°C to 125°C
75
70
V
−
− 0.2
60
55
50
14
9
116
0.201
0.302
86
78
100
CMVR
A
V
Input common mode voltage
Large signal voltage gain
LMV981-N (single)
Large signal voltage gain
LMV982-N (dual)
For CMRR range ≥ 50 dB
R
L
V
O
= 600 Ω to 2.5 V,
= 0.2 V to 4.8 V
R
L
V
O
= 2 kΩ to 2.5 V,
= 0.2 V to 4.8 V
R
L
V
O
= 600 Ω to 2.5 V,
= 0.2 V to 4.8 V
R
L
V
O
= 2 kΩ to 2.5 V,
= 0.2 V to 4.8 V
T
A
= 25°C
T
A
= −40°C to 85°C
T
A
= 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
V
−
V
−
+ 0.3
88
87
94
93
81
78
85
82
4.855
–0.2
5.3
V
+
+ 0.2
V
+
V
+
− 0.3
102
113
90
100
230
1
2
3.5
5
35
50
25
40
210
R
L
V
IN
= 600 Ω to 2.5 V,
= ±100 mV
T
J
= 25°C
4.89
0.12
V
O
Output swing
T
J
= –40°C to 125°C 4.835
4.945
0.16
0.18
R
L
V
IN
= 2 kΩ to 2.5 V,
= ±100 mV
T
J
= 25°C
4.967
0.037
T
J
= –40°C to 125°C 4.935
0.065
0.075
UNIT mV
µV/°C nA nA
µA
µA dB dB
V dB dB
V
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) For ensured temperature ranges, see input common mode voltage range specifications.
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Electrical Characteristics – DC, 5 V (continued)
T
J
= 25°C, V + = 5 V, V − = 0 V, V
CM
= V + /2, V
O
= V + /2, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
I
O
Output short-circuit current
(5)
LMV981-N, sourcing,
V
O
= 0 V, V
IN
= 100 mV
Sinking, V
O
V
IN
= 5 V,
= −100 mV
T
J
= 25°C
T
J
= –40°C to 125°C
T
J
= 25°C
T
J
= –40°C to 125°C
80
68
58
45
100
65
Ton
V
SHDN
Turnon time from shutdown
Turnon voltage to enable part
Turnoff voltage
8.4
4.2
0.8
UNIT mA
µs
V
(5) Applies to both single-supply and split-supply operation. Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of 45 mA over long term may adversely affect reliability.
Φ m
G m e n i n
7.10 Electrical Characteristics – AC, 5 V
T
J
= 25°C, V + = 5 V, V − = 0 V, V
CM
= V + /2, V
O
= 2.5 V, R
L
> 1 MΩ, and SHDN tied to V + (unless otherwise noted) (1)
PARAMETER TEST CONDITIONS MIN
(2)
TYP
(3)
MAX
(2)
SR Slew rate
(4)
0.42
GBW Gain-bandwidth product 1.5
THD
Phase margin
Gain margin
Input-referred voltage noise
Input-referred current noise
Total harmonic distortion f = 10 kHz, V
CM
= 1 V f = 10 kHz f = 1 kHz, A
V
V
O
= 1 V
PP
= +1, R
L
= 600 Ω,
71
8
50
0.08
0.022%
Amp-to-amp isolation
(5)
123
UNIT
V/µs
MHz
° dB nV/ √Hz pA/ √Hz dB
(1) Electrical characteristics table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in limited self-heating of the device such that T
J
= T
A
. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where T
J
> T
A
.
beyond which the device may be permanently degraded, either mechanically or electrically.
indicated junction temperature limits
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material.
(4) Connected as voltage follower with input step from V
–
(5) Input referred, R
V
O
= V
+
).
L
= 100 kΩ connected to V
+ to V
+
. Number specified is the slower of the positive and negative slew rates.
/2. Each amp excited in turn with 1 kHz to produce V
O
= 3 V
PP
(for supply voltages < 3 V,
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7.11 Typical Characteristics
V
S
= 5 V, single supply, and T
A
= 25°C (unless otherwise noted)
160
140
120
100
80
60
125°C 85°C
25°C
-40°C
40
20
0
0 1 2 3
SUPPLY VOLTAGE (V)
4 5
Figure 1. Supply Current vs Supply Voltage (LMV981-N)
100
V
S
= 5V
10
V
S
= 2.7V
1
V
S
= 1.8V
0.1
0.01
0.001
0.01
0.1
1
OUTPUT VOLTAGE REF TO GND (V)
10
Figure 3. Sinking Current vs Output Voltage
45
R
L
= 2k :
40
NEGATIVE SWING
35
30
25
POSITIVE SWING
20
0 1 2 3 4
SUPPLY VOLTAGE (V)
5
6
Figure 5. Output Voltage Swing vs Supply Voltage www.ti.com
100
10
V
S
= 5V
V
S
= 2.7V
1
0.1
V
S
= 1.8V
0.01
0.001
0.01
0.1
1 10
OUTPUT VOLTAGE REFERENCED TO V+ (V)
Figure 2. Sourcing Current vs Output Voltage
140
R
L
= 600 :
130
NEGATIVE SWING
120
110
100
90
80
POSITIVE SWING
70
40
60
0 1 2 3 4
SUPPLY VOLTAGE (V)
C
L
= 300pF
5
90.0
6
Figure 4. Output Voltage Swing vs Supply Voltage
60
50
V
S
= 1.8V
R
L
= 600 :
C
L
= 1000pF
135.
0
112.5
PHASE
C
L
= 0pF
30 67.5
GAIN
20
45.
0
10 22.5
0
CL = 1000pF
CL = 300pF
CL = 0pF
0.
0
-10
10k 100k 1M
FREQUENCY (Hz)
10
-22.5
M
Figure 6. Gain and Phase vs Frequency
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Typical Characteristics (continued)
V
S
= 5 V, single supply, and T
A
= 25°C (unless otherwise noted)
135.0
60
50
V
S
= 5.0V
R
L
= 600 :
C
L
= 1000pF
112.5
PHASE C
L
= 300pF
40 90.0
C
L
= 0pF
30 67.5
GAIN
20 45.0
10 22.5
0
CL = 1000pF
CL = 300pF
CL = 0pF
0.0
-10
10k
10
-22.5
M
60
50
40
Figure 7. Gain and Phase vs Frequency
V
S
= 5.0V
135.
0
R
L
= 600 :
C
L
= 150pF
112.5
90.0
PHASE
30
20
10
GAIN
-40°C
100k 1M
FREQUENCY (Hz)
-40°C
25°C
85°C
67.5
45.
0
125°C
22.5
0
25°C
85°C
125°C
0.
0
-10
10k 100k 1M
FREQUENCY (Hz)
10
-22.5
M
Figure 9. Gain and Phase vs Frequency
100
V
S
= 5V
+PSRR
90
80
70
60
50
40
-PSRR
30
10 100 1k
FREQUENCY (Hz)
Figure 11. PSRR vs Frequency
10k
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
60
50
V
S
= 1.8V
R
L
= 600 :
C
L
= 150pF
135.
0
112.5
40 90.0
PHASE
30
20
GAIN
-40°C
25°C
85°C
125°C
67.5
45.
0
10
0
-40°C
25°C
85°C
22.5
0.
0
-10
10k
125°C
100k 1M
FREQUENCY (Hz)
10
-22.5
M
Figure 8. Gain and Phase vs Frequency
90
V
S
= 5V
85
80 V
S
= 2.7V
75
V
S
= 1.8V
70
65
60
10 100 1k
FREQUENCY (Hz)
Figure 10. CMRR vs Frequency
10k
1000
100
10
10 100 1k 10k
FREQUENCY (Hz)
100k
Figure 12. Input Voltage Noise vs Frequency
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Typical Characteristics (continued)
V
S
= 5 V, single supply, and T
A
= 25°C (unless otherwise noted)
1
0.1
0.01
10 100 1k 10k
FREQUENCY (Hz)
100k
Figure 13. Input Current Noise vs Frequency
10
R
L
= 600 :
A
V
= +10
1
5V
0.1
1.8V
2.7V
0.01
10 100 1k 10k
FREQUENCY (Hz)
Figure 15. THD vs Frequency
100k
V
S
= 1.8V
R
L
= 2 k :
10
R
L
= 600 :
A
V
= +1
1
1.8V
0.1
2.7V
5V
0.01
10 100 1k
FREQUENCY (Hz)
10k
Figure 14. THD vs Frequency
100k
0.5
0.45
FALLING EDGE
0.4
RISING EDGE
0.35
0.3
0.25
0
R
L
= 2k :
A
V
= +1
V
IN
= 1V
PP
1 2 3 4
SUPPLY VOLTAGE (V)
5 6
Figure 16. Slew Rate vs Supply Voltage
V
S
= 2.7V
R
L
= 2 k : www.ti.com
TIME (2.5 P s/DIV)
Figure 17. Small-Signal Noninverting Response
TIME (2.5 P s/DIV)
Figure 18. Small-Signal Noninverting Response
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Typical Characteristics (continued)
V
S
= 5 V, single supply, and T
A
= 25°C (unless otherwise noted)
V
S
= 5V
R
L
= 2 k :
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
V
IN
TIME (2.5 P s/DIV)
Figure 19. Small-Signal Noninverting Response
V
IN
V
OUT
V
S
= 1.8V
R
L
= 2k :
A
V
= +1
TIME (10 P s/div)
Figure 20. Large-Signal Noninverting Response
V
IN
V
OUT
V
S
= 2.7V
R
L
= 2 k :
A
V
= +1
TIME (10 P s/DIV)
Figure 21. Large-Signal Noninverting Response
90
80
70
5V
60
50
40
30
20
2.7V
1.8V
10
0
-40 10 60
TEMPERATURE
(°C)
110
Figure 23. Short-Circuit Current vs Temperature (Sinking)
V
OUT
V
S
= 5.0V
R
L
= 2k :
A
V
= +1
TIME (10 P s/div)
Figure 22. Large-Signal Noninverting Response
90
5V
80
70
60
50
40
30
20
10
2.7V
1.8V
0
-40 10 60
TEMPERATURE
(°C)
110
Figure 24. Short-Circuit Current vs Temperature (Sourcing)
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Typical Characteristics (continued)
V
S
= 5 V, single supply, and T
A
= 25°C (unless otherwise noted)
3
V
S
= 1.8V
2.5
2
25°C -40°C
1.5
1
0.5
0
-0.5
85°C
125°C
1.5
1
0.5
0
-0.5
3
2.5
2
25°C
85°C
-40°C
125°C
V
S
= 2.7V
-1
-0.4
0 0.4
0.8
1.2
1.6
V
CM
(V)
2 2.4
Figure 25. Offset Voltage vs Common Mode Range
3
2.5
2
-1
-0.4
0.1
0.6
1.1
1.6
2.1
2.6
3.1
V
CM
(V)
Figure 26. Offset Voltage vs Common Mode Range
V
S
= 5V
-40°C
1.5
1
0.5
0
125°C 25°C 85°C
-0.5
-1
-0.4
0.6
1.6
2.6
V
CM
(V)
3.6
4.6
5.6
Figure 27. Offset Voltage vs Common Mode Range
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8 Detailed Description
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
8.1 Overview
The LMV98x-N are low-voltage, low-power operational amplifiers (op-amp) operating from 1.8-V to 5.5-V supply voltages and have rail-to-rail input and output with shutdown. LMV98x-N input common-mode voltage extends
200 mV beyond the supplies which enables user enhanced functionality beyond the supply voltage range.
8.2 Functional Block Diagram
V
+
IN –
_
+
OUT
IN +
V
–
Copyright © 2016,
Texas Instruments Incorporated
(each amplifier)
8.3 Feature Description
The differential inputs of the amplifier consist of a noninverting input (+IN) and an inverting input (–IN). The amplifer amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp V
V
OUT
= A
OL
(IN + – IN – )
OUT is given by
where
• A
OL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10 µV per volt).
(1)
8.4 Device Functional Modes
8.4.1 Input and Output Stage
The rail-to-rail input stage of this family provides more flexibility for the designer. The LMV98x-N use a complimentary PNP and NPN input stage in which the PNP stage senses common-mode voltage near V the NPN stage senses common-mode voltage near V
+
. The transition from the PNP stage to NPN stage occurs
1 V below V
+
. Because both input stages have their own offset voltage, the offset of the amplifier becomes a function of the input common-mode voltage and has a crossover point at 1 V below V
+
.
− and
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Device Functional Modes (continued)
www.ti.com
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Simplified Schematic Diagram
This V
OS crossover point can create problems for both DC
Large input signals that include the V
OS
− and AC-coupled signals if proper care is not taken.
crossover point causes distortion in the output signal. One way to avoid such distortion is to keep the signal away from the crossover. For example, in a unity gain buffer configuration with V
S
= 5 V, a 5-V peak-to-peak signal contains input-crossover distortion while a 3-V peak-to-peak signal centered at 1.5 V does not contain input-crossover distortion as it avoids the crossover point. Another way to avoid large signal distortion is to use a gain of −1 circuit which avoids any voltage excursions at the input terminals of the amplifier. In that circuit, the common-mode DC voltage can be set at a level away from the V
OS cross-over point. For small signals, this transition in V
OS shows up as a V
CM dependent spurious signal in series with the input signal and can effectively degrade small-signal parameters such as gain and common-mode rejection ratio. To resolve this problem, the small signal must be placed such that it avoids the V
OS crossover point. In addition to the rail-to-rail performance, the output stage can provide enough output current to drive
600-Ω loads. Because of the high-current capability, take care not to exceed the 150°C maximum junction temperature specification.
8.4.2 Shutdown Mode
The LMV98x-N family has a shutdown pin. To conserve battery life in portable applications, the LMV98x-N can be disabled when the shutdown pin voltage is pulled low. When in shutdown, the output stage is in a highimpedance state and the input bias current drops to less than 1 nA.
The shutdown pin cannot be left unconnected. In case shut-down operation is not required, the shutdown pin must be connected to V+ when the LMV98x-N are used. Leaving the shutdown pin floating results in an undefined operation mode, either shutdown or active, or even oscillating between the two modes.
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Device Functional Modes (continued)
8.4.3 Input Bias Current Consideration
The LMV98x-N family has a complementary bipolar input stage. The typical input bias current (I
B
) is 15 nA. The input bias current can develop a significant offset voltage. This offset is primarily due to I
B negative feedback resistor, R
F
. For example, if I
B is 50 nA and R
F flowing through the is 100 kΩ, then an offset voltage of 5 mV develops (V
OS
= I
B x R
F input offset current (I
OS
). Using a compensation resistor (R
C
), as shown in
Figure 29 , cancels this effect. But the
) still contributes to an offset voltage in the same manner.
Figure 29. Canceling the Offset Voltage due to Input Bias Current
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
www.ti.com
9.1 Application Information
The LMV98x-N devices bring performance, economy, and ease-of-use to low-voltage, low-power systems. They provide rail-to-rail input and rail-to-rail output swings into heavy loads.
9.2 Typical Applications
9.2.1 High-Side Current-Sensing Application
V
+
+
R
1
2 NŸ
-
R
SENSE
0.2 Ÿ
I
CHARGE
Load
R
2
2 NŸ
±
+
R
3
10 NŸ
Q1
2N3906
V
OUT
V
OUT
R
R
1 u
3 u I
CHARGE
: u I
CHARGE
Copyright © 2016, Texas Instruments Incorporated
Figure 30. High-Side Current Sensing
9.2.1.1 Design Requirements
The high-side current-sensing circuit (
) is commonly used in a battery charger to monitor charging current to prevent overcharging. A sense resistor R
SENSE is connected to the battery directly. This system requires an op amp with rail-to-rail input. The LMV98x-N are ideal for this application because its common-mode input range extends up to the positive supply.
9.2.1.2 Detailed Design Procedure
As seen in
V
SENSE
, the I
CHARGE current flowing through sense resistor R
SENSE develops a voltage drop equal to
. The voltage at the negative sense point is now less than the positive sense point by an amount proportional to the V
SENSE voltage.
The low-bias currents of the LMV98x cause little voltage drop through R
2
, so the negative input of the LMV98x amplifier is at essentially the same potential as the negative sense input.
The LMV98x detects this voltage error between its inputs and servo the transistor base to conduct more current through Q1, increasing the voltage drop across R
1 input. At this point, the voltage drop across R
1 until the LMV98x inverting input matches the noninverting now matches V
SENSE
.
I
G
, a current proportional to I
CHARGE
, flows according to
.
I
G
= V
RSENSE
/ R
1
= ( R
SENSE
× I
CHARGE
) / R
1
(2)
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SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Typical Applications (continued)
I
G also flows through the gain resistor R
3 developing a voltage drop equal to
and
V
3
= I
G
× R
3
= ( V
RSENSE
/ R
1
) × R
3
= ( ( R
SENSE
× I
CHARGE
V
OUT
= (R
SENSE
× I
CHARGE
) × G
) / R
2
) × R
3 where
• G = R
3
/ R
1
The other channel of the LMV98x may be used to buffer the voltage across R3 to drive the following stages.
(3)
(4)
9.2.1.3 Application Curve
shows the results of the example current sense circuit. After 4 V, there is an error where transistor Q1 runs out of headroom and saturates, limiting the upper output swing.
5
4
3
2
1
0
0 1 2 3
I
CHARGE
(A)
4
Figure 31. Current Sense Amplifier Results
5
C001
9.2.2 Half-Wave Rectifier Applications
R
I
V
IN V
OUT
R
I
V
IN
0 t
3
LMV981
+
1
4
V
OUT
V
CC t
Figure 32. Half-Wave Rectifier With Rail-To-Ground Output Swing Referenced to Ground
V
IN
V
CC
V
CC t
V
IN
R
I
3
+
LMV981
1
4
V
OUT
V
OUT
V
CC
R
I
Figure 33. Half-Wave Rectifier With Negative-Going Output Referenced to V
CC t
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Typical Applications (continued)
9.2.2.1 Design Requirements
Because the LMV98x-N input common-mode range includes both positive and negative supply rails and the output can also swing to either supply, achieving half-wave rectifier functions in either direction is an easy task.
All that is required are two external resistors; there is no requirement for diodes or matched resistors. The halfwave rectifier can have either positive or negative going outputs, depending on the way the circuit is arranged.
9.2.2.2 Detailed Design Procedure
In
the circuit is referenced to ground, while in
the circuit is biased to the positive supply.
These configurations implement the half-wave rectifier because the LMV98x-N can not respond to one-half of the incoming waveform. It can not respond to one-half of the incoming because the amplifier cannot swing the output beyond either rail; therefore, the output disengages during this half cycle. During the other half cycle, however, the amplifier achieves a half wave that can have a peak equal to the total supply voltage. R
I enough not to load the LMV98x-N.
must be large
9.2.2.3 Application Curves
Figure 34. Output of Ground-to-Rail Circuit
Figure 35. Output of Rail-to-Ground Circuit
9.2.3 Instrumentation Amplifier With Rail-to-Rail Input and Output Application
R2
R1
R3 R4
22
Figure 36. Rail-to-Rail Instrumentation Amplifier
9.2.3.1 Design Requirements
Using three of the LMV98x-N amplifiers, an instrumentation amplifier with rail-to-rail inputs and outputs can be made as shown in
9.2.3.2 Detailed Design Procedure
In this example, amplifiers on the left side act as buffers to the differential stage. These buffers assure that the input impedance is high. They also assure that the difference amp is driven from a voltage source. This is necessary to maintain the CMRR set by the matching R
1 and R
3 must equal R
1 and R
4 equal R
2 to R
2 with R
3 to R
4
. The gain is set by the ratio of R
2
/R
1
. With both rail-to-rail input and output ranges, the input and output are only limited by the supply voltages. Remember that even with rail-to-rail outputs, the output can not swing past the supplies so the combined common-mode voltages plus the signal must not be greater that the supplies or limiting occurs.
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
Typical Applications (continued)
9.2.3.3 Application Curve
shows the results of the instrumentation amplifier with R
1 gain of 100, running on a single 5-V supply with a input of V
CM offset voltages can be seen as a shift in the offset of the curve.
and R
= V
S
3
= 1 K, and R
2 and R
4
= 100 kΩ, for a
/2. The combined effects of the individual
5
4
3
2
1
0
0 10 20 30
V
DIFF
(mV)
40 50
C001
Figure 37. Instrumentation Amplifier Output Results
9.3 Do's and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes and ADC inputs.
Do add series current limiting resistors and external schottky clamp diodes if input voltage is expected to exceed the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
10 Power Supply Recommendations
The LMV98x-N is specified for operation from 1.8 V to 5 V; many specifications apply from –40°C to 125°C.
Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in
.
CAUTION
Supply voltages larger than 5.5 V can permanently damage the device; see
.
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI recommends that 10-nF capacitors be placed as close as possible to the op amp power supply pins. For singlesupply, place a capacitor between V
+ and V
− supply leads. For dual supplies, place one capacitor between V
+ and ground, and one capacitor between V – and ground.
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LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
11 Layout
11.1 Layout Guidelines
The V
+ pin must be bypassed to ground with a low-ESR capacitor.
The optimum placement is closest to the V
+ and ground pins.
Take care to minimize the loop area formed by the bypass capacitor connection between V + and ground.
The ground pin must be connected to the PCB ground plane at the pin of the device.
The feedback components must be placed as close to the device as possible minimizing strays.
11.2 Layout Example
www.ti.com
Figure 38. SOT-23 Layout Example
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12 Device and Documentation Support
LMV981-N, LMV982-N
SNOS976M – NOVEMBER 2001 – REVISED SEPTEMBER 2016
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Absolute Maximum Ratings for Soldering (SNOA549)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS
LMV981-N
LMV982-N
PRODUCT FOLDER
Click here
Click here
Table 1. Related Links
SAMPLE & BUY
Click here
Click here
TECHNICAL
DOCUMENTS
Click here
Click here
TOOLS &
SOFTWARE
Click here
Click here
SUPPORT &
COMMUNITY
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use .
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LMV981-N LMV982-N
Submit Documentation Feedback 25
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2017
PACKAGING INFORMATION
Orderable Device
LMV981MF
LMV981MF/NOPB
LMV981MFX/NOPB
LMV981MG/NOPB
LMV981MGX/NOPB
Status
(1)
NRND
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Type Package
Drawing
SOT-23
SOT-23
DBV
DBV
Pins Package
6
6
Qty
Eco Plan
(2)
1000 TBD
1000 Green (RoHS
& no Sb/Br)
SOT-23 DBV 6
SC70
SC70
DSBGA
DCK
DCK
YZR
6
6
6
3000 Green (RoHS
& no Sb/Br)
1000 Green (RoHS
& no Sb/Br)
3000 Green (RoHS
& no Sb/Br)
250 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
Call TI
CU SN
CU SN
CU SN
CU SN
MSL Peak Temp
(3)
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
A78A
A78A
A78A
A77
A77
Device Marking
(4/5)
LMV981TL/NOPB ACTIVE SNAGCU Level-1-260C-UNLIM -40 to 125 A
H
LMV981TLX/NOPB
LMV982MM/NOPB
ACTIVE
ACTIVE
DSBGA
VSSOP
YZR
DGS
6
10
3000 Green (RoHS
& no Sb/Br)
1000 Green (RoHS
& no Sb/Br)
SNAGCU
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
A
H
A87A
LMV982MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
CU SN Level-1-260C-UNLIM
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 125 A87A
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
24-Aug-2017
*All dimensions are nominal
Device
LMV981MF
LMV981MF/NOPB
LMV981MFX/NOPB
LMV981MG/NOPB
LMV981MGX/NOPB
LMV981TL/NOPB
LMV981TLX/NOPB
LMV982MM/NOPB
LMV982MMX/NOPB
Package
Type
Package
Drawing
SOT-23 DBV
SOT-23 DBV
SOT-23 DBV
SC70
SC70
DSBGA
DSBGA
DCK
DCK
YZR
YZR
VSSOP DGS
VSSOP DGS
Pins
6
6
6
6
6
6
6
10
10
SPQ
1000
1000
3000
1000
3000
250
3000
1000
3500
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
178.0
8.4
178.0
178.0
8.4
8.4
A0
(mm)
3.2
3.2
3.2
178.0
178.0
178.0
178.0
178.0
330.0
8.4
8.4
8.4
8.4
12.4
12.4
2.25
2.25
5.3
5.3
B0
(mm)
3.2
3.2
3.2
2.45
2.45
1.4
1.4
1.4
1.12
1.63
0.76
1.12
1.63
0.76
3.4
3.4
K0
(mm)
1.2
1.2
1.4
1.4
P1
(mm)
W
(mm)
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
12.0
8.0
12.0
8.0
8.0
8.0
8.0
Pin1
Quadrant
Q3
Q3
Q3
Q3
Q3
Q1
Q1
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
24-Aug-2017
*All dimensions are nominal
Device
LMV981MF
LMV981MF/NOPB
LMV981MFX/NOPB
LMV981MG/NOPB
LMV981MGX/NOPB
LMV981TL/NOPB
LMV981TLX/NOPB
LMV982MM/NOPB
LMV982MMX/NOPB
Package Type Package Drawing Pins
SOT-23
SOT-23
SOT-23
SC70
SC70
DSBGA
DSBGA
VSSOP
VSSOP
DBV
DBV
DBV
DCK
DCK
YZR
YZR
DGS
DGS
6
10
10
6
6
6
6
6
6
SPQ
1000
1000
3000
1000
3000
250
3000
1000
3500
Length (mm) Width (mm) Height (mm)
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
367.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0006xxx
0.600±0.075
D
E
TLA06XXX (Rev C)
D: Max = 1.565 mm, Min = 1.504 mm
E: Max = 1.057 mm, Min = 0.996 mm
NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
4215044/A 12/12 www.ti.com
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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