Intel 82545 EM, GM Gigabit Ethernet Controller, 82546 EB, GB Dual Port Gigabit Ethernet Controller Design Guide
The Intel® 82545 EM and 82545 GM Gigabit Ethernet Controllers are compact components with integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. The Intel® 82546 EB and 82546 GB Dual Port Gigabit Ethernet Controllers is a single, compact component with two full integrated MAC and PHY units. Each device enables Gigabit Ethernet implementations (or dual port implementations using the 82546 EB/82546 GB) in a very small area and can be used for desktop and workstation PC network designs with critical space constraints.
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Intel® 82545EM, 82545GM, 82546EB and 82546GB Gigabit Ethernet Controllers Design Guide September 2007 318226-001 Revision 4.1 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Legal Lines and Disclaimers Intel may make changes to specifications and product descriptions at any time, without notice. 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All Rights Reserved. 2 Design Guide—82545/82546 Contents 1.0 Introduction .............................................................................................................. 7 1.1 Serializer/Deserializer (SerDes) Interface ............................................................... 7 1.2 Design Guide Scope............................................................................................. 9 1.3 References ......................................................................................................... 9 2.0 PCI/PCI-X Signal Interface ....................................................................................... 9 2.1 PCI Master and Slave Operation .......................................................................... 10 2.2 PCI Signaling Environment ................................................................................. 10 3.0 LAN Disable Guidelines ............................................................................................ 10 4.0 Design Components ................................................................................................. 11 4.1 Serial EEPROM .................................................................................................. 11 4.2 Flash Memory ................................................................................................... 11 4.3 Timing Device ................................................................................................... 12 4.4 Magnetics Module .............................................................................................. 13 4.4.1 Combination Magnetics/RJ-45 Connectors.................................................. 13 4.5 Power Supplies ................................................................................................. 14 4.5.1 Power Supply Filtering ............................................................................ 15 4.5.2 1.5 V Regulator Circuit Operation Parameters (82546EB/82545EM)............... 15 4.5.3 Power Management and Wake Up............................................................. 16 4.5.4 System Power Budget Consideration ......................................................... 17 4.6 Light Emitting Diodes (LEDs) .............................................................................. 17 4.7 Test Access Port (TAP) ....................................................................................... 17 4.8 Frequency Control Device Design Considerations ................................................... 17 4.9 Frequency Control Component Types ................................................................... 17 4.10 Quartz Crystal .................................................................................................. 17 4.11 Fixed Crystal Oscillator....................................................................................... 18 4.12 Programmable Crystal Oscillators ........................................................................ 18 4.13 Ceramic Resonator ............................................................................................ 18 5.0 Crystal Selection Parameters................................................................................... 19 5.1 Vibrational Mode ............................................................................................... 19 5.2 Nominal Frequency ............................................................................................ 19 5.3 Frequency Tolerance.......................................................................................... 19 5.4 Temperature Stability and Environmental Requirements ......................................... 20 5.5 Calibration Mode ............................................................................................... 20 5.6 Load Capacitance .............................................................................................. 21 5.7 Shunt Capacitance............................................................................................. 21 5.8 Equivalent Series Resistance............................................................................... 21 5.9 Drive Level ....................................................................................................... 21 5.10 Aging............................................................................................................... 22 5.11 Reference Crystal .............................................................................................. 22 5.11.1 Reference Crystal Selection ..................................................................... 22 5.11.2 Circuit Board ......................................................................................... 23 5.11.3 Temperature Changes............................................................................. 23 6.0 Design and Layout Considerations ........................................................................... 23 6.1 Board Stack Recommendations ........................................................................... 24 6.1.1 Termination Plane and Chassis Ground ...................................................... 25 6.2 Signal Traces .................................................................................................... 26 6.2.1 Transmission Line Layout ........................................................................ 26 6.2.2 PCI/PCI-X Bus Routing ............................................................................ 27 6.2.3 Unused Connections ............................................................................... 27 3 82545/82546—Design Guide 6.3 1000BASE-T Physical Layer Conformance Testing...................................................27 7.0 Design and Layout Checklists ...................................................................................28 8.0 Reference Design Schematic ....................................................................................35 8.1 82545EM(GM) Schematics ..................................................................................35 8.2 82546EB(GB) Schematics ...................................................................................45 A Measuring LAN Reference Frequency Using a Frequency Counter.............................55 A.1 Background ......................................................................................................55 A.2 Required Test Equipment ....................................................................................55 A.3 Indirect Probing Method......................................................................................55 A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps..............56 A.5 Direct Probing Test Method, Applicable for Most 10/100 Devices (Devices that do NOT support 1000Base-T) ........................57 A.6 Direct Frequency Measurement and Frequency Accuracy Calculation Steps ................58 Figures 1 2 3 4 5 6 7 8 82546EB / 82546GB Gigabit Ethernet Controller Block Diagram ....................................... 8 82545 and 82546 Power Sequencing...........................................................................14 Maximum Difference between Voltage Rails..................................................................15 Internal Oscillator Circuit ...........................................................................................20 Six-layer Board Stack ...............................................................................................24 1000BASE-T Termination Plane and Chassis Ground......................................................25 Indirect Probing Setup ..............................................................................................56 Direct Probing Method ...............................................................................................58 Tables 1 2 3 4 5 6 7 8 4 SerDes vs. SGMII ...................................................................................................... 8 EEPROMs for the 82545EM/82545GM and 82546EB/82546GB .........................................11 Flash Memory Devices for the 82545EM/82545GM and 82546EB/82546GB .......................12 Reference Crystal Specification Requirements...............................................................12 Magnetics Modules....................................................................................................13 Crystal Parameters ...................................................................................................19 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist ..........................28 Combined Layout Checklist ........................................................................................32 Design Guide—82545/82546 Revision History Date Revision Description 4.1 Added Section 1.1; explained how the SerDes interface is not compatible with SGMII-capable devices. June 2005 4.0 Added Specification Change, Specification Clarification, and Document Change information from the 82546EB Gigabit Ethernet Controller Specification Update Revision 2.0. Removed detailed EEPROM mapping, word, and bit descriptions. This information can now be found in the 82545EM/GM and 82546EB/GB EEPROM Map and Programming Information application note or the 8254x Family of Gigabit Ethernet Controllers Software Developer’s Manual. Added a list of recommended flash memory devices. Jan 2005 3.6 Removed references to Catalyst EEPROMs. Sep 2004 3.5 Updated reference schematics for the 82545 and 82546 devices. Mar 2004 3.4 Added information for system power budget. (Section 4.5.4, “System Power Budget Consideration”) Dec 2003 3.3 Updated schematics for the 82546 and 82545 reference designs. Sep 2003 3.2 Nonclassified release (Confidential status removed). Revised schematics. Added Crystal and power sequencing information. Sept 2007 5 82545/82546—Design Guide Note: This page intentionally left blank. 6 82545/82546—Design Guide 1.0 Introduction The Intel® 82545EM and 82545GM Gigabit Ethernet Controllers are compact components with integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. The 82546EB and 82546GB Dual Port Gigabit Ethernet Controllers is a single, compact component with two full integrated MAC and PHY units. Each device enables Gigabit Ethernet implementations (or dual port implementations using the 82546EB/82546GB) in a very small area and can be used for desktop and workstation PC network designs with critical space constraints. The Intel® 82545EM/82545GM, 82546EB/82546GB integrate Intel’s fourth generation gigabit MAC and PHY to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab, respectively). The controllers are capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition, they provide a 64-bit wide direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant interface capable of operating at frequencies up to 133 MHz. The 82546EB/82546GB also deliver dual port PCI-X solutions without added bridge latency. Furthermore, the 82545GM and 82546GB also provide a PCI 2.3 compliant interface. Their on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting through the LAN. Using the SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Format (ASF), to be implemented using the 82545EM/82545GM, 82546EB or 82546GB. In addition, onchip ASF 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82545EM and 82545GM Gigabit Ethernet Controllers and the 82546EB and 82546GB Dual Port Gigabit Ethernet Controllers all have an architecture designed to deliver high performance and PCI/PCI-X bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the controllers efficiently handle packets with minimum latency. The devices include advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The controllers are able to cache up to 64 packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 Kbyte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. By using hardware acceleration, the controller can offload tasks, such as checksum calculations and TCP segmentation, from the host processor. The 82545EM/82545GM, 82546EB/82546GB are packaged in 21 mm2 364-ball grid arrays and are footprint compatible with the Intel® 82544GC Gigabit Ethernet Controller. 1.1 Serializer/Deserializer (SerDes) Interface The 82545 and 82546 components support a SerDes-to-SerDes interface. For more information on designing an application using SerDes, consult the Designing SerDesSerDes Interface with Intel® 82546GB Gigabit Ethernet Controller Application Note. 7 Design Guide—82545/82546 SerDes and Serial Gigabit Media Independent Interface (SGMII) are both MAC-to-PHY connections that can be used to connect to optical or copper modules. Both use serial encoding to transfer data and control information as well as having a GMII interface at one end and serial pairs at the other end. SGMII uses SerDes as a basis with added functionality. SerDes is essentially 1000Base-X, as defined in the 802.3 specification. Even though both specifications are similar, the interfaces are NOT compatible (see Table 1). Table 1. SerDes vs. SGMII SerDes SGMII Link speeds supported 1000 Mb/s 10/100/1000 Mb/s Encoding 8b/10b serial 8b/10b serial Frequency of serial pair 1.25 GHz 1.25 GHz Clocks needed as part of interface? No Yes, 625 MHz clocks added MDIO interface needed? If connecting to PHY If connecting to PHY Industry standard? Yes Pseudo-standard (defined by Cisco Systems Inc.* but not proprietary) Pin count Six if using MDIO 10 if using MDIO For more information regarding SGMII, contact your Intel Field Representative and request document ENG-46158 version 1.7 from Cisco Systems Inc. Figure 1. 82546EB / 82546GB Gigabit Ethernet Controller Block Diagram MDI Interface A MDI Interface B 1000Base-T PHY Interfaces Design For Test Interface External TBI Interface LED's 10/100/1000 PHY GMII/ MDIO MII Device Funct. #0 MAC/Controller (LAN A) 10/100/1000 PHY GMII/ MDIO MII Device Funct. #1 MAC/Controller (LAN B) S/W Defined Pins EEPROM Interface Flash Interface LED's S/W Defined Pins PCI (64 bit,33/66MHz); PCI-X (133MHz) 8 SM Bus Interface 82545/82546—Design Guide 1.2 Design Guide Scope The scope of this application note contains Ethernet design guidelines applicable to LAN on Motherboard (LOM) designs, enterprise networking, and Internet appliances that use the PCI and PCI-X bus backplanes and a twisted pair copper medium. Note: Product features, signal names, and targeted specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 1.3 References It is assumed that the designer is acquainted with high-speed design and board layout techniques. Documents that may provide additional information are: • 8254x Family of Gigabit Ethernet Controllers Software Developer’s Manual, Revision 2.0, Intel Corporation. • PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group. • PCI Local Bus Specification, Revision 2.3, PCI Special Interest Group. • PCI-X Specification, Revision 1.0a, PCI Special Interest Group. • PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group. • IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE). • IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE). • IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE). • IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE). • IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). • Oscillation Circuit Design Guide Application Note, Epson Electronics America, Inc. (www.eea.epson.com). • Quartz Crystal Theory of Operation and Design Notes. Fox Electronics (www.foxonline.com). • Crystal Technical Glossary. Fox Electronics. • Crystal Frequently Asked Questions. Fox Electronics. • Resonator Terminology and Formulas. Piezo Technology, Inc. (www.piezotech.com). 2.0 PCI/PCI-X Signal Interface The 82545EM/82545GM, 82546EB/82546GB provide a 32-bit and 64-bit interface for the 33 MHz or 66 MHz PCI bus. In addition, these devices also support the new PCI-X extension. PCI-X specifies an enhanced protocol that performs data transfers over the 32/64-bit bus at speeds up to 133 MHz. 9 Design Guide—82545/82546 2.1 PCI Master and Slave Operation Both controllers operate as a PCI slave device for configuration and register programming. After the device has been properly initialized, it can also operate as a PCI master. The controller accesses memory directly to fetch memory descriptors, read transmit data, and write receive data. 2.2 PCI Signaling Environment The devices are capable of operating in either a 5 V or 3.3 V PCI signaling environment. The device VIO terminals can be connected to either 5 V or 3.3 V to choose the appropriate PCI/PCI-X bus level. These connections bias the controller PCI I/O buffers for the correct switching strength. However, all other digital inputs and outputs use 3.3 V signaling unless specified separately. 3.0 LAN Disable Guidelines The 82545EM, 82545GM, 82546EB/82546GB controllers have a LAN disable function multiplexed on the FL_DATA0 signal (FL_DATA0/LAN_DISABLE#). For the dual port 82546EB or 82546GB controller, LAN A is disabled through the FL_DATA0/ LAN_DISABLE#. LAN B is disabled through the FL_DATA1/LAN_DISABLE# on ball G18. Each of these pins can be connected to a GPIO pin on the ICH5 component allowing the BIOS to disable the Ethernet port(s). If the serial Flash interface is populated, Flash data pins must not interfere with this function. The LAN_POWER_GOOD signal must not be used as a LAN disable input. This pin is intended to operate as a power-on reset connected to a power monitor circuit. The input of FLSH_DATA0 (or FLSH_DATA1 for LAN B of the 82546EB/82546GB) is the LAN_ENABLE signal. It is sampled on the rising edge of LAN_PWR_GOOD or PCI_RST#. The signal must be held valid for 80 ns after either rising edge. If it is sampled high, the LAN functions normally. If it is sample low, the following sequence occurs: 1. The LAN is disabled. 2. The PHY unit is powered down. 3. Most MAC clock domains are gated. 4. Most functional blocks are held in reset. 5. PCI I/O signals are tri-stated. 6. The device does not respond to PCI cycles (including configuration cycles). 7. The device is placed in a low power state (equivalent to D3 without wake-up or manageability). 10 82545/82546—Design Guide 4.0 Design Components 4.1 Serial EEPROM The 82545EM/82545GM, 82546EB/82546GB controllers use a 64-register by 16-bit serial EEPROM device for storing product configuration information. Several EEPROM words are automatically accessed by the devices after reset to provide pre-boot configuration data before it is accessed by the host software. The remainder of the stored information is available to software for storing the MAC address, serial numbers, and additional configuration information. Refer to the 82545EM/GM and 82546EB/GB EEPROM Map and Programming Information application note or the 8254x Family of Gigabit Ethernet Controllers Software Developer’s Manual for detailed EEPROM mapping, word, and bit descriptions. The EEPROM may be programmed using a utility developed by Intel called EEUPDATE. It operates on MS-DOS* and a copy can be obtained by contacting your local Intel representative. The EEPROM access algorithm programmed into the controller is compatible with most commercially available 3.3 V Microwire* interface, serial EEPROM devices, with a 64 x 16 (256 x 16 for ASF) organization and a 1 MHz speed rating (1 MHz speed rating is not limited to just 3.3 V). The algorithm drives extra pulses on the shift clock at the beginning and end of read and write cycles. (The extra pulses may violate timing specifications of some EEPROM devices.) A serial EEPROM that specifies “don’t care” shift clock states between accesses should be used. A list of EEPROMs that function satisfactorily with the 82545EM and 82545GM, 82546EB/82546GB are listed in Table 2. Table 2. EEPROMs for the 82545EM/82545GM and 82546EB/82546GB Manufacturer Atmel Catalyst Application Type Non-alerting application Part Number AT93C46 Alerting application AT93C66 Non-alerting application CAT93C46, except revision H Alerting application CAT93C66 Note: The EEPROM interface trace routing is not critical since it operates at a very slow speed. 4.2 Flash Memory The 82545EM/82545GM, 82546EB/82546GB controllers provide an external parallel interface to an optional Flash or boot EPROM device. Accesses to the Flash memory are controlled by the Ethernet device but are accessible to host software as normal PCI reads or writes to the Flash memory mapping range. Flash memory can also be mapped to I/O space. The 82545EM and 82545GM devices support an 8-bit wide parallel Flash memory up to 4 Mbytes (512 Kbytes). Most applications require 1 Mbyte (128 Kbytes). The Flash size in a design may be encoded into bits in the EEPROM. Flash and expansion ROM base address registers are reconfigured based on these EEPROM settings. Flash memory devices that function satisfactorily with the 82545EM and 82545GM controllers are listed in the following table. 11 Design Guide—82545/82546 Table 3. Flash Memory Devices for the 82545EM/82545GM and 82546EB/82546GB Manufacturer Part Number Atmel AT49LV010 AT49BV002AN-70J1 Silicon Storage Technology SST39V512 39VF020-90-4I-NH 39VF020-70-4C-NH The Flash memory interface trace routing is not critical since it runs at a very slow speed. In a space constrained design, the Flash device can be placed in relative isolation from the controller. 4.3 Timing Device All designs require a 25 MHz clock source. The 82545EM/82545GM, 82546EB/82546GB controllers use a 25 MHz source to generate clocks up to 125 MHz for the MAC and PHY circuits. For optimum results (with the lowest cost), a 25 MHz parallel resonant crystal with appropriate load capacitors can be connected to the XTAL1 and XTAL2 leads. Alternatively, a 25 MHz oscillator may be connected to XTAL1 with XTAL2 left unconnected. In either case, the frequency tolerance of the timing device should be 30 ppm or better. (Section 5.0 of this document provides information for crystal selection.) The controller uses the 25 MHz clock input to generate Ethernet data clocks as high as 125 MHz. Thus, the crystal is important to the physical layer IEEE specification conformance as well as to electromagnetic interference characteristics. There are three steps for crystal qualification: 1. Verify that the vendor’s published specifications in the component data sheet meet the required conditions for frequency, frequency tolerance, temperature, oscillation mode and load capacitance. 2. Independently measure the component’s electrical parameters in real systems. a. Measure frequency at GTX_CLK to avoid test probe loading effects at XTAL2. b. Check that the measured behavior is consistent from sample to sample and that it meets the published specifications. For crystals, it is also important to examine startup behavior while varying system voltage and temperature. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems. When crystals are changed, new EMI scans are not required if the existing design has sufficient margin and no other changes are made. The crystal and load capacitors should be placed on the printed circuit boards as close to the controller as possible. If an oscillator is used, the clock signal should be connected with the shortest, most direct trace possible. Other traces should be kept away from the clock trace. Table 4. Reference Crystal Specification Requirements Specification Vibrational Mode 12 Value Fundamental Nominal Frequency 25.000 MHz at 25° C Frequency Tolerance ±30 ppm 82545/82546—Design Guide Table 4. Reference Crystal Specification Requirements Specification 4.4 Value Temperature Stability ±30 ppm at 0° C to 70° C Calibration Mode Parallel Load Capacitance 20 pF to 24 pF Shunt Capacitance 6 pF maximum Series Resistance, Rs 50 Ω maximum Drive Level 0.5 mW maximum Aging ±5.0 ppm per year maximum Insulation Resistance 500 MΩ minimum at DC 100 V Magnetics Module Magnetics modules for 1000BASE-T Ethernet are similar to ones designed for 10/100 Mbps operation. The difference is that four differential signal pairs are used for 1000 Mbps operation instead of two. The magnetics module has a critical effect on overall IEEE and emissions conformance. The device should meet the performance required for a design with reasonable margin allowing for manufacturing variations. Occasionally, components that meet basic specifications may cause the system to fail IEEE testing because of interactions with other components or the printed circuit board itself. Careful qualification of new magnetics modules will help prevent this type of problem. The steps involved in magnetics module qualification are similar to those for oscillator qualification: 1. Verify that the vendor’s published specifications in the component data sheet meet the required IEEE specifications. 2. Independently measure the component’s electrical parameters, checking samples from multiple lots. Verify that the measured behavior is consistent from sample to sample as well as meeting the published specifications. 3. Perform physical layer conformance testing and EMC (FCC and EN) testing in real systems, varying temperature and voltage while performing system level tests. Magnetics modules that are known to work satisfactorily with the 82545EM and 82545GM, 82546EB/82546GB are listed in the following table: Table 5. Magnetics Modules Manufacturer 4.4.1 Part Number Pulse Engineering H5007, JW0A2P019D Bell Fuse S558-5999-P3 Combination Magnetics/RJ-45 Connectors Recently, manufacturers have designed combination magnetics module/RJ-45 connectors. These integrated components offer significant space savings for LAN on motherboard designs. Multiport integrated modules are available as well as single-port designs. 13 Design Guide—82545/82546 4.5 Power Supplies The 82545EM/82545GM, 82546EB/82546GB require three power supplies. Typically, the VDDO (3.3 V I/O) and AVDDH (3.3 V analog) leads can be tied to a single 3.3 V source. The other power supplies are DVDD (1.5 V digital) and AVDDL (2.5 V analog). (Since the 82546EB/82546GB are a dual port components, they will have two 2.5 V analog sources each, AVDDLA and AVDDLB.) A central power supply can provide all required voltage sources or the power can be derived and regulated locally near the Ethernet control circuitry. All voltage sources must remain present during powerdown in order to use the controller’s LAN wake-up capability. This ensures that at least some of the voltage sources will be local. Instead of using regulators to supply 1.5 V and 2.5 V, power transistors can be used in conjunction with the on-chip regulators. Note: For the 82546EB or 82546GB, if the control circuitry is used, separate analog 2.5 V sources must be used. If a regulator is used, the 2.5 V A and B rails can connect to the same regulator source. The 82545EM/82545GM, 82546EB/82546GB have a LAN_PWR_GOOD input signal to hold the device in reset during the power ramp and until all the voltage sources are stable. LAN_PWR_GOOD should also hold the device in reset a few extra milliseconds while the device’s frequency reference (crystal or oscillator) becomes stable. If a central power supply furnishes all the voltage sources, LAN_PWR_GOOD can usually be tied directly to the POWER_GOOD output signal on the power supply. Designs that generate some of the voltages locally for the Ethernet controller may require delaying LAN_PWR_GOOD assertion with additional circuitry to assure that all the sources have time to reach stable operating voltages. The power sources are all expected to ramp up during a brief power-up interval with LAN_PWR_GOOD de-asserted. The 82545EM/82545GM, 82546EB or 82546GB should not be left in a prolonged state where only some (not all) voltages are applied. The only exception to this rule is in power-down mode, where the device can continue to be powered up without the VIO reference (either 5 V or 3.3 V) present. The sequencing shown in Figure 2 to avoid latch-up and forward-biased internal diodes should be followed. The general guideline is that for power up, the higher voltage is up and stable prior to the next lower voltage. In other words, 3.3V is greater than 2.5V > 1.5V. Figure 2. 82545 and 82546 Power Sequencing V 3.3 V 2.5 V 1.5V t In addition, as shown on Figure 3, the voltages must not exceed by more than 0.5V in each of the following cases: • 2.5V must not exceed 3.3V 14 82545/82546—Design Guide • 1.5V must not exceed 3.3V • 1.5V must not exceed 2.5V Figure 3. Maximum Difference between Voltage Rails V VCCAUX3_3 Max difference = 0.5 V 2.5 V 1.5V Max difference = 0.5 V t For power down, there is no specific requirement, only charge that is stored in the decoupling caps remains. 4.5.1 Power Supply Filtering The controller switches relatively high currents at high frequencies, requiring generous use of both bulk capacitance and high speed decoupling capacitance adjacent to the device. In the case of a double-sided printed circuit board design, some of the capacitors can be placed directly under the controller. • Provide approximately six to eight bypass capacitors along each side of the controller, selecting values in the range of 0.001 µF to 0.01 µF. If possible, orient the capacitors close to the device and adjacent to power pads. Decoupling capacitors should connect to the power planes with short, thick (15 mils to 0.4 mm or more) traces and 14 mil (0.35 mm) vias. Capacitor arrays may be used to reduce the overall package count. • Furnish approximately 30 µF of bulk capacitance for each of the four voltage levels. This can be accomplished by using about a dozen 10 µF capacitors, placing them as close to the device power connections as possible. • Use decoupling and bulk capacitors generously. If the design is quieter than expected, it is easy to delete capacitors during manufacturing. 4.5.2 1.5 V Regulator Circuit Operation Parameters (82546EB/ 82545EM) Correct operation of the 1.5V regulation circuit depend on several factors: presence of minimum leakage current from the CTRL_15 output, supported min/max values for external PNP transistor gain (Beta), and the generation of sufficient 1.5 V rail current/ voltage to supply the regulator circuit. Refer Errata 8 in the 82546EB (or 82545EB) Gigabit Ethernet Controller Specification Update for more information. The minimum leakage current provided from the CTRL_15 regulator control pin during startup is 0 A. Maximum leakage current when the regulator circuit is operating and providing minimum transistor base current is 1 A. 15 Design Guide—82545/82546 The minimum 1.5 V rail current (PNP collector current) required for the regulator control circuitry to start up reliably on the 82546EB is 10 mA. System designers must ensure that the total collector current, IC = (IB * Beta), satisfies this requirement at startup conditions. For the recommended bias resistor R3 value of 15 K ohm, the selected PNP device must exhibit minimum gain (Beta) of approximately 75 during operation at <5 mA and VCE of approximately 1.0-1.8V at the worst-case temperature of 0 C. To ensure proper 1.5 V rail regulation during operation, system designers must further ensure that the highest-gain PNP transistors used do not produce IC currents significantly in excess of the 1.5 V power consumption in D3cold power states (typical 1.5 V consumption for D3cold states in no-wakeup/SMBus configuration and WOL/ SMBus-enabled configurations are provided). For example, for the 82546EB, with the recommended bias resistor R3 value of 15K ohm and recommended WOL/SMBusenabled configuration, the selected PNP device must exhibit maximum HFE gain (Beta) of no more than 275 during high-temperature operation (70 C) to source less than 50 mA of current. 4.5.3 Power Management and Wake Up The 82545EM/82545GM, 82546EB/82546GB support low power operation as defined in the PCI Bus Power Management Specification. There are two defined power states, D0 and D3. The D0 state provides full power operation and is divided into two substates: D0u (uninitialized) and D0a (active). The D3 state provides low power operation and is also divided into two substates: D3hot and D3cold. To enter the low power state, the software driver must stop data transmission and reception. Either the operating system or driver must program the Power Management Control/Status Register (PMCSR) and the Wake-up Control Register (WUC). If wake-up is desired, the appropriate wake-up LAN address filters must also be set. Then the system can optionally assert the PCI_RESET_N signal. The initial power management settings are specified by EEPROM bits. When the 82545EM/82545GM, 82546EB/82546GB controllers transition to either of the D3 low power states, VDDO and AVDDH (3.3 V), AVDDL (2.5 V), and DVDD (1.5 V) must continue to be supplied to the device; otherwise, it is not possible to use a wakeup mechanism. This should be taken into account when deciding whether to provide the power sources locally or from a central power supply. Commercial power supplies commonly provide a 3.3 V auxiliary power signal but not the full range of voltages required by these devices. The auxiliary power signal (AUX_POWER) is a logic input to the controller that denotes auxiliary power is available. If AUX_POWER is asserted, the controller advertises its wake-up support from a D3cold state. The controller also adjusts the effect of reset upon the Power Management Enable (PME_N) pin so that PCI_RESET_N de-assertion cannot disable certain power-down and wake-up settings. The 82545EM/82545GM, 82546EB/82546GB support both Advanced Power Management (APM) wake-up and Advanced Configuration and Power Interface (ACPI) wake-up. APM wake-up has also been known in the past as “Wake on LAN.” APM wake-up uses the APM_WAKEUP signal to wake the system and can optionally use the PME# signal. APM_WAKEUP is an active high output that pulses for approximately 50 ms when the controller receives a Magic Packet*. ACPI wake-up uses the PME_N signal to wake the system. PME_N is an active low signal that becomes active in response to receiving a Magic Packet, a network wake-up packet, or link status change indication. PME_N remains asserted until it is disabled through the PMCSR. 16 82545/82546—Design Guide 4.5.4 System Power Budget Consideration The information listed in the specification update for the 82545xx and 82546xx power specifications for the supported power states (D0a, D3cold - Wake-up enabled, D3cold - Wake-up disabled, etc.) needs to be carefully reviewed to determine the power requirements for your specific configuration. The system configuration must not exceed the power budget constraints imposed by the system power supply. 4.6 Light Emitting Diodes (LEDs) The 82545EM/82545GM, 82546EB/82546GB controllers provide several high-current outputs to directly drive LEDs for link status, speed and duplex mode. Trace routing to the LEDs should have a low priority since they are low frequency signals. 4.7 Test Access Port (TAP) The test access port conforms to the IEEE 1149.1a-1994 (JTAG) Boundary Scan Specification. The test access port can be used by connecting these test leads to pads accessible by test equipment. The TRST# input pin should be connected to ground through a pull-down resistor (approximately 1 KΩ) so that the test capability cannot be invoked by mistake. A Boundary Scan Definition Language (BSDL) file describing the 82545EM/82545GM, 82546EB or 82546GB device is also available. 4.8 Frequency Control Device Design Considerations This section provides information regarding frequency control devices, including crystals and oscillators, for use with all Intel® Ethernet controllers. Several suitable frequency control devices are available; none of which present any unusual challenges in selection. The concepts documented herein are applicable to other data communication circuits, including Physical Layer devices (PHYs). The Intel® Ethernet controllers contain amplifiers which, when used with the specific external components, form the basis for feedback oscillators. These oscillator circuits, which are both economical and reliable, are described in more detail in “Crystal Selection Parameters”. The Intel® Ethernet controllers also have bus clock input functionality, however a discussion of this feature is beyond the scope of this document, and will not be addressed. The chosen frequency control device vendor should be consulted early in the design cycle. Crystal and oscillator manufacturers familiar with networking equipment clock requirements may provide assistance in selecting an optimum, low-cost solution. 4.9 Frequency Control Component Types Several types of third-party frequency reference components are currently marketed. A discussion of each follows, listed in preferred order. 4.10 Quartz Crystal Quartz crystals are generally considered to be the mainstay of frequency control components due to their low cost and ease of implementation. They are available from numerous vendors in many package types and with various specification options. 17 Design Guide—82545/82546 4.11 Fixed Crystal Oscillator A packaged fixed crystal oscillator is comprised of an inverter, a quartz crystal, and passive components conveniently packaged together. The device renders a strong, consistent square wave output. Oscillators used with microprocessors are supplied in many configurations and tolerances. Crystal oscillators should be restricted to use in special situations, such as shared clocking among devices or multiple controllers. As clock routing can be difficult to accomplish, it is preferable to provide a separate crystal for each device. For Intel® Ethernet controllers, it is acceptable to overdrive the internal inverter by connecting a 25 MHz external oscillator to the XTAL1 lead, leaving the XTAL2 lead unconnected. The oscillator should be specified to drive CMOS logic levels, and the clock trace to the device should be as short as possible. Device specifications typically call for a 40% (minimum) to 60% (maximum) duty cycle and a ±50 ppm frequency tolerance. Note: Please contact your Intel Customer Representative to obtain the most current device documentation prior to implementing this solution. 4.12 Programmable Crystal Oscillators A programmable oscillator can be configured to operate at many frequencies. The device contains a crystal frequency reference and a phase lock loop (PLL) clock generator. The frequency multipliers and divisors are controlled by programmable fuses. A programmable oscillator’s accuracy depends heavily on the Ethernet device’s differential transmit lines. The Physical Layer (PHY) uses the clock input from the device to drive a differential Manchester (for 10 Mbps operation), an MLT-3 (for 100 Mbps operation) or a PAM-5 (for 1000 Mbps operation) encoded analog signal across the twisted pair cable. These signals are referred to as self-clocking, which means the clock must be recovered at the receiving link partner. Clock recovery is performed with another PLL that locks onto the signal at the other end. PLLs are prone to exhibit frequency jitter. The transmitted signal can also have considerable jitter even with the programmable oscillator working within its specified frequency tolerance. PLLs must be designed carefully to lock onto signals over a reasonable frequency range. If the transmitted signal has high jitter and the receiver’s PLL loses its lock, then bit errors or link loss can occur. PHY devices are deployed for many different communication applications. Some PHYs contain PLLs with marginal lock range and cannot tolerate the jitter inherent in data transmission clocked with a programmable oscillator. The American National Standards Institute (ANSI) X3.263-1995 standard test method for transmit jitter is not stringent enough to predict PLL-to-PLL lock failures, therefore, the use of programmable oscillators is generally not recommended. 4.13 Ceramic Resonator Similar to a quartz crystal, a ceramic resonator is a piezoelectric device. A ceramic resonator typically carries a frequency tolerance of ±0.5%, – inadequate for use with Intel® Ethernet controllers, and therefore, should not be utilized. 18 82545/82546—Design Guide 5.0 Crystal Selection Parameters All crystals used with Intel® Ethernet controllers are described as “AT-cut,” which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. Table 6 lists the crystal electrical parameters and provides suggested values for typical designs. These parameters are described in the following subsections. Table 6. Crystal Parameters Parameter Vibrational Mode Fundamental Nominal Frequency 25.000 MHz at 25° C (required) Frequency Tolerance Temperature Stability 5.1 Suggested Value • • ±30 ppm recommended ±50 ppm across the entire operating temperature range (required by IEEE specifications) ±50 ppm at 0° C to 70° C Calibration Mode Parallel Load Capacitance 16 pF to 20 pF Shunt Capacitance 6 pF maximum Equivalent Series Resistance 50 Ω maximum Drive Level 0.5 mW maximum Aging ±5 ppm per year maximum Vibrational Mode Crystals in the above-referenced frequency range are available in both fundamental and third overtone. Unless there is a special need for third overtone, use fundamental mode crystals. At any given operating frequency, third overtone crystals are thicker and more rugged than fundamental mode crystals. Third overtone crystals are more suitable for use in military or harsh industrial environments. Third overtone crystals require a trap circuit (extra capacitor and inductor) in the load circuitry to suppress fundamental mode oscillation as the circuit powers up. Selecting values for these components is beyond the scope of this document. 5.2 Nominal Frequency Intel® Ethernet controllers use a crystal frequency of 25.000 MHz. The 25 MHz input is used to generate a 125 MHz transmit clock for 100BASE-TX and 1000BASE-TX operation – 10 MHz and 20 MHz transmit clocks, for 10BASE-T operation. 5.3 Frequency Tolerance The frequency tolerance for an Ethernet physical layer device is dictated by the IEEE 802.3 specification as ±50 parts per million (ppm). This measurement is referenced to a standard temperature of 25° C. Intel recommends a frequency tolerance of ±30 ppm. 19 Design Guide—82545/82546 5.4 Temperature Stability and Environmental Requirements Temperature stability is a standard measure of how the oscillation frequency varies over the full operational temperature range (and beyond). Several optional temperature ranges are currently available, including -40° C to +85° C for industrial environments. Some vendors separate operating temperatures from temperature stability. Manufacturers may also list temperature stability as 50 ppm in their data sheets. Note: Crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. Crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements. 5.5 Calibration Mode The terms “series-resonant” and “parallel-resonant” are often used to describe crystal oscillator circuits. Specifying parallel mode is critical to determining how the crystal frequency is calibrated at the factory. A crystal specified and tested as series resonant oscillates without problem in a parallel-resonant circuit, but the frequency is higher than nominal by several hundred parts per million. The purpose of adding load capacitors to a crystal oscillator circuit is to establish resonance at a frequency higher than the crystal’s inherent series resonant frequency. Figure 4 illustrates a simplified schematic of the internal oscillator circuit. Pin X1 and X2 refers to XTAL1 and XTAL2 in the Ethernet device, respectively. The crystal and the capacitors form a feedback element for the internal inverting amplifier. This combination is called parallel-resonant, because it has positive reactance at the selected frequency. In other words, the crystal behaves like an inductor in a parallel LC circuit. Oscillators with piezoelectric feedback elements are also known as “Pierce” oscillators. Figure 4. Internal Oscillator Circuit Pin X1 C1 22pF 5% 20 Y1 25 MHz Pin X2 C2 22pF 5% 82545/82546—Design Guide 5.6 Load Capacitance The formula for crystal load capacitance is as follows: ( C1 Þ C2 ) C L = --------------------- + C stray ( C1 + C2 ) where C1 = C2 = 22 pF (as suggested in most Intel reference designs) and Cstray = allowance for additional capacitance in pads, traces and the chip carrier within the Ethernet device package An allowance of 3 pF to 7 pF accounts for lumped stray capacitance. The calculated load capacitance is 16 pF with an estimated stray capacitance of about 5 pF. Individual stray capacitance components can be estimated and added. For example, surface mount pads for the load capacitors add approximately 2.5 pF in parallel to each capacitor. This technique is especially useful if Y1, C1 and C2 must be placed farther than approximately one-half (0.5) inch from the device. It is worth noting that thin circuit boards generally have higher stray capacitance than thick circuit boards. Standard capacitor loads used by crystal manufacturers include 16 pF, 18 pF and 20 pF. Any of these values will generally operate with the device. However, a difference of several picofarads between the calibrated load and the actual load will pull the oscillator slightly off frequency. The oscillator frequency should be measured with a precision frequency counter where possible. The load specification or values of C1 and C2 should be fine tuned for the design. As the actual capacitance load increases, the oscillator frequency decreases. Note: C1 and C2 may vary by as much as 5% (approximately 1 pF) from their nominal values. 5.7 Shunt Capacitance The shunt capacitance parameter is relatively unimportant compared to load capacitance. Shunt capacitance represents the effect of the crystal’s mechanical holder and contacts. The shunt capacitance should equal a maximum of 6 pF (7 pF is also acceptable). 5.8 Equivalent Series Resistance Equivalent Series Resistance (ESR) is the real component of the crystal’s impedance at the calibration frequency, which the inverting amplifier’s loop gain must overcome. ESR varies inversely with frequency for a given crystal family. The lower the ESR, the faster the crystal starts up. Use crystals with an ESR value of 50 Ω or better. 5.9 Drive Level Drive level refers to power dissipation in use. The allowable drive level for a Surface Mounted Technology (SMT) crystal is less than its through-hole counterpart, because surface mount crystals are typically made from narrow, rectangular AT strips, rather than circular AT quartz blanks. 21 Design Guide—82545/82546 Some crystal data sheets list crystals with a maximum drive level of 1 mW. However, Intel® Ethernet controllers drive crystals to a level less than the suggested 0.5 mW value. This parameter does not have much value for on-chip oscillator use. 5.10 Aging Aging is a permanent change in frequency (and resistance) occurring over time. This parameter is most important in its first year because new crystals age faster than old crystals. Use crystals with a maximum of ±5 ppm per year aging. 5.11 Reference Crystal The normal tolerances of the discrete crystal components can contribute to small frequency offsets with respect to the target center frequency. To minimize the risk of tolerance-caused frequency offsets causing a small percentage of production line units to be outside of the acceptable frequency range, it is important to account for those shifts while empirically determining the proper values for the discrete loading capacitors, C1 and C2. Even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. Therefore, frequency measurements (which determine the correct value for C1 and C2) should be performed with an ideal reference crystal. When the capacitive load is exactly equal to the crystal’s load rating, an ideal reference crystal will be perfectly centered at the desired target frequency. 5.11.1 Reference Crystal Selection There are several methods available for choosing the appropriate reference crystal: If a Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation (with the appropriate capacitive load). A crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for C1 and C2. If a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors. The crystal, which has an oscillation frequency closest to the center of the distribution, should be the reference crystal used during testing to determine the best values for C1 and C2. It may also be possible to ask the approved crystal vendors or manufacturers to provide a reference crystal with zero or nearly zero deviation from the specified frequency when it has the specified CLoad capacitance. When choosing a crystal, customers must keep in mind that to comply with IEEE specifications for 10/100 and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be precise within ±50 ppm. Intel® recommends customers to use a transmitter reference frequency that is accurate to within ±30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance. For information about measuring transmitter reference frequency, refer to Appendix A, “Measuring LAN Reference Frequency Using a Frequency Counter”. 22 82545/82546—Design Guide 5.11.2 Circuit Board Since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. If the thickness tolerance for the outer layers of dielectric are controlled within ±17 percent of nominal, then the circuit board should not cause more than ±2 pF variation to the stray capacitance at the crystal. When tuning crystal frequency, it is recommended that at least three circuit boards are tested for frequency. These boards should be from different production lots of bare circuit boards. Alternatively, a larger sample population of circuit boards can be used. A larger population will increase the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance. Next, the exact same crystal and discrete load capacitors (C1 and C2) must be soldered onto each board, and the LAN reference frequency should be measured on each circuit board. The circuit board, which has a LAN reference frequency closest to the center of the frequency distribution, should be used while performing the frequency measurements to select the appropriate value for C1 and C2. 5.11.3 Temperature Changes Temperature changes can cause the crystal frequency to shift. Therefore, frequency measurements should be done in the final system chassis across the system’s rated operating temperature range. 6.0 Design and Layout Considerations In 1000BASE-T systems, the main design elements are the 82545EM and 82545GM Gigabit Ethernet Controllers or the 82546EB and 82546GB Dual Port Gigabit Ethernet Controllers, the magnetics module, and the RJ-45 connector. Since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. The primary scope of this section is gigabit operation design. However, 82545EM/ 82545GM, 82546EB/82546GB Ethernet designs for twisted pair copper wiring will also operate at 100 Mbps and 10 Mbps. Thus, system level tests should be performed at all three speeds. 23 Design Guide—82545/82546 6.1 Board Stack Recommendations Printed circuit boards for 1000BASE-T designs using the 82545EM/82545GM, 82546EB or 82546GB will typically have six, eight or more layers. The following diagram illustrates a possible six-layer board stack, 62 mil (1.6 mm) printed circuit board. Figure 5. Six-layer Board Stack Layer 1: Signal Layer Termination Plane 8 mil (0.2mm) separation Layer 2: Signal Ground Layer Chassis Ground 8 mil (0.2mm) separation Layer 3: Signal or Power Layer 32 mil (0.8mm) separation Layer 4: Power or Signal Layer Chassis Ground 8 mil (0.2mm) separation Layer 5: Signal Ground Layer 8 mil (0.2mm) separation Layer 6: Signal Layer Termination Plane • Layer 1: Signal Layer. This layer typically contains the differential analog pairs from the controller to the magnetics module and from the magnetics module to the RJ-45 connector. The termination plane described in Section 6.1.1, “Termination Plane and Chassis Ground” is also fabricated in Layer 1. • Layer 2: Signal Ground Layer. The chassis ground is also fabricated in Layer 2. • Layer 3 and 4: Power and/or Signal Layers. In the vicinity of the LAN controller, one or both layers may be broken up into power planes for the four voltage levels required by the device. The remaining area in these layers may be used for signal routing. In the vicinity of the RJ-45 connector, additional chassis ground metal can be fabricated in Layer 4. • Layer 5: Ground Layer. Layer 5 can be used as an additional ground layer. • Layer 6: Signal Layer. An additional termination plane area can also be fabricated in Layer 6. This board stack up configuration can be adjusted to conform to an OEM’s design rules. For example, an OEM may not allow asymmetrical power planes due to increased risk of board warpage. This can be addressed by adding extra metal fill in an offsetting board layer. 24 82545/82546—Design Guide 6.1.1 Termination Plane and Chassis Ground For Gigabit Ethernet designs, it is common practice to terminate center tap magnetics module connections (RJ-45 side) to ground as a path for low frequency noise. Depending on the overall shielding and grounding design, the specific ground used for this purpose can vary. Intel recommends the use of a dedicated termination plane, with the center tap leads connected to the termination plane through 75 Ω resistors. The termination plane is typically fabricated in Layer 1, with a matching chassis ground plane underneath as illustrated in Figure 6. The clearance between the termination plane and any traces should be at least 50 mils (1.25 mm) to prevent arcing during high voltage tests. The termination plane and chassis ground layer combination has some capacitance, which can be augmented by adding a discrete 1500 pF capacitor. Integrated magnetics model/RJ-45 connectors also contain the termination plane, 75 Ω termination resistors and a 1000 pF to 1500 pF capacitor. If integrated components are going to be used, their internal design needs to be evaluated carefully. The electrical parameters, EMI, and high voltage test results should be equivalent to, or better than, the characteristics of a discrete design. Additional capacitors are required to interconnect chassis ground and signal ground. The suggested technique is to use several different capacitor values (for example, two 1000 pF, one 4.7 mF, and one 10 µF). Depending on available board space, one set of capacitors should be placed on each side of the magnetics module. Modifications to this interconnection scheme are possible. Figure 6. 1000BASE-T Termination Plane and Chassis Ground Signal Ground Plane (Layer 2) Termination Plane (Layers 1 and 6) Gap RJ-45 Connector Chassis Ground (Layer 2) Magnetics Module Pads for Termination Resistors 25 Design Guide—82545/82546 6.2 Signal Traces Critical signal traces should be kept as short as possible to decrease the likelihood of any effects from other signals with high frequency noise, including noise carried on power and ground planes. Keeping the traces as short as possible also helps reduce capacitive loading. 6.2.1 Transmission Line Layout The following subsections detail the key interfaces for gigabit Ethernet LAN circuits requiring special placement and routing attention. The important signals are the differential signal pairs running from the Ethernet controller to the magnetics module and then to the RJ-45 connector. The interface from the 82545EM/82545GM, 82546EB or 82546GB device to the magnetics module operates with analog signaling at a clock rate of 125 MHz. The four pairs of signals should be treated as high-speed transmission lines, with careful attention to layout guidelines. Each pair of signals should have a target differential impedance of 100 Ω. If a particular tool or layout vendor cannot design differential traces, it is permissible to specify 55 Ω to 65 Ω single-ended traces as long as the spacing between the two traces is minimized. As an example, consider a differential trace pair on Layer 1 that is 8 mils (0.2 mm) wide and 2 mils (0.05 mm) thick, with a spacing of 8 mils (0.2 mm). If the fiberglass layer is 8 mils (0.2 mm) thick with a dielectric constant (ER) of 4.7, the calculated single-ended impedance would be approximately 61 Ω and the calculated differential impedance would be approximately 100 Ω. If a CAD tool is used, the auto-router should not be able to route the differential pairs without intervention. In most cases, the differential pairs will have to be routed manually. 6.2.1.1 Trace Length and Symmetry The differential pairs should be routed to be as short and symmetrical as possible. The overall length of differential pairs should be less than four inches measured from the controller across the magnetics module to the RJ-45 connector. The distance between the magnetics module and the RJ-45 connector is somewhat more important than the distance between the 82545EM/82545GM, 82546EB or 82546GB device and the magnetics module. The lengths of the differential traces (within each pair) should be equal within 50 mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise. The distance from trace to trace should be minimized within each pair to be no more than 30 mils (0.75 mm). To reduce crosstalk interference on signals between pairs, the minimum distance between unlike differential pairs must be 50 mils (1.25 mm). This rule also applies to differential pairs from other Ethernet controller circuits on the same board. 6.2.1.2 Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections. To minimize impedance discontinuity, traces within differential pairs must not have bends over 45 degrees. If possible, the corners of all bends should be rounded to enhance performance. Vias and other transmission line irregularities should be avoided. If vias must be used, a reasonable via budget is two per differential trace. Unused pads and stub traces should also be avoided. 26 82545/82546—Design Guide 6.2.1.3 Signal Clutter Signal integrity is maintained by placing digital signals far away from the analog traces. The general rule to follow is that no digital signal should be within 300 mils (7.5 mm) of the differential pairs. If digital signals on other board layers cannot be separated by a ground plane, they should be routed at right angles with respect to the differential pairs. If another LAN controller is present on the board, the differential pairs should be kept away from that circuit. Ganged RJ-45 connectors are allowed, but the signals for each circuit must also be carefully separated. Integrated magnetics modules with RJ-45 jacks may be used. If integrated components are used, the LAN controller should not be placed too close to the back edge of the board as this may lead to increased EMI. 6.2.1.4 Signal Terminations The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82545EM/82545GM, 82546EB or 82546GB. One resistor connects to the MDI+ signal trace and another resistor connects to the MDI- signal trace. The opposite ends of the resistors connect together and to ground through a single 0.01 mF capacitor. The suggested component values should not be varied. Symmetrical pads and traces for these components should be laid out for these components such that the length and symmetry of the differential pairs are not disturbed. 6.2.2 PCI/PCI-X Bus Routing The PCI and PCI-X specifications provide useful information and can be used as a guideline for connecting the PCI bus on the 82545EM/82545GM, 82546EB or 82546GB controller. Due to higher bus speeds, the PCI-X Specification has more stringent requirements on the number of devices that can be placed on the bus. In addition, it requires more tightly controlled board impedance for add-in cards. 6.2.3 Unused Connections Terminating unused inputs with a pull-up or pull-down resistor, unless otherwise specified, is recommended. Pins identified as “No Connect” should not be attached to pull-up or pull-down resistors, unless otherwise specified, since these devices may have special test modes that could be entered inadvertently. 6.3 1000BASE-T Physical Layer Conformance Testing Physical layer conformance testing (also known as IEEE testing) is a fundamental capability for all companies with Ethernet LAN products. If resources are not available to perform these tests, outside contractors with these capabilities will be able to assist. The crucial tests for 1000BASE-T designs are listed below in order of priority: 1. Bit Error Rate (BER). The BER provides a good indication of real world network performance. BER testing should be performed with long and short cables and several link partners. The test limit is 10 to 11 errors. 2. Output Amplitude, Symmetry and Droop. The appropriate controller PHY test waveform should be used when conducting this test. 3. Return Loss. The return loss indicates proper impedance matching, which is measured through the RJ-45 connector back toward the magnetics module. 4. Unfiltered Jitter Test. This test indicates the clock recovery ability as master and slave. 27 Design Guide—82545/82546 5. The unfiltered jitter test requires activation of a special test mode on the MAC as well as selecting test waveforms in the PHY. This test mode exposes the transmit clock (on GTX_CLK) and the internal receive clock (on RBC1) from the internal GMII interface for use as scope triggers. Since the devices are integrated MAC/PHY components, these signals are not brought out during normal operation. The Intel 1000BASE-T Physical Layer Conformance Tests Manual provides more detailed instructions for performing these tests. A copy may be obtained through your local Intel representative. 7.0 Design and Layout Checklists The following checklists should be used as design aids. Note: Applications using the SerDes interface should refer to the Designing SerDes-SerDes Interface with Intel® 82546GB Gigabit Ethernet Controller Application Note for more details and reference schematics. Table 7. 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist Section General Check Items Remarks Have most current product documentation and specification updates Documents are subject to frequent change Observe instructions for special pins needing pull-up or pulldown resistors. Do not connect pull-up or pulldown resistors to any pins marked No Connect. Connect the appropriate interface (either 32-bit PCI or 64-bit PCI-X) pins to corresponding system pins. Controller Option Connect Ball A17 LAN_PWR_GOOD to RSMRST# or other voltage supervisor circuit. Input should remain low until all power supplies are stable and for approximately 80 ms. LAN_PWR_GOOD works similar to an auxiliary chip reset. It should be a clean, glitch-free signal. It is not intended for use as a LAN Disable signal. LAN_PWR_GOOD must be asserted during powerdown states to allow wake-up. Connect Ball T4 PME# to the system for wake-up signaling. The typical connection is GPIO8 on ICH. Connect Ball R3 AUX_PWR signals correctly. AUX_PWR is a logic input denoting that auxiliary power is connected to the device. For wake-up, AUX_PWR must equal 1. Connect Ball T5 PCI_RST# to PCI_RST# on system. 28 Connect a 0.01µF capacitor between ball Y16 (M66EN) and ground. M66EN should have a pull-up resistor somewhere in the system. This is the capacitor value per specification for signal integrity. This signal may be grounded anywhere on the segment for any PCI device incapable of 66 MHz operation. Connect balls Y1 and Y20 (VIO) to 5V Standby or 3.3V Standby to match PCI signaling voltage. A 100 KΩ resistor should be used as a current limiter, and a 0.01 µF capacitor, as a bypass capacitor. √Done Comments 82545/82546—Design Guide Table 7. Section Controller Option (cont.) 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist Check Items Remarks Attach a 22.6 Ω 1% pull-up resistor from ball T2 (ZN_COMP) to 3.3 V rail. Attach a 35.7 Ω 1% pull-down resistor from ball R5 (ZP_COMP) to ground. This sets PCI bus drive strength. Use an AT93C46 EEPROM for non-alerting applications or an AT93C66 for alerting applications. For Microwire* EEPROMs, do not install a pull-down resistor on the EE_DO pin. Microwire EEPROMs should be rated for at least 1 MHz. Check reference schematic for connection of Software Defined Pins. Intel driver software may expect to use Software Defined Pins for special functions. Provide a test point for IEEE PHY conformance testing. Depopulate the header for production. This will be a header between ball P3 (CLK_VIEW) and ground (single-ended clock output). Drive ball H16 (FL_DATA0) for the 82545EM/GM if a LAN disable function is required. The ICH resume well connection (GPIO 25, 27, or 28) can be used. Drive balls H16 (FL_DATA0) and G18 (FL_DATA1) for the 82546EB/GB if a LAN disable function is required. The ICH resume well connection (GPIO25, 26, or 28) can be used. √Done Comments Connect ball E3, REFA, and ball L4, REFB, to ground through 2.49 KΩ 1% resistors. Clock Source EEPROM and Flash Memory Use 25 MHz 30 ppm accuracy at 25×Clock source. Avoid components that introduce jitter. Parallel resonant crystals are preferred. An oscillator can be used if testability rules require turning off the clock. If an oscillator is used, a termination resistor of 22 to 33 Ω might be considered for use. PLL clock buffers should be avoided. Connect two 22 pF load capacitors to crystal. Capacitance affects accuracy of the frequency. They must be matched to crystal specifications, including estimated trace capacitance in calculation. Use decoupling capacitor. This applies to EEPROM or Flash devices. Tie EEPROM ORG to 3.3 V for x16 access. This is for Microwire EEPROMs and depends on the EEPROM used. Consider whether to use Flash memory. Most LOM systems with boot ROM place the image in the system Flash. Select the appropriate device if Flash memory is used. 29 Design Guide—82545/82546 Table 7. Section SMB 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist Check Items Remarks Connect pull-up resistors to SMBClk, SMBData, and SMBAlert if SMB is not used 4.7 KΩ pull-up resistor values are reasonable. Ensure system has pull-up resistors if SMB is used. SMB signals are open-drain. For ASF applications only, connect ball A16 (SMB_ALRT#/ PCI_PWR_GOOD) to the system PCI_PWR_GOOD signal or Vcc through a 3.3 KΩ pull-up resistor. The 3.3V power supply should be used (not 3.3V auxiliary) for PCI_PWR_GOOD. Alternatively, ball A16 can be configured as an SMB_ALRT# output for SMB applications. All devices: The connections and transistor parameters are critical. 82545EM/GM: Connect external PNP transistors to the regulator control CTRL15 and CTRL25 outputs to supply 1.5V and 2.5V, respectively. 82546EB/GB: Use CTRL15, CTRL25A, and CTRL25B to supply 1.5V, 2.5V, and 2.5V, respectively. Alternatively, external regulators can be provided to generate these voltages. If the internal voltage regulator control circuit is not used, the CTRL pins may be left unconnected. Provide a 3.3V supply. Power Supply and Signal Ground 30 Design with power supplies that start up properly. A good guideline is that all voltages should ramp to within their control bands in 20 ms or less. It is desirable that voltages ramp in sequence and that the voltage rise is monotonic. Use auxiliary power supplies. It is necessary to have the Ethernet device wake up from power-down states. Use decoupling and bulk capacitors generously. Six to eight 0.001 µF bypass capacitors should be placed along each side of the controller. A 30 µF value of bulk capacitance per voltage rail should be added (typically using 10 µF capacitors). If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector. √Done Comments 82545/82546—Design Guide Table 7. Section LED Circuits Mfg Test 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist Check Items Remarks 82545EM/GM basic recommendation: one single orange LED for activity and a green LED for link. Many other configurations are possible. Two LED configuration is compatible with integrated magnetics modules. For the activity LED, the cathode should be connected to N1 (ACT_A#) and pull the anode up to 3.3V. The link LED should be connected to M1 (LINKA#). 82546EB/GB basic recommendation: one single orange LED for each activity port and a green LEF for link. Many other configurations are possible. For the activity LEDs, the cathodes should be connected to N1 (ACT_A#) and B13 (ACT_B#). The anodes for both ports should be pulled up to 3.3V. The link LEDs should be connected to M1 (LINKA#) and A13 (LINKB#). Connect LEDs to 3.3V as indicated in reference schematics. To support wake-up, a 3.3V auxiliary power is required. Filtering capacitors can be added for extremely noisy situations. The suggested starting value for capacitance is 470 pF. Add current limiting resistors to LED paths. Typical current limiting resistors are 300 to 330Ω when a 3.3V power supply is used. Current limiting resistors are typically included with integrated magnetics modules. Use a JTAG Test Access Port. 1 KΩ pull-down resistors should be placed on ball N5 (TRST#) and P1 (TCK). These connections hold the TAP controller in an inactive state. √Done Comments The following items in this table are only for copper applications. Transmit and Receive Differential Pairs Magnetics Module Use pairs of 49.9 Ω termination resistors with 0.01 µF capacitors attached between center nodes and ground. This should be applied to all four differential pairs. Use integrated magnetics modules/RJ-45 connectors to minimize space requirements. Modules with pin compatibility from Fast Ethernet to Gigabit Ethernet are available, containing internal jumpers for the unused pairs. Multivendor pin compatibility is possible. (Contact manufacturers.) Qualify magnetics module carefully for Return Loss, Insertion Loss, Open Circuit Inductance, Common Mode Rejection, and Crosstalk Isolation. Magnetics module is critical to passing IEEE PHY conformance tests and EMI test. Supply 2.5 V to the transformer center taps and use 0.1 µF bypass capacitors. These voltages bias the controller's output buffers. Magnetics with four center tap pins may have better characteristics than those with 1 to 2 center tap pins. Capacitors with low Equivalent Series Resistance should be used. 31 Design Guide—82545/82546 Table 7. Section Discrete Magnetics Module/RJ45 Connector Option Chassis Ground Termination Plane Table 8. Section General Ethernet Device 32 82545EM / 82545GM / 82546EB / 82546GB Combined Design Checklist Check Items Remarks Bob Smith termination: use four 75 Ω resistors for cable-side center taps and unused pins. This terminates pair-to-pair common mode impedance of the CAT5 cable. Bob Smith termination: use an EFT capacitor attached to the termination plane. Suggested values: 1500 pF/2 KV or 1000 pF/3 KV. This maintains greater than 25 mil spacing from capacitor to traces and components. Connect signal pairs correctly to RJ-45 connector. The differential pairs use pins 1 and 2 (transmit in 10/100 Mbps operation), 3 and 6 (receive in 10/100 Mbps), 4 and 5 (Gigabit Ethernet only), and 7 and 8 (Gigabit Ethernet only). Polarity should not be reversed. Provide a separate chassis ground, if possible, to connect the shroud of the RJ-45 connector and to terminate the line side of the magnetics module. This design improves EMI behavior. Place pads for approximately four stitching capacitors to bridge the gap from chassis ground to signal ground. Typical values range from 0.1 µF to 4.7 µF. This can be determined through experiments. Lay out the Bob Smith termination plane for designs with non-integrated magnetics modules. The termination plane floats over chassis ground. The splits in ground plane should be at least 50 mils to prevent arcing during hi-pot tests. √Done Comments Combined Layout Checklist Check Items Remarks Have up-to-date product documentation and specification updates Documents are subject to frequent change. Route the transmit and receive differential traces before routing the digital traces. Layout of differential traces is critical. Place the Ethernet silicon at least 1 inch from the edge of the board and at least 1 inch from any integrated magnetics module. With closer spacing, fields can follow the surface of the magnetics module or wrap past the edge of the board. EMI may increase. Optimum location is approximately 1 inch behind the magnetics module. √Done Comments 82545/82546—Design Guide Table 8. Section Combined Layout Checklist Check Items Place crystal and load capacitors within 0.75 inches from Ethernet device. Clock Source Remarks √Done Comments The Ethernet clock plays a key role in EMI. Keep clock lines away from other digital traces, I/O ports, board edge, transformers and differential pairs Ensure that the specification either meets or exceeds specifications listed in Section 4.3 if a crystal is being used. EEPROM and Flash Memory Transmit and Receive Differential Pairs Placement of these devices is not critical due to slow signal speeds. It is okay to place these devices a few inches away from the Ethernet controller or ICH to provide better spacing of critical components. Design traces for 100 Ω differential impedance (± 15%). This is a primary requirement for 10/100/1000 Mbps Ethernet. Paired 50 Ω traces do not make a 100 Ω differential. This should be verified with an impedance calculator. Use short traces. Trace length should be kept under 4 inches from the Ethernet controller through the magnetics to the RJ-45 connector. Avoid highly resistive traces. For example, 4 mil traces longer than 4 inches. If trace length is a problem, thicker board dielectrics can be used to allow wider traces. Thicker copper is even better than wider traces. Make traces symmetrical. If possible the pairs at the pads, vias and turns should match. Rules need to be established carefully for the autorouter. Asymmetry contributes to impedance mismatch. Do not make 90-degree bends. This can be addressed by beveled corners with turns based on 45degree angles Avoid through holes (vias). If using through holes (vias), the budget is two per trace. Keep traces close together within differential pairs. Traces must be kept within 30 mils regardless of trace geometry. Keep trace-to-trace length difference within each pair to less than 50 mils. This minimizes signal skew and common mode noise and improves long cable performance. Keep differential pairs 100 mils or more away from each other and away from parallel digital traces. This minimizes crosstalk and noise injection. 300 mil spacing is better. Guard traces are generally not recommended and will reduce the impedance if done incorrectly. 33 Design Guide—82545/82546 Table 8. Section Transmit and Receive Differential Pairs Magnetics Module Combined Layout Checklist Check Items Keep traces away from the board edge. This helps control EMI. Avoid unused pads and stubs along the traces. Zero Ω resistors should be used sparingly for dual footprint designs. Route traces on layers on appropriate layers. Pairs should be run on different layers as needed to improve routing. Layers adjacent to ground or power can be used. Make sure digital signals on adjacent layers cross at 90degree angles. Place termination resistors (and capacitors if applicable) as close as possible to Ethernet device. This prevents reflections. Symmetrical pads need to be used. Place capacitors connected to center taps very close to magnetics module. Keep the distance from the CTRL12/CTRL15/ CTRL18 output balls to the transistors very short (0.5 inches) and use 50 mil (minimum) wide traces when using the internal regulator control circuits of the controller with external PNP transistors. This reduces oscillation and ripple in the power supply. Use planes if possible. Narrow finger-like planes and very wide traces are allowed. Use decoupling and bulk capacitors generously. Decoupling and bulk capacitors should be placed close to Ethernet device, with some along every side, using short, wide traces and large vias. If power is distributed on traces, bulk capacitors should be used at both ends. If power is distributed on cards, bulk capacitors should be used at the connector. Place decoupling capacitors on LED lines carefully if they are used. Capacitors on LED lines should be placed near the LEDs. Provide a separate chassis ground island, if possible, to ground the shroud of the RJ-45 connector and to terminate the line side of the magnetics module. This design improves EMI behavior. The split in ground plane should be at least 50 mils. Split should run under center of magnetics module. Differential pairs never cross the split. Place 4 to 6 pairs of pads for stitching capacitors to bridge the gap from chassis ground to signal ground. Exact number and values empirically based on EMI performance should be determined. Power Supply and Signal Ground Chassis Ground 34 Remarks √Done Comments 82545/82546—Design Guide Table 8. Section Combined Layout Checklist Check Items Remarks Termination Plane Lay out Bob Smith termination plane for designs with nonintegrated magnetics modules. The termination plane floats over chassis ground. Splits in ground plane should be at least 50 mils. LED Circuits Keep LED traces away from sources of noise (for example, high speed digital traces running in parallel). LED traces can carry noise into integrated magnetics modules, RJ-45 connectors, or out to the edge of the board, increasing EMI. 8.0 √Done Comments Reference Design Schematic The following diagrams provide a representation of an Ethernet gigabit design using either the 82545EM/82545GM, 82546EB or 82546GB. It should be noted that if the 82546EB or 82546GB is used, the design uses less board space and is capable of fitting into less than seven square inches (including voltage regulators and a combination magnetics module/RJ-45 connector). The reference design provided is for illustration purposes only. Some of the components in the schematic may vary slightly (for example, the reference schematic does not contain voltage regulators). 8.1 82545EM(GM) Schematics The following pages contain reference schematics for an Ethernet design based on the 82545EM and 82545GM Gigabit Ethernet Controllers. Note: Applications using the SerDes interface should refer to the Designing SerDes-SerDes Interface with Intel® 82546GB Gigabit Ethernet Controller Application Note for more details and reference schematics. 35 36 PCI_AD[63..0] PCI_AD[63..0] LAN_PWR_GOOD is typically connected to RSM_RESET# in systems where all the power sources are available and known to ramp properly. In designs where some of the power sources are generated locally, additional circuitry may be required to hold LAN_PWR_GOOD inactive for a longer period. If the Ethernet controller is intended to wake up from powerdown states, LAN_PWR_GOOD must remain acive during powerdown. PCI add-on boards also call for presence detect and optional PCI-X capability connections. Make sure your design uses REQ64# and ACK64# pullups to comply to PCI 64-bit spec Follow recommendations in the PCI Local Bus Specification and the PCI-X Specification concerning board design and layout for the PCI/PCI-X bus. Connect VIO to 5V for a 5V PCI signaling environment, or to 3.3V for a 3.3V PCI signaling environment. ZN_COMP ZP_COMP VIO VIO SERR# PERR# CLK M66EN RST# INTA# NO_CONNECT REQ# GNT# REQ64# ACK64# LOCK# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# PAR PAR64 CBE0# CBE1# CBE2# CBE3# CBE4# CBE5# CBE6# CBE7# AUX_PWR LAN_PWR_GOOD PME# 82545 EM/GM U1A PCI_AD0 T14 PCI_AD1 V14 AD0 PCI_AD2 Y15 AD1 PCI_AD3 W14 AD2 PCI_AD4 T13 AD3 PCI_AD5 V13 AD4 PCI_AD6 Y14 AD5 PCI_AD7 U12 AD6 PCI_AD8 V12 AD7 PCI_AD9 T12 AD8 PCI_AD10 W12 AD9 PCI_AD11 Y12 AD10 PCI_AD12 V11 AD11 PCI_AD13 T11 AD12 PCI_AD14 Y11 AD13 PCI_AD15 W10 AD14 PCI_AD16 U8 AD15 PCI_AD17 Y7 AD16 PCI_AD18 Y6 AD17 PCI_AD19 V7 AD18 PCI_AD20 T7 AD19 PCI_AD21 W6 AD20 PCI_AD22 Y5 AD21 PCI_AD23 V6 AD22 PCI_AD24 U6 AD23 PCI_AD25 V5 AD24 PCI_AD26 W4 AD25 PCI_AD27 V4 AD26 PCI_AD28 Y3 AD27 PCI_AD29 U4 AD28 PCI_AD30 V3 AD29 PCI_AD31 V1 AD30 PCI_AD32 L16 AD31 PCI_AD33 M20 AD32 PCI_AD34 M19 AD33 PCI_AD35 M16 AD34 PCI_AD36 M18 AD35 PCI_AD37 M17 AD36 PCI_AD38 N20 AD37 PCI_AD39 N16 AD38 PCI_AD40 P20 AD39 PCI_AD41 N18 AD40 PCI_AD42 P19 AD41 PCI_AD43 P16 AD42 PCI_AD44 R20 AD43 PCI_AD45 P18 AD44 PCI_AD46 P17 AD45 PCI_AD47 T20 AD46 PCI_AD48 R16 AD47 PCI_AD49 U20 AD48 PCI_AD50 R18 AD49 PCI_AD51 T19 AD50 PCI_AD52 V20 AD51 PCI_AD53 T18 AD52 PCI_AD54 W20 AD53 PCI_AD55 V19 AD54 PCI_AD56 T17 AD55 PCI_AD57 U18 AD56 PCI_AD58 V18 AD57 PCI_AD59 U16 AD58 PCI_AD60 V17 AD59 PCI_AD61 W18 AD60 PCI_AD62 Y19 AD61 PCI_AD63 T16 AD62 AD63 AUX_PWR LAN_PWR_GOOD PME_N ZN_COMP ZP_COMP VIO VIO PCI_SERR_N PCI_PERR_N PCI_CLK PCI_M66EN PCI_RST_N PCI_INTA_N PCI_REQ_N PCI_GNT_N PCI_REQ64_N PCI_ACK64_N PCI_LOCK_N PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_IDSEL PCI_DEVSEL_N PCI_PAR PCI_PAR64 PCI_CBE_N0 PCI_CBE_N1 PCI_CBE_N2 PCI_CBE_N3 PCI_CBE_N4 PCI_CBE_N5 PCI_CBE_N6 PCI_CBE_N7 For Add-on boards: Capacitor required by PCI spec for signal integrity. Digital Input -Indicates if Aux Power is available. Allows controller to advertise D3 cold wake up capability. R3 A17 T4 T2 R5 Y1 Y20 T10 Y10 U2 Y16 T5 Y2 T1 W2 T3 U14 W16 Y9 V8 W8 Y8 V9 T6 T9 U10 V15 Y13 V10 T8 Y4 V16 Y18 Y17 T15 C52 0.01uF 10K R24 Monday, September 13, 2004 Document Number LAN_PWR_GOOD PME_N 3.3V_AUX PCI_SERR_N PCI_PERR_N PCI_CLK PCI_M66EN PCI_RST_N PCI_INTA_N PCI_REQ_N PCI_GNT_N PCI_REQ64_N PCI_ACK64_N PCI_LOCK_N PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_IDSEL PCI_DEVSEL_N PCI_PAR PCI_PAR64 PCI_CBE_N[7..0] SHEET: PCI INTERFACE Sheet 1 of 9 Rev 01 LAN_PWR_GOOD indicates that the LAN power supplies are good for operation in all modes, including powerdown if applicable. This signal acts like a LAN reset. 3.3V_AUX PCI_CBE_N[7..0] 82545EM/GM Gigabit Ethernet Controller Reference Design Date: Size A Title R25 35.7 1% R23 100K PCI ref (5V or 3.3V) Copyright (c) 2000-2004 Intel Corporation R22 22.6 1% C51 0.01uF 3.3V Design Guide—82545/82546 1 2 3 4 Select EEPROM carefully (see text). 93C66 VCC CS NC CLK ORG DI GND DO U2 EE_DI EE_DO EE_CS EE_SK C49 22pF 25.000 MHz 30ppm Y1 C50 22pF R21 2.49K 1% Flash ROM is not implemented for most LOM designs, because the Boot ROM code (PXE/Intel Boot Agent) is implemented in BIOS. For more information, refer to the Design Guide text. C48 0.01uF 8 7 6 5 25 MHz crystal is a critical component. Qualify carefully. Use short traces. 3.3V L4 E3 A3 A4 H16 G18 J16 H18 J17 J18 K17 K16 H20 K18 C17 F16 E18 E16 E15 E14 E13 D15 B16 F17 F18 G17 G16 B15 D19 D18 C15 D16 C18 D17 C19 B20 C20 D20 82545 EM/GM NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT FL_DATA0 NO_CONNECT FL_DATA1 NO_CONNECT FL_DATA2 NO_CONNECT FL_DATA3 NO_CONNECT FL_DATA4 FL_DATA5 ACT_# FL_DATA6 FL_DATA7 NO_CONNECT LINK# LINK100# XTAL1 LINK1000# XTAL2 NO_CONNECT NO_CNCT.NO_CONNECT NO_CONNECT REF FL_CS# FL_OE# FL_WE# SDPA0 SDPA1 SDPA6 SDPA7 FL_ADDR0 FL_ADDR1NO_CONNECT FL_ADDR2NO_CONNECT FL_ADDR3NO_CONNECT FL_ADDR4NO_CONNECT FL_ADDR5 SMBALRT# FL_ADDR6 SMBDAT FL_ADDR7 SMBCLK FL_ADDR8 FL_ADDR9 FL_ADDR10 MDI[0]FL_ADDR11 MDI[0]+ FL_ADDR12 MDI[1]FL_ADDR13 MDI[1]+ FL_ADDR14 MDI[2]FL_ADDR15 MDI[2]+ FL_ADDR16 MDI[3]FL_ADDR17 MDI[3]+ FL_ADDR18 EE_DI EE_DO EE_CS EE_SK U1B 4.7K R19 4.7K R20 MDI[0]MDI[0]+ MDI[1]MDI[1]+ MDI[2]MDI[2]+ MDI[3]MDI[3]+ LINK_N ACTIVITY_N Monday, September 13, 2004 Document Number SHEET: DATA INTERFACE Sheet 2 9 of 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation LINK_N ACTIVITY_N Rev 01 SMBALRT#/PCI_PWR_GOOD SMBDAT SMBCLK SMB_CLK, SMB_DAT, SMB_ALERT_N are open-drain I/Os and require 4.7K ohm pull-ups. Other LED drive configurations are possible. MDI[0]MDI[0]+ MDI[1]MDI[1]+ MDI[2]MDI[2]+ MDI[3]MDI[3]+ SMBALRT#/PCI_PWR_GOOD SMBDAT SMBCLK 4.7K R18 Software definable pins require modifications to software for implementation. 3.3V 3.3V 3.3V Date: Size A Title N1 B13 M1 N4 N3 A13 C14 C13 L3 K3 L1 K1 J2 J1 H3 J3 B1 B2 C1 C2 D1 D2 E1 E2 A16 A15 A14 G4 G5 E12 E11 D13 B12 C12 D12 82545/82546—Design Guide 37 38 1 2 2-PIN Header TP1 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N CLK_VIEW is a LAN clock test output for IEEE PHY conformance testing. The two pin header makes it easy to connect a probe. JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N R26 1K R28 1K R27 1K P3 P1 P4 P2 P5 N5 TEST# 82545 EM/GM CLK_VIEW JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# U3E A8 C58 0.01uF C57 0.01uF C55 0.01uF C59 0.01uF Date: Size A Title C56 0.01uF C60 0.01uF Monday, September 13, 2004 Document Number SHEET: TEST Sheet 3 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation 3.3V C54 0.01uF C53 0.01uF 3.3V of Use decoupling capacitors generously, placing them evenly around the 82545 EM/GM controller.At a minimum, use 1 bulk cap and 1 high frequency cap per side of the chip. Place caps as close to the chip as possible. 9 Rev 01 Design Guide—82545/82546 MDI[0]+ MDI[0]MDI[1]+ MDI[1]MDI[2]+ MDI[2]MDI[3]+ MDI[3]- 49.9 R10 49.9 R12 49.9 R14 MDI[2]+ MDI[3]+ 49.9 R15 C46 0.01uF MDI[1]+ C45 0.01uF 49.9 R13 49.9 R16 49.9 R17 C47 0.01uF MDI[0]+ C44 0.01uF 49.9 R11 Monday, September 13, 2004 Document Number SHEET: ETHERNET TERM Sheet 4 of 82545EM/GM Gigabit Ethernet Controller Reference Design Date: Size A Title Copyright (c) 2000-2004 Intel Corporation 9 Rev 01 82545/82546—Design Guide MDI[0]- MDI[1]- MDI[2]- MDI[3]- 39 40 LINK_N ACTIVITY_N MDI[0]+ MDI[0]MDI[1]+ MDI[1]MDI[2]+ MDI[2]MDI[3]+ MDI[3]- LINK_N ACTIVITY_N MDI[0]+ MDI[0]MDI[1]+ MDI[1]MDI[2]+ MDI[2]MDI[3]+ MDI[3]- 300 R9 300 R8 C41 470pF C42 470pF 3.3V C43 0.1uF S1A S2A A10 A11 A12 A9 A1 A2 A3 A4 A5 A6 A7 A8 Monday, September 13, 2004 Document Number SHEET: ETHERNET MAGJACKS Sheet 5 9 of 82545EM/GM Gigabit Ethernet Controller Reference Design Date: Size A Title Magnetics/RJ-45 SHLD1A SHLD2A CAT_ORN_A AN_A CAT_GRN_A CT_PT_A TD1+PT_A TD1-PT_A TD2+PT_A TD2-PT_A TD3+PT_A TD3-PT_A TD4+PT_A TD4-PT_A J1A Termination plane and components are contained in the integrated magnetics module/RJ-45 connector. Copyright (c) 2000-2004 Intel Corporation 2.5V Rev 01 Design Guide—82545/82546 C14 10uF C15 10uF C31 10uF C29 4.7uF C32 10uF C30 0.01uF 2.5V 2.5V C39 10uF C37 10uF C35 4.7uF C40 10uF C38 10uF C36 0.01uF Place caps as close to device as possible, using vias directly to 2.5V plane. Exact number of caps required may be fewer than shown. 2.5V 2.5V 2.5V If using regulators, both 2.5V planes may be connected. If using the integrated CTRL_xxx circuitry with external power transistors, the AVDDLA and AVDDLB planes must be separate. All 3.3V balls may be connected to the same power plane. 3.3V C16 10uF A1 A2 A5 A10 B3 B6 B11 B17 C3 D3 D8 D14 E19 F3 G10 G11 H2 H9 H10 H11 H12 H17 J8 L2 L5 L18 A19 G1 G2 G3 B4 F1 B8 B14 B19 C10 C16 D6 D11 E17 H4 H19 L17 M2 N19 R4 R17 U1 U3 U7 U11 U15 U19 W1 W5 W9 W13 W17 CTRL_25 CTRL_15 DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NO_CONNECT NO_CONNECT 82545 EM/GM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDL AVDDH AVDDH VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO U1C K7 K8 K9 K10 K11 K12 K13 K14 L7 L8 L9 L10 L11 L12 L13 L14 J9 J10 J11 J12 J13 K2 K4 K5 L20 H5 F2 A18 G7 G8 G9 G12 G13 G14 H7 H8 H13 H14 J7 J14 M7 M14 N7 N8 N13 N14 P7 P8 P9 P12 P13 P14 C18 0.01uF C10 0.01uF R6 R5 5.1K R4 1.0 (1W) C25 0.01uF C20 10uF C12 10uF C21 10uF C26 10uF C27 0.01uF 1.5V 1.5V C13 10uF C28 4.7uF C33 0.01uF Date: Size A Monday, September 13, 2004 Document Number 2.5V SHEET: POWER, LED, GND Sheet 6 9 of 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation Title C34 4.7uF 1.5V Gain characteristics for transistor Q1 are critical. Q2 BCP69T1 Gain characteristics for transistor Q1 are critical. Q1 BCP69-16 C24 0.01uF C19 0.01uF C11 0.01uF 15K 1% 3.3V Do Not Populate resistor for R7 82545GM. Populate 5.1K Do not for 82545EM populate according to TA 148. Do not populate 3.3V C22 C23 0.01uF 0.01uF C17 0.01uF C9 0.01uF 1.5V Rev 01 82545/82546—Design Guide 41 42 3.3V 3.3V 3.3V 3.3V C7 0.01uF C5 0.01uF C3 0.01uF C1 0.01uF 3.3V 3.3V 3.3V 3.3V C8 0.01uF C6 0.01uF C4 0.01uF C2 0.01uF L19 M4 M8 M9 M10 M11 M12 M13 N9 N10 N11 N12 N17 P10 P11 R2 R19 U5 U9 U13 U17 V2 W3 W7 W11 W15 W19 SIG_DETECT RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13 RESERVED14 RESERVED15 RESERVED16 RESERVED17 RESERVED18 RESERVED19 RESERVED20 RESERVED21 RESERVED22 RESERVED23 RESERVED24 RESERVED25 RESERVED26 RESERVED27 RESERVED28 RESERVED29 RESERVED30 NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT 82545 EM/GM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U1D R3 1K E20 D4 D5 C4 E4 C5 E5 B5 E6 D7 C7 E10 B7 A7 C8 E8 E9 D9 C9 B9 D10 A9 C11 B10 C6 A20 B18 M5 E7 A6 R1 L20 A11 A12 F4 F5 F19 F20 G19 G20 H1 J4 J5 J19 J20 K19 K20 L4 M3 N2 R2 1K Date: Size A Title Monday, September 13, 2004 Document Number SHEET: GND, NC, RESERVED Sheet 7 9 of 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation R1 1K The unconnected reserved pins may be connected to GND or left floating. The reserved pins shown connected to ground is the minimum that is required. Do not attach pulll up resistors, pull down resistors, or any other circuitry to leads designated as No Connect. Rev 01 Design Guide—82545/82546 PCI_5V If the Aux Power budget is sufficient to power normal operation, do not stuff D2 or D1, and instead stuff a zero Ohm Resistor. If the Aux Power budget is only sufficient for lower power operation, stuff D1 and D2 and do not stuff the resistor. This will enable 5V supply for normal operation and 3.3VAux for lowpower mode. If you chose to use 3.3V system power instead of the 5V power, you will have to redesign the circuit. 3.3V_AUX LAN_PWR_GOOD DIODE D2 C64 DIODE D1 0 Ohms R31 C68 Power Supervisor GND VCC RST# U5 R34 0 Ohms If the system will not support wake up from a low power state, you can eliminate this circuity and diode D1. You may also choose to use PCI_3.3V or 3.3VAux instead of PCI_5V. C66 C67 2.5V R33 20K R32 10K C62 1 2 3 4 C63 3.3V GND Linear Regulator EN VIN VOUT VADJ U6 R30 20K R29 10K 5 1 2 3 4 5 Date: Size A Monday, September 13, 2004 Document Number Sheet 9 Title 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation Leave some stuffing options (R's, D's) to control the current into your regulators. R35 0 Ohms GND Linear Regulator EN VIN VOUT VADJ U4 ALTERNATIVE LAN power circuit Layout Note: Place bypass/filter caps close to indicated part. Low impedance connections essential. C65 C61 1.5V of 9 Rev 01 82545/82546—Design Guide 43 44 Do Not stuff for 82545EM September 13, 2004 + Changed 1/2 W rating to 1W for resistor on 1.5 V control circuitry + Added note on minimum voltage rating of 2kV on caps between chassis ground and signal ground. + Part reference designators may not match with older revision history items above as they were refreshed to remove duplicates. + Changed stuffing option to CTRL_XX lines to reflect the fact that the Rb pull-up resistors on linear reg PNP not needed; improving circuit startup in presence of occasional DPM units. February 13, 2004 + Removed incorrect EEPROM statement. November 21, 2003 + Removed excess resistors on RESERVED pins. + Changed ZN_COMP and ZP_COMP resistor values. August 26, 2003 + Added node on Power page: Only stuff R10 for 82545GM. August 20, 2003 + Modified power sheet (sheet 6) Ctrl_15 to reflect design differences between 82545EM and 82545GM. Nov 15 2002 + Created 82545 schematic Dec 03 2002 + Added changes based on 82545 EM GbE Spec UPdate rev 1.0 Date: Size A Monday, September 13, 2004 Document Number Sheet 9 Title 82545EM/GM Gigabit Ethernet Controller Reference Design Copyright (c) 2000-2004 Intel Corporation of 9 Rev 01 Design Guide—82545/82546 82545/82546—Design Guide 8.2 82546EB(GB) Schematics The following pages contain a reference schematic for a dual port gigabit Ethernet design based on the 82546EB and 82546GB Dual Port Gigabit Ethernet Controllers. Note: Applications using the SerDes interface should refer to the Designing SerDes-SerDes Interface with Intel® 82546GB Gigabit Ethernet Controller Application Note for more details and reference schematics. 45 46 PCI_AD[63..0] PCI_AD[63..0] LAN_PWR_GOOD is typically connected to RSM_RESET# in systems where all the power sources are available and known to ramp properly. In designs where some of the power sources are generated locally, additional circuitry may be required to hold LAN_PWR_GOOD inactive for a longer period. If the Ethernet controller is intended to wake up from powerdown states, LAN_PWR_GOOD must remain acive during powerdown. PCI add-on boards also call for presence detect and optional PCI-X capability connections. Make sure your design uses REQ64# and ACK64# pullups to comply to PCI 64-bit spec Follow recommendations in the PCI Local Bus Specification and the PCI-X Specification concerning board design and layout for the PCI/PCI-X bus. Connect VIO to 5V for a 5V PCI signaling environment, or to 3.3V for a 3.3V PCI signaling environment. ZN_COMP ZP_COMP VIO VIO SERR# PERR# CLK M66EN RST# INTA# INTB# REQ# GNT# REQ64# ACK64# LOCK# FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# PAR PAR64 CBE0# CBE1# CBE2# CBE3# CBE4# CBE5# CBE6# CBE7# AUX_PWR LAN_PWR_GOOD PME# 82546EB/GB U1A PCI_AD0 T14 PCI_AD1 V14 AD0 PCI_AD2 Y15 AD1 PCI_AD3 W14 AD2 PCI_AD4 T13 AD3 PCI_AD5 V13 AD4 PCI_AD6 Y14 AD5 PCI_AD7 U12 AD6 PCI_AD8 V12 AD7 PCI_AD9 T12 AD8 PCI_AD10 W12 AD9 PCI_AD11 Y12 AD10 PCI_AD12 V11 AD11 PCI_AD13 T11 AD12 PCI_AD14 Y11 AD13 PCI_AD15 W10 AD14 PCI_AD16 U8 AD15 PCI_AD17 Y7 AD16 PCI_AD18 Y6 AD17 PCI_AD19 V7 AD18 PCI_AD20 T7 AD19 PCI_AD21 W6 AD20 PCI_AD22 Y5 AD21 PCI_AD23 V6 AD22 PCI_AD24 U6 AD23 PCI_AD25 V5 AD24 PCI_AD26 W4 AD25 PCI_AD27 V4 AD26 PCI_AD28 Y3 AD27 PCI_AD29 U4 AD28 PCI_AD30 V3 AD29 PCI_AD31 V1 AD30 PCI_AD32 L16 AD31 PCI_AD33 M20 AD32 PCI_AD34 M19 AD33 PCI_AD35 M16 AD34 PCI_AD36 M18 AD35 PCI_AD37 M17 AD36 PCI_AD38 N20 AD37 PCI_AD39 N16 AD38 PCI_AD40 P20 AD39 PCI_AD41 N18 AD40 PCI_AD42 P19 AD41 PCI_AD43 P16 AD42 PCI_AD44 R20 AD43 PCI_AD45 P18 AD44 PCI_AD46 P17 AD45 PCI_AD47 T20 AD46 PCI_AD48 R16 AD47 PCI_AD49 U20 AD48 PCI_AD50 R18 AD49 PCI_AD51 T19 AD50 PCI_AD52 V20 AD51 PCI_AD53 T18 AD52 PCI_AD54 W20 AD53 PCI_AD55 V19 AD54 PCI_AD56 T17 AD55 PCI_AD57 U18 AD56 PCI_AD58 V18 AD57 PCI_AD59 U16 AD58 PCI_AD60 V17 AD59 PCI_AD61 W18 AD60 PCI_AD62 Y19 AD61 PCI_AD63 T16 AD62 AD63 R35 22.6 1% AUX_PWR LAN_PWR_GOOD PME_N R38 35.7 1% For Add-on boards: Capacitor required by PCI spec for signal integrity. LAN_PWR_GOOD PME_N 3.3V_AUX PCI_SERR_N PCI_PERR_N PCI_CLK PCI_M66EN PCI_RST_N PCI_INTA_N PCI_INTB_N PCI_REQ_N PCI_GNT_N PCI_REQ64_N PCI_ACK64_N PCI_LOCK_N PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_IDSEL PCI_DEVSEL_N PCI_PAR PCI_PAR64 PCI_CBE_N[7..0] Monday, September 13, 2004 Document Number 10442 SHEET: PCI INTERFACE Sheet 1 of 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design 9 Rev 06 LAN_PWR_GOOD indicates that the LAN power supplies are good for operation in all modes, including powerdown if applicable. This signal acts like a LAN reset. 3.3V_AUX Copyright (c) 2000-2004 Intel Corporation Date: Size A Title C57 0.01uF 10K PCI_CBE_N[7..0] ZN_COMP ZP_COMP R36 100K PCI ref (5V or 3.3V) R37 C56 0.01uF 3.3V VIO VIO PCI_SERR_N PCI_PERR_N PCI_CLK PCI_M66EN PCI_RST_N PCI_INTA_N PCI_INTB_N PCI_REQ_N PCI_GNT_N PCI_REQ64_N PCI_ACK64_N PCI_LOCK_N PCI_FRAME_N PCI_IRDY_N PCI_TRDY_N PCI_STOP_N PCI_IDSEL PCI_DEVSEL_N PCI_PAR PCI_PAR64 PCI_CBE_N0 PCI_CBE_N1 PCI_CBE_N2 PCI_CBE_N3 PCI_CBE_N4 PCI_CBE_N5 PCI_CBE_N6 PCI_CBE_N7 Digital Input -Indicates if Aux Power is available. Allows controller to advertise D3 cold wake up capability. R3 A17 T4 T2 R5 Y1 Y20 T10 Y10 U2 Y16 T5 Y2 T1 W2 T3 U14 W16 Y9 V8 W8 Y8 V9 T6 T9 U10 V15 Y13 V10 T8 Y4 V16 Y18 Y17 T15 Design Guide—82545/82546 93C66 VCC CS NC CLK ORG DI GND DO 1 2 3 4 Select EEPROM carefully (see text). 8 7 6 5 U2 EE_DI EE_DO EE_CS EE_SK C54 22pF 25.000 MHz 30ppm Y1 C55 22pF R34 R33 2.49K 1% 2.49K 1% Flash ROM is not implemented for most LOM designs, because the Boot ROM code (PXE/Intel Boot Agent) is implemented in BIOS. For more information, refer to the Design Guide text. C53 0.01uF 25 MHz crystal is a critical component. Qualify carefully. Use short traces. Refer to Intel Ap-note 419. 3.3V L4 E3 A3 A4 H16 G18 J16 H18 J17 J18 K17 K16 H20 K18 C17 F16 E18 E16 E15 E14 E13 D15 B16 F17 F18 G17 G16 B15 D19 D18 C15 D16 C18 D17 C19 B20 C20 D20 82546EB/GB REFB REFA XTAL1 XTAL2 FL_DATA0 FL_DATA1 FL_DATA2 FL_DATA3 FL_DATA4 FL_DATA5 FL_DATA6 FL_DATA7 FL_CS# FL_OE# FL_WE# FL_ADDR0 FL_ADDR1 FL_ADDR2 FL_ADDR3 FL_ADDR4 FL_ADDR5 FL_ADDR6 FL_ADDR7 FL_ADDR8 FL_ADDR9 FL_ADDR10 FL_ADDR11 FL_ADDR12 FL_ADDR13 FL_ADDR14 FL_ADDR15 FL_ADDR16 FL_ADDR17 FL_ADDR18 EE_DI EE_DO EE_CS EE_SK U1B ACT_A# ACT_B# LINKA# LINKA100# LINKA1000# LINKB# LINKB100# LINKB1000# MDIB[0]MDIB[0]+ MDIB[1]MDIB[1]+ MDIB[2]MDIB[2]+ MDIB[3]MDIB[3]+ MDIA[0]MDIA[0]+ MDIA[1]MDIA[1]+ MDIA[2]MDIA[2]+ MDIA[3]MDIA[3]+ SMBALRT# SMBDAT SMBCLK SDPA0 SDPA1 SDPA6 SDPA7 SDPB0 SDPB1 SDPB6 SDPB7 4.7K R30 3.3V 4.7K R31 3.3V 4.7K R32 PORT2_LINK_N PORT1_ACTIVITY_N PORT2_ACTIVITY_N PORT1_LINK_N PORT2_MDI[0]PORT2_MDI[0]+ PORT2_MDI[1]PORT2_MDI[1]+ PORT2_MDI[2]PORT2_MDI[2]+ PORT2_MDI[3]PORT2_MDI[3]+ PORT1_MDI[0]PORT1_MDI[0]+ PORT1_MDI[1]PORT1_MDI[1]+ PORT1_MDI[2]PORT1_MDI[2]+ PORT1_MDI[3]PORT1_MDI[3]+ Copyright (c) 2000-2004 Intel Corporation Date: Size A Monday, September 13, 2004 Document Number 10442 SHEET: DATA INTERFACE Sheet 2 9 of Rev 06 SMBALRT#/PCI_PWR_GOOD SMBDAT SMBCLK SMB_CLK, SMB_DAT, SMB_ALERT_N are open-drain I/Os and require 4.7K ohm pull-ups. Other LED drive configurations are possible. PORT2_LINK_N PORT1_ACTIVITY_N PORT2_ACTIVITY_N PORT1_LINK_N PORT2_MDI[0]PORT2_MDI[0]+ PORT2_MDI[1]PORT2_MDI[1]+ PORT2_MDI[2]PORT2_MDI[2]+ PORT2_MDI[3]PORT2_MDI[3]+ PORT1_MDI[0]PORT1_MDI[0]+ PORT1_MDI[1]PORT1_MDI[1]+ PORT1_MDI[2]PORT1_MDI[2]+ PORT1_MDI[3]PORT1_MDI[3]+ SMBALRT#/PCI_PWR_GOOD SMBDAT SMBCLK 3.3V Title 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design N1 B13 M1 N4 N3 A13 C14 C13 L3 K3 L1 K1 J2 J1 H3 J3 B1 B2 C1 C2 D1 D2 E1 E2 A16 A15 A14 G4 G5 E12 E11 D13 B12 C12 D12 Software definable pins require modifications to software for implementation. 82545/82546—Design Guide 47 48 1 2 2-PIN Header TP1 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N CLK_VIEW is a LAN clock test output for IEEE PHY conformance testing. The two pin header makes it easy to connect a probe. JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N R39 1K R41 1K R40 1K P3 P1 P4 P2 P5 N5 TEST# 82546EB/GB CLK_VIEW JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST# U1E A8 C63 0.01uF C62 0.01uF C60 0.01uF C64 0.01uF C61 0.01uF C65 0.01uF Date: Size A Monday, September 13, 2004 Document Number 10442 SHEET: TEST Sheet 3 of Title 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Copyright (c) 2000-2004 Intel Corporation 3.3V C59 0.01uF C58 0.01uF 3.3V 9 Use decoupling capacitors generously, placing them evenly around the controller. At a minimum, use 1 bulk cap and 1 high frequency cap per side of the chip. Place caps as close to the chip as possible. Rev 06 Design Guide—82545/82546 Resistors are 1% tolerance PORT2_MDI[0]+ PORT2_MDI[0]PORT2_MDI[1]+ PORT2_MDI[1]PORT2_MDI[2]+ PORT2_MDI[2]PORT2_MDI[3]+ PORT2_MDI[3]- PORT1_MDI[0]+ PORT1_MDI[0]PORT1_MDI[1]+ PORT1_MDI[1]PORT1_MDI[2]+ PORT1_MDI[2]PORT1_MDI[3]+ PORT1_MDI[3]- 49.9 R14 49.9 R16 49.9 R18 49.9 R20 PORT2_MDI[0]+ PORT2_MDI[1]+ PORT2_MDI[2]+ PORT2_MDI[3]+ C49 0.01uF 49.9 R23 49.9 R24 C50 0.01uF 49.9 R25 PORT1_MDI[1]- PORT1_MDI[2]- 49.9 R28 Date: Monday, September 13, 2004 Document Number 10442 SHEET: ETHERNET TERM Sheet 4 of 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Copyright (c) 2000-2004 Intel Corporation C51 0.01uF 49.9 R27 PORT1_MDI[0]- Size A Title 49.9 R26 PORTS 1 & 2 49.9 R22 PORT1_MDI[3]+ C48 0.01uF 49.9 R21 PORT1_MDI[2]+ C47 0.01uF 49.9 R19 PORT1_MDI[1]+ C46 0.01uF 49.9 R17 49.9 R29 9 Rev 06 C52 0.01uF PORT1_MDI[0]+ C45 0.01uF 49.9 R15 82545/82546—Design Guide PORT1_MDI[3]- PORT2_MDI[0]- PORT2_MDI[1]+ PORT2_MDI[2]- PORT2_MDI[3]- 49 50 PORT1_LINK_N PORT1_ACTIVITY_N PORT1_MDI[0]+ PORT1_MDI[0]PORT1_MDI[1]+ PORT1_MDI[1]PORT1_MDI[2]+ PORT1_MDI[2]PORT1_MDI[3]+ PORT1_MDI[3]- PORT2_LINK_N PORT2_ACTIVITY_N PORT2_MDI[0]+ PORT2_MDI[0]PORT2_MDI[1]+ PORT2_MDI[1]PORT2_MDI[2]+ PORT2_MDI[2]PORT2_MDI[3]+ PORT2_MDI[3]- PORT2_LINK_N PORT2_ACTIVITY_N PORT2_MDI[0]+ PORT2_MDI[0]PORT2_MDI[1]+ PORT2_MDI[1]PORT2_MDI[2]+ PORT2_MDI[2]PORT2_MDI[3]+ PORT2_MDI[3]- PORTS 1 & 2 PORT1_LINK_N PORT1_ACTIVITY_N PORT1_MDI[0]+ PORT1_MDI[0]PORT1_MDI[1]+ PORT1_MDI[1]PORT1_MDI[2]+ PORT1_MDI[2]PORT1_MDI[3]+ PORT1_MDI[3]- 300 R13 300 R11 300 R12 300 R10 3.3V 2.5V B C44 0.1uF C43 0.1uF S1B S2B B10 B11 B12 B9 B1 B2 B3 B4 B5 B6 B7 B8 S1A S2A A10 A11 A12 A9 A1 A2 A3 A4 A5 A6 A7 A8 Magnetics/RJ-45 Dual SHLD1B SHLD2B CAT_ORN_B AN_B CAT_GRN_B CT_PT_B TD1+PT_B TD1-PT_B TD2+PT_B TD2-PT_B TD3+PT_B TD3-PT_B TD4+PT_B TD4-PT_B J1B Magnetics/RJ-45 Dual SHLD1A SHLD2A CAT_ORN_A AN_A CAT_GRN_A CT_PT_A TD1+PT_A TD1-PT_A TD2+PT_A TD2-PT_A TD3+PT_A TD3-PT_A TD4+PT_A TD4-PT_A J1A Termination plane and components are contained in the integrated magnetics module/RJ-45 connector. Monday, September 13, 2004 Document Number 10442 SHEET: ETHERNET MAGJACKS of Sheet 5 9 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Copyright (c) 2000-2004 Intel Corporation Date: Size A Title 2.5V A Rev 06 Design Guide—82545/82546 C9 10uF C10 10uF C31 10uF C29 4.7uF C32 10uF C30 0.01uF 2.5V B 2.5V B C41 10uF C39 10uF C35 4.7uF C42 10uF C40 10uF C36 0.01uF Place caps as close to device as possible, using vias directly to 2.5V plane. Exact number of caps required may be fewer than shown. 2.5V B 2.5V A 2.5V A If using regulators, both 2.5V planes may be connected. If using the integrated CTRL_xxx circuitry with external power transistors, the AVDDLA and AVDDLB planes must be separate. All 3.3V balls may be connected to the same power plane. 3.3V C11 10uF A1 A2 A5 A10 B3 B6 B11 B17 C3 D3 D8 D14 E19 F3 G10 G11 H2 H9 H10 H11 H12 H17 J8 L2 L5 L18 A19 G1 G2 G3 B4 F1 B8 B14 B19 C10 C16 D6 D11 E17 H4 H19 L17 M2 N19 R4 R17 U1 U3 U7 U11 U15 U19 W1 W5 W9 W13 W17 82546EB/GB GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AVDDLB AVDDLB AVDDLB AVDDLA AVDDLA AVDDLA AVDDLA AVDDH AVDDH VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO VDDO U1C GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CTRL_25B CTRL_25A CTRL_15 DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD J9 J10 J11 J12 J13 K2 K4 K5 K7 K8 K9 K10 K11 K12 K13 K14 L7 L8 L9 L10 L11 L12 L13 L14 H5 F2 A18 G7 G8 G9 G12 G13 G14 H7 H8 H13 H14 J7 J14 M7 M14 N7 N8 N13 N14 P7 P8 P9 P12 P13 P14 C25 0.01uF C20 10uF C15 10uF C27 0.01uF 1.5V 1.5V C26 10uF C21 10uF C16 10uF C28 4.7uF R9 5.1K Q2 BCP69T1 Q3 BCP69T1 C33 0.01uF C34 4.7uF 1.5V C37 0.01uF C38 4.7uF 2.5V A Monday, September 13, 2004 Document Number 10442 SHEET: POWER, LED, GND Sheet 6 9 of 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Copyright (c) 2000-2004 Intel Corporation Date: Size A Title Do not populate 3.3V R8 5.1K Do not populate Gain characteristics for transistor Q1 are critical. Q1 BCP69-16 C24 0.01uF C19 0.01uF C14 0.01uF 3.3V 1.0 (1W) 30.1K 1% R7 R6 5.1K R5 C23 0.01uF C18 0.01uF C13 0.01uF Do Not Populate resistor for 82546GB Populate according to TA 149 for 82546EB Do not populate 3.3V C22 0.01uF C17 0.01uF C12 0.01uF 1.5V Rev 06 2.5V B 82545/82546—Design Guide 51 52 3.3V 3.3V 3.3V 3.3V C7 0.01uF C5 0.01uF C3 0.01uF C1 0.01uF 3.3V 3.3V 3.3V 3.3V C8 0.01uF C6 0.01uF C4 0.01uF C2 0.01uF L19 M4 M8 M9 M10 M11 M12 M13 N9 N10 N11 N12 N17 P10 P11 R2 R19 U5 U9 U13 U17 V2 W3 W7 W11 W15 W19 RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 RESERVED7 RESERVED8 RESERVED9 RESERVED10 RESERVED11 RESERVED12 RESERVED13 RESERVED14 RESERVED15 RESERVED16 RESERVED17 RESERVED18 RESERVED19 RESERVED20 RESERVED21 RESERVED22 RESERVED23 RESERVED24 RESERVED25 RESERVED26 RESERVED27 RESERVED28 RESERVED29 NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT NO_CONNECT TXB+ TXBRXB+ RXBSIG_DETECT_B TXA+ TXARXA+ RXASIG_DETECT_A 82546EB/GB GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND U1D D4 D5 C4 E4 C5 E5 B5 E6 D7 C7 E10 B7 A7 C8 E8 E9 D9 C9 B9 D10 A9 C11 B10 C6 A20 B18 M5 E7 A6 R1 A11 A12 F4 F5 H1 J4 J5 M3 N2 K19 K20 J19 J20 L20 F19 F20 G19 G20 E20 R1 1K Copyright (c) 2000-2004 Intel Corporation R3 1K R2 1K Monday, September 13, 2004 Document Number 10442 SHEET: GND, NC, RESERVED Sheet 7 9 of 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Date: Size A Title R4 1K The unconnected reserved pins may be connected to GND or left floating. The reserved pins shown connected to ground is the minimum that is required. Do not attach pull up resistors, pull down resistors, or any other circuitry to leads designated as No Connect. Rev 06 Design Guide—82545/82546 PCI_5V If the Aux Power budget is sufficient to power normal operation, do not stuff D2 or D1, and instead stuff a zero Ohm Resistor. If the Aux Power budget is only sufficient for lower power operation, stuff D1 and D2 and do not stuff the resistor. This will enable 5V supply for normal operation and 3.3VAux for lowpower mode. If you chose to use 3.3V system power instead of the 5V power, you will have to redesign the circuit. 3.3V_AUX LAN_PWR_GOOD DIODE D2 C69 DIODE D1 0 Ohms R44 C73 Power Supervisor GND VCC RST# U4 R47 0 Ohms If the system will not support wake up from a low power state, you can eliminate this circuity and diode D1. You may also choose to use PCI_3.3V or 3.3VAux instead of PCI_5V. C71 C72 2.5V A C67 R46 20K 1 2 3 4 3.3V C68 R45 10K 2.5V B GND Linear Regulator EN VIN VOUT VADJ U5 R43 20K R42 10K 5 1 2 3 4 5 Date: Size A Monday, September 13, 2004 Document Number 10442 SHEET: SUPPLY Sheet 8 of Title 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design Copyright (c) 2000-2004 Intel Corporation Leave some stuffing options (R's, D's) to control the current into your regulators. R48 0 Ohms GND Linear Regulator EN VIN VOUT VADJ U3 ALTERNATIVE LAN power circuit Layout Note: Place bypass/filter caps close to indicated part. Low impedance connections essential. C70 C66 1.5V 9 Rev 06 82545/82546—Design Guide 53 54 Semptember 13, 2004 + Changed 1/2 W rating to 1W for resistor on 1.5 V control circuitry + Added note on minimum voltage rating of 2kV on caps between chassis ground and signal ground. + Part reference designators may not match with older revision history items above as they were refreshed to remove duplicates. + Changed stuffing option to CTRL_XX lines to reflect the fact that the Rb pull-up resistors on linear reg PNP not needed; improving circuit startup in presence of occasional DPM units. February 13, 2004 + Removed incorrect statement on EEPROM. November 21, 2003 + Changed to minimal required pulldowns for RESERVED pins August 26, 2003 + Added note to power page: Only stuff R10 for 82546GB. Do Not stuff for 82546EB +Changed Zn_comp resistor = 22.6 and Zp_comp resistor = 35.7 August 20, 2003 + Modified power sheet (sheet 6) Ctrl_15 to reflect design differences between 82546EB and 82546GB. June 3 2003 + Modified to support 82546EB and GB June 3, 2002 + Removed duplicate Ball B18 and added Ball B11 (GND) + Connected Balls J9, J10, J11 to GND + Connected Reserved[28:27} to GND through single pulldown resistor + Connected Ball L20 to GND + Connected CLK_VIEW to 2-pin header for ease of use + Indicated SERDES pins (not used in this design) + Changed TEST ball to TEST# + Changed JTAG_TCK from pull-up to pull-down for consistency with other designs + Changed resistor in Q1 circuit for erratum and added note concerning Q1 parameters + Removed R7, an unneeded pulldown resistor on the EEPROM DO line. + Added more comments and clarification to EEPROM, power, LAN_PWR_GOOD March 8, 2002 + Added workaround to 1.5V regulator circuit October 31, 2001 + Various corrections and clarifications August 15, 2001 + Changed various ball references + Removed 1.5 and 2.5 V regulators and replaced with power transistors + Left Sheet 8 in, just in case a designer choses not to use the internal power control function; otherwise it is not necessary July 31, 2001 + Sheet 1: Note on VIO power PCI reference (5V or 3.3V), see section 3.2.1 July 10, 2001 + Sheet 2: Deleted the PORT1 prefixes on the netnames for the EEPROM. + Sheet 2: PCI_PWR_GOOD shouldbe tied off to avoid a floating input... added note + Sheet 2: SMB_CLK, SMB_DAT, SMB_ALERT_N should be pulled high when not used. + Sheet 3: Cleaned up extra dots on the connections to the Anvik symbol and added pin numbers. + Sheet 3: Clarified the capacitor pack comment -- we don't intend to promote capacitor arrays. + Sheet 7: Added pin reference numbers to the Reserved pins + Sheet 8: Various changes Copyright (c) 2000-2004 Intel Corporation Date: Size A Monday, September 13, 2004 Document Number 10442 Sheet 9 of Title 82546EB/GB Gigabit Ethernet Controller Dual Port Reference Design 9 Rev 06 Design Guide—82545/82546 82545/82546—Design Guide Appendix A Measuring LAN Reference Frequency Using a Frequency Counter A.1 Background To comply with IEEE specifications for 10/100 Mbps and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be correct and accurate within ±50 parts per million (ppm). Note: Intel recommends a frequency tolerance of ±30 (ppm). Most Intel LAN devices will operate properly with a 25.000 MHz reference crystal, provided it meets the recommended requirements for frequency stability, equivalent series resistance at resonance (ESR), and load capacitance. Most circuits for series resonant crystals include two discrete capacitors (typically C1 and C2), with values between 5 pF and 36 pF. The most accurate way to determine the appropriate value for the discrete capacitors is to install the approximately correct values for C1 and C2. Next, a frequency counter should be used to measure the transmitter reference frequency (or transmitter reference clock). • If the transmitter reference frequency is more than 20 ppm below the target frequency, then the values for C1 and C2 are too big and should be decreased. • If the transmitter reference frequency is more than 20 ppm above the target frequency, then the values for C1 and C2 are too small and should be increased. This Appendix provides instructions and illustrations that explain how to use a frequency counter and probe to determine the Ethernet LAN device transmit center frequency. An example describing how to calculate the frequency accuracy of the measured and averaged center frequency with respect to the target center frequency is also included. A.2 Required Test Equipment • Tektronix CMC-251, or similar high resolution, digital counter • Tektronix P6246, or similar high bandwidth, low capacitance (less than 1 pF) probe • Tektronix 1103, or similar probe power supply or probe amplifier • BNC, 50-ohm coaxial cable (less than 6 feet long) • System with power supply and test software for the LAN circuit to be tested A.3 Indirect Probing Method The indirect probing test method is applicable foremost devices that support 100BASET. Since probe capacitance can load the reference crystal and affect the measured frequency, the preferred method is to use the indirect probing test method when possible. Almost all Intel LAN silicon that support 1000BASE-T Ethernet can provide a buffered 125 MHz clock, which can be used for indirect probing of the transmitter reference clock. The buffered 125 MHz clock will be a 5X multiple of the crystal circuit’s reference frequency (Figure 7). 55 Design Guide—82545/82546 Different LAN devices may require different register settings, to enable the buffered 125 MHz reference frequency. Please obtain the settings or instructions that are appropriate for the LAN device you are using. LAN Silicon IEEE Test Out + 2-pin header input P6246 or similar high impedance probe with less than 1 pF Ch.1 input Ch.2 LAN Silicon IEEE Test Out - Tektronix 1103 Probe Power Supply 50 ohm Coaxial Cable 50 ohm input 125.00047 Tektronix CMC251 or a similar capability Frequency Counter A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN device enabled. 2. Connect the test equipment as shown in Figure 7. 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 MHz with at least four decimal places frequency resolution. 4. Enable the 125 MHz buffered reference clock. 5. Determine the center reference frequency as accurately as possible. This can be done by taking 30 to 50 different readings using the frequency counter and then calculating the average results of the readings. 6. Calculate the accuracy of the measured and averaged center frequency with respect to an ideal 125.0000 MHz reference frequency. Figure 7. Indirect Probing Setup (x – y) FrequencyAccuracy ( ppm ) = -----------------------------( y § 1000000 ) where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz 56 82545/82546—Design Guide Example 1. Given: The measured averaged center frequency is 124.99942 MHz (or 124,999,420 Hertz). ( 124999420 – 125000000 ) FrequencyAccuracy ( ppm ) = --------------------------------------------------------- = – 4.64ppm ( 125000000 § 1000000 ) Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). ( 125000870 – 125000000 ) FrequencyAccuracy ( ppm ) = --------------------------------------------------------- = 6.96ppm ( 125000000 § 1000000 ) Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board. • If the transmitter reference frequency is more than 8 ppm below the target frequency, then the values for C1 and C2 are too big and they should be decreased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. • If the transmitter reference frequency is more than 8 ppm above the target frequency, then the values for C1 and C2 are too small and they should be increased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. A.5 Direct Probing Test Method, Applicable for Most 10/100 Devices (Devices that do NOT support 1000Base-T) Because probe capacitance can load the reference crystal affecting the measured frequency, it is preferable to use a probe with less than 1 pF capacitance. The probe should be connected between the XTAL2 pin of the LAN device and a nearby ground. Typically, it is possible to connect the probe pins across one of the discrete load capacitors (C2 in Figure 8). 57 Design Guide—82545/82546 Figure 8. Direct Probing Method A.6 Direct Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN device enabled. 2. Connect the test equipment as shown in Figure 8. 3. Using the appropriate controls for your model of high resolution digital counter, make sure it can display ~25.0000 MHz with at least four decimal places frequency resolution. 4. Ensure the LAN circuits are powered. 5. Determine the center reference frequency as accurately as possible. This can be done by taking 30 to 50 different readings using the frequency counter and then calculating the average results of the readings. 6. Calculate the accuracy of the measured and averaged center frequency with respect to an ideal 25.0000 MHz reference frequency. (x – y) FrequencyAccuracy ( ppm ) = -----------------------------( y § 1000000 ) 58 82545/82546—Design Guide where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz). ( 24999630 – 25000000 ) FrequencyAccuracy ( ppm ) = ---------------------------------------------------- = – 14.8ppm ( 25000000 § 1000000 ) Example 4. Given: The measured averaged center frequency is 25.00027 MHz (or 25,000,270 Hertz). ( 25000270 – 25000000 ) FrequencyAccuracy ( ppm ) = ---------------------------------------------------- = 10.8ppm ( 25000000 § 1000000 ) Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board. If the transmitter reference frequency is more than 8 ppm below the target frequency, then the values for C1 and C2 are too big and they should be decreased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. If the transmitter reference frequency is more than 8 ppm above the target frequency, then the values for C1 and C2 are too small and they should be increased. When tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. 59 Design Guide—82545/82546 Note: 60 This page intentionally left blank. ">

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Key features
- Compact design
- Integrated MAC and PHY
- Gigabit Ethernet and dual port support
- PCI/PCI-X bus interface
- System Management Bus (SMB) port
- Low power operation
- Wake-up support
Frequently asked questions
The 82545 EM/82545 GM, 82546 EB/82546 GB require three power supplies: VDDO (3.3 V I/O), AVDDH (3.3 V analog), DVDD (1.5 V digital), and AVDDL (2.5 V analog).
The controllers support two defined power states: D0 (full power operation) and D3 (low power operation).
To enable wake-up, you must program the appropriate Wake-up Control Register (WUC) and set the LAN wake-up address filters. The PME_N signal can be used to wake the system.
It is recommended to use a 25 MHz parallel resonant crystal with a frequency tolerance of ±30 ppm.
The controllers have a LAN disable function multiplexed on the FL_DATA0 signal (FL_DATA0/LAN_DISABLE#). When this signal is low, the LAN is disabled, the PHY is powered down, and the device enters a low power state.