GigaDevice Semiconductor Inc. GD32F303xx ARM® Cortex®

GigaDevice Semiconductor Inc. GD32F303xx ARM® Cortex®
GigaDevice Semiconductor Inc.
GD32F303xx
ARM® Cortex®-M4 32-bit MCU
Datasheet
GD32F303xx
Table of Contents
List of Figures ............................................................................................................................. 3
List of Tables ............................................................................................................................... 4
1
General description ......................................................................................................... 5
2
Device overview ............................................................................................................... 6
2.1
Device information .............................................................................................................................. 6
2.2
Block diagram ...................................................................................................................................... 8
2.3
Pinouts and pin assignment .............................................................................................................. 9
2.4
Memory map ...................................................................................................................................... 12
2.5
Clock tree ........................................................................................................................................... 16
2.6
Pin definitions .................................................................................................................................... 17
Functional description .................................................................................................. 25
3
3.1
ARM® Cortex®-M4 core .................................................................................................................... 25
3.2
On-chip memory................................................................................................................................ 26
3.3
Clock, reset and supply management ........................................................................................... 26
3.4
Boot modes ........................................................................................................................................ 27
3.5
Power saving modes ........................................................................................................................ 27
3.6
Analog to digital converter (ADC) ................................................................................................... 28
3.7
Digital to analog converter (DAC) ................................................................................................... 28
3.8
DMA .................................................................................................................................................... 29
3.9
General-purpose inputs/outputs (GPIOs) ...................................................................................... 29
3.10
Timers and PWM generation........................................................................................................... 30
3.11
Real time clock (RTC) ...................................................................................................................... 31
3.12
Inter-integrated circuit (I2C) ............................................................................................................. 31
3.13
Serial peripheral interface (SPI)...................................................................................................... 32
3.14
Universal synchronous asynchronous receiver transmitter (USART) ....................................... 32
3.15
Inter-IC sound (I2S) .......................................................................................................................... 32
3.16
Universal serial bus on-the-go full-speed (USB 2.0 FS) ............................................................. 33
3.17
Controller area network (CAN) ........................................................................................................ 33
3.18
Secure digital input and output card interface (SDIO) ................................................................. 33
3.19
External memory controller (EXMC) .............................................................................................. 34
3.20
Debug mode ...................................................................................................................................... 34
3.21
Package and operation temperature.............................................................................................. 34
Electrical characteristics .............................................................................................. 35
4
4.1
Absolute maximum ratings .............................................................................................................. 35
4.2
Recommended DC characteristics ................................................................................................. 35
4.3
Power consumption .......................................................................................................................... 36
4.4
EMC characteristics .......................................................................................................................... 37
4.5
Power supply supervisor characteristics ....................................................................................... 38
1 / 52
GD32F303xx
4.6
Electrical sensitivity........................................................................................................................... 38
4.7
External clock characteristics .......................................................................................................... 39
4.8
Internal clock characteristics ........................................................................................................... 40
4.9
PLL characteristics ........................................................................................................................... 41
4.10
Memory characteristics .................................................................................................................... 42
4.11
GPIO characteristics......................................................................................................................... 43
4.12
ADC characteristics .......................................................................................................................... 44
4.13
DAC characteristics .......................................................................................................................... 46
4.14
SPI characteristics ............................................................................................................................ 47
4.15
I2C characteristics ............................................................................................................................ 47
4.16
USART characteristics ..................................................................................................................... 47
Package information ..................................................................................................... 48
5
5.1
LQFP package outline dimensions ................................................................................................ 48
6
Ordering Information ..................................................................................................... 50
7
Revision History............................................................................................................. 51
2 / 52
GD32F303xx
List of Figures
Figure 1. GD32F303xx block diagram ...................................................................................................................... 8
Figure 2. GD32F303Zx LQFP144 pinouts ............................................................................................................... 9
Figure 3. GD32F303Vx LQFP100 pinouts ............................................................................................................. 10
Figure 4. GD32F303Rx LQFP64 pinouts ............................................................................................................... 11
Figure 5. GD32F303Cx LQFP48 pinouts ............................................................................................................... 11
Figure 6. GD32F303xx memory map ..................................................................................................................... 12
Figure 7. GD32F303xx clock tree............................................................................................................................ 16
Figure 8. LQFP package outline .............................................................................................................................. 48
3 / 52
GD32F303xx
List of Tables
Table 1. GD32F303xx devices features and peripheral list ................................................................................... 6
Table 2. GD32F303xx pin definitions ...................................................................................................................... 17
Table 3. Absolute maximum ratings ........................................................................................................................ 35
Table 4. DC operating conditions ............................................................................................................................ 35
Table 5. Power consumption characteristics ......................................................................................................... 36
Table 6. EMS characteristics ................................................................................................................................... 37
Table 7. EMI characteristics ..................................................................................................................................... 37
Table 8. Power supply supervisor characteristics ................................................................................................. 38
Table 9. ESD characteristics .................................................................................................................................... 38
Table 10. Static latch-up characteristics ................................................................................................................ 38
Table 11. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics.................. 39
Table 12. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ................... 39
Table 13. High speed internal clock (IRC8M) characteristics .............................................................................. 40
Table 14. High speed internal clock (IRC48M) characteristics ........................................................................... 40
Table 15. Low speed internal clock (IRC32K) characteristics ............................................................................. 41
Table 16. PLL characteristics ................................................................................................................................... 41
Table 17. PLL2/3 characteristics ............................................................................................................................. 41
Table 18. Flash memory characteristics ................................................................................................................. 42
Table 19. I/O port characteristics ............................................................................................................................. 43
Table 20. ADC characteristics .................................................................................................................................. 44
Table 21. ADC RAIN max for fADC=40MHz ................................................................................................................. 44
Table 22. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 45
Table 23. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 45
Table 24. ADC dynamic accuracy at fADC = 36 MHz ............................................................................................. 45
Table 25. ADC dynamic accuracy at fADC = 40 MHz ............................................................................................. 45
Table 26. ADC static accuracy at fADC = 15 MHz .................................................................................................. 45
Table 27. DAC characteristics ................................................................................................................................. 46
Table 28. SPI characteristics .................................................................................................................................... 47
Table 29. I2C characteristics .................................................................................................................................... 47
Table 30. USART characteristics ............................................................................................................................ 47
Table 31. LQFP package dimensions ..................................................................................................................... 49
Table 32. Part ordering code for GD32F303xx devices ....................................................................................... 50
Table 33. Revision history......................................................................................................................................... 51
4 / 52
GD32F303xx
1
General description
The GD32F303xx device belongs to the mainstream line of GD32 MCU Family. It is a new
32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best
cost-performance ratio in terms of enhanced processing capacity, reduced power
consumption and peripheral set. The Cortex®-M4 core features implements a full set of DSP
instructions to address digital signal control markets that demand an efficient, easy-to-use
blend of control and signal processing capabilities. It also provides a Memory Protection Unit
(MPU) and powerful trace technology for enhanced application security and advanced debug
support.
The GD32F303xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating
at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It
provides up to 3072 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range
of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three
12-bit 2.6M SPS ADCs, two 12-bit DACs, up to ten general-purpose 16-bit timers, two 16-bit
PWM advanced-control timers, and two 16-bit basic timers, as well as standard and advanced
communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two
I2Ss, an USB 2.0 FS, a CAN and a SDIO.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make GD32F303xx devices suitable for a wide range of interconnection
and advanced applications, especially in areas such as industrial control, motor drives,
consumer and handheld equipment, human machine interface, security and alarm systems,
POS, automotive navigation, IoT and so on.
5 / 52
GD32F303xx
2
Device overview
2.1
Device information
Table 1. GD32F303xx devices features and peripheral list
GD32F303xx
Part Number
CE
CG
RC
RE
RG
RI
RK
Code Area (KB)
256
256
256
256
256
256
256
256
Data Area (KB)
0
256
768
0
256
768
1792
2816
Total (KB)
256
512
1024
256
512
1024
2048
3072
48
64
96
48
64
96
96
96
16-bit GPTM
4
4
10
4
4
10
10
10
Adv. 16-bit TM
1
1
1
2
2
2
2
2
Basic 16-bit TM
2
2
2
2
2
2
2
2
SysTick
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
USART+UART
3
3
3
3+2
3+2
3+2
3+2
3+2
I2C
2
2
2
2
2
2
2
2
SPI/I2S
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
CAN 2.0B
1
1
1
1
1
1
1
1
USB 2.0 FS
1
1
1
1
1
1
1
1
GPIO
37
37
37
51
51
51
51
51
EXMC
0
0
0
0
0
0
0
0
EXTI
16
16
16
16
16
16
16
16
ADC Unit (CHs)
3(10)
3(10)
3(10)
3(16)
3(16)
3(16)
3(16)
3(16)
DAC
2
2
2
2
2
2
2
2
Flash
CC
Connectivity
Timers
SRAM (KB)
Package
LQFP48
LQFP64
6 / 52
GD32F303xx
Table 1. GD32F303xx devices features and peripheral list (Cont.)
GD32F303xx
Part Number
VE
VG
VI
VK
ZC
ZE
ZG
ZI
ZK
Code Area (KB)
256
256
256
256
256
256
256
256
256
256
Data Area (KB)
0
256
768
1792
2816
0
256
768
1792
2816
Total (KB)
256
512
1024
2048
3072
256
512
1024
2048
3072
48
64
96
96
96
48
64
96
96
96
16-bit GPTM
4
4
10
10
10
4
4
10
10
10
Adv. 16-bit TM
2
2
2
2
2
2
2
2
2
2
Basic 16-bit TM
2
2
2
2
2
2
2
2
2
2
SysTick
1
1
1
1
1
1
1
1
1
1
Watchdog
2
2
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
1
1
USART+UART
3+2
3+2
3+2
3+2
3+2
3+2
3+2
3+2
3+2
3+2
I2C
2
2
2
2
2
2
2
2
2
2
SPI/I2S
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
3/2
CAN 2.0B
1
1
1
1
1
1
1
1
1
1
USB 2.0 FS
1
1
1
1
1
1
1
1
1
1
GPIO
80
80
80
80
80
112
112
112
112
112
EXMC
1
1
1
1
1
1
1
1
1
1
EXTI
16
16
16
16
16
16
16
16
16
16
ADC Unit (CHs)
3(16)
3(16)
3(16)
3(16)
3(16)
3(21)
3(21)
3(21)
3(21)
3(21)
DAC
2
2
2
2
2
2
2
2
2
2
Flash
VC
Connectivity
Timers
SRAM (KB)
Package
LQFP100
LQFP144
7 / 52
GD32F303xx
2.2
Block diagram
Figure 1. GD32F303xx block diagram
SW/JTAG
TPIU
NVIC
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
F max : 120MHz
Dbus
FMC
Master
GP DMA 12 chs
Master
AHB Matrix
ICode DCode System
ARM Cortex-M4
Processor
Fmax:120MHz
POR/ PDR
EXMC
Slave
Slave
CRC
LDO
1.2V
RCU
AHB Peripherals
Slave
Slave
SDIO
SRAM
Controller
AHB to APB
Bridge2
IRC
8MHz
SRAM
HXTAL
4-16MHz
AHB to APB
Bridge1
LVD
Interrput request
CAN0
USART0
Slave
12-bit
SAR ADC
Slave
SPI0
WWDGT
ADC0~2
TIMER1~3
EXTI
SPI1~2\
I2S1~2
GPIOA
USART1~2
Powered By V DDA
GPIOD
GPIOE
APB1: Fmax = 60MHZ
GPIOC
APB2: Fmax = 120MHz
GPIOB
Powered By VDDA
I2C0
I2C1
USBD
FWDGT
GPIOF
RTC
GPIOG
DAC
TIMER0
TIMER4~6
TIMER7
UART3~4
TIMER8~10
TIMER
11~13
CTC
8 / 52
GD32F303xx
2.3
Pinouts and pin assignment
Figure 2. GD32F303Zx LQFP144 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
VSS_10
VDD_10
PD6
PD7
PG9
PG10
PG11
PG12
PG13
PG14
VSS_11
VDD_11
PG15
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109
PE2
1
108
PE3
PE4
2
107
VSS_2
3
106
NC
PE5
PE6
4
105
PA13
5
104
PA12
VBAT
6
103
PA11
PC13-TAMPER-RTC
PC14-OSC32_IN
7
102
PA10
8
101
PA9
PC15-OSC32_OUT
9
100
PA8
PF0
10
99
PC9
PC8
VDD_2
PF1
11
98
PF2
12
97
PC7
PF3
PF4
13
96
PC6
14
95
VDD_9
PF5
15
94
VSS_9
VSS_5
16
93
PG8
92
PG7
91
PG6
90
PG5
89
PG4
88
PG3
VDD_5
17
PF6
18
PF7
19
PF8
20
PF9
21
PF10
22
87
PG2
OSC_IN
23
86
PD15
OSC_OUT
24
85
PD14
NRST
25
84
VDD_8
PC0
26
83
VSS_8
PC1
27
82
PD13
PC2
28
81
PD12
PC3
VSSA
29
80
PD11
30
79
PD10
VREFVREF+
31
78
PD9
32
77
PD8
VDDA
33
76
PB15
PA0_WKUP
34
75
PB14
PA1
35
74
PB13
PA2
36
73
PB12
GigaDevice GD32F303Zx
LQFP144
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
VDD_1
VSS_1
PB11
PB10
PE15
PE13
PE14
PE12
PE11
VDD_7
PE10
VSS_7
PE9
PE7
PE8
PG1
PG0
PF15
PF14
VDD_6
PF13
VSS_6
PF12
PB2
PF11
PB1
PC5
PB0
PA7
PC4
PA6
PA5
VDD_4
PA4
VSS_4
PA3
9 / 52
GD32F303xx
Figure 3. GD32F303Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32_IN
7
70
69
PA10
8
68
PA9
PC15-OSC32_OUT
9
67
PA8
VSS_5
10
66
PC9
65
PC8
64
PC7
63
PC6
14
62
PD15
VDD_2
PA11
VDD_5
11
OSC_IN
12
OSC_OUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
GigaDevice GD32F303Vx
LQFP100
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PB2
PE7
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
10 / 52
GD32F303xx
Figure 4. GD32F303Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PD2
PC12
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32_IN
3
46
PA13
PC15-OSC32_OUT
PD0-OSC_IN
4
45
PA12
5
44
PA11
PD1 OSC_OUT
6
43
PA10
NRST
PC0
7
42
PA9
PC1
9
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
VBAT
GigaDevice GD32F303Rx
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
13
36
PB15
14
35
PB14
15
34
PB13
16
33
PB12
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB1
PB2
PB10
PB11
PB5
PB4
PB3
PA15
PA14
VDD_1
PB0
PB6
VSS_1
PC5
PC4
PA7
PA6
PA5
PA4
VDD_4
PA3
VSS_4
Figure 5. GD32F303Cx LQFP48 pinouts
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
VDD_2
PC13-TAMPER-RTC
2
35
VSS_2
VBAT
PC14-OSC32_IN
3
34
PA13
PC15-OSC32_OUT
PD0-OSC_IN
4
33
PA12
5
32
PA11
PD1-OSC_OUT
NRST
VSSA
6
31
PA10
30
PA9
GigaDevice
GD32F303Cx
LQFP48
7
8
29
VDDA
9
28
PA8
PB15
PA0-WKUP
10
27
PB14
PA1
PA2
11
26
PB13
25
PB12
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_1
VSS_1
PB11
PB10
PB2
PB1
PB0
PA7
PA6
PA5
PA4
PA3
11 / 52
GD32F303xx
2.4
Memory map
Figure 6. GD32F303xx memory map
Pre-defined
Regions
Bus
External
device
AHB3
External RAM
AHB1
Peripheral
APB2
Address
Peripherals
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
0x9000 0000 - 0x9FFF FFFF
EXMC - PC CARD
0x7000 0000 - 0x8FFF FFFF
EXMC - NAND
0x6000 0000 - 0x6FFF FFFF
EXMC - NOR/PSRAM/SRAM
0x5000 0000 - 0x5003 FFFF
Reserved
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
SDIO
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
12 / 52
GD32F303xx
Pre-defined
Regions
Bus
APB1
Address
Peripherals
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
TIMER10
0x4001 5000 - 0x4001 53FF
TIMER9
0x4001 4C00 - 0x4001 4FFF
TIMER8
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
ADC2
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
TIMER7
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
GPIOG
0x4001 1C00 - 0x4001 1FFF
GPIOF
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
CTC
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
13 / 52
GD32F303xx
Pre-defined
Regions
Bus
Address
0x4000 6000 - 0x4000 63FF
SRAM
AHB
Peripherals
Shared USBD/CAN SRAM 512
bytes
0x4000 5C00 - 0x4000 5FFF
USBD
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
TIMER13
0x4000 1C00 - 0x4000 1FFF
TIMER12
0x4000 1800 - 0x4000 1BFF
TIMER11
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2002 0000 - 0x2002 FFFF
Reserved
0x2001 C000 - 0x2001 FFFF
Reserved
0x2001 8000 - 0x2001 BFFF
0x2000 5000 - 0x2001 7FFF
SRAM
0x2000 0000 - 0x2000 4FFF
Code
AHB
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF F000 - 0x1FFF F7FF
0x1FFF C010 - 0x1FFF EFFF
0x1FFF C000 - 0x1FFF C00F
Boot loader
0x1FFF B000 - 0x1FFF BFFF
14 / 52
GD32F303xx
Pre-defined
Regions
Bus
Address
Peripherals
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0810 0000 - 0x082F FFFF
0x0802 0000 - 0x080F FFFF
Main Flash
0x0800 0000 - 0x0801 FFFF
0x0030 0000 - 0x07FF FFFF
0x0010 0000 - 0x002F FFFF
0x0002 0000 - 0x000F FFFF
Reserved
Aliased to Main Flash or Boot
loader
0x0000 0000 - 0x0001 FFFF
15 / 52
GD32F303xx
2.5
Clock tree
Figure 7. GD32F303xx clock tree
CTC
CK_IRC48M
CK_CTC
48 MHz
IRC48M
48 MHz
CK48MSEL
USBD
Prescaler
1,1.5,2,2.5
3,3.5,4
1
SCS[1:0]
CK_USBD
0
(to USBD)
CK_I2S
CK_IRC8M
8 MHz
IRC8M
1
I2S enable
(by hardware)
00
0
/2
1
PLLPRESEL
CK_IRC48M
1
×2,3,4
…63
PLL
PLLSEL PLLMF
CK_PLL
10
CK_SYS
120 MHz max
AHB
Prescaler
÷1,2...512
CK_AHB
120 MHz max
(to I2S1,2)
CK_EXMC
EXMC enable
(by hardware)
(to EXMC)
HCLK
01
AHB enable
(to AHB bus,Cortex-M4,SRAM,DMA,FMC)
/1 or /2
CK_CST
Clock
Monitor
0
4-16 MHz
HXTAL
÷8
(to Cortex-M4 SysTick)
PREDV0
FCLK
(free running clock)
CK_HXTAL
CK_SDIO
SDIO enable
(by hardware)
APB1
Prescaler
÷1,2,4,8,16
(to SDIO)
CK_APB1
PCLK1
to APB1 peripherals
60 MHz max
Peripheral enable
/128
TIMER1,2,3,4,5,6,
11,12,13 if(APB1
prescale =1)x1
else x 2
11
32.768 KHz
LXTAL
CK_TIMERx
TIMERx
enable
to TIMER1,2,3,4,
5,6,11,12,13
CK_RTC
01
(to RTC)
10
APB2
Prescaler
÷1,2,4,8,16
CK_APB2
PCLK2
to APB2 peripherals
120 MHz max
Peripheral enable
RTCSRC[1:0]
40 KHz
IRC40K
CK_FWDGT
(to FWDGT)
CK_OUT0
0xx
100
101
110
111
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CKOUT0SEL[2:0]
TIMER0,7,8,9,10
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
ADC
Prescaler
÷5,6,10,20
CK_TIMERx
TIMERx
enable
to
TIMER0,7,8,9,10
ADCPSC[3]
0
1
CK_ADCx to ADC0,1,2
40 MHz max
Legend:
HXTAL: High speed crystal oscillator
LXTAL: Low speed crystal oscillator
IRC8M: Internal 8M RC oscillators
IRC48M: Internal 48M RC oscillators
IRC32K: Internal 32K RC oscillator
16 / 52
GD32F303xx
2.6
Pin definitions
Table 2. GD32F303xx pin definitions
LQFP144
LQFP100
LQFP64
LQFP48
Pin Type(1)
I/O(2) Level
Pins
PE2
1
1
-
-
I/O 5VT
PE3
2
2
-
-
I/O 5VT
PE4
3
3
-
-
I/O 5VT
Pin Name
Functions description
Default: PE2
Alternate: TRACECK, EXMC_A23
Default: PE3
Alternate: TRACED0, EXMC_A19
Default: PE4
Alternate:TRACED1, EXMC_A20
Default: PE5
PE5
4
4
-
-
I/O 5VT Alternate:TRACED2, EXMC_A21
Remap: TIMER8_CH0
Default: PE6
PE6
5
5
-
-
I/O 5VT Alternate:TRACED3, EXMC_A22
Remap: TIMER8_CH1
VBAT
6
6
1
1
P
7
7
2
2
I/O
8
8
3
3
I/O
9
9
4
4
I/O
PC13TAMPERRTC
PC14OSC32_IN
PC15OSC32_OUT
Default: VBAT
Default: PC13
Alternate: TAMPER, RTC
Default: PC14
Alternate: OSC32_IN
Default: PC15
Alternate: OSC32_OUT
Default: PF0
PF0
10
-
-
-
I/O 5VT Alternate: EXMC_A0
Remap: CTC_SYNC
Default: PF1
PF1
11
-
-
-
I/O 5VT
PF2
12
-
-
-
I/O 5VT
PF3
13
-
-
-
I/O 5VT
PF4
14
-
-
-
I/O 5VT
PF5
15
-
-
-
I/O 5VT
VSS_5
16
10
-
-
P
Default: VSS_5
VDD_5
17
11
-
-
P
Default: VDD_5
Alternate: EXMC_A1
Default: PF2
Alternate: EXMC_A2
Default: PF3
Alternate: EXMC_A3
Default: PF4
Alternate: EXMC_A4
Default: PF5
Alternate: EXMC_A5
Default: PF6
PF6
18
-
-
-
I/O
Alternate: ADC2_IN4, EXMC_NIORD
Remap: TIMER9_CH0
17 / 52
GD32F303xx
I/O(2) Level
Pin Type(1)
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Functions description
Default: PF7
PF7
19
-
-
-
I/O
Alternate: ADC2_IN5, EXMC_NREG
Remap: TIMER10_CH0
Default: PF8
PF8
20
-
-
-
I/O
Alternate: ADC2_IN6, EXMC_NIOWR
Remap: TIMER12_CH0
Default: PF9
PF9
21
-
-
-
I/O
Alternate: ADC2_IN7, EXMC_CD
Remap: TIMER13_CH0
Default: PF10
PF10
22
-
-
-
I/O
OSC_IN
23
12
5
5
I
OSC_OUT
24
13
6
6
O
NRST
25
14
7
7
I/O
PC0
26
15
8
-
I/O
PC1
27
16
9
-
I/O
PC2
28
17
10
-
I/O
PC3
29
18
11
-
I/O
VSSA
30
19
12
8
P
Default: VSSA
VREF-
31
20
-
-
P
Default: VREF-
VREF+
32
21
-
-
P
Default: VREF+
VDDA
33
22
13
9
P
Default: VDDA
Alternate: ADC2_IN8, EXMC_INTR
Default: OSC_IN
Remap: PD0
Default: OSC_OUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC012_IN10
Default: PC1
Alternate: ADC012_IN11
Default: PC2
Alternate: ADC012_IN12
Default: PC3
Alternate: ADC012_IN13
Default: PA0
PA0-WKUP
34
23
14
10
I/O
Alternate: WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0_ETI,
TIMER4_CH0, TIMER7_ETI
PA1
35
24
15
11
I/O
PA2
36
25
16
12
I/O
Default: PA1
Alternate: USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1
Default: PA2
Alternate: USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2,
TIMER8_CH0, SPI0_IO2
Default: PA3
PA3
37
26
17
13
I/O
Alternate: USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3,
TIMER8_CH1, SPI0_IO3
VSS_4
38
27
18
-
P
Default: VSS_4
VDD_4
39
28
19
-
P
Default: VDD_4
PA4
40
29
20
14
I/O
Default: PA4
18 / 52
GD32F303xx
I/O(2) Level
Pin Type(1)
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Functions description
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0
Remap:SPI2_NSS, I2S2_WS
PA5
41
30
21
15
I/O
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
42
31
22
16
I/O
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BKIN,
TIMER12_CH0
Remap: TIMER0_BKIN
Default: PA7
PA7
43
32
23
17
I/O
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,
TIMER7_CH0_ON, TIMER13_CH0
Remap: TIMER0_CH0_ON
PC4
44
33
24
-
I/O
PC5
45
34
25
-
I/O
PB0
46
35
26
18
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON
Remap: TIMER0_CH1_ON
Default: PB1
PB1
47
36
27
19
I/O
Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON
Remap: TIMER0_CH2_ON
I/O 5VT Default: PB2, BOOT1
PB2
48
37
28
20
PF11
49
-
-
-
I/O 5VT
PF12
50
-
-
-
I/O 5VT
VSS_6
51
-
-
-
P
Default: VSS_6
VDD_6
52
-
-
-
P
Default: VDD_6
PF13
53
-
-
-
I/O 5VT
PF14
54
-
-
-
I/O 5VT
PF15
55
-
-
-
I/O 5VT
PG0
56
-
-
-
I/O 5VT
PG1
57
-
-
-
I/O 5VT
Default: PF11
Alternate: EXMC_NIOS16
Default: PF12
Alternate: EXMC_A6
Default: PF13
Alternate: EXMC_A7
Default: PF14
Alternate: EXMC_A8
Default: PF15
Alternate: EXMC_A9
Default: PG0
Alternate: EXMC_A10
Default: PG1
Alternate: EXMC_A11
Default: PE7
PE7
58
38
-
-
I/O 5VT Alternate: EXMC_D4
Remap: TIMER0_ETI
19 / 52
GD32F303xx
I/O(2) Level
Pin Type(1)
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Functions description
Default: PE8
PE8
59
39
-
-
I/O 5VT Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
I/O 5VT Alternate: EXMC_D6
PE9
60
40
-
-
VSS_7
61
-
-
-
P
Default: VSS_7
VDD_7
62
-
-
-
P
Default: VDD_7
Remap: TIMER0_CH0
Default: PE10
PE10
63
41
-
-
I/O 5VT Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
64
42
-
-
I/O 5VT Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
65
43
-
-
I/O 5VT Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
66
44
-
-
I/O 5VT Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
67
45
-
-
I/O 5VT Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
68
46
-
-
I/O 5VT Alternate: EXMC_D12
Remap: TIMER0_BKIN
Default: PB10
PB10
69
47
29
21
I/O 5VT Alternate: I2C1_SCL, USART2_TX
Remap: TIMER1_CH2
Default: PB11
PB11
70
48
30
22
I/O 5VT Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
71
49
31
23
P
Default: VSS_1
VDD_1
72
50
32
24
P
Default: VDD_1
PB12
73
51
33
25
Default: PB12
I/O 5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN,
I2S1_WS
PB13
74
52
34
26
I/O 5VT
Default: PB13
Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK
Default: PB14
PB14
75
53
35
27
I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,
TIMER11_CH0
20 / 52
GD32F303xx
LQFP100
LQFP64
LQFP48
Pin Type(1)
PB15
LQFP144
Pin Name
I/O(2) Level
Pins
76
54
36
28
I/O 5VT
Functions description
Default: PB15
Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1
Default: PD8
PD8
77
55
-
-
I/O 5VT Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
78
56
-
-
I/O 5VT Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
79
57
-
-
I/O 5VT Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
80
58
-
-
I/O 5VT Alternate: EXMC_A16
Remap: USART2_CTS
Default: PD12
PD12
81
59
-
-
I/O 5VT Alternate: EXMC_A17
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
82
60
-
-
I/O 5VT Alternate: EXMC_A18
Remap: TIMER3_CH1
VSS_8
83
-
-
-
P
Default: VSS_8
VDD_8
84
-
-
-
P
Default: VDD_8
PD14
85
61
-
-
Default: PD14
I/O 5VT Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
86
62
-
-
I/O 5VT Alternate: EXMC_D1
Remap: TIMER3_CH3, CTC_SYNC
Default: PG2
PG2
87
-
-
-
I/O 5VT
PG3
88
-
-
-
I/O 5VT
PG4
89
-
-
-
I/O 5VT
PG5
90
-
-
-
I/O 5VT
PG6
91
-
-
-
I/O 5VT
PG7
92
-
-
-
I/O 5VT
PG8
93
-
-
-
I/O 5VT Default: PG8
VSS_9
94
-
-
-
P
Alternate: EXMC_A12
Default: PG3
Alternate: EXMC_A13
Default: PG4
Alternate: EXMC_A14
Default: PG5
Alternate: EXMC_A15
Default: PG6
Alternate: EXMC_INT1
Default: PG7
Alternate: EXMC_INT2
Default: VSS_9
21 / 52
GD32F303xx
LQFP100
LQFP64
LQFP48
Pin Type(1)
VDD_9
95
-
-
-
P
PC6
96
63
37
-
Pin Name
I/O(2) Level
LQFP144
Pins
Functions description
Default: VDD_9
Default: PC6
I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0, SDIO_D6
Remap: TIMER2_CH0
Default: PC7
PC7
97
64
38
-
I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1, SDIO_D7
Remap: TIMER2_CH1
Default: PC8
PC8
98
65
39
-
I/O 5VT Alternate: TIMER7_CH2, SDIO_D0
Remap: TIMER2_CH2
Default: PC9
PC9
99
66
40
-
I/O 5VT Alternate: TIMER7_CH3, SDIO_D1
Remap: TIMER2_CH3
Default: PA8
PA8
100 67
41
29
I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,
CTC_SYNC
Default: PA9
PA9
101 68
42
30
I/O 5VT
PA10
102 69
43
31
I/O 5VT
PA11
103 70
44
32
I/O 5VT
PA12
104 71
45
33
I/O 5VT
PA13
105 72
46
34
I/O 5VT
NC
106 73
-
-
VSS_2
107 74
47
35
P
Default: VSS_2
VDD_2
108 75
48
36
P
Default: VDD_2
PA14
109 76
49
37
Alternate: USART0_TX, TIMER0_CH1
Default: PA10
Alternate: USART0_RX, TIMER0_CH2
Default: PA11
Alternate: USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3
Default: PA12
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP
Default: JTMS, SWDIO
Remap: PA13
-
I/O 5VT
Default: JTCK, SWCLK
Remap: PA14
Default: JTDI
PA15
110 77
50
38
I/O 5VT Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0_ETI, PA15, SPI0_NSS
Default: PC10
PC10
111 78
51
-
I/O 5VT Alternate: UART3_TX, SDIO_D2
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
112 79
52
-
I/O 5VT Alternate: UART3_RX, SDIO_D3
Remap: USART2_RX, SPI2_MISO
PC12
113 80
53
-
I/O 5VT
Default: PC12
Alternate: UART4_TX, SDIO_CK
22 / 52
GD32F303xx
I/O(2) Level
Pin Type(1)
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Functions description
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
114 81
-
-
I/O 5VT Alternate: EXMC_D2
Remap: CAN0_RX, OSC_IN
Default: PD1
PD1
115 82
-
-
I/O 5VT Alternate: EXMC_D3
Remap: CAN0_TX, OSC_OUT
PD2
116 83
54
-
I/O 5VT
Default: PD2
Alternate: TIMER2_ETI, SDIO_CMD, UART4_RX
Default: PD3
PD3
117 84
-
-
I/O 5VT Alternate: EXMC_CLK
Remap: USART1_CTS
Default: PD4
PD4
118 85
-
-
I/O 5VT Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
119 86
-
-
I/O 5VT Alternate: EXMC_NWE
Remap: USART1_TX
VSS_10
120
-
-
-
Default: VSS_10
VDD_10
121
-
-
-
Default: VDD_10
-
-
I/O 5VT Alternate: EXMC_NWAIT
Default: PD6
PD6
122 87
Remap: USART1_RX
Default: PD7
PD7
123 88
-
-
I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1
Remap: USART1_CK
Default: PG9
PG9
124
-
-
-
I/O 5VT
PG10
125
-
-
-
I/O 5VT
PG11
126
-
-
-
I/O 5VT
PG12
127
-
-
-
I/O 5VT
PG13
128
-
-
-
I/O 5VT
PG14
129
-
-
-
I/O 5VT
VSS_11
130
-
-
-
P
Default: VSS_11
VDD_11
131
-
-
-
P
Default: VDD_11
PG15
132
-
-
-
I/O 5VT Default: PG15
55
39
I/O 5VT Default: JTDO
PB3
133 89
Alternate: EXMC_NE1, EXMC_NCE2
Default: PG10
Alternate: EXMC_NCE3_0, EXMC_NE2
Default: PG11
Alternate: EXMC_NCE3_1
Default: PG12
Alternate: EXMC_NE3
Default: PG13
Alternate: EXMC_A24
Default: PG14
Alternate: EXMC_A25
23 / 52
GD32F303xx
I/O(2) Level
Pin Type(1)
LQFP48
LQFP64
LQFP100
Pin Name
LQFP144
Pins
Functions description
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK
Default: NJTRST
PB4
134 90
56
40
I/O 5VT Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
135 91
57
41
I/O
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
Remap: TIMER2_CH1, SPI0_MOSI
Default: PB6
PB6
136 92
58
42
I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, SPI0_IO2
Default: PB7
PB7
137 93
59
43
I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV
Remap: USART0_RX, SPI0_IO3
BOOT0
138 94
60
44
I
Default: BOOT0
Default: PB8
PB8
139 95
61
45
I/O 5VT Alternate: TIMER3_CH2, SDIO_D4, TIMER9_CH0
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
140 96
62
46
I/O 5VT Alternate: TIMER3_CH3, SDIO_D5, TIMER10_CH0
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
141 97
-
-
I/O 5VT
PE1
142 98
-
-
I/O 5VT
VSS_3
143 99
63
47
P
Default: VSS_3
VDD_3
144 100 64
48
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
1.
Type: I = input, O = output, P = power.
2.
I/O Level: 5VT = 5 V tolerant.
24 / 52
GD32F303xx
3
Functional description
3.1
ARM® Cortex®-M4 core
The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP
instructions which allow efficient signal processing and complex algorithm execution. It brings
an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital
signal control markets demand. The processor is highly configurable enabling a wide range
of implementations from those requiring floating point operations, memory protection and
powerful trace technology to cost sensitive devices requiring minimal area, while delivering
outstanding computational performance and an advanced system response to interrupts.
32-bit ARM® Cortex®-M4 processor core

Up to 120 MHz operation frequency

Single-cycle multiplication and hardware divider

Floating Point Unit (FPU)

Integrated DSP instructions

Integrated Nested Vectored Interrupt Controller (NVIC)

24-bit SysTick timer
The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb
and Thumb-2 instruction sets. Some system peripherals listed below are also provided by
Cortex®-M4:

Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private
Peripheral Bus (PPB) and debug accesses (AHB-AP)

Nested Vectored Interrupt Controller (NVIC)

Flash Patch and Breakpoint (FPB)

Data Watchpoint and Trace (DWT)

Instrument Trace Macrocell (ITM)

Memory Protection Unit (MPU)

Serial Wire JTAG Debug Port (SWJ-DP)

Trace Port Interface Unit (TPIU)
25 / 52
GD32F303xx
3.2
On-chip memory

Up to 3072 Kbytes of Flash memory, including code Flash and data Flash

Up to 96 KB of SRAM
The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use
separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most,
which includes code Flash that available for storing programs and data, and accessed (R/W)
at CPU clock speed with zero wait states. An extra data Flash is also included for storing data
mainly. The Figure of GD32F303xx memory map shows the memory of the GD32F303xx
series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.
3.3
Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator

Internal 48 MHz RC oscillator

Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator

2.6 to 3.6 V application supply and I/Os

Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These
include internal RC oscillator and external crystal oscillator, high speed and low speed two
types. Several prescalers allow the frequency configuration of the AHB and two APB domains.
The maximum frequency of the two AHB domains are 120 MHz. The maximum frequency of
the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See Figure 6 for
details on the clock tree.
The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor
core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are
always active, and ensures proper operation starting from/down to 2.6 V. The device remains
in reset mode when VDD is below a specified threshold. The embedded low voltage detector
(LVD) monitors the power supply, compares it to the voltage threshold and generates an
interrupt as a warning message for leading the MCU into security.
Power supply schemes:

VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.

VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,
RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
26 / 52
GD32F303xx
3.4
Boot modes
At startup, boot pins are used to select one of three boot options:

Boot from main flash memory (default)

Boot from system memory

Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART0, USART1, in device mode. It also can be
used to transfer and update the Flash memory code, the data and the vector table sections.
In default condition, boot from bank 1 of Flash memory is selected. It also supports to boot
from bank 2 of Flash memory by setting a bit in option bytes.
3.5
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.

Sleep mode
In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and
any interrupt/event can wake up the system.

Deep-sleep mode
In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed
crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and
registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the
system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the
LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is
selected as the system clock.

Standby mode
In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except
Backup Registers) are lost. There are four wakeup sources for the Standby mode,
including the external reset from NRST pin, the RTC, the FWDG reset, and the rising
edge on WKUP pin.
27 / 52
GD32F303xx
3.6
Analog to digital converter (ADC)

12-bit SAR ADC's conversion rate is up to 2.6MSPS

12-bit, 10-bit, 8-bit or 6-bit configurable resolution

Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit

Input voltage range: VSSA to VDDA (2.6 to 3.6 V)

Temperature sensor
Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of
18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor
(VSENSE), 1 channel for internal reference voltage (VREFINT). The input voltage range is between
2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while offloading the related computational burden from the CPU. An analog watchdog block can be
used to detect the channels, which are required to remain within a specific threshold window.
A configurable channel management block can be used to perform conversions in single,
continuous, scan or discontinuous mode to support more advanced use.
The ADC can be triggered from the events generated by the general-purpose level 0 timers
(TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The
temperature sensor can be used to generate a voltage that varies linearly with temperature.
It is internally connected to the ADC_IN16 input channel which is used to convert the sensor
output voltage in a digital value.
3.7
Digital to analog converter (DAC)

Two 12-bit DACs with independent output channels

8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC
channels can be triggered by the timer or EXTI with DMA support. In dual DAC channel
operation, conversions could be done independently or simultaneously. The maximum output
value of the DAC is VREF+.
28 / 52
GD32F303xx
3.8
DMA

7 channel DMA 1 controller and 5 channel DMA 2 controller

Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S
The flexible general-purpose DMA controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Four types of access method are supported: peripheral
to peripheral, peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9
General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)

Analog input/output configurable

Alternate function input/output configurable
There are up to 112 general purpose I/O pins (GPIO) in GD32F303xx, named PA0 ~ PA15
and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to
implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications. The external
interrupts on the GPIO pins of the device have related control and configuration registers in
the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other
alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the
GPIO pins can be configured by software as output (push-pull or open-drain), as input (with
or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are
shared with digital or analog alternate functions. All GPIOs are high-current capable except
for analog inputs.
29 / 52
GD32F303xx
3.10
Timers and PWM generation

Two 16-bit advanced-control timer (TM0 & TM7), ten 16-bit general-purpose timers (TM1
~ TM4, TM8 ~ TM13), and two 16-bit basic timer (TM5 & TM6)

Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input

16-bit, motor control PWM advanced-control timer with programmable dead-time
generation for output match

Encoder interface controller with two inputs using quadrature decoder

24-bit SysTick timer down counter

2 watchdog timers (Free watchdog and window watchdog)
The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed
on 6 channels. It has complementary PWM outputs with programmable dead-time generation.
It can also be used as a complete general-purpose timer. The 4 independent channels can
be used for input capture, output compare, PWM generation (edge- or center-aligned counting
modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has
the same functions as the TMx timer. It can be synchronized with external signals or to
interconnect with other GPTMs together which have the same architecture and features.
The general-purpose timer (GPTM), can be used for a variety of purposes including general
time, input signal pulse width measurement or output waveform generation such as a single
pulse generation or PWM output, up to 4 independent channels for input capture/output
compare. TM1 ~ TM4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.
TM8 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM
also supports an encoder interface with two inputs using quadrature decoder.
The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can
also be used as a simple 16-bit time base.
The GD32F303xx have two watchdog peripherals, Independent watchdog and window
watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.
The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit
prescaler, It is clocked from an independent 40 kHz internal RC and as it operates
independently of the main clock, it can operate in stop and standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management.
The window watchdog is based on a 7-bit down counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in debug
mode.
30 / 52
GD32F303xx
The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It
features:
3.11

A 24-bit down counter

Auto reload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source
Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler

Alarm function

Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate an
alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.
3.12
Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 1 MHz (Fast mode plus)

Provide arbitration function, optional PEC (packet error checking) generation and
checking

Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides several data transfer rates: 100 KHz of standard mode, 400
KHz of the fast mode and 1 MHz of the fast mode plus . The I2C module also has an arbitration
detect function to prevent the situation where more than one master attempts to transmit data
to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to
perform packet error checking for I2C data.
31 / 52
GD32F303xx
3.13
Serial peripheral interface (SPI)

Up to three SPI interfaces with a frequency of up to 30 MHz

Support both master and slave mode

Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.14
Universal synchronous asynchronous receiver transmitter
(USART)

Up to three USARTs and two UARTs with operating frequency up to 10.5 MHz

Supports both asynchronous and clocked synchronous serial communication modes

IrDA SIR encoder and decoder support

LIN break generation and detection

USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to
translate data between parallel and serial interfaces, provides a flexible full duplex data
exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232
standard communication. The USART/UART includes a programmable baud rate generator
which is capable of dividing the system clock to produce a dedicated clock for the USART
transmitter and receiver. The USART/UART also supports DMA function for high speed data
communication except UART4.
3.15
Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz

Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32F303xx contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported.
32 / 52
GD32F303xx
3.16
Universal serial bus on-the-go full-speed (USB 2.0 FS)

One full-speed USB Interface with frequency up to 12 Mbit/s

Internal 48 MHz oscillator support crystal-less operation

Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction
formatting is performed by the hardware, including CRC generation and checking. It supports
device modes. Transaction formatting is performed by the hardware, including CRC
generation and checking. The status of a completed USB transfer or error condition is
indicated by status registers. An interrupt is also generated if enabled. The required precise
48 MHz clock which can be generated from the internal main PLL (the clock source must use
an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode
that allows crystal-less operation.
3.17
Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s

Internal main PLL for CAN CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 28 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18
Secure digital input and output card interface (SDIO)

Support SD2.0/SDIO2.0/MMC4.2 host interface
The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD
memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media
card system specification version 4.2 with DMA supported. In addition, this interface is also
compliant with CE-ATA digital protocol rev1.1.
33 / 52
GD32F303xx
3.19
External memory controller (EXMC)

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and
CF card

Provide ECC calculating hardware module for NAND Flash memory block

Up to 16-bit data bus

Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It is
divided in to several sub-banks for external device support, each sub-bank has its own chip
selection signal but at one time, only one bank can be accessed. The EXMC support code
execution from external memory except NAND Flash and CF card. The EXMC also can be
configured to interface with the most common LCD module of Motorola 6800 and Intel 8080
series and reduce the system cost and complexity.
3.20
Debug mode

Serial wire JTAG debug port (SWJ-DP)
The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
3.21
Package and operation temperature

LQFP144 (GD32F303Zx), LQFP100 (GD32F303Vx), LQFP64 (GD32F303Rx) and

Operation temperature range: -40°C to +85°C (industrial level)
LQFP48 (GD32F303Cx)
34 / 52
GD32F303xx
4
Electrical characteristics
4.1
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
Min
Max
Unit
VDD
External voltage range
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
Input voltage on 5V tolerant pin
VSS - 0.3
VDD + 4.0
V
Input voltage on other I/O
VSS - 0.3
4.0
V
Variations between different VDD power pins
—
50
mV
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
25
mA
TA
Operating temperature range
-40
+85
°C
Storage temperature range
-55
+150
°C
Maximum junction temperature
—
125
°C
VIN
|ΔVDDx|
|VSSX −VSS|
TSTG
TJ
4.2
Parameter
Recommended DC characteristics
Table 4. DC operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
35 / 52
GD32F303xx
4.3
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 5. Power consumption characteristics
Symbol
Parameter
Conditions
VDD=VDDA=3.3V, HXTAL=25MHz, System
Min
Typ
Max Unit
—
45.6
—
mA
—
25.0
—
mA
-—
42.5
—
mA
—
22.5
—
mA
—
44.9
—
mA
—
13.86
—
mA
—
208
—
μA
—
180
—
μA
—
5.10
—
μA
—
4.90
—
μA
—
4.30
—
μA
—
1.78
—
μA
—
1.48
—
μA
—
1.16
—
μA
—
1.11
—
μA
clock=120MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL =25MHz, System
Supply current
clock =120MHz, All peripherals disabled
(Run mode)
VDD=VDDA=3.3V, HXTAL =25MHz, System
clock =108MHz, All peripherals enabled
VDD=VDDA=3.3V, HXTAL =25MHz, System
Clock =108MHz, All peripherals disabled
VDD=VDDA=3.3V, HXTAL =25MHz, CPU
clock off, System clock=120MHz, All
Supply current
peripherals enabled
(Sleep mode)
VDD=VDDA=3.3V, HXTAL =25MHz, CPU
clock off, System clock=120MHz, All
IDD
peripherals disabled
VDD=VDDA=3.3V, Regulator in run mode,
Supply current
(Deep-Sleep
mode)
IRC32K on, RTC on, All GPIOs analog
mode
VDD=VDDA=3.3V, Regulator in low power
mode, IRC32K on, RTC on, All GPIOs
analog mode
VDD=VDDA=3.3V, LXTAL off, IRC32K on,
RTC on
Supply current
VDD=VDDA=3.3V, LXTAL off, IRC32K on,
(Standby mode) RTC off
VDD=VDDA=3.3V, LXTAL off, IRC32K off,
RTC off
VDD not available, VBAT=3.6 V, LXTAL on
with external crystal, RTC on, Higher
driving
VDD not available, VBAT=3.3 V, LXTAL on
with external crystal, RTC on, Higher
IBAT
Battery supply
current
driving
VDD not available, VBAT=2.6 V, LXTAL on
with external crystal, RTC on, Higher
driving
VDD not available, VBAT=3.6 V, LXTAL on
with external crystal, RTC on, Lower driving
36 / 52
GD32F303xx
Symbol
Parameter
Conditions
Min
Typ
—
0.83
—
μA
—
0.51
—
μA
VDD not available, VBAT=3.3 V, LXTAL on
with external crystal, RTC on, Lower driving
VDD not available, VBAT=2.6 V, LXTAL on
with external crystal, RTC on, Lower driving
4.4
Max Unit
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the following table, based on the EMS levels and classes compliant with IEC 61000
series standard.
Table 6. EMS characteristics
Symbol
VESD
Parameter
Conditions
Voltage applied to all device pins to
VDD = 3.3 V, TA = +25 °C
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
induce a functional disturbance through
100 pF on VDD and VSS pins
Level/Class
3B
VDD = 3.3 V, TA = +25 °C
4A
conforms to IEC 61000-4-4
EMI (Electromagnetic Interference) emission testing result is given in the following table,
compliant with IEC 61967-2 standard which specifies the test board and the pin loading.
Table 7. EMI characteristics
Symbol
Parameter
Conditions
VDD = 5.0 V,
SEMI
Peak level
TA = +25 °C,
compliant with IEC
61967-2
Tested
frequency band
Conditions
Unit
24M
48M
0.1 to 2 MHz
<0
<0
2 to 30 MHz
-3.9
-2.8
30 to 130 MHz
-7.2
-8
130 MHz to 1GHz
-7
-7
dBμV
37 / 52
GD32F303xx
4.5
Power supply supervisor characteristics
Table 8. Power supply supervisor characteristics
Symbol
Parameter
Min
Typ
Max
Unit
2.30
2.40
2.48
V
1.72
1.80
1.88
V
PDR hysteresis
—
0.6
—
V
Reset temporization
—
2
—
ms
VPOR
Power on reset threshold
VPDR
Power down reset threshold
Conditions
—
VHYST
TRSTTEMP
4.6
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 9. ESD characteristics
Symbol
VESD(HBM)
VESD(CDM)
Parameter
Conditions
Electrostatic discharge
TA=25 °C; JESD22-
voltage (human body model)
A114
Electrostatic discharge
TA=25 °C;
voltage (charge device model)
JESD22-C101
Min
Typ
Max
Unit
—
—
6000
V
—
—
1000
V
Min
Typ
Max
Unit
—
—
±200
mA
—
—
5.4
V
Table 10. Static latch-up characteristics
Symbol
Parameter
Conditions
I-test
LU
TA=25 °C; JESD78
Vsupply over voltage
38 / 52
GD32F303xx
4.7
External clock characteristics
Table 11. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
Symbol
fHXTAL
CHXTAL
Parameter
Conditions
High Speed External oscillator
(HXTAL) frequency
Recommended load capacitance
on OSC_IN and OSC_OUT
Min
Typ
Max
Unit
VDD=5.0V
4
8
32
MHz
—
—
20
30
pF
—
—
400
—
KΩ
Recommended external feedback
RFHXTAL
resistor between OSC_IN and
OSC_OUT
DHXTAL
HXTAL oscillator duty cycle
—
30
50
70
%
IDDHXTAL
HXTAL oscillator operating current
VDD=3.3V, TA=25°C
—
1
—
mA
tSUHXTAL
HXTAL oscillator startup time
VDD=3.3V, TA=25°C
—
2
—
ms
Table 12. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
fLXTAL
Parameter
Min
Typ
Max
Unit
VDD=VBAT=3.3V
—
32.768
—
KHz
—
—
—
15
pF
LXTAL oscillator duty cycle
—
30
50
70
%
LXTAL oscillator operating
Low Drive
—
0.7
—
current
High Drive
—
1.3
—
μA
LXTAL oscillator startup time
VDD=VBAT=3.3V
—
2
—
Low Speed External oscillator
(LXTAL) frequency
Conditions
Recommended load
CLXTAL
capacitance on OSC32_IN
and OSC32_OUT
DLXTAL
IDDLXTAL
tSULXTAL
s
39 / 52
GD32F303xx
4.8
Internal clock characteristics
Table 13. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
8
—
MHz
VDD=3.3V, TA=-40°C ~+105°C
-4.0
—
+5.0
%
VDD=3.3V, TA=0°C ~ +85°C
-2.0
—
+2.0
%
VDD=3.3V, TA=25°C
-1.0
—
+1.0
%
—
—
0.5
—
%
VDD=3.3V, fIRC8M=8MHz
45
50
55
%
VDD=3.3V, fIRC8M=8MHz
—
66
80
μA
VDD=3.3V, fIRC8M=8MHz
—
2.5
4
us
Min
Typ
Max
Unit
—
48
—
MHz
High Speed Internal
fIRC8M
Oscillator (IRC8M)
VDD=3.3V
frequency
IRC8M oscillator Frequency
accuracy, Factory-trimmed
ACCIRC8M
IRC8M oscillator Frequency
accuracy, User trimming
step
DIRC8M
IDDIRC8M
tSUIRC8M
IRC8M oscillator duty cycle
IRC8M oscillator operating
current
IRC8M oscillator startup
time
Table 14. High speed internal clock (IRC48M) characteristics
Symbol
Parameter
Conditions
High Speed Internal
fIRC48M
Oscillator (IRC48M)
VDD=3.3V
frequency
IRC48M oscillator
VDD=3.3V, TA=-40°C ~+105°C
-4.0
—
+5.0
%
Frequency accuracy,
VDD=3.3V, TA=0°C ~ +85°C
-3.0
—
+3.0
%
Factory-trimmed
VDD=3.3V, TA=25°C
-2.0
—
+2.0
%
—
—
0.12
—
%
VDD=3.3V, fIRC48M=16MHz
45
50
55
%
VDD=3.3V, fIRC48M=16MHz
—
240
300
μA
VDD=3.3V, fIRC48M=16MHz
—
2.5
4
us
ACCIRC48M
IRC48M oscillator
Frequency accuracy, User
trimming step
DIRC48M
IDDIRC48M
tSUIRC48M
IRC48M oscillator duty
cycle
IRC48M oscillator operating
current
IRC48M oscillator startup
time
40 / 52
GD32F303xx
Table 15. Low speed internal clock (IRC32K) characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
20
40
45
KHz
VDD=VBAT=3.3V, TA=25°C
—
0.4
0.6
μA
VDD=VBAT=3.3V, TA=25°C
—
110
130
μs
Conditions
Min
Typ
Max
Unit
—
1
—
25
MHz
PLL output clock frequency —
16
—
120
MHz
—
32
—
240
MHz
—
—
—
300
μs
VCO freq=240MHz
—
450
—
μA
VCO freq=240MHz
—
680
—
μA
System clock
—
300
—
ps
Min
Typ
Max
Unit
—
1
—
25
MHz
PLL output clock frequency —
16
—
100
MHz
—
32
—
200
MHz
—
—
—
300
μs
VCO freq=200MHz
—
290
—
μA
VCO freq=200MHz
—
440
—
μA
System clock
—
300
—
ps
Low Speed Internal
fIRC32K
VDD=VBAT=3.3V,
oscillator (IRC32K)
TA=-40°C ~ +85°C
frequency
IDDIRC32K
tSUIRC32K
4.9
IRC32K oscillator operating
current
IRC32K oscillator startup
time
PLL characteristics
Table 16. PLL characteristics
Symbol
fPLLIN
fPLLOUT
fVCOOUT
tLOCK
IDD
IDDA
JitterPLL
Parameter
PLL input clock frequency
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDD
Current consumption on
VDDA
Cycle to cycle Jitter
Table 17. PLL2/3 characteristics
Symbol
fPLLIN
fPLLOUT
fVCOOUT
tLOCK
IDD
IDDA
JitterPLL
Parameter
PLL input clock frequency
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDD
Current consumption on
VDDA
Cycle to cycle Jitter
Conditions
41 / 52
GD32F303xx
4.10
Memory characteristics
Table 18. Flash memory characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
TA=-40°C ~ +85°C
100
—
—
kcycles
Data retention time
TA=125°C
20
—
—
years
tPROG
Word programming time
TA=-40°C ~ +85°C
200
—
400
us
tERASE
Page erase time
TA=-40°C ~ +85°C
60
100
450
ms
tMERASE
Mass erase time
TA=-40°C ~ +85°C
3.2
—
9.6
s
Number of guaranteed
PECYC
program /erase cycles
before failure (Endurance)
tRET
42 / 52
GD32F303xx
4.11
GPIO characteristics
Table 19. I/O port characteristics
Symbol
Parameter
Standard IO Low level
input voltage
Conditions
Min
Typ
Max
VDD=2.6V
—
—
0.97
VDD=3.3V
—
—
1.29
VDD=3.6V
—
—
1.42
VDD=2.6V
—
—
0.98
VDD=3.3V
—
—
1.29
VDD=3.6V
—
—
1.41
VDD=2.6V
1.67
—
—
VDD=3.3V
1.97
—
—
VDD=3.6V
2.09
—
—
VDD=2.6V
1.64
—
—
VDD=3.3V
1.97
—
—
VDD=3.6V
2.07
—
—
VDD=2.6V, IIO=8mA
—
—
0.17
VDD=3.3V, IIO=8mA
—
—
0.15
VDD=3.6V, IIO=8mA
—
—
0.15
VDD=2.6V, IIO=20mA
—
—
0.49
VDD=3.3V, IIO=20mA
—
—
0.40
VDD=3.6V, IIO=20mA
—
—
0.40
VDD=2.6V, IIO=8mA
2.40
—
—
VDD=3.3V, IIO=8mA
3.11
—
—
VDD=3.6V, IIO=8mA
3.44
—
—
VDD=2.6V, IIO=20mA
2.02
—
—
VDD=3.3V, IIO=20mA
2.81
—
—
VDD=3.6V, IIO=20mA
3.15
—
—
Unit
V
VIL
High Voltage tolerant IO
Low level input voltage
Standard IO High level
input voltage
VIH
High Voltage tolerant IO
High level input voltage
VOL
VOH
RPU
RPD
Low level output voltage
High level output voltage
V
V
VIN=VSS
30
40
50
up resistor
PA10
—
7.5
10
13.5
Internal
All pins
VIN=VDD
30
40
50
PA10
—
7.5
10
13.5
pull-
pull-
down resistor
V
V
All pins
Internal
V
kΩ
kΩ
43 / 52
GD32F303xx
4.12
ADC characteristics
Table 20. ADC characteristics
Symbol
VDDA
VADCIN
fADC
fS
VIN
Parameter
Conditions
Min
Typ
Max
Unit
Operating voltage
—
2.6
3.3
3.6
V
ADC input voltage range
—
0
—
VREF+
V
ADC clock
—
0.1
—
40
MHz
12-bit
0.007
—
2.86
10-bit
0.008
—
3.33
8-bit
0.01
—
4.00
6-bit
0.012
—
5.00
0
—
VDDA
V
Sampling rate
Analog input voltage
16 external;2 internal
MSPS
VREF+
Positive Reference Voltage —
—
VDDA
—
V
VREF-
Negative Reference Voltage —
—
0
—
V
RAIN
External input impedance
See Equation 2
—
—
32.9
kΩ
—
—
—
0.55
kΩ
RADC
Input sampling switch
resistance
CADC
Input sampling capacitance No pin/pad capacitance included
—
—
5.5
pF
tCAL
Calibration time
fADC=40MHz
—
3.275
—
μs
Sampling time
fADC=40MHz
0.0375
—
5.99
μs
12-bit
—
14
—
Total conversion time
10-bit
—
12
—
(including sampling time)
8-bit
—
10
—
6-bit
—
8
—
—
—
—
1
ts
tCONV
tSU
Startup time
Equation 2: RAIN max formula R AIN <
Ts
fADC ∗CADC ∗ln(2N+2 )
1/ fADC
μs
− R ADC
The formula above (Equation 2) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N=12 (from 12-bit resolution).
Table 21. ADC RAIN max for fADC=40MHz
Ts (cycles)
ts (us)
RAIN max (KΩ)
1.5
0.0375
0.15
7.5
0.1875
2.96
13.5
0.3375
5.77
28.5
0.7125
12.8
41.5
1.0375
18.9
55.5
1.3875
25.4
71.5
1.7875
32.9
239.5
5.9875
N/A
Note: Guaranteed by design, not tested in production.
44 / 52
GD32F303xx
Table 22. ADC dynamic accuracy at fADC = 30 MHz
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC=30MHz
10.5
10.6
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA=VREFP=2.6V
65
65.6
—
SNR
Signal-to-noise ratio
Input Frequency=110KHz
65.5
66
—
THD
Total harmonic distortion
Temperature=25℃
-74
-76
—
dB
Table 23. ADC dynamic accuracy at fADC = 30 MHz
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC=30MHz
10.7
10.8
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA=VREFP=3.3V
66.2
65.8
—
SNR
Signal-to-noise ratio
Input Frequency=110KHz
66.8
67.4
—
THD
Total harmonic distortion
Temperature=25℃
-71
-75
—
dB
Table 24. ADC dynamic accuracy at fADC = 36 MHz
Symbol
Parameter
ENOB
Effective number of bits
SNDR
SNR
THD
Test conditions
Min
Typ
Max
Unit
fADC=36MHz
10.3
10.4
—
bits
Signal-to-noise and distortion ratio
VDDA=VREFP=3.3V
63.8
64.4
—
Signal-to-noise ratio
Input Frequency=110KHz
64.2
65
—
Total harmonic distortion
Temperature=25℃
-70
-72
—
dB
Table 25. ADC dynamic accuracy at fADC = 40 MHz
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
ENOB
Effective number of bits
fADC=40MHz
9.9
10.0
—
bits
SNDR
Signal-to-noise and distortion ratio
VDDA=VREFP=3.3V
61.4
62
—
SNR
Signal-to-noise ratio
Input Frequency=110KHz
62
62.4
—
THD
Total harmonic distortion
Temperature=25℃
-68
-70
—
Typ
Max
±2
±3
±0.9
±1.2
±1.1
±1.5
dB
Table 26. ADC static accuracy at fADC = 15 MHz
Symbol
Parameter
Offset
Offset error
DNL
Differential linearity error
INL
Integral linearity error
Test conditions
fADC=15MHz
VDDA=VREFP=3.3V
Unit
LSB
45 / 52
GD32F303xx
4.13
DAC characteristics
Table 27. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.6
3.3
3.6
V
5
—
—
kΩ
—
—
15
kΩ
—
—
50
pF
0.2
—
—
V
0.5
—
—
mV
—
—
—
—
Middle code on the input
—
—
500
Worst code on the input
—
—
560
10-bit configuration
—
—
±0.5
12-bit configuration
—
—
±2
10-bit configuration
—
—
±1
12-bit configuration
—
—
±4
Gain error
—
—
±0.5
—
%
Settling time
CLOAD≤50pF, RLOAD≥5kΩ
—
0.5
1
μs
CLOAD≤50pF, RLOAD≥5kΩ
—
—
4
MS/s
CLOAD≤50pF, RLOAD≥5kΩ
—
1
2
μs
No RLoad, CLOAD=50pF
—
-90
-75
dB
VDDA
Operating voltage
—
RLOAD
Resistive load
Resistive load with buffer ON
RO
CLOAD
Impedance output
Capacitive load
Impedance output with buffer
OFF
Capacitive load with buffer ON
Lower DAC_OUT voltage with
DAC_OUTmin Lower DAC_OUT voltage
buffer ON
Lower DAC_OUT voltage with
buffer OFF
Higher DAC_OUT voltage with
buffer ON
DAC_OUTmax Higher DAC_OUT voltage
Higher DAC_OUT voltage with
buffer OFF
DC current
IDDA
DNL
Differential non linearity
INL
Integral non linearity
TSETTLING
0.2
VDDA1LSB
consumption in quiescent
mode with no load
Gain error
VDDA-
V
V
μA
LSB
LSB
Max frequency for a
Update rate
correct DAC_OUT
change from code i to
i±1LSB
TWAKEUP
PSRR
Wakeup time from off
state
Power supply rejection
ratio
46 / 52
GD32F303xx
4.14
SPI characteristics
Table 28. SPI characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
30
MHz
TSIK(H)
SCK clock high time
—
16
—
—
ns
TSIK(L)
SCK clock low time
—
16
—
—
ns
SPI master mode
tV(MO)
Data output valid time
—
—
—
25
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
SPI slave mode
4.15
tSU(NSS)
NSS enable setup time
fPCLK=54MHz
74
—
—
ns
tH(NSS)
NSS enable hold time
fPCLK=54MHz
37
—
—
ns
tA(SO)
Data output access time
fPCLK=54MHz
0
—
55
ns
tDIS(SO)
Data output disable time
—
3
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
I2C characteristics
Table 29. I2C characteristics
Symbol
4.16
Parameter
Conditions
Standard mode
Fast mode
Min
Max
Min
Max
Unit
fSCL
SCL clock frequency
—
0
100
0
1000
KHz
TSIL(H)
SCL clock high time
—
4.0
—
0.6
—
ns
TSIL(L)
SCL clock low time
—
4.7
—
1.3
—
ns
USART characteristics
Table 30. USART characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
84
MHz
TSIK(H)
SCK clock high time
—
5.5
—
—
ns
TSIK(L)
SCK clock low time
—
5.5
—
—
ns
47 / 52
GD32F303xx
5
Package information
5.1
LQFP package outline dimensions
Figure 8. LQFP package outline
48 / 52
GD32F303xx
Table 31. LQFP package dimensions
Symbol
LQFP48
LQFP64
LQFP100
LQFP144
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
A
1.20
-
1.60
-
-
1.60
-
-
1.60
-
-
1.60
A1
0.05
-
0.15
0.05
-
0.15
0.05
-
0.15
0.05
-
0.15
A2
0.95
1.00
1.05
1.35
1.40
1.45
1.35
1.40
1.45
1.35
1.40
1.45
D
-
9.00
-
-
12.00
-
-
16.00
-
-
22.00
-
D1
-
7.00
-
-
10.00
-
-
14.00
-
-
20.00
-
E
-
9.00
-
-
12.00
-
-
16.00
-
-
22.00
-
E1
-
7.00
-
-
10.00
-
-
14.00
-
-
20.00
-
R1
0.08
-
-
0.08
-
-
0.08
-
-
0.08
-
-
R2
0.08
-
0.20
0.08
-
0.20
0.08
-
0.20
0.08
-
0.20
θ
0°
3.5°
7°
0°
3.5°
7°
0°
3.5°
7°
0°
3.5°
7°
θ1
0°
-
-
0°
-
-
0°
-
-
0°
-
-
θ2
11°
12°
13°
11°
12°
13°
11°
12°
13°
11°
12°
13°
θ3
11°
12°
13°
11°
12°
13°
11°
12°
13°
11°
12°
13°
c
0.09
-
0.20
0.09
-
0.20
0.09
-
0.20
0.09
-
0.20
L
0.45
0.60
0.75
0.45
0.60
0.75
0.45
0.60
0.75
0.45
0.60
0.75
L1
-
1.00
-
-
1.00
-
-
1.00
-
-
1.00
-
S
0.20
-
-
0.20
-
-
0.20
-
-
0.20
-
-
b
0.17
0.22
0.27
0.17
0.20
0.27
0.17
0.20
0.27
0.17
0.20
0.27
e
-
0.50
-
-
0.50
-
-
0.50
-
-
0.50
-
D2
-
5.50
-
-
7.50
-
-
12.00
-
-
17.50
-
E2
-
5.50
-
-
7.50
-
-
12.00
-
-
17.50
-
aaa
0.20
0.20
0.20
0.20
bbb
0.20
0.20
0.20
0.20
ccc
0.08
0.08
0.08
0.08
(Original dimensions are in millimeters)
49 / 52
GD32F303xx
6
Ordering Information
Table 32. Part ordering code for GD32F303xx devices
Ordering code
Flash (KB)
Package
Package type
GD32F303CCT6
256
LQFP48
Green
GD32F303CET6
512
LQFP48
Green
GD32F303CGT6
1024
LQFP48
Green
GD32F303RCT6
256
LQFP64
Green
GD32F303RET6
512
LQFP64
Green
GD32F303RGT6
1024
LQFP64
Green
GD32F303RIT6
2048
LQFP64
Green
GD32F303RKT6
3072
LQFP64
Green
GD32F303VCT6
256
LQFP100
Green
GD32F303VET6
512
LQFP100
Green
GD32F303VGT6
1024
LQFP100
Green
GD32F303VIT6
2048
LQFP100
Green
GD32F303VKT6
3072
LQFP100
Green
GD32F303ZCT6
256
LQFP144
Green
GD32F303ZET6
512
LQFP144
Green
GD32F303ZGT6
1024
LQFP144
Green
GD32F303ZIT6
2048
LQFP144
Green
GD32F303ZKT6
3072
LQFP144
Green
Temperature
operating range
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
Industrial
-40°C to +85°C
50 / 52
GD32F303xx
7
Revision History
Table 33. Revision history
Revision No.
1.0
Description
Initial Release
Date
Mar.25, 2017
51 / 52
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement