Rev 2; 5/06 3.3V Center Spread-Spectrum EconOscillator™ Features The DS1089L is a clock generator that produces a spread spectrum (dithered) square-wave output of frequencies from 130kHz to 66.6MHz. The DS1089L is shipped from the factory programmed at a specific frequency. The DS1089L is pin-for-pin compatible with the DS1087L, however, the DS1089L dithers at equal percentages above and below the center frequency. The user still has access to the internal frequency divider, selectable ±1%, ±2%, ±4%, or ±8% dithered output, dithering rate, and programmable output powerdown/disable mode through an I2C-compatible programming interface. All the device settings are stored in nonvolatile (NV) EEPROM allowing it to operate in stand-alone applications. The DS1089L also has power-down and output-enable control pins for powersensitive applications. ♦ Factory-Programmed Square-Wave Generator from 33.3MHz to 66.6MHz ♦ Center Frequency Remains Constant Independent of Dither Percentage ♦ No External Timing Components Required ♦ EMI Reduction ♦ Variable Dither Frequency ♦ User Programmable Down to 130kHz with Divider (Dependent on Master Oscillator Frequency) ♦ ±1%, ±2%, ±4%, or ±8% Selectable Dithered Output ♦ Glitchless Output-Enable Control ♦ I2C-Compatible Serial Interface ♦ Nonvolatile Settings ♦ Power-Down Mode ♦ Programmable Output Power-Down/Disable Mode Applications Automotive Infotainment Printers Ordering Information Copiers Computer Peripherals PART POS Terminals DS1089LU-yxx* Cable Modems TEMP RANGE PIN-PACKAGE -40°C to +85°C 8 µSOP (118 mil) *See Standard Frequency Options Table. Pin Configuration and Typical Operating Circuits appear at end of data sheet. Standard Frequency Options FREQUENCY (MHz) SPREAD (±%) DITHER FREQUENCY DS1089LU-21G PART 14.7456 1 fMOSC / 4096 DS1089LU-4CL 18.432 2 fMOSC / 4096 DS1089LU-22F 24.576 1 fMOSC / 2048 DS1089LU-23C 33.3 1 fMOSC / 4096 DS1089LU-450 50.0 2 fMOSC / 4096 DS1089LU-866 66.6 4 fMOSC / 4096 DS1089LU-yxx Fixed up to 66.6 1, 2, 4, or 8 fMOSC / 2048 or 4096 or 8192 Add “/T” for Tape and Reel. Custom frequencies available, contact factory. EconOscillator is a trademark of Dallas Semiconductor Corp. ______________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1089L General Description DS1089L 3.3V Center Spread-Spectrum EconOscillator™ ABSOLUTE MAXIMUM RATINGS Voltage on VCC Relative to Ground.......................-0.5V to +6.0V Voltage on SPRD, PDN, OE, SDA, SCL Relative to Ground* ........................-0.5V to (VCC + 0.5V) Operating Temperature Range ...........................-40°C to +85°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................See IPC/JEDEC J-STD-020A *This voltage must not exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER SYMBOL Supply Voltage VCC High-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) VIH Low-Level Input Voltage (SDA, SCL, SPRD, PDN, OE) VIL CONDITION (Note 1) MIN TYP MAX UNITS 2.7 3.3 3.6 V VCC + 0.3 V 0.3 x VCC V MAX UNITS 0.7 x VCC -0.3 DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.6V, TA = -40°C to +85°C) PARAMETER SYMBOL High-Level Output Voltage (OUT) VOH IOH = -4mA, VCC = min Low-Level Output Voltage (OUT) VOL IOL = 4mA 0.4 VOL1 3mA sink current 0.4 VOL2 6mA sink current 0.6 Low-Level Output Voltage (SDA) CONDITION MIN TYP 2.4 V V High-Level Input Current IIH VIH = VCC Low-Level Input Current IIL VIL = 0V ICC CL = 15pF, fOUT = fMOSCmax 12 mA Power-down mode 10 µA Supply Current (Active) Standby Current (Power-Down) 2 ICCQ _____________________________________________________________________ 1 V -1 µA µA 3.3V Center Spread-Spectrum EconOscillator™ DS1089L MASTER OSCILLATOR CHARACTERISTICS (VCC = +2.7V to +3.6V, TA = -40°C to +85°C) PARAMETER Internal Master Oscillator Frequency Master Oscillator Frequency Tolerance Voltage Frequency Variation Temperature Frequency Variation (Note 4) SYMBOL CONDITION MAX UNITS 33.3 66.6 MHz VCC = 3.3V, TA = +25°C (Notes 2, 10) -0. 5 +0. 5 % TA = +25°C (Note 3) -0.75 +0.75 % TA = 0°C to +85°C -0.75 +0.75 TA = -40°C to 0°C -2.00 +0.75 fMOSC ∆fMOSC fMOSC ∆f fMOSC ∆f fMOSC Dither Frequency Range (Note 5) VCC = 3.3V, fOUT = fMOSCmax MIN % J3 = J2 = GND ±1 J3 = GND, J2 = VCC ±2 J3 = VCC, J2 = GND ±4 J3 = J2 = VCC Dither Frequency (Note 5) fMOD TYP % ±8 J1 = GND, J0 = VCC fMOSC / 2048 J1 = VCC, J0 = GND fMOSC / 4096 J1 = J0 = VCC fMOSC / 8192 Hz AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.6V, TA = -40°C to +85°C) PARAMETER SYMBOL CONDITION MIN TYP Frequency Stable After PRESCALER Change Power-Up Time tPOR + tSTAB (Note 6) Enable of OUT After Exiting Power-Down Mode tSTAB (Note 6) OUT Disabled After Entering Power-Down Mode tPDN 7 CL 15 Load Capacitance Output Duty Cycle (fOUT) 40 50 MAX UNITS 1 Period 200 µs 512 clock cycles µs 50 pF % _____________________________________________________________________ 3 DS1089L 3.3V Center Spread-Spectrum EconOscillator™ AC ELECTRICAL CHARACTERISTICS—I2C INTERFACE (VCC = +2.7V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS TYP UNITS 400 kHz fSCL Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs tHD:STA 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Setup Time tSU:DAT 100 Start Setup Time tSU:STA 0.6 SDA and SCL Rise Time SDA and SCL Fall Time Stop Setup Time 0 MAX SCL Clock Frequency Hold Time (Repeated) Start Condition (Note 7) MIN µs 0.9 ns µs tR (Note 8) 20 + 0.1CB 300 tF (Note 8) 20 + 0.1CB 300 tSU:STO 0.6 SDA and SCL Capacitive Loading CB (Note 8) EEPROM Write Time tWR (Note 9) µs ns ns µs 400 pF 10 20 ms TYP MAX UNITS NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.7V to +3.6V) PARAMETER Writes SYMBOL CONDITION +70°C MIN 10,000 All voltages are referenced to ground. This is the absolute accuracy of the master oscillator frequency at the default settings with spread disabled. This is the change that is observed in master oscillator frequency with changes in voltage at TA = +25°C. This is the change that is observed in master oscillator frequency with changes in temperature at VCC = 3.3V. The dither deviation of the master oscillator frequency is biderectional and results in an output frequency centered at the undithered frequency. Note 6: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tSTAB is equivalent to 512 master clock cycles and will depend on the programmed master oscillator frequency. Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing. Note 8: CB—total capacitance of one bus line in picofarads. Note 9: EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when WC = 0. The EEPROM write time begins after a stop condition occurs. Note 10: Typical frequency shift due to aging is ±0.25%. Aging stressing includes Level 1 moisture reflow conditioning (24hr) +125°C bake, 168hr +85°C/85°RH moisture soak, and three solder reflow passes +260 +0/-5°C peak) followed by 408hr max VCC biased 125°C HTOL, 500 temperature cycles at -55°C to +125°C, 96hr +130°C/85%RH/3,6V HAST and 168hr +121°C/2 ATM Steam/Unbiased Autoclave. Note 1: Note 2: Note 3: Note 4: Note 5: 4 _____________________________________________________________________ 3.3V Center Spread-Spectrum EconOscillator™ ACTIVE SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) 50MHz 130kHz 33MHz 2 66MHz 7 6 5 4 50MHz 3 10 130kHz 33MHz TA = +25°C, fMOSC = 50MHz, OUTPUT UNLOADED 8 2 DS 1089L toc03 8 6 4 TA = +25°C, OUTPUT UNLOADED 9 DS 1089L toc02 8 66MHz 10 SUPPLY CURRENT (mA) TA = +25°C, OUTPUT UNLOADED DS 1089L toc01 10 SUPPLY CURRENT vs. PRESCALER SUPPLY CURRENT (mA) ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 6 4 3.6V 3.3V 2.7V 2 1 0 0 2.7 3.0 3.3 3.6 -15 10 35 60 0 85 1 10 1000 PRESCALE DIVIDER (DECIMAL) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE FREQUENCY % CHANGE vs. SUPPLY VOLTAGE FREQUENCY % CHANGE vs. TEMPERATURE FREQUENCY CHANGE (%) 3 2 33MHz 0.25 66MHz 130kHz 0 0.2 DS 1089L toc05 4 TA = +25°C FREQUENCY CHANGE (%) DS 1089L toc04 0.50 -0.25 1 VCC = 3.3V 0 130kHz -0.2 -0.4 50MHz 66MHz -0.6 33MHz 50MHz 0 -0.50 -15 10 35 TEMPERATURE (°C) 60 85 DS 1089L toc06 TEMPERATURE (°C) VCC = 3.3V, PDN = GND -40 100 SUPPLY VOLTAGE (V) 5 SUPPLY CURRENT (µA) -40 -0.8 2.7 3.0 3.3 SUPPLY VOLTAGE (V) 3.6 -40 -15 10 35 60 85 TEMPERATURE (°C) _____________________________________________________________________ 5 DS1089L Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) 56 66MHz 33MHz DUTY CYCLE (%) 50MHz VCC = 3.3V 54 52 50MHz 54 52 33MHz 50 -10 POWER SPECTRUM (dBm) 66MHz 0 DS 1089L toc08 TA = +25°C 56 58 DS 1089L toc07 58 SPECTRUM COMPARISON (120kHz BW, SAMPLE DETECT) DUTY CYCLE vs. TEMPERATURE 2.7 3.0 3.3 SUPPLY VOLTAGE (V) NO SPREAD -20 -30 -40 ±8% ±4% -50 -60 fMOSC = 50MHz, DITHER RATE = fMOSC / 4096 -80 130kHz 3.6 ±1% -70 50 130kHz 48 ±2% DS 1089L toc09 DUTY CYCLE vs. SUPPLY VOLTAGE DUTY CYCLE (%) DS1089L 3.3V Center Spread-Spectrum EconOscillator™ -90 48 -40 -15 10 35 60 85 TEMPERATURE (°C) 44 46 48 50 52 54 56 FREQUENCY (MHz) Pin Description 6 PIN NAME 1 OUT Oscillator Output FUNCTION 2 SPRD Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled. 3 VCC Power Supply 4 GND Ground 5 OE Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is disabled but the internal master oscillator is still on. 6 PDN Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master oscillator and the output buffer are disabled (power-down mode). 7 SDA I2C Serial Data. This pin is for serial data transfer to and from the device. 8 SCL I2C Serial Clock. This pin is used to clock data into and out of the device. _____________________________________________________________________ 3.3V Center Spread-Spectrum EconOscillator™ PDN H/W GATED OUTPUT OE DS1089L SDA CONTROL REGISTERS I2C I2C SERIAL ADDRESS INTERFACE BITS OUTPUT CONTROL S/W GATED OUTPUT SCL ADDR J3 J2 OE X WC A2 A1 A0 WRITE EE COMMAND EEPROM WRITE CONTROL FACTORYPROGRAMMED MASTER OSCILLATOR PRESCALER fMOSC DIVIDE BY 1, 2, 4, 8, 16, 32, 64, 128, OR 256 33.3MHz TO 66.6MHz fOSC SYNCED OUTPUT BUFFER fOUT OUT f MOD EEPROM DITHER RATE DITHER % VCC J1 J0 VCC LO/ HIZ X P3 P2 P1 TRIANGLEWAVE GENERATOR fMOSC P0 PRESCALER SETTING GND OUTPUT CONFIGURATION PRESCALER SPRD Detailed Description Master Oscillator The internal master oscillator is capable of generating a square wave with a 33.3MHz to 66.6MHz frequency range. The master oscillator frequency (fMOSC) is factory programmed, and is specified in the Ordering Information. Prescaler The user can program the prescaler divider to produce an output frequency (fOUT) as low as 130kHz using bits P0, P1, P2, and P3 in the PRESCALER register. The output frequency can be calculated using Equation 1. Any value programmed greater than 28 will be decoded as 28. See Table 1 for prescaler divider settings. Table 1. Prescaler Divider Settings BITS P3, P2, P1, P0 2x = 0000 1 fMOSC 0001 2 fMOSC / 2 0010 4 fMOSC / 4 0011 8 fMOSC / 8 0100 16 fMOSC / 16 0101 32 fMOSC / 32 0110 64 fMOSC / 64 0111 128 fMOSC / 128 1000 256 fMOSC / 256 1111 256 fMOSC / 256 fOUT = fOSC Equation 1 f Output Frequency (Hz) fOSC = MOSC 2x where x = P3, P2, P1, P0 _____________________________________________________________________ 7 DS1089L Block Diagram DS1089L 3.3V Center Spread-Spectrum EconOscillator™ Output Control Dither Percentage Settings Two user control signals control the output. The output enable pin (OE) gates the output buffer and the powerdown pin (PDN) disables the master oscillator and turns off the output for power-sensitive applications. (Note: the power-down command must persist for at least two output frequency cycles plus 10µs for deglitching purposes.) On power-up, the output is disabled until power is stable and the master oscillator has generated 512 clock cycles. Additionally, the OE input is OR’ed with the OE bit in the ADDR register, allowing for either hardware or software gating of the output waveform (see the Block Diagram). Both controls feature a synchronous enable, which ensures that there are no output glitches when the output is enabled. The synchronous enable also ensures a constant time interval (for a given frequency setting) from an enable signal to the first output transition. The dither amplitude (measured in percentage of the master oscillator center frequency) is set using the J2 and J3 bits in the ADDR register. This circuit uses a sense current from the master oscillator bias circuit to adjust the amplitude of the triangle-wave signal to a voltage level that modulates the master oscillator to a percentage of its factory-programmed center frequency. This percentage is set in the application to be ±1%, ±2%, ±4%, or ±8% (see Table 3). The location of bits P3, P2, P1, P0, J1, and J0 in the PRESCALER register and bits J3 and J2 in the ADDR register are shown in the Register Summary section. Dither Generator The DS1089L has the ability to reduce radiated emission peaks. The output frequency can be dithered by ±1%, ±2%, ±4%, or ±8% symmetrically around the programmed center frequency. Although the output frequency changes when the dither is enabled, the duty cycle does not change. The dither rate (fMOD) is controlled by the J0 and J1 bits in the PRESCALER register and is enabled with the SPRD pin. The maximum spectral attenuation occurs when the prescaler is set to 1. The spectral attenuation is reduced by 2.7dB for every factor of 2 that is used in the prescaler. This happens because the prescaler’s divider function tends to average the dither in creating the lower frequency. However, the most stringent spectral emission limits are imposed on the higher frequencies where the prescaler is set to a low divider ratio. A triangle-wave generator injects an offset element into the master oscillator to dither its output. The dither rate can be calculated based on the master oscillator frequency (see Equation 2). Table 2. Dither Frequency Settings BITS J1, J0 DITHER FREQUENCY 00 No dither 01 fMOSC / 2048 10 fMOSC / 4096 11 fMOSC / 8192 Table 3. Dither Percentage Settings BITS J3, J2 DITHER AMOUNT 00 ±1% 01 ±2% 10 ±4% 11 ±8% Equation 2 f fMOD = MOSC n where fMOD = dither frequency, fMOSC = master oscillator frequency, and n = divider setting (see Table 2). 8 _____________________________________________________________________ 3.3V Center Spread-Spectrum EconOscillator™ DS1089L When dither is enabled (by selecting a dither frequency setting greater than 0 with SPRD high), the master oscillator frequency is dithered around the center frequency by the selected percentage from the programmed fMOSC (see Figure 2). For example, if fMOSC is programmed to 40MHz (factory setting) and the dither amount is programmed to ±1%, the frequency of fMOSC will dither between 39.6MHz and 40.4MHz at a modulation frequency determined by the selected dither frequency. Continuing with the same example, if J1 = 0 and J0 = 1, selecting fMOSC / 2048, then the dither frequency would be 19.531kHz. IF DITHER AMOUNT = 0% (+1, 2, 4, OR 8% OF fMOSC) PROGRAMMED fMOSC (-1, 2, 4, OR 8% OF fMOSC) fMOSC DITHER AMOUNT (2, 4, 8, OR 16%) 1 fMOD Register Summary The DS1089L registers are used to change the dither amount, output frequency, and slave address. A bit summary of the registers is shown in Table 4. Once programmed into EEPROM, the settings only need to be reprogrammed if it is desired to reconfigure the device. TIME Figure 2. Output Frequency vs. Dither Rate ADDR Register PRESCALER Register Bits 7 to 6: Bit 5: Bit 4: Bits 3 to 0: Dither Frequency. The J1 and J0 bits control the dither frequency applied to the output. See Table 2 for divider settings. If either of bits J1 or J0 is high and SPRD is high, dither is enabled. Output Low or Hi-Z. The LO/HIZ bit determines the state of the output during power-down. While the output is deactivated, if the LO/HIZ bit is set to 0, the output will be high impedance (high-Z). If the LO/HIZ bit is set to 1, the output will be driven low. Bits 7 to 6: Dither Percentage. The J3 and J2 bits control the selected dither amplitude (%). When both J3 and J2 are set to 0, the default dither rate is ±1%. Bit 5: Output Enable. The OE bit and the OE pin state determine if the output is on when the device is active (PDN = VIH). If (OE = 0 OR OE is high) AND the PDN pin is high, the output will be driven. Reserved. Write Control. The WC bit determines if the EEPROM is to be written after register contents have been changed. If WC = 0 (default), EEPROM is written automatically after a write. If WC = 1, the EEPROM is only written when the WRITE EE command is issued. See the WRITE EE Command section for more information. Address. The A0, A1, A2 bits determine the lower nibble of the I2C slave address. Bit 4: Bit 3: Reserved. Prescaler Divider. The prescaler bits (bits P3 to P0) divide the master oscillator frequency by 2x where x can be from 0 to 8. Any prescaler bit value entered that is greater than 8 will decode as 8. See Table 1 for prescaler settings. Bits 2 to 0: Table 4. Register Summary ADDR BIT7 PRESCALER 02h J1 J0 LO/ HIZ X P3 P2 ADDR 0Dh J3 J2 OE X WC A2 WRITE EE 3Fh REGISTER BINARY No Data BIT0 DEFAULT ACCESS P1 P0 xx00xxxxb R/W A1 A0 xx100000b R/W — — X = “don’t care” x = values depend on custom settings _____________________________________________________________________ 9 DS1089L 3.3V Center Spread-Spectrum EconOscillator™ bit, the value of the ADDR register is always written immediately to EEPROM. When the WRITE EE command has been received, the contents of the registers are written into the EEPROM, thus locking in the register settings. WRITE EE Command The WRITE EE command is useful in closed-loop applications where the registers are frequently written. In applications where the register contents are frequently written, the WC bit should be set to 1 to prevent wearing out the EEPROM. Regardless of the value of the WC I2C Serial Port Operation SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERRED Figure 3. I2C Data Transfer Protocol LSB MSB 1 0 1 1 DEVICE IDENTIFIER A2 A1 DEVICE ADDRESS A0 R/W READ/WRITE BIT Figure 4. Slave Address Byte 10 9 ACK ____________________________________________________________________ STOP CONDITION OR REPEATED START CONDITION 3.3V Center Spread-Spectrum EconOscillator™ DS1089L SDA tBUF tSP tHD:STA tLOW tR tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 5. I2C AC Characteristics TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 0 1 1 A2* A1* A0* R/W DEVICE ADDRESS DEVICE IDENTIFIER MSB SLAVE ACK READ/ WRITE b7 b5 b4 b3 b2 b1 b0 SLAVE ACK b7 COMMAND/REGISTER ADDRESS EXAMPLE I2C TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO) B0h 02h DATA SLAVE SLAVE A) SINGLE BYTE WRITE 10000000 START 1 0 1 1 0 0 0 0 ACK 0 0 0 0 0 0 1 0 ACK -WRITE PRESCALER REGISTER TO 128 B0h B) SINGLE BYTE READ -READ PRESCALER REGISTER MSB LSB b6 START 1 0 1 1 0 0 0 0 02h SLAVE SLAVE 00000010 ACK ACK b5 b4 b3 b2 b1 b0 SLAVE ACK STOP DATA SLAVE ACK STOP B1h REPEATED START LSB b6 10110001 DATA MASTER SLAVE 10000000 NACK ACK STOP *THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST MATCH THE ADDRESS SET IN THE ADDR REGISTER. Figure 6. I2C Transactions Applications Information Power-Supply Decoupling To achieve the best results when using the DS1089L, decouple the power supply with 0.01µF and 0.1µF high-quality, ceramic, surface-mount capacitors. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. These capacitors should be placed as close to the VCC and GND pins as possible. Stand-Alone Mode SCL and SDA cannot be left floating even in standalone mode. If the DS1089L will never need to be programmed in-circuit, including during production testing, SDA and SCL can be connected high. ____________________________________________________________________ 11 DS1089L 3.3V Center Spread-Spectrum EconOscillator™ Typical Operating Circuits STAND-ALONE MODE PROCESSOR-CONTROLLED MODE VCC DITHERED 130kHz TO 66.6MHz OUTPUT 4.7kΩ OUT SCL DS1089L SDA VCC OUT XTL1/OSC1 2-WIRE INTERFACE VCC SPRD DITHERED 130kHz TO 66.6MHz OUTPUT 4.7kΩ SCL* VCC XTL2/OSC2 N.C. SPRD VCC DS1089L SDA* MICROPROCESSOR VCC PDN VCC PDN GND OE GND OE DECOUPLING CAPACITORS (0.1µF and 0.01µF) DECOUPLING CAPACITORS (0.1µF and 0.01µF) *SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1089L NEVER NEEDS TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING. Pin Configuration Chip Topology TRANSISTOR COUNT: 5985 SUBSTRATE CONNECTED TO GROUND TOP VIEW OUT 1 8 SCL SPRD 2 7 SDA DS1089L VCC 3 6 PDN GND 4 5 OE Package Information For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. µSOP (118 mils) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Dallas Semiconductor Corporation. is a registered trademark of Maxim Integrated Products.
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