integrated processor user`s manual

• •

M

6340UM/AD

INTEGRATED

PROCESSOR

USER'S MANUAL

@

MOTOROLA

MC68340

Integrated Processor User's Manual

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and

® are registered trademarks of

Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action

Employer.

©MOTOROLA INC., 1990

PREFACE

The complete documentation package for the MC68340 consists ofthe MC68340

Integrated Processor Unit User's Manual

(MC68340UM/AD) and the MC68340

Integrated Processor Unit Technical Summary

(MC68340ID).

The MC68340 Integrated Processor Unit User's Manual describes the programming, capabilities, registers, and operation of the MC68340. The MC68340 In-

tegrated Processor Unit Technical Summary

provides a description of the

MC68340 capabilities and detailed electrical specifications.

This user's manual is organized as follows:

Section 1

Section 2

Section 3

Section 4

Section 5

Section 6

Section 7

Section 8

Section 9

Section 10

Section 11

Section 12

Device Overview

Signal Descriptions

Bus Operation

System Integration Module

CPU32

DMA Controller Module

Serial Module

Timer Modules

IEEE 1149.1 Test Access Port

Applications

Electrical Characteristics

Ordering Information and Mechanical Data

TABLE OF CONTENTS

Paragraph

Number Title

Page

Number

1.1

1.2

1.2.1

1.2.1.1

1.2.1.2

1.2.1.3

1.2.1.4

1.2.2

1.2.3

1.2.4

Section 1

Device Overview

Central Processor Unit............................................................. 1-2

Intelligent Peripherals.............................................................. 1-3

System Integration Module................................................ 1-3

External Bus Interface................................................. 1-3

Chip Selects .......................................... ............ ......... 1-3

System Protection Submodule..................................... 1-3

System Clock............................................................. 1-4

Direct Memory Access Module........................................... 1-4

Serial Module....... ...... ........................... .............. ...... ....... 1-4

Timer Modules................................................................. 1-5

2.7

2.7.1

2.7.2

2.7.3

2.7.4

2.7.5

2.7.6

2.8

2.8.1

2.8.2

2.1

2.2

2.2.1

2.2.2

2.3

2.4

2.5

2.6

Section 2

Signal Descriptions

Signal Index ........................................................................... 2-2

Address Bus........................................................................... 2-4

Address Bus (A23-AO)....................................................... 2-4

Address Bus (A31-A24) ..................................................... 2-4

Data Bus (015-00). .................. ...... ........... ... .................... ....... 2-4

Function Codes (FC3-FCO) ....................................................... 2-5

Chip Selects (CS3-CSO). .... ....... ...... .............. ....... ....... ...... ....... 2-5

Interrupt Request Level (IRQ7, IRQ6, IRQ5, IRQ3).. ................ ...... 2-6

Bus Control Signals................................................................ 2-6

Data and Size Acknowledge (DSACK1, DSACKO).................. 2-6

Autovector (AVEC) ............................................................ 2-6

Address Strobe (AS) .......................... .......... ....... ..... ......... 2-7

Data Strobe (OS)............................................................... 2-7

Transfer Size (SIZ1, SIZO)............................................ ....... 2-7

Read/Write (R/W) ... ............................. ... .............. ...... ....... 2-7

Bus Arbitration Signals................... ......... ...... ........... ............... 2-7

Bus Request (BR).............................................................. 2-8

Bus Grant (BG) ................................................................. 2-8

MOTOROLA

MC68340 USER'S MANUAL

iii

TABLE OF CONTENTS (Continued)

Paragraph

Number

Title

Page

Number

2.12.3

2.12.4

2.13

2.13.1

2.13.2

2.13.3

2.13.4

2.13.5

2.13.6

2.13.7

2.13.8

2.14

2.14.1

2.14.2

2.14.3

2.15

-2.15.1

2.10.4

2.11

2.11.1

2.11.2

2.11.3

2.11.4

2.12

2.12.1

2.12.2

2.8.3

2.8.4

2.9

2.9.1

2.9.2

2.9.3

2.10

2.10.1

2.10.2

2.10.3

2.15.2

2.15.3

Bus Grant Acknowledge (BGACK)............. .......................... 2-8

Read-Modify-Write Cycle (RMC) ......................................... 2-8

Exception Control Signals........................................................ 2-8

Reset (RESET) .................................................................. 2-8

Halt (HALT) ...................................................................... 2-9

Bus Error (BERR) .............................................................. 2-9

Clock Signals.......................................................................... 2-9

System Clock (CLKOUT) .................................................... 2-9

Crystal Oscillator (EXTAL, XTAL).... .......... .......................... 2-9

External Filter Capacitor (XFC)............................................ 2-9

Clock Mode Select (MODCK).............................................. 2-10

Instrumentation and Emulation Signals..................................... 2-10

Instruction Fetch (lFETCH) .................................................. 2-10

Instruction Pipe (lPIPE) ...................................................... 2-10

Breakpoint (BKPT) ............................................................. 2-10

Freeze (FREEZE)................................................................ 2-10

Test Signals ........................................................................... 2-11

Test Clock (TCK) ............................................................... 2-11

Test Mode Select (TMS) .................................................... 2-11

Test Data In (TDI) .............................................................. 2-11

Test Data Out (TDO) .......................................................... 2-11

Serial Module Signals .................................... ......................... 2-11

Serial Crystal Oscillator (X2,X1 ) .......................................... 2-11

Serial External Clock Input (SCLK) ...................................... 2-12

Receive Data (RxDA, RxDB)................................................ 2-12

Transmit Data (TxDA, TxDB) .............................................. 2-12

Clear to Send (CTSA, CTSB)........ ............... ............. ............ 2-12

Request to Send

(RfSA,

RfSB) ..........................................

2-12

Transmitter Ready (TxRDYA).... ................................ .......... 2-12

Receiver Ready (RxRDYA) .................................................. 2-13

DMA Module Signals ............................................................... 2-13

DMA Request (DREQ2, DREQ1) .......................................... 2-13

DMA Acknowledge (DACK2, DACK1) ................................... 2-13

DMA Done (DONE2, DONE1 ) .............................................. 2-14

Timer Signals ......................................................................... 2-14

Timer Gate (TGATE2, TGATE1 ) ........................................... 2-14

Timer Input (TIN2, TIN1) .................................................... 2-14

Timer Output (TOUT2, TOUT1 ) ........................................... 2-14 iv

MC68340 USER'S MANUAL MOTOROLA


Paragraph

Number

2.16

2.17

2.18

Title

Page

Number

Synthesizer Power (VCCSYN) ................................................... 2-14

System Power and Gound (VCC and GNO) ................................ 2-14

Signal Summary ..................................................................... 2-15

3.1

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

3.1.7

3.1.7.1

3.1.7.2

3.1.7.3

3.2

3.2.1

3.2.2

3.2.3

3.2.3.1

3.2.3.2

3.2.3.3

3.2.3.4

3.2.3.5

3.2.3.6

3.2.3.7

3.2.4

3.2.5

3.2.6

3.3

3.3.1

3.3.2

3.3.3

Section 3

Bus Operation

Bus Transfer Signals .............................................................. .

Bus Control Signals ......................................................... .

Function Codes ................................................................ .

Address Bus (A31-AO) ...................................................... .

3-1

3-2

3-3

3-3

Address Strobe (AS) ........................................................ . . 3-4

Data Bus (015-00) .................... , ....................................... .

Data Strobe (OS) .............................................................. .

3-4

3-4

3-5 Bus Cycle Termination Signals .......................................... .

Data Transfer and Size Acknowledge Signals (DSACK1 and DSACKO) ......................................................... .

Bus Error (BERR) ...................................................... ..

Autovector (AVEC) ..................................................... .

3-5

3-5

3-5

Data Transfer Mechanism ....................................................... .

Dynamic Bus Sizing ......................................................... .

Misaligned Operands ...................................................... ..

3-6

3-6

3-8

Operand Transfer Cases .................................................. ..

Byte Operand to 8-Bit Port, Even (AO

=

0) ...................... .

Byte Operand to 16-Bit Port, Even (AO

=

0) ................... ..

Byte Operand to 16-Bit Port, Odd (AO

=

1) .................... ..

Word Operand to 8-Bit Port, Aligned ........................... ..

3-9

3-9

3-9

3-10.

3-10

Word Operand to 16-Bit Port, Aligned ......................... ..

Long-Word Operand to 8-Bit Port, Aligned .................. ..

Long-Word Operand to 16-Bit Port, Aligned .................. .

Bus Operation ................................................................. .

Synchronous Operation with OSACKx ................................ .

Fast-Termination Cycles .................................................. ..

Data Transfer Cycles ............................................................. ..

Read Cycle ...................................................................... .

Write Cycle ..................................................................... .

Read-Modify-Write Cycle .................................................. .

3-11

3-11

3-14

3-14

3-16

3-16

3-17

3-18

3-19

3-21

MOTOROLA MC68340 USER'S MANUAL v


Paragraph

Number Title

Page

Number

3.5.2

3.5.3

3.5.4

3.6

3.6.1

3.6.2

3.6.3

3.6.4

3.6.5

3.7

3.4

3.4.1

3.4.2

3.4.3

3.4.4

3.4.4.1

3.4.4.2

3.4.4.3

3.5

3.5.1

CPU Space Cycles................................................................... 3-24

Breakpoint Acknowledge Cycle........................................... 3-24

LPSTOP Broadcast Cycle..... .............................................. 3-25

Module Base Address Register Access ................................ 3-29

Interrupt Acknowledge Bus Cycles............. ................ .... ..... 3-29

Interrupt Acknowledge Cycle Terminated Normally.... 3-29

Autovector Interrupt Acknowledge Cycle ............. ... ....... 3-30

Spurious Interrupt Cycle.............................................. 3-31

Bus Exception Control Cycles................................................... 3-34

Bus Errors........................................................................ 3-36

Retry Operation................................................................ 3-37

Halt Operation.................................................................. 3-38

Double Bus Fault ............... ............................................... 3-40

Bus Arbitration....................................................................... 3-42

Bus Request..................................................................... 3-43

Bus Grant........................................................................ 3-44

Bus Grant Acknowledge...... ............. ................................. 3-44

Bus Arbitration ControL..................................................... 3-45

Show Cycles ..................................................................... 3-45

Reset Operation...................................................................... 3-47

4.1

4.2

4.2.1

4.2.2

4.2.2.1

4.2.2.2

4.2.2.3

4.2.2.4

4.2.2.5

4.2.2.6

4.2.2.6.1

4.2.2.6.2

4.2.3

4.2.3.1

4.2.3.2

Section 4


Module Overview................................................................... 4-2

Module Operation ................................................................... 4-2

Module Base Address Register................................. .......... 4-2

System Configuration and Protection Submodule ................ 4-3

System Configuration.................................................. 4-4

Internal Bus Monitor................................................... 4-6

Double Bus Fault Monitor ................... ............... .......... 4-6

Spurious Interrupt Monitor.......................................... 4-6

Software Watchdog.................................................... 4-6

Periodic Interrupt Timer............................................... 4-7

Periodic Timer Period Calculation........................... 4-8

Using the Periodic Timer as a Real-Time Block ........ 4-9

Clock Synthesizer.............................................................. 4-9

Phase Comparator and Filter ........................................ 4-10

Frequency Divider ....................................................... 4-10 vi

MC68340 USER'S MANUAL

MOTOROLA


Paragraph

Number

4.3.2.7

4.3.2.8

4.3.3

4.3.4.

4.3.4.1

4.3.4.2

4.3.5

4.3.5.1

4.3.5.2

4.3.5.3

4.3.5.4

4.3.5.5

4.3.5.6

4.3.5.7

4.2.3.3

4.2.4

4.2.4.1

4.2.4.2

4.2.5

4.2.5.1

4.2.5.2

4.2.6

4.2.7

4.3

4.3.1

4.3.2

4.3.2.1

4.3.2.2

4.3.2.3

4.3.2.4

4.3.2.5

4.3.2.6

Title

Page

Number

Clock ControL............................................................. 4-12

Chip-Select Submodule ..................................................... 4-13

Programmable Features .............................................. 4-13

Global Chip-Select Operation ...... ............ ........... .......... 4-14

External Bus Interface ....................................................... 4-14

Port A ........................................................................ 4-14

Port B ........................................................................ 4-14

Low-Power Stop............................................................... 4-16

Freeze... ..... .......... ..... ..... ........ ..... ..... ...... ..... ....... ........... ... 4-17

Programmer's Model .............................................................. 4-17

Module Base Address Register ........................................... 4-19

System Configuration and Protection Registers .................... 4-19

Module Configuration Register (MCR).... ............... ........ 4-20

Autovector Register (AVR) ........................................... 4-21

Reset Status Register (RSR) .... .................... ............ ..... 4-22

Software Interrupt Vector Register (SWIV).... ................. 4-23

System Protection Control Register (SYPCR).................. 4-23

Periodic Interrupt Control Register (PICR) ...... ..... ........... 4-26

Periodic Interrupt Timer Register (PITR) ...... .................. 4-27

Software Service Register (SWSR) ................................ 4-27

Clock Synthesizer Control Register (SYNCR) ............ ............ 4-28

Chip-Select Registers........................................................ 4-30

Base Address Registers............................................... 4-30

Address Mask Registers.............................................. 4-32

External Bus Interface Control 4-33

Port A Pin Assignment Register 1 (PPARA 1) .. ................ 4-34

Port A Pin Assignment Register 2 (PPARA2) .................. 4-34

Port A Data Direction Register (DDRA) .................. ........ 4-35

Port A Data Register (PORTA) ...................................... 4-35

Port B Pin Assignment Register (PPARB)...... ................. 4-35

Port B Data Direction Register (DDRB).......... ................. 4-36

Port B Data Register (PORTB, PORTB1) ......................... 4-36

5.1

5.1.1

Section 5

CPU32

Overview............................................................................... 5-1

Features........................................................................... 5-2

MOTOROLA

MC68340 USER'S MANUAL vii


Paragraph

Number Title

Page

Number

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.1.7.1

5.1.7.2

5.1.8

5.1.9

5.2

5.2.1

5.2.2

5.2.3

5.2.3.1

5.2.3.1.1

5.2.3.1.2

5.2.3.1.3

5.2.3.2

5.3

5.3.1

5.3.2

5.3.3

5.3.4

5.3.4.1

5.3.4.1.1

5.3.4.1.2

5.3.4.2

5.3.4.2.1

5.3.4.2.2

5.3.4.2.3

5.3.4.2.4

5.3.4.2.5

5.3.4.2.6

5.3.4.3

5.3.4.3.1

Virtual Memory ............................................................... .

Loop Mode Instruction Execution ...................................... .

Vector Base Register ........................................................ .

Exception Handling ......................................................... ..

5-3

5-3

5-4

5-5

Addressing Modes ........................................................... .

Instruction Set ................................................................. .

Table Lookup and Interpolate Instructions .................... .

Low-Power Stop Instruction ........................................ .

Processing States ............................................................ .

Privilege States ................................................................ .

5-5

5-6

5-6

5-6

5-8

Architecture Summary ........................................................... .

Programming Model ........................................................ .

Registers ........................................................................ ..

Data Types ...................................................................... .

Organization in Registers ............................................ .

Data Registers ..................................................... .

5-8

q-8

5-9

5-11

5-12

5-12

5-12

Address Register ................................................. . 5-13

Control Registers ................................................. .

Organization in Memory ............................................. .

5-14

5-14

Data Organization and Addressing Capabilities ........................ ..

Program and Data References ........................................... .

Notation Conventions ....................................................... .

Implicit Reference ............................................................ .

5-16

5-16

5-17

5-18

Effective Address ............................................................. .

Register Direct Mode .................................................. .

Data Register Direct ............................................ ..

Address Register Direct ........................................ .

Memory Addressing Modes ........................................ .

Address Register Indirect ...

~

.................................. .

Address Register Indirect with Postincrement ........ ..

Address Register Indirect with Predecrement .......... .

Address Register Indirect with Displacement .......... .

Address Register Indirect with Index (8-Bit

Displacement) .................................................. .

Address Register Indirect with Index (Base

Displacement) .................................................. .

Special Addressing Modes ......................................... ..

Program Counter Indirect with Displacement .......... .

5-21

5-22

5-23

5-23

5-19

5-19

5-19

5-19

5-19

5-20

5-20

5-20

5-21 viii


MOTOROLA


Paragraph

Number Title

Page

Number

5.3.4.3.4

5.3.4.3.5

5.3.4.3.6

5.3.4.4

5.3.5

5.3.5.1

5.3.5.2

5.3.6

5.3.7

5.4.3

5.4.3.1

5.4.3.2

5.4.3.3

5.4.3.4

5.4.3.5

5.4.3.6

5.4.3.7

5.4.3.8

5.4.3.9

5.3.7.1

5.3.7.2

5.3.7.3

5.4

5.4.1

5.4.1.1

5.4.1.1.1

5.4.1.1.2

5.4.1.2

5.4.2

5.4.3.10

5.4.4

5.4.4.1

5.4.4.2

5.4.4.3

5.3.4.3.2

5.3.4.3.3

Program Counter Indirect with Index (8-Bit

Displacement) .................................................. . 5-23

Program Counter Indirect with Index (Base

Displacement) ................................................... 5-24

Absolute Short Address................ .............. ........... 5-24

Absolute long Address ...... ..................... ........ ...... 5-25

Immediate Data.................................... ................ 5-25

Effective Address Encoding Summary.. .............. ........... 5-25

Programming View of Addressing Modes........ ........ ........... 5-27

Addressing Capabilities...... ....... ............ ................ ...... 5-27

General Addressing Mode Summary............. .......... ..... 5-30

M68000 Family Addressing Capability ................................. 5-30

Other Data Structures........................................................ 5-32

System Stack............................................................. 5-32

User Stacks................................................................ 5-33

Queues ...................................................................... 5-34

Instruction Set.......... ...................... ............................. ...... ..... 5-35

M68000 Family Compatibility.......... .......... ...... ........ ........... 5-36

New Instructions......................................................... 5-36 low-Power Stop (lPSTOP) ..................................... 5-36

Table lookup and Interpolate (TBl) ........ ................ 5-36

Unimplemented Instructions...... ............ ...................... 5-36

Instruction Format and Notation ......................................... 5-37

Instruction Summary..................................... ..... .... ........... 5-39

Condition Code Register ............ ....................... ........... 5-43

Data Movement Instructions ......................................... 5-45

Integer Arithmetic Operations...................................... 5-46 logical Instructions.................................... ................. 5-47

Shift and Rotate Instructions ........................................ 5-48

Bit Manipulation Instructions ...... ...................... ...... ..... 5-49

Binary-Coded Decimal (BCD) Instructions...... ..... ........... 5-50

Program Control Instructions .......... .......... ........ ...... ..... 5-50

System Control Instructions ......................................... 5-51

Condition Tests ..... ........ ....... ....................... ... ..... ....... 5-53

Using the Table lookup and Interpolate Instruction.............. 5-53

Table Example 1: Standard Usage................... ............. 5-54

Table Example 2: Compressed Table ............................ 5-55

Table Example 3: 8-Bit Independent Variable...... ...... ..... 5-57

MOTOROLA


ix

x


Paragraph

Number Title

Page

Number

5.4.4.4

5.4.4.5

5.4.5

5.4.6

5.5

5.5.1

5.5.2

5.5.2.1

5.5.2.2

5.5.2.3

5.6

5.6.1

5.6.1.1

5.6.1.2

5.6.1.3

5.6.1.4

5.6.2

5.6.2.1

5.6.2.2

5.6.2.3

5.6.2.4

5.6.2.5

5.6.2.6

5.6.2.7

5.6.2.8

5.6.2.9

5.6.2.10

5.6.2.11

5.6.2.12

5.6.3

5.6.3.1

5.6.3.1.1

5.6.3.1.2

5.6.3.1.3

Table Example 4: Maintaining Precision ...................... ..

Table Example 5: Surface Interpolations ...................... .

Nested Subroutine Calls ................................................... .

Pipeline Synchronization with the NOP Instruction .............. .

Processing States ................................................................. ..

State Transitions .............................................................. .

Privilege Levels ............................................................... .

Supervisor Privilege Level .......................................... .

User Privilege Level ................................................... .

Changing Privilege Level ............................................ .

Exception Processing ............................................................. .

Exception Vectors ............................................................ .

Types of Exceptions ................................................... .

Exception Processing Sequence .................................. .

Exception Stack Frame ............................................... .

Multiple Exceptions .................................................... .

Processing of Specific Exceptions ...................................... .

Reset ........................................................................ .

Bus Error .................................................................. .

Address Error ............................................................ .

Instruction Traps ........................................................ .

Software Breakpoints ................................................. .

Hardware Breakpoints ................................................ .

Format Error ............................................................. .

Illegal or Unimplemented Instructions .......................... .

Privilege Violations .................................................... .

Tracing ..................................................................... .

Interrupts .................................................................. .

Return from Exception ............................................... .

Fault Recovery ................................................................. .

Types of Faults .......................................................... .

Type I: Released Write Faults ................................ .

Type II: Prefetch, Operand, RMW, and MOVEP

Faults .............................................................. .

Type III: Faults during MOVEM Operand Transfer .. ..

5-64

5-64

5-66

5-67

5-67

5-68

5-69

5-69

5-70

5-72

5-72

5-73

5-73

5-59

5-61

5-61

5-61

5-62

5-62

5-62

5-63

5-63

5-63

5-74

5-74

5-76

5-76

5-78

5-79

5-80

5-83

5-83

5-84

5-85


MOTOROLA


Paragraph

Number Title

Page

Number

5.6.3

5.6.3.1

5.6.3.1.1

5.6.3.1.2

5.6.3.1.3

5.6.3.1.4

5.6.3.2

5.6.3.2.1

5.6.3.2.2

5.6.3.2.3

5.6.3.2.4

5.6.3.2.5

5.6.3.2.6

5.6.3.2.7

5.6.4

5.6.4.1

5.6.4.2

5.7

5.7.1

5.7.1.1

5.7.1.2

5.7.1.3

5.7.2

5.7.2.1

5.7.2.2

5.7.2.2.1

5.7.2.2.2

5.7.2.2.3

5.7.2.2.4

5.7.2.3

5.7.2.4

5.7.2.5

5.7.2.5.1

5.7.2.5.2

5.7.2.5.3

5.7.2.6

Fault Recovery ................................................................. .

Types of Faults .......................................................... .

Type I: Released Write Faults ................................ .

Type II: Prefetch, Operand, RMW, and MOVEP

Faults .............................................................. .

Type III: Faults during MOVEM Operand Transfer .. ..

Type IV: Faults during Exception Processing .......... .

Correcting a Fault ...................................................... .

(Type I) Completing Released Writes via Software .. .

(Type I) Completing Released Writes via RTE .......... .

(Type II) Correcting Faults via RTE ........................ ..

(Type III) Correcting Faults via Software ................ ..

(Type III) Correcting Faults by Conversion and

Restart ............................................................. .

(Type III) Correcting Faults via RTE ........................ .

(Type IV) Correcting Faults via Software ................ ..

CPU32 Stack Frames ........................................................ .

Normal Four-Word Stack Frame ................................. ..

BERR Stack Frame ..................................................... .

Development Support ........................................... ,' ................ .

CPU32 Integrated Development Support ............................ .

Background Debug Mode (BDM) Overview .................. ..

Deterministic Opcode Tracking Overview .................... ..

On-Chip Hardware Breakpoint Overview ...................... .

Background Debug Mode (BDM) ...................................... ..

Enabling BDM ........................................................... .

BDM Sources ............................................................ .

External BKPT Signal ........................................... .

BGND Instruction ................................................. .

Double Bus Fault ................................................ ..

Peripheral Breakpoints ......................................... .

Entering BDM ............................................................ .

Command Execution .................................................. .

Background Mode Registers ...................................... ..

Fault Address Register (FAR) ................................ ..

Return Program Counter (RP) ................................ .

Current Instruction Program Counter (PCC) ............ .

Returning from BDM .................................................. .

5-80

5-83

5-83

5-84

5-85

5-85

5-86

5-86

5-87

5-87

5-88

5-88

5-89

5-89

5-90

5-90

5-91

5-93

5-94

5-94

5-95

5-95

5-95

5-96

5-97

5-97

5-97

5-97

5-98

5-98

5-99

5-99

5-100

5-100

5-100

5-100

MOTOROLA MC68340 USER'S MANUAL xi


Paragraph

Number Title

Page

Number

5.7.2.7

5.7.2.7.1

5.7.2.7.2

5.7.2.8

5.7.2.8.1

5.7.2.8.2

5.7.2.8.3

5.7.2.8.4

5.7.2.8.5

5.7.2.8.6

Serial Interface ......................................................... ..

CPU32 Serial Logic .............................................. .

Development System Serial Logic ........................ ..

Command Set ........................................................... .

Command Format ................................................ .

Command Sequence Diagrams ............................ ..

Command Set Summary ...................................... .

Read AID Register (RAREG/RDREG) ...................... ..

Write AID Register (WAREGIWDREG) .................... ..

Read System Register (RSREG) ............................ ..

5.7.2.8.7

5.7.2.8.8

5.7.2.8.9

5.7.2.8.10

Write System Register (WSREG) ............................ .

Read Memory Location (READ) ............................ ..

Write Memory Location (WRITE) .......................... ..

Dump Memory Block (DUMP) .............................. ..

5.7.2.8.11

5.7.2.8.12

5.7.2.8.13

5.7.2.8.14

5.7.2.8.15

5.7.2.8.16

5.7.3

5.7.3.1

5.7.3.2

5.7.3.3

5.8

5.8.1

5.8.1.1

5.8.1.2

5.8.1.3

Fill Memory Block (FILL) ...................................... ..

Resume Execution (GO) ........................................ .

Call User Code (CALL) .......................................... .

Reset Peripherals (RST) ........................................ .

No Operation (NOP) ............................................ ..

Future Commands .............................................. ..

Deterministic Opcode Tracking .......................................... .

Instruction Fetch (IFETCH) ........................................... .

Instruction PIPE (IPIPE) .............................................. ..

Opcode Tracking during Loop Mode ............................ .

Instruction Execution Timing ................................................... .

Resource Scheduling ........................................................ .

Microsequencer ......................................................... .

Instruction Pipeline .................................................... .

Bus Controller Resources ............................................ .

Prefetch Controller ............................................... . 5.8.1.3.1

5.8.1.3.2

5.8.1.3.3

5.8.1.4

5.8.1.5

5.8.1.6

Write-Pending Buffer ............................................ .

Microbus Controller ............................................. .

Instruction Execution Overlap ..................................... .

Effects of Wait States ................................................ ..

Instruction Execution Time Calculation ........................ ..

Effects of Negative Tails ............................................. . 5.8.1.7

5.8.2

5.8.2.1

Instruction Stream Timing Example .................................. ..

Timing Example 1: Execution Overlap ........................ ..

5-112

5-113

5-114

5-115

5-117

5-118

5-119

5-120

5-121

5-100

5-101

5-104

5-105

5-105

5-106

5-109

5-110

5-110

5-111

5-126

5-126

5-126

5-127

5-128

5-129

5-130

5-131

5-131

5-121

5-121

5-121

5-122

5-123

5-124

5-124

5-124

5-124

5-125 xii


Paragraph

Number

5.8.2.2

5.8.2.3

5.8.3

5.8.3.1

5.8.3.2

5.8.3.3

5.8.3.4

5.8.3.5

5.8.3.6

5.8.3.7

5.8.3.8

5.8.3.9

5.8.3.10

5.8.3.11

5.8.3.12

5.8.3.13

5.8.3.14


Title

Page

Number

Timing Example 2: Branch Instructions ... ; .................... .

Timing Example 3: Negative Tails .............................. ..

Instruction Timing Tables ................................................ ..

Fetch Effective Address .............................................. .

Calculate Effective Address ......................................... .

MOVE Instruction ....................................................... .

Special-Purpose MOVE Instruction .............................. ..

Arithmetic/Logical Instructions .................................... .

Immediate Arithmetic/Logical Instructions .................... .

Binary-Coded Decimal and Extended Instructions .......... .

Single Operand Instructions ........................................ .

Shift/Rotate Instructions ............................................. .

Bit Manipulation Instructions ...................................... .

Conditional Branch Instructions ................................... .

Control Instructions .................................................... .

Exception-Related Instructions and Operations ............ ..

Save and Restore Operations ...................................... .

5-132

5-133

5-134

5-136

5-138

5-139

5-139

5-141

5-143

5-144

5-144

5-145

5-146

5-147

5-148

5-149

5-150

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.2

6.2.1

6.2.2

6.2.2.1

6.2.2.2

6.2.2.3

6.2.2.4

6.2.3

6.2.3.1

6.2.3.1.1

6.2.3.1.2

Section 6


DMA Module Signals ............................................................... 6-2

DMA Request (DREQ2, DREQ1) .......................................... 6-2

DMA Acknowledge (DSACK2, DACK1)................................. 6-2

DMA Done (DONE2, DONE1 ).............................................. 6-2

Reset (RESET) .................................................................. 6-2

Operation............................................................................... 6-2

Channel Initialization .......................... '............................... 6-3

Channel Startup................................................................ 6-4

External Request......................................................... 6-4

External Request with Other Modules........................... 6-4

External Burst............................................................. 6-5

External Cycle Steal.................................................... 6-5

DMA Transfer Operation............ ........................................ 6-6

Dual-Address Mode.................................................... 6-6

Dual-Address Source Read ............ ........................ 6-6

Dual-Address Destination Write.............................. 6-6

MOTOROLA

MC68340 USER'S MANUAL xiii

7.1

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.2

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6


Paragraph

Number

Title

Page

Number

6.2.3.2

6.2.3.2.1

6.2.3.2.2

6.2.4

6.2.5

6.2.6

6.4.1

6.4.2

6.4.3

6.4.4

6.4.5

6.4.6

6.4.7

6.3

6.3.1

6.3.2

6.3.2.1

6.3.2.2

6.3.2.3

6.4

6.4.8

6.4.9

Single-Address Mode ................................................. .

Single-Address Source Read ................................ ..

Single-Address Destination Write .......................... .

Interrupt Operation .......................................................... .

Bus Arbitration ................................................................ .

Fast-Termination Option ................................................... .

Programming Sequence ........................................................ ..

Channel Startup ............................................................... .

Data Transfer .................................................................. .

Dual-Address Transfers .............................................. .

Single-Address Transfers ............................................ .

Channel Termination .................................................. .

Register Description ............................................................... .

Module Configuration Registers (MCRs) ............................ ..

Interrupt Registers (INTRs) ................................................ .

Channel Control Registers (CCRs) ..................................... ..

Channel Status Registers (CSRs) ...................................... ..

Function Code Registers (FCRs) ........................................ ..

Source Address Registers (SARs) ...................................... .

Destination Address Registers (DARs) ................................ .

Byte Transfer Counter Registers (BTCs) .............................. .

Data Holding Register (DHR) ............................................ ..

6-7

6-7

6-7

6-7

6-8

6-8

6-9

6-9

6-9

6-9

6-10

6-10

6-10

6-11

6-13

6-14

6-17

6-18

6-19

6-20

6-21

6-22

Section 7

Serial Module

Module Overview. ...... ..... ....................... .... ..... ......... .............. 7-2

Serial Communication Channels A and B ............................ 7-3

Baud Rate Generator Logic ................................................ 7-3

Internal Channel Control Logic .................... ....................... 7-3

Interrupt Control Logic ...................................................... 7-4

Comparison of Serial Module to MC68681........................... 7-4

Interface Signal Descriptions.............................................. 7-4

Crystal Input or External Clock (X1) .................................... 7-6

Crystal Output (X2) ........................................................... 7-6

External Input (SCLK) ........................................................ 7-6

Channel A Transmitter Serial Data Output (TxDA) ................ 7-6

Channel A Receiver Serial Data Input (RxDA) ....................... 7-6

Channel B Transmitter Serial Data Output (TxDB) ................ 7-7 xiv


MOTOROLA


Paragraph

Number Title

Page

Number

7.2.13

7.2.13.1

7.2.13.2

7.2.13.3

7.3

7.3.1

7.3.2

7.3.2.1

7.3.2.2

7.3.2.3

7.3.3

7.3.3.1

7.3.3.2

7.3.3.3

7.3.4

7.3.5

7.3.5.1

7.2.7

7.2.8

7.2.8.1

7.2.8.2

7.2.9

7.2.9.1

7.2.9.2

7.2.10

7.2.11

7.2.12

7.2.12.1

7.2.12.2

7.3.5.2

7.3.5.3

7.4

7.4.1

7.4.1.1

7.4.1.2

7.4.1.3

7.4.1.4

7.4.1.5

Channel B Receiver Serial Data Input (RxDB) ...................... . 7-7

Channel A Request To Send (RTSA) .................................. .

RTSA ........................................................................ .

OPO .......................................................................... .

Channel B Request To Send (RTSB) ................................... .

RTSB ........................................................................ .

OP1 .......................................................................... .

Channel A Clear To Send (CTSA) ....................................... .

Channel B Clear To Send (CTSB) ...................................... ..

Channel A Transmitter Ready (TxRDYA) ............................. .

TxRDYA .................................................................... .

OP6 .......................................................................... .

Channel A Receiver Ready (RxRDYA) ................................ ..

RxRDYA .................................................................... .

FFULLA ..................................................................... .

OP4 .......................................................................... .

Operation .............................................................................. .

Baud Rate Generator ........................................................ .

Transmitter and Receiver Operating Modes ........................ .

Transmitter ............................................................... .

Receiver .................................................................... .

FIFO Stack ................................................................. .

Loop Modes .................................................................... .

Automatic Echo Mode ................................................ .

Local Loopback Mode ............................................... ..

Remote Loopback Mode ............................................. .

Multidrop Mode ............................................................... .

Bus Operation ................................................................. .

Read Cycles ............................................................. ..

Write Cycles .............................................................. .

Interrupt Acknowledge Cycles .................................... ..

Register Description and Programming .................................... .

Register Description ........................................................ ..

Module Configuration Register (MCR) ......................... ..

Interrupt Level Register

(I

LR) ...................................... ..

I nterru pt Vector Reg ister (lVR). ................................... ..

Mode Register 1 (MR1) .............................................. ..

Status Register (SR) .................................................. ..

7-13

7-13

7-16

7-16

7-16

7-17

7-18

7-19

7-20

7-20

7-20

7-20

7-20

7-23

7-24

7-25

7-25

7-27

7-8

7-8

7-8

7-8

7-8

7-8

7-8

7-9

7-9

7-9

7-11

7-7

7-7

7-7

7-7

7-7

7-7

7-8

7-8

MOTOROLA

MC68340 USER'S MANUAL xv

Paragraph

Number

7.4.1.6

7.4.1.7

7.4.1.8

7.4.1.9

7.4.1.10

7.4.1.11

7.4.1.12

7.4.1.13

7.4.1.14

7.4.1.15

7.4.1.16

7.4.1.17

7.4.2

7.4.2.1

7.4.2.2

7.4.2.3


Title

Page

Number

Clock-Select Register (CSR).... .......... ............................ 7-29

Command Register (CR) .............................................. 7-31

Receiver Buffer (RB) .................. .................................. 7-34

Transmitter Buffer (TB).................... ...... ..... ............. .... 7-35

Input Port Change Register (lPCR) ................................ 7-35

Auxiliary Control Register (ACR).. .......... .................. ..... 7-36

Interrupt Status Register (ISR)......................................

7~37

Interrupt Enable Register (IER) ..................................... 7-39

Input Port (lP)............................................................. 7-40

Output Port Control Register (OPCR)............................. 7-41

Output Port Data Register (OP) ..................................... 7-42

Mode Register 2 (MR2) ................................................ 7-43

Programming ............................. .......... ...... ..... .... ............. 7-45

Serial Module Initialization................ ........................... 7-46

I/O Driver Example...................................................... 7-46

Interrupt Handling............. .............. ...... .................. .... 7-46

8.1.3

8.2

8.2.1

8.2.2

8.2.3

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.1

8.1.1

8.1.1.1

8.1.1.2

8.1.1.3

8.1.1.4

8;1.2

Section 8

Timer Modules

Module Overview ................................................................... 8-1

Timer and Counter Functions............................................. 8-2

Prescaler and Counter................................................. 8-2

Timeout Detection...................................... ................ 8-2

Comparator................................................................ 8-3

Clock Selection Logic.................................................. 8-3

Internal Control Logic........................................................ 8-4

Interrupt Control Logic...................................................... 8-4

Signal ,Definitions................................................................... 8-4

Timer Input (TIN) .......................... ............ ................ ........ 8-4

Timer Gate (TGATE)................ ............ ..... .... .............. ....... 8-6

Timer Output (TOUT) ........................................................ 8-6

Operating Modes............... ...................................................... 8-6

Input Capture/Output Compare........................................... 8-6

Square-Wave Generator .........................

~

.......................... 8--8

Variable Duty-Cycle Square-Wave Generator ....................... 8-10

Variable-Width Single-Shot Pulse Generator ........................ 8-11

Pulse-Width Measurement ................................................. 8-13 xvi MC68340 USER'S MANUAL MOTOROLA


Paragraph

Number Title

Page

Number

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

8.3.6

8.3.7

8.3.8

8.3.9

8.3.9.1

8.3.9.2

8.3.9.3

8.4

8.4.1

Period Measu rement......................................................... 8-14

Event Count ..................................................................... 8-16

Timer Bypass ................................................................... 8-17

Bus Operation.................................................................. 8-18

Read Cycles............................................................... 8-18

Write Cyles ................................................................ 8-18

Interrupt Acknowledge Cycles ...................................

~

.. 8-19

Register Description ................................................................ 8-19

Module Configuration Register (MCR)................................. 8-20

Interrupt Register (lR)........................................................ 8-21

Control Register (CR)......................................................... 8-21

Status Register................................................................. 8-25

Counter Register (CNTR).................................................... 8-27

Preload 1 Register (PREL 1 ).............. ................................... 8-28

Preload 2 Register (PREL2)...... ........................................... 8-29

Compare Register (COM) ................................ : .................. 8-29

9.1

9.2

9.2.1

9.2.2

9.2.3

9.2.4

9.3

9.4

Section 9


Overview ............................................................................... 9-1

Instruction Register................................................................. 9-2

Extest (000) .... ................................ .................................. 9-3

Bypass (X1X, 101) ............................................................. 9-10

Sample/Preload (001) .............................................. .......... 9-11

HI-Z (100) ......................................................................... 9-11

MC68340 Restrictions.............................................................. 9-11

Non-IEEE 1149.1 Operation ...................................................... 9-12

10.1

10.1.1

10.1.2

10.1.3

10.1.4

Section 10

Applications

Minimum System Configuration ............................................... 10-1

Processor Clock Circuitry ................................................... 10-2

Reset Circuitry .................................................................. 10-3

SRAM Interface ................................................................ 10-3

ROM Interface .................................................................. 10-4

MOTOROLA

MC68340 USER'S MANUAL xvii

TABLE OF CONTENTS (Concluded)

Paragraph

Number Title

Page

Number

10.1.5

10.2

10.2.1

10.2.2

10.2.3

10.2.3.1

10.2.3.2

10.2.3.3

10.2.4

10.2.5

10.3

10.3.1

10.3.2

10.3.3

10.3.4

Serial Interface ................................................................. 10-4

MC68340 Initialization Sequence .............................................. 10-5

Startup ............................................................................ 10-5

SIM Module Configuration ................................................. 10-6

DMA Module Configuration ............................................... 10-7

DMA Module Initialization ............................................ 10-7

DMA Module Operation (Single-Address Mode) ............. 10-8

DMA Module Operation (Dual-Address Mode) ............... 10-9

Serial Module Configuration .............................................. 10-10

Timer Module Configuration .............................................. 10-11

Memory Interface Information .................................................. 10-12

Using a 8-Bit Boot ROM .................................................... 10-12

Access Time Calculations .................................................. 10-13

Calculating Frequency-Adjusted Output.. ............................. 10-15

Interfacing an 8-Bit Device to 16-Bit Memory Using

Single-Address DMA Mode ............................................. 10-18

11.1

11.2

Section 11


Maximum Ratings ................................................................... 11-1

Thermal Characteristics ........................................................... 11-1

12.1

12.2

12.3

12.4

12.5

Section 12


Standard MC68340 Ordering Information .................................. 12-1

Pin Assignment Ceramic Surface Mount (FE Suffix) ................ 12-2

Pin Assignment Plastic Pin Grid Array (RP Suffix) .................. 12-4

Package Dimensions FE Suffix ................................................. 12-6

Package Dimensions RP Suffix ................................................. 12-7

Index xviii


MOTOROLA

LIST OF ILLUSTRATIONS

Figure

Number

1-1

Title

Page

Number

Block Diagram... .................................................................. 1-1

2-1 Functional Signal Groups ..................................................... 2-1

3-1

3-2

Input Sample Window.......................................................... 3-2

MC68340 Interface to Various Port Sizes .......... '...................... 3-7

3-3 Long-Word Operand Read Timing from 8-Bit Port................... 3-12

3-4 Long-Word Write Operand Timing to 8-Bit Port....................... 3-13

3-5 Long-Word and Word Read and Write Timing 16-Bit Port.... 3-15

3-6 Fast-Termination Timing....................................................... 3-17

3-7 Word Read Cycle Flowchart .................................................. 3-18

3-8 Write Cycle Flowchart.................................. ........................ 3-20

3-9 Read-Modify-Write Cycle Timing............................ ............... 3-22

3-10 CPU Space Address Encoding............................ ................... 3-24

3-11 Breakpoint Operation Flowchart ............................................ 3-26

3-12 Breakpoint Acknowledge Cycle Timing (Opcode Returned)....... 3-27

3-13 Breakpoint Acknowledge Cycle Timing (Exception Signaled).... 3-28

3-14 Interrupt Acknowledge Cycle Flowchart.................................. 3-31

3-15 Interrupt Acknowledge Cycle Timing.. ........................ ............ 3-32

3-16 Autovector Operation Timing................................................ 3-33

3-17 Bus Error without DSACKx ............................................ ....... 3-37

3-18 Late Bus Error with DSACKx................................................. 3-38

3-19 Retry Sequence................................................................... 3-39

3-20 Late Retry Sequence............................................................ 3-40

3-21 HALT Timing ....................................................................... 3-41

3-22 Bus Arbitration Flowchart for Single Request.... ...................... 3-43

3-23 Bus Arbitration State Diagram................................ ............... 3-46

3-24 Initial Reset Operation Timing............................................... 3-49

4-1

4-2

SIM Block Diagram .............................................................. 4-1

System Configuration and Protection Submodule ................... 4-5

4-3 Software Watchdog............................................................. 4-7

4-4 Clock Submodule Block Diagram........................................... 4-11

MOTOROLA

MC68340 USER'S MANUAL xix

xx

LIST OF ILLUSTRATIONS (Continued)

Figure

Number

4-5

4-6

Title

Page

Number

Full Interrupt Request Multiplexer ......................................... .

SIM Programming Model .................................................... .

4-15

4-18

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

, 5-18

5-26

5-27

5-28

5-29

5-30

5-31

5-32

5-33

5-34

5-35

5-19

5-20

5-21

5-22

5-23

5-24

5-25

CPU32 Block Diagram ........................................................ ..

Loop Mode Instruction Sequence ........................................ ..

User Programming Model ................................................... .

Supervisor Programming Model Supplement ........................ .

Status Register ................................................................... .

Data Organization in Data Registers ...................................... .

Address Organization in Address Registers .......................... ..

Memory Operand Addressing .............................................. .

Single EA Instruction Operation Word .................................. ..

EA Specification Formats ..................................................... .

SIZE in the Index Selection .................................................. .

Absolute Address with Indexes ............................................ .

Addressing Array Items ....................... ' ................................. .

M68000 Family Address Extension Words ............................ ..

Instruction Word General Format ........................................ ..

Table Example 1 ................................................................. .

Table Example 2 ................................................................ ..

Table Example 3 ................................................................. .

Exception Stack Frame ......................................................... .

Reset Operation Flowchart ................................................... .

Format $0 Four-Word Stack Frame .................................. ..

Format $2 Six-Word Stack Frame .................................... ..

Format $C BERR Stack for Prefetches and Operands .......... .

Format $C BERR Stack on MOVEM Operand ...................... .

Format $C Four- and Six-Word BERR Stack ...................... ..

Traditional In-Circuit Emulator Diagram ................................ .

Bus State Analyzer Configuration ........................................ ..

BDM Block Diagram ............................................................ .

BDM Command Execution Frowchart .................................... .

Debug Serial 1/0 Block Diagram .......................................... ..

Serial Interface Timing Diagram .......................................... ..

BKPT Timing for Single Bus Cycle ........................................ .

. BKPT Timing for Forcing BDM ............................................ ..

BKPT/DSCLK Logic Diagram ................................................ ..

Command Sequence Diagram Example ................................ .

5-3

5-4

5-10

5-10

5-11

5-13

5-14

5-15

5-16

5-26

5-28

5-28

5-29

5-31

5-37

5-55

5-56

5-57

5-68

5-71

5-90

5-91

5-92

5-92

5-93

5-95

5-95

5-96

5-99

5-102

5-103

5-104

5-104

5-105

5-107


LIST OF ILLUSTRATIONS (Continued)

Figure

Number Title

Page

Number

5-36

5-37

5-38

5-39

5-40

5-41

5-42

5-43

5-44

Functional Model of Instruction Pipeline ..............

~

................ ..

Instruction Pipeline Timing Diagram .................................... ..

Block Diagram of Independent Resources .............................. .

Simultaneous Instruction Execution ...................................... .

Attributed Instruction Times ................................................. .

Example 1 Instruction Stream .......................................... .

Example 2 Branch Taken ................................................ ..

Example 2 Branch Not Taken .......................................... ..

Example 3 Branch Negative Tail ...................................... ..

5-122

5-123

5-125

5-127

5-128

5-132

5-132

5-133

5-133

6-1

6-2

6-3

6-4

DMA Block Diagram ............................................................ .

DMA External Connections to Serial Module ........................ ..

Programmer's Model .......................................................... .

Packing and Unpacking of Operands .................................... ..

6-1

6-5

6-n

6-22

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

7-9

Simplified Block Diagram .................................................... .

External and Internal Interface Signals .................................. .

Baud Rate Generator Simplified Functional Diagram .............. .

Transmitter and Receiver Simplified Functional Diagram ........ .

Transmitter Timing Diagram ................................................ .

Receiver Timing Diagram ..................................................... .

Loop Modes Functional Diagram .......................................... .

Multidrop Mode Timing Diagram ......................................... .

Serial Module Programming Flowchart ................................ ..

7-1

7-5

7-9

7-10

7-12

·7-14

7-17

7-19

7-47

8-1

8-2

8-3

8-4

8-5

8-6

8-7

8-8

8-9

8-10

8-11

Simplified Block Diagram .................................................... .

Timer Functional Diagram .................................................. ..

External and Internal Interface Signals .................................. .

Input Capture/Output Compare Mode .................................. ..

Square-Wave Generator Mode ............................................. .

Variable Duty-Cycle Square-Wave Generator Mode ................ .

Variable-Width Single-Shot Pulse Generator Mode ................ ..

Pulse-Width Measurement Mode .......................................... .

Period Measurement Mode ................................................. ..

Event Count Mode ............................................................. ..

Programming Model ........................................................... .

8-1

8-3

8-5

8-7

8-9

8-11

8-12

8-14

8-15

8-16

8-19

MOTOROLA

MC68340 USER'S MANUAL xxi

LIST OF ILLUSTRATIONS (Concluded)

Figure

Number

Title

, Page

Number

9-1

9-2

9-3

9-4

9-5

9-6

9-7

9-8

Test Logic Block Diagram..................................................... 9-2

Output Latch Cell (O.Latch) ................................................... 9-7

Input Pin Cell (I,Pin) ................ :............................................ 9-8

Active-High Output Control Cell (lO.CtI1) ...................... .......... 9-8

Active-Low Output Control Cell (lO.CtIO)................... .............. 9-9

Bidirectional Data Cell (lO.Cell).... .......... ...................... .......... 9-9

General Arrangement for Bidirectional Pins............................ 9-10

Bypass Register................................................................... 9-10

10-1

10-2

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

10-12

10-13

Minimum System Configuration Block Diagram ...................... 10-1

Sample Crystal Circuit .......................................................... 10-2

XFC and VCCSYN Capacitor Connections ............................... 10-2

SRAM Interface ............................... ..... ................... ........ .... 10-3

EPROM Interface.................................................................. 10-4

Serial Interface.................................................................... 10-5

External Circuitry for 8-Bit Boot ROM ..................................... 10-13

8-Bit Boot ROM Timing ........................................................ 10-13

Access Time Computation Diagram ....................................... 10-14

Signal Relationships to CLKOUT ............................................ 10-15

Signal Width Specifications .......... ...... ...................... ............ 10-15

Skew between Two Outputs ................................................. 10-17

Circuitry for Interfacing 8-Bit Device to 16-Bit Memory in

Single-Address DMA Mode ................................................ 10-18 xxii MC68340 USER'S MANUAL

MOTOROLA

LIST OF TABLES

Table

Number Title

Page

Number

2-1 Signal Index ........................................................................... 2-2

2-2 Address Space Encoding ................................................ ......... 2-5

2-3 DSACKx Codes and Results .......... ................................ ........... 2-6

2-4 SIZx Signal Encoding......................................................... ..... 2-7

2-5 Signal Summary ..................................................................... 2-15

3-1 SIZx Signal Encoding .............................................................. 3-3

3-2 Address Space Encoding ...... ..................................... .............. 3-4

3-3 DSACKx Codes and Results............. ............................. ........... 3-6

3-4 DSACKx, BERR, and HALT Assertion Results............................. 3-35

3-5 Reset Source Summary...... .......................................... ........... 3-48

4-1 Location of Modules ............................................................... 4-3

4-2 System Frequencies from 32.768-kHz Reference ......................... 4-12

4-3 Clock Control Signals...................................................... ........ 4-12

4-4 Port A Pin Assignment Register Function.................................. 4-15

4-5 Port B Pin Assignment Register and FIRG Bit Function....... ........ 4-16

4-6 Show Cycle Control Bits.......................................................... 4-21

4-7 Deriving Software Watchdog Timeout.. ..................................... 4-24

4-8 BMT Encoding ........................................................................ 4-24

4-9 PIRGL Encoding...................................................................... 4-26

4-10 DD Encoding....................... ........................................... ........ 4-33

4-11 PS Encoding ........................................................................... 4-33

5-1 Instruction Set Summary................ ......................................... 5-7

5-2 Implicit Reference Instructions................................... .............. 5-18

5-3 EA Mode Categories ............................... .................... ............ 5-27

5-4 Instruction Set Summary................................................. ........ 5-39

5-5 Condition Code Computations........................................ .......... 5-44

5-6 Data Movement Operations..................................................... 5-46

5-7 Integer Arithmetic Operations.................................................. 5-47

5-8 Logical Operations.................................................................. 5-48

5-9 Shift and Rotate Operations..................................................... 5-49

5-10 Bit Manipulation Operations .................................................... 5-50

MOTOROLA

MC68340 USER'S MANUAL xxiii

LIST OF TABLES (Continued)

Table

Number Title

Page

Number

5-11 Binary-Coded Decimal Operations............................................ 5-50

5-12 Program Control Operations........... ............................ ............. 5-51

5-13 System Control Operations ...................................................... 5-52

5-14 Condition Tests ...................................................................... 5-53

5-15 Standard Usage Entries.......................................... ................. 5-54

5-16 Compressed Table Entries .... ................................. .................. 5-56

5-17 8-Bit Independent Variable Entries.......................... .................. 5-58

5-18 Exception Vector Assignments ................................................. 5-66

5-19 Exception Priority Groups ........................................................ 5-68

5-20 Tracing ControL...................................................................... 5-77

5-21 BDM Source Summary............... ............................................. 5-97

5-22 Polling the BDM Entry Source.................. ........... ..... .... ............ 5-98

5-23 CPU-Generated Message Encoding...................... ..................... 5-101

5-24 Size Field Encoding..... .................... ............... .... .... ................. 5-106

5-25 BDM Command Summary ....................................................... 5-109

5-26 Register Field for RSREG ......................................................... 5-112

5-27 Register Field for WSREG ...................... ................... ............... 5-113

6-1 FRZ Encoding ......................................................................... 6-12

6-2 SSIZE Encoding...................................................................... 6-15

6-3 DSIZE Encoding ...................................................................... 6-15

6-4 REQ Encoding ........................................................................ 6-16

6-5 BB Encoding.......................................................................... 6-16

6-6 Address Space Encoding.......................................... ............... 6-19

7-1

7-2

Register Addressing and Address-Triggered Commands ............. 7-22

FREEZE Control Bits.......................... .............. ..... ................... 7-23

7-3 Parity Mode and Parity Type Control Bits.................................. 7-26

7-4 Bits/Character Control Bits ............................................ ; .......... 7-27

7-5 Receiver Clock Select .................... ........................ .................. 7-30

7-6 Transmitter Clock Select .......................................................... 7-31

7-7 Miscellaneous Command Control Bits....................................... 7-32

7-8 Transmitter Command Bits................. ............ ......................... 7-33

7-9 Receiver Command Bits.......................................................... 7-34

7-10 Channel Mode Bits .................................................................. 7-43

7-11 Stop-Bit Length Control Bits ..................................................... 7-45 xxiv MC68340 USER'S MANUAL MOTOROLA

LIST OF TABLES (Concluded)

Table

Number Title

Page

Number

8-1 OC Encoding .......................................................................... 8-18

8-2 FRZ Encoding......................................................................... 8-20

8-3 IE Encoding ............................................................................ 8-22

8-4 POT Encoding........................................................................ 8-23

8-5 MODE Encoding..................................................................... 8-24

8-6 OC Encoding.......................................................................... 8-24

9-1 Instructions............................................................................ 9-3

9-2 Boundary Scan Bit Definitions.................................................. 9-5

10-1 Memory Access Times at 16.78 MHz ......................................... 10-14

MOTOROLA

MC68340 USER'S MANUAL xxv

xxvi


MOTOROLA

SECTION 1

DEVICE OVERVIEW

The MC68340 is a 32-bit integrated processor unit, combining high-performance data manipulation capabilities with powerful peripheral subsystems. The

MC68340 is a member of the M68300 Family of modular devices featuring fully static, high-speed complementary metal-oxide semiconductor (HCMOS) technology. Based on the powerful MC68000, the CPU32 central processing module of the MC68340 provides enhanced system performance and uses the extensive software base of the M68000 Family. Figure 1-1 shows the major components of the MC68340.

SYSTEM

INTEGRATION

MODULE

CPU32

CORE

TWO-

CHANNEL

SERIAL

110

TWO-CHANNEL DMA

CONTROLLER

TIMER TIMER

MODULE MODULE

Figure 1-1. Block Diagram

The MC68340 also contains intelligent peripheral modules such as the direct memory access (DMA) controller, which provides two channels of single- or dual-address transfer capability. Two channels of high-speed serial communications are provided by the serial module with synchronous and asynchron-

MOTOROLA

'MC68340

USER'S MANUAL

1-1

ous protocols available. The two timer modules are identical and can be externally cascaded. Four chip selects enhance system integration for easy external memory or peripheral access. These modules are connected on-chip via an intermodule bus (1MB).

The major features of the MC68340 are as follows:

• Integrated System Functions in a Single Chip

• 32-Bit M68000 Family Central Processor

Upward Object-Code Compatible with the MC68000 and MC68010

New Instructions for Controller Applications

Higher Performance Execution

• Two-Channel DMA Capability for Low-Latency Memory Accesses

• Two-Channel Serial 1/0

• Two Multiple-Mode 16-Bit Timers

• Four Programmable Chip-Select Signals

• System Failure Protection:

Software Watchdog Timer

Periodic Interrupt Timer

Spurious Interrupt, Double Bus Fault, and Bus Timeout Monitors

Automatic Programmable Bus Termination

• Up to 16 Discrete 1/0 Pins

• Low-Power Operation

• HCMOS Technology Reduces Power in Normal Operation

• LPSTOP Mode Provides Static State for Lower Standby Drain

• Frequency: 16.78-MHz Maximum Frequency at 5-V Supply, Software Programmable

• Packages: 144-Pin Ceramic Quad Flat Pack (CQFP)

145-Pin Plastic Pin Grid Array (PGA)

1.1

CENTRAL PROCESSOR UNIT

The central processing unit ofthe MC68340 is the CPU32, an upward-compatible

M68000 Family member that excels in processing calculation-intensive algorithms and supporting high-level languages. All MC68010 and most MC68020 enhancements, such as virtual memory support, loop mode operation, instruction pipeline, and 32-bit mathematical operations, are supported. Powerful addressing modes provide compatibility with existing software programs and

1-2 MC68340 USER'S MANUAL MOTOROLA

increase the efficiency of high-level language compilers. New instructions, such as table lookup and interpolate and low-power stop, support the specific requirements of controller applications. Most instructions can execute in onehalf the number of clocks required by an MC68000, yielding an overall 1.6 times performance of the same-speed MC68000.

1.2 INTELLIGENT PERIPHERALS

To improve total system throughput and reduce part count, size, and cost of system implementation, the MC68340 also features intelligent, on-chip, peripheral subsystems and typical glue logic. These subsystems include the system integration module (SIM), the DMA module, the serial module, and the timer modules.

1.2.1 System Integration Module

The SIM includes an external interface and various functions that reduce the need for external glue logic. The SIM contains the external bus interface, four chip selects, system protection, and clock generation.

1.2.1.1 EXTERNAL BUS INTERFACE. Based on the MC68020 bus, the external bus provides 32 address lines and 16 data lines. The data bus allows dynamic sizing between 8- and 16-bit data accesses. External bus arbitration is accomplished by a four-line handshaking interface. Transfers can be made in as little as two clock cycles.

1.2.1.2 CHIP SELECTS. Four independent chip selects can enable external circuits, providing all handshaking and timing signals with up to 265-ns access times.

Block size is programmable in 256-byte increments up to the 4-Gbyte address capability. Accesses can be preselected for either 8- or 16-bit transfers.

1.2.1.3 SYSTEM PROTECTION SUBMODULE. The M68000 Family of processors is designed with the concept of providing maximum system safeguards. Additional system protection is provided on the MC68340 by various monitors and timers, including the bus monitor, double bus fault monitor, spurious interrupt monitor, software watchdog timer, and the periodic interrupt timer.

These system functions are integrated on the MC68340 to reduce board size and the cost incurred with external components.

MOTOROLA

MC68340 USER'S MANUAL 1-3

1.2.1.4 SYSTEM CLOCK. The system clock can be generated by an on-chip phaselocked loop (PLL) circuit to run the device up to 16.78 MHz from a 32.768-kHz watch crystal. An external clock can also be used. The system speed can be changed dynamically with the PLL, providing either high performance or low power consumption under software control. With its fully static HCMOS design, it is possible to completely stop the system clock in software while still preserving the contents of the registers.

1.2.2 Direct Memory Access Module

In dual-address mode, the DMA module supports 32 bits of address and 16 bits of data with each of its two independent channels. In single-address mode, the DMA module supports 32 bits of address and 32 bits of data as well as providing address and control signals during a single-ended transfer. The requesting device either sends or receives data to or from the specified address.

In dual-address mode, two bus transfers occur, one from a source device and the other to a destination device. In dual-address mode, operands are packed or unpacked according to port sizes and addresses.

Each channel has an independent request, acknowledge, and done indication.

The request mode can be internal, with four adjustable bus bandwidths, or external, with edge or level trigger. The DMA module can sustain a transfer rate of 33.3 Mbytes per second in single-address mode, and nearly 8.4 Mbytes per second in dual-address mode.

1.2.3 Serial Module

The serial module contains two fully independent serial ports that have a maximum transfer rate of 3 million bits per second (Mbps) in synchronous mode.

Using the 1/16 clock in asynchronous mode, a channel can operate at 188 kbps.

The baud rate generator can be programmed for different baud rates on transmit and receive.

Full modem support is provided with separate request to send (RTS) and clear to send (CTS) signals for each channel. Full duplex, local loopback, or remote loop back modes are available. The data format can be 5, 6, 7, or 8 bits with even, odd, or no parity and a programmable number of stop bits. A wide variety of maskable interrupt capability is provided on each channel. Channel 1 also provides service request signals.

1-4


MOTOROLA

1.2.4

Timer Modules

The two timer modules are identical, and the timers can be externally cascaded.

Each timer has an 8-bit prescaler and a 16-bit counter. The prescaler input can be tied to the system clock or an external input frequency. The counter can be driven directly from the timer clock or tapped from any of the prescaler's eight bits.

Each timer has a variety of operational modes. Symmetrical or asymmetrical square-wave generation and pulse-width and period measurement are available. A variable-width single-shot pulse can be generated. Output compare and input capture can be performed concurrently, and a signal-generating capability based on output compare is available.

MOTOROLA


1-6


MOTOROLA

SECTION 2

SIGNAL DESCRIPTIONS

This section contains brief descriptions of the MC68340 input and output signals in their functional groups as shown in Figure 2-1.

A31IPORT A711ACK7

I

IW

I:J:

PORTA

A2SIPORT AlIIACK1

A24IPORTAO

CPU32

CORE

TWO-CHANNEL

SERIAL

110

RxDA

TxDA

CTSA

RxDB

TxDB

CTSB

A23-AO

D1~DO

FC3-FCO

RESET

BERR

HALT iSS

pjjj

SIZ1

SIZO

DSACK1

DSACKO

BR

BG

BGACK

RMC

SYSTEM

INTEGRATION

MODULE

TxRDYAlOP6

RxRDY AlFFULLAIOP4

RTSBlOP1

RTSAlOPO

TWO-CHANNEL

DMA

CONTROLLER

TIMER

MODULE

TIMER

MODULE

IR07/PORT B7

IROSIPORT B6

IROSIPORT B5

IR03IPORT B3

CS3t1R04IPORT B4

CS2t1R02IPORT B2

CS1t1R01IPORT B1

CSC/AVEC

MODCKlPORT BO

Ii I~ I~ lil§ I!

Figure 2-1. Functional Signal Groups

MOTOROLA


2-1

2.1

SIGNAL INDEX

The input and output signals for the MC68340 are listed in Table 2-1. The name, mnemonic, and brief functional description are presented. For more detail on each signal, refer to the paragraph named for the signal. Guaranteed timing specifications for the signals listed in Table 2-1 can be found in MC68340/D,

MC68340 Technical Summary.

Signal Name

Address Bus

Address Bus/Port A7-AO/IACK7-IACK1

Data Bus

Function Codes

Chip Select/IR04, IR02, IR01/Port B4, B2,

B1, AVEC

Bus Request

Bus Grant

Bus Grant Acknowledge

Data and Size Acknowledge

Read-Modify-Write Cycle

Address Strobe

Data Strobe

Size

Read/Write

Interrupt Request Level/Port B7, B6,

B5, B3

Reset

Halt

Bus Error

System Clock Out

Table 2-1. Signal Index

Mnemonic

A23-AO

A31-A24

D15-DO

FC3-FCO

CS3-CSO

BR

BG

BGACK

DSACK1,

DSACKO

RMC

AS

DS

SIZ1, SIZO

R/w

IR07, IR06,

IR05, IR03

RESET

HALT

BERR

CLKOUT

Function

Lower 24 bits of address bus

Upper eight bits of address bus, parallel I/O port, or interrupt acknowledge lines

16-bit data bus used to transfer byte or word data

Identifies the processor state and the address space of the current bus cycle

Enables peripherals at programmed addresses or provides parallel I/O and automatic vector request during an interrupt acknowledge cycle

Indicates that an external device requires bus mastership

Indicates that the current bus cycle is complete and the MC68340 has relinquished the bus

Indicates that an external device has assumed bus mastership

Provides asynchronous data transfers and dynamic bus sizing

Identifies the bus cycle as part of an indivisible read-modify-write operation

Indicates that a valid address is on the address bus

During a read cycle, DS indicates that an external device should place valid data on the data bus.

During a write cycle, DS indicates that valid data is on the data bus.

Indicates the number of bytes remaining to be transferred for this cycle

Indicates the direction of data transfer on the bus

Provides an interrupt priority level to the CPU32 or provides parallel I/O

System reset

Suspends external bus activity

Indicates an erroneous bus operation is being attempted

Internal system clock

2-2


Signal Name

Crystal Oscillator

External Filter Capacitor

Clock Mode Select/Port BO

Instruction Fetch

Instruction Pipe

Breakpoint

Freeze

Receive Data

Transmit Data

Clear to Send

Request to Send/OP1,OPO

Serial Crystal Oscillator

Serial Clock

Transmitter Ready/OP6

Receiver Ready/FIFO Full/OP4

DMA Request

DMA Acknowledge

DMA Done

Timer Gate

Timer Input

Timer Output

Test Clock

Test Mode Select

Test Data In

Test Data Out

Synchronizer Power

System Power Supply and Return

Table 2-1. Signal Index (Continued)

Mnemonic Function

EXTAL,XTAL Connections for an external crystal to the internal oscillator circuit

XFC Connection pin for an external capacitor to filter the circuit of the phase-locked loop

MODCK

IFETCH

Selects the source of the internal system clock or furnishes a parallel I/O bit

Indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed

IPIPE Used to track movement of words through the instruction pipeline

Signals a hardware breakpoint to the CPU32 BKPT

FREEZE Indicates that the CPU32 has acknowledged a breakpoint

RxDA,RxDB Serial input to the serial module

TxDA, TxDB Serial output from the serial module

CTSA,CTSB Serial module clear to send inputs

RTSA,RTSB Serial module request to send outputs or can be parallel outputs

X1, X2

SCLK

TxRDYA

Connections for an external crystal to the serial module internal oscillator circuit

External serial module clock input

RxRDYA

Indicates transmit buffer has a character or can be a parallel output

Indicates receive buffer has a character, the receiver FIFO buffer is full, or can be a parallel output

DREQ2, DREQ1 Input that starts DMA process

DACK2, DACK1 Output that signals an access during DMA

DONE2, DONE1 Bidirectional signal that indicates last transfer

TGATE2,

TGATE1

Counter enable input to timer

TIN2, TIN1 Time reference input to timer

TOUT2, TOUT1 Output waveform from timer

TCK

TMS

TDI

TDO

Provides a clock for IEEE 1149.1 test logic

Controls test mode operations

Serial test instructions and test data signal

Serial test instructions and test data signal

Power supply to VCO

VCCSYN

VCC, GND Power supply and return to the MC68340

MOTOROLA


2.2 ADDRESS BUS

The address bus consists of the following two groups. Refer to SECTION 3 BUS

OPERATION for information on the address bus and its relationship to bus operation.

2.2.1 Address Bus (A23-AO)

These three-state outputs (along with A31-A24) provide the address for the current bus cycle, except in the CPU address space. Refer to SECTION 3 BUS

OPERATION for more information on the CPU address space. A23 is the most significant address signal in this group.

2.2.2 Address Bus (A31-A24)

These pins can be programmed as the most significant eight address bits, port

A parallel

liD,

or interrupt acknowledge strobes. These pins can be used for more than one of their multiplexed functions as long as the external demultiplexing circuit properly resolves collisions between the different functions.

A31-A24. These pins can function as the most significant eight address bits.

A31 is the most significant address signal in this group.

Port A7-AO. These eight pins can serve as a dedicated parallel

liD

port. See

SECTION 4 SYSTEM INTEGRATION MODULE for more information on programming these pins.

IACK7-IACK1. The MC68340 asserts one of these pins to indicate the level of an external interrupt during an interrupt acknowledge (lACK) cycle. Peripherals can use the lACK strobes instead of monitoring the address bus and function codes to determine that an lACK cycle is in progress and to obtain the current interrupt level. See SECTION 3 BUS OPERATION for more information. Only seven of these eight pins are used as lACK 'strobe outputs since there is no

IACKO strobe.

2.3 DATA BUS (015-00)

These three-state bidirectional signals provide the general-purpose data path between the MC68340 and all other devices. Although the data path is a maximum of 16 bits wide, it can be dynamically sized to support 8- or 16-bit transfers. D15 is the most significant bit of the data bus. Refer to SECTION 3 BUS

OPERATION for information on the data bus and its relationship to bus operation.


2.4 FUNCTION CODES' (FC3-FCO)

These three-state outputs identify the processor state and the address space of the current bus cycle as noted in Table 2-2. Refer to SECTION 3 BUS OP-

ERATION for more information.

Table 2-2. Address Space Encoding

Function Code Bits

3

2 1 0

0 0 0 0

0 0 0

1

Address Spaces

Reserved (Motorola)

User Data Space

User Program Space

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

Reserved (User)

Reserved (Motorola)

Supervisor Data Space

0 1 1 0 Supervisor Program Space

0

1 1

1

1 x x x

CPU Space

DMA Space

2.5 CHIP SELECTS (CS3-CSO)

These pins can be programmed to be chip-select output signals, port B parallel

liD

and autovector input, or additional interrupt request lines.

CS3-CSO. The chip-select output signals enable peripherals at programmed addresses. CSO is the chip select for a ROM containing the user's reset vector and initialization program; therefore, it functions as the boot chip select immediately after reset. Refer to

SECTION 4 SYSTEM INTEGRATION MODULE for more information on chip selects.

Port B4, B2, B1, AVEC.

This signal group functions as three bits of parallel

liD

and the autovector input. Refer to SECTION 4 SYSTEM INTEGRATION MOD-

ULE for information on parallel

110

signals. AVEC requests an automatic vector during an interrupt acknowledge cycle. Refer to SECTION 3 BUS OPERATION and SECTION 4 SYSTEM INTEGRATION MODULE for more information on the autovector function.

IRQ4, IRQ2, IRQ1.

Interrupt request lines are prioritized external lines to the

CPU32. These additional interrupt request lines are selected by the FIRO bit in the MCR (see SECTION 4 SYSTEM INTEGRATION MODULE). Only three functions are available since there is no IROO function.

MOTOROLA MC68340 USER'S MANUAL 2-5

2.6 INTERRUPT REQUEST LEVEL (lRQ7, IRQ6, IRQ5, IRQ3)

These pins can be programmed to be either prioritized interrupt request lines or port B parallel

lID.

IRQ7, IRQ6, IRQ5, IRQ3. IRQ7, the highest priority, is nonmaskable.

IRQ6-IRQ1 are internally maskable interrupts. Refer to

SECTION 5 CPU32 for more information on interrupt request lines.

Port B7, B6, B5, B3.

These pins can be used as port

B parallel

lID.

Refer to

SECTION 4 SYSTEM INTEGRATION MODULE for more information on parallel

lID

signals.

2.7 BUS CONTROL SIGNALS

These signals control the bus transfer operations of the MC68340.

2.7.1 Data and Size Acknowledge (DSACK1, DSACKO)

These two active-low input signals allow asynchronous data transfers and dynamic data bus sizing between the

MC68340 and external devices as listed in the following table. Refer to

SECTION 3 BUS OPERATION for more information on these signals and their relationship to dynamic bus sizing.

Table 2-3. DSACKx Codes and Results

DSACK1 DSACKO

1

1

(Negated) (Negated)

Result

Insert Wait States in Current Bus Cycle

1

0

(Negated) (Asserted)

Complete Cycle Data Bus Port Size Is 8 Bits

0 1

(Asserted) (Negated)


0 0

Reserved Defaults to 16-Bit Port Size,

(Asserted) (Asserted) Can Be Used for 32-Bit DMA cycles

2.7.2 Autovector (AVEC)

See 2.5 CHIP SELECTS (CS3-CSO).

2-6


2.7.3 Address Strobe (AS)

This output signal is driven by the bus master to indicate a valid address on the address bus. The function code, size, and read/write signals are also valid when AS is asserted. Refer to SECTION 3 BUS OPERATION for information about the relationship of AS to bus operation.

2.7.4 Data Strobe (OS)

During a read cycle, this output signal is driven by the bus master to indicate that an external device should place valid data on the data bus. During a write cycle, the data strobe indicates that valid data is on the da!a bus. Refer to

SECTION 3 BUS OPERATION for information about the relationship of DS to bus operation.

2.7.5 Transfer Size (SIZ1, SIZO)

These output signals are driven by the bus master to indicate the number of operand bytes remaining to be transferred in the current bus cycle as noted in

Table 2-4. Refer to SECTION 3 BUS OPERATION for more information.

Table 2-4. SIZx Signal Encoding

SlZ1

0

1

1

0

SIZO

1

0

1

0

Transfer Size

Byte

Word

3 Byte

Long Word

2.7.6 Read/Write (R/W)

This active-high output signal is driven by the bus master to indicate the direction of data transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. Refer to SECTION 3 BUS

OPERATION for more information.

2.8 BUS ARBITRATION SIGNALS

The following signals are the four bus arbitration control signals used to determine the bus master. Refer to SECTION 3 BUS OPERATION for more information.

MOTOROLA


2.8.1 Bus Request (BR)

This active-low input signal indicates that an external device needs to become the bus master. This input is typically wire-ORed. Refer to SECTION 3 BUS

OPERATION for more information.

2.8.2 Bus Grant (BG)

Assertion of this active-low output signal indicates that the bus master has relinquished the bus. Refer to SECTION 3 BUS OPERATION for more information.

2.8.3 Bus Grant Acknowledge (BGACK)

Assertion of this active-low input indicates that an external device has become the bus master. Refer to SECTION 3 BUS OPERATION for more information.

2.8.4 Read-Modify-Write Cycle (RMC)

This output signal identifies the bus cycle as part of an indivisible read-modifywrite operation; it remains asserted during all bus cycles of the read-modifywrite operation to indicate that bus ownership cannot be transferred. Refer to

SECTION 3 BUS OPERATION for additional information.

2.9 EXCEPTION CONTROL SIGNALS

These signals are used by the integrated processor unit to recover from an exception.

2.9.1 Reset (RESET)

This active-low, open-drain, bidirectional signal is used to initiate a system reset. An external reset signal (as well as a reset from the SIM) resets the

MC68340 as well as all external devices. A reset signal from the CPU32 (asserted as part of the RESET instruction) resets external devices only the internal state of the CPU32 is not affected; other on-chip modules are reset, but the configuration is not altered. When asserted by the MC68340, this signal is guaranteed to be asserted for a minimum of 512 clock cycles. Refer to SECTION

3 BUS OPERATION for a description of bus reset operation and SECTION 5

CPU32 for information about the reset exception.

2-8


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2.9.2 Halt (HALT)

This active-low, open-drain, bidirectional signal is asserted to suspend external bus activity, to request a retry when used with BERR, or to perform a singlestep operation. As an output, HALT indicates a double bus fault by the CPU32.

Refer to

SECTION

3

BUS OPERATION for a description of the effects of HALT on bus operation.

2.9.3 Bus Error (BERR)

This active-low input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to

SECTION

3

BUS OPERATION for a description of the effects of

BERR on bus operation.

2.10 CLOCK SIGNALS

These signals are used by the MC68340 for controlling or generating the system clocks. Refer to SECTION 4 SYSTEM INTEGRATION MODULE for more information on the various clock signals.

2.10.1 System Clock (CLKOUT)

This output signal is the system clock and is used as the bus timing reference by external devices. CLKOUT can be slowed in low-power stop mode. See

SECTION

4

SYSTEM INTEGRATION MODULE for more information.

2.10.2 Crystal Oscillator (EXTAL, XTAL)

These two pins are the connections for an external crystal to the internal oscillator circuit. If an external oscillator is used, it should be connected to EXTAL, with XTAL left open. See SECTION 4 SYSTEM INTEGRATION MODULE for more information.

2.10.3 External Filter Capacitor (XFC)

This pin is used to add an external capacitor to the filter circuit of the phaselocked loop. The capacitor should be connected between XFC and VCCSYN.

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2-9

2.10.4 Clock Mode Select (MODCK)

This pin selects the source of the internal system clock during reset. After reset, it can be programmed to be port B parallel I/O.

MODCK. The state of this active-high input signal during reset selects the source of the internal system clock. If MODCK is high during reset, the internal voltage-controlled oscillator (VCO) furnishes the system clock. If MODCK is low during reset, an external frequency appearing at the EXTAL pin furnishes the system clock.

Port

BO.

This pin can be used as port B parallel I/O. Refer to SECTION 4 SYSTEM

INTEGRATION MODULE for more information on parallel I/O signals.

2.11 INSTRUMENTATION AND EMULATION SIGNALS

These signals are used for test or software debugging.

2.11.1 Instruction Fetch (lFETCH)

This active-low output signal indicates when the CPU32 is performing an instruction word prefetch and when the instruction pipeline has been flushed.

Refer to SECTION 5 CPU32 for information about IFETCH.

2.11.2 Instruction Pipe (lPIPE)

This active-low output signal is used to track movement of words through the instruction pipeline. Refer to SECTION 5 CPU32 for information about IPIPE.

2.11.3 Breakpoint (BKPT)

This active-low input signal is used to signal a hardware breakpoint to the

CPU32. Refer to SECTION 5 CPU32 for information about BKPT.

2.11.4 Freeze (FREEZE)

Assertion of this active-high output signal indicates the CPU32 has acknowledged a breakpoint and has initiated background mode operation. See SEC·

TION 5 CPU32 for more information about FREEZE and background mode.

2-10


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2.12 TEST SIGNALS

The following signals are used with the onboard test logic defined by the IEEE

1149.1 standard. See SECTION 9 IEEE 1149.1 TEST ACCESS PORT for more information on the use of these signals.

2.12.1 Test Clock (TCK)

This input provides a clock for onboard test logic defined by the IEEE 1149.1 standard.

2.12.2 Test Mode Select (TMS)

This input controls test mode operations for onboard test logic defined by the

IEEE 1149.1 standard.

2.12.3 Test Data In (TO I)

This input is used for serial test instructions and test data for onboard test logic defined by the IEEE 1149.1 standard.

2.12.4 Test Data Out (TOO)

This output is used for serial test instructions and test data for onboard test logic defined by the IEEE 1149.1 standard.

2.13 SERIAL MODULE SIGNALS

The following signals are used by the serial module for data and clock signals.

See SECTION 7 SERIAL MODULE for more information on the serial module signals.

2.13.1 Serial Crystal Oscillator (X2,X1)

These pins furnish the connection to a crystal or external clock, which must be supplied when using the baud rate generator. An external clock is connected to the X1 pin only. See SECTION 7 SERIAL MODULE for more information.

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2-11

2.13.2 Serial External Clock Input (SCLK)

This input can be used as the external clock input for channel A or channel 8, bypassing the baud rate generator. The clock inputs are controlled by the clock select registers (CSR). See SECTION 7 SERIAL MODULE for more information.

2.13.3 Receive Data (RxDA, RxDB)

These input signals furnish serial data input to the serial. module. Data is sampled on the rising edge of the selected clock source, with the least significant bit received first. See SECTION 7 SERIAL MODULE for more information.

2.13.4 Transmit Data (TxDA, TxDB)

These signals are the transmitter serial data outputs from the serial module.

The output is held high (mark condition) when the transmitter is disabled; idle, or in localloopback mode. Data is shifted out on the falling edge of the selected clock source, with the least significant bit transmitted first. See SECTION 7

SERIAL MODULE for more information.

2.13.5 Clear to Send (CTSA, CTSB)

These active-low inputs can be programmed as clear to send inputs. See SEC-

TION 7 SERIAL MODULE for more information.

2.13.6 Request to Send (RTSA, RTSB)

These active-low outputs can be programmed as request to send outputs or used as discrete outputs. See SECTION 7 SERIAL MODULE for more information.

RTSA, RTSB. These signals function as the channel request to send outputs.

OP1, OPO. These signals reflect the complement of the value of bit 1 and bit

0, respectively, in the output port data register.

2.13.7 Transmitter Ready (TxRDYA)

This active-low output can be programmed as the channel A transmitter ready status indicator or used as a discrete output. See SECTION 7 SERIAL MODULE for information on controlling the function of this bit.

2-12 MC68340 USER'S MANUAL

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TxRDVA. This signal reflects the complement ofthe value of bit 2 in the channel

A status register and can control parallel data flow by acting as an interrupt when the transmitter contains a character.

OP6. This signal reflects the complement of the value of bit 6 in the output port data register.

2.13.8 Receiver Ready (RxRDYA)

This active-low output can be programmed as the channel A receiver ready status indicator, the channel A FIFO full indicator, or used as a discrete output.

See SECTION 7 SERIAL MODULE for information on controlling the function of this bit.

RxRDVA. This signal reflects the complement of the value of bit 1 in the interrupt status register and can control parallel data flow by acting as an interrupt when the receiver contains a character.

FFULLA. This signal reflects the complement ofthe value of bit 1 in the interrupt status register and can control parallel data flow by acting as an interrupt when the receiver FIFO is full.

OP4. This signal reflects the complement of the value of bit 4 in the output port data register.

2.14 DMA MODULE SIGNALS

The following signals are used by the direct memory access (DMA) module to provide external handshake for either a source or destination. See SECTION 6

DMA MODULE for additional information.

2.14.1 DMA Request (DRE02, DRE01)

These inputs from a peripheral start the DMA transfer process. The assertion level can be either active-low or falling edge.

2.14.2 DMA Acknowledge (DACK2, DACK1)

These outputs to a peripheral are asserted during accesses, after a DMA transfer is in progress.

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2.14.3 DMA Done (DONE2, DONE1)

These active-low bidirectional signals indicate that the last transfer is being performed.

2.15 TIMER SIGNALS

The following external signals are used by the timer modules.

2.15.1 Timer Gate (TGATE2, TGATE1)

The low state of these input signals furnish counter enable inputs to the timer modules in most modes of operation. See

SECTION 8 TIMER MODULES

for additional information.

2.15.2 Timer Input (TIN2, TIN1)

The falling edge of these input signals can be programmed to furnish time references to the timer modules. See


for additional information on programming this function.

2.15.3 Timer Output (TOUT2, TOUT1)

These output signals provide the various output waveforms from the timer modules. See



2.16 SYNTHESIZER POWER (VeeSYN)

This pin supplies a quiet power source to the VCO to provide greater frequency stability.

2.17 SYSTEM POWER AND GROUND (Vee AND GND)

These pins provide system power and return to the MC68340. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression.

2-14


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2.18

SIGNAL SUMMARY

Table 2-5 presents a summary of all the signals discussed in the preceding paragraphs.

Table 2-5. Signal Summary

Signal Name

Address Bus

Address Bus/Port A7-AO/

IACK7-IACK1

Data Bus

Function Codes

Chip Select/IRQ4, IRQ2, IRQ1/Port B4,

B2, B1, AVEC

Bus Request

Bus Grant

Bus Grant Acknowledge

Data and Size Acknowledge

Mnemonic

A23-AO

A31-A24

D15-DO

FC3-FCO

CS3-CSO

Input/Output Active State Three-State

Output

-

Output/I/O/

Output

110

-/-/Low

Output

-

-

Output/lnput/ Low/Low/-

I/O

Input Low

Output

Input

Input

Low

Low

Low

Yes

Yes

Yes

Yes

No

-

No

-

Read-Modify-Write Cycle

Address Strobe

Data Strobe

Size

ReadlWrite

Interrupt Request Level/Port B7,

B6, B5, B3

Reset

Halt

Bus Error

System Clock Out

Crystal Oscillator

Crystal Oscillator

External Filter Capacitor

Clock Mode Select/Port BO

Instruction Fetch

Instruction Pipe

Breakpoint

Freeze

Receive Data

Transmit Data

Clear to Send

BR

BG

BGACK

DSACK1,

DSACKO

RMC

AS

DS

SIZ1, SIZO

-

RIW

- - - -

IRQ7,IRQ6,

IRQ5, IRQ3

RESET

HALT

BERR

CLKOUT

EXTAL

XTAL

XFC

MODCK

IFETCH

IPIPE

BKPT

FREEZE

RxDA,RxDB

TxDA,RxDB

CTSA,CTSB

Output

Output

Output

Output

Output

Input/I/O

1/0

I/O

Input

Output

Input

Output

Input

Input/I/O

Output

Output

Input

Output

Input

Output

Input

Low

Low

Low

-

High/Low

Low/-

Low

Low

Low

-

-

-

-

- / -

Low

Low

Low

High

-

-

Low

No

No

-

No

-

No

No

-

No

-

-

-

-

No

-

Yes

Yes

Yes

Yes

Yes

-


Table 2-5. Signal Summary

Signal Name

Request to Send/OP1,OPO



Serial Clock

Transmitter Ready/OP6

Receiver Ready/FIFO Full/OP4

DMA Request

DMA Acknowledge

DMA Done

Timer Gate

Timer Input

Timer Output

Test Clock

Test Mode Select

Test Data In

Test Data Out

Synchronizer Power

System Power Supply and Return

Mnemonic

RTSA,RTSB

X1

X2

SCLK

TxRDYA

RxRDYA

DRE02,DRE01

DACK2, DACK1

DONE2, DONE1

TGATE2,

TGATE1

TIN2, TIN1

TOUT2, TOUT1

TCK

TMS

TDI

TDO

VCCSYN

VCC, GND

Input/Output

Output/Output

Input

Output

Input

Output/Output

Output/Output/ Low/Low/-

Output

Input

Output

I/O

Input

Low

Low

Low

Low

Input

Output

Input

Input

Input

Output

-

-

Active State

Low/-

-

-

-

Low/-

-

-

-

High

High

High

-

-

Three-State

No

-

-

-

No

No

-

No

No

-

-

Yes

-

-

-

-

-

-

2-16


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SECTION 3

BUS OPERATION

This section provides a functional description of the bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the external bus is the same whether the MC68340 or an external device is the bus master; the names and descriptions of bus cycles are from the viewpoint of the bus master. For exact timing specifications, refer to

MC68340/D,


The MC68340 architecture supports byte, word, and long-word operands allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by the size outputs (SIZ1, SIZO) and data size acknowledge inputs (DSACK1, DSACKO). The MC68340 requires word and long-word operands to be located in memory on word boundaries. The only type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. For an 8-bit port, mUltiple bus cycles may be required for an operand transfer due to a word or long-word operand.

3.1

BUS TRANSFER SIGNALS

The bus transfers information between the MC68340 and external memory or a peripheral device. External devices can accept or provide 8 bits or 16 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68340 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning and type of the cycle as well as the address space and size of the transfer. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data' bus, indicate the validity of the address and provide timing information for the data. Both asynchronous and synchronous operation is possible for any port width. In asynchronous operation, the bus and control input signals are internally synchronized to the MC68340 clock, introducing a delay. This delay is the time required for the MC68340 to sample an input signal, synchronize the input to the internal clocks, and determine whether it is high or low. In synchronous operation, the bus and control input

MOTOROLA


signals must be timed to setup and hold times. Since no synchronization is needed, bus cycles can be completed in three clock cycles in this mode. Additionally, using the fast-termination option of the chip-select signals, two-clock operation for 16-bit ports is possible.

Furthermore, for all inputs, the MC68340 latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 3-1. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window .

. If an input makes a transition during the window time period, the level recognized by the MC68340 is not predictable; however, the MC68340 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section.

CLKOUT

EXT

~

SAMPLE WINDOW

Figure 3-1. Input Sample Window

3.1.1 Bus Control Signals

The MC68340 initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the beginning of a bus cycle, SIZ1 and SIZO are driven with the function code signals. SIZ1 and SIZO indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 3-1 lists the encoding of SIZ1 and SIZO. These signals are valid while address strobe (AS) is asserted. The read/write (R/W) signal determines the direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/W is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The read-modify-write cycle (RMC)

3-2


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signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation.

Table 3-1. SIZx Signal Encoding

Sl21

0

1

1

0

Sl20

1

0

1

0

Transfer Size

Byte

Word

3 Byte

Long Word

3.1.2 Function Codes

The function code signals (FC3-FCO) are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either normal or direct memory access (DMA) cycle, user or supervisor, and program or data spaces. One other address space is designated as CPU space to allow the CPU32 to acquire specific control information not normally associated with read or write bus cycles. The function code signals are valid while

AS is asserted.

Function codes (see Table 3-2) can be considered as extensions of the 32-bit linear address that can provide up to 16 different 4-Gbyte address spaces.

Function codes are automatically generated by the CPU32 to select address spaces for data and program at both user and supervisor privilege levels, a

CPU address space for processor functions, and an alternate master address space. User programs access only their own program and data areas to increase protection of system integrity and can be restricted from accessing other information. The S-bit in the CPU32 status register is set for supervisor accesses and cleared for user accesses to provide differentiation. Referto 3.4 CPU SPACE

CYCLES for more information.

3.1.3 Address Bus (A31-AO)

The address bus signals are outputs that define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The MC68340 places the address on the bus at the beginning of a bus cycle. The address is valid while AS is asserted.

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0

0

0

0

1

0

0

0

Function Code Bits

3 2 1 0

0 0 0 0

0

0

0

0

1

1

1

0

1

Address Spaces

Reserved (Motorola)

User Data Space

User Program Space

Reserved (User)

1

1

0

0

0

1

Reserved (Motorola)


1

1

1

1

0

Supervisor Program Space

1 CPU Space x x x

DMA Space

3.1.4 Address Strobe (AS)

AS is an output timing signal that indicates the validity of an address on the address bus and of many control signals. AS is asserted approximately onehalf clock after the beginning of a bus cycle.

3.1.5 Data Bus (015-00)

The data bus signals comprise a bidirectional, nonmultiplexed, parallel bus that contains the data being transferred to or from the MC68340. A read or write operation may transfer 8 or 16 bits of data (one or two bytes) in one bus cycle.

During a read cycle, the data is latched by the MC68340 on the last falling edge of the clock for that bus cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68340 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle.

3.1.6 Data Strobe (OS)

DS is an output timing signal that applies to the data bus. For a read cycle, the

-MC68340 asserts DS and AS simultaneously to signal the external device to place data on the bus. For a write cycle, DS signals to the external device that the data to be written is valid on the bus. The MC68340 asserts DS approximately one clock cycle after the assertion of AS during a write cycle.


3.1.7 Bus Cycle Termination Signals

The following signals can terminate a bus cycle.

3.1.7.1 DATA TRANSFER AND SIZE ACKNOWLEDGE SIGNALS (DSACK1 AND

DSACKO). During bus cycles, external devices assert DSACK1 and/or DSACKO as part of the bus protocol. During a read cycle, this signals the MC68340 to terminate the bus cycle and to latch the data. During a write cycle, this indicates that the external device has successfully stored the data and that the cycle may terminate. These signals also indicate to the MC68340 the size of the port for the bus cycle just completed (see Table 3-3). Refer to 3.3.1 Read Cycle for timing relationships of DSACK1 and DSACKO.

Additionally, the system integration module (SIM) can be programmed to internally generate DSACK1 and DSACKO for external accesses, eliminating logic required to generate these signals. The SIM can alternatively be programmed to generate a fast termination for 16-bit, synchronous accesses. Refer to 3.2.6

Fast Termination Cycles for additional information on these cycles.

3.1.7.2 BUS ERROR (BERR). This signal is also a bus cycle termination indicator and can be used in the absence of DSACKx to indicate a bus error condition.

BERR can also be asserted in conjunction with DSACKx to indicate a bus error condition, provided it meets the appropriate timing described in this section and in MC68340/D, MC68340 Technical Summary. Additionally, BERR and HALT can be asserted together to indicate a retry termination. Refer to 3.5 BUS

EXCEPTION CONTROL CYCLES for additional information on the use of these signals.

The internal bus monitor can be used to generate the BERR signal for internal and internal-to-external transfers in all the following descriptions. If the bus cycles of an external bus master are to be monitored, external BERR generation must be provided since the internal BERR monitor has no information about transfers initiated by an external bus master.

3.1.7.3 AUTOVECTOR (AVEC). This signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68340 should internally generate a vector number to locate an interrupt handler routine. AVEC can be generated either externally or internally by the SIM (refer to SECTION 4 SYSTEM INTE-

GRATION MODULE for additional information). AVEC is ignored during all other bus cycles.

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3.2 DATA TRANSFER MECHANISM

The MC68340 supports byte, word, and long-word operands, allowing access to 8- and 16-bit data ports through the use of asynchronous cycles controlled by DSACK1 and DSACKO. The MC68340 also supports byte, word, and longword operands, allowing access to 16-bit data ports through the use of synchronous cycles controlled by the fast termination capability of the SIM. The

MC68340 supports 32-bit single address mode DMA transfers on a 32-bit external bus, in a single bus cycle, if a 32-bit DSACKx is provided.

3.2.1 Dynamic Bus Sizing

The MC68340 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8- and 16-bit ports.

During an operand transfer cycle, the slave device signals its port size (byte or word) and indicates completion of the bus cycle to the MC68340 through the use of the DSACKx inputs. Refer to Table 3-3 for DSACKx encoding.

Table

3·3.

DSACKx Codes and Results

DSACK1

DSACKO

1 1

(Negated) (Negated)

Result

Insert Wait States in Current Bus Cycle

1 0

(Negated) (Asserted)


0 1

Complete Cycle Data Bus Port Size Is 16

(Asserted) (Negated) Bits

0 0 Reserved Defaults to 16-Bit Port Size Can

(Asserted)

(Asserted) Be Used for 32-Bit DMA Cycles

For example, if the MC68340 is executing an instruction that reads a long-word operand from a 16-bit port, the MC68340 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar but requires four read cycles. The addressed device uses DSACKx to indicate the port width. For instance, a 16-bit device always returns DSACKx for a 16-bit port (regardless of whether the bus cycle is a byte orword operation).

Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 16-bit port must reside on data bus bits 15-0, and an 8-bit port must reside on data bus bits 15-8. This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-bit ports and ensures that the MC68340 correctly transfers valid data.

3-6


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The MC68340 always attempts to transfer the maximum amount of data on all bus cycles; for a word operation, it always assumes that the port is 16 bits wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 3-2. The most significant byte of a long-word operand is OPO, and OP3 is the least significant byte. The two bytes of a word-length operand are OPO (most significant) and OP1. The single byte of a byte-length operand is OPO. These designations are used in the figures and descriptions that follow.

Case Transfer Case

SIZl

(a) Byte to Byte

(b)

Byte to Word (Even)

(c) Byte to Word (Odd)

(d) Word to Byte (Aligned)

(e)

Word to Byte (Misaligned)·

(Q Word to Word (Aligned)

(g) Word to Word (Misaligned)"

0

0

0

(h)

3 Byte to Byte (Aligned)·

(i) 3 Byte to Byte (Misaligned)·

0)

3 Byte to Word (Aligned)·

(k)

3 Byte to Word (Misaligned)·

(I) Long Word to Byte (Aligned)

1

0

(m)

Long Word to Byte (Misaligned)" 0

(n) Long Word to Word (Aligned)

0

(0) Long Word to Word (Misaligned)· 0

SIZO

1

0

0

0

0

0

0

0

0

OPERAND

I

OPO

I

OPl

31

I

OPO

23

AO DSACKl DSACKO

X

0

1

0

1

0

1

0

0

0

1

0 o o

X o

X

1 0 o o

X o

X o o o

X o

X

1 0 o o

X o

X

15

OP2

OPl

OPO

OP3

OP2

OPl

OP~

OataBus

015 08 07

OPO (0 PO)

DO

OPO

(OPO)

OPO

OPO

OPO

(OPO)

OPO

OP~

(OPO)

OPO

(OP1)

(0

PO)

OPl

OP~

(OP1)

(OPO)

OPO

(OPO)

OPO

OPO

OPO

(OPO)

OPl

OP~

(OP1)

(OPO)

OPl

OP~

0.

,

,

NOTES:

1. Operands in parentheses are ignored by the MC68340 during read cycles.

2. Misaligned and 3 byte transfer cases, identified by an asterisk, are not supported by the MC68340.

3. A 3-byte to byte transfer does occur as the second byte transfer of a long-word to byte port transfer.

Figure 3-2. MC68340 Interface to Various Port Sizes

Figure 3-2 shows the required organization of data ports on the MC68340 bus for both 8- and 16-bit devices. The four bytes shown in Figure 3-2 are connected through the internal data bus and data multiplexer to the external data bus.

The data multiplexer establishes the necessary connections for different com-

MOTOROLA


binations of address and data sizes. The multiplexer takes the two bytes of the

16-bit bus and routes them to their required positions. The positioning of bytes is determined by the size (SIZ1 and SIZO) and address (AO) outputs. The SIZ1 and SIZO outputs indicate the number of bytes to be transferred during the current bus cycle, as listed in Table 3-1. The number of bytes transferred during a write or read bus cycle is equal to or less than the size indicated by the SIZ1 and SIZO outputs, depending on port width. For example, during the first bus cycle of a long-word transfer to a word port, the size outputs indicate that four bytes are to be transferred although only two bytes are moved on that bus cycle.

The address line AO also affects the operation of the data multiplexer. During an operand transfer, A31-A 1 indicate the word base address of that portion of the operand to be accessed, and AO indicates the byte offset from the base.

Figure 3-2 lists the bytes required on the data bus for read cycles. The entries shown as OPn are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1, SIZO, and AO for the bus cycle.

The transfer cases marked misaligned are not generated by the MC68340.

3.2.2 Misaligned Operands

In this architecture, the basic operand size is 16 bits. Operand misalignment refers to whether an operand is aligned on a word boundary or overlaps the word boundary, determined by address line AO. When AO is low, the address is even and is a word and byte boundary. When AO is high, the address is odd and is a byte boundary only. A byte operand is properly aligned at any address; a word or long-word operand is misaligned at an odd address.

At most, each bus cycle can transfer a word of data aligned on a word boundary.

If the MC68340 transfers a long-word operand over a 16-bit port, the most significant operand word is transferred on the first bus cycle, and the least significant operand word is transferred on a following bus cycle.

The CPU32 restricts all operands (both data and instructions) to be aligned.

That is, word and long-word operands must be located on a word or long-word boundary, respectively. The only.type of transfer that can be performed to an odd address is a single-byte transfer, referred to as an odd-byte transfer. If a misaligned access is attempted, the CPU32 generates an address error exception and enters exception processing. Refer to SECTION 5 CPU32 for more information on exception processing.


MOTOROLA

3.2.3 Operand Transfer Cases

The following cases are examples of the allowable alignments of operands to ports.

3.2.3.1 BYTE OPERAND TO 8-BIT PORT, EVEN (AO

=

0). The MC68340 drives the address bus with the desired address and the size pins to indicate a singlebyte operand.

BYTE OPERAND

DATA BUS

CYCLE 1

D15 D8 D7 DO

I

OPO

I

(OPO)

I

SIZ1

0

SIZO AO DSACK1 DSACKO x

0

For a read operation, the slave responds by placing data on bits 15-8 of the data bus, asserting DSACKO and negating DSACK1 to indicate an 8-bit port.

The MC68340 then reads the operand byte from bits 15-8 and ignores bits 7-0.

For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACKx signals are read. The slave device reads the byte operand from bits 15-8 and places the operand in the specified location. The slave then asserts DSACKO to terminate the bus cycle.

3.2.3.2 BYTE OPERAND TO 16-BIT PORT, EVEN (AO=O).

The MC68340 drives the address bus with the desired address and the size pins to indicate a singlebyte operand.

BYTEOPERAND

~

7

Y

0

DATA BUS

CYCLE 1

D15

OPO

D8 D7

I

(OPO)

DO

I

SIZ1 o

SIZO AO DSACK1 DSACKO o

0 x

For a read operation, the slave responds by placing data on bits 15-8 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 15-8 and ignores bits 7-0.


For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACKx signals are read. The slave device reads the operand from bits 15-8 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle.

3.2.3.3

BYTE OPERAND TO 16-BIT PORT, ODD (AO= 1).

The MC68340 drives the address bus with the desired address and the size pins to indicate a singlebyte operand.

BYTE OPERAND

DATA BUS

CYCLE 1

D15

~

7

V

0

D8 D7 DO

I

(OPO)

OP~

I

SIZ1 o

SIZO AO DSACK1 DSACKO

1 0 X

For a read operation, the slave responds by placing data on bits 7-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 then reads the operand byte from bits 7-0 and ignores bits 15-8.

For a write operation, the MC68340 drives the single-byte operand on both bytes of the data bus because it does not know the port size until the DSACKx signals are read. The slave device reads the operand from bits 7-0 of the data bus and uses the address to place the operand in the specified location. The slave then asserts DSACK1 to terminate the bus cycle.

3.2.3.4

WORD OPERAND TO 8-BIT PORT, ALIGNED.

The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand.

WORD OPERAND

I

OP~

15

I

OP1

I t

87

0

DATA BUS

CYCLE 1

CYCLE 2

SIZ1

0

SIZO

0

1

AO DSACK1 DSACKO

0

1

0

0

For a read operation, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting DSACKO to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand from bits 15-8 and ignores bits 7-0. The MC68340 then decrements the transfer size

MOTOROLA


counter, increments the address, and reads the least significant byte of the operand from bits 15-8 of the data bus.

For a write operation, the MC68340 drives the word operand on bits 15-0 of the data bus. The slave device then reads the most significant byte of the operand from bits 15-8 of the data bus and asserts DSACKO to indicate that it received the data but is an 8-bit port. The MC68340 then decrements the transfer size counter, increments the address, and writes the least significant byte of the operand to bits 15-8 of the data bus.

3.2.3.5 WORD OPERAND TO 16-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a word operand.

WORD OPERAND

DATA BUS

CYCLE 1

I

OPO OP1

15

~ ~

0

I

D15 D8 D7 DO

I

OPO OP1

I

SIZ1

1

SIZO

0

- - - -

AO DSACK1 DSACKO

0 0 x

For a read operation, the slave responds by placing the data on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. When DSACK1 is asserted, the MC68340 reads the data on the data bus and terminates the cycle.

For a write operation, the MC68340 drives the word operand on bhs 15-0 of the data bus. The slave device then reads the entire operand from bits 15-0 of the data bus and asserts DSACK1 to terminate the bus cycle.

3.2.3.6 LONG-WORD OPERAND TO 8-BIT PORT, ALIGNED. The MC68340 drives the address bus with the desired address and the size pins to indicate a longword operand.

LONG-WORD OPERAND

I

OPO

I

OP1

I

OP2

31

~

23 15

DATA BUS

CYCLE 1

CYCLE 2

CYCLE 3

CYCLE 4

015

OPO

D8 D7

(OP1)

DO

OP1

OP2

OP3

(OP1)

(OP3)

(OP3)

I

OP3

7

0

I

SIZ1

0

1

0

SIZO

0

1

0

AO DSACK1 DSACKO

0 1

0

1 0

0 0

0

MOTOROLA


3-11

3-12

For a read operation, shown in Figure 3-3, the slave responds by placing the most significant byte of the operand on bits 15-8 of the data bus and asserting

DSACKO to indicate an 8-bit port. The MC68340 reads the most significant byte of the operand (byte 0) from bits 15-8 and ignores bits 7-0. The MC68340 then decrements the transfer size counter, increments the address, initiates a new cycle, and reads byte 1 of the operand from bits 15-8 of the data bus. The

MC68340 repeats the process of decrementing the transfer size counter, incrementing the address, initiating a new cycle, and reading a byte to transfer the remaining two bytes.

For a write operation, shown in Figure 3-4, the MC68340 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device

CLKOUT

A31-AO

FC3-FCO so

S2 S4 so

S2 54 so

S2

S4 so

S2 S4

_IL

rL

IL

n-n-n-

IL IL

n-

IL

rL rL 1L~

-

-~

-

-~

~

~

X

X

X

X c: c:

_V

-~

-1"\

I

r--\

/ r--\

I

~

I

~

I

~r-

I 1"\ I 1"\

I

~~

SIZO

-1\

4 BYTES

V

3 BYTES

\

2 BYTES

/

1 BYTE

:L~

Ir-~

SIZ1

-1\

V

\

_V

r\

/ r\

f

r\

f

\ fr-

_V

015-08

IQPO\

\...:.:...::...

IQP1\

~ roP2'

\..:.:....:....

V"'Qp3\

1"-=..:.1

07-00

~BYTE

READ

BYTE

READ

,.

BYTE

READ

LONG-WORD OPERAND READ FROM 8-BIT BUS

...

BYT~~

READ

Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port

MOTOROLA


then reads only the most significant byte of the operand (byte 0) from bits 15-8 of the data bus and asserts DSACKO to indicate reception and an 8-bit port.

The MC68340 then decrements the transfer size counter, increments the address, and writes byte 1 of the operand to bits 15-8 of the data bus. The

MC68340 continues to decrement the transfer size counter, increment the address, and write a byte to transfer the remaining two bytes to the slave device.

CLKOUT

A31-AO

FC3-FCO so

S2 S4 so

S2 S4 so

S2 S4 so

S2 S4

_iL rL iL

IL

rL

IL

IL

rL iL rL r1-

IL-

-

-X

-

-X

X

X

X

X

X

~

C= c=

-~

SIZO

SIZl

015-08

-~

\

J

I r \

/ r \

/ r \

I

~--

\

U

\

U

\

J

-1\

V

\

/

"""1\

4 BYTES

V

3 BYTES

2 BYTES

\

1 BYTE

ILr-

Vr-

-V

~

j

~

j

~

j

\ j r -

-V

/

\

OPO

)--{

OPl

)--{

OP2

)--{

OP3

}--r-

07-00

/

\

(OP1)

I

)--{

(OP1)

)--~

(OP3)

)--~

(OP3)

)--r-

I

I

-

WRITE

I

WRITE WRITE ~

LONG-WORD OPERAND WRITE TO 8-BIT BUS

Figure 3-4. Long-Word Write Operand Timing to 8-Bit Port

MOTOROLA


3.2.3.7 LONG-WORD OPERAND TO 16-81T PORT, ALIGNED.

Figure 3-5 shows both long-word and word read and write timing to a 16-bit port.

LONG·WORD OPERANDI OPO

31

I

OP1

I

OP2

I

OP3

I t

23 t

15 7 0

DATA BUS

015 08 07 DO

SIZ1 SIZO

CYCLE 1

CYCLE 2

I

OPO

OP2

OP1

OP3

I

0

1

0

0

AO DSACK1 DSACKO

0

0

0

0

X x

The MC68340 drives the address bus with the desired address and drives the size pins to indicate a long-word operand. For a read operation, the slave responds by placing the two most significant bytes of the operand on bits 15-0 of the data bus and asserting DSACK1 to indicate a 16-bit port. The MC68340 reads the two most significant bytes of the operand (bytes 0 and 1) from bits

15-0. The MC68340 then decrements the transfer size counter, increments the address, initiates a new cycle, and reads bytes 2 and 3 of the operand from bits 15-0 of the data bus.

For a write operation, the MC68340 drives the two most significant bytes of the operand on bits 15-0 of the data bus. The slave device then reads the two most significant bytes of the operand (bytes 0 and 1) from bits 15-0 of the data bus and asserts DSACK1 to indicate data reception and a 16-bit port. The

MC68340 then decrements the transfer size counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits 15-0 of the data bus.

3.2.4 Bus Operation

The MC68340 bus is asynchronous, allowing external devices connected to the bus to operate at clock frequencies different from the clock for the MC68340.

Bus operation uses the handshake lines (AS, DS, DSACK1, DSACKO, BERR, and

HALT) to control data transfers. AS signals a valid address on the address bus, and DS is used as a condition for valid data on a write cycle. Decoding the size outputs and lower address line AO provides strobes that select the active portion of the data bus. The slave device (memory or peripheral) responds by placing the requested data on the correct portion of the data bus for a read cycle or by latching the data on a write cycle; the slave asserts the DSACK1/DSACKO combination that corresponds to the port size to terminate the cycle. Alternatively, the SIM can be programmed to assert the DSACK1/DSACKO combination internally and respond forthe slave. If no slave responds orthe access is invalid, external control logic may assert BERR or BERR and HALT to abort or retry the

3-14 MOTOROLA


CLKOUT

A31-AO

FC3-FCO

.~

SO

.rL

IL

S4 SO S2 S4 so

S2 S4 SO S2 S4 so

S2 S4 SO S2

S4 nrL

IL ru

IL n-

IL n-

IL n-

IL

L L

L n-

IL r--

~

S2

~ ~ ~ ~ x

K

~ ~ ~ K

X

K

II

/

\

I

r\

I

r\

/ r\

j

r\

/

~

I

~

SIZO

SIZl

'1\

/

1\

/

1\

/ \ ~ \

~

\

J

,

1\

2 BYTES 2 BYTES

4 BYTES

2 BYTES 2 BYTES

1\

4 BYTES

1\

V

V

~

If f\.

015-08

07-00

II

r--

I\

V

n

I--

V-

h

~

~

VOPi' fC.:I

I - - -

1/1\

Ir--""I r-K

OPO

VI\

V-I\

V

L>-K

OP2

I)--K

OPO

[}-

~

~

VOP3'

[\.:.:..:I

~

I--K

OPl

I

l)-K

OP3

I

I)-K

OPl

I

1)-

-

LONG-WORD READ

...

, WORD READ ....

" . LONG-WORD WRITE TO

....

.-

WORD

WRITETO~

FROM 16 BIT BUS

FROM 16-BIT BUS

....

16 BIT BUS

16 BIT BUS

Figure 3-5. Long-Word and Word Read and Write Timing 16-Bit Port bus cycle, respectively, DSACKx can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACKx may precede data must not exceed a specified value in any asynchronous system to ensure that valid data is latched into the MC68340. (See MC68340/D, MC68340 Tech-

nical Summary

for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACKx. Although the MC68340 can transfer data in a minimum of three clock cycleswhen the cycle is terminated with DSACKx, the MC68340 inserts wait cycles in clock-period increments until DSACKx is recognized. BERR and/or HALT can be asserted after DSACK

MOTOROLA


3-15

is asserted. BERR and/or HALT must be asserted within the time specified after

DSACKx is asserted in any asynchronous system. If this maximum delay time is violated, the MC68340 may exhibit erratic behavior.

3.2.5 Synchronous Operation with DSACKx

Although cycles terminated with DSACKx are classified as asynchronous, cycles terminated with DSACKx can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these cycles must synchronize the response to the MC68340 clock (CLKOUT) to be synchronous.

Since the devices terminate bus cycles with DSACKx, the dynamic bus sizing capabilities of the MC68340 are available. The minimum cycle time for these cycles is also three clocks. To support systems that use the system clock to generate DSACKx and other asynchronous inputs, the asynchronous input setup time and the asynchronous input hold time are given. If the setup and

~old times are met for the assertion or negation of a signal, such as DSACKx, the

MC68340 is guaranteed to recognize that signal level on that specific falling edge of the system clock. If the assertion of DSACKx is recognized on a particular falling edge of the clock, valid data is latched into the MC68340 (for a read cycle) on the next falling clock edge if the data meets the data setup time.

In this case, the parameter for asynchronous operation can be ignored. The timing parameters are described in MC68340/D, MC68340 Technical Summary.

If a system asserts DSACKx for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACKx (and/or BERR/

HALT) until and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles terminated with DSACKx (three clocks per cycle). When BERR (or BERR and HALT) is asserted after DSACKx, BERR

(and HALT) must meet the appropriate setup time prior to the falling clock edge one clock cycle after DSACKx is recognized. This setup time is critical, and the

MC68340 may exhibit erratic behavior if it is violated. When operating synchronously, the data-in setup and hold times for synchronous cycles may be used instead of the timing requirements for data relative to DS.

3.2.6 Fast-Termination Cycles

With an external device that has a fast access time, the chip-select circuit fasttermination enable (FTE) can provide a two-clock external bus transfer. Since the chip-select circuits are driven from the system clock, the bus cycle termination is inherently synchronized with the system clock. When fast termination is selected, the DD and PS bits of the corresponding address mask register are

3-16


overridden. Fast termination can only be used with a 16-bit port and zero wait states. To use the fast-termination option, an external device should be fast enough to have data ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the OSACKx timing for two wait states in read and a fast-termination read and write. When using the fast-termination option, OS is asserted only in a read cycle, not in a write cycle.

Refer to

SECTION

4

SYSTEM INTEGRATION MODULE

for more information on chip selects.

CLKOUT

AS

SO S1 S2 S3 SW SW *sw sw *S4 S5 so S1. S4 S5 so S1 S4 S5 so

D15-DO

TWO WAlT STATES IN READ -~E--FAST- ~-++-

TERMINATION

READ

*

DSACKx only internally asserted for fast-termination cycles.

Figure 3-6. Fast-Termination Timing

3.3 DATA TRANSFER CYCLES

The transfer of data between the MC68340 and other devices involves the following signals:

• Address Bus A31-AO

• Data Bus 015-00

• Control Signals

The address and data buses are both parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for deskewing all signals it issues at both the


start and end of the cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave devices. The following paragraphs define read, write, and read-modify-write cycle operations. Each bus cycle is defined as a succession of states that apply to the bus operation.

These states are different from the MC68340 states described for the CPU32.

The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states.

3.3.1 Read Cycle

During a read cycle, the MC68340 receives data from a memory or peripheral device. If the instruction specifies a long-word or word operation, the MC68340 attempts to read two bytes at once. For a byte operation, the MC68340 reads one byte. The section of the data bus from which each byte is read depends on the operand size, address signal AO, and the port size. Refer to 3.2.1 Dynamic

Bus Sizing and 3.2.2 Misaligned Operands for more information. Figure 3-7 is a flowchart of a word read cycle.

SLAVE BUS MASTER

ADDRESS DEVICE

1. SET

RiWTO

READ

2. DRIVE ADDRESS ON A31-AO

3. DRIVE FUNCTION CODE ON FC3-FCO

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT

AS

AND

Os

ACQUIRE DATA

1. LATCH DATA

2. NEGATE

AS

AND

os

t

START NEXT CYCLE

PRESENT DATA

1. DECODE ADDRESS

2. PLACE OAT A ON 01 rHlO

3. DRIVE DSACKx SIGNALS

TERMINATE CYCLE

1. REMOVE DATA FROM D1rHlO

2. NEGATE DSACKx

Figure 3-7. Word Read Cycle Flowchart


MOTOROLA

3-18

State 0 The read cycle starts in state 0 (SO). During SO, the MC68340 places a valid address on A31-AO and valid function codes on FC3-FCO. The function codes select the address space for the cycle. The MC68340 drives

R/W

high for a read cycle. SIZ1 and SIZO become valid, indicating the number of bytes requested for transfer.

State 1 - One-half clock later, in state 1 (S1), the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during

S1. The selected device uses RIW, SIZ1 or SIZO, AO, and OS to place its information on the data bus. One or both of the bytes (D15-08 and D7-DO) are selected by SIZ1, SIZO, and AO. Concurrently, the selected device asserts

DSACKx.

State 2 As long as at least one of the DSACKx signals is recognized on the falling edge of S2 (meeting the asynchronous input setup time requirement), data is latched on the falling edge of S4, and the cycle terminates.

State 3 If DSACKx is not recognized by the start of state 3 (S3), the MC68340 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACKx on the falling edges of the clock until one is recognized.

State 4 At the falling edge of state 4 (S4), the MC68340 latches the incoming data and samples DSACKx to get the port size.

State 5 The MC68340 negates AS and DS during state 5 (S5). It holds the address valid during S5 to provide address hold time for memory systems.

RIW, SIZ1, SIZO, and FC3-FCO also remain valid throughout S5. The external device keeps its data and OSACKx signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACKx within approximately one clock period after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.

3.3.2

Write Cycle

During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure 3-8 is a flowchart of a write cycle operation for a word transfer.


3-20

State 0 The write cycle starts in SO. During SO, the MC68340 places a valid address on A31-AO and valid function codes on FC3-FCO. The function codes select the address space for the cycle. The MC68340 drives RIW low for a write cycle. SIZ1 and SIZO become valid, indicating the number of bytes to be transferred.

State 1 One-half clock later, in S1, the MC68340 asserts AS, indicating a valid address on the address bus.

State 2 During S2, the MC68340 places the data to be written onto D15-DO and samples DSACKx at the end of S2.

State 3 The MC68340 asserts DS during S3, indicating that data is stable on the data bus. As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and Sp. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACKx on the falling edges of the clock until one is recognized.

The selected device uses RIW, SIZ1, SIZO, and AO to latch data from the appropriate byte(s) of D15-D8 and D7-DO. SIZ1, SIZO, and AO select the

BUS MASTER

ADDRESS DEVICE

1. SET FWlTO WRITE

2. DRIVE ADDRESS ON A31-AO

3. DRIVE FUNCTION CODE ON FC3-FCO

4. DRIVE SIZE PINS FOR OPERAND SIZE

5. ASSERT

AS

6. PLACE DATA ON D15-DO

7. ASSERTD'S

TERMINATE OUTPUT TRANSFER

1.

NEGATE os

AND

AS

2. REMOVE DATA FROM D15-DO

~

START NEXT CYCLE

SLAVE

ACCEPT DATA

1. DECODE ADDRESS

2. LATCH DATA FROM D15-DO

3. ASSERT DSACKx SIGNALS

TERMINATE CYCLE

1.

NEGATE DSACKx

Figure 3-8. Write Cycle Flowchart


bytes of the data bus. If it has not already done so, the device asserts

DSACKx to signal that it has successfully stored the data.

State 4 The MC68340 issues no new control signals during S4.

State 5 The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems.

RIW, Sill, SilO, and FC3-FCO also remain valid throughout S5. The external device must keep DSACKx asserted until it detects the negation of AS or

DS (whichever it detects first). The device must negate DSACKx within approximately one clock period after sensing the negation of AS or DS.

DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle.

3.3.3

Read-Modify-Write Cycle

The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the

MC68340, this operation is indivisible, providing semaphore capabilities for multiprocessor systems. During the entire read-modify-write sequence, the

MC68340 asserts RMC to indicate that an indivisible operation is occurring. The

MC68340 does not issue a bus grant (BG) signal in response to a bus request

(BR) signal during this operation. Figure 3-9 is an example of a functional timing diagram of a read-modify-write instruction specified in terms of clock periods.

State 0 - The MC68340 asserts RMC in SO to identify a read-modify-write cycle.

The MC68340 places a valid address on A31-AO and valid function codes on FC3-FCO. The function codes select the address space for the operation.

Sill and SilO become valid in SO to indicate the operand size. The MC68340 drives RIW high for the read cycle.

State 1 One-half clock later, in Sl, the MC68340 asserts AS indicating a valid address on the address bus. The MC68340 also asserts DS during S1.

State 2 The selected device uses RIW, Sill, SilO, AO, and DS to place information on the data bus. Either or both ofthe bytes (D15-D8 and D7-DO) are selected by Sill, SilO, and AO. Concurrently, the selected device may assert DSACKx.

State 3 As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates.

If DSACKx is not recognized by the start of S3, the MC68340 inserts wait

MOTOROLA


3-22

Figure 3-9. Read-Modify-Write Cycle Timing states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACKx on the falling edges of the clock until one is recognized.

State 4 At the end of S4, the MC68340 latches the incoming data.

State 5 The MC68340 negates AS and DS during S5. If more than one read cycle is required to read in the operand(s), SO-S5 are repeated for each read cycle. When finished reading, the MC68340 holds the address, RIW, and FC3-FCO valid in preparation for the write portion of the cycle. The external device keeps its data and DSACKx signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACKx within approximately one clock period


after sensing the negation of AS or DS. DSACKx signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation.

Idle States The MC68340 does not assert any new control signals during the idle states, but it may internally begin the modify portion of the cycle at this time. SO-S5 are omitted if no write cycle is required. If a write cycle is required, RIW remains in the read mode until SO to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S2.

State 0 The MC68340 drives RIW low for a write cycle. Depending on the write operation to be performed, the address lines may change during SO.

State 1 In S1, the MC68340 asserts AS, indicating a valid address on the address bus.

State 2 During S2, the MC68340 places the data to be written onto D15-DO.

State 3 The MC68340 asserts DS during S3, indicating stable data on the data bus. As long as at least one of the DSACKx signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACKx is not recognized by the start of S3, the MC68340 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the MC68340 continues to sample DSACKx on the falling edges of the clock until one is recognized.

The selected device uses

R/W,

DS, Sll1, SilO, and AO to latch data from the appropriate section(s) of D15-D8 and D7-DO. Sll1, SilO, and AO select the data bus sections. If it has not already done so, the device asserts

DSACKx when it has successfully stored the data.

State 4 The MC68340 issues no new control signals during S4.

State 5 The MC68340 negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems.

RIW and FC3-FCO also remain valid throughout S5. If more than one write cycle is required, states SO-S5 are repeated for each write cycle. The external device keeps DSACKx asserted until it detects the negation of AS or

OS

(whichever it detects first). The device must remove its data and negate

DSACKx within approximately one clock period after sensing the negation of AS or DS.

MOTOROLA


3.4 CPU SPACE CYCLES

FC3-FCO select user and supervisor program and data areas. The area selected by function code FC3-FCO

=

$7 is classified as the CPU space. The breakpoint acknowledge, LPSTOP broadcast, module base address register access, and interrupt acknowledge cycles described in the following paragraphs use CPU space. The CPU space type, which is encoded on A 19-A 16 during a CPU space operation, indicates the function that the MC68340 is performing. On the

MC68340, four of the encodings are implemented as shown in Figure 3-10. All unused values are reserved by Motorola for additional CPU space types.

3-24


performs illegal instruction exception processing. If the bus cycle is terminated by OSACKx, the MC68340 uses the data on 015-00 (for 16-bit ports) or two reads from 015-08 (for 8-bit ports) to replace the BKPT instruction in the internal instruction pipeline and then begins execution of that instruction.

When the CPU32 acknowledges breakpoint pin assertion with background mode disabled, the CPU32 performs a word read from CPU space, type 0, at an address corresponding to all ones on A4-A2 (BKPT#7), and the T-bit (A1) set. If this bus cycle is terminated by BERR, the MC68340 performs hardware breakpoint exception processing. If this bus cycle is terminated by OSACKx, the MC68340 ignores data on the data bus and continues execution of the next instruction.

NOTE

The BKPT pin is sampled on the same clock phase as data and is latched with data as it enters the CPU32 pipeline. If BKPT is asserted for only one bus cycle and a pipeline flush occurs before BKPT is detected by the CPU32, BKPT is ignored. To ensure detection of BKPT by the CPU32,

BKPT can be asserted until a breakpoint acknowledge cycle is recognized.

The breakpoint operation flowchart is shown in Figure 3-11. Figures 3-12 and

3-13 show the timing diagrams for the breakpoint acknowledge cycle with instruction opcodes supplied on the cycle and with an exception signaled, respectively.

3.4.2

LPSTOP

Broadcast Cycle

The LPSTOP broadcast cycle is generated by the CPU32 executing the LPSTOP instruction. The external bus interface must get a copy of the interrupt mask level from the CPU32, so the CPU32 performs a CPU space type 3 write with the mask level encoded on the data bus, as shown in the following figure. The

CPU space type 3 cycle is shown externally, if the bus is available, to indicate to external devices that the MC68340 is going into low-power stop mode. The

SIM provides OSACKx response to this cycle. A complete description of how the SIM responds to low-power stop mode is included in SECTION 4 SYSTEM

INTEGRATION MODULE.

15 14 13 12 11 10

RESET: o o

0

4

12 o

I

11

I

10

MOTOROLA


3-26

EXTERNAL DEVICE BREAKPOINT OPERATION FLOW

PROCESSOR

ACKNOWLEDGE BREAKPOINT

IF BREAKPOINT INSTRUCTION EXECUTED:

1. SET

Rfii

TO READ

2. SET FUNCTION CODE TO CPU SPACE

3. PLACE CPU SPACE TYPE 0 ON A19-A16

4. PLACE BREAKPOINT NUMBER ON A2-A4

5. CLEART-BIT (A1)

6. SET SIZE TO WORD

7. ASSERT

AS

AND

OS

IF BKPT PIN ASSERTED:

1. SET RtWTO READ

2. SET FUNCTION CODE TO CPU SPACE

3. PLACE CPU SPACE TYPE 0 ON A19-A16

4. PLACE ALL ONE'S ON A4-A2

5. SETT-BIT (A-1) TO ONE

6. SET SIZE TO WORD

7. ASSERT /is AND

OS"

IF BEAKPOINT INSTRUCTION EXECUTED AND

DSACKx IS ASSERTED:

1. LATCH DATA

2. NEGATE

AS

AND

OS

3. GO TO (A)

IF BKPT PIN ASSERTED AND DSACKx IS ASSERTED:

1. NEGATE

AS

AND OS

2. GO TO (A)

IFBERR ASSERTED:

1.

NEGATE

AS

AND OS

2. GOTO(B)

(A) (B)

I

I,


1. PLACE LATCHED DATA IN INSTRUCTION PIPEUNE

2.

CONTINUE PROCESSING


1. CONTINUE PROCESSING

J

"'

,.


....

1. PLACE REPLACEMENT OPCODE ON DATA BUS

2. ASSERT DSACKx

-OR-

1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING


1. ASSERT DSACKx

-OR-

1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING

1.

NEGATE DSACKx or

BERR


1. INITIATE ILLEGAL INSTRUCTION PROCESSING


1.

INITIATE HARDWARE BREAKPOINT PROCESSING

J

"'

Figure 3-11. Breakpoint Operation Flowchart


MOTOROLA

so

S1 S2 S3 S4 S5 SO S1 S2 53 S4 S5 SO S1 S2 S3 S4 S5 SO

CLKOUT

A31-A20

~'--

_ _ _ _ _

~

A1S-A16

~'--

_ _ _ _ _

A4-A1

~

~

(~

~

BREAKPOINT NUMBEM-BW

FC3-FCO

~

SIZO

~

SIZ1

~

~

~

\

~

CPU SPACE

~

~

\

'"

r=

c=

\

~

\

~

'::r=

/

L

DS

'"

DSACKx

~

D~OO

D15-D8

- - - - - - - 4

CJ q

\

BERR

J

'"

HALT

J

'"

C

1 -

BREAKPOINT

----:l~E---

OCCURS

>1<

READ

'"

'\

7

'\

>1

\

7\ c=r.

CP

\

BREAKPOINT

">

ACKNOWLEDGE

INSTRUCTION WORD FETCH

\

7\

~

~

\

\

'"

Figure 3-12. Breakpoint Acknowledge Cycle Timing (Opcode Returned)

MOTOROLA


3-27

3-28 so

51 52 53 54 55 SO 51 52 53 54 55 SO 51 52 53 54 55 SO

CLKOUT

A31-A20

~""--

_ _ _ _ _

~

A19-A16

~

A4-A1

~

~

(~

~

BREAKPOINT NUMBEM-BD

51ZO

~I....-

51Z1

~

\

~

~

~

\

~

CPU5PACE

~

~

\ c=

C

\

~

~

\

":J:= c=

\

L

\

OS~~

07-00

015-08 q

':J

q

\

BERR

J

HAlT

J

\

BKPT

\ \

C

L--

,-OCCURS

~I«

\

READ

\

1\

\

CJ.

~

\

\

7

\

~I«

BREAKPOINT

ACKNOWLEDGE

BUS ERROR ASSERTED

\

\

7\

~

~

LJ

\

Figure 3-13. Breakpoint Acknowledge Cycle Timing (Exception Signaled)

MOTOROLA


3.4.3 Module Base Address Register Access

All internal module registers, including the SIM, occupy a single 4K-byte memory block that is relocatable along 4K-byte boundaries. The location is fixed by writing the desired base address of the SIM block to the module base address register using the MOVES instruction. The module base address register is only accessible in CPU32 space at address $03FFOO. Refer to

SECTION

4

SYSTEM

INTEGRATION MODULE

for additional information on the module base address register.

3.4.4 Interrupt Acknowledge Bus Cycles

The CPU32 makes an interrupt pending in three cases. The first case occurs when a peripheral device signals the CPU32 (with the IRQ7-IRQ1 signals) that the device requires service and the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register.

The second case occurs when a transition has occurred in the case of a level

7 interrupt. A recognized level 7 interrupt must be removed for one clock cycle before a second level 7 can be recognized. The third case occurs if, upon return from servicing a level 7 interrupt, the request level stays at 7 and the processor mask level changes from 7 to a lower level, a second level 7 is recognized. The

CPU32 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing.

3.4.4.1 INTERRUPT ACKNOWLEDGE CYCLE - TERMINATED NORMALLY.

When the CPU32 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in

3.4.4.2 AUTOVECTOR INTERRUPT

ACKNOWLEDGE CYCLE.


The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 3.3.1 Read Cycle in that it accesses the CPU address space.

Specifically, the differences are as follows:

1. FC3-FCO are set to seven (FC3/FC2/FC1/FCO

=

0111) for CPU address space.

2. A3, A2, and A 1 are set to the interrupt request level, and the IACKx strobe corresponding to the current interrupt level is asserted. (Either the function codes and address signals or the IACKx strobes can be monitored to determine that an interrupt acknowledge cycle is in progress and the current interrupt level.)

3. The CPU space type field (A 19-A 16) is set to $F, the interrupt acknowledge code.

4. Other address signals (A31-A20, A15-A4, and AO) are set to one.

5. The SIZO, SIZ1, and

R/W

signals are driven to indicate a single-byte read cycle. The responding device places the vector number on the least significant byte of the its data port (for an 8-bit port, the vector number must be on 015-08; for a 16-bit port, the vector must be on 07-00) during the interrupt acknowledge cycle. Beyond this, the cycle is terminated normally with OSACKx.

Figure 3-14 is a flowchart of the interrupt acknowledge cycle; Figure 3-15 shows the timing for an interrupt acknowledge cycle terminated with OSACKx.

3.4.4.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting device cannot supply a vector number, it requests an automatically generated vector (autovector). Instead of placing a vector number on the data bus and asserting OSACKx, the device asserts AVEC to terminate the cycle. The

OSACKx signals may not be asserted during an interrupt acknowledge cycle terminated by AVEC. The vector number supplied in an autovector operation is derived from the interrupt level of the current interrupt. When AVEC is asserted instead of OSACKx during an interrupt acknowledge cycle, the MC68340 ignores the state of the data bus and internally generates the vector number

(the sum of the interrupt level plus 24 ($18)).

AVEC is multiplexed with CSO, controlled by the FIRQ bit in the SIM MCR (refer to SECTION 4 SYSTEM INTEGRATION MODULE for additional information).

AVEC is only sampled during an interrupt acknowledge cycle. Ouring all other cycles, AVEC is ignored. Additionally, AVEC can be internally generated for external devices by programming the autovector register. Seven distinct autovectors can be used, corresponding to the seven levels of interrupt available with signals IRQ7-IRQ1. Figure 3-16 shows the timing for an autovector operation.


MOTOROLA

INTERRUPTING DEVICE

REQUEST INTERRUPT

PROVIDE VECTOR NUMBER

1. PLACE VECTOR NUMBER ON LEAST

SIGNIFICANT BYTE OF DATA BUS

2. ASSERT DSACKx (OR AVEC IF NO VECTOR

NUMBER)

1. NEGATE DSACKx

RELEASE

I

.,

-

MC68332

GRANT INTERRUPT

1. SYNCHRONIZE IRQ1-1RQ7

2. COMPARE IRQHRQ7 TO MASK LEVEL AND

WAIT FOR INSTRUCTION TO COMPLETE

3. PLACE INTERRUPT LEVEL ON A3-A1;

TYPE FIELD (A19-A16)

=

$F

4. SET

RIW

TO READ

5. SET FC3-FCO TO 0111

6. DRIVE SIZE PINS TO INDICATE A ONE-BYTE

TRANSFER

7. ASSERT

AS

AND

OS

.,

"'

ACQUIRE VECTOR NUMBER

1. LATCH VECTOR NUMBER

2. NEGATE

OS

AND

AS

_

...

START NEXT CYCLE

Figure 3-14. Interrupt Acknowledge Cycle Flowchart

3.4.4.3 SPURIOUS INTERRUPT CYCLE. Requested interrupts, whether internal or external, are arbitrated internally. When no internal module (including the SIM, which responds for external requests) responds during an interrupt acknowledge cycle by arbitrating for the interrupt acknowledge cycle internally, the spurious interrupt monitor generates an internal bus error signal to terminate the vector acquisition. The MC68340 automatically generates the spurious interrupt vector number, 24, instead of the interrupt vector number in this case.

When an external device does not respond to an interrupt acknowledge cycle with AVEC or DSACKx, a bus monitor must assert BERR, which results in the

CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68340 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector.

MOTOROLA


3-32

CLKOUT

A31-A4

A3-A1

AO

FC3-FCO

51Z0

51Z1 so

52 54 SO

521 522 523 524 51 52 54 r--

-rL rL rL

-

-[X

V

J.

~

·

50 52 u-u-

u-u-l rL

rL

1\

-

-[X

~

INTERRUPT LEVEL

-"

·

~

-

-[X

V

1\

-

-[X

~

( PU5PACE

D<

"

-

-~

V

r\

1 BYTE

1/

-

-~

~

,

J.

-V

-r\

-t-

\ r-----

-r\

-t-

07-00

015-08

-V

\ r---\

"---I

'/ r---\

"---'

\

VECTOR FROM 16-BIT PORT

I

/

-"

-"

~

VECTOR

I

FROM 8-BIT PORT

-"

"-

~

\

-"

·

/

'

J

\

~~it&~ f-E--WRITE

5TACK lACK CYCLE

Figure 3-15. Interrupt Acknowledge Cycle Timing


MOTOROLA

CLKOUT

A31-A4

A3-A1

AO so

S2

S4 so

S21 S22 S23 S24 Sl S2 S4

-rL

-

-rx

-

-D(

~

-

/

X

ULJL

INTERRUPT LEVEL

>-

,

. so

S2

~

\

X

,

-

-l>(

/

\

FC3-FCO

SIZO

SIZl

-

-D(

-

-X

-

-X

_I

X

/

~

CPU SPACE

1 BYTE

J,.

X

1\

V

- \

\

-

- \

J,.

"

_I

\ / L.

015-00 r--\.

1'----1

\

/

"

,,'

\

~~it3:~ ~~~f:T16~

\ lACK

C CLE

111'iL

'/

/ '

Figure 3-16. Autovector Operation Timing

MOTOROLA


3-33

3.5

BUS EXCEPTION CONTROL CYCLES

The bus architecture requires assertion of DSACKx from an external device to signal that a bus cycle is complete. Neither DSACKx nor AVEC is not asserted in the following cases:

• DSACKx/AVEC is programmed to respond internally.

• The external device does not respond.

• Various other application-dependent errors occur.

The MC68340 provides BERR when no device responds by asserting DSACKxl

AVEC within an appropriate period of time after the MC68340 asserts AS. This mechanism allows the cycle to terminate and the MC68340 to enter exception processing for the error condition. HALT is also used for bus exception control.

This signal can be asserted by an external device for debugging purposes to cause single bus cycle operation or, in combination with BERR, a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACKx, BERR, and HALT can be asserted and negated with the rising edge of the MC68340 clock. This precaution assures that when two signals are asserted simultaneously, the required setup and hold time for both is met for the same falling edge of the MC68340 clock. This or an equivalent precaution should be designed into the external circuitry to provide these signals. Alternatively, the internal bus monitor could be used. The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to

DSACKx assertion as follows (case numbers refer to Table 3-4):

Normal Termination DSACKx is asserted; BERR and HALT remain negated

(case 1).

Halt Termination HALT is asserted at the same time or' before DSACKx, and BERR remains negated (case 2).

Bus Error Termination BERR is asserted in lieu of, at the same time, or before DSACKx (case 3) or after DSACKx (case 4), and

HALT remains negated; BERR is negated at the same time or after DSACKx.

Retry Termination -

HALT and BERR are asserted in lieu of, at the same time, or before DSACKx (case 5) or after DSACKx (case 6); BERR is negated at the same time or after DSACKx, and HALT may be negated at the same time or after BERR.

Table 3-4 shows various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and

HALT should be negated according to the specifications in the MC68340/D,


DSACKx, BERR, and HALT may be negated after


AS. If DSACKx or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely.

Table 3-4. DSACKx, BERR, and HALT Assertion Results

Case

Num.

1

2

3

4

5

6

Control

Signal

DSACKx

BERR

HALT

DSACKx

BERR

HALT

DSACKx

BERR

HALT

DSACKx

BERR

HALT

DSACKx

BERR

HALT

DSACKx

BERR

HALT

Asserted on Rising

Edge of State

N N+2

A

NA

NA

S

NA

X

A

NA

AJS

NAJA

A

NA

A

NA

NA

NAJA

A

AJS

A

NA

NA

S

NA

S

X

S

X

X

A

NA

X

S

S

X

A

A

Normal cycle terminate and halt; continue when HALT negated

Terminate and take bus error exception, possibly deferred.

Terminate and take bus error exception, possibly deferred.

Result

Normal cycle terminate and continue.

Terminate and retry when HALT negated.

Terminate and retry when HALT negated.

NOTE:

N- The number of current even bus state (e.g., S2, S4, etc.)

A-Signal is asserted in this bus state

NA-Signal is not asserted in this state

X-Don't care

S-Signal was asserted in previous state and remains asserted in this state

EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3).

EXAMPLE B: A system uses error detection and correction on RAM contents.

The designer may:

1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to indicate to the MC68340 to automatically retry the error cycle

(case 5) or, if data is valid, assert DSACKx (case 1).

2. Delay DSACKx until data is verified and assert BERR with or without

DSACKx if data is in error (case 3). This initiates exception processing for software handling of the condition.

3. Return DSACKx priorto data verification; if data is invalid, BERR is asserted on the next clock cycle (case 4). This initiates exception processing for software handling of the condition.

MOTOROLA


4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry.

3.5.1 Bus Errors

BERR can be used to abort the bus cycle and the instruction being executed.

BERR takes precedence over DSACKx provided it meets the timing constraints described in

MC68340/D, MC68340 Technical Summary.

If BERR does not meet these constraints, it may cause unpredictable operation ofthe MC68340. If BERR remains asserted into the next bus cycle, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the MC68340 may enter exception processing immediately following the bus cycle, or it may defer processing the exception.

The instruction prefetch mechanism requests instruction words from the bus controller before it is ready to execute them. If a bus error occurs on an instruction fetch, the MC68340 does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. The bus error condition is recognized during a bus cycle in any of the following cases:

• DSACKx and HALT are negated, and

BERR is asserted.

• HALT and BERR are negated, and DSACKx is asserted. BERR is then asserted within one clock cycle (HALT remains negated).

• BERR and HALT are asserted together, indicating a retry.

When the MC68340 recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 3-17 shows the timing of a bus error for the case in which DSACKx is not asserted. Figure 3-18 shows the timing for a bus error that is asserted after DSACKx. Exceptions are taken in both cases.

(Refer to SECTION 5 CPU32 for details of bus error exception processing.)

In the second case, in which BERR is asserted after DSACKx is asserted, BERR must be asserted within the time specified for purely asynchronous operation, or it must be asserted and remain stable during the sample window around the next falling edge of the clock after DSACKx is recognized. If BERR is not stable at this time, the MC68340 may exhibit erratic behavior. BERR has priority over DSACKx. In this case, data may be present on the bus but may not be valid. This sequence can be used by systems that have memory error detection and correction logic and by external cache memories.

3-36


MOTOROLA

A5

OS

D5ACKx

015-00

BERR

CLKOUT so

52 5W 5W 54

A31-AO

FC3-FCO

Rfjj

50 52

54

READ CYCLE WITH BUS

-~~INTERNAL

ERROR PROCESSING

Figure 3-17. Bus Error without DSACKx

3.5.2 Retry Operation

When both BERR and HALT are asserted by an external device during a bus cycle, the MC68340 enters the retry sequence shown in Figure 3-19. A delayed retry, which is similar to the delayed bus error signal described previously, can also occur (see Figure 3-20). The MC68340 terminates the bus cycle, places the control signals in their inactive state, and does not begin another bus cycle until the BERR and HALT signals are negated by external logic. After a synchronization delay, the MC68340 retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before 52 of the retried cycle to ensure correct operation of the retried cycle.

The MC68340 retries any read or write cycle of a read-modify-write operation separately; RMC remains asserted during the entire retry sequence. Asserting

BR along with BERR and HALT provides a relinquish and retry operation. The

MC68340 does not relinquish the bus during a read-modify-write operation.

Any device that requires the MC68340 to give up the bus and retry a bus cycle during a read-modify-write cycle must assert BERR and BR only (HALT must

MOTOROLA


3-37

CLKOUT so

S2 S4

A31-AO

FC3-FCO so

S2 S4

015-00

-t---t<

-~~INTERNAL~E-

PROCESSING

Figure 3-18. Late Bus Error with DSACKx not be included). The bus error handler software should examine the readmodify-write bit in the special status word (refer to SECTION 5 CPU32) and take the appropriate action to resolve this type of fault when it occurs.

3.5.3 Halt Operation

When HALT is asserted and BERR is not asserted, the MC68340 halts external bus activity at the next bus cycle boundary (see Figure 3-21 ). HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. HALT affects external bus cycles only; thus, a program that does not require use of the external bus may continue executing. The singlecycle mode allows the user to proceed through (and debug) external MC68340 operations, one bus cycle at a time. Since the occurrence of a bus error while

HALT is asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow.

3-38


MOTOROLA

When the MC68340 completes a bus cycle with HALT asserted, D15-DO is placed in the high-impedance state, and bus control signals are driven inactive (not high-impedance state); the address, function code, size, and read/write signals remain in the same state. The halt operation has no effect on bus arbitration

(refer to 3.6 BUS ARBITRATION). When bus arbitration occurs while the MC68340 is halted, the address and control signals are also placed in the high-impedance state. Once bus mastership is returned to the MC68340, if HALT is still asserted, the address, function code, size, and read/write signals are again driven to their previous states. The MC68340 does not service interrupt requests while it is halted.

CLKOUT

A31-AO

FC3-FCO

ANi

As

Os

DSACKx

015-00

BERR

HALT so

S2 SW SW 54 so

S2

54

CYCLE WITH --~:-HALT-;Jo~READ RERUN

RETRY

Figure 3-19. Retry Sequence

MOTOROLA


CLKOUT so

S2 54

A31-A30

FC3-FCO

Rfii

AS os

OSACKx

015-010

BERR

HALT

SO S2 54

-~E--HALT-l~--~~~

Figure 3-20. Late Retry Sequence

3.5.4 Double Bus Fault

A double bus fault results when a bus error or an address error occurs during the exception processing sequence for any of the following:

• A previous bus error

• A previous address error

• A reset

For example, the MC68340 attempts to stack several words containing information about the state of the machine while processing a bus error exception.

If a bus error exception occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the MC68340 halts and drives the HALT line low. Only a reset operation can restart a halted

MC68340. However, bus arbitration can still occur (refer to 3.6 BUS ARBITRA-

TION). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine, or later) does not cause a double bus fault. A bus cycle that is retried does not


constitute a bus error or contribute to a double bus fault. The MC68340 continues to retry the same bus cycle as long as the external hardware requests it.

Reset can also be generated internally by the double bus fault monitor (see

SECTION 5 CPU32).

CLKOUT

A31-AO

FC3-FCO

Rfjj

AS os

DSACKx

015--010

HALT

BR

BG

BGACK

SO

S2

54

READ

J-1_ so

S2 54 so

~-

--~

HALT

(ARBITRATION PERMIITED

WHILE THE PROCESSOR IS

HALTED)

Figure

3-21.

HALT

Timing

READ

MOTOROLA


3-41

3.6

BUS ARBITRATION

The bus design of the MC68340 provides for a single bus master at anyone time, either the MC68340 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus, but not the MC68340 internal bus. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the

MC68340 manages the bus arbitration signals so that the MC68340 has the lowest priority. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in the following paragraphs.

Systems that include several devices that can become bus master require external circuitry to assign priorities to the devices, so that, when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. The sequence of the protocol is as follows:

1. An external device asserts BR.

2. The MC68340 asserts BG to indicate that the bus is available.

3. The external device asserts BGACK to indicate that it has assumed bus mastership.

BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR. To guarantee operand coherency, BG is only asserted at the end of an operand transfer. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal.

When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. When it assumes bus mastership, the external device asserts BGACK and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: 1) it must have received BG through the arbitration process, and 2) BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus.

Figure 3-22 is a flowchart showing the detail involved in bus arbitration for a single device. This technique allows processing of bus requests during data transfer cycles.

BR is negated at the time that BGACK is asserted. This type of operation applies to a system consisting of the MC68340 and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, the BR from each device can be wire-ORed to the MC68340. In such a system, more than one bus request could be asserted simultaneously. BG is negated a few clock cycles after the transition of BGACK. However, if bus requests are

3-42


PROCESSOR

GRANT BUS ARBITRATION

1. ASSERTBG

TERMINATE ARBITRATION

1.

NEGATE BG (AND WAlT FOR

BGACK TO BE NEGATED)

,,-

~

REQUESTING DEVICE

REQUEST THE BUS

1. ASSERT BR

ACKNOWLEDGE BUS MASTERSHIP

1.

EXTERNAL ARBITRATION DETERMINES

NEXT BUS MASTER

2. NEXT BUS MASTER WAITS FOR BGACK

TO BE NEGATED

3. NEXT BUS MASTER ASSERTS BGACK

TO BECOME NEW MASTER

4. BUS MASTER NEGATES eJ1

OPERATE AS BUS MASTER

1. PERFORM DATA TRANSFERS (READ AND

WRITE CYCLES) ACCORDING TO THE

SAME RULES THE PROCESSOR USES t

RELEASE BUS MASTERSHIP

1.

NEGATE BGACK

RE-ARBITRATE OR RESUME

PROCESSOR OPERATION

Figure 3-22. Bus Arbitration Flowchart for Single Request still pending after the negation of BG, the MC68340 asserts another BG within a few clock cycles after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished using the bus. The following paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, HALT assertion, and when the CPU32 has halted due to a double bus fault.

3.6.1 Bus Request

External devices capable of becoming bus masters request the bus by asserting

BA. This signal can be wire-ORed to indicate to the MC68340 that some external device requires control of the bus. The MC68340 is effectively at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while the BR is active, the MC68340 remains bus master once BR is negated.

This prevents unnecessary interference with ordinary processing if the arbitra-

MOTOROLA


tion circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership.

3.6.2

Bus Grant

This MC68340 supports operand coherency; thus, if an operand transfer requires multiple bus cycles, the MC68340 does not release the bus until the entire transfer is complete. The assertion of BG is therefore subject to the following constraints:

• The minimum time for BG assertion after BR is asserted depends on internal synchronization (see

MC68340/D, MC68340 Technical Summary).

• During an external operand transfer, the MC68340 does not assert

BG until after the last cycle of the transfer (determined by SIZx and DSACKx).

• During an external operand transfer, the MC68340 does not assert BG as long as RMC is asserted.

• If both show cycle bits are asserted and the CPU32 is making internal accesses, the MC68340 does not assert BG until the CPU32 finishes the internal transfers. Otherwise, the external bus is granted away, and the

CPU32 continues to execute internal bus transfers.

• If the show cycle bits are 10, the MC68340 does not assert BG to an external master.

Externally, the BG signal can be routed through a daisy-chained network or a priority-encoded network. The MC68340 is not affected by the method of arbitration as long as the protocol is obeyed.

3.6.3

Bus Grant Acknowledge

An external device cannot request and be granted the external bus while another device is the active bus master. A device that asserts BGACK remains the bus master until it negates BGACK. BGACK should not be negated until all required bus cycles are completed. Bus mastership is terminated at the negation of BGACK.

Once an external device receives the bus and asserts BGACK, it should negate

BR. If BR remains asserted after BGACK is asserted, the MC68340 assumes that another device is requesting the bus and prepares to issue another BG.


3.6.4 Bus Arbitration Control

The bus arbitration control unit in the MC68340 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68340 are internally synchronized in a maximum of two cycles of the clock. As shown in Figure 3-23, input signals labeled R and A are internally synchronized versions of BR and BGACK, respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the high-impedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic

(active high) regardless of their true active voltage level. The state machine shown in Figure 3-23 does not have a state 1 or state 4.

State changes occur on the next rising edge of the clock after the internal signal is valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the MC68340 immediately following a state change, when bus mastership is returned to the MC68340. State 0, in which G and T are both negated, is the state of the bus arbiter while the MC68340 is bus

master.

Rand

A keep the arbiter in state 0 as long as they are negated. The MC68340 does not allow arbitration of the external bus during the RMC sequence. For the duration of this sequence, the MC68340 ignores the BR input. If mastership of the bus is required during an RMC operation, BERR must be used to abort the

RMC sequence.

3.6.5 Show Cycles

The MC68340 can perform data transfers with its internal modules without using the external bus, but, when debugging, it is desirable to have address and data information appear on the external bus. These external bus cycles, called show cycles, are distinguished by the fact that AS is not asserted externally.

After reset, show cycles are disabled and must be enabled by writing to the

SHEN bits in the module configuration register. When show cycles are disabled, the address bus, function codes, size, and read/write signals continue to reflect internal bus activity. The only differences are that AS and OS are not asserted externally and the external data bus remains in a high-impedance state. The following paragraphs are a state-by-state description of show cycles. Refer to

MC68340/0, MC68340 Technical Summary for specific timing information.

MOTOROLA


3-46

R - BUS REQUEST

A - BUS GRANT ACKNOWLEDGE

B - BUS CYCLE IN PROGRESS

G-BUSGRANT

T - THREE-STATE SIGNAL TO BUS CONTROL

V - BUS AVAILABLE TO BUS CONTROL

Figure 3-23. Bus

Arbitrati~n

State Diagram

MC68340 USER'S MANUAL MOTOROLA

State 0 During state 0, the address and function codes become valid, RIW is driven to indicate a show read or write cycle, and the size pins indicate the number of bytes to transfer. During a read, the addressed peripheral is driving the data bus, and the user must take care to avoid bus conflicts.

State 41 One-half clock cycle later, DS (rather than AS) is asserted to indicate that address information is valid.

State 42 No action occurs in state 2. The bus controller remains in state 2 until the internal read cycle is complete.

State 43 DS is negated to indicate that show data is valid on the next falling edge of system clock. The external data bus drivers are enabled so that data becomes valid on the external bus as soon as it is available on the internal bus.

State 0 The address, function codes, read/write, and size pins change to begin the next cycle. Data from the preceding cycle is valid through state O.

3.7

RESET OPERATION

The MC68340 has reset control logic to determine the cause of reset, synchronize it if necessary, and assert the appropriate reset lines. The reset control logic can independently drive three different lines:

1. EXTRST (external reset) drives the external RESET pin.

2. CLKRST (clock reset) resets the clock module.

3. INTRST (internal reset) goes to all other internal circuits.

Table 3-5 summarizes the result of each reset source. Synchronous reset sources are not asserted until the end of the current bus cycle, whether or not RMC is asserted. The internal bus monitor is automatically enabled for synchronous resets; therefore, if the current bus cycle does not terminate normally, the bus monitor terminates it. Only single-byte or word transfers are guaranteed valid for synchronous resets. Asynchronous reset sources indicate a catastrophic failure, and the reset control logic immediately resets the system.

If an external device drives RESET low, the reset control logic holds reset asserted internally until the external RESET is released. When the reset control logic detects that external RESET is no longer being driven, it drives both internal and external reset low for an additional 512 cycles to guarantee this length of reset to the entire system.

MOTOROLA


3-47

If reset is asserted from any other source, the reset control logic asserts RESET for a minimum of 512 cycles until the source of reset is negated .

Type

External

Power-up

Software Watchdog

Double Bus Fault

Loss of Clock

RESET Instruction

. Table 3-5. Reset Source Summary

Source

External

EBI

Timing

Synchronous

Asynchronous

Sys Prot Asynchronous

Sys Prot Asynchronous

Clock Synchronous

CPU32 Asynchronous

Reset Lines Asserted by Controller

INTRST

INTRST

INTRST

INTRST

INTRST

-

CLKRST

CLKRST

CLKRST

CLKRST

CLKRST

-

EXTRST

EXTRST

EXTRST

EXTRST

EXTRST

EXTRST

After any internal reset occurs, a 14-cycle rise time is allowed before testing for the presence of an external reset. If no external reset is detected, the CPU32 begins its vector fetch.

Figure 3-24 is a timing diagram of the power-up reset operation, showing the relationships between RESET, VCC, and bus signals. During the reset period, the entire bus three-states (except for non-three-stateble signals, which are driven to their inactive state). Once RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins.

RESET should be asserted for at least 590 clock periods to ensure that the

MC68340 resets. Resetting the MC68340 causes any bus cycle in progress to terminate as if DSACKx or BERR had been asserted. In addition, the MC68340 appropriately initializes registers for a reset exception.

When a reset instruction is executed, the MC68340 drives the RESET signal for

512 clock cycles. In this case, the MC68340 resets the external devices of the system, and the internal registers of the MC68340 are unaffected. The external devices connected to the RESET signal are reset at the completion of the RESET instruction.

3-48


MOTOROLA

~ n

0) co w

~

(;)

C

en

en

~ l>

2 c: l> r-

~ o

-; o

:0 o

~

CLKOUT

VCO

...J

VCC

RESET

BUS

CYCLES

t------..J.....I

BUS STATE ;)

UNKNOWN

I

II(

NOTES:

1. Internal start-up time.

2. SSP read here.

3. PC read here.

4. First instruction fetched here.

ADDRESS AND

CONTROL SIGNALS

THREE-STATED

~

I

II(

Figure 3-24. Initial Reset Operation Timing

w

J;. to

3-50


MOTOROLA

SECTION 4

SYSTEM INTEGRATION MODULE

The MC68340 system integration module (SIM) consists of five submodules; four of these submodules control the system startup, initialization, configuration, and the external bus with a minimum of external devices. A fifth submodule provides

IEEE

1149.1 boundary scan capabilities. The five submodules, shown in Figure 4-1, are as follows:

• System Configuration and Protection

• Clock Synthesizer

• Chip Selects

• External Bus Interface

• IEEE

1149.1 Test Access Port

SYSTEM CONFIGURATION

AND PROTECTION r-------------~----~C~O~

I---~XTAL

~----

EXTAL

CLOCK

SYNTHESIZER

1ooI:;f-----

MODCK

... - - -

XFC

C HI

_

P

_ S_EL_EC_T_S __

-.IF

C"PSELECTS

~

EXTERNAL BUS

INTERFACE

A

-'"

,,-

v

EXTERNAL BUS

RESET

~I~:~-->-~

Figure 4-1. SIM Block Diagram


MOTOROLA 4-1

4.1 MODULE OVERVIEW

The system configuration and protection submodule controls system configuration and provides bus monitors and a software watchdog for system protection.

The clock synthesizer generates the clock signals used by the SIM as well as other modules and external devices.

The programmable chip-select submodule provides four chip-select signals.

Each chip-select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select.

The external bus interface (EBI) handles the transfer of information between the internal CPU32 and memory, peripherals, or other processing elements in the external address space. See SECTION 3 BUS OPERATION for furth~r information.

The MC68340 includes dedicated user-accessible test logic that is fully compliant with the IEEE 1149.1 Standard Test Access Port and Boundary Scan

Architecture. Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the IEEE Test

Technology Committee and Joint Test Action Group (JTAG). The MC68340 implementation supports circuit-board test strategies based on this standard.

Refer to SECTION 91EEE 1149.1 TEST ACCESS PORT for additional information.

4.2 MODULE OPERATION

The following paragraphs describe the operation of the module base address register, the system configuration and protection, clock synthesizer, and chipselect submodules, and the external bus interface.

4.2.1 Module Base Address Register

The module base address register controls the location of all module registers

(see 4.3.1 Module Base Address Register). All internal module registers occupy a single 4K-byte memory block that is relocatable along 4K-byte boundaries.

The location is fixed by writing the desired base address of the 4K-byte memory block to the module base address register using the MOVES instruction. In this manual, the offset from the base address is shown above the register diagram.

The module base address register is the only exception since it resides at a fixed location in CPU space.

4-2


MOTOROLA

The location of the module registers, fixed within the relocatable 4K-byte memory block, is listed in Table 4-1.

Table 4-1. Location of Modules

Module

SIM

Timer 1

Timer 2

Serial

DMA Channel 1

DMA Channel 2

Address Range

0OO-07F

600-63F

640-67F

700-73F

780-79F

7AO-7BF

4.2.2 System Configuration and Protection Submodule

The SIM allows the user to control certain features of system configuration by writing bits in the module configuration register (MCR). This register also contains read-only status bits that show the state of the SIM.

All M68000 Family members are designed to provide maximum system safeguards. As an extension of the family, the MC68340 promotes the same basic concepts of safeguarded design present in all M68000 members. In addition, many functions that normally must be provided in external circuits are incorporated in this device. The following features are provided in the system configuration and protection submodule:

SIM Configuration

The SIM allows the user to configure the system according to the particular requirements. The functions include control of FREEZE and show cycle operation, the function of the CS3-CSO signals, the access privilege of the supervisor/user registers, the level of interrupt arbitration, and automatic autovectoring for external interrupts.

Reset Status

The reset status register provides the user with information on the cause of the most recent reset. The possible causes include: external, power-up, software watchdog, double bus fault, loss of clock, and reset instruction.

MOTOROLA MC68340 USER'S MANUAL

4-3

Internal Bus Monitor

The SIM provides an internal bus monitor to monitor the data and size acknowledge (DSACK) response time for all internal bus accesses. An option allows the monitoring of internal-to-external bus accesses. Four selectable response times allow for variations in response speed of memory and peripherals used in the system. A bus error signal is asserted internally if the DSACK response limit is exceeded. BERR is not asserted externally.

This function can be disabled.

Double Bus Fault Monitor

The double bus fault monitor causes a reset to occur if the internal HALT is asserted by the CPU32, indicating a double bus fault. This function can be disabled. See

SECTION

3

BUS OPERATION

for more information.

Spurious Interrupt Monitor

If no interrupt arbitration occurs during an interrupt acknowledge cycle

(lACK), the bus error signal is asserted internally.

Software Watchdog

The software watchdog asserts reset or a level 7 interrupt (as selected by the system protection and control register) if the software fails to service the software watchdog for a designated period of time (i.e., because it is trapped in a loop or lost). There are eight selectable timeout periods. This function can be disabled.

Periodic Interrupt Timer

The SIM provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 f.Ls to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled.

Figure 4-2 shows a block diagram of the system configuration and protection submodule.

4.2.2.1

SYSTEM CONFIGURATION.

Aspects of the system configuration are controlled by the MCR and the autovector register (AVR). The configuration of port

B is controlled by the combination of the FIRQ bit in the MCR and the port B pin assignment register. Port B pins can function as dedicated

liD

lines, chip selects, or IRQx/AVEC.

For debug purposes, accesses to internal peripherals can be shown on the external bus. This function is called show cycles. The SHEN 1, SHE NO bits in the MCR control show cycles. Bus arbitration can be either enabled or disabled during show cycles.

4-4


MOTOROLA

MODULE

CONFIGURATION

RESET

STATUS

DOUBLE BUS

FAULT MONITOR

HALT t---~RESET

REQUEST

BUS

MONITOR

,

BERR

SPURIOUS

INTERRUPT MONITOR r - -

CLOCK ~

29

PRESCAlER

-

-

SOFTWARE

WATCHDOG

SOFTWARE

RESET

REQUESTor

IRQ7

PERIODIC

INTERRUPT TIMER

Figure 4·2. System Configuration and Protection Submodule

Arbitration for servicing interrupts is controlled by the value programmed into the interrupt arbitration (lARS) field of the MCR. Each module that generates interrupts, including the SIM, has an lARS field. (The SIM arbitrates for both its own interrupts and externally generated interrupts.) The value of the lARS field allows arbitration during an lACK cycle among modules that simultaneously generate the same interrupt level. No two modules should share the same lARS value.

There are eight arbitration levels for bus access, and the SIM is fixed at the highest level (level 7). The CPU32 is fixed at the lowest level (level 0). Only the

SIM, the CPU32, and the direct memory access (DMA) module can be bus masters and arbitrate for the bus.

The AVR contains bits that correspond to external interrupt levels that require an autovector response. The SIM supports up to seven discrete external interrupt requests. If the bit corresponding to an interrupt level is set in the AVR,

MOTOROLA


4-5

the SIM returns an autovector in response to the lACK cycle servicing that external interrupt request. Otherwise,external circuitry must either return an interrupt vector or assert the external AVEC signal.

4.2.2.2 INTERNAL BUS MONITOR. The internal bus monitor continually checks for the bus cycle termination response time by checking the DSACKx, BERR, and HALT status or the AVEC status during an lACK cycle. The monitor initiates

BERR if the response time is excessive. The internal bus monitor cannot check the DSACKx response on the external bus unless the MC68340 is the bus master. The BME bit in the system protection control register (SYPCR) enables the internal bus monitor for internal-to-external bus cycles. If the system contains external bus masters whose bus cycles must be monitored, an external bus monitor can be implemented. In this case, the internal-to-external bus monitor option must be disabled. The bus monitor feature cannot be disabled for internal accesses to internal modules.

The bus cycle termination response time is measured in clock cycles, and the maximum-allowable response time is programmable. The bus monitor response time period ranges from 8 to 64 system clocks (see Table 4-8). These options are provided to allow for different response times of peripherals that might be used in the system.

4.2.2.3 DOUBLE BUS FAULT MONITOR. The double bus fault monitor responds to an assertion of HALT on the internal bus. Refer to SECTION 3 BUS OPER-

ATION for more information. The DBF bit in the reset status register indicates that the last reset was caused by the double bus fault monitor. The double bus fault monitor reset ca,n be inhibited by the DBFE bit in the SYPCR.

4.2.2.4 SPURIOUS INTERRUPT MONITOR. The spurious interrupt monitor issues

BERR if no interrupt arbitration occurs during an lACK cycle. Normally, during an lACK cycle, on"e or more internal submodules -recognize that the CPU32 is responding to their interrupt request(s) and arbitrate for the privilege of returning a vector or asserting AVEC. (The SIM reports and arbitrates for externally generated interrupts.) This feature cannot be disabled.

4.2.2.5 SOFTWARE WATCHDOG. Once enabled by the SWE bit in the MCR, the software watchdog requires a special service sequence t,o be executed on a periodic basis. If this periodic servicing action does not occur, the software watchdog times out and issues a reset or a level 7 interrupt (as programmed

4-6


MOTOROLA

by the SWRI bit in the SYPCR). The address of the interrupt service routine for the software watchdog interrupt is stored in the software interrupt vector register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as the clock control circuits for the periodic interrupt timer. swp--------------------------~

P T P - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

FREEZE

EXTAL sweLl<

LPSTOP----------------------------------~

~---r'-"'T"'""-,.----'

PIT

INTERRUPT

Figure 4-3. Software Watchdog

This mechanism protects the system against the possibility of the software becoming trapped in loops or running away. See Table 4-7 for a list of watchdog timeout periods. The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer register (PITR) and the SWT bits in the SYPCR.

The software watchdog service sequence consists of the following two steps: write $55 to the software service register (SWSR) and write $AA to the SWSR.

Both writes must occur in the order listed prior to the watchdog timeout, but any number of instructions or accesses to the SWSR can be executed between the two writes.

4.2.2.6 PERIODIC INTERRUPT TIMER. The periodic interrupt timer consists of an

8-bit modulus counter that is loaded with the value contained in the' PITR (see

Figure 4-3). The modulus counter is clocked by a signal derived from the buffered crystal oscillator (EXTAL) input pin unless an external frequency source is used. When an external frequency source is used (MODCK low during reset), the default state of the prescaler control bits (SWP and PTP) in the PITR is changed to enable both prescalers.

MOTOROLA


Either clock source (EXTAL or EXTAL+512) is divided by four before driving the modulus counter (PITCLK). When the modulus counter value reaches zero, an interrupt is generated. The level of the generated interrupt is programmed into the PIROL bits in the periodic interrupt control register (PICR). During the lACK cycle, the SIM places the periodic interrupt vector, programmed into the

PIV bits in the PICR, onto the bus. The value of bits 7-0 in the PITR is then loaded again into the modulus counter, and the counting process starts over.

If a new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed.

4.2.2.6.1 Periodic Timer Period Calculation. The period of the periodic timer can be calculated using the following equation: periodic interrupt timer period

PITR count value

=

EXTAL frequency/prescaler value

22

Solving the equation using a crystal frequency of 32.768 kHz with the prescaler disabled gives: periodic interrupt timer period

PITR count value

32768/1 periodic interrupt timer period

=

PITR count value

8192

This gives a range from 122

~s, with a PITR value of $01 (00000001 binary), to

31.128 ms, with a PITR value of $FF (11111111 binary).

Solving the equation with the prescaler enabled (PTP

=

1) gives the following values: periodic interrupt timer period

PITR count value

32768/512 periodic interrupt timer period

PITR count value

16


This gives a range from 62.5 ms, with a PITR value of $01, to 15.94 s, with a

PITR value of $FF.

For fast calculation of periodic timer period using a 32.768-kHz crystal, the following equations can be used:

With prescaler disabled: programmable interrupt timer period

=

PITR (122 fLS)

With prescaler enabled: programmable interrupt timer period

=

PITR (62.5 ms)

4.2.2.6.2 Using the Periodic Timer as a Real-Time Clock. The periodic interrupt timer can be used as a real-time clock interrupt by setting it up to generate an interrupt with a one-second period. Rearranging the periodic timer period equation to solve for the desired count value:

PITR count value

PITR count value

(PIT period) (EXTAL frequency)

(Prescaler value) (22)

(1) (32768)

PITR count value

=

16 (decimal)

Therefore, when using a 32.768-kHz crystal, the PITR should be loaded with a value of $10 with the prescaler enabled to generate interrupts at a one-second rate.

4.2.3 Clock Synthesizer

The clock synthesizer can operate from an on-chip phase-locked loop (PLL) and voltage-controlled oscillator (VCO), using an external crystal connected between the EXTAL and XTAL pins as a reference frequency source. A 32.768kHz watch crystal provides an inexpensive reference, but the reference crystal frequency can be any frequency from 25 to 50 kHz. Additionally, the system clock frequency can be driven directly into the EXTAL pin (the XTAL pin must be left floating for this case).

When using a 32.768-kHz crystal, the system clock frequency is programmable

(using the W, X, and Y bits in the SYNCR) from 131 kHz to the maximum clock

MOTOROLA


4-9

frequency specified in

MC68340/D, MC68340 Technical Summary,

with a resolution of 131 kHz. A status bit (SLIMP) in the SYNCR indicates that a loss of crystal reference has been detected. The RSTEN bit controls whether a loss of crystal causes a system reset or causes the device to operate in limp mode. In limp mode, the VCO runs approximately one-half maximum speed, using an internal voltage reference. Another status bit (SLOCK) in the SYNCR indicates when the VCO has locked onto the desired frequency or if an external clock is being used.

A separate power pin (VCCSYN) is used to allow the clock circuits to run with the rest of the device powered down and to provide increased noise immunity for the clock circuits. The source for VCCSYN should be a quiet power supply with adequate external bypass capacitors placed as close as possible to the

VCCSYN pin to ensure a stable operating frequency. Figure 4-4 shows a block diagram of the clock submodule and typical values for the bypass and PLL external capacitors. The crystal manufacturer's documentation should be ·consuited for specific recommendations for external components.

4.2.3.1 PHASE COMPARATOR AND FILTER. The phase comparator takes the output of the frequency divider and compares it to a reference signal from an external crystal. The result of this compare is low-pass filtered and used to control the VCO. The comparator also detects when the crystal oscillator stops running to initiate the limp mode for the system clock.

The PLL requires an external low-leakage filter capacitor, typically in the range from 0.01 to 0.1 f,LF, connected between the XFC and VCCSYN pins. Smaller values of the external filter capacitor provide a faster response time for the

PLL, and larger values provide greater frequency stability.

4.2.3.2 FREQUENCY DIVIDER. The frequency divider circuits divide the VCO frequency down to the reference frequency for the phase comparator. The frequency divider consists of the following: 1) a 2-bit prescaler controlled by the

W bit in the SYNCR and 2) a 6-bit modulo downcounter controlled by the Y bits in the SYNCR.

Several factors are important to the design of the system clock. The resulting system clock frequency must be within the limits specified for the device. The frequency of the system clock is given by the following equation:

FSYSTEM

=

FCRYSTAL ( 4(Y

+

1)2

2W

+

X

)


20M

PHASE

COMPARATOR

VCO

FEEDBACK DIVIDER

SYSTEM CLOCK CONTROL

~-------------------------------------~

NOTE 1: Must be low-leakage capacitor.

EXTCLK

Figure 4-4. Clock Submodule Block Diagram

The maximum VCO frequency limit must also be observed. The VCO frequency is given by the following equation:

FVCO

=

FSYSTEM(2-X)

Since clearing the X-bit causes the VCO to run at twice the system frequency, the VCO upper frequency limit must be considered when programming the

SYNCR. Both the system clock and VCO frequency limits are given in the


Table

4-2 lists some the frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768 kHz.

MOTOROLA


4-11

Table 4-2. System Frequencies from 32.768-kHz Reference y

000000

000101

001010

001111

010100

011001

011111

100011

101000

101101

110010

110111

111100

111111

W=O; x=o W=O; X=1 W=1; x=o W=1; X=1

131 262 524 1049

786

1442

1573

2884

3146

5767

6291

11534

2097

2753

3408

4194

4194

5505

6816

8389

9437

8389

11010

13631

16777

4719

5374

6029

6685

7340

7995

8389

10748

12059

13369

14680

15991

16777

-

-

-

-

-

-

-

-

-

-

-

16777

-

-

-

-

-

NOTE: System frequencies are in kHz.

4.2.3.3 CLOCK CONTROL. The clock control circuits determine the source used for both internal and external clocks during special circumstances, such as lowpower stop (LPSTOP) execution.

Table 4-3 summarizes the clock activity during LPSTOP, with MODCK

=

1 during reset. Any clock in the off state is held low. Two bits in the SYNCR (STEXT and

STSIM) control clock activity during LPSTOP. Refer to 4.2.6 Low-Power Stop for additional information.

Table 4-3. Clock Control Signals

Control Bits

Clock Outputs

STSIM STEXT SIMCLK

CLKOUT

0 0 EXTAL Off

0

1

1

0

EXTAL

VCO

EXTAL

Off

1 1

VCO VCO

NOTE: SIMCLK runs the periodic interrupt,

RESET, and IRQx pin synchronizers in

LPSTOP mode.

4-12


MOTOROLA

4.2.4 Chip-Select Submodule

Typical microprocessor systems require external hardware to provide select signals to external memory and peripherals. This device integrates these functions on-chip to provide the cost, speed, and reliability benefits of a higher level of integration. The chip-select submodule contains register pairs for each external chip-select signal. The pair consists of a base address register and an address mask register that define the characteristics of a single chip select. The register pair provides flexibility for a wide variety of chip-select functions.

4.2.4.1 PROGRAMMABLE FEATURES. The chip-select submodule supports t,he following programmable features:

Four Programmable Chip-Select Circuits

All four chip-select circuits are independently programmable from the same list of selectable features. Each chip-select circuit has an individual base address register and address mask register that contain the programmed characteristics of that chip select. The valid (V) bit of the base address register indicates that the register information for that chip select is valid.

A global chip select allows address decode for a boot ROM before system initialization occurs.

Variable Block Sizes

The block size, starting from the specified base address, can vary in size from 256 bytes up to 4 Gbytes in 2 n increments. This size is specified in the address mask register.

Both 8- and 16-Bit Ports Supported

The 8-bit ports are accessible on both odd and even addresses when connected to data bus bits 15-8; the 16-bit ports can be accessed as odd bytes, even bytes, or even words. The port size is specified by the PS bits in the address mask register.

Write-Protect Capability

The WP bit in each base address register can restrict write access to its range of addresses.

Fast-Termination Option

Programming the FTE bit in the base address register for the fast-termination option causes the chip-select submodule to terminate the cycle by asserting the internal DSACKx early, providing a two-cycle external access.

Peripherals using the fast-termination option must be 16 bits wide.

MOTOROLA


4-13

Internal DSACKx Generation for External Accesses with Programmable Wait

States

The pin assignment register can be referenced for generating DSACKx with up to three wait states for a particular device using the DD bits in the address mask register.

Full 32-Bit Address Decode with Address Space Checking

All accesses privileges can be optionally checked through the use of the

FC bits in the base address register and the FCM bits in the address mask register.

4.2.4.2 GLOBAL CHIP-SELECT OPERATION. Global chip-select operation allows address decode for a boot ROM before system initialization occurs. CSO is the global chip-select output, and its operation differs from the other external chipselect outputs following reset. When the CPU32 begins fetching after reset,

CSO is asserted for every address, unless the module address base register is accessed or internal peripheral chip select is generated.

Global chip select provides a 16-bit port with three wait states, allowing a boot

ROM to be located in any address space and still providing the stack pointer and program counter values at $00000000 and $00000004, respectively. CSO operates in this manner until the V-bit is set in the CSO base address register.

CSO can be programmed to continue decode for a range of addresses after the

V-bit is set, provided the desired address range is first loaded into base address register O. After the V-bit is set for CSO, global chip select can only be restarted with a system reset.

A system can use an 8-bit boot ROM if an external 8-bit DSACK is generated which responds in two wait states or less.

4.2.5 External Bus Interface

This section describes port A and port B functions. Refer to SECTION 3 BUS

OPERATION for more information about the external bus interface.

4.2.5.1 PORT A. Port A pins can be programmed to be either addresses A31-A24, discrete

1/0

pins, or IACKx pins. The port A pin assignment registers (PPARA1 and PPARA2) control the function of the port A pins as shown in Table 4-4.

Each pin can be independently programmed. Upon reset, port A is configured


as input pins. If the system uses these signals as addresses, pulldowns should be put on these signals to avoid indeterminate values until the port A registers can be programmed.

A31

A30

A29

A28

A27

A26

A25

A24

Table 4-4. Port A Pin Assignment Register Function

Signal

Pin Function

PPARA1 BIT

PPARA2 BIT

=

0 PPARA1 BIT

=

1 PPARA 1 BIT

=

0

=

0 PPARA2 BIT

=

X PPARA2 BIT

=

1

A31 PORT A7 IACK7

PORT A6 A30

A29

A28

PORT A5

PORT A4

IACK6

IACK5

IACK4

A27

A26

A25

A24

PORT A3

PORT A2

PORT A1

PORT AO

IACK3

IACK2

IACK1

-

4.2.5.2 PORT B. Port B pins can be programmed to be chip selects, IROx and

MODCK pins, or discrete I/O pins. These pins are multiplexed as shown in

Figure 4-5. Selection of pin function is done by a combination of the port B pin assignment register (PPARB) and the FIRO bit of the MCR (see Table 4-5). Each pin can be independently programmed. Upon reset, port B is configured as

MODCK, IR07, IR06, IR05, IR03, and CS3-CSO.

INTERRUPT

PORT

LOGIC

-

I R04IPORT B4

IR02IPORT 82

IR01IPORT 81

MODCIVPORT 80

IR07IPORT 87

IR06IPORT 86

I R05IPORT B5

IR03IPORT 84

CHIP-

SELECT

MODULE

AVEC

CS3

CS2

CS1

CSO

- -

FULLIRO

MUX

CSO/AVEC

FIRO t

Figure 4-5. Full Interrupt Request Multiplexer

MOTOROLA


Table 4-5. Port B Pin Assignment Register and FIRQ Bit Function

Signal

IRQ7

IRQ6

IRQ5

CS3

IRQ3

FIRQ=O FIRQ = 0 FIRQ = 1 FIRQ = 1

PPARB BIT = 0 PPARB BIT = 1 PPARB BIT = 0 PPARB BIT = 1

PORT 87 IRQ7

Pin Function

PORT 87

IRQ7

PORT 86

PORT 85

IRQ6

IRQ5

PORT 86

PORT 85

IRQ6

IRQ5

CS3

PORT 83

CS3

IRQ3

CS2 CS2

CS1

CSO

CS2

CS1

CSO

CS1

CSO

MOOCK PORT 80 MOOCK

NOTE: MOOCK has no function after reset.

PORT 84

PORT 83

PORT 82

PORT 81

AVEC

PORT 80

IRQ4

IRQ3

IRQ2

IRQ1

AVEC

MOOCK

4.2.6 Low-Power Stop

The LPSTOP mode provides reduced power consumption when the MC68340 is idle. All internal modules have no clock, except the SIM, which remains active.

Operation of the SIM clock and CLKOUT during LPSTOP is controlled by the

STSIM and STEXT bits in the SYNCR. Execution of the LPSTOP instruction disables the clock to the software watchdog in the low state. The software watchdog remains stopped until the LPSTOP state is ended and begins to run again on the next rising clock edge.

NOTE

When the CPU32 executes the STOP instruction (as opposed to

LPSTOP), the software watchdog continues to run. If the software watchdog is enabled, it issues a reset or interrupt when timeout occurs.

The periodic interrupt timer does not respond to an LPSTOP instruction; thus, it can be used to exit LPSTOP as long as the interrupt request level is higher than the CPU32 interrupt mask level. To stop the periodic interrupt timer while in LPSTOP, the PITR must be loaded with a zero value before LPSTOP is executed. The bus monitor, double bus fault monitor, and spurious interrupt monitor are all inactive during LPSTOP.

4-16


MOTOROLA

4.2.7 Freeze

FREEZE is asserted by the CPU32 if a breakpoint is encountered with background mode enabled. Refer to SECTION 5 CPU32 for more information on the background mode. When FREEZE is asserted, the double bus fault monitor and spurious interrupt monitor continue to operate normally. However, the software watchdog and the periodic interrupt timer may be affected. Setting the FRZ1 bit in the MCR disables the software watchdog when FREEZE is asserted, and setting the FRZO bit in the MCR disables the periodic interrupt timer when

FREEZE is asserted.

4.3 PROGRAMMER'S MODEL

Figure 4-6 is a programmer's model (register map) of all registers in the SIM.

For more information about a particular register, refer to the description for the module or submodule indicated in the right column. The ADDR (address) column indicates the offset of the register from the address stored in the base address register. The FC (function code) column indicates whether a register is restricted to supervisor access (S) or programmable to exist in either supervisor or user space (S/U).

In the registers discussed in the following pages, the number in the upper righthand corner indicates the offset of the register from the address stored in the base address register. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after reset. The access privilege is indicated in the lower right-hand corner.

MOTOROLA


4-18

040 S

042 S

044 S

046 S

048 S

04A S

04C S

04E S

050 S

052 S

054

S

056

058 S

05A

05C S

05E

ADDR FC 15 8 7 r-------------------------------------------------~

SYSTEM

000 S MODULE CONFIGURATION REGISTER (MCR)

PROTECTION

004

006 S

CLOCK SYNTHESIZER CONTROL REGISTER (SYNCR)

AUTOVECTOR REGISTER (AVR)

I

RESET STATUS REGISTER (RSR)

CLOCK

SYSTEM

PROTECTION

010 StU

012 StU

014

S

016 S

018 StU

01A StU

O1C StU

OlE S

020 S

022 S

024 S

026 S

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

SW INTERRUPT VECTOR (SWIV)

PORT A DATA (PORTA)

PORT A DATA DIRECTION (DORA)

PORT A PIN ASSIGNMENT 1 (PPRA1)

PORT A PIN ASSIGNMENT 2 (PPRA2)

PORT B DATA (PORTB)

PORT B DATA (PORTBl)

PORT B DATA DIRECTION (DDRB)

PORT B PIN ASSIGNMENT (PPARB)

SYSTEM PROTECTION CONTROL (SYPCR)

PERIODIC INTERRUPT CONTROL REGISTER (PICR)

PERIODIC INTERRUPT TIMING REGISTER (PITR)

RESERVED SOFTWARE SERVICE (SWSR)

EBI

EBI

EBI

EBI

EBI

EBI

EBI

EBI

SYSTEM

PROTECTION

SYSTEM

PROTECTION

SYSTEM

PROTECTION

SYSTEM

PROTECTION

ADDRESS MASK 1 CSO

ADDRESS MASK 2 CSO

BASE ADDRESS 1 CSO

BASE ADDRESS 2 CSO

ADDRESS MASK 1 CSl

ADDRESS MASK 2 CSl

BASE ADDRESS 1 CSl

BASE ADDRESS 2 CSl

ADDRESS MASK 1 CS2

ADDRESS MASK 2 CS2

BASE ADDRESS 1 CS2

BASE ADDRESS 2 CS2

ADDRESS MASK 1 CS3

ADDRESS MASK 2 CS3

BASE ADDRESS 1 CS3

BASE ADDRESS 2 CS3

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

CHIP SELECT

Figure 4-6. SIM Programming Model

MC68340 USER'S MANUAL MOTOROLA

4.3.1 Module Base Address Register

Module Base Address Register 1 $03FFOO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

I

BA31

I

BA30

I

BA29

I

BA28

I

BA27

I

BA26

I

BA25

I

BA24

I

BA23

I

BAni BA21

I

BA20

I

BA19

I

BA18

I

BAni BA16

I

RESET: o o 0 0 0

CPU Space Only

Module Base Address Register 2

15 14 13 12 11 10

I

BA15

I

BA14

I

BA13

I

BA12

I

0

I

0

I

0

I

0

I

0

RESET: o o

$03FF02

I

0 o l o l o l o l v

CPU Space Only

BA31-BA12 Base Address Bits 31-12

The base address field is the upper 20 bits of the module base address register, providing for block starting locations in increments of 4K-bytes.

v -

Valid Bit

This bit indicates when the contents of the module base address register are valid. The base address value is not used; therefore, all internal module registers are not accessible until the V-bit is set.

1 = Contents valid

0= Contents not valid

NOTE

An access to this register does not affect external space since the cycle is not run externally.

4.3.2 System Configuration and Protection Registers

The following paragraphs provide descriptions of the system configuration and protection registers.

MOTOROLA

MC68340 USER'S

MANUAL

4-19

4.3.2.1 MODULE CONFIGURATION REGISTER (MCR). The MCR, which controls the SIM configuration, can be read or written at any time.

MCR $000

15 14 13 12 11 10 9 8 7 3 2 1 0

I

0

I

FRZI I FRZO I FIRQ I 0 I 0 I SHENll SHENO I sUPV I 0 I 0 I 0 IIAR

B3

11ARB211ARBI IIARBO I

RESET: o

Supervisor Only

FRZ1 Freeze Software Watchdog Enable

1

=

When FREEZE is asserted, the software watchdog counters are disabled, preventing interrupts from occurring during software debug.

0= When FREEZE is asserted, the software watchdog counters continue to run. See 4.2.7 Freeze for more information.

FRZO Freeze Periodic Interrupt Timer Enable

1

=

When FREEZE is asserted, the periodic interrupt timer counters are disabled.

0= When FREEZE is asserted, the periodic interrupt timer counters continue to operate as programmed.

FIRQ Full Interrupt Request Mode

1

=

Configures port B for seven interrupt request lines, autovector, and no external chip selects.

0= Configures port B for four interrupt request lines and four external chip selects.

See 4.2.5.2 PORT B for a description of the FIRQ bit and port B logic.

SHEN1, SHENO Show Cycle Enable

These two control bits determine what the EBI does with the external bus during internal transfer operations. A show cycle allows internal transfers to be externally monitored. The address, data, and control signals, except for

AS, are driven externally. Table 4-6 lists all show cycle bit combinations, whether or not show cycle data is driven externally, and whether external bus arbitration can occur. If external bus arbitration is disabled, the EBI will not recognize an external bus request until arbitration is enabled again. Address information is always driven externally unless the external bus is relinquished. However, data is not driven and DS is not asserted for internal accesses unless show cycles are enabled. When both show cycle bits are set, an external bus request causes an internal master to finish its current cycle and no longer initiate cycles on the internal bus. The internal master resumes


running cycles on the bus after BR and BGACK are negated. To prevent bus conflicts, external peripherals must not attempt to initiate cycles during show cycles with arbitration disabled.

Table 4-6. Show Cycle Control Bits

SHENl SHENO

0 0

ACTION

Show cycles disabled, external arbitration enabled

0

1

1

1

0

1

Show cycles enabled, external arbitration disabled

Show cycles enabled, external arbitration enabled

Show cycles enabled, external arbitration enabled, internal activity halted by a bus grant

SUPV Supervisor/User Data Space

The SUPV bit defines the SIM global registers as either supervisor data space or user (unrestricted) data space.

1 = The SIM registers defined as supervisor/user are restricted to supervisor data access (FC3-FCO = $5). An attempted user-space write is ignored and returns BERR.

0= The SIM registers defined as supervisor/user data are unrestricted (FC2 is a don't care).

IARB3-IARBO Interrupt Arbitration Bits 3-0

The reset value of IARB is $F, allowing the SIM to arbitrate during an lACK cycle immediately after reset. The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority). A value of

$0 prevents arbitration and causes all SIM interrupts, including external interrupts, to be discarded as extraneous.

4.3.2.2 AUTOVECTOR REGISTER (AVR). The AVR contains bits that correspond to external interrupt levels that require an autovector response. Setting a bit allows the SIM to assert an internal AVEC during the lACK cycle in response to the specified interrupt request level. This register can be read and written at any time.

AVR $006

7 6 5 4 3 2 1 0

I

AV7

I

AV6

I

AV5

I

AV4

I

AV3

I

AV2

I

AVl

I

AVO

RESET: o

Supervisor Only

MOTOROLA


4-21

4.3.2.3 RESET STATUS REGISTER (RSR).

The RSR contains a bit for each reset source to the SIM. A set bit indicates the last type of reset that occurred, and only one bit can be set in the register. The RSR is updated by the reset control logic when the SIM comes out of reset. This register can be read at any time; a write has no effect. For more information, see SECTION 3 BUS OPERATION.

RSR $007

2 1 0

I

EXT

I

POW

I sw

I

DSF

I

0

I lOC

I

SYS

I

0

I

Supervisor Only

EXT External Reset

1

=

The last reset was caused by an external signal driving RESET.

POW Power-Up Reset

1

=

The last reset was caused by the power-up reset circuit.

SW Software Watchdog Reset

1

=

The last reset was caused by the software watchdog circuit.

DBF Double Bus Fault Monitor Reset

1

=

The last reset was caused by the double bus fault monitor.

LOC Loss of Clock Reset

1

=

The last reset was caused by a loss of frequency reference to the clock submodule. This reset can only occur if the RSTEN bit in the clock submodule is set and the VCO is enabled.

SYS System Reset

1

=

The last reset was caused by the CPU32 executing a reset instruction.

The system reset does not load a reset vector or affect any internal

CPU32 registers or SIM configuration registers, but does reset external devices and other internal modules.

4-22


MOTOROLA

4.3.2.4 SOFTWARE INTERRUPT VECTOR REGISTER (SWIV).

The SWIV contains the 8-bit vector that is returned by the SIM during an lACK cycle in response to an interrupt generated by the software watchdog. This register can be read or written at any time. This register is set to the uninitialized vector, $OF, at reset.

SWIV $020

7 6 5 4 3 2 1 a

I

SWIV7! SWIV6! SWIV5! SWIV4! SWIV3! SWIV2! SWIVI ! sWlva !

RESET: a

Supervisor Only

4.3.2.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR).

The SYPCR controls the system monitors, the prescaler for the software watchdog, and the bus monitor timing. This register can be read at any time but can be written only once after reset.

SYPCR $021

7 6 5 4 3 2 1 a

I

SWE ! SWRI ! SWTI ! SWTa ! DBFE ! BME ! BMTl ! BMTa !

RESET: a

Supervisor Only

SWE Software Watchdog Enable

1

=

Software watchdog enabled

0= Software watchdog disabled

See

4.2.2.5 SOFTWARE WATCHDOG

for more information.

SWRI Software Watchdog Reset/Interrupt Select

1

=

Software watchdog causes a system reset.

0= Software watchdog causes a level 7 interrupt to the CPU32.

MOTOROLA


J

SWT1, SWTO Software Watchdog Timing

These bits, along with the SWP bit in the PITR, control the divide ratio used to establish the timeout period for the software watchdog. The software watchdog timeout period is given by the following formula:

EXTAL frequency/divide count or divide count

EXTAL frequency

The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the software watchdog timeout for any clock frequency. The timeout periods are listed for a 32.768-kHz crystal used with the

VCO

and for a 16.777-

MHz external oscillator.

SWP SWT1 SWTO

1

1

1

1

0

0

0

0

0

0

1

1

0

0

1

1

Table 4-7. Deriving Software Watchdog Timeout

0

1

0

1

0

1

0

1

Software Timeout Period

29/EXTAL Input Frequency

2

11

/EXTAL Input Frequency

2

13


2

15


2

18


2

20


2

22


2

24


32.76B-kHz

Crystal Period

15.6 ms

62.5 ms

250 ms

1 S

8s

32 S

128 S

512 S

16.777-MHz External

Clock Period

30 f-Ls

122 f-Ls

488 f-LS

1.45 f-Ls

15.6 f-Ls

62.5 f-Ls

250 f-Ls

1 f-LS

CAUTION

When the SWP and SWT bits are modified to select a software timeout other than the default, the software service sequence ($55 followed by

$AA written to the software service register) must be performed before the new timeout period takes effect.

Refer to 4.2.2.5 SOFTWARE WATCHDOG for more information.


MOTOROLA

DBFE Double Bus Fault Monitor Enable

1

=

Enable double bus fault monitor function

D

=

Disable double bus fault monitor function

For more information, see 4.2.2.3 DOUBLE BUS FAULT MONITOR and SEC-

TION 5 CPU32.

BME Bus Monitor External Enable

1

=

Enable bus monitor function for an internal-to-external bus cycle.

D

=

Disable bus monitor function for an internal-to-external bus cycle.

For more information see 4.2.2.2 INTERNAL BUS MONITOR.

BMT Bus Monitor Timing.

These bits select the timeout period for the bus monitor (see Table 4-8).

BMT1

0

0

1

1

BMTO

0

1

0

1

Table 4-8. BMT Encoding

Bus Monitor Timeout Period

64 system clocks (CLKOUT)

32 system clocks

16 system clocks

8 system clocks

MOTOROLA


4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the interrupt level and the vector number for the periodic interrupt request. This register can be read or written at any time. Bits 15-11 are unimplemented and always return zero; a write to these bits has no effect.

PICR

15 14 13

I a

I a

I a

RESET: a

$022

12

11 10 9 8 7 6 5 4 3 2 1 a

I a

I a

I

PIRQL21 PIRQL11 PIRQLO

I

PIV7

I

PIV6

I

PIV5

I

PIV4

I

PIV3

I

PIV2

I

PIVI

I

PIVO

I

Supervisor Only

PIROL2-PIROLO Periodic Interrupt Request Level

These bits contain the periodic interrupt request level. Table 4-9 lists which interrupt request level is asserted during an lACK cycle when a periodic interrupt is generated. The periodic timer continues to run when the interrupt is disabled.

Table 4-9. PIRQL Encoding

PIROL2 PIROL1 PIROLO

0

0

0

Interrupt Request Level

Periodic Interrupt Disabled

0 0 1

Interrupt Request Level 1

0

0

1

1

0

1



1

1

1

1

0

0

1

1

0

1

0

1





PIV7-PIVO Periodic Interrupt Vector Bits 7-0

These bits contain the value of the vector generated during an lACK cycle in response to an interrupt from the periodic timer. When the SIM responds to the lACK cycle, the periodic interrupt vector from the PICR is placed on the bus.

This vector number is multiplied by four to form the vector offset, which is added to the vector base register to obtain the address of the vector.

4-26


MOTOROLA

4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for prescaling the software watchdog and periodic timer as well as the count value for the periodic timer. This register can be read or written at any time.

Bits 15-10 are not implemented and always return zero when read. A write does not affect these bits.

PITR $024

15 14 13 12 11 10 8 7 6 5 4 3 2 1 0

I

0

I

0

I

0

I

0

I

0

I

0

I sWP

I

PTP

I

PITR71 PITR61 PITR51 PITR41 PITR31 PITR21 PITRI

I

PITRO

I

RESET: o o

MODCK MODCK 0

Supervisor Only

SWP Software Watchdog Prescale

This bit controls the software watchdog clock source as shown in 4.3.2.5

SYSTEM PROTECTION CONTROL REGISTER (SYPCR).

1 = Software watchdog clock prescaled by a value of 512

0= Software watchdog clock not prescaled

The SWP reset value is the inverse of the MODCK bit state on the rising edge of reset.

PTP Periodic Timer Prescaler Control

This bit contains the prescaler control for the periodic timer.

1 = Periodic timer clock prescaled by a value of 512

0= Periodic timer clock not prescaled

The PTP reset value is the inverse of the MODCK bit state on the rising edge of reset.

PITR7-PITRO Periodic Interrupt Timer Register Bits 7-0

The remaining bits of the PITR contain the count value for the periodic timer.

A zero value turns off the periodic timer.

4.3.2.8 SOFTWARE SERVICE REGISTER (SWSR). The SWSR is the location to which the software watchdog servicing sequence is written. The software watchdog can be enabled or disabled by the SWE bit in the SYPCR. SWSR can be written at any time but returns all zeros when read.

SWSR $027

7 6 5 4 3 2 1 0

I

RESET: o

Supervisor Only

MOTOROLA


4-27

4.3.3 Clock Synthesizer Control Register (SYNCR)

The SYNCR can be read or written only in supervisor mode. The reset state of

SYNCR produces an operating frequency of 8.38 MHz when the PLL is referenced to a 32.768-kHz crystal. The system frequency is controlled by the frequency control bits in the upper byte of the SYNCR as follows:

FSYSTEM = FCRYSTAL ( 4(Y

+

1 )22W+X)

SYNCR

15

I w

RESET:

0

14 13 12 11 10 7 4 3

I x

I

Y5

Y4

I

Y3

I

Y2

I

Y1

I

YO

I

RSVD

I

0

I

0

I

SLIMP

I

SLOCK

I

2 u u

$004

1 0

I

STSIM

I

STEXT

I

U = Unaffected by reset Supervisor Only

W -

Frequency Control Bit

This bit controls the prescaler tap in the synthesizer feedback loop. Setting the bit increases the VCO speed by a factor of four, requiring a time delay for the VCO to relock (see equation for determining system frequency). x -

Frequency Control Bit

This bit controls a divide-by-two prescaler, which is not in the synthesizer feedback loop. Setting the bit doubles the system clock speed without changing the VCO speed, as specified in the equation for determining system frequency; therefore, no delay is incurred to relock the VCO.

Y5-YO Frequency Control Bits

The V-bits, with a value from 0-63, control the modulus downcounter in the synthesizer feedback loop, causing it to divide by the value of Y

+

1 (see the equation for determining system frequency). Changing these bits requires a time delay for the VCO to relock.

RSVD Reserved

This bit is reserved for factory testing.

SLIMP Limp Mode

1 = A loss of crystal reference has been detected, and the VCO is running at approximately one-half maximum speed, determined from an internal voltage reference.

0= External crystal frequency is at VCO reference.


SLOCK Synthesizer Lock

1

=

VCO has locked onto the desired frequency (or system clock is driven externally). a

=

VCO is enabled but has not yet locked.

RSTEN Reset Enable

1

=

Loss of crystal causes a system reset. a

=

Loss of crystal causes the VCO to operate at a nominal speed without external reference (limp mode), and the device continues to operate at that speed.

STSIM Stop Mode System Integration Clock

1

=

When the LPSTOP instruction is executed, the SIM clock is driven from the VCO. a

=

When the LPSTOP instruction is executed, the SIM clock is driven from the crystal oscillator, and the VCO is turned off to conserve power.

STEXT Stop Mode External Clock

1

=

When the LPSTOP instruction is executed, the external clock pin

(CLKOUT) is driven from the SIM clock as determined by the STSIM bit. a

=

When the LPSTOP instruction is executed, the external clock is held low to conserve power.


4.3.4 Chip-Select Registers

The following paragraphs provide descriptions ofthe registers in the chip-select submodule.

4.3.4.1 BASE ADDRESS REGISTERS. There are four base address registers in the chip-select submodule, one for each chip-select signal.

Base Address 1 $044, $04C, $054, $05C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

I

BA31

I

BA30

I

BA29

I

BA28

I

BA27

I

BA26

I

BA25

I

BA24

I

BA23

I

BA22

I

BA21

I

BA20

I

BA19

I

BA18

I

BAni BA16

I

RESET:

U u u u u u u u u u u u u u u u

Supervisor Only

Base Address 2

15 14 13 12 11 10 9 S 7 6

I

BA15

I

BA14

I

BA13

I

BA12

I

BAll

I

BA10

I

BA9

I

BAS

I

FC3

I

FC2

I

FCI

RESET:

U U u u u u u u u u u

U

=

Unaffected by reset

$046, $04E, $056,$05E

FCO

3

I

WP

I

FTE

I

0

I v u u u

Supervisor Only

BA31-BA8 Base Address Bits 31-8

The base address field, the upper 24 bits of each base address register, provides for block sizes in increments of 256 bytes. The base address field

(and the function code field) is compared to the address on the address bus to determine if a chip select should be generated.

FC3-FCO Function Code Bits 3-0

This field can be used to specify access to a certain address space type.

WP Write Protect

This bit can restrict write accesses to the address range in a base address register. An attempt to write to the range of addresses specified in a base address register that has this bit set returns BERR.

1 = Only read accesses allowed

0= Either read or write allowed


FTE Fast-Termination Enable

This bit causes the submodule to terminate the cycle early with a word-sized

DSACKx, giving a fast two-clock external access. When clear, all external cycles are at least three clocks. If fast termination is enabled, the DD and PS bits of the corresponding address mask register are overridden (see SECTION

3 BUS OPERATION).

1

=

Fast-termination cycle enabled

0= Fast-termination cycle disabled (termination determined by DD and PS bits)

v -

Valid Bit

This bit indicates that the contents of its base address register and address mask register pair are valid. The programmed chip selects do not assert until the V-bit is set.

1

=

Contents valid

0= Contents not valid


4.3.4.2 ADDRESS MASK REGISTERS. There are four address mask registers in the chip-select submodule, one for each chip-select signal.

Address Mask 1 $040, $048, $050, $058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

I

AM31

I

AM30

I

AM29

I

AM28

I

AM27

I

AM26

I

AM25

I

AM24

I

AM23

I

AM22

I

AM21

I

AM20

I

AM191 AMI81 AMI71 AMI6

I

RESET:

U u u u u u u u u u u u u u u u

Supervisor Only

Address Mask 2 $042, $04A, $052,$05A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 I 0

I

AM5

I

AM14

I

AMI31 AM12

I

AMll

I

AM10

I

AM9

I

AM8

I

FCM31 FCM21 FCMl

I

FCMO

I

001

I

002

I

PSI

Ipso

RESET:

U U U U U U U U U U U U U U U U

U

=

Unaffected by reset

Supervisor Only

AM31-AM8 Address Mask Bits 31-8

The address mask field, the upper 24 bits of each address mask register, provides for masking any of the corresponding bits in the associated base address register. By masking the address bits independently, external devices of different size address ranges can be used. Any set bit masks the corresponding address bit. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time.

FCM3-FCMO Function Code Mask Bits 3-0

This field can be used to mask certain function code bits, allowing more than one address space type to be assigned to a chip select. Any set bit masks the corresponding function code bit.

DD1 ,DDO DSACK Delay Bits 1 and 0

This field determines the number of wait states added before DSACKx is returned for that entry. The port size field must be programmed for a DSACKx response, or the DD bits have no significance. Table 4-10 lists the encoding for the DD bits.

4-32 MC68340 USER'S MANUAL· MOTOROLA

Table 4-10. DD Encoding

001 000

0

0

1

1

0

1

0

1

Response

Zero Wait State

One Wait State

Two Wait States

Three Wait States

PS1, PSO Port Size Bits 1 and 0

This field determines whether a given chip select responds with DSACKx and, if so, what port size is returned. Table 4-11 lists the encoding for the PS bits.

Table 4-11. PS Encoding

PS1

0

0

1

1

PSO

0

1

0

Mode

Reserved

16-Bit Port

8-Bit Port

1 No DSACKx Response

An example of the address mask register for 128 kbytes in user space with a

16-bit port requiring one wait state is as follows:

Address Mask 1

=

$0001

Address Mask 2 = $FF15

4.3.5 External Bus Interface Control

The following paragraphs describe the registers that control the

I/O pins used with the external bus interface. Refer to the SECTION 3 BUS OPERATION for more information about the external bus interface. For a list of pin numbers used with port A and port B, see the pinout diagram in SECTION 12 ORDERING

INFORMATION AND MECHANICAL DATA. SECTION 2 SIGNAL DESCRIPTIONS shows a block diagram of the port control circuits.

MOTOROLA


4.3.5.1

PORT A PIN ASSIGNMENT REGISTER 1

(PPARA1). PPARA1 selects between an address and discrete I/O function for the port A pins. Any set bit defines the corresponding pin to be an

liD

pin, controlled by the port A data and data direction registers. Any cleared bit defines the corresponding pin to be an address bit as defined in the following register diagram. Bits set in this register override the configuration setting of PPARA2. The all-ones reset value of PPARA 1 configures it as an input port. This register can be read or written at any time.

PPARA1

$015

RESET:

1

Supervisor Only

4.3.5.2

PORT A PIN ASSIGNMENT REGISTER 2

(PPARA2). PPARA2 selects between an address and IACKx function for the port A pins. Any set bit defines the corresponding pin to be an IACKx output pin. Any cleared bit defines the corresponding pin to be an address bit as defined in the register diagram. Any set bits in PPARA 1 override the configuration set in PPARA2. Bit 0 has no function in this register because there is no level-zero interrupt. This register can be read or written at any time.

PPARA2

$017

RESET: o

Supervisor Only

The IACKx signals are asserted if a bit in PPARA2 is set and the CPU32 services an external interrupt at the corresponding level. IACKx signals have the same timing as address signals.

4-34


MOTOROLA

4.3.5.3 PORT A DATA DIRECTION REGISTER (DDRA). DDRA controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output. Any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O.

This register can be read or written at any time.

DDRA $013

7 6 5 4 3 2 t a

I

DD7

I

DD6

I

DD5

I

DD4

I

DD3

I

DD2

I

DDt

I

DDa

RESET: a

Supervisor/User

4.3.5.4 PORT A DATA REGISTER (PORTA). PORTA affects only pins configured as discrete I/O. A write to the port A data register is stored in the internal data latch, and, if any port A pin is configured as an output, the value stored for that bit is driven on the pin. A read of the port A data register returns the value at the pin only if the pin is configured as discrete input. Otherwise, the value read is the value stored in the internal data latch. This register can be read or written at any time.

PORTA $011

7

I

P7

RESET:

I

P6

I

P5

I

P4

I

P3

I

P2

I

Pt

I

PO

U

U

U U U

U

U u

Supervisor/User

4.3.5.5 PORT B PIN ASSIGNMENT REGISTER (PPARB). PPARB controls the function of each port B pin. Any set bit defines the corresponding pin to be an interrupt request or chip select as defined in Table 4-5. Any cleared bit defines the corresponding pin to be an I/O pin (or chip select if the FIRQ bit of the MCR is zero) controlled by the port B data and data direction registers. The MODCK signal has no function after reset. This register can be read or written at any time.

PPARB

$01F

RESET: t

Supervisor Only

MOTOROLA


4-35

4.3.5.6 PORT B DATA DIRECTION REGISTER (DDRB). DDRB controls the direction of the pin drivers when the pins are configured as I/O. Any set bit configures the corresponding pin as an output. Any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O.

This register can be read or written at any time.

·DDRB

$010

7 6 5 4 3 2 I 0

I

DD7

I

DD6

I

DD5

I

DD4

I

DD3

I

DD2

I

DDI

I

DDO

RESET: o

Supervisor/User

4.3.5.7 PORT B DATA REGISTER (PORTB, PORTB1). This is a single register that can be accessed at two different addresses. The port B data register affects only those pins configured as discrete I/O. A write is stored in the internal data latch, and, if any port B pin is configured as an output, the value stored for that bit is driven on the pin. A read of this register returns the value stored in the register only if the pin is configured as a discrete output. Otherwise, the value read is the value of the pin. This register can be read or written at any time.

PORTB, PORTB1

$019,01B

7

I

P7

RESET:

I

P6

I

P5

I

P4

I

P3

I

P2

I

PI

I

PO

U U U U U U

U u

Supervisor/User

4-36


SECTION 5

CPU32

The CPU32, the first-generation instruction processing module of the M68300

Family, is based on the industry-standard MC68000 core processor. It has many features of the MC68010 and MC68020 as well as unique features suited for high-performance controller applications. The CPU32 provides a significant performance increase over the MC68000 CPU, yet maintains source code and binary code compatibility with the M68000 Family.

5.1 OVERVIEW

The CPU32 is designed to interface to the intermodule bus (1MB), allowing interaction with other 1MB submodules. In this manner, integrated processors can be developed that contain useful peripherals on-chip. This integration provides high-speed accesses among the 1MB submodules, increasing system performance.

Another advantage of the CPU32 is low power consumption. The CPU32 is implemented in high-speed complementary metal-oxide semiconductor

(HCMOS) technology, providing low power use during normal operation. During periods of inactivity, the low-power stop (LPSTOP) instruction can be executed, shutting down the CPU32 and other 1MB submodules, greatly reducing power consumption.

Ease of programming is an important consideration when using a microcontroller. The CPU32 instruction format reflects a predominate register-memory interaction philosophy. All data resources are available to all operations that require them. The programming model includes eight multifunction data registers and seven general-purpose addressing registers. The data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. Address manipulation is supported by word and long-word operations. Although the program counter (PC) and stack pointers ·(SP) are special-purpose registers, they are also available for most data addressing activities. Ease of program checking and diagnosis is enhanced by trace and trap capabilities at the instruction level.

MOTOROLA


As controller applications become more complex and control programs become larger, high-level language (HLL) will become the system designer's choice in programming languages. HLL aids in the rapid development of complex algorithms with less error, and is readily portable. The CPU32 instruction set will efficiently support HLL.

5.1.1 Features

Features of the CPU32 are as follows:

• Fully Upward-Object-Code Compatible with M68000 Family

• Virtual Memory Implementation

• Loop Mode of Instruction Execution

• Fast Multiply, Divide, and Shift Instructions

• Fast Bus Interface with Dynamic Bus Port Sizing

• Improved Exception Handling for Controller Applications

• Additional Addressing Modes

Scaled Index

Address Register Indirect with Base Displacement and Index

Expanded PC Relative Modes

32-Bit Branch Displacements

• Instruction Set Additions

High-Precision Multiply and Divide

Trap On Condition Codes

Upper and Lower Bounds Checking

• Enhanced Breakpoint Instruction

• Trace on Change of Flow

• Table Lookup and Interpolate Instruction

• Low-Power Stop Instruction

• Hardware Breakpoint Signal, Background Mode

• Fully Static Implementation

A block diagram of the CPU32 is shown in Figure 5-1. The major blocks depicted operate in a highly independent fashion that maximizes concurrency of operation while managing the essential synchronization of instruction execution and bus operation. The bus controller loads instructions from the data bus into the decode unit. The sequencer and control unit provide overall chip control, managing the internal buses, registers, and functions of the execution unit.

5-2


MOTOROLA

SEQUENCER

CONTROL

UNIT

INSTRUCTION

PREFETCH

AND

DECODE

DATA BUS

ADDRESS

BUS

BUS

CONTROL

BUS CONTROL

Figure 5-1. CPU32 Block Diagram

5.1.2 Virtual Memory

A system that supports virtual memory has a limited amount of high-speed physical memory that can be accessed directly by the processor and maintains an image of a much larger "virtual" memory on a secondary storage device.

When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The suspended access is then restarted or continued. The CPU32 uses instruction restart, which requires that only a small portion ofthe internal machine state be saved. After correcting the fault, the machine state is restored, and the instruction is refetched and restarted. This process is completely transparent to the application program.

5.1.3 Loop Mode Instruction Execution

The CPU32 has several features that provide efficient execution of program loops. One of these features is the DScc looping primitive instruction. To increase the performance of the CPU32, a loop mode has been added to the processor. The loop mode is used by any single-word instruction that does not change the program flow. Loop mode is implemented in conjunction with the

DScc instruction. Figure 5-2 shows the required form of an instruction loop for the processor to enter loop mode.

MOTOROLA


5-3

The loop mode is entered when the DBcc instruction is executed and the loop displacement is -4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches.

The termination condition and count are checked after each execution of the data operations of the looped instruction. The CPU32 automatically exits the loop mode on interrupts or other exceptions.

ONE-WORD INSTRUCTION

DBcc

DBcc DISPLACEMENT

$FFFC=-4

~ t - - -

Figure 5-2. Loop Mode Instruction Sequence

5.1.4 Vector Base Register

The vector base register (VBR) contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize the supervisor SP and the address used to initialize the PC.

The address of an interrupt exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; other numbers are supplied automatically by the processor. The processor multiplies the vector number by four to calculate the vector offset, which is added to the VBR. The sum is the memory address of the vector. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Refer to 5.6 EXCEPTION PROCESSING for additional details.

31

VECTOR BASE REGISTER (VBR)

5-4


5.1.5 Exception Handling

The processing of an exception occurs in four steps, with variations for different exception causes. During the first step, a temporary internal copy of the status register is made, and the status register is set for exception processing. During the second step, the exception vector is determined; during the third step, the current processor context is saved. During the fourth step, a new context is obtained, and the processor then proceeds with instruction processing.

Exception processing saves the most volatile portion of the current context by pushing it on the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes the status register and PC context of the processor when the exception occurred. To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored.

5.1.6 Addressing Modes

Addressing in the CPU32 is register oriented. Most instructions allow the results ofthe specified operation to be placed either in a register or directly in memory; this flexibility eliminates the need for extra instructions to store register contents in memory.

The seven basic addressing modes are as follows:

• Register Direct

• Register Indirect

• Register Indirect with Index

• Program Counter Indirect with Displacement

• Program Counter Indirect with Index

• Absolute

• Immediate

Included in the register indirect addressing modes are the capabilities to postincrement, predecrement, and offset. The PC relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, SP and/or PC. Addressing is explained fully in 5.3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES.


5.1.7 Instruction Set

The instruction set of the CPU32 is very similar to that of the MC68020 (see

Table 5-1). Two new instructions have been added to facilitate controller applications: low-power stop (LPSTOP) and table lookup and interpolate (TBL).

The following M68020 instructions are

not implemented

on the CPU32:

BFxxx Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO,

BFINS, BFSET, BFTST)

CALLM, RTM Call Module, Return Module

CAS, CAS2 Compare and Set (Read-Modify-Write Instructions) cpxxx Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc)

PACK, UNPK Pack, Unpack BCD Instructions

The CPU32 traps on unimplemented instructions or illegal effective addre~sing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements.

5.1.7.1 TABLE LOOKUP AND INTERPOLATE INSTRUCTIONS. To maximize throughput for real-time applications, reference data is often "particulated" and stored in memory for quick access. The storage of each data point would require an inordinate amount of memory. The table instruction requires only a sample of data points stored in the array, thus reducing memory requirements. Intermediate values are recovered with this instruction via linear interpolation. The results may be rounded by a round-to-nearest algorithm.

5.1.7.2 LOW-POWER STOP INSTRUCTION. In applications where power consumption is a consideration, the CPU32 forces the device into a low-power standby mode when immediate processing is not required. The low-power stop mode is entered by executing the LPSTOP instruction. The processor will remain in this mode until a user-specified (or higher) interrupt level or reset occurs.

5-6


Bcc

BCHG

BCLR

BGND

BKPT

BRA

BSET

BSR

BTST

CHK

CHK2

Mnemonic

ABCD

ADD

ADDA

ADDI

ADDQ

ADDX

AND

ANDI

ASL, ASR

CLR

CMP

CMPA

CMPI

CMPM

CMP2

DBcc

DIVS, DIVSL

DIVU, DIVUL

EOR

EORI

EXG

EXT, EXTB

ILLEGAL

JMP

JSR

LEA

LINK

LPSTOP

LSL, LSR

Description

Add Decimal with Extend

Add

Add Address

Add Immediate

Add Quick

Add with Extend

Logical AND

Logical AND Immediate

Arithmetic Shift Left and Right

Branch Conditionally

Test Bit and Change

Test Bit and Clear

Enter Background Mode

Breakpoint

Branch Always

Test Bit and Set

Branch to Subroutine

Test Bit

Check Register Against Bounds

Check Register against Upper and

Lower Bounds

Clear Operand

Compare

Compare Address

Compare Immediate

Compare Memory to Memory

Compare Register Against Upper and Lower Bounds

Test Condition, Decrement and

Branch

Signed Divide

Unsigned Divide

Logical Exclusive OR

Logical Exclusive OR Immediate

Exchange Registers

Sign Extend

Take Illegal Instruction Trap

Jump

Jump to Subroutine

Load Effective Address

Link and Allocate

Low-Power Stop

Logical Shift Left and Right

Table 5·1. Instruction Set Summary

Mnemonic Description

MOVE

MOVE CCR

MOVE SR

MOVE USP

MOVEA

MOVEC

MOVEM

MOVEP

Move

Move Condition Code Register

Move to/from Status Register

Move User Stack Pointer

Move Address

Move Control Register

Move Multiple Registers

Move Peripheral Data

MOVEQ

MOVES

Move Quick

Move Alternate Address Space

MULS, MULS.L Signed MUltiply

MULU, MULU.L Unsigned Multiply

NBCD

NEG

NEGX

NOP

NOT

Negate Decimal with Extend

Negate

Negate with Extend

No Operation

Ones Complement

OR

ORI

PEA

RESET

ROL, ROR

ROXL, ROXR

RTD

RTE

RTR

RTS

SBCD

Scc

STOP

SUB

SUBA

SUBI

SUBQ

SUBX

SWAP

Logical Inclusive OR

Logical Inclusive OR Immediate

Push Effective Address

Reset External Devices

Rotate Left and Right

Rotate with Extend Left and Right

Return and Deallocate

Return from Exception

Return and Restore Codes

Return from Subroutine

Subtract Decimal with Extend

Set Conditionally

Stop

Subtract

Subtract Address

Subtract Immediate

Subtract Quick

Subtract with Extend

Swap Register Words

TAS

TBLS,TBLSN

Test Operand and Set

Table Lookup and Interpolate

(Signed)

TBLU, TBLUN Table Lookup and Interpolate

(Unsigned)

TRAP

TRAPcc

TRAPV

TST

Trap

Trap Conditionally

Trap on Overflow

Test Operand

UNLK Unlink

MOTOROLA


5-7

5.1.8 Processing States

The processor is always in one of four processing states: normal, exception, halted, or background. The normal processing state is that associated with instruction execution; the bus is used to fetch instructions and operands and to store results. The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally generated explicitly by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. The halted processing state is an indication of catastrophic hardware failure. For example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. The background processing state is initiated by breakpoints, execution of special instructions, or a double bus fault. Background processing allows interactive debugging of the system via a simple serial interface. Refer to 5.5 PROCESSING STATES for details.

5.1.9 Privilege States

The processor operates at one of two levels of privilege user or supervisor.

The supervisor level has higher privileges than the user level. Not all instructions are permitted to execute in the lower privileged user level, but all instructions are available at the supervisor level. This scheme allows the supervisor to protect system resources from uncontrolled access. The processor uses the privilege level indicated by the S bit in the status register to select either the user or supervisor privilege level and either the user stack pointer (USP) or supervisor stack pointer (SSP) for stack operations.

5.2 ARCHITECTURE SUMMARY

The CPU32 architecture includes several important features that provide both power and versatility to the user. The CPU32 is source and object code compatible with the M68000 and MC6801 O. All user state programs can be executed unchanged.

The major CPU32 features are as follows:

• 32-Bit Internal Data Path and Arithmetic Hardware

• 32-Bit Address Bus Supported by 32-Bit Calculations

• Rich Instruction Set

• Eight 32-Bit General-Purpose Data Registers

5-8


• Seven 32-Bit General-Purpose Address Registers

• Separate User and Supervisor Stack Pointers

• Separate User and Supervisor State Address Spaces

• Separate Program and Data Address Spaces

• Many Data Types

• Flexible Addressing Modes

• Full Interrupt Processing

• Expansion Capability

5.2.1

Programming Model

The programming model of the CPU32 consists of two groups of registers: user model and supervisor model that correspond to the user and supervisor privilege levels. Executing at the user privilege level, user programs can only use the registers of the user model. Executing at the supervisor level, system software can use both the control registers of the supervisor level 'and the user model registers to perform supervisor functions.

As shown in the programming models (see Figures 5-3 and 5-4), the CPU32 has 16 32-bit general-purpose registers, a 32-bit program counter, one 32-bit supervisor stack pointer, a 16-bit status register, two 3-bit alternate function code registers, and a 32-bit vector base register. The user programming model remains unchanged from previous M68000 Family microprocessors. The supervisor programming model, which supplements the user programming model, is used exclusively by the CPU32 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the CPU32. All application software, written to run at the nonprivileged user level, migrates to the CPU32 from any M68000 platform without modification.


5-9

5-10

I

31

I

31

31

31

16 15

16 15

16 15

I

8 7

15 8 7

~-----------,

0

04

05

06

07

DO

01

02

03

DATA REGISTERS

0

AO

A1

A2

A3

A4

A5

A6

ADDRESS REGISTERS

0

I

A7 (USP) USER STACK POINTER

0

I

PC PROGRAM COUNTER

0

I

CCR CONDITION CODE

REGISTER

Figure 5-3. User Programming Model

I

31 16 15

I

0

I

A7' (SSP) SUPERVISOR STACK

POINTER

31

I

15

I

87 0

I

(CCR)

I

SR STATUS REGISTER

0

I

VBR VECTOR BASE

REGISTER

31

2 0

~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-a

SFC

DFC

ALTERNATE

FUNCTION CODE

REGISTERS

Figure 5-4. Supervisor Programming Model Supplement


MOTOROLA

5.2.2 Registers

Registers 07-00 are used as data registers for bit, byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A6-AO and the user and supervisor stack pointers are address registers that may be used as software stack pointers or base address registers. Register A7 (shown as A7 and A7' in Figures 5-3 and 5-4) is a register designation that applies to the user stack pointer in the user privilege level and to the supervisor stack pointer in the supervisor privilege level. In addition, the address registers may be used for word and long-word operations. All 16 general-purpose registers (07-00,

A7-AO) may be used as index registers.

The program counter (PC) contains the address of the next instruction to be executed by the CPU32. Ouring instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate.

The status register (SR) stores the processor status (see Figure 5-5). The SR contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero (Z), overflow (V), and carry (C).

The user byte containing the condition codes is the only portion of the SR information available in the user privilege level; it is referenced as the condition code register (CCR) in user programs. In the supervisor privilege level, software can access the full status register, including the interrupt priority mask (three bits), as well as additional control bits. These bits put the processor in one of two trace modes (T1, TO) and in user or supervisor privilege level (S).

SYSTEM BYTE

USER BYTE

(CONDITION CODE REGISTER)

SUPERVISORAJSER

STATE

NEGATIVE

ZERO

OVERFLOW

CARRY

Figure 5-5. Status Register

The vector base register (VBR) contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table.

MOTOROLA


5-11

Alternate function code registers (SFC and DFC) contain 3-bit function codes.

Function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces. Function codes are automatically generated by the processor to select address spaces for data and program at the user and supervisor privilege levels and to select a CPU address space used for processor functions (such as breakpoint and interrupt acknowledge cycles). Registers SFC and DFC are used by the MOVE instructions to explicitly specify the function codes of the memory address.

5.2.3 Data

Types

Six basic data types are supported:

• Single Bits

• Binary-Coded Decimal (BCD) Digits

• Byte Integers (8 bits)

• Word Integers (16 bits)

• Long-word Integers (32 bits)

• Quad-Word Integers (64 bits)

5.2.3.1 ORGANIZATION IN REGISTERS. The eight data registers can store data operands of 1, 8, 16, 32, and 64 bits and addresses of 16 or 32 bits. The seven address registers and the two stack pointers are used for address operands of

16 or 32 bits. The PC is 32 bits wide.

5.2.3.1.1 Data Registers. Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word operands, the low-order 16 bits, and long-word operands, the entire 32 bits. When a data register is used as either a source or destination operand, only the appropriate low-order byte or word (in byte or word operations, respectively) is used or changed; the remaining high-order portion is neither used nor changed. The least significant bit (LSB) of a longword integer is addressed as bit 0, and the most significant bit (MSB) is addressed as bit 31. Figure 5-6 shows the organization of various types of data in the data registers.

Quad-word data consists of two long words: for example, the product of 32bit multiply or the quotient of 32-bit divide operations (signed and unsigned).

Quad words may be organized in any two data registers without restrictions on order or pairing. There are no explicit instructions for the management of this data type; however, the MOVEM instruction can be used to move a quad word into or out of the registers.

5-12


BIT (O.:;MODULO (OFFSET)<31. OFFSET OF O=MSB

31 30

IMSB I

BYTE

31

HIGH-ORDER BYTE

24 23

MIDDLE HIGH BYTE

16 15

MIDDLE LOW BYTE

16-BIT WORD

31 16 15

HIGH-ORDER WORD

LOW-ORDER BYTE

LOW-ORDER WORD

I LSB

I

LONG WORD

31

LONG WORD

QUAD WORD

63 62

IMSB

I

31

ANY Ox

32

ANY Ox

I LSB

I

Figure 5-6. Data Organization in Data Registers

BCD data represents decimal numbers in binary form. Although many BCD codes have been devised, the BCD instructions of the M68000 Family support formats in which the four LSBs consist of a binary number having the numeric value ofthe corresponding decimal number. In this BCD format, a byte contains one digit; the four LSBs contain the binary value, and the four MSBs are undefined. ABCD, SBCD, and NBCD operate on two BCD digits which are manually packed into a single byte.

5.2.3.1.2 Address Register. Each address register and stack pointer is 32 bits wide and holds a 32-bit address. Address registers cannot be used for byte-sized operands. Therefore, when an address register is used as a source operand, either the low-order word or the entire long-word operand is used, depending upon the operation size. When an address register is used as the destination operand, the entire register is affected, regardless of the operation size. If the source operand is a word size, it is first sign extended to 32 bits, and then used in the operation to an address register destination. Address registers are used primarily for addresses and to support address computation. The instruction set includes instructions that add to, subtract from, compare, and move the contents of address registers. Figure 5-7 shows the organization of addresses in address registers.

MOTOROLA


5-13

31

31

16 15

SIGN EXTENDED 16-BIT ADDRESS OPERAND

FULL 32-BIT ADDRESS OPERAND

Figure 5-7. Address Organization in Address Registers

5.2.3.1.3 Control Registers. The control registers described in this section contain control information for supervisor functions and vary in size. With the exception of the user portion of the SR (CCR), they are accessed only by instructions at the supervisor privilege level.

The SR shown in Figure 5-5 is

16 bits wide. Only

11 bits of the SR are defined; all undefined values are reserved by Motorola for future definition. The undefined bits are read as zeros and should be written as zeros for future compatibility. The lower byte of the SR is the CCR. Operations to the CCR can be performed at the supervisor or user privilege level. All operations to the SR and CCR are word-size operations, but for all CCR operations, the upper byte is read as all zeros and is ignored when written, regardless of privilege level.

The alternate function code registers (SFC and DFC) are 32-bit registers with only bits 2-0 implemented that contain the address space values (FC2-FCO) for the read or write operand of the MOVES instruction. The MOVEC instruction is used to transfer values to and from the alternate function code registers.

These are long-word transfers; the upper 29 bits are read as zeros and are ignored when written.

5.2.3.2 Organization in Memory. Memory is organized on a byte-addressable basis in which lower addresses correspond to higher order bytes. The address,

N, of a long-word data item corresponds to the address of the most significant byte of the highest order word. The lower order word is located at address

N

+

2, leaving the least significant byte at address N

+

3 (see Figure 5-3). The.

CPU32 requires long-word and word data as well as instruction words to be aligned on word boundaries (see Figure 5-8). Data misalignment is not supported.

5-14


BIT DATA

1 BYTE=8 BITS

I I

INTEGER DATA

1 BYTE = 8 BITS

15

MSB

MSB

BYTE 0

BYTE 2

LSB MSB

LSB MSB

WORD = 16 BITS

BYTE 1

BYTE 3

15

MSB

MSB

MSB

WORD 0

WORD 1

WORD 2

LONG WORD = 32 BITS

15

MSB

MSB

MSB

LONG WORD 0 (HIGH ORDER)

LONG WORD 0 (LOW ORDER)





AODRESS

1 ADDRESS = 32 BITS

15

MSB

MSB

MSB

ADDRESS 0 (HIGH ORDER)

ADDRESS 0 (LOW ORDER)


AODRESS 1 (LOW ORDER)


ADDRESS 2 (LOW ORDER)

Most Significant Bit

LSB = Least Significant Bit

15 12 11

MSD

MSD

BCDO

BCD4

MSD= Most Significant Digit

LSD = Least Significant Digit

BCDI

BCD5

DECIMAL DATA

BCD DIGITS = 1 BYTE

8 7

LSD MSD

LSD MSD

BCD2

BCD6

4 3

Figure

5-8.

Memory Operand Addressing

LSB

LSB

LSB

LSB

LSB

BCD3

BCD7

LSD

LSD

LSB

LSB

LSB

LSB

LSB

LSB

MOTOROLA MC68340 USER'S

MANUAL

5-15

5.3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES

The addressing mode of an instruction can specify the value of an operand

(with an immediate operand), a register that contains the operand (with the register direct addressing mode), or how the effective address (EA) of an operand in memory is derived.

Figure 5-9 shows the general format of the single EA instruction operation word. The EA field specifies the addressing mode for an operand that can use one of the numerous defined modes. The designation is composed of two 3bit fields: mode and register. The value in the mode field selects one mode or a set of addressing modes. The register field specifies a register for the mode or a submode for modes that do not use registers.

15 14 13 12 11 10 4 2

EFFECTIVE ADDRESS

MODE REGISTER

Figure 5-9. Single EA Instruction Operation Word

Many instructions imply the addressing mode for one of the operands. The formats of these instructions include appropriate fields for operands that use only one addressing mode.

The EA field may require additional information to fully specify the operand address. This additional information, called the EA extension, is contained in an additional word or words and is considered part of the instruction. Refer to

5.3.4.4 EFFECTIVE ADDRESS ENCODING SUMMARY for a description of the extension word formats.

When the addressing mode uses a register, the register field of the operation word specifies the register to be used. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used.

5.3.1 Program and Data References

An M68000 Family processor separates memory references into two classes, each with a complete logical address range. The first class is program references, which includes primarily references to opcodes and extension words.

The other class is data references. Operand reads are from the data space with two exceptions: 1) immediate operands embedded in the instruction stream


MOTOROLA

and 2) operands addressed relative to the current program counter. Operands satisfying either of these two exceptions are classified as program space references. All operand writes are to data space.

5.3.2

Notation Conventions

EA-Effective address

An-Address register n

Example: A3 is address register 3

Dn-Data register n

Example: D5 is data register 5

Rn-Any register, data or address

Xn.SIZE*SCALE -

Index register n (data or address),

Index size (W for word, L for long word),

Scale factor (1, 2, 4, or 8 for none, word, long-word, or quad-word scaling)

PC-Program counter

SR-Status register

SP-Stack pointer

CCR-Condition code register

USP-User stack pointer

SSP-Supervisor stack pointer dn-Displacement value, n bits wide bd-Base displacement

L-Long-word size

W-Word size

B-Byte size

O-Identify an indirect address in a register


5-17

5.3.3 Implicit Reference

Some instructions make implicit reference to the program counter, the system stack pointer, the user stack pointer, the supervisor stack pointer, or the status register. Table 5-2 enumerates these instructions and the registers involved:

Table 5-2. Implicit Reference Instructions

Instruction

ANDI to CCR

ANDI to SR

BRA

BSR

CHK (exception)

CHK2 (exception)

DBcc

DIVS (exception)

DIVU (exception)

EORI to CCR

EORI to SR

JMP

JSR

LINK

LPSTOP

MOVE CCR

MOVE SR

MOVE USP

ORI to CCR

ORI to SR

PEA

RTD

RTE

RTR

RTS

STOP

TRAP (exception)

TRAPV (exception)

UNLK

PC,SP

SP

SR

SR

SR

USP

SR

SR

SP

PC,SP

PC,SP,SR

PC,SP,SR

PC,SP

SR

Implicit Registers

SR

SR

PC

PC,SP

SSP,SR

SSP,SR

PC

SSP,SR

SSP,SR

SR

SR

PC

SSP,SR

SSP, SR

SP


5.3.4 Effective Address

Most instructions specify the location of an operand by a field in the operation word called an EA field. The EA is composed of two 3-bit subfields: mode specification field and register specification field. Each of the address modes is selected by a particular value in the mode specification subfield of the EA.

The EA field may require further information to fully specify the operand. This information, called the EA extension, is in a following word or words and is considered part of the instruction (see 5.3.1 Program and Data References).

5.3.4.1 REGISTER DIRECT MODE. These EA modes specify that the operand is in one of the 16 multifunction registers.

5.3.4.1.1 Data Register Direct. In the data register direct mode, the operand is in the data register specified by the EA register field.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

DATA REGISTER:

NUMBER OF EXTENSION WORDS:

EA

=

On

On

~ n

On

0

-----..t'l

~

'-_ _ _ _ _

0

5.3.4.1.2 Address Register Direct. In the address register direct mode, the operand is in the address register specified by the EA register field.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

DATA REGISTER:


EA.

An

001 n

An

An---~~I

0

OPERAND

I

' - - - - - - - - - - - - - - '

5.3.4.2 MEMORY ADDRESSING MODES. These EA modes specify the address of the memory operand.


5-19

5.3.4.2.1 Address Register Indirect. In the address register indirect mode, the operand is in memory, and the address of the operand is in the address register specified by the register field.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

ADDRESS REGISTER:

EA-(An)

(An)

010 n

An

31

MEMORY ADDRESS

0

31

MEMORY ADDRESS:

NUMBER OF EXTENSION WORDS: 0

OPERAND

5.3.4.2.2 Address Register Indirect with Postincrement. In the address register indirect with postincrement mode, the operand is in memory, and the address of the operand is in the address register specified by the register field. After the operand address is used, it is incremented by one, two, or four, depending on the size of the operand: byte, word, or long word. If the address register is the stack pointer and the operand size is byte, the address is incremented by two rather than one to keep the stack pointer aligned to a word boundary.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

ADDRESS REGISTER:

OPERAND LENGTH ( 1,2, OR 4):

MEMORY ADDRESS:


EA = (An)

An =An +SIZE

(An) +

011 n

An

~

31

0

31

MEMORY ADDRESS

OPERAND

5.3.4.2.3 Address Register Indirect with Predecrement. In the address register indirect with predecrement mode, the operand is in memory, and the address of the operand is in the address register specified by the register field. Before the operand address is used, it is decremented by one, two, or four, depending on the operand size: byte, word, or long word. If the address register is the stack pointer and the operand size is byte, the address is decremented by two rather than one to keep the stack pointer aligned to a word boundary.

5-20


MOTOROLA

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

ADDRESS REGISTER:

OPERAND LENGTH (1, 2, OR 4):

MEMORY ADDRESS:


An .. An-SIZE

EA-(An)

-(An)

100 n

A n - -_ _

31

31

OPERAND

5.3.4.2.4 Address Register Indirect with Displacement. In the address register indirect with displacement mode, the operand is in memory. The address of the operand is the sum of the address in the address register plus the signextended 16-bit displacement integer in the extension word. Displacements are always sign extended to 32 bits before being used in EA calculations.

EA .. (An)

+ d16

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

ADDRESS REGISTER:

DISPLACEMENT:

[

31

MEMORY ADDRESS:


(d16 An)

101 ' n

31 o

An----~

MEMORY ADDRESS

~---------~----------~

~~~D~

=

L . . . -_ _ o

31

OPERAND

5.3.4.2.5 Address Register Indirect with Index (8-Bit Displacement). This mode requires one extension word that contains the index register indicator and an

8-bit displacement. The index register indicator includes size and scale information. In this mode, the operand is in memory. The address of the operand is the sum of the contents of the address register, the sign-extended displacement value in the low-order eight bits of the extension word, and the signextended contents of the index register (possibly scaled). The user must specify the displacement, the address register, and the index register in this mode.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

ADDRESS REGISTER:

DISPLACEMENT:

INDEX REGISTER:

31

EA

= (An) +

(Xn-SCALE) + da

(da.An. SIZE-SCALE)

110 n

31

An----~

MEMORY ADDRESS

~------------------~--~

SI~ EEE~E~

_

SIGN-EXTENDED VALUE

I------~ o

SCALE:

MEMORY ADDRESS:


SCALE VALUE

31

OPERAND


This address mode can have either of two different formats of extension. The brief format requires one word of extension and provides fast indexed addressing; the full format provides a number of options in size of displacements.

Both formats use an index operand. The address of the operand is the sum of the address in the address register, the sign-extended displacement integer in the low-order eight bits of the extension word, and the index operand. The reference is classed as a data reference, except for the JMP and JSR instructions. The index operand is specified IIRi.sz*scl" ..

IIRi" specifies a general data or address register to be used as the index register.

The index operand is derived from the index register. The index register is a data register if bit [15]

=

0 in the first extension word and is an address register if bit [15]

=

1. The register number of the index register is given by bits [14: 12] of the extension word.

The term

I I

SZ"

refers to index size and may be either:

II

W" or ilL". Index size is given by bit [11] of the extension word; if bit [11]

=

0, the index value is the sign-extended low-order word integer of the index register ("W"); if bit [11] = 1, the index value is the long-word integer in the index register ("L").

The term "scl" refers to index scale selection and may be 1, 2, 4, or 8. The index value is scaled according to the scaling selection in bits [10:9] to derive the index operand. Scale selections 00, 01, 10, or 11 select scaling of the index value by 1, 2, 4, or 8, respectively.

5.3.4.2.6 Address Register Indirect with Index (Base Displacement). This mode requires an index register indicator and an optional 16- or 32-bit sign-extended base displacement. The index register indicator includes size and scale information. In this mode, the operand is in memory. The address of the operand is the sum of the contents of the address register, the scaled contents of the sign-extended index register, and the base displacement.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

PROGRAM COUNTER:

EA

=

(An) + (Xn'SCALE) +

(bd, An, Xn. SIZ~'SCALE) bd

~10

An

- - - - > l MEMORY ADDRESS

31

BASE DISPLACEMENT:

SIGN:EXTENDED VALUE

31

INDEX REGISTER: SIGN-EXTENDED VALUE

SCALE:

MEMORY ADDRESS:

NUMBER OF EXTENSION WORDS: 1,2,OR3

SCALE VALUE

31

OPERAND

MOTOROLA

5-22


5.3.4.3 SPECIAL ADDRESSING MODES. These special addressing modes do not use the register field to specify a register number but rather to specify a submode.

5.3.4.3.1 Program Counter Indirect with Displacement. In this mode, the operand is in memory. The address of the operand is the sum of the address in the program counter and the sign-extended 16-bit displacement integer in the

ex-

tension word. The value in the program counter is the address of the extension word. The reference is a program space reference and is only allowed for read accesses.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

PROGRAM COUNTER:

EA = (PC) + d16

(d16. PC)

111

010

31

ADDRESS OF EXTENSION WORD o

DISPLACEMENT:

31

~ ~I~ E~E~E~

31 o

MEMORY ADDRESS:


OPERAND

5.3.4.3.2 Program Counter Indirect with Index (8-Bit Displacement). This mode is similar to the mode described in 5.3.4.2.5 Address Register Indirect with

Index (8-Bit Displacement)' but the program counter is used as the base register.

The operand is in memory. The address ofthe operand is the sum ofthe address in the program counter, the sign-extended displacement integer in the lower eight bits of the extension word, and the sized, scaled, and sign-extended index operand. The value in the program counter is the address of the extension word. This reference is a program space reference and is only allowed for reads. The user must include the displacement, the program counter, and the index register when specifying this addressing mode.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

PROGRAM COUNTER:

DISPLACEMENT:

~

31

INDEX REGISTER:

SCALE:

MEMORY ADDRESS:


EA - (PC) + (Xn) +da

~~~.pc.

Xn.

SIZE'SCALE)

011

~31--------------=,

ADDRESS OF EXTENSION WORD

E~TENDE~

_ t-----~ o

SIGN-EXTENDED VALUE

SCALE VALUE

31

OPERAND

MOTOROLA


5-23

5.3.4.3.3 Program Counter Indirect with Index (Base Displacement). This mode is similar to the mode described in 5.3.4.2.6 Address Register Indirect with

Index (Base Displacement), but the program counter is used as the base register. It requires an index register indicator and an optional 16- or 32-bit signextended base displacement. The operand is in memory. The address of the operand is the sum of the contents of the program counter, the scaled contents of the sign-extended index register, and the base displacement. The value of the program counter is the address of the first extension word. The reference is a program space reference and is only allowed for read accesses.

In this mode, the program counter, the index register, and the displacement are all optional. However, the user must supply the assembler notation "ZPC"

(zero value is taken for the program counter) to indicate that the program counter is not used. This scheme allows the user to access the program space without using the program counter in calculating the EA. The user can access the program space with a data register indirect access by placing ZPC in the instruction and specifying a data register (Dn) as the index register.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

PROGRAM COUNTER:

BASE DISPLACEMENT:

INDEX REGISTER:

31

31

SCALE:

MEMORY ADDRESS:


EA .. (PC)

+

(Xn)

+ bd

(bd, PC, Xn. SIZE'SCALE)

SIGN-EXTENDED VALUE

SIGN-EXTENDED VALUE

SCALE VALUE

31

1,2,OR3

ADDRESS OF EXTENSION WORD o o

OPERAND

5.3.4.3.4 Absolute Short Address. In this addressing mode, the operand is in memory, and the address of the operand is in the extension word. The 16-bit address is sign extended to 32 bits before it is used.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

EXTENSION WORD:

MEMORY ADDRESS:


EAGIVEN

(xxx).w

----

31

~= ~I~E~~E~

15

I

0

MEMORY ADDRESS 0

I

31

OPERAND

MOTOROLA

5-24


5.3.4.3.5 Absolute Long Address. In this mode, the operand is in memory, and the address of the operand occupies the two extension words following the instruction word in memory. The first extension word contains the high-order part of the address; the low-order part of the address is the second extension word. .

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:

FI RST EXTENSION WORD:

SECOND EXTENSION WORD:

EAGIVEN

(xxx).L

111

001

15

ADDRESS HIGH

0

15

31

CONCATENATION

31

MEMORY ADDRESS:

NUMBER OF EXTENSION WORDS: 2

OPERAND

5.3.4.3.6 Immediate Data. In this addressing mode, the operand is in one or two extension words:

Byte Operation

The operand is in the low-order byte of the extension word.

Word Operation

The operand is in the extension word.

Long-word Operation

The high-order 16 bits of the operand are in the first extension word; the low-order 16 bits are in the second extension word.

GENERATION:

ASSEMBLER SYNTAX:

MODE:

REGISTER:


OPERAND GIVEN

#XXX

111

100

10R2

5.3.4.4 EFFECTIVE ADDRESS ENCODING SUMMARY. Most of the addressing modes use one of the three formats shown in Figure 5-10. The single EA instruction is in the format of the instruction word. The encoding of the mode field of this word selects the addressing mode. The register field contains the general register number or a value that selects the addressing mode when the mode field contains '111 '. Some indexed or indirect modes use the instruction word followed by the brief format extension word. Other indexed or indirect modes consist of the instruction word and the full format of extension words.

The longest instruction for the CPU32 contains six extension words. It is a

MOVE instruction with full format extension words for both the source and destination EAs and with 32-bit base displacements for both addresses.

MOTOROLA


5-25

5-26

15 14 13 12

SINGLE EA INSTRUCTION FORMAT

11 10

EFFECTIVE ADDRESS

MODE REGISTER

15

DIA

14 13

REGISTER

12

BRIEF FORMAT EXTENSION WORD

11

WIL

10

SCALE

I

0 DISPLACEMENT

15 14 13

REGISTER

12

FULL FORMAT EXTENSION WORD(S)

11 10

1

BASE DISPLACEMENT (0, I, OR 2 WORDSl

IllS

Field

Instruction Register

Extensions Register

D/A

W/L

Scale

Definition

General Register Number

Index Register Number

Index Register Type

O=Dn

1 =An

Word/Long-Word Index Size

0= Sign-Extended Word

1 = Long Word

Scale Factor

00=1

01 =2

10=4

11 =8

Field

BS

IS

BD SIZE

I/IS*

Definition

Base Register Suppress

0= Base Register Added

1 = Base Register Suppressed

Index Suppressed

0= Evaluate and Add Index Operand

1 = Suppress Index Operand

Base Displacement Size

00 = Reserved

01 = Null Displacement

10 = Word Displacement

11 = Long Word Displacement

Index/Indirect Selection

Indirect and Indexing

Operand Determined in Conjunction with Bit 6, Index Suppress

**Memory indirect addressing will cause illegal instruction trap; must be=OOO if IS=1.

Figure 5-10. EA Specification Formats

Grouped according to the use of the mode, EA modes can be classified as follows:

Data A data addressing EA mode is one that refers to data operands.

Memory A memory addressing EA mode is one that refers to memory operands.

Alterable An alterable addressing EA mode is one that "refers to alterable

(writable) operands.

Control A control addressing EA mode is one that refers to memory operands without an associated size.


These categories are sometimes combined, forming new categories that are more restrictive. Two combined classifications are alterable memory or alterable data. The former category refers to those addressing modes that are both alterable and memory addresses; the latter category refers to addressing modes that are both alterable and data addresses. Table 5-3 lists the categories to which each of the EA modes belong.

Address Modes

Data Register Direct

Address Register Direct

Address Register Indirect

Address Register Indirect with Postincrement

Address Register Indirect with Predecrement

Address Register Indirect with Displacement

Address Register Indirect with

Index (S-Bit Displacement)

Address Register Indirect with

Index (Base Displacement)

Absolute Short

Absolute Long

Program Counter Indirect with Displacement

Program Counter Indirect with

Index (S-Bit Displacement)

Program Counter Indirect with

Index (Base Displacement)

Immediate

Table 5-3. EA Mode Categories

Mode Register Data Memory Control Alterable Assembler Syntax

000 reg. no. X

-

-

X Dn

001 reg. no.

-

-

-

X An

010 reg. no. X X X

X (An)

011 reg. no. X X X

(An)+

100 reg. no. X X

-

-

X

-(An)

101 reg. no. X X X X (d16,An)

110 reg. no.

X

110 reg. no. X

111

111

000

001

X

X

111

111

111

111

010

011

011

100

X

X

X

X

X

X

X

X

-

-

-

X

X

X

X

X

X

X

-

X

X

X

-

X

X

X

X

X

(ds,An,Xn)

(bd,An,Xn)

(xxx).W

(xxx).L

(d16,PC)

(ds,PC,Xn)

(bd,PC,Xn)

#(data)

5.3.5 Programming View of Addressing Modes

Extensions to the indexed addressing modes, indirection, and full 32-bit displacements provide additional programming capabilities for the CPU32,

MC68020, MC68030, and MC68040. The following paragraphs describe addressing techniques that exploit these capabilities and summarize the addressing modes from a programming point of view.

5.3.5.1 ADDRESSING CAPABILITIES. In the CPU32, MC68020, MC68030, and

MC68040, setting the base register suppress (85) bit in the full format extension word (see Figure 5-10) suppresses use ofthe base address register in calculating the EA, allowing any index register to be used in place of the base register. In this way, a data re_gister indirect form (On) can be used since any of the data

MOTOROLA


5-27

registers can be an index register. Additionally, since either a data register or an address register can be used, the mode could be called register indirect

(Rn). This addressing mode is an extension to the M68000 Family because the

CPU32, MC68020, MC68030, and MC68040 can use both the data registers and the address registers to address memory. The capability of specifying the size and scale of an index register (Xn.SIZE*SCALE) in these modes provides additional addressing flexibility. Using the SIZE parameter, either the entire contents of the index register can be used, or the least significant word can be sign extended to provide a 32-bit index value (refer to Figure 5-11) ..

DLWI

31 16 15 0 f'0..~'\."''''~'''~''~''~~'\.'''~D1

Figure 5-11. SIZE in the Index Selection

For the CPU32, MC68020, MC68030, and MC68040, the register indirect modes can be extended further. Since displacements can be 32 bits wide, they can represent absolute addresses or the results of expressions that contain absolute addresses. This scheme allows the general register indirect form to be (bd,Rn) or (bd,An,Rn) when the base register is not suppressed. Thus, an absolute address can be directly indexed by one or two registers (refer to Figure 5-12).

SYNTAX: (bd,An,Rn) bd

An

Rn

5-28

Figure 5-12. Absolute Address with Indexes

The indirect suppressed index register mode (see Figure 5-13) uses the contents of register An as an index to the pointer located at the address specified by the displacement. The actual data item is at the address in the selected pointer.


MOTOROLA

SIMPLE ARRAY

(SCALE-1)

SYNTAX: MOVE.W (AS,A6.L'SCAlE),(A7)

WHERE:

AS. ADDRESS OF ARRAY STRUCTURE

A6 • INDEX NUMBER OF ARRAY ITEM

A7. STACK POINTER

15

A6-1-_1/

RECORD OF 1 WORD

(SCAlE-2) o

RECORD OF 2 WORDS

(SCALE-4)

RECORD OF 4 WORDS

(SCALE=B)

2

NOTE: Regardless of array structure, software increments index to point to next record.

Figure 5-13, Addressing Array Items

Scaling provides an optional shifting of the value in an index register to the left by zero, one, two, or three bits before using it in the EA calculation (the actual value in the index register remains unchanged). This is equivalent to multiplying the register by one, two, four, or eight for direct subscripting into an array of elements of corresponding size using an arithmetic value residing in any of the 16 general-purpose registers. Scaling does not add to the EA

MOTOROLA


5-29

calculation time. However, when combined with the appropriate derived modes, scaling produces additional capabilities. Arrayed structures can be addressed absolutely and then subscripted; for example, (bd,Rn*SCALE). Optionally, an address register that contains a dynamic displacement can be included in the address calculation (bd,An,Rn*SCALE). Another variation that can be derived is (An,Rn*SCALE). In the first case, the array address is the sum of the contents of a register and a displacement (see Figure 5-13). In the second example, An contains the address of an array and Rn contains a subscript.

5.3.5.2 GENERAL ADDRESSING MODE SUMMARY. The addressing modes described in the previous paragraphs are derived from specific combinations of options in the indexing mode or a selection of two alternate addressing modes.

For example, the addressing mode called register indirect (Rn) assembles as the address register indirect if the register is an address register. If Rn is a data register, the assembler uses the address register indirect with index mode, using the data register as the indirect register, and suppresses the address register by setting the base suppress bit in the EA specification. Assigning an address register as Rn provides higher performance than using a data register as Rn. Another case is (bd,An), which selects an addressing mode based on the size of the displacement. If the displacement is 16 bits or less, the address register indirect with displacement mode (d16,An) is used. When a 32-bit displacement is required, the address register indirect with index (bd,An,Xn) is used with the index register suppressed.

It is useful to examine the derived addressing modes available to a programmer

(without regard to the CPU32 EA mode actually encoded) because the programmer need not be concerned about these decisions. The assembler can choose the more efficient addressing mode to encode.

5.3.6 M68000 Family Addressing Capability

Programs can be easily transported from one member of the M6S000 Family to another member in an upward compatible fashion. The user object code of each early member of the family is upward compatible with newer members and can be executed on the newer microprocessor without change. The address extension word(s) are encoded with information that allows the CPU32 to distinguish the new address extensions to the basic M6S000 Family architecture.

The address extension words for the MC6S000/MC6S00S1 MC6S01 0 and CPU321

MC6~020/MC6S030/MC6S040 microprocessors are shown in Figure 5-1'4.


MOTOROLA

MC68000/MC68008/MC68010

ADDRESS EXTENSION WORD

15

D/A

D/A:

W/L:

14 13

REGISTER

12 11 10

I

W/L

I

0

I

0

I

0

I o

=

Data Register Select

1

=

Address Register Select o

=

Word-Size Operation

1

=

Long-Ward-Size Operation

CPU32/MC68020/MC68030/MC68040

EXTENSION WORD

15

D/A

14 13 12 11 10

I

REGISTER

I

W/L

I

SCALE o

I

D/A:

0

=

Data Register Select

1

=

Address Register Select

W/L: 0

=

Word-Size Operation

1

=

Long-Word-Size Operation

SCALE: 00

=

Scale Factor 1 (Compatible with MC68000)

01

=

Scale Factor 2 (Extension to MC68000)

10

=

Scale Factor 4 (Extension to MC68000)

11

=

Factor 8 (Extension ta MC68000)

DISPLACEMENT INTEGER

DISPLACEMENT INTEGER

Figure 5-14. M68000 Family Address Extension Words

The encoding for SCALE used by the CPU32/MC68020/MC68030/MC68040 is a compatible extension of the M68000 architecture. A value of zero for SCALE is the same encoding for both extension words; thus, software that uses this encoding is both upward and downward compatible across all processors in the product line. However, the other values of SCALE are not found in both extension formats; therefore, while software can be easily migrated in an upward compatible direction, only nonscaled addressing is supported in a downward fashion. If the MC68000 were to execute an instruction that encoded a scaling factor, the scaling factor would be ignored and would not access the desired memory address.

The earlier microprocessors have no knowledge of the extension word formats implemented by newer processors, and, while they do detect illegal instructions, they do not decode invalid encodings of the extension words as exceptions.

MOTOROLA


5-31

5.3.7 Other Data Structures

In addition to supporting the array data structure with the index addressing mode, M68000 processors also support stack and queue data structures with the address register indirect postincrement and predecrement addressing modes. A stack is a last-in-first-out (LIFO); a queue is a first-in-first-out (FIFO) list. When data is added to a stack or queue, it is pushed onto the structure; when it is removed, it is 'popped' or pulled from the structure. The system stack is used implicitly by many instructions; user stacks and queues may be created and maintained through use of addressing modes.

5.3.7.1

SYSTEM STACK.

Address register 7 (A7) is the system stack pointer (SP).

The SP is either the supervisor stack pointer (SSP) or the user stack pointer

(USP), depending on the state of the S bit in the status register. If the S bit indicates the supervisor state, the SSP is the SP, and the USP cannot be referenced as an address register. If the S bit indicates the user state, the USP is the active SP, and the SSP cannot be referenced. Each system stack fills from high memory to low memory. The address mode - (SP) creates a new item on the active system stack, and the address mode (SP)

+ deletes an item from the active system stack.

The program counter is saved on the active system stack on subroutine calls and is restored from the active system stack on returns. However, during the processing of traps and interrupts, both the program counter and the status register are saved on the supervisor stack. Thus, the correct execution of the supervisor state code is not dependent on the behavior of user code, and user programs may use the USP arbitrarily.

To keep data on the system stack aligned properly, data entry on the stack is restricted so that data is always put in the stack on a word boundary. Thus, byte data is pushed on or pulled from the system stack in the high-order half of the word; the low-order half is unchanged.


MOTOROLA

5.3.7.2 USER STACKS. The user can implement stacks with the address register indirect with postincrement and predecrement addressing modes. With address register An (n

=

0-6), the user can implement a stack that is filled either from high to low memory or from low to high memory. Important considerations are as follows:

• Use the predecrement mode to decrement the register before its contents are used as the pointer to the stack.

• Use the postincrement mode to increment the register after its contents are used as the pointer to the stack.

• Maintain the SP correctly when byte, word, and long-word items are mixed in these stacks.

To implement stack growth from high to low memory, use - (An) to push data on the stack and (An)

+ to pull data from the stack.

For this type of stack, after either a push or a pull operation, register An points to the top item on the stack. This scheme is illustrated as follows: lOW MEMORY

(FREE)

An

~

TOP OF STACK

·

sonOM OF STACK

I

HIGH MEMORY

To implement stack growth from low to high memory, use (An)

+ to push data on the stack and - (An) to pull data from the stack.

In this case, after either a push or pull operation, register An points to the next available space on the stack. This scheme is illustrated as follows: lOW MEMORY sonOM OF STACK

I

An

~

TOP OF STACK

(FREE)

HIGH MEMORY

MOTOROLA


5.3.7.3 QUEUES. The user can implement queues with the address register indirect with postincrement or predecrement addressing modes. Using a pair of address registers (two of AO-A6), the user can implement a queue which is filled either from high to low memory or from low to high memory. Two registers are used because queues are pushed from one end and pulled from the other. One register, An, contains the Iput' pointer; the other register, Am, contains the

Iget'

pointer.

To implement growth of the queue from low to high memory, use (An)

+ to put data into the queue and (Am)

+ to get data from the queue.

After a Iput' operation, the IpUt' address register points to the next available space in the queue, and the unchanged

Iget'

address register points to the next item to be removed from the queue. After a

Iget'

operation, the

Iget'

address register points to the next item to be removed from the queue, and the unchanged IpUt' address register points to the next available space in the queue, which is illustrated as follows:

LOW MEMORY

LAST GET (FREE)

GET (Am) +

~

NEXT GET

.

L

PUT (An) + - - >

LAST PUT

(FREE)

HIGH MEMORY

~

To implement the queue as a circular buffer, the relevant address register should be checked and adjusted, if necessary, before performing the Iput' or

Iget'

operation. The address register is adjusted by subtracting the buffer length

(in bytes) from the register contents.

To implement growth of the queue from high to low memory, use - (An) to put data into the queue and - (Am) to get data from the queue.

After a IpUt' operation, the Iput' address register points to the last item placed in the queue, and the unchanged

Iget'

address register points to the last item removed from the queue. After a

Iget'

operation, the

Iget'

address register points to the last item removed from the queue, and the unchanged Iput' address register points to the last item placed in the queue, which is illustrated as follows:

MOTOROLA

5-34


PUT -(An)

--> lOW MEMORY

(FREE)

LAST PUT

NEXT GET

GET -(Am)

~

LAST GET (FREE)

HIGH MEMORY

To implement the queue as a circular buffer, the 'get' or 'put' operation should be performed first, and then the relevant address register should be checked and adjusted, if necessary. The address register is adjusted by adding the buffer length (in bytes) to the register contents.

5.4

INSTRUCTION SET

This subsection describes the set of instructions provided in the CPU32 and demonstrates their use. For a more detailed description of the instructions, refer to M68000 PM/AD,

Programmer's Reference Manual.

The CPU32 instructions include machine functions for all the following operations: o Data Movement o Arithmetic Operations o Logical Operations o Shifts and Rotates o Bit Manipulation o Conditionals and Branches o System Control

The large instruction set encompasses a complete range of capabilities and, combined with the enhanced addressing modes, provides a flexible base for program development.


5.4.1 M68000 Family Compatibility

It is the philosophy of the M68000 Family that all user-mode programs can execute unchanged on a more advanced processor and that supervisor-mode programs and exception handlers should require only minimal alteration.

The CPU32 can be thought of as an intermediate member of the M68000 Family.

Object code from an MC68000 or MC68010 may be executed on the CPU32, and many of the instruction and addressing mode extensions of the MC68020 are also supported.

5.4.1.1 NEW INSTRUCTIONS. Two instructions have been added to the M68000 instruction set for use in controller applications. These are the low-power stop

(LPSTOP) and the table lookup and interpolate (TBL) commands.

5.4.1.1.1 Low-Power Stop (LPSTOP). In applications where power consumption is a consideration, the CPU32 can force the device into a low-power standby mode when immediate processing is not required. The low-power mode is entered by executing the LPSTOP instruction. The processor remains in this mode until a user-specified or higher level interrupt or a reset occurs.

5.4.1.1.2 Table Lookup and Interpolate (TBL). To maximize throughput for realtime applications, reference data is often precalculated and stored in memory for quick access. The storage of sufficient data points can require an inordinate amount of memory. The TBL instruction uses linear interpolation to recover intermediate values from a sample of data points, thus conserving memory.

When the TBL instruction is executed, the CPU32 looks up two table entries bounding the desired result and performs a linear interpolation between them.

Byte, word, and long-word operand sizes are supported. The result is rounded according to the round-to-nearest algorithm. Optionally, byte and word results can be left unrounded and returned along with the fractional portion of the calculated result. Software can make use of this extra precision to reduce the cumulative error in complex calculations. See 5.4.5 Using the Table Instruction for examples.

5.4.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000

5-36


enhancements. See 5.6.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS for more details.

5.4.2 Instruction Format and Notation

All instructions consist of at least one word. Some instructions can have as many as seven words, as shown in Figure 5-15. The first word of the instruction, called the operation word, specifies the instruction length and the operation to be performed. The remaining words, called extension words, further specify the instruction and operands. These words may be immediate operands, extensions to the effective address mode specified in the operation word, branch displacements, bit number, special register specifications, trap operands, or argument counts.

15

OPERATION WORD

(ONE WORD, SPECIFIES OPERATION AND MODES!

SPECIAL OPERAND SPECIFIERS

(IF ANY, ONE OR TWO WORDS!

IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION

(IF ANY, ONE TO THREE WORDS!

DESTINATION EFFECTIVE ADDRESS EXTENSION

(IF ANY, ONE TO THREE WORDS!

Figure 5-15. Instruction Word General Format

Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways:

• Register Specification A register field of the instruction contains the number of the register.

• Effective Address An effective address field of the instruction contains address mode information.

.Implicit Reference The definition of an instruction implies the use of specific reg isters.

The register field within an instruction specifies the register to be used. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. See 5.3 DATA ORGANI-

ZATION AND ADDRESSING CAPABILITIES for detailed register information.

MOTOROLA


5-37

5-38

Except where noted, the following notations are used:

An = any address register, A7-AO

On = any data register, 07-00

Rn = any address or data register

CCR = condition 'code register (lower byte of status register) cc = condition codes from CCR

SR = status register

SP = active stack pointer

USP = user stack pointer

SSP = supervisor stack pointer

OFC = destination function code register

SFC = source function code register

Rc = control register (VBR, SFC, OFC) d = displacement; d16 is a 16-bit displacement

(ea) = effective address list = list of registers (for example, 03-00)

#(data) = immediate data; a literal integer label = assembly program label

[7] = bit 7 of an operand

[31 :24] = bits 31-24 of operand (high-order byte of a register)

X=extend (X) bit in CCR

N = negative (N) bit in CCR

V = overflow (V) bit in CCR

C=carry (C) bit in CCR

+

= arithmetic addition or postincrement

- = arithmetic subtraction or predecrement x = arithmetic multiplication

/ = arithmetic division or conjunction symbol

A = logical ANO

V = logical OR

(E)

= logical exclusive OR

Oc = data register 07-00 used during compare

Ou = 07-00 used during update

Or, Oq = data registers, remainder or quotient of divide

Oh, 01 = data registers, high- or low-order 32 bits of product

MSW = most significant word'

LSW = least significant word

FC = function code

{RIW} = read or write indicator

[An] = address extensions


In the description of an operation, a destination operand is placed to the right of source operands and is indicated by an arrow ( • ).

5.4.3

Instruction Summary

All CPU32 instructions are summarized in Table 5-4.

Opcode

ABCD

ADD

ADDA

ADDI

ADDQ

ADDX

AND

ANDI Immediate DataADestination • Destination

SourceACCR .CCR ANDI to CCR

ANDI to SR

If supervisor state the SourceASR • SR else TRAP

ASl,ASR Destination Shifted by (count) • Destination

Bcc

BCHG

BClR

BGND

BKPT

BRA

BSET

BSR

Table 5-4. Instruction Set Summary

Operation

Source1Q+Destination1Q+X. Destination

Source + Destination. Destination

Source + Destination. Destination

Immediate Data + Destination. Destination

Immediate Data + Destination. Destination

Source + Destination + X • Destination

SourceADestination • Destination

If (condition true) then PC + d • PC

-((number) of Destination) • Z;

-((number) of Destination) • (bit number) of Destination

-((bit number) of Destination) • Z; o •

(bit number) of Destination

If (background mode enabled) then enter background mode else FormaWector offset. - (SSP)

PC. -(SSP)

SR. -(SSP)

(Vector) • PC

Run breakpoint acknowledge cycle;

TRAP as illegal instruction

PC+d. PC

-((bit number) of Destination) • Z;

1 • (bit number) of Destination

SP-4. SP; PC. (SP); PC+d. PC

Syntax

ABCD Dy,Dx

ABCD - (Ay), - (Ax)

ADD (ea),Dn

ADD Dn,(ea)

ADDA (ea),An

ADDI #(data),(ea)

ADDQ #(data),(ea)

ADDX Dy,Dx

ADDX - (Ay), - (Ax)

AND (ea),Dn

AND Dn,(ea)

ANDI #(data),(ea)

ANDI #(data),CCR

ANDI #(data),SR

ASd DX,Dy

ASd #(data),Dy

ASd (ea)

Bce (label)

BCHG Dn,(ea)

BCHG #(data),(ea)

BClR Dn,(ea)

BClR #(data),(ea)

BGND

BKPT #(data)

BRA (label)

BSET Dn,(ea)

BSET #(data),(ea)

BSR (label)


Opcode

BTST

CHK

CHK2

CLR

CMP

CMPA

CMPI

CMPM

CMP2

DBcc

DIVS

DIVSL

DIVU

DIVUL

EOR

EORI

EORI to CCR

EORI to SR

EXG

Table 5-4. Instruction Set Summary (Continued)

Operation

- ((bit number) of Destination) • Z;

Syntax

BTST Dn,(ea)

BTST #(data),(ea)

CHK (ea),Dn

CHK2 (ea),Rn

If Dn

<

0 or Dn

>

Source then TRAP

If Rn

Rn

<

> lower bound or upper bound then TRAP o •

Destination

Destination Source. cc

Destination Source

Destination Immediate Data

Destination Source. cc

Compare Rn

Rn

< lower-bound or

> upper-bound and Set Condition Codes

If condition false then (Dn -1 • Dn;

If Dn

~

-1 then PC

+ d • PC)

Destination/Source. Destination

Destination/Source. Destination

Source EB Destination. Destination

Immediate Data EB Destination. Destination

Source EB CCR • CCR

CLR (ea)

CMP (ea),Dn

CMPA (ea),An

CMPI #(data),(ea)

CMPM (Ay)

+

,(Ax)

+

CMP2 (ea),Rn

DBcc Dn,(label)

DIVS.w (ea),Dn

DIVS.L (ea),Dq

32/16. 16r:16q

32/32.32q

DIVS.L (ea),Dr:Dq 64/32 • 32r:32q

DIVSL.L (ea),Dr:Dq 32/32. 32r:32q

DIVU.w (ea),Dn

DIVU.L (ea),Dq

32/16. 16r:16q

32/32.32q

DIVU.L (ea),Dr:Dq 64/32 • 32r:32q

DIVUL.L (ea),Dr:Dq 32/32. 32r:32q

EOR Dn,(ea)

EORI #(data),(ea)

EORI #(data),CCR

If supervisor state the Source EB SR • SR else TRAP

Rx ••

Ry

EORI #(data),SR

EXT

EXTB

Destination Sign-Extended. Destination

EXG DX,Dy

EXG Ax.Ay

EXG Dx.Ay

EXG Ay,Dx

EXT.W Dn extend byte to word

EXT.L Dn extend word to long word

EXTB.L Dn extend byte to long word

ILLEGAL ILLEGAL

SSP-2. SSP; Vector Offset. (SSP);

SSP-4. SSP; PC. (SSP);

SSp - 2 • SSP; SR • (SSP);

Illegal Instruction Vector Address. PC

JMP Destination Address. PC

JSR

LEA

SP-4. SP; PC. (SP)

Destination Address. PC

(ea). An

JMP (ea)

JSR (ea)

LEA (ea).An

5-40


MOTOROLA


Opcode Operation

LINK SP-4. SP; An • (SP)

SP. An, SP+d • SP

LPSTOP If supervisor state

Immediate Data. SR

Interrupt Mask. External Bus Interface (EBI)

STOP else TRAP

LSL,LSR Destination Shifted by (count) • Destination

Syntax

LINK An,#(displacement)

LSd

1

LSd

1

LSd

1

Dx,Dy

#(data),Dy

(ea)

MOVE (ea),(ea)

MOVEA (ea),An

MOVE CCR,(ea)

MOVE

MOVEA

MOVE from CCR

MOVE to CCR

MOVE from SR

Source. Destination

Source. Destination

CCR • Destination

Source. CCR

MOVE to SR

If supervisor state then SR • Destination else TRAP

If supervisor state then Source. SR else TRAP

MOVE

USP

MOVEC

MOVEM

MOVEP

If supervisor state then USP • An or An • USP else TRAP

If supervisor state then Rc • Rn or Rn • Rc else TRAP

Registers. Destination

Source. Registers

Source. Destination

MOVEQ

Immediate Data. Destination

MOVES If supervisor state then Rn • Destination [DFC] or Source [SFC] • Rn else TRAP

MULS Source x Destination. Destination

MOVE (ea),CCR

MOVE SR,(ea)

MOVE (ea),SR

MOVE USP,An

MOVE An,USP

MOVEC RC,Rn

MOVEC Rn,Rc

MOVEM register list,(ea)

MOVEM (ea),register list

MOVEP DX,(d,Ay)

MOVEP (d,Ay).Dx

MOVED #(data),Dn

MOVES Rn,(ea)

MOVES (ea),Rn

MULU

NBCD

NEG

NEGX

NOP

Source x Destination. Destination

O-(Destination1Q)-X. Destination

0- (Destination) • Destination

0- (Destination) - X • Destination

None

MULS.w (ea),Dn 16x 16.32

MULS,L (ea),DI 32x 32.32

MULS,L (ea),Dh:DI 32x32. 64

MULU.w (ea),Dn

16 x 16.32

MULU,L (ea),DI 32 x 32.32

MULU,L (ea),Dh:DI 32 x 32.64

NBCD (ea)

NEG (ea)

NEGX (ea)

NOP

MOTOROLA


5-41


Opcode

NOT

OR

Operation

-Destination. Destination

Source V Destination. Destination

. Syntax

NOT (ea)

OR (ea),Dn

OR Dn,(ea)

ORI #(data),(ea)

ORI #(data),CCR

ORI

ORI to CCR

ORI to SR

Immediate Data V Destination. Destination

Source V CCR • CCR

If supervisor state then Source V SR • SR else TRAP

PEA

RESET

Sp-4. SP; (ea). (SP)

If supervisor s~ then Assert RESET else TRAP

ROL,ROR Destination Rotated by (count) • Destination

ORI #(data),SR

PEA (ea)

RESET

ROXL,ROXR Destination Rotated with X by (count) • Destination

RTD

RTE

ROd

1

ROd

1

ROd

1

RX,Dy

#(data),Dy

(ea)

ROXd

1

ROXd

1

ROXd

1

DX,Dy

#(data),Dy

(ea)

RTD #(displacement)

RTE

RTR

RTS

SBCD

Scc

STOP

SUB

(SP). PC; SP+4+d .'SP

If supervisor state the (SP) • SR; SP + 2. SP; (SP) • PC;

SP+4. SP; restore state and deallocate stack according to (SP) else TRAP

(SP). CCR; SP+2. SP;

(SP) • PC; SP+4. SP

(SP). PC; SP+4. SP

Destination1Q - Source1Q - X • Destination

If Condition True then 1 s • Destination else Os • Destination

If supervisor state then Immediate Data. SR; STOP else TRAP

Destination - Source. Destination

RTR

RTS

SBCD DX,Dy

SBCD - (Ax), - (Ay)

Scc (ea)

STOP #(data)

SUBA

SUBI

SUBQ

SUBX

SWAP

TAS

Destination - Source. Destination

Destination -Immediate Data. Destination

Destination -Immediate Data. Destination

Destination - Source - X • Destination

Register [31 :16] •• Register [15:0]

Destination Tested. Condition Codes; 1 • bit 7 of Destination

SUB (ea),Dn

SUB Dn,(ea)

SUBA (ea),An

SUBI #(data),(ea)

SUBQ #(data),(ea)

SUBX DX,Dy

SUBX -(Axl.-(Ay)

SWAP Dn

TAS (ea)

5-42


MOTOROLA

Table 5·4. Instruction Set Summary (Concluded)

Opcode Operation Syntax

TBLS

TBLSN

ENTRY(n)+{(ENTRY(n+1)-ENTRY(n))*Dx[7:0]}/256. Dx

ENTRY(n)'256 + {(ENTRY(n + 1) - ENTRY(n))·Dx[7:0]} • Dx

TBLU ENTRY(n) + {(ENTRY(n + 1) - ENTRY(n))*Dx[7:0]}/256 • Dx TBLU.(size) (ea),Dx

TBLU.(size) Dym:Dyn, Dx

TBLUN ENTRY(n)'256 + {(ENTRY(n + 1) - ENTRY(n))'Dx[7:0]} • Dx TBLUN.(size) (ea),Dx

TBLUN.(size) Dym:Dyn,Dx

TRAP #(vector) TRAP SSP-2. SSP; Format/Offset. (SSP);

SSP-4. SSP; PC. (SSP); SSP-2. SSP;

SR. (SSP); Vector Address. PC

TRAPcc If cc then TRAP TRAPcc

TRAPcc.W #(data)

TRAPcc.L #(data)

TRAPV If V then TRAP

TBLS.(size) (ea), Dx

TBLS.(size) Dym:Dyn, Dx

TBLSN.(size) (ea),Dx

TBLSN.(size) Dym:Dyn, Dx

TST

UNLK

Destination Tested. Condition Codes

An. SP; (SP). An; SP+4. SP

TRAPV

TST (ea)

UNLK An

NOTE 1: d is direction, L or R.

The instructions form a set of tools to perform the following operations:

Data Movement

Integer Arithmetic

Logical

Shift and Rotate

Bit Manipulation

Binary-Coded Decimal Arithmetic

Program Control

System Control

The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development.

5.4.3.1 CONDITION CODE REGISTER. The condition code register portion of the status register contains five bits that indicate the result of a processor operation.

Table 5-5 lists the effect of each instruction on these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family to simplify programming techniques that use them. Refer to Table 5-9 as an example.

MOTOROLA


Table 5-5. Condition Code Computations

Operations

ABCD

ADD, ADDI, ADDQ

ADDX

AND, ANDI, EOR, EORI,

MOVEQ, MOVE, OR,

ORI, CLR, EXT, NOT,

TAS, TST

CHK

CHK2, CMP2

SUB, SUBI, SUBQ

SUBX

CMP, CMPI, CMPM

DIVS, DIVU

MULS, MULU

SBCD,NBCD

NEG

NEGX

ASL

ASL (r=O)

LSL, ROXL

LSR (r=O)

ROXL (r=O)

ROL

ROL (r=O)

ASR, LSR, ROXR

ASR, LSR (r=O)

X N

Z

V C Special Definition

* U

?

U

? C= Decimal Carry

Z=ZARmA ... ARO

-

* * *

? ? V = Sm A Dm A Rm V Sm A Dm A Rm

C = Sm A Dm V Rm A Dm V Sm A Rm

-

-

-

* *

? ? ?

V = Sm A Dm A Rm V Sm A Dm A Rm


Z = Z A Rm A ... A RO

*

* 0 0

-

-

* U U U

U

?

U

? Z = (R = LB) V (R = UB)

C = (LB

<

= UB) A (lR

<

LB) V (R

>

UB)) V

(UB

<

LB) A (R

>

UB) A (R

<

LB)

-

* * *

?

? V = Sm A Dm A Rm V Sm A Dm A Rm


-

* *

? ? ? V = Sm A Dm A Rm V Sm A Dm A Rm



-

* *

? ?

V = Sm A Dm A Rm V Sm A Dm A Rm


-

-

* *

?

0 V = Division Overflow

* *

?

0 V = Multiplication Overflow

* U

?

U

?

C = Decimal Borrow

Z = Z A Rm A ... A Ro

*

* *

? ? V = Om A Rm

C = Om V Rm

* *

? ? ?

V = Om A Rm

C = Om V Rm


* * *

? ? V = Om A (Om -1 V ... V Om - r) V Om A (OM -1

V ... +Om-r)

C = Om-r+1

-

-

-

*

* 0 0

-

-

*

* *

0 ? C = Dm-r+1

* *

0 0

* *

0 ? C=X

*

*

*

*

0

?

0 0

C = Om-r+1

-

* * * 0

?

C = Or-1

* * 0 0

5-44


MOTOROLA

Table 5-5. Condition Code Computations (Continued)

Special Definition Operations X N Z V C

ROXR (r=O)

ROR

ROR (r=O)

-

-

-

* *

* *

* *

0

0

0

?

?

0

NOTE:

= Not Affected

U = Undefined, Result Meaningless

?

= Other See Special Definition

*

= General Case

X=C

N

=

Rm

Z = Rm A ... A RO

Sm = Source Operand Most Significant Bit

Dm = Destination Operand Most Significant Bit

Rm = Result Operand Most Significant Bit

R = Register Tested n = Bit Number r = Shift Count

LB = Lower Bound

UB = Upper Bound

A = Boolean AND

V

= Boolean OR

Rm

=

NOT Rm

C=X

C = Dr-1

5.4.3.2 DATA MOVEMENT INSTRUCTIONS. The MOVE instruction with its associated addressing modes is the basic means of transferring and storing address and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. Address movement instructions (MOVE or MOVEA) transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general MOVE instructions, there are several special data movement instructions: move multiple registers (MOVEM), move peripheral data (MOVEP), move quick (MOVEO), exchange registers (EXG), load effective address (LEA), push effective address (PEA), link stack (LINK), and unlink stack (UNLK). Table 5-6 is a summary of the data movement operations.

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5-45

Table 5-6. Data Movement Operations

Instruction

EXG

LEA

LINK

MOVE

MOVEA

MOVEM

MOVEP

Operand

Syntax

Rn,Rn

(ea), An

An, #(d)

(ea), (ea)

(ea), An list, (ea)

(ea), list

Dn, (d16,An)

MOVEQ

PEA

UNLK

(d16,An), Dn

#(data), Dn

(ea)

An

Operand

Size

32

32

Rn. Rn

(ea). An

Operation

16,32 SP -4. SP, An. (SP); SP. An, SP+d. SP

8,16,32 source. destination

16,32.32

16,32 listed registers. destination

16,32.32 source. listed registers

16,32

Dn[31:24]t(An + d); Dn[23:16]t(An+d+2);

Dn[15:8]. (An+d+4); Dn[7:0]. (An+d+6)

(An + d). Dn[31 :24]; (An + d + 2). Dn[23:16]

(An + d +4). Dn[15:8]; (An + d + 6). Dn[7:0]

8.32

32

32 immediate data. destination

SP -4. SP; (ea). (SP)

An. SP; (SP). An; SP+4. SP

5.4.3.3 INTEGER ARITHMETIC OPERATIONS. The arithmetic operations include the four basic operations of add (ADD), subtract (SUB), multiply (MUL), and divide (DIV) as well as arithmetic compare (CMP, CMPM, CMP2), clear (CLR), and negate (NEG). The instruction set includes ADD, CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The clear and negate instructions apply to all sizes of data operands.

Signed and unsigned MUL and DIV instructions include:

• Word mUltiply to produce a long-word product

• Long-word multiply to produce a long-word or quad-word product

• Division of a long-word dividend by a word divisor (word quotient and word remainder)

• Division of a long-word or quad-word dividend by a long-word divisor

(long-word quotient and long-word remainder)

A set of extended instructions provides multi precision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-7

. for a summary of the integer arithmetic operations.

5-46


MOTOROLA

Table 5-7. Integer Arithmetic Operations

Instruction

ADD

ADDA

ADDI

ADDQ

ADDX

CLR

CMP

CMPA

CMPI

Operand

Syntax

Dn, (ea)

(ea), Dn

(ea), An

Operand

Size

8, 16,32

8,16,32

16,32

#(data), (ea)

#(data), (ea)

8, 16, 32

8,16,32

Dn,Dn 8, 16,32

-(An). -(An) 8,16,32

8, 16,32 lea)

(ea), Dn

(ea), An

8,16,32

16,32

#(data), (ea) 8,16,32

Operation source + destination. destination immediate data + destination. destination source + destination + X • destination

(destination immediate data), CCR shows results

CMPM

CMP2

(An) +, (An) +

(ea), Rn

8,16,32 (destination source), CCR shows results

8,16,32 lower bound<

=

Rn<

= ujJper bound

DIVS/DIVU (ea), Dn

32/16.16:16 destination/source. destination (signed or unsigned)

(ea), Dr:Dq 64/32.32:32

(ea), Dq 32/32.32

DIVSUDIVUL (ea), Dr:Dq 32/32.32:32

EXT

EXTB

MULS/MULU

NEG

NEGX

SUB

SUBA

SUBI

SUBQ

SUBX

TBLSITBLU

TBLSN/

TBLUN

O. destination

(destination source), CCR shows results

On

Dn

Dn

8.16

16.32

8.32

(ea), Dn

(ea), DI

16 x 16.32 source*destination • destination (signed or unsigned)

32 x32. 32

(ea1 Dh:DI 32 x 32.64

(ea)

(ea)

·(ea), Dn

Dn, (ea)

(ea), An

8,16,32

8,16,32

8, 16,32

8,16,32

16,32 sign extended destination. destination

0 - destination. destination o destination X • destination destination source. destination

#(data), (ea)

#(data), (ea)

8, 16,32

8,16,32 destination immediate data. destination

Dn, Dn 8, 16,32 destination source.- X • destination

-(An), -(An)

8, 16, 32

(ea), Dn

Dym:Dyn, Dn

(ea), Dn

Dym:Dyn, Dn

8, 16,32 Dyn Dym. temp

[temp*Dx (7:0))) • temp

Dym*256)+temp. Dn

8, 16, 32 Dyn Dyn • Temp

(temp*Dn [7:0))1256. temp

Dym + temp. Dn

5.4.3.4 LOGICAL INSTRUCTIONS. The logical operation instructions (AND, OR,

EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provide these logical operations with all sizes of immediate data. The TST instruction

MOTOROLA


arithmetically compares the operand with zero, placing the result in the condition code register. Table 5-8 summarizes the logical operations.

Instruction

AND

ANDI

EOR

EORI

NOT

OR

ORI

TST

Table 5-8. Logical Operations

Operand

Syntax

(ea),Dn

Dn, (ea)

#(data),(ea)

Dn,(ea)

#(data),(ea)

(ea)

(ea),Dn

Dn,(ea)

#(data),(ea)

(ea)

Operand

Size

Operation

8,16,32 source A destination. destination

8, 16,32 8, 16,32

8,16,32 immediate data A destination. destination

8, 16,32 source EEl destination. destination

8, 16, 32 immediate data EEl destination. destination

8, 16,32 - destination. destination

8, 16, 32 source V destination. destination

8, 16,32

8, 16, 32 immediate data V destination. destination

8,16,32 source - 0 to set condition codes

5.4.3.5 SHIFT AND ROTATE INSTRUCTIONS. The arithmetic shift instructions, ASR and ASL, and logical shift instructions, LSR and LSL, provide shift operations in both directions. The ROR, ROL, ROXR, and ROXL instructions perform rotate

(circular shift) operations, with and without the extend bit. All shift and rotate operations can be performed on either registers or memory.

Register shift and rotate operations shift all operand sizes. The shift count may be specified in the instruction operation word (to shift from 1-8 places) or in a register (modulo 64 shift count).

Memory shift and rotate operations shift word-length operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Performance of shift/rotate instructions is enhanced so that use of the ROR and ROL instructions with a shift count of eight allows fast byte swapping. Table 5-9 is a summary of the shift and rotate operations.

5-48


Instruction

ASL

ASR

LSL

LSR

ROL

ROR

ROXL

ROXR

SWAP

Table 5.9. Shift and Rotate Operations

Operand

Syntax

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn,Dn

#(data),Dn

(ea)

Dn

Operand

Size

8,16,32

8, 16,32

16

8, 16,32

8,16,32

16

8,16,32

8, 16,32

16

8, 16,32

8,16,32

16

8,16,32

8,16,32

16

8,16,32

8,16,32

16

8, 16,32

8,16,32

16

8,16,32

8, 16,32

16

16 o~

Operation

~~ ro c:s

~~

~~

~ r - o

~

rr:r-Y

<

~

~ ~~

rr:r-Y

< 1< 1

X tJ

Y

X

1 >1

~~

1

+

+

1

5.4.3.6 BIT MANIPULATION INSTRUCTIONS. Bit manipulation operations are accomplished using the following instructions: bit test (BTST), bit test and set

(BSET), bit test and clear (BCLR), and bit test and change (BCHG). All bit manipulation operations can be performed on either registers or memory. The bit number is specified as immediate data or in a data register. Register operands are 32 bits long, and memory operands are 8 bits long. Table 5-10 is a summary of bit manipulation instructions.

MOTOROLA


Instruction

BCHG

BCLR

B5ET

BT5T

Table 5-10. Bit Manipulation Operations

Operand

Syntax

Dn,(ea)

#(data),(ea)

Dn,(ea)

#(data),(ea)

Dn,(ea)

#(data),(ea)

Dn,(ea)

#(data),(ea)

Operand

Size

Operation

8,32

- ((bit number) of destination) • Z • bit of destination

8,32

8,32

- ((bit number) of destination) • Z;

8,32

O. bit of destination

8, 32 - (bit number) of destination) • Z;

8,32 1 • bit of destination

8,32 - ((bit number) of destination) • Z

8,32

5.4.3.7 BINARY-CODED DECIMAL (BCD) INSTRUCTIONS. Five instructions support operations on BCD numbers. The arithmetic operations on packed BCD numbers are add decimal with extend (ABCD), subtract decimal with extend

(SBCD), and negate decimal with extend (NBCD). Table 5-11 is a summary of the BCD operations.

Table 5-11. Binary-Coded Decimal Operations

Instruction

ABCD

NBCD

5BCD

Operand

Syntax

Dn,Dn

- (An), - (An)

(ea)

Dn,Dn

- (An), - (An)

Operand

Size

8

8

8

8

8

Operation source1Q

+ destination1Q

+

X • destination

0 - destination1Q - X. destination destination10 - source1Q - X. destination

5.4.3.8 PROGRAM CONTROL INSTRUCTIONS. A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. Table 5-12 summarizes these instructions.

5-50


Bee

OBcc

Sec

BRA

BSR

JMP

JSR

NOP

Instruction

RTO

RTR

RTS

Table 5-12. Program Control Operations

Operand

Syntax

(label)

On,(label)

(ea)

(label)

(label)

(ea)

(ea) none

#(d) none none

Operand

Size

Operation

Conditional

8, 16, 32 if condition true, then PC + d • PC

16

8 if condition false, then On - 1 • On if On

=F

-1, then PC+d. PC+d. CP if condition true, then destination bits are set to 1; else destination bits are cleared to 0

Unconditional

8,16,32 PC+d. PC

8,16,32 SP-4. SP; PC. (SP); PC+d. PC none destination. PC none none

SP -4. SP; PC. (SP); destination. PC

16 none none

PC+2. PC

Returns

(SP). PC; SP+4+d. SP

(SP). CCR; SP+2. SP; (SP). PC; SP+4. SP

(SP). PC; SP+4. SP

To specify conditions for change in program control, condition codes must be substituted for the letters

"CC"

in conditional program control opcodes. Condition test mnemonics are given below. Refer to 5.4.3.10 CONDITION TESTS for detailed information on condition codes.

CC-Carry clear

CS-Carry set

EQ-Equal

F-False*

GE-Greater or equal

GT-Greater than

HI-High

LS-Low or same

L T -Less than

MI-Minus

NE-Not equal

PL-Plus

T-True

VC-Overflow clear

LE-Less or equal VS-Overflow set

*Not applicable to the Bcc instruction.

5.4.3.9 SYSTEM CONTROL INSTRUCTIONS. Privileged instructions, trapping instructions, and instructions that use or modify the condition code register provide system control operations. All of these instructions cause the processor to flush the instruction pipeline. Table 5-13 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.4.3.10 CONDITION TESTS for detailed information on condition codes.

MOTOROLA


5-51

5-52

Instruction

ANDI

EaRl

MOVE

MOVE

MOVEC

MOVES

ORI

RESET

RTE

STOP

LPSTOP

BKPT

BGND

CHK

CHK2

ILLEGAL

TRAP

TRAPcc

TRAPV

ANDI

EaRl

MOVE

ORI

Table 5-13. System Control Operations

Operand

Syntax

#(data),SR

#(data),SR

(ea),SR

SR,(ea)

USP,An

An,USP

Rc,Rn

Rn,Rc

Rn,(ea)

(ea),Rn

#(data),SR none none

#(data)

#(data)

#(data) none

(ea),Dn

(ea),Rn none

#(data) none

#(data) none

#(data),CCR

#(data),CCR

(ea),CCR

CCR,(ea)

#(data),CCR

Operand

Size

Operation

16

Privileged immediate data A SR • SR

16

16

16

32

32

32

32 immediate data EEl SR • SR source. SR

SR. destination

USP. An

An. USP

Rc. Rn

Rn. Rc

8, 16,32 Rn • destination using DFC source using SFC • Rn

16 none none immediate data V SR • SR assert RESET

(SP). SR; SP+2. SP; (SP). PC; SP+4. SP; restore stack according to format

16 none none none immediate data. SR; STOP immediate data. SR; interrupt mask. EBI; STOP

Trap Generating if breakpoint cycle acknowledged, then execute returned operation word, else trap as illegal instruction if background mode enabled, then enter background mode else format/vector offset. - (SSP);

PC. - (SSP); SR. - (SSP); (vector). PC

16,32 if Dn <0 or Dn <lea), then CHK exception

8, 16,32 if Rn <lower bound or Rn> upper bound, then CHK exception none none

SSP - 2. SSP; vector offset. (SSP);

SSP -4. SSP; PC. (SSP);

SSP -2. SSP; SR. (SSP); illegal instruction vector address. PC

SSP - 2 • SSP; format a nd vector offset. (SSP)

SSP -4. SSP; PC. (SSP); SR. (SSP); vector address. PC if cc true, then TRAP exception none

16,32 none if V then take overflow TRAP exception

8

, Condition Code Register immediate data A CCR • CCR

8

16

16

8 immediate data EEl CCR • CCR source. CCR

CCR • destination immediate data V CCR • CCR


MOTOROLA

5.4.3.10 CONDITION TESTS. Conditional program control instructic;ms and the

TRAPcc instruction execute on the basis of condition tests. A condition test is the evaluation of a logical expression related to the state of the CCR bits. If the result is one, the condition is true. If the result is zero, the condition is false.

For example, the T condition is always true, and the EQ condition is true only if the Z-bit condition code is true. Table 5-14 lists each condition test.

Table 5-14. Condition Tests

Mnemonic

T

F*

HI

LS

CC(HS)

CS(LO)

NE

EQ

VC

VS

Condition

True

False

High

Low or Same

Carry Clear

Carry Set

Not Equal

Equal

Overflow Clear

Overflow Set

PL

MI

GE

LT

Plus

Minus

Greater or Equal

Less Than

GT Greater Than

LE Less or Equal

*Not available for the Bee instruction .

• =

Boolean AND

+

=

Boolean OR

N =

Boolean NOT N

Encoding

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Test

1

0

C'Z

C+Z

C

C

Z

Z

V

V

N

N

- -

N·V+N·V

N·V+N·V

N·V·Z + N'V,Z

-

Z+N'V+N'V

5.4.4 Using the Table Lookup and Interpolate Instruction

There are four table lookup and interpolate instructions. TBLS returns a signed, rounded byte, word, or long-word result; TBLSN returns a signed, unrounded byte, word, or long-word result. TBLU returns an unsigned, rounded byte, word, or long-word result; TBLUN returns an unsigned, unrounded byte, word, or long-word result. All four instructions support two types of interpolation data: an n-element table stored in memory, and a 2-element range stored in a pair of data registers. The latter form provides a means of performing surface (3D) interpolation between two previously calculated linear interpolations.

MOTOROLA


5-53

The following examples show how a programmer can compress tables and use fewer interpolation levels between table entries. Example 1 (see Figure

5-16) demonstrates table lookup and interpolation for a 257-entry table, allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-17 reduces table length for the same data to four entries. Example 3 (see Figure

5-18) demonstrates using an 8-bit independent variable with an instruction.

Two additional examples show how TBLSN can reduce cumulative error when multiple table lookup and interpolation operations are used in a calculation.

Example 4 demonstrates adding the results of three table interpolations. Example 5 illustrates using TBLSN in surface interpolation.

5.4.4.1 TABLE EXAMPLE 1: STANDARD USAGE. The table consists of 257 word entries. As shown in Figure 5-16, the function is linear within the range 32768

::::; X ::::; 49152. Table entries within this range are as given in Table 5-15 ..

Table 5-15. Standard Usage Entries

Entry

Number

128*

162

X

Value

32768

41472 y

Value

1311

1659

163

164

41728

41984

1669

1679

165 42240 . 1690

192*

49152 1966

*These values are the end points of the range.

All entries between these points fall on the line.


~

!;¥

~

!z w o z

W

0o

16384

32768 49152 65536

INDEPENDENT VARIABLE

Figure 5-16. Table Example 1

The table instruction is executed with the following bit pattern in Ox:

31

NOT USED

16 15 0

1 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1

Table Entry Offset. Ox [8: 15]

=

$A3

=

163

Interpolation Fraction. Ox [0:7]

=

$80

=

128

Using this information, the table instruction calculates dependent variable Y:

Y

=

1669

+

(128 (1679 -1669))/256

=

1674

5.4.4.2 TABLE EXAMPLE 2: COMPRESSED TABLE. In Example 2 (see Figure

5-17), the data from Example 1 has been compressed by limiting the maximum value of the independent variable. Instead of the range 0

~

X

=

65535, X is limited to 0

~

X

~

1023. The table has been compressed to only 5 entries, but up to 256 levels of interpolation are allowed between entries.

MOTOROLA


z

W

0-

W o

~

!.2

~

~ y

5-56

256

512 786

I

X


1024


CAUTION

Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are given in Table 5-16.

Table 5-16. Compressed Table Entries

Entry

Number

2

3

X

Value

512

786

Y

Value

1311

1966

Since the table is reduced from 257 to 5 entries, independent variable X must be scaled appropriately. In this case, the scaling factor is 64, and the scaling is done by a single instruction:

LSR.W

#6,Dx

Thus, Dx now contains the following bit pattern:

31

NOT USED

16 15 0

\00 0 0 0 0 1 0 1 0 0 0 1 1 1 0\


MOTOROLA

Table Entry Offset Dx [8: 15]

=

$02

=

2

Interpolation Fraction Dx [0:7]

=

$8E

=

142

Using this information, the table instruction calculates dependent variable Y:

Y

=

1331

+

(142 (1966 - 1311 )

)/256

=

1674

The function chosen for Examples 1 and 2 is linear between data points. Had another function been used, interpolated values might not have been identical.

5.4.4.3 TABLE EXAMPLE 3: 8-BIT INDEPENDENT VARIABLE. This example shows how to use a table instruction within an interpolation subroutine. Independent variable

X is calculated as an 8-bit value, allowing 16 levels of interpolation on a 17-entry table.

X is passed to the subroutine, which returns an 8-bit result.

The subroutine uses the data given in Table 5-17, based on the function shown in Figure 5-18.

~

~

~

!z y w o z

W

0o

1024 2048 x

3072



4096


5-58

Table 5-17. 8-Bit Independent

Variable Entries

y

10

11

12

13

14

15

16

7

8

5

6

9

3

4

1

2

x x

(Subroutine) (Instruction)

0 0

3072

3328

3584

3840

4096

256

512

768

1024

1280

1536

1792

2048

2304

2560

2816

0

80

96

112

128

112

16

32

48

64

32

16

0

96

80

64

48

The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column. is the result returned by the subroutine.

The following value has been calculated for independent variable X:

31

NOT USED

16 15

I

0

0 0 0 0 0 0 0 1 0 1 1 1 1 0 1 1

Since X is an 8-bit value, the upper four bits are used as a table offset, and the lower four bits are used as an interpolation fraction. The following results are obtained from the subroutine:

Table Entry Offset. Dx [4:7]

=

$8

=

11

Interpolation Fraction. Dx [0:3]

=

$D

=

13


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Thus, Y is calculated as follows:

Y=80+(13

(64-80))/16=67

If the 8-bit value for X were used directly by the table instruction, interpolation would be incorrectly performed between entries 0 and 1. Data must be shifted to the left four places before use:

LSL.W #4, Ox

The new range for X is 0

~

X

~

4096; however, since a left shift fills the least significant digits of the word with zeros, the interpolation fraction can only have one of 16 values.

After the shift operation, Ox contains the following value:

31

NOT USED

16 15 0

1 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 1

Execution of the table instruction using the new value in Ox yields:

Table Entry Offset. Ox [8: 15] = $08 = 11

Interpolation Fraction. Ox [0:7] = $00 = 208

Thus, Y is calculated as follows:

Y = 80 + (208 (64 - 80) )/256 = 67

5.4.4.4 TABLE EXAMPLE 4: MAINTAINING PRECISION. In this example, three table lookup and interpolation (TLI) operations are performed, and the results are summed. The calculation is done once with the result of each TLI rounded before addition and once with only the final result rounded. Assume that the result of the three interpolations are as follows (a

t I . t I

indicates the binary radix point).

TLI

TLI

TLI

# 1

# 2

#

3

0010 0000 . 0111 0000

0011 1111 . 0111 0000

0000 0001 . 0111 0000


5-60

First, the results of each TLI are rounded with the TBLS round-to-nearest-even algorithm. The following values would be returned by TBLS:

TLI

TLI

TLI

#

1

# 2

# 3

0010 0000 .

0011 1111 .

0000 0001 .

Summing, the following result is obtained:

0010 0000 .

0011 1111 .

0000 0001 .

0110 0000 .

Now, using the same TLI results, the sum is first calculated and then rounded according to the same algorithm:

0010 0000 . 0111 0000

0011 1111 . 0111 0000

0000 0001 . 0111 0000

0110 0001 . 0101 0000

Rounding yields:

01100001.

The second result is preferred. The following code sequence illustrates how addition of a series of table interpolations can be performed without loss of precision in the intermediate results:

LO:

TBLSN.B

TBLSN.B

TBLSN.B

AOO.L

AOO.L

ASR.L

BCC.B

AOOQ.B

L1: ...

(ea), Ox

(ea), Ox

(ea), 01

Ox, Om

Om, 01

#8,01

L1

#1,01

Long addition avoids problems with carry

Move radix point

Fraction MSB in carry


5.4.4.5 TABLE EXAMPLE 5: SURFACE INTERPOLATIONS. The various forms of table can be used to perform surface (30) TLis. However, since the calculation must be split into a series of

20

TLls, losing precision in the intermediate results is possible. The following code sequence, incorporating both TBLS and TBLSN, eliminates this possibility:

LO:

MOVE.W

TBLSN.B

TBLSN.B

TBLS.W

ASR.L

BCC.B

AOOQ.B

L1: ...

Ox, 01 ea, Ox ea,OI

Ox:OI, Om

#8, Om

L1

#1,01

Copy entry number and fraction number

Surface interpolation, with round

Read just the result

No round necessary

Half round up

Before execution of this code sequence, Ox must contain fraction and entry numbers for the two TLls, and Om must contain the fraction for surface interpolation. The (ea) fields in the TBLSN instructions point to consecutive columns in a 30 table. The TBLS size parameter must be word if the TBLSN size parameter is byte, and must be long word ifTBLSN is word. Increased size is necessary because a larger number of significant digits is needed to accommodate the scaled fractional results of the 20 TLI.

5.4.5 Nested Subroutine Calls

The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack for use. Using this instruction in a series of subroutine calls will generate a linked list of stack frames.

The UNLK instruction removes a stack frame from the end of the list by loading an address into the stack pointer and pulling the value at that address from the stack. When the instruction operand is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from both the stack and the linked list.

5.4.6 Pipeline Synchronization with the NOP Instruction

Although the no operation (NOP) instruction performs no visible operation, it does force synchronization ofthe instruction pipeline since all previous instructions must complete execution before the NOP begins.

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5.5 PROCESSING STATES

This subsection describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the status register and an overview of processor response to exception conditions.

5.5.1 State Transitions

The processor is in normal, background, or exception processing state unless halted.

When the processor fetches instructions and operands or executes instructions, it is in the normal processing state. The stopped state, which the processor enters when a STOP or LPSTOP instruction is executed, is a special case of the normal state in which no further bus cycles are generated.

Background state is an alternate operational mode used for system debugging.

Refer to 5.7 DEVELOPMENT SUPPORT for more information.

Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes the stack operations, the exception vector fetch, and the filling of the instruction pipeline caused by an exception. Exception processing ends when execution of an exception handler routine begins. Refer to 5.6 EXCEPTION PROCESSING for comprehensive information.

A catastrophic system failure occurs if the processor detects a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if a bus error occurs during exception processing caused by a bus error, the CPU32 assumes that the system is not operational and halts. Only a reset can restart a halted processor. The halted condition should not be confused with the stopped condition. After the processor executes a STOP or LPSTOP instruction, execution of instructions can resume when a trace, interrupt, or reset exception occurs.

5.5.2 Privilege Levels

To protect system resources, the processor can operate with either oftwo levels of access user or supervisor. Supervisor level is more privileged than user level. All instructions are available at the supervisor level, but execution of some instructions is not permitted at the user level. There are separate stack


pointers for each level. The S-bit in the status register indicates privilege level and determines which stack pointer is used for stack operations. The processor identifies each bus access (supervisor or user mode) via function codes to enforce supervisor and user access levels.

In a typical system, most programs execute at the user level. User programs can access only their own code and data areas and are restricted from accessing other information. The operating system executes at the supervisor privilege level, has access to all resources, performs the overhead tasks for the user level programs, and coordinates their activities.

5.5.2.1 SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the status register is set, supervisor privilege level applies, and all instructions are executable. The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on

FC3-FCO refer to supervisor address spaces.

All exception processing is performed at the supervisor level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the supervisor stack pointer.

Instructions that have important system effects can only be executed at supervisor level. For instance, user programs are not permitted to execute STOP,

LPSTOP, or RESET instructions. To prevent a user program from gaining privileged access, except in a controlled manner, instructions that can alter the

S-bit in the status register are privileged. The TRAP #n instruction provides controlled user access to operating system services.

5.5.2.2 USER PRIVILEGE LEVEL. If the S-bit in the status register is cleared, the processor executes instructions at the user privilege level. The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the function codes on FC3-FCO specify user address spaces. While the processor is at the user level, implicit references to the system stack pointer and explicit references to address register seven (A7) refer to the user stack pointer (USP).

5.5.2.3 CHANGING PRIVILEGE LEVEL. To change from user privilege level to supervisor privilege level, a condition that causes exception processing must occur. When exception processing begins, the current values in the status register, including the S-bit , are saved on the supervisor stack, and then the

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S-bit is set, enabling supervisory access. Execution continues at supervisor level until exception processing is complete.

To return to user access level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE.

These instructions execute only at supervisor privilege level and can modify the S-bit of the status register. After these instructions execute, the instruction pipeline is flushed, then refilled from the appropriate address space.

The RTE instruction causes a return to a program that was executing when an exception occurred. When RTE is executed, the exception stack frame saved on the supervisor stack can be restored in either of two ways.

If the frame was generated by an interrupt, breakpoint, trap, or instruction exception, the status register and program counter are restored to the values saved on the supervisor stack, and execution resumes at the restored program counter address, with access level determined by the S-bit of the restored status register.

If the frame was generated by a bus error or an address error exception, the entire processor state is restored from the stack.

5.6 EXCEPTION PROCESSING

An exception is a special condition that pre-empts normal processing. Exception processing is the transition from normal mode program execution to normal mode execution of a routine that deals with an exception. Efficient exception processing is a critical constraint on system function. This section discusses system resources, exception processing sequence, and specific features of individual exception processing routines.

5.6.1 Exception Vectors

An exception vector is the address of a routine that handles an exception. The vector base register (VBR) contains the base address of a 1024-byte exception vector table, which consists of 256 exception vectors 64 vectors are defined by the processor, and 192 vectors are reserved for user definition as interrupt vectors. Except for the reset vector, each vector in the table is one long word in length. The reset vector is two long words in length. Refer to Table 5-18 for information on vector assignment.

5-64


CAUTION

Since there is no protection on the 64 processor-defined vectors, external devices can access vectors reserved for internal purposes. This practice is strongly discouraged.

All exception vectors, except the reset vector, are located in supervisor data space. The reset vector is located in supervisor program space. Only the initial reset vector is fixed in the processor memory map. When initialization is complete, there are no fixed assignments. Since the VBR stores the vector table base address, the table can be located anywhere in memory. It can also be dynamically relocated for each task executed by an operating system.

Each vector is assigned an 8-bit number. Vector numbers for some exceptions are obtained from an external device; others are supplied by the processor.

The processor multiplies the vector number by four to calculate vector offset, then adds the offset to the contents of the VBR. The sum is the memory address of the vector.

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Vector

Number

8

9

10

11

12

13

14

15

16-23

4

5

6

7

0

1

2

3

24

25

26

27

28

29

30

31

32-47

48-58

59-63

64-255

Table 5-18. Exception Vector Assignments

112

116

120

124

128

188

192

232

236

252

64

92

96

100

104

108

Dec

Vector Offset

Hex Space

32

36

40

44

16

20

24

28

0

4

8

12

000

004

008

OOC

010

014

018

01C

020

024

028

02C

SP

SP

SD

SD

SD

SD

SD

SD

SD

SD

SD

SD

48

52

56

60

030

034

038

03C

040

05C

060

064

068

06C

SD

SD

SD

SD

SO

SD

SD

SD

SD

070

074

078

07C

080

OBC

SD

SD

SD

SD

SD

256

1020

OCO

OE8

OEC

OFC

100

3FC

SD

SD

SD

Assignment

Reset: Initial Stack Pointer

Reset: Initial Program Counter

Bus Error

Address Error

Illegal Instruction

Zero Divide

CHK, CHK2 Instructions

TRAPcc, TRAPV Instructions

Privilege Violation

Trace

Line 1010 Emulator

Line 1111 Emulator

Hardware Breakpoint

(Reserved for Coprocessor Protocol Violation)

Format Error and Uninitialized Interrupt

Format Error and Uninitialized Interrupt

(Unassigned, Reserved)

-

Spurious Interrupt

Level 1 Interrupt Autovector







TRAP Instruction Vectors (0-15)

-

(Reserved for Coprocessor)

-

(Unassigned, Reserved)

-

User-Defined Vectors (192)

5.6.1.1 TYPES OF EXCEPTIONS. An exception can be due to internal or external causes.

An internal exception can be generated by an instruction or by an error. The

TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can cause exceptions during normal execution. Illegal instructions, instruction fetches from odd addresses, word or long-word operand accesses from odd addresses, and privilege violations also cause internal exceptions.

5-66


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Sources of external exception include interrupts, breakpoints, bus errors, and reset requests. Interrupts are requests for processor action from peripheral devices. Breakpoints are used to support development equipment. Bus error and reset are used for access control and processor restart.

5.6.1.2

EXCEPTION PROCESSING SEQUENCE.

For all exceptions other than a reset exception, exception processing occurs in the following sequence. Refer to 5.6.2.1

RESET

for details of reset processing.

As exception processing begins, the processor makes an internal copy of the status register. After the copy is made, the processor state bits in the status register are changed the S-bit is set, establishing supervisor access level, and bits T1 and TO are cleared, disabling tracing. For reset and interrupt exceptions, the interrupt priority mask is also updated.

Next, the exception number is obtained. For interrupts, the number is fetched from CPU space $F (the bus cycle is an interrupt acknowledge). For all other exceptions, internal logic provides a vector number.

Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the status register and the program counter for use by the RTE instruction. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame.

Finally, the processor prepares to resume normal execution of instructions.

The exception vector offset is determined by multiplying the vector number by four, and the offset is added to the contents of the VBR to determine displacement into the exception vector table. The exception vector is loaded into the program counter. If no other exception is pending, the processor will resume normal execution at the new address in the program counter.

5.6.1.3

EXCEPTION STACK FRAME.

During exception processing, the most volatile portion of the current context is saved on the top of the supervisor stack.

This context is organized in a format called the exception stack frame.

The exception stack frame always includes the contents of status register and program counter at the time the exception occurred. To support generic handlers, the processor also places the vector offset in the exception stack frame and marks the frame with a format code. The format field allows an RTE instruction to identify stack information so that it can be properly restored.

MOTOROLA


5-67

5-68

The general form of the exception stack frame is illustrated in Figure 5-19.

Although some formats are peculiar to a particular M68000 Family processor, format 0000 is always legal and always indicates that only the first four words of a frame are present. See 5.6.4 CPU32 Stack Frames for a complete discussion of exception stack frames. o

SP ~

I

FORMAT

STATUS REGISTER

PROGRAM COUNTER HIGH

PROGRAM COUNTER LOW

I

VECTOR OFFSET

OTHER PROCESSOR STATE INFORMATION,

DEPENDING ON EXCEPTION

(0, 2, OR 8 WORDS)

Figure 5-19. Exception Stack Frame

15

5.6.1.4

MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on its relative importance to system operation. Priority assignments are shown in Table 5-19. Group zero (0) exceptions have the highest priorities. Group four

(4) exceptions have the lowest priorities. Exception processing for exceptions that occur simultaneously is done by priority, from highest to lowest.

Table 5-19. Exception Priority Groups

Group!

Priority

0

1.1

1.2

2

3

4.1

4.2

4.3

Exception and

Relative Priority

Reset

Characteristics

Aborts all processing (instruction or exception); does not save old context.

Address Error

Bus Error

Suspends processing (instruction or exception); saves internal context.

BKPT#n, CHK, CHK2,

Exception processing is a part of instruction exe-

Divide by Zero, RTE, cution.

TRAP#n, TRAPcc,

TRAPV

Illegal Instruction, Line Exception processing begins before instruction is

A, Unimplemented executed.

Line F, Privilege

Violation

Trace Exception processing begins when current instruc-

Hardware Breakpoint tion or previous exception processing is completed.

Interrupt


It is important to be aware of the difference between exception processing mode and execution of an exception handler. Each exception has an assigned vector, which points to an associated handler routine. Exception processing includes steps described in 5.6.1.2

EXCEPTION PROCESSING SEQUENCE

but does not include execution of handler routines, which is done in normal mode.

When the CPU32 completes exception processing, it is ready to begin either exception processing for a pending exception or execution of a handler routine.

Priority assignment governs the order in which exception processing occurs, not the order in which exception handlers are executed.

As a general rule, when simultaneous exceptions occur, the handler routines for lower priority exceptions are executed before the handler routines for higher priority exceptions. For example, consider the arrival of an interrupt during execution of a TRAP instruction, while tracing is enabled. Trap exception processing (2) is done first, followed immediately by exception processing for the trace (4.1), and then by exception processing for the interrupt (4.3). Each exception places a new context on the stack. When the processor resumes normal instruction execution, it is vectored to the interrupt handler, which returns to the trace handler, which returns to the trap handler.

There are special cases to which the general rule does not apply. The reset exception will always be tHe first exception handled, since reset clears all other exceptions. It is also possible for high-priority exception processing to begin before low-priority exceptioh processing is complete. For example, if a bus error occurs during trace exception processing, the bus error will be processed and handled before trace exception processing is completed.

5.6.2 Processing of Specific Exceptions

The following paragraphs provide details concerning sources of specific exceptions, how each arises, and how each is processed.

5.6.2.1

RESET.

Assertion of RESET by external hardware or assertion of the internal RESET signal by an internal module causes a reset exception. The reset exception has the highest priority of any exception. Reset is used for system initialization and for recovery from catastrophic failure. The reset exception aborts any processing in progress when it is recognized, and that processing cannot be recovered. Reset performs the following operations:

1. Clears TO and T1 in the status register to disable tracing.

2. Sets the S-bit in the status register to establish supervisor privilege.

MOTOROLA


3. Sets the interrupt priority mask to the highest priority level (%111).

4. Initializes the vector base register to zero ($00000000).

5. Generates a vector number to reference the reset exception vector.

6. Loads the first long word of the vector into the interrupt stack pointer.

7. Loads the second long word of the vector into the program counter.

Figure 5-20 is a flowchart of the reset exception.

After initial instruction prefetches, normal program execution begins at the address in the program counter. The reset exception does not save the value of either the program counter or the status register.

If a bus error or address error occurs during a reset exception processing sequence, a double bus fault occurs. The processor halts, and the HALT signal is asserted to indicate the halted condition.

Execution of the RESET instruction does not cause a reset exception nor affect any internal register, but it does cause the CPU32 to assert the RESET signal, resetting all internal and external peripherals.

5.6.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal is acknowledged. BERR can be asserted by one of three sources:

1. External logic by assertion of the BERR input pin

2. Direct assertion of the internal BERR signal by an internal module

3. Direct assertion of the internal BERR signal by the on-chip bus monitor after detecting a no-response condition

Bus error exception processing begins when the processor attempts to use information from an aborted bus cycle.

When the aborted bus cycle is an instruction prefetch, the processor will not initiate exception processing unless the prefetched information is used. For example, if a branch instruction flushes an aborted prefetch, that word is not accessed, and no exception occurs.

When the aborted bus cycle is a data access, the processor initiates exception processing immediately, except in the case of released operand writes. Released write bus errors are delayed until the next instruction boundary or until another operand access is attempted.


MOTOROLA

(

ENTRY

)

OTHERWISE

SP • (VECTOR # 0)

FETCH VECTOR # 1

OTHERWISE

PC • (VECTOR # 1)

BUS ERROR

BUS ERROR/

ADDRESS

ERROR

OTHERWISE BEGIN

INSTRUCTION

EXECUTION

~

(DOUBLE BUS FAULT)

Figure 5-20. Reset Operation Flowchart

Exception processing for bus error exceptions follows the regular sequence, but context preservation is more involved than for other exceptions because a bus exception can be initiated while an instruction is executing. Several bus error stack format organizations are utilized to provide additional information regarding the nature of the fault.

First, any register altered by a faulted-instruction effective address calculation is restored to its initial value. Then a special status word (SSW) is placed on the stack. The SSW contains specific information about the aborted access -

MOTOROLA


size, type of access (read or write), bus cycle type, and function code are saved.

Finally, fault address, bus error exception vector number, program counter value, and a copy of the status register are saved.

If a bus error occurs during exception processing for a bus error, an address error, a reset, or while the processor is loading stack information during RTE execution, the processor halts. This simplifies isolation of catastrophic system failure by preventing processor interaction with stacks and memory. Only assertion of RESET can restart a halted processor.

5.6.2.3

ADDRESS ERROR.

Address error exceptions occur when the processor attempts to access an instruction, word operand, or long-word operand at an odd address. The effect is much the same as an internally generated bus error.

Address error exception processing begins when the processor attempts to use information from the aborted bus cycle.

If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the case of a released operand write. Released write exceptions are delayed until the next instruction boundary or attempted operand access.

An address exception on a branch to an odd address is delayed until the program counter is changed. No exception occurs if the branch is not taken.

The exception processing sequence is the same as that for bus error, except that the vector number refers to the address exception vector. The fault address and return program counter value placed in the exception stack frame are the odd address. The current instruction program counter points to the instruction that caused the exception.

If an address error occurs during exception processing for a bus error, another address error, or a reset, the processor halts.

5.6.2.4

INSTRUCTION TRAPS.

Traps are exceptions caused by instructions. They arise either from processor recognition of abnormal conditions during instruction execution or from use of specific trapping instructions. Traps are generally used to handle abnormal conditions that arise in control routines.

The TRAP instruction, which always forces an exception, is useful for implementing system calls for user programs. The TRAPcc, TRAPV, CHK, and CHK2

5-72


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instructions force exceptions when a program detects a run-time error. The

DIVS and DIVU instructions force an exception if a division operation is attempted with a divisor of zero.

Exception processing for traps follows the regular sequence. If tracing is enabled when an instruction that causes a trap begins execution, a trace exception will be generated by the instruction, but the trap handler routine will not be traced (the trap exception will be processed first, then the trace exception).

The vector number for the TRAP instruction is internally generated; part of the number comes from the instruction itself. The trap vector number, program counter value, and a copy of the status register are saved on the supervisor stack. The saved program counter value is the address of the instruction that follows the instruction which generated the trap. For all instruction traps other than TRAP, a pointer to the instruction causing the trap is also saved in the fifth and sixth words of the exception stack frame.

5.6.2.5 SOFTWARE BREAKPOINTS. To support hardware emulation, the CPU32 must provide a means of inserting breakpoints into target code and of clearly announcing when a breakpoint is reached.

The MC68000 and MC68008 can detect an illegal instruction inserted at a breakpoint when the processor fetches from the illegal instruction exception vector location. Since the VBR on the CPU32 allows relocation of exception vectors, the exception vector address is not a reliable indication of a breakpoint. CPU32 breakpoint support is provided by extending the function of a set of illegal instructions ($4848-$484F).

When a breakpoint instruction is executed, the CPU32 performs a read from

CPU space $0, at a location corresponding to the breakpoint number. If this bus cycle is terminated by BERR, the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK, the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See SECTION 3 BUS OPERATION for a description of CPU space operations.

5.6.2.6 HARDWARE BREAKPOINTS. The CPU32 recognizes hardware breakpoint requests. Hardware breakpoint requests do not force immediate exception processing but are left pending. An instruction breakpoint is not made pending until the instruction corresponding to the request is executed.

MOTOROLA


A pending breakpoint can be acknowledged between instructions or at the end of exception processing. To acknowledge a breakpoint, the CPU performs a read from CPU space $0 at location $1 E (see SECTION 3 BUS OPERATION).

If the bu-s cycle terminates normally, instruction execution continues with the next instruction as if no breakpoint request occurred. If the bus cycle is terminated by BERR, the CPU begins exception processing.

Exception processing follows the regular sequence. Vector number 12 (offset

$30) is internally generated. The program counter of the currently executing instruction, the program counter of the next instruction to execute, and a copy of the status register are saved on the supervisor stack. Data returned during this bus cycle is ignored.

5.6.2.7 FORMAT ERROR. The processor checks certain data values for control operations. The validity of the stack format code and, in the case of a bus cycle fault format, the version number of the processor that generated the frame are checked during execution of the RTE instruction. This check ensures that the program does not make erroneous assumptions about information in the stack frame.

If the format of the control data is improper, the processor generates a format error exception. This exception saves a four-word format exception fram~ and then vectors through vector table entry number 14. The stacked program counter is the address of the RTE instruction that discovered the format error.

5.6.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS. An instruction is illegal if it contains a word bit pattern that does not correspond to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC instruction that contains an undefined register specification field in the first extension word, or if it contains an indexed addressing mode extension word with bits [5:4]

=

00 or bits [3:0]

=1=

0000.

If an iJlegal instruction is fetched during instruction execution, an illegal instruction exception occurs. This facility allows the operating system to detect program errors or to emulate instructions in software.

Word patterns with bits [15: 12]

=

1010 (referred to as A-line opcodes) are unimplemented instructions. A separate exception vector (vector 10, offset $28) is given to unimplemented instructions to permit efficient emulation.


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Word patterns with bits [15: 12]

=

1111 (referred to as F-line opcodes) are used for M68000 Family instruction set extensions. They can generate an unimplemented instruction exception caused by the first extension word of the instruction or by the addressing mode extension word. A separate F-line emulation vector (vector 11, offset $2C) is used for the exception vector.

All unimplemented instructions are reserved for use by Motorola for enhancements and extensions to the basic M68000 architecture. Opcode pattern $4AFC is defined to be illegal on all M68000 Family members. Those customers requiring the use of an unimplemented opcode for synthesis of "custom instructions," operating system calls, etc. should use this opcode.

Exception processing for illegal and unimplemented instructions is similar to that for traps. The instruction is fetched and decoding is attempted. When the processor determines that execution of an illegal instruction is being attempted, exception processing begins. No registers are altered.

Exception processing follows the regular sequence. The vector number is generated to refer to the illegal instruction vector or, in the case of an unimplemented instruction, to the corresponding emulation vector. The illegal instruction vector number, current program counter, and a copy of the status register are saved on the supervisor stack, with the saved value of the program counter being the address of the illegal or unimplemented instruction.

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5.6.2.9 PRIVILEGE VIOLATIONS. To provide system security, certain instructions can be executed only at the supervisor access level. An attempt to execute one of these instructions at the user level will cause an exception. The privileged exceptions are as follows:

• AND Immediate to SR

• EOR Immediate to SR

• LPSTOP

• MOVE from SR

• MOVE to SR

• MOVE USP

• MOVEC

• MOVES

• OR Immediate to SR

• RESET

• RTE

• STOP

Exception processing for privilege violations is nearly identical to that for illegal instructions. The instruction is fetched and decoded. If the processor determines that a privilege violation has occurred, exception processing begins before instruction execution. Exception processing follows the regular sequence. The vector number is generated to reference the privilege violation vector. Privilege violation vector number, current program counter, and status register are saved on the supervisor stack. The saved program counter value is the address of the first word of the instruction causing the privilege violation.

5.6.2.10 TRACING. To aid in program development, M68000 processors include a facility to allow tracing of instruction execution. CPU32 tracing also has the ability to change program flow. In trace mode, a trace exception is generated after each instruction executes, allowing a debugging program to monitor the execution of a program under test. The T1 and TO bits in the supervisor portion of the status register are used to control tracing.

5-76


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When T[1 :0]

=

00, tracing is disabled, and instruction execution proceeds normally (see Table 5-20).

Table 5-20. Tracing Control

0

1

1

T1 TO

0 0

Tracing Function

No Tracing

1 Trace on Change of Flow

0 Trace on Instruction Execution

1 (Undefined; Reserved)

When T[1 :0]

=

01 at the beginning of instruction execution, a trace exception is generated if the program counter changes sequence during execution. All branches, jumps, subroutine calls, returns, and status register manipulations can be traced in this way. If a branch is not taken, an exception is not generated.

When T[1 :0]

=

10 at the beginning of instruction execution, a trace exception is generated when execution is complete. If the instruction is not executed, either because an interrupt is taken or because the instruction is illegal, unimplemented, or privileged, an exception is not generated.

At the present time, T[1 :0]

=

11 is an undefined condition. It is reserved by

Motorola for future use.

Exception processing for trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. Exception processing follows the regular sequence (tracing is disabled so that the trace exception itself is not traced). A vector number is generated to reference the trace exception vector. The address of the instruction that caused the trace exception, the trace exception vector offset, the current program counter, and a copy of the status register are saved on the supervisor stack. The saved value of the program counter is the address of the next instruction to be executed.

A trace exception can be viewed as an extension to the function of any instruction. If a trace exception is generated by an instruction, the execution of that instruction is not complete until the trace exception processing associated with it is also complete.

If an instruction is aborted by a reset, bus error, or address error exception, trace exception is deferred until normal execution resumes. An RTE from a bus error or address error will not be traced because of the possibility of continuing the instruction from the fault.


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If an instruction is executed and an interrupt is pending on completion, the trace exception is processed before the interrupt exception. If an instruction forces an exception, the forced exception is processed before the trace exception.

If an instruction is executed and a breakpoint is pending upon completion of the instruction, the trace exception is processed before the breakpoint.

If an attempt is made to execute an illegal, unimplemented, or privileged instruction while tracing is enabled, no trace exception will occur because the instruction is not executed. This condition is particularly important to an emulation routine that performs an instruction function, adjusts the stacked program counter to beyond the unimplemented instruction, and then returns. The status register on the stack must be checked to determine if tracing is on before the return is executed. If tracing is on, trace exception processing must be emulated so that the trace exception handler can account for the emulated instruction.

Tracing affects normal operation of the STOP and LPSTOP instructions. If either instruction begins execution with T1 set, a trace exception will be taken after the instruction loads the status register. Upon return from the trace handler routine, execution will continue with the instruction following STOP (LPSTOP), and the processor will not enter the stopped condition.

5.6.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable interrupt vectors within each exception vector table. Judicious use of mUltiple vector tables and hardware chaining will permit a virtually unlimited number of peripherals to interrupt the processor.

Interrupt recognition and subsequent processing are based on internal interrupt request signals (lRQ7-IRQ1) and the current priority set in status register priority mask 1[2:0]. Interrupt request level zero (IRQ7-IRQ1 negated) indicates that no service is requested. When an interrupt of level one through six is requested via IRQ6-IRQ1, the processor compares the request level with the interrupt mask to determine whether the interrupt should be processed. Interrupt requests are inhibited for all priority levels less than or equal to the current priority. Level seven interrupts are nonmaskable.

IRQ7-IRQ1 are synchronized and debounced by input circuitry on consecutive rising edges of the processor clock. To be valid, an interrupt request must be held constant for at least two consecutive clock periods.

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Interrupt requests do not force immediate exception processing but are left pending. A pending interrupt is detected between instructions or at the end of exception processing all interrupt requests must be held asserted until they are acknowledged by the CPU. If the priority of the interrupt is greater than the current priority level, exception processing begins.

Exception processing follows the regular sequence until after tracing is suppressed. Priority level is then set to the level of the interrupt, and the processor fetches a vector number from the interrupting device (CPU space $F). The fetch bus cycle is classified as an interrupt acknowledge, and the encoded level number of the interrupt is placed on the address bus.

If an interrupting device requests automatic vectoring, the processor generates a vector num~er

(25-31) determined by the interrupt level number.

If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken to be spurious, and the spurious interrupt vector number (24) is generated.

The exception vector number, program counter, and status register are saved on the supervisor stack. The saved value of the program counter is the address of the instruction that would have executed had the interrupt not occurred.

Priority level seven interrupt is a special case. Level seven interrupts are nonmaskable. These requests are transition sensitive to eliminate redundant servicing and concomitant stack overflow. Transition sensitive means that the level seven input must change state before the CPU will detect an interrupt.

A level seven interrupt is generated each time the interrupt request level changes to level seven, and each time the priority mask changes from seven to a lower number while the request level remains at seven.

Many M68000 peripherals provide for programmable interrupt vector numbers to be used in the system interrupt request/acknowledge mechanism. If the vector number is not initialized after reset and if the peripheral must acknowledge an interrupt request, the peripheral should return the uninitialized interrupt vector number (15). Refer to

SECTION 3 BUS OPERATION

for more information on interrupt acknowledge cycles.

5.6.2.12

RETURN FROM EXCEPTION.

When exception stacking operations are complete, the processor begins normal mode handler execution for the last exception processed. After the exception handler has executed, the processor

MOTOROLA MC68340 USER'S

MANUAL

5-79

must restore the system context in existence prior to the exception. The RTE instruction is designed to accomplish this task.

When RTE is executed, the processor examines the stack frame on top of the supervisor stack to determine if it is valid and determines what type of context restoration must be performed. See 5.6.4 CPU32

Stack

Frames for a description of stack frames.

For a normal four-word frame, the processor updates the status register and program counter with data pulled from the stack, increments the supervisor stack pointer by eight, and resumes normal instruction execution. For a sixword frame, the status register and program counter are updated from the stack, the active supervisor stack pointer is incremented by 12, and normal instruction execution resumes.

For a bus fault frame, the format value on the stack is first checked for validity.

In addition, the version number on the stack must match the version number of the processor that is attempting to read the stack frame. The version number is located in the most significant byte (bits [15:8]) of the internal register word at location SP

+

$14 in the stack frame. A validity check is used to ensure that data in a multiple processor system will be properly interpreted by an RTE instruction.

If a frame is invalid, a format error exception is taken. If it is inaccessible, a bus error exception is taken. Otherwise, the processor reads the entire frame into the proper internal registers, deallocates the stack (12 words), and resumes normal processing. Bus error frames for faults during exception processing require the RTE instruction to rewrite the faulted stack frame. If an error occurs during any of the bus cycles required by rewrite, the processor will halt.

If a format error occurs during RTE execution, the processor will create a normal four-word fault stack frame below the frame that it was attempting to use. If a bus error occurs, a bus cycle stack frame will be created. The faulty stack frame remains intact so that it may be examined and repaired by an exception handler or used by a different type processor (e.g., an MC68010, MC68020, or a future

M68000 processor) in a multiprocessor system.

5.6.3 Fault Recovery

There are four phases of recovery from a fault: recognizing the fault, saving the processor state, repairing the fault (if possible), and restoring the processor state. Saving and restoring the processor state are described in the following paragraphs.

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The stack contents are identified by the SSW. In addition to identifying the fault type represented by the stack frame, the SSW contains the internal processor state corresponding to the fault.

15 14 13 12 11 10 9

I

TP

I

MV

I

0

I

TR

I

81

I

80

I

RR RM

7

IN

6

I

RW

I

LG

4

SIZ

2 1

FUNC

TP-BERR Frame Type

MV-MOVEM in Progress

TR-Trace Pending

B1-Breakpoint Channel 1 Pending

BO-Breakpoint Channel a

Pending

RR-Rerun Write Cycle after RTE

RM-Faulted Cycle Was Read-Modify-Write

I N-/ nstruction/Other

RW-Read/Write of Faulted Bus Cycle

LG-Original Operand Size Was Long Word

SIZ-Remaining Size of Faulted Bus Cycle

FUNC-Function Code of Faulted Bus Cycle

The TP field defines the class of the faulted bus operation. Two BERR exception frame types are defined to support faults on prefetch and operand accesses and exception frame stacking: a

= Operand or prefetch bus fault

1

=

Exception processing bus fault

MV is set when the operand transfer portion of the MOVEM instruction is in progress atthe time of a bus fault. If a prefetch bus fault occurs while refetching the MOVEM opcode and extension word, both the MV and IN bits will be set in the stacked SSW.

0= MOVEM was not in progress when fault occurred

1

=

MOVEM was in progress when fault occurred

TR indicates that a trace exception was pending when a bus error exception was processed. The instruction that generated the trace will not be restarted upon return from the exception handler. This includes MOVEM and released write bus errors indicated by the assertion of either MV or RR in the SSW. a

= Trace not pending

1

=

Trace pending

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B1 indicates that a breakpoint exception was pending on channel 1 (external breakpoint source) when a bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception being processed.

0= Breakpoint not pending

1 = Breakpoint pending

BO indicates that a breakpoint exception was pending on channel 0 (internal breakpoint source) when the bus error exception was processed. Pending breakpoint status is stacked, regardless of the type of bus error exception being processed.

0= Breakpoint not pending

1 = Breakpoint pending

RR will be set in the SSW if the faulted bus cycle was a released write. If the write is completed (rerun) in the exception handler, the RR bit should be cleared before executing RTE. The bus cycle will be rerun if the RR bit is set upon return from the exception handler.

0= Faulted cycle was a read, RMW, or unreleased write

1 = Faulted cycle was a released write

Faulted RMW bus cycles set the RM bit in the SSW. This bit is ignored during unstacking.

0= Faulted cycle was a non-RMW cycle

1 = Faulted cycle was either the read or write of an RMW cycle

Instruction prefetch faults are distinguished from operand (both read and write) faults by the SSW IN bit. If IN is cleared, the error was on an operand cycle; if

IN is set, the error was on an instruction prefetch. IN is ignored during unstacking.

O=Operand

1 = Prefetch

Read and write bus cycles are distinguished by the SSW RW. Read bus cycles will set this bit, and write bus cycles will clear this bit. This bit is reloaded into the bus controller if the RR bit is set during unstacking.

0= Faulted cycle was an operand write

1 = Faulted cycle was a prefetch or operand read


An original operand size of long word is conveyed in the SSW LG bit. LG is cleared if the original size of the operand was byte or word; SIZ will indicate the original (and remaining) size. LG is set if the original size of the operand was long word; SIZ will indicate the remaining size at the time of the fault. LG is ignored during unstacking.

0= Original operand size was byte or word

1 = Original operand size was long word

The operand size remaining when the fault was detected is available in the SIZ field of the SSW. This field does not indicate the initial size of the operand. It does not necessarily indicate the proper status of a dynamically sized bus cycle.

Dynamic sizing occurs at the external bus and is transparent to the CPU32. The byte size is shown only when the original operand was a byte. This field is reloaded into the bus controller if the RR bit is set during unstacking. The SIZ field is encoded as follows:

00= Long word

01 = Byte

10=Word

11 = Unused, reserved

The function code for the faulted cycle is stacked in the FUNC field of the SSW, which is a copy of FC2-FCO for the faulted bus cycle. This field is reloaded into the bus controller if the RR bit is set during unstacking. All unused bits are stacked as zeros and are ignored during unstacking. Further discussion of the

SSW is included in 5.6.3.1 TYPES OF FAULTS.

5.6.3.1 TYPES OF FAULTS. An efficient implementation of instruction restart dictates that faults on some bus cycles be treated differently than faults on other bus cycles. The CPU32 defines four fault types: released write faults, faults during exception processing, faults during MOVEM operand transfer, and faults on any other bus cycle.

5.6.3.1.1 Type I: Released Write Faults. CPU32 instruction pipelining causes final instruction write to overlap the execution of the following instruction. A write that is overlapped is called a released write. Since the machine context is lost for the instruction that queued, the write is lost as soon as the following instruction starts. It is impossible to restart the faulted instruction.

Released write faults are taken at the next instruction boundary. The stacked program counter is that of the next unexecuted instruction. If a subsequent instruction attempts an operand access while a released write fault is pending,


the instruction is aborted, and the write fault is acknowledged. This action prevents stale data from being used by the instruction.

The SSW for a released write fault contains the following bit pattern:

15 14 13 12 11 10 9 8 7 6 5

I

0

I

0

I

0

I

TR

I

B1

I

BO

I

1

I

0

I

0

I

0

I

LG

I

SIZ FUNC

TR, B1, and BO are set if the corresponding exception is pending when the

BERR exception is taken. Status regarding the faulted bus cycle is reflected in the SSW LG, SIZ, and FUNC fields.

The remainder ofthe stack contains the program counter ofthe next unexecuted instruction, the current status register, the address of the faulted memory location, and the contents of the data buffer which was to be written to memory.

This data is written on the stack in the format depicted in Figure 5-21.

5.6.3.1.2 Type II: Prefetch, Operand, RMW, and MOVEP Faults. The majority of

BERR exceptions are included in this category all instruction prefetches, all operand reads, all RMW cycles, and all operand accesses resulting from execution of MOVEP (except the last write of a MOVEP Rn,(ea) or the last write of

MOVEM, which are type I faults). The TAS, MOVEP, and MOVEM instructions account for all operand writes not considered released.

All type II faults cause an immediate exception that aborts the current instruction. Any registers that were altered as the result of an effective address calculation (i.e., postincrement or predecrement) are restored prior to processing the bus cycle fault.

The SSW for faults in this category contains the following bit pattern:

15 14 13 12 11 10 9 8 7 6 5 4

I

0

I

0

I

0

I

0

I

B1

I

BO

I

0

I

RM

I

IN

I

RW

I

LG

I

SIZ FUNC

The trace pending bit is always cleared since the instruction will be restarted upon return from the handler. Saving a pending exception on the stack would result in a trace exception being taken prior to restarting the instruction. If the exception handler does not alter the stacked SR trace bits, the trace is requeued when the instruction is started.

The breakpoint pending bits are stacked in the SSW, even though the instruction is restarted upon return from the handler. This procedure avoids problems with


MOTOROLA

bus state analyzer equipment that has been programmed to breakpoint only the first access to a specific location or to count accesses to that location. If this response is not desired, the exception handler can clear the bits before return. The RM, IN, RW, LG, FUNC, and SIZ fields all reflect the type of bus cycle that caused the fault. If the bus cycle was an RMW, the RM bit will be set, and the RW bit will show whether the fault was on a read or write.

5.6.3.1.3 Type III: Faults during MOVEM Operand Transfer. Bus faults that occur as a result of MOVEM operand transfer are classified as type III faults. MOVEM instruction prefetch faults are type II faults.

Type III faults cause an immediate exception that aborts the current instruction.

None of the registers altered during execution of the faulted instruction are restored prior to execution of the fault handler. This includes any register predecremented as a result of the effective address calculation or any register overwritten during instruction execution. Since postincremented registers are not updated until the end of an instruction, the register retains its preinstruction value unless overwritten by operand movement.

The SSW for faults in this category contains the following bit pattern:

15 14 13 12 11 10 9 8 7 6 5 4

I

0

I

1

I

0

I

TR

I

81

I

80

I

RR

I

0

I

IN

I

RW

I

LG

I

SIZ

3 2 1

FUNC

MV is set, indicating that MOVEM should be continued from the point where the fault occurred upon return from the exception handler. TR, B1, and BO are set if a corresponding exception is pending when the BERR exception is taken.

IN is set if a bus fault occurs while refetching an opcode or an extension word during instruction restart. RW, LG, SIZ, and FUNC all reflect the type of bus cycle that caused the fault. All write faults have the RR bit set to indicate that the write should be rerun upon return from the exception handler.

The remainder of the stack frame contains sufficient information to continue

MOVEM with the operand transfer following a faulted transfer. The next operand to be transferred, incremented, or decremented is stored in the faulted address location ($08). The stacked transfer counter is set to 16 minus the number of transfers attempted (including the faulted cycle). Refer to Figure

5-21 for the stacking format.

5.6.3.1.4 Type IV: Faults during Exception Processing. The fourth type of fault occurs during exception processing. If the exception is a second address or bus error, the machine halts in the double bus fault condition. However, if the

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5-85

exception is one that causes a four- or six-word stack frame to be written, a bus cycle fault frame is written below the faulted exception stack frame.

The SSW for a fault within an exception contains the following bit pattern:

2

15 14 13 12 11 10 9 B 7 6 5 4

I

1

I

0

I

0

I

TR

I

81

I

80

I

0

I

0

I

0

I

1

I

LG

I

SIZ

3

FUNC

TR, B1, and BO are set if a corresponding exception is pending when the BERR exception is taken.

The contents of the faulted exception stack frame are included in the bus fault stack frame. The pre-exception status register and the format/vector word of the faulted frame are stacked. The type of exception can be determined from the format/vector word. If the faulted exception stack frame contains six words, the program counter of the instruction that caused the initial exception is, also stacked. This data is placed on the stack in the format shown in Figure 5-22.

The return address from the initial exception is stacked for RTE .

5.6.3.2 CORRECTING A FAULT. Fault correction methods are discussed in the following paragraphs.

There are two ways to complete a faulted released write (Type

I) bus cycle.

The first is to use a software handler. The second is to rerun the bus cycle via

RTE.

Type II fault handlers must terminate with RTE, but specific requirements must also be met before an instruction is restarted.

There are three varieties of Type III operand fault recovery. The first is completion of an instruction in software. The second is conversion to Type II with restart via RTE. The third is continuation from the fault via RTE.

5.6.3.2.1 (Type

I)

Completing Released Writes via Software. To complete a bus cycle in software, a handler must first read the SSW function code field to determine the appropriate address space, then access the fault address pointer in that space, and finally transfer data from the stacked image of the output buffer to the fault address.

Because the' CPU32 has a 16-bit internal data bus, long operands require two bus accesses. A fault during the second long-operand access causes the LG bit


MOTOROLA

in the SSW to be set. The SIZ field indicates remaining operand size. If operand coherency is important, the complete operand must be rewritten. After a long operand is rewritten, the RR bit must be cleared. Failure to clear the RR bit can cause RTE to rerun the bus cycle. Following rewrite, it is not necessary to adjust the program counter (or other stack contents) before executing RTE.

5.6.3.2.2 (Type

I)

Completing Released Writes via RTE. An exception handler can use the RTE instruction to complete a faulted bus cycle. When RTE executes, the fault address, data output buffer, program counter, and status register are restored from the stack. Any pending breakpoint or trace exceptions, as indicated by TR, 81, and 80 in the stacked SSW, are requeued during SSW restoration. The RR bit in the SSW is checked during the unstacking operation; if it is set, the RW, FUNC, and SIZ fields are used to rerun the released write cycle.

To maintain long-word operand coherence, stack contents must be adjusted prior to RTE execution. The fault address must be decremented by two if LG is set and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields should be left unchanged. The bus controller uses the modified fault address and SIZ field to rerun the complete released write cycle.

NOTE

Manipulating the stacked SSW can cause unpredictable results because RTE checks the RR bit but does not check the RW bit. The rerun bus cycle may not be a write or it may not access the same address space as the original bus cycle. If the rerun bus cycle is a read, returned data will be ignored.

5.6.3.2.3 (Type

II)

Correcting Faults via RTE. Instructions aborted due to a type II fault are restarted upon return from the exception handler. A fault handler must establish safe restart conditions. If a fault is due to a nonresident page in a demand-paged virtual memory configuration, the fault address must be read from the stack, and the appropriate page retrieved. An RTE instruction terminates the exception handler. After unstacking the machine state, the instruction is refetched and restarted.

MOTOROLA


5.6.3.2.4 (Type III ) Correcting Faults via Software. Sufficient information is contained in the stack frame to complete an instruction in software. After a fault is corrected, the faulted bus cycle must be rerun. The following steps are required to complete an instruction through software:

1.

Read the MOVEM opcode and extension from locations pointed to by stack frame PC and PC

+

2. The effective address need not be recalculated since the next operand address is saved in the stack frame. However, the opcode effective address field must be examined to determine how to update the address register and program counter when the instruction is' complete.

2. Adjust the mask to account for operands already transferred. Subtract the stacked operand transfer count from 16 to obtain the number of operands transferred. Scan the mask using this count value. Each time a set bit is found, clear it and decrement the counter. When the count is zero, the mask is ready for use.

3.

Adjust the operand address. If the predecrement addressing mode is in effect, subtract the operand size from the stacked value; otherwise, add the operand size to the stacked value.

4.

Scan the mask for set bits. Read/write the selected register from/to the operand address as each bit is found.

5. As each operand is transferred, clear the mask bit and increment (decrement) the operand address. When all bits in the mask are cleared, all . operands have been transferred.

6.

If the addressing mode is predecrement or postincrement, update the register to complete the execution of the instruction.

7.

If the TR bit is set in the stacked SSW, create a six-word stack frame and execute the trace handler. If either 81 or 80 in the SSW is set, create another six-word stack frame and execute the hardware breakpoint handier.

8. Deallocate the stack and return control to the faulted program.

5.6.3.2.5 (Type III) Correcting Faults by Conversion and Restart. In some situations, it may be necessary to rerun all the operand transfers for a faulted instruction rather than continue from a faulted operand. When a fault occurs

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MC68340 USER'S MANUAL,

MOTOROLA

after an operand has transferred, that transfer is not "undone". However, these memory locations are accessed a second time when the instruction is restarted.

Clearing the SSW MV bit will convert a type III fault into a type II fault. All type

II exceptions restart upon return from the exception handler.

NOTE

If a register used in an effective address calculation is overwritten before a fault occurs, an incorrect effective address is calculated upon instruction restart.

5.6.3.2.6 (Type III) Correcting Faults via RTE. The preferred method of MOVEM bus fault recovery is to correct the cause of the fault and then execute an RTE instruction without altering the stack contents. The RTE recognizes that MOVEM was in progress when a fault occurred, restores the appropriate machine state, refetches the instruction, repeats the faulted transfer, and continues the instruction.

MOVEM is the only instruction continued upon return from an exception handier. Although the instruction is refetched, the effective address is not recalculated, and the mask is rescanned the same number of times as before the fault. Modifying the code prior to RTE can cause unexpected results.

5.6.3.2.7 (Type IV) Correcting Faults via Software. BERR exceptions can occur during exception processing while the processor is fetching an exception vector or while it is stacking. The same stack frame and SSW are used in both cases, but each has a distinct fault address. The BERR stack frame format/vector word identifies the type of faulted exception and the contents of the remainder of the frame. A fault address corresponding to the stacked format/vector word indicates that the processor could not obtain the address of the exception handler.

A BERR exception handler should execute RTE after correcting a fault. RTE restores the internal machine state, fetches the address of the original exception handler, recreates the original exception stack frame, and resumes execution at the exception handler address.

If the fault is intractable, the exception handler should rewrite the faulted exception stack frame at SP

+

$14

+

$06 and then jump directly to the original exception handler. The stack frame can be generated from the information in the BERR frame: the pre-exception status register (SP

+

$OC)' the format/vector

MOTOROLA


word (SP

+

$OE), and, if the frame being written is a six-word frame, the program counter of the instruction causing the exception (SP

+

$1 0). The return program counter value is available at SP

+

$02.

A stacked fault address equal to the current stack pointer indicates that stacking was successfully completed even though a stacking bus error occurred. This is an extremely improbable occurrence, but the CPU32 supports recovery from it. Once the exception handler determines that the fault has been corrected, recovery can proceed as described previously. If the fault cannot be corrected, move the supervisor stack to another area of memory, copy all valid stack frames to the new stack, create a faulted exception frame on top of the stack, and resume execution at the exception handler address.

5.6.4 CPU32 Stack Frames

The CPU32 generates three different stack frames: the four-word, six-word frames and twelve-word BERR frames.

5.6.4.1 NORMAL FOUR-WORD STACK FRAME. This stack frame is created by interrupt, format error, TRAP #n, illegal instruction, A-line and F-line emulator trap, and privilege violation exception. Depending on the exception type, the program counter value is either the address of the next instruction to be executed or the address of the instruction that caused the exception (see Ftgure

5-21 ).

This stack frame is created by instruction-related traps, which include CHK,

CHK2, TRAPcc, TRAPV, and zero division, and by trace exceptions. The faulted instruction program counter value is the address of the instruction that caused the exception. The current program counter value (the address to which RTE returns) is the address of the next instruction to be executed.

SP.

+$02

15

+$06 o

I o

I o

I

0

I

STATUS REGISTER

PROGRAM COUNTER HIGH

PROGRAM COUNTER LOW

VECTOR OFFSET

Figure 5-21. Format $0 Four-Word Stack Frame

Hardware breakpoints also utilize this format. The faulted instruction program counter value is the address of the instruction executing when the breakpoint is sensed. Usually this is the address of the instruction that caused the break-

5-90


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point, but, because released writes can overlap a following instruction, the faulted instruction program counter may point to an instruction following the instruction that caused the breakpoint. The current program counter value (the address to which RTE returns) is the address of the next instruction to be executed (see Figure 5-22).

SP.

+$02

+$06

+$08

15

STATUS REGISTER

NEXT INSTRUCTION PROGRAM COUNTER HIGH o

I o

NEXT INSTRUCTION PROGRAM COUNTER LOW

I

1

I

0

I

VECTOR OFFSET

FAULTED INSTRUCTION PROGRAM COUNTER HIGH

FAULTED INSTRUCTION PROGRAM COUNTER LOW

Figure 5-22. Format $2 Six-Word Stack Frame

5.6.4.2 BERR STACK FRAME. This stack frame is created when a bus cycle fault is detected. The CPU32 BERR stack frame differs significantly from the equivalent stack frames of other M68000 Family members. The BERR stack frame is

12 words in length. There are three variations of the frame, each distinguished by different values in the SSW TP and MV fields.

The bus operation in progress at the time of a fault is conveyed by the SSW.

15 14 13 12 11 10 9 8 7 6 5 4

I

TP

I

MV

I

0

I

TR

I

B1

I

BO

I

RR

I

RM

I

IN

I

RW

I

LG

I

SIZ

1

FUNC

0

An internal transfer count register appears at location SP

+

14 in all BERR stack frames. The register contains an 8-bit microcode revision number, and, for type

III faults, an 8-bit transfer count. Register format is shown in the following illustration:

15

8 7 o

MICROCODE REVISION NUMBER TRANSFER CODE

The CPU32 checks the microcode revision number when it restores a BERR stack frame via RTE. In a multiprocessor system, this check ensures that the processor using the stacked information is at the same revision level as the processor that created it.

MOTOROLA


5-92

The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is set, the least significant byte of the internal register is reloaded into the MOVEM transfer counter during RTE execution.

For faults occurring during normal instruction execution (both prefetches and non-MOVEM operand accesses) SSW [TP:MV] =00. Stack frame format is shown in Figure 5-23.

SP.

+$02

+$06

+$08

+$OC

+$10

+$14

+$16

15

1

STATUS REGISTER

RETURN PROGRAM COUNTER HIGH

RETURN PROGRAM COUNTER LOW

VECTOR OFFSET

I

1

I

0

I

0

I

FAULTED ADDRESS HIGH

FAULTED AODRESS LOW

DBUF HIGH

DBUF LOW

CURRENT INSTRUCTION PROGRAM COUNTER HIGH o

I o

I

CURRENT INSTRUCTION PROGRAM COUNTER LOW

INTERNAL TRANSFER COUNT REGISTER

SPECIAL STATUS WORD

Figure 5-23. Format $C BERR Stack for Prefetches and Operands

Faults that occur during the operand portion of the MOVEM instruction.are identified by SSW [TP: MV]

=

01. Stack frame format is shown in Figure 5-24. o

SP.

+$02

+$06

+$08

+$OC

+$10

+$14

+$16

15

1

I

1

I o

I

1

I o

I o

I

STATUS REGISTER

RETURN PROGRAM COUNTER HIGH

RETURN PROGRAM COUNTER LOW

VECTOR OFFSET


FAULTED ADDRESS LOW

DBUF HIGH

DBUF LOW

CURRENT INSTRUCTION PROGRAM COUNTER HIGH

CURRENT INSTRUCTION PROGRAM COUNTER LOW


SPECIAL STATUS WORD

Figure 5-24. Format $C BERR Stack on MOVEM Operand


MOTOROLA

When a bus error occurs during exception processing, SSW [TP:MV]

=

10. The frame shown in Figure 5-25 is written below the faulting frame. Stacking begins at the address pointed to by SP 6 (SP value is the value before initial stacking on the faulted frame).

The frame can have either four or six words, depending on the type of error.

Four-word stack frames do not include the faulted instruction program counter

(the internal transfer count register is located at SP + $1 0 and the SSW is located at SP+$12).

The fault address of a dynamically sized bus cycle is the upper byte. There is no indication which of the two bytes caused the error.

SP.

+$02

+$06

+$08

+$OC

+$10

+$14

+$16

15

STATUS REGISTER

NEXT INSTRUCTION ROGRAM COUNTER HIGH

1

NEXT INSTRUCTION PROGRAM COUNTER LOW

I

1

I

0

I

0

I

VECTOR OFFSET


FAULTED ADDRESS LOW

PRE-EXCEPTION STATUS REGISTER

FAULTED EXCEPTION FORMATNECTOR WORD

1

I

0

FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLYI

FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLYI

I


SPECIAL STATUS WORD

Figure 5-25. Format $C Four- and Six-Word BERR Stack

5.7 DEVELOPMENT SUPPORT

All M68000 Family rl1embers include the following to facilitate applications development:

Trace on Instruction Execution M68000 processors include an instructionby-instruction tracing facility as an aid to program development; however, the MC68020, MC68030, and CPU32 also allow tracing only those instructions causing a change in program flow. In the trace mode, a trace exception is generated after each instruction is executed, allowing a debugger program to monitor the execution of a program under test. See 5.6.2.10 TRACING for more information.

MOTOROLA


Breakpoint Instruction An emulator may insert software breakpoints into the target code to indicate when a breakpoint has occurred. On the MC6801 0,

MC68020, MC68030, and CPU32, this function is provided via illegal instructions ($4848-$484F) that serve as breakpoint instructions. See 5.6.2.5 SOFT-

WARE BREAKPOINTS for more information.

Unimplemented Instruction Emulation When an attempt is made to execute an illegal instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, A-line, ... ) utilize separate exception vectors to permit efficient emulation of unimplemented instructions in software. See

5.6.2.8 ILLEGAL OR UNIMPLEMENTED INSTRUCTIONS for more information.

5.7.1 CPU32 Integrated Development Support

The CPU32 not only incorporates all the previous features but also provides additional features that aid development tools in advancing support for i'ntegrated system development. These additions include background debug mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in the single-chip environment.

5.7.1.1 BACKGROUND DEBUG MODE (BDM) OVERVIEW. Microprocessor systems generally provide a debugger, implemented in software, for system analysis at the lowest level. The BDM on the CPU32 is unique in that the debugger is implemented in CPU microcode. Registers can be viewed and/or altered, memory can be read or written to, and test features can be invoked. Incorporating these capabilities on-chip simplifies the environment in which an incircuit emulator operates. The traditional in-circuit emulator configuration (see

Figure 5-26) removes the processor from the target, replacing it with hardware resident in the emulator. An expensive cable provides the communication path between the target system and the emulator. By contrast, with an integrated debugger, the traditional emulator configuration can be replaced by a bus state analyzer (BSA) (see Figure 5-27). The advantage of this configuration is twofold:

1) the processor remains in the target hardware, serving as its own emulation processor and 2) this integration reduces cost by eliminating the cable. The

BSA provides a means for monitoring target processor operation; the on-chip debugger provides the mechanism for altering the operating environment.

Many of the problems experienced with the classic emulator configuration are minimized: i.e., limitations on high-frequency operation, AC and DC parametric mismatches, and restrictions on cable length.


MOTOROLA

IN-CIRCUIT

EMULATOR

TARGET

SYSTEM

Figure 5-26. Traditional In-Circuit Emulator Diagram

TARGET

SYSTEM

TARGET

MCU

i

"'

...

~

vi

BUS STATE

ANALVZER

~

"'

Figure 5-27. Bus State Analyzer Configuration

L,

5.7.1.2 DETERMINISTIC OPCODE TRACKING OVERVIEW. CPU32 function code outputs are augmented by two supplementary signals to monitor the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each new instruction and each mid-instruction pipeline advance. The instruction fetch

(IFETCH) output identifies those bus cycles in which the operand data is loaded into the instruction pipeline. Pipeline flushes are also signaled with IFETCH.

Monitoring these two signals allows a BSA to synchronize to the instruction stream and monitor the activity. Refer to 5.7.3 Deterministic Opcode Tracking for a complete description.

5.7.1.3 ON-CHIP HARDWARE BREAKPOINT OVERVIEW. An external breakpoint input and on-chip hardware breakpoint allow a breakpoint trap on any memory access. Off-chip address comparators preclude breakpoints on internal accesses unless show cycles are enabled. Breakpoints on instruction prefetches, which are ultimately flushed from the instruction pipeline, are not acknowledged; operand breakpoints are always acknowledged. Acknowledged breakpoints optionally initiate exception processing or BOM. See 5.6.2.6 HARDWARE

BREAKPOINTS for more information.

5.7.2 Background Debug Mode (BDM)

BOM is an alternate CPU32 operating mode in which normal instruction execution is suspended while special microcode performs the functions of a debugger. BOM is initiated by one of several sources: externally generated

MOTOROLA


5-95

breakpoints, internal peripheral breakpoints, the background (BGNO) instruction, or catastrophic exception conditions. While in BOM, the CPU32 ceases fetching instructions via the parallel bus and, instead, accepts commands via a dedicated serial interface. A high-speed, SPI-type serial link provides BOM communication between the CPU32 and the development system. Figure 5-28 illustrates a block diagram of the BOM.

SERIAL

INTERFACE

MICROCODE

SEQUENCER

EXECUTION

UNit

BUS

CONTROL

BKPTIDSCLK

DATA BUS

BERR

FREEZE

ADDRESS BUS

Figure 5-28. BDM Block Diagram

5.7.2.1 ENABLING BDM. Accidentally entering BOM in a nondevelopment environment could inadvertently lock up the CPU32 since the serial command interface would probably not be available. For this reason, BOM is enabled during reset via the breakpoint (BKPT) signal. When BKPT is asserted (low) at the rising edge on RESET, BOM operation is enabled until the next system reset. A high

BKPT signal at the trailing edge of RESET disables BOM, and all sources of entry revert to their normal operation. BKPT is relatched on each rising transition of RESET.

BKPT is synchronized internally; therefore, the signal must be held low for at least two clock cycles prior to the negation of RESET. Special care must be taken in the design of the BOM enable logic. If the hold time on BKPT (after


the trailing edge of RESET) extends into the first bus cycle, the possibility exists that the bus cycle could be inadvertently tagged with a breakpoint.

5.7.2.2 BDM SOURCES. Once BOM has been enabled, any of several sources are capable of causing the transition from normal operation into BOM. These sources include 1) external breakpoint hardware, 2) the BGNO instruction, 3) double bus fault, and 4) internal peripheral breakpoints. If BOM is not enabled when the exception condition occurs, the exception is processed normally. Table

5-21 summarizes the processing of each source for both the enabled and disabled cases. As depicted in the table, the BKPT instruction never causes a transition into the BOM of operation.

Table 5-21. 8DM Source Summary

Source

BKPT

Double Bus Fault

BGND Instruction

BKPT Instruction

BDM Enabled

Background

Background

Background

Opcode Substitution

Illegal Instruction

BDM Disabled

Breakpoint Exception

Halted

Illegal Instruction

Opcode Substitution

Illegal Instruction

5.7.2.2.1 External BKPT Signal. Once enabled, BOM is initiated whenever assertion of BKPT is acknowledged. If BOM is disabled, a breakpoint exception (vector

$OC) is acknowledged. Timing on the BKPT input is the same as that for read cycle data with respect to the trailing edge of data strobe. A breakpoint acknowledge bus cycle is not run when entering BOM.

5.7.2.2.2 BGND Instruction. An illegal instruction, $4AFA, is reserved for use by development tools. The CPU32 defines $4AFA (BGNO) to be a BOM entry point when BOM is enabled. If BOM is disabled, an illegal instruction trap is acknowledged. Illegal instruction traps are discussed in 5.6.2.8 ILLEGAL OR UNIMPLE-

MENTED INSTRUCTIONS.

5.7.2.2.3 Double Bus Fault. Two bus faults in succession, or a double bus fault, normally indicates that a catastrophic error has occurred within the system, resulting in the suspension of instruction execution. When this error condition occurs during initial system debug (e.g., a fault in the reset logic), further debugging is impossible until the situation is corrected. Through BDM, the fault can be bypassed temporarily, the cause of the problem can be determined,


5-97

and the effects of the problem can be corrected. Should 80M be disabled, a double bus fault causes the processor to terminate instruction execution until reset.

5.7.2.2.4 Peripheral Breakpoints. Peripherals capable of requesting breakpoints do so by asserting the BKPT signal. With respect to the CPU32, the operation of peripheral breakpoints is identical to that of external breakpoints. Consult the appropriate peripheral user's manual for additional details on the generation of peripheral breakpoints.

5.7.2.3 ENTERING BOM. Upon detecting a breakpoint or double bus fault or upon decoding a BGNO instruction, the processor suspends instruction execution and asserts the FREEZE output. This action is the first indication that the processor has entered BOM (see Figure 5-29). Once FREEZE has been asserted, the CPU32 enables the serial communication hardware and awaits the first command.

As part of the process of entering BOM, the CPU32 writes a unique value into temporary register A (ATEMP), indicating the source that caused the transition.

By issuing a read system register command as the initial command, the user can poll the register and determine the source (see Table 5-22).

Table 5-22. Polling the BOM Entry Source

Source

Double Bus Fault

BGND Instruction

Hardware Breakpoint

ATEMP [31:16]

SSW

$0000

$0000

ATEMP [15:0]

$FFFF

$0001

$0000

ATEMP is used in most debugger commands for temporary storage; therefore, it is imperative that the read system register (RSREG) command be the first command issued after the transition into BOM.

A double bus fault during the initial stack pointer/program counter (SP/PC) fetch sequence is further distinguished by a value of $FFFFFFFF in the current instruction PC. At no other time will the processor write an odd value into this register.


DEVELOPMENT SYSTEM ACnVITY CPU32 ACTIVITY

ENTER (BDM)

• ASSERT FREEZE SIGNAL

• WAIT FOR COMMAND

SEND INITIAL COMMAND

• LOAD COMMAND REGISTER

• ENABLE SHIFT CLOCK

• SHIFT OUT 17 BITS

• DISABLE SHIFT CLOCK

EXECUTE COMMAND

• LOAD: NOT READYI RESPONSE

• PERFORM COMMAND

• STORE RESULTS

-

-.

,

READ RESULTSINEW COMMAND

• LOAD COMMAND REGISTER

• ENABLE SHIFT CLOCK

• SHIFT INIOUT 17 BITS

• DISABLE SHIFT CLOCK

• READ RESULT REGISTER

'I'

IF RESULTS.

'NOTREADY"

YES

NO

CONTINUE

Figure 5-29. BDM Command Execution Flowchart

5.7.2.4 COMMAND EXECUTION. As each command is accumulated in the serial shifter, the microcode routine corresponding to that command is executed. If the command can complete without additional serial traffic, it does. However, if addresses or operands are required, the microcode reads each word as it is assembled by the serial interface. The CPU32 then performs the desired operation, including any necessary memory or register accesses. Result operands are loaded into the output shift register to be shifted out as the next command is read. This process is repeated for each instruction until the CPU32 returns to the normal operating mode.

5.7.2.5 BACKGROUND MODE REGISTERS. The following paragraphs describe three special-purpose registers used in 80M.

MOTOROLA 5-99


5.7.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulted bus cycle immediately following a bus or address error. This address remains available until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR contains the address of the last bus cycle. The address of the first fault (if one occurred) is not visible to the user.

5.7.2.5.2 Return Program Counter (RPC). The RPC points to the location from which fetching will commence at the transition from BOM into normal mode.

This register should be accessed to change the flow of a program under development. Changing the RPC to an odd value causes an address error, which is generated when fetching begins.

5.7.2.5.3 Current Instruction Program Counter (PCC). The PCC holds the pointer to the first word of the last instruction executed prior to the transition into

BOM. Oue to the pipelined nature of the CPU32, the instruction pointed to by the PCC may not be the instruction that caused the BOM transition. An example is a breakpoint on a released write. The bus cycle may extend into as many as two subsequent instructions before stalling the instruction sequencer. A breakpoint asserted during this cycle will not be acknowledged until the end of the instruction executing at the completion of the bus cycle.

5.7.2.6 RETURNING FROM 80M. BOM is terminated when a resume execution

(GO) or call user code (CALL) command is received. Both GO and CALL flush the instruction pipeline and prefetch instructions from the location pointed to by the current PC. The current PC and the memory space referred to by the status register SUPV bit reflect any changes made during BOM. FREEZE is negated prior to initiating the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals revert to IPIPE/IFETCH functionality.

5.7.2.7 SERIAL INTERFACE. Communication with the CPU32 during BOM sessions occurs via a dedicated serial interface, which shares pins with other development features. The BKPT signal becomes the serial clock (OSCLK); serial input data (OSI) is received on IFETCH, and serial output data (OSO) is transmitted on IPIPE.

The serial interface is a full-duplex synchronous protocol similar to the serial peripheral interface protocol. The development system serves as the master of the serial link since it is responsible for the generation of OSCLK. By deriving

5-100


MOTOROLA

DSCLK from the CPU32 system clock, the design of the development system serial logic is unhindered by the operating frequency of the target processor.

Operable frequency range of the serial clock is from DC to one-half the processor system clock frequency.

The serial interface operates in a full-duplex mode that is, data is both transmitted and received simultaneously by the master and slave devices. In general, data transitions occur on the falling edge of the DSCLK and are stable by the following rising edge of DSCLK. Data is transmitted most significant bit first and is latched on the rising edge of DSCLK.

The serial data word is 17 bits wide 16 data bits and a status/control bit.

16 15

I

SIC

STATUS/CONTROL

DATA FIELD o

For CPU-generated messages, bit 16 indicates the message status as shown in

Table 5-23.

Bit 16

0

0

1

1

1

Table 5-23. CPU-Generated Message Encoding

Data Message Type

xxxx

Valid Data Transfer

FFFF

Command Complete; Status OK

0000

Not Ready with Response; Come Again

0001

BERR Terminated Bus Cycle; Data Invalid

FFFF

Illegal Command

Command and data transfers initiated by the development system should clear bit 16. The current implementation ignores this bit; however, Motorola reserves the right to use this bit for future enhancements.

5.7.2.7.1 CPU32 Serial Logic. The CPU32 serial logic block diagram, pictured in the left-hand portion of Figure 5-30, consists of the transmit and receive shift registers and control logic containing the synchronization logic, serial clock generation circuitry, and a received bit counter.

MOTOROLA


5-102

CPU

INSTRUCTION

REGISTER BUS

__

'~_"_"""""W'''''~'_~''''''_''''!

DEVELOPMENT SYSTEM

1

I

DATA

I

I

PARAlLELIN

SERIAL OUT

DSI

SERIAL IN

PARALLEL OUT

PARALLELIN

SERIAL OUT

STATUS

EXECUlJ~I~~L....-

_ _ _ _

16

SERIAL IN

PARALLEL OUT

STATUS

DATA

~

................................................................................................... "" .. " ........................ J

DSCLK

SERIAL

CLOCK

..........................................................................

"

................

~

Figure 5-30. Debug Serial 1/0 Block Diagram

Both DSCLK and DSI are synchronized to the on-chip clocks, thereby minimizing the chance of propagating metastable states into the serial state machine. Data is sampled during the high phase of CLKOUT. At the falling edge of CLKOUT, the sampled value is made available to the internal logic. Thus, the minimum hold time on DSI with respect to DSCLK is one full period of CLKOUT.

The serial state machine begins a sequence of events based on the rising edge of the synchronized DSCLK (see Figure 5-31). The synchronized serial data is transferred to the input shift register, and the received bit counter is decremented. One-half clock period later, the output shift register is updated, bringing the next output bit to the DSO signal. DSO changes relative to the rising edge of DSCLK and does not necessarily remain stable until the falling edge of DSCLK.


CLKOUT

FREEZE

~

DSCLK r-

DSI

SAMPLE

WINDOW

INTERNAL

SYNCHRONIZED

DSCLK

~ B.

~

B.

~

I I

INTERNAL

SYNCHRONIZED

DSI

DSO

CLKOUT

Figure 5-31. Serial Interface Timing Diagram

One clock period after the synchronized DSCLK has been seen internally, the updated counter value is checked. If the counter has reached zero, the receive data latch is updated from the input shift register. At this same time, the output shift register is reloaded with the "not ready/come again" response. Once the receive data latch has been loaded, the CPU32 is released to act on the new data. Response data overwrites the "not ready" response when the CPU32 has completed the current operation.

Data written into the output shift register appears immediately on the DSO signal. In general, this action changes the state of the signal from a high ("not ready" response status bit) to a low (valid data status bit) logic level. However, this level change only occurs if the command completes successfully. Error conditions overwrite the "not ready" response with the appropriate response that also has the status bit set.

A user may take advantage of the state change on DSO to signal hardware that the next serial transfer may begin. A timeout of sufficient length should also be incorporated into the design to trap error conditions that do not change the state of DSO. Hardware interlocks in the CPU32 prevent result data from corrupting serial transfers in progress.

MOTOROLA


5.7.2.7.2 Development System Serial Logic. The development system, as the master of the serial data link, must supply the serial clock. However, normal and BOM operations could inadvertently interact if the dual operating modes are not properly considered when designing the clock generator.

Breakpoint requests are made by asserting BKPT to the low state using one of two methods. The predominant method (one described thus far) is to assert

BKPT during the single bus cycle for which the exception is desired. A second method is to assert BKPT and continue asserting it until the CPU32 responds by asserting FREEZE. This method is useful for forcing a transition into BOM when the bus is not being monitored. Each BKPT assertion method requires a slightly different approach in the design of the serial logic to avoid spurious serial clocks.

Figure 5-32 represents the timing required for asserting BKPT during a single bus cycle. Figure 5-33 depicts the timing of the BKPT/FREEZE method. In both cases, the serial clock is left high after the final shift of each transfer. This technique eliminates the possibility of accidentally tagging the prefetch initiated at the conclusion of a BOM session. As mentioned previously, all timing within the CPU32 is derived from the rising edge of the clock; the falling edge is effectively ignored.

FORCE_BGND - - - - - - - - - - - - - - - - - - - - - - - - - -

~~-------------------------------------

BKPT

L

Figure 5-32. BKPT Timing for Single Bus Cycle

SHIFT_CLK

FORCE_BGND

_

5-104

L

Figure 5-33. BKPT Timing for Forcing BOM


MOTOROLA

Figure 5-34 represents a sample circuit providing for both BKPT assertion methods. As the name implies, FORCE-BGNO is used to force a transition into BOM by the assertion of BKPT. FORCE-BGNO can be a short pulse or can remain asserted until FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first SHIFT -ClK is applied.

8KPT_TAG --~

SHIFT_CLK --,-------~~

RESET

FORCE_8GND --~L-

_ _

Figure 5-34. BKPT/DSCLK Logic Diagram

BKPT -TAG should be timed to the bus cycles since it is not latched. If extended past the assertion of FREEZE, the negation of BKPT -TAG appears to the CPU32 as the first OSClK.

OSClK is the gated serial clock. Normally high, it pulses low for each bit to be transferred. At the end of the seventeenth clock period, it returns high until the start of the next transmission. Clock frequency is implementation dependent and may range from OC to the maximum specified frequency. Although performance considerations might dictate a hardware implementation, software solutions are not precluded provided serial bus timing is maintained.

5.7.2.8 COMMAND SET. The following paragraphs describe the command set available in BOM.

5.7.2.8.1 Command Format. The following standard bit format is utilized by all

BOM commands.

15 14 13 12

OPERATION

11 10 8

I

0

I

RfW

I

OP SIZE

I

0 o

I

AID

I

REGISTER

EXTENSION WORD(S)

Operation Field:

Commands are distinguished by the operation field. This 6-bit field provides for a maximum of 64 unique commands.

MOTOROLA


5-105

RIW

Field:

The direction of the operand transfer is specified in this field. When this bit is set, the operation direction is from the CPU32 to the development system.

When this bit is clear, data is written into the CPU32 or memory from the development system.

Operand Size:

For sized operations, this field specifies the operand data size. All addresses are expressed as 32-bit absolute values. The size field is encoded as listed in Table 5-24.

Table 5-24. Size Field Encoding

Encoding

00

01

10

11

Operand Size

Byte

Word

Long

Reserved

AddresslData (AID)

Field:

Used by commands that operate on address and data registers, the

AID

field determines whether the register field specifies a data or address register. A one indicates an address register; a zero selects a data register. For other commands, this field may be interpreted differently.

Register Field:

In most commands, this field specifies the register number when operating on an address or data register.

Extension Words (as required):

Some commands require immediate data or addresses in the form of extension words. Addresses require two extension words each since addressing capability is limited to absolute long. Immediate data can be either one or two words. Byte and word data each require a single extension word; longword data requires two words. Operands and addresses are transferred most significant word first. At this time, no command requires an extension word to fully specify the operation to be performed (i.e., single-word commands only).

5.7.2.8.2 Command Sequence Diagrams. A command sequence diagram illustrates the serial bus traffic for each command. Each bubble in the diagram represents a single 17-bit transfer across the bus. The top half in each diagram

5-106


corresponds to the data transmitted by the development system to the CPU32; likewise, the bottom half corresponds to the data returned by the CPU32 in response to the development system commands. Command and result transactions are overlapped to minimize latency.

The command sequence diagram in Figure 5-35 demonstrates the use of these diagrams. The cycle in which the command is issued contains the command mnemonic issued by the development system (in this example, read memory location). During the same cycle, the CPU32 is responding with either the lowest order results of the previous command or with a command complete status if no other results were required.

COMMANDS TRANSMITIED TO THE CPU32

COMMAND CODE TRANSMITIED DURING THIS CYClE

HIGH-ORDER 16 BITS OF MEMORY ADDRESS

LOW-ORDER 16 BITS OF MEMORY ADDRESS

NONSERIAL-RELA TED ACTIVITY

SEQUENCE TAKEN IF

OPERATION HAS NOT

COMPLETED

DATA UNUSED FROM

THIS TRANSFER

SEQUENCE TAKEN IF

ILLEGAL COMMAND

IS RECEIVED BY CPU32

RESULTS FROM PREVIOUS COMMAND

RESPONSES FROM THE CPU

SEQUENCE TAKEN IF BUS ERROR

OR ADDRESS ERROR OCCURS ON

MEMORY ACCESS

HIGH- AND LOW-ORDER

16 BITS OF RESULT

Figure 5-35. Command Sequence Diagram Example

During the second cycle of the diagram, the development system supplies the high-order 16 bits of the memory address. The CPU32 returns the

I I not ready" response unless the received command was decoded as unimplemented, in which case the response data is the illegal command encoding. If an illegal command response occurs, the development system should retransmit the command.

MOTOROLA


NOTE

The "not ready" response can be ignored except in those cases when a memory bus cycle is in progress. In all other cases, the CPU32 can accept a new serial transfer with eight system clock periods.

In the third cycle, the development system supplies the low-order 16 bits of the memory address. The CPU32 always returns the "not ready" response in this cycle. At the completion of the third cycle, the CPU32 initiates the memory read operation. Any serial transfers that begin while the memory access is in progress return the "not ready" response.

The results are returned in the two serial transfer cycles following the completion of the memory access. The data transmitted to the CPU32 during the final transfer is the opcode for the following command. Should the memory access generate either a bus or address error, an error status is returned in place of the result data.

5-108


MOTOROLA

5.7.2.8.3 Command Set Summary. The 8DM command set is summarized in Table

5-25. Detailed descriptions of each command can be found in subsequent paragraphs.

Command

Read AID Register

Write AID Register

Read System Register

Write System Register

Read Memory Location

Write Memory Location

Dump Memory Block

Fill Memory Block

Resume Execution

Call User Code

Reset Peripherals

No Operation

Table 5-25. 80M Command Summary

Mnemonic

RAREG/RDREG

WAREGIWDREG

RSREG

WSREG

READ

WRITE

DUMP

FILL

GO

CALL

RST

NOP

Description

Read the selected address or data register and return the results via the serial interface.

The data operand is written to the specified address or data register.

The specified system control register is read. All registers that can be read in supervisor mode can be read in BDM.

The operand data is written into the specified system control register.

Read the sized data at the memory location specified by the long-word address. The source function code (SFC) register determines the address space accessed.

Write the operand data to the memory location specified by the long-word address. The destination function code (DFC) register determines the address space accessed.

Used in conjunction with the READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command.

Used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command.

The pipeline is flushed and refilled before resuming instruction execution at the current PC.

Current PC is stacked at the location of the current

SP. Instruction execution begins at user patch code.

Asserts RESET for 512 clock cycles. The CPU32 is not reset by this command. Synonymous with the

CPU32 RESET instruction.

NOP performs no operation and may be used as a null command.

MOTOROLA


5-109

5.7.2.8.4 Read

AID

Register (RAREG/RDREG). Read the selected address or data register and return the results via the serial interface.

Command Format:

15 14 13 12 11 10 o

I

0 o

1

AID I

REGISTER

Command Sequence:

Operand Data:

None

Result Data:

The contents of the selected reg'ister are returned as a long-word value. The data is returned most significant word first.

NOTE

Accesses to register A7 follow the supervisor (S) bit at the time 8DM was entered. If S

=

0, A7 corresponds to the user SP; if S

=

1, A7 corresponds to the supervisor SP. 8DM writes to the SR, which affect the

S-bit, have no effect on the selection of A7. Use the RSREG/WSREG commands to directly access a specific SP.

5.7.2.8.5 Write

AID

Register (WAREG/WDREG). The operand (long-word) data is written to the specified address or data register. All 32 bits of the register are altered by the write.

Command Format:

15 14 13 12 11 10 9,

0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1

3 o

1 0 1 0 1 AID 1

REGISTER

5-110


MOTOROLA

Command Sequence:

Operand Data:

The long-word data is written into the specified address or data register. The data is supplied most significant word first.

Result Data:

Command complete status ($OFFFF) is returned when the register write has completed.

NOTE

Accesses to register A7 follow the S-bit at the time 80M was entered.

If S

=

0, A7 corresponds to the user SP; if S

=

1, A7 corresponds to the supervisor SP. 80M writes to SR, which affect the S-bit, have no effect on the selection of A7. Use the RSREGIWSREG commands to directly access a specific SP.

5.7.2.S.6 Read System Register (RSREG). The specified system control register is read. All registers that can be read in supervisor mode can be read in 80M.

Several internal temporary registers are also accessible.

Command Format:

15 14 13 12 11 10 o

I

0

I

REGISTER

Command Sequence:

MOTOROLA


5-111

Operand Data:

None

Result Data:

Always returns 32 bits of data, regardless of the size of the register being read. If the register is less than 32 bits, the result is returned zero extended.

Register Field:

The system control register is specified by the register field (see Table 5-26).

Table 5-26. Register Field for RSREG

System Register

Return Program Counter (RPC)

Current Instruction Program Counter (PCC)

Select Code

0000

0001

Status Register (SR)

User Stack Pointer (USP)

Supervisor Stack Pointer (SSP)

Source Function Code Register (SFC)

1011

1100

1101

1110

Destination Function Code Register (DFC)

Temporary Register A (ATEMP)

Fault Address Register (FAR)

Vector Base Register (VBR)

1111

1000

1001

1010

5.7.2.8.7 Write System Register (WSREG).

The operand data is written into the specified system control register. All registers that can be written in supervisor mode can be written in 80M. Several internal temporary registers are also

. accessible.

Command Format:

15 14 13 12 11 o

10

I

1 o

I

0

I

1 o

I

0

I

0

I

REGISTER

Command Sequence:

5-112


MOTOROLA

Operand Data:

The data to be written into the register is always supplied as a 32-bit long word. If the written register is less than 16 bits, the least significant word is used.

Result Data:

"Command complete" status is returned when the register write is completed.

Register Field:

The system control register is specified by the register field (see Table 5-27).

The FAR is a read-only register; any write to this register is ignored.

Table 5-27. Register Field for WSREG

System Register

Return Program Counter (RPC)

Current Instruction Program Counter (PCC)


User Stack Pointer (USP)

Select Code

0000

0001

1011

1100

Supervisor Stack Pointer (SSP)

Source Function Code Register (SFC)

Destination Function Code Register (DFC)

Temporary Register A (ATEMP)

Fault Address Register (FAR)

Vector Base Register (VBR)

1101

1110

1111

1000

1001

1010

5.7.2.8.8 Read Memory Location (READ). Read the sized data at the memory location specified by the long-word address. Only absolute addressing is supported. The source function code (SFC) register determines the address space accessed. Valid data sizes include byte, word, or long word.

Command Format:

15 14 13 12 11 10 o

1 0 1

1

1

OP SIZE

010101 0 1010

MOTOROLA


5-113

Command Sequence:

Operand Data:

The single operand is the long-word address of the requested memory location.

Resu It Data:

The requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result with the upper byte cleared. Word results return 16 bits of significant data; long-word results return 32 bits.

A successful read operation returns data bit 16 cleared; whereas, if a bus or address error is encountered, the returned data is $10001.

5.7.2.8.9 Write Memory Location (WRITE). Write the operand data to the memory location specified by the long-word address. The destination function code

(DFC) register determines the address space accessed. Only absolute addressing is supported. Valid data sizes include byte, word, and long word.

Command Format:

15 14 13 12 11 10

0.10 1 OPSIZE

0 1 0 1 0 1 0 1 0 1 0

5-114


MOTOROLA

Command Sequence:

Operand Data:

Two operands are required for this instruction. The first operand is a longword absolute address specifying the location to which the operand data is to be written. The second operand is the data. Byte data is transmitted as a

16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted as 16 and 32 bits, respectively.

Result Data:

Successful write operations return a status of $OFFFF. Bus or address errors on the write cycle are indicated by the assertion of bit 16 in the status message and by a data pattern of $0001.

5.7.2.8.10 Dump Memory Block (DUMP). DUMP is used in conjunction with the

READ command to dump large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. Subsequent operands are retrieved with the DUMP command. The initial address is incremented by the operand size (1,2, or 4) and saved in a temporary register.

Subsequent DUMP commands use this address, increment it by the current operand size, and store the updated address back in the temporary register.

MOTOROLA


5-115

NOTE

The DUMP command does not check to see that a valid address is present in the temporary register. Therefore, DUMP is a valid command only when preceded by another DUMP or by a READ command; otherwise, the results are undefined.

The size field is examined each time a DUMP command is given, allowing the operand size to be altered dynamically.

Command Format:

15 o

14

I

0

13

12 11 10

OP SIZE

I

0 o

I

0 o

I

0

I

0

Command Sequence:

Operand Data:

None

Resu It Data:

The requested data is returned as either a word or long word. Byte data is returned in the least significant byte of a word result. Word results return 16 bits of significant data; long-word results return 32 bits. Status of the read operation is returned as in the READ command: $Oxxxx for success, $10001 for bus or address errors.

5-116

MC68340 USER'S

MANUAL

MOTOROLA

5.7.2.8.11 Fill Memory Block (FILL). FILL is used in conjunction with the WRITE command to fill large blocks of memory. An initial WRITE is executed to set up the starting address of the block and to supply the first operand. Subsequent operands are written with the FILL command. The initial address is incremented by the operand size (1,2, or 4) and is saved in a temporary register. Subsequent

FILL commands use this address, increment it by the current operand size, and store the updated address pack in the temporary register.

NOTE

The FILL command does not check to see that a valid address is present in the temporary register. Therefore, FILL is a valid command only when preceded by another FILL or by a WRITE command; otherwise, the resulrs are undefined.

The size field is examined each time a FILL command is given, allowing the operand size to be altered dynamically.

Command Format:

15 14 13 12 11 10 o

I

0

OP SIZE

Command Sequence:


5-117

Operand Data:

A single operand is data to be written to the memory location. Byte data is transmitted as a 16-bit word, justified in the least significant byte; 16- and

32-bit operands are transmitted as 16 and 32 bits, respectively.

Resu It Data:

Status is returned as in the WRITE command: $OFFFF for a successful operation and $10001 for a bus or address error during write.

5.7.2.8.12

Resume Execution

(GO).

The pipeline is flushed and refilled before normal instruction execution is resumed. Prefetching begins at the current PC and current privilege level. If either the PC or SR is altered during BDM, the updated value of these registers is used when prefetching commences.

NOTE

A bus error or address error on the first instruction prefetch from the new PC allows BDM to exit and to be trapped as a normal mode exception. The stacked value of the current PC mayor may not be valid in this case, depending on the state of the machine prior to entering BDM. In the case of an address error, the PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return

PC.

Command Format:

15 14 13 12 11 10 o

I

0

I

0

I

0 o

I

0

I

0

Command Sequence:

Operand Data:

None

Result Data:

None

5-118


MOTOROLA

5.7.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch user code. The current PC is stacked at the location pointed to by the current SP (SP selected by S-bit latched when BOM entered). The stacked PC serves as a return address to be restored by the return from subroutine (RTS), which terminates the patch routine. The 32-bit operand data is then loaded into the PC. The pipeline is flushed and refilled from the location pointed to by the new PC. BOM is exited, and instruction execution is initiated.

As an example, consider the following code segment that is supposed to output a character to an asynchronous communications interface adaptor. Note the missing check of the transmit data register empty (TORE) flag.

CHKSTAT MOVE.B

BEQ.B

MOVE.B

ACIAS,OO

CHKSTAT

OATA,ACIAO

Move ACIA status to 00

Loop till condition true

Output data

MISSING ANOI.B

RTS

#2,00 Check for TORE

Return to in-line code

BOM and the CALL command can be used to insert the missing code by observing the following sequence:

1.

Breakpoint user program at CHKSTAT;

2. Enter BOM;

3. Execute CALL command to MISSING; Exit BOM;

4. Execute MISSING code; and

5. Return to user program.

NOTE

Bus errors or address errors that occur during stacking of the return address cause the CPU32 to return an error status via the serial interface and to remain in BOM. A bus error or address error on the first instruction prefetch from the new PC allows BOM to exit and to be trapped as a normal mode exception. The stacked value of the current

PC mayor may not be valid in this case, depending on the state of the machine prior to entering BOM. In the case of an address error, the return PC does not reflect the true return PC. Instead, the stacked fault address is the (odd) return PC.


5-119

Command Format:

15 14 13 12 11 10

1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0

010101010

Command Sequence:

Operand Data: .

The 32-bit operand data is the starting location of the patch routine, which is the initial PC upon exiting 80M.

Result Data:

None

5.7.2.8.14 Reset Peripherals (RST). RST asserts RESET for 512 clock cycles. The

CPU32 is not reset by this command. This command is synonymous with the

CPU32 RESET instruction.

Command Format:

15 14 13 12 11

10

1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 o

I

0

Command Sequence:

5-120


MOTOROLA

Operand Data:

None

Resu It Data:

The IIcommand complete" response ($OFFFF) is loaded into the serial shifter after the negation of RESET.

5.7.2.8.15 No Operation (NOP). NOP performs no operation and may be used as a null command where required.

Command Format:

15 14 13 12 11 10

0 1 0 1 0 1 0 1 0 1 0 010 a

I a

Command Sequence:

Operand Data:

None

Result Data:

The IIcommand complete" response ($OFFFF) is returned during the next shift operation.

5.7.2.8.16 Future Commands. Unassigned command opcodes are reserved by

Motorola for future expansion. All unused formats within any revision level will perform a NOP and return the ILLEGAL command.

5.7.3 Deterministic Opcode Tracking

The CPU32 utilizes deterministic opcode tracking to trace program execution.

Two new signals, IPIPE and IFETCH , provide all the information required to analyze the operation of the instruction pipeline.

5.7.3.1 INSTRUCTION FETCH (lFETCH). IFETCH indicates which bus cycles are accessing data to fill the instruction pipeline. IFETCH is pUlse-width modulated

MOTOROLA


5-121

to multiplex two indications on a single pin. Asserted for a single clock cycle,

IFETCH indicates that the data from the current bus cycle is routed to the instruction pipeline. IFETCH held low for two clock cycles indicates that the instruction pipeline has been flushed. The operand of the bus cycle is used to begin filling the empty pipeline. Both user and supervisor mode fetches are signaled by IFETCH.

Proper tracking of bus cycles via the IFETCH signal on a fast bus requires a simple state machine. On a two-clock bus, IFETCH may signal a pipeline flush with associated prefetch and a consecutive prefetch. That is, IFETCH remains asserted for three clocks, two clocks indicating the flush/fetch and a third clock signaling the second fetch. These two operations are easily discerned if the tracking logic samples IFETCH on the two rising edges of CLKOUT, which follow the address strobe (data strobe during show cycles) falling edge. Three-clock and slower bus cycles allow time for negation of the signal between consecutive indications and do not experience this operation.

5.7.3.2 INSTRUCTION PIPE (lPIPE). IPIPE signals the advances of the internal instruction pipeline (see Figure 5-36). The pipeline can be modeled as a threestage FIFO in which data can be used out of both the second and third stages.

The instruction register B (lRB) stage, which provides for initial decoding of the opcode and decoding of any extension words, is a source for immediate data. On the other hand, the IRC stage supplies residual decoding of the opcode during instruction execution. Assertion of IPIPE for a single clock cycle indicates the use of data out of the second stage (lRB). Regardless of the presence of valid data in the initial stage (lR), the contents of IRB are invalidated. If the IR stage contains valid data, the data is copied into IRB (lR. IRB), and the IRB stage is revalidated.

5-122

DATA

BUS

R

B

R

C

EXTENSION

WORDS

OPCODES

RESIDUAL

Figure 5-36. Functional Model of Instruction Pipeline


MOTOROLA

Assertion of IPIPE for two clock cycles indicates the start of a new instruction and subsequent replacement of data in the final stage (IRC). This action causes a full advance of the pipeline: IRS. IRC and IR • IRS. IR is refilled during the next instruction fetch bus cycle. Data loaded into IR propagates through empty pipeline stages automatically, which implies that an accurate model of pipeline operation should include valid bits for the IR and IRS stages. Advancing the pipeline, either explicitly via IPIPE or implicitly by negated valid bits, should set the valid bit of the stage being loaded and negate the valid bit of the register supplying the data.

Secause instruction execution is not timed to bus activity, IPIPE is synchronized with the system clock and not the bus. Figure 5-37 illustrates the timing in relation to the system clock. IPIPE should be sampled on the falling edge of the clock. The assertion of IPIPE for a single cycle after deassertion for one or more cycles indicates a use of the data in IRS (advance of IR into IRB). Assertion for two clock cycles indicates that a new instruction has started and both the

IR • IRS and IRS. IRC transfers have occurred. Loading IRC always indicates that a new instruction is beginning execution. The opcode is the word loaded into IRC by the transfer.

In some cases, instructions using immediate addressing initiate the start of an instruction and a second pipeline advance. That is, the IPIPE signal is not to be negated between the two indications, which implies the need for a state machine to track the state of IPIPE. The state machine can be resynchronized during periods of inactivity on the signal.

CLKOUT

EXTENSION

WORD USED

INSTRUCTION

START

EXTENSION

WORD USED

,-_--1,----

INSTRUCTION

START

Figure 5-37. Instruction Pipeline Timing Diagram

5.7.3.3 OPCODE TRACKING DURING LOOP MODE. IPIPE and IFETCH continue to work normally during loop mode. IFETCH indicates all instruction fetches up through the point that data begins recirculating within the instruction pipeline.

IPIPE continues to signal the start of instructions and the use of extension words even though data is being recirculated internally. IFETCH returns to normal operation with the first fetch after exiting loop mode.


5.S

INSTRUCTION EXECUTION TIMING

This section, which describes the instruction execution timing of the CPU32 using external clock cycles, provides accurate execution and operation timing guidelines but not exact timings for every possible circumstance. This approach is used since exact execution time for an instruction or operation is highly dependent on concurrency of independently scheduled resources, memory speeds, and other variables. The timing numbers presented in this section allow the assembly language programmer or compiler writer to predict the performance of the CPU32. Additionally, the timings for exception processing are included so that designers of multitasking or real-time systems can predict taskswitch overhead, maximum interrupt latency, and similar timing parameters.

Instruction timings are given in clock cycles to eliminate clock frequency dependencies.

5.S.1

Resource Scheduling

Some of the variability in instruction execution timings results from the overlap of resource utilization. The processor can be viewed as consisting of several independently scheduled resources. Since little of the resource scheduling is directly related to instruction boundaries, it is impossible to make accurate estimates of the time required to execute a particular instruction without knowing the complete context within which the instruction is executing. The position of these resources within the CPU32 is shown in Figure 5-38.

5.8.1.1

MICROSEQUENCER.

The microsequencer is either executing microinstructions or awaiting completion of accesses necessary to continue executing microcode. The microsequencer controls the bus controller, instruction execution, and internal processor operations such as calculation of effective address and setting of condition codes. The microsequencer initiates instruction word prefetches after a change of flow and controls the validation of instruction words in the instruction pipeline.

5.8.1.2

INSTRUCTION PIPELINE.

The CPU32 contains a two-word instruction pipeline where instruction opcodes are decoded. As shown in Figure 5-38, instruction words (instruction operation words and all extension words) enter the pipeline at stage B. To reach stage C, an instruction word must have been completely decoded. Each of the pipeline stages has a status bit that reflects whether or not the word in that stage was loaded with data from a bus cycle which terminated abnormally. Stages of the pipeline are filled from an initial request by the microsequencer and are subsequently filled by the prefetch controller as they are emptied.


MOTOROLA

The instruction pipeline contains an additional stage which serves as a buffer.

Prefetches completing on the bus before stage B of the instruction pipeline have been emptied are temporarily stored in this buffer.

MICROSEQUENCER AND CONTROL

EXECUTION UNIT

PROGRAM

COUNTER

SECTION

DATA

SECTION

DATA

BUS

ADDRESS

BUS

BUS CONTROL

SIGNALS

Figure 5-38. Block Diagram of Independent Resources

5.8.1.3 BUS CONTROLLER RESOURCES. The bus controller and microsequencer can operate concurrently. The bus controller can perform a read or write or schedule a prefetch while the microsequencer controls an effective address calculation or sets the condition codes. The microsequencer may also request a bus cycle that the bus controller cannot perform immediately. In this case, the bus cycle is queued, and the bus controller runs the cycle when the current cycle is complete.

The bus controller consists of the instruction prefetch controller, the writepending buffer, and the microbus controller. These three resources transact all reads, writes, and instruction prefetches required for instruction execution.


5-125

5.8.1.3.1 Prefetch Controller. The instruction prefetch controller receives an initial request from the microsequencer to initiate prefetching at a given address.

Subsequent prefetches are requested by the prefetch controller whenever a pipeline stage is invalidated, either through completion of an instruction or use of extension words. The prefetch occurs as soon as the bus is free of operand accesses already requested by the microsequencer. Additional state information permits the controller to inhibit prefetch requests when a change in instruction flow (e.g., JMP) is anticipated.

For the typical program, a change of flow can be expected in approximately

10 to 25 percent of the instructions executed. Each time this happens, the instruction pipeline must be flushed and refilled from the new instruction stream.

If priority were given to instruction prefetches rather than to operand accesses, it is likely that many instruction words would be flushed and never used, meanwhile delaying needed operand cycles. To maximize the available bus bandwidth, the CPU32 will schedule a prefetch only when the next instruction is not a change-of-flow instruction and when room exists in the pipeline for the prefetch.

5.8.1.3.2 Write-Pending Buffer. The CPU32 incorporates a single-operand writepending buffer, allowing the microsequencer to continue execution after the

. request for a write cycle is queued in the bus controller. The time occupied by the write at the end of an instruction can utilize the next instruction's ,head cycle time, thus reducing overall execution time. Interlocks prevent the microsequencer from overwriting this buffer.

5.8.1.3.3 Microbus Controller. The microbus controller performs the bus cycles issued to the bus controller by the microsequencer. Operand accesses always take priority over instruction prefetches. Word and byte operands are accessed in a single CPU-initiated bus cycle, although the external bus interface may be required to initiate a second cycle in the case of a word operand to a bytesized external port. Long operands are accessed in two bus cycles, the most significant word first.

The goal of the bus controller is to maximize the useful bandwidth of the bus by not starting prefetches when those prefetches will be discarded due to a change of flow. The instruction pipeline is capable of recognizing certain instructions like branches and RTS and informs the bus controller that no more prefetches are required.

5-126


MOTOROLA

5.8.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock cycles, that an instruction executes concurrently with the previous instruction. As illustrated in Figure 5-39, portions of instructions A and B execute simultaneously. The overlapped portion of instruction B is absorbed in the execution time of A. Similarly, the overlap time between instructions Band C reduces the overall execution time of the two instructions. Each instruction contributes to the total overlap time. The portion of the time at the end of the execution time of instruction A that can overlap at the beginning of instruction

B is called the tail of instruction A. The portion of time at the beginning of instruction B that can overlap the end of instruction A is called the head of instruction B. The total overlap time between instructions A and B consists of the lesser of the tail of A and the head of B.

I----INSTRUCTIONA

---~

I----INSTRUCTION B

- - - - l

I-----INSTRUCTION C

- - - - l

OVERLAP

OVERLAP

Figure 5-39. Simultaneous Instruction Execution

The execution time attributed to instructions A, B, and C after considering the overlap is illustrated in Figure 5-40. The overlap time is attributed to the execution time of the completing instruction. The following equation shows the method for calculating the overlap time:

Overlap

= in (TaiIN, HeadN

+

1)

MOTOROLA


I----IINSTRUCTION A

- - - - I t-----INSTRUCTION B

- - - - l

I-----INSTRUCTION C

- - - - I

OVERLAP

PERIOD

(ABSORBED BY

INSTRUCTION A)

OVERLAP

PERIOD

(ABSORBED BY

INSTRUCTION B)

Figure 5-40. Attributed Instruction Times

5.8.1.5 EFFECTS ,OF WAIT STATES. The CPU32 is capable of accessing on-chip memory and peripherals with an access time of two clocks. While it is possible to get two-clock external accesses when the bus is operated in a synchronous mode, the typical external memory speed is three clocks or more.

All instruction times given in the following timing tables assume that both instruction fetches and operand cycles are to the two-clock memory and are for word access only (unless explicitly mentioned otherwise). Any time a long access is made, the time for the additional bus cycle(s) must be added to the overall execution time. Wait states due to slow external memory must be added into that memory for each bus cycle.

A typical application will have a mixture of bus speeds: e.g., program executing from an off-chip ROM, accesses to on-chip peripherals, storage of variables in a slower off-chip RAM, and external peripherals with speeds ranging from moderate to very slow. To arrive at an accurate instruction time calculation, each bus access must be individually considered. Many instructions have a head cycle count, which can overlap the cycles of an operand fetch to slower memory started by the previous instruction. For such cases, the increase in access time has no effect on the total execution time of that pair of instructions.

When tracing the execution time of instructions by monitoring the external bus, note that the order of operand accesses is always the same for a particular instruction sequence, and, provided the bus speed is identical across those sequences, the interleaving of instruction prefetches with operands is also identical.

5-128


MOTOROLA

5.8.1.6

INSTRUCTION EXECUTION TIME CALCULATION.

The overall execution time for an instruction may depend on the overlap with the previous and following instructions. Therefore, to calculate instruction time estimations, the entire code sequence must be analyzed as a whole. To derive the actual instruction execution times for an instruction sequence, the instruction times listed in the tables must be adjusted to account for the overlap with previous and subsequent instructions.

The formula for this calculation is as follows:

C1-min (T1, H2)+C2-min (T2, H3)+C3-min (T3, H4)+ ... where:

CN is the number of cycles listed for instruction N

HN is the head time for instruction N

TN is the tail time for instruction N min (TN, HM) is the minimum of parameters TN and HM

The number of cycles for the instruction (CN above) can also be composed of one or two effective address calculations in addition to the raw number in the cycles column. In these cases, overall instruction time is calculated as if it were multiple instructions according to the following equation:

(CEA) - min (TEA, HOp) + COP where:

(CEA) is the instruction's effective address time

COP is the instruction's operation time

HOp is the instruction operation's head time

TEA is the effective address' tail time min (TN, HM) is the minimum of parameters TN and HM

The overall head for the instruction is the head for the effective address, and the overall tail for the instruction is the tail for the operation. Therefore, the actual equation of the execution time becomes:

COp1 - min (T Op1, HEA2) + (CEA2) - min

(TEA2, HOP2)+COP2-min (TOP2, HEA3)+ ...

MOTOROLA


5-129

Every instruction must prefetch to replace itself in the instruction pipe. Usually, these prefetches occur during or after the instruction. A prefetch is permitted to begin in the first clock of any indexed effective addressing mode. Additionally, a prefetch for an instruction is permitted to begin two clocks before the end of an instruction, provided the bus is not being used. If the bus is being used, then the prefetch will occur at the next available time when the bus would otherwise be idle.

5.8.1.7

EFFECTS OF NEGATIVE

TAILS. When the CPU32 changes instruction flow, the instruction decode pipeline must begin refilling before instruction execution can resume. Refilling forces a two-clock idle period at the end of the changeof-flow instruction, which can be used to prefetch an additional word on the new instruction path. Because of the stipulation that each instruction must prefetch to replace itself, the concept of negative tails has been introduced to account for these free clocks on the bus.

On a two-clock bus, it is not necessary to adjust the instruction timings to account for the potential extra prefetch. The cycle time of the microsequencer and bus are matched; therefore, no additional benefit or penalty is obtained.

On slower buses, negative tails are used to compensate for the pipeline delays by increasing the caculated instruction overlap. Normally, increasing the length of prefetch bus cycles directly affects the cycle count and tail values found in the tables. By using the following equations, negative tail values are used to negate the effects of the slower bus.

Note that many instructions listed as having negative tails are change-of-flow instructions and that the bus speed used in the calculation is the new instruction stream.

5-130


MOTOROLA

Use the following equations to apply a negative tail on a bus slower than two clocks. However, the equations are generalized so that they can be used on any speed bus with any tail value.

NEW-TAIL=OLD-TAIL+(NEW-CLOCK-2)

IF ((NEW-CLOCK-4) >0) then

NEW-CYCLE = OLD-CYCLE + (NEW-CLOCK - 2) + (NEW-CLOCK - 4)

ELSE

NEW-CYCLE = OLD-CYCLE + (NEW-CLOCK - 2) where:

NEW-TAIL/NEW-CYCLE is the adjusted tail/cycle at the slower speed

OLD-TAIL/OLD-CYCLE is the value listed in the instruction timing tables

NEW-CLOCK is the number of clocks per cycle at the slower speed

5.8.2 Instruction Stream Timing Example

Some programming examples will allow a more detailed examination of these effects. For all examples, the memory access is from external synchronous memory, the bus is idle, and the instruction pipeline is full at the start.

5.S.2.1 TIMING EXAMPLE 1: EXECUTION OVERLAP. The example shown in Figure 5-41 illustrates the overlapping of execution due to the bus controller's ability to execute bus cycles while the sequencer is calculating the next effective address. One clock is saved between each instruction since that is the minimum time of the individual head and tail numbers.


5-131

2

Instructions

MOVE.W

AOOO.W

CLR.W

A1, (AO)+

#1, (AO)

$30 (A1) o

7 8

CLOCK

BUS

CONTROLLER

3

PREWRITE r--1-':"'~-1--':~~Er~bmdqrm±E_~dL---':I-t_F_E_TC_H-t......:...FO~R:..::3---1

INSTRUCTION

Jb~~lmmd~EE~bmEEmm±mQl

__

1--1 __

CLR

<_E~ l

EXECUTION

TIME

MOVE.WA1,(AO)+ CLR.w$30(A1)

L ____________ -LlmmgmmgmmmillmmmillR_L ______________

---.J

Figure 5-41. Example 1 Instruction Stream

5.8.2.2 TIMING EXAMPLE 2: BRANCH INSTRUCTIONS. Example 2 shows what happens when a branch instruction is executed for both the taken and nottaken cases (see Figures 5-42 and 5-43). The instruction stream is for a simple limit check with the variable already in a data register.

Instructions

MOVEO

CMP.L

BLE.B

MOVE.L

6

#7,01

01,00

NEXT

01, (AO) o

CLOCK

CONTROL~~~ 1-~_lT_~E_H --W.ii:ml~§l;;T~;gEHgI4--1----_1__-lE-~-~H~~:-E~-~H--pl·ilri::::::~:.i:~~ci]ci:~:±]I!lb~~

INSTRUCTION

CONTROLLER

MOVEO

Ilil:::::::::~~::::.::]11 O~~t~T

TAKEN TAKEN TAKEN il[::::::~~y:::::11111

EXECUTION

TIME

BLE.B NOT TAKEN

Figure 5-42. Example 2 Branch Taken


o

CLOCK

BUS

CONTROLLER

INSTRUCTION

CONTROLLER

EXECUTION

TIME

1 PRE·

FETCH

3 PRE·

FETCH

MOVEa

#7,01

NOT

TAKEN

:f':':':'~~~':':':'l::

.......

?~.~.~.?

...... :::

BLE.B NOTTAKEN ilil:~:~~~!:~lllli

II![:::::::::::::::::::::.:::::~~~;'~~::~:~:~~~~~:::::::::::::::::::::::::::::::::]111

Figure 5-43. Example 2 Branch Not Taken

5.8.2.3 TIMING EXAMPLE 3: NEGATIVE TAILS. This example (see Figure 5-44) shows how to properly account for the negative tail figures for branches and other change-of-flow instructions. For this example, the bus speed is assumed to be four clocks per access. Instruction three is at the branch destination.

Instructions

MOVEQ

BRA.W

MOVE.L

#7,01

FARAWAY

01,00

The CPU32 has a two-word instruction pipeline, but, due to internal delays, the minimum time for a branch instruction allows three bus cycles. The negative tail is intended to serve as a reminder that on a fast bus an extra two clocks are available for prefetching a third word but that on a slower bus the third word is not forced to be fetched.

CLOCK

BUS

CONTROLLER

INSTRUCTION

CONTROLLER

EXECUTION

TIME

Figure 5-44. Example 3 Branch Negative Tail


MOTOROLA

5-133

Example 3 actually illustrates three different considerations in calculating the time for an instruction. The branch instruction does not attempt to prefetch beyond the minimum number of words needed for itself; the negative tail allows execution to begin sooner than would be calculated for a three-word pipeline; and there is a one-clock delay caused by the displacement arriving late at the CPU32.

The negative tail only needs to be calculated on changes of flow, but the concept can be generalized to any instruction so that only two words are required to be in the pipeline, but up to three words may be present. When there is an opportunity for the extra prefetch, it is made. A prefetch to replace an instruction can begin ahead of the instruction, resulting in a faster processor.

5.8.3

Instruction Timing Tables

The following assumptions apply to the times shown in the tables in this section:

• A 16-bit data bus is used for all memory accesses.

• All memory accesses occur with two-clock bus cycles and no wait states.

• The instruction pipeline is full at the beginning of the instruction and is refilled by the end of the instruction.

Three values are listed for each instruction and addressing mode:

Head

Tail

Cycles

This value is the number of cycles at the beginning of the instruction available for the previous instruction's write to complete or for a prefetch to occur.

This value is the number of cycles at the end of the instruction used by the instruction to complete a write.

This field contains four numbers per entry, three of which are contained in parenthesis. The outer number represents the minimum number of cycles required for the instruction to complete. Within the parenthesis, the numbers represent the number of bus accesses performed by the instruction. The first number inside the parenthesis is the number of operand read accesses performed by the instruction. The second number is the number of instruction fetches performed by the instruction, including all prefetches to keep the instruction and the instruction pipeline filled. The third number is the number of write accesses performed by the instruction.

5-134


TOTAlNUMBEROFCLOCKS~~r

NUM'EROF READ CYCLES

NUMBER OF INSTRUCTION ACCESS CYCLES ml

NUMBER OF WRITE CYCLES

The total number of bus-activity clocks and internal clocks (not overlapped by bus activity) of the instruction in this example are derived as follows:

(2 reads 2 clocks/read)

+

(1 instruction access x 2 clocks/access)

+

(0 writes x 2 clocks/write)

=

6 clocks of bus activity

8 clocks total- 6 clocks bus activity

=

2 internal clocks

One example from the timing tables is the ADD.L (12, A3, D7.W· 4), D2 instruction, with the instructions and data from two-clock memory. The effective addressing mode is listed as head

=

4, tail

=

4, cycles

=

10 (2/1/0). The difference from FEA timing table (see 5.8.3.1 FETCH EFFECTIVE ADDRESS) is because the table is listed for word accesses, and this example is for a long access. The instruction itself has a head

=

0, tail

=

0, and cycles

=

2(0/1/0) from the arithmetic/ logical timing table (see 5.8.3.5 ARITHMETIC/LOGICAL INSTRUCTIONS). Assuming no trailing write exists from the previous instruction, the execution time is calculated in the following manner.

The effective address calculation requires six clocks, with the replacement fetch for the effective address occurring during this time (leaving a head of four):. If there had not been time in the head to perform the prefetch due to a previous trailing write, then time must be allotted in the middle of the instruction or after the tail to do the prefetches. The read of the memory requires two bus cycles at two clocks each. This read time, implied in the tail figure for the effective address, cannot be overlapped with the instruction since the instruction has a head of zero. An additional two clocks are required for the actual

ADD, which makes the total 6

+

4

+

2

=

12 clocks. If the bus cycles take more time (i.e., the memory is off-chip), then add the appropriate number of clocks to each memory access.

An example of the overlapped execution possible on the CPU32 is with the instruction sequence MOVE.L DO, (AO) followed by LSL.L #7, D2. The MOVE has a head of zero and a tail of four, since it is a long write. The LSL has a head of four; therefore, the trailing write from the MOVE will overlap the LSL completely. Thus, this two-instruction sequence has a head of zero and a tail

5-135


of zero and a total execution of eight clocks instead of 12 clocks obtained by adding the individual cycle times.

General observations regarding calculation of execution time are as follows:

• Any time the number of bus cycles is listed as "y," substitute a value of one for byte and word cycles and a value of two for long cycles. For long bus cycles, usually add a value of two to the tail.

• The time calculated for an instruction on a three-clock (or longer) bus is usually longer than the actual execution time. All times shown are for twoclock bus cycles.

• If the previous instruction has a negative tail, then a prefetch for the current instruction may begin during the execution of the previous instruction in advance of the instruction needing the prefetch.

• Certain instructions requiring an immediate extension word (immediate word effective address, absolute word effective address, address register indirect with displacement effective address, conditional branches with word offsets, bit operations, LPSTOP, TSL, MOVEM, MOVEC, MOVES,

MOVEP, MUL.L, DIV.L, CHK2, CMP2, and DScc) are not permitted to begin until the extension word has been in the instruction pipeline for at least one cycle. This does not apply to long offsets or displacements.


MOTOROLA

5.S.3.1

FETCH EFFECTIVE

ADDRESS. The fetch effective address table indicates the number of clock periods needed for the processor to calculate and fetch the specified effective address. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

On

An

(An)

(An)+

-(An)

(d16)

(d32)

(An)

(Xm.SzxSc)

Instruction

(d16,An) or (d16,PC)

(yyy).W

(yyy).L

#(data).W

#(data).B

#(data).L

(d8,An,Xn.Sz x Sc) or (d8,PC,Xn.Sz x Sc)

(0) (All Suppressed)

(An,Xm.Sz x Sc)



(d16,An,Xm) or (d16,PC,Xm)

2

1

1

1

4

4

Head

-

-

1

1

2

1

1

1

1

1

1

4

1

1

Tail

-

-

5

1

2

2

2

2

3

1

1

2

3

3

5

1

1

3

3

5

2

Cycles Notes

0(0/010)

0(01010)

3(y/010)

-

-

1

3(y/010)

4(y/010)

5(y/1/0)

5(y/1/0)

1

1

1,3

1

7(y/2/0)

3(0/1/0)

3(01110)

5(0/2/0)

7(y/2/0)

9(y/3/0)

1

1

1

1

8(y/1l0)

1,2,3,4

6(y/1/0)

1,4

1,4

1,4

5(y/1/0)

8 (yJ1l0)

1,2,4

1,2,4

8(y/1/0)

1,2,3,4

7(y/2/0)

1,3,4

9(y/3/0)

1,3,4

8(y/2/0)

1,3,4

9(y/3/0)

1,3,4 (d32,An,Xm) or (d32,PC,Xm)

2

1 3

(d16,An,Xm.Sz x Sc) or (d16,PC,Xm.Sz x Sc) 2 2

8(y/2/0)

1,2,3,4

(d32,An,Xm.Sz x Sc) or (d32,PC,Xm.Sz x Sc)

1 3

9(y/3/0)

1,2,3,4 y

=

There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles.

NOTES:

1. The read of the effective address and replacement fetches overlap the head of the operation by the amount specified in the tail.

2. Size and scale of the index register do not affect execution time.

3. The program counter may be substituted for the base address register An.

4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts.

MOTOROLA


5-137

5.8.3.2

CALCULATE EFFECTIVE ADDRESS.

The calculate effective address table indicates the number of clock periods needed for the processor to calculate the specified effective address. The timing is equivalent to fetch effective address except there is no read cycle. The tail and cycle time are reduced by the amount of time the read would occupy. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

Dn

An

(An)

(An)+

-(An)


(yyy).W

(yyy).L

(da,An,Xn.Sz x ScI or (da,PC,Xn.Sz x ScI

(0) (All Suppressed)

(d16)

(d32)

(An)

(Xm.SzxSc)

(An,Xm.Sz x ScI

Instruction Head

-

-

1

1

2

1

1

1

4

2

1

1

1

4

Tail

-

-

0

0

0

1

1

3

0

0

1

3

0

0

Cycles Notes

0(01010)

0(01010)

2(01010)

2(01010)

2(01010)

3(0/1/0)

3(0/1/0)

5(0/2/0)

6(01110)

4(01110)

5(0/2/0)

7(0/3/0)

4(01110)

6(01110)

-

-

-

-

-

1,3

1

1

2,3,4

4

1,4

1,4

4

2,4

2,4

4

0

6(01110)


1 1

5(0/2/0)

1,3,4

(d32,An) or (d32,PC) 1 3

7(0/3/0)

1,3,4

(d16,An,Xm) or (d16,PC,Xm) 2 0

6(0/2/0)

3,4

(d32,An,Xm) or (d32,PC,Xm) 1 1

7(0/3/0)

1,3,4

(d16,An,Xm.Szx ScI or (d16,PC,Xm.Sz x ScI

(d32,An,Xm.Sz x ScI or (d32,PC,Xm.Sz x ScI

2

1

0

1

6(0/2/0)

2,3,4

7(0/3/0)

1,2,3,4 y

=

There is one bus cycle for byte and word oper(lnds and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and to the number of cycles.

NOTES:

1. Replacement fetches overlap the head of the operation by the amount specified in the tail.

2. Size and scale of the index register do not affect execution time.

3. The program counter may be substituted for the base address register An.

4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from the head until the head reaches zero, at which time additional clocks must be added to both the tail and cycle counts.

5-138


MOTOROLA

5.8.3.3 MOVE INSTRUCTION. The MOVE instruction table indicates the number of clock periods needed for the processor to calculate the destination effective address and to perform the MOVE or MOVEA instruction. For entries with CEA or FEA, refer to the appropriate table to calculate this portion of the instruction timing. The destination effective addresses are divided by their formats (refer to 5.3.4.4 EFFECTIVE ADDRESS ENCODING SUMMARY). The total number of clock cycles is outside the parentheses. The numbers inside parentheses

(r/pl

w) are included in the total clock cycle number. All timing data assumes twoclock reads and writes.

When using this table, begin at the top and move downward. Use the first entry that matches both source and destination addressing modes.

Instruction

MOVE Rn, Rn

MOVE (FEA), Rn

MOVE Rn, (Am)

MOVE Rn, (Am)

+

MOVE Rn, - (Am)

MOVE Rn, (CEA)

MOVE #, (CEA)

MOVE (FEA), (An)

MOVE (FEA), (An)

+

MOVE (FEA), - (An)

Head

0

0

0

2

2

2

1

2

1

2

Tail

0

0

2

1

2

3

2

2

2

2

Cycles

2(011/0)

2(0/1/0)

4(0/1/y)

5(0/1/y)

6 (Ol1ly)

5(0/1/y)

6(0/1/y)*

6 (Ol1ly)

6(0/1/y)

6(0/1/y)

MOVE (CEA), (FEA) 2 2

6(0/1/y)

y

=


*

=

An

# fetch effective address time must be added for this instruction

(e.g., (FEA)

+

(CEA)

+

(OPER)).

NOTE:

For instructions not explicitly listed, use the (MOVE (CEA), (FEA)) entry.

The source effective address is calculated by the calculate effective address table, and the destination effective address is calculated by the fetch effective address table, even though the bus cycle is for the source effective address.

5.8.3.4 SPECIAL-PURPOSE MOVE INSTRUCTION. The special-purpose MOVE instruction table indicates the number of clock periods needed for the processor to fetch, calculate, and perform the special-purpose MOVE operation on the control registers or specified effective address. Footnotes indicate when to account for the appropriate effective address times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

MOTOROLA


5-140

EXG

MOVEC

MOVEC

MOVE

MOVE

MOVE

MOVE

MOVE

MOVE

MOVE

MOVE

MOVEM.L

MOVEM.L

MOVEP.W

MOVEP.W

MOVEP.L

Instruction

MOVEM.W

MOVEM.W

Rn, Rm

Cr, Rn

Rn, Cr

CCR,On

CCR, (CEA)

On,CCR

(FEA), CCR

SR,On

SR, (CEA)

On,SR

(FEA), SR

(CEA), RL

RL, (CEA)

(CEA), RL

RL, (CEA)

On, (d16, An)

(d16, An), On

On, (d16, An)

MOVEP.L

(d16, An), On

MOVES (Save) (CEA), Rn

MOVES (Op) (CEA), Rn

MOVES (Save) Rn, (CEA)

1

1

1

2

0

4

0

1

1

2

1

1

7

1

Head

2

10

12

2

0

2

0

2

Tail

0

0

0

0

2

0

0

0

2

-2

-2

0

2

0

2

0

0

0

2

1

1

1

Cycles

4(0/1/0)

14(012/0)

14-16(0/1/0)

4(0/1/0)

4(0/1/1)

4(0/1/0)

4(0/1/0)

4(0/1/0)

4(0/1/1 )

10(013/0)

10(0/3/0)

8+n·4(n+1, 2, 0)*

8+ n·4(0, 2, n)*

12+n·4(2n+2, 2, 0)

10+ n·4(0, 2, 2n)

10(0/2/2)

11 (2/2/0)

14(0/2/4)

19(4/2/0)

3(0/110)

11(y/1/0)

3(0/1/0)

MOVES (Op) Rn, (CEA) 9 2

12(0/1/y)

MOVE USP, An 0 0

2(011/0)

MOVE An,USP 0 0

2(0/1/0)

SWAP On 4 0

6(0/1/0)

y

=


*

=

Each bus cycle may take up to four clocks without increasing total execution time.

Cr

=

Control registers USP, VBR, SFC, and OFC n

=

Number of registers to transfer

RL

=

Register list

<

=

Maximum time is indicated; certain data or mode combinations may execute faster.

NOTE: The MOVES instruction involves a save step which other instructions do not have. To calculate total the instruction time, calculate the save, the effective address, and the operation execution times, and combine in the order listed, using the equations given in 5.8.1.6 INSTRUCTION

EXECUTION TIME CALCULATION.


MOTOROLA

5.8.3.5 ARITHMETIC/LOGICAL INSTRUCTIONS. The arithmetical/logical instruction table indicates the number of clock periods needed for the processor to perform the specified arithmetical/logical instruction using the specified addressing mode. Footnotes indicate when to accountforthe appropriate effective address times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number.

All timing data assumes two-clock reads and writes.

MOTOROLA


5-141

5-142

ADD(A)

ADD(A)

ADD

AND

AND

AND

EaR

EaR

OR

OR

OR

SUB (A)

SUB (A)

Instruction

Rn, Rm

(FEA), Rn

Dn, (FEA)

Dn, Dm

(FEA), Dn

Dn, (FEA)

Dn, Dm

Dn, (FEA)

Dn, Dm

(FEA), Dn

Dn, (FEA)

Rn, Rm

(FEA), Rn

SUB

CMP(A)

Dn, (FEA)

Rn, Rm

CMP(A) (FEA), Rn

CMP2 (Save) (FEA), Rn

CMP2 (Op)

MULsu.W

(FEA), Rn

(FEA), Dn

MULsu.L (Save)(FEA), Dn

MULsu.L (Op) (FEA), Dn

DIVU.W (FEA), Dn

DIVS.W

DIVU.W

(FEA), Dn

(FEA), Dn

DIVS.W (FEA), Dn

DIVU.L (Save) (FEA), Dn

DIVU.L (Op) (FEA), Dn

DIVS.L (Save) (FEA), Dn

DIVS.L (Op)

TBLsu

(FEA), Dn

Dn:Dm, Dp

TBLsu (Save) (CEA), Dn

TBLsu (Op) (CEA), Dn

TBLNs Dn:Dm, Dp

TBLNs (Save) (CEA), Dn

TBLNs (Op) (CEA), Dn

TBLNu

Dn:Dm, Dp

TBLNu (Save)

(CEA), Dn

TBLNu (Op) (CEA), Dn

0

0

1

0

1

0

0

0

1

0

0

1

0

0

1

0

0

1

0

3

0

0

0

3

0

0

1

0

0

Tail

0

3

0

3

0

0

0

3

0

0

0

1

2

1

2

0

0

1

2

26

1

30

1

6

6

30

1

6

0

0

0

0

0

0

0

1

2

0

Head

0

0

0

0

0

0

0

0

0

Cycles

2(0/1/0)

2(0/1/0)

5(0/1/V)

2(0/1/0)

2(0/1/0)

5(0/1/v)

2(0/1/0)

5(0/1/v)

2(0/1/0)

62(01010)

28-30(

0/2/0)

3(0/110)

33-35(2V/1/0)

30-34(

0/2/0)

3(0/1/0)

35-39(2V/l/0)

34-40(01210)

3(0/1/0)

29-45(2V/l/0)

2(0/1/0)

5(0/1/V)

2(0/1/0)

2(0/1/0)

5(0/1/V)

2(0/1/0)

2(0/1/0)

3(0/1/0)

18(V/1/0)

26(0/1/0)

3(0/1/0)

50(01010)

32(0/1/0)

42(0/1/0)

32(0/1/0)

42(0/1/0)

3(0/110)

46(01010)

3(0/1/0)


MOTOROLA

y

=

There is one bus cycle for byte and word operands and two bus cycles for long operands. For long bus cycles, add two clocks to the tail and

< to the number of cycles.

=

Maximum time is indicated; certain data or mode combinations will execute faster. su

=

The execution time is identical for signed or unsigned operands.

NOTE: The CMP2, MUL.L, DIV.L, TBL, and TBLN instructions involve a save step which other instructions do not have. To calculate the total instruction time, calculate the save, the effective address, and the operation execution times, and combine in the order listed, using the equations given in 5.8.1.6 INSTRUCTION EXECUTION TIME CAL-

CULATION.

S.S.3.6

IMMEDIATE ARITHMETIC/LOGICAL INSTRUCTIONS.

The immediate arithmetical/logical instruction table indicates the number of clock periods needed for the processor to fetch the source immediate data value and to perfo~m the specified arithmetical/logical instruction using the specified addressing mode.

Footnotes indicate when to account for the appropriate fetch effective or fetch immediate effective address times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

Instruction Head Tail Cycles

MOVEO

AD DO

ADDO

SUBO

SUBO

ADDI

ADDI

ANDI

#,Dn

#,Rn

#, (FEA)

#,Rn

#, (FEA)

#,Rn

#, (FEA)

#,Rn

0

0

0

0

0

0

0

0

3

0

3

0

0

0

3

0

2(0/1/0)

2(0/1/0)

5(011/y)

2(011/0)

5(0/1/y)

2(0/1/0)*

5(0/1/y)*

2(0/1/0)*

ANDI

EORI

#, (FEA)

#, Rn

0

0

3

0

5(0/1/y)*

2(01110)*

EORI

ORI

#, (FEA)

#,Rn

0

0

3

0

5(0/1/y)*

2(0/1/0)*

ORI #, (FEA)

0 3

5(0/1/y)*

SUBI

SUBI

#,Rn

#, (FEA)

0

0

0

3

2(0/1/0)*

5(0/1/y)*

CMPI

CMPI

#,Rn

#, (FEA)

0

0

0

3

2(0/1/0)*

5(0/1/y)*

y

=


*

=

An # fetch effective address time must be added for this instruction

(e.g., (FEA)+(FEA)+(OPER»).

MOTOROLA MC68340 USER'S MANUAL 5-.143

5.8.3.7 BINARY-CODED DECIMAL AND EXTENDED INSTRUCTIONS. The binarycoded decimal and extended instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

ABCD

ABCD

SBCD

SBCD

ADDX

ADDX

SUBX

SUBX

CMPM

Instruction

Dn, Om

-(An), -(Am)

Dn, Dm

-(An), -(Am)

Dn, Dm

-(An), -(Am)

Dn, Dm

-(An), -(Am)

(An)+, (Am)+

Head

2

2

2

2

0

2

0

2

1

Tail

0

2

0

2

0

2

0

2

0

Cycles

4(01110)

12(2/1/1 )

4(01110)

12(2/111 )

2(011/0)

10(2/111 )

2(01110)

10(2/111 )

8(2/110)

5.8.3.8 SINGLE OPERAND INSTRUCTIONS. The single operand instruction table indicates the number of clock periods needed for the processor to perform the specified operation using the specified addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/pl w) are included in the total clock cycle number. All timing data assumes twoclock reads and writes.

5-144


CLR

CLR

NEG

NEG

NEGX

NEGX

NOT

NOT

EXT

NBCO

Instruction

On

(CEA)

On

(FEA)

On

(FEA)

On

(FEA)

On

On

Head

0

0

0

0

0

0

0

0

0

Tail

0

2

0

3

0

3

0

3

0

Cycles

2(0/1/0)

4(0/1/y)

2(01110)

5(0/1/y)

2(01110)

5(0/1/y)

2(0/1/0)

5(0I1ly)

2(01110)

2 0

4(0/1/0)

NBCO

Scc

Scc

(FEA)

On

(CEA)

0

2

2

0

6(01111 )

4(01110)

2 2 6(01111 )

TAS

TAS

On

(CEA)

4

1

0

0

6(0/1/0)

10(0/1/1)

TST (FEA)

0 0

2(01110)

y

=


5.8.3.9 SHIFT/ROTATE INSTRUCTIONS. The shift/rotate instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate effective address times. The number of bits shifted does not affect the execution time, unless noted. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

MOTOROLA


Clocks

6

8

10

12

14

16

18

20

22

LSd

LSd

LSd

ASd

ASd

ASd

ROd

ROd

ROd

ROXd

Instruction

Dn, Dm

#, Dm

(FEA)

Dn, Dm

#,

Dm

(FEA)

Dn, Dm

#,

Dm

(FEA)

Dn, Dm

Head

-2

4

0

-2

4

0

-2

4

0

-2

Tail

0

0

2

0

0

2

0

0

2

0

Cycles

(0/1/0)

6(011/0)

6(0/1/1 )

(011/0)

6(0/1/0)

6(0/1/1)

(011/0)

6(0/1/0)

6(0/1/1 )

(0/1/0)

ROXd

ROXd

#, Dm

(FEA)

-2

0

0

2

(0/1/0)

6(0/1/1 ) d

=

Direction (left or right).

NOTES:

1. Execution time is calculated by this formula: max(3

+

(n/4)

+ mod (n,

4)

+

mod(((n/4 )

+ mod(n, 4)

+

1,2) ,6) or by the following table.

2. Execution time is calculated by this formula (count

~

63): max(3

+ n

+ mod(n

+

1, 2), 6).

3. Execution time is calculated by this formula (count

~

8): max(2

+ n

+ mod(n, 2), 6).

Notes

-

1

-

-

1

-

-

1

-

2

-

3

39

47

55

63

0

7

15

23

31

1

10

18

26

34

42

50

58

35

43

51

59

2

11

19

27

3

13

21

29

37

45

53

61

30

38

46

54

62

Shift Counts

4 5

14

22

16

24

32

40

48

56

41

49

57

6

17

25

33

44

52

60

8

20

28

36

9 12

5.8.3.10 BIT MANIPULATION INSTRUCTIONS. The bit manipulation instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/pl w) are included in the total clock cycle number. All timing data assumes twoclock reads and writes.

5-146


BCLR

BSET

BSET

BSET

BSET

BTST

BTST

BTST

BCHG

BCHG

BCHG

BCHG

BCLR

BCLR

BCLR

Instruction

#,On

On, Om

#, (FEA)

On, (FEA)

#,On

On, Om

#, (FEA)

On, (FEA)

#,On

On, Om

#, (FEA)

On, (FEA)

#,On

On, Om

#, (FEA)

Head

2

4

1

2

2

4

1

2

2

4

1

2

2

2

1

Tail

0

0

0

0

2

2

0

2

2

0

0

0

2

2

0

Cycles

6(0/2/0)*

6(0/1/0)

8(0/2/1

)*

8(0/1/1)

6(0/2/0)*

6(01110)

8(0/2/1)*

8(0/1/1)

6(0/2/0)*

6(01110)

8(0/2/1

)*

8(0/1/1 )

4(0/2/0)*

4(0/1/0)

4(0/2/0)*

BTST On, (FEA)

2

0

4(0/1/0)

*

=An # fetch effective address time must be added for this instruction (e.g.,

(FEA)

+

(FEA)

+

(OPER)).

5.8.3.11 CONDITIONAL BRANCH INSTRUCTIONS. The conditional branch instruction table indicates the number of clock periods needed for the processor to perform the specified branch on the given branch size, with complete execution times given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

Bcc

Bcc.B

Bcc.W

Bce.L

OBee

OBee

OBcc

OBee

OBee

Instruction

(taken)

(not taken)

(not taken)

(not taken)

(T, not taken)

(F, -1, not taken)

(F, not -1, taken)

(T, not taken)

(F, -1, not taken)

DBee (F, not -1, taken)

*

=

In loop mode.

2

6

4

6

6

Head

2

2

0

0

1

0

1

0

-2

Tail

-2

0

0

0

0

0

Cycles

8(012/0)

4(0/1/0)

4(0/2/0)

6(0/310)

4(012/0)

6(0/2/0)

10(012/0)

6(011/0)*

8(0/1/0)*

10(0/010)*

MOTOROLA


5.8.3.12 CONTROL INSTRUCTIONS. The control instruction table indicates the number of clock periods needed for the processor to perform the specified operation on the given addressing mode. Footnotes indicate when to account for the appropriate effective address times. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

ANDI

EORI

ORI

ANDI

EORI

ORI

BSR.B

BSR.W

Instruction

#,SR

#,SR

#,SR

#,CCR

#,CCR

#,CCR

BSR.L

CHK

(FEA), Dn (no ex)

CHK (FEA), Dn (ex)

CHK2 (Save)(FEA), Dn (no ex)

CHK2 (Op) (FEA), Dn (ex)

CHK2 (Save)(FEA), Dn (ex)

CHK2 (Op) (FEA), Dn (ex)

Head

0

0

0

2

2

2

0

0

0

-2

-2

Tail

-2

-2

-2

-2

0

-2

Cycles

12(0/2/0)

12(0/2/0)

12(0/2/0)

6(0/210)

6(0/2/0)

6(0/2/0)

13(012/2)

JMP

JSR

LEA

L1NK.W

L1NK.L

NOP

PEA

RTD

RTR

(CEA)

(CEA)

(CEA), An

An,#

An, #

(CEA)

#

0

3

0

2

1

2

1

2

3

3

1

2

2

0

0

0

1

1

1

0

1

-2

-2

-2

0

0

0

0

0

-2

-2

-2

13(0/2/2)

13(0/2/2)

8(0/110)

42(2/2/6)

3(0/1/0)

18(y/010)

3(0/1/0)

52(y

+

2/1/6)

6(0/2/0)

13(012/2)

2(0/110)

10(012/2)

10(0/3/2)

2(0/110)

8{O/1/2)

12(2/2/0)

14(3/2/0)

RTS 1

12(2/2/0)

UNLK An 1 0

9(21110)

y

=


NOTE: The CHK2 instruction involves a save step which other instructions do not have. To calculate the total instruction time, calculate the save, the effective address, and the operation execution times, and combine in the order listed, using the equations given in 5.8.1.6 INSTRUCTION

EXECUTION TIME CALCULATION.

5-148


5.8.3.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The exception-related instructions and operations table indicates the number of clock periods needed for the processor to perform the specified exception-related actions. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

Instruction

BKPT (Acknowledged)

BKPT (Bus Error)

Breakpoint (Acknowledged)

Breakpoint (Bus Error)

Interrupt

RESET

STOP

LPSTOP

Divide-by-Zero

Trace

TRAP

#

ILLEGAL

A-line

F-line (First Word Illegal)

Head

0

0

0

0

0

0

2

3

0

0

0

0

4

0

1

Tail

0

-2

0

-2

-2

0

0

-2

-2

-2

-2

-2

-2

-2

-2

Cycles

14(1/010)

35(3/2/4)

10(1/010)

42(3/2/6)

30(3/2/4)*

518(011/0)

12(011/0)

25(0/3/1 )

36(2/2/6)

36(2/2/6)

29(2/2/4)

25(2/2/4)

25(2/2/4)

25(2/2/4)

25(2/3/4)

F-line (Second Word Illegal) ea=Rn

F-line (Second Word Illegal) ea

=1=

Rn (Save)

F-line (Second Word Illegal) ea=l=Rn (Op)

Privileged

1

4

1

-2

3(0/110)

29(212/4)

0

-2

25(2/2/4)

TRAPcc (trap)

TRAPcc (no trap)

TRAPcc.W (trap)

2

2

2

-2

0

-2

38(2/2/6)

4(0/1/0)

38(2/2/6)

TRAPcc.W (no trap)

TRAPcc.L (trap)

0

0

0

-2

4(0/2/0)

38(2/2/6)

TRAPcc.L (no trap)

TRAPV (trap)

0

2

0

-2

6(0/3/0)

38(212/6)

TRAPV (no trap)

2

0

4(0/110)

*

= Minimum interrupt acknowledge cycle time is assumed to be three clocks.

NOTE: The F-line (second word illegal) operation involves a save step which other operations do not have. To calculate, total the operation time, the save, the effective address, and the operation execution times, and combine in the order listed, using the equations given in 5.8.1.6 IN-

STRUCTION EXECUTION TIME CALCULATION.

MOTOROLA


5-149

5.8.3.14 SAVE AND RESTORE OPERATIONS. The save and restore operations table indicates the number of clock periods needed for the processor to perform the specified state save or return from exception. Complete execution times and stack length are given. No additional tables are needed to calculate total effective execution time for these instructions. The total number of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the total clock cycle number. All timing data assumes two-clock reads and writes.

Instruction

BERR on Instruction

BERR on Exception

Head

0

0

Tail

-2

-2

-2

Cycles

<58(2/2/12)

48(212112)

RTE (Four-Word Frame)

RTE (Six-Word Frame)

RTE (BERR on Instruction)

1

1

1

-2

-2

-2

24(4/2/0)

26(4/2/0)

50(12/2/z)

RTE (BERR on Four-Word Frame)

1

66(10/2/4)

RTE (BERR on Six-Word Frame) 1

-2

70(12/2/6)

< =

Maximum time is indicated; certain data or mode combinations will execute faster. z

=

If a bus error occurred during a write cycle, the cycle is rerun by the RTE.

5-150


MOTOROLA

SECTION 6

DMA CONTROLLER MODULE

The direct memory access (DMA) controller module provides low-latency transfer capability to an external peripheral or for memory-to-memory data transfer.

The DMA module, shown in Figure 6-1, provides two channels that allow byte, word, or long-word operand transfers. These single- or dual-address transfers can be to devices that are either on-chip or off-chip. The DMA contains the following features: o Two, Independent, Fully Programmable DMA Channels o Single Address Transfers with 32-Bit Address and 32-Bit Data Capability

CD

Dual-Address Transfers with 32-Bit Address and 16-Bit Data Capability o Two 32-Bit Transfer Counters

CD

Four 32-Bit Address Pointers That Can Increment or Remain Constant

CD

Operand Packing and Unpacking for Dual-Address Transfers o Supports all Bus-Termination Modes

• Provides Two-Clock-Cycle Internal Module Access o Provides Full DMA Handshake for Cycle Steal and Burst Transfers

DMA

HANDSHAKE

SIGNALS

MOTOROLA

Figure 6-1. DMA Block Diagram


DMA

HANDSHAKE

SIGNALS

6-1

6.1 DMA MODULE SIGNALS

The following signals are used by the DMA module to provide handshake control for either a source or destination external device.

6.1.1 DMA Request (DREQ2, DREQ1)

These inputs from a peripheral start the DMA process. The assertion level can be either active-low or falling edge.

6.1.2 DMA Acknowledge (DACK2, DACK1)

These outputs to a peripheral are asserted during accesses, after a DMA is in progress.

6.1.3 DMA Done (DONE2, DONE1)

These active-low bidirectional signals indicate that the last transfer is being performed.

6.1.4 Reset (RESET)

Assertion of RESET aborts any bus cycle in progress and sets all control bits back to their reset state, preventing the DMA channel from recognizing any further DMA requests. In addition, any pending requests are lost.

6.2 OPERATION

The following paragraphs describe the programmable channel functions available with the DMA module, the manner in which data transfer operations are executed, and behavior during exception conditions. This description applies to both channels.

Any channel operation adheres to the following basic sequence:

1. The processor initializes the channel registers.

2. Channel Startup The STR bit is set in the channel control register, and the first operand transfer request is recognized (either internally or externally generated).

6-2


3. Transfer Data Block After a channel is started, it transfers one operand in response to each request until an entire data block is transferred.

4. Channel Termination The channel can terminate by normal completion or from an error.

6.2.1

Channel Initialization

Before starting a block transfer operation, the processor must initialize the channel registers with information describing the data block, request generation method, etc. This initialization is accomplished by moving the appropriate values into the registers using the MOVE instruction.

The source address register (SAR) is loaded with the source (read) address. If the transfer is from a peripheral device to memory, this is the location of the peripheral data register. If the transfer is from memory to a peripheral device or memory to memory, the source address is the starting address of the data block. This address may be any byte address. In the single-address write mode of operation, this register is not used.

The destination address register (DAR) should contain the destination (write) address. If the transfer is from a peripheral device to memory or memory to memory, the DAR is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, the DAR is loaded with the address of the peripheral data register. This address may be any byte address. In the single-address read mode of operation, this register is not used.

The manner in which the SAR and DAR change after each cycle depends upon the values in the source size control (SSIZE) and destination size control (DSIZE) fields in the channel control register (CCR), the starting address in the SAR and

DAR, and the source address pointer increment (SAPI) and destination address pointer increment (DAPI) bits in the CCR. If programmed to increment, the increment value is 1,2, or 4 for byte, word, or long-word operands, respectively.

If the address register is programmed to remain unchanged (no count), the register is not changed after the operand transfer. The SAR and DAR increment if a bus error terminates the transfer. Therefore, either the SAR or the DAR contains the the next address after the one that caused the bus error.

The byte transfer counter (BTC) must be loaded with the number of byte transfers that are to occur. This register is decremented by 1, 2, or 4 at the end of each transfer. The function code register (FCR) must be loaded with the source

MOTOROLA


and destination function codes. Although these function codes may not be used in the address decode for the memory or peripheral, they are provided if needed.

6.2.2 Channel Startup

After initialization, the channel is started by writing a one to the start (STR) bit in the CCR. If the channel is programmed for internal request, the channel immediately requests the bus and starts transferring data. If the channel is programmed for external request, an external request (DREOx) signal must be asserted before the channel requests the bus.

6.2.2.1 EXTERNAL REQUEST. To control the transfer of operands to or from memory in an orderly manner, a peripheral device uses the DREOx pins on the DMA module to request service. If a memory-to-memory transfer is desired 'or a peripheral with no explicit request signal is used, the DMA module can be programmed to internally generate requests. The request generation method used for the channel is programmed in the request generation field (REO) in the CCR. If external requests are chosen, the generation of the request from the source or destination is specified by the external control option (ECO) bit of the CCR. The external requests can be for either dual- or single-address transfers. Care must be taken in setting the size of the source and destination ports, due to the control that the size settings have over the SAR, DAR, and

BTC. The BTC is decremented by the larger size (SSIZE or DSIZE) contained in the CCR, and multiple cycles are run to complete the entire transfer. Therefore, multiple cycles can result from a single external request.

6.2.2.2 EXTERNAL REQUEST WITH OTHER MODULES. The DMA controller can be externally connected to the serial module and used in conjunction with the serial module to send or receive data. The DMA takes the place of a separate service routine for accessing or storing data that is sent or received by the serial module. Using the DMA also lowers the CPU32 overhead required to handle the data transferred by the serial module. Figure 6-2 shows the external connections required for using the DMA with the serial module.

For serial receive, the DMA reads data from the serial receive data register

(when the serial module has filled the buffer on input) and writes data to memory. For serial transmit, the DMA reads data from memory and writes data to the serial transmit data register. Only dual-address mode can be used with the serial module.


MOTOROLA

DMAMODULE

DREa1

- -

DREa2

SERIAL MODULE

TxRDYA

- -

RxRDYA

Figure 6-2. DMA External Connections to Serial Module

The timer modules can be used with the DMA in a similar manner. By connecting TOUT to DREQx, the timer can request a DMA transfer.

6.2.2.3 EXTERNAL BURST. For external devices that require very high data transfer rates, the burst request mode allows the DMA channel to use all bus bandwidth under control of the external device. In burst mode, the DREQx input to the DMA is level sensitive and is sampled during the current bus cycle to determine when a valid request is asserted by the device for the next bus cycle.

The device requests service by asserting DREQx and leaving it asserted. In response, the DMA arbitrates for the system bus and performs an operand transfer. During each access to the device, the DMA asserts DMA acknowledge

(DACKx) to indicate to the device that a request is being serviced. If DREQx is asserted when the DMA completes the requested cycle a setup time before

DACKx, then a valid request for another operand transfer is recognized, and the DMA services that request immediately. If DREQx is negated before DACKx is negated, a new request is not recognized, and the DMA channel releases ownership of the bus.

6.2.2.4 EXTERNAL CYCLE STEAL. For external devices that generate a pulsed signal for each operand to be transferred, the cycle steal request mode uses

DREQx as a falling-edge-sensitive input. The DMA channel responds to cycle steal requests the same as all other requests; however, if subsequent DREQx pulses are generated before DACKx is asserted in response to each request, they are ignored. If DREQx is asserted after the DMA channel asserts DACKx for the previous request but before DACKx is negated, then the new request is serviced before bus ownership is released. If a new request is not generated by the time DACKx is negated, the bus is released.

MOTOROLA


6.2.3 DMA Transfer Operation

The two-channel DMA module supports dual- and single-address transfers. The dual-address operand transfer consists of a source operand read and a destination operand write. Each single-address operand transfer consists of one external bus cycle, which allows either a read or a write cycle to occur.

6.2.3.1 DUAL-ADDRESS MODE. The two DMA channels can each be programmed to operate in a dual-address transfer mode. In this mode, the operand is read from the source address specified in the SAR and placed in the data holding register (DHR). The operand read may take up to four bus cycles to complete because of differences in operand sizes of the source and destination. The operand is then written to the address specified in the DAR. This transfer may also be up to four bus cycles long. In this manner, various combinations of peripheral, memory, and operand sizes may be used.

The dual-address transfers can be started by either the internal request mode or by an external device using the DREQx input signal. When the external device uses DREQx, the channel can be programmed to operate in either the cycle steal or burst transfer modes. See 6.2.2.3 EXTERNAL BURST and 6.2.2.4. EX-

TERNAL CYCLE STEAL for information about these modes.

6.2.3.1.1 Dual-Address Source Read. During this type of DMA cycle, the SAR drives the address bus, the FCR drives the source function codes, and the CCR drives the size control. Data is read from the memory or peripheral and placed in the

DHR when the bus cycle is terminated. When the complete operand has been read, the SAR is incremented by 1, 2, or 4, depending on the address and size information specified by the SAPI and SSIZE bits of the CCR. See 6.4.6 Source

Address Registers for more information.

6.2.3.1.2 Dual-Address Destination Write. During this type of DMA cycle, the data in the DHR is written to the device or memory selected by the address in the

DAR, the destination function codes in the FCR, and the size in the CCR. The same options exist for operand size and alignment as in the dual-address source read. When the complete operand is written, the DAR is incremented by 1, 2, or 4, according to the DAPI and DSIZE bits of the CCR, and the BTC is decremented by the number of bytes transferred. If the BTC is equal to zero and there were no errors, the DONE bit in the CSR and the DONEx signal for the

DMA handshake are asserted. See 6.4.7 Destination Address Registers (DARs) and 6.4.8 Byte Transfer Counters (BTCs) for more information.


6.2.3.2 SINGLE-ADDRESS MODE. Each DMA channel can be independently programmed to provide single-address transfers. Only external request can be used to start a transfer when the single-address mode is selected. The ECO bit in the CCR controls whether a source read or a destination write cycle occurs on the data bus. If the ECO bit is set, the external handshake signals are used with the source operand and a single address source read occurs. If the ECO bit is cleared, the external handshake signals are used with the destination operand, and a single address destination write takes place.

If external 32-bit devices and a 32-bit bus are used with the MC6834D, the DMA can control 32-bit transfers between devices that use the 32-bit bus, in singleaddress mode only. If both byte and word devices are used on an external bus, then an external multiplexer must be used to correctly transfer data. The SIZx and

AD

signals can be used to control this external multiplexer.

6.2.3.2.1 Single-Address Source Read. During the single-address source read cycle, the device or memory selected by the address specified in the SAR, the source function codes in the FCR, and the size in the CCR provide the data and control signals on the data bus. This bus cycle operates like a normal read bus cycle.

The destination device is controlled by the DMA handshake signals (DREQx,

DACKx, and DONEx). The assertion of DACKx provides the write control to the destination device. For more details about the DMA handshake signals, see 6.1

DMA MODULE SIGNALS.

6.2.3.2.2 Single-Address Destination Write. During the single-address destination write cycle, the source device is controlled by the DMA handshake signals

(DREQx, DACKx, and DONE). When the source device requests service from the DMA channel, the assertion of DACKx by the DMA channel allows the source device to drive data onto the data bus. The data is written to the device or to memory selected by the address specified in the DAR, the destination function codes in the FCR, and the size in the CCR. The data bus is placed in a highimpedance state for this write cycle. For more details about the DMA handshake signals, see 6.1 DMA MODULE SIGNALS.

6.2.4 Interrupt Operation

The processor can determine the status of a DMA operation by reading the channel status register (CSR), or the DMA channel can interrupt the processor to inform it of certain events.

MOTOROLA


Interrupts can be generated by error termination of a bus cycle or by normal channel completion. Specifically, if the interrupt enable for error bit INTE in the CCR is set and BES, BED, or CONF is set, the IRQ bit is set. In this case, clearing the INTE, BES, BED, or CONF bits causes the IRQ bit to be cleared. If the INTN bit in the CCR is set and the DONE bit is set, the IRQ bit is set. In this case, clearing the INTN or the DONE bit causes the IRQ bit to be cleared. If the

INTB bit in the CCR is set and the BRKP bit in the CSR is set, the IRQ bit is set.

Clearing INTB or BRKP clears IRQ.

6.2.5 Bus Arbitration

The DMA controller uses the M68000 bus arbitration protocol to request bus mastership for DMA transfers. Each channel arbitrates for the bus independently, and priority is fixed by hardware in the bus interface unit.

The DMA module transfers are unique in one respect; FC3 can be asserted during the source operand bus cycle and remain asserted until the end of the destination operand bus cycle. The source DMA bus cycle has timing identical to a read bus cycle. The destination DMA bus cycle has timing identical to a write bus cycle.

To guarantee that the DMA does not use all available system bus bandwidth during a transfer, internal requests can specify the amount of bus bandwidth allocated to the DMA. This allocation is done by programming the REQ bits in the CCR to internal programmable rate and the BB bits in the CCR to the percentage of bandwidth desired. When the STR bit in the CCR is set, the DMA channel arbitrates for the bus and begins to transfer data when it becomes bus master. If no exception occurs, the DMA uses the percentage of bus bandwidth, which is programmed into the control register.

6.2.6 Fast-Termination Option

The fast-termination option, using the system integration module (SIM) chipselect logic, can be employed to give a fast bus access of two clock cycles rather than the standard three-cycle access time. The fast-termination option is described in SECTION 4 SYSTEM INTEGRATION MODULE and in SECTION

3 BUS OPERATION.

If the fast-termination option is used with external request burst mode, an extra

DMA cycle results on every burst transfer. Normally, DREQx is negated when

DACKx is returned. In the burst mode with fast termination selected, a new cycle starts even if DREQx is negated simultaneously with DACKx assertion.


MOTOROLA

6.3 PROGRAMMING SEQUENCE

To begin a data transfer operation, move the appropriate values into the registers using the MOVE instruction and the following sequence: a. Write a zero to the STR bit in CCR. b. Load the SAR, DAR, and BTC with the source and destination addresses and the byte count. c. Write the CCR with parameters describing the desired operation of the channel: operand size, count mode, request method, etc. If the STR bit is set at this time, the channel is started. d. Write to the peripheral device control registers as necessary to enable the device to generate requests and begin operation.

6.3.1 Channel Startup

Once the channel has been initialized, it is started by writing a one to the STR bit in the CCR., If the channel is programmed for internal request, this causes the channel to request the bus and start transferring data. If the channel is programmed for external request, DREQx must be asserted before the channel requests the bus. The DREQx input is ignored until the channel is started since the channel does not recognize transfer requests until it is active.

If any fields in the CCR are modified while the channel is active, that change is effective immediately. To avoid any problems with changing the setup for the DMA channel, a zero should be written to the STR bit in the CCR to halt the DMA channel at the end of the current bus cycle.

6.3.2 Data Transfers

Each operand transfer requires from one to five bus cycles to complete. Once a bus request is recognized and the operand transfer begins, both the source read and/or destination write occur before a new bus request may be honored, even if the new bus request is of higher priority.

6.3.2.1 DUAL-ADDRESS TRANSFERS. Each operand transfer in the dual-address mode requires from two to five bus cycles in response to each operand transfer request. If the source and destination operands are the same size, two cycles


will transfer the complete operand. If the source and destination operands are different sizes, the number of cycles will vary. If the source is a long-word and the destination is a byte, there would be one bus cycle for the read and four bus cycles for the write. Once the DMA channel has started a dual-address operand transfer, it must complete that transfer before releasing ownership of the bus or servicing a request for another channel of equal or higher priority, unless one of the bus cycles is terminated with a bus error during the transfer.

6.3.2.2 SINGLE-ADDRESS TRANSFERS. When a request is recognized internally, the DMA channel arbitrates for the bus and executes one bus cycle in response to each request. Since the operand size must be equal to the device port size for single-address transfers and only one bus cycle is run for each request, the number of normally terminated bus cycles executed during a transfer operation is always equal to the value programmed into the corresponding size field of the CCR. The sequencing of the address bus follows the programming of the

CCR and address register (SAR or DAR) for the channel.

6.3.2.3

CHANNEL TERMINATION.

The channel operation can be terminated for several reasons: the BTC is decremented to zero, a peripheral device asserts

DONEx during an operand transfer, the STR bit is cleared in the CCR, a bus cycle is terminated with a bus error, or a reset occurs.

6.4 REGISTER DESCRIPTION

Figure 6-3 is a programmer's model (register map) of all registers in the DMA.

Each channel has an independent set of registers that are located at the base address added to the address specified in the columns for channel 1 and channel 2. The base address is specified in SECTION 4 SYSTEM INTEGRATION

MODULE. The column titled FC (function code) indicates whether a register is restricted to supervisor access (S) or is programmable to exist in either supervisor or user space (S/U).

Unimplemented memory locations return logic zero when accessed. All registers support both byte and word transfers.

6-10


ADDRESS

CHI CH2

780 7Ao

782 7A2

784 7A4

786 7A6

FC

S

S/U

788 7A8

78A 7AA

S/U

S/U

78C 7AC

78E 7AE

790 7Bo

792

7B2

794

7B4

796

7B6

798 7B8

S/U

S/U

S/U

S/U

S/U

S/U

S/U

79A 7BA

79C 7BC

79E 7BE

S/U

S/U

S/U

15

MODULE CONFIGURATION REGISTER (MCRI

RESERVED

INTERRUPT REGISTER

RESERVED

CHANNEL CONTROL REGISTER

CHANNEL STATUS REGISTER

I

FUNCTION CODE REGISTER

SOURCE ADDRESS REGISTER MSBs

SOURCE ADDRESS REGISTER LSBs

DESTINATION ADDRESS REGISTER MSBs

DESTINATION ADDRESS REGISTER LSBs

BYTE TRANSFER COUNTER MSBs

BYTE TRANSFER COUNTER LSBs

RESERVED

RESERVED

RESERVED

RESERVED

Figure 6-3. Programmer's Model

6.4.1 Module Configuration Registers (MCRs)

The two 16-bit MCRs are always readable and writable in the supervisor mode, although writing is discouraged unless the module is disabled.

MCR1, MCR2

15 14 13 12 11 10

I

STP

I

FRZI

I

FRZo

I

SE o

I

ISM

I sUPV

I

MAID

RESET:

$780, $7AO

IARB

Supervisor/User

STP Stop Bit

1 = The system clock stops within the module except for the intermodule bus (1MB) bus interface unit (BIU). The BIU continues to operate to allow the CPU32 access to the module's MCR. All other register accesses cause a bus error without changing the data. The system clock stops on the low phase of the clock and remains stopped until STP is cleared by the CPU32 or until reset.

0= The system clock operates normally within the module.

MOTOROLA


6-12

NOTE

The DMA module uses only one set of FRZ bit for both channels. A read or write to either MCR accesses the same control bit.

FRZ1 ,FRZO Freeze

These bits determine the action to be taken when the FREEZE signal is asserted. The DMA module negates BR and keeps it negated until FREEZE is negated or reset. Table 6-1 shows the definition for these two bits.

Table 6-1. FRZ Encoding

FRZ1 FRZO

0

Action

0 Ignore FREEZE

0

1

1 Reserved

0 Freeze on Boundary

1 1 Reserved

NOTE: The boundary is defined as any bus cycle by the DMA module.

NOTE

The DMA module uses only one set of FRZ bits for both channels. A read or write to either MCR accesses the same control bit.

SE Single-Address Enable

1

=

Selects single-address mode of operation for the channel; external data bus is driven during DMA transfer.

0= External data bus remains in a high-impedance state during the DMA transfer.

ISM2-ISMO Interrupt Service Mask

These bits contain the interrupt service mask. When the interrupt service level on the 1MB is greater than the interrupt service mask, the DMA vacates the bus and negates BR until the interrupt service level is less than or equal to the interrupt service mask.

SUPV Supervisor/User

This bit affects all registers that are defined as supervisor/user and determines whether the registers reside in supervisor data space or can be accessed from both supervisor and user programs.

1

=

Supervisor-only access; FC2 must be logic one during access.

0= Unrestricted access; FC2 is ignored during access.


MAID Master Arbitration ID

These bits establish bus arbitration priority level among modules that have the capability of becoming bus master. In the MC68340, only the SIM and the DMA can be bus masters. Zero is the lowest priority and seven is the highest priority.

IARB Interrupt Arbitration ID

This field is used to arbitrate for the 1MB in the event two or more modules simultaneously generate an interrupt of the same priority level. This field is set to $0 after reset, which prevents this module from arbitrating during the interrupt acknowledge cycle. If no arbitration occurs during the interrupt acknowledge cycle, the spurious interrupt vector is generated and the interrupt is discarded. Initialization software must set this field to a nonzero value.

NOTE

The DMA module uses only one set of IARB bits for both channels. A read or write to either MCR accesses the same control bits.

6.4.2 Interrupt Registers (lNTRs)

The INTRs are accessible only in supervisor space.

INTR1, INTR2

15 14 13 12 11 10

I

0

I

0

I

0 0

I

0

I

INTL

RESET:

$784, $7A4

INTV o

0 0 0'

Supervisor Only

INTL Interrupt Level

The interrupt level field contains the priority level of the interrupt for its associated channel.

INTV Interrupt Vector

This field is used by the DMA channel to arbitrate for the bus during interrupt acknowledge bus cycles. During an interrupt acknowledge cycle, the module with the highest priority pending interrupt places the content of this field on the data bus.

MOTOROLA


6-13

6.4.3 Channel Control Registers (CCRs)

The CCRs are accessible in either supervisor or user space.

CCR1, CCR2

15 14 13 12 11 10

IINTB IINTN IINTE I ECO I SAPI I OAPI I SSIZE

OSIZE

REG

RESET:

U U u u u u u u u u u u

U

=

Unaffected by reset

BB

$788, $7A8

S/O

I STR I u u u

Supervisor/User

INTB Interrupt Breakpoint

Setting the breakpoint bit sets the BRKP bit in the CSR. The logic AND of

INTB and BRKP generates an interrupt request.

1

=

Enables IROx when breakpoint is recognized and this channel is bus master

0= Not enabled

INTN Interrupt Normal

1

=

Enables IROx when this channel finishes a transfer without an error condition (DONE)

0= Not enabled

INTE Interrupt Error

1

=

Enables IROx when this channel encounters an error on source read

(BES), destination write (BED), or configuration for channel setup (CONF)

0= Not enabled

ECO External Control Option

Dual-Address Mode this bit defines which device generates requests.

1

=

If request generation is programmed to be external (REO

=

1 XL the source device generates the request, and the control signals (DREOx,

DACKx, and DONEx) are part of the source (read) portion of the transfer.

0= If REO is programmed to be external, the destination device generates the request, and the control signals (DREOx, DACKx, and DONEx) are part of the destination (write) portion of the transfer.

Single-Address Mode this bit defines the direction of transfer.

1

=

If REO is programmed to be external, the requesting device receives the data (read from memory), and the control signals (DREOx, DACKx, and DONEx) are used by the requesting device to write data during the source (read) portion of the transfer.

6-14


MOTOROLA

0= If REO is programmed to be external, the requesting device provides the data (write to memory), and the control signals (DREQx, DACKx, and DONEx) are used by the requesting device to provide data during the destination (write) portion of the transfer.

SAPI Source Address Pointer Increment

1

=

The SAR is incremented by 1, 2, or 4 after each transfer, according to the source size.

0= The SAR is not incremented during operand transfer. The address that is written into the SAR under program control is used for the complete data transfer.

DAPI Destination Address Pointer Increment

1

=

The DAR is incremented by 1, 2, or 4 after each transfer, according to the source size.

0= The DAR is not incremented during operand transfer. The address that is written into the DAR under program control is used for the complete data transfer.

SSIZE Source Size Control

These bits control the size of the source read bus cycle that the DMA channel is running. Table 6-2 defines these bits.

Table 6-2. SSIZE Encoding

Bit 9 Bit 8

0 0

Definition

Long Word

0

1

1

1

0

1

Byte

Word

Not Used

DSIZE Destination Size Control

These bits control the size of the destination write bus cycle that the DMA channel is running. Table 6-3 defines these bits.

Table 6-3. DSIZE Encoding

Bit 7 Bit 6

0

0

Definition

0

Long Word

1 Byte

1

1

0

Word

1 Not Used

MOTOROLA


6-16

REO Request Generation

These bits control the mode of operation the DMA channel uses to make an operand transfer request. Table 6-4 defines these bits.

Table 6-4. REQ Encoding

Bit 5 Bit 4

0

0

1

1

Definition

0 Internal Request at Programmable Rate

1 Reserved

0 External Request Burst Transfer Mode

1 External Request Cycle Steal

BB Bus Bandwidth

These bits control the percentage of the 1MB that the DMA channel can use during internal requests only. Table 6-5 defines these bits.

Table 6-5. BB Encoding

Bit 5 Bit 4

0 0

0

1

1

1

0

1

Definition

25%

50%

75%

100%

SID Single-/Dual-Address Transfer

1

=

The DMA channel runs single-address transfers from peripherals or from memory to peripherals or memory. The destination holding register is not used for these transfers because the data is transferred directly into the destination location.

0= The DMA channel runs standard dual-address transfers.

STR Start

Internal Request

1

=

Start DMA transfer

0= No action

External Request

1 =

This bit must be set for the DMA bus controller to recognize the first request for DMA by the external device using the DREOx input. This bit is set by writing a logic zero to bit 0 of the CCR.

0= No action

This bit is cleared by reset, writing a logic zero, the DONE status bit being set, or one of the error status bits (BES, BED, or CONF) being set.


MOTOROLA

6.4.4

Channel Status Registers (CSRs)

The CSRs are accessible in either supervisor or user space.

CSR1, CSR2 $78A, $7AA

7 6 5 4 3 2

I

IRQ

I

DONE

I

BES

I

BED

I

CONF

I

BRKP

I

0

I

0

RESET:

Supervisor/User

IRQ Interrupt Request

1

=

An interrupt condition has occurred.

D

=

An interrupt condition has not occurred.

This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared when they are all cleared. IRQ is positioned to allow conditional testing as a signed binary integer. The state of this bit is not affected by the interrupt enable bits in the CCRs. The STR bit in the CCR cannot be set when this bit is set; all error status bits must be cleared before the STR bit can be set.

DONE DMA Done

1

=

The DMA channel has terminated normally.

D

=

The DMA channel has not terminated normally.

This bit is cleared by writing a logic one or by reset. Writing a zero has no effect.

BES Bus Error on Source

1

=

The DMA channel has terminated with a bus error during the read bus cycle.

D

=

The DMA channel has not terminated with a bus error during the read bus cycle.


BED Bus Error on Destination

1

=

The DMA channel has terminated with a bus error during the write bus cycle.

D

=

The DMA channel has not terminated with a bus error during the write bus cycle.


MOTOROLA


CONF Configuration Error

A configuration error results when either the SAR or the DAR contains an address that does not match the port size specified in the CCR and the BTC register does not match the larger port size or is zero.

1

=

The STR bit is set in the CCR, and a configuration error is present.

0= If STR is set, no configuration error exists.


BRKP - Breakpoint

1

=

The breakpoint signal was set during a DMA transfer.

0= The breakpoint signal was not set during a DMA transfer.


6.4.5 Function Code Registers (FCRs)

The FCRs are accessible in either supervisor or user space.

FCR1,FCR2 $78B, $7AB

SFC DFC

RESET:

U U u u u u u u

U

=

Unaffected by reset Supervisor/User

SFC Source Function Code

The source function code bits are defined in Table 6-6.

DFC Destination Function Code

The destination function code bits are defined in Table 6-6.

NOTE

FC3 can be set for DMA transfers to distinguish the source or destination space from other data or program space, but is not required to be set. Since the CPU32 currently has only 3-bit SFC and DFC capability, it cannot emulate FC3

=

1 at this time.



Function Code Bits

3 2 1 0

Address Spaces

0

0 0 0

Reserved (Motorola)

0 0 0 1 User Data Space

0

0

1

0 User Program Space

0 0

1 1 Reserved (User)

0 1 0 0 Reserved (Motorola)

0

1

0

1


0

1

1

0 Supervisor Program Space

0 1 1 1 CPU Space

1 x x x

DMA Space

6.4.6 Source Address Registers (SARs)

The SARs are accessible in either supervisor or user space.

SAR1, SAR2 $78C, $7AC

31 29 27 23 21 19

30 28 26 25 24 22 20 18 17 16

I

A31

I

A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19

I

A18

I

A17

I

A16

RESET:

U U U U U U U U U U U U U U U

15 14 13 12 11

A15

RESET:

U

A14 A13 A12 All

U U U U

U = Unaffected by reset

10

A10

U

A9

U

AS

U

A7

U

A6

U

A5

U

A4

U

A3 A2

I

Al

AO

U U U

Supervisor/User

This 32-bit register contains the address of the source operand used by the

DMA to access memory or peripheral controller registers. During the DMA read cycle, this register drives the address on the address bus. This register can be programmed to increment or remain constant after each operand transfer.

The register is incremented using unsigned arithmetic and will rollover if overflow occurs. For example, if the register contains $FFFFFFFF and is incremented by 1, it will rollover to $00000000. This register is incremented by 1,

2, or 4, depending on the size of the operand and the memory starting address.

If the operand size is byte, then the register is always incremented by 1. If the operand size is word and the starting address is even-word aligned, then the register is incremented by 2; if the operand size is word and the address is odd-byte aligned, then the CONF bit is set in the CSR and no transfer occurs.


If the operand size is long word and the address is long-word aligned, then the register is incremented by 4; if the operand size is long word and the address is odd-word or odd-byte aligned, then the CONF bit is set, and no transfer occurs.

When read, this register always contains the next source address. If a bus error terminates the transfer, this register contains the next source address that would have been run had the error not occurred.

6.4.7 Destination Address Registers (OARs)

The DARs are accessible in either supervisor or user space.

DAR1, DAR2 $790, $780

31 30 29 28 27 26 25 24 23 22 21

20 19

18

17 16

I

A31 ! A30

A29

A28

A27

A26 A25 A24 A23 A22 A21 A20

A19 ! A18 ! A17'! A16

RESET:

U


15 14 13 12 11

A15 A14 A13 A12 All

RESET:

U

U U U U

U

=

Unaffected by reset

10

AlO

U

A9

U

A8

U

A7

U

A6

U

A5

U

A4

U

A3 A2 ! Al AO

U U U U

Supervisor/User

This 32-bit register contains the address of the destination operand used by the DMA to write to memory or peripheral controller registers. During the DMA write cycle, this register drives the address on the address bus. This register can be programmed to increment or remain constant after each operand transfer.

The register is incremented using unsigned arithmetic and will roll over if overflow occurs. For example, if a register contains $FFFFFFFF and is incremented by 1, it will rollover to $00000000. This register can be incremented by 1, 2, or 4, depending on the size of the operand and the starting address. If the operand size is byte, the register is always incremented by 1. If the operand size is word and the starting address is even-word aligned, the register is incremented by 2; if the operand size is word and the address is odd-byte aligned, the CONF bit is set in the CSR, and no transfer occurs. If the operand size is long word and the address is long-word aligned, the register is incremented by 4; if the operand size is long word and the address is odd-word or odd-byte aligned, then the CONF bit is set, and no transfer occurs.

6-20


MOTOROLA

When read, this register always contains the next destination address. If a bus error terminates the transfer, this register contains the next destination address that would have been run had the error not occurred.

6.4.8

Byte Transfer Counter Registers (BTCs)

The BTCs are accessible in either supervisor or user space.

BTC1, BTC2 $794,$7B4

31

30 29 28 27 26

25 24 23 22 21 20 19 18 17 16

I

A31

I

A30

I

A29

I

A28

I

A27 A26

I

A25

I

A24

I

A23

I

A22

I

A21

I

A20

I

A19

I

A18

I

A17

I

A16

RESET:


15 14 13 12 11 10

I

A15

I

A14

I

A13

I

A12

I

All

I

AlO

I

A9 A8 A7 A6 A5 A4 A3 A2

I

Al

AO

RESET:

U

U U U U U U U U U U U U U U

U

=

Unaffected by reset

Supervisor/User

This 32-bit register contains the number of bytes left to transfer in a given block.

This register is decremented by 1, 2, or 4 for each successful operand transfer from source to destination locations. When the BTC decrements to zero and no error has occurred, the DONE bit is set in the CSR. In the external request mode, the DONE handshake line is also asserted when the BTC is decremented to zero.

If the operand size is byte then the register is always decremented by 1. If the operand size is word and the starting count is even word, the register is decremented by 2. If the operand size is word and the count is odd byte, then the

CONF bit is set in the CSR, and no transfer occurs. If the operand size is long word and the count is long word, then the register is incremented by 4; if the operand size is long word and the count is odd word or odd byte, the CONF bit is set, and no transfer occurs. If the STR bit is set with a zero count in the

BTC, the CONF bit is set, and the STR bit is cleared.

When read, this register always contains the count for the next access. If a bus error terminates the transfer, this register contains the count for the next access that would have been run had the error not occurred.

MOTOROLA


6.4.9 Data Holding Register (DHR)

This 32-bit register serves as a buffer register for the data being transferred during dual-address DMA cycles. No address is specified since this register can not be addressed by the programmer. The DHR allows the data to be packed and unpacked by the DMA during the transfer. For example, if the source operand size is byte and the destination operand size is word, then two-byte read cycles occur, followed by a one-word write cycle (see Figure 6-4). The two bytes of data are buffered in the DHR until the word write cycle occurs. The

DHR allows for packing and unpacking of operands for the following sizes: bytes to words, bytes to long words, words to long words, words to bytes, long words to bytes, and long words to words.

SOURCEJDESTINATION

~

>

BYTEO

BYTE1

BYTE2

BYTE3

II(

>

BYTEO

DESTINATIONISOURCE

BYTEO

BYTE1

BYTE1

BYTE2 BYTE3

II(

>

BYTEO

BYTE1 BYTE2 BYTE3

Figure 6-4. Packing and Unpacking of Operands

For normal transfers aligned with the size and address, only two bus cycles are required for each transfer: a read from the source and a write to the destination.

6-22


SECTION 7

SERIAL MODULE

The MC68340 serial module is a dual universal asynchronous/synchronous receiver/transmitter that interfaces directly to the CPU32 processor via an intermodule bus (1MB). The serial module, shown in Figure 7-1, consists of the following major functional areas:

• Two Independent Serial Communication Channels (A and B)

• Baud Rate Generator Logic

• Internal Channel Control Logic

• Interrupt Control Logic

SERIAL COMMUNICATIONS

CHANNELS A AND B

BAUD RATE .

GENERATOR LOGIC

CTSA

RTSA

RxDA

TxDA

RxRDYA

TxRDYA

CTSB

RTSB

RxDB

TxDB

X1

X2

SCLI<

INTERNAL CHANNEL

CONTROL LOGIC

INTERRUPT CONTROL

LOGIC

Figure 7-1. Simplified Block Diagram


7.1

MODULE OVERVIEW

Features of the serial module are as follows:

• Two, Independent, Full-Duplex Asynchronous/Synchronous Receiver/

Transmitter Channels

• Maximum Data Transfer:

1 x -3 Mbps

16 x - 188 kbps

• Quadruple-Buffered Receiver

• Double-Buffered Transmitter

• Independently Programmable Baud Rate for Each Receiver and Transmitter

Selectable from:

19 Fixed Rates: 50 to 76.8k Baud

External 1 x Clock or 16 x Clock

• Programmable Data Format:

Five to Eight Data Bits Plus Parity

Odd, Even, No Parity, or Force Parity

One, One and One-Half, or Two Stop Bits Programmable in One-

Sixteenth Bit Increments

• Programmable Channel Modes:

Normal (Full Duplex)

Automatic Echo

Local Loopback

Remote Loopback

• Automatic Wakeup Mode for Multidrop Applications

• Seven Maskable Interrupt Conditions

• Parity, Framing, and Overrun Error Detection

• False-Start Bit Detection

• Line-Break Detection and Generation

• Detection of Breaks Originating in the Middle of a Character

• Start/End Break Interrupt/Status

• On-Chip Crystal Oscillator

• TTL Compatibility


MOTOROLA

7.1.1 Serial Communication Channels A and B

Each communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter using an operating frequency independently selected from a baud rate generator or an external clock input. The transmitter accepts parallel data from the 1MB, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial data stream on the channel transmitter serial data output (TxDx). Refer to 7.3.2.1

TRANSMITTER for additional information.

The receiver accepts serial data on the channel receiver serial data input (RxDx), converts it to parallel format, checks for a start bit, stop bit, parity (if any), or break condition, and transfers the assembled character onto the 1MB during read operations. Refer to 7.3.2.2 RECEIVER for additional information.

7.1.2 Baud Rate Generator Logic

The crystal oscillator operates directly from a 3.6864-MHz crystal connected across the X1 input and the X2 output or from an external clock of the same frequency connected to X1. The clock serves as the basic timing reference for the baud rate generator and other internal circuits.

The baud rate generator operates from the oscillator or external TTL clock input and is capable of generating 19 commonly used data communication baud rates ranging from 50 to 76.8k by producing internal clock outputs at 16 times the actual baud rate. Refer to 7.2 INTERFACE SIGNAL DESCRIPTIONS and 7.3.1

Baud Rate Generator for additional information.

The external clock input (SCLK), which bypasses the baud rate generator, is a synchronous mode of operation when used with a divide-by-1 clock and an asynchronous mode when used with divide-by-16 clock. The external clock input allows the user to use SCLK as the only clock source for the serial module if baud rates are not required.

7.1.3 Internal Channel Control Logic

The serial module receives operation commands from the host and, in turn, issues appropriate operation signals to the internal serial module control logic.

This mechanism allows the registers within the module to be accessed and various commands to be performed. Refer to 7.4 REGISTER DESCRIPTION AND

PROGRAMMING for additional information.

MOTOROLA


7-3

7.1.4 Interrupt Control Logic

Seven interrupt request (lRQ7-IRQ1) outputs are provided to notify the CPU32 that an interrupt has occurred. These interrupts are described in 7.4 REGISTER

DESCRIPTION AND PROGRAMMING. The interrupt status register (lSR) is read by the CPU32 to determine all currently active interrupt conditions. The interrupt enable register (IER) is programmable to mask any events that can cause an interrupt.

7.1.5 Comparison of Serial Module to MC6S6S1

The serial module is code compatible with the MC68681 with some modifications. The following paragraphs describe the differences.

The programming model is slightly altered. The supervisor/user block in the

MC68340 closely follows the MC68681. The supervisor-only block has the following changes:

• The interrupt vector register is moved from supervisor/user to supervisor only at a new address.

• MR2A and MR2B are moved from a hidden address location to a location at the bottom of the programming model.

• The timer/counter is eliminated as well as all associated command and status registers.

• Only certain output port pins are available.

• The XTAL_RDY bit in the ISR should be polled until it is cleared to prevent an unstable frequency from being applied to the baud rate generator. The following code is an example: if (XTAL_RDY= =0) begin write CSR end else begin wait jump loop end

7.2 INTERFACE SIGNAL DESCRIPTIONS

The following paragraphs contain a brief description of the serial module signals. Figure 7-2 shows both the external and internal signal groups.

7-4


NOTE

The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and activehigh signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.

X1

BAUD RATE

GENERATOR

LOGIC

SCLI<

CHANNEL A

FOUR-CHARACTER

~I-----'-'=_

RECEIVE BUFFER

CHANNELB

FOUR-CHARACTER

RECEIVE BUFFER

~t---=-=-

MOTOROLA

Figure 7-2. External and Internal Interface Signals


7-5

7.2.1 Crystal Input or External Clock (X1)

This input is one of two connections to a crystal or a single connection to an external clock. A crystal or an external clock signal, at 3.6864 MHz, must be supplied when using the baud rate generator. If a crystal is used, a capacitor of approximately 10 pF should be connected from this signal to ground. If this input is not used, it must be connected to VCC or GND. Refer to SECTION 10

APPLICATIONS for an example of a clock driver circuit.

7.2.2 Crystal Output (X2)

This output is the additional connection to a crystal. If a crystal, is used, a capacitor of approximately 5 pF should be connected from this signal to ground.

If an external TTL-level clock is used on X1 or SCLK, the baud rate generator is bypassed and the X2 output must be left open. Refer to SECTION 10 AP-

PLICATIONS for an example of a clock driver circuit.

7.2.3 External Input (SCLK)

This input can be used as the clock input for channel A and/or channel Band is programmable in the clock-select registers (CSR). When used as the receiver clock, received data is sampled on the rising edge of the clock. When used as the transmitter clock, data is output on the falling edge of the clock. If this input is not used, it must be connected to VCC or GND.

7.2.4 Channel A Transmitter Serial Data Output (TxDA)

This signal is the transmitter serial data output for channel A. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the local loop back mode. Data is shifted out on this signal on the falling edge of the programmed clock source, with the least significant bit transmitted first.

7.2.5 Channel A Receiver Serial Data Input (RxDA)

This signal is the receiver serial data input for channel A. Data received on this signal is sampled on the rising edge of the programmed clock source, with the least significant bit received first.

7-6


7.2.6 Channel B Transmitter Serial Data Output (TxDB)

This signal is the transmitter serial data output for channel B. The output is held high ('mark' condition) when the transmitter is disabled, idle, or operating in the localloopback mode. Data is shifted out on this signal at the falling edge of the programmed clock source, with the least significant bit transmitted first.

7.2.7 Channel B Receiver Serial Data Input (RxDB)

This signal is the receiver serial data input for channel B. Data on this signal is sampled on the rising edge of the programmed clock source, with the least significant bit received first.

7.2.8 Channel A Request To Send (RTSA)

This active-low output signal is programmable as the channel A request to send or as a dedicated parallel output.

7.2.8.1 RTSA. When used for this function, this signal can be programmed to be automatically negated and asserted by either the receiver or transmitter. When connected to the c1ear-to-send (CTS) input of a receiver, this signal can be used to control serial data flow.

7.2.8.2 OPO. When used for this function, this output reflects the complement of the value of bit 0 in the output port data register (OP).

7.2.9 Channel B Request To Send (RTSB)

This active-low output signal is programmable as the channel B request to send or as a dedicated parallel output.

7.2.9.1 RTSB. When used for this function, this signal can be programmed t9 be automatically negated and asserted by either the receiver or transmitter. When connected to the c1ear-to-send (CTS) input of a port, this signal can be used to control serial data flow.

7.2.9.2 OP1. When used for this function, this output reflects the complement of the value of bit 1 in the OP.

MOTOROLA


7-7

7.2.10 Channel A Clear To Send (CTSA)

This active-low input is the channel A clear to send.

7.2.11 Channel B Clear To Send (CTSB)

This active-low input is the channel B clear to send.

7.2.12 Channel A Transmitter Ready (TxRDYA)

This active-low output signal is programmable as the channel A transmitter ready or as a dedicated parallel output.

7.2.12.1 TxRDYA. When used for this function, this signal reflects the status of bit 2 of the channel A status register (SRA). This signal can be used to control parallel data flow by acting as an interrupt to indicate when the transmitter contains a character.


7.2.13 Channel A Receiver Ready (RxRDYA)

This active-low output signal is programmable as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output.

7.2.13.1 RxRDYA. When used for this function, this signal reflects the status of

ISR bit 1. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver contains a character.

7.2.13.2 FFULLA. When used for this function, this signal reflects the status of

ISR bit 1. This signal can be used to control parallel data flow by acting as an interrupt to indicate when the receiver FIFO is full.



MOTOROLA

7.3 OPERATION

The following paragraphs describe the operation of the baud rate generator, transmitter and receiver, and other functional operating modes of the serial module.

7.3.1 Baud Rate Generator

The baud rate generator consists of a crystal oscillator, baud rate generator, and clock selectors (see Figure 7-3). The crystal oscillator operates directly from a 3.6864-MHz crystal or from an external clock of the same frequency. The SCLK input bypasses the baud rate generator and provides a synchronous mode of operation when used with a divide-by-1 clock and an asynchronous mode when used with the divide-by-16 clock. The clock is selected by programming the

CSR for each channel.

BAUD RATE

GENERATOR LOGIC

CRYSTAL

OSCILLATOR

BAUD RATE

GENERATOR

t

CLOCK

SELECTORS

EXTERNAL

INTERFACE

"

X1

X2

SCLI<

..

Figure 7-3. Baud Rate Generator Simplified Functional Diagram

7.3.2 Transmitter and Receiver Operating Modes

The simplified functional block diagram of the transmitter and receiver, including command and operating registers, is shown in Figure 7-4. The paragraphs that follow contain descriptions for both these functions in reference to this diagram. For detailed register information, refer to 7.4.1 REGISTER DE-

SCRIPTION AND PROGRAMMING.

MOTOROLA


CHANNEL A EXTERNAL

INTERFACE

TRANSMIT { ....

BUFFER (TBA)

(2 REGISTERS)

TxDA

CHANNELB

I •• ·••·•· ····.···.•··•• ••••••.••

9.9.MM*N9ft§qi.§T§R(§R~j

•.• ·.··)

.H)·······.·.···.···.·····.·.·.···.·.· .•

·w.1

~I

'

..

II

TxDB

RxDB

7-10

NOTE:

RIW=AEADiWRITE

R=READ

W=WRITE

Figure 7-4. Transmitter and Receiver Simplified Functional Diagram


MOTOROLA

7.3.2.1 TRANSMITIER.

The transmitters are enabled through their respective command registers (CR) located within the serial module. The serial module signals the CPU32 when it is ready to accept a character by setting the transmitter-ready bit (TxRDY) in the channel's status register (SR). Functional timing information for the transmitter is shown in Figure 7-5.

The transmitter converts parallel data from the CPU32 to a serial bit stream on

TxDx. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits.

The least significant bit is sent first. Data is shifted from the transmitter output on the falling edge of the programmed clock source.

Following transmission of the stop bits, if a new character is not available in the transmitter holding register, the TxDx output remains high ('mark' condition), and the transmitter empty bit (TxEMP) in the SR is set. Transmission resumes and the TxEMP bit is cleared when the CPU32 loads a new character into the transmitter buffer (TB). If a disable command is sent to the transmitter, it continues operating until the character in the transmit shift register, if any, is completely sent out. If the transmitter is reset through a software command, operation ceases immediately (refer to 7.4.1.7 COMMAND REGISTER). The transmitter is re-enabled through the CR to resume operation after a disable or softwa re reset.

If clear-to-send (CTS) operation is enabled, CTSx must be asserted for the character to be transmitted. If CTSx is negated in the middle of a transmission, the character in the shift register is transmitted, and TxDx remains in the 'mark' state until CTSx is asserted again. If the transmitter is forced to send a continuous low condition by issuing a send break command, the state of CTSx is ignored by the transmitter. .

The transmitter can be programmed to automatically negate request-to-send

(RTS) upon completion of a message transmission. If the transmitter is programmed to operate in this mode, RTSx must be manually asserted before a message is transmitted. In applications in which the transmitter is disabled after transmission is complete and RTSx is appropriately programmed, RTSx is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually re-enabled by reasserting RTSx before the next message is to be sent.

MOTOROLA


~

I\.)

~ a

-I a

::IJ a

~ s: n co

~. o s: l>

2

C l> rc

en

m

:lJ

en

C11N

TRANSMISSION

TxDx

TRANSMITTER

ENABLED

TxRDY

(SR2)

CS

CTS

1

RTS2

MANUAlLY ASSERTED

BY BIT- SET COMMAND

NOTES:

1. TIMING SHOWN FOR MR2(4) = 1

2. TIMING SHOWN FOR MR2(5) = 1

3. C N = TRANSMIT CHARACTER

4. W=WRlTE

Figure 7-5. Transmitter Timing Diagram

C5

NOT

TRANSMITTED

MANUAlLY

ASSERTED

7.3.2.2

RECEIVER.

The receivers are enabled through their respective CRs located within the serial module. Functional timing information for the receiver is shown in Figure 7-6. The receiver looks for a high-to-Iow (mark-to-space) transition of the start bit on RxDx. When a transition is detected, the state of RxDx is sampled each 16 x clock for seven and one-half clocks (16 x clock mode) or at the next rising edge of the bit time clock (1 x clock mode). If RxDx is sampled high, the start bit is invalid and the search for the valid start bit begins again. If RxDx is still low, a valid start bit is assumed, and the receiver continues to sample the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the RxDx input is sampled on the rising edge of the programmed clock source. The least significant bit is received first. The data is then transferred to a receiver holding register, and the receiver-ready bit (RxRDY) in the appropriate SR is set. If the character length is less than eight bits, the most significant unused bits in the holding register are cleared.

After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a nonzero character is received without a stop bit (framing error) and RxDx remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit is detected. The parity error

(PE), framing error (FE), overrun error (OE), and received break (RB) conditions

(if any) set error and break flags in the appropriate SR at the received character boundary and are valid only when the RxRDY bit in the SR is set.

If a break condition is detected (RxDx is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register, and the RB and RxRDY bits in the SR are set. The RxDx signal must return to a high condition for at least one-half bit time before a search for the next start bit begins.

The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. When the break begins in the middle of a character, the receiver places the damaged character in the receiver first-in-first-out (FIFO) stack and sets the corresponding error conditions and RxRDY bit in the SA. Then, if the break persists until the next character time, the receiver places an all-zero character into the receiver FIFO and sets the corresponding RB and RxRDY bits in the SR.

7.3.2.3

FIFO

STACK. The FIFO stack is used in each channel's receiver buffer logic.

The stack consists of three receiver holding registers. The RB consists of the

FIFO and a receiver shift register connected to the RxDx (refer to Figure 7-4).

Data is assembled in the shift register and loaded into the top empty receiver

MOTOROLA


RxD

RECEIVER

ENABLED

RxRDY

(SRO) holding register position of the FIFO. Thus, data flowing from the receiver to the CPU32 is quadruple buffered.

In addition to the data byte, three status bits, PE, FE, and RB, are appended to each data character in the FIFO (OE is not). By programming the error mode control bit in the channel's mode register (MR1), status is provided in character or block modes.

II

II

FFULL

(SR1)

RxRDYA

R R

\STATU~I

C1

C5LOST

OVERRUN

(SR4)

OPR(O) .. 1

NOTES:

1. Timing shown for MR1(7)-1

2. Timing shown for OPCR(4) .. 1 and MR1 (6) _ 0

3. R .. Read

4. CN" Received Character

Figure 7-6. Receiver Timing Diagram

RESET BY COMMAND

7-14


MOTOROLA

The RxRDY bit in the SR is set whenever one or more characters are available to be read by the CPU32. A read of the RS produces an output of data from the top of the FIFO stack. After the read cycle, the data at the top of the FIFO stack and its associated status bits are 'popped', and new data can be added at the bottom of the stack by the receiver shift register. The FIFO-full status bit

(FFULL) is set if all three stack positions are filled with data. Either the RxRDY or FFULL bit can be selected to cause an interrupt.

In the character mode, status provided in the SR is given on a character-bycharacter basis and thus applies only to the character at the top of the FIFO.

In the block mode, the status provided in the SR is the logical OR of all characters coming to the top of the FIFO stack since the last reset error command. A continuous logical OR function of the corresponding status bits is produced in the SR as each character reaches the top of the FIFO stack. The block mode is useful in applications where the software overhead of checking each character's error cannot be tolerated. In this mode, entire messages are received, and only one data integrity check is performed at the end of the message. This mode allows a data-reception speed advantage, but does have a disadvantage since each character is not individually checked for error conditions by software. If an error occurs within the message, the error is not recognized until the final check is performed, and no indication exists as to which character in the message is at fault.

In either mode, reading the SR does not affect the FIFO. The FIFO is 'popped' only when the RS is read. The SR should be read prior to reading the RS. If all three of the FIFO's receiver holding registers are full when a new character is received, the new character is held in the receiver shift register until a FIFO position is available. If an additional character is received during this state, the contents of the FIFO are not affected. However, the character previously in the receiver shift register is lost, and the OE bit in the SR is set when the receiver detects the start bit of the new overrunning character.

To support control-flow capability, the receiver can be programmed to automatically negate and assert RTSx. When in this mode, RTSx is automatically negated by the receiver when data is detected and the FIFO stack is full. When a FIFO position becomes available, RTSx is asserted by the receiver. Using this mode of operation, overrun errors are prevented by connecting the RTSx to the CTSx input of the transmitting device. RTSx must be manually asserted the first time in this mode.

If the FIFO stack contains characters and the receiver is disabled, the characters in the FIFO can still be read by the CPU32. If the receiver is reset, the FIFO stack


and all of the receiver status bits, the corresponding output ports, and the interrupt request are reset. No additional characters are received until the receiver is re-enabled.

7.3.3 Loop Modes

Each serial module channel can be configured to operate in various loop modes as shown in Figure 7-7. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs with further information available in 7.4 REGISTER DESCRIPTION AND PRO-

GRAMMING.

The channel should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.

7.3.3.1 AUTOMATIC ECHO MODE. In this mode, the channel automatically retransmits the received data on a bit-by-bit basis. The local CPU32-to-receiver communication continues normally, but the CPU32-to-transmitter link is disabled. While in this mode, received data is clocked on the receiver clock and retransmitted on TxDx. The receiver must be enabled, but the transmitter need not be enabled.

Since the transmitter is not active, the SR TxRDY and TxEMP bits are inactive, and data is transmitted as it is received. Received parity is checked, but not recalculated for transmission. Character framing is also checked, but stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected.

7.3.3.2 LOCAL LOOPBACK MODE. In this mode, TxDx is internally connected to

RxDx. This mode is useful for testing the operation of a local serial module channel by sending data to the transmitter and checking data assembled by the receiver. In this manner, correct channel operations can be assured. Also, both transmitter and CPU32-to-receiver communications continue normally in this mode. While in this mode, the RxDx input data is ignored, the TxDx is held marking, and the receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be enabled.

7-16


7.3.3.3 REMOTE LOOPBACK MODE. In this mode, the channel automatically transmits received data on the TxDx output on a bit-by-bit basis. The local

CPU32-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. While in this mode, the receiver clock is used for the transmitter.

Since the receiver is not active, received data can not be read by the CPU32, and the error status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are transmitted as received. A received break is echoed as received until the next valid start bit is detected.

CPU

~-----«:----

RxDx

INPUT

_

.L--_----'~

~

TxDx

OUTPUT

(a) Automatic Echo

CPU

(b) Local Loopback

CPU

B ~S~BI!D_

~

C

RxDx

INPUT

~S~BI!D_

~

(c) Remote Loopback

TxDx

OUTPUT

TxDx

OUTPUT

INPUT

Figure 7-7. Loop Modes Functional Diagram

7-17


7.3.4

Multidrop Mode

A channel can be programmed to operate in a wakeup mode for multidrop or multiprocessor applications. Functional timing information for the multidrop mode is shown in Figure 7-8. The mode is selected by setting bits 3 and 4 in mode register 1 (MR1). This mode of operation allows the master station to be connected to several slave stations (maximum of 256). In this mode, the master transmits an address character followed by a block of data characters targeted for one of the slave stations. The slave stations have their channel receivers disabled. However, they continuously monitor the data stream sent out by the master station. When an address character is sent by the master, the slave receiver channel notifies its respective CPU by setting the RxRDY bit in the SR and generating ar"! interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Slave stations not addressed continue to monitor the data stream for the next address character. Data fields in the data stream are separated by an address character. After a slave receives a block of data, the slave station's CPU disables the receiver and initiates the process again.

A transmitted character from the master station consists of a start bit, a programmed number of data bits, an addressldata (AID) bit flag, and a programmed number of stop bits. The AID bit identifies the type of character being transmitted to the slave station. The character is interpreted as an address character if the AID bit is set or as a data character if the AID bit is cleared. The polarity of the AID bit is selected by programming bit 2 of the MR1. The MR1 should be programmed before enabling the transmitter and loading the corresponding data bits into the transmitter buffer (TB).

In multidrop mode, the receiver continuously monitors the received data stream regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RxRDY bit and loads the character into the receiver holding register

FIFO stack provided the received AID bit is a one (address tag). The character is discarded if the received

AID bit is a zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU32 via the receiver holding register stack during read operations.

In either case, the data bits are loaded into the data portion of the stack while the AID bit is loaded into the status portion of the stack normally used for a parity error (SR bit 5). Framing error, overrun error, and break-detection operate normally. The AID bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection

7-18


and correction information. One way to provide error detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the unused 5-, 6-, or 7-bit character.

MASTER STATION

TxD

AID

\ADfRll \

Icol~IO

AID

\AD~Rll

I

I

I

~

~

TRANSMITTER

ENABLED

TxRDY

(SR2)

/

cs

ADDRl MR1(2) ..

O

PERIPHERAL

STATION

~

AID

I

°

AID

I

I

IA~DRlll

RECEIVER

ENABLED

RxROY

(SRO)

MR1(2)=1 ADDR2

Ico::1

CJ

\AD2DRll \

AID

I

I

\

I

~ t"II ....

I

° ltvk

4

W

MR1(4:3)

W R R R

ENABLE ADDR STATUS DATA

'----..--' co

Figure 7-8. Multidrop Mode Timing Diagram

R R

STATUS DATA

~

ADDR

7.3.5 Bus Operation

This section describes the operation ofthe 1MB during read, write, and interrupt acknowledge cycles to the serial module.

MOTOROLA 7-19


7.3.5.1 READ CYCLES. The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte, word, and long-word reads, although only eight bits of valid data are returned. Reserved registers return logic zero during reads.

7.3.5.2 WRITE CYCLES.

The serial module is accessed by the CPU32 with no wait states. The serial module responds to byte, word, and long-word writes, but care must be taken to properly align and size write operations as AD determines the alignment of the data. Write cycles to read-only registers and reserved registers complete in a normal manner without exception processing; however, the data is ignored.

7.3.5.3 INTERRUPT ACKNOWLEDGE CYCLES. The serial module is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt vector register (IVR) must be initialized. If the IVR is not initialized, a spurious interrupt exception will be taken if interrupts are generated.

7.4 REGISTER DESCRIPTION AND PROGRAMMING

This section contains a detailed description of each 'register and its specific function as well as examples of basic serial m.odule programming.

7.4.1 Register Description

The operation of the serial module is controlled by writing control words into the appropriate registers. A list of serial module registers and their associated addresses are listed in Table 7-1. The command, clock-select, status, and mode registers are duplicated for each channel to provide independent operation and control.

NOTE

The contents of the mode registers (MR1 and MR2), clock-select register (CSR), and the auxiliary control register (ACR) bit 7 should only be changed after the receiver/transmitter is issued a software reset command i.e., channel operation must be disabled. Care should also be taken if the register contents are changed during receiver/ transmitter operations, as undesirable results may be produced.


MOTOROLA

In the registers discussed in the following pages, the numbers in the upper right-hand corner indicate the offset of the register from the base address specified in the base address register in the SIM. The numbers above the register description represent the bit position in the register. The second line contains the mnemonic for the bit. The values shown below the register diagram are the values of those register bits after reset. A value of U indicates that the bit value is unaffected by reset. The read/write status and the access privilege are shown in the last line.


ADDRESS FC

700

S'

701

702

703

704

705

Table 7-1.

Re~ister

Addressing and Address-Triggered Commands

REGISTER READ (RIW =

11

MCR (HIGH BYTE!

MCR (LOW BYTEI

DO NOT ACCESS3

DO NOT ACCESS3

INTERRUPT LEVEL (ILRI

INTERRUPT VECTOR (IVRI

REGISTER WRITE (RIW=OI

MCR (HIGH BYTEI

MCR (LOW BYTEI

DO NOT ACCESS3

DO NOT ACCESS3

INTERRUPT LEVEL (ILRI

INTERRUPT VECTOR (lVRI

710

711

712

713

S/U2

S/U

S/U

S/U

MODE REGISTER MR1A

STATUS REGISTER A (SRA)

DO NOT ACCESS3

RECEIVER BUFFER A (RBAI

MODE REGISTER MR1A

CLOCK-SELECT REGISTER A (CSRA)

COMMAND REGISTER A (CRA)

TRANSMITIER BUFFER A (TBAI

714

715

716

717

718

719

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

INPUT PORT CHANGE REGISTER (lPCRI

INTERRUPT STATUS REGISTER (ISRI

DO NOT ACCESS3

DO NOT ACCESS3

MODE REGISTER MR1 B

RECEIVER BUFFER B (RBBI

DO NOT ACCESS3

AUXILIARY CONTROL REGISTER (ACRI

INTERRUPT ENABLE REGISTER (lERI

DO NOT ACCESS3

DO NOT ACCESS3

MODE REGISTER MR1B

CLOCK SELECT REGISTER B (CSRBI

71A

71B

71C

710

71E

71F

S/U

S/U

S/U

STATUS REGISTER B (SRBI

DO NOT ACCESS3

INPUT PORT REGISTER (lPI

DO NOT ACCESS3

DO NOT ACCESS3

COMMAND REGISTER B (CRBI

TRANSMITIER BUFFER B (TBBI

DO NOT ACCESS3

OUTPUT PORT CONTROL REGISTER (OPCRI

OUTPUT PORT (oPl4 BIT SET

720 S/U MODE REGISTER MR2A

721

S/U MODE REGISTER MR2B

NOTES:

1. S Register permanently defined as supervisor-only access

2. S/U Register programmable as either supervisor or user access

3. A read or write to these locations currently has no effect.

4. Address-triggered commands

OUTPUT PORT (OPI4 BIT RESET

MODE REGISTER MR2A

MODE REGISTER MR2B

7-22


MOTOROLA

7.4.1.1 MODULE CONFIGURATION REGISTER (MCR). The MCR controls the serial module configuration. The register can be either read or written when the module is enabled and is in the supervisor state.

MCR

15 14 13 12 11

I

STP , FRll , FRlO 'ICCS , 0

RESET:

10 7 3 2 1

$700

0

Read/Write Supervisor/User

STP Stop Mode

1

=

Stops all clocks within the serial module (including the crystal and SCLK) except for the clock from the 1MB. The clocks are stopped on the low phase of the clock and will remain stopped until this bit is cleared. The clock from the 1MB remains active to allow the CPU32 to access the

MCR. Accesses to other serial module registers produce a bus error while in stop mode. The serial module should be disabled (in a known state) prior to setting the STP bit; otherwise, unpredictable results may occur.

0= The serial module operates in normal mode.

FRZ1-FRZO Freeze

These bits determine the action taken when the FREEZE signal is asserted by the 1MB. Table 7-2 lists the action taken for each combination of bits.

Table 7-2. FREEZE Control Bits

FRZ1 FRZO

0 0

ACTION

Ignore FREEZE

0

1

1

1 Reserved (FREEZE Ignored)

0 Freeze on Character Boundary

1

Freeze on Character Boundary

If FREEZE is asserted, channel A and channel B freeze independently of each other. The transmitter and receiver freeze at character boundaries. The transmitter does not freeze in the send break mode. Communications can be lost if the channel is not programmed to support flow control. If the channel is programmed for flow control, the assertion of FREEZE causes the RTSx and CTSx pins to disable at the end of the character boundary. See SECTION 4 SYSTEM

INTEGRATION MODULE for more information.

MOTOROLA


7-23

ICCS Input Capture Clock Select

1

=

Selects SCLK as the input capture clock for both channels. The data is captured on the CTSA and CTSB pins on the rising edge of the clock.

0= The crystal clock is the input capture clock for both channels.


1

=

The serial module registers, which are defined as supervisor or user, reside in supervisor data space and are only accessible from supervisor programs.

0= The serial module registers, which are defined as supervisor or user, reside in user data space and are accessible from either supervisor or user programs.

The value of this bit has no effect on registers permanently defined as supervisor only.

IARB3-IARBO Interrupt Arbitration Bits

Each module that generates interrupts has an IARB field. The value of the

IARB field allows arbitration during an interrupt acknowledge cycle among modules that simultaneously generate the same interrupt level. No two modules can share the same IARB value. The reset value of IARB is $0, which prevents this module from arbitrating during the interrupt acknowledge cycle.

The system software should initialize the IARB field to a value from $F (highest priority) to $1 (lowest priority).

7.4.1.2 INTERRUPT LEVEL REGISTER (lLR). The ILR contains the priority level for the serial module interrupt request. When the serial module is enabled, this register can be read or written to at any time while in supervisor mode.

ILR $704

I

0 o

I

0

I

0 o

I

IL2

I

III ILO

RESET:


IL2-ILO Interrupt Level Bits

Each module that can generate interrupts has an ILR. The priority level encoded in these bits is sent to the CPU32 on the appropriate IRQx signal. The

CPU32 uses this value to determine servicing priority. See SECTION 5 CPU32 for more information.

.7-24


MOTOROLA

7.4.1.3 INTERRUPT VECTOR REGISTER (iVR). The IVR contains the 8-bit vector number of the interrupt.

IVR $705

6 5 3 0

I

IVA7

I

IVAG

I

IVA5

I

IVA4

I

IVA3

I

IVA2

I

IVAI

I

IVAO

AESET:

Read /Write Supervisor Only

IVR7-IVRO Interrupt Vector Bits

Each module that can generate interrupts has an IVR. This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IVR is reset to $OF, which indicates an uninitialized interrupt condition. See SECTION 5

CPU32 for more information.

7.4.1.4 MODE REGISTER 1 (MR1). MR1 controls some of the serial module configuration. This register can be read or written at any time when the serial module is enabled.

MR1A, MR1B $710,$718

I

AxATS

I

A/F

I

EAA

I

PMI

I

PMO

I

PT

I

Blel

I

B/eo

I

AESET:

Read/Write Su pervisor/User

RxRTS Receiver Request-to-Send Control

1 = Upon receipt of a valid start bit, RTSx is negated if the channel's FIFO is full. RTSx is reasserted when the FIFO has an empty position available.

0= RTSx is asserted by setting bit 1 or 0 in the OP and negated by clearing bit 1 or 0 in the OP.

This feature can be used for flow control to prevent overrun in the receiver by using the RTSx output to control the CTSx input of the transmitting device.

If both the receiver and transmitter are programmed for RTS control, RTS control will be disabled for both, as this configuration is incorrect. See 7.4.1.17

MODE REGISTER 2 for information on programming the transmitter RTS control.


7-26

R/F Receiver-Ready Select

1

=

Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel

FIFO full status. These ISR bits are set when the receiver FIFO is full and are cleared when a position is available in the FIFO.

0= Bit 5 for channel B and bit 1 for channel A in the ISR reflect the channel receiver-ready status. These ISR bits are set when a character has been received and are cleared when the CPU32 reads the receiver buffer.

ERR-Error Mode

This bit controls the meaning of the three FIFO status bits (FE, PE, and RB) for the channel.

1

=

Block mode The values in the channel SR are the accumulation (i.e., the logical OR) of the status for all characters coming to the top of the

FIFO since the last reset error status command for the channel was issued. Refer to 7.4.1.7 COMMAND REGISTER (CR) for more information on serial module commands.

0= Character mode The values in the channel SR reflect the status of the character at the top of the FIFO.

PM1-PMO Parity Mode

These bits encode the type of parity used for the channel. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. These bits can alternatively select multidrop mode for the channel. Table 7-3 lists the parity mode and type or the multidrop mode for each combination of the parity mode and the parity type bits.

PT Parity Type

This bit selects the parity type if parity is programmed by the parity mode bits, and, if multidrop mode is selected, it configures the transmitter for address character transmission or data character transmission.

Table 7-3. Parity Mode and Parity Type Control Bits

PM1

0

0

0

0

1

1

1

PMO

0

0

1

1

0

1

1

Parity Mode

With Parity

With Parity

Force Parity

Force Parity

No Parity

,Multidrop Mode

Multidrop Mode

1

X

0

1

PT

0

1

0

Parity Type

Even Parity

Odd Parity

Low Parity

High Parity

No Parity

Data Character

Address Character


MOTOROLA

B/C1 ,B/CO Bits per Character

These bits select the number of data bits per character to be transmitted.

The character length listed in Table 7-4 does not include start, parity, or stop bits.

Table 7-4. Bits/Character

Control Bits

B/C1 B/CO

0

0

1

1

0

1

0

1

Bits/Character

Five Bits

Six Bits

Seven Bits

Eight Bits

7.4.1.5 STATUS REGISTER (SR). The SR indicates the status of the characters in the FIFO and the status of the channel transmitter and receiver. This register can only be read when the serial module is enabled.

SRA,SRB

$711,$719

I

RB

I

FE

PE CE

I

3

RESET:

2 1 0

I

TxRDY

I

FFULL

I

RxRDY

I

Read Only Supervisor/User

RB Received Break

1 =An all-zero character ofthe programmed length has been received without a stop bit. The RB bit is only valid when the RxRDY bit is set. Ohly a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until the channel RxDx returns to the high state for at least one-half bit time, which is equal to two successive edges of the internal or external 1 x clock or 16 successive edges of the external 16 x clock.

The received break circuit detects breaks that originate in the middle of a received character. However, if a break begins in the middle of a character, it must persist until the end of the next detected character time. a

= No break has been received.

MOTOROLA


7-28

FE Framing Error

1 =A stop bit was not detected when the corresponding data character in the FIFO was received. The stop-bit check is made in the middle of the first stop-bit position. The bit is valid only when the RxRDY bit is set. a

=

No framing error has occurred.

PE Parity Error

1 = When the with parity or force parity mode is programmed (MR1), the corresponding character in the FIFO was received with incorrect parity.

When the multidrop mode is programmed, this bit stores the received

AID

bit. This bit is valid only when the RxRDY bit is set. a

=

No parity error has occurred.

OE Overrun Error

1

=

One or more characters in the received data stream have been lost.

This bit is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, parity error, and framing error status, if any, are lost. This bit is cleared by the reset error status command in the CR. a

=

No overrun has occurred.

TxEMP Transmitter Empty

1

=

The channel transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission. This bit is cleared when the transmitter holding register is loaded by the CPU32 or when the transmitter is disabled. a

=

The TB is not empty.

TxRDY Transmitter Ready

1

=

The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted and are lost. a

=

The transmitter holding register was loaded by the CPU32. This bit is also cleared when the transmitter is disabled.


MOTOROLA

FFULL FIFO Full

1 = A character was transferred from the receiver shift register to the receiver FIFO and the transfer caused the FIFO to become full (all three

FIFO holding register positions are occupied).

0= The CPU32 has read the RB and one or more FIFO positions are available. Note that if there is a character in the receiver shift register because the FIFO is full, this character will be moved into the FIFO when a position is available, and the FIFO will remain full.

RxRDY Receiver Ready

1 =A character has been received and is waiting in the FIFO to be read by the CPU32. This bit is set when a character is transferred from the receiver shift register to the FIFO.

0= The CPU32 has read the RB, and no characters remain in the FIFO after this read.

7.4.1.6 CLOCK-SELECT REGISTER (CSR). The CSR selects the baud rate clock for the channel receiver and transmitter. This register can only be written.

NOTE

This register should only be written after the external crystal is stable

(XTAL_RDY bit (bit 3) of the ISR is zero).

CSRA, CSRB $711, $719

7 6 5 4 3 2 1 0

I

RCS3

I

RCS2

I

RCS1

I

RCSO

I

TCS3

I

TCS2

I

TCS1

I

TCSO

I

RESET:

Write Only Supervisor/User


7-29

RCS3-RCSO Receiver Clock Select

These bits select the baud rate clock for the channel receiver from a set of baud rates listed in Table 7-5. The baud rate set selected depends upon ACR bit 7. Set 1 is selected if ACR bit 7

=

0, and set 2 is selected if ACR bit 7

=

1.

The receiver clock is always 16 times the baud rate shown in this list, except when SCLK is used.

1

1

1

1

1

0

1

1

1

0

0

0

0

RCS3

0

0

0

1

0

0

1

1

1

0

0

1

RCS1

0

0

1

1

0

0

1

1

1

1

1

0

0

0

0

0

1

1

1

1

RCS2

0

0

0

Table 7-5. Receiver Clock Select

0

1

0

1

0

1

0

1

0

1

RCSO

0

1

0

1

0

1

Set 1

50

110

134.5

200

300

600

1200

1050

2400

4800

7200

9600

38.4k

76.8k

SCLK/16

SCLK/1

Set 2

75

110

134.5

150

300

600

1200

2000

2400

4800

1800

9600

19.2k

38.4k

SCLK/16

SCLK/1

TCS3-TCSO Transmitter Clock Select

These bits select the baud rate clock for the channel transmitter from a set of baud rates listed in Table 7-6. The baud rate set selected depends upon

ACR bit 7. Set 1 is selected if ACR bit 7

=

0, and set 2 is selected if ACR bit

7

=

1. The receiver clock is always 16 times the baud rate shown in this list, except when SCLK is used.


MOTOROLA

Table 7-6. Transmitter Clock Select

0

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

0

0

0

0

1

TCS3 TCS2 TCS1

TCSO

0 0 0 0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Set 1

50

110

134.5

200

300

600

1200

1050

2400

4800

7200

9600

38.4k

76.8k

SCLKl16

SCLKl1

Set 2

75

110

134.5

150

300

600

1200

2000

2400

4800

1800

9600

19.2k

38.4k

SCLKl16

SCLK/1

7.4.1.7 COMMAND REGISTER (CR). CR is used to supply commands to the channel. Multiple commands can be specified in a single write to the CR if the commands are not conflicting e.g., enable transmitter and reset transmitter commands cannot be specified in a single command. This register can only be written when the serial module is enabled.

CRA,CRB

$712, $71A

7 6 5 4

I

MISC31 MISC21 MISCI

I

MISCO

I

TCI TCO RCI RCa

RESET:

Write Only

Supervisor/User

MISC3-MISCO Miscellaneous Commands

These bits select a single command as listed in Table 7-7.

MOTOROLA


7-32

Table 7-7. Miscellaneous Command Control Bits

MISC3 MISC2 MISC1 MISCO

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

Command

No Command

No Command

Reset Receiver

Reset Transmitter

Reset Error Status

Reset Break-Change Interrupt

Start Break

Stop Break

-

Assert RTS

1

1

1

1

1

1

1

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

Negate RTS

No Command

No Command

No Command

No Command

No Command

No Command

Reset Receiver The reset receiver command resets the channel receiver.

The receiver is immediately disabled, the SR RxRDY and FFULL bits (bits 0 and 1) are cleared, and the receiver FIFO pointer is reinitialized. All other registers are unaltered. This command should be used in lieu of the receiver disable command whenever the receiver configuration is changed because it places the receiver in a known state.

Reset Transmitter - The reset transmitter command resets the channel transmitter. The transmitter is immediately disabled, and the SR TxRDY and TxEMP bits (bits 2 and 3) are cleared. All other registers are unaltered. This command should be used in lieu of the transmitter disable command whenever the transmitter configuration is changed because it places the transmitter in a known state.

Reset Error Status The reset error status command clears the channel's

SR RB, PE, FE, and OE (bits

7-4).

This command is also used in the block mode to clear all error bits after a data block is received.

Reset Break-Change Interrupt The reset break-change interrupt command clears the break-detect change bit (bit 2 of the ISR).


MOTOROLA

Start Break The start break command forces the channel's TxDx low. If the transmitter is empty, the start of the break conditions can be delayed up to one bit time. If the transmitter is active, the break begins when transmission of the character is complete. If a character is in the transmitter shift register, the start of the break is delayed until the character is transmitted. If the transmitter holding register has a character, that character is transmitted after the break. The transmitter must be enabled for this command to be accepted.

The state of the CTSx input is ignored for this command.

Stop Break The stop break command causes the channel's TxDx to go high (mark) within two bit times. Characters stored in the TB, if any, are transmitted.

Assert RTS The assert RTS command forces the channel's RTSx output low.

Negate RTS The negate RTS command forces the channel's RTSx output high.

TC1-TCO Transmitter Commands


Table 7-8. Transmitter Command Bits

TC1

0

0

1

1

TCO

0

1

0

1

Command

No Action Taken

Transmitter Enable

Transmitter Disable

Do Not Use

No Action Taken The no action taken command causes the transmitter to stay in its current mode. If the transmitter is enabled, it remains enabled; if disabled, it remains disabled.

Transmitter Enable The transmitter enable command enables operation of the channel's transmitter. The TxRDY and TxEMP bits (bits 2 and 3 of the

SR) are also set. If the transmitter is already enabled, this command has no effect.

Transmitter Disable The transmitter disable command terminates transmitter operation and clears the TxRDY and TxEMP bits (bits 2 and 3 of the

MOTOROLA


SR). However, if a character is being transmitted when the transmitter is disabled, the transmission of the character is completed before the transmitter becomes inactive. If the transmitter is already disabled, this command has no effect.

Do Not Use Do not use this bit combination as the result is indeterminate.

RC1-RCO Receiver Commands


RC1

0

0

1

1

Table 7-9. Receiver Command Bits

RCO

0

1

0

1

Command

No Action Taken

Receiver Enable

Receiver Disable

Do Not Use

No Action Taken The no action taken command causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.

Receiver Enable The receiver enable command enables operation of the channel's receiver. If the serial module is not in multidrop mode, this command also forces the receiver into the search-for-start-bit state. If the receiver is already enabled, this command has no effect.

Receiver Disable The receiver disable command disables the receiver immediately. Any character being received is lost. The command has no effect on the receiver status bits or any other control register. If the serial module is programmed to operate in the local loopback mode or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, this command has no effect.

Do Not Use Do not use this bit combination because the result is indeterminate.

7.4.1.8 RECEIVER BUFFER (RB). The RB contains three receiver holding registers and a serial shift register. The channel's RxDx pin is connected to the serial shift register. The holding registers act as a FIFO. The CPU32 reads from the top of the stack while the receiver shifts and updates from the bottom of the


stack when the shift register has been filled (see Figure 7-4). This register can only be read when the serial module is enabled.

RBA,RBB $713,$71B

7 6 5 4 3 2 1 0

I

RB7

I

RB6

I

RB5

I

RB4

I

RB3

I

RB2

I

RB1

I

RBO

RESET:


RB7-RBO These bits contain the character in the RB.

7.4.1.9 TRANSMITTER BUFFER (TB). The TB consists of two registers, the transmitter holding register and the transmitter shift register (See Figure 7-4). The holding register accepts characters from the bus master if the TxRDY bit in the channel SR is set. A write to the TB clears the TxRDY bit, inhibiting any more characters until the shift register is ready to accept more data. The shift register, when empty, checks to see if the holding register has a valid character to be sent (TxRDY bit cleared). If there is a valid character, the shift register loads the character and reasserts the TxRDY bit in the channel's SR. Writes to the

TB when the channel's SR TxRDY bit is clear and when the transmitter is disabled have no effect on the TB. This register can only be written when the serial module is enabled.

TBA, TBB $713, $71B

7 6 5 4 3 2 1 0

I

TB7

I

TB6

I

TB5

I

TB4

I

TB3

I

TB2

I

TB1

I

TBO

RESET:


TB7-TBO These bits contain the character in the TB.

7.4.1.10 INPUT PORT CHANGE REGISTER (lPCR). The IPeR shows the current state and the change of state for the eTSA and eTSB pins. This register can only be read when the serial module is enabled.


IPCR

7 '6

$714

0 5 4 1

I 0 I 0 I COSB I COSA I 0 I 0 I CTSB I CTSA I

RESET: u u


COSB, COSA Change of State

1 =A change of state, a high-to-Iow or low-to-high transition, lasting longer than 25-50 jJ.s when using a crystal as the sampling clock, or longer than one period when using SCLK, has occurred at the corresponding

CTSx input (MCR bit 12 controls selection of sampling clock). When these bits are set, the ACR can be programmed to generate an interrupt to the CPU32.

0= The CPU32 has read the IPCR. A read of the IPCR also clears bit 7 of the ISR.

CTSB, CTSA Current State

1 = The current state of the respective CTSx input is negated.

0= The current state of the respective CTSx input is asserted.

The information contained in these bits is latched and reflects the state of the input pins at the time that the IPCR is read.

7.4.1.11 AUXILIARY CONTROL REGISTER (ACR). The ACR selects which baud rate is used and controls the handshake of the transmitter/receiver. This register can only be written when the serial module is enabled.

ACR $714

1 0

I

BRG

I

0 o

I

0 o \

0

IIECB \IECA \

RESET:


BRG Baud Rate Generator Set Select

1 = Set 2 of the available baud rates is selected.

0= Set 1 of the available baud rates is selected. Refer to 7.4.1.6 CLOCK

SELECT REGISTER (CSR) for more information on the baud rates.

7-36


MOTOROLA

IECB, IECA Input Enable Control

1 = ISR bit 7 will be set and an interrupt output will be generated when the corresponding bit in the IPCR (COSB or COSA) is set by an external transition on the channel's CTSx input (if bit 7 of the interrupt enable register (IER) is set to enable interrupts).

0= Setting the corresponding bit in the IPCR has no effect on ISR bit 7.

7.4.1.12 INTERRUPT STATUS REGISTER (lSR). The ISR provides status for all potential interrupt sources. The contents of this register are masked by the IER.

If a flag in the ISR is set and the corresponding bit in IER is also set, the IRQx output is asserted. If the corresponding bit in the IER is cleared, the state of the bit in the ISR has no effect on the output. This register can only be read when the serial module is enabled.

NOTE

The IER does not mask reading of the ISR. True status is provided regardless of the contents of IER. The contents of ISR are cleared when the serial module is reset.

ISR $715

RESET:


COS Change of State

1 =A change of state has occurred at one of the CTSx inputs, and has been selected to cause an interrupt by programming bit 1 and/or bit 0 of the

ACR.

0= The CPU32 has read the IPCR.

DBB Delta Break B

1 = The channel B receiver has detected the beginning or end of a received break.

0= The CPU32 has issued a channel B reset break change interrupt command. Refer to 7.4.1.7 COMMAND REGISTER (CR) for more information on this command.

MOTOROLA


7-38

RxRDYB Channel B Receiver Ready or FIFO Full

The function of this bit is programmed by MR1 B bit 6.

1

=

If programmed as receiver ready, a character has been received in channel B and is waiting in the RB FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the

FIFO, and the transfer has caused the channel B FIFO to become full

(all three positions are occupied).

0= If programmed as receiver ready, the CPU32 has read the RB. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is "popped." If programmed as FIFO full, the CPU32 has read the RB. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO.

TxRDYB Channel B Transmitter Ready

This bit is the duplication of the TxRDY bit in SRB.

1

=

The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted.

0= The transmitter holding register was loaded by the CPU32. This bit is also cleared when the transmitter is disabled.

XTAL_RDY Serial Clocks Running

This bit is always read as a zero when the serial clock is running. Note that this bit cannot be enabled to generate an interrupt.

1

=

This bit is set at reset. See

MC68340/D, MC68340 Technical Summary,

for more information on the timing of reset and power-down.

0= This bit is cleared after the baud rate generator is stable. The CSR should not be accessed until this bit is zero.

DBA Delta Break A

1

=

The channel A receiver has detected the beginning or end of a received break.

0= The CPU32 has issued a channel A reset break change interrupt command. Refer to 7.4.1.7

REGISTER

(CR) for more information on this command.


RxRDYA Channel A Receiver Ready or FIFO Full

The function of this bit is programmed by MR1A bit 6.

1

=

If programmed as receiver ready, a character has been received in channel A and is waiting in the RB FIFO. If programmed as FIFO full, a character has been transferred from the receiver shift register to the

FIFO, and the transfer has caused the channel A FIFO to become full

(all three positions are occupied).

0= If programmed as receiver ready, the CPU32 has read the RB. After this read, if more characters are still in the FIFO, the bit is set again after the FIFO is IIpopped.

1I

If programmed as FIFO full, the CPU32 has read the RB. If a character is waiting in the receiver shift register because the FIFO is full, the bit will be set again when the waiting character is loaded into the FIFO.

TxRDYA Channel A Transmitter Ready

This bit is the duplication of the TxRDY bit in SRA.

1

=

The transmitter holding register is empty and ready to be loaded with a character. This bit is set when the character is transferred to the transmitter shift register. This bit is also set when the transmitter is first enabled. Characters loaded into the transmitter holding register while the transmitter is disabled are not transmitted.

0= The transmitter holding register was loaded by the CPU32. This bit is also cleared when the transmitter is disabled.

7.4.1.13

INTERRUPT ENABLE REGISTER

(lER). The IER selects the corresponding bits in the ISR that cause an interrupt output (lRQx). If one of the bits in the

ISR is set and the corresponding bit in the IER is also set, the IRQx output is asserted. If the corresponding bit in the IER is zero, the state of the bit in the

ISR has no effect on the IRQx output. The IER does not mask the reading of the ISR. Note that the XTAL_RDY bit cannot be enabled to generate an interrupt.

This register is equivalent to the interrupt mask register (IMR) in the MC68681.

This register can only be written when the serial module is enabled.

IER $715

7 6 5 4 2 1 0

I cos

I DBB IRxRDYBITXRDYBI

0

I DBA I RXRDYAITXRDYAI

RESET: o


MOTOROLA


cos -

Change of State

1

=

Enable interrupt

0= Disable interrupt

DBB Delta Break B

1

=

Enable interrupt


RxRDYB Channel B Receiver Ready or FIFO full

1

=

Enable interrupt

0=

Disable interrupt

TxRDYB Channel B Transmitter Ready

1

=

Enable interrupt


DBA Delta Break A

1

=

Enable interrupt


RxRDYA Channel A Receiver Ready or FIFO full

1

=

Enable interrupt

0=

Disable interrupt

TxRDYA Channel A Transmitter Ready

1

=

Enable interrupt


7.4.1.14

INPUT PORT

can only be read.

(lP).

The IP register enables the CTSx inputs. This register

IP $71D

I

0 o

RESET:

I

0

I

0 o

I

0

I eTSB

I eTSA

I u u


7-40


CTSB, CTSA Current State

1 = The current state of the respective CTSx input is negated.

0= The current state of the respective CTSx input is asserted.

The information contained in these bits is latched and reflects the state of the input pins at the time that the IP is read.

NOTE

These bits have the same function and value of the IPCR bits 1 and O.

7.4.1.15 OUTPUT PORT CONTROL REGISTER (OPCR). The OPCR individually configures each bit ofthe 8-bit parallel OP for general-purpose use or as an auxiliary function serving the communication channels. This register can only be written.

OPCR $71D


NOTE

OP bits 7,5,3, and 2 are not pinned out on the MC68340; thus changing bits 7, 5, 3, and 2 of this register has no effect.

OP6 Output Port 6/TxRDYA

1 = The TxRDYA pin functions as the transmitter-ready signal for channel

A. The signal reflects the complement of the value of bit 2 of the channel

A SR; thus, TxRDYA is a logic zero when the transmitter is ready.

0= The TxRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 6 of the OP.

OP4 Output Port 4/RxRDYA

1 =The RxRDYA pin functions as the receiver ready or FIFO-full signal for channel A (depending on the value of bit 6 of MR1A). The signal reflects the complement of the value of ISR bit 1; thus, RxRDYA is a logic zero when the receiver is ready.

0= The RxRDYA pin functions as a dedicated output. The signal reflects the complement of the value of bit 4 of the OP.


OP1 Output Port 1/RTSB

1 = The RTSB pin functions as the ready-to-send signal for channel B. The signal is asserted and negated according to the configuration programmed by MR1 B bit 7 for the receiver and MR2B bit 5 for the transmitter.

0= The RTSB pin functions as a dedicated output. The signal reflects the complement of the value of bit 1 of the OP.

OPO Output Port O/RTSA

1 = The RTSA pin functions as the ready-to-send signal for channel A. The signal is asserted and negated according to the configuration programmed by MR1A bit 7 for the receiver and MR2A bit 5 for the transmitter.

0= The RTSA pin functions as a dedicated output. The signal reflects the complement of the value of bit 0 of the OP.

7.4.1.16 OUTPUT PORT DATA REGISTER (OP). The OP contains the complements of the logic levels that are driven if any of the TxRDYA, RxRDYA, RTSB, and

RTSA outputs are configured as parallel outputs in the OPCR. The bits in this register are set by performing a bit set command (writing to offset $71 E) and are cleared by performing a bit reset command (writing to offset $71 F). This register can only be written when the serial module is enabled.

Bit Set

OP $71E

6 5 4 3 2 1 0

I

OP7

I

OP6

I

OP5

I

OP4

I

OP3

I

OP2

I

OP1

I

OPO

RESET:


NOTE

OP bits 7, 5, 3, and 2 are not pinned out on the MC68340; thus, changing these bits has no effect.

OP6, OP4, OP1, OPO Output Port Parallel Outputs

1 = These bits can be set by performing a bit set command (writing a one to the bit position(s) at this address).

0= These bits are not affected by writing a zero to this address.

7-42


MOTOROLA

Bit Reset

OP $71F

7 6 5 4 3 2 1 0

I

OP7

I

OP6

I

OP5

I

OP4

I

OP3

I

OP2

I

OP1

I

OPO

RESET:


NOTE

OP bits 7,5,3, and 2 are not pinned out on the MC68340; thus, changing these bits has no effect.

OP6, OP4, OP1, OPO Output Port Parallel Outputs

1

=

These bits can be cleared by performing a bit reset command (writing a one to the bit position(s) at this address). a

=

These bits are not affected by writing a zero to this address.

7.4.1.17 MODE REGISTER 2 (MR2). MR2 controls some of the serial module configuration. This register can be read or written at any time the serial module is enabled.

MR2A, MR2B

$720, $721

7 6 5 4 3 2 1 0

I

CM1

I

CMO

I

TxRTS

I

TxCTS

I

SB3

I

SB2

I

SB1

I

SBO

RESET:


CM1-CMO Channel Mode

These bits select a channel mode as listed in Table 7-10. See 7.3.3 Loop

Modes for more information on the individual modes.

Table 7-10. Channel Mode Bits

CM1 CMO

0 0 Normal

0

1

1

Mode

1 Automatic Echo

0 Local Loopback

1

Remote Loopback

MOTOROLA


7-43

7-44

TxRTS Transmitter Ready to Send

This bit controls the negation of the RTSA or RTSB signals. The output is normally asserted by setting OPO or OP1 and negated by clearing OPO or

OP1 (see 7.4.1.14 OUTPUT PORT DATA REGISTER (OP)).

1

=

In applications where the transmitter is disabled after transmission is complete, setting this bit causes the particular OP bit to be cleared automatically one bit time after the characters, if any, in the channel transmit shift register and the transmitter holding register are completely transmitted, including the programmed number of stop bits.

This feature is used to automatically terminate transmission of a message. If both the receiver and the transmitter in the same channel are programmed for RTS control, RTS control is disabled for both since this is an incorrect configuration. a

=

Clearing this bit has no effect on the transmitter RTSx.

TxCTS Clear to Send

1

=

The transmitter checks the state of the CTSx input each time it is ready to send a character. If CTSx is asserted, the character is transmitted. If

CTSx is' negated, the channel TxDx remains in the high state, and the transmission is delayed until CTSx is asserted. Changes in CTSx while a character is being transmitted do not affect transmission of that character. If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter. a

=

The CTSx has no effect on the transmitter.

SB3-SBO Stop-Bit Length Control

These bits select the length of the stop bit appended to the transmitted character as listed in Table 7-11. Stop-bit lengths of nine-sixteenth to two bits, in increments of one-sixteenth bit, are programmable for character lengths of six, seven, and eight bits. For a character length of five bits, one and one-sixteenth to two bits are programmable in increments of onesixteenth bit. In all cases, the receiver only checks for a high condition at the center of the first stop-bit position i.e., one bit time after the last data bit or after the parity bit, if parity is enabled.

If an external 1 x clock is used for the transmitter, MR2 bit 3

= a selects one stop bit, and MR2 bit 3

=

1 selects two stop bits for transmission.


Table 7-11. Stop-Bit Length Control Bits

1

1

1

1

0

0

0

1

SB3 SB2 SB1 SBO Length 6-8 Bits

0 0 0 0 0.563

0

0

0

0

0

1

1

0

0.625

0.688

0

0

0

1

1

1

1

1

0

0

1

1

1

0

1

0

1

0.750

0.813

0.875

0.938

1.000

0

0

0

0

1

0

0

1

1

0

1

0

1

1.563

1.625

1.688

1.750

1.813

1

1

1

1

1

1

0

0

1

1

0

1

0

1

1.875

1.938

2.000

Length 5 Bits

1.063

1.125

1.188

1.250

1.313

1.375

1.438

1.500

1.563

1.625

1.688

1.750

1.813

1.875

1.938

2.000

7.4.2

PROGRAMMING

The basic interface software required for operation of the serial module is shown in Figure 7-9. The routines are divided into three categories:

• Serial Module Initialization

• I/O Driver

• Interrupt Handling

MOTOROLA


7.4.2.1 SERIAL MODULE INITIALIZATION. The serial module initialization routines consist of SINIT and CHCHK. SINIT is called at system initialization time to check channel A and channel B operation. Before SINIT is called, the calling routine allocates two words on the system stack. Upon return to the calling routine, SINIT passes information on the system stack to reflect the status of the channels. If SINIT finds no errors in either channel A or channel B, the respective receivers and transmitters are enabled. The CHCHK routine performs the actual channel checks as called from the SINIT routine. When called, SINIT places the specified channel in the local loopback mode and checks for the following errors:

• Transmitter Never Ready

• Receiver Never Ready

• Parity Error

• Incorrect Character Received

7.4.2.2 1/0

DRIVER EXAMPLE. The

liD

driver routines consist of INCH, DUTCH, and POUTCH. INCH is the terminal input character routine and gets a character from the channel A receiver and places it in the lower byte of register

DO.

DUTCH is used to send the character in the lower byte of register

DO to the channel A transmitter. POUTCH sends the character in the lower byte of DO to the channel B transmitter.

7.4.2.3 INTERRUPT HANDLING. The interrupt handling routine consists of SIRO which is executed after the serial module generates an interrupt caused by a channel A change in break (beginning of a break). SIRO then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor.

7-46


MOTOROLA

INITIATE:

CHANNEL A

CHANNELS

INTERRUPTS

ENABLA

Figure 7-9. Serial Module Programming Flowchart (1 of 5)

MOTOROLA


7-47

7-48

PLACE CHANNEL IN

LOCAL LOOPBACK

MODE

ENABLE CHANNEL'S

TRANSMITIER CLEAR

CHANNEL

STATUS WORD

SET TRANSMITTER-

NEVER-READY FLAG

SET RECEIVER-

NEVER-READY FLAG



MOTOROLA

MOTOROLA

Figure 7-9. Serial Module Programming Flowchart (3 of 5)


7-49

REMOVE BREAK

CHARACTER FROM

RECEIVER FIFO

REPLACE RETURN

ADDRESS ON SYSTEM

STACK AND MONITOR

WARM START ADDRESS

7-50



MOTOROLA

N

SEND CHARACTER

IN DO TO CHANNEL A

TRANSMITTER

N

N

SEND CHARACTER

IN DO TO CHANNEL

B TRANSMITTER

N

SENDAUNE

FEED CHARACTER TO

CHANNEL A

TRANSMITTER

OUTCHR

N N

SEND AUNE

FEED CHARACTER TO

CHANNELB

TRANSMITTER

POUTCHR

/ 0 + - - - - - - - - - - '


MOTOROLA


7-51

7-52


MOTOROLA

SECTION 8

TIMER MODULES

Each MC68340 timer module contains a counter/timer (timer 1 and timer 2) as shown in Figure 8-1. Each timer interfaces directly to the CPU32 via an intermodule bus (1MB). Each timer consists of the following major areas:

• A General-Purpose CounterlTimer

• Internal Control Logic

• Interrupt Control Logic

TIMER 1

TIMER 1

TIN1

-

TOUT1

'romf

INTERRUPT

CONTROL

LOGIC

TIMER 2

TIMER 2

TIN2

-

TOUT2 roATE2

INTERRUPT

CONTROL

LOGIC

1MB

INTERFACE

1MB

INTERFACE

Figure 8-1. Simplified Block Diagram

8.1

MODULE OVERVIEW

Each timer module consists of the following functional features:

• Versatile General-Purpose Timer

• 8-Bit Prescaler/16-Bit Counter

• Timers Can Be Externally Cascaded for a Maximum Count Width of 48 Bits


8-1

• Programmable Timer Modes:

Event Counting

Period and Pulse-Width Measurement

Input Capture

Output Compare

Waveform Generation

Pulse Generation

• Seven Maskable Interrupt Conditions Based on Programmable Events

8.1.1 Timer and Counter Functions

The term IItimer" is used to reference either timer 1 or timer 2, since the two are functionally equivalent.

The timer can perform virtually any application traditionally assigned to timers and counters. The timer can be used to generate timed events that are independent of the timing errors to which real-time programmed microprocessors are susceptible for example, those of dynamic memory refreshing, DMA cycle steals, and interrupt servicing.

The timer has several functional areas: an 8-bit countdown prescaler, a 16-bit downcounter, timeout logic, compare logic, and clock selection logic. Figure

8-2 shows a block diagram of the timer module.

8.1.1.1 PRESCALER AND COUNTER. The counter can be driven directly by the selected clock or the prescaler output. Both the counter and prescaler are updated on the falling edge of the clock. During reset, the prescaler is set to $FF, and the counter is set to $0000. The counter is loaded with a programmed value on the first falling edge of the counter clock after the timer is enabled and again when a timeout occurs (counter reaches $0000). The prescaler and counter can be used as one 24-bit counter by enabling the prescaler and selecting the divide-by-256 prescaler output. Refer to 8.4 REGISTER DESCRIPTION for additional information on how to program the timer.

8.1.1.2 TIMEOUT DETECTION. Timeout is achieved when all 16 stages of the counter transition to zero, a counter value of $0000. Timeout is a defined counter event which triggers specific actions depending upon the programmed mode of operation. Refer to 8.3 OPERATING MODES for descriptions of the individual modes.

8-2


MOTOROLA

8.1.1.3 COMPARATOR. The comparator block compares the value in the 16-bit compare register (COM) with the output of the 16-bit counter. When an exact match is detected, bits in the status register (SR) are set to indicate this condition. When in the input capture/output compare mode, a match is a defined counter event that can affect the output of the timer (TOUT). Refer to 8.3.1

Input Capture/Output Compare for additional information on this mode.

8.1.1.4 CLOCK SELECTION LOGIC. The clock selection logic consists of two multiplexers that select the clocks applied to the prescaler and counter. The first multiplexer (labeled clock logic in Figure 8-2) selects between the clock input to the timer (TIN) or one-half the frequency of the system clock (CLKOUT). This output of the first multiplexer (called selected clock) is applied to both the

8-bit prescaler and the second multiplexer. The second multiplexer selects the clock for the 16-bit counter, which is either the selected clock or the 8-bit prescaler output.

TIMER

EXTERNAL

INTERFACE

, ••••••••••••••••••••••••••

iNi~eeUet.~~I$.l~e

••••••••••••••••••••••••••••. ,

, .•••••••••••••••••••••••••

§§@~§~~&i$ig~

••••.••••••••••••••••••••••••••• ,

, ••••••••••••••••••••••••••••••

·~jAfu$·.~~~.I§.t~~

•••••••••••••••••••••••••••••••••• ,

SELECTED

CLOCK

MOTOROLA

Figure 8-2. Timer Functional Diagram


8.1.2 Internal Control Logic

The timer receives operation commands on the

1MB and, in turn, issues appropriate operation signals to the internal timer control logic. This mechanism allows the timer registers to be accessed and programmed. Refer to 8.4 REG-

ISTER DESCRIPTION for additional information.

8.1.3 Interrupt Control Logic

Each timer has seven interrupt request outputs (IRQ7-IRQ1) provided to notify the CPU32 that an interrupt has occurred. The interrupts are described in 8.4

REGISTER DESCRIPTION. SR bits indicate all currently active interrupt conditions. The interrupt enable bits (IE) in the control register (CR) are programmable to mask any events that may cause an interrupt.

8.2 SIGNAL DEFINITIONS

This section contains a brief description ofthe timer interface signals (see Figure

8-3).

NOTE

The terms assertion and negation are used throughout this section to avoid confusion when dealing with a mixture of active-low and activehigh signals. The term assert or assertion indicates that a signal is active or true independent of the level represented by a high or low voltage. The term negate or negation indicates that a signal is inactive or false.

8.2.1 Timer Input (TIN)

This input can be programmed to be the clock that causes events to occur in the counter and prescaler. TIN is internally synchronized to the system clock to guarantee that a valid TIN level is recognized. Additionally, the high and low levels of TIN must each be stable for at least one system clock period plus the sum of the setup and hold times for TIN. Refer to MC68340/D,

MC68340 Technical Summary,



MOTOROLA

TIMER 1

EXTERNAL

INTERFACE

SIGNALS

INTERRUPT

CONTROL

TIMER 2

EXTERNAL

INTERFACE

SIGNALS

MOTOROLA

Figure 8-3. External and Internal Interface Signals


8-5

8.2.2 Timer Gate (TGATE)

This active-low input can be programmed to enable and disable the counter and prescaler. TGATE may also be programmed to be a simple input. For more information on the modes of operation, refer to 8.3 OPERATING MODES. To guarantee that the timer recognizes a valid level on TGATE, the signal is synchronized with the system clock. Additionally, the high and low levels of this input must each be stable for at least one system clock period plus the sum of the setup and hold times for TGATE. Refer to

MC683401D, MC68340 Technical

Summary,


8.2.3 Timer Output (TOUT)

This output drives the various output waveforms generated by the timer. The initial level and transitions can be programmed by the output control (OC) bits in the CR.

8.3 OPERATING MODES

The following paragraphs contain a detailed description of each timer operation mode and of the 1MB operation during accesses to the timer. Changing the mode of operation should only be attempted when the timer is in reset (the software reset (SWR) bit in the CR is cleared). Changing modes while the timer is running may produce unpredictable results.

8.3.1 Input Capture/Output Compare

This mode has the capability of capturing a counter value by holding the value in the counter register (CNTR). Additionally, this mode can provide compare information via TOUT to indicate when the counter has reached the compare value. This mode can be used for square-wave generation, pulse-width modulation, or periodic interrupt generation. This mode can be selected by programming the operation mode bits (MODE) in the CR to 000.

The timer is enabled when the counter prescaler enable (CPE) and SWR bits in the CR are set. Once enabled, the counter enable (ON) bit in the SR is set, and the next falling edge of the counter clock causes the counter to be loaded with the value in the preload 1 register (PREL 1).

The TGATE signal functions differently in this mode than it does in the other modes. TGATE does not enable or disable the counter/prescaler input clock; instead, it is used to disable shadowing. Normally, the counter is decremented


MOTOROLA

on the falling edge of the counter clock, and the CNTR is updated on the next rising edge of the system clock; thus, the CNTR shadows the actual value of the counter. The timer gate interrupt (TG) bit in the SR must be cleared for shadowing to occur. TGATE is used to set the TG bit and disable shadowing.

If the timing gate is enabled (TGE bit of the CR is set), the TG bit is set by the rising edge of TGATE. Shadowing is disabled until the TG bit is cleared by writing a one to its location in the SR. See Figure 8-4 for a depiction of this mode. If the timing gate is disabled (TGE bit is cleared), TGATE has no effect on the operation of the timer; thus the input capture function is inoperative.

At all times, the TGATE level bit (TGL) in the SR reflects the level ofthe TGATE signal.

COUNTER

CLOCK

COUNTER

COUNTER

REGISTER

TGATE 1

TOUT 2

1

1

1

1

0 1 0 8

8:

1

7

01 0 0

81 8

1

1

1 1

1

1

:

7

7

6

7 6

1

1

1

6 is 5

~

6 6 6

6

6: 3

2 2 1

1

4 4

3

3:

2 2 1

1

1

r--LJ:1

1

TGSET TGCLEARED

TIMEOUT

1

1

0 8

8

1

1

7 7

8 8 0 0 8 1

1

1

i t

TG~ET

1 r

TCSET

ENABLE TCSET

Operation Mode Bits In Control Register

B

000

Preload 1 Register = 8

Compare Register .. 7

TGE Bit of Status Register .. 1

1: TG Bit in Status Register Initially .. 0

2: Output Control Bits in Control Register .. 10

Figure 8-4. Input Capture/Output Compare Mode

Because it is not affected by TGATE, the counter continues to decrement on the falling edge of the counter clock and load from the PREL 1 at timeout, regardless of the value of TGATE.

When the counter counts down to the value contained in the COM, this condition is reflected by setting the timer compare (TC) and compare (COM) bits in the SR. TOUT responds as selected by the OC bits in the CR. The output level (OUT) bit in the SR reflects the value on TOUT. Shadowing does not affect this operation.

MOTOROLA


8-7

If the counter counts down to $0000, a timeout is detected, causing the SR timeout interrupt (TO) bit to be set and the SR COM bit to be cleared. On the next falling edge of the counter clock after the timeout is detected, the value in PREL 1 is again loaded into the counter. TOUT responds as selected by the

CR OC bits.

A square-wave generator can be implemented by programming the CR OC.bits to toggle mode. The value in the COM should be one-half the value in PREL 1 to cause an event to happen twice in the countdown.

This mode can be used as a pUlse-width modulator by programming the CR

OC bits to zero mode or one mode. The value in the PREL 1 specifies the frequency, and the COM determines the pulse width. The pulse widths can be changed by writing a new value to the COM.

Periodic interrupt generation can be accomplished by enabling the TO, TC, and/ or TG bits in the SR to generate interrupts by programming the IE bits of the

CR. When enabled, the programmed IRQx signal is asserted whenever the specified bits are set.

TOUT signal transitions can be controlled by writing new values into the COM.

Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may actually get compared to the counter value.

8.3.2 Square-Wave Generator

This mode can be used for generating both square-wave output and periodic interrupts. The square wave is generated by counting down from the value in the PREL 1 to timeout (counter value of $0000). TOUT changes state on each timeout as programmed. This mode can be selected by programming the CR

MODE bits to 001.

The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is programmed to control enabling and disabling the counter (TGE bit set in the CR), then asserting TGATE. When the timer is enabled, the ON bit in the

SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL 1 (N). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N to N

+

1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see MC68340/D, MC68340 Technical Summary.

8-8


MOTOROLA

TOUT behaves as a square wave when the OC bits of the CR are programmed for toggle mode. A timeout occurs every N

+

1 periods (allowing for the zero cycle), resulting in a change of state on TOUT (see Figure 8-5). The SR OUT bit reflects the level of TOUT. If this mode is used to generate periodic interrupts,

TOUT may be enabled if a square wave is also desired.

COUNTER

CLOCK

COUNTER

0

TOUT o

I

I

I

I

I

I

I

ENABLE

N: N+l

2

Operation Mode Bits in Control Register = 001

Preload 1 Register .. N a

3

Output Control Bits in Control Register - 01

I

10

I

2

I

:/

N+l

TIMEOUT

I

I 0

I

I

:\

TIMEOUT

Figure 8-5. Square-Wave Generator Mode

I

0

I

I

:~

TIMEOUT

If TGATE is negated when it is enabled to control the timer (TGE

=

1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated. The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again.

If TGATE is disabled (TGE

=

0), TGATE has no effect on the operation of the timer. In this case, the counter begins counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The TG bit of the SR cannot be set. At all times, TGL in the SR reflects the level of TGATE.

If the counter counts down to the value stored in the COM register, then the

COM and TC bits in the SR are set. The counter continues counting down to timeout. At this time, the SR TO bit is set, and the SR COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL 1 to be loaded back into the counter, and the counter begins counting down from this value.

The period of the square-wave generator can be changed dynamically by writing a new value into the PREL 1. Caution must be used because, if PREL 1 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL 1 value may actually get loaded into the counter at timeout.

MOTOROLA 8-9


Periodic interrupt generation can be accomplished by enabling the TO, Te, and/ or TG bits in the SR to generate interrupts by programming the CR IE bits.

When enabled, the programmed IRQx signal is asserted whenever the specified bits are set.

8.3.3 Variable Duty-Cycle Square-Wave Generator

In this mode, both the PREL 1 and PREL2 registers are used to generate a square wave with virtually any duty cycle. The square wave is generated by counting down from the value in the PREL 1 to timeout (count value $0000), then loading that value from PREL2 and again counting down to timeout. When this second timeout occurs, the value from PREL 1 is loaded into the counter, and the cycle repeats. TOUT can be programmed to change state with every timeout, thus generating a variable duty-cycle square wave. This mode can be selected by programming the MODE bits in the CR to 010.

The timer is enabled by setting both the SWR and CPE bits in the CR and, if

TGATE is enabled (CR TGE bit is set), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL 1 register (N1).

With each successive falling edge of the counter clock, the counter decrements.

The time between enabling the timer and the first timeout can range from N1 to N1

+

1 periods. When TGATE is used to enable the timer, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see the

MC68340/D, MC68340 Technical Summary.

If the counter counts down to the value stored in the COM register, the COM and timer compare interrupt (TC) bits in the SR are set. The counter continues counting down to timeout. At this time, the TO bit in the SR is set, and the

COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be loadedinto the counter, and the counter begins counting down from this value. Each successive timeout causes the counter to be loaded alternately with the values from PREL 1 and PREL2.

TOUT behaves as a variable duty-cycle square wave when the CR OC bits are programmed for toggle mode. The second timeout occurs after N2

+

1 periods

(allowing for the zero cycle), resulting in a change of state on TOUT. The third timeout occurs after N1

+

1 periods, resulting in a change of state on TOUT, and so on (see Figure 8-6). The OUT bit in the SR reflects the level of TOUT.


MOTOROLA

COUNTER

CLOCK

COUNTER 0

I o

I

4

I

10

I

TOUT _ _ _

I

--.;...~.;...-.

_ _ _

I

~fl'

ENABLE TIMEOUT

Operation Mode Bits in Control Register a

010

Preload 1 Register

=

N1 = 4

Preload 2 Register

:0

N2

=

2

Output Control Bits in Control Register

: 0

01

N2+1

I

:0

4

f\

~

TIMEOUT

: 0

I

1;l

TIMEOUT

Figure 8-6. Variable Duty-Cycle Square-Wave Generator Mode

N2+1

I

I

:0

I\.

TIMEOUT

If TGATE is negated when it is enabled (TGE

=

1), the prescaler and counter are disabled. Additionally, the TG bit of the SR is set, indicating that TGATE was negated. The ON bit of the SR is cleared, indicating that the timer is disabled.

If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again.

If TGATE is not enabled (TGE

=

0), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The

SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of

TGATE.

The duty cycle of the waveform generated on TOUT can be dynamically changed by writing new values into PREL 1 and/or PREL2. If PREL 1 or PREL2 is bei'ng accessed simultaneously by the counter logic and a CPU32 write, the old preload value may actually get loaded into the counter at timeout. If at timeout, the counting logic was accessing PREL2 and the CPU32 was writing to PREL 1

(or visa versa), there would be no unexpected results.

8.3.4 Variable-Width Single-Shot Pulse Generator

This mode is used to produce a one-time pulse that has a delay controlled by the value stored in PREL 1 and a duration controlled by the value stored in

PREL2. With TOUT programmed to change state, this sequence creates a single pulse of variable width. This mode can be selected by programming the CR

MODE bits to 011.

MOTOROLA


8-12

The timer is enabled by setting both the SWR and CPE bits in the CR and, if

TGATE is enabled (TGE bit in the CR is set), then asserting TGATE. When the timer is enabled, the ON bit in the SR is set. On the next falling edge of the counter clock, the counter is loaded with the value stored in the PREL 1 register

(N1). With each successive falling edge of the counter clock, the counter decrements. The time between enabling the timer and the first timeout can range from N1 to N1

+

1 periods. When TGATE is used to enable the counter, the enabling of the timer is asynchronous; however, if timing is carefully considered, the time to the first timeout can be known. For additional details on timing, see


If the counter counts down to the value stored in the COM, the COM and TC bits in the SR are set. The counter continues counting down to timeout. At this time, the SR TO bit is set and the SR COM bit is cleared. The next falling edge of the counter clock after timeout causes the value in PREL2 (N2) to be loaded into the counter, and the counter begins counting down from this value. After the second timeout, the selected clock is held high, disabling the prescaler and counter. Additionally, the SR ON and COM bits are cleared.

TOUT behaves as a variable-width pulse when the OC bits of the CR are programmed for toggle mode. TOUT is a logic zero between the time that the timer is enabled and the first timeout. When this event occurs, TOUT transitions to a logic one. The second timeout occurs after N2

+

1 periods (allowing for the zero cycle), resulting in TOUT returning to a logic zero (see Figure 8-7). The

OUT bit in the SR reflects the level of TOUT.

COUNTER

CLOCK

COUNTER

0

TOUT

1

1

I

I

1

1

1

0

1

ENABLE

Nt N1 +1

1

: 0

1

I

V

TIMEOUT

5

Operation Mode Bits in Control Register

=

011

Preload 1 Register

=

N 1

=

2

Preload 2 Register

=

N2

=

5

Output Control bits in Control Register

=

01

N2+1

1

: 0

I

:\

1 ' - - - - - - - -

TIMEOUT

Figure 8-7. Variable-Width Single-Shot Pulse Generator Mode


MOTOROLA

If TGATE is negated when it is enabled (TGE = 1), the prescaler and counter are disabled. Additionally, the SR TG bit is set, indicating that TGATE was negated.

The SR ON bit is cleared, indicating that the timer is disabled. If TGATE is reasserted, the timer is re-enabled and begins counting from the value attained when TGATE was negated. The ON bit is set again. If TGATE is not enabled

(TGE=O), TGATE has no effect on the operation of the timer. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the SWR and CPE bits in the CR are set. The SR TG bit cannot be set. At all times, the TGL bit in the SR reflects the level of TGATE.

The width of the pulse generated on TOUT (the value in PREL2) can be changed while the counter is counting down from the value in PREL 1. Caution must be used because, if PREL2 is accessed simultaneously by the counting logic and a CPU32 write, the old PREL2 value may actually get loaded into the counter at timeout.

8.3.5

Pulse-Width Measurement

This mode is used to count the clock cycles during a particular event (see Figure

8-8). The event is defined by the assertion and negation ofTGATE. When TGATE is asserted, the counter begins counting down from $FFFF. When TGATE is negated, the counter stops counting and holds the value at which it stopped.

Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODE bits to 100.

The timer is enabled by setting the SWR, CPE, and TGE bits in the CR. TGATE assertion starts the counter. When the timer is enabled, the SR ON bit is set.

On the next falling edge of the counter clock, the counter is loaded with the value $FFFF. With each successive falling edge of the counter clock, the counter decrements. PREL 1 and PREL2 are not used in this mode.

When TGATE is negated, the SR TG bit is set, the ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter. The TGL bit in the SR reflects the level of TGATE at all times.

If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This sets the SR TO, and the clears the COM bit. At timeout, the next falling edge of the counter clock causes the counter to reload with $FFFF.

TOUT transitions at timeout or is disabled as programmed by the OC bits of the CR. The OUT bit in the SR reflects the level on TOUT.


COUNTER

CLOCK

COUNTER 0 f: f f

TGATE f e d c bl

I

---rt

MEASURED PULSE f

I~---=~~~~----~I

ENABLE

1

I

START

COUNTING

1

I

STOP

COUNTING


=

100

TGE Bit of Control Register = 1 t t t

~t /~-

NO EFFECT f f b

Figure 8-8. Pulse-Width Measurement Mode

To determine the number of cycles counted, the value in the CNTR must be read, inverted, and incremented by 1 (the first count is $FFFF which, in effect, includes a count of zero). The counter counts in a true 2

16 fashion. For measuring pulses of even greater duration, the value in the prescaler output bits in the SR are readable and can be thought of as an extension ofthe least significant bits in the CNTR.

NOTE

Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated.

8.3.6 Period Measurement

This mode is used to count the period of a particular event. The event is defined by the assertion, negation, and subsequent reassertion ofTGATE. When TGATE is asserted, the counter begins counting down from $FFFF. The negation of

TGATE has no effect on the counter. When TGATE is reasserted, the counter stops counting and holds the value at which it stopped. Further assertions and negations of TGATE have no effect on the counter. This mode can be selected by programming the CR MODE bits to 101.

The timer is enabled by setting the SWR, CPE, and the TGE bits in the CR. The assertion of TGATE starts the counter. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL 1 and PREL2 registers are not used in this mode.

8-14


The first negation of TGATE is ignored, but on the second assertion of TGATE, the SR TG bit is set, the SR ON bit is negated, and the prescaler and counter are disabled. Subsequent transitions on TGATE do not re-enable the counter.

See Figure 8-9 for a depiction of this mode. The TGL in the SR reflects the level of TGATE at all times.

COUNTER

CLOCK

I

I

COUNTER 0 :

:

: e f f

~ c f : f :

~ a

! : ------------------------

f

~ f

TGATE

~f-I

___

ENABLEl <E----PERIOD MEASUREO-----'l>o t~1

__

~

/ c~J~~1G COtW~NG

NO EFFECT

I


=

101

TGE Bit of Control Register

=

1

Figure 8-9. Period Measurement Mode

If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This sets the SR TO bit, and clears the SR COM bit. At timeout, the next falling edge of the counter clock reloads the counter with $FFFF. TOUT transitions at timeout or is disabled as programmed by the OC bits of theCR, and the OUT bit in the SR reflects the level on TOUT.


16 fashion. For measuring pulses of even greater duration, the value in the PO bits in the SR are readable and can be thought of as an extension of the least significant bits in the CNTR.

NOTE

Once the timer has been enabled, do not clear the SR TG bit until the pulse has been measured and TGATE has been negated.

MOTOROLA


8.3.7 Event Count

This mode is used to count events by interpreting the falling edges the counter clock as events (see Figure 8-10). These events may be external or internal to the chip for example, counting the number of system clock cycles required to execute a sequence of instructions. As another example, by connecting AS to TIN, the number of bus cycles to complete a sequence of instructions could be counted. This mode can be selected by programming the CR MODE bits to

110.

COUNTER

CLOCK

COUNTER

TGATE

1

I

I

0

I

I

I

I

I

I

I

I

I

!

I

ENABLE e f f f d c

Operation Mode Bits In Control Register

=

110

1: TGE Bit of the Control Register Set f f f b

\

0

0

0

2

0:

0 1

0

1

11

I

I

I

I

TGBITSET

0

0

0

1

0

0

0

1

I

0

10

0

:0

0

10

1

:0

J

I

TIMEOUT

TO BIT SET e

Figure 8-10. Event Count Mode

The timer is enabled by setting the SWR and CPE bits in the CR and, if TGATE is enabled (TGE bit of the CR is set), then asserting TGATE. When the timer is enabled, the SR ON bit is set. On the next falling edge of the counter clock, the counter is loaded with the value of $FFFF. With each successive falling edge of the counter clock, the counter decrements. The PREL 1 and PREL2 registers are not used in this mode.

If TGATE is not enabled (CR TGE bit is cleared), then TGATE does not start or stop the timer or affect the TG bit of the SR. In this case, the counter would begin counting on the falling edge of the counter clock immediately after the

SWR and CPE bits in the CR are set.

If TGATE is enabled (CR TGE bit is set), then the assertion of TGATE starts the counter. The negation of TGATE disables the counter, sets the SR TG bit, and clears the ON bit in the SR. If TGATE is reasserted, the timer resumes counting from where it was stopped, and the ON bit is set again. Further assertions and negations of TGATE have the same effect. The TGL bit in the SR reflects the level of TGATE at all times.

MOTOROLA


If the counter counts down to the value stored in the COM register, the COM and TC bits in the SR are set. If the counter counts down to $0000, a timeout is detected. This event sets the TO in the SR and clears the COM bit. At timeout, the next falling edge of the counter clock reloads the counter with $FFFF. TOUT transitions at timeout or is disabled as programmed by the CR DC bits. The

SR OUT bit reflects the level on TOUT.


16 fashion. For measuring pulses of even greater duration, the value in the PO bits in the SR are readable, and can be thought of as an extension of the least significant bits in the CNTR.

8.3.8 Timer Bypass

In this mode, the counter and prescaler cannot be enabled. However TGATE and TOUT can be used for

1/0.

This mode can be selected by programming the CR MODE bits to 111.

TGATE can be used as a simple input port when the CR is configured as follows:

CR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I

SWR I IE2 lEI lEO I TGE I PSE I CPE I ClK I POT2 I pon I POTO I MODE21 MODEllMODEOI OCI loco

TGATE AS A SIMPLE INPUT:

X X X x x x x x x x x

X

=

Don't care

When TGATE is asserted, the SR ON bit is set. When TGATE is negated, the

ON bit is cleared. The value of the TGL bit in the SR reflects the level of TGATE.

TGATE can also be used as an input port that generates interrupts on a lowto-high transition of TGATE when the CR is configured as follows:

CR

15 14 13 12 11 10 9 8 7 6 5

I

SWR I IE2 lEI lEO

I

TGE

I

PSE

I

CPE

I

ClK

I

POT2

I

POTI

I

POTO

I

4

TGATE AS A INPUT/INTERRUPT:

X X 1 X x x x x x

3 2 1 0 x x

When TGATE is negated, the SR TG bit is set, and the programmed IRQx signal is asserted to the CPU32 . .The TG bit can only be cleared by writing a one to this bit position. The value of the SR TGL bit reflects the level of TGATE.

MOTOROLA


Additionally, TOUT can be used as a simple output port when the CR is configured as follows:

CR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I

SWR I IE2 lEI lEO I TGE IpSE

I

CPE

I

ClK I P0T21 POTI I POTO IMODE21MODE11MODEOI OCI loco

I

TGATE AS A SIMPLE OUTPUT o

X x x x x x x x x

OCI OCO

SWR must be a zero to change the valu'e of TOUT. Changing the value of the

CR OC bits determines the level of TOUT as shown in Table 8-1.

Table 8-1. OC Encoding

OC1 OCD

0 0

0

1

1

1

0

1

TOUT

Hi-Z

0

0

1

A read of the SR while in this mode always shows the TO, TC, and COM bits cleared, and the PO bits as $FF. The SR OUT bit always indicates the level on the TOUT pin.

8.3.9 Bus Operation

The following paragraphs describe the operation of the 1MB during read, write, and interrupt acknowledge cycles to the timer.

8.3.9.1 READ CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word reads, and

16 bits of valid data are returned. Read cycles from reserved registers return logic zero.

8.3.9.2 WRITE CYCLES. The timer is accessed with no wait states. The timer responds to byte, word, and long-word writes. Write cycles to read-only registers and bits as well as reserved registers complete in a normal manner without exception processing; however, the data is ignored.


MOTOROLA

8.3.9.3 INTERRUPT ACKNOWLEDGE CYCLES.

The timer is capable of arbitrating for interrupt servicing and supplying the interrupt vector when it has successfully won arbitration. The vector number must be provided if interrupt servicing is necessary; thus, the interrupt register OR) must be initialized. If the IR is not initialized, a spurious interrupt exception will be taken if interrupt servicing is necessary.

8.4 REGISTER DESCRIPTION

The following paragraphs contain a detailed description of each register and its specific function. The operation of the timer is controlled by writing control words into the appropriate registers. Timer registers and their associated addresses are listed in Figure 8-11. For more information about a particular register, refer to the individual register description. The ADDR column indicates the offset of the register from the base address of the timer. An FC column designation of S indicates that register access is restricted to supervisor only.

A designation of S/U indicates that access is governed by the SUPV bit in the module configuration register (MCR).

TIMER 1

$600

$602

$604

$606

$608

$60A

$60C

$60E

$610

$612-$63F

TIMER 2

$640

$642

$644

$646

$648

$64A

$64C

$60E

$650

$652-$67F

Fe

S

S/U

S/U

S/U

S/U

S/U

S

S

S/U

S/U

15

MODULE CONFIGURATION REGISTER (MCR)

RESERVED

INTERRUPT REGISTER (lR)

CONTROL REGISTER (CR)

STATUS/PRESCALER REGISTER (SR)

COUNTER REGISTER (CNTR)

PRELOAD 1 REGISTER (PREL 1)

PRELOAD 2 REGISTER (PREL2)

COMPARE REGISTER (COM)

RESERVED

Figure 8-11. Programming Model

In the registers discussed in the following paragraphs, the numbers in the upper right-hand corner indicate the offset of the register from the base address specified by the base address register in the SIM. The first number is the offset for timer 1; the second number is the offset for timer 2. The numbers on the top line of the register represent the bit position in the register. The second line contains the mnemonic for the bit. The value of these bits after reset is shown below the register. The access privilege is shown in the lower righthand corner.

MOTOROLA


8.4.1 Module Configuration Register (MCR)

The MCR controls the timer configuration. The register can be either read or written when in supervisor state.

MCR

15 14 13 12 11 10

I

STP I FRZI I FRZO I 0 I 0 I 0 I 0 I 0 I sUPV I 0 I 0

RESET: o

3 2

$600,$640

1 0 o IlARB31lARB21lARBl IIARBo I

Supervisor Only

STP Stop Mode

1

=

Stops all clocks within the timer except for the clock from the 1MB. The clocks are stopped on the low phase ofthe clock and will remain stopped until this bit is cleared. The clock from the 1MB remains active to allow the CPU32 to access the MCR. Accesses to other timer registers produce a bus error while in stop mode. The timer should be disabled (in a known state) prior to setting the STP bit; otherwise, unpredictable results may occur.

0= The timer operates in normal mode.

FRZ1,FRZO Freeze

These bits determine the action taken when the FREEZE signal is asserted on the 1MB. Table 8-2 lists the action taken for each bit combination.

Table 8-2. FRZ Encoding

FRZ1 FRZO

0 0

ACTION

Ignore FREEZE

0

1

1

1

Reserved (FREEZE ignored)

0

Execution Freeze

1

Execution Freeze


1

=

The timer registers defined as supervisor/user reside in supervisor data space and are only accessible from supervisor programs.

0= The timer registers defined as supervisor/user reside in user data space and are accessible from either supervisor or user programs.

The value of this bit has no effect on registers permanently defined as supervisor-only access.

8-20


MOTOROLA

IARB3-IARBO Interrupt Arbitration Bits

Each module that generates interrupts has an IARB field. The value of the

IARB field allows arbitration during an interrupt acknowledge (lACK) cycle among modules that simultaneously generate the same interrupt level. No two modules can share the same IARB value. (Timer 1 and timer 2 should be programmed with different values if both are used.) The reset value of

IARB is $0, which prevents this module from arbitrating during the lACK cycle. The system software should initialize the IARB field to a value from

$F (highest priority) to $1 (lowest priority).

8.4.2 Interrupt

Regis~er

(tR)

The IR contains the priority level for the timer interrupt request and the 8-bit vector number of the interrupt. The register can be read or written to at any time while in supervisor mode when the timer is enabled (STP bit in the MCR

=

0).

IR $604,$644

15 14 13 12 11 10 7 6 5 4 3 2 1 0

I

0 0

I

0

I

0

I

0

I

IL2

I

III ILO

I

IVR7

I

IVR6

I

IVR5

I

IVR4

I

IVR3

I

IVR2

I

IVRl

I

IVRO

I

RESET: o

Supervisor Only

IL2-ILO Interrupt Level Bits

Each module that can generate interrupts has an interrupt level field. The priority level encoded in these bits is sent to the CPU32 on the appropriate

IRQx signal. The CPU32 uses this value to determine servicing priority. See

SECTION 5 CPU32 for more information.

IVR7-IVRO Interrupt Vector Bits

Each module that can generate interrupts has an interrupt vector register

(IVR). This 8-bit number indicates the offset from the base of the vector table where the address of the exception handler for the specified interrupt is located. The IVR is reset to $OF, which indicates an uninitialized interrupt condition. See SECTION 5 CPU32 for more information.

8.4.3 Control Register (CR)

The CR controls the operation of the timer. The register can be always read or written when the timer is enabled (STP bit in the MCR

=

0). Writing to the CR is discouraged when the timer is in enabled (SWR bit

=

1); however it is allowed so that the programmer can have total control of timer operation.

MOTOROLA


8-22

NOTE

Changing the mode of operation while the timer is running may produce unpredictable results.

CR

$606, $646

15 14 13 12 11 10

9 8 7 6

5 4

3

2 1 0

I

SWR I IE2

IEl lEO I TGE I· PSE I CPE I ClK I POT2 I POTl I POTO I MODE21 MODEllMODEOI OCl loco

RESET:

0

Supervisor/User

SWR Softwa re Reset

1 = Removes the software reset.

0= A sotcware reset is performed by first clearing this bit and then clearing the TC, TG, and TO bits in the SR. The prescaler is loaded with $Ff, the counter is set to $0000, and the SR COM bit is cleared. When this bit is zero, the timer is disabled.

IE2-IEO Interrupt Enable

These bits determine which sources of interrupts, TO, TG, and TC, are enabled to generate an interrupt request to the CPU32. Table 8-3 lists which interrupts are enabled for all bit combinations.

IE2

0

0

0

0

1

1

1

1

1

0

0

1

1

IE1

0

0

1

Table 8-3. IE Encoding lEO Enabled Interrupts

0 Polling Mode (No Interrupts Enabled)

1

TC Enabled

0 TG Enabled

1

TG and TC Enabled

0

TO Enabled

1

TO and TC Enabled

0

TO and TG Enabled

1

TO, TG, and TC Enabled

TGE Timing Gate Enable

1 =The TGATE signal is enabled to control the enabling and disabling of the prescaler and counter, except in the input capture/output compare mode (see 8.3.1 Input Capture/Output Compare).

O=The TGATE signal has no effect on timer operation.


PSE Prescaler Select Enable

This bit selects which clock is used for the counter clock.

1

=

The counter is decremented by the prescaler output tap as selected by the POT field in the CR.

0= The counter is decremented by the selected clock.

The prescaler continues to decrement regardless of how PSE is set.

CPE Counter Prescaler Enable

1

=

The selected clock is enabled. If the TGE bit is set, then TGATE must also be asserted (except in the input capture/output compare mode).

0= The selected clock is held high, halting the prescaler and counter.

ClK Clock

1

=

The selected clock is taken from the TIN input.

0= The selected clock is one-half the system clock's frequency.

The TOUT of one timer can be fed externally into the TIN input of the other timer, resulting in a 32-bit counter if the prescalers are not used and a 48bit counter if they are used.

POT2-POTO Prescaler Output Tap

If PSE is set, these bits encode which of the prescaler's output taps act as the counter clock. A division of the selected clock is applied to the counter as listed in Table 8-4.

Table 8-4. POT Encoding

POT2 POT1 POTO

1

1

1

0

0

0

1

0

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

Division of

Selected Clock

Divide by 2

Divide by 4

Divide by 8

Divide by

16

Divide by

32

Divide by

64

Divide by

128

Divide by

256

MODE2-MODEO Operation Mode

These bits select one of the eight modes of operation for the timer as listed in Table 8-5. Refer to 8.3 OPERATING MODES for more information on the individual modes.


8-24

Table 8-5. MODE Encoding

MODE2 MODE1 MODEO

0

0

0

OPERATION MODE

Input Capture/Output Compare

0

0

0

1

1

0

Square-Wave Generator

Variable Duty-Cycle Square-Wave Generator

0

1

1

1

1

1

0

0

1

1

1

0

1

0

1

Variable-Width Single-Shot Pulse Generator

Pulse-Width Measurement

Period Measurement

Event Count

Timer Bypass (Simple Test Model

OC1-0CO Output Control

These bits select the conditions under which TOUT changes (see Table 8-6).

These bits may have a different effect when in the input capture/output compare mode. Caution should be used when modifying the OC bits near timer events.

Table 8-6. OC Encoding

OC1

0

0

1

1 oeo

TOUT MODE

0 Disabled

1 Toggle Mode

0 Zero Mode

1 One Mode

Disabled TOUT is disabled and three-stated.

Toggle Mode If the timer is disabled (SWR

=

0) when this encoding is programmed, TOUT is immediately set to zero. If the timer is enabled

(SWR

=

1), timeout events (counter reaches

$0000) toggle TOUT. In the input capture/output compare mode, TOUT is immediately set to zero if the timer is disabled (SWR

=

0).

If the timer is enabled (SWR

=

1), timer compare events toggle TOUT. (Timer compare events occur when the counter reaches the value stored in the COM.)

Zero Mode If the timer is disabled (SWR

=

0) when this encoding is programmed, TOUT is immediately set to zero. If the timer is enabled (SWR

=

1),

TOUT will be set to zero at the next

~imeout.

In the input capture/output compare mode, TOUT is immediately set to zero if the timer is disabled


MOTOROLA

(SWR

=

0). If the timer is enabled (SWR

=

1), TOUT will be set to zero at timeouts and set to one at timer compare events. If the COM is $0000, TOUT will be set to zero at the timeout/timer compare event.

One Mode If the timer is disabled (SWR

=

0) when this encoding is programmed, TOUT is immediately set to one. If the timer is enabled (SWR =

1),

TOUT will be set to one at the next timeout. In the input capture/output compare mode, TOUT is immediately set to one if the timer is disabled

(SWR

=

0). If the timer is enabled (SWR

=

1), TOUT will be set to one at timeouts and set to zero at timer compare events. If the COM is $0000, TOUT will be set to one at the timeout/timer compare event.

8.4.4

Status Register (SR)

The SR contains timer status information as well as the state of the prescaler.

This register is updated on the rising edge of the system clock when a read of its location is not in progress, allowing the most current information to be contained in this register. The register can be read, and the TO, TG, and TC bits can be written when the timer is enabled

(MCR STP bit

=

0).

SR $608,$648

15 14 13 12 11 10 9 8 J 6 5 4 3 2 1 0

I

IRQ

I

TO TG TC

I

TGL

I

ON lOUT

I

COM

I

POJ

I

POG

I

P05

I

P04

I

P03

I

P02

I

POI

I

POO

I

RESET (TGATE NEGATED): o

0 0

RESET (TGATE ASSERTED): o

0 0

0

0

Supervisor/User

Interrupt Request

The positioning of this bit in the most significant location in this register allows it it be conditionally tested as if it were a signed binary integer.

1

=

An interrupt condition has occurred. This bit is the logical OR of the enabled TO, TG, and TC interrupt bits.

0= The bit(s) that caused the interrupt condition has been cleared. If an

IRQx signal has been asserted, it is negated when this bit is cleared.


8-25

8-26

TO Timeout Interrupt

1 = The counter has transitioned from $0001 to $0000, and the counter has rolled over. This bit does not affect the programmed IRQx signal if the

IE2 bit in the CR is cleared.

0= This bit is cleared by the timer whenever the RESET signal is asserted on the 1MB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR cleared).

TG Timer Gate Interrupt

1 = This bit is set whenever the CR TGE bit is set and the TGATE signal transitions in the manner to which the particular mode of operation responds. Refer to 8.3 OPERATING MODES for more details. This bit does not affect the programmed IRQx signal if the IE1 bit in the CR is cleared.

0= This bit is cleared by the timer whenever the RESET signal is ass,erted on the 1MB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR clea red).

TC Timer Compare Interrupt

1 = This bit is set when the counter transitions (off a clock/event falling edge) to the value in the COM. This bit does not affect the programmed

IRQx signal if the lEO bit in the CR is cleared.

0= This bit is cleared by the timer whenever the RESET signal is asserted on the 1MB, regardless of the mode of operation. This bit may also be cleared by writing a one to it. Writing a zero to this bit does not alter its contents. This bit is not affected by disabling the timer (SWR cleared).

TGL TGATE Level

1 = The TGATE signal is negated.

O=The TGATE signal is asserted.

ON Counter Enabled

1 = This bit is set whenever the SWR and CPE bits are set in the CR. If the

CR TGE bit is set, TGATE must also be asserted (except in the input capture/output compare mode), since this signal then controls the enabling and disabling of the counter. If all these conditions are met, the counter is enabled and begins counting down.

0= The counter is not enabled and does not begin counting down.

OUT Output Level

1 = TOUT is a logic one.

0= TOUT is a logic zero, or the pin is three-stated.


COM Compare Bit

This bit is used to indicate when the counter output value is at or between the value in the COM and $0000 (timeout), inclusive.

1

=

This bit is set when the counter output equals the value in the COM. a

= This bit is cleared when a timeout occurs, the COM register is accessed

(read or write), the timer is reset with the SWR bit, or the RESET signal is asserted on the 1MB. This bit is cleared regardless of the state of the

TC bit.

This bit can be used to indicate when a write to the PREL 1 or PREL2 registers will not cause a problem during a counter reload at timeout. To ensure that the write to the PREL register is recognized at timeout, the latency between the read of the COM bit and the write to the PREL register must be taken into account.

P07-POO Prescaler Output

These bits show the levels on each of the eight output taps of the prescaler.

These values are updated every time that the system clock goes high and a read cycle of this byte in the SR is not in progress.

8.4.5 Counter Register (CNTR)

The CNTR reflects the value of the counter. This value can be reliably read at any time since it is updated on every rising edge of the system clock (except in the input capture/output compare mode) when a read of the register is not in progress. This read-only register can be read when the timer is enabled (STP bit of the MCR

=

0).

CNTR $60A, $64A

15 14 13 12 11 10 9 B 7 6 5 4 3 2 1 0

I

CNTl51 CNT14

I

CNTl31 CNTl21 CNTll

I

CNTlO

I

CNT9

I

CNTB

I

CNT7

I

CNT6

I

CNT5

I

CNT4

I

CNT31 CNT21 CNTl

I

CNTO

I

RESET: o

Supervisor/User

All 24 bits of the prescaler and the counter may be obtained by one long-word read at the address of the SR, since the CNTR is contiguous to it. Any changes in the prescaler value due to the two cycles necessary to perform a long-word read should be considered. If this latency presents a problem, the TGATE signal may be used to disable the decrement function while the reads are occurring.


8-27

8.4.6 Preload 1 Register (PREL 1)

The PREL 1 stores a value that is loaded into the counter in some modes of operation. This value is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. This register can be be read and written when the timer is enabled (STP bit of the MCR

=

0). However, a write to this register must be completed before timeout for the new value to be reliably loaded into the counter.

PREL1 $60C,$64C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I

PRl-151 PRl-141 PRl-13 I PRI-121 PRI-llI PR1-1O I PRl-91 PRl-81 PRl-71 PRl-51 PRl-51 PRl-41 PRl-31 PRl-21 PR1-l I PR1-0 I

RESET:

Supervisor/User

For some modes of operation, this register is also used to reload the counter one falling clock edge after a timeout occurs. Refer to 8.3

OPERATING MODES

for more information on the individual modes.

8.4.7 Preload 2 Register (PREL2)

PREL2 is used in addition to PREL 1 in the variable duty-cycle square-wave generator and variable-width single-shot pulse generator modes. When in either of these modes, the value in PREL 1 is loaded into the counter on the first falling edge of the counter clock after the counter is enabled. After timeout, the value in PREL2 is loaded into the counter. This register can be be read and written when the timer is enabled (STP bit in the MCR

=

0). However, a write to this register must be completed before timeout for the new value to be reliably loaded into the counter.

PREL2

$60E,$64E

15 14 13 12 11 10 9 8 7 5 5 4 3 2 1 0

I

PR2-151 PR2-14I PR2-13 I PR2-121 PR2-11 I PR2-10 I PR2-9 I PR2-8 I PR2-7 I PR2-5 I PR2-5 I PR2-4 I PR2-3 I PR2-21 PR2-1 I PR2-0 I

RESET:

1

Supervisor/User

8-28


MOTOROLA

8.4.8 Compare Register (COM)

The COM can be used in any mode. When the 16-bit counter reaches the value in the COM, the TC and COM bits in the SR are set. In the input capture/output compare mode, a compare event can be programmed to set, clear, or toggle

TOUT. The register can be be read and written when the timer is enabled (STP bit in the MCR

=

0).

COM $610, $650

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I

COM151 COM141 COM131 COM121 COMll

I

COMlO

I

COM91 COMB

I

COM71 COM61 COM51 COM41 COM31 COM21 COM1

I

COMO

I

RESET: o

Supervisor/User

The COM can be used to produce an interrupt when the SR TC bit has been enabled to produce an interrupt and the counter counts down to a preselected value. The COM can also be used to indicate that the timer is approaching timeout.

Caution must be exercised when accessing the COM. If it were to be accessed simultaneously by the compare logic and by a write, the old compare value may get compared to the counter value.

MOTOROLA


8-29

8-30


MOTOROLA

SECTION 9

IEEE 1149.1 TEST ACCESS PORT

The MC68340 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan

Architecture.

Problems associated with testing high-density circuit boards have led to development of this proposed standard under the sponsorship of the

Test Technology Committee of IEEE and the Joint Test Action Group (JTAG).

The MC68340 implementation supports circuit-board test strategies based on this standard.

The test logic includes a test access port (TAP) consisting of four dedicated signal pins, a 16-state controller, and two test data registers. A boundary scan register links all device signal pins into a single shift register. The test logic, implemented utilizing static logic design, is independent of the device system logic. The MC68340 implementation provides the following capabilities: a. Perform boundary scan operations to test circuit-board electrical continuity b. Bypass the MC68340 for a given circuit-board test by effectively reducing the boundary scan register to a single cell c. Sample the MC68340 system pins during operation and transparently shift out the result in the boundary scan register d. Disable the output drive to pins during circuit-board testing

NOTE

Certain precautions must be observed to ensure that the IEEE 1149.1 test logic does not interfere with nontest operation. See 9.4 NON·IEEE

1149.1 OPERATION for details.

9.1 OVERVIEW

This section, which includes aspects of the IEEE 1149.1 implementation that are specific to the MC68340, is intended to be used with the supporting IEEE

1149.1 document. The discussion includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the MC68340 implementation. For internal details and applications of the standard, refer to the IEEE 1149.1 document.


An overview of the MC68340 implementation of IEEE 1149.1 is shown in Figure

9-1. The MC68340 implementation includes a 3-bit instruction register and two test registers, a 1-bit bypass register and a 133-bit boundary scan register. This implementation includes a dedicated TAP consisting of the following signals:

TCK a test clock input to synchronize the test logic

TMS a test mode select input (with an internal pullup resistor) that is sampled on the rising edge of TCK to sequence the test controller's state machine

TDI a test data input (with an internal pullup resistor) that is sampled on the rising edge of TCK

TOO a three-stateable test data output that is actively driven in the shift-

IR and shift-DR controller states. TOO changes on the falling edge of TCK.

TEST DATA REGISTERS

TOI

3-BIT INSTRUCTION REGISTER

TMS

TCK

TAP

CTLR

1 - - - - - - - - - - - - - - - - - '

M

U x

TOO

Figure 9-1. Test Logic Block Diagram

9.2

INSTRUCTION REGISTER

The MC68340 IEEE 1149.1 implementation includes the three mandatory public instructions (BYPASS, SAMPLE/PRELOAD, and EXTEST) but does not support any of the optional public instructions defined by IEEE 1149.1. One additional

9-2


public instruction (HI-Z) provides the capability for disabling all device output drivers. The MC68340 includes a 3-bit instruction register without parity consisting of a shift register with three parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state.

The three bits are used to decode the four unique instructions shown in Table

9-1.

The parallel output of the instruction register is reset to all ones in the testlogic-reset controller state. Note that this preset state is equivalent to the BY-

PASS instruction.

Table 9-1.

Instructions

Code

B2 B1 BO

Instruction

0

0

0

0

0

1

EXTEST

SAMPLE/PRELOAD

X

1

X BYPASS

1

1

0

0

0

HI-Z

1

BYPASS

During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the 2-bit binary value into the two least significant bits and the loss-of-crystal (LOC) status signal into bit 2. The parallel outputs, however, remain unchanged by this action since an update-IR signal is required to modify them.

The LOC status bit of the instruction register indicates whether an internal clock is detected when operating with a crystal clock source. The LOC bit is clear when a clock is detected and set when it is not. The LOC bit is always clear when an external clock is used. The LOC bit can be used to detect faulty connectivity when a crystal is used to clock the device.

9.2.1

EXTEST (000)

The external test (EXTEST) instruction selects the 133-bit boundary scan register, including cells for all device signal and clock pins and associated control signals. The XTAL, X2, and XFC pins are associated with analog signals and are not included in the boundary scan register. EXTEST also asserts internal reset for the MC68340 system logic to force a predictable benign internal state while performing external boundary scan operations.


9-4

By using the TAP, the register is capable of a) scanning user-defined values into the output buffers, b) capturing values presented to input pins, c) controlling the direction of bidirectional pins, and d) controlling the output drive of three-stateable output pins.

All MC68340 bidirectional pins, exceptthe open-drain

1/0

pins (DONE1, DONE2,

HALT, and RESET), have a single register bit in the boundary scan register for pin data. All bidirectional pins, except

HALf and

RESET, have an associated control bit in the boundary scan register. DONE1 and DONE2 have two control bits in the boundary scan register: one for on (logic zero), and one for off (high impedance). To ensure proper operation, these open-drain pins require external pullups. Twenty-four bits in the boundary scan register define the output enable signal for associated groups of bidirectional and three-stateable pins.

Boundary scan bit definitions are shown in Table 9-2. The first column in Table

9-2 defines the bit's ordinal position in the boundary scan register. The shift register cell nearest TOO (i.e., first to be shifted out) is defined as bit zero; the last bit to be shifted out is 132.

The second column references one of the five MC68340 cell types depicted in

Figures 9-2-9-6, which describe the cell structure for that bit.

The third column lists the pin name for all pin-related cells or defines the name of bidirectional control register bits. The 24 control bits and their bit positions are as follows:

1. tout2.ctl (29)

2. irq7.ctl (52)

3. irq6.ctl (54)

4. irq5.ctl (56)

5. cs3.ctl

6. irq3.ctl (60)

7. cs2.ctl (62)

8. cs1.ctl

9. csO.ctl

10. dma.ctl

11. ab.ctl

12. berr.ctl

(58)

(64)

(66)

(83)

(84)

(85)

13. db.ctl (86)

14. ab24.ctl (88)

15. ab25.ctl (90)

16. ab26.ctl (92)

17. ab27.ctl (94)

18. ab28.ctl (96)

19. ab29.ctl (98)

20. ab30.ctl (100)

21. ab31.ctl (102)

22. pbO.ctl (123)

23. ifetch.ctl (126)

24. tout1.ctl (131)

The active level of the control bits (i.e., output driver on) is defined by the last digit of the cell type listed for each control bit. For example, the active-high level for tout2.ctl (bit 29) is logic one since the cell type is 10.CtI1. The active


MOTOROLA

level for irq7.ctl (bit 52) is logic zero since the cell type is 10.CtIO. 10.Ct10 (see

Figure 9-5) differs from 10.Ct11 (see Figure 9-4) by an inverter in the output enable path.

The fourth column lists the pin type for convenience where TS-Output indicates a three-stateable output pin,

1/0

indicates a bidirectional pin, and

00-1/0

denotes an open-drain bidirectional pin. An open-drain output pin has two states: off (high impedance) and logic zero.

The last column indicates the associated boundary scan register control bit for bidirectional, three-state, and open-drain output pins.

Bidirectional pins include a single scan cell for data (lO.Cell) as depicted in

Figure 9-6. These cells are controlled by one of the two cells shown in Figures

9-4 and 9-5. One or more bidirectional data cells can be serially connected to a control cell as shown in Figure 9-7. Note that, when sampling the bidirectional data cells, the cell data can be interpreted only after examining the 10 control cell to determine pin direction.

BIT

#

0

15

16

17

11

12

13

14

7

8

9

10

1

2

3

4

5

6

10.Cell

10.Cell

10.Cell

10.Cell

10.Cell

10.Cell

10.Cell

CELL PIN/CELL

TYPE NAME

10.Cell FC3

10.Cell

10.Cell

10.Cell

FC2

FC1

FCO

A23 10.Cell

10.Cell

10.Cell

A22

A21

10.Cell

10.Cell

10.Cell

10.Cell

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

Table 9-2. Boundary Scan Bit Definitions

OUTPUT

CTL CELL ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl

PIN

TYPE

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

BIT CELL PIN/CELL

# TYPE NAME

18 10.Cell A9

19 10.Cell A8

20 10.Cell

21 10.Cell

22 10.Cell

23 10.Cell

24 10.Cell

25 10.Cell

26 10.Cell

27 LPin

A7

A6

A5

A4

A3

A2

A1

TGATE2

PIN

TYPE

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

1/0*

Input

OUTPUT eTL CELL ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl ab.etl

-

28 O.Lateh TOUT2 TS-Output tout2.etl

29 10.Ct11 tout2.etl

30 LPin TIN2

-

Input

-

-

31 LPin

32 O.Lateh

33 O.Lateh

RxD1

TxD1

RTS1

Input

Output

Output

-

-

-

34 LPin CTS1

35 O.Lateh RxRDY1

Input

Output

-

MOTOROLA


9-5

Table 9-2. Boundary Scan Bit Definitions (Continued)

BIT

CELL PIN/CELL

# TYPE NAME

36 O.Latch TxRDY1

37 LPin

38 O.Latch

39 O.Latch

RxD2

TxD2

RTS2

PIN

TYPE

Output

Input

Output

Output

OUTPUT

CTL CELL

-

-

-

40 LPin

41 LPin

42 LPin

43 LPin

CTS2

SCLK

X1

DREQ1

Input

Input

Input

Input

-

-

-

-

44 O.Latch DACK1 TS-Output dma.ctl

45 O.Latch DONE1

46 LPin DONE1

47 LPin DREQ2

48 O.Latch

DACK2

49 O.Latch

DONE2

50 LPin

51 10.Cell

DONE2

IRQ7

52 10.Ct10 irq7.ctl

53 10.Cell IRQ6

54 10.Ct10 irq6.ctl

55 10.Cell IRQ5

56 10.Ct10 irq5.ctl

57 10.Cell CS3

58 10.Ct10

59 10.Cell cs3.ctl

IRQ3

60 10.Ct10 irq3.ctl

61 10.Cell CS2 aD-I/O aD-I/O

Input

aD-I/O

OD-I/O

cs3.ctl

irq3.ctl

-

62 10.Ct10

63 10.Cell

64 10.Ct10

65 10.Cell

66 10.Ct10

67 10.Cell

68 10.Cell

69 10.Cell cs2.ctl

CS1 cs1.ctl

CSO csO.ctl

DO

D1

D2

1/0

-

1/0

-

1/0

1/0

1/0

1/0

-

1/0

-

1/0

-

1/0

-

110

-

1/0

cs2.ctl

cs1.ctl

csO.ctl

db.ctl db.ctl dma.ctl

-

dma.ctl dma.ctl

irq7.ctl

irq6.ctl

irq5.ctl db.ctl

70 10.Cell

71 10.Cell

D3

D4

1/0

1/0

db.ctl db.ctl

1/0

-

1/0

-

1/0

-

1/0

-

1/0

-

1/0*

1/0**

1/0**

1/0

1/0*

1/0

-

1/0

-

1/0

-

-

-

-

1/0

-

1/0

1/0

1/0

1/0

1/0

1/0

1/0

PIN

TYPE

1/0

1/0

1/0

BIT CELL PINICELL

# TYPE NAME

72 10.Cell D5

73 10.Cell

74 10.Cell

75 10.Cell

76 10.Cell

77 10.Cell

78 10.Cell

79

10.Cell

80

10.Cell

81 10.Cell

82

84

10.Cell

83 10.Ct11

10.Ct11

D14

D15 dma.ctl ab.ctl

85 10.Ct10 berr.ctl

86 10.Ct11

87 10.Cell db.ctl

A24

88 10.Ct10 ab24.ctl

89 10.Cell A25

90

10.Ct10 ab25.ctl

91 10.Cell A26

92 10.Ct10 ab26.ctl

D10

D11

D12

D13

D6

D7

D8

D9

93 10.Cell A27

94 10.Ct10 ab27.ctl

95 10.Cell A28

96 10.Ct10 ab28.ctl

97 10.Cell A29

98 10.Ct10 ab29.ctl

99 10.Cell A30

100 10.Ct10 ab30.ctl

101 10.Cell A31

102 10.Ct10 ab31.ctl

103 10.Cell AO

104 10.Ct10 DSACKO

105 10.Cell

DSACK1

106 10.Cell RMC

107 10.Cell Rm db.ctl db.ctl

-

-

-

ab24.ctl

ab25.ctl

ab26.ctl

ab27.ctl

ab28.ctl

ab29.ctl

ab30.ctl

ab31.ctl

ab.ctl berr.ctl berr.ctl ab.ctl ab.ctl

OUTPUT

CTL CELL db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl db.ctl


Table 9-2. Boundary Scan Bit Definitions (Continued)

BIT CELL PIN/CELL

# TYPE NAME

108 10.Cell SIZ1

109 10.Cell

110 10.Cell

111 10.Cell

112 I,Pin

113 O.Latch

114 I,Pin

115 10.Cell

117

I,Pin

SIZO

OS

AS

BGACK

BG

BR

BERR

- -

116 O.Latch HALT

HALT

118 O.Latch RESET

119

I,Pin

RESET

120 O.Latch CLKOUT

PIN

TYPE

1/0*

1/0*

1/0*

1/0*

Input

Output

Input

1/0**

00-1/0

00-1/0

00-1/0

00-1/0

Output

OUTPUT

CTL CELL ab.ctl ab.ctl ab.ctl ab.ctl berr.ctl

-

-

-

-

-

BIT CELL PIN/CELL

# TYPE NAME

121

I,Pin EXTAL

122

10.Cell MODCK

123 10.Ct10 pbO.ctl

124 O.Latch

IPIPE

125 10.Cell IFETCH

126 10.Ct10 ifetch.ctl

127

I,Pin

BKPT

128 O.Latch FREEZE

129 I,Pin TIN1

PIN

TYPE

Input

1/0

-

Output

1/0

-

Input

Output

Input

130 O.Latch TOUT1 TS-Output

131 10.Ct11 tout1.ctl

-

132 O.Latch

TGATE1 Input

NOTES:

The noted pins are implemented differently than defined in the signal definition description:

*Input during Motorola factory test

**Output during Motorola factory test

OUTPUT

CTL CELL

pbO.ctl

-

ifetch.ctl

-

-

-

tout1.ctl

-

-

SHIFT DR

TO NEXT

CELL

1-EXTEST

0- OTHERWISE

DATA FROM

SYSTEM---

4 lOGIC

TO OUTPUT

BUFFER

MOTOROLA

. FROM

. LAST

CELL

CLOCK DR UPDATE DR

Figure 9-2. Output Latch Cell (O.Latch)


9-7

TO SYSTEM

LOGIC

1-EXTEST

0OTHERWISE

TO NEXT

CELL

'-_----Ir------+-------------.----~B

UPDATE DR

CLOCK DR

Figure 9-3. Input Pin Cell (I.Pin)

FROM LAST SHIFT DR

CELL

1-EXTEST o -

OTHERWISE

OUTPUT

CONTROL

FROM----t

SYSTEM

LOGIC

TO NEXT

CELL

TO OUTPUT

~~~----------+_-----~EWffi~

(1 c

DRIVE)

9-8

SHIFT DR FROM

LAST

CELL

CLOCK DR RESET

UPDATE DR

Figure 9-4. Active-High Output Control Cell (lO.CtI1)


MOTOROLA

1-EXTEST

0- OTHERWISE

OUTPUT

CONTROL

FROM----I

SYSTEM

LOGIC

TO NEXT

CELL

TO OUTPUT

~----~-----~~ENAB~

(1=DRIVE)

1-EXTEST o -

OTHERWISE

OUTPUT

CONTROL

FROM---I

SYSTEM

LOGIC

SHIFT DR FROM

LAST

CELL

1----'---110

.-----DC1

R

CLOCK DR RESET

UPDATE DR

Figure 9-5. Active-Low Output Control Cell (lO.CtIO)

SHIFT DR

TO NEXT

CELL

MOTOROLA

FROM OUTPUT FROM PIN

ENAB~

FROM LAST

CELL

CLOCK DR

UPDATE DR

Figure 9-6. Bidirectional Data Cell (lO.Cell)


9-9

TO NEXT CELL

IO.CIIO or

IO.Ctll

:;:: ::::::::::::::::::::::::::::::::::::::::::~:~:~:~:

OU6~¥l

__

~r--L....----'-~-~'--

_ _

--Il----r'-IEll

IO.Cell :::::::. ::.:'.::::}:::: ........ .

INPUT DATA

_ _

FROM LAST CELL

TO NEXT

BIDIRECTIONAL

PIN

NOTE:

More than one IO.Cell could be serially connected and conlrolled by a single IO.Ctlx cell.

Figure 9-7. General Arrangement for Bidirectional Pins

9.2.2

BYPASS

(X1X,

101)

The BYPASS instruction selects the single-bit bypass register as shown in

Figure 9-8. This creates a shift-register path from TOI to the bypass register and, finally, to TOO, circumventing the 133-bit boundary scan' register. This instruction is used to enhance test efficiency when a component other than the MC68340 becomes the device under test.

FROMTDI l---TOTDO

CLOCK DR

Figure 9-8. Bypass Register


When the bypass register is selected by the current instruction, the shift-register stage is setto a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero.

9.2.3 SAMPLE/PRELOAD (001)

The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a means to obtain a snapshot of system data and control signals. The snapshot occurs on the rising edge of TCK in the capture-DR controller state.

The data can be observed by shifting it transparently through the boundary scan register.

NOTE

Since there is no internal synchronization between the IEEE 1149.1 clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results.

The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output cells prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction.

9.2.4 HI-Z (100)

The HI-Z instruction is not included in the IEEE 1149.1 standard. It is provided as a manufacturer's optional public instruction to prevent having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance).

The instruction selects the bypass register.

9.3 MC68340 RESTRICTIONS

The control afforded by the output enable signals using the boundary scan register and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the MC68340 output drivers are enabled into actively driven networks.

The MC68340 includes on-chip circuitry to detect the initial application of power to the device. Power-on reset (POR), the output of this circuitry, is used to reset


9-11

both the system and IEEE 1149.1 logic. The purpose for applying POR to the

IEEE 1149.1 circuitry is to avoid the possibility of bus contention during poweron. The time required to complete device power-on is power-supply dependent.

However, the IEEE 1149.1 TAP controller remains in the test-logic-reset state while POR is asserted. The TAP controller does not respond to user commands until POR is negated.

The MC68340 features a low-power stop mode, which is invoked using a CPU instruction called LPSTOP. The interaction of the IEEE 1149.1 interface with low-power stop mode is as follows:

1. The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. Leaving the TAP controller test-Iogicreset state negates the ability to achieve low-power, but does not otherwise affect device functionality.

2. The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input should be externally connected to VCC or ground.

3. The TMS and TDI pins include on-chip pullup resistors. In low-power stop mode, these two pins should remain either unconnected or connected to

VCC to achieve minimal power consumption.

9.4

NON-IEEE 1149.1 OPERATION

In non-IEEE 1149.1 operation, there are two constraints. First, the TCK input does not include an internal pullup resistor and should not be left unconnected to preclude mid-level inputs. The second constraint is to ensure that the IEEE

1149.1 test logic is kept transparent to the system logic by forcing TAP into the test-logic-reset controller state, using either of two methods. During power-up,

POR forces the TAP controller into this state. After power-up is concluded, TMS must be sampled as a logic one for five consecutive TCK rising edges. If TMS either remains unconnected or is connected to VCC, then the TAP controller cannot leave the test-logic-reset state, regardless of the state of TCK.


MOTOROLA

SECTION 10

APPLICATIONS

This section provides guidelines for using the MC68340. Included in this section are a discussion of the requirements for a minimum system configuration, sample initialization sequences for system startup, and interfacing to memory.

10.1 MINIMUM SYSTEM CONFIGURATION

One of the powerful features of the MC68340 is the small number of external components needed to create an entire system. The information contained in the following paragraphs details a simple high-performance MC68340 system

(see Figure 10-1). This system configuration features the following hardware:

• Processor Clock Circuitry

• Reset Circuitry

• SRAM Interface

• ROM Interface

• Serial Interface

CLOCK

CIRCUITRY

SRAM

MC68340

SERIAL

INTERFACE

ROM

Figure 10-1. Minimum System Configuration Block Diagram

MOTOROLA


10-1

10.1.1 Processor Clock Circuitry

The MC68340 has an on-chip clock synthesizer that can operate from an onchip phase-locked loop (PLL) and a voltage-controlled oscillator (VCO). The clock synthesizer uses an external crystal connected between the EXTAL and

XTAL pins as a reference frequency source. Figure 10-2 shows a typical circuit using an inexpensive 32.768-kHz watch crystal. The 20-M resistor connected between the EXTAL and XTAL pins provides biasing for a faster oscillator startup time. The crystal manufacturer's documentation should be consulted for specific recommendations on external component values.

MC68340

XTAL

EXTAL

330k

32.768 kHz

C1

20pF

~"d

20pF _

Figure 10-2. Sample Crystal Circuit

A separate power pin (VCCSYN) is used to allow the clock circuits to operate with the rest of the device powered down and to provide increased noise immunity for the clock circuits. The source for VCCSYN should be a quiet power supply, and external bypass capacitors (see Figure 10-3) should be placed as close as possible to the VCCSYN pin to ensure a stable operating frequency.

VCCSYN

VCCSYN 1--_.--.......1.-~

...,

MC68340

XFC

NOTE 1: Must be a low leakage capacitor.

Figure 10-3. XFC and VCCSYN Capacitor Connections

MOTOROLA

10-2


Additionally, the PLL requires that an external low-leakage filter capacitor, typically in the range of 0.01 to 0.1 f.LF, be connected between the XFC and V CCSYN pins. Smaller values of the external filter capacitor provide a faster response time for the PLL, and larger values provide greater frequency stability. Figure

10-3 depicts examples of both an external filter capacitor and bypass capacitors for VCCSYN.

10.1.2 Reset Circuitry

Because it is optional, reset circuitry is not shown in Figure 10-1. The MC68340 holds itself in reset after power-up and asserts RESET to the rest of the system.

If an external reset pushbutton switch is desired, an external reset circuit is easily constructed by using open-collector cross-coupled NAND gates to debounce the output from the switch.

10.1.3 SRAM Interface

The SRAM interface is very simple when the programmable chip selects are used. External circuitry to decode address information and circuitry to return data and size acknowledge (DSACK) is not required. However, external ICs are required to provide write enables for the high and low bytes of data.

A15-A1

~------------~-----~

ANi

AO

MCGB340

MCM6206-35 o-:-:W=L

Riii

015-00

SIZO

.---.-----ICE

CSI----------'

MCM6206-35

pjjj

CE

015-0B

Figure 10-4. SRAM Interface

MOTOROLA


The SRAM interface shown in Figure 10-4 is a two-clock interface at 16.78-MHz operating frequency. The MCM6206-35 memories provide an access time of 15 ns when the

E input is low. If buffers are required to reduce signal loading or if slower and less expensive memories are desired, a three-clock cycle can be used. In the circuit shown in Figure 10-4, additional memories can be used provided that the MC68340 specification for load capacitance on the chip-select

(CS) signal is not exceeded. (Address buffers may be needed, however.)

10.1.4 ROM Interface

Using the programmable chip selects creates a very straightforward ROM interface. As shown in Figure 10-5, no external circuitry is needed. Care must be used, however, not to overload the address bus. Address buffers may be required to ensure that the total system input capacitance on the address signals does not exceed the CL specification.

MC68340

A16-A1

015-00

eso

CE

16-BIT

ROM

DE

-.L

Figure 10-5. EPROM Interface

10.1.5 Serial Interface

The necessary circuitry to create an RS-232 interface with the MC68340 includes an external crystal and an RS-232 receiver/driver (see Figure 10-6). The resistor and capacitor values shown are typical; the crystal manufacturer's documentation should be consulted for specific recommendations on external component values. The circuit shown does not include modem support (ready to send

(RTS) and clear to send (CTS) are not shown); however, these signals can be connected to the receiver/driver and to the connector in a similar manner as the connections for TxD and RxD.


MOTOROLA

MCG8340

Xl

10M

X2

470

RxD

TxD a:

0

N t -

MC,)

NW

(J)Z a:Z

0

C,)

Figure 10-6. Serial Interface

10.2 MC68340 INITIALIZATION SEQUENCE

The following paragraphs discuss a suggested method for initializing the

MC68340 after power-up.

10.2.1 Startup

RESET is asserted by the MC68340 during the time in which VCC is ramping up, the VCO is locking onto the frequency, and the MC68340 is going through the reset operation. After RESET is negated, four bus cycles are run, with CS.o being asserted to fetch the 32-bit program counter (PC) and the 32-bit stack pointer (SP) from the boot ROM. Until programmed differently, CSO is a

16-bit-wide, three-wait-state chip select.

After the PC and the SP are fetched, the following programming steps should be followed:

• Initialize and set the valid bit in the module base address register (CPU space address $03FFOO) with the desired base address for the internal modules .

• Initialize and set the valid bits in the necessary chip-select base address and address mask registers. Following this step, other system resources requiring the CSx signals can be accessed. Care must be exercised when changing the address for CSO. The address of the instruction following the

MOVE instruction to the CSO base address register must match the value of the PC at that time.

MOTOROLA


10.2.2

SIM Module Configuration

The order ofthe following SIM register initializations is not important; however, time can be saved by initializing the clock synthesizer control register first to quickly increase to the desired processor operating frequency. The module base address register must be initialized prior to any of following steps.

Clock Synthesizer Control Register (SYNCR)

• Set frequency control bits (W, X, Y) to specify frequency.

• Select action taken during loss of crystal (RSTEN bit): activate a system reset or operate in limp mode.

• Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits).

Module Configuration Register (MCR)

• If using the software watchdog and/or the periodic interrupt timer, select action taken when FREEZE is asserted (FRZ bits).

• Select port B configuration (FIRQ bit). Note that this bit is used in combination with the bits in the port B pin assignment register (PPARB) to program the function of the port B pins.

• Select the access privilege for the supervisor/user registers (SUPV bit).

• Select the interrupt arbitration level for the SIM (lARB bits).

Autovector Register (AVR)

• Select the desired external interrupt levels for internal autovectoring.

System Protection Control Register (SYPCR) (Note that this register can only be written once after reset.)

• Enable the software watchdog, if desired (SWE bit).

• If the watchdog is enabled, select whether a system reset or a level 7 interrupt is desired at timeout (SWRI bit).

• If the watchdog is enabled, select the timeout period (SWT bits).

• Enable the double bus fault monitor, if desired (DBF bit).

• Enable the external bus monitor, if desired (BME bit).

• Select timeout period for bus monitor (BMT bits).

Software Watchdog Interrupt Vector Register (SWIV)

• If using the software watchdog, program the vector number for a software watchdog interrupt.


MOTOROLA

Periodic Interrupt Timer Register (PITR)

• If using the software watchdog, select whether or not to prescale (SWP bit).

• If using the periodic interrupt timer, select whether or not to prescale (PTP bit).

• Program the count value for the periodic timer, or program a zero value to turn off the periodic timer (PITR bits).

Periodic Interrupt Control Register (PICR)

• If using the periodic timer, program the desired interrupt level for the periodic interrupt timer (PIRQL bits).

• If using the periodic timer, program the vector number for a periodic timer interrupt.

Port A and B Registers

• Program the desired function of the port A signals (PPARA 1 and PPARA2 registers).

• Program the desired function of the port B signals (PPARB register).

10.2.3 DMA Module Configuration

The following paragraphs describe DMA module initialization and operation.

If the DMA capability of the MC68340 is being used, the initialization steps should be performed during the initialization sequence for the part. The operation steps should be performed to start a DMA transfer.

10.2.3.1 DMA MODULE INITIALIZATION. The following steps can be accomplished in any order when initializing the DMA module. These steps need to be performed for each channel used.


• Initialize the stop bit (STP) for normal operation. (Only one STP bit exists for both channels.)

• Select whether to respond to or ignore FREEZE (FRZ bits). (Only one set of FRZ bits exits for both channels.)

• If desired, enable single-address mode (SE bit).

• Program the interrupt service mask to set the level below which interrupts are ignored during a DMA transfer (ISM bits).

MOTOROLA


10-7


• Program the master arbitration ID (MAID) to establish priority on the intermodule bus. Note that the two DMA channels should have distinct IDs if both channels are being used. (If they are programmed the same, channel

1 has priority.)

• Select the interrupt arbitration level for the DMA channel (lARB bits). (Only one set of IARB bits exits for both channels.)

Interrupt Register (INTR)

• Program the interrupt priority level for the channel interrupt (lNTL bits).

• Program the vector number for a channel interrupt (lNTV bits).

Channel Control Register (CCR)

• If desired, enable the interrupt when breakpoint is recognized and the channel is the bus master (lNTB bit).

• If desired, enable the interrupt when done without an error condition (lNTN bit).

• If desired, enable the interrupt when the channel encounters an error (INTE bit).

• Select which device generates requests if in dual-address mode, or select the direction of transfer if in single-address mode (ECO bit).

10.2.3.2 DMA MODULE OPERATION (SINGLE-ADDRESS MODE). The following steps are required to begin a DMA transfer in single-address mode.


• Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely.

• Select the amount by which to increment the source address for a read cycle (SAPI bits) or the destination address for a write cycle (DAPI bits).

• Define the transfer size by selecting the destination size for a write cycle

(DSIZE) or by selecting the source size for a read cycle (SSIZE bits).

• Select signal address transfer (S/D bit).

Address Register (SAR or DAR)

• Write the source address for a read cycle or the destination address for a write cycle.

10·8 MC68340 USER'S MANUAL MOTOROLA

Function Code Register (FCR)

• Encode the source function code for a read cycle or the destination function code for a write cycle.

Byte Transfer Counter (BTC)

• Encode the number of bytes to be transferred.


• Write a one to the start bit (STR) to allow the transfer to begin.

10.2.3.3 DMA MODULE OPERATION (DUAL-ADDRESS MODE). The following steps are required to begin a DMA transfer in dual-address mode.


• Write a zero to the start bit (STR) to prevent the channel from starting the transfer prematurely. o Select the amount by which to increment the source and destination addresses (SAPI and DAPI bits).

• Select the source and destination sizes (SSIZE and DSIZE bits). o Select internal request, external request burst mode, or external request cycle steal (REO bits).

• If using internal request, select the amount of bus bandwidth used by the

DMA (BB bits).

• Select dual-address transfer (SID bit).

Address Registers (SAR and DAR)

• Write the source and destination addresses.

Function Code Register (FCR)

• Encode the source and destination function codes.

Byte Transfer Counter (BTC)

• Encode the number of bytes to be transferred.


• Write a one to the start bit (STR) to allow the transfer to begin.

MOTOROLA


10-9

10.2.4 Serial Module Configuration

If the serial capability of the MC68340 is being used, the following steps are required to properly initialize the serial module. Note that the serial module registers can only be accessed by byte operations.

Command Register (CR)

• Reset the receiver and transmitter for each channel.

The following steps program both channels:


• Initialize the stop bit (STP) for normal operation.

• Select whether to respond to or ignore FREEZE (FRZ bits).

• Select the input capture clock (lCCS bit).


• Select the interrupt arbitration level for the serial module (IARB bits).

Interrupt Vector Register (IVR) o Program the vector number for a serial module interrupt.

Interrupt Level Register (lLR)

• Program the interrupt priority level for a serial module interrupt.

Interrupt Enable Register (lER)

• Enable the desired interrupt sources.

Auxiliary Control Register (ACR)

• Select baud rate set (BRG bit).

• Initialize the input enable control (lEC bits).

Output Port Control Register (OPCR)

• Select the function of the output port pins.

Interrupt Status Register (lSR)

• The XTAL-RDY bit should be polled until it is cleared to ensure that an unstable crystal input is not applied to the baud rate generator.


The following steps are channel specific:

Clock Select Register (CSR)

• Select the receiver and transmitter clock.

Mode Register 1 (MR1)

• If desired, program operation of receiver ready-to-send (RxRTS bit).

• Select receiver-ready or FIFO-full notification (R/F bit).

• Select character or block error mode (ERR bit).

• Select parity mode and type (PM and PT bits).

• Select number of bits per character (B/C bits).

Mode Register 2 (MR2)

• Select the mode of channel operation (CM bits).

• If desired, program operation of transmitter ready-to-send (TxRTS bit).

• If desired, program operation of clear-to-send (CTS bit).

• Select stop-bit length (SB bits).


• Enable the receiver and transmitter.

10.2.5

Timer Module Configuration

If the timer capability of the MC68340 is being used, the following steps should be followed to initialize a timer module properly. Note that this sequence must be done for each timer module used.


• Clear the SWR bit to disable the timer.


• Clear the TC, TG, and TO bits to reset the interrupts.

M'odule Configuration Register (MCR)

• Initialize the stop bit (STP) for normal operation.

• Select whether to respond to or ignore FREEZE (FRZ bits).



• Select the interrupt arbitration level for the serial module (IARB bits).

Interrupt Register (IR)

• Program the interrupt priority level for the channel interrupt (ll bits).

• Program the vector number for a channel interrupt (lVR bits).

Preload Registers (PREl1 and PREl2)

• If required, initialize the preload registers for mode of operation.

Compare Register (COM)

• If desired, initialize the compare register.

The following steps begin operation:


• Set the SWR bit to enable the timer.

• Enable the desired interrupts (IE bits).

• Enable TGATE if required for mode of operation (TGE bit).

• Select the counter clock (PSE bit).

• Enable the selected clock (CPE bit).

• Select the selected clock (ClK bit).

• If the PSE bit is set, select the prescaler output tap (POT bits).

• Select the mode of operation (MODE bits).

• Select the operation of TOUT (OC bits).

10.3 MEMORY INTERFACE INFORMATION

The following paragraphs contain information on using an 8-bit boot ROM, performing access time calculations, calculating frequency-adjusted outputs, and interfacing an 8-bit device to 16-bit memory using single-address mode.

10.3.1 Using a 8-Bit Boot ROM

Upon power-up, the MC68340 uses CSO to begin operation. CSO, until otherwise programmed, is a three-wait-state, 16-bit chip select. If an 8-bit ROM is desired, external circuitry can be added to return an 8-bit DSACK in two wait states (see

Figure 10-7).


MOTOROLA

CLKOUT

MC68340

CP

MR

'393

00

01

02

03

Figure 10-7. External Circuitry for 8-Bit Boot ROM

The '393 is a falling edge triggered counter; thus, CSO is stable during the time in which it is being clocked. CSO acts as th'e asynchronous reset i.e., when it is asserted, the '393 is allowed to count. The falling edge of S2 provides the first counting edge. 01 does not transition on this falling edge, but transitions to a logic one on the subsequent edge. DSACKO is 01 inverted; thus, on the next falling edge, DSACKO is seen as asserted, indicating an 8-bit port. When

CSO is negated, 01 is again held in reset and DSACKO is negated. The timing diagram in Figure 10-8 illustrates this operation.

CLKOUT

CSO(MR)

00

01

_ _ _ _ _

1

--II

\""'------

Figure 10-8. 8-bit Boot ROM Timing

10.3.2 Access Time Calculations

The two time paths that are critical in an MC68340 application using the CS signals are shown in Figure 10-9. The first path is the time from adddress valid to when data must be available to the processor; the second path is the time from CS asserted to when data must be available to the processor.

MOTOROLA


50 51 54 55 50

Figure 10-9. Access Time Computation Diagram

As shown in the diagram, an equation for the address access time, tADV, can be developed as follows: where:

T = system clock period

N = number of clocks per access t6 = CLKOUT high to address valid = 30-ns maximum at 16.78 MHz t27 = data-in valid to CLKOUT low setup = 5-ns minimum at 16.78 MHz

An equation for the chip select access time, tCSDV, can be developed as follows: tCSDV= T(N -1) -tg -t27 where:

T = system clock period

N = number of clocks per access tg = CLKOUT low to CS asserted = 30-ns maximum at 16.78 MHz t27 = data-in valid to CLKOUT low setup = 5-ns minimum at 16.78 MHz

Using these equations, the memory access times at 16.78 MHz are shown in

Table 10-1.

Table 10-1. Memory Access Times at 16.78 MHz tADV tCSDV

N=2

55 ns

25 ns

N=3

115 ns

85 ns

N=4

175 ns

145 ns

N=5

235 ns

205 ns

N=6

295 ns

265 ns


MOTOROLA

The values can be used to determine how many clock cycles an access will take, given the access time of the memory devices and any delays through buffers or external logic that may be needed.

10.3.3 Calculating Frequency-Adjusted Output

The general relationship between the CLKOUT and most input and output signals is shown in Figure 10-10. Most outputs transition off of a falling edge of CLKOUT, but the same principle applies to those outputs that transition off of a rising edge.

CLKOUT

I

_------II

Id~'I--_

OUTPUTS

ASYNCHRONOUS

INPUTS ..........

-><.....> _ _ _

~ 't----~

Figure 10-10. Signal Relationships to CLKOUT

For outputs that are referenced to a clock edge, the propagation delay (td) does not change as the frequency changes. For instance, specification 6 in the electrical characteristics, shown in MC68340/0,

MC68340 Technical Summary,

shows that address, function code, and size information is valid 3 to 30 ns after the rising edge of SO. This specification does not change even if the device frequency is less than 16.78 MHz. Additionally, the relationship between the asynchronous inputs and the clock edge, as shown in Figure 10-10, does not change as frequency changes.

A second type of specification indicates the minimum amount of time a signal will be asserted. This type of specification is illustrated in Figure 10-11.

MOTOROLA

CLKOUT

OUTPUT

;:~========-tw-

~

_-_-_-_-_-_-_-_-

-->~r

'-

Figure 10-11. Signal Width Specifications


The method for calculating a frequency-adjusted tw is as follows: tw'=tw+ N

(

T-T

+ T-td where: tw' =the frequency-adjusted signal width tw=the signal width at 16.78 MHz

N

=the number of full one-half clock periods in tw

~f

= one-half the clock period at full speed td =the propagation time from the clock edge

The following calculation uses a 16.78-MHz part, specification 14,

AS width asserted, at 12.5 MHz as an example: tw = 100 ns

N

=3

Tf'

=~=40

2 2 ns

Tf

=~=30

2 2 ns td = 30 ns maximum therefore: tw'=100+3(40-30)+(40-30)=140 ns

The third type of specification used is a skew between two outputs, as shown in Figure 10-12.

10-16


MOTOROLA

CLKOUT

~--TI2--~

~--4----------

OUTPUT2

-------~--------~

14---ts-~~

Figure 10-12. Skew between Two Outputs

The method for calculating a frequency-adjusted ts is as follows: ts'=ts+N

(

2 - 2

+

2 td1

) where: ts' = the frequency-adjusted skew ts =the skew at full speed

N =the number of full one-half clock periods in ts, if any

Tf' = one-half the new clock period

2

~f

= one-half the clock period at full speed td1 =the propagation time for the first output from the clock edge

The following calculation uses a 16.78-MHz port, specification 21,

RIW

high'to

AS asserted, at 8 MHz as an example: ts = 15 ns minimum

N =0

Tfl 125

2=2=62.5 ns

.lL=

60 =30 ns

2 2 td1 = 30 ns maximum therefore: tw'=15+0(62.5-30)+(62.5-30)=47.5 ns minimum

In this manner,new specifications for lower frequencies can be derived for an

MC68340.

MOTOROLA


10-17

10.3.4 Interfacing an a-Bit Device to 16-Bit Memory

Using Single-Address DMA Mode

One of the requirements of single-address mode is that the source and destination must be the same port size. However, the MC68340 can perform direct memory accesses in single-address mode between an 8-bit device and 16-bit memory. The port size must be specified as 8 bits, and some external logic is required as shown in Figure 10-13.

DEVICE

015-08

Riii

1 - - - - - 1

MC68340 AO

SIZ11---I

SIZO

MEMORY

Figure 10-13. Circuitry for Interfacing 8-Bit Device to

16-Bit Memory in Single-Address DMA Mode

Ouring even-byte accesses, the data is transferred directly on 015-08. However, during odd-byte accesses, the data must be routed on 015-08 for the 8-bit device and on 07-00 for the 16-bit memory.


MOTOROLA

SECTION 11

ELECTRICAL CHARACTERISTICS

This section contains information on the maximum ratings and thermal characteristics of the MC68340. Detailed information on power considerations, DC electrical characteristics, and AC timing specifications is provided in the


11.1 MAXIMUM RATINGS

Rating Symbol

Supply Voltage

Input Voltage

Operating Temperature Range

Storage Temperature Range

VCC

Vin

TA

Tstg

Value

-0.3 to +7.0

-0.3 to +7.0 o to 70

-55 to + 150

Unit

V

V

°c

°c

11.2 THERMAL CHARACTERISTICS

Symbol Characteristic

Thermal Resistance Junction to Case

Ceramic 144-Pin OFP

Plastic 145-Pin PGA

Thermal Resistance Junction to Ambient

Ceramic 144-Pin OFP

Plastic 145-Pin PGA

*Estimated

TBD To be determined

8JA

8JA

Value

15*

TBD

46*

27*

Unit

°C/W

°C/W

The following ratings define a range of conditions in which the device will operate without being damaged. However, sections of the device may not operate normally while being exposed to the electrical extremes. This device contains circuitry to protect against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum·rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or Vee).

MOTOROLA


11-1

11-2


MOTOROLA

SECTION 12

ORDERING INFORMATION AND

MECHANICAL DATA

This section contains the pin assignments and package dimensions of the

MC68340. In addition, detailed information is provided to be used as a guide when ordering.

12.1 STANDARD MC68340 ORDERING INFORMATION

Package Type

Frequency Temperature

Order Number

(MHz)

16.78 O°C to

+

70°C MC68340FE16 Ceramic Surface Mount

FE Suffix

Plastic Pin Grid Array

RP Suffix

16.78 O°C to

+

70°C MC68340RP16

MOTOROLA


12-1

12.2 PIN ASSIGNMENT CERAMIC SURFACE MOUNT

(FE SUFFIX)

RMC

RiW

SIZl

SIZO

55

AS

BGACK

BG

BR

VCC

IPIPE

IFETCH

BKPT

FREEZE

TINl

TOUTl

TGATEl

TCK

TMS

TOI

TOO

VCC

GND

BERR

HALT

RESET

GND

CLKOUT

VCC

XFC

VCC

EXTAL

VCCSYN

XTAL

GND

MODCK

TOP VIEW

MC68340

OREQl

Xl

GND

VCC

X2

SCLK

CTSB

RTSB

TxOB

RxOB

RxROYA

TxROYA

CTSA

RTSA

GND

VCC

TxOA

RxOA

TIN2

TooT2

TGATE2 csa

CSl

CS2

IRQ3

CS3

GNO

VCC

IRas

IRQ6

IRQ7

OONE2

DACK2

DREQ2

OONEl

DACKl

12-2


MOTOROLA

The VCC and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340. These groups are shown in the following table.

Pin Group - FE Suffix

Address Bus, FCx vcc

GND

41,50,59,68,134 42,51,60,69,135

Data Bus 113, 123

CSx, IRQx, DACKx, DONEx, RTSx, TxDx, 78, 90, 102

RxRDYA, TxRDYA, TOUT2, Internal Logic

114,124

RMC, R/W, SIZx, DS, AS, BG, HALT, RESET, 15,17,35, 143 13,21,36,144

CLKOUT, MODCK, IPIPE, IFETCH, FREEZE,

TOUT1, Internal Logic

79,91,103

Oscillator

Internal Only

19

23 55,126

-

MOTOROLA


12-3

12.3 PIN ASSIGNMENT PLASTIC PIN GRID ARRAY (RP SUFFIX)

o

P

N

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FC1 FC3 TOI TCK TIN1 FREEZE IPIPE MODCK EXT AL XFC RESET BERR

BR AS

SIZ1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A2.3 FC2 TOO TMS TOUT1 BKPT VCC XTAL VCC CLKOUT HALT BGACK

OS

Riii

RMC

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A2.2 FCO GNO VCC TGATE1 IFETCH GNO VCCSYN VCC GNO BG SIZO GNO OSACK1 OSACKO

MOO

0

A2.0 GNO VCC

L

0 0 0

A18 A19 A2.1

0 0 0

VCC AO A30

0 0 0

A31 A2.9 A2.8

K

0 0 0

A1S A17 VCC

0 0 0

A14 A15 GNO

H

0 0 0

A12 A13 GNO

GOO 0

A11 GNO VCC

F

0 0 0

A10 A9 AS

BonOM

VIEW

0 0 0

GNO VCC A2.7

0 0 0

A2.5 A2.4 A2.S

0 0 0

GNO 014 015

0 0 0

GNO 012 013

0 0 0

VCC 011 010

E

0 0 0

A7 AS AS

0 0 0

07 08 09 o

0 0 0 0

A4 VCC GNO NC

0 0 0

GNO 05 OS c O O

0 0 0 0 0 0 0 0 0 0 0 0 0

A3 A2. TGATE2 VCC GNO TxOB VCC GNO OACK1 IR07 GNO CS2 01 VCC 04

A

BOO

0 0 0 0 0 0 0 0 0 0 0 0 0

A1 TOUT2 TxOA RTSA TxROYA RTSB X2 X1 OONE1 OONE2 VCC CS3 CS1 DO 03 o

0 0 0 0 0 0 0 0 0 0 0 0 0

RxOA ClSA RxRDYA RxOB ClSB SCLK ORE01 ORE02 OACK2 tROS IR05 IR03 csa

02

2 5 10 11 12 13 14 15

S 7

12-4


MOTOROLA

The VCC and GND pins are separated into groups to help electrically isolate the different output drivers of the MC68340. These groups are shown in the following table.

Pin Group· RP Suffix

Address Bus, FCx

VCC

GND

D2, G3, K3, K14, D3, G2, J3, K13,

M3 M2

Data Bus

C14, F13 D13, G13

RMC, RIW, SIZx, DS, AS, BG, HALT, RESET, M13, N4, N9, P9 N3,N7,N10,N13

CLKOUT, MODCK, IPIPE, IFETCH, FREEZE,

TOUT1, Internal Logic

CSx, IRQx, DACKx, DONEx, RTSx, TxDx, B11, C4, C7

RxRDYA, TxRDYA, TOUT2, Internal Logic

C5, C8, C11

Oscillator

Internal Only

N8

P7

-

G13, H3

MOTOROLA MC68340 USER'S MANUAL 12·5

12.4 PACKAGE DIMENSIONS

FE Suffix

FE SUFFIX PACKAGE

CERAMlcaFP

CASE 863-01

PIN ONE INDENT

TOP VIEW

TRIMMED, FORMED DISCRETE UNIT

SHOWING DATUM FEATURES

12-6

~--------------SN--------------~lrr~~,-,-~~~

SIDE VIEW

GULL WING LEAD CONFIGURATION

MILUMETERS

DIM MIN MAX

A 25.84 27.70

B 25.84 27.70

C

3.55 4.31

0

G

M

0.22 0.41

0.65BSC

H

0.25

J

0.13

K

0.65

O·

0.88

0.25

0.95

8· a

0.325 BSC

R

0.71

S

30.95

V

30.95

I - -

I

I

31.45

31.45

INCHES

MIN MAX

1.017 1.091

1.017

0.140

0.009

1.091

0.170

0.016

0.0256 BSC

0.010

0.005

0.026

O·

0.035

0.010

0.037

8·

0.0128 BSC

0.028

I

--

1.219

1.219

I 1.238

1.238

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS

3. DIM A AND B DEFINE MAXIMUM CERAMIC BODY DIMENSIONS

INCLUDING GLASS PROTRUSION AND MISMATCH OF CERAMIC

BODY TOP AND BOTTOM.

4. DATUM PLANE -W- IS LOCATED AT THE UNDERSIDE OF LEADS

WHERE LEADS EXIT PACKAGE BODY.

5. DATUMS X-Y AND Z TO BE DETERMINED WHERE CENTER LEADS

EXIT PACKAGE BODY AT DATUM -Woo

6. DIM S AND V TO BE DETERMINED AT SEATING PLANE, DATUM -T-.

7. DIM A AND B TO BE DETERMINED AT DATUM PLANE -W-.


MOTOROLA

12.5

PACKAGE DIMENSIONS

RP Suffix

MC68340

145 PIN PLASTIC PGA CASE OUTUNE

~ a o

0 0 0 0 o

0 o

0 0 0 0 0 p o@oo o b

0 0 0 0 0 0 0

N o

0 0 0 0 o

0 0 0 0 0 0 0 o

0

M 0 0 0

0 0 0

L

K 0 0 0

0 0 0

J

BonOM

H o

0 0

G o

0 0

1 2 3

VIEW

~I<~-------B--------~

~J~ rc

0 0 0

F

~

0 0 0

D o

0 0 0

T

0

C 0 0 0

B

0 0 0

0 0 0

0 0 0 o

0 0 0 0 0 0 0 0 0 0 0 o@o o

0 o

0 o

0 o

0 oo@o

A o

0 0 0 0 o

0 o

0 0 0 0 0 0 0

0 0 0

9 10 11 12 13 14 15

0 0 0

0 o

0

0 o

0

0 0 0

0 0 0

DIM

MILUMETERS

MIN

A 39.37 39.88

B

39.37 39.88

C

D

2.79

0.43

3.56

0.55

G

K

2.54BSC

4.32 4.95

INCHES

MAX

MIN

MAX

1.550 1.570

1.550 1.570

0.110 0.140

0.017 0.022

0.100BSC

0.170

0.195

MOTOROLA


12-8


MOTOROLA

INDEX

-A-

A-Line Instructions,

5-74

AID

Bit, 7-18

Field, 5-106

AO Signal, 3-7-3-13

Absolute Long Address, 5-25

Absolute Short Address, 5-23

Access Times, 10-13

Address

Access Time,

10-14

Bus Signals, 2-4, 3-3, 3-17

Error Exception, 3-8, 3-40, 5-72, 5-77

Mask Register Example, 4-33

Mask Reg isters, 4-32, 10-5

Registers, 5-11, 5-13

Space Block Size, 4-13

Spaces 2-5, 3-3, 3-4, 4-30-4-31, 6-19

Strobe Signal, 2-7, 3-2, 3-4, 3-15, 3-16, 3-19-3-23,

3-~5, 3-47

Address Register Indirect Mode, 5-20 with Displacement, 5-21 with Index, 5-21-5-22 with Postincrement, 5-20, 5-33, 5-34 with Predecrement, 5-20, 5-33, 5-34

Addressing Capabilities, 5-27

Addressing Modes, 5-30

Categories, 5-27

Alterable Addressing Effective Address Mode, 5-26

Alternate Function Code Registers, 5-12, 5-14

Arithmetic/Logical Instruction Timing Table,

5-141-5-143

Assert RTS Command, 7-33

Asynchronous

Inputs, 3-2, 3-15, 3-16, 3-45

Operation, 3-14

Setup and Hold Times, 3-2, 3-16, 3-19-3-21, 10-15

ATEMP Register, 5-98

Automatic Echo Mode, 7-16, 7-43

Autovector

Operation Timing, 3-33

Register, 4-5, 4-21, 10-6

Signal, 2-5, 3-5, 3-30, 3-34, 4-6

Auxiliary Control Register, 7-20, 7-30, 7-36, 10-10

-B-

B Bits, 5-82

B/C Bits, 7-27, 10-11

Background Debug Mode, 5-94, 3-25

Command Execution, 5-99

Command Summary, 5-109

Serial Interface,

5-100

Background Processing State, 5-8, 5-62, 5-95-5-101

Base Address Registers, 4-30, 10-5

Baud Rate

Clock, 7-29

Generator, 7-3, 7-9

BB Bits, 6-8, 6-16

BDM Sources, 5-96

BED Bit, 6-8, 6-14, 6-16-6-17

BERR Signal, 5-70, 5-73

BES Bit, 6-8, 6-14, 6-16-6-17

BGND Instruction, 5-97

Binary-Coded Decimal

Data, 5-13

Extended Instructions Timing Table, 5-144

Instructions, 5-50

Bit Manipulation Instructions, 5-49-5-50

Timing Table, 5-146-5-147

Bit Set /Reset Command, 7-42, 7-43

Bits per Character, 7-27

BKPT Signal,

5-95,. 5-97, 5-100

BKPT_ TAG,

5-105

Block Mode, 7-15, 7-26

BME Bit, 4-6, 4-25, 10-6

BMT Bits, 4-25, 10-6

Boot ROM, 4-13,4-14, 10-5

Boundary Scan

Bit Definitions, 9-4

Register, 9-1-9-3

Break Condition, 7-13

Breakpoint Acknowledge Cycle

Operation, 3-24

Flowchart, 3-26

Timing, Opcode Returned, 3-27

Timing, Exception Signaled, 3-28

Breakpoint Instruction, 3-24, 5-73, 5-94, 5-97

Breakpoint Signal, 2-10, 3-24,3-25,6-18

BRG Bit, 7-36, 10-10

Brief Format Instruction Word,

5-22, 5-25, 5-31

BRKP Bit, 6-8, 6-14, 6-17-6-18

Burst Mode Transfers, 6-5, 6-8, 6-16

Bus Arbitration

Bandwidth, 6-8

Control, 3-45

Controller Operation, 5-125

Cycle, 3-2

Cycle Termination,

3-34-3-36, 3-48

Cycle Termination Response Time,

4-6

During DMA transfers, 6-3, 6-10, 6-17, 6-20-6-21

Error Exception, 5-70-5-72, 5-77

Error Signal, 2-9, 3-5, 3-14-3-16, 3-24, 3-31,

3-34-3-38, 3-45, 4-4, 4-6, 4-30

Error Stack Frame, 5-80, 5-91-5-93

Flowchart, 3-43

Grant Acknowledge Signal, 2-8, 3-42-3-45

MOTOROLA

MC68340 USER'S MANUAL INDEX-1

Interaction with Show Cycles, 3-44

Operation, 3-40, 3-42-3-45

Request Signal, 2-8, 3-37, 3-42-3-45, 6-12

Resulting in Double Bus Faults, 3-40

State Diagram, 3-46

Timing, without DSACK, 3-37

Timing, late Bus Error, 3-38

Types, 3-36

Bypass Register, 9-10

Byte

Operands, 5-12

Transfer Counter, 6-3, 6-4, 6-9, 6-10, 6-18, 6-21,

10-9

-c-

Calculate Effective Address Instruction Timing Table,

5-138

Calculating Frequency Adjusted Output, 10-15

CAll Command, 5-100, 5-119-5-120

Cell Types, 9-4

Output latch Diagram, 9-7

Input Pin Diagram, 9-8

Active-High Output Control Diagram, 9-8

Active-low Output Control Diagram, 9-9

Bidirectional Data Diagram, 9-9

Change of Flow, 5-126

Changing

Privilege levels, 5-63-5-64

Timer Modes, 8-6

Channel

Control Register, 6-3, 6-6-6-10, 6-14, 6-17,

10-8-10-9

Mode, 7-43

Status Register, 6-6,6-8,6-14,6-17

Character Mode, 7-15, 7-26

Chip-Select 0 Sighal, 3-30, 4-14,10-5,10-12-10-13

Chip Select, 4-13, 4-30

Access Time, 10-14

Signals, 2-5, 4-2, 4-3, 10-4

Clear-to-Send Signal, 2-12

ClK Bit, 8-23, 10-12

ClKOUT Signal, 2-9, 4-12, 5-102, 8-3, 9-11

Clock

Select Register, 7-9, 7-20, 7-29, 7-38, 10-11

Synthesizer Control Register, 4-9-4-11, 4-28, 10-6

Synthesizer, 4-2, 4-9

CM Bits, 7-43

Code Compatibility, 5-8, 5-36

COM Bit, 8-7-8-8, 8-10, 8-27, 10-11

Command Format, 5-105

Register, 7-11, 7-13, 7-28, 7-31,10-10-10-12

Sequence Diagram, 5-106-5-107

Compare Register, 8-3, 8-13, 8-29,10-12

Compressed Tables, 5-55-5-57

Condition Code Register, 5-11, 5-14, 5-43

Condition Codes, 5-11, 5-44-5-45, 5-51

Condition Test Instructions, 5-53

Conditional Branch Instruction Timing Table, 5-147

CONF Bit, 6-8, 6-14, 6-16-6-21

Control Addressing Effective Address Mode, 5-26

Control Instruction Timing Table, 5-148

Control Register, 8-4, 8-21

COS Bit, 7-37, 7-40

COSA Bit, 7-36

COSB Bit, 7-36

Counter

Clock,8-3

Events, 8-2

Register, 8-6-8-7, 8-14, 8-27

CPE Bit, 8-6, 8-8, 8-23,10-12

CPU Space, 3-3, 3-24, 3-30

Address Encoding, 3-24

CPU32

Block Diagram, 5-3

Privilege levels, 5-8, 5-62

Processing States, 5-8, 5-62

Programming Model, 5-9-5-10

Serial logic, 5-101-5-102

Stack Frames, 5-90-5-93

Crystal Oscillator, 4-7, 4-9

CTS

Bits, 7-36, 7-41,10-11

Operation, 7-11

CTSx Signal, 7-8, 7-11, 7-23, 7-24, 7-25, 7-33, 7-35,

7-37, 7-40, 7-44

Current Instruction Program Counter, 5-100

Cycle Steal Transfers, 6-5, 6-16

Cycle Termination, 3-1

-D-

DAPI Bits, 6-3, 6-6, 6-15,10-8, 10-9

Data

Addressing Effective Address Mode, 5-26

Bus Signals, 2-4, 3-4, 3-17

Holding Register, 6-6, 6-22

Misalignment, 5-14, 5-66, 5-72

Movement Instructions, 5-45-5-46

Port Organization, 3-7

References, 5-16

Registers, 5-11, 5-12

Strobe Signal, 2-7, 3-4, 3-16, 3-19-3-23, 3-45, 3-47

Transfer and Size Acknowledge Signals, 2-6, 3-5,

3-8-3-16,3-19-3-24,3-30,3-34,3-37,4-6

Transfer Capabilities, 3-6, 3-8-3-13

Types, 5-12

DBA Bit, 7-38, 7-40

DBB Bit, 7-37, 7-40

DBcc Instruction, 5-3

DBF Bit, 4-6, 10-6

DBFE Bit, 4-6, 4-25

DD Bits, 4-14, 4-31-4-33

INDEX-2


MOTOROLA

Destination Address Register, 6-3, 6-6, 6-9, 6-15,

6-18,6-20-6-21, 10-8, 10-9

Deterministic Opcode Tracking, 5-95, 5-121-5-123

DFC Bits, 6-18

Differences Between MC68020 Instruction Set and

MC68340 Instruction Set, 5-6

DIV Instructions, 5-46

DMA

Acknowledge Signals, 2-13, 6-2, 6-5, 6-8, 6-14-6-15

Capabilities, 6-1

Channel

Initialization, 6-3, 10-7

Operation Sequence, 6-2-6-3

Termination, 6-10,6-17

Done Signals, 2-14, 6-2, 6-6-6-7, 6-10, 6-14-6-15,

6-21

Programming Model, 6-11

Programming Sequence, 6-9

Request Signals, 2-13, 6-2, 6-4-6-9, 6-14-6-16

Transfer Types, 3-6

Transfers, Control of Bus, 6-6-6-7

Transfers, 32 Bits, 6-7

DONE Bit, 6-6, 6-8, 6-14, 6-16-6-17, 6-21

Double Bus Fault, 3-40, 3-43, 5-70, 5-97

Monitor, 3-41, 4-4, 4-6, 4-16

DSACK

Encoding, 3-6

Signals, 5-73, 10-13

DSCLK Signal, 5-100, 5-102-5-105

DSI Signal, 5-100, 5-102-5-105

DSIZE Bits, 6-3, 6-4, 6-6, 6-15, 10-8, 10-9

DSO Signal, 5-100,5-102-5-105

Dual-Address

Destination Write, 6-6

Mode, 6-6, 6-9, 6-14, 6-16, 6-22, 10-9

Source Read, 6-6

Du mp Memory Block Command, 5-115-5-116

Dynamic Bus Sizing, 3-6, 3-16

-E-

Early Bus Error, 3-36

EBI,4-2

ECO Bit, 6-4, 6-7, 6-14, 10-8

Effective Address

Extension Words, 5-16

Formats; 5-26

Effects of Wait States on Instruction Timing, 5-128

ERR Bit, 7-26,10-11

Error Status, Serial, 7-15

Event Counting, 8-16

Exception

Handler, 5-69, 5-80, 5-87, 5-89

Priorities, 5-68

Processing, 3-34, 5-5, 5-64

Faults, 5-85-5-86, 5-89-5-90

Sequence, 5-67

State, 5-8, 5-62

Stack Frame, 5-5, 5-64, 5-67

Vectors, 5-4, 5-64

Exception-Related Instructions and Operands Timing

Table, 5-149

EXTAL Pin, 2-9, 4-9, 10-2

External

Bus Interface, 4-2

Bus Master, 3-5, 3-17, 3-42-3-45, 4-6

DMA Request, 6-4, 6-6-6-7, 6-16

Exceptions, 5-67

Reset, 10-3

- F -

F-Line Instructions, 5-75

Fast Termination Timing, 3-17

Operation, 3-5, 3-16, 4-13, 4-30

DMA Transfers, 6-8

Fault

Address Register, 5-100

Correction, 5-86-5-89

Recovery, 5-80

Types, 5-83-5-86

FC Bits, 4-14, 4-30

FCM Bits, 4-14, 4-31

FE Bit, 7-14, 7-28, 7-32

Fetch Effective Address Instruction Timing Table,

5-136-5-137

FFULL Bit, 7-15, 7-29

FFULLA Signal, 7-8

Fill Memory Block Command, 5-117-5-118

FIRQ Bit, 4-4, 4-16, 4-20, 4-35, 10-6

FORCE_BGND,5-105

Format Error Exception, 5-74, 5-80

Four-Word Stack Frame, 5-80, 5-90

Framing Error, 7-13, 7-28

Freeze Operation, 4-17, 6-12, 8-20, 7-23

FREEZE Signal, 2-10, 4-17,5-98,5-100,5-105

Frequency Adjusted Signal

Skew, 10-17

Width, 10-16

Frequency Divider, 4-10

FRZ Bits, 4-17, 4-20,6-12,7-23,8-20,10-6, 10-7,

10-10, 10-11

FTE Bit, 4-13, 4-31

Full Format Instruction Word, 5-25

FUNC Bits, 5-83

Function Code 3, 6-8, 6-18

Encoding, 2-5, 3-4

Register, 6-3, 6-6-6-7, 6-18, 10-9

Signals, 2-5, 3-3, 3-17,5-63

-G-

Global Chip Select, 4-13, 4-14

GO Command, 5-100, 5-118

MOTOROLA


INDEX-3

-H-

Halt

Operation, 3-38, 3-39, 3-43

Signal, 2-9, 3-5, 3-14-3-16, 3-31, 3-34-3-40, 4-6,

5-70

Halted Processing State, 5-8, 5-62

Halted Processor Causes, 3-40

Timing, 3-41

Hardware Breakpoints, 5-73-5-74, 5-78, 5-82, 5-95

- 1 lACK Signals, 4-34

IARB Bits, 4-21,6-13,7-24,8-20,10-6,10-8,10-10,

10-12

ICCS Bit, 7-24, 10-10

IE Bits, 8-4, 8-8, 8-10, 8-22,10-12

IEC Bits, 7-37, 10-10

IEEE 1149.1

Capabilities, 9-1, 9-4

Implementation 9-2

Block Diagram, 9-2

Instruction Encoding, 9-3

Control Bits, 9-4

Restrictions, 9-11

IFETCH Signal, 5-95, 5-100, 5-121-5-122, 5-123

IL Bits, 7-24, 8-21, 10-12

Illegal Instruction Exception, 5-74-5-75, 5-78

1MB, 1-2,5-1

Immediate Arithmetic/Logical Instruction Timing

Table, 5-143

Immediate Data, 5-25

Implicit Reference Instructions, 5-18, 5-37

IN Bit, 5-82

Independent Variable, 8-Bit Tables, 5-57-5-59

Index

Register, 5-22

Scale, 5-22, 5-29, 5-31

Size, 5-22

Capture/Output Compare Mode, 8-3, 8-6-8-8

Input Port, 7-40

Change Register, 7-35

Instruction

Cycles, 5-134

Execution Overlap, 5-127

Execution Time Calculation, 5-129

Fetch Signal, 2-10

Format, 5-37

Heads, 5-127, 5-134

Pipe Signal, 2-10

Pipeline Operation, 5-124-5-125, 5-130

Pipeline Synchronization, 5-61

Register, 9-2, 9-3

Set Summary, 5-7

Stream Timing Examples, 5-131-5-134

Summary, 5-39-5-43

INDEX-4

Tails, 5-127, 5-134

Timing Table Overview, 5-134-5-136

Traps, 5-72-5-73

INTB Bit, 6-8, 6-14, 10-8

INTE Bit, 6-8, 6-14, 10-8

Integer Arithmetic Operations, 5-46-5-47

Internal

Autovector, 3-5, 3-30, 4-5-4-6, 4-21, 10-6

Bus Arbitration, 6-8-6-9

Bus Masters, 4-5, 6-13

Bus Monitor, 3-5, 3-34, 4-4, 4-6,4-16

Data Multiplexer, 3-7, 3-8

DMA Request, 6-4, 6-16

DSACK signals, 3-5, 3-14, 3-17, 3-25, 4-4,

4-13-4-14

Exceptions, 5-66

Interrupt

Acknowledge Arbitration, 4-6, 6-13, 7-20

Acknowledge CycleTypes, 3-29

Autovector, 3-30

Autovector, Timing, 3-33

Acknowledge Cycle, 5-79

Acknowledge Signals, 3-30

Arbitration, 4-4-4-6, 7-24

Enable Register, 7-4,7-39,10-10

Exception, 5-78-5-79

Flowchart, 3-31

Level Register, 7-24, 10-10

Mask, 5-78

Priority Mask, 5-11

Register, 6-13, 8-21, 10-8, 10-12

Request Signals, 2-5-2-6, 3-29, 3-30, 5-78, 6-14,

7 -4, 7-24, 7-39, 8-4, 8-8, 8-10

Status Register, 7-4, 7-26, 7-37, 7-39, 10-10

Terminated Normally, 3-29, 4-8

Timing, 3-32

Vector Register, 7-4, 7-20, 7-25, 10-10

INTL Bits, 6-13, 10-8

INTN Bit, 6-8, 6-14, 10-8

INTV Bits, 6-13, 10-8

IPIPE Signal, 5-95, 5-100, 5-122-5-123

IRQ Bit, 6-8, 6-17, 8-25

ISM Bits, 6-12, 10-7

IVR Bits, 7-25, 8-21, 10-12

- J -

JTAG,9-1

-L-

Late Bus Error, 3-36

Level 7 Interrupt, 5-80

LG Bit, 5-83

Limp Mode, 4-10, 4-28

LINK Instruction, 5-61


MOTOROLA

Local Loopback Mode, 7-16, 7-43

Location of Modules, 4-3

Logical Instructions, 5-47-4-48

Long-Word

Operands, 5-12

Read

8-Bit Port, Timing, 3-12


Write



Loop Mode Execution, 5-3-5-4

Loop Modes, 7-16-7-17

Loss of Crystal, 4-10, 4-29

Low Power Stop

Instruction, 5-1, 5-6, 5-36, 5-62, 5-78

Mode, 3-25, 4-12, 4-16, 4-29, 9-12, 10-6

LPSTOP Cycle, 3-25

-M-

MAID Bits, 6-13, 10-8

Maintaining Precision with Tables, 5-59-5-60

Master Station, 7-18

MC68681, 7-4, 7-39

Memory

Access Times, 10-14

Addressing Effective Address Mode, 5-26

Organization, 5-14

Memory-to-Memory Transfer, 6-4

Microbus Controller, 5-126

Microsequencer Operation, 5-124, 5-125

Misaligned Operands, 3-7, 3-8

MISC Bits, 7-31

MODCK Signal, 2-10, 4-7, 4-35

MODE Bits, 8-6, 8-8, 8-10, 8-11, 8-14, 8-16, 8-17,

8-23-8-24, 10-12

Mode Register 1, 7-14, 7-18, 7-20, 7-25, 7-38, 10-11

Mode Register 2, 7-4, 7-20, 7-43, 10-11

Module Base Address Register, 4-2, 4-19, 10-5

Access, 3-29

Module

Configuration Register, 4-20, 6-11, 7-23, 8-20, 10-6,

10-7, 10-10, 10-11

Locations, 4-3

MOVE Instruction Timing Table, 5-139

MOVEC Instruction, 5-74

MOVEM

Faults, 5-85, 5-88-5-89, 5-92

Instruction, 5-81

MOVEP Faults, 5-84-5-85, 5-87

MUL Instructions, 5-46

Multidrop Mode, 7-18-7-19, 7-26

Timing, 7-19

Multiprocessor Systems, 5-91

MV Bit, 5-81

MOTOROLA

-N-

Negate RTS Command, 7-33

Negative Tails, 5-130

Nested Subroutine Calls, 5-61

No Operation Command, 5-61, 5-121

Normal Processing State, 5-8, 5-62

- 0 -

OC Bits, 8-9-8-10, 8-24,10-12

OE Bit, 7-15, 7-28, 7-32

ON Bit, 8-6, 8-10, 8-11, 8-26

One Mode, 8-25

OPO, 7-42-7-43

OP1,7-42-7-43

OP4,7-41-7-43

OP6,7-41-7-43

Opcode Tracking in Loop Mode, 5-123

Operand

Faults, 5-84-5-85, 5-87, 5-92

Misalignment, 3-8

Size Field, 5-106

Operation Field, 5-105

OUT Bit, 8-7, 8-10, 8-26

Output Port

Control Register, 7-41,10-10

Data Register, 7-7, 7-8, 7-25, 7-42

Overrun Error, 7-13, 7-28

- p -

Packing and Unpacking of Operands, 6-22

Parity

Error, 7-13, 7-28

Mode, 7-26

Type, 7-26

PE Bit, 7-14, 7-28, 7-32

Pending Interrupt, 5-79

Period Measurement, 8-14

Periodic Interrupt

Control Register, 4-8, 4-26, 10-7

Generation, 8-6, 8-8, 8-10

Timer Register, 4-7, 4-27, 10-7

Timer, 4-4,4-7,4-16

Periodic Timer Period Calculation, 4-8

Phase Comparator, 4-10

Phase-Locked Loop, 4-9-4-10, 10-2, 10-3

PIROL Bits, 4-8, 4-26, 10-7

PITR Bits, 4-27, 10-7

PIV Bits, 4-26

PM Bits, 7-26,10-11

PO Bits, 8-27

Port A

Data Direction Register, 4-35

Data Register, 4-35


INDEX-5

Pin Assignment Register 1,4-34,10-7

Pin Assignment Register 2,4-34, 10-7

Pins

Functions, 4-14

Reset Value, 4-14

Assignment Encoding, 4-15, 4-34

Port B

Configuration, 4-4

Data Direction Register, 4-36

Data Register, 4-36

Functions, 4-4

Pin Assignment Register, 4-35,10-7

Pins

Functions, 2-5-2-6, 4-15

Reset Value, 4-15

Pin Assignment Encoding, 4-16, 4-35

Port Size, 3-5, 3-6, 4-13, 6-10, 6-18

Port Width, 3-1, 3-6, 3-8

POT Bits, 8-23, 10-12

Prefetch Controller, 5-126

Prefetch Faults, 5-84-5-85, 5-87,5-92

Preload Register 1, 8-6, 8-8-8-11, 8-27, 8-28,10-12

Preload Register 2, 8-10-8-11, 8-27, 8-28,10-12

Privilege Violations, 5-76, 5-78

Processor Clock Circuitry, 10-2

Program Control Instructions, 5-50-5-51

Program Counter, 5-11, 5-23, 5-32, 5-67, 5-70, 5-79,

5-98, 10-5

Indirect with Displacement Mode, 5-23

Indirect with Index Mode, 5-23

Program References, 5-16

Programming

After Startup, 10-5

Programming Model

CPU32, 5-9-5-10

DMA,6-11

Serial, 7-22

SIM,4-18

Timer, 8-19

Propagation Delays, 10-15

PS Bits, 4-13, 4-31-4-32

PSE Bit, 8-23, 10-12

PT Bit, 7-26, 10-11

PTP Bit, 4-7, 4-27, 10-7

Pulse-Width Measurement, 8-13

Pulse-Width Modulation, 8-6, 8-8

- Q -

Quad-Word Operands, 5-12

Queue Data Structures, 5-32, 5-34

R/F Bit, 7-26, 10-11

RIW Field, 5-106

-R-

RB Bit, 7-13, 7-14, 7-27

RC Bits, 7-34

RCS Bits, 7-30

Read

AID Register Command, 5-110

Cycle Word Read, Flowchart, 3-18

Interruption, 3-37, 3-45

Memory Location Command, 5-113-5-114

Modify Write Cycle, 5-82

Modify Write Faults, 5-84-5-85, 5-87

System Register Command, 5-98, 5-111-5-112

Read-Modify-Write Cycle Timing, 3-22

Retry Operation, 3-37

Operation, 3-4-3-5

Read-Modify Write Signal, 2-8, 3-21-3-23, 3-42, 3-44,

3-45,3-47

Read/Write Signal, 2-7, 3-2

Real-Time Clock, 4-9

Receive Data Signal, 2-12

Received Break, 7-13, 7-27, 7-38

Receiver, 7-10, 7-13

Baud Rates, 7-30

Buffer, 7-13, 7-15, 7-29, 7-34-7-35

Disable Command, 7-34

Enable Command, 7-34

FIFO, 7-13-7-15, 7-18, 7-25, 7-26, 7-29, 7-38-7-39

Holding Registers, 7-13

Ready Signal, 2-13

Shift Register, 7-13

Timing, 7-14

Register

Direct Mode, 5-19

Field, 5-106

Indirect Addressing Mode, 5-5, 5-28

Notations, 5-17

Released Write, 5-82, 5-83-5-84, 5-86-5-87

Remote Loopback Mode, 7-16, 7-43

REQ Bits, 6-4, 6-8, 6-14-6-16

Request to Send Signal, 2-12

Reset

Break-Change Interrupt, 7-32

Effect on DMA Transfers, 6-10

Error Status Command, 7-32

Exception, 5-69-5-70, 5-77

Instruction, 5-70, 5-120

Peripherals Command, 5-120-5-121

Operation, 3-47, 3-48

Receiver Command, 7-32

Signal, 2-8,3-47,3-48,5-69,5-95, 10-3,

Status Register, 4-3, 4-22

Types, 3-47

Timing, 3-49

Transmitter Command, 7-32

Values for Counter and Prescaler, 8-2

Vector, 5-4, 5-64, 5-65

Retry Bus Cycle Operation, 3-34, 3-36, 3-37

Timing, 3-39

Timing, Late Retry, 3-40

Return From Exception, 5-79-5-80

INDEX-6


MOTOROLA

Return Program Counter, 5-100

Returning From Background Mode, 5-100

RMW Bit, 5-82

ROM Interface, 10-4

RR Bit, 5-82

RS-232 Interface, 10-4

RSTEN Bit, 4-10,10-6

RTE Instruction, 5-64, 5-74, 5-80, 5-87

RTS Operation, 7-11, 7-25

RTSA Signal, 7-42

RTSB Signal, 7-42

RTSx Signal, 7-7, 7-11, 7-15, 7-23, 7-25, 7-33, 7-44

RW Bit, 5-82

RxDx Signal, 7-3, 7-6-7-7, 7-13, 7-16, 7-27

RxRDY Bit, 7-13, 7-15, 7-18, 7-27, 7-29

RxRDYA Bit, 7-39, 7-40

RxRDYA Signal, 7-8, 7-41

RxRDYB Bit, 7-38, 7-40

RxRTS Bit, 7-25, 10-11

- 5 -

SID Bit, 6-16,10-8,10-9

SAP I Bits, 6-3, 6-6, 6-15, 10-8, 10-9

Save and Restore Operations Timing Table, 5-150

SB Bits, 7-44, 10-11

SCLK Signal, 7-3, 7-6, 7-9, 7-24

SE Bit, 6-12,10-7

Selected Clock, 8-3

Serial

Clock Signal, 2-12

Command Control, 7-32

Communication Overview, 7-3

Compatibility with MC68681, 7-4

Crystal Oscillator, 7-3, 7-6

Diagnostic Functions, 7-16

Initialization, 10-10

Interface Timing, 5-103

Interface, 10-4

Maximum Data Transfer Rate, 7-2

Module

Capabilities, 7-2


Programming, 7-45-7-51

State Machine, 5-102-5-103

SFC Bits, 6-18

Shadowing, 8-6-8-7

SHEN Bits, 4-20-4-21

Shift and Rotate

Instructions, 5-48-5-49

Instruction Timing Table, 5-145-5-146

Show Cycles, 4-4, 4-20-4-21

Operation, 3-44, 3-45, 3-47

Signal Relationships to CLKOUT, 10-15

Signal Widths, 10-15

SIM

Configuration, 4-3


MOTOROLA

Single Address

Mode, 6-3, 6-7, 6-9, 6-12, 6-14, 6-16,10-8,10-18

Source Read, 6-7

Source Write, 6-7

Single Effective Address Instruction, 5-16, 5-25

Single Operand Instruction Timing Table,

5-144-5-145

Single Step Operation, 3-38

Six-Word Stack Frame, 5-80, 5-91

SIZ Bits, 5-83

Size

Signal Encoding, 2-7, 3-3

Signals, 2-7, 3-2, 3-7-3-13

Skew Between Outputs, 10-17

Slave Station, 7-18

SLIMP Bit, 4-9, 4-28

SLOCK, 4-10, 4-28

Software

Breakpoints, 5-73, 5-78, 5-82

Interrupt Vector Register, 4-7, 4-23, 10-6

Service Register, 4-7, 4-27

Watchdog

Clock Rate, 4-7

Operation, 4-4, 4-7, 4-16, 4-27

Service Routine, 4-7

Timeout, 4-24

Source Address Register, 6-3, 6-6-6-7,6-9,6-15,

6-18-6-19, 10-8, 10-9

Special Status Word, 5-71, 5-81

Special-Purpose MOVE Instruction Timing Table,

5-139-5-140

Spurious Interrupt, 3-31, 5-79

Monitor, 4-4, 4-6, 4-16

Square-Wave Generation, 8-6, 8-8

SRAM Interface, 10-3

SSIZE Bits, 6-3, 6-4, 6-6, 6-15,10-8,10-9

Stack

Data Structures, 5-32

Pointer, 5-11, 5-20, 5-32, 5-61, 10-5

Start Break Command, 7-33

Status Register, 3-3, 5-11, 5-14, 5-63, 5-67, 5-69, 5-70,

5-79, 7-11, 7-13, 7-27, 8-3, 8-25, 10-11

STEXT Bit, 4-12, 4-16, 4-29,10-6

Stop Bit, 7-13

Length, 7-44-7-45

Stop Break Command, 7-33

STOP Instruction, 4-16, 5-62, 5-78

Stop Module Operation, 6-11, 7-23, 8-20

Stopped Processing State, 5-62

STP Bit, 6-11, 7-23, 8-20, 10-7, 10-10, 10-11

STR Bit, 6-4, 6-8-6-10, 6-16, 6-17,6-18,6-21,10-8,

10-9

STSIM Bit, 4-12, 4-16, 4-29,10-6

Supervisor Privilege Level, 3-3, 5-8, 5-62, 5-63, 5-76

SUPV Bit, 4-21, 6-12, 7-24, 8-20,10-6,10-8,10-10,

10-12

Surface Interpolation with Tables, 5-61

SWE Bit, 10-6

SWP Bit, 4-7, 4-24, 4-27,10-7

SWR Bit, 8-6, 8-8, 8-22, 10-11, 10-12


INDEX-7

SWRI Bit, 4-7, 4-23, 10-6

SWT Bits, 4-7, 4-24, 10-6

Synchronous

Accesses, 3-5

Operation, 3-16

System

Clock, 8-3

Configuration and Protection, 4-3, 4-23

Control Instructions, 5-51-5-52

Protection and Control Register, 4-7, 10-6

Stack, 5-32

-T-

Table Lookup and Interpolate Instructions, 5-6, 5-36,

5-53-5-61

TC Bits, 7-33, 8-7, 8-26,10-11

TCK Signal, 2-11, 9-2, 9-11, 9-12

TCS Bits, 7-30

TDI Signal, 2-11, 9-2

TDO Signal, 2-11, 9-2, 9-4

Test Access Port, 9-1

TG Bit, 8-7, 8-26,10-11

TGE Bit, 8-7, 8-9, 8-11, 8-22, 10-12

TGL Bit, 8-7, 8-9, 8-26

Timeout, 8-2, 8-8, 8-10

Timer

Bypass, 8-17

Clock Selection Logic, 8-3

Compare Function, 8-3, 8-7, 8-9, 8-10, 8-12, 8-13,

8-15,8-17,8-27

Counter, 8-2

Counting Function, 8-14-8-17

Gate Signal, 2-14, 8-6, 8-8-8-17

Initialization, 10-11

Input Signal, 2-14, 8-3, 8-4

Interrupt Operation, 8-4, 8-21-8-22, 8-25-8-26

Output Signal, 2-14, 8-3, 8-6, 8-8-8-12, 8-17

Prescaler, 8-2


Uses, 8-2

Using to Compare Values, 8-6

TMS Signal, 2-11, 9-2

TO Bit, 8-26,10-11

Toggle Mode, 8-24

TP Bit, 5-81

TR Bit, 5-81

Trace

Exception, 5-76-5-78

Modes, 5-11 on Instruction Execution, 5-93

Tracing, 5-67, 5-69, 5-76-5-77, 5-81

Control Bits Encoding, 5-77

Transfer

Cases, 3-7

Mechanism, 3-7, 3-17-3-19

Transition to Background Mode, 5-98

Transmit

Data Signal, 2-12

Shift Register, 7-11

Transmitter, 7-10-7-11

Baud Rates, 7-31

Buffer, 7-11, 7-28, 7-35

Disable Command, 7-33

Enable Command, 7-33

Holding Register, 7-11, 7-28, 7-38

Ready Signal, 2-12

Timing, 7-12

TRAP Instruction, 5-72

Two-Clock Bus Cycles, 3-16, 10-4

TxCTS Bit, 7-44

TxDx Signal, 7-3, 7-6-7-7, 7-11, 7-16, 7-33

TxEMP Bit, 7-11, 7-28, 7-33

TxRDY Bit, 7-11, 7-28, 7-33, 7-35

TxRDYA Bit, 7-39, 7-40

TxRDYA Signal, 7-8, 7-41

TxRDYB Bit, 7-38, 8-40

TxRTS Bit, 7-44, 10-11

Types of DMA Interrupts, 6-8

-u-

Unimplemented Instructions, 5-36

Emulation, 5-94

Exception, 5-74-5-75, 5-78

UNLK Instruction, 5-61

Use of Chip Selects, 10-3

User

Privilege Level, 3-3, 5-8, 5-62, 5-63, 5-76

Stacks, 5-33

Using 8-Bit Boot ROM, 10-12

TGATE as an Input Port, 8-17

Table Lookup and Interpolate Instructions,

5-53-5-61

TOUT as an Output Port, 8-18

-v-

Bit, 4-13, 4-14, 4-19, 4-30

Variable Duty-Cycle Square-Wave Generator, 8-10

Variable-Width Single-Shot Pulse Generator, 8-11

VCCSYN, 2-14,4-10, 10-2-10-3

Vector Base Register, 5-4, 5-11, 5-64, 5-65, 5-70

Vector Numbers, 5-4, 5-65

Virtual Memory, 5-3

Voltage-Controlled Oscillator, 4-9-4-11, 4-28-4-29,

10-2

MOTOROLA

INDEX-8


-w-

W Bit, 4-9, 4-10, 4-28,10-6

Wait States, 3-15, 3-17, 3-19-3-22, 4-14

Wakeup Mode, 7-18

Word Operands, 5-12

WP Bit, 4-13, 4-30

Write

AID Register Command, 5-110-5-111

Cycle Word, Flowchart, 3-20

Memory Location Command, 5-114-5-115

System Register Command, 5-112-5-113

Write-Pending Buffer, 5-126

-x-

X Bit, 4-9, 4-11, 4-28, 10-6

X1 Signal, 2-11, 7-6

X2 Signal, 2-11, 7-6

XFC Pin, 2-9,4-10, 10-3

XTAL Pin, 2-9, 4-9, 10-2

XTAL_RDY Bit, 7-4, 7-29, 7-38, 7-39,10-10

- y -

Y Bits, 4-9, 4-10, 4-28, 10-6

Zero Mode, 8-24-8-25

-z-

MOTOROLA


INDEX-9

INDEX-10


MOTOROLA

NOTES

NOTES

NOTES

NOTES

Device Overview

Signal Descriptions

Bus Operation


CPU32


Serial Module

Timer Modules


Applications



Index

Device Overview

Signal Descriptions

Bus Operation

System Integration Module

CPU32

DMA Controller Module

Serial Module

Timer Modules

IEEE 1149.1 Test Access Port

Applications

Electrical Characteristics

Ordering Information and Mechanical Data

Index

A26290 PRINTED IN USA 9/90 EVANS PRESS EMTR 1148 20,000 MPU YGACAA

-

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

Order this document by MC68340UMAD/AD

MC68340

Errata to

MC68340 Integrated Processor User's Manual

January 24, 1991

This errata applies to the MC68340UM/AD, MC68340 Integrated Processor User's Manual. The following pages have been amended.

Page:

2-14 In paragraph 2.14.3, the following sentences should be added: "DONEx is an active input in any mode. As an output, DONEx is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode."

3-31

4-11

4-14

4-32

4-34

5-128

6-2

6-3

In Figure 3-14, the flowchart should be labeled "INTERRUPTING DEVICE-MC68340."

In Figure 4-4, the value of the resistor in series with the crystal should be 330 ohms. Also, the external pin labeled CLKOUT should be labeled EXTCLK.

The sentence under Internal DSACKx Generation for External Acesses with Programmable

Wait States should say, "DSACKx can be generated internally with up to three wait states for a particular device using the DO bits in the address mask register."

In paragraph 4.2.4.2, all references to CSO should be CSO. In the second paragraph after the first sentence, add, "Global chip select does not provide write protection and responds to all function codes."

Address mask register 2, bit 15 should be AM15; bit 2 should be DDQ..

In paragraph 4.3.5.2, the last sentence should say, "IACKx signals have the same timing as address~."

In paragraph 5.8.1.5, the first sentence should read, ''The CPU is capable of accessing onchip peripherals with an access time of two clocks."

In paragraph 6.1.3, the following sentences should be added: "DONEx is an active input in any mode. As an output, DONEx is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode."

In paragraph 6.2.1, the second sentence should say, ''This initialization is accomplished by programming the appropriate registers"

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

______________ ®

MOTOROLA -

@

MOTOROLA INC., 1991

6-12

6-13

6-14

6-16

7-8

7-15

7 -23

7-27

The first note should say, ''The DMA module uses only one

~ channel~.';

The SE bit description should be:

1 = In single-address mode,Jllil external data bus is driven during DMA transfer. o

= In single-address mode,..1I:m external data bus remains in a high-impedance state during a DMA transfer (used for intermodule DMA).

In dual-address mode, the SE bU has no effect

In paragraph 6.4.2, the reset value of bits 7-0 of the interrupt registers should be

OOOOllll. .

In the INTV bit description, the first sentence should be deleted.

In the ECO bit description, add the sentence, "If request generation is programmed to be internal, this bit has no effect." .

In Table 6-5, the BB bits should be labeled bit 3 and bit 2.

Replace. the entire STR bit description with the following:

STR Start

Internal Request

1 = Start DMA transfer. In internal request mode, the transfer· starts immediately when STR is set

0= The transfer can be stopped by clearing STR.

External Request

1 = Setting this bit enables the QMA to start the transfer when a "()'j3EQX input is

. received from an external device o

= The transfer can be stopped by clearing STR

The bit is .cleared by reset, writing a logic zero, the DONE status bit being set, or one of the error status bits (BES, BED, or CONF) being set.

Paragraph 7.2.12 should say, ''This active-low output signal is programmable as the channel

A transmitter ready or as a dedicated parallel output, and cannot be masked by the IER "

Paragraph 7.2.12.1 should read, "When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register (SRA)."

Paragraph 7.2.13 should read, "This active-low output signal is programmable as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output,

.aru! cannot be masked by the IER"

The first sentence in paragraph 7.2.13.1 should say, "When used for this function, this signal reflects the complement of the status of bit 0 of the ISR."

The first sentence in paragraph 7.2.13.2 should read, "When used for this function, this signal reflects the complement of the status of bit 1 of the ISA."

The second sentence in the fourth paragraph should say, "When in this mode, RTSx is automatically negated by the receiver when a valid start bit is detected and the FIFO stack is full."

The fifth sentence in the last paragraph should be deleted.

In paragraph 7.4.1.5, bit 4 in the register diagram should be labeled QE.

Errata-2

MC68340

MOTOROLA

8-19

8-21

9-3

9-4

9-5

In Figure 8-11, the fourth line should be labeled "Command Register (CR)."

Also in Figure 8-11, the address of preload 2 register for timer 2 should be

$~E.

In paragraph 8.4.3, the title should be, "Command Register (CR)."

In the third paragraph, the first sentence should say, "During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the standard 2-bit binary value

L01l into the two least significant bits and the loss-ot-crystal (LOC) status signal into bit 2."

In the second paragraph, the third sentence should be deleted.

Also in the second paragraph, the fourth sentence should read, "To ensure proper operation,

~

In the list of control bits following the fifth paragraph, bits 1 0 and 22 should be:

10. dQrla.ctl (83) 22.

~.ctl

(123)

The second sentence in the last paragraph should say, "For example, the active-high level

tor

.d.Qne..ctl (bit.am is logic one since the cell type is IO.Ctl1."

In Table 9-2, the following bit numbers require correction:

O.Latch

O.Latch

O.Latch

10.Ct11

10.~

10.Cell

I.Pin

O.Latch

I.Pin

10.Cell

10.Ct10

10.Ctl.Q.

10.Ctl.Q.

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

45

48

49

83

104

106

112

113

114

122

123

131

132

29

31

32

33

34

35

36

37

38

39

40

44

.Lfin tout2.ctl

RxDA

TxDA

RTSA

CTSA

RxRDYA

TxRDYA

RxO.6.

TxO.6.

RTS.B.

CTSa

DACKl

DONE1

DACK2

DONE2

Q.Q.M..ctl

DSACKO

RMC

BGACK

BG

BR

MooCK

~.ctl tout1.ctl

TGATE1

Input

Output

Output

Input

Output

Output

Input

Output

Output

Input

Output

00-/10

QJ.tlrutl

00-1/0

1/0**

1/0':'

Input

Output

Input

1/0

.Input

-

~

~ berr.ctl

-

ab.ctl

~.ctl

9-8

9-9

1 0-2

In Figure 9-3, the MUX output should be ".QAIA TO SYSTEM LOGIC."

In Figure 9-6, the

T input to the top, left-hand MUX should be

"D.AIa

FROM SYSTEM

LOGIC."

In Figure 10-2, the value of the resistor in series with the crystal should be 330 ohms.

MOTOROLA

MC68340

Errata-3

10-7 In paragraph 10.2.3, add the following sentence: "The DONEx pin requires an external pullup resistor even if operating only in the internal request mode."

12-5 The GND pins for internal only should be .l:i13, H3.

Index-8 TxRDYB bit should reference pages 7-38 and 1-40.

Motorola reserves the right to make changes without further notice to any products herein to Improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, Intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death assodated with such unintended or unauthorized use, even if such daim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the

Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Literature Distribution Centers:

USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.

EUROPE: Motorola ltd.; European Literature Center; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.

JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.

ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No.2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.,

Hong Kong.

_ ®

MOTOROLA

A26290-1 PRINTED IN USA 1/91 IMPERIAL LITHO C77282 18,000

-

MOTOROLA

SEMICONDUCTOR

TECHNICAL DATA

Order this document by MC68340UMAD/AD

MC68340

Errata to

MC68340 Integrated Processor User's Manual

January 24, 1991

This errata applies to the MC68340UM/AO, MC68340 Integrated Processor User's Manual. The following pages have been amended.

Page:

2-14 In paragraph 2.14.3, the following sentences should be added: "DONEx is an active input in any mode. As an output, DONEx is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode."

3-31

4-11

In Figure 3-14, the flowchart should be labeled "INTERRUPTING OEVICE-MC68340."

In Figure 4-4, the value of the resistor in series with the crystal should be 330 ohms. Also, the external pin labeled CLKOUT should be labeled EXTCLK.

4-14 The sentence under Internal DSACKx Generation for External Acesses with Programmable

Wait States should say, "DSACKx can be generated internally with up to three wait states for a particular device using the DO bits in the address mask register."

In paragraph 4.2.4.2, all references to CSO should be

cso.

In the second paragraph after the first sentence, add, "Global chip select does not provide write protection and responds to all function codes."

4-32

4-34

Address mask register 2, bit 15 should be AM15; bit 2 should be 00.0..

In paragraph 4.3.5.2, the last sentence should say, "IACKx signals have the same timing as address~."

5-128

6-2

6-3

In paragraph 5.8.1.5, the first sentence should read, "The CPU is capable of accessing onchip peripherals with an access time of two clocks."

In paragraph 6.1.3, the following sentences should be added: "DONEx is an active input in any mode. As an output, DONEx is only active in external request mode. An external pullup resistor is required even if operating only in the internal request mode."

In paragraph 6.2.1, the second sentence should say, ''This initialization is accomplished by programming the apprqprjate registers"

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

- _____________ ®

MOTOROLA _

©

MOTOROLA INC., 1991

6-12

6-13

6-14

6-16

7-8

7-15

7 -23

7 -27

The first note should say, ''The DMA module uses only one

SIE.

bit for both channels."

The SE bit description should be:

1

=

In single-address mode,..lOO external data bus is driven during DMA transfer. o

= In sjngle-address mode,..lOO external data bus remains in a high-impedance state during a DMA transfer (used for jntermodule PMA).

In dual-address mode, the SE bit has no effect

In paragraph 6.4.2, the reset value of bits 7-0 of the interrupt registers should be

00001lll..

In the INTV bit description, the first sentence should be deleted.

In the ECO bit description, add the sentence, "If request generation is programmed to be internal, this bit has no effect."

In Table 6-5, the BB bits should be labeled bit 3 and bit 2.

Replace the entire STR bit description with the following:

STR Start

Internal Request

1

=

Start DMA transfer. In internal reQuest mode, the transfer starts immediately when SIR is set

o

= The transfer can be stopped by clearing SIR

External Request

1 = Setting this bit enables the PMA to start the transfer when a 'j)BEOx input is received from an external device

o

= Ihe transfer can be stopped by clearing SIR

The bit is cleared by reset, writing a logic zero, the DONE status bit being set, or one of the error status bits (BES, BED, or CONF) being set.

Paragraph 7.2.12 should say, ''This active-low output signal is programmable as the channel

A transmitter ready or as a dedicated parallel output, and cannot be masked by the IER "

Paragraph 7.2.12.1 should read, "When used for this function, this signal reflects the complement of the status of bit 2 of the channel A status register (SRA)."

Paragraph 7.2.13 should read, "This active-low output signal is programmable as the channel A receiver ready, channel A FIFO full indicator, or a dedicated parallel output, ami. cannot be masked by the IER "

The first sentence in paragraph 7.2.13.1 should say,"When used for this function, this signal reflects the complement of the status of bit 0 of the ISA."

The first sentence in paragraph 7.2.13.2 should read, "When used for this function, this signal reflects the complement of the status of bit 1 of the ISA."

The second sentence in the fourth paragraph should say, "When in this mode, RTSx is automatically negated by the receiver when a yalid start bit is detected and the FIFO stack is full."

The fifth sentence in the last paragraph should be deleted.

In paragraph 7.4.1.5, bit 4 in the register diagram should be labeled QE.

Errata-2 MC68340 MOTOROLA

8-19

8-21

9-3

9-4

9-5

9-8

9-9

1 0-2

In Figure 8-11, the fourth line should be labeled "Command Register (CR)."

Also in Figure 8-11, the address of preload 2 register for timer 2 should be $61E.

In paragraph 8.4.3, the title should be, "Command Register (CR)."

In the third paragraph, the first sentence should say, "During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the standard 2-bit binary value !.Q.1l into the two least significant bits and the loss-of-crystal (LOC) status

Signal into bit 2."

In the second paragraph, the third sentence should be deleted.

Also in the second paragraph, the fourth sentence should read, "To ensure proper operation,

1b.a. open-drain pins require external pullups."

In the list of control bits following the fifth paragraph, bits 10 and 22 should be:

10 . .d..o.n.e..ctl (83) 22. m.o..d.ck.ctl (123)

The second sentence in the last paragraph should say, "For example, the active-high level for .d..o.n.e..ctl (bit am is logic one since the cell type is IO.Ctl1."

In Table 9-2, the following bit numbers require correction:

35

36

37

38

39

40

29

31

32

33

34

44

45

48

49

83

104

106

112

113

114

122

123

131

132

10.Ctlo.

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

O.Latch

I.Pin

O.Latch

O.Latch

O.Latch

O.Latch

IO.CtI1

10.~

10.Cell

I.Pin

O.Latch

I.Pin

10.Cell

10.Ct10

10.Ctlo.

LEin tout2.ctl

RxDA

TxDA

RTSA

CTSA

RxRDYA

TxRDYA

RxO.6.

TxO.6.

RTS.6.

CTS.6.

DACKl

DONEl

DACK2

DONE2

~ctl

DSACKO

RMC

BGACK

BG

BR

MooCK

~.ctl tout1.ctl

TGATEl

Input

Output

Output

Input

Output

Output

Input

Output

Output

Input

Output

00-1/0

Q!tlW!l

00-1/0

110··

1/0':

Input

Output

Input

1/0

Input

-

~

~ berr.ctl

ab.ctl

~.ctl

In Figure 9-3, the MUX output should be ".QAIA TO SYSTEM LOGIC."

In Figure 9-6, the

LOGIC."

T input to the top, left-hand MUX should be

"D.AIA

FROM SYSTEM

In Figure 1 0-2, the value of the resistor in series with the crystal should be 330 ohms.

MOTOROLA MC68340 Errata-3

10-7 In paragraph 10.2.3, add the following sentence: "The DONEx pin requires an external pullup resistor even if operating only in the internal request mode."

12-5 The GND pins for internal only should be .l:l.13, H3.

Index-8 TxRDYB bit should reference pages 7-38 and 1-40.

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