External Memory Interface Handbook

External Memory Interface Handbook
External Memory Interface Handbook Volume 1:
Introduction to Altera External Memory Interfaces
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_INTRO-1.1
Document Version:
Document Date:
1.1
January 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
Contents
Section Revision Dates
Section I. About This Handbook
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. How to Use this Handbook
Introduction to Altera External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device, Pin, and Board Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Implementing Altera Memory Interface IPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Simulation, Timing Analysis, and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Implementing a Custom PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Design Flow Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Recommended Design Flow
Select a Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Determine Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Perform Board-Level Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Device-Side Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Memory-Side Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Adjust Termination and Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Instantiate PHY and Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Verify Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Adjust Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Perform Timing Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Verify Design Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Design Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Glossary
Section II. Memory Standard Overviews
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. Selecting your Memory Component
Memory Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
DDR, DDR2, and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
RLDRAM and RLDRAM II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
QDR, QDR II, and QDR II+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Memory Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
High-Speed Memory in Embedded Processor Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
High-Speed Memory in Telecom Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Chapter 2. DDR, DDR2, and DDR3 SDRAM Overview
© January 2010
Altera Corporation
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
iv
DDR SDRAM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
DDR2 SDRAM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
DDR3 SDRAM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
DDR, DDR2 and DDR3 SDRAM Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
DDR, DDR2, and DDR3 SDRAM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Data, Data Strobes, DM, and Optional ECC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Address and Command Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
DIMM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. QDR II and QDR II+ SRAM Overview
QDR II+ and QDR II SRAM Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Command Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Address Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Data and QVLD Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Chapter 4. RLDRAM II Overview
RLDRAM II Interface Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Data, DM and QVLD Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Section III. System Performance Specifications
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. DDR SDRAM Specifications
Maximum Clock Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Maximum Number of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. DDR2 SDRAM Specifications
Maximum Clock Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Maximum Number of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. DDR3 SDRAM Specifications
Maximum Clock Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Maximum Number of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–4
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Chapter 4. QDR II and QDR II+ SRAM Specifications
Maximum Clock Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Maximum Number of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
Chapter 5. RLDRAM II Specifications
Maximum Clock Rate Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Maximum Number of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
© January 2010
Altera Corporation
v
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
© January 2010
Altera Corporation
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
vi
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
© January 2010
Altera Corporation
Section Revision Dates
The following table shows the revision dates for the sections in this volume.
Section
Version
Date
Part Number
About This Handbook
1.1
January 2010
EMI_INTRO_ABOUT-1.1
Memory Standard Overviews
1.1
January 2010
EMI_INTRO_OVER-1.1
System Performance Specifications
1.1
January 2010
EMI_INTRO_SPECS-1.1
© January 2010
Altera Corporation
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
viii
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
Section Revision Dates
© January 2010
Altera Corporation
Section I. About This Handbook
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_INTRO_ABOUT-1.1
Document Version:
Document Date:
1.1
January 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
About This Section
Revision History
The following table shows the revision history for this section.
Date
Version
January 2010
1.1
November 2009
© January 2010
1.0
Altera Corporation
Changes Made
■
Improved description for Implementing Altera Memory Interface IP chapter.
■
Added timing simulation to flow chart and to design checklist.
First published.
About This HandbookPreliminary
iv
About This Section
Revision History
About This Handbook
© January 2010
Preliminary
Altera Corporation
1. How to Use this Handbook
The External Memory Interface Handbook contains information that you require to
implement an external memory interface. The handbook focuses on the Altera®
solution for DDR, DDR2, DDR3 SDRAM; QDR II and QDR II+ SRAM; and RLDRAM
II interfaces. The handbook is organized with a typical design flow in mind, into the
following six volumes:
■
“Introduction to Altera External Memory Interfaces”
■
“Device, Pin, and Board Layout Guidelines”
■
“Implementing Altera Memory Interface IPs”
■
“Simulation, Timing Analysis, and Debugging”
■
“Implementing a Custom PHY”
■
“Design Flow Tutorials”
Introduction to Altera External Memory Interfaces
This volume includes this How to Use this Handbook chapter, recommended design
flow, and a glossary. In addition, this volume includes basic information for various
memory standards.
The Specifications section lists a complete scorecard of Altera device family support for
various memory standards.
Device, Pin, and Board Layout Guidelines
This volume describes the initial steps of selecting the correct Altera device with the
right resources and number of user I/O available for that interface.
The second section of the volume describes how you can select the correct termination
and drive strength based on your board simulation for DDR, DDR2, and DDR3
SDRAM interfaces. It offers board results correlated with board simulation and the
Altera recommended settings based on this correlation.
Implementing Altera Memory Interface IPs
This volume covers the following Altera memory IP products:
© January 2010
■
DDR and DDR2 SDRAM High Performance Controllers
■
DDR and DDR2 SDRAM High Performance Controllers II
■
DDR3 SDRAM High Performance Controllers
■
QDR II and QDR II+ SRAM Controllers with UniPHY
■
RLDRAM II Controllers with UniPHY
Altera Corporation
About This Handbook
Preliminary
1–2
Chapter 1: How to Use this Handbook
Simulation, Timing Analysis, and Debugging
Each IP has two modules: the PHY and the memory controller. The DDR, DDR2, and
DDR3 SDRAM high-performance controllers use the Altera ALTMEMPHY
megafunction for the PHY, which you can use standalone from the controller. The
QDR II, QDR II+, and RLDRAM II IP use the Altera UniPHY PHY.
The functional description of each of these modules is described separately so you do
not need to read the memory controller functional description if you are creating your
own custom memory controller.
The volume also contains information on how to implement the IP, including a
description of the parameterization GUI, the required constraints, and latency
information. The last chapter of this volume includes timing diagrams showing the
memory operations that may help you debug your system or help you create a
custom memory controller.
Simulation, Timing Analysis, and Debugging
When you have implemented your external memory interface, you can use this
volume for information on how to perform functional simulation, how to analyze
timing, and how to debug your design.
Implementing a Custom PHY
This volume describes the steps to create a custom PHY and offers examples on some
custom PHYs that are already available for some interfaces.
Design Flow Tutorials
This volume offers step-by-step tutorials in creating a memory interface for specific
Altera development boards for debugging and testing. In addition, this volume also
discusses special information such as how to implement external memory interfaces
using SOPC builder or how to implement multiple memory interfaces. The design
flow tutorials follow the flow in “Recommended Design Flow” on page 2–1.
About This Handbook
© January 2010
Preliminary
Altera Corporation
2. Recommended Design Flow
This chapter describes the Altera-recommended design flow for successfully
implementing external memory interfaces in Altera devices. Altera recommends that
you create an example top-level file with the desired pin outs and all interface IP
instantiated, which enables the Quartus® II software to validate your design and
resource allocation before PCB and schematic sign off. Use the “Design Checklist” on
page 2–6, to verify whether you have performed all the recommended steps in
creating a working and robust external memory interface.
Figure 2–1 shows the design flow to provide the fastest out-of-the-box experience
with external memory interfaces in Altera devices. This topic directs you where to
find information on how to perform each step of the recommended design flow. The
flow assumes that you are using Altera IP to implement the external memory
interface.
f
© January 2010
For design examples that follow the recommended design flow in this chapter, refer to
Volume 6: Design Flow Tutorials of the External Memory Interface Handbook.
Altera Corporation
About This Handbook
Preliminary
2–2
Chapter 2: Recommended Design Flow
Figure 2–1. External Memory Interfaces Design Flowchart
Select Device
Start Design
Instantiate
PHY and Controller
UniPHY-Based
Designs Only on Arria II GX
and Stratix IV Devices
Determine Board
Layout
SOPC Builder
Flow
Perform Board Level
Simulations
Adjust Termination
and Drive Strength
No
MegaWizard
Flow
Specify Parameters
Do Signals
Meet Electrical
Requirements?
Specify Parameters
Complete
SOPC Builder System
Yes
Optional
Perform
Functional Simulation
Yes
Does
Simulation Give
Expected Results?
Add Constraints and
Compile Design
Verify Timing
No
Does the
Design Have Positive
Margin?
Debug Design
Optional
Perform
Timing Simulation
Yes
Does
Simulation Give
Expected Results?
No
Adjust Constraints
Yes
Verify Design
Functionality on Board
Is Design Working?
No
Debug Design
Yes
No
Debug Design
Design Done
About This Handbook
© January 2010
Preliminary
Altera Corporation
Chapter 2: Recommended Design Flow
Select a Device
2–3
Select a Device
f
For more information on selecting a device, refer to the Device and Pin Planning section
in volume 2 of the External Memory Interface Handbook.
Determine Board Layout
Altera recommends prelayout SI simulations (line simulations) should take place
before board layout and that you use these parameters and rules during the initial
design development cycle. Advanced I/O timing and board trace models now
directly impact device timing closure.
In addition, the termination scheme that you use, the drive strength setting on the
FPGA, and the loading seen by the driver can directly affect the signal integrity. You
must understand the tradeoffs between the different types of termination schemes
and the effects of output drive strengths and loading, to choose the best possible
settings for your designs.
f
For more information, refer to the Board Layout Guidelines section in volume 2 of the
External Memory Interface Handbook.
Perform Board-Level Simulations
To determine the correct board constraints, perform board-level simulations to see if
the settings provide the optimal signal quality. With many variables that can affect the
signal integrity of the memory interface, simulating the memory interface provides an
initial indication of how well the memory interface performs. There are various EDA
simulation tools available to perform board-level simulations. The simulations should
be performed on the data, data strobe, control, command, and address signals. If the
memory interface does not have good signal integrity, adjust the settings, such as
drive strength setting, termination scheme or termination values to improve the
signal integrity (realize that changing these settings affects the timing and it may be
necessary to go back to the timing closure if these change).
f
For detailed information about understanding the different effects on signal integrity
design, refer to the Board Layout Guidelines section in volume 2 of the External Memory
Interface Handbook.
Enter topology information from your board-level simulations into the Quartus II
board trace model information. The typical information required includes, but is not
limited to, the following values:
© January 2010
■
Near and far trace lengths
■
Near and far trace distributed inductance
■
Near and far trace distributed capacitance
■
Near end deration capacitor values (if fitted)
■
Far end capacitive (IC) load
■
Far end termination values
Altera Corporation
About This Handbook
Preliminary
2–4
Chapter 2: Recommended Design Flow
Adjust Termination and Drive Strength
Device-Side Termination
Many Altera devices support both series and parallel OCT resistors to improve signal
integrity. OCT eliminates the need for external termination resistors on the FPGA
side, which simplifies board design and reduces overall board cost. You can
dynamically switch between the series and parallel OCT resistor depending on
whether the FPGA devices are performing a write or a read operation. The OCT
features offer user-mode calibration to compensate for any variation in VT during
normal operation to ensure that the OCT values remain constant. The parallel and
series OCT features are available in either 25 or 50  settings.
Memory-Side Termination
The DDR2, DDR3 SDRAM, and QDR II SRAM have a dynamic parallel ODT feature
that you can turn on when the FPGA is writing to the memory and turn off when the
FPGA is reading from the memory. To further improve signal integrity, DDR2
SDRAM supports output drive strength control so that the driver can better match the
transmission line. DDR3 SDRAM devices additionally support calibrated output
impedances.
f
For more information on available settings of the ODT, the output drive strength
features, and the timing requirements for driving the ODT pin, refer to your DDR2 or
DDR3 SDRAM datasheet.
Adjust Termination and Drive Strength
Although the recommended terminations are based on the simulations and
experimental results, you must perform simulations, either using I/O buffer
information specification (IBIS) or HSPICE models, to determine the quality of signal
integrity on your designs.
1
f
Any changes made to the board should also be made in the board trace model in the
Quartus II software.
For information on Altera-recommended terminations for memory interfaces, refer to
the Board Layout Guidelines section in volume 2 of the External Memory Interface
Handbook.
Instantiate PHY and Controller
After selecting the appropriate device and memory type, create a project in the
Quartus II software that targets the device and memory type.
When implementing external memory interfaces, Altera recommends that you use
Altera memory interface IP, which includes a PHY that you can use with the Altera
high-performance controller or with your own custom controller.
Instantiating the PHY and controller includes the following steps:
■
Specify parameters
■
Perform functional simulation
■
Add constraints and compile design
About This Handbook
© January 2010
Preliminary
Altera Corporation
Chapter 2: Recommended Design Flow
Verify Timing
2–5
f
For more information about specifying parameters, adding constraints, and
compiling, refer to the DDR and DDR2 SDRAM High-Performance Controller and
ALTMEMPHY IP User Guide section and the DDR3 SDRAM High-Performance
Controller and ALTMEMPHY IP User Guide section in volume 3 of the External Memory
Interface Handbook.
f
For more information about simulation, refer to the Simulation section in volume 4 of
the External Memory Interface Handbook.
Verify Timing
f
For more information about verifying timing, refer to the Timing Analysis section in
volume 4 of the External Memory Interface Handbook.
Adjust Constraints
In the timing report of the design, you can see the worst case setup and hold margin
for the different paths in the design. If the setup and hold margin are unbalanced,
achieve a balanced setup and hold margin by adjusting the phase setting of the clocks
associated with these paths.
For example, for the address and command margin, the address and command
outputs are clocked by an address and command clock that can be different with
respect to the system clock, which is –30°. The system clock controls the clock outputs
going to the memory. If the report timing script indicates that using the default phase
setting for the address and command clock results in more hold time than setup time,
adjust the address and command clock to be less negative than the default phase
setting with respect to the system clock, so that there is less hold margin. Similarly,
adjust the address and command clock to be more negative than the default phase
setting with respect to the system clock if there is more setup margin.
f
For more information on adjusting constraints, refer to the Timing Analysis section in
volume 4 of the External Memory Interface Handbook.
Perform Timing Simulation
This step is optional, but recommended to ensure that the IP is working properly. This
step only applies to UniPHY-based interfaces (on Arria® II GX and Stratix® IV devices
only), as ALTMEMPHY-based interfaces do not support timing simulation.
f
For more information about simulating, refer to the Simulation section in volume 4 of
the External Memory Interface Handbook.
Verify Design Functionality
Perform system level verification to correlate the system against your design targets,
using the Altera SignalTap® II logic analyzer.
f
© January 2010
For more information about using the SignalTap II analyzer, refer to the Debugging
section in volume 4 of the External Memory Interface Handbook.
Altera Corporation
About This Handbook
Preliminary
2–6
Chapter 2: Recommended Design Flow
Design Checklist
Design Checklist
This topic contains a design checklist that you can use when implementing external
memory interfaces in Altera devices.
Done
Select Device
1.

Select the memory interface frequency of operation and bus width.
For information about selecting memory, refer to the Memory Standard Overview
section in volume 1 of the External Memory Interface Handbook.
2.

Select the FPGA device density and package combination that you want to target.
For information about selecting an Altera device, refer to the Device and Pin Planning
section in volume 2 of the External Memory Interface Handbook.
3.

Ensure that the target FPGA device supports the desired clock rate and memory bus
width. Also the FPGA must have sufficient I/O pins for the DQ/DQS read and write
groups.
For detailed device resource information, refer to the relevant device handbook
chapter on external memory interface support.
For information about supported clock rates for external memory interfaces, refer to
the External Memory Interface System Specifications section in volume 1 of the
External Memory Interface Handbook.
Determine Board Layout
4.

Select the termination scheme and drive strength settings for all the memory
interface signals on the memory side and the FPGA side.
5.

Ensure you apply appropriate termination and drive strength settings on all the
memory interface signals, and verify using board level simulations.
6.

Use board level simulations to pick the optimal setting for best signal integrity. On
the memory side, Altera recommends the use of external parallel termination on
input signals to the memory (write data, address, command, and clock signals).
For information, refer to the Board Layout Guidelines section in volume 2 of the
External Memory Interface Handbook.
Perform Board Level Simulations
7.

Perform board level simulations, to ensure electrical and timing margins for your
memory interface
8.

Ensure you have a sufficient eye opening using simulations. Use the latest FPGA and
memory IBIS models, board trace characteristics, drive strength, and termination
settings in your simulation.
Any timing uncertainties at the board level that you calculate using simulations must
be used to adjust the input timing constraints to ensure the accuracy of Quartus II
timing margin reports. For example crosstalk, ISI, and slew rate deration.
For information, refer to the Board Layout Guidelines section in volume 2 of the
External Memory Interface Handbook.
Instantiate PHY and Controller
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© January 2010
Preliminary
Altera Corporation
Chapter 2: Recommended Design Flow
Design Checklist
2–7
Done
9.

Parameterize and instantiate the Altera external memory IP for your target memory
interface.
You have the following three choices in implementing a memory interface in the
Quartus II software:
■
Using the Altera memory controller and PHY.
For information about how to implement a specific memory interface, refer to
Volume 3: Implementing Altera Memory Interface IP of the External Memory
Interface Handbook.
The Parameter Settings chapter of each section describes the IP supported
features page by page.
■
Using the Altera PHY with your own custom controller.
For information about how to implement a specific memory interface, refer to
Volume 3: Implementing Altera Memory Interface IP of the External Memory
Interface Handbook.
The Parameter Settings chapter of each section describes the IP supported
features page by page. The Functional Description chapter describes the
workings of the PHY and how you can connect a custom controller to the PHY.
■
Implement a custom PHY and custom controller.
For information about creating custom IP, refer to Volume 5: Implementing
CustomMemory Interface PHY of the External Memory Interface Handbook.
10.
11.


Ensure that you perform the following actions:
■
Pick the correct memory interface data rates, width, and configurations.
■
For DDR, DDR2, and DDR3 SDRAM interfaces, ensure that you derate the tIS, tIH,
tDS, and tDH parameters, as necessary.
■
Include the board skew parameter for your board.
Connect the PHY's local signals to your driver logic and the PHY's memory interface
signals to top-level pins.
Ensure that the local interface signals of the PHY are appropriately connected to
your own logic. If the ALTMEMPHY megafunction is compiled without these local
interface connections, you may encounter compilation problems, when the number
of signals exceeds the pins available on your target device.
For more information about the example top-level file, refer to the Functional
Description chapter for the relevant memory controller.
You may also use the example top-level file as an example on how to connect your
own custom controller to the Altera memory PHY.
Perform Functional Simulation
12.

Simulate your design using the RTL functional model.
Use the IP functional simulation model with your own driver logic, testbench, and a
memory model, to ensure correct read and write transactions to the memory.
You may need to prepare the memory functional model by setting the speed grade
and device bus mode.
For more information about simulation, refer to the Simulation section in volume 4
of the External Memory Interface Handbook.
Add Contraints
© January 2010
Altera Corporation
About This Handbook
Preliminary
2–8
Chapter 2: Recommended Design Flow
Design Checklist
Done
13.

Add timing constraints. The wizard-generated .sdc file adds timing constraints to the
interface. However, you may need to adjust these settings to best fit your memory
interface configuration.
14.

Add pin settings and DQ group assignments. The wizard-generated .tcl file includes
I/O standard and pin loading constraints to your design.
15.

Ensure that generic pin names used in the constraint scripts are modified to match
your top-level pin names. The loading on memory interface pins is dependent on
your board topology (memory components).
16.

Add pin location assignments. However, you need to assign the pin location
assignments manually using the Pin Planner.
17.


Ensure that the example top-level file or your top-level logic is set as top-level entity.
18.
Adjust optimization techniques, to ensure the remaining unconstrained paths are
routed with the highest speed and efficiency:
a. On the Assignments menu click Settings.
b. Select Analysis & Synthesis Settings.
c. Select Speed under Optimization Technique.
d. Expand Fitter Settings.
e. Turn on Optimize Hold Timing and select All Paths.
f. Turn on Optimize Fast Corner Timing.
g. Select Standard Fit under Fitter Effort.
19.

Provide board trace delay model. For accurate I/O timing analysis, you specify the
board trace and loading information in the Quartus II software. This information
should be derived and refined during your board development process of prelayout
(line) simulation and finally post-layout (board) simulation. Provide the board trace
information for the output and bidirectional pins through the board trace model in
the Quartus II software.
For more information, refer to the Add Constraints chapter for the relevant memory
standard in volume 3 of the External Memory Interface Handbook or refer to Volume
6: Design Flow Tutorials.
Compile Design and Verify Timing
20.
21.
22.
23.


Compile your design and verify timing closure using all available models.


If there are timing violations, adjust your constraints to optimize timing
Run the wizard-generated <variation_name>_report_timing.tcl file, to generate a
custom timing report for each of your IP instances. Run this process across all
device timing models (slow 0C, slow 85C, fast 0C).
As required, adjust PLL clock phase shift settings or appropriate timing and location
assignments margins for the various timing paths within the IP.
For information, refer to the Timing Analysis section in volume 4 of the External
Memory Interface Handbook.
Perform Timing Simulation
About This Handbook
© January 2010
Preliminary
Altera Corporation
Chapter 2: Recommended Design Flow
Design Checklist
2–9
Done
24.

Perform gate-level or timing simulation to ensure that all the memory transactions
meet the timing specifications with the vendor's memory model. Timing simulation
is only supported with UniPHY-based memory interfaces.
For more information about simulation, refer to the Simulation section in volume 4
of the External Memory Interface Handbook.
Verify Design Functionality
25.

Verify the functionality of your memory interface in the system
For more information, refer to Volume 6: Design Flow Tutorials. in the External
Memory Interface Handbook.
© January 2010
Altera Corporation
About This Handbook
Preliminary
2–10
Chapter 2: Recommended Design Flow
Design Checklist
About This Handbook
© January 2010
Preliminary
Altera Corporation
3. Glossary
This chapter lists the definitions of the terms that the Altera external memory
interfaces solutions use.
Table 3–1 shows a glossary of terms.
Table 3–1. Glossary of Terms (Part 1 of 3)
Term
Description
×36 emulation
A QDR II or QDR II+ SRAM implementation to support ×36 QDR II and QDR II+ SRAM
devices with Stratix III or Stratix IV devices that do not support ×36 DQS groups. Two ×18
DQS groups are combined to emulate the ×36 group. The CQ and CQn signals have to be split
on the board to go to the DQS and CQn pins of the two ×18 DQS groups.
Advanced I/O timing
Advanced I/O timing allows the TimeQuest timing analyzer to produce enhanced timing
reports based on the board layout information included in the design. Use advanced I/O
timing with the board trace model.
Altera PHY interface (AFI)
The bus that connects calibrated PHYs with the Altera memory controller IP.
ALTMEMPHY megafunction
The Altera PHY IP that the high-performance controllers use. The latest generation PHY is the
UniPHY IP.
Board trace model
The board trace model in the Quartus II software includes the board termination, trace length,
and impedance in the project so that TimeQuest can produce enhanced timing reports with
the included board information. You must have the advance I/O timing enabled when using he
board trace model.
Calibration
The process of setting up the initial relationship between clocks. For example, the
resynchronization window to provide the greatest timing margin in DDR, DDR2, and DDR3
SDRAM interfaces in Altera devices. The initial calibration is done only once at system reset
after device initialization is complete.
Cascaded PLLs
A scheme whereby the clock for the PLL in the memory interface IP comes from another PLL.
For more information about cascaded PLLs, refer to the Device and Pin Planning section in
volume 2 of the External Memory Interface Handbook.
Cascaded
A signal topology, in which a signal is routed from one component to the next in series, but is
buffered by each component.
Column address strobe
(CAS)
A signal sent from a memory controller to a DRAM circuit to indicate the column address
lines are valid.
Complementary clocks
A clocking scheme where only the rising edges of a clock and its inverted clock clock double
data rate data into a device, for example on QDR II and QDR II+ SRAM interfaces.
Daisy-chain
A routing topology in which a single trace is routed from one component to the next, and so
on, in series to the last component.
DDR
Double data-rate transfer, where data is latched and sent at both rising and falling edges of
the (accompanying) clock. Operates at the full-rate clock frequency (twice the width of SDR
data).
DDR3 SDRAM with leveling
A standard DDR3 SDRAM topology that requires the use of the ALTMEMPHY megafunction
with read and write leveling. DDR3 SDRAM with levelling applies to any DDR3 DIMM
interfaces.
DDR3 SDRAM without
leveling
A non standard topology with synchronous DDR2-like balanced address, command, and
clock layout.
© January 2010
Altera Corporation
About This Handbook
Preliminary
3–2
Chapter 3: Glossary
Table 3–1. Glossary of Terms (Part 2 of 3)
Term
Description
Deskew
Aligning the data signals with respect to the clock signal to compensate for the skew between
the data and clock signals, by using the delay chains in the IOEs.
Fly-by topology
When the termination is placed after the component at the end of the line.
Full-rate clock
Clock with a frequency that is equal to the frequency of the memory interface clock.
Full-rate controller
A memory controller implemented as a full-rate design.
Full-rate design
A variation of the memory interfaces where the clock frequency of the controller and
user-interface logic is the same as the memory interface clock (refer to Figure 3–1).
Half data rate (HDR)
Data that changes on one edge of the half-rate clock (twice the width of DDR data and four
times the width of SDR data).
Half-rate clock
Clock with a frequency that is half the frequency of the memory interface clock.
Half-rate controller
A memory controller implemented as a half-rate design.
Half-rate design
A variation of the memory interface where the clock frequency of the controller and
user-interface logic is half of the memory interface clock frequency (refer to Figure 3–1).
High-performance
controller
Altera memory controller that uses the ALTMEMPHY megafunction for the datapath. Altera
offers the high-performance controller for DDR, DDR2, and DDR3 SDRAM interfaces.
High-performance
controller II
Latest version of the Altera memory controller for DDR, DDR2, and DDR3 interfaces. Several
new features, including command look-ahead, which improves interface efficiency.
Hybrid
Obsolete term for wraparound I/Os.
Legacy controller
The legacy integrated static datapath and controller MegaCore® functions with no support for
calibration and tracking. For more information about legacy integrated static datapath and
controller MegaCore functions, refer to the DDR and DDR2 SDRAM Controller Compiler User
Guide, QDR II SRAM Controller MegaCore Function User Guide, and RLDRAM II Controller
MegaCore Function User Guide.
Memory pessimism
removal (MPR)
Memory chip calibration—when the PHY calibrates some portion of the JEDEC variation.
Multiple chip select and
multiple rank
Multiple chip select is the general term, whereas multple rank is reserved for DIMMs. A rank
refers to a group of DRAM components. Each rank has an individual CS signal. When there
are N such ranks in a system, it is referred to as multiple rank.
Non-AFI
The legacy interface standard between the controller and PHY. Not recommended for new
designs.
On-chip termination (OCT)
An FPGA device feature that eliminates the need for external resistors for termination. The
ALTMEMPHY megafunction supports dynamic OCT for DDR2 and DDR3 SDRAM variations
for Altera devices and static OCT for QDR II and QDR II+ SRAM and RLDRAM II variations.
On-die termination (ODT)
A memory vendor device feature equivalent to Altera’s OCT.
Planar
Topology of some DIMM raw cards.
Quad data rate (QDR)
Two data writes and two data reads per memory clock cycle.
RLDRAM II
A DDR memory standard that has reduced latency and simpler bank management compared
to the DDR, DDR2, or DDR3 SDRAM memory standard.
RLDRAM II CIO
A variant of the RLDRAM II devices that uses common I/O pins for read and write data pins.
RLDRAM II SIO
A variant of the RLDRAM II devices that uses separate I/O pins for read and write data pins.
Row address strobe (RAS)
A signal sent from a memory controller to a DRAM circuit to indicate the row address lines
are valid.
RUP and RDN pins
Reference pins for the OCT block.
Sequencer
The logic block that performs calibration and tracking operations.
About This Handbook
© January 2010
Preliminary
Altera Corporation
Chapter 3: Glossary
3–3
Table 3–1. Glossary of Terms (Part 3 of 3)
Term
Description
Signal splitter
The ablility of the Stratix III and Stratix IV DDIO output to feed both the positive and negative
legs of the differential I/O pins.
SDR
Data that changes on one edge of the full-rate clock.
T topology
A tree-type topology with balanced routing as used on DDR2 SDRAM DIMMs for address and
command signals.
Tracking
Performed as a background process during device operation, to track voltage and
temperature (VT) variations to maintain the data valid window that was achieved at
calibration. Only applies to DDR, DDR2, and DDR3 SDRAM interfaces.
UniPHY
The latest generation Altera PHY IP.
Wraparound interface
Previously referred to as hybrid memory interface. A memory interface where the read or
write or bidirectional datapath is split across the top or bottom and left or right of the device.
However, a read datapath on one edge and a write datapath on an adjacent edge is not
classed as a wraparound interface.
ZQ calibration
The DDR commands that calibrate the DDR3 SDRAM component ODT values.
Figure 3–1 shows the differences in the datapath width and frequency at which data is
handled between full-rate and half-rate controllers.
Figure 3–1. Full-Rate and Half-Rate Controller Description
Memory
Full Rate Design
8
DDR
16
to SDR
User
Logic
FPGA
DDR
200 MHz
SDR
200 MHz
Memory
Half Rate Design
8
DDR
16
to SDR
SDR
to HDR
32
User
Logic
FPGA
200 MHz
DDR
© January 2010
200 MHz
SDR
Altera Corporation
100 MHz
HDR
About This Handbook
Preliminary
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Chapter 3: Glossary
About This Handbook
© January 2010
Preliminary
Altera Corporation
Section II. Memory Standard Overviews
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_INTRO_OVER-1.1
Document Version:
Document Date:
1.1
January 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
About This Section
Revision History
The following table shows the revision history for this section.
Date
Version
Changes Made
January 2010
1.1
Corrected minor typos.
November 2009
1.0
First published.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
iv
About This Section
Revision History
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
1. Selecting your Memory Component
This chapter details some of the high-speed memory selection criteria and describes
some typical applications where these memories are used. It looks at the main types of
high-speed memories available, memory selection based on strengths and
weaknesses, and which Altera® FPGAs these devices can interface with. It concludes
with some typical application examples.
This chapter highlights the memory component's capability. The Altera IP may or
may not support all of the features supported by the memory.
f
For the maximum supported performance supported by Altera FPGAs, refer to the
External Memory Interface System Specifications section in volume 1 of the External
Memory Interface Handbook.
System architects must resolve a number of complex issues in high-performance
system applications that range from architecture, algorithms, and features of the
available components. Typically, one of the fundamental problems in these
applications is memories, as the bottlenecks and challenges of system performance
often reside in its memory architecture. As higher speeds become necessary for
external memories, signal integrity gets more difficult. Newer devices have added
several features to overcome this issue. Altera FPGAs also support these
advancements with dedicated I/O circuitry, various I/O standard support, and
specialized intellectual property (IP).
Memory Overview
The main considerations for choosing an external memory device are bandwidth, size,
cost, latency, and power. Since no single memory type can excel in every area, system
architects must determine the right balance for their design.
There are two common types of high-speed memories: DRAM and SRAM. DRAM
devices are volatile memories offering a lower cost per bit than SRAM devices. A
compact memory cell consisting of a capacitor and a single transistor makes this
possible, as opposed to the six-transistor cell used in SRAM. However, as the
capacitor discharges, the memory cell loses its state. This means that DRAM memory
must be refreshed periodically, resulting in lower overall efficiency and more complex
controllers. Generally, designers only choose DRAM where cost per bit is important.
DDR, DDR2, and DDR3 SDRAM
The desktop computing market has positioned double data rate (DDR) SDRAM as a
mainstream commodity product, which means this memory is very low-cost. DDR
SDRAM is also high-density and low-power. Relative to other high-speed memories,
DDR SDRAM has higher latency-they have a multiplexed address bus, which reduces
the pin count (minimizing cost) at the expense of a longer and more complex bus
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
1–2
Chapter 1: Selecting your Memory Component
Memory Selection
cycle. DDR2 SDRAM includes additional features such as increased bandwidth due to
higher clock speeds, improved signal integrity on DIMMs with on-die terminations,
and lower supply voltages to reduce power. DDR3 SDRAM is the latest generation of
SDRAM and further increases bandwidth, lowers power, and improves signal
integrity with fly-by and dynamic on-die terminations.
RLDRAM and RLDRAM II
Reduced latency DRAM (RLDRAM) is optimized to reduce latency primarily for
networking and cache applications. RLDRAM is partitioned into eight smaller banks.
This partioning reduces the parasitic capacitance of the address and data lines,
allowing faster accesses and reducing the probability of random access conflicts. Also,
most DRAM memory types need both a row and column phase on a multiplexed
address bus to support full random access, while RLDRAM supports a
non-multiplexed address, saving bus cycles at the expense of more pins. RLDRAM
utilizes higher operating frequencies and uses the 1.8V High-Speed Transceiver Logic
(HSTL) standard with DDR data transfer to provide a very high throughput.
RLDRAM II offers faster random access times, on-die termination, a delay-locked
loop (DLL) for higher frequency operation, larger densities, wider data paths, and
higher bus utilization compared with RLDRAM.
QDR, QDR II, and QDR II+ SRAM
SRAMs are fundamentally different from DRAMs in that a typical SRAM memory cell
consists of six transistors, while a DRAM cell consists of a transistor and a capacitor
used to store a charge. Inherently, SRAM is a low-density, high-power memory
device, with very low latency compared to DRAM (as the capacitor in the DRAM is
slow). In most cases, SRAM latency is one clock cycle.
Quad Data Rate (QDR) SRAM has independent read and write ports that run
concurrently at double data rate. QDR SRAM is true dual-port (although the address
bus is still shared), which gives this memory a significantly higher bandwidth. QDR
SRAM is best suited for applications where the required read/write ratio is near
one-to-one. QDR II SRAM includes additional features such as increased bandwidth
due to higher clock speeds, lower voltages to reduce power, and on-die termination to
improve signal integrity. QDR II+ SDRAM is the latest and fastest generation.
Memory Selection
One of the first considerations in choosing a high-speed memory is data bandwidth.
Based on the system requirements, an approximate data rate to the external memory
should be determined. Table 1–1 details the memory bandwidth for various
technologies with the assumptions of a 32-bit data bus, operating at the maximum
supported frequency in a Stratix® IV FPGA. The bandwidth column in this table
includes a conservative DRAM bandwidth at 70 percent efficiency, which takes into
consideration bus turnaround, refresh, burst length, and random access latency. The
calculation assumes 85 % efficiency for QDR and QDR II SRAM.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 1: Selecting your Memory Component
Memory Selection
1–3
Table 1–1. Memory Bandwidth for 32-bit Wide Data Bus in Stratix IV FPGA
Clock Frequency (MHz)
Bandwidth for 32 bits
(Gbps)
Bandwidth at % Efficiency (Gbps)
(1)
DDR3 SDRAM
533
34.1
23.9
DDR2 SDRAM
400
25.6
17.9
DDR SDRAM
200
12.8
9
RLDRAM II
400
25.6
17.9
QDR SRAM
200
25.6
21.8
Memory
QDR II SRAM
350
44.8
38.1
QDR II+ SRAM
350
44.8
38.1
Note to Table 1–1:
(1) 70% for DDR memories, 85% for QDR memories
You must also consider other memory attributes, including how much memory is
required (density), how much latency can be tolerated, what is the power budget, and
whether the system is cost sensitive. Table 1–2 is an overview of high-speed
memories, and details some of the features and target markets of each technology.
Table 1–2. Memory Selection Overview
Parameter
DDR3 SDRAM
DDR2 SDRAM
DDR SDRAM
RLDRAM II
QDR II/+ SRAM
Performance
400–800 MHz
200–400 MHz
100–200 MHz
200–533 MHz
154–350 MHz
Altera-supported
data rate
Up to 1066 Mbps
Up to 800 Mbps
Up to 400 Mbps
Up to 2132 Mbps
Up to 1400 Mbps
Density
512 Mbytes–
8 Gbytes,
32 Mbytes –
8 Gbytes (DIMM)
256 Mbytes–
1 Gbytes,
32 Mbytes –
4 Gbytes (DIMM)
128 Mbytes–
1 Gbytes,
32 Mbytes –
2 Gbytes (DIMM)
288 Mbytes,
576 Mbytes
8–72 Mbytes
I/O standard
SSTL-15 Class I, II SSTL-18 Class I, II SSTL-2 Class I, II
HSTL-1.8V/1.5V
HSTL-1.8V/1.5V
Data width (bits)
4, 8, 16
9, 18, 36
8, 9, 18, 36
4, 8, 16
4, 8, 16, 32
Burst length
8
4, 8
2, 4, 8
2, 4, 8
2, 4
Number of banks
8
8 (>1 GB), 4
4
8
N/A
Row/column
access
Row before
column
Row before
column
Row before
column
N/A
Row and column
together or
multiplexed option
CAS latency (CL)
5, 6, 7, 8, 9, 10
3, 4, 5
2, 2.5, 3
4, 6, 8
N/A
Posted CAS
additive latency
(AL)
0, CL-1, CL-2
0, 1, 2, 3, 4
N/A
N/A
N/A
Read latency (RL)
RL = CL + AL
RL = CL + AL
RL = CL
RL = CL/CL + 1
1.5 clock cycles
On-die termination Yes
Yes
No
Yes
Yes
Data strobe
Differential
bidirectional
strobe only
Differential or
single-ended
bidirectional
strobe
Single-ended
bidirectional
strobe
Free-running
differential read
and write clocks
Free-running read
and write clocks
Refresh
requirement
Yes
Yes
Yes
Yes
No
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
1–4
Chapter 1: Selecting your Memory Component
High-Speed Memory in Embedded Processor Application Example
Table 1–2. Memory Selection Overview
Parameter
DDR3 SDRAM
DDR2 SDRAM
DDR SDRAM
Relative cost
comparison
Presently lower
than DDR2
Less than DDR
Low
SDRAM with
market acceptance
Target market
Desktops, servers,
storage, LCDs,
displays,
networking, and
communication
equipment
Desktops, servers,
storage, LCDs,
displays,
networking, and
communication
equipment
Desktops, servers,
storage, LCDs,
displays,
networking, and
communication
equipment
RLDRAM II
QDR II/+ SRAM
Higher than DDR
SDRAM,
less than SRAM
Highest
Main memory,
cache memory,
networking,
packet processing,
and traffic
management
Cache memory,
routers, ATM
switches, packet
memories, lookup,
and classification
memories
Altera supports these memory interfaces, provides various IP for the physical
interface and the controller, and offers many reference designs (refer to Altera’s
Memory Solutions Center).
f
For Altera support and the maximum performance for the various high-speed
memory interfaces, refer to the External Memory Interface System Specifications section
in volume 1 of the External Memory Interface Handbook.
High-Speed Memory in Embedded Processor Application Example
In embedded processor applications—any system that uses processors, excluding
desktop processors—DDR SDRAM is typically used for main memory due to its very
low cost, high density, and low power. Next-generation processors invest a large
amount of die area to on-chip cache memory to prevent the execution pipelines from
sitting idle. Unfortunately, these on-chip caches are limited in size, as a balance of
performance, cost, and power must be taken into consideration. In many systems,
external memories are used to add another level of cache. In high-performance
systems, three levels of cache memory is common: level one (8 Kbytes is common)
and level two (512 Kbytes) on chip, and level three off chip (2 Mbytes).
High-end servers, routers, and even video game systems are examples of
high-performance embedded products that require memory architectures that are
both high speed and low latency. Advanced memory controllers are required to
manage transactions between embedded processors and their memories. Altera
Arria® series and Stratix series FPGAs optimally implement advanced memory
controllers by utilizing their built-in DQS (strobe) phase shift circuitry. Figure 1–1
highlights some of the features available in an Altera FPGA in an embedded
application, where DDR2 SDRAM is used as the main memory and QDR II SRAM or
RLDRAM II is an external cache level.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 1: Selecting your Memory Component
High-Speed Memory in Telecom Application Example
1–5
Figure 1–1. Memory Controller Example Using FPGA
533-Mbps DDR2 SDRAM (1)
DDR2 SDRAM
DIMM
IP available for processor interfaces
such as PowerPC, MIPs, and ARM
Embedded
processor
Altera
FPGA
DDR2 Interface
Processor
Interface
Memory
controller
PCI interface
PCI Master/Target cores capable of
64-bit, 66-MHz 1361 LEs,
4% of an EP2S30
Memory Interface
350-MHz embedded SRAM (2)
600-Mbps RLDRAM II (3)
or 1-Gbps QDR II SRAM (4)
RLDRAM II or
QDR II SRAM
[
Notes to Figure 1–1:
(1) 533-Mbps DDR2 SDRAM operation using dedicated DQS circuitry, post-amble circuitry, automatic phase shifting, and six registers in the I/O
element: 790 LEs, 3% of an EP2S30, and four clock buffers (for a 72-bit interface).
(2) High-speed memory interfaces such as QDR II SRAM require at least four clock buffers to handle all the different clock phases and data directions.
(3) 600-Mbps RLDRAM II operation: 740 logic elements (LEs), 3% of an EP2S30, and four clock buffers (for a 36-bit wide interface).
(4) Embedded SRAM with features such as true-dual port and 350-MHz operation allows complex “store and forward” memory controller
architectures.
(5) The Quartus II software reports the number of adaptive look-up tables (ALUTs) that the design uses in the FPGA. The LE count is based on this
number of ALUTs.
One of the target markets of RLDRAM II and QDR/QDR II SRAM is external cache
memory. RLDRAM II has a read latency close to SSRAM, but with the density of
SDRAM. A 16 times increase in external cache density is achievable with one
RLDRAM II versus that of SSRAM. In contrast, consider QDR and QDR II SRAM for
systems that require high bandwidth and minimal latency. Architecturally, the
dual-port nature of QDR and QDR II SRAM allows cache controllers to handle read
data and instruction fetches completely independent of writes.
High-Speed Memory in Telecom Application Example
Because telecommunication network architectures are becoming more complex,
high-end network systems are running multiple 10-Gbps line cards that connect to
multi-shelf switch fabrics scaling to Terabits per second. Figure 1–2 shows an example
of a typical system line interface card. These line cards offer interfaces ranging from a
single-port OC-192 to multi-port Gigabit Ethernet, and consist of a number of devices,
including a PHY/framer, network processors, traffic managers, fabric interface
devices, and high-speed memories.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
1–6
Chapter 1: Selecting your Memory Component
High-Speed Memory in Telecom Application Example
Figure 1–2. Typical Telecom System Line Interface Card
Telecom line card datapath
Lookup
table
Coprocessor
Lookup
table
Buffer
memory
Pre-processor
Buffer
memory
Buffer
memory
Network
processor
Traffic
manager
PHY/
framer
Pre-processor
Buffer
memory
Network
processor
Traffic
manager
Buffer
memory
Buffer
memory
Switch fabric
interface
As packets traverse from the PHY/framer device to the switch fabric interface, they
are buffered into memories, while the data path devices process headers (determining
the destination, classifying packets, and storing statistics for billing) and control the
flow of packets into the network to avoid congestion. Typically DDR/DDR2/DDR3
SDRAM and RLDRAM II are used for large buffer memories off network processors,
traffic managers, and fabric interfaces, while QDR and QDR II SRAMs are used for
look-up tables (LUTs) off preprocessors and coprocessors.
In many designs, FPGAs connect devices together for interoperability and
coprocessing, implement features that are not supported by ASIC devices, or
implement a device function entirely. Altera Stratix series FPGAs implement traffic
management, packet processing, switch fabric interfaces, and coprocessor functions,
using features such as 1 Gbps LVDS I/O, high-speed memory interface support,
multi-gigabit transceivers, and IP cores. Figure 1–3 highlights some of these features
in a packet buffering application where RLDRAM II is used for packet buffer memory
and QDR II SRAM is used for control memory.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 1: Selecting your Memory Component
High-Speed Memory in Telecom Application Example
1–7
Figure 1–3. FPGA Example in Packet Buffering Application
RLDRAM II
Altera
FPGA (1)
RLDRAM II
Interface (2)
Dedicated SERDES and DPA (3)
SP14.2i
RX
Differential termination (4)
Core
logic
PCI
Interface (6)
SP14.2i
TX (5)
QDRII SRAM
Interface (7)
QDRII SRAM
Notes to Figure 1–3:
(1) As an example, 85% of the LEs still available in an EP2S90.
(2) 600-Mbps RLDRAM II operation: 740 LEs, 1% of an EP2S90, and four clock buffers (for a 36-bit wide interface).
(3) Dedicated hardware SERDES and DPA circuitry allows clean and reliable implementation of 1-Gbps LVDS.
(4) Differential termination is built in Stratix FPGAs, simplifying board layout and improving signal quality.
(5) SPI 4.2i core capable of 1 Gbps: 5178 LEs per Rx, 6087 LEs per Tx, 12% of an ES2S90, and four clock buffers (for both directions using individual
buffer mode, 32-bit data path, and 10 logical ports).
(6) PCI cores capable of 64-bit 66-MHz 656 LEs, 1% of an EP2S90 for a 32-bit target
(7) 1-Gbps QDR II SRAM operation: 100 LEs, 0.1% of an EP2S90, and four clock buffers (for an 18-bit interface).
(8) Note that the Quartus II software reports the number of ALUTs that the design uses in Stratix II devices. The LE count is based on this number of
ALUTs.
SDRAM is usually the best choice for buffering at high data rates due to the large
amounts of memory required. Some system designers take a hybrid approach to the
memory architecture, using SRAM to store the packet headers and DRAM to store the
payload. The depth of the memories depends on the architecture and throughput of
the system.
The buffer memory for the packet buffering application of an OC-192 line card
(approximately 10 Gbps) must be able to sustain a minimum of one write and one
read operation, which requires a memory bandwidth of 20 Gbps to operate at full line
rate (more bandwidth is required if the headers are modified). The bandwidth
requirement for memory is a key factor in memory selection (see Table 1–1). As an
example, a simple first-order calculation using RLDRAM II as buffer memory requires
a bus width of 48 bits to sustain 20 Gbps (300 MHz × 2 DDR × 0.70 efficiency × 48 bits
= 20.1 Gbps), which needs two RLDRAM II parts (one ×18 and one ×36). RLDRAM II
also inherently includes the additional memory bits used for parity or error correction
code (ECC).
QDR and QDR II SRAM have bandwidth and low random access latency advantages
that make them useful for control memory in queue management and traffic
management applications. Another typical implementation for this memory is billing
and packet statistics, where each packet requires counters to be read from memory,
incremented, and then rewritten to memory. The high bandwidth, low latency, and
optimal one-to-one read/write ratio make QDR SRAM ideal for this feature.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
1–8
Chapter 1: Selecting your Memory Component
High-Speed Memory in Telecom Application Example
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
2. DDR, DDR2, and DDR3 SDRAM
Overview
This chapter provides an overview of DDR, DDR2, and DDR3 SDRAM in Altera
devices. DDR3 SDRAM is the latest generation of DDR SDRAM technology, with
improvements that include lower power consumption, higher data bandwidth,
enhanced signal quality with multiple on-die termination (ODT) selection and output
driver impedance control. DDR3 SDRAM brings higher memory performance to a
broad range of applications, such as PCs, embedded processor systems, image
processing, storage, communications, and networking. DDR2 SDRAM is the second
generation of DDR SDRAM technology. DDR and DDR2 SDRAMs are available as
components and modules, such as DIMMs, SODIMMs, and RDIMMs
f
For more information about Altera DDR3 SDRAM IP, refer to the External Memory
Interface System Specifications section in volume 1 of the External Memory Interface
Handbook.
DDR SDRAM Overview
DDR SDRAM is a 2n prefetch architecture with two data transfers per clock cycle. It
uses a single-ended strobe, DQS, which is associated with a group of data pins, DQ,
for read and write operations. Both DQS and DQ ports are bidirectional. Address
ports are shared for read and write operations.
Write and read operations are sent in bursts, DDR SDRAM supports burst lengths of
2, 4, and 8. The column address strobe (CAS) latency is the latency between when the
read command is clocked into the memory and the requested data is presented at the
memory pins. DDR SDRAM can have CAS latencies of 2, 2.5, and 3, depending on
operating frequency.
DDR SDRAM devices use the SSTL-2 2.5V I/O standard and can hold between 64 MB
and 1 GB of data. Each device is divided into four banks, and each bank has a fixed
number of rows and columns. Only one row per bank can be accessed at a time. The
ACTIVE command opens a row and the PRECHARGE command closes a row.
DDR SDRAM has a maximum frequency of 200 MHz or 400 Mbps per DQ pin.
DDR2 SDRAM Overview
DDR2 SDRAM is the second generation of the DDR SDRAM standard. It is a 4n
prefetch architecture (internally the memory operates at half the interface frequency)
with two data transfers per clock cycle. DDR2 SDRAM can use a single-ended or
differential strobe, DQS or DQSn, which is associated with a group of data pins, DQ,
for read and write operations. DQS, DQSn, and DQ ports are bidirectional. Address
ports are shared for read and write operations.
Write and read operations are sent in bursts, DDR2 SDRAM supports burst lengths of
4 and 8. DDR2 SDRAM supports CAS latencies of 2, 3, 4, and 5.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
2–2
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DDR3 SDRAM Overview
DDR2 SDRAM devices use the SSTL-18 1.8-V I/O standard and can hold between 256
MB and 4 GB of data. All DDR2 SDRAM devices have at least four banks, but
higher-density devices (typically 1 GB and above) have eight internal banks. With
more banks available, the page-to-hit ratio is twice as great when compared to DDR
SDRAM. DDR2 SDRAM also allows bank interleaving, which represents a significant
advantage for applications accessing random data. Bank interleaving can be
extremely effective for concurrent operations and can hide the timing overhead that
are otherwise required for opening and closing individual banks.
DDR2 SDRAM also supports ODT signal options of 50, 75, or 150  on all DQ, DM,
and DQS and DQSn signals.
DDR2 SDRAM has a maximum frequency of 533 MHz or 1,066 Mbps per DQ pin.
DDR3 SDRAM Overview
DDR3 SDRAM is more effective at saving system power and increasing system
performance than DDR2 SDRAM. DDR3 SDRAM offers lower power by using 1.5 V
for the supply and I/O voltage compared to the 1.8-V supply and I/O voltage used by
DDR2 SDRAM. DDR3 SDRAM also has better maximum throughput compared to
DDR2 SDRAM by increasing the data rate per pin and the number of banks (to eight
banks). DDR3 SDRAM also has the following additional benefits:
1
■
Supports read/write levelling functionality required in the FPGA to interface with
DDR3 DIMMs.
■
Supports calibrated parallel ODT via an external resistor RZQ signal termination
options of RZQ/2, RZQ/4, or RZQ/6  on all DQ, DM, and DQS and DQSn signals.
■
Supports controlled output driver impedance options of RZQ/6 or RZQ/7.
■
Maximum frequency of 800 MHz or 1600 Mbps per DQ pin.
■
Minimum operating frequency is 300 MHz.
The DDR3 SDRAM high-performance controller only supports local interfaces
running at half the rate of the memory interface.
DDR3 SDRAMs are available as components and modules, such as DIMMs,
SODIMMs, and RDIMMs.
DDR3 SDRAM is internally configured as an eight-bank DRAM. DDR3 SDRAM uses
an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch
architecture is combined with an interface that transfers two data words per clock
cycle at the I/O pins. A single read or write operation for DDR3 SDRAM consists of a
single 8n-bit wide, four-clock data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operations to the DDR3 SDRAM are burst oriented. Operation begins
with the registration of an active command, which is then followed by a read or write
command. The address bits registered coincident with the active command select the
bank and row to be activated (BA0 to BA2 select the bank; A0 to A15 select the row).
The address bits registered coincident with the read or write command select the
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DDR, DDR2 and DDR3 SDRAM Comparison
2–3
starting column location for the burst operation, determine if the auto precharge
command is to be issued (via A10), and select burst chop (BC) of 4 or burst length (BL)
of 8 mode at runtime (via A12), if enabled in the mode register. Before normal
operation, the DDR3 SDRAM must be powered up and initialized in a predefined
manner.
Differential strobes DQS and DQSn are mandated for DDR3 SDRAM and are
associated with a group of data pins, DQ, for read and write operations. DQS, DQSn,
and DQ ports are bidirectional. Address ports are shared for read and write
operations.
Write and read operations are sent in bursts, DDR3 SDRAM supports BC of 4 and BL
of 8. DDR3 SDRAM supports CAS latencies of 5 to 10.
DDR3 SDRAM devices use the SSTL-15 1.5-V I/O standard and can hold between
512 MB and 8 GB of data. The 1.5-V operational voltage reduces power consumption
by 17% compared to DDR2 SDRAM.
All DDR3 SDRAM devices have eight internal banks. With more banks available, the
page-to-hit ratio is twice that of DDR SDRAM. DDR3 SDRAM also allows bank
interleaving, which represents a significant advantage for applications accessing
random data. Bank interleaving can be extremely effective for concurrent operations
and can hide the timing overhead that is otherwise required for opening and closing
individual banks.
DDR, DDR2 and DDR3 SDRAM Comparison
Table 2–1 compares DDR, DDR2, and DDR3 SDRAM features.
Table 2–1. DDR, DDR2, and DDR3 SDRAM Features (Part 1 of 2)
Feature
DDR SDRAM
DDR2 SDRAM
DDR3 SDRAM
DDR3 SDRAM Advantage
Voltage
2.5 V
1.8 V
1.5 V
Reduces memory system power
demand by 17%.
Density
64 MB to 1GB
256 MB to 4 GB
512 MB to 8 GB
High-density components simplify
memory subsystem.
Internal banks
4
4 and 8
8
Page-to-hit ratio increased.
Prefetch
2
4
8
Lower memory core speed results in
higher operating frequency and
lower power operation.
Speed
100 to 200 MHz
200 to 533 MHz
300 to 800 MHz
Higher data rate.
Read latency
2, 2.5, 3 clocks
3, 4, 5 clocks
5, 6, 7, 8, 9, 10, and 11
Eliminating half clock setting allows
8n prefetch architecture.
Additive latency
(1)
—
0, 1, 2, 3, 4
0, CL1, or CL2
Improves command efficiency.
Write latency
One clock
Read latency – 1
5, 6, 7, or 8
Improves command efficiency.
Termination
PCB, discrete to VTT Discrete to VTT or
ODT
Discrete to VTT or ODT
parallel termination.
Controlled impedance
output.
Improves signaling, eases PCB
layout, reduces system cost.
Data strobes
Single-ended
Differential mandated
Improves timing margin.
© January 2010
Differential or
single-ended
Altera Corporation
Memory Standard Overviews
Preliminary
2–4
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DDR, DDR2, and DDR3 SDRAM Interface Pins
Table 2–1. DDR, DDR2, and DDR3 SDRAM Features (Part 2 of 2)
Feature
DDR SDRAM
Clock, address,
and command
(CAC) layout
Balanced tree
DDR2 SDRAM
Balanced tree
DDR3 SDRAM
DDR3 SDRAM Advantage
Series or daisy chained
The DDR3 SDRAM read and write
leveling feature allows for a much
simplified PCB and DIMM layout.
You can still optionally use the
balanced tree topology by using the
DDR3 without the leveling option.
Note to Table 2–1:
(1) The Altera DDR and DDR2 SDRAM high-performance controllers do not support additive latency, but the high-performance controller II does.
DDR, DDR2, and DDR3 SDRAM Interface Pins
This section describes the DDR, DDR2, and DDR3 SDRAM interface pins.
Clock Signals
DDR, DDR2, and DDR3 SDRAM devices use CK and CK# signals to clock the address
and command signals into the memory. Furthermore, the memory uses these clock
signals to generate the DQS signal during a read through the DLL inside the memory.
The SDRAM data sheet specifies the following timings:
■
tDQSCK is the skew between the CK or CK# signals and the SDRAM-generated DQS
signal
■
tDSH is the DQS falling edge from CK rising edge hold time
■
tDSS is the DQS falling edge from CK rising edge setup time
■
tDQSS is the positive DQS latching edge to CK rising edge
These SDRAM have a write requirement (tDQSS) that states the positive edge of the
DQS signal on writes must be within ± 25% (± 90) of the positive edge of the SDRAM
clock input. Therefore, you should generate the CK and CK# signals using the DDR
registers in the IOE to match with the DQS signal and reduce any variations across
process, voltage, and temperature. The positive edge of the SDRAM clock, CK, is
aligned with the DQS write to satisfy tDQSS.
1
The Altera SDRAM high-performance controllers generate the CK and CK# signals
using the DDR registers in the IOE with the DQS signal and reduce any variations
across process, voltage, and temperature.
DDR3 SDRAM can use a daisy-chained CAC topology, the memory clock must arrive
at each chip at a different time. To compensate for this flight-time skew between
devices across a typical DIMM, write leveling must be employed.
Data, Data Strobes, DM, and Optional ECC Signals
DDR SDRAM uses bidirectional single-ended data strobe (DQS); DDR3 SDRAM uses
bidirectional differential data strobes. The DQSn pins in DDR2 SDRAM devices are
optional but recommended for DDR2 SDRAM designs operating at more than 333
MHz. Differential DQS operation enables improved system timing due to reduced
crosstalk and less simultaneous switching noise on the strobe output drivers. The DQ
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DDR, DDR2, and DDR3 SDRAM Interface Pins
2–5
pins are also bidirectional. Regardless of interface width, DDR SDRAM always
operates in ×8 mode DQS groups. DQ pins in DDR2 and DDR3 SDRAM interfaces can
operate in either ×4 or ×8 mode DQS groups, depending on your chosen memory
device or DIMM, regardless of interface width. The ×4 and ×8 configurations use one
pair of bidirectional data strobe signals, DQS and DQSn, to capture input data.
However, two pairs of data strobes, UDQS and UDQS# (upper byte) and LDQS and
LDQS# (lower byte), are required by the ×16 configuration devices. A group of DQ
pins must remain associated with its respective DQS and DQSn pins.
The DQ signals are edge-aligned with the DQS signal during a read from the memory
and are center-aligned with the DQS signal during a write to the memory. The
memory controller shifts the DQ signals by –90 during a write operation to center
align the DQ and DQS signals. ALTMEMPHY delays the DQS signal during a read, so
that the DQ and DQS signals are center aligned at the capture register. Altera devices
use a phase-locked loop (PLL) to center-align the DQS signal with respect to the DQ
signals during writes and Altera devices (except Cyclone III devices) use dedicated
DQS phase-shift circuitry to shift the incoming DQS signal during reads. Figure 2–1
shows an example where the DQS signal is shifted by 90 for a read from the DDR2
SDRAM.
Figure 2–1. DQ and DQS Relationship During a DDR2 SDRAM Read in Burst-of-Four Mode
DQS pin to
register delay (2)
DQS at
FPGA Pin
Preamble
Postamble
DQ at
FPGA Pin
DQS at DQ
IOE registers
DQ at DQ
IOE registers
90 degree shift
DQ pin to
register delay (2)
Figure 2–2 shows an example of the relationship between the data and data strobe
during a burst-of-four write.
Figure 2–2. DQ and DQS Relationship During a DDR2 SDRAM Write in Burst-of-Four Mode
DQS at
FPGA Pin
DQ at
FPGA Pin
The memory device's setup (tDS) and hold times (tDH) for the write DQ and DM pins
are relative to the edges of DQS write signals and not the CK or CK# clock. Setup and
hold requirements are not necessarily balanced in in DDR2 and DDR3 SDRAM,
unlike in DDR SDRAM devices.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
2–6
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DDR, DDR2, and DDR3 SDRAM Interface Pins
The DQS signal is generated on the positive edge of the system clock to meet the tDQSS
requirement. DQ and DM signals use a clock shifted –90 from the system clock, so
that the DQS edges are centered on the DQ or DM signals when they arrive at the
DDR2 SDRAM. The DQS, DQ, and DM board trace lengths need to be tightly matched
(20 ps).
The SDRAM uses the DM pins during a write operation. Driving the DM pins low
shows that the write is valid. The memory masks the DQ signals if the DM pins are
driven high. While you can use any of the I/O pins in the same bank as the associated
DQS and DQ pins, to generate the DM signal, Altera recommends that you use the
spare DQ pin within the same DQS group as the respective data, to minimize skew.
The DM signal's timing requirements at the SDRAM input are identical to those for
DQ data. The DDR registers, clocked by the –90 shifted clock, create the DM signals.
Some SDRAM modules support error correction coding (ECC) to allow the controller
to detect and automatically correct error in data transmission. The 72-bit SDRAM
modules contain eight extra data pins in addition to 64 data pins. The eight extra ECC
pins should be connected to a single DQS or DQ group on the FPGA.
Address and Command Signals
Address and command signals in SDRAM devices are clocked into the memory
device using the CK or CK# signal. These pins operate at single data rate (SDR) using
only one clock edge. The number of address pins depends on the SDRAM device
capacity. The address pins are multiplexed, so two clock cycles are required to send
the row, column, and bank address. The CS#, RAS, CAS, WE, CKE, and ODT pins are
SDRAM command and control pins. DDR3 SDRAM has additional pins: RESET#,
PAR_In and ERR_OUT#. The RESET# pin uses 1.5-V LVCMOS I/O standard, while
the rest of the DDR3 SDRAM pins use the SSTL-15 I/O standard.
The DDR2 SDRAM address and command inputs do not have a symmetrical setup
and hold time requirement with respect to the SDRAM clocks, CK, and CK#.
For ALTMEMPHY or Altera SDRAM high-performance controllers in Stratix III and
Stratix IV devices, the address and command clock is a dedicated PLL clock output
whose phase can be adjusted to meet the setup and hold requirements of the memory
clock. The address and command clock is also typically half-rate, although a full-rate
implementation can also be created. The command and address pins use the DDIO
output circuitry to launch commands from either the rising or falling edges of the
clock. The chip select (mem_cs_n), clock enable (mem_cke), and ODT (mem_odt) pins
are only enabled for one memory clock cycle and can be launched from either the
rising or falling edge of the address and command clock signal. The address and other
command pins are enabled for two memory clock cycles and can also be launched
from either the rising or falling edge of the address and command clock signal.
1
In ALTMEMPHY-based designs, the address and command clock ac_clk_1x is
always half rate. However, because of the output enable assertion, CS#, CKE, and
ODT behave like full-rate signals even in a half-rate PHY.
In Arria II GX and Cyclone III devices, the address and command clock is either
shared with the write_clk_2x or the mem_clk_2x clock.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DIMM Options
2–7
DIMM Options
Compared to the unbuffered DIMMs (UDIMM), both single-rank and double-rank
registered DIMMs (RDIMM) use only one pair of clocks and two chip selects
CS#[1:0]in DDR3. An RDIMM has extra parity signals for address, RAS#, CAS#, and
WE#.
Dual-rank DIMMs have the following extra signals for each side of the DIMM:
■
CS# (RDIMM always has two chip selects, DDR3 uses a minimum of 2 chip selects,
even on a single rank module)
■
CK (only UDIMM)
■
ODT signal
■
CKE signal
Table 2–2 compares the UDIMM and RDIMM pin options.
Table 2–2. UDIMM and RDIMM Pin Options
UDIMM Pins (Single
Rank)
Pins
Data
UDIMM Pins
(Dual Rank)
RDIMM Pins (Single
Rank)
RDIMM Pins
(Dual Rank)
72 bit DQ[71:0] =
72 bit DQ[71:0] =
72 bit DQ[71:0] =
72 bit DQ[71:0]=
{CB[7:0],
DQ[63:0]}
{CB[7:0],
DQ[63:0]}
{CB[7:0],
DQ[63:0]}
{CB[7:0],
DQ[63:0]}
DM[8:0]
DM[8.0]
DM[8.0]
DM[8.0]
Data Strobe (1) DQS[8:0] and
DQS#[8:0]
DQS[8:0] and
DQS#[8:0]
DQS[8:0] and
DQS#[8:0]
DQS[8:0] and
DQS#[8:0]
Address
BA[2:0], A[15:0]–
BA[2:0], A[15:0]–
BA[2:0], A[15:0]–
2 GB: A[13:0]
2 GB: A[13:0]
BA[2:0], A[15:0]–
2 GB: A[13:0]
4 GB: A[14:0]
4 GB: A[14:0]
4 GB: A[14:0]
8 GB: A[15:0]
8 GB: A[15:0]
8 GB: A[15:0]
8 GB: A[15:0]
Clock
CK0/CK0#
CK0/CK0#, CK1/CK1#
CK0/CK0#
CK0/CK0#
Command
ODT, CS#, CKE, RAS#,
CAS#, WE#
ODT[1:0],
CS#[1:0],
CKE[1:0], RAS#,
CAS#, WE#
ODT, CS#[1:0], CKE,
RAS#, CAS#, WE#
ODT[1:0],
CS#[1:0],
CKE[1:0], RAS#,
CAS#, WE#
PAR_IN, ERR_OUT
PAR_IN, ERR_OUT
SA[2:0], SDA, SCL,
EVENT#, RESET#
SA[2:0], SDA, SCL,
EVENT#, RESET#
Data Mask
4 GB: A[14:0]
Parity
—
Other Pins
SA[2:0], SDA, SCL,
EVENT#, RESET#
—
SA[2:0], SDA, SCL,
EVENT#, RESET#
2 GB: A[13:0]
Note to Table 2–2:
(1) DQS#[8:0] is optional in DDR2 SDRAM and is not supported in DDR SDRAM interfaces.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
2–8
Chapter 2: DDR, DDR2, and DDR3 SDRAM Overview
DIMM Options
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
3. QDR II and QDR II+ SRAM Overview
This chapter provides an overview of QDR II and QDR II+ SRAM in Altera devices
Synchronous static RAM (SRAM) architectures support the high throughput
requirements of communications, networking, and digital signal processing (DSP)
systems. The successor to quad data rate (QDR) SRAM, QDR II+ and QDR II SRAM
support higher memory bandwidth and improved timing margins and offer more
flexibility in system designs.
f
For more information about Altera QDR II and QDR II+ SRAM IP, refer to the External
Memory Interface System Specifications section in volume 1 of the External Memory
Interface Handbook.
QDR II+ and QDR II SRAM can perform two data writes and two data reads per clock
cycle. They use one port for writing data (D) and another port for reading data (Q).
These unidirectional data ports support simultaneous reads and writes and allows
back-to-back transactions without the contention issues that can occur when using a
single bidirectional data bus. Write and read operations share address ports.
The QDR II SRAM devices are available in ×8, ×9, ×18, and ×36 data bus width
configurations. The QDR II+ SRAM devices are available in ×9, ×18, and ×36 data bus
width configurations. Write and read operations are burst-oriented. All the data bus
width configurations of QDR II SRAM support burst lengths of two and four. QDR
II+ SRAM supports only a burst length of four. Burst-of-two and burst-of-four for
QDR II and burst-of-four for QDR II+ SRAM devices provide the same overall
bandwidth at a given clock speed.
Read latency is the time between the read command being clocked into memory and
the time data is presented at the memory pins. For QDR II SRAM devices, the read
latency is 1.5 clock cycles, while for QDR II+ SRAM devices it is 2 or 2.5 clock cycles,
depending on the memory device. Write latency is the time between the write
command being clocked into memory and the time data is presented at the memory
pins. For QDR II+ and burst-of-four QDR II SRAM devices, the write commands and
addresses are clocked on the rising edge of clock and write latency is one clock cycle.
For burst-of-two QDR II SRAM devices, the write command is clocked on the rising
edge of clock and the write address is clocked on the falling edge of clock. Therefore,
the write latency is zero, because the write data is presented at the same time as the
write command.
Altera supports both 1.5-V and 1.8-V HSTL I/O standards for QDR II+ and QDR
II SRAM interfaces. QDR II+ and QDR II SRAM interfaces use a delay-locked loop
(DLL) inside the device to edge-align the data with respect to the K and Kn or C and
Cn pins. You can optionally turn off the DLL, but the performance of the QDR II+ and
QDR II SRAM devices is degraded. All timing specifications listed in this document
assume that the DLL is on.
QDR II+ and QDR II SRAM devices also offer programmable impedance output
buffers. You can set the buffers by terminating the ZQ pin to VSS through a resistor, RQ.
The value of RQ should be five times the desired output impedance. The range for RQ
should be between 175  and 350  with a tolerance of 10%.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
3–2
Chapter 3: QDR II and QDR II+ SRAM Overview
QDR II+ and QDR II SRAM Interface Pin Description
QDR II+ and QDR II SRAM Interface Pin Description
This section provides a description of the clock, control, address, and the data signals
on QDR II and QDR II+ SRAM devices.
Clock Signals
QDR II+ and QDR II SRAM devices have three pairs of clocks:
■
Input clocks K and K#
■
Input clocks C and C#
■
Echo clocks CQ and CQ#
The positive input clock, K, is the logical complement of the negative input clock, K#.
Similarly, C and CQ are complements of C# and CQ#, respectively. With these
complementary clocks, the rising edges of each clock leg latch the DDR data.
The QDR II+ and QDR II SRAM devices use the K and K# clocks for write access and
the C and C# clocks for read accesses only when interfacing more than one QDR II+ or
QDR II SRAM device. Because the number of loads that the K and K# clocks drive
affects the switching times of these outputs when a controller drives a single QDR II+
or QDR II SRAM device, C and C# are unnecessary. This is because the propagation
delays from the controller to the QDR II+ or QDR II SRAM device and back are the
same. Therefore, to reduce the number of loads on the clock traces, QDR II+ and QDR
II SRAM devices have a single clock mode, and the K and K# clocks are used for both
reads and writes. In this mode, the C and C# clocks are tied to the supply voltage
(VDD).
CQ and CQ# are the source-synchronous output clocks from the QDR II or QDR
II+ SRAM device that accompanies the read data.
The Altera device outputs the K and K# clocks, data, address, and command lines to
the QDR II+ or QDR II SRAM device. For the controller to operate properly, the write
data (D), address (A), and control signal trace lengths (and therefore the propagation
times) should be equal to the K and K# clock trace lengths.
You can generate C, C#, K, and K# clocks using any of the PLL registers via the DDR
registers. Because of strict skew requirements between K and K# signals, use adjacent
pins to generate the clock pair. The propagation delays for K and K# from the FPGA to
the QDR II+ or QDR II SRAM device are equal to the delays on the data and address
(D, A) signals. Therefore, the signal skew effect on the write and read request
operations is minimized by using identical DDR output circuits to generate clock and
data inputs to the memory.
Command Signals
QDR II+ and QDR II SRAM devices use the write port select (WPSn) signal to control
write operations and the read port select (RPSn) signal to control read operations. The
byte write select signal (BWSn) is a third control signal that indicates to the QDR II+ or
QDR II SRAM device which byte to write into the QDR II+ or QDR II SRAM device.
You can use any of the FPGA's user I/O pins to generate control signals, preferably on
the same side and the same bank.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 3: QDR II and QDR II+ SRAM Overview
QDR II+ and QDR II SRAM Interface Pin Description
3–3
Address Signals
QDR II+ and QDR II SRAM devices use one address bus (A) for both read and write
addresses. You can use any of the FPGA's user I/O pins to generate address signals,
preferably on the same side and the same banks.
Data and QVLD Signals
QDR II+ and QDR II SRAM devices use two unidirectional data buses: one for
writes (D) and one for reads (Q). The read data is edge-aligned with the CQ and CQ#
clocks while the write data is center-aligned with the K and K# clocks (see Figure 3–1
and Figure 3–2).
Figure 3–1. CQ and Q Relationship During QDR II+ SRAM Read
DQS pin to
register delay
CQ at
FPGA Pin
CQ# at
FPGA Pin
Q at
FPGA Pin
CQ at
Capture Register
CQ# at
Capture Register
Q at
Capture Register
DQS phase DQ pin to
shift
register delay
Figure 3–2. K and D Relationship During QDR II+ SRAM Write
K at
FPGA Pin
K# at
FPGA Pin
D at
FPGA Pin
QDR II+ SRAM devices also have a QVLD pin that indicates valid read data. The
QVLD signal is edge-aligned with the echo clock and is asserted high for
approximately half a clock cycle before data is output from memory.
1
© January 2010
The Altera QDR II+ SRAM Controller MegaCore function does not use the QVLD
signal.
Altera Corporation
Memory Standard Overviews
Preliminary
3–4
Chapter 3: QDR II and QDR II+ SRAM Overview
QDR II+ and QDR II SRAM Interface Pin Description
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
4. RLDRAM II Overview
This chapter provides an overview of RLDRAM II in Altera devices
Reduced latency DRAM II (RLDRAM II) is a DRAM-based point-to-point memory
device designed for communications, imaging, and server systems requiring high
density, high memory bandwidth, and low latency. The fast random access speeds in
RLDRAM II devices make them a viable alternative to SRAM devices at a lower cost.
f
For more information about Altera RLDRAM II IP, refer to the External Memory
Interface System Specifications section in volume 1 of the External Memory Interface
Handbook.
There are two types of RLDRAM II devices: common I/O (CIO) and separate I/O
(SIO). CIO devices share a single data I/O bus which is similar to the double data rate
(DDR) SDRAM interface. SIO devices, with separate data read and write buses, have
an interface similar to SRAM.
Compared to DDR SDRAM, RLDRAM II has simpler bank management and lower
latency inside the memory. RLDRAM II devices are divided into eight banks instead
of the typical four banks in most memory devices, providing a more efficient data
flow within the device. RLDRAM II offers up to 2.4 Gigabytes per second (Gbps)
aggregate bandwidth.
RLDRAM II uses a DDR scheme, performing two data transfers per clock cycle.
RLDRAM II CIO devices use the bidirectional data pins (DQ) for both read and write
data, while RLDRAM II SIO devices use D pins for write data (input to the memory)
and Q pins for read data (output from the memory). Both types use two pairs of
uni-directional free-running clocks. The memory uses DK and DK# pins during write
operations, and generates QK and QK# pins during read operations. In addition,
RLDRAM II uses the system clocks (CK and CK# pins) to sample commands and
addresses and generate the QK and QK# read clocks. Address ports are shared for
write and read operations.
The RLDRAM II SIO devices are available in ×9 and ×18 data bus width
configurations, while the RLDRAM II CIO devices are available in ×9, ×18, and
×36 data bus width configurations. RLDRAM II CIO interfaces may require an extra
cycle for bus turnaround time for switching read and write operations.
Write and read operations are burst oriented and all the data bus width configurations
of RLDRAM II support burst lengths of two and four. In addition, RLDRAM II
devices with data bus width configurations of ×9 and ×18 also support burst length of
eight.
The read latency is the time between when the read command is clocked into the
memory and the time data is presented at the memory pins. There is a similar latency
for write operations called the write latency. The write latency is equal to the read
latency plus one clock cycle. The RLDRAM devices have up to three programmable
configuration settings that determine the row cycle times, read latency, and write
latency of the interface at a given frequency of operation.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
4–2
Chapter 4: RLDRAM II Overview
RLDRAM II Interface Pin Description
RLDRAM II devices use either the 1.5-V HSTL or 1.8-V HSTL I/O standard. You can
use either I/O standard to interface with Altera FPGAs. Each RLDRAM II device is
divided into eight banks, where each bank has a fixed number of rows and columns.
Only one row per bank is accessed at a time. The memory (instead of the controller)
controls the opening and closing of a row, which is similar to an SRAM interface.
RLDRAM II also offers programmable impedance output buffers and on-die
termination. The programmable impedance output buffers are for impedance
matching and are guaranteed to produce 25- to 60-ohm output impedance. The on-die
termination is dynamically switched on during read operations and switched off
during write operations. Perform an IBIS simulation to observe the effects of this
dynamic termination on your system. IBIS simulation can also show the effects of
different drive strengths, termination resistors, and capacitive loads on your system.
RLDRAM II Interface Pin Description
This section describes the RLDRAM II interface pin description.
Clock Signals
RLDRAM II devices use CK and CK# signals to clock the command and address bus in
single data rate (SDR). There is one pair of CK and CK# pins per RLDRAM II device.
Instead of a strobe, RLDRAM II devices use two sets of free-running differential
clocks to accompany the data. The DK and DK# clocks are the differential input data
clocks used during writes while the QK or QK# clocks are the output data clocks used
during reads. Even though QK and QK# signals are not differential signals according to
the RLDRAM II data sheets, Micron treats these signals as such for their testing and
characterization. Each pair of DK and DK#, or QK and QK# clocks are associated with
either 9 or 18 data bits.
The exact clock-data relationships are as follows:
■
For ×36 data bus width configuration, there are 18 data bits associated with each
pair of write and read clocks. So, there are two pairs of DK and DK# pins and two
pairs of QK or QK# pins.
■
For ×18 data bus width configuration, there are 18 data bits per one pair of write
clocks and nine data bits per one pair of read clocks. So, there is one pair of DK and
DK# pins, but there are two pairs of QK and QK# pins.
■
For ×9 data bus width configuration, there are nine data bits associated with each
pair of write and read clocks. So, there is one pair of DK and DK# pins and one pair
of QK and QK# pins each.
There are tCKDK timing requirements for skew between CK and DK or CK# and DK#.
Because of the loads on these I/O pins, the maximum frequency you can achieve
depends on the number of RLDRAM II devices you are connecting to the Altera
device. Perform SPICE or IBIS simulations to analyze the loading effects of the
pin-pair on multiple RLDRAM II devices.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Chapter 4: RLDRAM II Overview
RLDRAM II Interface Pin Description
4–3
Data, DM and QVLD Signals
The read data is edge-aligned with the QK or QK# clocks while the write data is
center-aligned with the DK and DK# clocks (see Figure 4–1 and Figure 4–2). The
memory controller shifts the DK or DK# signal to center align the DQ and DK or DK#
signal during a write and to shift the QK signal during a read, so that read data (DQ or
Q signals) and QK clock is center-aligned at the capture register. Altera devices use
dedicated DQS phase-shift circuitry to shift the incoming QK signal during reads and
use a PLL to center-align the DK and DK# signals with respect to the DQ signals during
writes.
Figure 4–1. DQ and QK Relationship During RLDRAM II Read
DQS Pin to
Register Delay (2)
QK at
FPGA Pin
DQ at
FPGA Pin
QK at DQ
LE Registers
DQ at DQ
LE Registers
90 Degree Shift
DQ Pin to
Register Delay (2)
Notes to Figure 4–1:
(1) This is an example of a 90° shift. The required phase shift for your system should be based on your timing analysis and may not be 90°.
Figure 4–2. DQ and QK Relationship During RLDRAM II Write
DK at
FPGA Pin
DQ at
FPGA Pin
The RLDRAM II data mask (DM) pins are only used during a write. The memory
controller drives the DM signal low when the write is valid and drives it high to mask
the DQ signals. There is one DM pin per RLDRAM II device.
The DM timing requirements at the input to the RLDRAM II are identical to those for
DQ data. The DDR registers, clocked by the write clock, create the DM signals. This
reduces any skew between the DQ and DM signals.
© January 2010
Altera Corporation
Memory Standard Overviews
Preliminary
4–4
Chapter 4: RLDRAM II Overview
RLDRAM II Interface Pin Description
The RLDRAM II device's setup time (tDS) and hold (tDH) time for the write DQ and DM
pins are relative to the edges of the DK or DK# clocks. The DK and DK# signals are
generated on the positive edge of system clock, so that the positive edge of CK or CK#
is aligned with the positive edge of DK or DK# respectively to meet the RLDRAM II
tCKDK requirement. The DQ and DM signals are clocked using a shifted clock so that
the edges of DK or DK# are center-aligned with respect to the DQ and DM signals when
they arrive at the RLDRAM II device.
The clocks, data, and DM board trace lengths should be tightly matched to minimize
the skew in the arrival time of these signals.
RLDRAM II devices also have a QVLD pin indicating valid read data. The QVLD
signal is edge-aligned with QK or QK# and is high approximately half a clock cycle
before data is output from the memory.
1
The Altera RLDRAM II Controller IP does not use the QVLD signal.
Commands and Addresses
The CK and CK# signals clock the commands and addresses into RLDRAM II devices.
These pins operate at single data rate using only one clock edge. RLDRAM II devices
have 18 to 21 address pins, depending on the data bus width configuration and burst
length. RLDRAM II supports both non-multiplexed and multiplexed addressing.
Multiplexed addressing allows you to save a few user I/O pins while
non-multiplexed addressing allows you to send the address signal within one clock
cycle instead of two clock cycles. CS#, REF#, and WE# pins are input commands to the
RLDRAM II device.
The commands and addresses must meet the memory address and command setup
(tAS, tCS) and hold (tAH, tCH) time requirements.
Memory Standard Overviews
© January 2010
Preliminary
Altera Corporation
Section III. System Performance Specifications
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_INTRO_SPECS-1.1
Document Version:
Document Date:
1.1
January 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
About This Section
Revision History
The following table shows the revision history for this section.
Date
Version
Changes Made
January 2010
1.1
Updated DDR, DDR2, and DDR3 specifications.
November 2009
1.0
First published.
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
iv
About This Section
Revision History
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
1. DDR SDRAM Specifications
This chapter describes the following specifications when using the Altera® DDR
SDRAM IP:
■
Maximum clock rate supported
■
Maximum number of interfaces
■
Unsupported features
Maximum Clock Rate Support
The DDR SDRAM IP offers the following features:
■
Full-rate and half-rate designs
■
Both UDIMM and RDIMM in any form factor (refer to “DDR, DDR2, and DDR3
SDRAM Overview” on page 2–1)
■
Burst length of 4 when using DDR SDRAM high-performance controller; burst
length of 8 (for half-rate designs) or 4 (for full-rate designs) when using the DDR
SDRAM high-performance controller II
Table 1–1 shows supported features at maximum clock rates for ALTMEMPHY-based
DDR SDRAM controllers (such as the DDR SDRAM high-performance controller) on
various Altera devices. The number in brackets is the memory component required
clock rate. For example, you require a 200-MHz memory component to get 133-MHz
maximum frequency on an Cyclone IV E device.
f
For recommended termination and drive strength settings, refer to the Board Layout
Guidelines section in volume 2 of the External Memory Interface Handbook.
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
1–2
Chapter 1: DDR SDRAM Specifications
Maximum Clock Rate Support
Table 1–1. DDR SDRAM Support on Altera Devices
Arria®
II GX
Row I/Os
Wraparound I/Os
Maximum
Full-Rate Clock
Rate (MHz) (1)
Column I/Os
Row I/Os
C4
Wraparound I/Os
Device
Speed
Grade
Column I/Os
Maximum
Half-Rate Clock
Rate (MHz) (1)
200
200
C5
Memory Type (2)
■
Single component
■
Multiple component in a single
rank UDIMM or RDIMM layout
■
Single rank UDIMM and RDIMM
I5
C6
Cyclone® III
and
Cyclone IV GX
(3)
167
C6 (4)
167
150
133
167
150
133
C7
150
133
125
150
133
125
133
125
100
133
125
100
133 {200}
125
{200}
133 {200}
100
{200}
100 {200}
83
{200}
SSTL-2 Class I
SSTL-2 Class I
and Class II
(5)
I7
A7 (4)
I/O Standard
and
Termination
C8
Cyclone IV E
C8L
I8L
C9L
Stratix® III
C2
200
200
200
200
C3
I3
C4
I4
C4L
I4L
Stratix IV
–2
–2x
–3
–4
Stratix IV GT
–1
Note to Table 1–1:
(1) The first number is the maximum clock rate. The number in brackets is the memory device speed grade. If there is no number in brackets, use
the same memory component speed grade as the maximum clock rate shown.
(2) Multiple chip select and multiple rank DIMMs are supported at a lower maximum clock rate based on your board layout. To calculate the
maximum clock rate for designs with multiple chip select, refer to the Timing Analysis section in volume 4 of the External Memory Interface
Handbook.
(3) In Cyclone IV GX devices, left side is not supported for external memory interface.
(4) Cyclone III LS devices do not support C6 and A7 speed grades. These frequencies are only applicable to Cyclone III non LS devices.
(5) In Stratix IV devices, class II termination is not available on row I/Os.
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 1: DDR SDRAM Specifications
Maximum Number of Interfaces
1–3
Maximum Number of Interfaces
Table 1–2 shows available device resources for DDR SDRAM. Table 1–2 also describes
the maximum number of ×8 DDR SDRAM components fit in the smallest and biggest
devices and pin packages assuming the device is blank.
Each n (where n is a multiple of 8) interface consists of:
■
n DQ pins (including ECC)
■
n/8 DM pins
■
n/8 DQS pins
■
18 address pins
■
7 command pins (CAS, RAS, WE, CKE, ODT, reset, and CS)
■
1 CK, CK# pin pair for every three ×8 DDR SDRAM components
1
Unless otherwise noted, this calculation for the maximum number of interfaces is
based on independent interfaces where the address or command pins are not shared.
1
Timing closure depends on device resource and routing utilization.
f
For more information about timing closure, refer to the Area and Timing Optimization
Techniques chapter in the Quartus II Handbook.
1
You need to share DLLs if the total number of interfaces is more than 4. You may also
need to share PLL clock outputs depending on your clock network usage, refer to the
Device and Pin Planning section in volume 2 of the External Memory Interface Handbook.
f
For information on the number of DQ and DQS in other packages, refer to the DQ and
DQS tables in the relevant device handbook.
Table 1–2. Maximum Number of DDR SDRAM Controllers Supported per FPGA (Part 1 of 2)
Device
Arria II GX
Device
Type
Package Pin
Count
EP2AGX190 1,152
EP2AGX260
EP2AGX45
358
EP2AGX65
© January 2010 Altera Corporation
Maximum Number of Controllers
Four ×8 interfaces or one ×72 interface on each
side (no DQ pins on left side)
■
On top side, one ×16 interface
■
On bottom side, one ×16 interface
■
On right side (no DQ pins on left side), one ×8
interface
System Performance Specifications
Preliminary
1–4
Chapter 1: DDR SDRAM Specifications
Unsupported Features
Table 1–2. Maximum Number of DDR SDRAM Controllers Supported per FPGA (Part 2 of 2)
Device
Cyclone III
Device
Type
EP3C120
EP3C5
Stratix III
EP3SL340
EP3SE50
Stratix IV
Package Pin
Count
780
256
1,760
484
EP4SGX290 1,932
Maximum Number of Controllers
■
On top side, three ×16 interfaces
■
On bottom side, three ×16 interfaces
■
On left side, two ×16 interfaces
■
On right side, two ×16 interfaces
■
On top side, two ×8 interfaces
■
On bottom side, two ×8 interfaces
■
On right side, one ×8 interfaces
■
On left side, one ×8 interfaces
■
On top side, two ×72 interfaces
■
On bottom side, two ×72 interfaces
■
On left side, one ×72 interfaces
■
On right side, one ×72 interfaces
■
On top side, two ×8 interfaces
■
On bottom side, two ×8 interfaces
■
On right side, three ×8 interfaces
■
On left side, three ×8 interfaces
■
One ×72 interface on each side
EP4SGX360
or
EP4SGX530
■
One ×72 interface on each side and two
additional ×72 wraparound interfaces, only if
sharing DLL and PLL resources
■
On top side, three ×8 interfaces or one ×64
interface
■
On bottom side, three ×8 interfaces or one ×64
interface
■
On left side (no DQ pins on right side), one ×48
interface or two ×8 interfaces
EP4SE530
1,760
EP4SE820
EP4SGX70
780
EP4SGX110
EP4SGX180
EP4SGX230
Unsupported Features
For features not supported by Altera memory IP, you can create a controller using a
custom PHY with the ALTDQ_DQS megafunction. However, you must create the
timing constraints and timing analysis methodology to determine your maximum
interface frequency. Altera only supports the ALTDQ_DQS part of your design.
1
Cyclone III devices do not support ×4 DQS groups and hence cannot support ×4 DDR
SDRAM components or DIMMs.
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
2. DDR2 SDRAM Specifications
This chapter describes the following specifications when using the Altera DDR2
SDRAM IP:
■
Maximum clock rate supported
■
Maximum number of interfaces
■
Unsupported features
Maximum Clock Rate Support
The DDR2 SDRAM IP offers the following features:
■
Full-rate and half-rate designs
■
Both UDIMM and RDIMM in any form factor (refer to “DDR, DDR2, and DDR3
SDRAM Overview” on page 2–1)
■
Burst length of 4 when using DDR2 SDRAM high-performance controller; burst
length of 8 (for half-rate designs) or 4 (for full-rate designs) when using the DDR2
SDRAM high-performance controller II
■
Multiple component in a single rank UDIMM or RDIMM layout
Table 2–1 and Table 2–2 show supported features at maximum clock rates for
ALTMEMPHY-based DDR2 SDRAM controllers (such as the DDR2 SDRAM
high-performance controller) on various Altera devices. The number in brackets is the
memory component required clock rate. For example, you require a 400-MHz
memory component to get 300-MHz maximum frequency on an Arria II GX device.
f
For recommended termination and drive strength settings, refer to the Board Layout
Guidelines section in volume 2 of the External Memory Interface Handbook.
Table 2–1. Half-Rate DDR2 SDRAM Support on Altera Devices (Part 1 of 3)
Maximum Half-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Arria II GX
Speed
Grade
Single
C4
333
C5
333
{400}
I5
300
{400}
C6
267
Dual
Quad
Single
Dual
Quad
300 {400}
267 {333}
267
267
{333}
Single
Dual
Quad
I/O Standard and
Termination
SSTL-18 Class I
267
300
267
233
267
233
200
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
2–2
Chapter 2: DDR2 SDRAM Specifications
Maximum Clock Rate Support
Table 2–1. Half-Rate DDR2 SDRAM Support on Altera Devices (Part 2 of 3)
Maximum Half-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Cyclone III
and
Cyclone IV GX
(2)
Speed
Grade
Single
C6 (3)
200
C7
Cyclone IV E
Quad
— (6)
Single
167
Dual
Quad
— (6)
Single
{200}
{267}
167
150
133
{200}
{200}
{200}
133
125
{200}
{200}
167
A7 (3)
{267
or
333}
(5)
Dual
167
{267
or
333}
(5)
I7
C8 (4)
Dual
— (6)
C8L
166 {333}
133 {200}
I8L
150 {267}
125 {200}
C9L
133 {200}
—
System Performance Specifications
Quad
I/O Standard and
Termination
SSTL-18 Class I
and Class II
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR2 SDRAM Specifications
Maximum Clock Rate Support
2–3
Table 2–1. Half-Rate DDR2 SDRAM Support on Altera Devices (Part 3 of 3)
Maximum Half-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Stratix III
Speed
Grade
Single
Dual
Quad
Single
— (6)
Dual
400
Quad
— (6)
Single
C2
400
C3
333
333
333
200
200
200
Dual
400
Quad
— (6)
I/O Standard and
Termination
SSTL-18 Class I
and Class II (7)
I3
C4
I4
C4L
I4L
C4L (8)
I4L (8)
Stratix IV
–2
400
333
400
333
400
333
–2x
–3
Stratix IV GT
333
–4
333
300
333
300
333
300
–1
400
333
400
333
400
333
Note to Table 2–1:
(1) The first number is the maximum clock rate. The number in brackets is the memory device speed grade. If there is no number in brackets, you
may use the same memory component speed grade as the maximum clock rate shown.
(2) In Cyclone IV GX devices, left side is not supported for external memory interface.
(3) Cyclone III LS devices do not support C6 and A7 speed grades. These frequencies are only applicable to Cyclone III non LS devices.
(4) For a Q240 C8 device with 167-MHz performance on column I/Os, a 333-MHz DDR2 SDRAM component is required.
(5) You need 267-MHz memory component speed grade when using class I I/O standard and 333-MHz memory component speed grade when
using Class II I/O standard.
(6) Multiple chip select and multiple rank DIMMs are supported at a lower maximum clock rate based on your board layout. To calculate the
maximum clock rate for designs with multiple chip select, refer to the Timing Analysis section in volume 4 of the External Memory Interface
Handbook.
(7) In Stratix IV devices, class II termination is not available on row I/Os.
(8) VCCL = 0.9 V.
Table 2–2. Full-Rate DDR2 SDRAM Support on Altera Devices
Maximum Full-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Arria II GX
Speed
Grade
Single
Dual
Quad
Single
Dual
Quad
Single
Dual
Quad
C4
267
{333}
267 {400}
267
{333}
267 {400}
233
{267}
233 {400}
C5
233
{267}
233 {333}
233
{267}
233 {333}
200
{267}
200 {333}
I5
C6
233 {333}
233 {333}
200
I/O Standard and
Termination
SSTL-18 Class I
200 {333}
167 {200}
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
2–4
Chapter 2: DDR2 SDRAM Specifications
Maximum Clock Rate Support
Table 2–2. Full-Rate DDR2 SDRAM Support on Altera Devices
Maximum Full-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Cyclone III
and
Cyclone IV GX
(2)
Speed
Grade
Single
C6 (3)
167
C7
Cyclone IV E
Quad
— (6)
Single
Dual
167
Quad
— (6)
Single
167
{267
or
333}
(5)
{200}
{267}
150
150
133
{200}
{200}
{200}
133
125
{200}
{200}
I7
150
A7 (3)
{267
or
333}
(5)
C8 (4)
Dual
C8L
150 {200}
I8L
150 {267}
C9L
Dual
Quad
— (6)
I/O Standard and
Termination
SSTL-18 Class I
and Class II
125 {200}
—
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR2 SDRAM Specifications
Maximum Number of Interfaces
2–5
Table 2–2. Full-Rate DDR2 SDRAM Support on Altera Devices
Maximum Full-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
Chip Select
Device
Stratix III
Speed
Grade
Single
Dual
Quad
Single
— (6)
Dual
300
(7)
Quad
— (6)
Single
C2
300
(7)
300
(7)
C3
I3
267
(7)
267
(7)
267
(7)
C4
233
233
233
167
167
167
Dual
Quad
— (6)
I/O Standard and
Termination
SSTL-18 Class I
and Class II (7)
I4
C4L
I4L
C4L (8)
I4L (8)
Stratix IV
–2
300 (7)
–2x
Stratix IV GT
–3
267 (7)
–4
233
–1
300 (7)
Note to Table 2–2:
(1) The first number is the maximum clock rate. The number in brackets is the memory device speed grade. If there is no number in brackets, you
may use the same memory component speed grade as the maximum clock rate shown.
(2) In Cyclone IV GX devices, left side is not supported for external memory interface.
(3) Cyclone III LS devices do not support C6 and A7 speed grades. These frequencies are only applicable to Cyclone III non LS devices.
(4) For a Q240 C8 device with 167-MHz performance on column I/Os, a 333-MHz DDR2 SDRAM component is required.
(5) You need 267-MHz memory component speed grade when using class I I/O standard and 333-MHz memory component speed grade when
using Class II I/O standard.
(6) Multiple chip select and multiple rank DIMMs are supported at a lower maximum clock rate based on your board layout. To calculate the
maximum clock rate for designs with multiple chip select, refer to the Timing Analysis section in volume 4 of the External Memory Interface
Handbook.
(7) May require some optimization to meet core timing.
(8) In Stratix IV devices, class II termination is not available on row I/Os.
(9) VCCL = 0.9 V.
Maximum Number of Interfaces
Table 2–3 shows available device resources for DDR2 SDRAM. Table 2–3 describes the
maximum number of ×8 DDR2 SDRAM components that can be fitted in the smallest
and biggest devices and pin packages assuming the device is blank.
Each n (where n is a multiple of 8) interface consists of:
■
n DQ pins (including ECC)
■
n/8 DM pins
■
n/8 DQS,DQSn pin pairs
■
18 address pins
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
2–6
Chapter 2: DDR2 SDRAM Specifications
Maximum Number of Interfaces
■
7 command pins (CAS, RAS, WE, CKE, ODT, reset, and CS)
■
1 CK, CK# pin pair for every three ×8 DDR2 components
1
Unless otherwise noted, this calculation for the maximum number of interfaces is
based on independent interfaces where the address or command pins are not shared.
1
Timing closure depends on device resource and routing utilization.
f
For more information about timing closure, refer to the Area and Timing Optimization
Techniques chapter in the Quartus II Handbook.
1
You need to share DLLs if your total number of interfaces is more than 4. You may
also need to share PLL clock outputs depending on your clock network usage, refer to
the Device and Pin Planning section in volume 2 of the External Memory Interface
Handbook.
f
For information on the number of DQ and DQS in other packages, refer to the DQ and
DQS tables in the relevant device handbook.
Table 2–3. Maximum Number of DDR2 SDRAM Controllers Supported per FPGA
Device
Arria II GX
Device
Type
Package Pin
Count
EP2AGX190 1,152
EP2AGX260
EP2AGX45
358
EP2AGX65
Cyclone III
EP3C120
EP3C5
Stratix III
EP3SL340
EP3SE50
780
256
1,760
484
System Performance Specifications
Maximum Number of Controllers
Four ×8 interfaces or one ×72 interface on each
side (no DQ pins on left side)
■
On top side, one ×16 interface
■
On bottom side, one ×16 interface
■
On right side (no DQ pins on left side), one ×8
interface
■
On top side three ×16 interfaces
■
On bottom side, three ×16 interfaces
■
On left side, two ×16 interfaces
■
On right side, two ×16 interfaces
■
On top side, two ×8 interfaces
■
On bottom side, two ×8 interfaces
■
On right side, one ×8 interfaces
■
On left side, one ×8 interfaces
■
On top side, two ×72 interfaces
■
On bottom side, two ×72 interfaces
■
On left side, one ×72 interface
■
On right side, one ×72 interface
■
On top side, two ×8 interfaces
■
On bottom side, two ×8 interfaces
■
On left side, three ×8 interfaces
■
On right side, three ×8 interfaces
© January 2010
Preliminary
Altera Corporation
Chapter 2: DDR2 SDRAM Specifications
Unsupported Features
2–7
Table 2–3. Maximum Number of DDR2 SDRAM Controllers Supported per FPGA
Device
Stratix IV
Device
Type
Package Pin
Count
EP4SGX290 1,932
Maximum Number of Controllers
■
One ×72 interface on each side
EP4SGX360
or
EP4SGX530
■
One ×72 interface on each side and two
additional ×72 wraparound interfaces only if
sharing DLL and PLL resources
■
On top, three ×8 interfaces or one ×64 interface
■
On bottom, three ×8 interfaces or one ×64
interface
■
On left side (no DQ pins on right side), one ×48
interface or two ×8 interfaces
EP4SE530
1,760
EP4SE820
EP4SGX70
780
EP4SGX110
EP4SGX180
EP4SGX230
Unsupported Features
For features not supported by Altera memory IP, you can create a controller using a
custom PHY with the ALTDQ_DQS megafunction. However, you muist create the
timing constraints and timing analysis methodology to determine your maximum
interface frequency. Altera only supports the ALTDQ_DQS part of your design.
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
2–8
Chapter 2: DDR2 SDRAM Specifications
Unsupported Features
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
3. DDR3 SDRAM Specifications
This chapter describes the following specifications when using the Altera DDR3
SDRAM IP:
■
Maximum clock rate supported
■
Maximum number of interfaces
■
Unsupported features
Maximum Clock Rate Support
The DDR3 SDRAM IP supports the following features:
■
Half-rate designs
■
Leveling support:
■
Without leveling for Arria II GX and Stratix III devices up to 400 MHz and for
Stratix IV devices up to 533 MHz
1
■
With leveling for Stratix III and Stratix IV devices between 400 and 533 MHz
1
■
You must set the Memory Format to Discrete Device in the MegaWizard
Plug-In, even if you are interfacing with multiple DDR3 SDRAM
components laid out on the board like a (T-topology) DDR2 SDRAM
UDIMM.
You must set the Memory Format to Unbuffered DIMM in the
MegaWizard Plug-In, even if you are you are interfacing with multiple
DDR3 SDRAM components laid out on the board like a (fly-by) DDR3
SDRAM UDIMM.
Maximum data width with leveling is 80 bits
1
The leveling delay on the board between first and last DDR3 SDRAM
component laid out as a DIMM must be less than a single memory clock
cycle period.
■
Both UDIMM and RDIMM support for Stratix III and Stratix IV devices in any
form factor (refer to “DDR, DDR2, and DDR3 SDRAM Overview” on page 2–1)
■
No quad-rank RDIMM support
■
Burst length of 8 and burst chop of 4
■
A single DDR3 SDRAM component
■
Multiple DDR3 SDRAM components in a single-rank DDR2 SDRAM UDIMM or
RDIMM layout
■
Multiple DDR3 SDRAM components in a single-rank DDR3 SDRAM UDIMM or
RDIMM layout (except for Arria II GX devices)
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
3–2
Chapter 3: DDR3 SDRAM Specifications
Maximum Clock Rate Support
■
1
Single-rank DDR3 SDRAM UDIMM (not Arria II GX devices)
No (fly-by) DDR3 SDRAM DIMM support for Arria II GX devices as there is no
leveling circuitry
Table 3–1 and Table 3–2 show supported features at maximum clock rates for
ALTMEMPHY-based DDR3 SDRAM controllers (such as the DDR3 SDRAM
high-performance controller) on various Altera devices. The number in brackets is the
memory component required clock rate. For example, you require a 400-MHz
memory component to get 300-MHz maximum frequency on an Arria II GX device.
1
Table 3–1 shows DIMM support; Table 3–2 shows component suppport.
Table 3–1. DDR3 SDRAM DIMM Support on Altera Devices
Maximum Half-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
I/O Standard and
Termination
Chip Select
Device
Stratix III
Speed
Grade
Single
Dual
Quad
— (2)
Single
Dual
533
(3)
Quad
— (2)
Single
C2
533
(3)
533
(3)
C3
400
400
400
333
333
333
Dual
Quad
— (2)
SSTL-15 Class I
and Class II (4)
I3
C4
I4
C4L (5)
I4L (5)
Stratix IV
–2
–2x
533
(3)
400
–C3
533
(3)
400
400
533
(3)
333
400
400
333
–I3
–C4
400
{533}
333
400
{533}
533
(3)
400
533
(3)
–I4
Stratix IV
GT
–1
333
333
400
533
(3)
400
Note to Table 3–1:
(1) The first number is the maximum clock rate. The number in brackets is the memory device speed grade. If there is no number in brackets, you
may use the same memory component speed grade as the maximum clock rate shown.
(2) Multiple chip select and multiple rank DIMMs are supported at a lower maximum clock rate based on your board layout. To calculate the
maximum clock rate for designs with multiple chip select, refer to the Timing Analysis section in volume 4 of the External Memory Interface
Handbook..
(3) Any DDR3 SDRAM interfaces operating higher than 400 MHz must use the leveling circuitry, and the memory components must be laid out
like a (fly-by) DDR3 SDRAM UDIMM. The leveling circuitry is enabled by setting the Memory Format to Unbuffered DIMM.
(4) In Stratix IV devices, class II termination is not available on row I/Os.
(5) Applies to VCCL=1.1 V only. There is no DDR3 SDRAM support for VCCL = 0.9V.
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 3: DDR3 SDRAM Specifications
Maximum Clock Rate Support
3–3
Table 3–2. DDR3 SDRAM Component Support on Altera Devices
Maximum Half-Rate Clock Rate (MHz) (1)
Column I/Os
Row I/Os
Wraparound I/Os
I/O Standard and
Termination
Chip Select
Device
Arria II GX
Speed
Grade
Single
C4
400
{533}
(2)
C5
333
{400}
I5
300
{400}
Dual
Quad
300 {400}
Single
Quad
333
{400}
Single
Dual
Quad
300 {400}
SSTL-15 Class I
— (3)
C6
Stratix III
Dual
— (2)
C2
533
(4)
— (2)
533
(3)
— (2)
533
(3)
C3
400
400
400
333
333
333
— (2)
SSTL-15 Class I
and Class II (5)
I3
C4
I4
C4L (6)
I4L (5)
Stratix IV
–2
–2x
400
533
(3)
–C3
400
333
–I3
–C4
533
(3)
400
400
{533}
333
–1
333
533
(3)
400
400
333
400
333
400
400
{533}
–I4
Stratix IV
GT
400
333
333
333
533
(3)
400
533
(3)
400
333
533
(3)
400
333
Note to Table 3–1:
(1) The first number is the maximum clock rate. The number in brackets is the memory device speed grade. If there is no number in brackets, you
may use the same memory component speed grade as the maximum clock rate shown.
(2) To achieve the maximum frequency, you require a low board skew within a DQS or DQ group.
(3) Multiple chip select and multiple rank DIMMs are supported at a lower maximum clock rate based on your board layout. To calculate the
maximum clock rate for designs with multiple chip select, refer to the Timing Analysis section in volume 4 of the External Memory Interface
Handbook..
(4) Any DDR3 SDRAM interfaces operating higher than 400 MHz must use the leveling circuitry, and the memory components must be laid out
like a (fly-by) DDR3 SDRAM UDIMM. The leveling circuitry is enabled by setting the Memory Format to Unbuffered DIMM.
(5) In Stratix IV devices, class II termination is not available on row I/Os.
(6) Applies to VCCL=1.1 V only. There is no DDR3 SDRAM support for VCCL = 0.9V.
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
3–4
Chapter 3: DDR3 SDRAM Specifications
Maximum Number of Interfaces
Maximum Number of Interfaces
Table 3–3 shows available device resources for DDR3 SDRAM. Table 3–3 also
describes the maximum number of ×8 DDR3 SDRAM components that can be fitted in
the smallest and biggest devices and pin packages assuming the device is blank.
Each n (where n is a multiple of 8) interface consists of:
■
n DQ pins (including ECC)
■
n/8 DM pins
■
n/8 DQS,DQSn pin pairs
■
17 address pins
■
7 command pins (CAS, RAS, WE, CKE, ODT, reset, and CS)
■
1 CK, CK# pin pair
1
Unless otherwise noted, this calculation for the maximum number of interfaces is
based on independent interfaces where the address or command pins are not shared.
1
Timing closure depends on device resource and routing utilization.
f
For more information about timing closure, refer to the Area and Timing Optimization
Techniques chapter in the Quartus II Handbook.
1
You need to share DLLs if your total number of interfaces is more than 4. You may
also need to share PLL clock outputs depending on your clock network usage, refer to
the Device and Pin Planning section in volume 2 of the External Memory Interface
Handbook.
f
For information on the number of DQ and DQS in other packages, refer to the DQ and
DQS tables in the relevant device handbook.
Table 3–3. Maximum Number of DDR3 SDRAM Controllers Supported per FPGA
Device
Arria II GX
Device
Type
Package Pin
Count
EP2AGX190 1,152
Maximum Number of Controllers
■
Four ×8 interfaces or one ×72 interface on each
side (no DQ pins on left side)
■
On top side, one ×16 interface
■
On bottom side, one ×16 interface
■
On right Side (no DQ pins on left side), one ×8
interface
EP2AGX260
EP2AGX45
358
EP2AGX65
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 3: DDR3 SDRAM Specifications
Unsupported Features
3–5
Table 3–3. Maximum Number of DDR3 SDRAM Controllers Supported per FPGA
Device
Stratix III
Device
Type
EP3SL340
EP3SE50
Stratix IV
Package Pin
Count
1,760
484
EP4SGX290 1,932
Maximum Number of Controllers
■
On top side, two ×72 interfaces
■
On bottom side, two ×72 interfaces
■
On left side, one ×72 interface
■
On right side, one ×72 interface
■
On top side, two ×8 interfaces
■
On bottom side, two ×8 interfaces
■
On left side, three ×8 interfaces
■
On right side, three ×8 interfaces
■
One ×72 interface on each side
EP4SGX360
or
EP4SGX530
■
One ×72 interface on each side and 2 additional
×72 wraparound interfaces only if sharing DLL
and PLL resources
■
On top, three ×8 interfaces or one ×64 interface
■
On bottom, three ×8 interfaces or one ×64
interface
■
On left side (no DQ pins on right side), one ×48
interface or two ×8 interfaces
EP4SE530
1,760
EP4SE820
EP4SGX70
780
EP4SGX110
EP4SGX180
EP4SGX230
Unsupported Features
For features not supported by Altera memory IP, you can create a controller using a
custom PHY with the ALTDQ_DQS megafunction. However, you must create the
timing constraints and timing analysis methodology to determine your maximum
interface frequency. Altera only supports the ALTDQ_DQS part of your design.
Altera DDR3 SDRAM IP does not support the following features:
■
Quad-rank RDIMMs and any form of DIMM in Arria II GX devices
■
Full-rate designs
■
Data widths greater than 80 bits when using leveling
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
3–6
Chapter 3: DDR3 SDRAM Specifications
Unsupported Features
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
4. QDR II and QDR II+ SRAM
Specifications
This chapter describes the following specifications when using the Altera QDR II and
QDR II+ SRAM IP:
■
Maximum clock rate supported
■
Maximum number of interfaces
■
Unsupported features
Maximum Clock Rate Support
The QDR II and QDR II+ SRAM controllers with UniPHY give the following support:
■
■
Burst length:
■
4 (half rate)
■
2 or 4 (full rate)
Memory read latency:
■
2 and 2.5 for ×9, ×18, and × 36 QDR II+
■
1.5 for QDR II
Table 4–1 shows supported features at maximum clock rates for QDR II SRAM
controllers with UniPHY on various Altera devices. Table 4–2 shows supported
features at maximum clock rates for QDR II+ SRAM controllers with UniPHY on
various Altera devices.
f
For recommended termination and drive strength settings, refer to the Board Layout
Guidelines section in volume 2 of the External Memory Interface Handbook.
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
4–2
Chapter 4: QDR II and QDR II+ SRAM Specifications
Maximum Clock Rate Support
Table 4–1. QDR II SRAM Support on Altera Devices
Maximum Half-Rate
Clock Rate (MHz) (1)
Device
Arria II GX
Speed
Grade
C4
Maximum Full-Rate Clock
Rate (MHz) (1)
×9, ×18,
and ×36
×36
Emulation
(2)
×9, ×18,
and ×36
×36
Emulation
(2)
250
200
250
200
I/O
Standard
Memory Type
■
Single component
■
HSTL15
Class I
■
HSTL18
Class I
■
HSTL15
Class I/II
■
HSTL18
Class I/II
(3)
C5
I5
Stratix III
C6
200
150
C2
350
300
C3
300
250
200
150
300
300
250
I3
C4
267
250
C4L
I4
I4L
C4L (4)
250
200
–2
350
300
–3
300
250
167
I4L (4)
Stratix IV
–4
Stratix IV
GT
–1
300
300
250
267
350
300
300
300
Note to Table 4–1:
(1) The same frequency for column, row , and wraparound I/Os.
(2) Not supported with wraparound I/Os.
(3) In Stratix IV devices, class II termination is not available on row I/Os.
(4) VCCL = 0.9 V
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 4: QDR II and QDR II+ SRAM Specifications
Maximum Number of Interfaces
4–3
Table 4–2. QDR II+ SRAM Support on Altera Devices
Maximum Half-Rate
Clock Rate (MHz) (1)
Device
Arria II GX
Speed
Grade
C4
Maximum Full-Rate Clock
Rate (MHz) (1)
×9, ×18,
and ×36
×36
Emulation
(2)
×9, ×18,
and ×36
×36
Emulation
(2)
250
200
250
200
I/O
Standard
Memory Type
■
Single component
■
HSTL15
Class I
■
HSTL18
Class I
C5
I5
Stratix III
C6
200
150
C2
400 (3)
300
C3
350
250
200
150
300
300
250
I3
C4
300
267
C4L
I4L
C4L (4)
250
167
I4L (4)
Stratix IV
Stratix IV
GT
–2
400
–3
350
–4
300
–1
400
300
250
300
250
267
300
Note to Table 4–1:
(1) The same frequency for column, row, and wraparound I/Os.
(2) Not supported with wraparound I/Os.
(3) To achieve this data rate, the QDR II+ SRAM device must have an echo clock tCQHCQ#H specification of 0.9 ns or higher.
(4) VCCL= 0.9 V.
Maximum Number of Interfaces
Table 4–3 shows available device resources for QDR II and QDR II+ SRAM. Table 4–3
also describes the maximum number of independent QDR II+ or QDR II SRAM
interfaces that can be fitted in the smallest and biggest devices and pin packages
assuming the device is blank.
One interface of ×36 consists of:
■
36 Q pins
■
36 D pins
■
1 K, K# pin pairs
■
1 CQ, CQ# pin pairs
■
19 address pins
■
4 BSWn pins
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
4–4
Chapter 4: QDR II and QDR II+ SRAM Specifications
Maximum Number of Interfaces
■
WPS, RPS
One interface of ×9 consists of:
■
9 Q pins
■
9 D pins
■
1 K, K# pin pairs
■
1 CQ, CQ# pin pairs
■
21 address pins
■
1 BWSn pin
■
WPS, RPS
1
Unless otherwise noted, this calculation for the maximum number of interfaces is
based on independent interfaces where the address or command pins are not shared.
1
Timing closure depends on device resource and routing utilization.
f
For more information about timing closure, refer to the Area and Timing Optimization
Techniques chapter in the Quartus II Handbook.
1
You need to share DLLs if your total number of interfaces is more than 4. You may
also need to share PLL clock outputs depending on your clock network usage, refer to
the Device and Pin Planning section in volume 2 of the External Memory Interface
Handbook.
f
For information on the number of DQ and DQS in other packages, refer to the DQ and
DQS tables in the relevant device handbook.
Table 4–3. Maximum Number of QDR II and QDR II+ SRAM Controllers Supported per FPGA
Device
Arria II GX
Device
Type
Package Pin
Count
EP2AGX190 1,152
EP2AGX260
EP2AGX45
One ×36 interface and one ×9 interface one each
side
358
One ×9 interface on each side (no DQ pins on left
side)
1,760
■
On bottom side, two ×36 interfaces and one ×9
interface
■
On top side, two ×36 interfaces and one ×9
interface
■
On left side, five ×9 interfaces
■
On right side, five ×9 interfaces
■
On bottom side, one ×9 interface
EP3SL50
■
On top side, one ×9 interface
EP3SL70
■
On left side, two ×9 interfaces
■
On right side, two ×9 interfaces
EP2AGX65
Stratix III
Maximum Number of Controllers
EP3SL340
EP3SE50
484
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 4: QDR II and QDR II+ SRAM Specifications
Unsupported Features
4–5
Table 4–3. Maximum Number of QDR II and QDR II+ SRAM Controllers Supported per FPGA
Device
Stratix IV
Device
Type
Package Pin
Count
Maximum Number of Controllers
EP4SGX290 1,932
■
On top side, two ×36 interfaces
EP4SGX360
■
On bottom side, two ×36 interfaces
EP4SGX530
■
On left side, one ×36 interface
1,760
■
On right side, one ×36 interface
780
■
Two ×9 interfaces on each side (no DQ pins on
right side)
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Unsupported Features
For features not supported by Altera memory IP, you can create a controller using a
custom PHY with the ALTDQ_DQS megafunction. However, you must create the
timing constraints and timing analysis methodology to determine your maximum
interface frequency. Altera only supports the ALTDQ_DQS part of your design.
Altera QDR II and QDR II+ SRAM IP does not support the following features:
■
Multiple chip selects
■
Width expansion
■
Deterministic latency
■
ECC
■
Controlled input and output impedance (ODT)
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
4–6
Chapter 4: QDR II and QDR II+ SRAM Specifications
Unsupported Features
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
5. RLDRAM II Specifications
This chapter describes the following specifications when using the Altera RLDRAM II
IP:
■
Maximum clock rate supported
■
Maximum number of interfaces
■
Unsupported features
Maximum Clock Rate Support
The RLDRAM II controller with UniPHY supports the following features:
■
Burst length:
■
4 and 8 (half rate)
■
2, 4, and 8 (full rate)
Table 5–1 shows supported features at maximum clock rates for RLDRAM II
controllers with UniPHY on various Altera devices.
f
For recommended termination and drive strength settings, refer to the Board Layout
Guidelines section in volume 2 of the External Memory Interface Handbook.
Table 5–1. RLDRAM II Support on Altera Devices
Device
Stratix III
Maximum
Half-Rate Clock
Rate (MHz) (1)
Maximum
Full-Rate Clock
Rate (MHz) (1)
C2
400
300
C3
350
275
Speed
Grade
■
I3
C4
300
267
–2
400
300
–3
350
–4
300
267
–1
400
300
I/O
Standard
Memory Type
Single component common I/O
■
HSTL15
Class I/II
■
HSTL18
Class I/II
(2)
C4L (3)
I4L (3)
Stratix IV
Stratix IV
GT
Note to Table 5–1:
(1) The same frequency for column, row, and wraparound I/Os.
(2) In Stratix IV devices, class II termination is not available on row I/Os.
(3) Support for VCCL= 1.1V only
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
5–2
Chapter 5: RLDRAM II Specifications
Maximum Number of Interfaces
Maximum Number of Interfaces
Table 5–2 shows available device resources for RLDRAM II. Table 5–2 also describes
the maximum number of independent RLDRAM II interfaces that can be fitted in the
smallest and biggest devices and pin packages assuming the device is blank.
One common I/O ×36 interface consists of:
■
36 DQ
■
1 DM pin
■
2 DK, DK# pin pairs
■
2 QK, QK# pin pairs
■
1 CK, CK# pin pair
■
24 address pins
■
1 CS# pin
■
1 REF# pin
■
1 WE# pin
■
1 QVLD pin
One common I/O ×9 interface consists of:
■
9 DQ
■
1 DM pins
■
1 DK, DK# pin pair
■
1 QK, QK# pin pair
■
1 CK, CK# pin pair
■
25 address pins
■
1 CS# pin
■
1 REF# pin
■
1 WE# pin
■
1 QVLD pin
1
Unless otherwise noted, this calculation for the maximum number of interfaces is
based on independent interfaces where the address or command pins are not shared.
1
Timing closure depends on device resource and routing utilization.
f
1
For more information about timing closure, refer to the Area and Timing Optimization
Techniques chapter in the Quartus II Handbook.
You need to share DLLs if your total number of interfaces is more than 4. You may
also need to share PLL clock outputs depending on your clock network usage, refer to
the Device and Pin Planning section in volume 2 of the External Memory Interface
Handbook.
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Chapter 5: RLDRAM II Specifications
Unsupported Features
f
5–3
For information on the number of DQ and DQS in other packages, refer to the DQ and
DQS tables in the relevant device handbook.
Table 5–2. Maximum Number of RLDRAM II Controllers Supported per FPGA
Device
Stratix III
Device
Type
EP3SL340
Package Pin
Count
1,760
Maximum Number of RLDRAM II CIO
■
On top side, four ×36 components
■
On bottom side, four ×36 components
■
On right side, three ×36 interfaces
■
On left side, three ×36 interfaces
■
On left side, one ×9 interface
■
On right side, one ×9 interface
EP4SGX290 1,932
■
On top side, three ×36 interfaces
EP4SGX360
■
On bottom side, three ×36 interfaces
EP4SGX530
■
On left side, two ×36 interfaces
■
On right sides, two ×36 interfaces
■
On top side, three ×36 interfaces
■
On bottom side, three ×36 interfaces
■
On left side, three ×36 interfaces
■
On right sides, three ×36 interfaces
EP3SE50
484
EP3SL50
EP3SL70
Stratix IV
EP4SE530
1,760
EP4SE820
EP4SGX70
780
EP4SGX110
One ×36 interface on each side (no DQ pins on
right side)
EP4SGX180
EP4SGX230
Unsupported Features
For features not supported by Altera memory IP, you can create a controller using a
custom PHY with the ALTDQ_DQS megafunction. However, you must create the
timing constraints and timing analysis methodology to determine your maximum
interface frequency. Altera only supports the ALTDQ_DQS part of your design.
Altera RLDRAM II IP does not support the following features:
■
Multiplexed addressing
■
Width expansion
■
Multiple chip selects
■
Separate I/O
■
Dynamic read latency change
■
ECC
■
Multicast write
■
VCCL = 0.9 V
© January 2010 Altera Corporation
System Performance Specifications
Preliminary
5–4
Chapter 5: RLDRAM II Specifications
Unsupported Features
■
Controlled input and output impedance (ODT)
System Performance Specifications
© January 2010
Preliminary
Altera Corporation
Additional Information
How to Contact Altera
For the most up-to-date information about Altera® products, see the following table.
Contact (Note 1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Altera literature services
Email
[email protected]
Non-technical support (General)
Email
[email protected]
(Software Licensing)
Email
[email protected]
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue
Meaning
Bold Type with Initial Capital
Letters
Indicates command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, dialog box options, software utility names, and other GUI labels. For
example, \qdesigns directory, d: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters
Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.
Italic type
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters
Indicates keyboard keys and menu names. For example, Delete key and the Options
menu.
“Subheading Title”
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Courier type
Indicates signal, port, register, bit, block, and primitive names. For example, data1,
tdi, and input. Active-low signals are denoted by suffix n. For example,
resetn.
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
© January 2010
Altera Corporation
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
Info–2
Additional Information
Typographic Conventions
Visual Cue
Meaning
1., 2., 3., and
a., b., c., and so on.
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
■ ■
Bullets indicate a list of items when the sequence of the items is not important.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
w
A warning calls attention to a condition or possible situation that can cause you
injury.
r
The angled arrow instructs you to press Enter.
f
The feet direct you to more information about a particular topic.
External Memory Interface Handbook Volume 1: Introduction to Altera External Memory Interfaces
Preliminary
© January 2010
Altera Corporation
External Memory Interface Handbook Volume 2: Device,
Pin, and Board Layout Guidelines
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_PLAN-1.0
Document Version:
Document Date:
1.0
November 2009
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
Contents
Section Revision Dates
Section I. Device and Pin Planning
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. Select a Device
Memory Standards and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Device Pin Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Top or Bottom and Left or Right Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Wraparound Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
IP Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Full or Half Rate SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
External Memory Interface Features of Altera Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
IOE Dedicated Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
DDR Input and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Synchronization and Alignment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Half-Rate Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
DQS Postamble Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Differential DQS Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Read and Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Dynamic OCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
PLL and DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
Cyclone III and Cyclone IV GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15
Chapter 2. Pin and Resource Planning
I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
OCT Support for Arria II GX, Stratix III, and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
General Pinout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
© November 2009
Altera Corporation
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
iv
Pinout Rule Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II GX, Stratix III and
Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
Timing Impact on x36 Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Determining the CQ/CQn Arrival Time Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Exceptions for RLDRAM II Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
Interfacing with ×9 RLDRAM II CIO Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
Interfacing with ×18 RLDRAM II CIO Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Interfacing with RLDRAM II ×36 CIO Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Exceptions for QDR II and QDR II+ SRAM Burst-Length-Of-Two Interfaces . . . . . . . . . . . . . . . . . 2–15
Pin Connection Guidelines Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
PLLs and Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
PLL Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25
Other FPGA Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Section II. Board Layout Guidelines
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
External Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Simulation and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Recommended Termination Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
Dynamic On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–10
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
On-Chip Termination (Non-Dynamic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14
Class II External Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18
Class I External Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–21
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–23
Class I Termination Using ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–24
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
No-Parallel Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–26
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–28
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31
Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31
How Strong is Strong Enough? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–31
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–32
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
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System Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33
Component Versus DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–33
FPGA Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–35
Single- Versus Dual-Rank DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–36
Single DIMM Versus Multiple DIMMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37
DDR2 SDRAM Design Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–37
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–40
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–42
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–43
Chapter 2. DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
With Leveling or Without Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
With Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Without Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Comparing DDR3 and DDR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Read and Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Calibrated Output Impedance and ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Dynamic OCT in Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Termination for DDR3 SDRAM Unbuffered DIMMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
DDR3 SDRAM Unbuffered DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
DQS, DQ, and DM for DDR3 SDRAM Unbuffered DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
Memory Clocks for DDR3 SDRAM Unbuffered DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
Commands and Addresses for DDR3 SDRAM Unbuffered DIMM . . . . . . . . . . . . . . . . . . . . . . . 2–13
Stratix III and Stratix IV FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
DQS, DQ, and DM for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Memory Clocks for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Commands and Addresses for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
Termination for DDR3 SDRAM Components (With Leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
DQS, DQ, and DM for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Memory Clocks for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Commands and Addresses for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20
Stratix III and Stratix IV FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21
DQS, DQ, and DM Termination for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . 2–21
Memory Clocks Termination for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . 2–22
Command and Address Termination for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . 2–22
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Layout Considerations (with Leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Trace Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
Maximum Trace Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23
General Routing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24
Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
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Termination for DDR3 SDRAM Components (Without Leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26
DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
DQS, DQ, and DM for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Memory Clocks for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27
Command and Address for DDR3 SDRAM Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
Stratix III and Stratix IV FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29
DQS, DQ, and DM Termination for Stratix III Stratix IV FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Memory Clocks Termination for Stratix III and Stratix IV FPGA . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Command and Address for Termination for Stratix III and Stratix IV FPGAs . . . . . . . . . . . . . . 2–30
Arria II GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
DQS, DQ and DM Termination for Arria II GX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30
Memory Clocks Termination for Arria II GX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
Command and Address for Termination for Arria II GX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
Layout Considerations (without Leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–32
Chapter 3. Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and
Board Layout Guidelines
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Stratix II High Speed Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Overview of ODT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
DIMM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Dual-DIMM Memory Interface with Slot 1 Populated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Write to Memory Using an ODT Setting of 150   
Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–7
Dual-DIMM with Slot 2 Populated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
Write to Memory Using an ODT Setting of 150   
Reading from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated . . . . . . . . . . . . . . . . . . . . . . . 3–11
FPGA Writing to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Write to Memory in Slot 1 Using an ODT Setting of 75-  
Write to Memory in Slot 2 Using an ODT Setting of 75-  
Reading From Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
FPGA OCT Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–20
Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology . . . . . . . . . . . . . . 3–20
Address and Command Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–21
Control Group Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
Clock Group Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–22
Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology . . . . . . . . . . . . . . . . . 3–23
Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology . . . . . . . . . . . . . . 3–23
Address and Command Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Control Group Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Clock Group Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–24
Write to Memory in Slot 1 Using an ODT Setting of 75  With One Slot Populated . . . . . . . . . . . . . . 3–24
Write to Memory in Slot 2 Using an ODT Setting of 75  With One Slot Populated . . . . . . . . . . . . . . 3–25
Write to Memory in Slot 1 Using an ODT Setting of 150  With Both Slots Populated . . . . . . . . . . . . 3–26
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
© November 2009
Altera Corporation
vii
Write to Memory in Slot 2 Using an ODT Setting of 150  With Both Slots Populated . . . . . . . . . . . . 3–27
Read from Memory in Slot 1 Using an ODT Setting of 150  on Slot 2 with Both Slots Populated . . 3–28
Read From Memory in Slot 2 Using an ODT Setting of 150  on Slot 1 With Both Slots Populated . 3–29
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–30
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31
Chapter 4. Power Estimation Methods for External Memory Interface Designs
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
© November 2009
Altera Corporation
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
viii
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
© November 2009
Altera Corporation
Section Revision Dates
The following table shows the revision dates for the sections in this volume.
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Date
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Device and Pin Planning
1.0
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Board Layout Guidelines
1.0
November 2009
EMI_PLAN_BOARD-1.0
© November 2009
Layout Guidelines
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External Memory Interface Handbook Volume 2: Device, Pin, and Board
Preliminary
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External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
Section Revision Dates
© November 2009
Altera Corporation
Section I. Device and Pin Planning
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Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
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but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
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About This Section
Revision History
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Date
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Version
1.0
Changes Made
First published.
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Device and Pin Planning
Preliminary
vi
About This Section
Revision History
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
1. Select a Device
This chapter is for use as part of the planning stage, to ensure that you know what to
look for when selecting the right Altera® FPGA device for your memory interface.
f
Use this document with “Pin and Resource Planning” on page 2–1, before you start
implementing your external memory interface.
Memory controllers in Altera devices require access to dedicated IOE features, PLLs,
and several clock networks. Altera devices are feature rich in all these areas, so you
must consider detailed resource and pin planning whenever implementing complex
IP or multiple IP cores. This chapter provides an overview of what to consider in such
instances.
f
For information about the terms used in this document, refer to the Glossary chapter in
volume 1 of the External Memory Interface Handbook.
f
For more information about supported memory types and configurations, refer to the
External Memory Interface System Specifications section in volume 1 of the External
Memory Interface Handbook.
When selecting the optimal Altera device for your memory interface, consider the
following topics:
■
“Memory Standards and Configurations” on page 1–1
■
“Bandwidth” on page 1–2
■
“Device Pin Count” on page 1–2
■
“IP Support” on page 1–4
■
“External Memory Interface Features of Altera Devices” on page 1–5
Memory Standards and Configurations
There are two common types of high-speed memories that are supported by Altera
devices: DRAM and SRAM. Commonly used DRAM devices are DDR, DDR2, DDR3
SDRAM, and RLDRAM II; SRAM devices include QDR II and QDR II+ SRAM.
Different Altera devices support different memory types; not all Altera devices
support all memory types and configurations. Before you start your design, you must
select an Altera device, which supports the memory standard and configurations you
plan to use.
f
© November 2009
For more information about these memory standards, refer to the Memory Standard
Overview section in volume 1 of the External Memory Interface Handbook.
Altera Corporation
Device and Pin Planning
Preliminary
1–2
Chapter 1: Select a Device
Bandwidth
Bandwidth
Before designing any memory interface, determine the required bandwidth of the
memory interface. Bandwidth can be expressed as:
Bandwidth = data width (bits) × data transfer rate (1/s) × efficiency
Data rate transfer (1/s) = 2 × frequency of operation (4 × for QDR SRAM interfaces)
After calculating the bandwidth requirements of your system, determine which
memory type and device to use.
DRAM typically has an efficiency of around 70%, but when using the Altera memory
controller efficiency can vary from 10 to 92%.
In QDR II+ or QDR II SRAM the IP implements two separate unidirectional write and
read data buses, so the data transfer rate is four times the clock rate. The data transfer
rate for a 400-MHz interface is 1,600 Mbps. The efficiency is the percentage of time the
data bus is transferring data. It is dependent on the type of memory. For example, in a
QDR II+ or QDR II SRAM interface with separate write and read ports, the efficiency
is 100%, when there is an equal number of read and write operations on these
memory interfaces.
In addition, Altera's FPGA devices support various data widths for different memory
interfaces. The memory interface support between density and package combinations
differs, so you must determine which FPGA device density and package combination
best suits your application.
Device Pin Count
To meet the growing demand for memory bandwidth and memory data rates,
memory interface systems use parallel memory channels and multiple controller
interfaces. However, the number of memory channels is limited by the package pin
count of the Altera devices. Hence, you must consider device pin count when you
select a device—you must select a device with enough I/O pins for your memory
interface requirement.
The number of device pins depends on the memory standard, the number of memory
interfaces, and the memory data width. For example, a ×72 DDR3 SDRAM
single-rank interface requires 125 I/O pins:
f
■
72 DQ pins (including ECC)
■
9 DM pins
■
9 DQS, DQSn differential pin pairs
■
17 address pins (address and bank address)
■
7 command pins (CAS, RAS, WE, CKE ODT, reset, and CS)
■
1 CK, CK# differential pin pair
For the available number of DQS groups and the maximum number of controllers that
is supported by the FPGAs for different memory types, refer to the External Memory
Interface System Specifications section in volume 1 of the External Memory Interface
Handbook.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
Device Pin Count
1–3
Altera devices do not limit the interface widths beyond the following requirements:
1
f
■
DQS, DQ, clock, and address signals of the entire interface should reside within
the same bank or side of the device if possible, to achieve better performance.
Although wraparound interfaces are also supported at limited frequencies.
■
The maximum possible interface width in any particular device is limited by the
number of DQS and DQ groups available within that bank or side.
■
Sufficient regional clock networks are available to the interface PLL to allow
implementation within the required number of quadrants.
■
Sufficient spare pins exist within the chosen bank or side of the device to include
all other clock, address, and command pin placement requirements.
■
The greater the number of banks, the greater the skew. Altera recommends that
you always compile a test project of your desired configuration and confirm that it
meets timing requirement.
There is a constraint in Arria® II GX devices when assigning DQS and DQ pins. You
are only allowed to use twelve of the sixteen I/O pins in an I/O module for DQ pin.
The remaining four pins can only be used as input pin.
For DQS groups pin-out restriction format, refer to Arria II GX Pin Connection
Guidelines.
Your pin count calculation also determines which device side to use (top or bottom,
left or right, and wraparound).
Top or Bottom and Left or Right Interfaces
Ideally any interface should wholly reside in a single bank. However, interfaces that
span across multiple adjacent banks or the entire side of a device are also fully
supported. Although vertical and horizontal I/O timing parameters are not identical,
timing closure can be achieved on all sides of the FPGA for the maximum interface
frequency.
Arria II GX, Cyclone® III, and Cyclone IV GX devices support interfaces spanning the
top and bottom sides. In addition, Cyclone III devices also supports interfaces
spanning left and right sides.
1
Arria II GX and Cyclone IV GX devices do not support the left interface. There is no
user I/O pins, other than the transceiver pins available in these devices.
Wraparound Interfaces
For maximum performance, Altera recommends that data groups for external
memory interfaces should always be within the same side of a device, ideally reside
within a single bank. High-speed memory interfaces using top or bottom I/O bank
versus left or right IO bank have different timing characteristics, so the timing
margins are also different. However, Altera can support interfaces with wraparound
data groups that wraparound a corner of the device between vertical and horizontal
I/O banks at some speeds. Some devices wraparound interfaces are same speed as
row or column interfaces.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–4
Chapter 1: Select a Device
IP Support
Arria II GX, Cyclone III and Cyclone IV GX devices can support wraparound interface
across all sides of devices that are not used for transceivers. Other Altera devices only
support interfaces with data groups that wraparound a corner of the device.
IP Support
Altera offers IP solutions to help you create your own external memory interface
system. There are two parts of the external memory interface IPs:
f
■
PHY
■
Memory controller
For more information on the IP Altera offers, refer to Volume 3: Implementing Altera
Memory Interface IP of the External Memory Interface Handbook.
PHY
Altera offers external memory interface PHYs for calibration and tracking
mechanisms. These PHYs support full-rate and half-rate interfaces, which you can
then plug a custom controller with the PHY using the AFI. For example, the
ALTMEMPHY megafunction.
The Altera UniPHY IP provides better performance and lower latency. The UniPHY
IP instantiates the PLL and DLL in the top-level design to support multiple interfaces.
Alternatively, you can build a custom PHY using the ALTDLL or ALTDQ_DQS
megafunctions. However, you are then responsible for determining the maximum
interface frequency of your system and in creating the timing constraints required to
create a robust PHY.
f
For more information about creating custom interfaces, refer to Volume 5: Implementing
CustomMemory Interface PHY of the External Memory Interface Handbook.
Controllers
Altera offers controllers for a full solution that you can immediately integrate with
your user logic. For example, the DDR, DDR2, or DDR3 SDRAM high-performance
controllers, or the RLDRAM II or QDR II controllers with UniPHY. These controllers
include the Altera PHY IP and thus provide a simplified interface to DDR, DDR2,
DDR3 SDRAM, RLDRAM II, and QDR II and QDR II+ SRAM components.
Full or Half Rate SDRAM Controller
When implementing memory controllers consider whether a half-rate or a full-rate
datapath is optimal for your design. Full or half-rate designs have the following
definitions:
■
Full-rate designs present data to the local interface at twice the width of the actual
SDRAM interface at the full SDRAM clock rate
■
Half-rate designs present data to the local interface at four times the width of the
actual SDRAM interface at half the SDRAM clock rate
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
1–5
Implementing half-rate memory controllers results in the highest possible SDRAM
clock frequency, at the expense of latency and efficiency. You need to decide whether
system efficiency or system bandwidth is more important.
This implementation is most useful when core HDL designs are difficult to implement
at the higher SDRAM clock frequency, but the required SDRAM bandwidth per I/O
pin is still quite high.
However, full-rate controller operations are faster with the IP operating at the same
clock frequency as your system.
Consider that DDR devices can have a number of banks open at once. Each bank has a
currently selected row. Changing the column within the selected row of an open bank
requires no additional bank management commands to be issued. Changing the row
in an active bank, or changing the bank, both incur a protocol penalty that requires the
precharge (PCH) command closes the active row or bank, and the activate (ACT)
command opens (or activates) the new row or bank combination.
The duration of this penalty is a function of the controller clock frequency, the
memory clock frequency, and the memory device characteristics. Calculating the
impact of a change of memory and controller configuration on a given system is not a
trivial task, as it depends on the nature of the accesses that are performed.
In this example each command takes a single clock cycle in a full-rate controller, but
two clock cycles in a half-rate controller. The bank is not available for the subsequent
ACT command until (tRP) after the PCH. So while the issuing of commands can be
slower using a half-rate controller, the respective memory timing parameters remain
the same.
Hence, when a design uses a half-rate memory controller, the control circuitry is
clocked at half rate and so control operations are slower than a full-rate design.
However, the memory's clock frequency and physical properties are not affected.
External Memory Interface Features of Altera Devices
This topic describes features from the Altera device families that enable external
memory interfaces.
f
For more information on the external memory interface circuitry in an Altera FPGA
device family, refer to the External Memory Interfaces chapter in the relevant device
family handbook.
IOE Dedicated Features
When selecting an Altera device for your external memory system, you must select a
device that is equipped with the features that suit your memory system requirements
and configurations.
Altera devices have enhanced upon the IOE DDR capabilities by including the feature
functionality availability directly in the IOE.
Table 1–1 shows which device families support these features.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–6
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
Table 1–1. Device IOE Dedicated Features (Note 1)
Device Family
Arria II GX
Cyclone III and
Cyclone IV GX
Stratix III and
Stratix IV
DDR input register
v
— (2)
v
DDR output register
v
v
v
Synchronization registers
v
— (2)
v
Alignment registers
—
—
v
Features
— (2)
— (2)
v
DQS phase-shift circuitry
v
—
v
DQS postamble circuitry
v
—
v
Differential DQS signaling
v
—
v
Read and write leveling
circuitry
—
—
v
Dynamic on-chip termination
(OCT) control
—
—
v
Half-rate data registers
Clock divider
—
—
v
Programmable delay
v
v
v
PLL
v
v
v
DLL
v
—
v
Note to Table 1–1:
(1) For more information, refer to the Device I/O Features chapter in the relevant device handbook.
(2) Implemented in the FPGA core fabric.
To use these features implement one of the Altera high-performance controllers (a
complete solution) or Altera PHY IP.
Alternatively, you may access these IOE features directly using the following
low-level megafunctions:
■
1
ALTDQ_DQS megafunction—allows you to parameterize the following features:
■
DDR I/O registers
■
Alignment and synchronization registers
■
Half data rate registers
■
DQS bus mode
■
ALTDLL megafunction—allows you to parameterize the DQS phase-shift circuitry
■
ALTOCT megafunction—allows you to parameterize the IOE OCT features.
■
ALTPLL megafunction—allows you to parameterize the device PLL
■
ALTIOBUF megafunction—allows you to parameterize the device IO features
Altera offers no support using these low-level megafunctions as an external memory
PHY to implement your memory interfaces. If you use low-level megafunctions, you
are solely responsible in creating every aspect of the interface, including timing
analysis and debugging.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
1–7
DDR Input and Output Registers
DDR input and output registers are provided on all sides of the Stratix® III and
Stratix IV devices. In Arria II GX and Cyclone IV GX devices the left side of the device
is not available for interfacing. The DDR I/O structures can be directly implemented
in the IOE in these devices, thus saving core logic and ensuring tight skew is easily
maintained, which eases timing.
For Cyclone III and Cyclone IV GX devices, the DDR input registers are implemented
in the core of the device. For Cyclone III and Cyclone IV GX devices, the read capture
clock is derived from the PHY and is generated by the PLL to clock the DDR capture
registers instead of using DQS read clock strobe from the memory device.
Synchronization and Alignment Registers
Resynchronization registers resynchronize the data from memory clock domain to the
memory controller system clock domain. Alignment registers align the data after read
resynchronization or write leveling process.
In some devices, the synchronization registers are located in the core of the device,
which makes the placement of these registers with respect to the DDR IOE critical to
ensure that timing is achieved. Stratix III and Stratix IV devices have been enhanced
to include the alignment and synchronization registers directly within the IOE, hence
timing is now significantly improved and you are no longer concerned with ensuring
critical register placement with respect to the DDR IOE. Typically, the
resynchronization register is clocked via a dedicated output from the PLL. However,
it may also be clocked directly from the read-leveling delay chain. The output
alignment registers are typically clocked from the PLL.
If the resynchronization clock is sourced from the leveling delay chain, it may be
cascaded from bank to bank, say 1A to 1B. In this configuration, memory controllers
must form a single contiguous block of DQS groups that are not staggered or
interleaved with another memory controller. Additionally, two PHYs cannot share the
same subbank as only one leveling delay chain exists per subbank.
Arria II GX, Cyclone III, and Cyclone IV GX devices do not have leveling circuitry, so
there is no need for alignment registers. Synchronization registers for Arria II GX
devices are implemented in the IOE. These synchronization registers in Cyclone III
and Cyclone IV GX devices are implemented in the FPGA core fabric and are clocked
directly by the PLL. In Cyclone III and Cyclone IV GX devices, these registers are
clocked by the same PLL output clock that also clocks the DDR registers.
1
Generally, alignment and synchronization registers are optional and can be bypassed
if not required. However, Altera external memory interface IP always implements
these synchronization registers, regardless of interface speed. Hence latency through
the PHY may not be optimal for lower frequency designs.
Half-Rate Data Registers
As external memory interface clock speeds increase, the core fMAX can become the
limiting factor in interface design. A common solution, which increases core fMAX
timing problems, is to implement a half-rate architecture. This solution doubles the
data width on the core side interfaces compared to a full-rate SDR solution, but also
halves the required operating frequency.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–8
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
Stratix III and Stratix IV devices include dedicated full-rate to half-rate registers
within the IOE.
Arria II GX, Cyclone III, and Cyclone IV GX devices implement half-rate registers in
the core of the device.
DQS Phase-Shift Circuitry
Devices that use DQS or CQ pins to clock the read data during read operation offer
DQS phase-shift circuitry. This circuitry phase shifts the DQS and CQn pins during
the transaction, to obtain optimal read capture margin. DQS phase-shift circuitry
consists of a DLL and phase offset control block, to further fine tune the DQS phase
shift.
Cyclone III and Cyclone IV GX devices do not have this feature, because DQS signals
are not needed during read operations at lower frequencies.
DQS Postamble Circuitry
DQS postamble circuitry eliminates invalid DQ data capturing, because of the
postamble glitches on the DQS signals through an override on DQS. This feature
ensures the correct clock cycle timing of the postamble enable signal.
DQS postamble circuitry is only needed in devices that use the DQS scheme in read
operation for clocking read data. Arria II GX, Stratix III, Stratix IV devices have this
feature.
As Cyclone III and Cyclone IV GX devices do not use DQS for capturing read data,
they do not have this circuitry.
Differential DQS Signaling
Altera devices (except Cyclone III and Cyclone IV GX devices) directly support
differential DQS signalling and the single-ended standard supported in previous
device families. DDR SDRAM only supports single-ended DQS, DDR2 SDRAM
additionally includes the option of differential DQS signaling. DDR3 SDRAM only
supports differential DQS signaling.
Differential DQS signaling is recommended for DDR2 SDRAM designs operating at
or above 333 MHz. Differential DQS strobe operation enables improved system
timing due to reduced crosstalk and less simultaneous switching noise on the strobe
output drivers. You can use single-ended DQS mode for DDR2 SDRAM interfaces,
but it requires more pessimistic timing data and hence results in less system timing
margin.
Cyclone III and Cyclone IV devices do not support differential signalling and thus do
not support DDR3 SDRAM, which requires DQS signaling.
Read and Write Leveling
Stratix III and Stratix IV I/O registers include read and write leveling circuitry to
enable skew to be removed or applied to the interface on a DQS group basis. There is
one leveling circuit located in each I/O subbank.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
1–9
1
ALTMEMPHY-based designs for DDR and DDR2 SDRAM (and DDR3 SDRAM
without leveling) do not use leveling circuitry, as it is not needed by the memory
standard.
1
ALTMEMPHY-based designs for DDR3 SDRAM DIMMs (and components with
fly-by topology like DIMMs) use leveling circuitry.
Dynamic OCT
Stratix III and Stratix IV devices support dynamic calibrated OCT. This feature allows
the specified series termination to be enabled during writes, and parallel termination
to be enabled during reads. These I/O features allow you to greatly simplify PCB
termination schemes.
Clock Divider
To ease data alignment, a single I/O clock divider may be used for an entire interface,
as the half-rate resynchronization clock can be cascaded from DQ group to the
adjacent DQ group. Hence, when using a common I/O clock divider, data alignment
may be performed across the entire interface. Individual I/O clock dividers require
the data alignment to be performed on a DQ group basis.
Stratix III and Stratix IV devices include a dedicated I/O clock divider on a per DQS
group basis, to simplify and reduce the number of clocks required. The output of this
clock divider can then directly source the half-rate resynchronization clock from the
full-rate version.
Arria II GX, Cyclone III, and Cyclone IV GX devices do not have the clock divider
feature, and so must use separate PLL output.
ALTMEMPHY-based designs support both balanced (without leveling) and
unbalanced (with leveling) CAC topologies. ALTMEMPHY-based designs with
leveling designs use multiple I/O clock dividers on a DQ group basis and do not
support balanced CAC topologies, as a dedicated resynchronization and half-rate
resynchronization clock is required on a per DQS group basis. ALTMEMPHY-based
designs without leveling designs use a single I/O clock divider for the whole interface
to reduce PHY complexity and reduce latency. However, ALTMEMPHY-based
without leveling interfaces cannot be interleaved, because of FPGA limitations.
Programmable Delay
I/O registers include programmable delay chains that you may use to deskew
interfaces. Each pin can have different delay settings, hence read and write margins
can be increased as uncertainties between signals can be minimized.
The DQ-DQS offset scheme is applicable for interfacing systems using QDR II and
QDR II+ SRAM, RLDRAM II, DDR, DDR2 and DDR3 SDRAM components for
frequencies of 400 MHz and below. For interfacing system using DDR3 SDRAM
components with frequencies above 400 MHz, a dynamic deskew scheme improves
the timing margins.
For DQ-DQS offset schemes, delay-chains in the IOE shift the offset between DQ and
DQS, to meet timing. The offsets employed are FPGA family, speed grade and
frequency dependent.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–10
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
For systems using DDR3 SDRAM interfaces at frequencies above 400 MHz, the timing
margins are too small to be fixed by the static DQ-DQS offset scheme. Hence, a
dynamic scheme improves the setup and hold margin at the memory component with
the DLL set to 8-tap mode. Configurable delay elements and delay-chains in the IOE
observe the write window in the DDR3 SDRAM components. This information
configures the delays for each individual DQ and DM pins, to meet the memory
component setup and hold requirements and reduce skew between DQ and DM pins
in a DQS group.
PLL and DLL
Altera devices use PLLs to generate the memory controller clocks. The simplest
slowest speed memory controllers may only require two clocks (0 system clock and
–90 write clock). However, as interface speeds increase, it becomes harder to close
timing and so dedicated resynchronization, postamble, and address and command
clocks are typically required. Additionally, at higher frequencies the maximum
frequency becomes the bottleneck and half-rate designs are the typical solution. Thus
complex half high data rate designs require typically 10 clock networks. Altera
devices are well equipped to address the clocking requirements of external memory
interfaces. This topic describes the availability of PLL and DLL for each of the Altera
devices.
Arria II GX Devices
Arria II GX devices offer up to six PLLs per device with seven outputs per PLL. Each
corner of the device has one PLL. Another two PLLs are located at the middle of the
right side of the device.
There is a total maximum of 64 clock networks provided in Arria II GX devices. 16
global clock networks and 48 regional clock networks. Each corner PLL has access to
the 8 global clocks and 24 regional clocks. Each middle PLL has access to 4 global
clocks and 12 regional clocks.
Arria II GX devices support two DLLs. They are located in the top-left and
bottom-right corners of the device. These two DLLs can support a maximum of two
different frequencies, with each DLL running at one frequency. Each DLL can have
two outputs with different phase offsets, which allows one Arria II GX device to have
four different DLL phase-shift settings. Each DLL can access the top, bottom, and
right side of the device. Each I/O bank is accessible by two DLLs, giving more
flexibility to create multiple frequencies and multiple-type interfaces. The DLL
outputs the same DQS delay settings for the different sides of the device.
f
For more information, refer to the Clock Networks and PLLs in Arria II GX Devices
chapter and the External Memory Interfaces chapter in the Arria II GX Device Handbook.
Figure 1–1 shows the PLL and DLL locations in Arria II GX devices.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
1–11
Figure 1–1. PLL and DLL Locations in Arria II GX Devices
PLL1
8B
7A
8A
7B
PLL2
6
6
DLL1
6
RCLK[47:42]
RCLK[41:36]
GCLK[15:12]
6B
6A
RCLK[35:30]
PLL5
RCLK[5:0]
Q1
Q2
Q3
Q4
GCLK[3:0]
GCLK[11:8]
PLL6
RCLK[11:6]
RCLK[29:24]
5A
5B
GCLK[7:4]
RCLK[17:12]
RCLK[23:18]
6
6
6
DLL2
6
PLL4
3B
4A
3A
4B
PLL3
Consider the following points:
© November 2009
■
Each corner PLL in Arria II GX devices connects to eight global clock nets and 24
regional clock nets.
■
Center PLLs in Arria II GX devices connect to four maximum global clock nets and
12 regional clock nets.
■
Arria II GX devices have two PLLs at the middle of right side of the device and one
PLL at each of the corners of the device.
■
Dual regional clock nets are created by using a regional clock net from each region.
For example, a single dual regional clock net uses two regional clock nets.
Altera Corporation
Device and Pin Planning
Preliminary
1–12
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
■
If the design uses a dedicated PLL to only generate a DLL input reference clock,
the PLL mode must be set to No Compensation or the Quartus® II software forces
this setting automatically. No compensation mode is used to minimize jitter. The
PLL does not generate other outputs, so it does not need to compensate for any
clock paths.
■
If the design cascades PLLs, the source (upstream) PLL must have a
low-bandwidth setting, while the destination (downstream) PLL must have a
high-bandwidth setting.
■
In Arria II GX devices, PLL_5 and PLL_6 on the right side may be cascaded to each
other as you can then use the direct connection between these two PLLs instead of
going through the clock network. The direct connection is required when you have
to cascade PLLs for external memory interface to reduce the output clock jitter
from the cascaded PLL. Cascaded PLLs are not recommended for external
memory interface designs, as jitter can accumulate with the use of cascaded PLLs.
The memory output clock may violate the memory device jitter specification.
■
Input and output delays are only fully compensated for when the dedicated clock
input pins associated with that specific PLL are used as the clock source.
■
If the clock source for the PLL is not a dedicated clock pin for that specific PLL,
jitter is increased, timing margin suffers, and the design may require an additional
global or regional clock. Hence, dedicated PLL input clock pin is strongly
commended for clock source for the PLL.
The following additional IP-specific points apply:
f
■
ALTMEMPHY megafunctions require five global clock nets in Arria II GX devices;
UniPHY IP requires three global clock networks.
■
Ideally, you must pick a PLL and PLL input clock pin that are located on the same
side of the device as the memory interface pins.
■
You may also share the DLL and PLL static clocks for multiple memory interfaces
provided the controllers are on the same side or adjacent side of the device and
running at the same memory clock.
■
If a single memory interface spans two right-side quadrants, a middle-side PLL
must be the source for that interface.
For more information about clock networks, refer to the Clock Networks and PLLs in
Arria II GX Devices chapter in volume 1 of the Arria II GX Device Handbook.
Cyclone III and Cyclone IV GX Devices
There are a maximum of four PLLs in Cyclone III and Cyclone IV GX devices with
five PLL clock outputs each. Each PLL is located in each corner of the device and
drives up to 10 global clock networks. Cyclone III and Cyclone IV GX devices only
have global clock network and offer up to 20 global clock networks.
Cyclone III and Cyclone IV GX devices do not have DLL circuitry. Cyclone III and
Cyclone IV GX devices use a PLL clock generated by the PHY to clock the read
capture register during the read operation. The DQS strobe from the memory
component is ignored during the read operation.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
f
1–13
For more information, refer to the Clock Networks and PLLs in Cyclone III Devices
chapter and the External Memory Interfaces chapter in the Cyclone III Device Handbook.
Figure 1–2 shows the PLL locations and resources in Cyclone III devices.
Figure 1–2. PLL Locations in Cyclone III Devices
PLL3
I/O Bank 8
I/O Bank 7
PLL2
GCLK[14:10]
I/O
Bank
1
I/O
Bank
6
GCLK[4:0]
GCLK[9:5]
PLL5
PLL6
I/O
Bank
2
PLL1
I/O
Bank
5
GCLK[19:15]
I/O Bank 3
I/O Bank 4
PLL4
Figure 1–3 shows the PLL locations in Cyclone IV GX devices.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–14
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
Figure 1–3. PLL and DLL Locations in Cyclone IV GX Devices
I/O Bank 8
I/O Bank 7
PLL4
I/O Bank 6
PLL2
GCLK[14:10]
GCLK[9:5]
I/O Bank 5
GCLK[4:0]
GCLK[19:15]
PLL1
I/O Bank 3
I/O Bank 4
PLL3
Consider the following points:
■
Cyclone III and Cyclone IV GX devices only support global clock networks.
■
Each PLL in Cyclone III and Cyclone IV GX devices connects to a maximum of ten
global clock networks.
■
Cyclone III and Cyclone IV GX devices have maximum of four PLLs. Each PLL is
located at each corner of the device.
■
You do not need to set the PLL in With No Compensation mode as the jitter for
Cyclone III and Cyclone IV GX PLLs in normal mode is low. Changing the PLL
compensation mode may result in inaccurate timing results.
■
Cascading PLLs is not supported in Cyclone III and Cyclone IV GX devices.
■
Input and output delays are only fully compensated for when the dedicated clock
input pins associated with that specific PLL are used as the clock source.
■
Ensure the clock source for the PLL is a dedicated clock pin for that specific PLL, to
reduce jitter, improve timing margins, and to avoid the design requiring an
additional global clock.
The following additional ALTMEMPHY megafunction-specific points apply:
■
ALTMEMPHY megafunctions require four global clock nets in Cyclone III and
Cyclone IV GX devices.
■
Any PLL on any side of an Cyclone III or Cyclone IV GX device can support an
ALTMEMPHY interface. Ideally, you must pick a PLL and PLL input clock pin that
are located on the same side of the device as the memory interface pins.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
■
1–15
You may also share the PLL static clocks for multiple ALTMEMPHY interface,
provided the controllers are on the same side or adjacent side of the device and
running at the same memory clock.
Stratix III and Stratix IV Devices
Stratix III and Stratix IV PLLs have an increased number of outputs and global clock
routing resources when compared to earlier device generations. Stratix III and
Stratix IV top and bottom PLLs feature 10 output (C) counters, also left and right PLLs
feature 7 output (C) counters. This increased number of PLL outputs allows for the
use of dedicated clock phases. In previous Stratix II designs, clock phases had to be
shared.
In general, each Stratix III or Stratix IV PLL has access to four global clocks (GCLK)
and six regional clocks (RCLK) (left and right) or ten RCLK (top and bottom).
Stratix III and Stratix IV devices also feature four DLLs (one located in each corner of
the device). Thus the FPGA can support a maximum of four unique frequencies, with
each DLL running at one frequency. Each DLL can also support two different phase
offsets, which allow a single Stratix III or Stratix IV device to support eight different
DLL phase shift settings. Additionally, each DLL can access the two sides adjacent to
its location. Thus each I/O bank is accessible by two different DLLs, giving more
flexibility when creating multiple frequency and phase shift memory interfaces.
Figure 1–4 shows PLL and DLL locations in Stratix III and Stratix IV devices with
global and regional clock resources.
f
© November 2009
For more information, refer to the Clock Networks and PLLs in Stratix III Devices chapter
and the External Memory Interfaces chapter in the Stratix III Device Handbook or refer to
the Clock Networks and PLLs in Stratix IV Devices chapter and the External Memory
Interfaces chapter in the Stratix IV Device Handbook
Altera Corporation
Device and Pin Planning
Preliminary
1–16
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
Figure 1–4. PLL and DLL Locations in Stratix III and Stratix IV Devices
PLL_L1
8A
8B
8C
PLL_T1
PLL_T2
7C
7B
PLL_R1
7A
6
6
DLL1
DLL4
6
6
1A
RCLK[87:82]
RCLK[63:54]
RCLK[53:45]
6A
RCLK[81:76]
GCLK[15:12]
1B
6B
1C
6C
PLL_L2
RCLK[5:0]
Q2
Q3
Q4
GCLK[3:0]
PLL_L3
PLL_R2
RCLK[43:38]
Q1
GCLK[11:8]
PLL_R3
RCLK[37:32]
RCLK[11:6]
2C
5C
2B
5B
GCLK[7:4]
RCLK[69:64]
2A
RCLK[21:12]
RCLK[31:22]
5A
RCLK[75:70]
6
6
DLL2
6
DLL3
6
PLL_L4
3A
3B
3C
PLL_B1
PLL_B2
4C
4A
4B
PLL_R4
Consider the following points:
■
Each PLL connects to four maximum global clock nets.
■
Top or bottom PLLs connect to ten maximum regional clock nets.
■
Left or right PLLs connect to six maximum regional clock nets.
■
EP4S…110 and smaller devices have only one PLL located in the middle of each
side of the device
■
EP3S...80 and larger devices and EP4S…180 and larger devices have two PLLs in
the middle of each side of the device.
■
EP3S...200 and larger devices, and also EP4S…290 and larger devices additionally
have corner PLLs, which connect to six regional clock nets only.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
1–17
■
Dual regional clock nets are created by using a regional clock net from each region.
For example, a single dual regional clock net uses two regional clock nets.
■
If the design uses a dedicated PLL to only generate a DLL input reference clock,
the PLL mode must be set to No Compensation, or the Quartus II software forces
this setting automatically.
■
If the design cascades PLLs, the source (upstream) PLL should have a
low-bandwidth setting, while the destination (downstream) PLL should have a
high-bandwidth setting.
■
If you are required to cascade two PLLs, use two adjacent PLLs, as you can use a
direct connection instead of going through the clock network.. The direct
connection is required when you have to cascade PLLs for external memory
interface to reduce the output clock jitter from the cascaded PLL. Cascaded PLLs
are not recommended for external memory interface designs, as jitter can
accumulate with the use of cascaded PLLs. The memory output clock may violate
the memory device jitter specification.
■
Input and output delays are only fully compensated for, when the dedicated clock
input pins associated with that specific PLL are used as its clock source.
■
If the clock source for the PLL is not a dedicated clock pin for that specific PLL,
jitter is increased, timing margin suffers, and the design may require an additional
global or regional clock. Hence, a dedicated PLL input clock pin is recommended
for the PLL clock source.
The following additional IP specific points apply for Stratix III and Stratix IV devices:
■
ALTMEMPHY megafunctions require one global or regional clock, and six
regional clock nets. Hence seven clock nets in total are required. RLDRAM II
controller with UniPHY requires one global clock net and four regional clock nets;
QDR II SRAM with controller UniPHY requires three regional clock nets.
■
Ideally, you should pick a PLL and a PLL input clock pin that are located on the
same side of the device as the memory interface pins.
■
You may also share the DLL and PLL static clocks for multiple memory interfaces,
provided the controllers are on the same side or adjacent side of the device and
running at the same memory clock.
■
As each PLL can only connect to four global clock nets, while the memory IP
requires more than four clock nets, an external memory interface design cannot
cross from one side of a device to the other side. For example, an external memory
interface design can only exist within a dual regional side of a device.
■
If a single memory interface spans two top or bottom quadrants, a middle top or
bottom PLL must be the source for that interface. The ten dual region clocks that
the single interface require should not block the design using the adjacent PLL (if
available) for a second interface.
f
For more information on clock networks, refer to Clock Networks and PLLs in Stratix III
Devices in the Stratix III Device Handbook and Clock Networks and PLLs in Stratix IV
Devices in the Stratix IV Device Handbook.
f
For more information on multiple memory controllers, refer to Volume 6: Design Flow
Tutorials of the External Memory Interface Handbook.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
1–18
Chapter 1: Select a Device
External Memory Interface Features of Altera Devices
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
2. Pin and Resource Planning
This chapter is for board designers who need to determine the FPGA pin usage, to
create the board layout for the system, as the board design process sometimes occurs
concurrently with the RTL design process.
f
Use this document with the External Memory Interfaces chapter of the relevant device
family handbook.
All external memory interfaces typically require the following FPGA resources:
■
I/O pins
■
PLL and clock network
■
DLL (not applicable in Cyclone III and Cyclone IV GX devices)
■
Other FPGA resources—for example, core fabric logic, and on-chip termination
(OCT) calibration blocks
When you know the requirements for your memory interface, you can then start
planning how you can architect your system. The I/O pins and internal memory
cannot be shared for other applications or memory interfaces. However, if you do not
have enough PLLs, DLLs, or clock networks for your application, you may share
these resources among multiple memory interfaces or modules in your system.
Ideally, any interface should wholly reside in a single bank. However, interfaces that
span multiple adjacent banks or the entire side of a device are also fully supported. In
addition, you may also have wraparound memory interfaces, where the design uses
two adjacent sides of the device and the memory interface logic resides in a device
quadrant. In some cases, top or bottom bank interfaces have higher supported clock
rate than left or right or wraparound interfaces.
f
For the maximum clock rate supported for your memory interface, refer to the
External Memory Interface System Specifications section in volume 1 of the External
Memory Interface Handbook.
f
For information about the terms used in this document, refer to the Glossary chapter in
volume 1 of the External Memory Interface Handbook.
I/O Pins
Any I/O banks that do not support transceiver operations in Arria II GX, Cyclone III,
Cyclone IV GX, Stratix III, and Stratix IV devices, support memory interfaces.
However, DQS (data strobe or data clock) and DQ (data) pins are listed in the device
pin tables and fixed at specific locations in the device. You must adhere to these pin
locations as these locations are optimized in routing to minimize skew and maximize
margin. Always check the external memory interfaces chapters for the number of
DQS and DQ groups supported in a particular device and the pin table for the actual
locations of the DQS and DQ pins.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–2
Chapter 2: Pin and Resource Planning
I/O Pins
For maximum performance and best skew across the interface, each required memory
interface should completely reside within a single I/O bank, or at least one side of the
device. Address and command pins can be constrained in a different side of the
device if there are not enough pins available. For example, you may have the read and
write data pins on the top side of the device, and have the address and command pins
on the left side of the device. In memory interfaces with unidirectional data, you may
also have all the read data pins on the top side of the device and the write data pin on
the left side of the device. However, you should not break a unidirectional pin group
across multiple sides of the device. Memory interfaces typically have the following
pin groups:
■
Write data pin group and read data pin group
■
Address and command pin group
Table 2–1 shows a summary of the number of pins required for various example
memory interfaces. Table 2–1 uses series OCT with calibration, parallel OCT with
calibration, or dynamic calibrated OCT, when applicable, shown by the usage of RUP
and RDN pins.
f
For the memory device pin description, refer to the Memory Standard Overview section
in volume 1 of the External Memory Interface Handbook.
Table 2–1. Pin Counts for Various Example Memory Interfaces (Note 1), (2) (Part 1 of 2)
Memory
Interface
FPGA
DQS Bus
Width
Number
of DQ
Pins
Number
of DQS
Pins
Number of
DM/BWSn
Pins
Number of
Address
Pins (3)
Number of
Command
Pins
Number
of Clock
Pins
RUP/RDN
Pins (4)
Total
Pins
×4
4
2
0 (7)
14
10
2
2
34
×8
8
2
1
14
10
2
2
39
16
4
2
14
10
2
2
50
72
18
9
14
14
4
2
134
DDR3
SDRAM (5),
(6)
×4
4
1
1 (7)
15
9
2
2
34
×8
8
1 (9)
1
15
9
2
2
38
16
2 (9)
2
15
9
2
2
48
72
9 (9)
9
15
12
6
2
125
×4
4
1
1 (7)
14
7
2
2
29
×8
8
1
1
14
7
2
2
33
16
2
2
14
7
2
2
43
72
9
9
13
9
6
2
118
DDR2
SDRAM (8)
DDR SDRAM
(6)
QDR II+
SRAM
QDR II
SRAM
×9
18
2
1
19
3 (10)
4
2
49
×18
36
2
2
18
3 (10)
4
2
67
×36
72
2
4
17
3 (10)
4
2
104
×9
18
2
1
19
2
4
2
48
×18
36
2
2
18
2
4
2
66
×36
72
2
4
17
2
4
2
103
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
I/O Pins
2–3
Table 2–1. Pin Counts for Various Example Memory Interfaces (Note 1), (2) (Part 2 of 2)
Memory
Interface
FPGA
DQS Bus
Width
Number
of DQ
Pins
Number
of DQS
Pins
Number of
DM/BWSn
Pins
Number of
Address
Pins (3)
Number of
Command
Pins
Number
of Clock
Pins
RUP/RDN
Pins (4)
Total
Pins
×9
9
2
1
22
7 (10)
4
2
47
18
2
1
21
7 (10)
6
2
57
×18
36
2
1
20
7 (10)
8
2
76
×9
18
2
1
22
7 (10)
4
2
56
36
2
1
21
7 (10)
6
2
75
72
2
1
20
7 (10)
8
2
112
RLDRAMII
CIO
RLDRAM II
SIO
×18
Notes to Table 2–1:
(1) These example pin counts are derived from memory vendor data sheets. Check the exact number of addresses and command pins of the
memory devices in the configuration that you are using.
(2) PLL and DLL input reference clock pins are not counted in this calculation.
(3) The number of address pins depend on the memory device density.
(4) Some DQS or DQ pins are dual purpose and can also be required as RUP, RDN, or configuration pins. A DQS group is lost if you use these pins
for configuration or as RUP or RDN pins for calibrated OCT. Pick RUP and RDN pins in a DQS group that is not used for memory interface
purposes. You may need to place the DQS and DQ pins manually if you place the RUP and RDN pins in the same DQS group pins.
(5) The TDQS and TDQS# pins are not counted in this calculation, as these pins are not used in the memory controller.
(6) Numbers are based on 1-GB memory devices.
(7) Altera FPGAs do not support DM pins in ×4 mode with differential DQS signaling.
(8) Numbers are based on 2-GB memory devices without using differential DQS, RDQS, and RDQS# pin support.
(9) Assumes single ended DQS mode. DDR2 SDRAM also supports differential DQS, which makes these DQS and DM numbers identical to DDR3
SDRAM.
(10) The QVLD pin that indicates read data valid from the QDR II+ SRAM or RLDRAM II device, is included in this number.
f
1
For more information on the following topics, refer to the External Memory Interface
chapter of the relevant FPGA family handbook.
Maximum interface width varies from device to device depending on the number of
I/O pins and DQS or DQ groups available. Achievable interface width also depends
on the number of address and command pins that the design requires. To ensure
adequate PLL, clock, and device routing resources are available, you should always
test fit any IP in the Quartus II software before PCB sign-off.
Altera devices do not limit the width of external memory interfaces beyond the
following requirements:
■
Maximum possible interface width in any particular device is limited by the
number of DQS groups available.
■
Sufficient clock networks are available to the interface PLL as required by the IP.
■
Sufficient spare pins exist within the chosen bank or side of the device to include
all other address and command, and clock pin placement requirements.
■
The greater the number of banks, the greater the skew, hence Altera recommends
that you always generate a test project of your desired configuration and confirm
that it meets timing.
While you should use the Quartus II software for final pin fitting, you can estimate
whether you have enough pins for your memory interface using the following steps:
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–4
Chapter 2: Pin and Resource Planning
I/O Pins
1. Find out how many read data pins are associated per read data strobe or clock
pair, to determine which column of the DQS and DQ group availability (×4,
×8/×9, ×16/×18, or ×32/×36) look at the pin table.
2. Check the device density and package offering information to see if you can
implement the interface in one I/O bank or on one side or on two adjacent sides.
1
If you target Arria II GX devices and you do not have enough I/O pins to
have the memory interface on one side of the device, you may place them
on the other side of the device. Arria II GX devices are the only family that
allow a memory interface to span across the top and bottom sides of the
device.
3. Calculate the number of other memory interface pins needed, including any other
clocks (write clock or memory system clock), address, command, RUP and RDN, and
any other pins to be connected to the memory components. Ensure you have
enough pins to implement the interface in one I/O bank or one side or on two
adjacent sides.
1
The DQS groups in Arria II GX devices reside on I/O modules, each
consisting of 16 I/O pins. You can only use a maximum of 12 pins per I/O
modules when the pins are used as DQS or DQ pins or HSTL/SSTL output
or HSTL/SSTL bidirectional pins. When counting the number of available
pins for the rest of your memory interface, ensure you do not count the
leftover four pins per I/O modules used for DQS, DQ, address and
command pins. The leftover four pins can be used as input pins only.
f
Refer to the device pinout tables and look for the blank space in the
relevant DQS group column to identify the four pins that cannot be used
in an I/O module.
You should always try the proposed pinouts with the rest of your design in the
Quartus II software (with the correct I/O standard and OCT connections) before
finalizing the pinouts, as there may be some interactions between modules that are
illegal in the Quartus II software that you may not find out unless you try compiling a
design and use the Quartus II Pin Planner.
OCT Support for Arria II GX, Stratix III, and Stratix IV Devices
This section is not applicable to Cyclone III and Cyclone IV GX devices as OCT is not
used by the Altera IP.
f
If you use OCT for your memory interfaces, refer to the Device I/O Features chapter in
the Cyclone III or Cyclone IV GX Device Handbook.
If your system uses any FPGA OCT calibrated series, parallel, or dynamic termination
for any I/O in your design, you need a calibration block for the OCT circuitry. This
calibration block is not required to be within the same bank or side of the device as the
I/O pins it is serving. However, the block requires a pair of RUP and RDN pins that
must be placed within an I/O bank that has the same VCCIO voltage as the VCCIO
voltage of the I/O pins that use the OCT calibration block.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
General Pinout Guidelines
2–5
The RUP and RDN pins in Stratix III and Stratix IV devices are dual functional pins that
can also be used as DQ and DQS pins in Stratix III and Stratix IV devices when they
are not used to support OCT, giving the following impacts on your DQS groups:
■
If the RUP and RDN pins are part of a ×4 DQS group, you cannot use that DQS group
in ×4 mode.
■
If the RUP and RDN pins are part of a ×8 DQS group, you can only use this group in
×8 mode if either of the following conditions apply:
■
You are not using DM or BWSn pins.
■
You are not using a ×8 or ×9 QDR II and QDR II+ SRAM devices, as the RUP and
RDN pins may have dual purpose function as the CQn pins. In this case, pick
different pin locations for RUP and RDN pins, to avoid conflict with memory
interface pin placement. You have the choice of placing the RUP and RDN pins in
the same bank as the write data pin group or address and command pin group.
1
■
The QDR II and QDR II+ SRAM controller with UniPHY do not support ×8
QDR II and QDR II+ SRAM devices in the Quartus II software version 9.1.
You are not using complementary or differential DQS pins
A DQS/DQ ×8/×9 group in Stratix III and Stratix IV devices comprises 12 pins. A
typical ×8 memory interface consists of one DQS, one DM, and eight DQ pins which
add up to 10 pins. If you choose your pin assignment carefully, you can use the two
extra pins for RUP and RDN. However, if you are using differential DQS, you do not
have enough pins for RUP and RDN as you only have one pin leftover. In this case, as
you do not have to put the OCT calibration block with the DQS or DQ pins, you can
pick different locations for the RUP and RDN pins. As an example, you can place it in
the I/O bank that contains the address and command pins, as this I/O bank has the
same VCCIO voltage as the I/O bank containing the DQS and DQ pins.
There is no restriction when using ×16/×18 or ×32/×36 DQS groups that include the
×4 groups when pin members are used as RUP and RDN pins, as there are enough extra
pins that can be used as DQS or DQ pins.
f
You need to pick your DQS and DQ pins manually for the ×8, ×9, ×16 and ×18, or ×32
and ×36 groups, if they are using RUP and RDN pins within the group. The Quartus II
software may not place these pins optimally and may give you a no-fit.
General Pinout Guidelines
Altera recommends that you place all the pins for one memory interface (attached to
one controller) on the same side of the device. For projects where I/O availability is a
challenge and therefore it is necessary spread the interface on two sides, for optimal
performance, place all the input pins on one side, and the output pins on an adjacent
side of the device along with their corresponding source-synchronous clock.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–6
Chapter 2: Pin and Resource Planning
General Pinout Guidelines
1
For a unidirectional data bus as in QDR II and QDR II+ SRAM interfaces, do not split
a read data pin group or a write data pin group onto two sides. It is also strongly
recommended not to split the address and command group onto two sides either,
especially when you are interfacing with QDR II and QDR II+ SRAM
burst-length-of-two devices, where the address signals are double data rate also.
Failure to adhere to these rules may result in timing failure.
In addition, there are some exceptions for the following interfaces:
■
×36 emulated QDR II and QDR II+ SRAM in Arria II GX, Stratix III and Stratix
IV devices
■
RLDRAM II CIO devices—RLDRAM II SIO pinout guidelines are covered in
the general pinout guidelines
■
QDR II/+ SDRAM burst-length-of-two devices
c You need to compile the design in Quartus II to ensure that you are not violating
signal integrity and Quartus II placement rules, which is critical when you have
transceivers in the same design.
The following list gives some general guidelines on how to place pins optimally for
your memory interfaces:
1. For Arria II GX, Stratix III, and Stratix IV designs, if you are using OCT, the RUP
and RDN pins need to be in any bank with the same I/O voltage as your memory
interface signals and often use two DQS and DQ pins from a group. If you decide
to place the RUP and RDN pins in a bank where the DQS and DQ groups are used,
place these pins first and then see how many DQ pins you have left after, to find
out if your data pins can fit in the remaining pins. Refer to “OCT Support for Arria
II GX, Stratix III, and Stratix IV Devices” on page 2–4.
2. Use the PLL that is on the same side of the memory interface. If the interface is
spread out on two adjacent sides, you may use the PLL that is located on either
adjacent side. You must use the dedicated input clock pin to that particular PLL as
the reference clock for the PLL as the input of the memory interface PLL cannot
come from the FPGA clock network.
3. The Altera IP uses the output of the memory interface PLL for the DLL input
reference clock. Therefore, ensure you pick a PLL that can directly feed a suitable
DLL.
1
Alternatively, you can use an external pin to feed into the DLL input
reference clock. The available pins are also listed in the External Memory
Interfaces chapter of the relevant device family handbook. You can also
activate an unused PLL clock outputs , set it at the desired DLL frequency,
and route it to a PLL dedicated output pin. Connect a trace on the PCB from
this output pin to the DLL reference clock pin, but be sure to include any
signal integrity requirements such as terminations.
4. Read data pins require the usage of DQS and DQ group pins to have access to the
DLL control signals.
Device and Pin Planning
© November 2009
Preliminary
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Chapter 2: Pin and Resource Planning
General Pinout Guidelines
1
2–7
In addition, QVLD pins in RLDRAM II and QDR II+ SRAM must use DQS
group pins, when the design uses the QVLD signal. None of the Altera IP
uses QVLD pins as part of read capture, so theoretically you do not need to
connect the QVLD pins if you are using the Altera solution. It is good to
connect it anyway in case the Altera solution gets updated to use QVLD
pins.
5. The read data strobe or read data clock must connect to a DQS pin. In differential
clocking (DDR3/DDR2 SDRAM and RLDRAM II interfaces), connect the negative
leg of the read data strobe or clock to a DQSn pin. In complementary clocking
(QDR II and QDR II+ SRAM interfaces), connect the complement clock (CQn) pin
to the CQn pin (and not the DQSn pin) from the pin table.
6. Write data (if unidirectional) and data mask pins (DM or BWSn) pins must use
DQS groups. While the DLL phase shift is not used, using DQS groups for write
data minimizes skew, and must use the SW and TCCS timing analysis
methodology.
7. Place the write data strobe or write data clock (if unidirectional) in the
corresponding DQS/DQSn pin with the write data groups that place in DQ pins
(except in RLDRAM II CIO devices, refer to “Pinout Rule Exceptions” on
page 2–8)
1
When interfacing with a DDR, or DDR2, or DDR3 SDRAM without
leveling, put the three CK and CK# pairs in a single ×4 DQS group to
minimize skew between clocks and maximize margin for the tDQSS, tDSS, and
tDSH specifications from the memory devices.
8. Place memory clock pins in the following way:
■
© November 2009
For DDR and DDR2 SDRAM, if you are using single-ended DQS signaling, use
any DIFFOUT pins in the same bank or on the same side as the data pins. If you
are using differential DQS signaling, the first CK/CK# pairs (namely
mem_clk[0] or mem_clk_n[0] in the IP) must use any unused DIFFIO_RX
pins in the same bank or on the same side as the data pins. You can use either
Altera Corporation
Device and Pin Planning
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Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
side of the device for wraparound interfaces. This placement allows the mimic
path, for IP VT tracking, to go through differential I/O buffers, to mimic the
differential DQS signals. Any other CK and CK# pairs (mem_clk[n:1] and
mem_clk_n [n:1]) can use any unused DIFFOUT pins in the same bank or
on the same side as the data pins.
■
For DDR3 SDRAM, place the first CK and CK# pairs (namely mem_clk[0] or
mem_clk_n[0] in the IP) and any unused DIFFIO_RX pins in the same bank
or on the same side as the data pins. You can use either side of the device for
wraparound interfaces. This placement allows the mimic path that the IP VT
tracking uses to go through differential I/O buffers to mimic the differential
DQS signals. Any other CK and CK# pairs (mem_clk[n:1] and mem_clk_n
[n:1]) can use any unused DIFFOUT pins in the same bank or on the same
side as the data pins.
■
For QDR II and QDR II+ SRAM, place the K and K# signal on the DQS and
DQSn pins associated with the write data pins. The C and C# clock pins should
also be placed within the write data DQS group.s.
■
For RLDRAM II, place any differential output-capable pins in the same bank as
the address and command pins
9. Place any address pins on any user I/O pin. To minimize skew within the address
pin group, you should place address and command pins in the same bank or side
of the device.
10. Place command pins on any I/O pins and place in the same bank or device side as
the other memory interface pins, especially address and memory clock pins. The
memory device usually uses the same clock to register address and command
signals.
1
In QDR II and QDR II+ SRAM interfaces where the memory clock also
registers the write data, place the address and command pins in the same
I/O bank or same side as the write data pins, to minimize skew.
Pinout Rule Exceptions
The following sub sections described exceptions to the rule described in the “General
Pinout Guidelines” on page 2–5.
Exceptions for ×36 Emulated QDR II and QDR II+ SRAM Interfaces in Arria II GX, Stratix III
and Stratix IV Devices
A few packages in the Arria II GX, Stratix III, and Stratix IV device families do not
offer any ×32/×36 DQS groups where one read clock or strobe is associated with 32 or
36 read data pins. This limitation exists in the following I/O banks:
■
All I/O banks in U358-pin and F572 packages for all Arria II GX devices
■
All I/O banks in F484-pin packages for all Stratix III devices
■
All I/O banks in F780-pin and F1152-pin packages for all Stratix III and Stratix IV
devices
■
Side I/O banks in F1517-pin and F1760-pin packages for all Stratix III devices
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
2–9
■
All I/O banks in F1517-pin for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360,
and EP4SGX530 devices
■
Side I/O banks in F1517-, F1760-, and F1932-pin packages for all Stratix IV devices
This limitation limits support for ×36 QDR II and QDR II+ SRAM devices. To support
these memory devices, this following section describes how you can emulate the
×32/×36 DQS groups for these devices.
c The maximum frequency supported in ×36 QDR II and QDR II+ SRAM interfaces
using ×36 emulation is lower than the maximum frequency when using a native ×36
DQS group.
1
The F484-pin package in Stratix III devices cannot support ×32/×36 DQS group
emulation, as it does not support ×16/×18 DQS groups.
To emulate a ×32/×36 DQS group, combine two ×16/×18 DQS groups together. For
×36 QDR II and QDR II+ SRAM interfaces, the 36-bit wide read data bus uses two
×16/×18 groups; the 36-bit wide write data uses another two ×16/×18 groups or four
×8/×9 groups. The CQ and CQn signals from the QDR II and QDR II+ SRAM device
traces are then split on the board to connect to two pairs of CQ/CQn pins in the
FPGA. You may then need to split the QVLD pins also (if you are connecting them).
These connections are the only connections on the board that you need to change for
this implementation. There is still only one pair of K and Kn# connections on the
board from the FPGA to the memory (see Figure 2–1). Use an external termination for
the CQ/CQn signals at the FPGA end. You can use the FPGA OCT features on the
other QDR II interface signals with ×36 emulation.. In addition, there may be extra
assignments to be added with ×36 emulation.
1
Other QDR II and QDR II+ SRAM interface rules also apply for this implementation.
You may also combine four ×9 DQS groups (or two ×9 DQS groups and one ×18
group) on the same side of the device, if not the same I/O bank, to emulate a x36 write
data group, if you need to fit the QDR II interface in a particular side of the device that
does not have enough ×18 DQS groups available for write data pins. Altera does not
recommend using ×4 groups as the skew may be too large, as you need eight ×4
groups to emulate the ×36 write data bits.
You cannot combine four ×9 groups to create a ×36 read data group as the loading on
the CQ pin is too large and hence the signal is degraded too much.
When splitting the CQ and CQn signals, the two trace lengths that go to the FPGA
pins must be as short as possible to reduce reflection. These traces must also have the
same trace delay from the FPGA pin to the Y or T junction on the board. The total
trace delay from the memory device to each pin on the FPGA should match the Q
trace delay (I2).
1
© November 2009
You must match the trace delays. However, matching trace length is only an
approximation to matching actual delay.
Altera Corporation
Device and Pin Planning
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Pinout Rule Exceptions
Figure 2–1. Board Trace Connection for Emulated x36 QDR II and QDR II+ SRAM Interface
FPGA IOE
D, A
DDR
DDR
length = l1
K
length = l1
Kn
DDR
length = l1
DQ (18-bit)
Q
QDR II
SRAM
length = l2
DDR
Latch
DDR
ena
DQS length = l2
DQS Logic
Block
DQSn length = l2
DQ (18-bit)
CQ
CQn
Q
length = l2
DDR
Latch
DDR
ena
Device and Pin Planning
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Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
2–11
Timing Impact on x36 Emulation
With ×36 emulation, the CQ/CQn signals are split on the board, so these signals see
two loads (to the two FPGA pins)—the DQ signals still only have one load. The
difference in loading gives some slew rate degradation, and a later CQ/CQn arrival
time at the FPGA pin.
The slew rate degradation factor is taken into account during timing analysis when
you indicate in the ALTMEMPHY Preset Editor that you are using ×36 emulation
mode. However, you must determine the difference in CQ/CQn arrival time as it is
highly dependent on your board topology.
The slew rate degradation factor for ×36 emulation assumes that CQ/CQn has a
slower slew rate than a regular ×36 interface. The slew rate degradation is assumed
not to be more than 500 ps (from 10% to 90% VCCIO swing). You may also modify your
board termination resistor to improve the slew rate of the ×36-emulated CQ/CQn
signals. If your modified board does not have any slew rate degradation, you do not
need to enable the ×36 emulation timing in the ALTMEMPHY wizard.
f
For more information on how to determine the CQ/CQn arrival time skew, see
“Determining the CQ/CQn Arrival Time Skew” on page 2–12. .
Because of this effect, the maximum frequency supported using x36 emulation is
lower than the maximum frequency supported using a native x36 DQS group, as
indicated in the Stratix III and Stratix IV device family handbook.
Rules to Combine Groups
f
For information about group combining in Arria II GX devices, refer to the External
Memory Interface chapter in the Arria II GX Device Handbook.
For devices that do not have four ×16/×18 groups in a single side of the device to
form two ×36 groups for read and write data, you can form one ×36 group on one side
of the device, and another ×36 group on the other side of the device. All the read
groups have to be on the same edge (column I/O or row I/O) and all write groups
have to be on the same type of edge (column I/O or row I/O), so you can have an
interface with the read group in column I/O and the write group in row I/O. The only
restriction is that you cannot combine an ×18 group from column I/O with an ×18
group from row IO to form a x36-emulated group.
For vertical migration with the ×36 emulation implementation, check if migration is
possible and enable device migration in the Quartus II software.
1
I/O bank 1C in both Stratix III and Stratix IV devices has dual-function configuration
pins. Some of the DQS pins may not be available for memory interfaces if these are
used for device configuration purposes.
Each side of the device in these packages has four remaining ×8/×9 groups You can
combine four of the remaining for the write side (only) if you want to keep the ×36
QDR II and QDR II+ SRAM interface on one side of the device, by changing the
Memory Interface Data Group default assignment, from the default 18 to 9.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
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Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
1
The ALTMEMPHY megafunction does not support ×36 mode emulation wraparound
interface, where the ×36 group consists of a ×18 group from the top/bottom I/O bank
and a ×18 group from the side I/O banks.
Determining the CQ/CQn Arrival Time Skew
Before compiling a design in Quartus II, you need to determine the CQ/CQn arrival
time skew based on your board simulation. You then need to apply this skew in the
report_timing.tcl file of your QDR II and QDR II+ SRAM interface in the Quartus II
software. Figure 2–2 shows an example of a board topology comparing an emulated
case where CQ is double-loaded and a non-emulated case where CQ only has a single
load.
Figure 2–2. Board Simulation Topology Example
Run the simulation and look at the signal at the FPGA pin. Figure 2–3 shows an
example of the simulation results from Figure 2–2. As expected, the double-loaded
emulated signal, in pink, arrives at the FPGA pin later than the single-loaded signal,
in red. You then need to calculate the difference of this arrival time at VREF level (0.75
V in this case). Record the skew and re-run the simulation in the other two cases
(slow-weak and fast-strong). To pick the largest and smallest skew to be included in
Quartus II timing analysis, follow these steps:
1. Open the <variation_name>_report_timing.tcl and search for
tmin_additional_dqs_variation.
2. Set the minimum skew value from your board simulation to
tmin_additional_dqs_variation.
Device and Pin Planning
© November 2009
Preliminary
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Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
2–13
3. Set the maximum skew value from your board simulation to
tmax_additional_dqs_variation.
4. Save the .tcl file.
Figure 2–3. Board Simulation Results
Exceptions for RLDRAM II Interfaces
RLDRAM II CIO devices have one bidirectional bus for the data, but there are two
different sets of clocks: one for read and one for write. As the QK and QK# already
occupies the DQS and DQSn pins needed for read, placement of DK and DK# pins are
restricted due to the limited number of pins in the FPGA. This limitations causes the
exceptions to the previous rules, which are discussed in the following sections.
1
DK and DK# signals need to use DQS- and DQSn-capable pins to ensure accurate
timing analysis, as the TCCS specifications are characterized using DQS and DQSn
pins. As you must use the DQS and DQSn pins for the DQS group to connect to QK
and QK# pins, pick a pair of DQ pins that are DQS and DQSn pins when configured
as a smaller DQS group size. For example, if the interfaces uses a ×16/×18 DQS group,
the DQS and DQSn pins connect to QK and QK# pins, pick differential DQ pin pairs
from that DQS group that are DQS and DQSn pins for ×8/×9 DQS groups or ×4 DQS
groups.
Interfacing with ×9 RLDRAM II CIO Devices
These devices have the following pins:
© November 2009
■
2 pins for QK and QK# signals
■
9 DQ pins (in a ×8/×9 DQS group)
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Device and Pin Planning
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Chapter 2: Pin and Resource Planning
Pinout Rule Exceptions
■
2 pins for DK and DK# signals
■
1 DM pin
■
1 QVLD pins
■
15 pins total
In the FPGA, the ×8/×9 DQS group consists of 12 pins: 2 for the read clocks and 10 for
the data. In this case, move the QVLD (if you want to keep this connected even
though this is not used in the Altera memory interface solution) and the DK and DK#
pins to the adjacent DQS group. If that group is in use, move to any available user I/O
pins in the same I/O bank. The DK and DK# must use DQS- and DQSn-capable pins.
Interfacing with ×18 RLDRAM II CIO Devices
These devices have the following pins:
■
4 pins for QK/QK# signals
■
18 DQ pins (in ×8/×9 DQS group)
■
2 pins for DK/DK# signals
■
1 DM pin
■
1 QVLD pins
■
26 pins total
In the FPGA, you use two ×8/×9 DQS group totaling 24 pins: 4 for the read clocks and
20 for the data. In this case, move the DK and DK# pins to DQS- and DQSn-capable
pins in the adjacent DQS group. Or if that group is in use, move to any DQS- and
DQSn-capable pins in the same I/O bank.
Each ×8/×9 group has one DQ pin left over that can either use QVLD or DM, so one
×8/×9 group has the DM pin associated with that group and one ×8/×9 group has the
QVLD pin associated with that group.
Interfacing with RLDRAM II ×36 CIO Devices
These devices have the following pins:
■
4 pins for QK/QK# signals
■
36 DQ pins (in x16/x18 DQS group)
■
4 pins for DK/DK# signals
■
1 DM pins
■
1 QVLD pins
■
46 pins total
In the FPGA, you use two ×16/×18 DQS groups totaling 48 pins: 4 for the read clocks
and 36 for the read data. Configure each ×16/×18 DQS group to have:
■
Two QK/QK# pins occupying the DQS/DQSn pins
■
Pick two DQ pins in the ×16/×18 DQS groups that are DQS and DQSn pins in the
×4 or ×8/×9 DQS groups for the DK and DK# pins
■
18 DQ pins occupying the DQ pins
Device and Pin Planning
© November 2009
Preliminary
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Chapter 2: Pin and Resource Planning
Pin Connection Guidelines Tables
■
2–15
There are two DQ pins leftover that you can use for QVLD or DM pins. Put the
DM pin in the group associated with DK[1] and the QVLD pin in the group
associated with DK[0].
1
Check that DM is associated with DK[1] for your chosen memory
component.
Exceptions for QDR II and QDR II+ SRAM Burst-Length-Of-Two Interfaces
Altera IP does not support QDR II and QDR II+ SRAM burst-length-of-two devices. If
you are using the QDR II SRAM controller with UniPHY or creating your own
interface for QDR II and QDR II+ SRAM burst-length-of-two devices, you may want
to place the address pins in a DQS group also, because these pins are now double data
rate too. The address pins typically do not exceed 22 bits, so you may use one ×18
DQS groups or two ×9 DQS groups on the same side of the device, if not the same I/O
bank. In Stratix III and Stratix IV devices, one ×18 group typically has 22 DQ bits and
2 pins for DQS/DQSn pins, while one ×9 group typically has 10 DQ bits with 2 pins
for DQS/DQSn pins. Using ×4 DQS groups should be a last resort.
Pin Connection Guidelines Tables
Table 2–2 shows the FPGA pin utilizations for DDR, DDR2 SDRAM, and DDR3
SDRAM without leveling interfaces.
Table 2–2. DDR, DDR2 SDRAM, and DDR3 SDRAM Without Leveling Interface Pin Utilization (Part 1 of 3)
FPGA Pin Utilization
Interface
Pin
Description
Memory Device Pin
Name
Arria II GX Devices
Cyclone III and
Cyclone IV GX Devices
Stratix III and
Stratix IV Devices
Data
DQ
Data mask
DM
Data strobe
DQS or DQS and
DQSn (DDR2 and
DDR3 SDRAM only)
DQS (S in the Quartus II Pin Planner) for single-ended DQS signaling or DQS and
DQSn (S and Sbar in the Quartus II Pin Planner) for differential DQS signaling. DDR2
supports either single-ended or differential DQS signaling. However, Cyclone III and
Cyclone IV GX devices do not support differential DQS signaling. DDR3 SDRAM
mandates differential DQS signaling.
Address and
command
A[], BA[], CAS#, CKE,
CS#, ODT, RAS#,
WE#, RESET#
Any user I/O pin. To minimize skew, you should place address and command pins in
the same bank or side of the device as the following pins: CK/CK# pins, DQ, DQS, or
DM pins. The reset# signal is only available in DDR3 SDRAM interfaces. The
RESET# pin uses 1.5-V CMOS I/O standard, so you should not terminate this signal
to VTT.
© November 2009
DQ in the pin table, marked as Q in the Quartus II Pin Planner. Each DQ group has a
common background color for all of the DQ and DM pins, associated with DQS (and
DQSn) pins.
Altera Corporation
Device and Pin Planning
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Chapter 2: Pin and Resource Planning
Pin Connection Guidelines Tables
Table 2–2. DDR, DDR2 SDRAM, and DDR3 SDRAM Without Leveling Interface Pin Utilization (Part 2 of 3)
FPGA Pin Utilization
Interface
Pin
Description
Memory Device Pin
Name
Memory
CK and CK#
system clock
Arria II GX Devices
If you are using single-ended
DQS signaling, any unused DQ
or DQS pins with DIFFOUT
capability located in the same
bank or on the same side as
the data pins.
If you are using differential
DQS signaling, the first
CK/CK# pairs (namely
mem_clk[0] or
mem_clk_n[0] in the IP)
must use any unused DQ or
DQS pins with DIFFIO_RX
or DIFFIN capability in the
same bank or on the same side
as the data pins. You can use
either side of the device for
wraparound interfaces.
This placement allows the
mimic path that the IP VT
tracking uses to go through
differential I/O buffers to
mimic the differential DQS
signals. If there are other
CK/CK# pairs
(mem_clk[n:1] and
mem_clk_n[n:1] where n
<= 1), place on DIFF_OUT in
the same single DQ group of
adequate width to minimize
skew.
For example, DIMMs requiring
three memory clock pin-pairs
need to use a ×4 DQS group,
where mem_clk[0] and
mem_clk_n[0] pins use
the DIFFIO_RX or DIFFIN
pins in that group, while,
mem_clk[2:1] and
mem_clk_n[2:1] pins use
DIFF_OUT pins in that DQS
group.
Device and Pin Planning
Cyclone III and
Cyclone IV GX Devices
Stratix III and
Stratix IV Devices
Any differential I/O pin
pair (DIFFOUT) in the
same bank or on the
same side as the data
pins. You can use either
side of the device for
wraparound interfaces.
If you are using
single-ended DQS
signaling, any
DIFFOUT pins in the
same bank or on the
same side as the data
pins.
mem_clk[0] and
mem_clk_n[0]
cannot be placed in the
same row or column pad
group as any of the DQ
pins (Figure 2–4 and
Figure 2–5).
If you are using
differential DQS
signaling, the first
CK/CK# pairs (namely
mem_clk[0] or
mem_clk_n[0] in
the IP) must use any
unused DIFFIO_RX
pins in the same bank
or on the same side as
the data pins. You can
use either side of the
device for wraparound
interfaces.
This placement allows
the mimic path that the
IP VT tracking uses to
go through differential
I/O buffers to mimic the
differential DQS
signals. If there are
other CK/CK# pairs
(mem_clk[n:1] and
mem_clk_n[n:1]
where n <= 1), place on
DIFF_OUT in the
same single DQ group
of adequate width to
minimize skew.
For example, DIMMs
requiring three memory
clock pin-pairs need to
use a ×4 DQS group,
where mem_clk[0]
and mem_clk_n[0]
pins use the
DIFFIO_RX or
DIFFIN pins in that
group, while,
mem_clk[2:1] and
mem_clk_n[2:1]
pins use DIFF_OUT
pins in that DQS group.
© November 2009
Preliminary
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Chapter 2: Pin and Resource Planning
Pin Connection Guidelines Tables
2–17
Table 2–2. DDR, DDR2 SDRAM, and DDR3 SDRAM Without Leveling Interface Pin Utilization (Part 3 of 3)
FPGA Pin Utilization
Interface
Pin
Description
Memory Device Pin
Name
Arria II GX Devices
Cyclone III and
Cyclone IV GX Devices
Stratix III and
Stratix IV Devices
Dedicated PLL clock
input pin with direct (not
using a global clock net)
connection to the PLL
Dedicated PLL clock
input pin with direct
(not using a global
clock net) connection to
the PLL. Ensure that the
PLL can supply the
input reference clock to
the DLL also, otherwise
refer to alternative DLL
input reference clocks
(“General Pinout
Guidelines” on
page 2–5).
Clock Source —
Dedicated PLL clock input pin
with direct (not using a global
clock net) connection to the
PLL. Ensure that the PLL can
supply the input reference
clock to the DLL also,
otherwise refer to alternative
DLL input reference clocks
(“General Pinout Guidelines”
on page 2–5).
Reset
Dedicated clock input pin to accommodate the high fan-out signal.
—
Figure 2–4 shows an example of placing mem_clk[0] and mem_clk_n[0]
incorrectly. As you can see, mem_clk[0] pin is placed at the same column pad group s
mem_dq pin (in column X = 1). This placement results in the Quartus II software
showing the following critical warning:
Register <name> fed by pin mem_clk[0] must be placed in adjacent LAB X:1
Y:0 instead of X:2 Y:0
1
Placing the mem_clk[0] pin on the same row or column pad group as the DQ pin pins
will also result in the failure to constrain the DDIO input nodes correctly and close
timing. Hence, the Read Capture and Write timing margins computed by Time Quest
may not be valid due to the violation of assumptions made by the timing scripts.
Figure 2–4. Incorrect Placement of mem_clk[0] and mem_clk_n[0] in Cyclone III and Cyclone IV
Devices.
To eliminate this critical warning, place the mem_clk[0] pin at different column or
row from the data pin (Figure 2–5).
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–18
Chapter 2: Pin and Resource Planning
Pin Connection Guidelines Tables
Figure 2–5. Correct Placement of mem_clk[0] and mem_clk_n[0] in Cyclone III and Cyclone IV
Devices.
Table 2–3 shows the FPGA pin utilizations for DD3 SDRAM with leveling interfaces.
Table 2–3. DDR3 SDRAM With Leveling Interface Pin Utilization Applicable for Stratix III and Stratix IV Devices
Interface Pin
Description
Memory Device Pin
Name
Data
DQ
Data Mask
DM
FPGA Pin Utilization
DQ in the pin table, marked as Q in the Quartus II Pin Planner. Each DQ
group has a common background color for all of the DQ and DM pins,
associated with DQS (and DQSn) pins. The ×4 DIMM has the following
mapping between DQS and DQ pins:
■
DQS[0] maps to DQ[3:0]
■
DQS[9] maps to DQ[7:4]
■
DQS[1] maps to DQ[11:8]
■
DQS[10] maps to DQ[15:12]
The DQS pin index in other DIMM configurations typically increases
sequentially with the DQ pin index (DQS[0]: DQ[3:0]; DQS[1]:
DQ[7:4]; DQS[2]: DQ[11:8])
Data Strobe
DQS and DQSn
DQS and DQSn (S and Sbar in the Quartus II Pin Planner)
Address and Command
A[], BA[], CAS#, CKE,
CS#, ODT, RAS#, WE#,
RESET#
Any user I/O pin. To minimize skew, you should place address and
command pins in the same bank or side of the device as the following
pins: CK/CK# pins, DQ, DQS, or DM pins. The RESET# pin uses 1.5-V
CMOS I/O standard, so you should not terminate this signal to VTT.
Memory system clock
CK and CK#
The first CK/CK# pairs (namely mem_clk[0] or mem_clk_n[0]
in the IP) must use any unused DQS and DQSn pins with
DIFFIO_RX pins in the same bank or on the same side as the data
pins. You can use either side of the device for wraparound interfaces.
This placement is to allow the mimic path used in the IP VT tracking to
go through differential I/O buffers to mimic the differential DQS
signals. Any other CK/CK# pairs (mem_clk[n:1] and mem_clk_n
[n:1]) can use any unused DQS and DQSn pins in the same bank or
on the same side as the data pins. The DQS and DQSn pins are needed
to allow access to the leveling circuitry.
Clock Source
—
Dedicated PLL clock input pin with direct (not using a global clock net)
connection to the PLL and optional DLL required by the interface.
Reset
—
Dedicated clock input pin to accommodate the high fan-out signal
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
Pin Connection Guidelines Tables
2–19
Table 2–4 shows the FPGA pin utilizations for QDR II and QDR II+ SRAM interfaces.
Table 2–4. QDR II and QDR II+ SRAM Pin Utilization for Arria II GX, Stratix III, and Stratix IV Devices
Memory Device Pin
Name
Interface Pin Description
FPGA Pin Utilization
Read Clock
CQ and CQn
DQS and CQn pins (S and Qbar in the Quartus II pin planner).
Read Data
Q
Data Valid
QVLD
DQ pins (Q in the Quartus II pin planner). Ensure that you are
using the DQ pins associated with the chosen read clock pins
(DQS and CQn pins). QVLD pins are only available for QDR II+
SRAM dvices and note that Altera IP does not use the QVLD
pin.
Memory and Write Data Clock
K and K#
DQS and DQSn pins (S and Sbar in the Quartus II Pin
Planner)
Write Data
D
Byte Write Select
BWS#, NWS#
DQ pins. Ensure that you are using the DQ pins associated
with the chosen memory and write data clock pins (DQS and
DQS pins).
Address and Control Signals
A, WPS#, RPS#
Any user I/O pin. To minimize skew, you should place address
and command pins in the same bank or side of the device as
the following pins: K and K# pins, DQ, DQS, BWS#, and
NWS# pins. If you are using burst-length-of-two devices,
place the address signals in a DQS group pin as these signals
are now double data rate.
Clock source
—
Dedicated PLL clock input pin with direct (not using a global
clock net) connection to the PLL and optional DLL required by
the interface.
Reset
—
Dedicated clock input pin to accommodate the high fan-out
signal
Table 2–5 shows the FPGA pin utilizations for RLDRAM II CIO interfaces.
Table 2–5. RLDRAM II CIO Pin Utilization for Stratix III, and Stratix IV Devices
Interface
Pin
Description
Memory Device
Pin Name
FPGA Pin Utilization
Read Clock
QK and QK#
DQS and DQSn pins (S and Sbar in the Quartus II Pin Planner)
Data
Q
Data Valid
QVLD
Data Mask
DM
DQ pins (Q in the Quartus II pin planner). Ensure that you are using the DQ pins
associated with the chosen read clock pins (DQS and DQSn pins). Altera IP does not
use the QVLD pin. You may leave this pin unconnected on your board. You may not be
able to fit these pins in a DQS group. Refer to “Exceptions for RLDRAM II Interfaces”
on page 2–13, for more information on how to place these pins.
Write Data
Clock
DK and DK#
DQ pins in the same DQS group as the read data (Q) pins or in adjacent DQS group or
in the same bank as the address and command pins. Refer to “Exceptions for RLDRAM
II Interfaces” on page 2–13, for more details. DK/DK# must use differential
output-capable pins.
Memory
Clock
CK and CK#
Any differential output-capable pins in the same bank as the address and command
pins
Address
and Control
Signals
A, BA, CS#, REF#,
WE#
Any user I/O pin. To minimize skew, you should place address and command pins in the
same bank or side of the device as the following pins: CK/CK# pins, DQ, DQS, and DM
pins.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–20
Chapter 2: Pin and Resource Planning
PLLs and Clock Networks
Table 2–5. RLDRAM II CIO Pin Utilization for Stratix III, and Stratix IV Devices
Interface
Pin
Description
Memory Device
Pin Name
FPGA Pin Utilization
Clock
source
—
Dedicated PLL clock input pin with direct (not using a global clock net) connection to
the PLL and optional DLL required by the interface.
Reset
—
Dedicated clock input pin to accommodate the high fan-out signal
Table 2–6 shows the FPGA pin utilizations for RLDRAM II SIO interfaces.
Table 2–6. RLDRAM II SIO Pin Utilization Applicable for Stratix III, and Stratix IV Devices
Interface Pin
Description
Memory Device Pin
Name
FPGA Pin Utilization
Read Clock
QK and QK#
DQS and DQSn pins (S and Sbar in the Quartus II Pin Planner) in the same
DQS group as the respective read data (Q) pins.
Read Data
Q
Data valid
QVLD
DQ pins (Q in the Quartus II pin planner). Ensure that you are using the DQ
pins associated with the chosen read clock (DQS and DQSn) pins. Altera does
not use the QVLD pin. You may leave this pin unconnected on your board.
Memory and
Write Data
Clock
DK and DK#
DQS and DQSn pins (S and Sbar in the Quartus II Pin Planner) in the same
DQS group as the respective read data (Q) pins.
Write Data
D
Data Mask
DM
DQ pins. Ensure that you are using the DQ pins associated with the chosen
write data clock (DQS and DQSn) pins.
Memory Clock CK and CK#
Any differential output-capable pins in the same bank as the address and
command pins
Address and
Control
Signals
A, BA, CS#, REF#, WE#
Any user I/O pin. To minimize skew, you should place address and command
pins in the same bank or side of the device as the following pins: CK/CK# pins,
DQ, DQS, or DM pins.
Clock source
—
Dedicated PLL clock input pin with direct (not using a global clock net)
connection to the PLL and optional DLL required by the interface.
Reset
—
Dedicated clock input pin to accommodate the high fan-out signal
PLLs and Clock Networks
The exact number of clocks and hence PLLs required in your design depends greatly
on the memory interface frequency, and the IP that your design uses.
For example, you can build simple DDR slow-speed interfaces that typically require
only two clocks: system and write. You can then use the rising and falling edges of
these two clocks to derive four phases (0, 90, 180, and 270°). However, as clock speeds
increase, the timing margin decreases and additional clocks are required, to optimize
setup and hold and meet timing. Typically, at higher clock speeds, you need to have
dedicated clocks for resynchronization, and address and command paths.
In addition, some memory controller designs that use the ALTMEMPHY
megafunction, use a VT tracking clock to measure and compensate for VT changes
and their effects.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
PLLs and Clock Networks
2–21
Altera memory interface IP uses one PLL, which generates the various clocks needed
in the memory interface data path and controller, and provides the required phase
shifts for the write clock and address and command clock. The PLL is instantiated
when you generate the Altera memory interface MegaCore functions or
megafunctions.
By default, the PLL also generates the input reference clock for the DLL, available in
all device families except for the Cyclone III and Cyclone IV GX devices. This method
eliminates the need of an extra pin for the DLL input reference clock.
The input reference clock to the DLL can come from certain input clock pins or clock
output from certain PLLs.
f
For the actual pins and PLLs connected to the DLLs, refer to the External Memory
Interfaces chapter of the relevant device family handbook.
You must use the PLL located in the same device quadrant or side as the memory
interface and the corresponding dedicated clock input pin for that PLL, to ensure
optimal performance and accurate timing results from the Quartus II software. The
input clock to the PLL should not fan out to any logic other than the PHY, as you
cannot use a global clock resource for the path between the clock input pin to the PLL.
Table 2–7 and Table 2–8 show a comparison of the number of PLLs and dedicated
clock outputs available respectively in Arria II GX, Cyclone III, Stratix III, and Stratix
IV devices.
Table 2–7. Number of PLLs Available in Altera Device Families (Note 1)
Device Family
Enhanced PLLs Available
Arria II GX
4-6
Cyclone III and Cyclone IV GX
2-4
Stratix III
4-12
Stratix IV
3-12
Notes to Table 2–7:
(1) For more details, refer to the Clock Networks and PLL chapter of the respective device family handbook.
Table 2–8. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Altera
Device Families (Note 1) (Part 1 of 2)
Device Family
Arria II GX (2)
Number of Enhanced PLL Clock
Outputs
4 clock outputs each
Number Dedicated Clock Outputs
1 single-ended or 1 differential pair
3 single-ended or 3 differential pair total
(3)
Cyclone III and
Cyclone IV GX
5 clock outputs each
1 single-ended or 1 differential pair total
(not for memory interface use)
Stratix III
Left/right: 7 clock outputs
Left/right: 2 single-ended or 1
differential pair
Top/bottom: 10 clock outputs
Top/bottom: 6 single-ended or 4
single-ended and 1 differential pair
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–22
Chapter 2: Pin and Resource Planning
PLLs and Clock Networks
Table 2–8. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Altera
Device Families (Note 1) (Part 2 of 2)
Number of Enhanced PLL Clock
Outputs
Device Family
Stratix IV
Left/right: 7 clock outputs
Number Dedicated Clock Outputs
Left/right: 2 single-ended or 1
differential pair
Top/bottom: 10 clock outputs
Top/bottom: 6 single-ended or 4
single-ended and 1 differential pair
Note to Table 2–8:
(1) For more details, refer to the Clock Networks and PLL chapter of the respective device family handbook.
(2) PLL_5 and PLL_6 of Arria II GX devices do not have dedicated clock outputs.
(3) The same PLL clock outputs drives three single-ended or three differential I/O pairs, which are only supported in
PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
Table 2–9 shows the number of clock networks available in the Altera device families.
Table 2–9. Number of Clock Networks Available in Altera Device Families (Note 1)
Device Family
Global Clock Network
Regional Clock Network
10-20
N/A
Stratix III
16
64-88
Stratix IV
16
64-88
Cyclone III and
Cyclone IV GX
Note to Table 2–9:
(1) For more information on the number of available clock network resources per device quadrant to better understand
the number of clock networks available for your interface, refer to the Clock Networks and PLL chapter of the
respective device family handbook.
1
You must decide whether you need to share clock networks, PLL clock outputs, or
PLLs if you are implementing multiple memory interfaces.
Table 2–10 shows the number of PLL outputs and clock networks required for the
memory solution using Altera IPs. Table 2–11 shows the names and frequency of the
clocks used.
Table 2–10. Clock Network Usage in Altera IP
DDR3 SDRAM
DDR2/DDR SDRAM
Half-Rate
Device
ArriaII GX
Half-Rate
Number of
full-rate
clock
Number of
half-rate
clock
4 global
2 global
Cyclone III
N/A
Stratix III
and Stratix
IV
1 global 2
regional
2 regional
Number of
full-rate
clock
Full-Rate
Number of
half-rate
clock
Number of
full-rate
clock
Number of
half-rate
clock
1 global
4 global
2 global
5 global
4 global
1 global
5 global
1 regional 2
dual-regional
1 global 2
dual-region
al
1 global 2
dual-region
al
Device and Pin Planning
© November 2009
Preliminary
2
dual-region
al
Altera Corporation
Chapter 2: Pin and Resource Planning
PLLs and Clock Networks
2–23
Table 2–11. Clocks Used in the ALTMEMPHY Megafunction (Note 1)
Clock Name
Usage Description
phy_clk_1x
Static system clock for the half-rate data path and controller.
mem_clk_2x
Static DQS output clock that generates DQS, CK/CK# signals, the input reference clock to the
DLL, and the system clock for the full-rate datapath and controller.
mem_clk_1x
This clock drives the aux_clk output or clocking DQS and as a reference clock for the
memory devices.
write_clk_2x
Static DQ output clock used to generate DQ signals at 90o earlier than DQS signals. Also may
generate the address and command signals.
mem_clk_ext_2x
This clock is only used if the memory clock generation uses dedicated output pins. Applicable
only in HardCopy II or Stratix II prototyping for HardCopy II designs.
resynch_clk_2x
Dynamic-phase clock used for resynchronization and postamble paths. Currently, this clock
cannot be shared by multiple interfaces.
measure_clk_2x/
measure_clk_1x (2)
Dynamic-phase clock used for VT tracking purposes. Currently, this clock cannot be shared by
multiple interfaces.
ac_clk_2x
Dedicated static clock for address and command signals.
ac_clk_1x
scan_clk
Static clock to reconfigure the PLL
seq_clk
Static clock for the sequencer logic
Notes to Table 2–11:
(1) For more information on the clocks used in the ALTMEMPHY megafunction, refer to the Clock Networks and PLL chapter of the respective
device family handbook for more details.
(2) This clock should be of the same clock network clock as the resync_clk_2x clock.
In every ALTMEMPHY solution, the measure_clk and resync_clk_2x clocks
(Table 2–11) are calibrated and hence may not be shared or used for other modules in
your system. You may be able to share the other statically phase-shifted clocks with
other modules in your system provided that you do not change the clock network
used.
Changing the clock network that the ALTMEMPHY solution uses may affect the
output jitter, especially if the clock is used to generate the memory interface output
pins. Always check the clock network output jitter specification in the DC and
Switching Characteristics chapter of the device handbook, before changing the
ALTMEMPHY clock network, to ensure that it meets the memory standard jitter
specifications, which includes period jitter, cycle-to-cycle jitter and half duty cycle
jitter.
If you need to change the resync_clk_2x clock network, you have to change the
measure_clk_1x clock network also to ensure accurate VT tracking of the memory
interface.
f
For more information about sharing clocks in multiple controllers, refer to Volume 6:
Design Flow Tutorials of the External Memory Interface Handbook.
In addition, you should not change the PLL clock numbers as the wizard-generated
.sdc file assumes certain counter outputs from the PLL (Table 2–12 through
Table 2–13).
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–24
Chapter 2: Pin and Resource Planning
PLL Cascading
Table 2–12. PLL Usage for DDR and DDR2 SDRAM and DDR3 SDRAM without leveling Interfaces
Clock
C0
C1
C2
C3
Arria II GX Devices
Cyclone III and Cyclone IV GX
Devices
Stratix III and Stratix IV Devices
■
phy_clk_1x in half-rate
designs
■
phy_clk_1x in half-rate
designs
■
phy_clk_1x in half-rate
designs
■
aux_half_rate_clk
■
aux_half_rate_clk
■
aux_half_rate_clk
■
PLL scan_clk
■
PLL scan_clk
■
phy_clk_1x in full-rate
designs
■
phy_clk_1x in full-rate
designs
■
mem_clk_2x
■
aux_full_rate_clk
■
aux_full_rate_clk
■
mem_clk_2x to generate
DQS and CK/CK# signals
■
mem_clk_2x to generate
DQS and CK/CK# signals
■
ac_clk_2x
■
ac_clk_2x
■
cs_n_clk_2x
■
cs_n_clk_2x
■
Unused
■
write_clk_2x (for DQ)
■
■
ac_clk_2x
phy_clk_1x in full-rate
designs
■
cs_n_clk_2x
■
aux_full_rate_clk
■
resynch_clk_2x
■
write_clk_2x
measure_clk_2x
■
resync_clk_2x
■
write_clk_2x (for DQ)
■
ac_clk_2x
■
cs_n_clk_2x
C4
■
resync_clk_2x
■
C5
■
measure_clk_2x
—
■
measure_clk_1x
C6
—
—
■
ac_clk_1x
Table 2–13. PLL Usage for DDR3 SDRAM With Leveling Interfaces
Clock
C0
Stratix III and Stratix IV Devices
■
phy_clk_1x in half-rate designs
■
aux_half_rate_clk
■
PLL scan_clk
C1
■
mem_clk_2x
C2
■
aux_full_rate_clk
C3
■
write_clk_2x
C4
■
resync_clk_2x
C5
■
measure_clk_1x
C6
■
ac_clk_1x
PLL Cascading
Stratix III PLLs, Stratix IV PLLs, and the two middle PLLs in Arria II GX EP2AGX125
EP2AGX190, and EP2AGX260 devices can be cascaded using either the global or
regional clock trees, or the cascade path between two adjacent PLLs.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
DLL
1
2–25
Use this feature at your own risk. You should use faster memory devices to maximize
timing margins.
Cyclone III and Cyclone IV GX devices do not support PLL cascading for external
memory interfaces.
ALTMEMPHY supports PLL cascading using the cascade path without any
additional timing derating when the bandwidth and compensation rules are
followed. The timing constraints and analysis assume that there is no additional jitter
due to PLL cascading when the upstream PLL uses no compensation and low
bandwidth, and the downstream PLL uses no compensation and high bandwidth.
ALTMEMPHY does not support PLL cascading using the global and regional clock
networks. You can implement PLL cascading at your own risk without any additional
guidance and specifications from Altera. The Quartus II software does issue a critical
warning suggesting use of the cascade path to minimize jitter, but does not explicitly
state that Altera does not support cascading using global and regional clock networks.
1
The Quartus II software does not issue a critical warning stating that Cyclone III
ALTMEMPHY designs do not support PLL cascading; it issues the Stratix III warning
message requiring use of cascade path.
Some Arria II GX devices (EP2AGX125, EP2AGX190, and EP2AGX260) have direct
cascade path for two middle right PLLs. Arria II GX PLLs have the same bandwidth
options as Stratix IV GX left and right PLLs.
DLL
The Altera memory interface IP uses one DLL (except in Cyclone III and
Cyclone IV GX devices, where this resource is not available). The DLL is located at the
corner of the device and can send the control signals to shift the DQS pins on its
adjacent sides for Stratix-series devices, or DQS pins in any I/O banks in Arria II GX
devices.
For example, the top-left DLL can shift DQS pins on the top side and left side of the
device. The DLL generates the same phase shift resolution for both sides, but can
generate different phase offset to the two different sides, if needed. Each DQS pin can
be configured to use or ignore the phase offset generated by the DLL.
The DLL cannot generate two different phase offsets to the same side of the device.
However, you can use two different DLLs to for this functionality.
DLL reference clocks must come from either dedicated clock input pins located on
either side of the DLL or from specific PLL output clocks. Any clock running at the
memory frequency is valid for the DLLs.
To minimize the number of clocks routed directly on the PCB, typically this reference
clock is sourced from the memory controllers PLL. In general, DLLs can use the PLLs
directly adjacent to them (corner PLLs when available) or the closest PLL located in
the two sides adjacent to its location.
1
© November 2009
By default, the DLL reference clock in Altera external memory IP is from a PLL
output.
Altera Corporation
Device and Pin Planning
Preliminary
2–26
Chapter 2: Pin and Resource Planning
DLL
When designing for 780-pin packages with SE80, SE110 and SL150 devices, the PLL to
DLL reference clock connection is limited.
Figure 2–6 shows the 780-pin package devices PLL and DLL reference clock
connections. DLL3 is isolated from a direct PLL connection and can only receive a
reference clock externally from pins clk[11:4]p.
Figure 2–6. PLL and DLL Reference Clock Connections in 780-pin Package Devices
Optional Clock Connection
DLL1
PLL_T1
PLL_L1
DLL2
DLL4
PLL_R1
PLL_B1
DLL3
Optional Clock Connection
The DLL reference clock should be the same frequency as the memory interface, but
the phase is not important.
The required DQS capture phase is optimally chosen based on operating frequency
and external memory interface type (DDR, DDR2, DDR3 SDRAM, and QDR II SRAM,
or RLDRAM II). As each DLL supports two possible phase offsets, two different
memory interface types operating at the same frequency can easily share a single
DLL. More may be possible, depending on the phase shift required.
f
Altera memory IP always specifies a default optimal phase setting, to override this
setting, refer to the DDR and DDR2 SDRAM High-Performance Controller and
ALTMEMPHY IP User Guide section and the DDR3 SDRAM High-Performance
Controller and ALTMEMPHY IP User Guide section in volume 3 of the External Memory
Interface Handbook.
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Chapter 2: Pin and Resource Planning
Other FPGA Resources
2–27
When sharing DLLs, your memory interfaces must be of the same frequency. If the
required phase shift is different amongst the multiple memory interfaces, you can use
a different delay chain in the DQS logic block or use the DLL phase offset feature.
To simplify the interface to IP connections, multiple memory interfaces operating at
the same frequency usually share the same system and static clocks as each other
where possible. This sharing minimizes the number of dedicated clock nets required
and reduces the number of different clock domains found within the same design.
As each DLL can directly drive four banks, but each PLL only has complete C (output)
counter coverage of two banks (using dual regional networks), situations can occur
where a second PLL operating at the same frequency is required. As cascaded PLLs
increase jitter and reduce timing margin, you are advised to first ascertain if an
alternative second DLL and PLL combination is not available and more optimal.
Select a DLL that is available for the side of the device where the memory interface
resides. If you select a PLL or a PLL input clock reference pin that can also serve as the
DLL input reference clock, you do not need an extra input pin for the DLL input
reference clock.
Other FPGA Resources
The Altera memory interface IP uses FPGA fabric, including registers and the
TriMatrix Memory Block to implement the memory interface.
f
For resource utilization examples to ensure that you can fit your other modules in the
device, refer to the DDR and DDR2 SDRAM High-Performance Controller and
ALTMEMPHY IP User Guide section and the DDR3 SDRAM High-Performance
Controller and ALTMEMPHY IP User Guide section in volume 3 of the External Memory
Interface Handbook.
In addition, one OCT calibration block is used if you are using the FPGA OCT feature
in the memory interface.The OCT calibration block uses two pins (RUP and RDN),
(“OCT Support for Arria II GX, Stratix III, and Stratix IV Devices” on page 2–4). You
can select any of the available OCT calibration block as you do not need to place this
block in the same bank or device side of your memory interface. The only requirement
is that the I/O bank where you place the OCT calibration block uses the same VCCIO
voltage as the memory interface. You can share multiple memory interfaces with the
same OCT calibration block if the VCCIO voltage is the same.
Even though Cyclone III devices support OCT, this feature is not turned on by default
in the Altera IP solution.
© November 2009
Altera Corporation
Device and Pin Planning
Preliminary
2–28
Chapter 2: Pin and Resource Planning
Other FPGA Resources
Device and Pin Planning
© November 2009
Preliminary
Altera Corporation
Section II. Board Layout Guidelines
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About This Section
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Date
November 2009
© November 2009
Version
1.0
Changes Made
First published.
Altera Corporation
Board Layout Guidelines
Preliminary
viii
About This Section
Revision History
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
1. DDR2 SDRAM Interface Termination,
Drive Strength, Loading, and Board Layout
Guidelines
This chapter recommends the ideal termination schemes for the DDR2 SDRAM
interface with Arria® GX, Arria II GX, Cyclone® II, Cyclone III, Stratix® III, and Stratix
IV devices.
This chapter focuses on the following key factors that affect signal quality at the
receiver:
■
Proper use of termination
■
Output driver drive strength setting
■
Loading at the receiver
■
Layout guidelines
As memory interface performance increases, board designers must pay closer
attention to the quality of the signal seen at the receiver because poorly transmitted
signals can dramatically reduce the overall data-valid margin at the receiver.
Figure 1–1 shows the differences between an ideal and real signal seen by the receiver.
VIH
Voltage
Voltage
Figure 1–1. Ideal and Real Signal at the Receiver
VIH
VIL
VIL
Time
Time
Ideal
Real
In addition, this chapter compares various types of termination schemes, and their
effects on the signal quality on the receiver. It also discusses the proper drive strength
setting on the FPGA to optimize the signal integrity at the receiver, and the effects of
different loading types, such as components versus DIMM configuration, on signal
quality. Finally, this chapter provides DDR2 SDRAM layout guidelines.
The objective of this chapter to understand the trade-offs between different types of
termination schemes, the effects of output drive strengths, and different loading
types, so you can swiftly navigate through the multiple combinations and choose the
best possible settings for your designs.
Board Termination
In board-level design, you can use a variety of termination schemes. DDR2 adheres to
the JEDEC standard of governing Stub-Series Terminated Logic (SSTL), JESD8-15a,
which includes four different termination schemes.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–2
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Two commonly used termination schemes of SSTL are:
■
Single parallel terminated output load with or without series resistors (Class I, as
stated in JESD8-15a)
■
Double parallel terminated output load with or without series resistors (Class II,
as stated in JESD8-15a)
Depending on the type of signals you choose, you can use either termination scheme.
Also, depending on your design’s FPGA and SDRAM memory devices, you may
choose external or internal termination schemes.
With the ever-increasing requirements to reduce system cost and simplify printed
circuit board (PCB) layout design, you may choose not to have any parallel
termination on the transmission line, and use point-to-point connections between the
memory interface and the memory. In this case, you may take advantage of internal
termination schemes such as on-chip termination (OCT) on the FPGA side and on-die
termination (ODT) on the SDRAM side when it is offered on your chosen device.
External Parallel Termination
If you use external termination, you must study the locations of the termination
resistors to determine which topology works best for your design. Figure 1–2 and
Figure 1–3 illustrate the two most commonly used termination topologies: fly-by
topology and non-fly-by topology, respectively.
Figure 1–2. Fly-By Placement of a Parallel Resistor
VTT
RT = 50 Ω
Board Trace
FPGA Driver
Board Trace
DDR2 SDRAM
DIMM
(Receiver)
With fly-by topology (Figure 1–2), you place the parallel termination resistor after the
receiver. This termination placement resolves the undesirable unterminated stub
found in the non-fly-by topology. However, using this topology can be costly and
complicate routing. The Stratix II Memory Board 2 uses the fly-by topology for the
parallel terminating resistors placement. The Stratix II Memory Board 2 is a memory
test board available only within Altera for the purpose of testing and validating
Altera’s memory interface.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–3
Figure 1–3. Non-Fly-By Placement of a Parallel Resistor
VTT
RT = 50 Ω
DDR2 SDRAM
DIMM
(Receiver)
FPGA Driver
With non-fly-by topology (Figure 1–3), the parallel termination resistor is placed
between the driver and receiver (closest to the receiver). This termination placement is
easier for board layout, but results in a short stub, which causes an unterminated
transmission line between the terminating resistor and the receiver. The unterminated
transmission line results in ringing and reflection at the receiver.
If you do not use external termination, DDR2 offers ODT and Altera® FPGAs have
varying levels of OCT support. You should explore using ODT and OCT to decrease
the board power consumption and reduce the required board real estate.
On-Chip Termination
OCT technology is offered on Arria II GX, Cyclone III, Stratix III, and Stratix IV
devices. Table 1–1 summarizes the extent of OCT support for each device. This table
provides information about SSTL-18 standards because SSTL-18 is the supported
standard for DDR2 memory interface by Altera FPGAs.
On-chip series (Rs) termination is supported only on output and bidirectional buffers.
The value of Rs with calibration is calibrated against a 25- resistor for class II and
50- resistor for class I connected to RUP and RDN pins and adjusted to ± 1% of 25  or
50 . On-chip parallel (Rt) termination is supported only on inputs and bidirectional
buffers. The value of Rt is calibrated against 100  connected to the RUP and RDN pins.
Calibration occurs at the end of device configuration. Dynamic OCT is supported
only on bidirectional I/O buffers.
Table 1–1. On-Chip Termination Schemes
FPGA Device
Stratix III
and Stratix IV
Termination Scheme
On-Chip Series Termination without
Calibration
© November 2009
Cyclone III and
Cyclone IV GX
Arria II GX
SSTL-18
Column
I/O
Row
I/O
Column
I/O
Row
I/O
Column
I/O
Row
I/O
Class I
50
50
50
50
50
50
Class II
25
25
25
25
25
—
Altera Corporation
Board Layout Guidelines
Preliminary
1–4
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Table 1–1. On-Chip Termination Schemes
FPGA Device
Stratix III
and Stratix IV
Termination Scheme
On-Chip Series Termination with
Calibration
On-Chip Parallel Termination with
Calibration
Cyclone III and
Cyclone IV GX
Arria II GX
SSTL-18
Column
I/O
Row
I/O
Column
I/O
Row
I/O
Column
I/O
Row
I/O
Class I
50
50
50
50
—
—
Class II
25
25
25
25
—
—
Class I
and
Class II
50
50
—
—
—
—
Note to Table 1–1:
(1) Programmable Drive Strength
(2) Non-dynamic on-chip parallel termination is only supported for input pins.
The dynamic OCT scheme is only available in Stratix III and Stratix IV FPGAs. The
dynamic OCT scheme enables series termination (Rs) and parallel termination (Rt) to
be dynamically turned on and off during the data transfer.
The series and parallel terminations are turned on or off depending on the read and
write cycle of the interface. During the write cycle, the Rs is turned on and the Rt is
turned off to match the line impedance. During the read cycle, the Rs is turned off and
the Rt is turned on as the Stratix III FPGA implements the far-end termination of the
bus (Figure 1–4).
Figure 1–4. Dynamic OCT for Memory Interfaces
Write Cycle
Read Cycle
VTT
VTT
Z0 = 50 Ω
Z0 = 50 Ω
22 Ω
OE
Stratix III (TX)
VTT
22 Ω
OE
DDR2 DIMM
Stratix III (RX)
DDR2 DIMM
Simulation and Measurement Setup
To study the different types of termination schemes properly, the simulation and
measurement setups described in this chapter use two options:
■
Altera Stratix III FPGA interfacing with a 400-MHz DDR2 SDRAM unbuffered
DIMM
■
Altera Stratix II FPGA interfacing with a 267-MHz DDR2 SDRAM unbuffered
DIMM
1
The maximum achievable frequency in Straitx II DDR2 SDRAM is
333 MHz. The 267 MHz frequency is due to the device speed grade
mounted on the Stratix II Memory Board 2 board.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–5
The Stratix III FPGA is interfacing with a 400-MHz DDR2 SDRAM unbuffered DIMM.
This DDR2 memory interface is built on the Stratix III Host Development Kit Board
(Figure 1–5). This board is available for purchase at the Altera web site.
Figure 1–5. Stratix III Host Development Kit Board with DDR2 SDRAM DIMM Interface
The Altera Stratix II FPGA is interfacing with a 267-MHz DDR2 SDRAM unbuffered
DIMM. This DDR2 memory interface is built on the Stratix II Memory Board 2
(Figure 1–6). and is not available to customers. This board is used internally within
Altera for validation and testing of memory interfaces with Stratix II devices.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–6
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Figure 1–6. Stratix II Memory Board 2 with DDR2 SDRAM DIMM Interface
The DDR2 SDRAM DIMM on both Stratix III and Stratix II boards contains a 22-
external series termination resistor for each data line, so all of the measurements and
simulations must account for the effect of these series termination resistors.
To correlate the bench measurements performed on the Stratix III Host Development
Kit Board and the Stratix II Memory Board 2, the simulations are performed using
HyperLynx LineSim software with IBIS models from Altera and memory vendors.
Figure 1–7 and Figure 1–8 show the setup in HyperLynx used for the simulation for
Stratix III and Stratix II boards. The simulation files, Simulation Example are on the
Altera website.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–7
Figure 1–7. HyperLynx Setup for Stratix III Host Development Kit Board with DDR2 SDRAM DIMM Interface Simulation
U1.AP6
R5
1.7 ohms
Stratix III
sstl18c1_cio_r50
L1
TL5
TL17
TL4
R2
TL2
U2.C8
6.1 nH
55.0 ohms
534.449 ps
3.042 in
SIII pin to DIMM
53.0 ohms
45.000 ps
DIMM Socket
55.0 ohms
28.286 ps
0.161 in
DIMM to R22
22.0 ohms
50.7 ohms
134.227 ps
0.764 in
R22 to SDRAM
MT47H128M8HQ
DQ0
C7
2.4 pF
U2.C8
MT47H128M8HQ
DQ0
850 fF
TL22
R4
TL23
TL24
TL25
R7
50.7 ohms
134.227 ps
0.764 in
R22 to SDRAM
22.0 ohms
55.0 ohms
28.286 ps
0.161 in
DIMM to R22
53.0 ohms
45.000 ps
DIMM Socket
55.0 ohms
534.449 ps
3.042 in
SIII pin to DIMM
1.7 ohms
L3
U7.AP6
6.1 nH
Stratix III
3s_sstl18_cin_g50c
C15
850 fF
2.4 pF
Figure 1–8. HyperLynx Setup for Stratix II Memory Board 2 with DDR2 SDRAM DIMM Interface Simulation
Vpull Up = 0.900 V
56.0 ohms
RP(AO)
Vpull Up = 0.900 V
56.0 ohms
RP(AO)
MT47H32M8BP_5
DQ0
CELL:B0
CELL:A0
CELL:C0
50.7 ohms
61.492 ps
0.350 in
Stripline
50.7 ohms
24.245 ps
0.138 in
Stripline
CELL:D0
50.7 ohms
132.119 ps
0.752 in
Stripline
CELL:E0
2.0 pF
C(EO)
Vpull Dn=0.000 V
54.0 ohms
45.000 ps
DIMM2-DIMM2L
CELL:F0
50.7 ohms
60.437 ps
0.344 in
Stripline
Stratix II
2s_sstl18c_cio...
50.7 ohms
105.765 ps
0.602 in
Stripline
CELL:A1
CELL:B1
50.7 ohms
423.589 ps
2.411 in
Stripline
CELL:C1
CELL:D1
CELL:E1
CELL:F1
The trace length of DQ0 from DDR2 SDRAM memory interface in the FPGA to DQ0 at
DDR2 SDRAM DIMM is extracted for the simulation and is approximately 3 inches
long for both the Stratix III device on the Stratix III Development Kit Board and the
Stratix II device on the Stratix II Memory Board 2.
In Figure 1–7, resistance, inductance, and capacitance (RLC) values of the Stratix III
FPGA I/O package are extracted from Stratix3_rlc.xls document in the Altera Device
IBIS Models available on the Altera IBIS Models page at Altera’s web site. At the point
of measurements, 0.85 pF of capacitance was added to represent the scope cable.
f
The trace information for DDR2 SDRAM DIMM on the Stratix II Memory Board 2 can
be found in the PC4300 DDR2 SDRAM Unbuffered DIMM Design Specification.
f
The trace information for DDR2 SDRAM DIMM on the Stratix III Host Development
Kit Board can be found in the PC5300/6400 DDR2 SDRAM Unbuffered DIMM Design
Specification.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–8
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Recommended Termination Schemes
Table 1–2 provides the recommended termination schemes for major DDR2 memory
interface signals. Signals include data (DQ), data strobe (DQS/DQSn), data mask
(DM), clocks (mem_clk/mem_clk_n), and address and command signals.
When interfacing with multiple DDR2 SDRAM components where the address,
command, and memory clock pins are connected to more than one load, follow these
steps:
1. Simulate the system to get the new slew-rate for these signals.
2. Use the derated tIS and tIH specifications from the DDR2 SDRAM datasheet based
on the simulation results.
3. If timing deration causes your interface to fail timing requirements, consider
signal duplication of these signals to lower their loading, and hence improve
timing.
1
Altera uses Class I and Class II termination in this table to refer to drive strength, and
not physical termination.
1
You must simulate your design for your system to ensure correct functionality.
Table 1–2. Termination Recommendations (Part 1 of 2) (Note 1)
Device Family
SSTL 18 IO Standard
(2), (3), (4), (5), (6)
FPGA End Discrete
Termination
Memory End
Termination 1
Rank/DIMM
Class I 12 mA
50  Parallel to VTT
discrete
ODT75 (8)
Class I R50 NO CAL
N/A
Class I MAX
N/A
Clock
Class I 12 mA
N/A
DQ/DQS
Class I 12 mA
50  Parallel to VTT
discrete
DM
Class I12 mA
N/A
Address and
command
Class I MAX
N/A
56  parallelto V TT
discrete
N/A
Class I 12 mA
N/A
N/A = on DIMM
N/A
Signal Type
Memory
I/O
Standard
Cyclone III and Cyclone IV GX
DQ/DQS
DM
DDR2 component
DDR2 DIMM
Address and
command
Clock
HALF (7)
N/A
N/A
N/A
×1 = 100  differential (10)
×2 = 200  differential (11)
ODT75 (8)
N/A
FULL (9)
N/A
Stratix III and Stratix IV
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–9
Table 1–2. Termination Recommendations (Part 2 of 2) (Note 1)
Device Family
Signal Type
DQ/DQS
SSTL 18 IO Standard
(2), (3), (4), (5), (6)
FPGA End Discrete
Termination
Memory End
Termination 1
Rank/DIMM
Memory
I/O
Standard
Class I R50/P50 DYN CAL
N/A
ODT75 (8)
HALF (7)
Class I R50 CAL
N/A
ODT75 (8)
N/A
Class I R50 CAL
N/A
56  Parallel to VTT
discrete
N/A
DIFF Class I R50 NO CAL
N/A
x1 = 100  differential (10)
N/A
DIFF Class I R50 NO CAL
N/A
X2 = 200  differential
(11)
N/A
DIFF Class I R50/P50 DYN
CAL
N/A
ODT75 (8)
HALF (7)
DM
Address and
command
DDR2 component
Clock
DQS DIFF
recommended
DQS SE
Class I R50/P50 DYN CAL
N/A
ODT75 (8)
HALF (7)
DQ/DQS
Class I R50/P50 DYN CAL
N/A
ODT75 (8)
FULL (9)
Class I R50 CAL
N/A
ODT75 (8)
N/A
Class I MAX
N/A
56  Parallel to VTT
discrete
N/A
Clock
DIFF Class I R50 NO CAL
N/A
N/A = on DIMM
N/A
DQS DIFF
recommended
DIFF Class I R50/P50 DYN
CAL
N/A
ODT75 (8)
FULL (9)
DQS SE
Class I R50/P50 DYN CAL
N/A
ODT75 (8)
FULL (9)
DM
Address and
command
DDR2 DIMM
Notes to Table 1–2:
(1) N/A is not available.
(2) R is series resistor.
(3) P is parallel resistor.
(4) DYN is dynamic OCT.
(5) NO CAL is OCT without calibration.
(6) CAL is OCT with calibration.
(7) HALF is reduced drive strength.
(8) ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
(9) FULL is full drive strength.
(10) x1 is a single-device load.
(11) x2 is two-device load.
Dynamic On-Chip Termination
The termination schemes are described in JEDEC standard JESD8-15a for
SSTL 18 I/O. Dynamic OCT is available in Stratix III and Stratix IV. When the
Stratix III FPGA (driver) is writing to the DDR2 SDRAM DIMM (receiver), series OCT
is enabled dynamically to match the impedance of the transmission line. As a result,
reflections are significantly reduced. Similarly, when the FPGA is reading from the
DDR2 SDRAM DIMM, the parallel OCT is dynamically enabled.
f
© November 2009
For information about setting the proper value for termination resistors, refer to the
Stratix III Device I/O Features chapter in the Stratix III Device Handbook and the I/O
Features in Stratix IV Devices chapter in the Stratix IV Device Handbook..
Altera Corporation
Board Layout Guidelines
Preliminary
1–10
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
FPGA Writing to Memory
Figure 1–9 shows dynamic series OCT scheme when the FPGA is writing to the
memory. The benefit of using dynamic series OCT is that when driver is driving the
transmission line, it “sees” a matched transmission line with no external resistor
termination.
Figure 1–9. Dynamic Series OCT Scheme with ODT on the Memory
FPGA
DDR2 DIMM
DDR2 Component
50 Ω
Driver
100 Ω
50 Ω
RS = 22 Ω
150 Ω
3” Trace Length
Receiver
100 Ω
Driver
Receiver
150 Ω
Figure 2 and Figure 1–10 show the simulation and measurement results of a write to
the DDR2 SDRAM DIMM. The system uses Class I termination with a 50- series
OCT measured at the DIMM with a full drive strength and a 75  ODT at the DIMM.
Both simulation and bench measurements are in 200 pS/div and 200 mV/div.
Figure 2. HyperLynx Simulation FPGA Writing to Memory
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–11
Figure 1–10. Board Measurement, FPGA Writing to Memory
Table 1–3 summarizes the comparison between the simulation and the board
measurement of the signal seen at the DDR2 SDRAM DIMM.
Table 1–3. Signal Comparison When the FPGA is Writing to the Memory (Note 1)
Eye Width (ns) (2)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.194
0.740
N/A
N/A
Board Measurement
1.08
0.7
N/A
N/A
Notes to Table 1–3:
(1) N/A is not applicable.
(2) The eye width is measured from VIH/VIL(ac) = VREF ±250 mV to VIH/VIL(dc) = VREF ±125 mV, where VIH and VI L
are determined per the JEDEC specification for SSTL-18.
The data in Table 1–3 and Figure 2 and Figure 1–10 suggest that when the FPGA is
writing to the memory, the bench measurements are closely matched with simulation
measurements. They indicate that using the series dynamic on-chip termination
scheme for your bidirectional I/Os maintains the integrity of the signal, while it
removes the need for external termination.
Depending on the I/O standard, you should consider the four parameters listed in
Table 1–3 when designing a memory interface. Although the simulation and board
measurement appear to be similar, there are some discrepancies when the key
parameters are measured. Although simulation does not fully model the duty cycle
distortion of the I/O, crosstalk, or board power plane degradation, it provides a good
indication on the performance of the board.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–12
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
For memory interfaces, the eye width is important when determining if there is a
sufficient window to correctly capture the data. Regarding the eye height, even
though most memory interfaces use voltage-referenced I/O standards (in this case,
SSTL-18), as long as there is sufficient eye opening below and above VIL and VIH,
there should be enough margin to correctly capture the data. However, because effects
such as crosstalk are not taken into account, it is critical to design a system to achieve
the optimum eye height, because it impacts the overall margin of a system with a
memory interface.
f
Refer to the memory vendors when determining the over- and undershoot. They
typically specify a maximum limit on the input voltage to prevent reliability issues.
FPGA Reading from Memory
Figure 1–11 shows the dynamic parallel termination scheme when the FPGA is
reading from memory. When the DDR2 SDRAM DIMM is driving the transmission
line, the ringing and reflection is minimal because the FPGA-side termination 50-
pull-up resistor is matched with the transmission line. Figure 1–12 shows the
simulation and measurement results of a read from DDR2 SDRAM DIMM. The
system uses Class I termination with a 50- calibrated parallel OCT measured at the
FPGA end with a full drive strength and a 75- ODT at the memory. Both simulation
and bench measurements are in 200 pS/div and 200 mV/div.
Figure 1–11. Dynamic Parallel OCT Scheme with Memory-Side Series Resistor
FPGA
DDR2 DIMM Full Strength
DDR2 Component
Driver
100 Ω
50 Ω
Receiver
3” Trace Length
Driver
RS = 22 Ω
Receiver
100 Ω
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–13
Figure 1–12. Hyperlynx Simulation and Board Measurement, FPGA Reading from Memory
Table 1–4 summarizes the comparison between the simulation and the board
measurement of the signal seen at the FPGA end.
Table 1–4. Signal Comparison When the FPGA is Reading from the Memory (Note 1), (2)
Eye Width (ns) (3)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.206
0.740
N/A
N/A
Board Measurement
1.140
0.680
N/A
N/A
Notes to Table 1–4:
(1) The drive strength on the memory DIMM is set to Full.
(2) N/A is not applicable.
(3) The eye width is measured from VIH/VIL(ac) = VREF ±250 mV to VIH/VIL(dc) = VREF ±125 mV, in which VIH and VIL
are determined per the JEDEC specification for SSTL-18.
The data in Table 1–4 and Figure 1–12 suggest that bench measurements are closely
matched with simulation measurements when the FPGA is reading from the memory.
They indicate that using the parallel dynamic on-chip termination scheme in
bidirectional I/Os maintains the integrity of the signal, while it removes the need for
external termination.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–14
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
On-Chip Termination (Non-Dynamic)
When you use the 50- OCT feature in a Class I termination scheme using ODT with
a memory-side series resistor, the output driver is tuned to 50, which matches the
characteristic impedance of the transmission line. Figure 1–13 shows the Class I
termination scheme using ODT when the 50- OCT on the FPGA is turned on.
Figure 1–13. Class I Termination Using ODT with 50- OCT
FPGA
DDR2 DIMM
DDR2 Component
50 Ω
Driver
3” Trace Length
Receiver
VREF
Driver
RS = 22 Ω
50 Ω
VREF = -0.9 V
Receiver
The resulting signal quality has a similar eye opening to the 8 mA drive strength
setting (refer to “Drive Strength” on page 1–31) without any over- or undershoot.
Figure 1–14 shows the simulation and measurement of the signal at the memory side
(DDR2 SDRAM DIMM) with the drive strength setting of 50- OCT in the FPGA.
Figure 1–14. HyperLynx Simulation and Measurement, FPGA Writing to Memory
Table 1–5 shows data for the signal at the DDR2 SDRAM DIMM of a Class I scheme
termination using ODT with a memory-side series resistor. The FPGA is writing to the
memory with 50- OCT.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–15
Table 1–5. Simulation and Board Measurement Results for 50-OCT and8-mA Drive Strength
Settings (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
50- OCT Drive Strength Setting
Simulation
1.68
0.82
N/A
N/A
Board Measurement
1.30
0.70
N/A
N/A
Note to Table 1–5:
(1) N/A is not applicable.
When you use the 50- OCT setting on the FPGA, the signal quality for the Class I
termination using ODT with a memory-side series resistor is further improved with
lower over- and undershoot.
In addition to the 50- OCT setting, Stratix II devices have a 25- OCT setting that
you can use to improve the signal quality in a Class II terminated transmission line.
Figure 1–15 shows the Class II termination scheme using ODT when the 25- OCT on
the FPGA is turned on.
Figure 1–15. Class II Termination Using ODT with 25- OCT
VTT = -0.9 V
FPGA
DDR2 DIMM
RT = 56 Ω
25 Ω
DDR2 Component
Driver
50 Ω
3” Trace Length
Receiver
VREF
RS = 22 Ω
VREF = 0.9 V
Driver
Receiver
Figure 1–16 shows the simulation and measurement of the signal at the DDR2
SDRAM DIMM (receiver) with a drive strength setting of 25- OCT in the FPGA.
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Figure 1–16. HyperLynx Simulation and Measurement, FPGA Writing to Memory
Table 1–6 shows the data for the signal at the DDR2 SDRAM DIMM of a Class II
termination with a memory-side series resistor. The FPGA is writing to the memory
with 25- OCT.
Table 1–6. Simulation and Board Measurement Results for 25-OCT and16-mA Drive Strength
Settings (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
25- OCT Drive Strength Setting
Simulation
1.70
0.81
N/A
N/A
Board Measurement
1.47
0.51
N/A
N/A
Note to Table 1–6:
(1) N/A is not applicable.
This type of termination scheme is only used for bidirectional signals, such as data
(DQ), data strobe (DQS), data mask (DM), and memory clocks (CK) found in DRAMs.
Class II External Parallel Termination
The double parallel (Class II) termination scheme is described in JEDEC standards
JESD8-6 for HSTL I/O, JESD8-9b for SSTL-2 I/O, and JESD8-15a for SSTL-18 I/O.
When the FPGA (driver) is writing to the DDR2 SDRAM DIMM (receiver), the
transmission line is terminated at the DDR2 SDRAM DIMM. Similarly, when the
FPGA is reading from the DDR2 SDRAM DIMM, the DDR2 SDRAM DIMM is now
the driver and the transmission line is terminated at the FPGA (receiver). This type of
termination scheme is typically used for bidirectional signals, such as data (DQ) and
data strobe (DQS) signal found in DRAMs.
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Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–17
FPGA Writing to Memory
Figure 1–17 shows the Class II termination scheme when the FPGA is writing to the
memory. The benefit of using Class II termination is that when either driver is driving
the transmission line, it sees a matched transmission line because of the termination
resistor at the receiver-end, thereby reducing ringing and reflection.
Figure 1–17. Class-II Termination Scheme with Memory-Side Series Resistor
VTT = 0.9 V
VTT = 0.9 V
FPGA
DDR2 DIMM
RT = 50 Ω
RT = 50 Ω
DDR2 Component
16 mA
Driver
Receiver
RS = 22 Ω
50 Ω
VREF
3” Trace Length
VREF = 0.9 V
Driver
Receiver
Figure 1–18 and Figure 1–19 show the simulation and measurement result of a write
to the DDR2 SDRAM DIMM. The system uses Class II termination with a
source-series resistor measured at the DIMM with a drive strength setting of 16 mA.
Figure 1–18. HyperLynx Simulation, FPGA Writing to Memory
The simulation shows a clean signal with a good eye opening, but there is slight overand undershoot of the 1.8-V signal specified by DDR2 SDRAM. The over- and
undershoot can be attributed to either overdriving the transmission line using a
higher than required drive strength setting on the driver or the over-termination on
the receiver side by using an external resistor value that is higher than the
characteristic impedance of the transmission line. As long as the over- and undershoot
do not exceed the absolute maximum rating specification listed in the memory
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Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
vendor’s DDR2 SDRAM data sheet, it does not result in any reliability issues. The
simulation results are then correlated with actual board level measurements.
Figure 1–19 shows the measurement obtained from the Stratix II Memory Board 2.
The FPGA is using a 16 mA drive strength to drive the DDR2 SDRAM DIMM on a
Class II termination transmission line.
Figure 1–19. Board Measurement, FPGA Writing to Memory
Table 1–7 summarizes the comparison between the simulation and the board
measurement of the signal seen at the DDR2 SDRAM DIMM.
Table 1–7. Signal Comparison When the FPGA is Writing to the Memory (Note 1)
Eye Width (ns) (2)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.65
1.28
0.16
0.14
Board Measurement
1.35
0.83
0.16
0.18
Notes to Table 1–7:
(1) The drive strength on the FPGA is set to 16 mA.
(2) The eye width is measured from VREF ± 125 mV where VIH and VIL are determined per the JEDEC specification for
SSTL-18.
A closer inspection of the simulation shows an ideal duty cycle of 50%–50%, while the
board measurement shows that the duty cycle is non-ideal, around 53%–47%,
resulting in the difference between the simulation and measured eye width. In
addition, the board measurement is conducted on a 72-bit memory interface, but the
simulation is performed on a single I/O.
FPGA Reading from Memory
Figure 1–20 shows the Class II termination scheme when the FPGA is reading from
memory. When the DDR2 SDRAM DIMM is driving the transmission line, the ringing
and reflection is minimal because of the matched FPGA-side termination pull-up
resistor with the transmission line.
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Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
1–19
Figure 1–20. Class II Termination Scheme with Memory-Side Series Resistor
VTT = 0.9 V
VTT = 0.9 V
FPGA
DDR2 DIMM Full Strength
RT = 56 Ω
Driver
Receiver
RT = 56 Ω
RS = 22 Ω
50 Ω
VREF = 0.9 V
3” Trace Length
VREF
Driver
Receiver
Figure 1–21 and Figure 1–22 show the simulation and measurement, respectively, of
the signal at the FPGA side with the full drive strength setting on the DDR2 SDRAM
DIMM. The simulation uses a Class II termination scheme with a source-series
resistor transmission line. The FPGA is reading from the memory with a full drive
strength setting on the DIMM.
Figure 1–21. HyperLynx Simulation, FPGA Reading from Memory
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Figure 1–22. Board Measurement, FPGA Reading from Memory
Table 1–8 summarizes the comparison between the simulation and board
measurements of the signal seen by the FPGA when the FPGA is reading from
memory (driver).
Table 1–8. Signal Comparison, FPGA is Reading from Memory (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.73
0.76
N/A
N/A
Board Measurement
1.28
0.43
N/A
N/A
Note to Table 1–8:
(1) The drive strength on the DDR2 SDRAM DIMM is set to full strength.
(2) N/A is not applicable.
Both simulation and measurement show a clean signal and a good eye opening
without any over- and undershoot. However, the eye height when the FPGA is
reading from the memory is smaller compared to the eye height when the FPGA is
writing to the memory. The reduction in eye height is attributed to the voltage drop
on the series resistor present on the DIMM. With the drive strength setting on the
memory already set to full, you cannot increase the memory drive strength to
improve the eye height. One option is to remove the series resistor on the DIMM
when the FPGA is reading from memory (refer to the section “Component Versus
DIMM” on page 1–33). Another option is to remove the external parallel resistor near
the memory so that the memory driver sees less loading. For a DIMM configuration,
the latter option is a better choice because the series resistors are part of the DIMM
and you can easily turn on the ODT feature to use as the termination resistor when the
FPGA is writing to the memory and turn off when the FPGA is reading from memory.
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Board Termination
1–21
The results for the Class II termination scheme demonstrate that the scheme is ideal
for bidirectional signals such as data strobe and data for DDR2 SDRAM memory.
Terminations at the receiver eliminate reflections back to the driver and suppress any
ringing at the receiver.
Class I External Parallel Termination
The single parallel (Class I) termination scheme refers to when the termination is
located near the receiver side. Typically, this scheme is used for terminating
unidirectional signals (such as clocks, address, and command signals) for DDR2
SDRAM.
However, because of board constraints, this form of termination scheme is sometimes
used in bidirectional signals, such as data (DQ) and data strobe (DQS) signals. For
bidirectional signals, you can place the termination on either the memory or the FPGA
side. This section focuses only on the Class I termination scheme with memory-side
termination. The memory-side termination ensures impedance matching when the
signal reaches the receiver of the memory. However, when the FPGA is reading from
the memory, there is no termination on the FPGA side, resulting in impedance
mismatch. This section describes the signal quality of this termination scheme.
FPGA Writing to Memory
When the FPGA is writing to the memory (Figure 1–23), the transmission line is
parallel-terminated at the memory side, resulting in minimal reflection on the receiver
side because of the matched impedance seen by the transmission line. The benefit of
this termination scheme is that only one external resistor is required. Alternatively,
you can implement this termination scheme using an ODT resistor instead of an
external resistor.
Refer to the section “Class I Termination Using ODT” on page 1–24 for more
information about how an ODT resistor compares to an external termination resistor.
Figure 1–23. Class I Termination Scheme with Memory-Side Series Resistor
VTT = 0.9 V
FPGA
DDR2 DIMM
RT = 56 Ω
Driver
Receiver
RS = 22 Ω
50 Ω
VREF
3” Trace Length
DDR2 Component
VREF = 0.9 V
Driver
Receiver
Figure 1–24 shows the simulation and measurement of the signal at the memory
(DDR2 SDRAM DIMM) of Class I termination with a memory-side resistor. The FPGA
writes to the memory with a 16 mA drive strength setting.
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Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Figure 1–24. HyperLynx Simulation and Board Measurement, FPGA Writing to Memory
Table 1–9 summarizes the comparison of the signal at the DDR2 SDRAM DIMM of a
Class I and Class II termination scheme using external resistors with memory-side
series resistors. The FPGA (driver) writes to the memory (receiver).
Table 1–9. Signal Comparison When the FPGA is Writing to Memory (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Class I Termination Scheme With External Parallel Resistor
Simulation
1.69
1.51
0.34
0.29
Board Measurement
1.25
1.08
0.41
0.34
Class II Termination Scheme With External Parallel Resistor
Simulation
1.65
1.28
0.16
0.14
Board Measurement
1.35
0.83
0.16
0.18
Note to Table 1–9:
(1) The drive strength on the FPGA is set to 16 mA.
Table 1–9 shows the overall signal quality of a Class I termination scheme is
comparable to the signal quality of a Class II termination scheme, except that the eye
height of the Class I termination scheme is approximately 30% larger. The increase in
eye height is due to the reduced loading “seen” by the driver, because the Class I
termination scheme does not have an FPGA-side parallel termination resistor.
However, increased eye height comes with a price: a 50% increase in the over- and
undershoot of the signal using Class I versus Class II termination scheme. You can
decrease the FPGA drive strength to compensate for the decreased loading seen by
the driver to decrease the over- and undershoot.
Refer to the section “Drive Strength” on page 1–31 for more information about how
drive strength affects the signal quality.
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Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Board Termination
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FPGA Reading from Memory
As described in the section “FPGA Writing to Memory” on page 1–21, in Class I
termination, the termination is located near the receiver. However, if you use this
termination scheme to terminate a bidirectional signal, the receiver can also be the
driver. For example, in DDR2 SDRAM, the data signals are both receiver and driver.
Figure 1–25 shows a Class I termination scheme with a memory-side resistor. The
FPGA reads from the memory.
Figure 1–25. Class I Termination Scheme with Memory-Side Series Resistor
VTT = 0.9 V
FPGA
DDR2 DIMM Full Strength
RT = 56 Ω
Driver
Receiver
DDR2 Component
RS = 22 Ω
50 Ω
VREF = 0.9 V
3” Trace Length
VREF
Driver
Receiver
When the FPGA reads from the memory (Figure 1–25), the transmission line is not
terminated at the FPGA, resulting in an impedance mismatch, which then results in
over- and undershoot. Figure 1–26 shows the simulation and measurement of the
signal at the FPGA side (receiver) of a Class I termination. The FPGA reads from the
memory with a full drive strength setting on the DDR2 SDRAM DIMM.
Figure 1–26. HyperLynx Simulation and Board Measurement, FPGA Reading from Memory
Table 1–10 summarizes the comparison of the signal “seen” at the FPGA of a Class I
and Class II termination scheme using an external resistor with a memory-side series
resistor. The FPGA (receiver) reads from the memory (driver).
© November 2009
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Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Table 1–10. Signal Comparison When the FPGA is Reading From Memory (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Class I Termination Scheme with External Parallel Resistor
Simulation
1.73
0.74
0.20
0.18
Board Measurement
1.24
0.58
0.09
0.14
Class II Termination Scheme with External Parallel Resistor
Simulation
1.73
0.76
N/A
N/A
Board Measurement
1.28
0.43
N/A
N/A
Note to Table 1–10:
(1) The drive strength on the DDR2 SDRAM DIMM is set to full strength.
(2) N/A is not applicable.
When the FPGA reads from the memory using the Class I scheme, the signal quality is
comparable to that of the Class II scheme, in terms of the eye height and width.
Table 1–10 shows the lack of termination at the receiver (FPGA) results in impedance
mismatch, causing reflection and ringing that is not visible in the Class II termination
scheme. As such, Altera recommends using the Class I termination scheme for
unidirectional signals (such as command and address signals), between the FPGA and
the memory.
Class I Termination Using ODT
Presently, ODT is becoming a common feature in memory, including SDRAMs,
graphics DRAMs, and SRAMs. ODT helps reduce board termination cost and
simplify board routing. This section describes the ODT feature of DDR2 SDRAM and
the signal quality when the ODT feature is used.
FPGA Writing to Memory
DDR2 SDRAM has built-in ODT that eliminates the need for external termination
resistors. To use the ODT feature of the memory, you must configure the memory to
turn on the ODT feature during memory initialization. For DDR2 SDRAM, set the
ODT feature by programming the extended mode register. In addition to
programming the extended mode register during initialization of the DDR2 SDRAM,
an ODT input pin on the DDR2 SDRAM must be driven high to activate the ODT.
f
Refer to the respective memory data sheet for additional information about setting the
ODT feature and the timing requirements for driving the ODT pin in DDR2 SDRAM.
The ODT feature in DDR2 SDRAM is controlled dynamically—it is turned on while
the FPGA is writing to the memory and turned off while the FPGA is reading from the
memory. The ODT feature in DDR2 SDRAM has three settings: 50, 75, and 150.
If there are no external parallel termination resistors and the ODT feature is turned on,
the termination scheme resembles the Class I termination described in “Class I
External Parallel Termination” on page 1–21.
Figure 1–27 shows the termination scheme when the ODT on the DDR2 SDRAM is
turned on.
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Board Termination
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Figure 1–27. Class I Termination Scheme Using ODT
FPGA
DDR2 DIMM
DDR2 Component
16 mA
Driver
Receiver
VREF
Driver
RS = 22 Ω
50 Ω
3” Trace Length
VREF = 0.9 V
Receiver
Figure 1–28 shows the simulation and measurement of the signal visible at the
memory (receiver) using 50  ODT with a memory-side series resistor transmission
line. The FPGA writes to the memory with a 16 mA drive strength setting.
Figure 1–28. Simulation and Board Measurement, FPGA Writing to Memory
Table 1–11 summarizes the comparisons of the signal seen the DDR2 SDRAM DIMM
of a Class I termination scheme using an external resistor and a Class I termination
scheme using ODT with a memory-side series resistor. The FPGA (driver) writes to
the memory (receiver).
Table 1–11. Signal Comparison When the FPGA is Writing to Memory (Part 1 of 2) (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Class I Termination Scheme with ODT
Simulation
1.63
0.84
N/A
0.12
Board Measurement
1.51
0.76
0.05
0.15
Class I Termination Scheme with External Parallel Resistor
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Table 1–11. Signal Comparison When the FPGA is Writing to Memory (Part 2 of 2) (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.69
1.51
0.34
0.29
Board Measurement
1.25
1.08
0.41
0.34
Note to Table 1–11:
(1) The drive strength on the FPGA is set to 16 mA.
(2) N/A is not applicable.
When the ODT feature is enabled in the DDR2 SDRAM, the eye width is improved.
There is some degradation to the eye height, but it is not significant. When ODT is
enabled, the most significant improvement in signal quality is the reduction of the
over- and undershoot, which helps mitigate any potential reliability issues on the
memory devices.
Using memory ODT also eliminates the need for external resistors, which reduces
board cost and simplifies board routing, allowing you to shrink your boards.
Therefore, Altera recommends using the ODT feature on the DDR2 SDRAM memory.
FPGA Reading from Memory
Altera’s Stratix II series, Arria GX and Cyclone series of devices are not equipped with
ODT. When the DDR2 SDRAM ODT feature is turned off when the FPGA is reading
from the memory, the termination scheme resembles the no-parallel termination
scheme illustrated by Figure 1–31 on page 1–28.
No-Parallel Termination
The no-parallel termination scheme is described in the JEDEC standards JESD8-6 for
HSTL I/O, JESD8-9b for SSTL-2 I/O, and JESD8-15a for SSTL-18 I/O. Designers who
attempt series-only termination schemes such as this often do so to eliminate the need
for a VTT power supply.
This is typically not recommended for any signals between an FPGA and DDR2
interface; however, information about this topic is included here as a reference point
to clarify the challenges that may occur if you attempt to avoid parallel termination
entirely.
FPGA Writing to Memory
Figure 1–29 shows a no-parallel termination transmission line of the FPGA driving
the memory. When the FPGA is driving the transmission line, the signals at the
memory-side (DDR2 SDRAM DIMM) may suffer from signal degradation (for
example, degradation in rise and fall time). This is due to impedance mismatch,
because there is no parallel termination at the memory-side. Also, because of factors
such as trace length and drive strength, the degradation seen at the receiver-end
might be sufficient to result in a system failure. To understand the effects of each
termination scheme on a system, perform system-level simulations before and after
the board is designed.
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Board Termination
1–27
Figure 1–29. No-Parallel Termination Scheme
FPGA
DDR2 DIMM
DDR2 Component
Driver
Receiver
RS = 22 Ω
50 Ω
VREF
3” Trace Length
VREF = 0.9 V
Driver
Receiver
Figure 1–30 shows a HyperLynx simulation and measurement of the FPGA writing to
the memory at 533 MHz with a no-parallel termination scheme using a 16 mA drive
strength option. The measurement point is on the DDR2 SDRAM DIMM.
Figure 1–30. HyperLynx Simulation and Board Measurement, FPGA Writing to Memory
The simulated and measured signal shows that there is sufficient eye opening but also
significant over- and undershoot of the 1.8-V signal specified by the DDR2 SDRAM.
From the simulation and measurement, the overshoot is approximately 1 V higher
than 1.8 V, and undershoot is approximately 0.8 V below ground. This over- and
undershoot might result in a reliability issue, because it has exceeded the absolute
maximum rating specification listed in the memory vendors’ DDR2 SDRAM data
sheet.
Table 1–12 summarizes the comparison of the signal visible at the DDR2 SDRAM
DIMM of a no-parallel and a Class II termination scheme when the FPGA writes to
the DDR2 SDRAM DIMM.
Table 1–12. Signal Comparison When the FPGA is Writing to Memory (Part 1 of 2) (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
1.10
0.90
0.80
No-Parallel Termination Scheme
Simulation
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Table 1–12. Signal Comparison When the FPGA is Writing to Memory (Part 2 of 2) (Note 1)
Board Measurement
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
1.25
0.60
1.10
1.08
Class II Termination Scheme With External Parallel Resistor
Simulation
1.65
1.28
0.16
0.14
Board Measurement
1.35
0.83
0.16
0.18
Note to Table 1–12:
(1) The drive strength on the FPGA is set to Class II 16 mA.
Although the appearance of the signal in a no-parallel termination scheme is not
clean, when you take the key parameters into consideration, the eye width and height
is comparable to that of a Class II termination scheme. The major disadvantage of
using a no-parallel termination scheme is the over- and undershoot. There is no
termination on the receiver, so there is an impedance mismatch when the signal
arrives at the receiver, resulting in ringing and reflection. In addition, the 16-mA drive
strength setting on the FPGA also results in overdriving the transmission line, causing
the over- and undershoot. By reducing the drive strength setting, the over- and
undershoot decreases and improves the signal quality “seen” by the receiver.
For more information about how drive strength affects the signal quality, refer to
“Drive Strength” on page 1–31.
FPGA Reading from Memory
In a no-parallel termination scheme (Figure 1–31), when the memory is driving the
transmission line, the resistor, Rs acts as a source termination resistor. The DDR2
SDRAM driver has two drive strength settings:
■
Full strength, in which the output impedance is approximately 18
■
Reduced strength, in which the output impedance is approximately 40
When the DDR2 SDRAM DIMM drives the transmission line, the combination of the
22- source-series resistor and the driver impedance should match that of the
characteristic impedance of the transmission line. As such, there is less over- and
undershoot of the signal visible at the receiver (FPGA).
Figure 1–31. No-Parallel Termination Scheme, FPGA Reading from Memory
FPGA
DDR2 DIMM Full Strength
DDR2 Component
Driver
Receiver
50 Ω
VREF = 0.9 V
3” Trace Length
RS = 22 Ω
VREFF
Driver
Receiver
Figure 1–32 shows the simulation and measurement of the signal visible at the FPGA
(receiver) when the memory is driving the no-parallel termination transmission line
with a memory-side series resistor.
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Board Termination
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Figure 1–32. HyperLynx Simulation and Board Measurement, FPGA Reading from Memory
Table 1–13 summarizes the comparison of the signal seen on the FPGA with a
no-parallel and a Class II termination scheme when the FPGA is reading from
memory.
Table 1–13. Signal Comparison, FPGA Reading From Memory (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
No-Parallel Termination Scheme
Simulation
1.82
1.57
0.51
0.51
Board Measurement
1.62
1.29
0.28
0.37
Class II Termination Scheme with External Parallel Resistor
Simulation
1.73
0.76
N/A
N/A
Board Measurement
1.28
0.43
N/A
N/A
Note to Table 1–13:
(1) The drive strength on the DDR2 SDRAM DIMM is set to full strength.
(2) N/A is not applicable.
As in the section “FPGA Writing to Memory” on page 1–26, the eye width and height
of the signal in a no-parallel termination scheme is comparable to a Class II
termination scheme, but the disadvantage is the over- and undershoot. There is overand undershoot because of the lack of termination on the transmission line, but the
magnitude of the over- and undershoot is not as severe when compared to that
described in “FPGA Writing to Memory” on page 1–26. This is attributed to the
presence of the series resistor at the source (memory side), which dampens any
reflection coming back to the driver and further reduces the effect of the reflection on
the FPGA side.
When the memory-side series resistor is removed (Figure 1–33), the memory driver
impedance no longer matches the transmission line and there is no series resistor at
the driver to dampen the reflection coming back from the unterminated FPGA side.
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Figure 1–33. No-Parallel Termination Scheme, FPGA REading from Memory
FPGA
DDR2 Component Full Strength
Driver
Receiver
Driver
50 Ω
VREF = 0.9 V
3” Trace Length
VREF
Receiver
Figure 1–34 shows the simulation and measurement of the signal at the FPGA side in
a no-parallel termination scheme with the full drive strength setting on the memory.
Figure 1–34. HyperLynx Simulation and Measurement, FPGA Reading from Memory
Table 1–14 summarizes the difference between no-parallel termination with and
without memory-side series resistor when the memory (driver) writes to the FPGA
(receiver).
Table 1–14. No-Parallel Termination with and without Memory-Side Series Resistor (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Simulation
1.81
0.85
1.11
0.77
Board Measurement
1.51
0.92
0.96
0.99
Simulation
1.82
1.57
0.51
0.51
Board Measurement
1.62
1.29
0.28
0.37
Without Series Resistor
With Series Resistor
Note to Table 1–14:
(1) The drive strength on the memory is set to full drive strength.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Drive Strength
1–31
Table 1–14 highlights the effect of the series resistor on the memory side with the
dramatic increase in over- and undershoot and the decrease in the eye height. This
result is similar to that described in “FPGA Writing to Memory” on page 1–26. In that
simulation, there is a series resistor but it is located at the receiver side (memory-side),
so it does not have the desired effect of reducing the drive strength of the driver and
suppressing the reflection coming back from the unterminated receiver-end. As such,
in a system without receiver-side termination, the series resistor on the driver helps
reduce the drive strength of the driver and dampen the reflection coming back from
the unterminated receiver-end.
Summary
This section compared the various types of termination schemes and studied the
benefits and disadvantages of each scheme.
For bidirectional signals, such as the DQ and DQS signals of DDR2 SDRAM, dynamic
OCT should be regarded as the ideal termination method when the feature is
available; otherwise, a Class II termination scheme with fly-by topology should be
regarded as the ideal termination method.
For unidirectional signals, such as the command and address signals of DDR and
DDR2 SDRAM, a memory-side Class I termination scheme with fly-by topology
provides the best results.
If board real estate and cost is prohibitive to placing on-board termination resistors,
you can use the ODT feature on the DDR2 SDRAM memory for the memory-side
Class II termination when the controller drives the transmission line. If a Stratix III
series device is used, dynamic OCT can achieve a termination solution comparable to
a fully discrete terminated system.
Drive Strength
Altera’s FPGA products offer numerous drive strength settings, allowing you to
optimize your board designs to achieve the best signal quality. This section focuses on
the most commonly used drive strength settings of 8 mA and 16 mA, as
recommended by JEDEC for Class I and Class II termination schemes.
1
You are not restricted to using only these drive strength settings for your board
designs. You should perform simulations using I/O models available from Altera and
memory vendors to ensure that you use the proper drive strength setting to achieve
optimum signal integrity.
How Strong is Strong Enough?
Figure 1–19 on page 1–18 shows a signal probed at the DDR2 SDRAM DIMM
(receiver) of a far-end series-terminated transmission line when the FPGA writes to
the DDR2 SDRAM DIMM using a drive strength setting of 16 mA. The resulting
signal quality on the receiver shows excessive over- and undershoot. To reduce the
over- and undershoot, you can reduce the drive strength setting on the FPGA from
16 mA to 8 mA. Figure 1–35 shows the simulation and measurement of the FPGA
with a drive strength setting of 8 mA driving a no-parallel termination transmission
line.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–32
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Figure 1–35. HyperLynx Simulation and Measurement, FPGA Writing to Memory
Table 1–15 compares the signals at the DDR2 SDRAM DIMM with no-parallel
termination and memory-side series resistors when the FPGA is writing to the
memory with 8-mA and 16-mA drive strength settings.
Table 1–15. Simulation and Board Measurement Results for 8 mA and 16 mA Drive Strength
Settings
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
8-mA Drive Strength Setting
Simulation
1.48
1.71
0.24
0.35
Board Measurement
1.10
1.24
0.24
0.50
Simulation
1.66
1.10
0.90
0.80
Board Measurements
1.25
0.60
1.10
1.08
16-mA Drive Strength Setting
With a lower strength drive setting, the overall signal quality is improved. The eye
width is reduced, but the eye height is significantly larger with a lower drive strength
and the over- and undershoot is reduced dramatically.
To improve the signal quality further, you should use 50- on-chip series termination
in place of an 8mA drive strength and 25- on-chip series termination in place of a
16 mA drive strength. Refer to “On-Chip Termination (Non-Dynamic)” on page 1–14
for simulation and board measurements.
Summary
This section compared the effects of drive strength on the signal quality seen at the
receiver. As shown, the drive strength setting is highly dependent on the termination
scheme, so it is critical that you perform pre- and post-layout board-level simulations
to determine the proper drive strength settings. However, page 1–14 through
page 1–16 show that 50- OCT and 25- OCT drive strength settings for Class I and
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
System Loading
1–33
Class II, respectively, provide the optimum signal quality because the output driver
matches the impedance “seen” by the driver. In addition, using the OCT feature in
Altera’s FPGA devices eliminates the need for external series resistors and simplifies
board design. Finally, using the FPGA’s OCT with the SDRAM ODT feature results in
the best signal quality without any over- or undershoot.
System Loading
You can use memory in a variety of forms, such as individual components or multiple
DIMMs, resulting in different loading seen by the FPGA. This section describes the
effect on signal quality when interfacing memories in component, dual rank, and dual
DIMMs format.
Component Versus DIMM
When using discrete DDR2 SDRAM components, the additional loading from the
DDR2 SDRAM DIMM connector is eliminated and the memory-side series resistor on
the DDR2 SDRAM DIMM is no longer there. You must decide if the memory-side
series resistor near the DDR2 SDRAM is required.
FPGA Writing to Memory
Figure 1–36 shows the Class II termination scheme without the memory-side series
resistor when the FPGA is writing to the memory in the component format.
Figure 1–36. Class II Termination Scheme without Memory-Side Series Resistor
VTT = 0.9 V
VTT = 0.9 V
FPGA
RT = 56 Ω
RT = 56 Ω
DDR2 Component
16 mA
Driver
Receiver
Driver
50 Ω
VREF
3” Trace Length
VREF = 0.9 V
Receiver
Figure 1–37 shows the simulation and measurement results of the signal seen at a
DDR2 SDRAM component of a Class II termination scheme without the DIMM
connector and the memory-side series resistor. The FPGA is writing to the memory
with a 16-mA drive strength setting.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–34
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Figure 1–37. HyperLynx Simulation and Measurement of the Signal, FPGA Writing to Memory
Table 1–16 compares the signal for a single rank DDR2 SDRAM DIMM and a single
DDR2 SDRAM component in a Class II termination scheme when the FPGA is writing
to the memory.
Table 1–16. Simulation and Board Measurement Results for Single Rank DDR2 SDRAM DIMM and Single DDR2 SDRAM
Component (Note 1), (2)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Rising Edge
Rate (V/ns)
Falling Edge
Rate (V/ns)
Single DDR2 SDRAM Component
Simulation
1.79
1.15
0.39
0.33
3.90
3.43
Measurement
1.43
0.96
0.10
0.13
1.43
1.43
Single Rank DDR2 SDRAM DIMM
Simulation
1.65
0.86
N/A
N/A
1.71
1.95
Measurement
1.36
0.41
N/A
N/A
1.56
1.56
Note to Table 1–16:
(1) The drive strength on the FPGA is set to Class II 16 mA.
(2) N/A is not applicable.
The overall signal quality is comparable between the single rank DDR2 SDRAM
DIMM and the single DDR2 SDRAM component, but the elimination of the DIMM
connector and memory-side series resistor results in a more than 50% improvement in
the eye height.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
System Loading
1–35
FPGA Reading from Memory
Figure 1–38 shows the Class II termination scheme without the memory-side series
resistor when the FPGA is reading from memory. Without the memory-side series
resistor, the memory driver has less loading to drive the Class II termination.
Compare this result to the result of the DDR2 SDRAM DIMM described in “FPGA
Reading from Memory” on page 1–28 where the memory-side series resistor is on the
DIMM.
Figure 1–38. Class II Termination Scheme without Memory-Side Series Resistor
VTT = 0.9 V
VTT = 0.9 V
FPGA
DDR2 DIMM Full Strength
RT = 56 Ω
Driver
Receiver
RT = 56 Ω
RS = 22 Ω
50 Ω
VREF = 0.9 V
3” Trace Length
VREF
Driver
Receiver
Figure 1–39 shows the simulation and measurement results of the signal seen at the
FPGA. The FPGA reads from memory without the source-series resistor near the
DDR2 SDRAM component on a Class II-terminated transmission line. The FPGA
reads from memory with a full drive strength setting.
Figure 1–39. HyperLynx Simulation and Measurement, FPGA Reading from the DDR2 SDRAM Component
Table 1–17 compares the signal at a single rank DDR2 SDRAM DIMM and a single
DDR2 SDRAM component of a Class II termination scheme. The FPGA is reading
from memory with a full drive strength setting.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–36
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Table 1–17. Simulation and Board Measurement Results of Single Rank DDR2 SDRAM DIMM and DDR2 SDRAM
Component (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Rising Edge
Rate (V/ns)
Falling Edge
Rate (V/ns)
Single DDR2 SDRAM Component
Simulation
1.79
1.06
N/A
N/A
2.48
3.03
Measurement
1.36
0.63
0.13
0.00
1.79
1.14
Single Rank DDR2 SDRAM DIMM
Simulation
1.73
0.76
N/A
N/A
1.71
1.95
Measurement
1.28
0.43
N/A
N/A
0.93
0.86
Note to Table 1–17:
(1) N/A is not applicable.
The effect of eliminating the DIMM connector and memory-side series resistor is
evident in the improvement in the eye height.
Single- Versus Dual-Rank DIMM
DDR2 SDRAM DIMMs are available in either single- or dual-rank DIMM. Single-rank
DIMMs are DIMMs with DDR2 SDRAM memory components on one side of the
DIMM. Higher-density DIMMs are available as dual-rank, which has DDR2 SDRAM
memory components on both sides of the DIMM. With the dual-rank DIMM
configuration, the loading is twice that of a single-rank DIMM. Depending on the
board design, you must adjust the drive strength setting on the memory controller to
account for this increase in loading. Figure 1–40 shows the simulation result of the
signal seen at a dual rank DDR2 SDRAM DIMM. The simulation uses Class II
termination with a memory-side series resistor transmission line. The FPGA uses a
16-mA drive strength setting.
Figure 1–40. HyperLynx Simulation with a 16-mA Drive Strength Setting on the FPGA
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM Design Layout Guidelines
1–37
Table 1–18 compares the signals at a single- and dual-rank DDR2 SDRAM DIMM of a
Class II and far-end source-series termination when the FPGA is writing to the
memory with a 16-mA drive strength setting.
Table 1–18. Simulation Results of Single- and Dual-Rank DDR2 SDRAM DIMM (Note 1)
Eye Width (ns)
Eye Height (V)
Overshoot (V)
Undershoot (V)
Rising Edge
Rate (V/ns)
Falling Edge
Rate (V/ns)
1.27
0.12
0.12
0.99
0.94
1.27
0.10
0.10
1.71
1.95
Dual Rank DDR2 SDRAM DIMM
Simulation
1.34
Single Rank DDR2 SDRAM DIMM
Simulation
1.65
Note to Table 1–18:
(1) The drive strength on the FPGA is set to Class II 16 mA.
In a dual-rank DDR2 SDRAM DIMM, the additional loading leads to a slower edge
rate, which affects the eye width. The slower edge rate leads to the degradation of the
setup and hold time required by the memory as well, which must be taken into
consideration during the analysis of the timing for the interface. The overall signal
quality remains comparable, but eye width is reduced in the dual-rank DIMM. This
reduction in eye width leads to a smaller data capture window that must be taken into
account when performing timing analysis for the memory interface.
Single DIMM Versus Multiple DIMMs
Some applications, such as packet buffering, require deeper memory, making a single
DIMM interface insufficient. If you use a multiple DIMM configuration to increase
memory depth, the memory controller is required to interface with multiple data
strobes and the data lines instead of the point-to-point interface in a single DIMM
configuration. This results in heavier loading on the interface, which can potentially
impact the overall performance of the memory interface.
f
For detailed information about a multiple DIMM DDR2 SDRAM memory interface,
refer to Chapter 3, Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Drive Strength, Loading, and Board Layout Guidelines.
Summary
This section compared the effects of various loading styles on the system. With larger
loading, the eye width is reduced, shrinking the data capture window, which must be
taken into account when performing the timing analysis for the memory interface.
DDR2 SDRAM Design Layout Guidelines
Table 1–19 summarizes DDR2 SDRAM layout guidelines.
1
© November 2009
The following layout guidelines include several +/- length based rules. These length
based guidelines for first order timing approximations if you cannot simulate the
actual delay characteristic of the interface. They do not include any margin for
crosstalk.
Altera Corporation
Board Layout Guidelines
Preliminary
1–38
Loading, and Board Layout Guidelines
1
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Altera advise that when possible customers simulate their specific implementation to
get accurate time base skew numbers.
Table 1–19. DDR2 SDRAM Layout Guidelines (Part 1 of 3) (Note 1)
Parameter
Guidelines
DIMMs
If you consider a normal DDR2 unbuffered, unregistered DIMM, essentially you are planning to
perform the DIMM routing directly on your PCB. Therefore, each address and control pin
routes from the FPGA (single pin) to all memory devices must be on the same side of the
FPGA.
Impedance
■
All signal planes must be 50-60-, single-ended, ±10%
■
All signal planes must be 100, differential ±10%
■
All unused via pads must be removed, because they cause unwanted capacitance
■
Use 0.1 F in 0402 size to minimize inductance
■
Make VTT voltage decoupling close to pull-up resistors
■
Connect decoupling caps between VTT and ground
■
Use a 0.1F cap for every other VTT pin and 0.01F cap for every VDD and VDDQ pin
■
GND, 2.5 V/1.8 V must be routed as planes
■
VCCIO for memories must be routed in a single split plane with at least a 20-mil
(0.020 inches, or 0.508 mm) gap of separation
■
VTT must be routed as islands or 250-mil (6.35-mm) power traces
■
Oscillators and PLL power must be routed as islands or 100-mil (2.54-mm) power traces
Decoupling Parameter
Power
General Routing
All specified delay matching requirements include PCB trace delays, different layer propogation
velocity variance, and crosstalk. To minimise PCB layer propogation variance, Altera
recommend that signals from the same net group always be routed on the same layer.
■
Use 45° angles (not 90° corners)
■
Avoid T-Junctions for critical nets or clocks
■
Avoid T-junctions greater than 250 mils (6.35 mm)
■
Disallow signals across split planes
■
Restrict routing other signals close to system reset signals
■
Avoid routing memory signals closer than 0.025 inch (0.635 mm) to PCI or system clocks
■
All data, address, and command signals must have matched length traces ± 50 ps (±0.250
inches or 6.35 mm)
■
All signals within a given Byte Lane Group should be matched length with maximum
deviation of ±10 ps or approximately ±0.050 inches (1.27 mm) and routed in the same layer.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM Design Layout Guidelines
1–39
Table 1–19. DDR2 SDRAM Layout Guidelines (Part 2 of 3) (Note 1)
Parameter
Clock Routing
Address and Command
Routing
External Memory Routing
Rules
Guidelines
■
Clocks should be routed on inner layers with outer-layer run lengths held to under 500 mils
(12.7 mm)
■
These signals should maintain a10-mil (0.254 mm) spacing from other nets
■
Clocks should maintain a length-matching between clock pairs of ±5 ps or approximately
±25 mils (0.635 mm)
■
Differential clocks should maintain a length-matching between P and N signals of ±2 ps or
approximately ±10 mils (0.254 mm), routed in parallel
■
Space between different pairs should be at least three times the space between the
differential pairs and must be routed differentially (5-mil trace, 10-15 mil space on centers)
and equal to or up to 100 mils (2.54 mm) longer than signals in the Address/Command
Group
■
4.5 inches maximum length
■
Unbuffered address and command lines are more susceptible to cross-talk and are
generally noisier than buffered address or command lines. Therefore, un-buffered address
and command signals should be routed on a different layer than data signals (DQ) and data
mask signals (DM) and with greater spacing.
■
Do not route differential clock (CK) and clock enable (CKE) signals close to address signals.
■
Keep the distance from the pin on the DDR2 DIMM or component to the termination resistor
pack (VTT) to less than 500 mils for DQS[x] Data Groups.
■
Keep the distance from the pin on the DDR2 DIMM or component to the termination resistor
pack (VTT) to less than 1000 mils for the ADR_CMD_CTL Address Group.
■
Parallelism rules for the DQS[x] Data Groups are as follows:
■
© November 2009



4 mils for parallel runs < 0.1 inch (approximately 1X spacing relative to plane distance)

15 mils for parallel runs between 1.0 and 6.0 inch (approximately 3X spacing relative to
plane distance)
5 mils for parallel runs < 0.5 inch (approximately 1X spacing relative to plane distance)
10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2X spacing relative
to plane distance)
Parallelism rules for the ADR_CMD_CTL group and CLOCKS group are as follows:



4 mils for parallel runs < 0.1 inch (approximately 1X spacing relative to plane distance)

20 mils for parallel runs between 1.0 and 6.0 inches (approximately 4X spacing relative
to plane distance)
10 mils for parallel runs < 0.5 inch (approximately 2X spacing relative to plane distance)
15 mils for parallel runs between 0.5 and 1.0 inches (approximately 3X spacing relative
to plane distance)
■
All signals are to maintain a 20-mil separation from other, non-related nets.
■
All signals must have a total length of < 6 inches.
Altera Corporation
Board Layout Guidelines
Preliminary
1–40
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Table 1–19. DDR2 SDRAM Layout Guidelines (Part 3 of 3) (Note 1)
Parameter
Termination Rules
Guidelines
■
When pull-up resistors are used, fly-by termination configuration is recommended. Fly-by
helps reduce stub reflection issues.
■
Pull-ups should be within 0.5 to no more than 1 inch.
■
Pull up is typically 56 .
■
If using resistor networks:
■

Do not share R-pack series resistors between address/command and data lines (DQ,
DQS, and DM) to eliminate crosstalk within pack.




Series and pull up tolerances are 1–2%.
Series resistors are typically 10 to 20.
Address and control series resistor typically at the FPGA end of the link.
DM, DQS, DQ series resistor typically at the memory end of the link (or just before the
first DIMM).
If termination resistor packs are used:


The distance to your memory device should be less than 750 mils.
The distance from your Altera’s FPGA device should be less than 1250 mils.
Notes to Table 1–19:
(1) For point-to-point and DIMM interface designs, refer to the Micron website, www.micron.com.
f
For more information about how the memory manufacturers route these address and
control signals on their DIMMs, refer to the Cadence PCB browser from the Cadence
website, at www.cadence.com. The various JEDEC example DIMM layouts are
available from the JEDEC website, at www.jedec.org.
Conclusion
This chapter provides Altera’s recommendations about the termination schemes to
use when interfacing Altera FPGA devices with DDR2 SDRAM devices. However,
you must simulate your own design to find the best-suited termination scheme for
your design.
This chapter also provides data comparisons from simulation and experimental bench
results, so you can draw your own conclusions for optimum design guidelines to
achieve the best signal quality.
For termination schemes, Altera recommends that receiver-side parallel termination
be used for best signal quality. Therefore, for a bidirectional signal, such as data (DQ)
or data strobe (DQS), the recommended termination scheme is Class II termination.
You can implement Class II termination by using external parallel resistors at the
FPGA and memory side, ODT and OCT at the memory and FPGA side, or a
combination of the DDR2 SDRAM ODT and an external parallel resistor at the FPGA
side. For a unidirectional signal, such as command or address, the recommended
termination scheme is Class I termination, in which the termination is located at the
memory side. If you use on-chip termination, refer to Table 1–2 on page 1–8.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Conclusion
1–41
Choosing the drive strength setting on the FPGA depends on the termination
scheme—Class I or Class II—but the simulation results show that you should set the
drive strength to match the loading the output driver sees. For Class II termination,
Altera recommends using 25- OCT drive strength settings. They offer the best
results because the impedance of the output driver impedance matches the
impedance the output driver sees. For a Class I termination scheme, Altera
recommends the 50- OCT drive strength setting.
Moreover, this chapter describes the effects that different memory loading styles (such
as component versus DIMM) have on signal quality. From the results in “SingleVersus Dual-Rank DIMM” on page 1–36, the higher loading decreases the edge rates
of the signal, thus reducing the eye width visible at the receiver. You can increase the
edge rates by using a higher drive strength setting on the FPGA, but the output driver
impedance decreases because the higher drive strength setting causes impedance
mismatch.
Finally, this chapter provides DDR2 SDRAM layout guidelines. Although the
recommendations in this chapter are based on the simulations and experimental
results of the Stratix III Host Development Board and Stratix II Memory Board 2, you
can apply the same general principles when determining the best termination scheme,
drive strength setting, and loading style to any board designs. Even armed with this
knowledge, it is still critical that you perform simulations, either using IBIS or
HSPICE models, to determine the quality of signal integrity on your designs.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–42
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
References
This chapter references the following documents and websites:
■
Cadence website, www.cadence.com
■
JEDEC website, www.jedec.org
■
PC4300 DDR2 SDRAM Unbuffered DIMM Design Specification
■
PC5300/6400 DDR2 SDRAM Unbuffered DIMM Design Specification
■
Stratix III Device I/O Features chapter in the Stratix III Device Handbook
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Bibliography
1–43
Bibliography
“High-Speed Digital Design—A Handbook of Black Magic,” Howard Johnson and
Martin Graham, Prentice Hall, 1993.
“Circuits Interconnects, and Packaging for VLSI,“ H.B. Bakoglu, Addison Wesley,
1990.
“Signal Integrity—Simplified,“ Eric Bogatin, Prentice Hall Modern Semiconductor
Design Series, 2004.
“Handbook of Digital Techniques for High-Speed Design,“ Tom Granberg, Prentice
Hall Modern Semiconductor Design Series, 2004.
“DDR2 Design Guide for Two-DIMM Systems,“ Micron Technical Note, TN-47-01,
2004.
“Termination Placement in PCB Design: How Much Does it Matter?”, Doug Brooks,
UltraCAD Design Inc.
“Stratix II Memory Board 2 Rev A User Guide 1.0,“ Altera’s High-Speed/End
Applications Team, 2004.
“Stratix II Memory Board 2 Layout Guidelines Rev 0.4,“ Altera’s High-Speed/End
Applications Team, 2004.
“Stratix to DDR-I Memory Devices Interface Analysis,“ Altera’s High-Speed/End
Applications Team, 2004.
“Multiconductor Transmission Line Analysis for Board-Level Digital Design,“
Emmanuel A. Maitre, Master Thesis, Santa Clara University, 1994.
JEDEC Standard Publication JESD79C, DDR SDRAM Specification, JEDEC Solid State
Technology Association.
JEDEC Standard Publication JESD79-2, DDR2 SDRAM Specification, JEDEC Solid
State Technology Association.
JEDEC Standard Publication JESD8-9B, Stub Series Termination Logic for 2.5 V
(SSTL-2), JEDEC Solid State Technology Association.
JEDEC Standard Publication JESD8-15A, Stub Series Termination Logic for 1.8 V
(SSTL-18), JEDEC Solid State Technology Association.
PC4300 DDR2 SDRAM Unbuffered DIMM Design Specification, Revision 0.5, Oct 30,
2003.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
1–44
Loading, and Board Layout Guidelines
Chapter 1: DDR2 SDRAM Interface Termination, Drive Strength,
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
2. DDR3 SDRAM Interface Termination,
Drive Strength, Loading, and Board Layout
Guidelines
This chapter provides guidelines on how to improve the signal integrity of your
system and layout guidelines to help you successfully implement a DDR3 SDRAM
interface on your system.
Synchronous Dynamic Random Access Memory (SDRAM) has continually evolved
over the years to keep up with ever-increasing computing needs. The latest addition
to SDRAM technology is DDR3 SDRAM. DDR3 SDRAM is the third generation of the
DDR SDRAM family, and offers improved power, higher data bandwidth, and
enhanced signal quality with multiple on-die termination (ODT) selection and output
driver impedance control while maintaining partial backward compatibility with the
existing DDR2 SDRAM standard.
DDR3 SDRAM offers features designed to improve signal integrity of increased bus
speed. While some of the features are already available in DDR2 SDRAM, these
features are further enhanced in DDR3 SDRAM. For example, the ODT feature is
available in both DDR2 and DDR3 SDRAM, but in DDR3 SDRAM, the values of the
ODT are based on the value of an external resistor—the RZQ resistor. In addition to
using this ZQ resistor for setting the ODT value, it is also used for calibrating the ODT
value so that it maintains its resistance value to within a 10% tolerance. This chapter
describes the following updated and new features in DDR3 SDRAM:
■
ODT values selection
■
Output driver impedance selection
■
ZQ calibration
■
Dynamic ODT usage
To take advantage of these new features offered by DDR3 SDRAM, Altera's Stratix III
and Stratix IV FPGAs have special features to ease and expedite your implementation
of DDR3 SDRAM interfaces.
With Leveling or Without Leveling
Altera offers the DDR3 SDRAM PHY with or without leveling.
With Leveling
DDR3 SDRAM DIMMs, as specified by JEDEC, always use a fly-by topology for the
address, command, and clock signals. This standard DDR3 SDRAM topology requires
the use of the Altera DDR3 SDRAM ALTMEMPHY megafunction with read and write
leveling.
Altera recommends that for full DDR3 SDRAM compatibility when using discrete
DDR3 SDRAM components, you should mimic the JEDEC DDR3 uDIMMs fly-by
topology on your custom PCBs.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–2
Loading, and Board Layout Guidelines
1
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Arria II GX devices do not support DDR3 SDRAM with read or write leveling, so
standard DDR3 SDRAM DIMMs or DDR3 SDRAM components using the standard
DDR3 SDRAM fly-by address, command, and clock layout topology are not
supported. Refer to “Termination for DDR3 SDRAM Components (Without
Leveling)” on page 2–26, for more information on how to use DDR3 SDRAM
components with Arria II GX devices.
Use of the standard JEDEC DDR3 fly-by topology with leveling offers the following
advantages:
f
■
Easier layout
■
Lower SSN for the memory
■
Higher data rates
Refer to “Read and Write Leveling” on page 2–2 for more detailed information on
read and write leveling.
Without Leveling
Altera also supports DDR3 SDRAM components without leveling, using a
nonstandard, synchronous DDR2-like balanced address, command, and clock layout
topology. DDR3 SDRAM interfaces without leveling operate at lower maximum data
rates compared to the standard fly-by topology. DDR3 SDRAM interfaces without
leveling may be desirable for the following reasons:
■
The Arria II GX device family does not support read and write leveling, so DDR3
SDRAM DIMMs or topology is not supported, but the I/O electrical standard is
supported
■
DDR3 SDRAM PHYs without leveling typically have a slightly lower PHY latency
when compared to the DDR3 SDRAM PHY with leveling
■
The DDR3 SDRAM PHY without leveling typically requires less FPGA resources
than an equivalent DDR3 SDRAM PHY with leveling
■
You may only require DDR2-like interface performance but want to use the lower
power, potential cost, and availability benefits of DDR3 SDRAM components
Comparing DDR3 and DDR2
The following sections review the differences between DDR2 and DDR3 SDRAM and
the changes in the features that were made to DDR3 SDRAM. Understanding these
differences makes the design process for your DDR3 SDRAM interface easier.
Read and Write Leveling
One major difference between DDR2 and DDR3 SDRAM is the use of leveling. To
improve signal integrity and support higher frequency operations, the JEDEC
committee defined a fly-by termination scheme used with the clocks and command
and address bus signals. Fly-by topology reduces simultaneous switching noise (SSN)
by deliberately causing flight-time skew between the data and strobes at every DRAM
as the clock, address, and command signals traverse the DIMM (Figure 2–1).
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Comparing DDR3 and DDR2
2–3
Figure 2–1. DDR3 DIMM Fly-By Topology Requiring Write Leveling (Note 1)
Command, Address, Clock in
“Flyby” topology in DDR3 DIMM
VTT
Data Skew
Data Skew Calibrated Out at Power Up with Write Leveling
Note to Figure 2–1:
(1) Source: Consumer Electronics are Changing the Face of DRAMs, By Jody Defazio, Chip Design Magazine, June 29, 2007.
The flight-time skew due to the fly-by topology led the JEDEC committee to introduce
the write leveling feature on the DDR3 SDRAMs, thus requiring controllers to
compensate for this skew by adjusting the timing per byte lane.
During a write, DQS groups are launched at separate times to coincide with a clock
arriving at components on the DIMM, and must meet the timing parameter between
the memory clock and DQS defined as tDQSS of ± 0.25 tCK.
During the read operation, the memory controller must compensate for the delays
introduced by the fly-by topology. In Stratix® III and Stratix IV FPGAs, there are
alignment and synchronization registers built in the input output element (IOE) to
properly capture the data. Figure 2–2 shows two DQS groups returning from the
DIMM for the same read command.
f
For information about the IOE block in Stratix III devices, refer to the External Memory
Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook.
For information about the IOE block in Stratix IV devices, refer to the External Memory
Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
FPGA Fabric
Half Data Rate Registers
Alignment & Synchronization Registers
0
Double Data Rate Input Registers
D
D
Q
D
Q
D
DFF
Q
D
DFF
DFF
1
Q
Q
D
DFF
DQ
Input Reg A I
Q
To Core
(rdata1)
DFF
DFF
D
D
Q
neg_reg_out
D
Q
D
DQS
DFF
DFF
I
Input Reg C
I
0
D
D
DQSn
Q
D
To Core (rdata2)
1
Q
Q
0
CQn
dataoutbypass
Q
Q
DFF
DFF
Input Reg B
Differential
Input
Buffer
To Core (rdata0)
DFF
D
1
DFF
Q
DFF
D
Q
To Core
(rdata3)
DFF
D
DFF
Resynchronization
Clock
(resync_clk_2x)
Q
D
Q
DFF
DFF
Preliminary
to core
I/O Clock
Divider
IOE
Half-Rate Resynchronization Clock (resync_clk_1x)
0
D
D
Q
D
Q
D
D
DFF
DQ
DFF
Q
D
DFF
DFF
Input Reg A I
Q
To Core
(rdata1)
DFF
DFF
D
D
Q
neg_reg_out
D
Q
D
© November 2009
DQS
DFF
DFF
I
Input Reg C
I
0
D
D
DQSn
CQn
Q
D
1
Q
Q
0
DFF
D
1
DFF
Q
DFF
D
Q
To Core
(rdata3)
DFF
DFF
Altera Corporation
Resynchronization
Clock
(resync_clk_2x)
IOE
dataoutbypass
Q
Q
DFF
DFF
Input Reg B
To Core (rdata0)
1
Q
Q
D
Q
DFF
I/O Clock
Divider
D
Q
DFF
to core
Half-Rate Resynchronization Clock (resync_clk_1x)
To Core (rdata2)
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Half Data Rate Registers
Alignment & Synchronization Registers
Double Data Rate Input Registers
Differential
Input
Buffer
2–4
Loading, and Board Layout Guidelines
Board Layout Guidelines
Figure 2–2. DDR3 DIMM Fly-By Topology Requiring Read Leveling
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Comparing DDR3 and DDR2
2–5
Calibrated Output Impedance and ODT
In DDR2 SDRAM, there are only two drive strength settings, full or reduced, which
correspond to the output impedance of 18  and 40 , respectively. These output
drive strength settings are static settings and are not calibrated; as a result, the output
impedance varies as the voltage and temperature drifts. The DDR3 SDRAM uses a
programmable impedance output buffer. Currently, there are two drive strength
settings, 34 and 40 . The 40- drive strength setting is currently a reserved
specification defined by JEDEC, but available on the DDR3 SDRAM, as offered by
some memory vendors. Refer to the datasheet of the respective memory vendors for
more information about the output impedance setting. The drive strength setting is
selected by programming the memory mode register setting defined by mode
register 1 (MR1). To calibrate output driver impedance, an external precision resistor,
RZQ, is connected between the ZQ pin and VSSQ. The value of this resistor must be
240  ± 1%. If you are using a DDR3 SDRAM DIMM, RZQ is soldered on the DIMM
so you do not need to layout your board to account for it. Output impedance is set
during initialization. To calibrate output driver impedance after power-up, the DDR3
SDRAM needs a calibration command that is part of the initialization and reset
procedure and is updated periodically when the controller issues a calibration
command.
In addition to calibrated output impedance, the DDR3 SDRAM also supports
calibrated parallel ODT via the same external precision resistor, RZQ, which is
possible by using a merged output driver structure in the DDR3 SDRAM, which also
helps to improve pin capacitance in the DQ and DQS pins. The ODT values supported
in DDR3 SDRAM are 20 , 30 , 40 , 60 , and 120 , assuming that RZQ is 240 .
In DDR3 SDRAM, there are two commands related to the calibration of the output
driver impedance and ODT. The first calibration command, ZQ CALIBRATION
LONG (ZQCL), is often used at initial power-up or when the DDR3 SDRAM is in a
reset condition. This command calibrates the output driver impedance and ODT to
the initial temperature and voltage condition, and compensates for any process
variation due to manufacturing. If the ZQCL command is issued at initialization or
reset, it takes 512 memory clock cycles to complete; otherwise, it requires 256 memory
clock cycles to complete. The second calibration command, ZQ CALIBRATION
SHORT (ZQCS) is used during regular operation to track any variation in
temperature or voltage. The ZQCS command takes 64 memory clock cycles to
complete. Use the ZQCL command any time there is more impedance error than can
be corrected with a ZQCS command.
f
For more information about using ZQ Calibration in DDR3 SDRAM, refer to the
application note by Micron, TN-41-02 DDR3 ZQ Calibration.
Dynamic ODT
Dynamic ODT is a new feature in DDR3 SDRAM, and not available in DDR2 SDRAM.
Dynamic ODT can change the ODT setting without issuing a mode register set (MRS)
command. When you enable dynamic ODT, and there is no write operation, the DDR3
SDRAM is terminated to a termination setting of RTT_NORM; when there is a write
operation, the DDR3 SDRAM is terminated to a setting of RTT_WR. The values of
RTT_NORM and RTT_WR are preset by programming the mode registers, MR1 and
MR2. Figure 2–3 shows the behavior of ODT when dynamic ODT is enabled.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–6
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–3. Dynamic ODT: Behavior with ODT Asserted Before and After the Write (Note 1)
Note to Figure 2–3:
(1) Source: TN-41-04 DDR3 Dynamic On-Die Termination, Micron.
In the two-DIMM DDR3 SDRAM configuration, dynamic ODT helps reduce the jitter
at the module being accessed, and minimizes reflections from any secondary
modules.
f
For more information about using the dynamic ODT on DDR3 SDRAM, refer to the
application note by Micron, TN-41-04 DDR3 Dynamic On-Die Termination.
Dynamic OCT in Stratix III and Stratix IV Devices
Stratix III and Stratix IV devices support on-off dynamic series and parallel
termination for a bi-directional I/O in all I/O banks. Dynamic OCT is a new feature in
Stratix III and Stratix IV FPGA devices. Dynamic parallel termination is enabled only
when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bi-directional I/O acts
as a driver and is disabled when it acts as a receiver. The default setting for dynamic
OCT is series termination, to save power when the interface is idle (no active reads or
writes).
1
Additionally, the dynamic control operation of the OCT is separate to the output
enable signal for the buffer. Hence, the Altera ALTMEMPHY megafunction can only
enable parallel OCT during read cycles, saving power when the interface is idle.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Unbuffered DIMMs
2–7
Figure 2–4. Dynamic OCT Between Stratix III and Stratix IV FPGA Devices
FPGA
DDR3 DIMM
DDR3 Component
50 Ω
34 W
Driver
Driver
100 W
R S = 15 Ω
50 Ω
3" Trace Length
VREF = 0.75 V
VREF = 0.75 V
Receiver
100 W
Receiver
FPGA
DDR3 DIMM
DDR3 Component
34 Ω
50 W
Driver
Driver
100 Ω
R S = 15 Ω
50 Ω
3" Trace Length
VREF = 0.75 V
VREF = 0.75 V
100 Ω
Receiver
Receiver
This feature is useful for terminating any high-performance bi-directional path
because signal integrity is optimized depending on the direction of the data. In
addition, dynamic OCT also eliminates the need for external termination resistors
when used with memory devices that support ODT (such as DDR3 SDRAM), thus
reducing cost and easing board layout.
However, dynamic OCT in Stratix III and Stratix IV FPGA devices is different from
dynamic ODT in DDR3 SDRAM mentioned in previous sections and these features
should not be assumed to be identical.
f
For detailed information about the dynamic OCT feature in the Stratix III FPGA, refer
to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device
Handbook.
For detailed information about the dynamic OCT feature in the Stratix IV FPGA, refer
to the I/O Features in Stratix IV Devices chapter in volume 1 of the Stratix IV Device
Handbook.
Termination for DDR3 SDRAM Unbuffered DIMMs
The following sections describe the correct way to terminate a DDR3 SDRAM
interface together with Altera® Stratix III and Stratix IV FPGA devices.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–8
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
DDR3 SDRAM Unbuffered DIMM
The most common implementation of the DDR3 SDRAM interface is the unbuffered
DIMM. Unbuffered DDR3 SDRAM DIMMs can be found in many applications,
especially in personal computer (PC) applications. A DDR3 SDRAM unbuffered
DIMM interface can be implemented in several permutations, such as single DIMM or
multiple DIMMs, using either single-ranked or dual-ranked unbuffered DIMMs. In
addition to the unbuffered DIMMs form factor, these termination recommendations
are also valid for small-outline (SO) DIMMs and MicroDIMMs.
Table 2–1 outlines the different permutations of a two-slot DDR3 SDRAM interface
and the recommended ODT settings on both the memory and controller when writing
to memory.
Table 2–1. DDR3 SDRAM ODT Matrix for Writes (Note 1) and (2)
Slot 1
Slot 1
Slot 2
Write To
Slot 2
Controller
OCT (3)
Rank 1
Series 50 
120 (4)
ODT off
Rank 2
Rank 1
Rank 2
40 (4)
DR
DR
Slot 1
ODT off
Slot 2
Series 50 
ODT off
40 (4)
120 (4)
ODT off
SR
SR
Slot 1
Series 50 
120  (4)
Unpopulated
40 (4)
Unpopulated
Slot 2
Series 50 
40  (4)
Unpopulated
120  (4)
Unpopulated
DR
Empty
Slot 1
Series 50 
120 
ODT off
Unpopulated
Unpopulated
Empty
DR
Slot 2
Series 50 
Unpopulated
Unpopulated
120 
ODT off
SR
Empty
Slot 1
Series 50 
120 
Unpopulated
Unpopulated
Unpopulated
Empty
SR
Slot 2
Series 50 
Unpopulated
Unpopulated
120 
Unpopulated
Notes to Table 2–1:
(1) SR: single-ranked DIMM; DR: dual-ranked DIMM.
(2) These recommendations are taken from the DDR3 ODT and Dynamic ODT session of the JEDEC DDR3 2007 Conference, Oct 3-4, San Jose, CA.
(3) The controller in this case is the FPGA.
(4) Dynamic ODT is required. For example, the ODT of Slot 2 is set to the lower ODT value of 40  when the memory controller is writing to Slot 1,
resulting in termination and thus minimizing any reflection from Slot 2. Without dynamic ODT, Slot 2 will not be terminated.
Table 2–2 outlines the different permutations of a two-slot DDR3 SDRAM interface
and the recommended ODT settings on both the memory and controller when
reading from memory.
Table 2–2. DDR3 SDRAM ODT Matrix for Reads (Note 1) and (2) (Part 1 of 2)
Slot 1
Slot 1
DR
SR
Slot 2
DR
SR
Read From
Controller
OCT (3)
Rank 1
Slot 2
Rank 2
Rank 1
Rank 2
Slot 1
Parallel 50 
ODT off
ODT off
ODT off
40 
Slot 2
Parallel 50 
ODT off
40 
ODT off
ODT off
Slot 1
Parallel 50 
ODT off
Unpopulated
40 
Unpopulated
Slot 2
Parallel 50 
40 
Unpopulated
ODT off
Unpopulated
DR
Empty
Slot 1
Parallel 50 
ODT off
ODT off
Unpopulated
Unpopulated
Empty
DR
Slot 2
Parallel 50 
Unpopulated
Unpopulated
ODT off
ODT off
SR
Empty
Slot 1
Parallel 50 
ODT off
Unpopulated
Unpopulated
Unpopulated
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Unbuffered DIMMs
2–9
Table 2–2. DDR3 SDRAM ODT Matrix for Reads (Note 1) and (2) (Part 2 of 2)
Slot 1
Slot 1
Empty
Slot 2
SR
Read From
Slot 2
Slot 2
Controller
OCT (3)
Rank 1
Rank 2
Parallel 50 
Unpopulated
Unpopulated
Rank 1
ODT off
Rank 2
Unpopulated
Notes to Table 2–2:
(1) SR: single-ranked DIMM; DR: dual-ranked DIMM.
(2) These recommendations are taken from the DDR3 ODT and Dynamic ODT session of the JEDEC DDR3 2007 Conference, Oct 3-4, San Jose, CA.
(3) The controller in this case is the FPGA. JEDEC typically recommends 60 , but this value assumes that the typical motherboard trace impedance
is 60 and that teh controller supports this termination. Altera recommends using a 50- parallel OCT when reading from the memory.
DQS, DQ, and DM for DDR3 SDRAM Unbuffered DIMM
On a single-ranked DIMM, DQS, and DQ signals are point-to-point signals.
Figure 2–5 shows the net structure for differential DQS and DQ signals. There is an
external 15- stub resistor, RS, on each of the DQS and DQ signals soldered on the
DIMM, which helps improve signal quality by dampening reflections from unused
slots in a multi-DIMM configuration.
Figure 2–5. DQ and DQS Net Structure for 64-Bit DDR3 SDRAM Unbuffered DIMM (Note 1)
(2)
(2)
Notes to Figure 2–5:
(1) Source: PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Unbuffered DIMM Design Specification, July 2007, JEDEC Solid State
Technology Association. For clarity of the signal connections in the illustration, the same SDRAM is drawn as two separate SDRAMs.
As mentioned in “Dynamic ODT” on page 2–5, DDR3 SDRAM supports calibrated
ODT with different ODT value settings. If dynamic ODT is not enabled, there are
three possible ODT settings available for RTT_NORM: 40 , 60 , and 120 . When
dynamic ODT is enabled, the number of possible ODT settings available for
RTT_NORM increases from three to five with the addition of 20  and 30 . Table 2–1
shows that the recommended ODT setting on the DDR3 SDRAM is 120 . Trace
impedance on the DIMM is 60 , and over-terminating the DDR3 SDRAM
components on the DIMM with 120  compensates for trace impedance variation on
the DIMM due to manufacturing.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–10
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–6 shows the write-eye diagram at the DQ0 of a DDR3 SDRAM DIMM using
the 120- ODT setting, driven by a Stratix III or Stratix IV FPGA using a calibrated
series 50- OCT setting.
Figure 2–6. Simulated Write-Eye Diagram of a DDR3 SDRAM DIMM Using a 120-  ODT Setting
When over-terminating the receiver, the mismatch between load impedance and trace
impedance causes ringing at the receiver (Figure 2–6). When the DDR3 SDRAM ODT
setting is set to 60 , there is less ringing at the receiver (Figure 2–7).
Figure 2–7. Simulated Write-Eye Diagram of a DDR3 SDRAM DIMM Using a 60- ODT Setting
Table 2–3 compares the effects of the ODT setting on the eye diagram at the DDR3
SDRAM (receiver) when the Stratix III or Stratix IV FPGA is writing to memory.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Unbuffered DIMMs
2–11
Table 2–3. Write-Eye Diagram Using Different ODT Setting
ODT
Eye Height (V)
Eye Width (ps)
Overshoot (V)
Undershoot (V)
120- ODT
0.84
713
—
—
60- ODT
0.73
715
—
—
Although both 120- and 60- ODT settings result in excellent signal quality and
acceptable eye opening, using 120  results in a larger eye height because of
under-termination, yet it has a minimal effect on eye width. Because the use of 60-
ODT results in less ringing, the 60- ODT setting is used on the remaining DDR3
SDRAM DIMM testing featured in this document. Figure 2–8 shows the measured
write-eye diagram using Altera’s Stratix III and Stratix IV memory board.
Figure 2–8. Measured Write-Eye Diagram of a DDR3 SDRAM DIMM Using the 60- ODT Setting
The measured eye diagram correlates well with the simulation. The faint line in the
middle of the eye diagram is the effect of the refresh operation during a regular
operation. Because these simulations and measurements are based on a narrow set of
constraints, you must perform your own board-level simulation to ensure that the
chosen ODT setting is right for your setup.
Memory Clocks for DDR3 SDRAM Unbuffered DIMM
For the DDR3 SDRAM unbuffered DIMM, memory clocks are already terminated on
the DIMM, so you do not need to place any termination on your board. Figure 2–9
shows the net structure for the memory clocks and the location of the termination
resistors, RTT. The value of RTT is 36  which results in an equivalent differential
termination value of 72 . On the DDR3 SDRAM DIMM, there is also a compensation
capacitor, CCOMP of 2.2 pF, placed between the differential memory clocks to improve
signal quality.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–12
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–9. Clock Net Structure for a 64-Bit DDR3 SDRAM Unbuffered DIMM (Note 1)
Note to Figure 2–9:
(1) Source: PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Unbuffered DIMM Design Specification, July 2007, JEDEC Solid State
Technology Association.
From Figure 2–9, you can see that the DDR3 SDRAM clocks are routed in a fly-by
topology, as mentioned in “Read and Write Leveling” on page 2–2, resulting in the
need for write-and-read leveling. Figure 2–10 shows the HyperLynx simulation of the
differential clock seen at the first and last DDR3 SDRAM component on the
unbuffered DIMM using the 50- OCT setting on the output driver of the Stratix III
and Stratix IV FPGA.
Figure 2–10. Differential Memory Clock of a DDR3 SDRAM DIMM at the First and Last Component on the DIMM
Figure 2–10 shows that the memory clock seen at the first DDR3 SDRAM component
(the yellow signal) leads the memory clock seen at the last DDR3 SDRAM component
(the green signal) by 1.3 ns, which is about 0.69 tCK for a 533 MHz operation.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Unbuffered DIMMs
2–13
Commands and Addresses for DDR3 SDRAM Unbuffered DIMM
Similar to memory clock signals, the command and address signals are also
terminated on the DIMM, so you do not need to place any termination on your board.
Figure 2–11 shows the net structure for the command and address signals and the
location of the termination resistor, RTT, which has an RTT value of 39 .
Figure 2–11. Command and Address Net Structure for a 64-Bit DDR3 SDRAM Unbuffered DIMM (Note 1)
Note to Figure 2–11:
(1) Source: PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Unbuffered DIMM Design Specification, July 2007, JEDEC Solid State
Technology Association.
In Figure 2–11, you can see that the DDR3 SDRAM command and address signals are
routed in a fly-by topology, as mentioned in “Read and Write Leveling” on page 2–2,
resulting in the need for write-and-read leveling.
Figure 2–12 shows the HyperLynx simulation of the command and address signal
seen at the first and last DDR3 SDRAM component on the unbuffered DIMM, using a
25- OCT setting on the output driver of the Stratix III and Stratix IV FPGA.
Figure 2–12. Command and Address Eye Diagram of a DDR3 SDRAM DIMM at the First and Last DDR3 SDRAM Component
at 533 MHz (Note 1)
Note to Figure 2–12:
(1) The command/address simulation is performed using a bit period of 1.875 ns.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–14
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–12 shows that the command and address signal seen at the first DDR3
SDRAM component (the green signal) leads the command and address signals seen at
the last DDR3 SDRAM component (the red signal) by 1.2 ns, which is 0.64 tCK for a
533-MHz operation.
Stratix III and Stratix IV FPGAs
The following sections review termination used on the single-ranked single DDR3
SDRAM DIMM interface side and investigate the use of different termination features
available in Stratix III and Stratix IV FPGA devices to achieve optimum signal
integrity for your DDR3 SDRAM interface.
DQS, DQ, and DM for Stratix III and Stratix IV FPGA
As mentioned in “Dynamic OCT in Stratix III and Stratix IV Devices” on page 2–6,
Stratix III and Stratix IV FPGAs support the dynamic OCT feature, which switches
from series termination to parallel termination depending on the mode of the I/O
buffer. Because DQS and DQ are bi-directional signals, DQS and DQ can be both
transmitters and receivers. “DQS, DQ, and DM for DDR3 SDRAM Unbuffered
DIMM” on page 2–9 describes the signal quality of DQ, DQS, and DM when the
Stratix III or Stratix IV FPGA device is the transmitter with the I/O buffer set to a 50-
series termination. This section details the condition when the Stratix III or Stratix IV
device is the receiver, the Stratix III and Stratix IV I/O buffer is set to a 50- parallel
termination, and the memory is the transmitter. DM is a unidirectional signal, so the
DDR3 SDRAM component is always the receiver. Refer to “DQS, DQ, and DM for
DDR3 SDRAM Unbuffered DIMM” on page 2–9 for receiver termination
recommendations and transmitter output drive strength settings.
Figure 2–13 illustrates the DDR3 SDRAM interface when the Stratix III and Stratix IV
FPGA device is reading from the DDR3 SDRAM using a 50- parallel OCT
termination on the Stratix III and Stratix IV FPGA device, and the DDR3 SDRAM
driver output impedance is set to 34 .
Figure 2–13. DDR3 SDRAM Component Driving the Stratix III and Stratix IV FPGA Device with Parallel 50- OCT Turned On
Figure 2–14 shows the simulation of a read from the DDR3 SDRAM DIMM with a
50- parallel OCT setting on the Stratix III and Stratix IV FPGA device.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Unbuffered DIMMs
2–15
Figure 2–14. Read-Eye Diagram of a DDR3 SDRAM DIMM at the Stratix III and Stratix IV FPGA Using a Parallel 50-
OCT Setting
Use of the Stratix III and Stratix IV parallel 50- OCT feature matches receiver
impedance with the transmission line characteristic impedance. This eliminates any
reflection that causes ringing, and results in a clean eye diagram at the Stratix III and
Stratix IV FPGA.
Memory Clocks for Stratix III and Stratix IV FPGA
Memory clocks are unidirectional signals. Refer to “Memory Clocks for DDR3
SDRAM Unbuffered DIMM” on page 2–11 for receiver termination recommendations
and transmitter output drive strength settings.
Commands and Addresses for Stratix III and Stratix IV FPGA
Commands and addresses are unidirectional signals. Refer to “Commands and
Addresses for DDR3 SDRAM Unbuffered DIMM” on page 2–13 for receiver
termination recommendations and transmitter output drive strength settings.
Summary
This section discusses terminations used for implementing the DDR3 SDRAM
interface using the single-ranked, single unbuffered DIMM. Terminations for
unidirectional signals, such as memory clocks and addresses and commands, are
placed on the DIMM, thus eliminating the need to place terminations on the board. In
addition, using the ODT feature on the DDR3 SDRAM and the Dynamic OCT feature
of Stratix III and Stratix IV FPGA devices completely eliminates any external
termination resistors, thus simplifying the layout for the DDR3 SDRAM interface
when compared to that of the DDR2 SDRAM interface.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–16
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Termination for DDR3 SDRAM Components (With Leveling)
In addition to using DDR3 SDRAM DIMM to implement your DDR3 SDRAM
interface, you can also use DDR3 SDRAM components. However, for applications
that have limited board real estate, using DDR3 SDRAM components reduces the
need for a DIMM connector and places components closer, resulting in denser
layouts.
DDR3 SDRAM Components
The DDR3 SDRAM unbuffered DIMM is laid out to the JEDEC specification. The
JEDEC specification is available from either the JEDEC Organization website
(www.JEDEC.org) or from the memory vendors. However, when you are designing
the DDR3 SDRAM interface using discrete SDRAM components, you may desire a
layout scheme that is different than the DIMM specification. You have the following
two options:
■
Mimic the standard DDR3 SDRAM DIMM, using a fly-by topology for the
memory clocks, address, and command signals. This options needs read and write
leveling, so you must use the ALTMEMPHY megafunction with leveling.
f
■
For more information on this fly-by configuration, continue reading this
chapter.
Mimic a standard DDR2 SDRAM DIMM, using a balanced (symmetrical) tree-type
topology for the memory clocks, address, and command signal. Using this
topology results in unwanted stubs on the command, address, and clock, which
degrades signal integrity and limits the performance of the DDR3 SDRAM
interface.
f
For more information on using this non-standard symmetrical
configuration, refer to “Termination for DDR3 SDRAM Components
(Without Leveling)” on page 2–26.
DQS, DQ, and DM for DDR3 SDRAM Components
When you are laying out the DDR3 SDRAM interface using Stratix III or Stratix IV
devices, you do not need to include the 15- stub series resistor that is on every DQS,
DQ, and DM signal, because DQS, DQ, and DM are point-to-point connections.
Therefore, the recommended DQS, DQ, and DM topology appears (Figure 2–15) when
the Stratix III or Stratix IV FPGA is writing to the DDR3 SDRAM.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (With Leveling)
2–17
Figure 2–15. Stratix III and Stratix IV FPGA Writing to a DDR3 SDRAM Components
When you are using DDR3 SDRAM components, there are no DIMM connectors. This
minimizes any impedance discontinuity, resulting in better signal integrity.
Figure 2–16 shows the simulated write-eye diagram at the DQ0 of a DDR3 SDRAM
component using the 120- ODT setting, and driven by a Stratix III or Stratix IV
FPGA using a calibrated series 50- OCT setting.
Figure 2–16. Write-Eye Diagram of a DDR3 SDRAM Component Using a 120- ODT Setting
Similarly, Figure 2–17 shows the simulated write-eye diagram at the DQ0 of a DDR3
SDRAM component using the 60- ODT setting, and driven by a Stratix III or Stratix
IV FPGA using a calibrated series 50- OCT setting.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–18
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–17. Write-Eye Diagram of a DDR3 SDRAM Component Using a 60- ODT Setting
Table 2–4 compares the effects of the series stub resistor on the eye diagram at the
DDR3 SDRAM (receiver) when the Stratix III or Stratix IV FPGA is writing to
memory.
Table 2–4. Simulated Write-Eye Diagram with and without RS and Using Different ODT Settings
ODT
Eye Height (V)
Eye Width (ps)
Overshoot (V)
Undershoot (V)
120- ODT with RS
0.84
713
—
—
60- ODT with RS
0.73
715
—
—
120- ODT without RS
0.95
734
—
—
60- ODT without RS
0.83
737
—
—
Without the 15- stub series resistor to dampen the signal arriving at the receiver of
the DDR3 SDRAM component, the signal at the receiver of that component is larger
than the signal at the receiver of a DIMM (Figure 2–6 and Figure 2–7).
Memory Clocks for DDR3 SDRAM Components
When you use DDR3 SDRAM components, you must account for the compensation
capacitor and differential termination resistor between the differential memory clocks
of the DIMM. Figure 2–18 shows the HyperLynx simulation of the differential clock
seen at the first and last DDR3 SDRAM component using a flyby topology on a board,
without the 2.2 pF compensation capacitor using the 50- OCT setting on the output
driver of the Stratix III and Stratix IV FPGA.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (With Leveling)
2–19
Figure 2–18. Differential Memory Clock of a DDR3 SDRAM Component without the Compensation Capacitor at the First and
Last Component Using a Fly-by Topology on a Board
Without the compensation capacitor, the memory clocks (the yellow signal) at the first
component have significant ringing, whereas, with the compensation capacitor the
ringing is dampened. Similarly, the differential termination resistor needs to be
included in the design. Depending on your board stackup and layout requirements,
you choose your differential termination resistor value. Figure 2–19 shows the
HyperLynx simulation of the differential clock seen at the first and last DDR3 SDRAM
component using a fly-by topology on a board, and terminated with 100  instead of
the 72  used in the DIMM.
Figure 2–19. Differential Memory Clock of a DDR3 SDRAM DIMM Terminated with 100  at the First and Last Component
Using a Fly-by Topology on a Board
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–20
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Terminating with 100  instead of 72  results in a slight reduction in peak-to-peak
amplitude. To simplify your design, use the terminations outlined in the JEDEC
specification for unbuffered DDR3 SDRAM DIMM as your guide and perform
simulation to ensure that the unbuffered DDR3 SDRAM DIMM terminations provide
you with optimum signal quality.
In addition to choosing the value of the differential termination, you must consider
the trace length of the memory clocks. There is no specification on the flight-time
skew between the first and last component when designing with DDR3 SDRAM
components on your board. Altera’s DDR3 ALTMEMPHY megafunction currently
supports a flight-time skew of no more than 0.69 tCK. If you use Altera’s DDR3
ALTMEMPHY megafunction to create your DDR3 SDRAM interface, ensure that the
flight-time skew of your memory clocks is not more than 0.69 tCK.
1
Refer to “Layout Considerations (with Leveling)” on page 2–23 for more information
about layout guidelines for DDR3 SDRAM components.
Commands and Addresses for DDR3 SDRAM Components
As with memory clock signals, you must account for the termination resistor on the
command and address signals when you use DDR3 SDRAM components. Choose
your termination resistor value depending on your board stackup and layout
requirements. Figure 2–20 shows the HyperLynx simulation of the command and
address seen at the first and last DDR3 SDRAM component using a flyby topology on
a board terminated with 60  instead of the 39  used in the DIMM.
Figure 2–20. Command and Address Eye Diagram of a DDR3 SDRAM Component Using Flyby Topology on a Board at the
First and Last DDR3 SDRAM Component at 533 MHz, Terminated with 60 
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (With Leveling)
2–21
Terminating with 60  instead of 39  results in eye closure in the signal at the first
component (the green signal), while there is no effect on the signal at the last
component (the red signal). To simplify your design with discrete DDR3 SDRAM
components, use the terminations outlined in the JEDEC specification for unbuffered
DDR3 SDRAM DIMM as your guide, and perform simulation to ensure that the
unbuffered DDR3 SDRAM DIMM terminations provide you with the optimum signal
quality.
As with memory clocks, you must consider the trace length of the command and
address signals so that they match the flight-time skew of the memory clocks.
Stratix III and Stratix IV FPGAs
The following sections describe termination used on the DDR3 SDRAM component
interface side and investigate using the different termination features available in
Stratix III and Stratix IV FPGA devices, so you can achieve optimum signal integrity
for your DDR3 SDRAM interface.
DQS, DQ, and DM Termination for Stratix III and Stratix IV FPGA
Similar to the scenario highlighted in “DQS, DQ, and DM for Stratix III and Stratix IV
FPGA” on page 2–14, the Stratix III and Stratix IV FPGA device is the receiver, the
Stratix III and Stratix IV I/O buffer is set to a 50- parallel termination, and the
memory is the transmitter. The difference between the setup in “DQS, DQ, and DM
for Stratix III and Stratix IV FPGA” on page 2–14 and the setup in this section is that
there is no series stub resistor on the DQS, DQ, and DM signals. DM is a
unidirectional signal, so the DDR3 SDRAM component is always the receiver. Refer to
“DQS, DQ, and DM for DDR3 SDRAM Components” on page 2–16 for receiver
termination recommendations and transmitter output drive strength settings.
Figure 2–21 illustrates the DDR3 SDRAM interface when the Stratix III and Stratix IV
FPGA device is reading from the DDR3 SDRAM using a 50- parallel OCT
termination on the Stratix III and Stratix IV FPGA device and the DDR3 SDRAM
driver output impedance is set to 34  without the series stub resistor of 15 .
Figure 2–21. DDR3 SDRAM Component Driving the Stratix III and Stratix IV FPGA Device with Parallel 50- OCT Turned On
Figure 2–22 shows a simulation of a read from the DDR3 SDRAM DIMM with a 50-
parallel OCT setting on the Stratix III or Stratix IV FPGA device.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–22
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–22. Read-Eye Diagram of a DDR3 SDRAM Component at the Stratix III and Stratix IV FPGA Using a Parallel 50-W
OCT Setting
Table 2–5 compares the effects of the series stub resistor on the eye diagram at the
Stratix III and Stratix IV FPGA (receiver) when the Stratix III or Stratix IV FPGA is
reading from the memory.
Table 2–5. Read-Eye Diagram with and without RS Using 50- Parallel OCT
ODT
Eye Height (V)
Eye Width (ps)
Overshoot (V)
Undershoot (V)
With RS
0.70
685
—
—
Without RS
0.73
724
—
—
Without the 15- stub series resistor to dampen the signal, the signal at the receiver of
the Stratix III and Stratix IV FPGA driven by the DDR3 SDRAM component is larger
than the signal at the receiver of the Stratix III and Stratix IV FPGA driven by DDR3
SDRAM DIMM (Figure 2–13), and similar to the write-eye diagram in “DQS, DQ, and
DM for DDR3 SDRAM Components” on page 2–16.
Memory Clocks Termination for Stratix III and Stratix IV FPGA
Memory clocks are unidirectional signals. Refer to “Memory Clocks for DDR3
SDRAM Components” on page 2–18 for receiver termination recommendations and
transmitter output drive strength settings.
Command and Address Termination for Stratix III and Stratix IV FPGA
Commands and addresses are unidirectional signals. Refer to “Commands and
Addresses for DDR3 SDRAM Components” on page 2–20 for receiver termination
recommendations and transmitter output drive strength setting.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (With Leveling)
2–23
Summary
This section discusses terminations used to achieve optimum performance for
designing the DDR3 SDRAM interface using discrete DDR3 SDRAM components.
Though you must include termination for unidirectional signals, the overall layout for
the DDR3 SDRAM interface using discrete DDR3 SDRAM components is easier
compared to DDR2 SDRAM interfaces using discrete DDR2 SDRAM components,
because of the fly-by daisy chain topology. To simplify your design processes, use the
DDR3 SDRAM unbuffered DIMM specification provided by JEDEC as your
guideline, because the trace length and termination values used in the DIMM
configuration provide excellent signal quality.
Layout Considerations (with Leveling)
This section discusses general layout guidelines for designing your DDR3 SDRAM
interface. These layout guidelines help you plan your board layout, but are not meant
as strict rules that must be adhered to. Altera recommends that you perform your
own board-level simulations to ensure that the layout you choose for your board
allows you to achieve your desired performance.
Trace Impedance
The layout of single-ended signal traces are to be 50  and the differential signal
traces are to be 100  with a  10% tolerance. Remove unused via pads as these cause
unwanted capacitance.
Decoupling
To minimize inductance, use 0.1 µF in 0402 size or smaller capacitors. Keep VTT
voltage decoupling close to the DDR3 SDRAM components and pull-up resistors.
Connect decoupling capacitors between VTT and ground using a 0.1 µF capacitor for
every other VTT pin. For VDD and VDDQ, use 0.1 µF and 0.01 µF capacitors for every VDD
and VDDQ pin.
Power
Route the ground, 1.5 V, and 0.75 V as planes. Route VCCIO for memories in a
single-split plane with at least a 20-mil (0.508 mm) gap of separation. Route VTT as
islands or 250-mil (6.35 mm) power traces. Route oscillators and PLL power as islands
or 100-mil (2.54 mm) power traces.
Maximum Trace Length
Maximum trace length for all signals from FPGA to first DIMM slot is 4.5 inches.
Maximum trace length for all signals from DIMM slot to DIMM slot is 0.425 inches.
When interfacing with multiple DDR3 SDRAM components, the maximum trace
length for address, command, control and clock from FPGA to first component is
maximum 7 inches, minimum of 3 inches.
Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to first component is
5 inches.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–24
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
General Routing Guidelines
Route using 45° angles and not 90° corners. Do not route critical signals across split
planes. Route over appropriate VCC and ground planes. Avoid routing memory
signals closer than 25-mil (0.635 mm) to the memory clocks. Keep the signal routing
layers close to ground and power planes. All specified delay matching requirements
include PCB trace delays, different layer propogation velocity variance, and crosstalk.
To minimise PCB layer propagation variance, Altera recommend that signals from the
same net group always be routed on the same layer.
Clock Routing Guidelines
Route clocks on inner layers with outer-layer run lengths held to under 500 mils
(12.7 mm).
■
10-mil spacing for parallel runs < 0.5 inches
(2× trace-to-plane distance)
■
15-mil spacing for parallel runs between 0.5 and 1.0 inches
(3× trace-to-plane distance)
■
20-mil spacing for parallel runs between 1 and 6 inches
(4× trace-to-plane distance)
Clocks must maintain a length matching between clock pairs of ±5 ps or
approximately ± 25 mils (0.635 mm). Differential clocks need to maintain length
matching between positive and negative signals of ±2 ps or approximately ± 10 mils
(0.254 mm), routed in parallel. The space between differential pairs must be at least 2×
the trace width of the differential pair to minimize loss and maximize interconnect
density. The maximum length from the first SDRAM to the last SDRAM must be no
more than 6 inches (approximately 153 mm) or 0.69 tCK, which is the same maximum
length for clocks specified by JEDEC for unbuffered DIMM. This maximum
clock-length specification is only valid for unbuffered DIMM. For other DIMM
configurations, check the necessary JEDEC specifications, as the maximum clock
length may be different. For example, JEDEC specifies the maximum clock length for
SODIMM to be 6.5 inches (approximately 166 mm).
For example, differential clocks must be routed differentially (5 mil trace width,
10-15 mil space on centers, and equal in length to signals in the Address/Command
Group). Take care with the via pattern used for clock traces. To avoid
transmission-line-to-via mismatches, Altera recommends that your clock via pattern
be a Ground-Signal-Signal-Ground (GSSG) topology (via topology:
GND | CLKP | CLKN | GND).
Address and Command Routing Guidelines
Similar to the clock signals in DDR3 SDRAM, address and command signals are
routed in a daisy chain topology from the first SDRAM to the last SDRAM. The
maximum length from the first DRAM to the last SDRAM must be no more than
6 inches (approximately 153 mm) or 0.69 tCK, which is the same maximum length for
clocks specified by JEDEC for unbuffered DIMMs. Ensure that each net maintains the
same consecutive order. Unbuffered DIMMs are more susceptible to crosstalk and are
generally noisier than buffered DIMMs. Route the address and command signals of
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (With Leveling)
2–25
unbuffered DIMMs on a different layer than DQ and DM, and with greater spacing.
Do not route differential clock and clock enable signals close to address signals. Route
all addresses and commands to match the clock signals to within ±25 ps or
approximately ± 125 mil (± 3.175 mm) to each discrete memory component.
Figure 2–23 shows the DDR3 SDRAM routing guidelines, where:
■
x = y ± 125 mil
■
x + x1 = y + y1 ± 125 mil
■
x + x1 + x2 = y + y1 + y2 ± 125 mil
Figure 2–23. DDR3 SDRAM Component Routing Guidelines
6 inches maximum
FPGA
x
clock
address and
command
y
x2
x1
DDR3 SDRAM
Component
y1
DDR3 SDRAM
Component
y2
VTT
x3
DDR3 SDRAM
Component
y3
DDR3 SDRAM
Component
VTT
DQ, DQS, and DM Routing Guidelines
All signals within a given byte-lane group must be matched in length with a
maximum deviation of ±10 ps or approximately ± 50 mils (± 1.27 mm). Ensure all
signals within a given byte lane group are routed on the same layer to aviod layer to
layer transmission velocity differences, which otherwise increase the skew within the
group. Keep the maximum byte-lane group-to-byte group matched length deviation
to ± 150 ps or ± 0.8 inches (± 20 mm).
Maintain all other signals to a spacing that is based on its parallelism with other nets:
■
5 mils for parallel runs < 0.5 inches (approximately 1× spacing relative to plane
distance)
■
10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2× spacing
relative to plane distance)
■
15 mils for parallel runs between 1.0 and 6.0 inches (approximately 3× spacing
relative to plane distance)
Figure 2–24 shows the DDR3 SDRAM components DQ, DQS, and DM guidelines,
where:
© November 2009
■
X > 2 + 0.5 + 0.125 inches
■
X < 2 + 0.5 – 0.125 inches
■
So, 2.375 inches < X < 2.625 inches
Altera Corporation
Board Layout Guidelines
Preliminary
2–26
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–24. DDR3 SDRAM Components DQ, DQS, DM Routing Guidelines
FPGA
2 inches
clock
address and
command
DQ Group 0
DQ Group 1
DQ Group 2
DQ Group 3
2 inches
VTT
0.5 inch
DDR3 SDRAM
Component
0.5 inch
DDR3 SDRAM
Component
DDR3 SDRAM
Component
DDR3 SDRAM
Component
VTT
2 inches
X inches
Do not use DDR3 deskew to correct for more than 20 ps of DQ group skew. The
deskew algorithm only removes the following possible uncertainties:
■
Minimum and maximum die IOE skew or delay mismatch
■
Minimum and maximum device package skew or mismatch
■
Board delay mismatch of 20 ps
■
Memory component DQ skew mismatch
Hence increasing any of these four parameters runs the risk of the deskew algorithm
limiting, failing to correct for the total observed system skew. If the algorithm cannot
compensate without limiting the correction, timing analysis shows reduced margins.
Termination
The previous sections use the combination of DDR3 SDRAM ODT and Stratix III and
Stratix IV Dynamic OCT for DQS, DQS#, DQ, and DM. This practise reduces the need
for external termination, and thus reduces both bill-of materials (BOM) cost and PCB
size.
When using DIMMs, you have no concerns about terminations on memory clocks,
addresses, and commands. If you are using components, use an external parallel
termination of 40  to VTT at the end of the fly-by daisy chain topology on the
addresses and commands. For memory clocks, use an external parallel termination of
75  differential at the end of the fly-by daisy chain topology on the memory clocks.
Using fly-by daisy chain topology helps reduce any stub reflection. Keep the length of
the traces to the termination to within 0.5 inch (14 mm). Use resistors with tolerances
of 1 to 2%.
Termination for DDR3 SDRAM Components (Without Leveling)
Altera support the use of DDR3 SDRAM components using a PHY without leveling.
To use the PHY without leveling, you should layout the DDR3 SDRAM components
on your PCB in a DDR2-like topology. Operating DDR3 SDRAM components without
leveling requires tighter layout rules and the use of more complex topologies. This
section discusses these termination and layout requirements.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (Without Leveling)
2–27
DDR3 SDRAM Components
This chapter describes how to implement the nonstandard DDR2-like balanced
(symmetrical) topology for command, address, and clock signals. Using this
alternative topology results in unwanted stubs on the address, command, and clock
signals, which degrades signal integrity and limits the performance of any DDR3
SDRAM interface.
DQS, DQ, and DM for DDR3 SDRAM Components
The DDR3 SDRAM PHY without leveling uses the same topology and termination
settings for the DQS, DQ and DM signals as the DDR3 SDRAM with leveling (refer to
“DQS, DQ, and DM for DDR3 SDRAM Components” on page 2–16). However, while
the topology and termination of these signals is identical, the layout rules differ,
because of the balanced command, address, and clock signals. DDR3 SDRAM without
leveling interfaces require much tighter DQ group to DQ group timing, refer to
“Layout Considerations (without Leveling)” on page 2–31.
Memory Clocks for DDR3 SDRAM Components
Memory clocks in a DDR3 SDRAM interface without leveling should follow the same
topology guidelines as a DDR2 SDRAM-type interface. However, SSTL15 type
signaling is used instead of SSTL18.
f
For more information, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive
Strength, Loading, and Board Layout Guidelines.
If your DDR3 SDRAM interface connects to a single component, you can use a simple
point-to-point topology a 100 differential terminator at the component end of the
line.
Most interfaces use two, four, or eight DDR3 SDRAM components, so you should use
a balanced T-type routing pattern, where all the trace segments are balanced for each
path. The total trace length to the first DDR3 SDRAM component is identical to that of
the last component, hence the trace delay for each component is the same, ensuring
matched timing while helping to control any reflections.
Differentially terminate clocks at the component end of the line with a 100  resistor.
For more than one DDR3 SDRAM component, split the clock using a balanced
T-topology. Place the 100  termination resistor at the first split in the T (refer to
Figure 2–25), or increase the resistor value and place a resistor at the end of each
segment at the DDR3 SDRAM component (refer to Figure 2–26). Typically two
segments require 200  resistors; and four segments require 400  resistors, but Altera
recommend that you simulate your specific topology to be ascertain the correct value.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–28
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Figure 2–25. Placement of the Termination Resistor—at First Split
CK
SDRAM
TL3
CK#
TL2
CK
FPGA
TL1
R = 100 Ω
CK#
TL2
CK
SDRAM
TL3
CK#
Figure 2–26. Placement of the Termination Resistor—End of Each Segment
CK
TL3
SDRAM
R = 200 Ω
CK#
TL2
CK
FPGA
TL1
CK#
TL2
CK
TL3
SDRAM
R = 200 Ω
CK#
Loading must not excessively degrade the slew rate of the memory clocks, so ideally a
single differential clock pair does not drive more than four components. If a single
clock pair drives eight or larger numbers of DDR3 SDRAM components, you must
perform setup and hold deration, to allow accurate timing analysis. Altera
recommend that you simulate any proposed topology before board completion, so
you can perform deration and final timing analysis. DDR3 setup and hold deration
may result in a lower than stated interface frequency to be achieved in any given
device or speed grade combination.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (Without Leveling)
2–29
Command and Address for DDR3 SDRAM Components
Command and address signals are similar to memory clocks in topology, so you
should use a balanced T-type routing pattern, where all the trace segments are
balanced for each path. The loading on the address and command signals is typically
larger with eight or sixteen loads not unusual. You should mimic the topologies that
Jedec uses on DDR2 unbuffered DIMM raw cards A to C, as these topologies provide
the best results.
Avoid topologies that Jedec uses on DDR2 unbuffered DIMM raw cards D, E, and F.
Raw card D topologies typically suffer from loading resonances, which reduce timing
margin. Additionally, raw cards E and F are not symmetrical balanced trees, as they
use a planar solution, which again can reduce timing margin.
Command and address signals should always be terminated with a 50  resistor to
VTT. Always place this single 50  resistor at the first split in the T (Figure 2–27).
Figure 2–27. Placing the 50- Resistor
Match each TL5 for each SDRAM
TL5
Second T.
Total length = TL3 + TL4
SDRAM
TL5
SDRAM
First T.
Total length = TL1 + TL2
TL4
TL3
TL5
TL4
TL2
Memory
Controller
SDRAM
TL5
SDRAM
TL1
TL6
TL5
SDRAM
TL2
TL5
SDRAM
TL4
TL3
TL5
TL4
SDRAM
TL5
SDRAM
Stratix III and Stratix IV FPGAs
The following sections describe the termination used on the DDR3 SDRAM
components interface side and the different termination features available in the
Stratix III and Stratix IV FPGAs when using a PHY without leveling, so that optimum
signal integrity can be achieved for your DDR3 SDRAM interface.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
VTT
2–30
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
DQS, DQ, and DM Termination for Stratix III Stratix IV FPGAs
It should be understood that the termination and topology for DQS, DQ, and DM
signals is identical. The choice of leveling or without leveling DDR3 SDRAM PHY
only affects the address, command, and clock termination schemes (refer to “DQS,
DQ, and DM for Stratix III and Stratix IV FPGA” on page 2–14).
Because of the different timing requirements, the layout (trace matching) constraints
for DQS, DQ, and DM do differ (refer to “Layout Considerations (without Leveling)”
on page 2–31).
Memory Clocks Termination for Stratix III and Stratix IV FPGA
Memory clocks are unidirectional signals. When using DDR3 SDRAM components
without leveling, mimic the termination and topology used for DDR2 SDRAM
components, substituting differential SSTL18 class I with differential SSTL15 class I.
f
For more information, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive
Strength, Loading, and Board Layout Guidelines.
Command and Address for Termination for Stratix III and Stratix IV FPGAs
Commands and addresses are unidirectional signals. When using DDR3 SDRAM
components without leveling, mimic the termination and topology used for DDR2
SDRAM components, substituting SSTL18 class I with SSTL15 class I.
f
For more information, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive
Strength, Loading, and Board Layout Guidelines.
Arria II GX FPGA
The following sections describe the termination used on the DDR3 SDRAM
components interface side and the different termination features available in the
Arria II GX devices when using a PHY without leveling, so that optimum signal
integrity can be achieved for your DDR3 SDRAM interface without leveling.
DDR3 SDRAM component interfaces without leveling are routed identically to DDR2
SDRAM interfaces without leveling, hence DDR2 SDRAM interface recommendations
apply.
DQS, DQ and DM Termination for Arria II GX FPGAs
The termination and topology and layout of DQS, DQ, and DM signals is identical if
DDR2 (differential DQS mode) is compared to DDR3 SDRAM.
DDR3 SDRAM without leveling on Arria II GX devices should be considered identical
to any DDR2 SDRAM components interface.
The memory end termination (Table 2–1 and Table 2–2) still applies. But you should
use the FPGA end termination settings from AN 408: DDR2 Memory Interface
Termination, Drive Strength, Loading, and Design Layout Guidelines.
As Arria II GX devices don't feature dynamic OCT, 50  parallel discrete termination
to VTT should be used at the FPGA end of the line.
f
For more information, refer to “Layout Considerations (without Leveling)” on
page 2–31.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Termination for DDR3 SDRAM Components (Without Leveling)
2–31
Memory Clocks Termination for Arria II GX FPGAs
Memory clocks are unidirectional signals. When using DDR3 SDRAM components
without leveling, mimic the termination and topology used for DDR2 SDRAM
components, substituting Differential SSTL18 Class I with Differential SSTL15 Class I.
f
For more information about component termination and FPGA drive strength
settings, refer to “Memory Clocks for DDR3 SDRAM Components” on page 2–18 and
Chapter 1, DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board
Layout Guidelines.
Command and Address for Termination for Arria II GX FPGAs
Commands and addresses are unidirectional signals. When using DDR3 SDRAM
components without leveling, mimic the termination and topology used for DDR2
SDRAM components, substituting Differential SSTL18 Class I with Differential
SSTL15 Class I.
f
For more information about component termination and FPGA drive strength
settings, refer to “Commands and Addresses for DDR3 SDRAM Components” on
page 2–20 and Chapter 1, DDR2 SDRAM Interface Termination, Drive Strength,
Loading, and Board Layout Guidelines.
Summary
This section discusses the I/O standards, drive strength, termination and topologies
to use so that you achieve optimum performance when designing with DDR3
SDRAM components without leveling. The topology is more challenging for
command, address, and clock signals, but it is no harder than the previous generation
DDR2 SDRAM interface, as the same requirements are used.
Layout Considerations (without Leveling)
This section discusses general layout guidelines for designing your DDR3 SDRAM
component without leveling interface. These guidelines help you plan your board
layout, but are not meant as strict rules that must be adhered to. Altera recommends
that you perform your own board-level simulations to ensure that your implemented
topology allows you to achieve your desired performance.
f
For more information, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive
Strength, Loading, and Board Layout Guidelines.
When mimicking DDR2 unbuffered DIMM JEDEC topologies, Altera recommends
that you use only raw cards A to C, as these are balanced symmetrical topologies and
result in the optimum performance. Raw cards D to F are not symmetrical and are
planar solutions, so should be avoided where possible.
When following DDR2 SDRAM component guidelines, the I/O standard for DDR3 is
SSTL15 and not SSTL18. DDR3 SDRAM components have enhanced ODT and output
drive strength features that you can use to improve the SI performance of a DDR3
SDRAM component without leveling solution, above that of a standard DDR2
implementation.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
2–32
Loading, and Board Layout Guidelines
1
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Altera's timing analysis assumes single-ranked DDR3 SDRAM designs only. Dual or
quad ranked designs require timing deration. For more information on multirank
topologies and layout guidelines, refer to Chapter 3, Dual-DIMM DDR2 and DDR3
SDRAM Interface Termination, Drive Strength, Loading, and Board Layout
Guidelines.
Conclusion
By using the new features of DDR3 SDRAM and the Stratix III and Stratix IV FPGAs,
you simplify your design process for DDR3 SDRAM. Using the fly-by daisy chain
topology increases the complexity of the datapath and controller design to achieve
leveling, but also greatly improves performance and eases board layout for DDR3
SDRAM.
DDR3 SDRAM components without leveling can also be used in an design when this
may result in a more optimal solution or for use with devices that support the
required electrical interface standard, but do not support the required read and write
leveling functionality.
By using Altera FPGAs and the DDR3 SDRAM ALTMEMPHY megafunction, you
simplify the datapath design and can take advantage of either the higher DDR3
SDRAM performance and straightforward board design in a design with leveling, or
the lower power and cost performance advantages of DDR3 SDRAM components in a
design without leveling.
References
This chapter references the following documents:
■
JEDEC Standard Publication JESD79-3A, DDR3 SDRAM Specification, JEDEC Solid
State Technology Association
■
External Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III
Device Handbook
■
Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook
■
External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV
Device Handbook
■
I/O Features in Stratix IV Devices chapter in volume 1 of the Stratix IV Device
Handbook
■
Micron Technical Note TN41-04: DDR3 Dynamic On-Die Termination Introduction
■
Micron Technical Note TN41-08: DDR3-1066 Memory Design Guide for Two-Dimm
Unbuffered Systems
■
TN-41-02 DDR3 ZQ Calibration, Micron
■
TN-41-04 DDR3 Dynamic On-Die Termination, Micron
■
TN47-06: Updated JEDEC DDR2 Specifications, Micron
■
TN47-17: DDR2 SODIMM Optimized Address/Command Nets, Micron
■
TN47-19: DDR2 (Point-to-Point) Features and Functionality, Micron
■
TN47-20: Point-to-Point Package Sizes and Layout Basics, Micron
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
References
© November 2009
2–33
■
Consumer Electronics are Changing the Face of DRAMs, Jody Defazio, Chip Design
Magazine, June 29, 2007
■
DDR3 ODT and Dynamic ODT, JEDEC DDR3 2007 Conference,
Oct 3-4, San Jose, CA.
■
PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Unbuffered DIMM Design
Specification, July 2007, JEDEC Solid State Technology Association
Altera Corporation
Board Layout Guidelines
Preliminary
2–34
Loading, and Board Layout Guidelines
Chapter 2: DDR3 SDRAM Interface Termination, Drive Strength,
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
3. Dual-DIMM DDR2 and DDR3 SDRAM
Interface Termination, Drive Strength,
Loading, and Board Layout Guidelines
This chapter describes guidelines for implementing dual-unbuffered DIMM DDR2
and DDR3 SDRAM interfaces. This chapter discusses the impact on signal integrity of
the data signal with the following conditions in a dual-DIMM configuration:
f
■
Populating just one slot versus populating both slots
■
Populating slot 1 versus slot 2 when only one DIMM is used
■
On-die termination (ODT) setting of 75  versus an ODT setting of 150 
For detailed information about a single-DIMM DDR2 SDRAM interface, refer to
Chapter 1, DDR2 SDRAM Interface Termination, Drive Strength, Loading, and Board
Layout Guidelines.
DDR2 SDRAM
This section describes guidelines for implementing a dual slot unbuffered DDR2
SDRAM interface, operating at up to 400-MHz and 800-Mbps data rates. Figure 3–1
shows a typical DQS, DQ, and DM signal topology for a dual-DIMM interface
configuration using the ODT feature of the DDR2 SDRAM components.
Figure 3–1. Dual-DIMM DDR2 SDRAM Interface Configuration (Note 1)
V TT
Board Trace
R T = 54Ω
DDR2 SDRAM
DIMMs
(Receiver)
Slot 1
FPGA
(Driver)
Slot 2
Board Trace
Board Trace
Note to Figure 3–1:
(1) The parallel termination resistor RT = 54  to VTT at the FPGA end of the line is optional for devices that support dynamic on-chip termination
(OCT).
The simulations in this section use a Stratix® II device-based board. Because of
limitations of this FPGA device family, simulations are limited to 266 MHz and 533
Mbps so that comparison to actual hardware results can be directly made.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–2
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Stratix II High Speed Board
To properly study the dual-DIMM DDR2 SDRAM interface, the simulation and
measurement setup evaluated in the following analysis features a Stratix II FPGA
interfacing with two 267-MHz DDR2 SDRAM unbuffered DIMMs. This DDR2
SDRAM interface is built on the Stratix II High-Speed High-Density Board
(Figure 3–2).
f
For more information about the Stratix II High-Speed High-Density Board, contact
your Altera representative.
Figure 3–2. Stratix II High-Speed Board with Dual-DIMM DDR2 SDRAM Interface
The Stratix II High-Speed Board uses a Stratix II 2S90F1508 device. For DQS, DQ, and
DM signals, the board is designed without external parallel termination resistors near
the DDR2 SDRAM DIMMs, to take advantage of the ODT feature of the DDR2
SDRAM components. Stratix II FPGA devices are not equipped with dynamic OCT, so
external parallel termination resistors are used at the FPGA end of the line.
Stratix III and Stratix IV devices, which support dynamic OCT, do not require FPGA
end parallel termination. Hence this discrete parallel termination is optional.
The DDR2 SDRAM DIMM contains a 22- external series termination resistor for
each data strobe and data line, so all the measurements and simulations need to
account for the effect of these series termination resistors.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–3
To correlate the bench measurements done on the Stratix II High Speed High Density
Board, the simulations are performed using HyperLynx LineSim Software with IBIS
models from Altera and memory vendors. Figure 3–3 is an example of the simulation
setup in HyperLynx used for the simulation.
Figure 3–3. HyperLynx Setup for Simulating the Stratix II High Speed High Density with Dual-DIMM DDR2 SDRAM Interface
Overview of ODT Control
When there is only a single-DIMM on the board, the ODT control is relatively
straightforward. During write to the memory, the ODT feature of the memory is
turned on; during read from the memory, the ODT feature of the memory is turned
off. However, when there are multiple DIMMs on the board, the ODT control becomes
more complicated.
With a dual-DIMM interface on the system, the controller has different options for
turning the memory ODT on or off during read or write. Table 3–1 shows the DDR2
SDRAM ODT control during write to the memory; Table 3–2 during read from the
memory. These DDR2 SDRAM ODT controls are recommended by Samsung
Electronics. The JEDEC DDR2 specification was updated to include optional support
for RTT(nominal) = 50 .
f
© November 2009
For more information about the DDR2 SDRAM ODT controls recommended by
Samsung, refer to the Samsung DDR2 Application Note: ODT (On Die Termination)
Control.
Altera Corporation
Board Layout Guidelines
Preliminary
3–4
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Table 3–1. DDR2 SDRAM ODT Control—Writes (Note 1)
Module in Slot 1
Slot 1 (2) Slot 2 (2)
Write
To
FPGA
Rank 1
Series 50 
Infinite
Slot 2
Series 50 
75 or 50 
Slot 1
Series 50 
Infinite
Slot 2
Series 50 
75 or 50 
DR
DR
Slot 1
SR
SR
Rank 2
Module in Slot 2
Rank 3
Rank 4
75 or 50 
Infinite
Infinite
Infinite
infinite
Unpopulated
75 or 50 
Unpopulated
Unpopulated
Infinite
Unpopulated
Infinite
DR
Empty
Slot 1
Series 50 
150 
Infinite
Unpopulated
Unpopulated
Empty
DR
Slot 2
Series 50 
Unpopulated
Unpopulated
150 
Infinite
SR
Empty
Slot 1
Series 50 
150 
Unpopulated
Unpopulated
Unpopulated
Empty
SR
Slot 2
Series 50 
Unpopulated
Unpopulated
150 
Unpopulated
Note to Table 3–1:
(1) For DDR2 at 400 MHz and 533 Mbps = 75 ; for DDR2 at 667 MHz and 800 Mbps = 50 .
(2) SR = single ranked; DR i= dual ranked.
Table 3–2. DDR2 SDRAM ODT Control—Reads (Note 1)
Module in Slot 1
Slot 1 (2) Slot 2 (2)
DR
SR
DR
SR
Read
From
FPGA
Rank 1
Rank 2
Module in Slot 2
Rank 3
Rank 4
Slot 1
Parallel 50 
Infinite
Infinite
75 or 50 
Infinite
Slot 2
Parallel 50 
75 or 50 
Infinite
Infinite
Infinite
Slot 1
Parallel 50 
Infinite
Unpopulated
75 or 50 
Unpopulated
Slot 2
Parallel 50 
75 or 50 
Unpopulated
Infinite
Unpopulated
Unpopulated
Unpopulated
DR
Empty
Slot 1
Parallel 50 
Infinite
Infinite
Empty
DR
Slot 2
Parallel 50 
Unpopulated
Unpopulated
Infinite
Infinite
SR
Empty
Slot 1
Parallel 50 
Infinite
Unpopulated
Unpopulated
Unpopulated
Empty
SR
Slot 2
Parallel 50 
Unpopulated
Unpopulated
Infinite
Unpopulated
Note to Table 3–1:
(1) For DDR2 at 400 MHz and 533 Mbps = 75 ; for DDR2 at 667 MHz and 800 Mbps = 50 .
(2) SR = single ranked; DR i= dual ranked.
A 54- external parallel termination resistor is placed on all the data strobes and data
lines near the Stratix II device on the Stratix II High Speed High Density Board.
Although the characteristic impedance of the transmission is designed for 50 , to
account for any process variation, it is advisable to underterminate the termination
seen at the receiver. This is why the termination resistors at the FPGA side use 54-
resistors.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–5
DIMM Configuration
While populating both memory slots is common in a dual-DIMM memory system,
there are some instances when only one slot is populated. For example, some systems
are designed to have a certain amount of memory initially and as applications get
more complex, the system can be easily upgraded to accommodate more memory by
populating the second memory slot without re-designing the system. The following
section discusses a dual-DIMM system where the dual-DIMM system only has one
slot populated at one time and a dual-DIMM system where both slots are populated.
ODT controls recommended by the memory vendors listed in Table 3–1 as well as
other possible ODT settings will be evaluated for usefulness in an FPGA system.
Dual-DIMM Memory Interface with Slot 1 Populated
This section focuses on a dual-DIMM memory interface where slot 1 is populated and
slot 2 is unpopulated. This section examines the impact on the signal quality due to an
unpopulated DIMM slot and compares it to a single-DIMM memory interface.
FPGA Writing to Memory
In the DDR2 SDRAM, the ODT feature has two settings: 150  and 75 . In Table 3–1,
the recommended ODT setting for a dual DIMM configuration with one slot occupied
is 150 .
1
f
On DDR2 SDRAM devices running at 333 MHz/667 Mbps and above, the ODT
feature supports an additional setting of 50 .
Refer to the respective memory decathlete for additional information about the ODT
settings in DDR2 SDRAM devices.
Write to Memory Using an ODT Setting of 150
Figure 3–4 shows a double parallel termination scheme (Class II) using ODT on the
memory with a memory-side series resistor when the FPGA is writing to the memory
using a 25- OCT drive strength setting on the FPGA.
Figure 3–4. Double Parallel Termination Scheme (Class II) Using ODT on DDR2 SDRAM DIMM with Memory-Side Series
Resistor
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
RT= 54Ω
300Ω/
150Ω
RS = 22Ω
Receiver
VREF
© November 2009
Receiver
50Ω
3" Trace Length
Altera Corporation
VREF = 0.9V
300Ω/
150Ω
Board Layout Guidelines
Preliminary
3–6
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–5 shows a HyperLynx simulation and board measurement of a signal at the
memory of a double parallel termination using ODT 150  with a memory-side series
resistor transmission line when the FPGA is writing to the memory with a 25- OCT
drive strength setting.
Figure 3–5. HyperLynx Simulation and Board Measurement of the Signal at the Memory in Slot 1 with Slot 2 Unpopulated
Table 3–3 summarizes the comparison between the simulation and board
measurements of the signal at the memory of a single-DIMM and a dual-DIMM
memory interface with slot 1 populated using a double parallel termination using an
ODT setting of 150  with a memory-side series resistor with a 25- OCT strength
setting on the FPGA.
Table 3–3. Comparison of Signal at the Memory of a Single-DIMM and a Dual-DIMM Interface with Slot 1 Populated
(Note 1)
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM memory interface with slot 1 populated
Simulation
1.68
0.97
0.06
NA
2.08
1.96
Measurements
1.30
0.63
0.22
0.20
1.74
1.82
Simulation
1.62
0.94
0.10
0.05
2.46
2.46
Measurements
1.34
0.77
0.04
0.13
1.56
1.39
Single-DIMM
Note to Table 3–3:
(1) The simulation and board measurements of the single-DIMM DDR2 SDRAM interface are based on the Stratix II Memory Board 2. For more
information about the single-DIMM DDR2 SDRAM interface, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive Strength, Loading,
and Board Layout Guidelines.
Table 3–3 indicates that there is not much difference between a single-DIMM memory
interface or a dual-DIMM memory interface with slot 1 populated. The over and
undershooting observed in both the simulations and board measurements can be
attributed to the use of the ODT setting of 150  on the memory resulting in
over-termination at the receiver. In addition, there is no significant effect of the extra
DIMM connector due to the unpopulated slot.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–7
When the ODT setting is set to 75 , there is no difference in the eye width and height
compared to the ODT setting of 150 . However, there is no overshoot and
undershoot when the ODT setting is set to 75 , which is attributed to proper
termination resulting in matched impedance seen by the DDR2 SDRAM devices.
1
For information about results obtained from using an ODT setting of 75  refer to
page 3–24.
Reading from Memory
During read from the memory, the ODT feature is turned off. Thus, there is no
difference between using an ODT setting of 150  and 75 . As such, the termination
scheme becomes a single parallel termination scheme (Class I) where there is an
external resistor on the FPGA side and a series resistor on the memory side as shown
in Figure 3–6.
Figure 3–6. Single Parallel Termination Scheme (Class I) Using External Resistor and Memory-Side Series Resistor
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
300Ω/
150Ω
RT= 54Ω
RS = 22Ω
Receiver
Receiver
50Ω
VREF = 0.9V
3" Trace Length
VREF
300Ω/
150Ω
Figure 3–7 shows the simulation and board measurement of the signal at the FPGA of
a single parallel termination using an external parallel resistor on the FPGA side with
a memory-side series resistor with full drive strength setting on the memory.
Figure 3–7. HyperLynx Simulation and Board Measurement of the Signal at the FPGA When Reading From Slot 1 With Slot 2
Unpopulated
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–8
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Table 3–4 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a single-DIMM and a dual-DIMM
memory interface with a slot 1 populated memory interface using a single parallel
termination using an external parallel resistor at the FPGA with a memory-side series
resistor with full strength setting on the memory.
Table 3–4. Comparison of Signal at the FPGA of a Dual-DIMM Memory Interface with Slot 1 Populated (Note 1)
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM memory interface with slot 1 populated
Simulation
1.76
0.80
NA
NA
2.29
2.29
Measurements
1.08
0.59
NA
NA
1.14
1.59
Simulation
1.80
0.95
NA
NA
2.67
2.46
Measurements
1.03
0.58
NA
NA
1.10
1.30
Single-DIMM1
Note to Table 3–4:
(1) The simulation and board measurements of the single-DIMM DDR2 SDRAM interface are based on the Stratix II Memory Board 2. For more
information about the single-DIMM DDR2 SDRAM interface, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive Strength, Loading,
and Board Layout Guidelines,
Table 3–4 demonstrates that there is not much difference between a single-DIMM
memory interface or a dual-DIMM memory interface with only slot 1 populated.
There is no significant effect of the extra DIMM connector due to the unpopulated
slot.
Dual-DIMM with Slot 2 Populated
This section focuses on a dual-DIMM memory interface where slot 2 is populated and
slot 1 is unpopulated. Specifically, this section discusses the impact of location of the
DIMM on the signal quality.
FPGA Writing to Memory
The previous section focused on the dual-DIMM memory interface where slot 1 is
populated resulting in the memory being located closer to the FPGA. When slot 2 is
populated, the memory is located further away from the FPGA, resulting in
additional trace length that potentially affects the signal quality seen by the memory.
The next section explores if there are any differences between populating slot 1 and
slot 2 of the dual-DIMM memory interface.
Write to Memory Using an ODT Setting of 150
Figure 3–8 shows the double parallel termination scheme (Class II) using ODT on the
memory with the memory-side series resistor when the FPGA is writing to the
memory using a 25- OCT drive strength setting on the FPGA.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–9
Figure 3–8. Double Parallel Termination Scheme (Class II) Using ODT on DDR2 SDRAM DIMM with Memory-side Series
Resistor
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
RT= 54Ω
300Ω/
150Ω
RS = 22Ω
Receiver
Receiver
50Ω
3" Trace Length
VREF
VREF = 0.9V
300Ω/
150Ω
Figure 3–9 shows the simulation and board measurement of the signal at the memory
of a double parallel termination using an ODT setting of 150  with a memory-side
series resistor transmission line when the FPGA is writing to the memory with a 25-
OCT drive strength setting.
Figure 3–9. HyperLynx Simulation and Board Measurement of the Signal at the Memory in Slot 2 With Slot 1 Unpopulated
Table 3–5 summarizes the comparison between the simulation and board
measurements of the signal seen at the DDR2 SDRAM DIMM of a dual-DIMM
memory interface with either only slot 1 populated or only slot 2 populated using a
double parallel termination using an ODT setting of 150  with a memory-side series
resistor with a 25- OCT strength setting on the FPGA.
Table 3–5. Comparison of Signal at the Memory of a Dual-DIMM Interface with Either Only Slot 1 Populated or Only Slot 2
Populated (Part 1 of 2)
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM memory interface with slot 2 populated
Simulation
1.69
0.94
0.07
0.02
1.96
2.08
Measurements
1.28
0.68
0.24
0.20
1.60
1.60
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–10
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Table 3–5. Comparison of Signal at the Memory of a Dual-DIMM Interface with Either Only Slot 1 Populated or Only Slot 2
Populated (Part 2 of 2)
Eye Width
(ns)
Type
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM memory interface with slot 1 populated
Simulation
1.68
0.97
0.06
NA
2.08
2.08
Measurements
1.30
0.63
0.22
0.20
1.74
1.82
Table 3–5 shows that there is not much difference between populating slot 1 or slot 2
in a dual-DIMM memory interface. The over and undershooting observed in both the
simulations and board measurements can be attributed to the use of the ODT setting
of 150  on the memory, resulting in under-termination at the receiver.
When the ODT setting is set to 75 , there is no difference in the eye width and height
compared to the ODT setting of 150 . However, there is no overshoot and
undershoot when the ODT setting is set to 75 , which is attributed to proper
termination resulting in matched impedance seen by the DDR2 SDRAM devices.
f
For detailed results for the ODT setting of 75 , refer to page 3–25.
Reading from Memory
During read from memory, the ODT feature is turned off, thus there is no difference
between using an ODT setting of 150  and 75 . As such, the termination scheme
becomes a single parallel termination scheme (Class I) where there is an external
resistor on the FPGA side and a series resistor on the memory side, as shown in
Figure 3–10.
Figure 3–10. Single Parallel Termination Scheme (Class I) Using External Resistor and Memory-Side Series Resistor
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
300Ω/
150Ω
RT= 54Ω
RS = 22Ω
Receiver
Receiver
50Ω
VREF = 0.9V
3" Trace Length
VREF
300Ω/
150Ω
Figure 3–11 shows the simulation and board measurement of the signal at the FPGA
of a single parallel termination using an external parallel resistor on the FPGA side
with a memory-side series resistor with full drive strength setting on the memory.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–11
Figure 3–11. HyperLynx Simulation and Board Measurement of the Signal at the FPGA When Reading From Slot 2 With Slot
1 Unpopulated
Table 3–6 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a dual-DIMM memory interface with
either slot 1 or slot 2 populated using a single parallel termination using an external
parallel resistor at the FPGA with a memory-side series resistor with full strength
setting on the memory.
Table 3–6. Comparison of the Signal at the FPGA of a Dual-DIMM Memory Interface with Either Slot 1 or Slot 2 Populated
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Simulation
1.80
0.80
NA
NA
3.09
2.57
Measurements
1.17
0.66
NA
NA
1.25
1.54
Simulation
1.80
0.95
NA
NA
2.67
2.46
Measurements
1.08
0.59
NA
NA
1.14
1.59
Type
Slot 2 populated
Slot 1 populated
From Table 3–6, you can see the signal seen at the FPGA is similar whether the
memory DIMM is located at either slot 1 or slot 2.
Dual-DIMM Memory Interface with Both Slot 1 and Slot 2 Populated
This section focuses on a dual-DIMM memory interface where both slot 1 and slot 2
are populated. As such, you can write to either the memory in slot 1 or the memory in
slot 2.
FPGA Writing to Memory
In Table 3–1, the recommended ODT setting for a dual DIMM configuration with both
slots occupied is 75 . Since there is an option for an ODT setting of 150 , this section
explores the usage of the 150  setting and compares the results to that of the
recommended 75 .
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–12
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Write to Memory in Slot 1 Using an ODT Setting of 75-
Figure 3–12 shows the double parallel termination scheme (Class II) using ODT on the
memory with the memory-side series resistor when the FPGA is writing to the
memory using a 25- OCT drive strength setting on the FPGA. In this scenario, the
FPGA is writing to the memory in slot 1 and the ODT feature of the memory at slot 2
is turned on.
Figure 3–12. Double Parallel Termination Scheme (Class II) Using ODT on DDR2 SDRAM DIMM with a Memory-Side Series
Resistor
Slot 1
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
RT= 54Ω
300Ω/
150Ω
RS = 22Ω
Receiver
Receiver
50Ω
3" Trace Length
VREF
300Ω/
150Ω
Slot 2
50Ω
VREF
DDR2 DIMM
DDR2 Component
Driver
300Ω/
150Ω
RS = 22Ω
Receiver
VREF = 0.9V
300Ω/
150Ω
Figure 3–13 shows a HyperLynx simulation and board measurement of the signal at
the memory in slot 1 of a double parallel termination using an ODT setting of 75 
with a memory-side series resistor transmission line when the FPGA is writing to the
memory with a 25- OCT drive strength setting.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–13
Figure 3–13. HyperLynx Simulation and Board Measurements of the Signal at the Memory in Slot 1 with Both Slots
Populated
Table 3–7 summarizes the comparison of the signal at the memory of a dual-DIMM
memory interface with one slot and with both slots populated using a double parallel
termination using an ODT setting of 75  with a memory-side series resistor with a
25- OCT strength setting on the FPGA.
Table 3–7. Comparison of the Signal at the Memory of a Dual-DIMM Interface With One Slot and With Both Slots Populated
Eye Width
(ns)
Type
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM interface with both slots populated writing to slot 1
Simulation
1.60
1.18
0.02
NA
1.71
1.71
Measurements
0.97
0.77
0.05
0.04
1.25
1.25
Dual-DIMM interface with slot 1 populated
Simulation
1.68
0.97
0.06
NA
2.08
2.08
Measurements
1.30
0.63
0.22
0.20
1.74
1.82
Table 3–7 shows that there is not much difference in the eye height between
populating one slot or both slots. However, the additional loading due to the
additional memory DIMM results in a slower edge rate, which results in smaller eye
width and degrades the setup and hold time of the memory. This reduces the
available data valid window.
When the ODT setting is set to 150 , there is no difference in the eye width and
height compared to the ODT setting of 75 . However, there is some overshoot and
undershoot when the ODT setting is set to 150 , which is attributed to under
termination resulting in mismatched impedance seen by the DDR2 SDRAM devices.
1
© November 2009
For more information about the results obtained from using an ODT setting of 150 ,
refer to page 3–26.
Altera Corporation
Board Layout Guidelines
Preliminary
3–14
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Write to Memory in Slot 2 Using an ODT Setting of 75-
In this scenario, the FPGA is writing to the memory in slot 2 and the ODT feature of
the memory at slot 1 is turned on. Figure 3–14 shows the HyperLynx simulation and
board measurement of the signal at the memory in slot 1 of a double parallel
termination using an ODT setting of 75  with a memory-side series resistor
transmission line when the FPGA is writing to the memory with a 25- OCT drive
strength setting.
Figure 3–14. HyperLynx Simulation and Board Measurements of the Signal at the Memory in Slot 2 With Both Slots
Populated
Table 3–8 summarizes the comparison of the signal at the memory of a dual-DIMM
memory interface with slot 1 populated using a double parallel termination using an
ODT setting of 75  with a memory-side series resistor with a 25- OCT strength
setting on the FPGA.
Table 3–8. Comparison of the Signal at the Memory of a Dual-DIMM Interface With Both Slots Populated
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rise Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM interface with both slots populated writing to slot 2
Simulation
1.60
1.16
0.10
0.08
1.68
1.60
Measurements
1.10
0.85
0.16
0.19
1.11
1.25
Dual-DIMM interface with both slots populated writing to slot 1
Simulation
1.60
1.18
0.02
NA
1.71
1.71
Measurements
1.30
0.77
0.05
0.04
1.25
1.25
From Table 3–8, you can see that both simulations and board measurements
demonstrate that the eye width is larger when writing to slot 1, which is due to better
edge rate seen when writing to slot 1. The improvement on the eye when writing to
slot 1 can be attributed to the location of the termination. When you are writing to slot
1, the ODT feature of slot 2 is turned on, resulting in a fly-by topology. When you are
writing to slot 2, the ODT feature of slot 1 is turned on resulting in a non fly-by
topology.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–15
When the ODT setting is set to 150 , there is no difference in the eye width and
height compared to the ODT setting of 75 . However, there is some overshoot and
undershoot when the ODT setting is set to 150 , which is attributed to under
termination resulting in mismatched impedance seen by the DDR2 SDRAM devices.
1
For more information about the results obtained from using an ODT setting of 150 ,
refer to “Write to Memory in Slot 2 Using an ODT Setting of 150  With Both Slots
Populated” on page 3–27.
Reading From Memory
In Table 3–1, the recommended ODT setting for a dual-DIMM configuration with both
slots occupied is to turn on the ODT feature using a setting of 75  on the slot that is
not read from. Since there is an option for an ODT setting of 150 , this section
explores the usage of the 150  setting and compares the results to that of the
recommended 75 .
Read From Memory in Slot 1 Using an ODT Setting of 75- on Slot 2
Figure 3–15 shows the double parallel termination scheme (Class II) using ODT on the
memory with the memory-side series resistor when the FPGA is reading from the
memory using a full drive strength setting on the memory. In this scenario, the FPGA
is reading from the memory in slot 1 and the ODT feature of the memory at slot 2 is
turned on.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–16
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–15. Double Parallel Termination Scheme (Class II) Using External Resistor and Memory-Side Series Resistor and
ODT Feature Turned On
Slot 1
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
Driver
25Ω
RT= 54Ω
300Ω/
150Ω
RS = 22Ω
Receiver
Receiver
50Ω
3" Trace Length
VREF
300Ω/
150Ω
Slot 2
50Ω
VREF
DDR2 DIMM
DDR2 Component
Driver
300Ω/
150Ω
RS = 22Ω
VREF
Receiver
300Ω/
150Ω
Figure 3–16 shows the simulation and board measurement of the signal at the FPGA
when the FPGA is reading from the memory in slot 1 using a full drive strength
setting on the memory.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–17
Figure 3–16. HyperLynx Simulation and Board Measurement of the Signal at the FPGA When Reading From Slot 1 With Both
Slots Populated (Note 1)
Note to Figure 3–16:
(1) The vertical scale used for the simulation and measurement is set to 200 mV per division.
Table 3–9 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a dual-DIMM memory interface with
both slots populated and a dual-DIMM memory interface with a slot 1 populated
memory interface.
Table 3–9. Comparison of the Signal at the FPGA of a Dual-DIMM Interface Reading From Slot 1 With One Slot and With Both
Slots Populated
Eye Width
(ns)
Type
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM with one slot populated with an ODT setting of 75- on slot 2
Simulation
1.74
0.87
NA
NA
1.91
1.88
Measurements
0.86
0.58
NA
NA
1.11
1.09
Dual-DIMM with one slot populated in slot 1 without ODT setting
Simulation
1.76
0.80
NA
NA
2.29
2.29
Measurements
1.08
0.59
NA
NA
1.14
1.59
Table 3–9 shows that when both slots are populated, the additional loading due to the
additional memory DIMM results in a slower edge rate, which results in a
degradation in the eye width.
1
For more information about the results obtained from using an ODT setting of 150 ,
refer to “Read from Memory in Slot 1 Using an ODT Setting of 150  on Slot 2 with
Both Slots Populated” on page 3–28.
Read From Memory in Slot 2 Using an ODT Setting of 75- on Slot 1
In this scenario, the FPGA is reading from the memory in slot 2 and the ODT feature
of the memory at slot 1 is turned on.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–18
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–17. Double Parallel Termination Scheme (Class II) Using External Resistor and a Memory-Side Series Resistor and
ODT Feature Turned On
Slot 1
FPGA
DDR2 DIMM
VTT = 0.9V
DDR2 Component
Driver
25Ω
Driver
RT= 54Ω
RS = 22Ω
Receiver
150Ω/
300Ω
Receiver
50Ω
3" Trace Length
VREF
150Ω/
300Ω
Slot 2
50Ω
VREF = 0.9V
DDR2 DIMM
DDR2 Component
Driver
150Ω/
300Ω
RS = 22Ω
VREF
Receiver
150Ω/
300Ω
Figure 3–18 shows the HyperLynx simulation and board measurement of the signal at
the FPGA of a double parallel termination using an external parallel resistor on the
FPGA side with a memory-side series resistor and an ODT setting of 75  with a full
drive strength setting on the memory.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–19
Figure 3–18. HyperLynx Simulation and Board Measurements of the Signal at the FPGA When Reading From Slot 2 With
Both Slots Populated (Note 1)
Notes to Figure 3–18:
(1) The vertical scale used for the simulation and measurement is set to 200 mV per division.
Table 3–10 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a dual-DIMM memory interface with
both slots populated and a dual-DIMM memory interface with a slot 1 populated
memory interface.
Table 3–10. Comparison of the Signal at the FPGA of a Dual-DIMM Interface Reading From Slot 2 With One Slot and With
Both Slots Populated
Eye Width
(ns)
Type
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
Dual-DIMM with both slots populated with an ODT setting of 75- setting on slot 1
Simulation
1.70
0.81
NA
NA
1.72
1.99
Measurements
0.87
0.59
NA
NA
1.09
1.14
Dual-DIMM with one slot populated in slot 2 without an ODT setting
Simulation
1.80
0.80
NA
NA
3.09
2.57
Measurements
1.17
0.66
NA
NA
1.25
1.54
Table 3–10 shows that when only one slot is populated in a dual-DIMM memory
interface, the eye width is larger as compared to a dual-DIMM memory interface with
both slots populated. This can be attributed to the loading from the DIMM located in
slot 1.
When the ODT setting is set to 150 , there is no difference in the signal quality
compared to the ODT setting of 75 .
1
© November 2009
For more information about the results obtained from using an ODT setting of 150  ,
refer to “Read From Memory in Slot 2 Using an ODT Setting of 150  on Slot 1 With
Both Slots Populated” on page 3–29.
Altera Corporation
Board Layout Guidelines
Preliminary
3–20
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
FPGA OCT Features
Many FPGA devices offer OCT. Depending on the chosen device family, series
(output), parallel (input) or dynamic (bidirectional) OCT may be supported.
f
For more information specific to your device family, refer to the respective I/O
features chapter in the relevant device handbook.
Use series OCT in place of the near-end series terminator typically used in both Class
I or Class II termination schemes that both DDR2 and DDR3 type interfaces use.
Use parallel OCT in place of the far-end parallel termination typically used in Class I
termination schemes on unidirectional input only interfaces. For example, QDR
II-type interfaces, when the FPGA is at the far end.
Use dynamic OCT in place of both the series and parallel termination at the FPGA end
of the line. Typically use dynamic OCT for DQ and DQS signals in both DDR2 and
DDR3 type interfaces. As the parallel termination is dynamically disabled during
writes, the FPGA driver only ever drives into a Class I transmission line. When
combined with dynamic ODT at the memory, a truly dynamic Class I termination
scheme exists where both reads and writes are always fully Class I terminated in each
direction. Hence, you can use a fully dynamic bidirectional Class I termination
scheme instead of a static discretely terminated Class II topology, which saves power,
PCB real estate, and component cost.
Stratix III and Stratix IV Devices
Stratix III and Stratix IV devices feature full dynamic OCT termination capability,
Altera advise that you use this feature combined with the SDRAM ODT to simplify
PCB layout and save power.
Arria II GX Devices
Arria II GX devices do not support dynamic OCT. Altera recommend that you use
series OCT with SDRAM ODT. Use parallel discrete termination at the FPGA end of
the line when necessary,
f
For more information, refer to Chapter 1, DDR2 SDRAM Interface Termination, Drive
Strength, Loading, and Board Layout Guidelines.
Dual-DIMM DDR2 Clock, Address, and Command Termination and Topology
The address and command signals on a DDR2 SDRAM interface are unidirectional
signals that the FPGA memory controller drives to the DIMM slots. These signals are
always Class-I terminated at the memory end of the line (Figure 3–19). Always place
DDR2 SDRAM address and command Class-I termination after the last DIMM. The
interface can have one or two DIMMs, but never more than two DIMMs total.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR2 SDRAM
3–21
Figure 3–19. Multi DIMM DDR2 Address and Command Termination Topology
V TT
DDR2 SDRAM
DIMMs
(Receiver)
Slot 1
FPGA
(Driver)
Board Trace C
R P = 47 
Slot 2
Board Trace B
Board Trace A
In Figure 3–19, observe the following points:
■
Board trace A = 1.9 to 4.5 inches (48 to 115 mm)
■
Board trace B = 0.425 inches (10.795 mm)
■
Board trace C = 0.2 to 0.55 inches (5 to 13 mm)
■
Total of board trace A + B + C = 2.5 to 5 inches (63 to 127 mm)
■
RP = 36 to 56 
■
Length match all address and command signals to +250 mils (+5 mm) or +/– 50 ps
of memory clock length at the DIMM.
You may place a compensation capacitor directly before the first DIMM slot 1 to
improve signal quality on the address and command signal group. If you fit a
capacitor, Altera recommend a value of 24 pF.
f
For more information, refer to Micron TN47-01.
Address and Command Signals
The address and command group of signals: bank address, address, RAS#, CAS#, and
WE# operate a different toggle rate depending on whether a you implement a full-rate
or half-rate memory controller.
In full-rate designs, the address and command group of signals are 1T signals, which
means that the signals can change every memory clock cycle. Address and command
signals are also single data rate (SDR). Hence in a full-rate PHY design, the address
and command signals operate at a maximum frequency of 0.5 × the data rate. For
example in a 266-MHz full rate design, the maximum address and command
frequency is 133 MHz.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–22
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
In half-rate designs the address and command group of signals are 2T signals, which
means that the signals change only every two memory clock cycles. As the signals are
also SDR, in a half-rate PHY design, the address and command signals operate at a
maximum frequency of 0.25 × the data rate. For example, in a 400-MHz half-rate
design, the maximum address and command frequency is 100 MHz.
Control Group Signals
The control group of signals: chip select CS#, clock enable CKE, and ODT are always
1T regardless of whether you implement a full-rate or half-rate design. As the signals
are also SDR, the control group signals operate at a maximum frequency of 0.5 × the
data rate. For example, in a 400-MHz design, the maximum control group frequency
is 200 MHz.
Clock Group Signals
Depending on the specific form factor, DDR2 SDRAM DIMMs have two or three
differential clock pairs, to ensure that the loading on the clock signals is not excessive.
The clock signals are always terminated on the DIMMs and hence no termination is
required on your PCB. Additionally, each DIMM slot is required to have its own
dedicated set of clock signals. Hence clock signals are always point-to-point from the
FPGA PHY to each individual DIMM slot. Individual memory clock signals should
never be shared between two DIMM slots.
A typical two slot DDR2 DIMM design therefore has six differential memory clock
pairs—three to the first DIMM and three to the second DIMM. All six memory clock
pairs must be delay matched to each other to ±25 mils (±0.635 mm) and ±10 mils
(±0.254 mm) for each CLK to CLK# signal.
You may place a compensation capacitor between each clock pair directly before the
DIMM connector, to improve the clock slew rates. As FPGA devices have fully
programmable drive strength and slew rate options, this capacitor is usually not
required for FPGA design. However, Altera advise that you simulate your specific
implementation to ascertain if this capacitor is required or not. If fitted the best value
is typically 5 pF.
DDR3 SDRAM
This section details the system implementation of a dual slot unbuffered DDR3
SDRAM interface, operating at up to 400 MHz and 800 Mbps data rates. Figure 3–20
shows a typical DQS, DQ, and DM, and address and command signal topology for a
dual-DIMM interface configuration, using the on-die termination (ODT) feature of the
DDR3 SDRAM components combined with the dynamic OCT features available in
Stratix III and Stratix IV devices.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
DDR3 SDRAM
3–23
Figure 3–20. Multi DIMM DDR3 DQS, DQ, and DM, and Address and Command Termination Topology
DDR3 SDRAM
DIMMs
Slot 1
FPGA
(Driver)
Board Trace A
Slot 2
Board Trace B
In Figure 3–20, observe the following points:
■
Board trace A = 1.9 to 4.5 inches (48 to 115 mm)
■
Board trace B = 0.425 inches (10.795 mm)
■
This topology to both DIMMs is accurate for DQS, DQ, and DM, and address and
command signals
■
This topology is not correct for CLK and CLK# and control group signals (CS#,
CKE, and ODT), which are always point-to-point single rank only.
Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology
DDR3 and DDR2 SDRAM systems are quite similar. The physical topology of the data
group of signals may be considered nearly identical. The FPGA end (driver) I/O
standard changes from SSTL18 for DDR2 to SSTL15 for DDR3, but all other OCT
settings are identical. DDR3 offers enhanced ODT options for termination and
drive-strength settings at the memory end of the line.
f
For more information, refer to the DDR3 SDRAM ODT matrix for writes and the
DDR3 SDRAM ODT matrix for reads tables in Chapter 2, DDR3 SDRAM Interface
Termination, Drive Strength, Loading, and Board Layout Guidelines.
Dual-DIMM DDR3 Clock, Address, and Command Termination and Topology
One significant difference between DDR3 and DDR2 DIMM based interfaces is the
address, command and clock signals. DDR3 uses a daisy chained based architecture
when using JEDEC standard modules. The address, command, and clock signals are
routed on each module in a daisy chain and feature a fly-by termination on the
module. Impedance matching is required to make the dual-DIMM topology work
effectively—40 to 50  traces should be targeted on the main board.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–24
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Address and Command Signals
Two unbuffered DIMMs result in twice the effective load on the address and
command signals, which reduces the slew rate and makes it more difficult to meet
setup and hold timing (tIS and tIH). However, address and command signals operate at
half the interface rate and are SDR. Hence a 400-Mbps data rate equates to an address
and command fundamental frequency of 100 MHz.
Control Group Signals
The control group signals (chip Select CS#, clock enable CKE, and ODT) are only ever
single rank. A dual-rank capable DDR3 DIMM slot has two copies of each signal, and
a dual-DIMM slot interface has four copies of each signal. Hence the signal quality of
these signals is identical to a single rank case. The control group of signals, are always
1T regardless of whether you implement a full-rate or half-rate design. As the signals
are also SDR, the control group signals operate at a maximum frequency of 0.5 × the
data rate. For example, in a 400 MHz design, the maximum control group frequency is
200 MHz.
Clock Group Signals
Like the control group signals, the clock signals in DDR3 SDRAM are only ever single
rank loaded. A dual-rank capable DDR3 DIMM slot has two copies of the signal, and
a dual-slot interface has four copies of the mem_clk and mem_clk_n signals.
f
1
For more information about a DDR3 two-DIMM system design, refer to Micron
TN-41-08: DDR3 Design Guide for Two-DIMM Systems.
The Altera DDR3 ALTMEMPHY megafunction does not support the 1T address and
command topology referred to in this Micron Technical Note—only 2T
implementations are supported.
Write to Memory in Slot 1 Using an ODT Setting of 75  With One Slot
Populated
Figure 3–21 shows the simulation and board measurement of the signal at the
memory when the FPGA is writing to the memory with an ODT setting of 75  and
using a 25- OCT drive strength setting on the FPGA.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Write to Memory in Slot 2 Using an ODT Setting of 75  With One Slot Populated
3–25
Figure 3–21. HyperLynx Simulation and Board Measurement of the Signal at the Memory in Slot 1 With Slot 2 Unpopulated
Table 3–11 summarizes the comparison between the simulation and board
measurements of the signal seen at the DDR2 SDRAM of a dual-DIMM with slot 1
populated by a memory interface using a different ODT setting.
Table 3–11. Comparison of the Signal at the Memory of a Dual-DIMM Interface With Only Slot 1 Populated and a Different
ODT Setting
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 75-
Simulation
1.68
0.91
NA
NA
1.88
1.88
Measurements
1.28
0.57
NA
NA
1.54
1.38
Simulation
1.68
0.97
0.06
NA
2.67
2.13
Measurements
1.30
0.63
0.22
0.20
1.74
1.82
ODT setting of 150-
Write to Memory in Slot 2 Using an ODT Setting of 75  With One Slot
Populated
Figure 3–22 shows the simulation and measurements result of the signal seen at the
memory when the FPGA is writing to the memory with an ODT setting of 75  and
using a 25- OCT drive strength setting on the FPGA.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–26
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–22. HyperLynx Simulation and Board Measurement of the Signal at the Memory in Slot 2 with Slot 1 Unpopulated
Table 3–12 summarizes the comparison of the signal at the memory of a dual-DIMM
memory interface with either slot 1 or slot 2 populated using a double parallel
termination using an ODT setting of 75  with a memory-side series resistor with a
25- OCT strength setting on the FPGA.
Table 3–12. Comparison of Signal at the Memory of a Dual-DIMM Interface With Only Slot 2 Populated and a Different ODT
Setting
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 75-
Simulation
1.68
0.89
NA
NA
1.82
1.93
Measurements
1.29
0.59
NA
NA
1.60
1.29
Simulation
1.69
0.94
0.07
0.02
1.88
2.29
Measurements
1.28
0.68
0.24
0.20
1.60
1.60
ODT setting of 150-
Write to Memory in Slot 1 Using an ODT Setting of 150  With Both
Slots Populated
Figure 3–23 shows the HyperLynx simulation and board measurement of the signal at
the memory in slot 1 of a double parallel termination using an ODT setting of 150 
on Slot 2 with a memory-side series resistor transmission line when the FPGA is
writing to the memory with a 25- OCT drive strength setting.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Write to Memory in Slot 2 Using an ODT Setting of 150  With Both Slots Populated
3–27
Figure 3–23. HyperLynx Simulation and Board Measurement of the Signal at the Memory in Slot 1 With Both Slots Populated
Table 3–13 summarizes the comparison between the simulation and board
measurements of the signal seen at the memory in slot 1 of a dual-DIMM memory
interface with both slots populated using a double parallel termination using a
different ODT setting on Slot 2 with a memory-side series resistor with a 25- OCT
strength setting on the FPGA.
Table 3–13. Comparison of Signal at the Memory of a Dual-DIMM Interface with Both Slots Populated and a Different ODT
Setting on Slot 2
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 150-
Simulation
1.60
1.18
0.02
NA
1.71
1.71
Measurements
0.89
0.78
0.13
0.17
1.19
1.32
Simulation
1.60
1.18
0.02
NA
1.71
1.71
Measurements
0.97
0.77
0.05
0.04
1.25
1.25
ODT setting of 75-
Write to Memory in Slot 2 Using an ODT Setting of 150  With Both
Slots Populated
Figure 3–24 shows the HyperLynx simulation and board measurement of the signal at
the memory in slot 2 of a double parallel termination using an ODT setting of 150 
on slot 1 with a memory-side series resistor transmission line when the FPGA is
writing to the memory with a 25- OCT drive strength setting.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–28
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–24. HyperLynx Simulation and Board Measurements of the Signal at the Memory in Slot 2 with Both Slots
Populated
Table 3–14 summarizes the comparison between the simulation and board
measurements of the signal seen at the memory of a dual-DIMM memory interface
with both slots populated using a double parallel termination using a different ODT
setting on Slot 1 with a memory-side series resistor with a 25- OCT strength setting
on the FPGA.
Table 3–14. Comparison of the Signal at the Memory of a Dual-DIMM Interface With Both Slots Populated and a Different
ODT Setting on Slot 1
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 150-
Simulation
1.45
1.11
0.19
0.17
1.43
2.21
Measurements
0.71
0.81
0.12
0.20
0.93
1.00
Simulation
1.60
1.16
0.10
0.08
1.68
1.60
Measurements
1.10
0.85
0.16
0.19
1.11
1.25
ODT setting of 75-
Read from Memory in Slot 1 Using an ODT Setting of 150  on Slot 2
with Both Slots Populated
Figure 3–25 shows the HyperLynx simulation and board measurement of the signal at
the FPGA of a double parallel termination using an external parallel resistor on the
FPGA side with a memory-side series resistor and an ODT setting of 150  with a full
drive strength setting on the memory.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
Read From Memory in Slot 2 Using an ODT Setting of 150  on Slot 1 With Both Slots Populated
3–29
Figure 3–25. HyperLynx Simulation and Board Measurement of the Signal at the FPGA When Reading From Slot 1 With Both
Slots Populated (Note 1)
Note to Figure 3–25:
(1) The vertical scale used for the simulation and measurement is set to 200 mV per division.
Table 3–15 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a dual-DIMM memory interface with
both slots populated using a different ODT setting on Slot 2.
Table 3–15. Comparison of Signal at the FPGA of a Dual-DIMM Interface With Both Slots Populated and a Different ODT
Setting on Slot 2
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rise Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 150 
Simulation
1.68
0.77
NA
NA
1.88
1.88
Measurements
0.76
0.55
NA
NA
1.11
1.14
Simulation
1.74
0.87
NA
NA
1.91
1.88
Measurements
0.86
0.59
NA
NA
1.11
1.09
ODT setting of 75 
Read From Memory in Slot 2 Using an ODT Setting of 150  on Slot 1
With Both Slots Populated
Figure 3–26 shows the HyperLynx simulation board measurement of the signal seen
at the FPGA of a double parallel termination using an external parallel resistor on the
FPGA side with memory-side series resistor and an ODT setting of 150  with a full
drive strength setting on the memory.
© November 2009
Altera Corporation
Board Layout Guidelines
Preliminary
3–30
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Figure 3–26. HyperLynx Simulation Board Measurement of the Signal at the FPGA When Reading From Slot 2 With Both
Slots Populated (Note 1)
Note to Figure 3–26:
(1) The vertical scale used for the simulation and measurement is set to 200 mV per division.
Table 3–16 summarizes the comparison between the simulation and board
measurements of the signal seen at the FPGA of a dual-DIMM memory interface with
both slots populated using a different ODT setting on Slot 1.
Table 3–16. Comparison of Signal at the FPGA of a Dual-DIMM Interface With Both Slots Populated and a Different ODT
Setting on Slot 1
Type
Eye Width
(ns)
Eye Height
(V)
Overshoot
(V)
Undershoot
(V)
Rising Edge Rate
(V/ns)
Falling Edge Rate
(V/ns)
ODT setting of 150-
Simulation
1.70
0.74
NA
NA
1.91
1.64
Measurements
0.74
0.64
NA
NA
1.14
1.14
Simulation
1.70
0.81
NA
NA
1.72
1.99
Measurements
0.87
0.59
NA
NA
1.09
1.14
ODT setting of 75-
Conclusion
This chapter looks at single- and dual-DIMM DDR2 and DDR3 SDRAM interfaces
and makes recommendations on topology and termination, to ensure optimum
design guidelines and best signal quality.
In the design of any dual-DIMM interface, you should follow the memory vendor
recommendations on the optimum ODT setting, slot population, and operations to
the DIMM locations. In addition, this chapter recommends the OCT settings to use at
the FPGA, to ensure optimum configuration.
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination, Drive Strength, Loading, and Board Layout Guidelines
References
3–31
The simulations and experiments referenced throughout this chapter show that you
can achieve good signal quality, if you follow the memory vendors recommended
ODT settings. Although the DDR2 simulations and experimental results in this
chapter are based on the Stratix II High Speed High Density Board, you can apply the
general principles to any dual-DIMM design. The addition of dynamic OCT in Stratix
III and Stratix IV devices has simplified the board design further by removing the
need for the previously required FPGA end discrete parallel termination.
Even though this chapter covers several combinations of ODT and OCT termination,
it is critical that as a board designer you perform system specific simulations to ensure
good signal integrity in your dual-DIMM SDRAM designs.
References
© November 2009
■
JEDEC Standard Publication JESD79-2, DDR2 SDRAM Specification, JEDEC Solid
State Technology Association.
■
JEDEC Standard Publication JESD8-15A, Stub Series Termination Logic for 1.8 V
(SSTL-18), JEDEC Solid State Technology Association.
■
Micron TN-47-01: DDR2 Design Guide for Two-DIMM Systems.
■
Micron TN-41-08: DDR3 Design Guide for Two-DIMM Systems
■
Micron TN-47-17: DDR2 SODIMM Optimized Address/Command Nets Introduction.
■
Samsung Electronics Application Note: DDR2 ODT Control
■
High-Speed Digital Design – A Handbook of Black Magic, Howard Johnson and Martin
Graham, Prentice Hall, 1993.
■
Circuits Interconnects, and Packaging for VLSI, H.B. Bakoglu, Addison Wesley, 1990.
■
Signal Integrity – Simplified, Eric Bogatin, Prentice Hall Modern Semiconductor
Design Series, 2004.
■
Handbook of Digital Techniques for High-Speed Design, Tom Granberg, Prentice Hall
Modern Semiconductor Design Series, 2004.
■
Termination Placement in PCB Design How Much Does it Matter?, Doug Brooks,
UltraCAD Design Inc.
■
PC4300 DDR2 SDRAM Unbuffered DIMM Design Specification, Revision 0.5, Oct 30,
2003.
Altera Corporation
Board Layout Guidelines
Preliminary
3–32
Drive Strength, Loading, and Board Layout Guidelines
Chapter 3: Dual-DIMM DDR2 and DDR3 SDRAM Interface Termination,
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
4. Power Estimation Methods for External
Memory Interface Designs
Table 4–1 shows the Altera-supported power estimation methods for external
memory interfaces.
Table 4–1. Power Estimation Methods for External Memory Interfaces
Method
Vector Source
ALTMEMPHY
Support
UniPHY Support
Early power
estimator (EPE)
Not applicable
v
v
Vector-less
PowerPlay power
analysis (PPPA)
Not applicable
v
v
Vector-based
PPPA
RTL simulation
v
v
Zero-delay
simulation (2)
v
v
Timing simulation
(2)
(2)
Accuracy
Estimation Time (1)
Lowest
Fastest
Highest
Slowest
Note to Table 4–1:
(1) To decrease the estimation time, you can skip power estimation during calibration. Power consumption during calibration is typically equivalent
to power consumption during user mode.
(2) Power analysis using timing simulation vectors is not supported.
When using Altera IP, you can use the zero-delay simulation method to analyze the
power required for the external memory interface. Zero-delay simulation is as
accurate as timing simulation for 95% designs (designs with no glitching). For a
design with glitching, power may be under estimated.
f
For more information about zero-delay simulation, refer to the Power Estimation and
Analysis section in the Quartus II Handbook.
1
The size of the vector file (.vcd) generated by zero-delay simulation of an Altera
DDR3 SDRAM High-Performance Controller Example Design is 400 GB. The .vcd
includes calibration and user mode activities. When vector generation of calibration
phase is skipped, the vector size decreases to 1 GB.
To perform vector-based PPPA using zero-delay simulation, follow these steps:
1. Perform design compilation in the Quartus® II software to generate your design's
Netlist <project_name>.vo.
1
© November 2009
The <project_name>.vo is generated in the last stage of a compile EDA
Netlist Writer.
Altera Corporation
Board Layout Guidelines
Preliminary
4–2
Designs
Chapter 4: Power Estimation Methods for External Memory Interface
2. In <project_name>.vo, search for the include statement for <project_name>.sdo,
comment the statement out, and save the file.
3. Create a simulation script containing device model files and libraries and design
specific files:
■
Netlist file for the design, <project_name>.vo
■
RTL or netlist file for the memory device
■
Testbench RTL file
4. Compile all the files.
5. Invoke simulator with commands to generate .vcd files.
6. Generate .vcd files for the parts of the design that contribute the most to power
dissipation.
7. Run simulation
8. Use the generated .vcd files in PPPA tool as the signal activity input file.
9. Run PPPA
f
For more information about estimating power, refer to the Power Estimation and
Analysis section in the Quartus II Handbook
Board Layout Guidelines
© November 2009
Preliminary
Altera Corporation
Additional Information
How to Contact Altera
For the most up-to-date information about Altera® products, see the following table.
Contact (Note 1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Altera literature services
Email
[email protected]
Non-technical support (General)
Email
[email protected]
(Software Licensing)
Email
[email protected]
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue
Meaning
Bold Type with Initial Capital
Letters
Indicates command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, dialog box options, software utility names, and other GUI labels. For
example, \qdesigns directory, d: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters
Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.
Italic type
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters
Indicates keyboard keys and menu names. For example, Delete key and the Options
menu.
“Subheading Title”
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
Courier type
Indicates signal, port, register, bit, block, and primitive names. For example, data1,
tdi, and input. Active-low signals are denoted by suffix n. For example,
resetn.
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
© November 2009
Altera Corporation
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
Info–2
Additional Information
Typographic Conventions
Visual Cue
Meaning
1., 2., 3., and
a., b., c., and so on.
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
■ ■
Bullets indicate a list of items when the sequence of the items is not important.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
w
A warning calls attention to a condition or possible situation that can cause you
injury.
r
The angled arrow instructs you to press Enter.
f
The feet direct you to more information about a particular topic.
External Memory Interface Handbook Volume 2: Device, Pin, and Board Layout Guidelines
Preliminary
© November 2009
Altera Corporation
External Memory Interface Handbook Volume 3:
Implementing Altera Memory Interface IP
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_IP-1.3
Document Version:
Document Date:
1.3
February 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
Contents
Section Revision Dates
Section I. DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User
Guide
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. About This IP
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
ALTMEMPHY Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
High-Performance Controller (HPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
High-Performance Controller II (HPC II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–11
Free Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
SOPC Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Complete the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Parameter Settings
ALTMEMPHY Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Memory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Use the Preset Editor to Create a Custom Memory Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Derate Memory Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–8
PHY Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11
Controller Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings . . . . . . . . . . . . . . . . . . . . . . 3–13
Controller Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Chapter 4. Compile and Simulate
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Simulating Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
© February 2010
Altera Corporation
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
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IP Functional Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–6
Chapter 5. Functional Description—ALTMEMPHY
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Step 1: Memory Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Step 2: Write Training Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Step 3: Read Resynchronization (Capture) Clock Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Step 4: Read and Write Datapath Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 5: Address and Command Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 6: Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 7: Prepare for User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Address and Command Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices . . . . . . . . 5–7
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Clock and Reset Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices . . . . . . . . . . . . . . . . . . . 5–9
Cyclone III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–16
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices . . . . . . . . . . . . . . . . . . 5–22
Cyclone III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26
Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–27
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices . . . . . . . 5–27
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28
ALTMEMPHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29
PHY-to-Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–35
Using a Custom Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45
Preliminary Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45
Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–45
Calibration Process Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–46
Other Local Interface Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–46
Address and Command Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–46
Handshake Mechanism Between Read Commands and Read Data . . . . . . . . . . . . . . . . . . . . . . . 5–46
Handshake Mechanism Between Write Commands and Write Data . . . . . . . . . . . . . . . . . . . . . . 5–47
Partial Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–48
Chapter 6. Functional Description—High-Performance Controller
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
Command FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Write Data FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Write Data Tracking Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Main State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Bank Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Timer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Initialization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Address and Command Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
PHY Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
ODT Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Low-Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
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Preliminary
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Error Correction Coding (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Partial Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ECC Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ECC Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–11
Example Top-Level File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Top-level Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16
Chapter 7. Functional Description—High-Performance Controller II
Upgrading from HPC to HPC II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
Avalon-MM Data Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
Write Data FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Command Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Bank Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Timer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Command-Issuing State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
Address and Command Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
Write and Read Datapath, and Write Data Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
ODT Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
User-Controlled Side-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
User Auto-Precharge Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
User-Refresh Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Multi-Cast Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Low-Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Configuration and Status Register (CSR) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
Error Correction Coding (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
Partial Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
Example Top-Level File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–10
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
Top-level Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–13
Register Maps Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20
Chapter 8. Latency
Chapter 9. Timing Diagrams
DDR and DDR2 High-Performance Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
User Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Full-Rate Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Half-Rate Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6
Full-Rate Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Half Rate Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
DDR and DDR2 High-Performance Controllers II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16
Half-Rate Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17
Half-Rate Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19
Full-Rate Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
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Altera Corporation
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Full-Rate Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23
Section II. DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. About This IP
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
ALTMEMPHY Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
High-Performance Controller (HPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
High-Performance Controller II (HPC II) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–7
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
OpenCore Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–8
OpenCore Plus Time-Out Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
SOPC Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Complete the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
MegaWizard Plug-In Manager Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Parameter Settings
ALTMEMPHY Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Memory Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Use the Preset Editor to Create a Custom Memory Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3
Derate Memory Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9
PHY Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10
Board Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–12
Controller Interface Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
DDR3 SDRAM High-Performance Controller Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Controller Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–14
Chapter 4. Compile and Simulate
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Simulate the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–4
Simulating Using NativeLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
IP Functional Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7
Chapter 5. Functional Description—ALTMEMPHY
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
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Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
DDR3 SDRAM (without leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Step 1: Memory Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Step 2: Write Training Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
Step 3: Read Resynchronization (Capture) Clock Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 4: Read and Write Datapath Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 5: Address and Command Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 6: Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Step 7: Prepare for User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
DDR3 SDRAM (with leveling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–7
Step 1: Memory Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Step 2: Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Step 3: Write Training Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Step 4: Read Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Step 5: Address and Command Path Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Step 6: Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10
Step 7: Write Clock Path Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Step 8: Prepare for User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
VT Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Mimic Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Address and Command Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–11
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Clock and Reset Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13
Reset Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–17
Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–18
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22
Stratix III and Stratix IV Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23
ALTMEMPHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24
PHY-to-Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31
Using a Custom Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Preliminary Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Clocks and Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–39
Calibration Process Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–40
Other Local Interface Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–40
Address and Command Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–40
Handshake Mechanism Between Read Commands and Read Data . . . . . . . . . . . . . . . . . . . . . . . 5–40
Handshake Mechanism Between Write Commands and Write Data . . . . . . . . . . . . . . . . . . . . . . 5–41
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–42
Chapter 6. Functional Description—High-Performance Controller
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Command FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Write Data FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Write Data Tracking Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Main State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Bank Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Timer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Initialization State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
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Address and Command Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
PHY Interface Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
ODT Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Low-Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Error Correction Coding (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–7
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
Partial Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ECC Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
ECC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–10
ECC Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–12
Example Top-Level File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–15
Top-level Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17
Chapter 7. Functional Description—High-Performance Controller II
Upgrading from HPC to HPC II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
Avalon-MM Data Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
Write Data FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Command Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Bank Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Timer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Command-Issuing State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
Address and Command Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
Write and Read Datapath, and Write Data Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
ODT Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
User-Controlled Side-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
User Auto-Precharge Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
User-Refresh Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Multi-Cast Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Low-Power Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–6
Configuration and Status Register (CSR) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
Error Correction Coding (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–7
Partial Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8
Partial Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
Example Top-Level File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–9
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–11
Top-level Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12
Register Maps Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18
Chapter 8. Latency
Chapter 9. Timing Diagrams
DDR3 High-Performance Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
Auto-Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–2
User Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3
Half-Rate Read for Avalon Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–4
Half-Rate Write for Avalon Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–6
Half Rate Write for Native Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8
Initialization Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10
Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12
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Preliminary
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DDR3 High-Performance Controllers II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14
Half-Rate Read (Burst-Aligned Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–15
Half-Rate Write (Burst-Aligned Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–17
Half-Rate Read (Non Burst-Aligned Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19
Half-Rate Write (Non Burst-Aligned Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21
Half-Rate Read With Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23
Half-Rate Write With Gaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–25
Half-Rate Write Operation (Merging Writes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–26
Write-Read-Write-Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. About This IP
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
MegaWizard Plug-In Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
SOPC Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Complete the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulate the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Constraining and Compiling
Add Pin and DQ Group Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Board Trace Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Chapter 4. Functional Description—Controller
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon-MM Slave Read and Write Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Command Issuing FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Avalon-MM and Memory Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Avalon-MM Slave Read Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Avalon-MM Slave Write Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Chapter 5. Functional Description—UniPHY
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
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I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Reset and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Address and Command Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
The Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
The DLL and PLL Sharing Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
UniPHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
AFI Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
The QDR II and QDR II+ SRAM controllers with UniPHY use AFI. . . . . . . . . . . . . . . . . . . . . . . . . 5–8
PHY-to-Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Using a Custom Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Chapter 6. Functional Description—Example Top-Level Project
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Individual Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Block Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Address and Burst Length Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Sequential Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Random Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Sequential and Random Interleaved Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Chapter 7. Latency
Chapter 8. Timing Diagrams
Section IV. RLDRAM II Controller with UniPHY IP User Guide
About This Section
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Chapter 1. About This IP
Release Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
MegaCore Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Installation and Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Chapter 2. Getting Started
Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
MegaWizard Plug-In Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
SOPC Builder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Specify Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Complete the SOPC Builder System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulate the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
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Preliminary
© February 2010 Altera Corporation
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Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Chapter 3. Constraining and Compiling
Add Pin and DQ Group Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Board Trace Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Compile the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Chapter 4. Functional Description—Controller
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Avalon-MM Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Write Data FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Command Issuing FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Refresh Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Bank Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Avalon-MM and Memory Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Avalon-MM Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–3
Chapter 5. Functional Description—UniPHY
Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
I/O Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Reset and Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Address and Command Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
Write Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Read Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4
The Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
The DLL and PLL Sharing Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
UniPHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
AFI Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
The RLDRAM II controller with UniPHY uses AFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–8
PHY-to-Controller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–9
Using a Custom Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–15
Chapter 6. Functional Description—Example Top-Level Project
Example Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Individual Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Block Read and Write Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Address and Burst Length Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Sequential Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Random Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Sequential and Random Interleaved Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
Chapter 7. Latency
Chapter 8. Timing Diagrams
Additional Information
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
© February 2010
Altera Corporation
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
xii
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
Preliminary
© February 2010 Altera Corporation
Section Revision Dates
The following table shows the revision dates for the sections in this volume.
Section
Version
Date
Part Number
DDR and DDR2 SDRAM High-Performance Controllers
and ALTMEMPHY IP User Guide
1.3
February 2010
EMI_DDR_UG-1.3
DDR3 SDRAM High-Performance Controller and
ALTMEMPHY IP User Guide
1.3
February 2010
EMI_DDR3_UG-1.3
QDR II and QDR II+ SRAM Controller with UniPHY User
Guide
1.2
February 2010
EMI_QDRII_UG-1.2
RLDRAM II Controller with UniPHY IP User Guide
1.2
February 2010
EMI_RLDRAM_II_UG-1.2
© February 2010
Altera Corporation
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
xiv
External Memory Interface Handbook Volume 3: Implementing Altera Memory Interface IP
Preliminary
Section Revision Dates
© February 2010 Altera Corporation
Section I. DDR and DDR2 SDRAM High-Performance
Controllers and ALTMEMPHY IP User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_DDR_UG-1.3
Document Version:
Document Date:
1.3
February 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
About This Section
Revision History
The following table shows the revision history for this section.
Date
Version
Changes Made
February 2010
1.3
Corrected typos.
February 2010
1.2
■
Full support for Stratix IV devices.
■
Added timing diagrams for initialization and calibration stages for HPC.
November 2009
1.1
Minor corrections.
November 2009
1.0
First published.
© February 2010
Preliminary
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
iv
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Preliminary
About This Section
Revision History
© February 2010 Altera Corporation
1. About This IP
The Altera® DDR and DDR2 SDRAM High-Performance Controller MegaCore®
functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2
SDRAM. The ALTMEMPHY megafunction is an interface between a memory
controller and the memory devices, and performs read and write operations to the
memory. The MegaCore functions work in conjunction with the Altera ALTMEMPHY
megafunction.
The DDR and DDR2 SDRAM High-Performance Controller MegaCore functions and
ALTMEMPHY megafunction offer full-rate or half-rate DDR and DDR2 SDRAM
interfaces. The DDR and DDR2 SDRAM High-Performance Controller MegaCore
functions offer two controller architectures: high-performance controller (HPC) and
high-performance controller II (HPC II). HPC II provides higher efficiency and more
advanced features.
1
The DDR and DDR2 SDRAM high-performance controllers denote both HPC and
HPC II unless indicated otherwise.
Figure 1–1 shows a system-level diagram including the example top-level file that the
DDR or DDR2 SDRAM High-Performance Controller MegaCore functions create for
you.
Figure 1–1. System-Level Diagram
Example Top-Level File
ALTMEMPHY
External
Memory
Device
DLL
PLL
(1)
HighPerformance
Controller
Example
Driver
Pass or Fail
Note to Figure 1–1:
(1) When you choose Instantiate DLL Externally, DLL is instantiated outside the ALTMEMPHY megafunction.
The MegaWizard™ Plug-In Manager generates an example top-level file, consisting of
an example driver, and your DDR or DDR2 SDRAM high-performance controller
custom variation. The controller instantiates an instance of the ALTMEMPHY
megafunction which in turn instantiates a PLL and DLL. You can optionally
instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL
between multiple instances of the ALTMEMPHY megafunction. You cannot share a
PLL between multiple instances of the ALTMEMPHY megafunction, but you may
share some of the PLL clock outputs between these multiple instances.
The example top-level file is a fully-functional design that you can simulate,
synthesize, and use in hardware. The example driver is a self-test module that issues
read and write commands to the controller and checks the read data to produce the
pass or fail, and test complete signals.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–2
Chapter 1: About This IP
Release Information
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller. The megafunction is available as a stand-alone product or
can be used in conjunction with Altera high-performance memory controllers. As a
stand-alone product, use the ALTMEMPHY megafunction with either custom or
third-party controllers.
Release Information
Table 1–1 provides information about this release of the DDR and DDR2 SDRAM
high-performance controllers and ALTMEMPHY IP.
Table 1–1. Release Information
Item
Version
Release Date
Ordering Codes
Description
9.1 SP1
February 2010
IP-SDRAM/HPDDR (DDR SDRAM HPC)
IP-SDRAM/HPDDR2 (DDR2 SDRAM HPC)
IP-HPMCII (HPC II)
Product IDs
00BE (DDR SDRAM)
00BF (DDR2 SDRAM)
00CO (ALTMEMPHY Megafunction)
Vendor ID
6AF7
Altera verifies that the current version of the Quartus® II software compiles the
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release. For information
about issues on the DDR and DDR2 SDRAM high-performance controllers and the
ALTMEMPHY megafunction in a particular Quartus II version, refer to the Quartus II
Software Release Notes.
Device Family Support
The MegaCore functions provide either full or preliminary support for target Altera
device families:
■
Full support means the megafunction meets all functional and timing
requirements for the device family and can be used in production designs.
■
Preliminary support means the megafunction meets all functional requirements,
but can still be undergoing timing analysis for the device family.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Features
1–3
Table 1–2 shows the level of support offered by the DDR and DDR2 SDRAM
high-performance controller to each of the Altera device families.
Table 1–2. Device Family Support
Device Family
Support
Arria® GX
Full
Arria II GX
Preliminary
Cyclone III
Full
Cyclone III LS
Preliminary
Cyclone IV
Preliminary
HardCopy II
Full
HardCopy III
Preliminary
HardCopy IV E
Preliminary
Stratix® II
Full
Stratix II GX
Full
Stratix III
Full
Stratix IV
Full
Other device families
No support
®
®
Features
The ALTMEMPHY megafunction offers the following features:
© February 2010
■
Simple setup
■
Support for the Altera PHY Interface (AFI) for DDR and DDR2 SDRAM on all
supported devices
■
Automated initial calibration eliminating complicated read data timing
calculations
■
VT tracking that guarantees maximum stable performance for DDR and DDR2
SDRAM interfaces
■
Self-contained datapath that makes connection to an Altera controller or a
third-party controller independent of the critical timing paths
■
Full-rate and half-rate DDR and DDR2 SDRAM interfaces
■
Easy-to-use MegaWizard interface
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–4
Chapter 1: About This IP
Features
In addition, Table 1–3 shows the features provided by the DDR and DDR2 SDRAM
HPC and HPC II.
Table 1–3. DDR and DDR2 SDRAM HPC and HPC II Features
Controller Architecture
Features
HPC
HPC II
v
v
v
v
Support for Avalon Memory Mapped (MM) local interface
v
v
Support for Native local interface
v
—
Configurable command look-ahead bank management with in-order reads and
writes
—
v
Additive latency
—
v(1)
Optional support for multi-cast write for tRC mitigation
—
v
Support for arbitrary Avalon burst length
—
v
Memory burst length of 4
v
v(2)
Memory burst length of 8
—
v(3)
Built-in flexible memory burst adapter
—
v
Configurable Local-to-Memory address mappings
—
v
Half-rate controller
Support for AFI ALTMEMPHY
®
Integrated half-rate bridge for low latency option
—
v
Optional run-time configuration of size and mode register settings, and memory
timing
—
v
Partial array self-refresh (PASR)
—
v
Support for industry-standard DDR and DDR2 SDRAM devices; and DIMMs
v
v
Optional support for self-refresh command
v
v
Optional support for user-controlled power-down command
v
—
Optional support for automatic power-down command with programmable
time out
—
v
Optional support for auto-precharge read and auto-precharge write commands
v
v
Optional support for user-controller refresh
v
v
Optional multiple controller clock sharing in SOPC Builder Flow
v
v
Integrated error correction coding (ECC) function 72-bit
v
v
Integrated ECC function 40-bit
—
v
Support for partial-word write with optional automatic error correction
—
v
SOPC Builder ready
v
v
Support for OpenCore Plus evaluation
v
—
Support for the Quartus II IP Advisor
v
—
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulator
v
v
Notes to Table 1–3:
(1) HPC II supports additive latency values greater or equal to tRCD - 1, in clock cycle unit (tCK).
(2) HPC II only supports memory burst length of 4 in full-rate mode.
(3) HPC II only supports memory burst length of 8 in half-rate mode.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Unsupported Features
1–5
Unsupported Features
■
Timing simulation
■
Burst length of 2
■
Partial burst and unaligned burst in ECC and non-ECC mode when DM pins are
disabled.
MegaCore Verification
MegaCore verification involves simulation testing. Altera has carried out extensive
random, directed tests with functional test coverage using industry-standard Denali
models to ensure the functionality of the DDR and DDR2 SDRAM high-performance
controllers.
Resource Utilization
The following sections show the resource utilization data for the ALTMEMPHY
megafunction, and the DDR and DDR2 high-performance controllers (HPC and
HPC II).
ALTMEMPHY Megafunction
Table 1–4 through Table 1–7 show the typical size of the ALTMEMPHY megafunction
with the AFI in the Quartus II software version 9.1 for the following devices:
1
■
Arria II GX (EP2AGX260FF35C4) devices
■
Cyclone III (EP3C16F484C6) devices
■
Stratix II (EP2S60F1020C3) devices
■
Stratix III (EP3SL110F1152C2) devices
■
Stratix IV (EP4SGX230HF35C2) devices
The resource utilization for Arria and Stratix GX devices is similar to Stratix II devices.
Table 1–4. Resource Utilization in Arria II GX Devices (Part 1 of 2) (Note 1)
© February 2010
PHY
Rate
Memory
Width
(Bits)
Combinational
ALUTS
Logic Registers
M9K
Blocks
Memory
ALUTs
Half
8
1,428
1,179
2
18
16
1,480
1,254
4
2
64
1,787
1,960
12
22
72
1,867
2,027
13
2
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–6
Chapter 1: About This IP
Resource Utilization
Table 1–4. Resource Utilization in Arria II GX Devices (Part 2 of 2) (Note 1)
PHY
Rate
Memory
Width
(Bits)
Combinational
ALUTS
Logic Registers
M9K
Blocks
Memory
ALUTs
Full
8
1,232
975
0
35
16
1,240
915
3
1
64
1,287
1,138
7
41
72
1,303
1,072
9
1
Note to Table 1–4:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory
controller overhead is additional.
Table 1–5. Resource Utilization in Cyclone III Devices
(Note 1)
PHY
Rate
Memory
Width
(Bits)
Combinational
LUTS
Logic Registers
M9K
Blocks
Half
8
1,995
1,199
2
16
2,210
1,396
3
64
3,523
2,574
9
72
3,770
2,771
9
8
1,627
870
2
16
1,762
981
2
64
2,479
1,631
5
72
2,608
1,740
5
Full
Note to Table 1–5:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory
controller overhead is additional.
Table 1–6. Resource Utilization in Stratix II Devices
PHY
Rate
(Note 1) and (2)
Memory
Width
(Bits)
Combinational
LUTS
Logic Registers
M512K
Blocks
M4K
Blocks
Half
8
1,444
1,201
4
1
16
1,494
1,375
4
2
64
1,795
2,421
5
7
72
1,870
2,597
4
8
Notes to Table 1–6:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory
controller overhead is additional.
(2) The resource utilization for Arria and Stratix GX devices is similar to Stratix II devices.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Resource Utilization
1–7
Table 1–7. Resource Utilization in Stratix III and Stratix IV Devices
(Note 1)
PHY
Rate
Memory
Width
(Bits)
Combinational
ALUTS
Logic Registers
M9K
Blocks
Memory
ALUTs
Half
8
1,356
1,040
1
40
16
1,423
1,189
1
80
64
1,805
2,072
1
320
72
1,902
2,220
1
360
8
1,216
918
1
20
16
1,229
998
1
40
64
1,319
1,462
1
160
72
1,337
1,540
1
180
Full
Note to Table 1–7:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory
controller overhead is additional.
High-Performance Controller (HPC)
Table 1–8 through Table 1–13 show the typical sizes for the DDR or DDR2 SDRAM
HPC with the AFI (including ALTMEMPHY) for Arria GX, Arria II GX, Cyclone III,
Stratix II, Stratix II GX, Stratix III, and Stratix IV devices.
Table 1–8. Resource Utilization in Arria GX Devices
Memory
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
M512
M4K
Half
32
8
1,851
1,562
4
2
64
16
1,904
1,738
4
4
256
64
2,208
2,783
5
15
288
72
2,289
2,958
4
17
16
8
1,662
1,332
6
0
32
16
1,666
1,421
3
3
128
64
1738
1,939
3
9
144
72
1,758
2,026
4
9
Full
Table 1–9. Resource Utilization in Arria II GX Devices (Part 1 of 2)
Memory
Controller Rate
Local Data
Width (Bits)
Half
32
8
1,837
1,553
3
64
16
1,894
1,628
6
256
64
2,201
2,334
20
288
72
2,279
2,401
22
© February 2010
Altera Corporation
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
(M9K)
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–8
Chapter 1: About This IP
Resource Utilization
Table 1–9. Resource Utilization in Arria II GX Devices (Part 2 of 2)
Memory
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
(M9K)
Full
16
8
1,671
1400
1
32
16
1,684
1,340
4
128
64
1725
1,562
11
144
72
1,738
2,497
14
Table 1–10. Resource Utilization in Cyclone III Devices
Controller Rate
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
2,683
1,563
3
64
16
2,905
1,760
5
256
64
4,224
2,938
17
288
72
4,478
3,135
18
16
8
2,386
1,276
3
32
16
2,526
1,387
3
Full
128
64
3,257
2,037
9
144
72
3,385
2,146
10
Table 1–11. Resource Utilization in Stratix II and Stratix II GX Devices
Memory
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
M512
M4K
Half
32
8
1,853
1,581
4
2
64
16
1,901
1,757
4
4
256
64
2,206
2,802
5
15
288
72
2,281
2,978
4
17
16
8
1,675
1,371
6
0
32
16
1,675
1,456
3
3
128
64
1740
1,976
3
9
144
72
1,743
2,062
4
9
Full
Table 1–12. Resource Utilization in Stratix III Devices (Part 1 of 2)
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
1,752
1,432
2
64
16
1,824
1,581
3
256
64
2,210
2,465
9
288
72
2,321
2,613
10
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Resource Utilization
1–9
Table 1–12. Resource Utilization in Stratix III Devices (Part 2 of 2)
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Full
16
8
1,622
1,351
2
32
16
1,630
1,431
2
128
64
1736
1,897
5
144
72
1,749
1,975
6
Table 1–13. Resource Utilization in Stratix IV Devices
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
1,755
1,452
1
64
16
1,820
1,597
2
256
64
2,202
2,457
8
288
72
2,289
2,601
9
Full
16
8
1,631
1,369
1
32
16
1,630
1,448
1
128
64
1731
1,906
4
144
72
1,743
1,983
5
High-Performance Controller II (HPC II)
Table 1–14 through Table 1–18 show the typical sizes for the DDR or DDR2 SDRAM
HPC II (including ALTMEMPHY) for Arria II GX, Cyclone III, Stratix II, Stratix II GX,
Stratix III, and Stratix IV devices.
Table 1–14. Resource Utilization in Arria II GX Devices
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
3,038
2,041
3
64
16
3,156
2,197
5
256
64
3,649
3,115
17
288
72
3,716
3,269
18
16
8
2,860
1,856
1
32
16
2,900
1,872
2
128
64
3,138
2,246
7
144
72
3,187
2,251
9
Full
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–10
Chapter 1: About This IP
Resource Utilization
Table 1–15. Resource Utilization in Cyclone III Devices
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
4,229
1,979
3
64
16
4.409
2,155
5
256
64
5,632
3,207
17
288
72
5,811
3,382
18
16
8
4,003
1,684
3
Full
32
16
4,090
1,763
3
128
64
4,680
2,221
9
144
72
4,776
2,298
10
Table 1–16. Resource Utilization in Stratix II and Stratix II GX Devices
Memory
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
M512
M4K
Half
32
8
3,063
1,991
4
3
64
16
3,122
2,145
4
6
256
64
3,433
3,065
5
23
288
72
3,517
3,219
4
26
16
8
2,818
1,756
4
2
32
16
2,833
1,817
3
4
128
64
2,869
2,137
3
13
144
72
2,906
2,193
3
14
Full
Table 1–17. Resource Utilization in Stratix III Devices
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
Half
32
8
2,907
1,935
2
64
16
2,997
2,084
3
256
64
3,392
2,968
9
288
72
3,464
3,116
10
16
8
2,859
1,758
2
Full
32
16
2,872
1,838
2
128
64
2,948
2,302
5
144
72
2,914
2,378
6
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
System Requirements
1–11
Table 1–18. Resource Utilization in Stratix IV Devices
Controller Rate
Local Data
Width (Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
M9K
Half
32
8
2,935
1,966
2
64
16
3,018
2,111
3
256
64
3,405
2,971
9
288
72
3,475
3,115
10
16
8
2,856
1,792
2
Full
32
16
2,872
1,871
2
128
64
2,938
2,329
5
144
72
2,962
2,404
6
System Requirements
The DDR and DDR2 SDRAM High-Performance Controller MegaCore functions are
part of the MegaCore IP Library, which is distributed with the Quartus II software and
downloadable from the Altera website, www.altera.com.
f
For system requirements and installation instructions, refer to Altera Software
Installation & Licensing.
Installation and Licensing
Figure 1–2 shows the directory structure after you install the DDR and DDR2 SDRAM
High-Performance Controller MegaCore functions, where <path> is the installation
directory. The default installation directory on Windows is c:\altera\<version>; on
Linux it is /opt/altera<version>.
Figure 1–2. Directory Structure
<path>
Installation directory.
ip
Contains the Alterar MegaCore IP Library and third-party IP cores.
altera
Contains the Altera MegaCore IP Library.
common
Contains shared components.
ddr_high_perf
Contains the DDR SDRAM High-Performance Controller MegaCore function files.
doc
Contains the documentation for the DDR SDRAM High-Performance Controller MegaCore function.
lib
Contains encypted lower-level design files and other support files.
You need a license for the MegaCore function only when you are completely satisfied
with its functionality and performance, and want to take your design to production.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
1–12
Chapter 1: About This IP
Installation and Licensing
To use the DDR or DDR2 SDRAM HPC, you can request a license file from the Altera
web site at www.altera.com/licensing and install it on your computer. When you
request a license file, Altera emails you a license.dat file. If you do not have Internet
access, contact your local representative.
To use the DDR or DDR2 HPC II, contact your local sales representative to order a
license.
Free Evaluation
Altera's OpenCore Plus evaluation feature is only applicable to the DDR or DDR2
SDRAM HPC. With the OpenCore Plus evaluation feature, you can perform the
following actions:
■
Simulate the behavior of a megafunction (Altera MegaCore function or AMPPSM
megafunction) within your system
■
Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
■
Generate time-limited device programming files for designs that include
MegaCore functions
■
Program a device and verify your design in hardware
You need to purchase a license for the megafunction only when you are completely
satisfied with its functionality and performance, and want to take your design to
production.
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation can support the following two modes of
operation:
■
Untethered—the design runs for a limited time
■
Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
All megafunctions in a device time-out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
2. Getting Started
Design Flow
You can implement a DDR or DDR2 SDRAM High-Performance Controller MegaCore
functions using either one of the following flows:
■
SOPC Builder flow
■
MegaWizard Plug-In Manager flow
You can only instantiate the ALTMEMPHY megafunction using the MegaWizard
Plug-In Manager flow.
Figure 2–1 shows the stages for creating a system in the Quartus II software using
either one of the flows.
Figure 2–1. Design Flow
Select Design Flow
SOPC Builder
Flow
MegaWizard
Flow
Specify Parameters
Specify Parameters
Complete
SOPC Builder System
Optional
Perform
Functional Simulation
Does
Simulation Give
Expected Results?
Yes
Add Constraints
and Compile Design
IP Complete
Debug Design
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
2–2
Chapter 2: Getting Started
SOPC Builder Flow
The SOPC Builder flow offers the following advantages:
■
Generates simulation environment
■
Creates custom components and integrates them via the component wizard
■
Interconnects all components with the Avalon-MM interface
The MegaWizard Plug-In Manager flow offers the following advantages:
■
Allows you to design directly from the DDR or DDR2 SDRAM interface to
peripheral device or devices
■
Achieves higher-frequency operation
SOPC Builder Flow
The SOPC Builder flow allows you to add the DDR and DDR2 SDRAM
high-performance controllers directly to a new or existing SOPC Builder system.
You can also easily add other available components to quickly create an SOPC Builder
system with a DDR or DDR2 SDRAM high-performance controller, such as the Nios II
processor and scatter-gather direct memory access (DMA) controllers. SOPC Builder
automatically creates the system interconnect logic and system simulation
environment.
f
For more information about SOPC Builder, refer to volume 4 of the Quartus II
Handbook. For more information about how to use controllers with SOPC Builder,
refer to the DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the
External Memory Interface Handbook. For more information on the Quartus II software,
refer to the Quartus II Help.
Specify Parameters
To specify the parameters for the DDR and DDR2 SDRAM high-performance
controllers using the SOPC Builder flow, perform the following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard.
2. On the Tools menu, click SOPC Builder.
3. For a new system, specify the system name and language.
4. Add DDR or DDR2 SDRAM High-Performance Controller to your system from
the System Contents tab.
1
The DDR or DDR2 SDRAM High-Performance Controller is in the
SDRAM folder under the Memories and Memory Controllers folder.
5. Specify the required parameters on all pages in the Parameter Settings tab.
f
For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1.
6. Click Finish to complete parameterizing the DDR or DDR2 SDRAM
high-performance controller and add it to the system.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
SOPC Builder Flow
2–3
Complete the SOPC Builder System
To complete the SOPC Builder system, perform the following steps:
1. In the System Contents tab, select Nios II Processor and click Add.
2. On the Nios II Processor page, in the Core Nios II tab, select altmemddr for Reset
Vector and Exception Vector.
3. Change the Reset Vector Offset and the Exception Vector Offset to an Avalon
address that is not written to by the ALTMEMPHY megafunction during its
calibration process.
c The ALTMEMPHY megafunction performs memory interface calibration
every time it is reset, and in doing so, writes to a range of addresses. If you
want your memory contents to remain intact through a system reset, you
should avoid using these memory addresses. This step is not necessary if
you reload your SDRAM memory contents from flash every time you reset
your system.
If you are upgrading your Nios system design from version 8.1 or previous,
ensure that you change the Reset Vector Offset and the Exception Vector
Offset to AFI mode.
To calculate the Avalon-MM address equivalent of the memory address range 0×0
to 0×1f, multiply the memory address by the width of the memory interface data
bus in bytes. Refer to Table 2–1 for more Avalon-MM addresses.
Table 2–1. Avalon-MM Addresses for AFI Mode
External Memory Interface
Width
Reset Vector Offset
Exception Vector Offset
8
0×40
0×60
16
0×80
0×A0
32
0×100
0×120
64
0×200
0×220
4. Click Finish.
5. On the System Contents tab, expand Interface Protocols and expand Serial.
6. Select JTAG UART and click Add.
7. Click Finish.
1
If there are warnings about overlapping addresses, on the System menu,
click Auto Assign Base Addresses.
If you enable ECC and there are warnings about overlapping IRQs, on the
System menu click Auto Assign IRQs.
8. For this example system, ensure all the other modules are clocked on the
altmemddr_sysclk, to avoid any unnecessary clock-domain crossing logic.
9. Click Generate.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
2–4
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
1
Among the files generated by SOPC Builder is the Quartus II IP File (.qip).
This file contains information about a generated IP core or system. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file. In that case, the system .qip file references the
component .qip file.
10. Compile your design, refer to “Compile and Simulate” on page 4–1.
MegaWizard Plug-In Manager Flow
The MegaWizard Plug-In Manager flow allows you to customize the DDR and DDR2
SDRAM high-performance controllers or ALTMEMPHY megafunction, and manually
integrate the function into your design.
1
f
You can alternatively use the IP Advisor to help you start your DDR or DDR2 SDRAM
high-performance controller design. On the Quartus II Tools menu, point to Advisors,
and then click IP Advisor. The IP Advisor guides you through a series of
recommendations for selecting, parameterizing, evaluating, and instantiating a DDR2
SDRAM high-performance controller into your design. It then guides you through a
complete Quartus II compilation of your project.
For more information about the MegaWizard Plug-In Manager and the IP Advisor,
refer to the Quartus II Help.
Specify Parameters
To specify parameters using the MegaWizard Plug-In Manager flow, perform the
following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard.
2. On the Tools menu, click MegaWizard Plug-In Manager to start the MegaWizard
Plug-In Manager.
■
The DDR or DDR2 SDRAM high-performance controller is in the Interfaces
folder under the External Memory folder.
■
The ALTMEMPHY megafunction is in the I/O folder.
1
The <variation name> must be a different name from the project name and
the top-level design entity name.
3. Specify the parameters on all pages in the Parameter Settings tab.
f
For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
2–5
4. On the EDA tab, turn on Generate simulation model to generate an IP functional
simulation model for the MegaCore function in the selected language.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
c Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional
design.
1
Some third-party synthesis tools can use a netlist that contains only the
structure of the MegaCore function, but not detailed logic, to optimize
performance of the design that contains the MegaCore function. If your
synthesis tool supports this feature, turn on Generate netlist.
When targeting a VHDL simulation model, the MegaWizard Plug-In
Manager still generates the <variation_name>_alt_mem_phy.v file for the
Quartus II synthesis. Do not use this file for simulation. Use the
<variation_name>.vho file for simulation instead.
The ALTMEMPHY megafunction only supports functional simulation. You
cannot perform timing or gate-level simulation when using the
ALTMEMPHY megafunction.
5. On the Summary tab, select the files you want to generate. A gray checkmark
indicates a file that is automatically generated. All other files are optional.
6. Click Finish to generate the MegaCore function and supporting files. A generation
report appears.
7. If you generate the MegaCore function instance in a Quartus II project, you are
prompted to add the .qip files to the current Quartus II project. When prompted to
add the .qip files to your project, click Yes. The addition of the .qip files enables
their visibility to Nativelink. Nativelink requires the .qip files to include libraries
for simulation.
1
The .qip file is generated by the MegaWizard interface, and contains
information about the generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore function or system in the Quartus II compiler. The MegaWizard
interface generates a single .qip file for each MegaCore function.
8. After you review the generation report, click Exit to close the MegaWizard Plug-In
Manager.
9. For the high-performance controller (HPC or HPC II), set the <variation
name>_example_top.v or .vhd file to be the project top-level design file.
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
2–6
Chapter 2: Getting Started
Generated Files
Generated Files
Table 2–2 shows the ALTMEMPHY generated files.
Table 2–2. ALTMEMPHY Generated Files (Part 1 of 2)
File Name
alt_mem_phy_defines.v
Description
Contains constants used in the interface. This file is
always in Verilog HDL regardless of the language you
chose in the MegaWizard Plug-In Manager.
<variation_name>.ppf
Pin planner file for your ALTMEMPHY variation.
<variation_name>.qip
Quartus II IP file for your ALTMEMPHY variation,
containing the files associated with this megafunction.
<variation_name>.v/.vhd
Top-level file of your ALTMEMPHY variation, generated
based on the language you chose in the MegaWizard
Plug-In Manager.
<variation_name>.vho
Contains functional simulation model for VHDL only.
<variation_name>_alt_mem_phy_seq_wrapper.vo/.vho
A wrapper file, for simulation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
<variation_name>.html
Lists the top-level files created and ports used in the
megafunction.
<variation_name>_alt_mem_phy_seq_wrapper.v/.vhd
A wrapper file, for compilation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
<variation_name>_alt_mem_phy_seq.vhd
Contains the sequencer used during calibration. This
file is always in VHDL language regardless of the
language you chose in the MegaWizard Plug-In
Manager.
<variation_name>_alt_mem_phy.v
Contains all modules of the ALTMEMPHY variation
except for the sequencer. This file is always in Verilog
HDL language regardless of the language you chose in
the MegaWizard Plug-In Manager. The DDR3 SDRAM
sequencer is included in the
<variation_name>_alt_mem_phy_seq.vhd file.
<variation name>_alt_mem_phy_pll_<device>.ppf
This XML file describes the MegaCore pin attributes to
the Quartus II Pin Planner.
<variation_name>_alt_mem_phy_pll.v/.vhd
The PLL megafunction file for your ALTMEMPHY
variation, generated based on the language you chose
in the MegaWizard Plug-In Manager.
<variation_name>_alt_mem_phy_delay.vhd
Includes a delay module for simulation. This file is only
generated if you choose VHDL as the language of your
MegaWizard Plug-In Manager output files.
<variation_name>_alt_mem_phy_dq_dqs.vhd or .v
Generated file that contains DQ/DQS I/O atoms
interconnects and instance. Arria II GX devices only.
<variation_name>_alt_mem_phy_dq_dqs_clearbox.txt
Specification file that generates the
<variation_name>_alt_mem_phy_dq_dqs file using
the clearbox flow. Arria II GX devices only.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
Generated Files
2–7
Table 2–2. ALTMEMPHY Generated Files (Part 2 of 2)
File Name
Description
<variation_name>_alt_mem_phy_pll.qip
Quartus II IP file for the PLL that your ALTMEMPHY
variation uses that contains the files associated with
this megafunction.
<variation_name>_alt_mem_phy_pll_bb.v/.cmp
Black box file for the PLL used in your ALTMEMPHY
variation. Typically unused.
<variation_name>_alt_mem_phy_reconfig.qip
Quartus II IP file for the PLL reconfiguration block.
Only generated when targeting Arria GX, HardCopy II,
Stratix II, and Stratix II GX devices.
<variation_name>_alt_mem_phy_reconfig.v/.vhd
PLL reconfiguration block module. Only generated
when targeting Arria GX, HardCopy II, Stratix II, and
Stratix II GX devices.
<variation_name>_alt_mem_phy_reconfig_bb.v/cmp
Black box file for the PLL reconfiguration block. Only
generated when targeting Arria GX, HardCopy II,
Stratix II, and Stratix II GX devices.
<variation_name>_bb.v/.cmp
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
<variation_name>_ddr_pins.tcl
Contains procedures used in the
<variation_name>_ddr_timing.sdc and
<variation_name>_report_timing.tcl files.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable
grouping, DQ/DQS grouping, and termination
assignments for your ALTMEMPHY variation. If your
top-level design pin names do not match the default
pin names or a prefixed version, edit the assignments
in this file.
<variation_name>_ddr_timing.sdc
Contains timing constraints for your ALTMEMPHY
variation.
<variation_name>_report_timing.tcl
Script that reports timing for your ALTMEMPHY
variation during compilation.
Table 2–3 shows the modules that are instantiated in the
<variation_name>_alt_mem_phy.v/.vhd file. A particular ALTMEMPHY variation
may or may not use any of the modules, depending on the memory standard that you
specify.
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 1 of 2)
Module Name
Usage
Description
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
addr_cmd
Generates the address and command structures.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
clk_reset
Instantiates PLL, DLL, and reset logic.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
dp_io
Generates the DQ, DQS, DM, and QVLD I/O pins.
<variation_name>_alt_mem_phy_ DDR2/DDR SDRAM
mimic
ALTMEMPHY variation
Creates the VT tracking mechanism for DDR and
DDR2 SDRAM PHYs.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
2–8
Chapter 2: Getting Started
Generated Files
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Module Name
<variation_name>_alt_mem_phy_
oct_delay
Usage
Description
DDR2/DDR SDRAM
ALTMEMPHY variation when
dynamic OCT is enabled.
Generates the proper delay and duration for the
OCT signals.
<variation_name>_alt_mem_phy_ DDR2/DDR SDRAM
postamble
ALTMEMPHY variations
Generates the postamble enable and disable
scheme for DDR and DDR2 SDRAM PHYs.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
read_dp
(unused for Stratix III or
Stratix IV devices)
Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.
<variation_name>_alt_mem_phy_ DDR2/DDR SDRAM
read_dp_group
ALTMEMPHY variations
(Stratix III and Stratix IV
devices only)
A per DQS group version of
<variation_name>_alt_mem_phy_read_dp.
<variation_name>_alt_mem_phy_ DDR2/DDR SDRAM
rdata_valid
ALTMEMPHY variations
Generates read data valid signal to sequencer and
controller.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
seq_wrapper
Generates sequencer for DDR and DDR2 SDRAM.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
write_dp
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
<variation_name>_alt_mem_phy_ DDR2/DDR SDRAM
write_dp_fr
ALTMEMPHY variations
A full-rate version of
<variation_name>_alt_mem_phy_
write_dp.
Table 2–4 through Table 2–6 show the additional files generated by the
high-performance controllers, that may be in your project directory. The names and
types of files specified in the MegaWizard Plug-In Manager report vary based on
whether you created your design with VHDL or Verilog HDL.
1
In addition to the files in Table 2–4 through Table 2–6, the MegaWizard also generates
the ALTMEMPHY files in Table 2–2, but with a _phy prefix. For example,
<variation_name>_alt_mem_phy_delay.vhd becomes
<variation_name>_phy_alt_mem_phy_delay.vhd.
Table 2–4. Controller Generated Files—All High Performance Controllers (Part 1 of 2)
Filename
Description
<variation name>.bsf
Quartus II symbol file for the MegaCore function variation. You
can use this file in the Quartus II block diagram editor.
<variation name>.html
MegaCore function report file.
<variation name>.v or .vhd
A MegaCore function variation file, which defines a VHDL or
Verilog HDL top-level description of the custom MegaCore
function. Instantiate the entity defined by this file inside of your
design. Include this file when compiling your design in the
Quartus II software.
<variation name>.qip
Contains Quartus II project information for your MegaCore
function variations.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
Generated Files
2–9
Table 2–4. Controller Generated Files—All High Performance Controllers (Part 2 of 2)
Filename
Description
<variation name>.ppf
XML file that describes the MegaCore pin attributes to the
Quartus II Pin Planner. MegaCore pin attributes include pin
direction, location, I/O standard assignments, and drive
strength. If you launch IP Toolbench outside of the Pin Planner
application, you must explicitly load this file to use Pin Planner.
<variation name>_example_driver.v or .vhd
Example self-checking test generator that matches your
variation.
<variation name>_example_top.v or .vhd
Example top-level design file that you should set as your
Quartus II project top level. Instantiates the example driver and
the controller.
Table 2–5. Controller Generated Files—DDR and DDR2 High-Performance Controllers (HPC)
Filename
Description
<variation name>_auk_ddr_hp_controller_wrapper.vo or .vho VHDL or Verilog HDL IP functional simulation model.
<variation_name>_auk_ddr_hp_controller_ecc_wrapper.vo or ECC functional simulation model.
.vho
Table 2–6. Controller Generated Files—DDR and DDR2 High-Performance Controllers II (HPC II) (Part 1 of 2)
Filename
Description
<variation name>_alt_ddrx_controller_wrapper. A controller wrapper that instantiates the alt_ddrx_controller.v file and
v or .vho
configures the controller accordingly by the wizard.
alt_ddrx_addr_cmd.v
Decodes the state machine outputs into the memory address and
command signals.
alt_ddrx_afi_block.v
Generates the read and write control signals for the AFI.
alt_ddrx_bank_tracking.v
Tracks which row is open in which memory bank.
alt_ddrx_clock_and_reset.v
Contains the clock and reset logic.
alt_ddrx_cmd_queue.v
Contains the command queue logic.
alt_ddrx_controller.v
The controller top-level file that instantiates all the sub-blocks.
alt_ddrx_csr.v
Contains the control and status register interface logic.
alt_ddrx_ddr2_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR2 memory
interfaces.
alt_ddrx_avalon_if.v
Communicates with the Avalon-MM interface.
alt_ddrx_decoder_40.v
Contains the 40 bit version of the ECC decoder logic.
alt_ddrx_decoder_72.v
Contains the 72 bit version of the ECC decoder logic.
alt_ddrx_decoder.v
Instantiates the appropriate width ECC decoder logic.
alt_ddrx_encoder_40.v
Contains the 40 bit version of the ECC encoder logic.
alt_ddrx_encoder_72.v
Contains the 72 bit version of the ECC encoder logic.
alt_ddrx_encoder.v
Instantiates the appropriate width ECC encoder logic.
alt_ddrx_input_if.v
The input interface block. It instantiates the alt_ddrx_cmd_queue.v,
alt_ddrx_wdata_fifo.v, and alt_ddrx_avalon_if.v files.
alt_ddrx_odt_gen.v
Instantiates the alt_ddrx_ddr2_odt_gen.v file selectively. It also controls
the ODT addressing scheme.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
2–10
Chapter 2: Getting Started
Generated Files
Table 2–6. Controller Generated Files—DDR and DDR2 High-Performance Controllers II (HPC II) (Part 2 of 2)
Filename
Description
alt_ddrx_state_machine.v
The main state machine of the controller.
alt_ddrx_timers_fsm.v
The state machine that tracks the per-bank timing parameters.
alt_ddrx_timers.v
Instantiates alt_ddrx_timers_fsm.v and contains the rank specific
timing tracking logic.
alt_ddrx_wdata_fifo.v
The write data FIFO logic. This logic buffers the write data and
byte-enables from the Avalon interface.
alt_avalon_half_rate_bridge_constraints.sdc
Contains timing constraints if your design has the Enable Half Rate
Bridge option turned on.
alt_avalon_half_rate_bridge.v
The integrated half-rate bridge logic block.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
3. Parameter Settings
ALTMEMPHY Parameter Settings
The ALTMEMPHY Parameter Settings page in the ALTMEMPHY MegaWizard
interface (Figure 3–1) allows you to parameterize the following settings:
■
Memory Settings
■
PHY Settings
■
Board Settings
■
Controller Interface Settings
Figure 3–1. ALTMEMPHY Parameter Settings Page
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–2
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
The text window at the bottom of the MegaWizard Plug-In Manager displays
information about the memory interface, warnings, and errors if you are trying to
create something that is not supported. The Finish button is disabled until you correct
all the errors indicated in this window.
The following sections describe the four tabs of the Parameter Settings page in more
detail.
Memory Settings
In the Memory Settings tab, you can select a particular memory device for your
system and choose the frequency of operation for the device. Under General Settings,
you can choose the device family, speed grade, and clock information. In the middle
of the page (left-side), you can filter the available memory device listed on the right
side of the Memory Presets dialog box, refer to Figure 3–1. If you cannot find the
exact device that you are using, choose a device that has the closest specifications,
then manually modify the parameters to match your actual device by clicking Modify
parameters, next to the Selected memory preset field.
Table 3–1 describes the General Settings available on the Memory Settings page of
the ALTMEMPHY MegaWizard interface.
Table 3–1. General Settings
Parameter Name
Description
Device family
Targets device family (for example, Stratix III). Table 1–2 on page 1–3 shows supported device
families. The device family selected here must match the device family selected on MegaWizard
page 2a.
Speed grade
Selects a particular speed grade of the device (for example, 2, 3, or 4 for the Stratix III device
family).
PLL reference clock
frequency
Determines the clock frequency of the external input clock to the PLL. Ensure that you use three
decimal points if the frequency is not a round number (for example, 166.667 MHz or 100 MHz) to
avoid a functional simulation or a PLL locking problem.
Memory clock
frequency
Determines the memory interface clock frequency. If you are operating a memory device below its
maximum achievable frequency, ensure that you enter the actual frequency of operation rather than
the maximum frequency achievable by the memory device. Also, ensure that you use three decimal
points if the frequency is not a round number (for example, 333.333 MHz or 400 MHz) to avoid a
functional simulation or a PLL locking issue.
Controller data rate
Selects the data rate for the memory controller. Sets the frequency of the controller to equal to
either the memory interface frequency (full-rate) or half of the memory interface frequency
(half-rate).
Enable half rate bridge This option is only available for HPC II.
Turn on to keep the controller in the memory full clock domain while allowing the local side to run
at half the memory clock speed, so that latency can be reduced.
Local interface clock
frequency
Value that depends on the memory clock frequency and controller data rate, and whether or not
you turn on the Enable Half Rate Bridge option.
Local interface width
Value that depends on the memory clock frequency and controller data rate, and whether or not
you turn on the Enable Half Rate Bridge option.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–3
Table 3–2 describes the options available to filter the Memory Presets that are
displayed. This set of options is where you indicate whether you are creating for DDR
or DDR2 SDRAM.
Table 3–2. Memory Presets List
Parameter Name
Description
Memory type
You can filter the type of memory to display, for example, DDR2 SDRAM. The ALTMEMPHY
megafunction supports DDR SDRAM and DDR2 SDRAM.
Memory vendor
You can filter the memory types by vendor. JEDEC is also one of the options, allowing you to
choose the JEDEC specifications. If your chosen vendor is not listed, you can choose JEDEC for the
DDR and DDR2 SDRAM interfaces. Then, pick a device that has similar specifications to your
chosen device and check the values of each parameter. Make sure you change the each parameter
value to match your device specifications.
Memory format
You can filter the type of memory by format, for example, discrete devices or DIMM packages.
Maximum frequency
You can filter the type of memory by the maximum operating frequency.
Use the Preset Editor to Create a Custom Memory Preset
Pick a device in the Memory Presets list that is closest or the same as the actual
memory device that you are using. Then, click the Modify Parameters button to
parameterize the following settings in the Preset Editor dialog box:
1
■
Memory attributes—These are the settings that determine your system's number
of DQ, DQ strobe (DQS), address, and memory clock pins.
■
Memory initialization options—These settings are stored in the memory mode
registers as part of the initialization process.
■
Memory timing parameters—These are the parameters that create and
time-constrain the PHY.
Even though the device you are using is listed in Memory Presets, ensure that the
settings in the Preset Editor dialog box are accurate, as some parameters may have
been updated in the memory device datasheets.
You can change the parameters with a white background to reflect your system. You
can also change the parameters with a gray background so the device parameters
match the device you are using. These parameters in gray background are
characteristics of the chosen memory device and changing them creates a new custom
memory preset. If you click Save As (at the bottom left of the page) and save the new
settings in the <quartus_install_dir>\quartus\common\ip\altera\altmemphy\lib\
directory, you can use this new memory preset in other Quartus II projects created in
the same version of the software.
When you click Save, the new memory preset appears at the bottom of the Memory
Presets list in the Memory Settings tab.
1
© February 2010
If you save the new settings in a directory other than the default directory, click Load
Preset in the Memory Settings tab to load the settings into the Memory Presets list.
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–4
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Figure 3–2 shows the Preset Editor dialog box for a DDR2 SDRAM.
Figure 3–2. DDR2 SDRAM Preset Editor
The Advanced option is only available for Arria II GX and Stratix IV devices. This
option shows the percentage of memory specification that is calibrated by the FPGA.
The percentage values are estimated by Altera based on the process variation.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–5
Table 3–3 through Table 3–5 describe the DDR2 SDRAM parameters available for
memory attributes, initialization options, and timing parameters. DDR SDRAM has
the same parameters, but their value ranges are different than DDR2 SDRAM.
Table 3–3. DDR2 SDRAM Attributes Settings (Part 1 of 2)
Parameter Name
Range (1)
Units
Description
Output clock pairs from FPGA
1–6
pairs
Defines the number of differential clock pairs driven from
the FPGA to the memory. More clock pairs reduce the
loading of each output when interfacing with multiple
devices. Memory clock pins use the signal splitter feature
in Arria II GX, Stratix IV and Stratix III devices for
differential signaling.
1, 2, 4, or 8
bits
Sets the number of chip selects in your memory
interface. The depth of your memory in terms of number
of chips. You are limited to the range shown as the local
side binary encodes the chip select address. You can set
this value to the next higher number if the range does not
meet your specifications. However, the highest address
space of the ALTMEMPHY megafunction is not mapped
to any of the actual memory address. The ALTMEMPHY
megafunction works with multiple chip selects and
calibrates against all chip select, mem_cs_n signals.
? 4–288
bits
Defines the total number of DQ pins on the memory
interface. If you are interfacing with multiple devices,
multiply the number of devices with the number of DQ
pins per device. Even though the GUI allows you to
choose 288-bit DQ width, the interface data width is
limited by the number of pins on the device. For best
performance, have the whole interface on one side of the
device.
Memory vendor
JEDEC, Micron,
Qimonda,
Samsung, Hynix,
Elpida, Nanya,
other
—
Lists the name of the memory vendor for all supported
memory standards.
Memory format
Discrete Device,
Unbuffered
DIMM,
Registered
DIMM
—
Specifies whether you are interfacing with devices or
modules. SODIMM is supported under unbuffered or
registered DIMMs.
Maximum memory frequency
See the memory
device datasheet
MHz
Sets the maximum frequency supported by the memory.
Column address width
9–11
bits
Defines the number of column address bits for your
interface.
Row address width
13–16
bits
Defines the number of row address bits for your
interface.
Bank address width
2 or 3
bits
Defines the number of bank address bits for your
interface.
Chip selects per DIMM
1 or 2
bits
Defines the number of chip selects on each DIMM in your
interface.
Memory chip selects
Memory interface DQ width
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–6
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–3. DDR2 SDRAM Attributes Settings (Part 2 of 2)
Parameter Name
Range (1)
Units
Description
DQ bits per DQS bit
4 or 8
bits
Defines the number of data (DQ) bits for each data strobe
(DQS) pin.
Precharge address bit
8 or 10
bits
Selects the bit of the address bus to use as the precharge
address bit.
Yes or No
—
Specifies whether you are using DM pins for write
operation. Altera devices do not support DM pins in ×4
mode.
80–533
MHz
Drive DM pins from FPGA
Maximum memory frequency
for CAS latency 3.0
Maximum memory frequency
for CAS latency 4.0
Maximum memory frequency
for CAS latency 5.0
Specifies the frequency limits from the memory data
sheet per given CAS latency. The ALTMEMPHY
MegaWizard interface generates a warning if the
operating frequency with your chosen CAS latency
exceeds this number.
Maximum memory frequency
for CAS latency 6.0
Notes to Table 3–3:
(1) The range values depend on the actual memory device used.
Table 3–4. DDR2 SDRAM Initialization Options
Parameter Name
Memory burst length
Range
Units
Description
4 or 8
beats
Sets the number of words read or written per transaction.
Memory burst length of four equates to local burst length
of one in half-rate designs and to local burst length of two
in full-rate designs.
Memory burst ordering
Sequential or
Interleaved
—
Controls the order in which data is transferred between
memory and the FPGA during a read transaction. For
more information, refer to the memory device datasheet.
Enable the DLL in the
memory devices
Yes or No
—
Enables the DLL in the memory device when set to Yes.
You must always enable the DLL in the memory device as
Altera does not guarantee any ALTMEMPHY operation
when the DLL is turned off. All timings from the memory
devices are invalid when the DLL is turned off.
Memory drive strength
setting
Normal or
Reduced
—
Controls the drive strength of the memory device’s output
buffers. Reduced drive strength is not supported on all
memory devices. The default option is normal.
Disabled, 50, 75,
150
Ohms
Sets the memory ODT value. Not available in DDR
SDRAM interfaces.
3, 4, 5, 6
Cycles
Sets the delay in clock cycles from the read command to
the first output data from the memory.
Memory ODT setting
Memory CAS latency setting
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–7
Table 3–5. DDR2 SDRAM Timing Parameter Settings (Note 1) (Part 1 of 2)
Parameter
Name
Range
Units
Description
tINIT
0.001–
1000
µs
Minimum memory initialization time. After reset, the controller does not issue
any commands to the memory during this period.
tMRD
2–39
ns
Minimum load mode register command period. The controller waits for this
period of time after issuing a load mode register command before issuing any
other commands.
tMRD is specified in ns in the DDR2 SDRAM high-performance controller and in
terms of tCK cycles in Micron's device datasheet. You need to convert tMRD to ns
by multiplying the number of cycles specified in the datasheet times tCK. Where
tCK is the memory operation frequency and not the memory device's tCK.
tRAS
8–200
ns
Minimum active to precharge time. The controller waits for this period of time
after issuing an active command before issuing a precharge command to the
same bank.
tRCD
4–65
ns
Minimum active to read-write time. The controller does not issue read or write
commands to a bank during this period of time after issuing an active
command.
tRP
4–65
ns
Minimum precharge command period. The controller does not access the
bank for this period of time after issuing a precharge command.
tREFI
1–65534
µs
Maximum interval between refresh commands. The controller performs
regular refresh at this interval unless user-controlled refresh is turned on.
tRFC
14–1651
ns
Minimum autorefresh command period. The length of time the controller waits
before doing anything else after issuing an auto-refresh command.
tWR
4–65
ns
Minimum write recovery time. The controller waits for this period of time after
the end of a write transaction before issuing a precharge command.
tWTR
1–3
tCK
Minimum write-to-read command delay. The controller waits for this period of
time after the end of a write command before issuing a subsequent read
command to the same bank. This timing parameter is specified in clock cycles
and the value is rounded off to the next integer.
tAC
300–750
ps
DQ output access time from CK/CK# signals.
tDQSCK
100–750
ps
DQS output access time from CK/CK# signals.
tDQSQ
100–500
ps
The maximum DQS to DQ skew; DQS to last DQ valid, per group, per access.
tDQSS
0–0.3
tCK
Positive DQS latching edge to associated clock edge.
tDS
10–600
ps
DQ and DM input setup time relative to DQS, which has a derated value
depending on the slew rate of the DQS (for both DDR and DDR2 SDRAM
interfaces) and whether DQS is single-ended or differential (for DDR2 SDRAM
interfaces). Ensure that you are using the correct number and that the value
entered is referenced to VREF(dc), not VIH(ac) min or VIL(ac) max. Refer to
“Derate Memory Setup and Hold Timing” on page 3–8 for more information
about how to derate this specification.
tDH
10–600
ps
DQ and DM input hold time relative to DQS, which has a derated value
depending on the slew rate of the DQS (for both DDR and DDR2 SDRAM
interfaces) and whether DQS is single-ended or differential (for DDR2 SDRAM
interfaces). Ensure that you are using the correct number and that the value
entered is referenced to VREF(dc), not VIH(dc) min or VIL(dc) max. Refer to
“Derate Memory Setup and Hold Timing” on page 3–8 for more information
about how to derate this specification.
tDSH
0.1–0.5
tCK
DQS falling edge hold time from CK.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–5. DDR2 SDRAM Timing Parameter Settings (Note 1) (Part 2 of 2)
Parameter
Name
Range
Units
Description
tDSS
0.1–0.5
tCK
DQS falling edge to CK setup.
tIH
100–1000
ps
Address and control input hold time, which has a derated value depending on
the slew rate of the CK and CK# clocks and the address and command signals.
Ensure that you are using the correct number and that the value entered is
referenced to VREF(dc), not VIH(dc) min or VIL(dc) max. Refer to “Derate
Memory Setup and Hold Timing” on page 3–8 for more information about how
to derate this specification.
tIS
100–1000
ps
Address and control input setup time, which has a derated value depending on
the slew rate of the CK and CK# clocks and the address and command signals.
Ensure that you are using the correct number and that the value entered is
referenced to VREF(dc), not VIH(ac) min or VIL(ac) max. Refer to “Derate
Memory Setup and Hold Timing” on page 3–8 for more information about how
to derate this specification.
tQHS
100–700
ps
The maximum data hold skew factor.
tRRD
2.06–64
ns
The activate to activate time, per device, RAS to RAS delay timing parameter.
tFAW
7.69–256
ns
The four-activate window time, per device.
tRTP
2.06–64
ns
Read to precharge time.
Note to Table 3–5:
(1) See the memory device data sheet for the parameter range. Some of the parameters may be listed in a clock cycle (tCK) unit. If the MegaWizard
Plug-In Manager requires you to enter the value in a time unit (ps or ns), convert the number by multiplying it with the clock period of your
interface (and not the maximum clock period listed in the memory data sheet).
Derate Memory Setup and Hold Timing
Because the base setup and hold time specifications from the memory device
datasheet assume input slew rates that may not be true for Altera devices, derate and
update the following memory device specifications in the Preset Editor dialog box:
1
■
tDS
■
tDH
■
tIH
■
tIS
For Arria II GX and Stratix IV devices, you need not derate using the Preset Editor.
You only need to enter the parameters referenced to VREF, and the deration is done
automatically when you enter the slew rate information on the Board Settings tab.
After derating the values, you then need to normalize the derated value because
Altera input and output timing specifications are referenced to VREF. However, JEDEC
base setup time specifications are referenced to VIH/VIL AC levels; JEDEC base hold
time specifications are referenced to VIH/VIL DC levels.
When the memory device setup and hold time numbers are derated and normalized
to VREF, update these values in the Preset Editor dialog box to ensure that your timing
constraints are correct.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–9
For example, according to JEDEC, 400-MHz DDR2 SDRAM has the following
specifications, assuming 1V/ns DQ slew rate rising signal and 2V/ns differential slew
rate:
1
■
Base tDS = 50
■
Base tDH = 125
■
VIH(ac) = VREF + 0.2 V
■
VIH(dc) = VREF + 0.125V
■
VIL(ac) = VREF – 0.2 V
■
VIL(dc) = VREF – 0.125 V
JEDEC lists two different sets of base and derating numbers for tDS and tDH
specifications, whether you are using single-ended or differential DQS signaling, for
any DDR2 SDRAM components with a maximum frequency up to 267 MHz. In
addition, the VIL(ac) and VIH(ac) values may also be different for those devices.
The VREF referenced setup and hold signals for a rising edge are:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 50 + 0 + 200 = 250 ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 125 + 0 + 67.5 =
192.5 ps
If the output slew rate of the write data is different from 1V/ns, you have to first
derate the tDS and tDH values, then translate these AC/DC level specs to VREF
specification.
For a 2V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn slew rate:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 25 + 100 + 100 = 225
ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 100 + 45 + 33.75 =
178.75 ps
For a 0.5V/ns DQ slew rate rising signal and 1V/ns DQS-DQSn slew rate:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 25 + 0 + 400 = 425 ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 100 – 65 + 250 =
285 ps
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–10
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
PHY Settings
Click Next or the PHY Settings tab to set the options described in Table 3–6. The
options are available if they apply to the target Altera device.
Table 3–6. ALTMEMPHY PHY Settings (Part 1 of 2)
Parameter Name
Use dedicated PLL
outputs to drive
memory clocks
Applicable Device Families
HardCopy II and Stratix II
(prototyping for
HardCopy II)
Description
Turn on to use dedicated PLL outputs to generate the external
memory clocks, which is required for HardCopy II ASICs and their
Stratix II FPGA prototypes. When turned off, the DDIO output
registers generate the clock outputs.
When you use the DDIO output registers for the memory clock,
both the memory clock and the DQS signals are well aligned and
easily meets the tDQSS specification. However, when the dedicated
clock outputs are for the memory clock, the memory clock and the
DQS signals are not aligned properly and requires a positive phase
offset from the PLL to align the signals together.
Dedicated memory
clock phase
HardCopy II and Stratix II
(prototyping for
HardCopy II)
The required phase shift to align the CK/CK# signals with
DQS/DQS# signals when using dedicated PLL outputs to drive
memory clocks.
Use differential DQS
Arria II GX, Stratix III, and
Stratix IV
Enable this feature for better signal integrity. Recommended for
operation at 333 MHz or higher. An option for DDR2 SDRAM only,
as DDR SDRAM does not support differential DQSS.
Enable external access
to reconfigure PLL
prior to calibration
HardCopy II and Stratix II
(prototyping for
HardCopy II)
When enabling this option for Stratix II and HardCopy II devices,
the inputs to the ALTPLL_RECONFIG megafunction are brought to
the top level for debugging purposes.
This option allows you to reconfigure the PLL before calibration to
adjust, if necessary, the phase of the memory clock
(mem_clk_2x) before the start of the calibration of the
resynchronization clock on the read side. The calibration of the
resynchronization clock on the read side depends on the phase of
the memory clock on the write side.
Instantiate DLL
externally
All supported device
families, except for
Cyclone III devices
Use this option with Stratix III, Stratix IV, HardCopy III, or
HardCopy IV devices, if you want to apply a non-standard phase
shift to the DQS capture clock. The ALTMEMPHY DLL offsetting I/O
can then be connected to the external DLL and the Offset Control
Block.
As Cyclone III devices do not have DLLs, this feature is not
supported.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–11
Table 3–6. ALTMEMPHY PHY Settings (Part 2 of 2)
Parameter Name
Applicable Device Families
Enable dynamic parallel Stratix III and Stratix IV
on-chip termination
Description
This option provides I/O impedance matching and termination
capabilities. The ALTMEMPHY megafunction enables parallel
termination during reads and series termination during writes with
this option checked. Only applicable for DDR and DDR2 SDRAM
interfaces where DQ and DQS are bidirectional. Using the dynamic
termination requires that you use the OCT calibration block, which
may impose a restriction on your DQS/DQ pin placements
depending on your RUP/RDN pin locations.
Although DDR SDRAM does not support ODT, dynamic OCT is still
supported in Altera FPGAs.
For more information, refer to either the External Memory
Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III
Device Handbook or the External Memory Interfaces in Stratix IV
Devices chapter in volume 1 of the Stratix IV Device Handbook.
Clock phase
Arria II GX, Arria GX,
Cyclone III, HardCopy II,
Stratix II, and Stratix II GX
Adjusting the address and command phase can improve the
address and command setup and hold margins at the memory
device to compensate for the propagation delays that vary with
different loadings. You have a choice of 0°, 90°, 180°, and 270°,
based on the rising and falling edge of the phy_clk and
write_clk signals. In Stratix IV and Stratix III devices, the clock
phase is set to dedicated.
Dedicated clock phase
Stratix III and Stratix IV
When you use a dedicated PLL output for address and command,
you can choose any legal PLL phase shift to improve setup and
hold for the address and command signals. You can set this value
to between 180° and 359°, the default is 240°. However, generally
PHY timing requires a value of greater than 240° for half-rate
designs and 270° for full-rate designs.
Board skew
All supported device
families except Arria II GX
and Stratix IV devices
Maximum skew across any two memory interface signals for the
whole interface from the FPGA to the memory (either a discrete
memory device or a DIMM). This parameter includes all types of
signals (data, strobe, clock, address, and command signals). You
need to input the worst-case skew, whether it is within a DQS/DQ
group, or across all groups, or across the address and command
and clocks signals. This parameter generates the timing constraints
in the .sdc file.
Autocalibration
simulation options
All supported device
families
Choose between Full Calibration (long simulation time), Quick
Calibration, or Skip Calibration.
For more information, refer to the Simulation section in volume 4 of
the External Memory Interface Handbook.
Board Settings
Click Next or the Board Settings tab to set the options described in Table 3–7. The
board settings parameters are set to model the board level effects in the timing
analysis. The options are available if you choose Arria II GX or Stratix IV device for
your interface. Otherwise, the options are disabled.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–12
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–7. ALTMEMPHY Board Settings
Parameter Name
Units
Number of slots/discrete devices
—
Description
Sets the single-rank or multirank configuration.
CK/CK# slew rate (differential)
V/ns
Sets the differential slew rate for the CK and CK# signals.
Addr/command slew rate
V/ns
Sets the slew rate for the address and command signals.
DQ/DQS# slew rate (differential)
V/ns
Sets the differential slew rate for the DQ and DQS# signals.
DQ slew rate
V/ns
Sets the slew rate for the DQ signals.
Addr/command eye reduction
(setup)
ns
Sets the reduction in the eye diagram on the setup side due to the ISI on
the address and command signals.
Addr/command eye reduction
(hold)
ns
Sets the reduction in the eye diagram on the hold side due to the ISI on
the address and command signals.
DQ eye reduction
ns
Sets the total reduction in the eye diagram on the setup side due to the ISI
on the DQ signals.
Delta DQS arrival time
ns
Sets the increase of variation on the range of arrival times of DQS due to
ISI.
Max skew between
DIMMs/devices
ns
Sets the largest skew or propagation delay on the DQ signals between
ranks, especially true for DIMMs in different slots.
This value affects the Resynchronization margin for the DDR2 interfaces
in multi-rank configurations for both DIMMs and devices.
Max skew within DQS groups
ns
Sets the largest skew between the DQ pins in a DQS group. This value
affects the Read Capture and Write margins for the DDR2 interfaces in all
configurations (single- or multi-rank, DIMM or device).
Max skew between DQS group
ns
Sets the largest skew between DQS signals in different DQS groups. This
value affects the Resynchronization margin for the DDR2 interfaces in
both single- or multi-rank configurations.
Addr/command to CK skew
ns
Sets the skew or propagation delay between the CK signal and the address
and command signals. The positive values represent the address and
command signals that are longer than the CK signals, and the negative
values represent the address and command signals that are shorter than
the CK signals. This skew is used by the Quartus II software to optimize
the delay of the address/command signals to have appropriate setup and
hold margins for the DDR2 interfaces.
Controller Interface Settings
The Controller Interface Settings tab allows you to specify the native interface or the
default Avalon-MM interface for your local interface as required by the
ALTMEMPHY megafunction for DDR and DDR2 SDRAM. The options are disabled if
you select AFI for the controller-to-PHY interface protocol. The Avalon-MM interface
is the only local interface supported in these variations.
1
Altera recommends that you use the AFI for new designs; only use the non-AFI for
existing designs.
Native interface is a superset of the Avalon-MM interface, containing the following
additional signals in addition to the Avalon-MM interface signals:
■
local_init_done
■
local_refresh_req
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings
■
local_refresh_ack
■
local_wdata_req
3–13
These signals provide extra information and control that is not possible in the
Avalon-MM bus protocol.
The other difference between the native and the Avalon-MM local interface is in the
write transaction. In an Avalon-MM interface, the write data is presented along with
the write request. In native local interfaces, the write data (and byte enables) are
presented in the clock cycle after the local_wdata_req signal is asserted.
Avalon-MM interfaces do not use the local_wdata_req signal.
1
There is no difference in latency between the native and Avalon-MM interfaces.
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings
The DDR or DDR2 SDRAM High-Performance Controller Parameter Settings page
in the DDR or DDR2 SDRAM High-Performance Controller MegaWizard interface
(Figure 3–3) allows you to parameterize the following settings:
■
Memory Settings
■
PHY Settings
■
Board Settings
■
Controller Settings
The Memory Settings, PHY Settings, and Board Settings tabs provide the same
options as in the ALTMEMPHY Parameter Settings page.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–14
Chapter 3: Parameter Settings
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings
Figure 3–3. DDR2 SDRAM High-Performance Controller Settings
Controller Settings
Table 3–8 shows the options provided in the Controller Settings tab.
Table 3–8. Controller Settings (Part 1 of 3)
Parameter
Controller architecture
Controller Architecture
—
Description
Specifies the controller architecture.
Enable self-refresh controls
Both
Turn on to enable the controller to allow you to have control on
when to place the external memory device in self-refresh mode,
refer to “User-Controlled Self-Refresh Logic” on page 7–7.
Enable power down controls
HPC
Turn on to enable the controller to allow you to have control on
when to place the external memory device in power-down mode.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings
3–15
Table 3–8. Controller Settings (Part 2 of 3)
Parameter
Controller Architecture
Description
Enable auto power down
HPC II
Turn on to enable the controller to automatically place the
external memory device in power-down mode after a specified
number of idle controller clock cycles is observed in the
controller. You can specify the number of idle cycles after which
the controller powers down the memory in the Auto Power
Down Cycles field, refer to “Automatic Power-Down with
Programmable Time-Out” on page 7–7.
Auto power down cycles
HPC II
Determines the desired number of idle controller clock cycles
before the controller places the external memory device in a
power-down mode. The legal range is 1 to 65,535.
The auto power-down mode is disabled if you set the value to 0
clock cycles.
Enable user auto-refresh
controls
Both
Turn on to enable the controller to allow you to have control on
when to place the external memory device in refresh mode.
Enable auto-precharge
control
Both
Turn on to enable the auto-precharge control on the controller
top level. Asserting the auto-precharge control signal while
requesting a read or write burst allows you to specify whether or
not the controller should close (auto-precharge) the current
opened page at the end of the read or write burst.
HPC II
Allows you to control the mapping between the address bits on
the Avalon interface and the chip, row, bank, and column bits on
the memory interface.
Local-to-memory address
mapping
If your application issues bursts that are greater than the
column size of the memory device, choose the
Chip-Row-Bank-Column option. This option allows the
controller to use its look-ahead bank management feature to
hide the effect of changing the currently open row when the
burst reaches the end of the column.
On the other hand, if your application has several masters that
each use separate areas of memory, choose the
Chip-Bank-Row-Column option. This option allows you to use
the top address bits to allocate a physical bank in the memory to
each master. The physical bank allocation avoids different
masters accessing the same bank which is likely to cause
inefficiency, as the controller must then open and close rows in
the same bank.
Command queue look-ahead
depth
HPC II
This option allows you to select a command queue look-ahead
depth value to control the number of read or write requests the
look-ahead bank management logic examines, refer to
“Command Queue” on page 7–4.
Local maximum burst count
HPC II
Specifies a burst count to configure the maximum Avalon burst
count that the controller slave port accepts.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
3–16
Chapter 3: Parameter Settings
DDR or DDR2 SDRAM High-Performance Controller Parameter Settings
Table 3–8. Controller Settings (Part 3 of 3)
Parameter
Controller Architecture
Description
Enable configuration and
status register interface
HPC II
Turn on to enable run-time configuration and status retrieval of
the memory controller. Enabling this option adds an additional
Avalon-MM slave port to the memory controller top level that
allows run-time reconfiguration and status retrieving for
memory timing parameters, memory address size and mode
register settings, and controller features. If the Error Detection
and Correction Logic option is enabled, the same slave port also
allows you to control and retrieve the status of this logic. Refer
to “Configuration and Status Register (CSR) Interface” on
page 7–7.
Enable error detection and
correction logic
Both
Turn on to enable error correction coding (ECC) for single-bit
error correction and double-bit error detection. Refer to “Error
Correction Coding (ECC)” on page 6–5 for HPC, and “Error
Correction Coding (ECC)” on page 7–7 for HPC II.
Enable auto error correction
HPC II
Turn on to allow the controller to perform auto correction when
ECC logic detects a single-bit error. Alternatively, you can turn
off this option and schedule the error correction at a desired
time for better system efficiency. Refer to “Error Correction
Coding (ECC)” on page 7–7.
Enable multi-cast write
control
HPC II
Turn on to enable the multi-cast write control on the controller
top level. Asserting the multi-cast write control when requesting
a write burst causes the write data to be written to all the chip
selects in the memory system. Multi-cast write is not supported
for registered DIMM interfaces or if the ECC logic is enabled.
Multiple controller clock
sharing
Both
This option is only available in SOPC Builder Flow. Turn on to
allow one controller to use the Avalon clock from another
controller in the system that has a compatible PLL. This option
allows you to create SOPC Builder systems that have two or
more memory controllers that are synchronous to your master
logic. Refer to
Local interface protocol
HPC
Specifies the local side interface between the user logic and the
memory controller. The Avalon-MM interface allows you to
easily connect to other Avalon-MM peripherals.
The HPC II architecture supports only the Avalon-MM interface.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
4. Compile and Simulate
After setting the parameters to the MegaCore function, you can now integrate the
MegaCore function variation into your design, and compile and simulate. The
following sections detail the steps you need to perform to compile and simulate your
design:
■
Compile the Design
■
Simulate the Design
Compile the Design
Figure 4–1 shows the top-level view of the Altera high-performance controller design
as an example on how your final design looks after you integrate the controller and
the user logic.
Figure 4–1. High-Performance Controller System-Level Diagram
Example Top-Level File
ALTMEMPHY
External
Memory
Device
DLL
PLL
(1)
HighPerformance
Controller
Example
Driver
Pass or Fail
Note to Figure 4–1:
(1) When you choose Instantiate DLL Externally, DLL is instantiated outside the controller.
Before compiling a design with the ALTMEMPHY variation, you must edit some
project settings, include the .sdc file, and make I/O assignments. I/O assignments
include I/O standard, pin location, and other assignments, such as termination and
drive strength settings. Some of these tasks are listed at the ALTMEMPHY
Generation window. For most systems, Altera recommends that you use the
Advanced I/O Timing feature by using the Board Trace Model command in the
Quartus II software to set the termination and output pin loads for the device.
1
© February 2010
You cannot compile the ALTMEMPHY variation as a stand-alone top-level design
because the generated .sdc timing constraints file requires the ALTMEMPHY
variation be part of a larger design (with a controller and/or example driver). If you
want to check whether the ALTMEMPHY variation meets your required target
frequency before your memory controller is ready, create a top-level file that
instantiates this ALTMEMPHY variation.
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
4–2
Chapter 4: Compile and Simulate
Compile the Design
To use the Quartus II software to compile the example top-level file and perform
post-compilation timing analysis, follow these steps:
1. Set up the TimeQuest timing analyzer:
a. On the Assignments menu, click Timing Analysis Settings, select Use
TimeQuest Timing Analyzer during compilation, and click OK.
b. Add the Synopsys Design Constraints (.sdc) file,
<variation name>_phy_ddr_timing.sdc, to your project. On the Project menu,
click Add/Remove Files in Project and browse to select the file.
c. Add the .sdc file for the example top-level design,
<variation name>_example_top.sdc, to your project. This file is only required if
you are using the example as the top-level design.
2. You can either use the <variation_name>_pin_assignments.tcl or the
<variation_name>.ppf file to apply the I/O assignments generated by the
MegaWizard Plug-In Manager. Using the .ppf file and the Pin Planner gives you
the extra flexibility to add a prefix to your memory interface pin names. You can
edit the assignments either in the Assignment Editor or Pin Planner. Use one of the
following procedures to specify the I/O standard assignments for pins
■
If you have a single SDRAM interface, and your top-level pins have default
naming shown in the example top-level file, run
<variation name>_pin_assignments.tcl.
or
■
If your design contains pin names that do not match the design, edit the
<variation name>_pin_assignments.tcl file before you run the script. Follow these
steps:
a. Open <variation name>_pin_assignments.tcl file.
b. Based on the flow you are using, set the sopc_mode value to Yes or No.
■
SOPC Builder System flow:
if {![info exists sopc_mode]} {set sopc_mode YES}
■
MegaWizard Plug-In Manager flow:
if {![info exists sopc_mode]} {set sopc_mode NO}
c. Type your preferred prefix in the pin_prefix variable. For example, to add
the prefix my_mem, do the following:
if {![info exists set_prefix}{set pin_prefix “my_mem_”}
After setting the prefix, the pin names are expanded as shown in the following:
■
SOPC Builder System flow:
my_mem_cs_n_from_the_<your instance name>
■
MegaWizard Plug-In Manager flow:
my_mem_cs_n[0]
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Compile the Design
1
4–3
If your top-level design does not use single bit bus notation for the
single-bit memory interface signals (for example, mem_dqs rather than
mem_dqs[0]), in the Tcl script you should change set single_bit
{[0]} to set single_bit {}.
or
■
Alternatively, to change the pin names that do not match the design, you can add a
prefix to your pin names by doing the following:
a. On the Assignments menu, click Pin Planner.
b. On the Edit menu, click Create/Import Megafunction.
c. Select Import an existing custom megafunction and navigate to
<variation name>.ppf.
d. Type the prefix you want to use in Instance name. For example, change
mem_addr to core1_mem_addr.
3. Set the top-level entity to the top-level design.
a. On the File menu, click Open.
b. Browse to your SOPC Builder system top-level design or <variation
name>_example_top if you are using MegaWizard Plug-In Manager, and click
Open.
c. On the Project menu, click Set as Top-Level Entity.
4. Assign the DQ and DQS pin locations.
a. You should assign pin locations to the pins in your design, so the Quartus II
software can perform fitting and timing analysis correctly.
b. Use either the Pin Planner or Assignment Editor to assign the clock source pin
manually. Also choose which DQS pin groups should be used by assigning
each DQS pin to the required pin. The Quartus II Fitter then automatically
places the respective DQ signals onto suitable DQ pins within each group.
1
To avoid no-fit errors when you compile your design, ensure that you place
the mem_clk pins to the same edge as the mem_dq and mem_dqs pins, and
set an appropriate I/O standard for the non-memory interfaces, such as the
clock source and the reset inputs, when assigning pins in your design. For
example, for DDR SDRAM select 2.5 V and for DDR2 SDRAM select 1.8 V.
Also select in which bank or side of the device you want the Quartus II
software to place them.
5. For Stratix III and Stratix IV designs, if you are using advanced I/O timing, specify
board trace models in the Device & Pin Options dialog box. If you are using any
other device and not using advanced I/O timing, specify the output pin loading
for all memory interface pins.
6. Select your required I/O driver strength (derived from your board simulation) to
ensure that you correctly drive each signal or ODT setting and do not suffer from
overshoot or undershoot.
7. To compile the design, on the Processing menu, click Start Compilation.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
4–4
Chapter 4: Compile and Simulate
Simulate the Design
f
To attach the SignalTap® II logic analyzer to your design, refer to AN 380: Test DDR or
DDR2 SDRAM Interfaces on Hardware Using the Example Driver.
After you have compiled the example top-level file, you can perform RTL simulation
or program your targeted Altera device to verify the example top-level file in
hardware.
Simulate the Design
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. The MegaWizard also generates a set of
ModelSim Tcl scripts and macros that you can use to compile the testbench, IP
functional simulation models, and plain-text RTL design files that describe your
system in the ModelSim simulation software (refer to “Generated Files” on page 2–6).
f
For more information about simulating SOPC Builder systems, refer to volume 4 of
the Quartus II Handbook and AN 351: Simulating Nios II Systems. For more information
about simulation, refer to the Simulating an External Memory Interface Design section in
volume 4 of the External Memory Interfaces Handbook. For more information about how
to include your board simulation results in the Quartus II software and how to assign
pins using pin planners, refer to DDR, DDR2, and DDR3 Tutorials in volume 6 of the
External Memory Interfaces Handbook.
In ALTMEMPHY variations for DDR or DDR2 SDRAM interfaces, you have the
following simulation options:
■
Skip calibration—Performs a static setup of the ALTMEMPHY megafunction to
skip calibration and go straight into user mode.
1
■
Quick calibration—Performs a calibration on a single pin and chip select.
1
■
1
Skip calibration mode supports the default ALTMEMPHY
parameterization with CAS latency of 3 for DDR memory, and all CAS
latencies for DDR2 memory. The additive latency must be disabled for all
memory types.
You may see memory model warnings about initialization times.
Full calibration—Across all pins and chip selects. This option allows for longer
simulation time.
In quick and skip calibration modes, the ALTMEMPHY megafunction is not able to
cope with any delays, and it simply assumes that all delays in the testbench and
memory model are 0 ps. In order to successfully simulate a design with delays in the
testbench and memory model, you must generate a full calibration mode model in the
MegaWizard Plug-In Manager.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
4–5
Simulating Using NativeLink
To set up simulation using NativeLink for the DDR or DDR2 high-performance
controllers (HPC and HPC II), follow these steps:
1. Create a custom variation with an IP functional simulation model, refer to step 4 in
the “Specify Parameters” section on page 2–4.
2. Set the top-level entity to the example project.
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
3. Set up the Quartus II NativeLink.
a. On the Assignments menu, click Settings. In the Category list, expand EDA
Tool Settings and click Simulation.
b. From the Tool name list, click on your preferred simulator.
1
Check that the absolute path to your third-party simulator executable is set.
On the Tools menu, click Options and select EDA Tools Options.
c. In NativeLink settings, select Compile test bench and click Test Benches.
d. Click New at the Test Benches page to create a testbench.
4. On the New Test Bench Settings dialog box, do the following:
a. Type a name for the Test bench name.
b. In Top level module in test bench, type the name of the automatically
generated testbench, <variation name>_example_top_tb.
1
If you modified the <variation name>_example_top_tb to have a different
port name, you need to change the testbench file with the new port names
as well.
c. In Design instance in test bench, type the name of the top-level instance, dut.
d. Under Simulation period, set Run simulation until all vector simuli are used.
e. Add the testbench files and automatically-generated memory model files. In
the File name field, browse to the location of the memory model and the
testbench, click Open and then click Add. The testbench is
<variation name>_example_top_tb.v; memory model is
<variation name>_mem_model.v.
f
The auto generated generic SDRAM model may be used as a placeholder
for a specific memory vendor supplied model.
f. Select the files and click OK.
5. On the Processing menu, point to Start and click Start Analysis & Elaboration to
start analysis.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
4–6
Chapter 4: Compile and Simulate
Simulate the Design
6. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
Simulation.
1
f
Ensure that the Quartus II EDA Tool Options are configured correctly for
your simulation environment. On the Tools menu, click Options. In the
Category list, click EDA Tool Options and verify the locations of the
executable files.
If your Quartus II project appears to be configured correctly but the example
testbench still fails, check the known issues on the Knowledge Database page before
filing a service request.
IP Functional Simulations
For VHDL simulations with IP functional simulation models, perform the following
steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool from this directory and create the following libraries:
■
altera_mf
■
lpm
■
sgate
■
<device name>
■
altera
■
ALTGXB
■
<device name>_hssi
■
auk_ddr_hp_user_lib
3. Compile the files into the appropriate library (AFI mode) as shown in Table 4–1.
The files are in VHDL93 format.
Table 4–1. Files to Compile—VHDL IP Functional Simulation Models (Part 1 of 2)
Library
File Name
altera_mf
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd
lpm
/eda/sim_lib/220pack.vhd
/eda/sim_lib/220model.vhd
sgate
eda/sim_lib/sgate_pack.vhd
eda/sim_lib/sgate.vhd
<device name>
eda/sim_lib/<device name>_atoms.vhd
eda/sim_lib/<device name>_ components.vhd
eda/sim_lib/<device name>_hssi_atoms.vhd (1)
altera
eda/sim_lib/altera_primitives_components.vhd
eda/sim_lib/altera_syn_attributes.vhd
eda/sim_lib/altera_primitives.vhd
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
4–7
Table 4–1. Files to Compile—VHDL IP Functional Simulation Models (Part 2 of 2)
Library
File Name
ALTGXB (1)
<device name>_mf.vhd
<device name>_mf_components.vhd
<device name>_hssi (1)
<device name>_hssi_components.vhd
<device name>_hssi_atoms.vhd
auk_ddr_hp_user_lib
<QUARTUS ROOTDIR>/
libraries/vhdl/altera/altera_europa_support_lib.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vho
<project directory>/<variation name>_phy.vho
<project directory>/<variation name>.vhd
<project directory>/<variation name>_example_top.vhd
<project directory>/<variation name>_controller_phy.vhd
<project directory>/<variation name>_phy_alt_mem_phy_reconfig.vhd (2)
<project directory>/<variation name>_phy_alt_mem_phy_pll.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq.vhd
<project directory>/<variation name>_example_driver.vhd
<project directory>/<variation name>_ex_lfsr8.vhd
testbench/<variation name>_example_top_tb.vhd
testbench/<variation name>_mem_model.vhd
<project directory>/<variation name>_auk_ddr_hp_controller_wrapper.vho (HPC)
<project directory>/<variation name>_alt_ddrx_controller_wrapper.vho (HPC II)
Note for Table 4–1:
(1) Applicable only for Arria GX, Arria II GX, Stratix GX, Stratix II GX and Stratix IV devices.
(2) Applicable only for Arria GX, Hardcopy II, Stratix II and Stratix II GX devices.
1
If you are targeting Stratix IV devices, you need both the Stratix IV and
Stratix III files (stratixiv_atoms and stratixiii_atoms) to simulate in your
simulator, unless you are using NativeLink.
4. Load the testbench in your simulator with the timestep set to picoseconds.
For Verilog HDL simulations with IP functional simulation models, follow these
steps:
1. Create a directory in the <project directory>\testbench directory.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
4–8
Chapter 4: Compile and Simulate
Simulate the Design
2. Launch your simulation tool from this directory and create the following libraries:
■
altera_mf_ver
■
lpm_ver
■
sgate_ver
■
<device name>_ver
■
altera_ver
■
ALTGXB_ver
■
<device name>_hssi_ver
■
auk_ddr_hp_user_lib
3. Compile the files into the appropriate library as shown in Table 4–2.
Table 4–2. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 1 of 3)
Library
File Name
altera_mf_ver
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v
lpm_ver
/eda/sim_lib/220model.v
sgate_ver
eda/sim_lib/sgate.v
<device name>_ver
eda/sim_lib/<device name>_atoms.v
eda/sim_lib/<device name>_hssi_atoms.v (1)
altera_ver
eda/sim_lib/altera_primitives.v
ALTGXB_ver (1)
<device name>_mf.v
<device name>_hssi_ver (1)
<device name>_hssi_atoms.v
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
4–9
Table 4–2. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 2 of 3)
Library
File Name
auk_ddr_hp_user_lib
<QUARTUS ROOTDIR>/
libraries/vhdl/altera/altera_europa_support_lib.v
alt_mem_phy_defines.v
<project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vo
<project directory>/<variation name>.v
<project directory>/<variation name>_example_top.v
<project directory>/<variation name>_phy.v
<project directory>/<variation name>_controller_phy.v
<project directory>/<variation name>_phy_alt_mem_phy_reconfig.v (2)
<project directory>/<variation name>_phy_alt_mem_phy_pll.v
<project directory>/<variation name>_phy_alt_mem_phy.v
<project directory>/<variation name>_example_driver.v
<project directory>/<variation name>_ex_lfsr8.v
testbench/<variation name>_example_top_tb.v
testbench/<variation name>_mem_model.v
<project directory>/<variation name>_auk_ddr_hp_controller_wrapper.vo (HPC)
<project directory>/<variation name>_alt_ddrx_controller_wrapper.v (HPC II)
<project directory>/alt_ddrx_addr_cmd.v (HPC II)
<project directory>/alt_ddrx_afi_block.v (HPC II)
<project directory>/alt_ddrx_bank_tracking.v (HPC II)
<project directory>/alt_ddrx_clock_and_reset.v (HPC II)
<project directory>/alt_ddrx_cmd_queue.v (HPC II)
<project directory>/alt_ddrx_controller.v (HPC II)
<project directory>/alt_ddrx_csr.v (HPC II)
<project directory>/alt_ddrx_ddr2_odt_gen.v (HPC II)
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
4–10
Chapter 4: Compile and Simulate
Simulate the Design
Table 4–2. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 3 of 3)
Library
File Name
<project directory>/alt_ddrx_avalon_if.v (HPC II)
<project directory>/alt_ddrx_decoder_40.v (HPC II)
<project directory>/alt_ddrx_decoder_72.v (HPC II)
<project directory>/alt_ddrx_decoder.v (HPC II)
<project directory>/alt_ddrx_encoder_40.v (HPC II)
<project directory>/alt_ddrx_encoder_72.v (HPC II)
<project directory>/alt_ddrx_encoder.v (HPC II)
<project directory>/alt_ddrx_input_if.v (HPC II)
<project directory>/alt_ddrx_odt_gen.v (HPC II)
<project directory>/alt_ddrx_state_machine.v (HPC II)
<project directory>/alt_ddrx_timers_fsm.v (HPC II)
<project directory>/alt_ddrx_timers.v (HPC II)
<project directory>/alt_ddrx_wdata_fifo.v (HPC II)
<project directory>/alt_avalon_half_rate_bridge.v (HPC II)
Notes for Table 4–2:
(1) Applicable only for Arria GX, Arria II GX, Stratix GX, Stratix II GX and Stratix IV devices.
(2) Applicable only for Arria GX, Hardcopy II, Stratix II and Stratix II GX devices.
1
If you are targeting Stratix IV devices, you need both the Stratix IV and
Stratix III files (stratixiv_atoms and stratixiii_atoms) to simulate in your
simulator, unless you are using NativeLink.
4. Configure your simulator to use transport delays, a timestep of picoseconds, and
to include all the libraries in Table 4–2.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
5. Functional Description—ALTMEMPHY
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller, and user logic in various Altera devices. The
ALTMEMPHY megafunction GUI helps you configure multiple variations of a
memory interface. You can then connect the ALTMEMPHY megafunction variation
with either a user-designed controller or with an Altera high-performance controller.
In addition, the ALTMEMPHY megafunction and the Altera high-performance
controllers are available for full-rate and half-rate DDR and DDR2 SDRAM interfaces.
1
For legacy device families not supported by the ALTMEMPHY megafunction (such as
Cyclone, Cyclone II, Stratix, and Stratix GX devices), use the Altera legacy integrated
static datapath and controller MegaCore functions.
1
If the ALTMEMPHY megafunction does not meet your requirements, you can also
create your own memory interface datapath using the ALTDLL and ALTDQ_DQS
megafunctions, available in the Quartus II software. However, you are then
responsible for every aspect of the interface, including timing analysis and
debugging.
This chapter describes the DDR and DDR2 SDRAM ALTMEMPHY megafunction,
which uses AFI as the interface between the PHY and the controller.
Block Description
Figure 5–1 on page 5–2 shows the major blocks of the ALTMEMPHY megafunction
and how it interfaces with the external memory device and the controller. The
ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction, so that
you do not need to generate the clock to any of the ALTMEMPHY blocks.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–2
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–1. ALTMEMPHY Megafunction Interfacing with the Controller and the External Memory
FPGA
ALTMEMPHY
Write
Datapath
Address
and
Command
Datapath
External
Memory
Device
Memory
Controller
User
Logic
Clock
and Reset
Management
DLL
PLL
Read
Datapath
Sequencer
The ALTMEMPHY megafunction comprises the following blocks:
■
Write datapath
■
Address and command datapath
■
Clock and reset management, including DLL and PLL
■
Sequencer for calibration
■
Read datapath
Calibration
This section describes the calibration that the sequencer performs, to find the optimal
clock phase for the memory interface.
The ALTMEMPHY variation for DDR/DDR2 SDRAM interfaces has a similar
calibration process for the AFI and non-AFI.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–3
The calibration process for the DDR/DDR2 SDRAM PHY includes the following
steps:
f
■
“Step 1: Memory Device Initialization”
■
“Step 2: Write Training Patterns”
■
“Step 3: Read Resynchronization (Capture) Clock Phase”
■
“Step 4: Read and Write Datapath Timing”
■
“Step 5: Address and Command Clock Cycle”
■
“Step 6: Postamble”
■
“Step 7: Prepare for User Mode”
For more detailed information about each calibration step, refer to the Hardware
Debugging section in volume 4 of the External Memory Interfaces Handbook.
Figure 5–2 shows the calibration flow.
Figure 5–2. Calibration Flow—DDR/DDR2 SDRAM
Memory Device
and PHY Initialization
Write Training
Patterns
Read Resynchronization
Clock Phase
Read and Write
Datapath Timing
Address and Command
Clock Cycle
Postamble
Prepare for User Mode
VT Tracking
© February 2010
Altera Corporation
User Mode
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–4
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Step 1: Memory Device Initialization
This step initializes the memory device according to the DDR and DDR2 SDRAM
specification. The initialization procedure includes specifying the mode registers and
memory device ODT setting (DDR2 only), and initializing the memory device DLL.
Calibration requires overriding some of the user-specified mode register settings,
which are reverted in “Step 7: Prepare for User Mode”.
Step 2: Write Training Patterns
In this step, a pattern is written to the memory to be read in later calibration stages.
The matched trace lengths to DDR SDRAM devices mean that after memory
initialization, write capture functions. The pattern is 0x30F5 and comprises the
following separately written patterns:
1
■
All 0: ‘b0000 - DDIO high and low bits held at 0
■
All 1: ‘b1111 - DDIO high and low bits held at 1
■
Toggle: ‘b0101 - DDIO high bits held at 0 and DDIO low bits held at 1
■
Mixed: ‘b0011 - DDIO high and low bits have to toggle
This pattern is required to match the characterization behavior for non-DQS capturebased schemes, for example, the Cyclone III devices.
Loading a mixed pattern is complex, because the write latency is unknown at this
time. Two sets of write and read operations (single pin resynchronization (capture)
clock phase sweeps, (“Step 3: Read Resynchronization (Capture) Clock Phase”) are
required to accurately write the mixed pattern to memory.
1
Memory bank 0, row 0, and column addresses 0 to 55 store calibration data.
Step 3: Read Resynchronization (Capture) Clock Phase
This step adjusts the phase of the resynchronization (or capture) clock to determine
the optimal phase that gives the greatest margin. For DQS-based capture schemes, the
resynchronization clock captures the outputs of DQS capture registers (DQS is the
capture clock). In a non-DQS capture-based scheme, the capture clock captures the
input DQ pin data (the DQS signal is unused, and there is no resynchronization
clock).
To correctly calibrate resynchronization (or capture) clock phase, based on a data
valid window, requires the following degrees of phase sweep:
■
720° for all half-rate interfaces and full-rate DQS-based capture PHY
■
360° for a full-rate non-DQS capture PHY
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–5
Step 4: Read and Write Datapath Timing
In this step, the sequencer calculates the calibrated write latency (the ctl_wlat
signal) between write commands and write data. The sequencer also calculates the
calibrated read latency (the ctl_rlat signal) between the issue of a read command
and valid read data. Both read and write latencies are output to a controller. In
addition to advertising the read latency, the sequencer calibrates a read data valid
signal to the delay between a controller issuing a read command and read data
returning. The controller can use the read data valid signal in place of the advertised
read latency, to determine when the read data is valid.
Step 5: Address and Command Clock Cycle
For half-rate interfaces, this step also optionally adds an additional memory clock
cycle of delay from the address and command path. This delay aligns write data to
memory commands given in the controller clock domain. If you require this
additional delay, this step reruns the calibration (“Step 2: Write Training Patterns” to
“Step 4: Read and Write Datapath Timing”) to calibrate to the new setting.
Step 6: Postamble
This step sets the correct clock cycle for the postamble path. The aim of the postamble
path is to eliminate false DQ data capture because of postamble glitches on the DQS
signal, through an override on DQS. This step ensures the correct clock cycle timing of
the postamble enable (override) signal.
1
Postamble is only required for DQS-based capture schemes.
Step 7: Prepare for User Mode
In this step, the PHY applies user mode register settings and performs periodic VT
tracking.
VT Tracking
VT tracking is a background process that tracks the voltage and temperature
variations to maintain the relationship between the resynchronization or capture
clock and the data valid window that are achieved at calibration.
When the data calibration phase is completed, the sequencer issues the mimic
calibration sequence every 128 ms.
During initial calibration, the mimic path is sampled using the measure clock
(measure_clk has a _1x or _2x suffix, depending whether the ALTMEMPHY is a
full-rate or half-rate design). The sampled value is then stored by the sequencer. After
a sample value is stored, the sequencer uses the PLL reconfiguration logic to change
the phase of the measure clock by one VCO phase tap. The control sequencer then
stores the sampled value for the new mimic path clock phase. This sequence
continues until all mimic path clock phase steps are swept. After the control
sequencer stores all the mimic path sample values, it calculates the phase which
corresponds to the center of the high period of the mimic path waveform. This
reference mimic path sampling phase is used during the VT tracking phase.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–6
Chapter 5: Functional Description—ALTMEMPHY
Block Description
In user mode, the sequencer periodically performs a tracking operation as defined in
the tracking calibration description. At the end of the tracking calibration operation,
the sequencer compares the most recent optimum tracking phase against the reference
sampling phase. If the sampling phases do not match, the mimic path delays have
changed due to voltage and temperature variations.
When the sequencer detects that the mimic path reference and most recent sampling
phases do not match, the sequencer uses the PLL reconfiguration logic to change the
phase of the resynchronization clock by the VCO taps in the same direction. This
allows the tracking process to maintain the near-optimum capture clock phase setup
during data tracking calibration as voltage and temperature vary over time.
The relationship between the resynchronization or capture clock and the data valid
window is maintained by measuring the mimic path variations due to the VT
variations and applying the same variation to the resynchronization clock.
Mimic Path
The mimic path mimics the FPGA elements of the round-trip delay, which enables the
calibration sequencer to track delay variation due to VT changes during the memory
read and write transactions without interrupting the operation of the ALTMEMPHY
megafunction.
The assumption made about the mimic path is that the VT variation on the round trip
delay path that resides outside of the FPGA is accounted for in the board skew and
memory parameters entered in the MegaWizard Plug-In Manager. For the write
direction, any VT variation in the memory devices is accounted for by timing analysis.
Figure 5–3 shows the mimic path in Arria GX, Cyclone III, Stratix II, and Stratix II GX
devices, which mimics the delay of the clock outputs to the memory as far as the pads
of the FPGA and the delay from the input DQS pads to a register in the FPGA core.
During the tracking operation, the sequencer measures the delay of the mimic path by
varying the phase of the measure clock. Any change in the delay of the mimic path
indicates a corresponding change in the round-trip delay, and a corresponding
adjustment is made to the phase of the resynchronization or capture clock.
1
The mimic path in Arria II GX, Stratix III and Stratix IV devices is similar to
Figure 5–3. The only difference is that the mem_clk[0] pin is generated by DDIO
register; mem_clk_n[0] is generated by signal splitter.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–7
Figure 5–3. Mimic Path in Arria GX, Arria II GX, Cyclone III, Stratix II, and Stratix II GX Devices
datain
1
mem_clk[0]
ddiodatain
0
outclk
mem_clk_2x
combout
ALTPLL
measure_clk
mimic_data_in
alt_mem_phy_mimic
measure_clk
Address and Command Datapath
This topic describes the address and command datapath.
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices
The address and command datapath for full-rate designs is similar to half-rate
designs, except that the address and command signals are all asserted for one
memory clock cycle only (1T signaling).
The address and command datapath is responsible for taking the address and
command outputs from the controller and converting them from half-rate clock to
full-rate clock. Two types of addressing are possible:
f
■
1T (full rate)—The duration of the address and command is a single memory clock
cycle (mem_clk_2x, Figure 5–4). This applies to all address and command signals
in full-rate designs or mem_cs_n, mem_cke, and mem_odt signals in half-rate
designs.
■
2T (half rate)—The duration of the address and command is two memory clock
cycles. For half-rate designs, the ALTMEMPHY megafunction supports only a
burst size of four, which means the burst size on the local interface is always set to
1. The size of the data is 4n-bits wide on the local side and is n-bits wide on the
memory side. To transfer all the 4n-bits at the double data rate, two memory-clock
cycles are required. The new address and command can be issued to memory
every two clock cycles. This scheme applies to all address and command signals,
except for mem_cs_n, mem_cke, and mem_odt signals in half-rate mode.
Refer to Table 5–4 in “PLL” on page 5–9 to see the frequency relationship of
mem_clk_2x with the rest of the clocks.
Figure 5–4 shows a 1T chip select signal (mem_cs_n), which is active low, and
disables the command in the memory device. All commands are masked when the
chip-select signal is inactive. The mem_cs_n signal is considered part of the command
code.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–8
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–4. Arria GX, Arria II GX, Cyclone II, HardCopy III, Stratix II, and Stratix II GX Address and Command Datapath
PHY Command Outputs
ac_clk_2x
Command
NOP
PCH
ACT
NOP
0001
0000
NOP
NOP
WR
mem_ras_n
mem_cas_n
mem_we_n
mem_cs_n
mem_addr
mem_ba
0000
0008
0004
000C
0010
0000
00
mem_dq
mem-dqs
[1] [1]
[2]
[3]
[3] [4]
[4]
[4]
The command interface is made up of the signals mem_ras_n, mem_cas_n,
mem_we_n, mem_cs_n, mem_cke, and mem_odt.
The waveform in Figure 5–4 shows a NOP command followed by back-to-back write
commands. The following sequence corresponds with the numbered items in
Figure 5–4:
1. The commands are asserted either on the rising edge of ac_clk_2x. The
ac_clk_2x is derived from either mem_clk_2x (0°), write_clk_2x (270°), or
the inverted variations of those two clocks (for 180° and 90° phase shifts). This
depends on the setting of the address and command clock in the ALTMEMPHY
MegaWizard interface. Refer to “Address and Command Datapath” on page 5–7
for illustrations of this clock in relation to the mem_clk_2x or write_clk_2x
signals.
2. All address and command signals (except for mem_cs_ns, mem_cke, and
mem_odt signals) remain asserted on the bus for two clock cycles, allowing
sufficient time for the signals to settle.
3. The mem_cs_n, mem_cke, and mem_odt signals are asserted during the second
cycle of the address/command phase. By asserting the chip-select signal in
alternative cycles, back-to-back read or write commands can be issued.
4. The address is incremented every other ac_clk_2x cycle.
1
The ac_clk_2x clock is derived from either mem_clk_2x (when you choose 0° or
180° phase shift) or write_clk_2x (when you choose 90° or 270° phase shift).
1
The address and command clock can be 0, 90, 180, or 270° from the system clock (refer
to “Address and Command Datapath” on page 5–7).
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–9
Stratix III and Stratix IV Devices
The address and command clock in Stratix III and Stratix IV devices is one of the PLL
dedicated clock outputs whose phase can be adjusted to meet the setup and hold
requirements of the memory clock. The Stratix III address and command clock,
ac_clk_1x, is half-rate. The command and address pins use the DDIO output
circuitry to launch commands from either the rising or falling edges of the clock. The
chip select (cs_n) pins and ODT are only enabled for one memory clock cycle and can
be launched from either the rising or falling edge of ac_clk_1x signal, while the
address and other command pins are enabled for two memory clock cycles and can
also be launched from either the rising or falling edge of ac_clk_1x signal.
The full-rate address and command datapath is the same as that of the half-rate
address and command datapath, except that there is no full-rate to half-rate
conversion in the IOE. The address and command signals are full-rate here.
Clock and Reset Management
This topic describes the clock and reset management for specific device types.
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices
The clocking and reset block is responsible for clock generation, reset management,
and phase shifting of clocks. It also has control of clock network types that route the
clocks.
Clock Management
The clock management feature allows the ALTMEMPHY megafunction to work out
the optimum resynchronization clock phase during calibration, and track the system
voltage and temperature (VT) variations. Clock management is achieved by
phase-shifting the clocks relative to each other.
Clock management circuitry is implemented by the following device resources:
■
PLL
■
PLL reconfiguration
■
DLL
PLL
The ALTMEMPHY MegaWizard interface automatically generates an ALTPLL
megafunction instance. The ALTPLL megafunction is responsible for generating the
different clock frequencies and relevant phases used within the ALTMEMPHY
megafunction.
The minimum PHY requirement is to have 16 phases of the highest frequency clock.
The PLL uses the With No Compensation option to minimize jitter.
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
for DDR/DDR2 SDRAM interfaces as jitter can accumulate with the use of cascaded
PLLs causing the memory output clock to violate the memory device jitter
specification. Also, ensure that the input clock to the PLL is stable before the PLL
locks. If not, you must perform a manual PLL reset and relock the PLL to ensure that
the phase relationship between all PLL outputs are properly set.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–10
Chapter 5: Functional Description—ALTMEMPHY
Block Description
1
If the design cascades PLLs, the source (upstream) PLL should have a low-bandwidth
setting; the destination (downstream) PLL should have a high-bandwidth setting.
Adjacent PLLs cascading is recommended to reduce clock jitters.
f
For more information about the VCO frequency range and the available phase shifts,
refer to the PLLs in Stratix II and Stratix II GX Devices chapter in the respective device
family handbook.
Table 5–4 shows the clock outputs for Arria GX, HardCopy II, Stratix II, and
Stratix II GX devices.
Table 5–1. DDR/DDR2 SDRAM Clocking in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices (Part 1 of 3)
Design
Rate
Half-rate
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock
Network Type
C0
0°
Half-Rate
Global
The only clocks
parameterizable for the
ALTMEMPHY
megafunction. These
clocks also feed into a
divider circuit to provide
the PLL scan_clk
signal (for
reconfiguration) that must
be lower than 100 MHz.
C1
0°
Full-Rate
Global
Clocks DQS and as a
reference clock for the
memory devices.
aux_half_rate_
clk
C0
0°
Half-Rate
Global
The only clock
parameterizable for the
ALTMEMPHY
megafunction. This clock
also feeds into a divider
circuit to provide the PLL
scan_clk signal (for
reconfiguration) that must
be lower than 100 MHz.
phy_clk_1x (1)
C1
0°
Full-Rate
Global
Clocks DQS and as a
reference clock for the
memory devices.
Clock Name
phy_clk_1x
and
aux_half_rate_
clk
mem_clk_2x
and
Notes
aux_full_
rate_clk
Full rate
and
mem_clk_2x
and
aux_full_
rate_clk
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–11
Table 5–1. DDR/DDR2 SDRAM Clocking in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices (Part 2 of 3)
Design
Rate
Clock Name
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock
Network Type
Notes
Half-rate
and full rate
write_clk_2x
C2
–90°
Full-Rate
Global
Clocks the data out of the
DDR I/O (DDIO) pins in
advance of the DQS strobe
(or equivalent). As a
result, its phase leads that
of the mem_clk_2x by
90°.
Half-rate
and full rate
mem_clk_ext_2x
C3
> 0°
Full-Rate
Dedicated
This clock is only used if
the memory clock
generation uses dedicated
output pins. Applicable
only in HardCopy II or
Stratix II prototyping for
HardCopy II designs.
Half-rate
and full rate
resync_clk_2x
C4
Calibrated
Full-Rate
Regional
Clocks the
resynchronization
registers after the capture
registers. Its phase is
adjusted to the center of
the data valid window
across all the
DQS-clocked DDIO
groups.
Half-rate
and full rate
measure_clk_2x
C5
Calibrated
Full-Rate
Regional (2)
This clock is for VT
tracking. This free-running
clock measures relative
phase shifts between the
internal clock(s) and those
being fed back through a
mimic path. As a result,
the ALTMEMPHY
megafunction can track
VT effects on the FPGA
and compensate for the
effects.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–12
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–1. DDR/DDR2 SDRAM Clocking in Arria GX, HardCopy II, Stratix II, and Stratix II GX Devices (Part 3 of 3)
Design
Rate
Half-rate
and full rate
Clock Name
ac_clk_2x
Postscale
Counter
Phase
(Degrees)
—
0,
90°,180°,
270°
Clock Rate
Clock
Network Type
Full-Rate
Global
Notes
The ac_clk_2x clock is
derived from either
mem_clk_2x (when you
choose 0° or 180° phase
shift) or
write_clk_2x (when
you choose 90° or 270°
phase shift). Refer to
“Address and Command
Datapath” on page 5–7 for
illustrations of the address
and command clock
relationship with the
mem_clk_2x or
write_clk_2x
signals.
Notes to Table 5–4:
(1) In full-rate designs a _1x clock may run at full rate clock.
(2) This clock should be of the same clock network clock as the resync_clk_2x clock.
For full-rate clock and reset management refer to Table 5–4. The PLL is configured
exactly in the same way as in half-rate designs. The PLL information and restriction
from half-rate designs also applies.
1
The phy_clk_1x clock is now full-rate, despite the “1x” naming convention.
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
for DDR/DDR2 SDRAM interfaces as jitter can accumulate with the use of cascaded
PLLs causing the memory output clock to violate the memory device jitter
specification. Also, ensure that the input clock to the PLL is stable before the PLL
locks. If not, you must perform a manual PLL reset and relock the PLL to ensure that
the phase relationship between all PLL outputs are properly set. The PLL restrictions
in half-rate designs also applies to full-rate designs.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–13
Table 5–2 shows the clock outputs that Arria II GX devices use.
Table 5–2. DDR/DDR2 SDRAM Clocking in Arria II GX Devices (Part 1 of 2)
Design
Rate
Half-rate
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock
Network Type
C0
0°
Half-Rate
Global
The only clock
parameterizable for the
ALTMEMPHY
megafunction. This clock
also feeds into a divider
circuit to provide the PLL
scan_clk signal (for
reconfiguration) that must
be lower than 100 MHz.
C1
0°
Full-Rate
Global
Clocks DQS and as a
reference clock for the
memory devices.
aux_half_rate_
clk
C0
0°
Half-Rate
Global
The only clock
parameterizable for the
ALTMEMPHY
megafunction. This clock
also feeds into a divider
circuit to provide the PLL
scan_clk signal (for
reconfiguration) that must
be lower than 100 MHz.
phy_clk_1x (1)
C1
0°
Full-Rate
Global
Clocks DQS and as a
reference clock for the
memory devices.
Clock Name (1)
phy_clk_1x
and
aux_half_rate_
clk
mem_clk_2x
and
Notes
aux_full_
rate_clk
Full rate
and
mem_clk_2x
and
aux_full_
rate_clk
Half-rate
and full rate
Unused
C2
—
—
—
Half-rate
and full rate
write_clk_2x
C3
–90°
Full-Rate
Global
© February 2010
Altera Corporation
—
Clocks the data out of the
DDR I/O (DDIO) pins in
advance of the DQS strobe
(or equivalent). As a
result, its phase leads that
of the mem_clk_2x by
90°.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–14
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–2. DDR/DDR2 SDRAM Clocking in Arria II GX Devices (Part 2 of 2)
Design
Rate
Half-rate
and full rate
Clock Name (1)
ac_clk_2x
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock
Network Type
C3
90°
Full-Rate
Global
Notes
Address and command
clock.
The ac_clk_2x clock is
derived from either
mem_clk_2x (when you
choose 0° or 180° phase
shift) or
write_clk_2x (when
you choose 90° or 270°
phase shift). Refer tp
“Address and Command
Datapath” on page 5–7 for
illustrations of the address
and command clock
relationship with the
mem_clk_2x or
write_clk_2x
signals.
Half-rate
and full rate
cs_n_clk_2x
C3
90°
Full-Rate
Global
Memory chip-select clock.
Half-rate
and full rate
resync_clk_2x
C4
Calibrated
Full-Rate
Global
Clocks the
resynchronization
registers after the capture
registers. Its phase is
adjusted to the center of
the data valid window
across all the
DQS-clocked DDIO
groups.
Half-rate
and full rate
measure_clk_2x
C5
Calibrated
Full-Rate
Global
This clock is for VT
tracking. This free-running
clock measures relative
phase shifts between the
internal clock(s) and those
being fed back through a
mimic path. As a result,
the ALTMEMPHY
megafunction can track
VT effects on the FPGA
and compensate for the
effects.
The cs_n_clk_2x
clock is derived from
ac_clk_2x.
Note to Table 5–2:
(1) In full-rate designs, a _1x clock may run at full-rate clock rate.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–15
PLL Reconfiguration
The ALTMEMPHY MegaWizard interface automatically generates the PLL
reconfiguration block by instantiating an ALTPLL_RECONFIG variation for Stratix II
and Stratix II GX devices to match the generated ALTPLL megafunction instance. The
ALTPLL_RECONFIG megafunction varies the resynchronization clock phase and the
measure clock phase.
1
The ALTMEMPHY MegaWizard interface does not instantiate an
ALTPLL_RECONFIG megafunction for Arria II GX devices, as this device uses the
dedicated phase stepping I/O on the PLL.
DLL
A DLL instance is included in the generated ALTMEMPHY variation. When using the
DQS to capture the DQ read data, the DLL center-aligns the DQS strobe to the DQ
data. The DLL settings depend on the interface clock frequency.
f
For more information, refer to the External Memory Interfaces chapter in the device
handbook for your target device family.
Reset Management
The reset management block is responsible for the following:
■
Provides appropriately timed resets to the ALTMEMPHY megafunction datapaths
and functional modules
■
Performs the reset sequencing required for different clock domains
■
Provides reset management of PLL and PLL reconfiguration functions
■
Manages any circuit-specific reset sequencing
Each reset is an asynchronous assert and synchronous deassert on the appropriate
clock domain. The reset management design uses a standard two-register
synchronizer to avoid metastability. A unique reset metastability protection circuit for
the clock divider circuit is required because the phy_clk domain reset metastability
protection flipflops have fan-in from the soft_reset_n input, and so these registers
cannot be used.
Figure 5–5 shows the ALTMEMPHY reset management block for Arria GX,
Arria II GX, HardCopy II, Stratix II, and Stratix II GX devices. The pll_ref_clk
signal goes directly to the PLL, eliminating the need for global clock network routing.
If you are using the pll_ref_clk signal to feed other parts of your design, you must
use a global clock network for the signal. If pll_reconfig_soft_reset_en signal
is held low, the PLL reconfig is not reset during a soft reset, which allows designs
targeting HardCopy II devices to hold the PHY in reset while still accessing the PLL
reconfig block. However, designs targeting Arria GX, Arria II GX, or Stratix II devices
are expected to tie the pll_reconfig_soft_en shell to VCC to enable PLL reconfig
soft resets.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–16
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Figure 5–5. ALTMEMPHY Reset Management Block for Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices (Note 1)
phy_clk
clk_div_reset_ams_n_r
D SET Q
clk_div_reset_ams_n
D SET Q
clk
divider
circuit
clk_divider_reset_n reset_n
PLL
reconfig
pll_reconfig_reset_ams_n
D SET Q
D SET Q
CLR Q
CLR Q
reset
scan_clk
CLR Q
CLR Q
pll_reconfig_reset_ams_n_r
scan_clk
pll_locked
pll_reconfig_reset_n
reset_request_n
locked
Another
system
clock
pll_ref_clk
reset_master_ams global_pre_clear
refclk
PLL
Optional
reset_request_n
edge detect and
reset counter
global_reset_n
D SET Q
D SET Q
CLR Q
CLR Q
pll_reset
areset (active HIGH)
phy_clk_out
c0
pll_reconfig_soft_reset_en
soft_reset_n
global_or_soft_reset_n
phy_internal_reset_n
Reset
pipes
PHY resets
(1) The reset circuit for Arria II GX and Cyclone III devices have no PLL reconfig block.
© February 2010 Altera Corporation
Cyclone III Devices
Clock management circuitry is implemented using the ALTPLL megafunction.
The ALTPLL megafunction is instantiated within the ALTMEMPHY megafunction and is responsible for generating all the
clocks used by the ALTMEMPHY megafunction and the memory controller.
The minimum PHY requirement is to have 48 phases of the highest frequency clock. The PLL uses Normal mode, unlike other
device families. Cyclone III PLL in normal mode emits low jitter already such that you do not require to set the PLL in the With
no compensation option. Changing the PLL compensation mode may result in inaccurate timing results.
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Note to Figure 5–5:
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–17
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
as jitter can accumulate with the use of cascaded PLLs causing the memory output
clock to violate the memory device jitter specification. Also, ensure that the input
clock to the PLL is stable before the PLL locks. If not, you must perform a manual PLL
reset and relock the PLL to ensure that the phase relationship between all PLL outputs
are properly set.
Table 5–3 lists the clocks generated by the ALTPLL megafunction.
Table 5–3. DDR/DDR2 SDRAM Clocking in Cyclone III Devices (Part 1 of 2) (Part 1 of 2)
Post-Scale
Counter
Phase
(Degrees)
Clock
Rate
Clock
Network
Type
C0
0°
Half-Rate
Global
The only half-rate clock
parameterizable for the
ALTMEMPHY megafunction to
be used by the controller. This
clock is not used in full-rate
controllers. This clock also
feeds into a divider circuit to
provide the PLL scan_clk
signal for reconfiguration.
C1
0°
Full-Rate
Global
Generates DQS signals and the
memory clock and to clock the
PHY in full-rate mode.
aux_half_rate_
clk
C0
0°
Half-Rate
Global
The only half-rate clock
parameterizable for the
ALTMEMPHY megafunction to
be used by the controller. This
clock is not used in full-rate
controllers. This clock also
feeds into a divider circuit to
provide the PLL scan_clk
signal for reconfiguration.
phy_clk_1x
C1
0°
Full-Rate
Global
Generates DQS signals and the
memory clock and to clock the
PHY in full-rate mode.
C2
-90°
Full-Rate
Global
Clocks the data (DQ) when you
perform a write to the memory.
Design
Rate
Half-rate
Clock Name
phy_clk_1x
and
aux_half_rate_
clk
mem_clk_2x
and
Notes
aux_full_
rate_clk
Full rate
and
mem_clk_2x
and
aux_full_
rate_clk
Half-rate
and full rate
write_clk_2x
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–18
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–3. DDR/DDR2 SDRAM Clocking in Cyclone III Devices (Part 2 of 2) (Part 2 of 2)
Clock Name
Post-Scale
Counter
Phase
(Degrees)
Clock
Rate
Clock
Network
Type
Half-rate
and full rate
resynch_clk_2x
C3
Calibrated
Full-Rate
Global
A full-rate clock that captures
and resynchronizes the
captured read data. The capture
and resynchronization clock has
a variable phase that is
controlled via the PLL
reconfiguration logic by the
control sequencer block.
Half-rate
and full rate
measure_clk_2x
C4
Calibrated
Full-Rate
Global
This clock is for VT tracking.
This free-running clock
measures relative phase shifts
between the internal clock(s)
and those being fed back
through a mimic path. As a
result, you can track VT effects
on the FPGA and compensate
for them.
Half-rate
and full rate
ac_clk_2x
—
0°, 90°,
180°, 270°
Full-Rate
Global
This clock is derived from
mem_clk_2x when you
choose 0° or 180° phase shift)
or write_clk_2x (when you
choose 90° or 270° phase
shift), refer to “Address and
Command Datapath” on
page 5–7.
Design
Rate
Notes
Reset Management
The reset management for Cyclone III devices is instantiated in the same way as it is
with Stratix II devices.
Stratix III and Stratix IV Devices
The clocking and reset block is responsible for clock generation, reset management,
and phase shifting of clocks. It also has control of clock network types that route the
clocks.
The ability of the ALTMEMPHY megafunction to work out the optimum phase
during calibration and to track voltage and temperature variation relies on phase
shifting the clocks relative to each other.
1
Certain clocks need to be phase shifted during the ALTMEMPHY megafunction
operation.
Clock management circuitry is implemented by using:
■
PLL
■
DLL
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–19
PLL
The ALTMEMPHY MegaWizard interface automatically generates an ALTPLL
megafunction instance. The ALTPLL megafunction is responsible for generating the
different clock frequencies and relevant phases used within the ALTMEMPHY
megafunction.
The device families available have different PLL capabilities. The minimum PHY
requirement is to have 16 phases of the highest frequency clock. The PLL uses With
No Compensation operation mode to minimize jitter. Changing the PLL
compensation mode may result in inaccurate timing results.
You must choose a PLL and PLL input clock pin that are located on the same side of
the device as the memory interface to ensure minimal jitter. Cascaded PLLs are not
recommended as jitter can accumulate, causing the memory output clock to violate
the memory device jitter specification. Also, ensure that the input clock to the PLL is
stable before the PLL locks. If not, you must perform a manual PLL reset (by driving
the global_reset_n signal low) and relock the PLL to ensure that the phase
relationship between all PLL outputs are properly set.
f
For more information about the VCO frequency range and the available phase shifts,
refer to the Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the
Stratix III Device Handbook or the Clock Networks and PLLs in Stratix IV Devices chapter
in volume 1 of the Stratix IV Device Handbook.
For Stratix IV and Stratix III devices, the PLL reconfiguration is done using the
phase-shift inputs on the PLL instead of using the PLL reconfiguration megafunction.
Table 5–4 shows the Stratix IV and Stratix III PLL clock outputs.
Table 5–4. DDR2 SDRAM Clocking in Stratix IV and Stratix III Devices (Part 1 of 3)
Design Rate
Half-rate
Clock Name (1)
phy_clk_1x
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock Network
Type
C0
30
Half-Rate
Global
The only clock
parameterizable for the
ALTMEMPHY
megafunction. It is set to
30° to ensure proper
half-rate to full-rate
transfer for write data and
DQS. This clock also feeds
into a divider circuit to
provide the PLL
scan_clk signal for
reconfiguration.
C2
60
Full-Rate
Global
The aux_clk. The
60°-offset maintains edge
alignment with the offset
on phy_clk_1x.
and
aux_half_
rate_clk
aux_full_
rate_clk
© February 2010
Altera Corporation
Notes
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–20
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Table 5–4. DDR2 SDRAM Clocking in Stratix IV and Stratix III Devices (Part 2 of 3)
Design Rate
Full-rate
Clock Name (1)
aux_half_
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock Network
Type
C0
0
Half-Rate
Global
The aux_clk.
C2
0
Full-Rate
Global
The only clock
parameterizable for the
ALTMEMPHY
megafunction. This clock
also feeds into a divider
circuit to provide the PLL
scan_clk signal for
reconfiguration.
Notes
rate_clk
phy_clk_1x
and
aux_full_
rate_clk
Half-rate and
full-rate
mem_clk_2x
C1
0
Full-Rate
Special
Generates mem_clk that
provides the reference
clock for the DLL. A
dedicated routing resource
exists from the PLL to the
DLL, which you select with
the regional routing
resource for the
mem_clk using the
following attribute in the
HDL:
(-name
global_signal
dual_regional
_clock;
-to dll~DFFIN
-name
global_signal
off). If you use an
external DLL, apply this
attribute similarly to the
external DLL.
Half-rate and
full-rate
write_clk_
C3
–90
Full-Rate
Dual regional
Clocks the data out of the
double data rate
input/output (DDIO) pins
in advance of the DQS
strobe (or equivalent). As
a result, its phase leads
that of the mem_clk_2x
clock by 90°.
2x
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–21
Table 5–4. DDR2 SDRAM Clocking in Stratix IV and Stratix III Devices (Part 3 of 3)
Design Rate
Clock Name (1)
Postscale
Counter
Phase
(Degrees)
Clock Rate
Clock Network
Type
Half-rate and
full-rate
resync_clk_
C4
Calibrated
Full-Rate
Dual regional
This clock feeds the I/O
clock divider that then
clocks the
resynchronization
registers after the capture
registers. Its phase is
adjusted in the calibration
process. You can use an
inverted version of this
clock for postamble
clocking.
Half-rate and
full-rate
measure_clk
_1x (2)
C5
Calibrated
Half-Rate
Dual regional
This clock is for VT
tracking. This free-running
clock measures relative
phase shifts between the
internal clock(s) and those
being fed back through a
mimic path. As a result,
the ALTMEMPHY
megafunction can track VT
effects on the FPGA and
compensate for the
effects.
Half-rate and
full-rate
ac_clk_1x
C6
Set in the
GUI
Half-Rate
Dual regional
Address and command
clock.
2x
Notes
Notes to Table 5–4:
(1) In full-rate designs a _1x clock may run at full-rate clock rate.
(2) This clock should be of the same clock network clock as the resync_clk_2x clock.
Clock and reset management for full-rate designs is similar to half-rate support (see
Table 5–4 on page 5–19). The PLL is configured exactly in the same way as for
half-rate support. The mem_clk_2x output acts as the PHY full-rate clock. Also,
instead of going through the I/O clock divider, the resync_clk_2x output is now
directly connected to the resynchronization registers. The rest of the PLL outputs are
connected in the same way as for half-rate support.
You must choose a PLL and PLL input clock pin that are located on the same side of
the device as the memory interface to ensure minimal jitter. Cascaded PLLs are not
recommended as jitter can accumulate, causing the memory output clock to violate
the memory device jitter specification. Also, ensure that the input clock to the PLL is
stable before the PLL locks. If not, you must perform a manual PLL reset (by driving
the global_reset_n signal low) and relock the PLL to ensure that the phase
relationship between all PLL outputs are properly set. The PLL restrictions in half-rate
designs also applies to full-rate designs.
DLL
DLL settings are set depending on the memory clock frequency of operation.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–22
Chapter 5: Functional Description—ALTMEMPHY
Block Description
f
For more information on the DLL, refer to the External Memory Interfaces in Stratix III
Devices chapter in volume 1 of the Stratix III Device Handbook and the External Memory
Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.
Reset Management
Figure 5–6 shows the main features of the reset management block for the DDR3
SDRAM PHY. You can use the pll_ref_clk input to feed the optional
reset_request_n edge detect and reset counter module. However, this requires the
pll_ref_clk signal to use a global clock network resource.
There is a unique reset metastability protection circuit for the clock divider circuit
because the phy_clk domain reset metastability protection registers have fan-in
from the soft_reset_n input so these registers cannot be used.
Figure 5–6. ALTMEMPHY Reset Management Block for Stratix IV and Stratix III Devices
phy_clk
clk_div_reset_ams_n_r
D SET Q
D SET Q
pll_reconfig_reset_ams_n
clk
divider
circuit
clk_divider_reset_n reset_n
D SET Q
D SET Q
CLR Q
CLR Q
Internal reset signal
signal for the
PLL clock-domain
crossing registers
scan_clk
CLR Q
CLR Q
clk_div_reset_ams_n
pll_reconfig_reset_ams_n_r
pll_locked
pll_reconfig_reset_n
reset_request_n
locked
pll_ref_clk
Another
system
clock
reset_master_ams
refclk
PLL
Optional
reset_request_n
edge detect and
reset counter, not
created by the PHY
global_reset_n
pll_reset
areset
(active HIGH)
global_pre_clear
D SET Q
D SET Q
CLR Q
CLR Q
phy_clk_out
c0
soft_reset_n
global_or_soft_reset_n
phy_internal_reset_n
Reset
Pipes
PHY resets
Read Datapath
This topic describes the read datapath.
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices
The following section discusses support for DDR/DDR2 SDRAM for
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX devices.
The full-rate datapath is similar to the half-rate datapath. The full-rate datapath also
consists of a RAM with the same width as the data input (just like that of the
half-rate), but the width on the data output of the RAM is half that of the half-rate
PHY. The function of the RAM is to transfer the read data from the resynchronization
clock domain to the system clock domain.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–23
The read datapath logic is responsible for capturing data sent by the memory device
and subsequently aligning the data back to the system clock domain. The following
functions are performed by the read datapath:
1. Data capture and resynchronization
2. Data demultiplexing
3. Data alignment
Figure 5–7 shows the order of the functions performed by the read datapath, along
with the frequency at which the read data is handled.
Figure 5–7. DDR/DDR2 SDRAM Read Datapath in Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX
Devices (Note 1)
DDR
SDR
SDR/HDR
Data Resynchronization
Data Capture
IOE
Data Demux and Alignment
DQS
DQ[n]
rdata_2x_p[n]
D
Q
D
Q
D
Q
wr_data[2n] rd_data[4n]
wr_clk
rdata_1x[4n]
rd_clk
rdata_2x_n[n]
D
Q
D
Q
FIFO
phy_clk_1x
resync_clk_2x
Note to Figure 5–7:
(1) In Arria II GX devices the resynchronization register is implemented in IOE.
Data Capture and Resynchronization
Data capture and resynchronization is the process of capturing the read data (DQ)
with the DQS strobe and re-synchronizing the captured data to an internal
free-running full-rate clock supplied by the enhanced phase-locked loop (PLL).
The resynchronization clock is an intermediate clock whose phase shift is determined
during the calibration stage.
Timing constraints ensure that the data resynchronization registers are placed close to
the DQ pins to achieve maximum performance. Timing constraints also further limit
skew across the DQ pins. The captured data (rdata_2x_p and rdata_2x_n) is
synchronized to the resynchronization clock (resync_clk_2x), refer to Figure 5–7.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–24
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Data Demultiplexing
Data demultiplexing is the process of SDR data into HDR data. Data demultiplexing
is required to bring the frequency of the resynchronized data down to the frequency
of the system clock, so that data from the external memory device can ultimately be
brought into the FPGA DDR or DDR2 SDRAM controller clock domain. Before data
capture, the data is DDR and n-bit wide. After data capture, the data is SDR and 2n-bit
wide. After data demuxing, the data is HDR of width 4n-bits wide. The system clock
frequency is half the frequency of the memory clock.
Demultiplexing is achieved using a dual-port memory with a 2n-bit wide write-port
operating on the resynchronization clock (SDR) and a 4n-bit wide read-port operating
on the PHY clock (HDR). The basic principle of operation is that data is written to the
memory at the SDR rate and read from the memory at the HDR rate while
incrementing the read- and write-address pointers. As the SDR and HDR clocks are
generated, the read and write pointers are continuously incremented by the same
PLL, and the 4n-bit wide read data follows the 2n-bit wide write data with a constant
latency.
Read Data Alignment
Data alignment is the process controlled by the sequencer to ensure the correct
captured read data is present in the same half-rate clock cycle at the output of the read
data DPRAM. Data alignment is implemented using either M4K or M512K memory
blocks. The bottom of Figure 5–8 shows the concatenation of the read data into valid
HDR data.
Postamble Protection
The ALTMEMPHY megafunction provides the DQS postamble logic. The postamble
clock is derived from the resynchronization clock and is the negative edge of the
resynchronization clock. The ALTMEMPHY megafunction calibrates the
resynchronization clock such that it is in the center of the data-valid window. The
clock that controls the postamble logic, the postamble clock, is the negative edge of
the resynchronization clock. No additional clocks are required. Figure 5–8 shows the
relationship between the postamble clock and the resynchronization clock.
Figure 5–8. Relationship Between Postamble Clock and Resynchronization Clock (Note 1)
resync_clk_2x
postamble_clk
dqs (90˚ shifted)
dq
Data input to resync reg's
H1
L1
L2
H2
H1L1
H2L2
ARST at postamble reg's
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–25
Figure 5–8. Relationship Between Postamble Clock and Resynchronization Clock (Note 1)
Note to Figure 5–8:
(1) resync_clk_2x is delayed further to allow for the I/O element (IOE) to core transition time.
f
For more information about the postamble circuitry, refer to the External Memory
Interfaces chapter in the Stratix II Device Handbook.
Cyclone III Devices
Figure 5–9 shows the Cyclone III read datapath for a single DQ pin. The diagram
shows a half-rate read path where four data bits are produced for each DQ pin. Unlike
Stratix® II and Stratix III devices, data capture is entirely done in the core logic
because the I/O element (IOE) does not contain DDIO capture registers (nonDQS
capture).
Figure 5–9. Cyclone III Read Datapath
Data Pipeline Registers
Data Capture
DQ
D
D
Q
Q
Data Demux & Alignment
4-bits
wr_data
rd_data
read_data
FIFO
phy_clk
D
Q
D
Q
D
Q
resync_clk_2x
The full-rate read datapath for Cyclone III devices is similar to the half-rate
Cyclone III implementation, except that the data is read out of the FIFO buffer with a
full-rate clock instead of a half-rate clock.
Capture and Pipelining
The DDR and DDR2 SDRAM read data is captured using registers in the Cyclone III
FPGA core. These capture registers are clocked using the capture clock
(resynch_clk_2x). The captured read data generates two data bits per DQ pin; one
data bit for the read data captured by the rising edge of the capture clock and one data
bit for the read data captured by the falling edge of the capture clock.
After the read data has been captured, it may be necessary to insert registers in the
read datapath between the capture registers and the read data FIFO buffer to help
meet timing. These registers are known as pipeline registers and are clocked off the
same clock used by the capture registers, the capture clock (resync_clk_2x).
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
Block Description
Data Demultiplexing
The data demultiplexing for Cyclone III devices is instantiated in the same way as it is
with Stratix II devices.
Postamble Protection
Postamble protection circuitry is not required in the Cyclone III device
implementation as DQS mode capture of the DQ data is not supported. The data
capture is done using the clock (resync_clk_2x) generated from the ALTPLL
megafunction.
Stratix III and Stratix IV Devices
Stratix IV and Stratix III devices support half-rate or full-rate DDR/DDR2 SDRAM.
The Stratix IV and Stratix III read datapath (Figure 5–10) consists of two main blocks:
■
Data capture, resynchronization, and demultiplexing
■
Read datapath logic (read datapath)
Figure 5–10. DDR/DDR2 SDRAM Data Capture and Read Data Mapping in Stratix IV and Stratix III Devices
Data Capture, Resynchronization,
and Data Demultiplexing
Read Datapath
dio_rdata3_1x
dio_rdata2_1x
IOE
dio_rdata1_1x
mem_dq
ram_rdata_1x[4n]
Dual Port RAM
4n bits
wr_data rd_data
dio_rdata0_1x
mem_dqs
wr_clk
Data
Mapping
Logic
ctl_rdata
rd_clk
resync_clk_1x
mem_dqsn
phy_clk_1x
Note to Figure 5–10:
(1) This figure shows a half-rate variation. For a full-rate controller, dio_radata2_1x and dio_rdata3_1x are unconnected.
Data Capture, Resynchronization, and Demultiplexing
In Stratix IV and Stratix III devices, the smart interface module in the IOE performs
the following tasks:
■
Captures the data
■
Resynchronizes the captured data from the DQS domain to the resynchronization
clock (resync_clk_1x) domain
■
Converts the resynchronized data into half-rate data, which is performed by
feeding the resynchronized data into the HDR conversion block within the IOE,
which is clocked by the half-rate version of the resynchronization clock. The
resync_clk_1x signal is generated from the I/O clock divider module based on
the resync_clk_2x signal from the PLL.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
f
5–27
For more information about IOE registers, refer to the External Memory Interfaces in
Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook and the
External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV
Device Handbook.
Data Resynchronization
The read datapath block performs the following two tasks:
1. Transfers the captured read data (rdata[n]_1x) from the half-rate
resynchronization clock (resync_clk_1x) domain to the half-rate system clock
(phy_clk_1x) domain using DPRAM. Resynchronized data from the FIFO buffer
is shown as ram_data_1x.
2. Reorders the resynchronized data (ram_rdata_1x) into ctl_mem_rdata.
The full-rate datapath is similar to the half-rate datapath, except that the
resynchronization FIFO buffer converts from the full-rate resynchronization clock
domain (resync_clk_2x) to the full-rate PHY clock domain, instead of converting it
to the half-rate PHY clock domain as in half-rate designs.
Postamble Protection
A dedicated postamble register controls the gating of the shifted DQS signal that
clocks the DQ input registers at the end of a read operation. This ensures that any
glitches on the DQS input signals at the end of the read postamble time do not cause
erroneous data to be captured as a result of postamble glitches. The postamble path is
also calibrated to determine the correct clock cycle, clock phase shift, and delay chain
settings. You can see the process in simulation if you choose Full calibration (long
simulation time) mode in the MegaWizard Plug-In Manager.
f
For more information about the postamble protection circuitry, refer to the External
Memory Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device
Handbook and the External Memory Interfaces in Stratix IV Devices chapter in volume 1
of the Stratix IV Device Handbook.
Write Datapath
This topic describes the write datapath.
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX Devices
The write datapath logic efficiently transfers data from the HDR memory controller to
DDR SDRAM-based memories. The write datapath logic consists of:
■
DQ and DQ output-enable logic
■
DQS and DQS output-enable logic
■
Data mask (DM) logic
The memory controller interface outputs 4n-bit wide data (ctl_wdata[4n]) at
half-rate frequency. Figure 5–11 shows that the HDR write data (ctl_wdata[4n]) is
clocked by the half-rate clock phy_clk_1x and is converted into SDR which is
represented by wdp_wdata_h and wdp_wdata_l and clocked by the full-rate clock
write_clk_2x.
The DQ IOEs convert 2-n SDR bits to n-DDR bits.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–11. DDR/DDR2 SDRAM Write Datapath in Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX
Devices
Write Datapath
Stratix II IOE
wdp_wdata_h
OE
Q
D
ctl_wdata[4n]
DQ[n]
Data
Multiplexing
wdp_wdata_l
Q
phy_clk_1x (ctl_clk)
write_clk_2x
D
write_clk_2x
The write datapath for full-rate PHYs is similar to the half-rate PHY. The IOE block is
identical to the half-rate PHY. The latency of the write datapath in the full-rate PHY is
less than in the half-rate PHY because the full-rate PHY does not have the
half-rate-to-full-rate conversion logic.
Stratix III and Stratix IV Devices
The memory controller interface outputs 4 n-bit wide data (ctl_wdata) at
phy_clk_1x frequency. The write data is clocked by the system clock phy_clk_1x
at half data rate and reordered into HDR of width 4 n-bits represented in Figure 5–12
by wdp_wdata3_1x, wdp_wdata2_1x, wdp_wdata1_1x, and wdp_wdata0_1x.
Figure 5–12. DDR and DDR2 SDRAM Write Datapath in Stratix IV and Stratix III Devices
HDR to DDR
Conversion
Data Ordering
wdp_wdata3_1x
mem_dq
Stratix III
IOE
wdp_wdata2_1x
wdp_wdata1_1x
ctl_wdata[4n]
Data
Ordering
phy_clk_1x
wdp_wdata0_1x
write_clk_2x
phy_clk_1x
All of the write datapath registers in the Stratix IV and Stratix III devices are clocked
by the half-rate clock, phy_clk_1x.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
1
5–29
For full-rate controllers, phy_clk_1x runs at full rate and there are only two bits of
wdata.
The write datapath for full-rate PHYs is similar to the half-rate PHY. The IOE block is
identical to the half-rate PHY. The latency of the write datapath in the full-rate PHY is
less than in the half-rate PHY because the full-rate PHY does not have half-rate to
full-rate conversion logic.
f
For more information about the Stratix III I/O structure, refer to the External Memory
Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook and
the External Memory Interfaces in Stratix IV Devices chapter in volume 1 of the Stratix IV
Device Handbook.
ALTMEMPHY Signals
This section describes the ALMEMPHY megafunction ports for AFI variants.
Table 5–5 through Table 5–7 show the signals.
1
Signals with the prefix mem_ connect the PHY with the memory device; signals with
the prefix ctl_ connect the PHY with the controller.
The signal lists include the following signal groups:
■
I/O interface to the SDRAM devices
■
Clocks and resets
■
External DLL signals
■
User-mode calibration OCT control
■
Write data interface
■
Read data interface
■
Address and command interface
■
Calibration control and status interface
■
Debug interface
Table 5–5. Interface to the SDRAM Devices (Note 1)
Signal Name
Type
Width (2)
Description
mem_addr
Output
MEM_IF_ROWADDR_WIDTH
The memory row and column address bus.
mem_ba
Output
MEM_IF_BANKADDR_WIDTH
The memory bank address bus.
mem_cas_n
Output
1
The memory column address strobe.
mem_cke
Output
MEM_IF_CS_WIDTH
The memory clock enable.
mem_clk
Bidirectional
MEM_IF_CLK_PAIR_COUNT
The memory clock, positive edge clock. (3)
mem_clk_n
Bidirectional
MEM_IF_CLK_PAIR_COUNT
The memory clock, negative edge clock.
mem_cs_n
Output
MEM_IF_CS_WIDTH
The memory chip select signal.
mem_dm
Output
MEM_IF_DM_WIDTH
The optional memory DM bus.
mem_dq
Bidirectional
MEM_IF_DWIDTH
The memory bidirectional data bus.
© February 2010
Altera Corporation
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Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Table 5–5. Interface to the SDRAM Devices (Note 1)
Signal Name
Type
Width (2)
Description
mem_dqs
Bidirectional
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
The memory bidirectional data strobe bus.
mem_dqsn
Bidirectional
MEM_IF_DWIDTH/
MEM_IF_DQ_PER_DQS
The memory bidirectional data strobe bus.
mem_odt
Output
MEM_IF_CS_WIDTH
The memory on-die termination control signal.
mem_ras_n
Output
1
The memory row address strobe.
mem_reset_n Output
1
The memory reset signal.
Output
1
The memory write enable signal.
mem_we_n
Notes to Table 5–5:
(1) Connected to I/O pads.
(2) Refer to Table 5–8 for parameter description.
(3) Output is for memory device, and input path is fed back to ALTMEMPHY megafunction for VT tracking.
Table 5–6. AFI Signals (Part 1 of 3)
Signal Name
Type
Width (1)
Description
Clocks and Resets
pll_ref_clk
Input
1
The reference clock input to the PHY PLL.
global_reset_n
Input
1
Active-low global reset for PLL and all logic in the
PHY. A level set reset signal, which causes a complete
reset of the whole system. The PLL may maintain
some state information.
soft_reset_n
Input
1
Edge detect reset input intended for SOPC Builder use
or to be controlled by other system reset logic.
Causes a complete reset of PHY, but not the PLL used
in the PHY.
reset_request_n
Output
1
Directly connected to the locked output of the PLL
and is intended for optional use either by automated
tools such as SOPC Builder or could be manually
ANDed with any other system-level signals and
combined with any edge detect logic as required and
then fed back to the global_reset_n input.
Reset request output that indicates when the PLL
outputs are not locked. Use this as a reset request
input to any system-level reset controller you may
have. This signal is always low while the PLL is
locking (but not locked), and so any reset logic using
it is advised to detect a reset request on a falling-edge
rather than by level detection.
ctl_clk
Output
1
Half-rate clock supplied to controller and system
logic. The same signal as the non-AFI phy_clk.
ctl_reset_n
Output
1
Reset output on ctl_clk clock domain.
Output
1
In half-rate designs, a copy of the phy_clk_1x
signal that you can use in other parts of your design,
same as phy_clk port.
Other Signals
aux_half_rate_clk
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
5–31
Table 5–6. AFI Signals (Part 2 of 3)
Signal Name
Type
Width (1)
Description
aux_full_rate_clk
Output
1
In full-rate designs, a copy of the mem_clk_2x
signal that you can use in other parts of your design.
aux_scan_clk
Output
1
Low frequency scan clock supplied primarily to clock
any user logic that interfaces to the PLL and DLL
reconfiguration interfaces.
aux_scan_clk_reset_ Output
n
1
This reset output asynchronously asserts (drives low)
when global_reset_n is asserted and de-assert
(drives high) synchronous to aux_scan_clk
when global_reset_n is deasserted. It allows
you to reset any external circuitry clocked by
aux_scan_clk.
Write Data Interface
ctl_dqs_burst
Input
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
When asserted, mem_dqs is driven. The
ctl_dqs_burst signal must be asserted before
ctl_wdata_valid and must be driven for the
correct duration to generate a correctly timed
mem_dqs signal.
ctl_wdata_valid
Input
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
Write data valid. Generates ctl_wdata and
ctl_dm output enables.
ctl_wdata
Input
MEM_IF_DWIDTH ×
DWIDTH_RATIO
Write data input from the controller to the PHY to
generate mem_dq.
ctl_dm
Input
MEM_IF_DM_WIDTH ×
DWIDTH_RATIO
DM input from the controller to the PHY.
ctl_wlat
Output
5
Required write latency between address/command
and write data that is issued to ALTMEMPHY
controller local interface.
This signal is only valid when the ALTMEMPHY
sequencer successfully completes calibration, and
does not change at any point during normal
operation.
The legal range of values for this signal is 0 to 31; and
the typical values are between 0 and ten, 0 mostly for
low CAS latency DDR memory types.
Read Data Interface
ctl_doing_rd
Input
MEM_IF_DQS_WIDTH ×
DWIDTH_RATIO / 2
Doing read input. Indicates that the DDR or DDR2
SDRAM controller is currently performing a read
operation.
The controller generates ctl_doing_rd to the
ALTMEMPHY megafunction. The ctl_doing_rd
signal is asserted for one phy_clk cycle for every
read command it issues. If there are two read
commands, ctl_doing_rd is asserted for two
phy_clk cycles. The ctl_doing_rd signal also
enables the capture registers and generates the
ctl_mem_rdata_valid signal. The
ctl_doing_rd signal should be issued at the
same time the read command is sent to the
ALTMEMPHY megafunction.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Table 5–6. AFI Signals (Part 3 of 3)
Signal Name
Type
Width (1)
Description
ctl_rdata
Output
DWIDTH_RATIO ×
MEM_IF_DWIDTH
Read data from the PHY to the controller.
ctl_rdata_valid
Output
DWIDTH_RATIO/2
Read data valid indicating valid read data on
ctl_rdata. This signal is two-bits wide (as only
half-rate or DWIDTH_RATIO = 4 is supported) to
allow controllers to issue reads and writes that are
aligned to either the half-cycle of the half-rate clock.
ctl_rlat
Output
READ_LAT_WIDTH
Contains the number of clock cycles between the
assertion of ctl_doing_rd and the return of valid
read data (ctl_rdata). This is unused by the
Altera high-performance controllers do not use
ctl_rlat.
Address and Command Interface
ctl_addr
Input
MEM_IF_ROWADDR_WI
DTH × DWIDTH_RATIO /
2
Row address from the controller.
ctl_ba
Input
MEM_IF_BANKADDR_W
IDTH ×
DWIDTH_RATIO / 2
Bank address from the controller.
ctl_cke
Input
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
Clock enable from the controller.
ctl_cs_n
Input
MEM_IF_CS_WIDTH
×DWIDTH_RATIO / 2
Chip select from the controller.
ctl_odt
Input
MEM_IF_CS_WIDTH ×
DWIDTH_RATIO / 2
On-die-termination control from the controller.
ctl_ras_n
Input
DWIDTH_RATIO / 2
Row address strobe signal from the controller.
ctl_we_n
Input
DWIDTH_RATIO / 2
Write enable.
ctl_cas_n
Input
DWIDTH_RATIO / 2
Column address strobe signal from the controller.
ctl_rst_n
Input
DWIDTH_RATIO / 2
Reset from the controller.
Calibration Control and Status Interface
ctl_mem_clk_disable Input
MEM_IF_CLK_PAIR_
COUNT
When asserted, mem_clk and mem_clk_n are
disabled. Unsupported for Cyclone III devices.
ctl_cal_success
Output
1
A 1 indicates that calibration was successful.
ctl_cal_fail
Output
1
A 1 indicates that calibration has failed.
ctl_cal_req
Input
1
When asserted, a new calibration sequence is started.
Currently not supported.
ctl_cal_byte_lane_
sel_n
Input
MEM_IF_DQS_WIDTH ×
MEM_CS_WIDTH
Indicates which DQS groups should be calibrated.
Not supported.
Note to Table 5–5:
(1) Refer to Table 5–8 for parameter descriptions.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
5–33
Table 5–7. Other Interface Signals
Signal Name
Type
Width
Description
External DLL Signals
dqs_delay_ctrl_ex
port
Output
DQS_DEL
AY_CTL_
WIDTH
Allows sharing DLL in this ALTMEMPHY instance with another
ALTMEMPHY instance. Connect the dqs_delay_ctrl_export
port on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY
instance.
dqs_delay_ctrl_im
port
Input
DQS_DEL
AY_CTL_
WIDTH
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the dqs_delay_ctrl_export
port on the ALTMEMPHY instance with a DLL to the
dqs_delay_ctrl_import port on the other ALTMEMPHY
instance.
dqs_offset_delay_
ctrl_ width
Input
DQS_DEL
AY_CTL_
WIDTH
Connects to the DQS delay logic when dll_import_export is
set to IMPORT. Only connect if you are using a DLL offset, which
can otherwise be tied to zero. If you are using a DLL offset, connect
this input to the offset_ctrl_out output of the
dll_offset_ctrl block.
dll_reference_
clk
Output
1
Reference clock to feed to an externally instantiated DLL. This clock
is typically from one of the PHY PLL outputs.
User-Mode Calibration OCT Control Signals
oct_ctl_rs_value
Input
14
OCT RS value port for use with ALT_OCT megafunction if you want
to use OCT with user-mode calibration.
oct_ctl_rt_value
Input
14
OCT RT value port for use with ALT_OCT megafunction if you want to
use OCT with user-mode calibration.
Debug Interface Signals (Note 1), (Note 2)
dbg_clk
Input
1
Debug interface clock.
dbg_reset_n
Input
1
Debug interface reset.
dbg_addr
Input
DBG_A_W
IDTH
Address input.
dgb_wr
Input
1
Write request.
dbg_rd
Input
1
Read request.
dbg_cs
Input
1
Chip select.
dbg_wr_data
Input
32
Debug interface write data.
dbg_rd_data
Output
32
Debug interface read data.
dbg_waitrequest
Output
1
Wait signal.
PLL Reconfiguration Signals—Stratix III and Stratix IV Devices
pll_reconfig_enab
le
Input
1
This signal enables the PLL reconfiguration I/O, and is used if the
user requires some custom PLL phase reconfiguration. It should
otherwise be tied low.
pll_phasecounters
elect
Input
4
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phasecounterselect input. Otherwise
this input has no effect.
pll_phaseupdown
Input
1
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phaseupdown input. Otherwise this input
has no effect.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
ALTMEMPHY Signals
Table 5–7. Other Interface Signals
Signal Name
Type
Width
Description
pll_phasestep
Input
1
When pll_reconfig_enable is asserted, this input is directly
connected to the PLL's phasestep input. Otherwise this input has
no effect.
pll_phase_done
Output
1
Directly connected to the PLL's phase_done output.
PLL Reconfiguration Signals—Stratix II Devices
pll_reconfig_
enable
Input
1
Allows access to the PLL reconfiguration block. This signal should
be held low in normal operation. While the PHY is held in reset (with
soft_reset_n), and reset_request_n is 1, it is safe to
reconfigure the PLL. To reconfigure the PLL, set this signal to 1 and
use the other pll_reconfig signals to access the PLL. When
finished reconfiguring set this signal to 0, and then set the
soft_reset_n signal to 1 to bring the PHY out of reset. For this
signal to work, the PLL_RECONFIG_PORTS_EN GUI parameter
must be set to TRUE.
pll_reconfig_
write_param
Input
9
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_read
_param
Input
9
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig
Input
1
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_
counter_type
Input
4
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_
counter_param
Input
3
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_data
_in
Input
9
Refer to the ALTPLL_RECONFIG User Guide for more information.
pll_reconfig_busy
Output
1
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_data
_out
Output
9
Refer to the ALTPLL_RECONFIG User Guide, for more information.
pll_reconfig_clk
Output
1
Synchronous clock to use for any logic accessing the
pll_reconfig interface. The same as aux_scan_clk.
pll_reconfig_
reset
Output
1
Resynchronised reset to use for any logic accessing the
pll_reconfig interface.
Calibration Interface Signals—without leveling only
rsu_codvw_phase
Output
—
The sequencer sweeps the phase of a resynchronization clock across
360° or 720° of a memory clock cycle. Data reads from the DIMM
are performed for each phase position, and a data valid window is
located, which is the set of resynchronization clock phase positions
where data is successfully read. The final resynchronization clock
phase is set at the center of this range: the center of the data valid
window or CODVW. This output is set to the current calculated value
for the CODVW, and represents how many phase steps were
performed by the PLL to offset the resynchronization clock from the
memory clock.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
5–35
Table 5–7. Other Interface Signals
Signal Name
Type
Width
Description
rsu_codvw_size
Output
—
The final centre of data valid window size (rsu_codvw_size) is
the number of phases where data was successfully read in the
calculation of the resynchronization clock centre of data valid
window phase (rsu_codvw_phase).
rsu_read_latency
Output
—
The rsu_read_latency output is then set to the read latency (in
phy_clk cycles) using the rsu_codvw_phase
resynchronization clock phase. If calibration is unsuccessful then
this signal is undefined.
rsu_no_dvw_err
Output
—
If the sequencer sweeps the resynchronization clock across every
phase and does not see any valid data at any phase position, then
calibration fails and this output is set to 1.
rsu_grt_one_dvw_
err
Output
—
If the sequencer sweeps the resynchronization clock across every
phase and sees multiple data valid windows, this is indicative of
unexpected read data (random bit errors) or an incorrectly
configured PLL that must be resolved. Calibration has failed and this
output is set to 1.
Notes to Table 5–7:
(1) The debug interface uses the simple Avalon-MM interface protocol.
(2) These ports exist in the Quartus II software, even though the debug interface is for Altera’s use only.
Table 5–8 shows the parameters that Table 5–5 through Table 5–7 refer to.
Table 5–8. Parameters
Parameter Name
Description
DWIDTH_RATIO
The data width ratio from the local interface to the memory interface.
DWIDTH_RATIO of 2 means full rate, while DWIDTH_RATIO of 4 means half rate.
LOCAL_IF_DWIDTH
The width of the local data bus must be quadrupled for half-rate and doubled for
full-rate.
MEM_IF_DWIDTH
The data width at the memory interface. MEM_IF_DWIDTH can have values that are
multiples of MEM_IF_DQ_PER_DQS.
MEM_IF_DQS_WIDTH
The number of DQS pins in the interface.
MEM_IF_ROWADDR_WIDTH
The row address width of the memory device.
MEM_IF_BANKADDR_WIDTH
The bank address with the memory device.
MEM_IF_CS_WIDTH
The number of chip select pins in the interface. The sequencer only calibrates one chip
select pin.
MEM_IF_DM_WIDTH
The number of mem_dm pins on the memory interface.
MEM_IF_DQ_PER_DQS
The number of mem_dq[] pins per mem_dqs pin.
MEM_IF_CLK_PAIR_COUNT
The number of mem_clk/mem_clk_n pairs in the interface.
PHY-to-Controller Interfaces
The following section describes the typical modules that are connected to the
ALTMEMPHY variation and the port name prefixes each module uses. This section
also describes using a custom controller. This section describes the AFI.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–36
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
The AFI standardizes and simplifies the interface between controller and PHY for all
Altera memory designs, thus allowing you to easily interchange your own controller
code with Altera's high-performance controllers. The AFI includes an administration
block that configures the memory for calibration and performs necessary mode
registers accesses to configure the memory as required (these calibration processes are
different). Figure 5–13 shows an overview of the connections between the PHY, the
controller, and the memory device.
1
Altera recommends that you use the AFI for new designs.
Figure 5–13. AFI PHY Connections
Altera Device
AFI PHY
ctl_addr
ctl_cas_n
ctl_we_n
local_wdata
AFI
Controller
Admin
mem_dqs
mem_dq
DDR3
SDRAM
Sequencer
local_rdata
ctl_rdata
For half-rate designs, the address and command signals in the ALTMEMPHY
megafunction are asserted for one mem_clk cycle (1T addressing), such that there are
two input bits per address and command pin in half-rate designs. If you require a
more conservative 2T addressing, drive both input bits (of the address and command
signal) identically in half-rate designs.
For DDR3 SDRAM with the AFI, the read and write control signals are on a per-DQS
group basis. The controller can calibrate and use a subset of the available DDR3
SDRAM devices. For example, two devices out of a 64- or 72-bit DIMM, for better
debugging mechanism.
For half-rate designs, the AFI allows the controller to issue reads and writes that are
aligned to either half-cycle of the half-rate phy_clk, which means that the datapaths
can support multiple data alignments—word-unaligned and word-aligned writes and
reads. Figure 5–14 and Figure 5–15 display the half-rate write operation.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
5–37
Figure 5–14. Half-Rate Write with Word-Unaligned Data
ctl_clk
ctl_dqs_burst
00
11
00
ctl_wdata_valid
ctl_wdata
--
01
00
00
10
11
01
ax
cb
xd
Figure 5–15. Half-Rate Write with Word-Aligned Data
ctl_clk
00
10
11
00
11
00
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
00
--
ba
dc
--
Figure 5–16 shows a full-rate write.
Figure 5–16. Full-Rate Write
ctl_clk
ctl_dqs_burst
ctl_wdata_valid
ctl_wdata
--
a
b
--
After calibration completes, the sequencer sends the write latency in number of clock
cycles to the controller.
Figure 5–17 shows full-rate reads; Figure 5–18 shows half-rate reads.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–38
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–17. Full-Rate Reads
ctl_rlat = 9
1
2
3
4
5
6
7
8
9
6
7
8
clock
ctl_addr
ctl_cs_n
ctl_doing_rd
mem_dqs
mem_dq
ctl_rdata_valid
ctl_rdata
Figure 5–18. Half-Rate Reads
ctl_rlat = 9
1
2
3
4
5
9
clock
ctl_addr
AX
ctl_cs_n
ctl_doing_rd
XA
10
10
01
mem_dqs
mem_dq
ctl_rdata_valid
10
01
ctl_rdata
DX
XD
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
5–39
Figure 5–19 and Figure 5–20 show word-aligned writes and reads. In the following
read and write examples the data is written to and read from the same address. In
each example, ctl_rdata and ctl_wdata are aligned with controller clock
(ctl_clk) cycles. All the data in the bit vector is valid at once. For comparison, refer
Figure 5–21 and Figure 5–22 that show the word-unaligned writes and reads.
1
The ctl_doing_rd is represented as a half-rate signal when passed into the PHY.
Therefore, the lower half of this bit vector represents one memory clock cycle and the
upper half the next memory clock cycle. Figure 5–22 on page 5–44 shows separated
word-unaligned reads as an example of two ctl_doing_rd bits are different.
Therefore, for each x16 device, at least two ctl_doing_rd bits need to be driven,
and two ctl_rdata_valid bits need to be interpreted.
The AFI has the following conventions:
■
With the AFI, high and low signals are combined in one signal, so for a single chip
select (ctl_cs_n) interface, ctl_cs_n[1:0], where location 0 appears on the
memory bus on one mem_clk cycle and location 1 on the next mem_clk cycle.
1
■
This convention is maintained for all signals so for an 8 bit memory
interface, the write data (ctl_wdata) signal is ctl_wdata[31:0], where
the first data on the DQ pins is ctl_wdata[7:0], then
ctl_wdata[15:8], then ctl_wdata[23:16], then
ctl_wdata[31:24].
Word-aligned and word-unaligned reads and writes have the following
definitions:
■
Word-aligned for the single chip select is active (low) in location 1 (_l).
ctl_cs_n[1:0] = 01 when a write occurs. This alignment is the easiest
alignment to design with.
■
Word-unaligned is the opposite, so ctl_cs_n[1:0] = 10 when a read or
write occurs and the other control and data signals are distributed across
consecutive ctl_clk cycles.
1
The Altera high-performance controllers use word-aligned data only.
The timing analysis script does not support word-unaligned reads and
writes.
Word-unaligned reads and writes are only supported on Stratix III and
Stratix IV devices.
■
© February 2010
Spaced reads and writes have the following definitions:
■
Spaced writes—write commands separated by a gap of one controller clock
(ctl_clk) cycle
■
Spaced reads—read commands separated by a gap of one controller clock
(ctl_clk) cycle
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–40
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–19 through Figure 5–22 assume the following general points:
■
The burst length is four. A DDR2 SDRAM is used—the interface timing is identical
for DDR3 devices.
■
An 8-bit interface with one chip select.
■
The data for one controller clock (ctl_clk) cycle represents data for two memory
clock (mem_clk) cycles (half-rate interface).
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
5–41
Figure 5–19. Word-Aligned Writes
(1)
(2)
(3)
(4)
ctl_clk
2
ctl_wlat
ctl_ras_n
00
11
ctl_cas_n
11
00
ctl_we_n
11
00
ctl_cs_n
11
ctl_dqs_burst
01
11
00
01
10
ctl_wdata_valid
00
11
11
10
11
11
00
11
ctl_wdata
00000000
ctl_addr
00000000
0020008
ACT
WR
03020100
07060504
0b0a0908
00
0f0e0d0c
Memory
Interface
mem_clk
command
(Note 5)
mem_cs_n
mem_dqs
mem_dq
Notes to Figure 5–19:
(1) To show the even alignment of ctl_cs_n, expand the signal (this convention applies for all other signals).
(2) The ctl_dqs_burst must go high one memory clock cycle before ctl_wdata_valid. Compare with the word-unaligned case.
(3) The ctl_wdata_valid is asserted two ctl_wlat controller clock (ctl_clk) cycles after chip select (ctl_cs_n) is asserted. The
ctl_wlat indicates the required write latency in the system. The value is determined during calibration and is dependant upon the relative delays
in the address and command path and the write datapath in both the PHY and the external DDR SDRAM subsystem. The controller must drive
ctl_cs_n and then wait ctl_wlat (two in this example) ctl_clks before driving ctl_wdata_valid.
(4) Observe the ordering of write data (ctl_wdata). Compare this to data on the mem_dq signal.
(5) In all waveforms a command record is added that combines the memory pins ras_n, cas_n and we_n into the current command that is issued.
This command is registered by the memory when chip select (mem_cs_n) is low. The important commands in the presented waveforms are WR
= write, ACT = activate.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–42
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–20. Word-Aligned Reads
(1)
( 2)
(3)
(3)
ctl_clk
ctl_rlat
15
ctl_ras_n
11
ctl_cas_n
0
ctl_we_n 00
ctl_cs_n 11
ctl_doing_rd
00
11
01
11
11
ctl_rdata_valid
01
00
11
11
00
00
ctl_rdata
00
11
00
FFFFFFFF
ctl_ba
ctl_addr
11
00
0000000
0020008
ctl_dm
Memory
Interface
mem_clk
command
ACT
RD
mem_cs_n
mem_dqs
mem_dq
(4)
Notes to Figure 5–20:
(1) For AFI, ctl_doing_rd is required to be asserted one memory clock cycle before chip select (ctl_cs_n) is asserted. In the half-rate
ctl_clk domain, this requirement manifests as the controller driving 11 (as opposed to the 01) on ctl_doing_rd.
(2) AFI requires that ctl_doing_rd is driven for the duration of the read. In this example, it is driven to 11 for two half-rate ctl_clks, which
equates to driving to 1, for the four memory clock cycles of this four-beat burst.
(3) The ctl_rdata_valid returns 15 (ctl_rlat) controller clock (ctl_clk) cycles after ctl_doing_rd is asserted. Returned is when
the ctl_rdata_valid signal is observed at the output of a register within the controller. A controller can use the ctl_rlat value to
determine when to register to returned data, but this is unnecessary as the ctl_rdata_valid is provided for the controller to use as an enable
when registering read data.
(4) Observe the alignment of returned read data with respect to data on the bus.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
5–43
Figure 5–21 and Figure 5–22 show spaced word-unaligned writes and reads.
Figure 5–21. Word-Unaligned Writes
(2)
(1)
(3) (4)
(5)
ctl_clk
2
ctl_wlat
ctl_ras_n
10
ctl_cas_n
01
00
ctl_we_n
01
00
ctl_cs_n
11
10
ctl_dqs_burst
00
ctl_wdata_valid
00
ctl_wdata
11
10
11
10
00000000
11
01
11
01
11
10
11
01
00
01
00
01000000 05040302 05040706 09080706 0d0c0b0a
0d0c0f0e
00
ctl_ba
ctl_addr
0000000
020000
020008
Memory
Interface
mem_clk
command
ACT
WR
mem_cs_n
mem_dqs
mem_dq
Notes to Figure 5–21:
(1) Alternative word-unaligned chip select (ctl_cs_n).
(2) As with word- aligned writes, ctl_dqs_burst is asserted one memory clock cycle before ctl_wdata_valid. You can see
ctl_dqs_burst is 11 in the same cycle where ctl_wdata_valid is 10. The LSB of these two becomes the first value the signal takes in
the mem_clk domain. You can see that ctl_dqs_burst has the necessary one mem_clk cycle lead on ctl_wdata_valid.
(3) The latency between ctl_cs_n being asserted and ctl_wdata_valid going high is effectively ctl_wlat (in this example, two) controller
clock (ctl_clk) cycles. This can be thought of in terms of relative memory clock (mem_clk) cycles, in which case the latency is four mem_clk
cycles.
(4) Only the upper half is valid (as the ctl_wdata_valid signal demonstrates, there is one ctl_wdata_valid bit to two 8-bit words). The
write data bits go out on the bus in order, least significant byte first. So for a continuous burst of write data on the DQ pins, the most significant
half of write data is used, which goes out on the bus last and is therefore contiguous with the following data. The converse is true for the end of
the burst. Write data is spread across three controller clock (ctl_clk) cycles, but still only four memory clock (mem_clk) cycles. However, in
relative memory clock cycles the latency is equivalent in the word-aligned and word-unaligned cases.
(5) The 0504 here is residual from the previous clock cycle. In the same way that only the upper half of the write data is used for the first beat of the
write, only the lower half of the write data is used in the last beat of the write. These upper bits can be driven to any value in this alignment.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–44
Chapter 5: Functional Description—ALTMEMPHY
PHY-to-Controller Interfaces
Figure 5–22. Word-Unaligned Reads
(1)
(2) (3)
ctl_clk
15
ctl_rlat
ctl_ras_n
ctl_cas_n
ctl_we_n 00
ctl_cs_n
ctl_doing_rd
10
11
00
10
10
11
11
01
ctl_rdata_valid
10
11
11
01
0
00
ctl_rdata
10
11
01
10
11
01
00
0f0e0f0e
FFFFFFFF
00
ctl_ba
ctl_addr
10
0000000
ctl_dm
Memory
Interface
mem_clk
command
ACT
RD
mem_cs_n
mem_dqs
mem_dq
Notes to Figure 5–22:
(1) Similar to word-aligned reads, ctl_doing_rd is asserted one memory clock cycle before chip select (ctl_cs_n) is asserted, which for a
word-unaligned read is in the previous controller clock (ctl_clk) cycle. In this example the ctl_doing_rd signal is now spread over three
controller clock (ctl_clk) cycles, the high bits in the sequence '10','11','01','10','11','01' providing the required four memory clock cycles of
assertion for ctl_doing_rd for the two 4-beat reads in the full-rate memory clock domain, '011110','011110'.
(2) The return pattern of ctl_rdata_valid is a delayed version of ctl_doing_rd. Advertised read latency (ctl_rlat) is the number of
controller clock (ctl_clk) cycles delay inserted between ctl_doing_rd and ctl_rdata_valid.
(3) The read data (ctl_rdata) is spread over three controller clock cycles and in the pointed to vector only the upper half of the ctl_rdata bit
vector is valid (denoted by ctl_rdata_valid).
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
5–45
Using a Custom Controller
The ALTMEMPHY megafunction can be integrated with your own controller. This
section describes the interface requirement and the handshake mechanism for
efficient read and write transactions.
Preliminary Steps
Perform the following steps to generate the ALTMEMPHY megafunction:
1. If you are creating a custom DDR or DDR2 SDRAM controller, generate the Altera
High-Performance Controller MegaCore function targeting your chosen Altera
memory devices.
2. Compile and verify the timing. This step is optional; refer to “Compile and
Simulate” on page 4–1.
3. If targeting a DDR or DDR2 SDRAM device, simulate the high-performance
controller design.
4. Integrate the top-level ALTMEMPHY design with your controller. If you started
with the high-performance controller, the PHY variation name is
<controller_name>_phy.v/.vhd. Details about integrating your controller with
Altera’s ALTMEMPHY megafunction are described in the following sections.
5. Compile and simulate the whole interface to ensure that you are driving the PHY
properly and that your commands are recognized by the memory device.
Design Considerations
This section discuss the important considerations for implementing your own
controller with the ALTMEMPHY megafunction. This section describes the design
considerations for AFI variants.
1
Simulating the high-performance controller is useful if you do not know how to drive
the PHY signals.
Clocks and Resets
The ALTMEMPHY megafunction automatically generates a PLL instance, but you
must still provide the reference clock input (pll_ref_clk) with a clock of the
frequency that you specified in the MegaWizard Plug-In Manager. An active-low
global reset input is also provided, which you can deassert asynchronously. The clock
and reset management logic synchronizes this reset to the appropriate clock domains
inside the ALTMEMPHY megafunction.
A clock output (half the memory clock frequency for a half-rate controller; the same as
the memory clock for a full-rate controller) is provided and all inputs and outputs of
the ALTMEMPHY megafunction are synchronous to this clock. For AFIs, this signal is
called ctl_clk.
There is also an active-low synchronous reset output signal provided, ctl_reset_n.
This signal is synchronously de-asserted with respect to the ctl_clk or phy_clk
clock domain and it can reset any additional user logic on that clock domain.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–46
Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
Calibration Process Requirements
When the global reset_n signal is released, the ALTMEMPHY handles the
initialization and calibration sequence automatically. The sequencer calibrates
memory interfaces by issuing reads to multiple ranks of DDR SDRAM (multiple chip
select). Timing margins decrease as the number of ranks increases. It is impractical to
supply one dedicated resynchronization clock for each rank of memory, as it
consumes PLL resources for the relatively small benefit of improved timing margin.
When calibration is complete, the ctl_cal_success signal goes high if successful;
the ctl_cal_fail signal goes high if calibration fails. Calibration can be repeated
by the controller using the soft_reset_n signal, which when asserted puts the
sequencer into a reset state and when released the calibration process begins again.
1
You can ignore the following two warning and critical warning messages:
Warning: Timing Analysis for multiple chip select DDR/DDR2/DDR3-SDRAM
configurations is preliminary (memory interface has a chip select width
of 4)
Critical Warning: Read Capture and Write timing analyses may not be
valid due to violated timing model assumptions
Other Local Interface Requirements
The memory burst length can be two, four, or eight for DDR SDRAM devices, and
four or eight for DDR2 SDRAM devices. For a half-rate controller, the memory clock
runs twice as fast as the clock provided to the local interface, so data buses on the local
interface are four times as wide as the memory data bus. For a full-rate controller, the
memory clock runs at the same speed as the clock provided to the local interface, so
the data buses on the local interface are two times as wide as the memory data bus.
This section describes the DDR or DDR2 SDRAM high-performance controllers with
the AFI.
Address and Command Interfacing
Address and command signals are automatically sized for 1T operation, such that for
full-rate designs there is one input bit per pin (for example, one cs_n input per
chip-select configured); for half-rate designs there are two. If you require a more
conservative 2T address and command scheme, use a full-rate design and drive the
address/command inputs for two clock cycles, or in a half-rate design drive both
address/command bits for a given pin identically.
1
Although the PHY inherently supports 1T addressing, the high performance
controllers support only 2T addressing, so PHY timing analysis is performed
assuming 2T address and command signals.
Handshake Mechanism Between Read Commands and Read Data
When performing a read, a high-performance controller with the AFI asserts the
ctl_doing_read signal to indicate that a read command is requested and the byte
lanes that it expects valid data to return on. ALTMEMPHY uses the
ctl_doing_read signal for the following actions:
■
Control of the postamble circuit
■
Generation of ctl_rdata_valid
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
■
5–47
Dynamic termination (Rt) control timing
The read latency, ctl_rlat, is advertised back to the controller. This signal indicates
how long it takes in ctl_clk clock cycles from assertion of the ctl_doing_read
signal to valid read data returning on ctl_rdata. The ctl_rlat signal is only valid
when calibration has successfully completed and never changes values during normal
user mode operation.
The ALTMEMPHY provides a signal, ctl_rdata_valid, to indicate that the data on
read data bus is valid. The width of this signal varies between half-rate and full-rate
designs to support the option to indicate that the read data is not word aligned.
Figure 5–23 and Figure 5–24 show these relationships.
Figure 5–23. Address and Command and Read-Path Timing—Full-Rate Design
ctl_rlat = 9
1
2
3
4
5
6
7
8
9
6
7
8
9
10
01
DX
XD
ctl_clk
ctl_addr
ctl_cs_n
ctl_doing_read
mem_dqs
mem_dq
ctl_rdata_valid
ctl_rdata
Figure 5–24. Second Read Alignment—Half-Rate Design
ctl_rlat = 9
1
2
3
4
5
ctl_clk
ctl_addr
A
XA
ctl_cs_n
ctl_doing_read
10
10
01
mem_dqs
mem_dq
ctl_rdata_valid
ctl_rdata
Handshake Mechanism Between Write Commands and Write Data
In the AFI, the ALTMEMPHY output ctl_wlat gives the number of ctl_clk cycles
between the write command that is issued ctl_cs_n asserted and ctl_dqs_burst
asserted. The ctl_wlat signal takes account of the following actions to provide a
single value in ctl_clk clock cycles:
© February 2010
■
CAS write latency
■
Additive latency
■
Datapath latencies and relative phases
■
Board layout
■
Address and command path latency and 1T register setting, which is dynamically
setup to take into account any leveling effects
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
5–48
Chapter 5: Functional Description—ALTMEMPHY
Using a Custom Controller
The ctl_wlat signal is only valid when the calibration has been successfully
completed by the ALTMEMPHY sequencer and does not change at any point during
normal user mode operation. Figure 5–25 shows the operation of ctl_wlat port.
Figure 5–25. Timing for ctl_dqs_burst, ctl_wdata_valid, Address, and Command—Half-Rate Design
ctl_wlat = 2
1
2
ctl_clk
ctl_addr
AdAd
ctl_cs_n
01
ctl_dqs_burst
10
11
ctl_wdata_valid
ctl_wdata
For a half-rate design ctl_cs_n is 2 bits, not 1. Also the ctl_dqs_burst and
ctl_wdata_valid waveforms indicate a half-rate design. This write results in a
burst of 8 at the DDR. Where ctl_cs_n is driven 2'b01, the LSB (1) is the first value
driven out of mem_cs_n, and the MSB (0) follows on the next mem_clk. Similarly, for
ctl_dqs_burst, the LSB is driven out of mem_dqs first (0), then a 1 follows on the
next clock cycle. This sequence produces the continuous DQS pulse as required.
Finally, the ctl_addr bus is twice MEM_IF_ADDR_WIDTH bits wide and so the
address is concatenated to result in an address phase two mem_clk cycles wide.
Partial Write Operations
As part of the DDR and DDR2 SDRAM memory specifications, you have the option
for partial write operations by asserting the DM pins for part of the write signal.
For designs targeting the Stratix III device families, deassert the ctl_wdata_valid
signal during partial writes, when the write data is invalid, to save power by not
driving the DQ outputs.
For designs targeting other device families, use only the DM pins if you require
partial writes. Assert the ctl_dqs_burst and ctl_wdata_valid signals as for full
write operations, so that the DQ and DQS pins are driven during partial writes.
The I/O difference between Stratix III device families and other device families makes
it only possible to use the ctl_dqs_burst signal for the DQS enable in Stratix III
devices.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
6. Functional Description—
High-Performance Controller
The high-performance controller (HPC) architecture instantiates encrypted control
logic and the ALTMEMPHY megafunction. The controller accepts read and write
requests from the user on its local interface, using either the Avalon-MM interface
protocol or the native interface protocol. It converts these requests into the necessary
SDRAM commands, including any required bank management commands. Each read
or write request on the Avalon-MM or native interface maps to one SDRAM read or
write command. Since the controller uses a memory burst length of 4, read and write
requests are always of length 1 on the local interface if the controller is in half-rate
mode. In full-rate mode, the controller accepts requests of size 1 or 2 on the local
interface. Requests of size 2 on the local interface produce better throughput as whole
memory burst is used.
The bank management logic in the controller keeps a row open in every bank in the
memory system. For example, a controller configured for a double-sided, 4-bank DDR
or DDR2 SDRAM DIMM keeps an open row in each of the 8 banks. The controller
allows you to request an auto-precharge read or auto-precharge write, allowing
control over whether to keep that row open after the request. You can achieve
maximum efficiency when you issue reads and writes to the same bank, with the last
access to that bank being an auto-precharge read or write. The controller does not do
any access reordering.
Block Description
Figure 6–1 shows the top-level block diagram of the DDR or DDR2 SDRAM HPC.
Figure 6–1. DDR and DDR2 SDRAM HPC Block Diagram
local_addr
local_be
local_burstbegin
local_read_req
local_refresh_req
local_size
local_wdata
local_write_req
local_autopch_req
local_powerdn_req
local_self_rfsh_req
DDR/DDR2 SDRAM HighPerformance Controller
Control
Logic
(Encrypted)
local_init_done
local_rdata
local_rdata_valid
local_ready
local_refresh_ack
local_wdata_req
local_powerdn_ack
local_self_rfsh_ack
mem_a
mem_ba
mem_cas_n
mem_cke
mem_cs_n
mem_dq
mem_dqs
mem_dm
mem_odt (1)
mem_ras_n
mem_we_n
ALTMEMPHY
Megafunction
Note to Figure 6–1:
(1) For DDR2 SDRAM HPC only.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–2
Chapter 6: Functional Description—High-Performance Controller
Block Description
Figure 6–2 shows a block diagram of the DDR or DDR2 SDRAM high-performance
controller architecture.
Figure 6–2. DDR and DDR2 SDRAM High-Performance Controller Architecture Block Diagram
Timer
Logic
Initialization
State Machine
Address and
Command
Decode
Command
FIFO
ALTMEMPHY
Interface
Main State
Machine
Avalon-MM or Native
Slave Interface
PHY Interface
Logic
Write Data
FIFO
Write Data
Tracking Logic
Bank
Management
Logic
The blocks in Figure 6–2 on page 6–2 are described in the following sections.
Command FIFO Buffer
This FIFO buffer allows the controller to buffer up to four consecutive read or write
commands. It is built from logic elements, and stores the address, read or write flag,
and burst count information. If this FIFO buffer fills up, the local_ready signal to
the user is deasserted until the main state machine takes a command from the FIFO
buffer.
Write Data FIFO Buffer
The write data FIFO buffer holds the write data from the user until the main state
machine can send it to the ALTMEMPHY megafunction, which does not have a write
data buffer. In the Avalon-MM interface mode, the user logic presents a write request,
address, burst count, and one or more beats of data at the same time. The write data
beats are placed into the FIFO buffer until they are needed. In the native interface
mode, the user logic presents a write request, address, and burst count. The controller
then requests the correct number of write data beats from the user via the
local_wdata_req signal, and the user logic must return the write data in the clock
cycle after the write data request signal.
This FIFO buffer is sized to be deeper than the command FIFO buffer to prevent it
from filling up and interrupting streaming writes.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Block Description
6–3
Write Data Tracking Logic
The write data tracking logic keeps track of the number of write data beats in the FIFO
buffer. In the native interface mode, this logic manages how much more data to
request from the user logic and issues the local_wdata_req signal.
Main State Machine
The main state machine decides what DDR commands to issue based on inputs from
the command FIFO buffer, the bank management logic, and the timer logic.
Bank Management Logic
The bank management logic keeps track the current state of each bank. It can keep a
row open in every bank in your memory system. The state machine uses the
information provided by this logic to decide whether it needs to issue bank
management commands before it reads or writes to the bank. The controller always
leaves the bank open unless the user requests an auto-precharge read or write. The
periodic refresh process also causes all the banks to be closed.
Timer Logic
The timer logic tracks whether the required minimum number of clock cycles has
passed since the last relevant command was issued. For example, the timer logic
records how many cycles have elapsed since the last activate command so that the
state machine knows it is safe to issue a read or write command (tRCD). The timer logic
also counts the number of clock cycles since the last periodic refresh command and
sends a high priority alert to the state machine if the number of clock cycles has
expired.
Initialization State Machine
The initialization state machine issues the appropriate sequence of command to
initialize the memory devices. It is specific to DDR and DDR2 as each memory type
requires a different sequence of initialization commands.
With the AFI, the ALTMEMPHY megafunction initializes the memory, otherwise the
controller is responsible for initializing the memory.
Address and Command Decode
When the state machine wants to issue a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these into the
DDR-specific RAS, CAS, and WE commands.
PHY Interface Logic
When the main state machine issues a write command to the memory, the write data
for that write burst has to be fetched from the write data FIFO buffer. The relationship
between write command and write data depends on the memory type, ALTMEMPHY
megafunction interface type, CAS latency, and the full-rate or half-rate setting. The
PHY interface logic adjusts the timing of the write data FIFO read request signal so
that the data arrives on the external memory interface DQ pins at the correct time.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–4
Chapter 6: Functional Description—High-Performance Controller
Block Description
ODT Generation Logic
The ODT generation logic (not shown) calculates when and for how long to enable the
ODT outputs. It also decides which ODT bit to enable, based on the number of chip
selects in the system.
■
1 DIMM (1 or 2 Chip Selects)
In the case of a single DIMM, the ODT signal is only asserted during writes. The
ODT signal on the DIMM at mem_cs[0] is always used, even if the write
command on the bus is to mem_cs[1]. In other words, mem_odt[0] is always
asserted even if there are two ODT signals.
■
2 or more DIMMs
Table 6–1 shows which ODT signal on the adjacent DIMM is enabled.
Table 6–1. ODT
Write or Read On
ODT Enabled
mem_cs[0]or cs[1]
mem_odt[2]
mem_cs[2] or cs[3]
mem_odt[0]
mem_cs[4] or cs[5]
mem_odt[6]
mem_cs[6] or cs[7]
mem_odt[4]
Low-Power Mode Logic
The low-power mode logic (not shown) monitors the local_powerdn_req and
local_self_rfsh_req request signals. This logic also informs the user of the
current low-power state via the local_powerdn_ack and local_self_rfsh_ack
acknowledge signals.
Control Logic
Bus commands control SDRAM devices using combinations of the mem_ras_n,
mem_cas_n, and mem_we_n signals. For example, on a clock cycle where all three
signals are high, the associated command is a no operation (NOP). A NOP command
is also indicated when the chip select signal is not asserted. Table 6–2 shows the
standard SDRAM bus commands.
Table 6–2. Bus Commands
Command
Acronym
ras_n
cas_n
we_n
No operation
NOP
High
High
High
Active
ACT
Low
High
High
Read
RD
High
Low
High
Write
WR
High
Low
Low
Burst terminate
BT
High
High
Low
Precharge
PCH
Low
High
Low
Auto refresh
ARF
Low
Low
High
Load mode register
LMR
Low
Low
Low
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Block Description
6–5
The DDR or DDR2 SDRAM HPC must open SDRAM banks before they access the
addresses in that bank. The row and bank to be opened are registered at the same time
as the active (ACT) command. The HPC closes the bank and opens it again if it needs
to access a different row. The precharge (PCH) command closes only a bank.
The primary commands used to access SDRAM are read (RD) and write (WR). When
the WR command is issued, the initial column address and data word is registered.
When a RD command is issued, the initial address is registered. The initial data
appears on the data bus 2 to 3 clock cycles later (3 to 5 for DDR2 SDRAM). This delay
is the column address strobe (CAS) latency and is due to the time required to read the
internal DRAM core and register the data on the bus. The CAS latency depends on the
speed of the SDRAM and the frequency of the memory clock. In general, the faster the
clock, the more cycles of CAS latency are required. After the initial RD or WR
command, sequential reads and writes continue until the burst length is reached or a
burst terminate (BT) command is issued. DDR and DDR2 SDRAM devices support
burst lengths of 2, 4, or 8 data cycles. The auto-refresh command (ARF) is issued
periodically to ensure data retention. This function is performed by the DDR or DDR2
SDRAM high-performance controller.
The load mode register command (LMR) configures the SDRAM mode register. This
register stores the CAS latency, burst length, and burst type.
f
For more information, refer to the specification of the SDRAM that you are using.
Error Correction Coding (ECC)
The optional ECC comprises an encoder and a decoder-corrector, which can detect
and correct single-bit errors and detect double-bit errors. The ECC uses an 8-bit ECC
for each 64-bit message. The ECC has the following features:
© February 2010
■
Hamming code ECC that encodes every 64-bits of data into 72-bits of codeword
with 8-bits of Hamming code parity bits
■
Latency:
■
Maximum of 1 or 2 clock delay during writes
■
Minimum 1 or 3 clock delay during reads
■
Detects and corrects all single-bit errors. Also the ECC sends an interrupt when the
user-defined threshold for a single-bit error is reached.
■
Detects all double-bit errors. Also, the ECC counts the number of double-bit errors
and sends an interrupt when the user-define threshold for double-bit error is
reached.
■
Accepts partial writes
■
Creates forced errors to check the functioning of the ECC
■
Powers up to a ready state
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–6
Chapter 6: Functional Description—High-Performance Controller
Block Description
Figure 6–3 shows the ECC block diagram.
Figure 6–3. ECC Block Diagram
ECC
From Local
Interface
Write
Message
N x 64 Bits
To Local
Interface
To and From
Local Interface
Write
Codeword
N x 72 Bits
Encoder
Read
Message
N x 64 Bits
32 Bits
DecoderCorrector
Read
Codeword
N x 72 Bits
Memory
Controller
N x 72 Bits
DDR or DDR2
SDRAM
ECC
Controller
The ECC comprises the following blocks:
■
The encoder—encodes the 64-bit message to a 72-bit codeword
■
The decoder-corrector—decodes and corrects the 72-bit codeword if possible
■
The ECC logic—controls multiple encoder and decoder-correctors, so that the ECC
can handle different bus widths. Also, it controls the following functions of the
encoder and decoder-corrector:
■
■
■
■
Interrupts:
■
Detected and corrected single-bit error
■
Detected double-bit error
■
Single-bit error counter threshold exceeded
■
Double-bit error counter threshold exceeded
Configuration registers:
■
Single-bit error detection counter threshold
■
Double-bit error detection counter threshold
■
Capture status for first encountered error or most recent error
■
Enable deliberate corruption of ECC for test purposes
Status registers:
■
Error address
■
Error type: single-bit error or double-bit error
■
Respective byte error ECC syndrome
Error signal—an error signal corresponding to the data word is provided with
the data and goes high if a double-bit error that cannot be corrected occurs in
the return data word.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Block Description
■
6–7
Counters:
■
Detected and/or corrected single-bit errors
■
Detected double-bit errors
The ECC can instantiate multiple encoders, each running in parallel, to encode any
width of data words assuming they are integer multiples of 64.
The ECC operates between the local (native or Avalon-MM interface) and the memory
controller.
The ECC has an N × 64-bit (where N is an integer) wide interface, between the local
interface and the ECC, for receiving and returning data from the local interface. This
interface can be a native interface or an Avalon-MM slave interface, you select the
type of interface in the MegaWizard interface.
The ECC has a second interface between the local interface and the ECC, which is a
32-bit wide Avalon-MM slave to control and report the status of the operation of the
ECC logic.
The encoded data from the ECC is sent to the memory controller using a N × 72-bit
wide Avalon-MM master interface, which is between the ECC and the memory
controller.
When testing the DDR SDRAM high-performance controller, you can turn off the
ECC.
Interrupts
The ECC issues an interrupt signal when one of the following scenarios occurs:
■
The single-bit error counter reaches the set maximum single-bit error threshold
value.
■
The double-bit error counter reaches the set maximum double-bit error threshold
value.
The error counters increment every time the respective event occurs for all N parts of
the return data word. This incremented value is compared with the maximum
threshold and an interrupt signal is sent when the value is equal to the maximum
threshold. The ECC clears the interrupts when you write a 1 to the respective status
register. You can mask the interrupts from either of the counters using the control
word.
Partial Writes
The ECC supports partial writes. Along with the address, data, and burst signals, the
Avalon-MM interface also supports a signal vector that is responsible for byte-enable.
Every bit of this signal vector represents a byte on the data-bus. Thus, a 0 on any of
these bits is a signal for the controller not to write to that particular location—a partial
write.
For partial writes, the ECC performs the following steps:
1. The ECC logic stalls further read or write commands from the Avalon-MM
interface when it receives a partial write condition.
2. It simultaneously sends a self-generated read command, for the partial write
address, to the memory controller.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–8
Chapter 6: Functional Description—High-Performance Controller
Block Description
3. Upon receiving the returned read data from the memory controller for the
particular address, the decoder decodes the data, checks for errors, and then sends
it to the ECC logic.
4. The ECC logic merges the corrected or correct dataword with the incoming
information.
5. The ECC logic sends the updated dataword to the encoder for encoding, and then
sends updated dataword to the memory controller with a write command.
6. The ECC logic stops stalling the commands from the Avalon-MM interface so that
the logic can receive new commands.
The following corner cases can occur:
■
A single-bit error during the read phase of the read-modify-write process. In this
case, the single-bit error is corrected first, the single-bit error counter is
incremented and then a partial write is performed to this corrected decoded data
word.
■
A double-bit error during the read phase of the read-modify-write process. In this
case, the double-bit error counter is incremented and an interrupt is sent through
the Avalon-MM interface. The new write word is not written to its location. A
separate field in the interrupt status register highlights this condition.
Figure 6–4 and Figure 6–5 show the partial write operation for HPC in full-rate and
half-rate mode. The full-rate HPC supports a local size of 1 and 2, and the half-rate
HPC supports a local size of 1 only.
Figure 6–4. Partial Write for HPC—Full Rate
0
local_address
1
2
local_size
X1
local_be
local_wdata
XF
01234567
89ABCDEF
mem_dm
67
mem_dq
R
R
R
EF
CD
AB
89
Note to Figure 6–4:
(1) R represents the internal read-back memory data during the read-modify-write process.
Figure 6–5. Partial Write for HPC—Half Rate
local_address
0
local_size
1
local_be
X1
local_wdata
01234567
mem_dm
mem_dq
67
R
R
R
Note to Figure 6–5:
(1) R represents the internal read-back memory data during the read-modify-write process.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Block Description
6–9
Partial Bursts
DIMMs that do not have the DM pins do not support partial bursts. A minimum of
four words must be written to the memory at the same time.
Figure 6–6 shows the partial burst operation for HPC.
Figure 6–6. Partial Burst for HPC
local_address
0
local_size
1
local_be
X1
local_wdata
01234567
mem_dm
67
mem_dq
45
23
01
ECC Latency
Using the ECC results in the following latency changes:
■
Local Burst Length 1
■
Local Burst Length 2
Local Burst Length 1
For a local burst length of 1, the write latency increases by one clock cycle; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC logic, so latency
depends on the time the controller takes to fetch the data from the particular address.
Table 6–3 shows the relationship between burst lengths and rate.
Table 6–3. Burst Lengths and Rates
Local Burst Length
Rate
Memory Burst Length
1
Half
4
2
Full
4
Local Burst Length 2
For a local burst length of 2, the write latency increases by two clock cycles; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC logic, so latency
depends on the time the controller takes to fetch the data from the particular address.
For a single-bit error, the automatic correction of memory takes place without stalling
the read cycle (if enabled), which stalls further commands to the ECC logic, while the
correction takes place.
ECC Registers
Table 6–4 shows the ECC registers.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–10
Chapter 6: Functional Description—High-Performance Controller
Block Description
Table 6–4. ECC Registers (Part 1 of 2)
Name
Address
Size
(Bits)
Attribute
Default
Control word specifications
00
32
R/W
0000000F
This register contains all commands for
the ECC functioning.
Maximum single-bit error
counter threshold
01
32
R/W
00000001
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC generates an interrupt.
Maximum double-bit error
counter threshold
02
32
R/W
00000001
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold, as defined by this
register. When this threshold is crossed,
the ECC generates an interrupt.
Current single-bit error
count
03
32
RO
00000000
The single-bit error counter increments
(when a single-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
Current double-bit error
count
04
32
RO
00000000
The double-bit error counter increments
(when a double-bit error occurs) until the
maximum threshold. You can find the
value of the count by reading this status
register.
Last or first single-bit error
error address
05
32
RO
00000000
This status register stores the last
single-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
Last or first double-bit error
error address
06
32
RO
00000000
This status register stores the last
double-bit error error address. It can be
cleared using the control word clear. If bit
10 of the control word is set high, the
first occurred address is stored.
Last single-bit error error
data
07
32
RO
00000000
This status register stores the last
single-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N-deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Description
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Block Description
6–11
Table 6–4. ECC Registers (Part 2 of 2)
Address
Size
(Bits)
Attribute
Default
Description
Last single-bit error
syndrome
08
32
RO
00000000
This status register stores the last
single-bit error syndrome, which
specifies the location of the error bit on a
64-bit data word. As the data word is an
Nth multiple of 64, the syndrome is
stored in a N deep, 8-bit wide FIFO buffer
where each syndrome represents errors
in every 64-bit part of the data word. The
register gets updated with the correct
syndrome depending on which part of the
data word is shown on the last single-bit
error error data register. It can be cleared
individually by using the control word
clear.
Last double-bit error error
data
09
32
RO
00000000
This status register stores the last
double-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
Interrupt status register
0A
5
RO
00000000
This status register stores the interrupt
status in four fields (refer to Table 6–6).
These status bits can be cleared by
writing a 1 in the respective locations.
Interrupt mask register
0B
5
WO
00000001
This register stores the interrupt mask in
four fields (refer to Table 6–7).
Single-bit error location
status register
0C
32
R/W
00000000
This status register stores the occurrence
of single-bit error for each 64-bit part of
the data word in every bit (refer to
Table 6–8). These status bits can be
cleared by writing a 1 in the respective
locations.
Double-bit error location
status register
0D
32
R/W
00000000
This status register stores the occurrence
of double-bit error for each 64-bit part of
the data word in every bit (refer to
Table 6–9). These status bits can be
cleared by writing a 1 in the respective
locations.
Name
ECC Register Bits
Table 6–5 shows the control word specification register.
Table 6–5. Control Word Specification Register (Part 1 of 2)
Bit
Name
Direction
Description
0
Count single-bit error
Decoder-corrector
When 1, count single-bit errors.
1
Correct single-bit error
Decoder-corrector
When 1, correct single-bit errors.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 6: Functional Description—High-Performance Controller
Block Description
Table 6–5. Control Word Specification Register (Part 2 of 2)
Bit
Name
Direction
Description
2
Double-bit error enable
Decoder-corrector
When 1, detect all double-bit errors and
increment double-bit error counter.
3
Reserved
N/A
Reserved for future use.
4
Clear all status registers
Controller
When 1, clear counters single-bit error and
double-bit error status registers for first and last
error address.
5
Reserved
N/A
Reserved for future use.
6
Reserved
N/A
Reserved for future use.
7
Counter clear on read
Controller
When 1, enables counters to clear on read
feature.
8
Corrupt ECC enable
Controller
When 1, enables deliberate ECC corruption
during encoding, to test the ECC.
9
ECC corruption type
Controller
When 0, creates single-bit errors in all ECC
codewords; when 1, creates double-bit errors in
all ECC codewords.
10
First or last error
Controller
When 1, stores the first error address rather
than the last error address of single-bit error or
double-bit error.
11
Clear interrupt
Controller
When 1, clears the interrupt.
Table 6–6 shows the interrupt status register.
Table 6–6. Interrupt Status Register
Bit
Name
Description
0
Single-bit error
When 1, single-bit error occurred.
1
Double-bit error
When 1, double-bit error occurred.
2
Maximum single-bit error
When 1, single-bit error maximum threshold
exceeded.
3
Maximum double-bit error
When 1, double-bit error maximum threshold
exceeded.
4
Double-bit error during
read-modify-write
When 1, double-bit error occurred during a read
modify write condition. (partial write).
Reserved
Reserved.
Others
Table 6–7 shows the interrupt mask register.
Table 6–7. Interrupt Mask Register (Part 1 of 2)
Bit
Name
Description
0
Single-bit error
When 1, masks single-bit error.
1
Double-bit error
When 1, masks double-bit error.
2
Maximum single-bit error
When 1, masks single-bit error maximum
threshold exceeding condition.
3
Maximum double-bit error
When 1, masks double-bit error maximum
threshold exceeding condition.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Example Top-Level File
6–13
Table 6–7. Interrupt Mask Register (Part 2 of 2)
Bit
Name
4
Others
Description
Double-bit error during
read-modify-write
When 1, masks interrupt when double-bit error
occurs during a read-modify-write condition.
(partial write).
Reserved
Reserved.
Table 6–8 shows the single-bit error location status register.
Table 6–8. Single-Bit Error Location Status Register
Bit
Name
Description
Bits N – 1 down to 0
Interrupt
When 0, no single-bit error; when 1, single-bit
error occurred in this 64-bit part.
Others
Reserved
Reserved.
Table 6–9 shows the double-bit error location status register.
Table 6–9. Double-Bit Error Location Status Register
Bit
Name
Description
Bits N-1 down to 0
Cause of Interrupt
When 0, no double-bit error; when 1,
double-bit error occurred in this 64-bit part.
Others
Reserved
Reserved.
Example Top-Level File
The MegaWizard Plug-In Manager helps you create an example top-level file that
shows you how to instantiate and connect the DDR or DDR2 SDRAM HPC. The
example top-level file consists of the DDR or DDR2 SDRAM HPC, some driver logic
to issue read and write requests to the controller, a PLL to create the necessary clocks,
and a DLL (Stratix series only). The example top-level file is a working system that
you can compile and use for both static timing checks and board tests.
Figure 6–7 shows the testbench and the example top-level file.
Figure 6–7. Testbench and Example Top-Level File
Testbench
Example Design
pnf
test_complete
Example Driver
DDR SDRAM Controller
WizardGenerated
Memory Model
ALTMEMPHY
Control
Logic
clock_source
© February 2010
Altera Corporation
DLL
PLL
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 6: Functional Description—High-Performance Controller
Example Top-Level File
Table 6–10 describes the files that are associated with the example top-level file and
the testbench.
Table 6–10. Example Top-Level File and Testbench Files
Filename
Description
<variation name>_example_top_tb.v or .vhd
Testbench for the example top-level file.
<variation name>_example_top.v or .vhd
Example top-level file.
<variation name>_mem_model.v or .vhd
Associative-array memory model.
<variation name>_full_mem_model.v or .vhd
Full-array memory model.
<variation name>_example_driver.v or .vhd
Example driver.
<variation name> .v or .vhd
Top-level description of the custom MegaCore function.
<variation name>.qip
Contains Quartus II project information for your MegaCore
function variations.
There are two Altera-generated memory models available—associative-array
memory model and full-array memory model.
The associative-array memory model (<variation name>_mem model.v) allocates
reduced set of memory addresses with a default depth of 2,048 or 2K address spaces.
This allocation allows for a larger memory array compilation and simulation which
enables you to easily reconfigure the depth of the associate array.
The full-array memory model (<variation name>_mem model_full.v) allocates
memory for all addresses accessible by the DDR cores. This allocation makes it
impossible to simulate large memory (more than 2K address spaces) designs, because
simulators need more memory than what is available on a typical system.
Both the memory models display similar behaviors and have the same calibration
time.
1
The memory model, <variation name>_test_component.v/vhd, used in SOPC Builder
designs, is actually a variation of the full-array memory model. To ensure your
simulation works in SOPC Builder, use memory model with less than 512-Mbit
capacity.
Example Driver
The example driver is a self-checking test pattern generator for the memory interface.
It uses a state machine to write and read from the memory to verify that the interface
is operating correctly.
It performs the following tests and loops back the tests indefinitely:
■
Sequential addressing writes and reads
The state machine writes pseudo-random data generated by a linear feedback shift
register (LFSR) to a set of incrementing row, bank, and column addresses. The
state machine then resets the LFSR, reads back the same set of addresses, and
compares the data it receives against the expected data. You can adjust the length
and pattern of the bursts that are written by changing the MAX_ROW, MAX_BANK,
and MAX_COL constants in the example driver source code, and the entire memory
space can be tested by adjusting these values. You can skip this test by setting the
test_seq_addr_on signal to logic zero.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Example Top-Level File
■
6–15
Incomplete write operation
The state machine issues a series of write requests that are less than the maximum
burst size supported by your controller variation. The addresses are then read
back to ensure that the controller has issued the correct signals to the memory. This
test is only applicable in full-rate mode, when the local burst size is two. You can
skip this test by setting the test_incomplete_writes_on signal to logic zero.
■
Byte enable/data mask pin operation
The state machine issues two sets of write commands, the first of which clears a
range of addresses. The second set of write commands has only one byte enable bit
asserted. The state machine then issues a read request to the same addresses and
the data is verified. This test checks if the data mask pins are operating correctly.
You can skip this test by setting the test_dm_pin_on signal to logic zero.
■
Address pin operation
The example driver generates a series of write and read requests starting with an
all-zeros pattern, a walking-one pattern, a walking-zero pattern, and ending with
an all-zeros pattern. This test checks to make sure that all the individual address
bits are operating correctly. You can skip this test by setting the
test_addr_pin_on signal to logic zero.
■
Low-power mode operation
The example driver requests that the controller place the memory into
power-down and self-refresh states, and hold it in those states for the amount of
time specified by the COUNTER_VALUE signal. You can vary this value to adjust
the duration the memory is kept in the low-power states. This test is only available
if your controller variation enables the low-power mode option.
The example driver has four outputs that allow you to observe which tests are
currently running and if the tests are passing. The pass not fail (pnf) signal goes low
once one or more errors occur and remains low. The pass not fail per byte
(pnf_per_byte) signal goes low when there is incorrect data in a byte but goes back
high again once correct data is observed in the following byte. The test_status
signal indicates the test that is currently running, allowing you to determine which
test has failed. The test_complete signal goes high for a single clock cycle at the
end of the set of tests.
Table 6–11 shows the bit mapping for each test status.
Table 6–11. Test Status[] Bit Mapping
Bit
0
© February 2010
Altera Corporation
Test
Sequential address test
1
Incomplete write test
2
Data mask pin test
3
Address pin test
4
Power-down test
5
Self-refresh test
6
Auto-precharge test
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Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
Top-level Signals Description
Table 6–12 shows the clock and reset signals.
Table 6–12. Clock and Reset Signals
Name
Direction
Description
global_reset_n
Input
The asynchronous reset input to the controller. All other reset signals
are derived from resynchronized versions of this signal. This signal
holds the complete ALTMEMPHY megafunction, including the PLL, in
reset while low.
pll_ref_clk
Input
The reference clock input to PLL.
soft_reset_n
Input
Edge detect reset input intended for SOPC Builder use or to be
controlled by other system reset logic. It is asserted to cause a
complete reset to the PHY, but not to the PLL used in the PHY.
oct_ctl_rs_value
Input
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol.
oct_ctl_rt_value
Input
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol.
dqs_delay_ctrl_import
Input
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the export port on the
ALTMEMPHY instance with a DLL to the import port on the other
ALTMEMPHY instance.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
6–17
Table 6–13 shows the DDR and DDR2 SDRAM HPC local interface signals.
Table 6–13. Local Interface Signals (Part 1 of 4)
Signal Name
local_address[]
Direction
Input
Description
Memory address at which the burst should start.
■
Full rate controllers
The width of this bus is sized using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 1
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 24 bits wide. To map local_address to
bank, row and column address:
local_address[23:22] = bank address [1:0]
local_address[21:9] = row address [13:0]
local_address [8:0] = col_address[9:1]
The least significant bit (LSB) of the column address (multiples of four) on the
memory side is ignored, because the local data width is twice that of the
memory data bus width.
■
Half rate controllers
The width of this bus is sized using the following equation:
For one chip select:
width = bank bits + row bits + column bits – 2
For multiple chip selects:
width = chip bits + bank bits + row bits + column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 23 bits wide. To map local_address to
bank, row and column address:
local_address is 23 bits wide
local_address[22:21] = bank address
local_address[20:8] = row address [13:0]
local_address [7:0] = col_address[9:2]
Two LSBs of the column address on the memory side are ignored, because the
local data width is four times that of the memory data bus width.
1
© February 2010
Altera Corporation
You can get the information on address mapping from the
<variation_name>_example_top.v or vhd file.
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Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
Table 6–13. Local Interface Signals (Part 2 of 4)
Signal Name
local_be[]
Direction
Input
Description
Byte-enable signal, which you use to mask off individual bytes during writes.
local_be is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm, consider
a full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be
=<
1100
><
0110
><
1010
>
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
local_burstbegin
Input
The Avalon burst begin strobe, which indicates the beginning of an Avalon
burst. This signal is only available when the local interface is an Avalon-MM
interface and the memory burst length is greater than 2. Unlike all other
Avalon-MM signals, the burst begin signal does not stay asserted if
local_ready is deasserted.
For write transactions, assert this signal at the beginning of each burst transfer
and keep this signal high for one cycle per burst transfer, even if the slave has
deasserted the local_ready signal. This signal is sampled at the rising edge
of phy_clk when the local_write_req signal is asserted. After the
slave deasserts the local_ready signal, the master keeps all the write
request signals asserted until local_ready signal becomes high again.
For read transactions, assert this signal for one clock cycle when read request
is asserted and the local_address from which the data should be read is
given to the memory. After the slave deasserts local_ready
(waitrequest_n in Avalon interface), the master keeps all the read request
signals asserted until the local_ready signal becomes high again.
local_read_req
Input
Read request signal.
You cannot assert read request and write request signals at the same time.
local_refresh_req
Input
User-controlled refresh request. If Enable User Auto-Refresh Controls option
is turned on, local_refresh_req becomes available and you are
responsible for issuing sufficient refresh requests to meet the memory
requirements. This option allows complete control over when refreshes are
issued to the memory including ganging together multiple refresh commands.
Refresh requests take priority over read and write requests unless they are
already being processed.
local_size[]
Input
Controls the number of beats in the requested read or write access to memory,
encoded as a binary number. The range of values depend on the memory burst
length and whether you select full or half rate in the wizard.
If you select a memory burst length 4 and half rate, the local burst length is 1
and so local_size should always be driven with 1.
If you select a memory burst length 4 and full rate, the local burst length is 2
and you should set the local_size to either 1 or 2 for each read or write
request.
local_wdata[]
Input
Write data bus. The width of local_wdata is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
local_write_req
Input
Write request signal. You cannot assert read request and write request signals
at the same time.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
6–19
Table 6–13. Local Interface Signals (Part 3 of 4)
Signal Name
Direction
Description
local_autopch_req
Input
User control of precharge. If Enable Auto-Precharge Control is turned on,
local_autopch_req becomes available and you can request the
controller to issue an auto-precharge write or auto-precharge read command.
These commands cause the memory to issue a precharge command to the
current bank at the appropriate time without an explicit precharge command
from the controller. This is particularly useful if you know the current read or
write is the last one you intend to issue to the currently open row. The next
time you need to use that bank, the access could be quicker as the controller
does not need to precharge the bank before activating the row you wish to
access.
local_powerdn_req
Input
User control of the power-down feature. If Enable Power Down Controls
option is enabled, you can request that the controller place the memory
devices into a power-down state as soon as it can without violating the relevant
timing parameters and responds by asserting the local_powerdn_ack
signal. You can hold the memory in the power-down state by keeping this
signal asserted. The controller brings the memory out of the power-down state
to issue periodic auto-refresh commands to the memory at the appropriate
interval if you hold it in the power-down state. You can release the memory
from the power-down state at any time by deasserting the
local_powerdn_ack signal once it has successfully brought the memory
out of the power-down state.
local_self_rfsh_req
Input
User control of the self-refresh feature. If Enable Self-Refresh Controls
option is enabled, you can request that the controller place the memory
devices into a self-refresh state by asserting this signal. The controller places
the memory in the self-refresh state as soon as it can without violating the
relevant timing parameters and responds by asserting the
local_self_rfsh_ack signal. You can hold the memory in the
self-refresh state by keeping this signal asserted. You can release the memory
from the self-refresh state at any time by deasserting the
local_self_rfsh_req signal and the controller responds by
deasserting the local__self_rfsh_ack signal once it has successfully
brought the memory out of the self-refresh state.
phy_clk
Output
The system clock that the ALTMEMPHY megafunction provides to the user. All
user inputs to and outputs from the DDR high-performance controller must be
synchronous to this clock.
reset_phy_clk_n
Output
The reset signal that the ALTMEMPHY megafunction provides to the user. It is
asserted asynchronously and deasserted synchronously to phy_clk clock
domain.
aux_full_rate_clk
Output
An alternative clock that the ALTMEMPHY megafunction provides to the user.
This clock always runs at the same frequency as the external memory
interface. In half-rate mode, this clock is twice the frequency of the phy_clk
and can be used whenever a 2x clock is required. In full-rate mode, this clock
is driven by the same PLL output as the phy_clk signal.
aux_half_rate_clk
Output
An alternative clock that the ALTMEMPHY megafunction provides to the user.
This clock always runs at half the frequency as the external memory interface.
In full-rate mode, this clock is half the frequency of the phy_clk and can be
used, for example to clock the user side of a half-rate bridge. In half-rate
mode, this clock is driven by the same PLL output as the phy_clk signal.
dll_reference_clk
Output
Reference clock to feed to an externally instantiated DLL.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
Table 6–13. Local Interface Signals (Part 4 of 4)
Signal Name
Direction
Description
reset_request_n
Output
Reset request output that indicates when the PLL outputs are not locked. Use
this signal as a reset request input to any system-level reset controller you
may have. This signal is always low when the PLL is trying to lock, and so any
reset logic using it is advised to detect a reset request on a falling edge rather
than by level detection.
local_init_done
Output
When the memory initialization, training, and calibration are complete, the
ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the
memory controller, which then asserts this signal to indicate that the memory
interface is ready to be used.
Read and write requests are still accepted before local_init_done is
asserted, however they are not issued to the memory until it is safe to do so.
This signal does not indicate that the calibration is successful. To find out if the
calibration is successful, look for the calibration signal,
resynchronization_successful, or postamble_successful
for Stratix IV devices.
local_rdata[]
Output
Read data bus. The width of local_rdata is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
local_rdata_error
Output
Asserted if the current read data has an error. This signal is only available if the
Enable Error Detection and Correction Logic option is turned on. This signal
is asserted together with the local_rdata_valid signal.
If the controller encounters double-bit errors, no correction is made and the
controller asserts this signal.
local_rdata_valid
Output
Read data valid signal. The local_rdata_valid signal indicates that
valid data is present on the read data bus.
local_ready
Output
The local_ready signal indicates that the DDR or DDR2 SDRAM
high-performance controller is ready to accept request signals. If
local_ready is asserted in the clock cycle that a read or write request is
asserted, that request has been accepted. The local_ready signal is
deasserted to indicate that the DDR or DDR2 SDRAM high-performance
controller cannot accept any more requests. The controller is able to buffer
four read or write requests.
local_refresh_ack
Output
Refresh request acknowledge, which is asserted for one clock cycle every time
a refresh is issued. Even if the Enable User Auto-Refresh Controls option is
not selected, local_refresh_ack still indicates to the local interface that
the controller has just issued a refresh command.
local_wdata_req
Output
Write data request signal, which indicates to the local interface that it should
present valid write data on the next clock edge. This signal is only required
when the controller is operating in Native interface mode.
local_powerdn_ack
Output
Power-down request acknowledge signal. This signal is asserted and
deasserted in response to the local_powerdn_req signal from the user.
local_self_rfsh_ack
Output
Self-refresh request acknowledge signal. This signal is asserted and
deasserted in response to the local_self_rfsh_req signal from the
user.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
6–21
Table 6–14 shows the DDR and DDR2 SDRAM interface signals.
Table 6–14. DDR and DDR2 SDRAM Interface Signals
Signal Name
Direction
Description
mem_dq[]
Bidirectional
Memory data bus. This bus is half the width of the local read and write data
busses.
mem_dqs[]
Bidirectional
Memory data strobe signal, which writes data into the DDR or DDR2 SDRAM and
captures read data into the Altera device.
mem_clk (1)
Bidirectional
Clock for the memory device.
mem_clk_n (1)
Bidirectional
Inverted clock for the memory device.
mem_a[]
Output
Memory address bus.
mem_ba[]
Output
Memory bank address bus.
mem_cas_n
Output
Memory column address strobe signal.
mem_cke[]
Output
Memory clock enable signals.
mem_cs_n[]
Output
Memory chip select signals.
mem_dm[]
Output
Memory data mask signal, which masks individual bytes during writes.
mem_odt[]
Output
Memory on-die termination control signal, for DDR2 SDRAM only.
mem_ras_n
Output
Memory row address strobe signal.
mem_we_n
Output
Memory write enable signal.
Note to Table 6–14:
(1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT)
I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses.
Table 6–15 shows the ECC logic signals.
Table 6–15. ECC Logic Signals
Signal Name
© February 2010
Direction
Description
ecc_addr[]
Input
Address for ECC logic.
ecc_be[]
Input
ECC logic byte enable.
ecc_read_req
Input
Read request for ECC logic.
ecc_wdata[]
Input
ECC logic write data.
ecc_write_req
Input
Write request for ECC logic.
ecc_interrupt
Output
Interrupt from ECC logic.
ecc_rdata[]
Output
Return data from ECC logic.
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
6–22
Chapter 6: Functional Description—High-Performance Controller
Top-level Signals Description
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
7. Functional Description—
High-Performance Controller II
The high-performance controller II (HPC II) architecture is an upgraded controller
with higher efficiency and more features than the HPC. HPC II is recommended for all
new designs.
HPC II is pin-out compatible with your existing DDR high-performance designs.
HPC II has the following additional features:
■
Higher efficiency with in-order read and write commands, and out-of-order bank
management command.
■
Run-time programmability to configure the behavior of the controller.
■
Half-rate bridge option to reduce memory access latency.
■
Integrated burst adapter supporting a range of burst sizes on the local interface.
■
Integrated ECC, supporting 40-bit and 72-bit interfaces with partial word writes
and optional write back on error.
■
Support for multi-rank UDIMMs and RDIMMs.
Upgrading from HPC to HPC II
If you want to migrate your designs from the existing HPC to the more efficient
HPC II, you have to ensure that you do the following:
■
In the Preset Editor dialog box, assign the following HPC II timing parameters to
match your memory specification. Set these parameters according to the memory
datasheet:
■
tFAW
■
tRRD
■
tRTP
For example, for Micron DDR3-800 datasheet, tFAW=40 ns, tRRD=10 ns, tRTP=10 ns.
■
If you are using the Avalon-MM interface, HPC II replaces the port interface level
for the AFI and Avalon interface without requiring any top-level change.
■
The side-band signals differ slightly for HPC II. If you use these signals, you need
to perform the following steps.
■
local_refresh_req
You need to drive an additional active high signal, local_refresh_chip, to
control which chip to issue the user-refresh to.
■
local_powerdn_req
The user-manual power signal is no longer supported in HPC II. Instead, you
can select auto power-down on the Controller Settings tab in the MegaWizard
Plug-In Manager, and specify the desired time-out (n cyles) after which the
controller automatically powers down the memory.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
■
Because HPC II only supports a specific memory burst length, you must update
the memory burst length to match the controller settings in Table 7–1.
Table 7–1. Burst Length Support
Controller
HPC
DDR
Burst length of 2 and 4
DDR2
Burst length of 4
■
HPC II
Burst length of 4 in full-rate
mode, and burst length of 8 in
half-rate mode.
Because HPC II supports arbitrary user burst length ranging from of 1 to 64, you
can adjust the max_local_size value in HPC II. Adjusting the maximum local
size value changes the width of the local_size signal. The maximum
local_size signal value is 2n–1, where n is the width of the local_size signal.
HP has a fixed local_size signal width of either 1 or 2.
Block Description
Figure 7–1 shows the top-level block diagram of the DDR or DDR2 SDRAM HPC II.
Figure 7–1. DDR and DDR2 SDRAM HPC II Block Diagram
local_addr
local_be
local_burstbegin
local_read_req
local_refresh_req
local_refresh_chip
local_size
local_wdata
local_write_req
local_autopch_req
local_self_rfsh_req
local_multicast
csr_addr
csr_read_req
csr_wdata
csr_write_req
local_init_done
local_rdata
local_rdata_valid
local_rdata_error
local_ready
local_refresh_ack
local_wdata_req
local_powerdn_ack
local_self_rfsh_ack
ecc_interrupt
csr_rdata
csr_rdata_valid
csr_waitrequest
DDR/DDR2 SDRAM HighPerformance Controller II
Control
Logic
mem_a
mem_ba
mem_cas_n
mem_cke
mem_cs_n
mem_dq
mem_dqs
mem_dm
mem_odt (1)
mem_ras_n
mem_we_n
ALTMEMPHY
Megafunction
Note to Figure 7–1:
(1) For DDR2 SDRAM HPC II only.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Block Description
7–3
Figure 7–2 shows a block diagram of the DDR or DDR2 SDRAM HPC II architecture.
Figure 7–2. DDR and DDR2 SDRAM HPC II Architecture Block Diagram
Address and
Command
Decode
Bank
Management
Logic
Command-Issuing
State Machine
Half-Rate Bridge
Avalon-MM Data Slave Interface
Timer
Logic
Write Data
Timing Logic
ODT
Generation
Logic
AFI
Command
Queue
ECC-enabled
Write Data
FIFO
Write Data
Write
Datapath
ECC
Encoder
ECC-enabled
Read Data
Avalon-MM CSR
Slave Interface
ECC
Decoder and
Correction
Read
Datapath
Control Register
Table
PHY Register
Table
The blocks in Figure 7–2 are described in the following sections.
Avalon-MM Data Slave Interface
The Avalon-MM data slave interface accepts read and write requests from the
Avalon-MM master. The width of the data busses, local_wdata and local_rdata,
is twice or four times the width of the external memory interface, depending on
whether you choose full or half rate.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
The local address width is sized based on the memory chip, row, bank, and column
address widths. For example:
■
For multiple chip selects:
width = chip bits + row bits + bank bits + column – N
■
For a single chip select:
width = row bits + bank bits + column – N
Where N = 1 for full-rate controller and 2 for half-rate controller.
For every Avalon transaction, the number of read or write requests can go up to the
maximum local burst count of 64. Altera recommends that you set this maximum
burst count to match your system master's supported burst count.
Write Data FIFO Buffer
The write data FIFO buffer holds the write data and byte-enable from the user logic
until the data is needed by the main state machine. The local_ready signal is
deasserted when either the command queue or write data FIFO buffer is full. The
write data FIFO buffer is wide enough to store the write data and the byte-enable
signals.
Command Queue
The command queue allows the controller to buffer up to eight consecutive reads or
writes. The command queue presents the next 4, 6, or 6 accesses to the internal logic
for the look-ahead bank management. The bank management is more efficient if the
look-ahead is deeper, but a deeper queue consumes more resources, and may cause
maximum frequency degradation.
Other than storing incoming commands, the command queue also maps the local
address to memory address based on the address mapping option selected. By
default, the command queue leverages bank interleaving scheme, where the address
increment goes to the next bank instead of the next row to increase chances of page
hit.
Bank Management Logic
The bank management logic keeps track of the current state in each bank across
multiple chips. It can keep a row open in every bank in your memory system. When a
command is issued by the state machine, the bank management logic is updated with
the latest bank status. With the look-ahead capability, the main state machine is able to
issue early bank management commands. With the auto-precharge feature, the
controller supports an open page policy, where the last accessed row in each bank is
kept open and a close page policy, where a bank is closed after it is used.
Timer Logic
The timer logic models the state of each bank in the memory interface. The timer logic
models the internal behavior of each bank and provides status output signals to the
state machine. The state machine then decides whether to issue the look-ahead bank
management command based on the timer status signals.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
7–5
Command-Issuing State Machine
The command-issuing state machine decides what DDR commands to issue based on
the inputs from the command queue, the bank management logic, and the timer logic.
The command-issuing state machine operates in two modes: full-rate or half-rate. The
full-rate state machine supports 1T address and command, and always issues
memory burst length of 4. The half-rate state machine supports 2T address and
command, and always issues memory burst length of 8.
1
A longer memory burst length, in this case 8 beats, increases the command bandwidth
by allowing more data cycles for the same amount of command cycles. A longer
memory burst length also provides more command cycles that ensures a more
effective look-ahead bank management. However, longer memory burst lengths are
less efficient if the bursts you issue do not provide enough data to fill the burst.
This state machine accepts any local burst count of 1 to 64. The built-in burst adapter
in this state machine maps the local burst count to the most efficient memory burst.
The state machine also supports reads and writes that start on non-aligned memory
burst boundary addresses. For effective command bus bandwidth, this state machine
supports additive latency which issues reads and writes immediately after the ACT
command. This state machine accepts additive latency values greater or equal to tRCD
– 1, in clock cycle unit (tCK).
Address and Command Decode Logic
When the main state machine issues a command to the memory, it asserts a set of
internal signals. The address and command decode logic turns these signals into AFI
specific commands and address. This block generates the following signals:
■
Clock enable and reset signals: afi_cke, afi_rst_n
■
Command and address signals: afi_cs_n, afi_ba, afi_addr, afi_ras_n,
afi_cas_n, afi_we_n
Write and Read Datapath, and Write Data Timing Logic
The write and read datapath, and the write data timing logic generate the AFI read
and write control signals.
When the state machine issues a write command to the memory, the write data for
that write burst has to be fetched from the write data FIFO buffer. The relationship
between the write command and write data depends on the afi_wlat signal. This
logic presents the write data FIFO read request signal so that the data arrives on the
external memory interface DQ pins at the correct time.
During write, the following AFI signals are generated based on the state machine
outputs and the afi_wlat signal:
© February 2010
■
afi_dqs_burst
■
afi_wdata_valid
■
afi_wdata
■
afi_dm
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
During read, the afi_doing_read signal generates the afi_rdata_valid signal
and controls the ALTMEMPHY postamble circuit.
ODT Generation Logic
The ODT generation logic generates the necessary ODT signals for DDR2 memory
devices, based on the scheme recommended by Altera.
Figure 7–2 shows which ODT signal on the adjacent DIMM is enabled for DDR2
SDRAM.
Table 7–2. ODT
Write or Read On
ODT Enabled
mem_cs[0]
mem_odt[2]
mem_cs[1]
mem_odt[3]
mem_cs[2]
mem_odt[0]
mem_cs[3]
mem_odt[1]
User-Controlled Side-Band Signals
The user-controlled side-band signals consists of the following signals.
User Auto-Precharge Commands
The auto-precharge read and auto-precharge write commands allow you to indicate
to the memory device that this read or write command is the last access to the
currently open row. The memory device automatically closes or auto-precharges the
page it is currently accessing so that the next access to the same bank is quicker.
This command is useful for applications that require fast random accesses. You can
request an auto-precharge by asserting the local_autopch signal during a read or
write request.
User-Refresh Commands
The user-refresh command enables the request to place the memory into refresh
mode. The user-refresh control takes precedence over a read or write request. You can
issue up to nine consecutive refresh commands to the memory.
Multi-Cast Write
The multi-cast write request signal allows you to ask the controller to send the current
write requests to all the chip-selects. This means that the write data is written to all the
ranks in the system. The multi-cast write feature is useful for tRC mitigation where you
can cycle through chips to continuously read data without hitting tRC. The multi-cast
write is not supported in ECC and RDIMM modes.
Low-Power Mode Logic
There are two types of low-power mode logic: user-controlled self-refresh logic and
automatic power-down with programmable time-out logic.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
7–7
User-Controlled Self-Refresh Logic
When you assert the local_self_rfsh_req signal, the controller completes all
pending reads and writes before it places the memory into self-refresh mode. Once the
controller places the memory into self-refresh mode, it responds by asserting the
acknowledge signal, local_self_rfsh_ack. You can leave the memory in
self-refresh mode for as long as you choose.
To bring the memory out of self-refresh mode, you must deassert the request signal,
and the controller responds by deasserting the acknowledge signal when the memory
is no longer in self-refresh mode.
Automatic Power-Down with Programmable Time-Out
The controller automatically places the memory in power-down mode to save power
if the requested number of idle controller clock cycles is observed in the controller.
The Auto Power Down Cycles parameter on the Controller Settings tab allows you
to specify a range between 1 to 65,535 idle controller clock cycles. The counter for the
programmable time-out starts when there are no user read or write requests in the
command queue. Once the controller places the memory in power-down mode, it
responds by asserting the acknowledge signal, local_powerdown_ack.
Configuration and Status Register (CSR) Interface
The configuration and status register interface is a 32-bit wide interface that uses the
Avalon-MM interface standard. The CSR interface allows you to configure the timing
parameters, address widths, and the behavior of the controller. If you do not need this
feature, you can disable it and all the programmable settings are fixed to the values
configured during the generation process. This interface is synchronous to the
controller clock.
Refer to Table 7–9 through Table 7–23 on page 7–20 for detailed information about the
register maps.
Error Correction Coding (ECC)
The optional ECC logic comprises an encoder and a decoder-corrector, which can
detect and correct single-bit errors, and detect double-bit errors. The ECC logic is
available in two widths: 64/72 bit and 32/40 bit. The ECC logic has the following
features:
© February 2010
■
Hamming code ECC that encodes every 64 or 32 bits of data into 72 or 40 bits of
codeword.
■
A latency increase of one clock for both writes and reads.
■
Detects and corrects all single-bit errors.
■
Detects all double-bit errors.
■
Counts the number of single-bit and double-bit errors.
■
Accepts partial writes, which trigger a read-modify-write cycle, for memory
devices with dm pins.
■
Is able to inject single-bit and double-bit errors to trigger ECC correction for
testing and debugging purposes.
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
■
Generates an interrupt signal when an error occurs.
When a single-bit or double-bit error occurs, the ECC logic triggers the
ecc_interrupt signal to inform you that an ECC error has occurred. When a
single-bit error occurs, the ECC logic issues an internal read to the error address, and
performs an internal write to write back the corrected data. When a double-bit error
occurs, the ECC logic does not do any error correction but it asserts the
local_rdata_error signal to indicate that the data is incorrect. The
local_rdata_error signal follows the same timing as the local_rdata_valid
signal.
Enabling auto-correction allows the ECC logic to hold off all controller pending
activities until the correction is complete. You can choose to disable auto-correction
and schedule the correction manually when the controller is idle to ensure better
system efficiency. To manually correct ECC errors, do the following:
1. When an interrupt occurs, read out the SBE_ERROR register. When a single-bit
error occurs, the SBE_ERROR register is equal to one.
2. Read out the ERR_ADDR register.
3. Correct the single-bit error by doing one of the following:
■
Issue a dummy write to the memory address stored in the ERR_ADDR register.
A dummy write is a write request with the local_be signal zero, that triggers
a partial write which is effectively a read-modify-write event. The partial write
corrects the data at that address and writes it back.
or
■
Enable the ENABLE_AUTO_CORR register using the CSR interface and issue a
read request to the memory address stored in the ERR_ADDR register. The read
request triggers auto-error correction to the memory address stored in the
ERR_ADDR register.
Partial Writes
The ECC logic supports partial writes. Along with the address, data, and burst
signals, the Avalon-MM interface also supports a signal vector, local_be, that is
responsible for byte-enable. Every bit of this signal vector represents a byte on the
data-bus. Thus, a logic low on any of these bits instructs the controller not to write to
that particular byte, resulting in a partial write. The ECC code is calculated on all
bytes of the data-bus. If any bytes are changed, the ECC code must be recalculated
and the new code must be written back to the memory.
For partial writes, the ECC logic performs the following steps:
1. The ECC logic sends a read command to the partial write address.
2. Upon receiving a return data from the memory for the particular address, the ECC
logic decodes the data, checks for errors, and then merges the corrected or correct
dataword with the incoming information.
3. The ECC logic issues a write to write back the updated data and the new ECC
code.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Block Description
7–9
The following corner cases can occur:
■
A single-bit error during the read phase of the read-modify-write process. In this
case, the single-bit error is corrected first, the single-bit error counter is
incremented and then a partial write is performed to this corrected decoded data
word.
■
A double-bit error during the read phase of the read-modify-write process. In this
case, the double-bit error counter is incremented and an interrupt is issued. A new
write word is written back to the memory location. The ECC status register keeps
track of the error information.
Figure 7–3 and Figure 7–4 show the partial write operation for HPC II.
Figure 7–3. Partial Write for HPC II—Full Rate
0
local_address
1
2
local_size
X1
local_be
local_wdata
XF
01234567
89ABCDEF
mem_dm
67
mem_dq
R
R
R
EF
CD
AB
89
Note to Figure 7–3:
(1) R represents the internal read-back memory data during the read-modify-write process.
Figure 7–4. Partial Write for HPC II—Half Rate
local_address
0
local_size
1
local_be
X1
local_wdata
01234567
mem_dm
mem_dq
67
R
R
R
Note to Figure 7–4:
(1) R represents the internal read-back memory data during the read-modify-write process.
Partial Bursts
DIMMs that do not have the DM pins do not support partial bursts. A minimum of
four (half rate) or eight words (full rate) must be written to the memory at the same
time.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Example Top-Level File
Figure 7–5 shows the partial burst operation for HPC II.
Figure 7–5. Partial Burst for HPC II
local_address
0
local_size
1
local_be
X1
local_wdata
01234567
mem_dm
mem_dq
67
45
23
01
Example Top-Level File
The MegaWizard Plug-In Manager helps you create an example top-level file that
shows you how to instantiate and connect the DDR or DDR2 SDRAM HPC II. The
example top-level file consists of the DDR or DDR2 SDRAM HPC II, some driver logic
to issue read and write requests to the controller, a PLL to create the necessary clocks,
and a DLL (Stratix series only). The example top-level file is a working system that
you can compile and use for both static timing checks and board tests.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Example Top-Level File
7–11
Figure 7–6 shows the testbench and the example top-level file.
Figure 7–6. Testbench and Example Top-Level File
Testbench
Example Design
pnf
test_complete
WizardGenerated
Memory Model
DDR SDRAM Controller
Example Driver
ALTMEMPHY
Control
Logic
DLL
PLL
clock_source
Table 7–3 describes the files that are associated with the example top-level file and the
testbench.
Table 7–3. Example Top-Level File and Testbench Files
Filename
Description
<variation name>_example_top_tb.v or .vhd
Testbench for the example top-level file.
<variation name>_example_top.v or .vhd
Example top-level file.
<variation name>_mem_model.v or .vhd
Associative-array memory model.
<variation name>_full_mem_model.v or .vhd
Full-array memory model.
<variation name>_example_driver.v or .vhd
Example driver.
<variation name> .v or .vhd
Top-level description of the custom MegaCore function.
<variation name>.qip
Contains Quartus II project information for your MegaCore
function variations.
There are two Altera-generated memory models available—associative-array
memory model and full-array memory model.
The associative-array memory model (<variation name>_mem model.v) allocates
reduced set of memory addresses with a default depth of 2,048 or 2K address spaces.
This allocation allows for a larger memory array compilation and simulation which
enables you to easily reconfigure the depth of the associate array.
The full-array memory model (<variation name>_mem model_full.v) allocates
memory for all addresses accessible by the DDR cores. This allocation makes it
impossible to simulate large memory designs.
Both the memory models display similar behaviors and have the same calibration
time.
1
© February 2010
The memory model, <variation name>_test_component.v/vhd, used in SOPC Builder
designs, is actually a variation of the full-array memory model. To ensure your
simulation works in SOPC Builder, use memory model with less than 512-Mbit
capacity.
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Chapter 7: Functional Description—High-Performance Controller II
Example Top-Level File
Example Driver
The example driver is a self-checking test pattern generator for the memory interface.
It uses a state machine to write and read from the memory to verify that the interface
is operating correctly.
The example driver performs the following tests and loops back the tests indefinitely:
■
Sequential addressing writes and reads
The state machine writes pseudo-random data generated by a linear feedback shift
register (LFSR) to a set of incrementing row, bank, and column addresses. The
state machine then resets the LFSR, reads back the same set of addresses, and
compares the data it receives against the expected data. You can adjust the length
and pattern of the bursts that are written by changing the MAX_ROW, MAX_BANK,
and MAX_COL constants in the example driver source code, and the entire memory
space can be tested by adjusting these values. You can skip this test by setting the
test_seq_addr_on signal to logic zero.
■
Incomplete write operation
The state machine issues a series of write requests that are less than the maximum
burst size supported by your controller variation. The addresses are then read
back to ensure that the controller has issued the correct signals to the memory. This
test is only applicable in full-rate mode, when the local burst size is two. You can
skip this test by setting the test_incomplete_writes_on signal to logic zero.
■
Byte enable/data mask pin operation
The state machine issues two sets of write commands, the first of which clears a
range of addresses. The second set of write commands has only one byte enable bit
asserted. The state machine then issues a read request to the same addresses and
the data is verified. This test checks if the data mask pins are operating correctly.
You can skip this test by setting the test_dm_pin_on signal to logic zero.
■
Address pin operation
The example driver generates a series of write and read requests starting with an
all-zeros pattern, a walking-one pattern, a walking-zero pattern, and ending with
an all-zeros pattern. This test checks to make sure that all the individual address
bits are operating correctly. You can skip this test by setting the
test_addr_pin_on signal to logic zero.
■
Low-power mode operation
The example driver requests the controller to place the memory into power-down
and self-refresh states, and hold it in those states for the amount of time specified
by the COUNTER_VALUE signal. You can vary this value to adjust the duration the
memory is kept in the low-power states. This test is only available if your
controller variation enables the low-power mode option.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
7–13
The example driver has four outputs that allow you to observe which tests are
currently running and if the tests are passing. The pass not fail (pnf) signal goes low
once one or more errors occur and remains low. The pass not fail per byte
(pnf_per_byte) signal goes low when there is incorrect data in a byte but goes back
high again once correct data is observed in the following byte. The test_status
signal indicates the test that is currently running, allowing you to determine which
test has failed. The test_complete signal goes high for a single clock cycle at the
end of the set of tests.
Table 7–4 shows the bit mapping for each test status.
Table 7–4. Test Status[] Bit Mapping
Bit
Test
0
Sequential address test
1
Incomplete write test
2
Data mask pin test
3
Address pin test
4
Power-down test
5
Self-refresh test
6
Auto-precharge test
Top-level Signals Description
Table 7–5 shows the clock and reset signals.
Table 7–5. Clock and Reset Signals (Part 1 of 2)
Name
Direction
Description
global_reset_n
Input
The asynchronous reset input to the controller. All other reset signals
are derived from resynchronized versions of this signal. This signal
holds the complete ALTMEMPHY megafunction, including the PLL, in
reset while low.
pll_ref_clk
Input
The reference clock input to PLL.
phy_clk
Output
The system clock that the ALTMEMPHY megafunction provides to the
user. All user inputs to and outputs from the DDR HPC II must be
synchronous to this clock.
reset_phy_clk_n
Output
The reset signal that the ALTMEMPHY megafunction provides to the
user. It is asserted asynchronously and deasserted synchronously to
phy_clk clock domain.
aux_full_rate_clk
Output
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at the same frequency as the external
memory interface. In half-rate mode, this clock is twice the frequency
of the phy_clk and can be used whenever a 2x clock is required. In
full-rate mode, this clock is driven by the same PLL output as the
phy_clk signal.
© February 2010
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–5. Clock and Reset Signals (Part 2 of 2)
Name
Direction
Description
aux_half_rate_clk
Output
An alternative clock that the ALTMEMPHY megafunction provides to
the user. This clock always runs at half the frequency as the external
memory interface. In full-rate mode, this clock is half the frequency of
the phy_clk and can be used, for example to clock the user side of a
half-rate bridge. In half-rate mode, or if the Enable Half Rate Bridge
option is turned on, this clock is driven by the same PLL output that
drives the phy_clk signal.
dll_reference_clk
Output
Reference clock to feed to an externally instantiated DLL.
reset_request_n
Output
Reset request output that indicates when the PLL outputs are not
locked. Use this signal as a reset request input to any system-level
reset controller you may have. This signal is always low when the PLL
is trying to lock, and so any reset logic using it is advised to detect a
reset request on a falling edge rather than by level detection.
soft_reset_n
Input
Edge detect reset input intended for SOPC Builder use or to be
controlled by other system reset logic. It is asserted to cause a
complete reset to the PHY, but not to the PLL used in the PHY.
oct_ctl_rs_value
Input
ALTMEMPHY signal that specifies the serial termination value. Should
be connected to the ALT_OCT megafunction output
seriesterminationcontrol.
oct_ctl_rt_value
Input
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol.
dqs_delay_ctrl_import
Input
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the export port on the
ALTMEMPHY instance with a DLL to the import port on the other
ALTMEMPHY instance.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
7–15
Table 7–6 shows the DDR and DDR2 SDRAM HPC II local interface signals.
Table 7–6. Local Interface Signals (Part 1 of 4)
Signal Name
local_address[]
Direction
Input
Description
Memory address at which the burst should start.
By default, the local address is mapped to the bank interleaving scheme. You
can change the ordering via the Local-to-Memory Address Mapping option
in the Controller Settings page.
The width of this bus is sized using the following equation:
■
Full rate controllers
The width of this bus is sized using the following equation:
For one chip select:
width = row bits + bank bits + column bits – 1
For multiple chip selects:
width = chip bits + row bits + bank bits + column bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 24 bits wide. To map local_address to
bank, row and column address:
local_address is 24 bits wide
local_address[23:11] = row address[12:0]
local_address[10:9] = bank address [1:0]
local_address [8:0] = column address[9:1]
The least significant bit (LSB) of the column address (multiples of four) on
the memory side is ignored, because the local data width is twice that of the
memory data bus width.
■
Half rate controllers
The width of this bus is sized using the following equation:
For one chip select:
width = row bits + bank bits + column bits – 2
For multiple chip selects:
width = chip bits + row bits + bank bits + column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, then the local address is 23 bits wide. To map local_address to
bank, row and column address:
local_address is 23 bits wide
local_address[22:10] = row address[12:0]
local_address[9:8] = bank address [1:0]
local_address [7:0] = column address[9:2]
Two LSBs of the column address on the memory side are ignored, because
the local data width is four times that of the memory data bus width.
© February 2010
Altera Corporation
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–6. Local Interface Signals (Part 2 of 4)
Signal Name
local_be[]
Direction
Description
Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm,
consider a full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be
=<
1100
><
0110
><
1010
>
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
local_burstbegin
Input
The Avalon burst begin strobe, which indicates the beginning of an Avalon
burst. Unlike all other Avalon-MM signals, the burst begin signal does not
stay asserted if local_ready is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even if the
slave has deasserted the local_ready signal. This signal is sampled at the
rising edge of phy_clk when the local_write_req signal is asserted.
After the slave deasserts the local_ready signal, the master keeps all the
write request signals asserted until local_ready signal becomes high
again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and the local_address from which the data should
be read is given to the memory. After the slave deasserts local_ready
(waitrequest_n in Avalon interface), the master keeps all the read
request signals asserted until the local_ready signal becomes high
again.
local_read_req
Input
Read request signal. You cannot assert read request and write request signal
at the same time.
local_refresh_req
Input
User-controlled refresh request. If Enable User Auto-Refresh Controls
option is turned on, local_refresh_req becomes available and you are
responsible for issuing sufficient refresh requests to meet the memory
requirements. This option allows complete control over when refreshes are
issued to the memory including grouping together multiple refresh
commands. Refresh requests take priority over read and write requests,
unless the requests are already being processed.
local_refresh_chip
Input
Controls which chip to issue the user refresh to. This active high signal is
used together with the local_refresh_req signal. This signal is as
wide as the memory chip select. This signal asserts a high value to each bit
that represents the refresh for the corresponding memory chip.
For example: If the local_refresh_chip signal is assigned with a
value of 4’b0101, the controller refreshes the memory chips 0 and 2, and
memory chips 1 and 3 are not refreshed.
local_size[]
Input
Controls the number of beats in the requested read or write access to
memory, encoded as a binary number. The range of supported Avalon burst
lengths is 1 to 64. The width of this signal is derived based on the burst count
specified in the Local Maximum Burst Count option. With the derived width,
choose a value ranging from 1 to the local maximum burst count specified.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
7–17
Table 7–6. Local Interface Signals (Part 3 of 4)
Signal Name
Direction
Description
local_wdata[]
Input
Write data bus. The width of local_wdata is twice that of the memory
data bus for a full rate controller; four times the memory data bus for a half
rate controller.
local_write_req
Input
Write request signal. You cannot assert read request and write request signal
at the same time.
local_multicast
Input
In-band multi-cast write request signal. This active high signal is used
together with the local_write_req signal. When this signal is asserted
high, data is written to all the memory chips available.
local_autopch_req
Input
User control of auto-precharge. If Enable Auto-Precharge Control option is
turned on, the local_autopch_req signal becomes available, and you
can request the controller to issue an auto-precharge write or auto-precharge
read command. These commands cause the memory to issue a precharge
command to the current bank at the appropriate time without an explicit
precharge command from the controller. This is particularly useful if you
know the current read or write is the last one you intend to issue to the
currently open row. The next time you need to use that bank, the access
could be quicker as the controller does not need to precharge the bank before
activating the row you wish to access.
If you issue a local burst longer than the memory burst with the
local_autopch_req signal asserted, the controller only issues
auto-precharge with the last read or write command.
local_self_rfsh_req
local_init_done
Input
User control of the self-refresh feature. If Enable Self-Refresh Controls
option is enabled, you can request that the controller place the memory
devices into a self-refresh state by asserting this signal. The controller places
the memory in the self-refresh state as soon as it can without violating the
relevant timing parameters and responds by asserting the
local_self_rfsh_ack signal. You can hold the memory in the
self-refresh state by keeping this signal asserted. You can release the
memory from the self-refresh state at any time by deasserting the
local_self_rfsh_req signal and the controller responds by
deasserting the local__self_rfsh_ack signal once it has
successfully brought the memory out of the self-refresh state.
Output
When the memory initialization, training, and calibration are complete, the
ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the
memory controller, which then asserts this signal to indicate that the memory
interface is ready to be used.
Read and write requests are still accepted before local_init_done is
asserted, however they are not issued to the memory until it is safe to do so.
This signal does not indicate that the calibration is successful.
local_rdata[]
Output
Read data bus. The width of local_rdata is twice that of the memory
data bus for a full rate controller; four times the memory data bus for a half
rate controller.
local_rdata_error
Output
Asserted if the current read data has an error. This signal is only available if
the Enable Error Detection and Correction Logic option is turned on. This
signal is asserted together with the local_rdata_valid signal.
If the controller encounters double-bit errors, no correction is made and the
controller asserts this signal.
local_rdata_valid
© February 2010
Altera Corporation
Output
Read data valid signal. The local_rdata_valid signal indicates that
valid data is present on the read data bus.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
Table 7–6. Local Interface Signals (Part 4 of 4)
Signal Name
Direction
Description
local_ready
Output
The local_ready signal indicates that the DDR or DDR2 SDRAM HPC II
is ready to accept request signals. If local_ready is asserted in the clock
cycle that a read or write request is asserted, that request has been accepted.
The local_ready signal is deasserted to indicate that the DDR or DDR2
SDRAM HPC II cannot accept any more requests. The DDR or DDR2 SDRAM
HPC II is able to buffer eight read or write requests.
local_refresh_ack
Output
Refresh request acknowledge, which is asserted for one clock cycle every
time a refresh is issued. Even if the Enable User Auto-Refresh Controls
option is not selected, local_refresh_ack still indicates to the local
interface that the controller has just issued a refresh command.
local_self_rfsh_ack
Output
Self-refresh request acknowledge feature. This signal is asserted and
deasserted in response to the local_self_rfsh_req signal from the
user.
local_power_down_ack
Output
Auto power-down acknowledge signal. This signal is asserted for one clock
cycle every time auto power-down is issued.
ecc_interrupt
Output
Interrupt signal from the ECC logic. This signal is asserted when the ECC
feature is turned on, and an error is detected. This signal remains asserted
until the user logic clears the error through the CSR interface.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Top-level Signals Description
7–19
Table 7–7 shows the DDR and DDR2 SDRAM HPC II CSR interface signals.
Table 7–7. CSR Interface Signals
Signal Name
Direction
Description
csr_addr[]
Input
Register map address.The width of csr_addr is 16 bits.
csr_be[]
Input
Byte-enable signal, which you use to mask off individual bytes during writes.
csr_be is active high.
csr_wdata[]
Input
Write data bus. The width of csr_wdata is 32 bits.
csr_write_req
Input
Write request signal. You cannot assert csr_write_req and
csr_read_req signals at the same time.
csr_read_req
Input
Read request signal. You cannot assert csr_read_req and
csr_write_req signals at the same time.
csr_rdata[]
Output
Read data bus. The width of csr_rdata is 32 bits.
csr_rdata_valid
Output
Read data valid signal. The csr_rdata_valid signal indicates that valid
data is present on the read data bus.
csr_waitrequest
Output
The csr_waitrequest signal indicates that the HPC II is busy and not
ready to accept request signals. If the csr_waitrequest signal goes
high in the clock cycle when a read or write request is asserted, that request
is not accepted. If the csr_waitrequest signal goes low, the HPC II is
then ready to accept more requests.
Table 7–8 shows the DDR and DDR2 SDRAM interface signals.
Table 7–8. DDR and DDR2 SDRAM Interface Signals
Signal Name
Direction
Description
mem_dq[]
Bidirectional
Memory data bus. This bus is half the width of the local read and write data
busses.
mem_dqs[]
Bidirectional
Memory data strobe signal, which writes data into the DDR or DDR2 SDRAM and
captures read data into the Altera device.
mem_dqs_n[]
Bidirectional
Inverted memory data strobe signal, which is used together with the mem_dqs
signal to improve signal integrity.
mem_clk (1)
Bidirectional
Clock for the memory device.
mem_clk_n (1)
Bidirectional
Inverted clock for the memory device.
mem_addr[]
Output
Memory address bus.
mem_ba[]
Output
Memory bank address bus.
mem_cas_n
Output
Memory column address strobe signal.
mem_cke[]
Output
Memory clock enable signals.
mem_cs_n[]
Output
Memory chip select signals.
mem_dm[]
Output
Memory data mask signal, which masks individual bytes during writes.
mem_odt[]
Output
Memory on-die termination control signal, for DDR2 SDRAM only.
mem_ras_n
Output
Memory row address strobe signal.
mem_we_n
Output
Memory write enable signal.
Note to Table 7–8:
(1) The mem_clk signals are output only signals from the FPGA. However, in the Quartus II software they must be defined as bidirectional (INOUT)
I/Os to support the mimic path structure that the ALTMEMPHY megafunction uses.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Register Maps Description
Table 7–9 through Table 7–23 show the register maps for the DDR and DDR2 SDRAM
HPC II.
Table 7–9. Register Map
Address
Contents
0x005
Mode register 0-1
0x006
Mode register 2-3
0x100
ALTMEMPHY status and control register
0x110
Controller status and configuration register
0x120
Memory address size register 0
0x121
Memory address size register 1
0x122
Memory address size register 2
0x123
Memory timing parameters register 0
0x124
Memory timing parameters register 1
0x125
Memory timing parameters register 2
0x126
Memory timing parameters register 3
0x130
ECC control register
0x131
ECC status register
0x132
ECC error address register
Table 7–10. Address 0x005 Mode Register 0-1 (Part 1 of 2)
Bit
Name
Default
Access
Description
0-2
Burst length
8
RO
This value is set to 4 for full-rate and 8 in half-rate
for DDR or DDR2 SDRAM HPC II
BT
0
RO
This value is set to 0 because the DDR or DDR2
SDRAM HPC II only supports sequential bursts.
CAS latency
—
RW
This value must be set to match the memory CAS
latency. You must set this value in CSR interface
register map as well.
7
Reserved
0
—
Reserved for future use.
8
DLL
0
RW
Not used by the controller, but you can set and
programm into the memory device mode register.
Write recovery
—
RW
This value must be set to match the memory write
recovery time (tWR). You must set this value in CSR
interface register map as well.
PD
0/1
RO
This value is set to 0 because the DDR or DDR2
SDRAM HPC II only supports power-down fast exit
mode.
3
4–6
9–11
12
13–15
Reserved
0
—
Reserved for future use.
16
DLL
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
17
ODS
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
7–21
Table 7–10. Address 0x005 Mode Register 0-1 (Part 2 of 2)
Bit
Name
Default
Access
Description
18
RTT
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
19–21
AL
—
RW
Additive latency setting. The default value for these
bits is set by the MegaWizard Additive Latency
setting for your controller instance. You must set
this value in CSR interface register map as well.
22
RTT
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
RTT/WL/OCD
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
26
DQS#
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
27
TDQS/RDQS
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
28
QOFF
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved
0
—
Reserved for future use.
23–25
29–31
Table 7–11. Address 0x006 Mode Register 2-3
Bit
Name
Default
Access
Description
0-2
Reserved
0
—
Reserved for future use.
3-5
CWL
—
RW
CAS write latency setting. You must set this value
in CSR interface register map as well.
6
ASR
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
7
SRT/ET
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
8
Reserved
0
—
Reserved for future use.
9–10
RTT_WR
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
11–15
Reserved
0
—
Reserved for future use.
16–17
MPR_RF
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
MPR
0
RW
Not used by the controller, but you can set and
program into the memory device mode register.
Reserved
0
—
Reserved for future use.
18
19–31
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–12. Address 0x100 ALTMEMPHY Status and Control Register
Bit
Name
Default
Access
Description
0
CAL_SUCCESS
—
RO
This bit reports the value of the ALTMEMPHY
ctl_cal_success output. Writing to this bit
has no effect.
1
CAL_FAIL
—
RO
This bit reports the value of the ALTMEMPHY
ctl_cal_fail output. Writing to this bit has no
effect.
2
CAL_REQ
0
RW
Writing a 1 to this bit asserts the ctl_cal_req
signal to the ALTMEMPHY megafunction. Writing a
0 to this bit deaaserts the signal, and the
ALTMEMPHY megafunction will then initiate its
calibration sequence.
c You must not use this register during the
ALTMEMPHY megafunction calibration. You
must wait until the CAL_SUCCESS or
CAL_FAIL register shows a value of 1.
3–7
Reserved
0
—
Reserved for future use.
8–13
CLOCK_OFF
0
RW
Writing a 1 to any of the bits in this register causes
the appropriate ctl_mem_clk_disable signal
to the ALTMEMPHY megafunction to be asserted,
which will disable the memory clock outputs.
Writing a 0 to this register causes the signal to be
deasserted and the memory clocks to be reenabled.
ALTMEMPHY can support up to 6 individual
memory clocks, each bit will represent each
individual clock.
14-30
Reserved
0
—
Reserved for future use.
Table 7–13. Address 0x110 Controller Status and Configuration Register (Part 1 of 2)
Bit
0–15
Name
AUTO_PD_CYCLES
Default
Access
Description
0x0
RW
The number of idle clock cycles after which the
controller should place the memory into
power-down mode. The controller is considered
to be idle if there are no commands in the
command queue. Setting this register to 0
disables the auto power-down mode. The
default value of this register depends on the
values set during the generation of the design.
16
AUTO_PD_ACK
1
RO
This bit indicates that the memory is in
power-down state.
17
SELF_RFSH
0
RW
Setting this bit, or asserting the
local_self_rfsh signal, causes the
memory to go into self-refresh state.
18
SELF_RFSH-ACK
0
RO
This bit indicates that the memory is in
self-refresh state.
19
Reserved
0
—
Reserved for future use.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
7–23
Table 7–13. Address 0x110 Controller Status and Configuration Register (Part 2 of 2)
Bit
20–21
Name
ADDR_ORDER
Default
Access
00
RW
Description
00 - Chip, row, bank, column.
01 - Chip, bank, row, column.
10 - Reserved for future use.
11 - Reserved for future use.
22
23–24
REGDIMM
0
RW
Setting this bit to 1 enables REGDIMM support
in controller.
CTRL_DRATE
00
RO
These bits represent controller date rate:
00 - Full rate.
01 - Half rate.
10 - Reserved for future use.
11 - Reserved for future use.
24–30
Reserved
0
—
Reserved for future use.
Table 7–14. Address 0x120 Memory Address Size Register 0
Bit
Name
Default
Access
Description
0–7
Column address
width
—
RW
The number of column address bits for the
memory devices in your memory interface. The
range of legal values is 7-12.
8–15
Row address width
—
RW
The number of row address bits for the memory
devices in your memory interface. The range of
legal values is 12-16.
16–19
Bank address width
—
RW
The number of bank address bits for the memory
devices in your memory interface. The range of
legal values is 2-3.
20–23
Chip select address
width
—
RW
The number of chip select address bits for the
memory devices in your memory interface. The
range of legal values is 0-2. If there is only one
single chip select in the memory interface, set
this bit to 0.
24–31
Reserved
0
—
Reserved for future use.
Table 7–15. Address 0x121 Memory Address Size Register 1
Bit
0–31
Name
Data width
representation
(word)
© February 2010
Altera Corporation
Default
Access
Description
—
RW
The number of DQS bits in the memory interface.
This bit can be used to derive the width of the
memory interface by multiplying this value by the
number of DQ pins per DQS pin (typically 8).
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–16. Address 0x122 Memory Address Size Register 2
Bit
0–7
Name
Chip select
representation
Default
Access
—
RW
Description
The number of chip select in binary
representation.
For example, a design with 2 chip selects has the
value of 00000011.
8–31
Reserved
0
—
Reserved for future use.
Table 7–17. Address 0x123 Memory Timing Parameters Register 0
Bit
Name
Default
Access
Description
0–3
tRCD
—
RW
The activate to read or write the timing
parameter. The range of legal values is 2-11
cycles.
4–7
tRRD
—
RW
The activate to activate timing parameter. The
range of legal values is 2-8 cycles.
8–11
tRP
—
RW
The precharge to activate timing parameter. The
range of legal values is 2-11 cycles.
11–15
tMRD
—
RW
The mode register load time parameter. This
value is not used by the controller, as the
controller derives the correct value from the
memory type setting.
16–23
tRAS
—
RW
The activate to precharge timing parameter. The
range of legal values is 4-29 cycles.
24–31
tRC
—
RW
The activate to activate timing parameter. The
range of legal values is 8-40 cycles.
Table 7–18. Address 0x124 Memory Timing Parameters Register 1
Bit
Name
Default
Access
Description
0–3
tWTR
—
RW
The write to read timing parameter. The range of
legal values is 1-10 cycles.
4–7
tRTP
—
RW
The read to precharge timing parameter. The
range of legal values is 2-8 cycles.
8–15
tFAW
—
RW
The four-activate window timing parameter. The
range of legal values is 6-32 cycles.
16–31
Reserved
0
—
Reserved for future use.
Table 7–19. Address 0x125 Memory Timing Parameters Register 2
Bit
Name
Default
Access
Description
0–15
tREFI
—
RW
The refresh interval timing parameter. The range
of legal values is 780-6240 cycles.
16–23
tRFC
—
RW
The refresh cycle timing parameter. The range of
legal values is 12-88 cycles.
24–31
Reserved
0
—
Reserved for future use.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
7–25
Table 7–20. Address 0x126 Memory Timing Parameters Register 3
Bit
Name
Default
Access
Description
0–3
CAS latency, tCL
—
RW
This value must be set to match the memory CAS
latency. You must set this value in the 0x04
register map as well.
4–7
Additive latency, AL
—
RW
Additive latency setting. The default value for
these bits is set in the Memory additive CAS
latency setting in the Preset Editor dialog
box.You must set this value in the 0x05 register
map as well.
8–11
CAS write latency,
CWL
—
RW
CAS write latency setting. You must set this value
in the 0x06 register map as well.
12–15
Write recovery, tWR
—
RW
This value must be set to match the memory
write recovery time (tWR). You must set this value
in the 0x04 register map as well.
16–31
Reserved
0
—
Reserved for future use.
Table 7–21. Address 0x130 ECC Control Register
Bit
Name
Default
Access
Description
0
ENABLE_ECC
1
RW
When 1, enables the generation and checking
of ECC.
1
ENABLE_AUTO_CORR
1
RW
When 1, enables auto-correction when a
single-bit error is detected.
2
GEN_SBE
0
RW
When 0, enables the deliberate insertion of
single-bit errors, bit 0, in the data written to
memory. This bit is only used for testing
purposes.
3
GEN_DBE
0
RW
When 0, enables the deliberate insertion of
double-bit errors, bits 0 and 1, in the data
written to memory. This bit is only used for
testing purposes.
4
ENABLE_INTR
0
RW
When 0, enables the interrupt output.
5
MASK_SBE_INTR
0
RW
When 0, masks the single-bit error interrupt.
6
MASK_DBE_INTR
0
RW
When 0, masks the double-bit error interrupt
7
CLEAR
0
RW
When 0, writing to this self-clearing bit clears
the interrupt signal, and the error status and
error address registers.
9
Reserved
0
—
Reserved for future use.
Table 7–22. Address 0x131 ECC Status Register (Part 1 of 2)
Bit
Name
Default
Access
Description
0
SBE_ERROR
1
RO
Set to 1 when any single-bit errors occur.
1
DBE_ERROR
1
RO
Set to 1 when any double-bit errors occur.
Reserved
0
—
Reserved for future use.
2–7
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
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Chapter 7: Functional Description—High-Performance Controller II
Register Maps Description
Table 7–22. Address 0x131 ECC Status Register (Part 2 of 2)
Bit
Name
Default
Access
Description
8–15
SBE_COUNT
0
RO
Reports the number of single-bit errors that have
occurred since the status register counters were
last cleared.
16–23
DBE_COUNT
0
RO
Reports the number of double-bit errors that
have occurred since the status register counters
were last cleared.
24–31
Reserved
0
—
Reserved for future use.
Table 7–23. Address 0x132 ECC Error Address Register
Bit
0–31
Name
ERR_ADDR
Default
Access
0
RO
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Description
The address of the most recent ECC error. This
address contains concatenation of chip, bank,
row, and column addresses.
© February 2010 Altera Corporation
8. Latency
Latency is defined using the local (user) side frequency and absolute time (ns). There
are two types of latencies that exists while designing with memory controllers—read
and write latencies, which have the following definitions:
1
■
Read latency—the amount of time it takes for the read data to appear at the local
interface after initiating the read request.
■
Write latency—the amount of time it takes for the write data to appear at the
memory interface after initiating the write request.
For a half-rate controller, the local side frequency is half of the memory interface
frequency. For a full-rate controller, the local side frequency is equal to the memory
interface frequency.
Altera defines read and write latencies in terms of the local interface clock frequency
and by the absolute time for the memory controllers. These latencies apply to
supported device families (Table 1–1 on page 1–2) with the following memory
controllers:
■
Legacy DDR and DDR2 SDRAM controllers
■
Half-rate HPC and HPC II
■
Full-rate HPC and HPC II
The latency defined in this section uses the following assumptions:
■
The row is already open, there is no extra bank management needed.
■
The controller is idle, there is no queued transaction pending, indicated by the
local_ready signal asserted high.
■
No refresh cycles occur before the transaction.
The latency for the high-performance controllers comprises many different stages of
the memory interface. Figure 8–1 on page 8–2 shows a typical memory interface read
latency path showing read latency from the time a local_read_req signal assertion
is detected by the controller up to data available to be read from the dual-port RAM
(DPRAM) module.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
8–2
Chapter 8: Latency
Figure 8–1. Typical Latency Path
control_doing_rd
local_read_req
local_addr
FPGA Device
Memory Device
PHY
HighPerformance
Controller
Latency T3
(includes CAS
latency)
Latency T2
Address/Command Generation
Core
mem_cs_n
I/O
Latency T1
Latency T4
Read Datapath
local_rdata
DPRAM
Alignment and
Synchronization
Halfrate
mem_dq [ ]
Capture
mem_dqs [ ]
mem_clk [ ]
Resynchronization
Clock
PLL
0° or 180°
phy_clk
Shifted
Shifted
DQS
Clk
DQS
Clock
mem_clk_n [ ]
PLL
Table 8–1 shows the different stages that make up the whole read and write latency
that Figure 8–1 shows.
Table 8–1. High Performance Controller Latency Stages and Descriptions
Latency Number
Latency Stage
Description
T1
Controller
local_read_req or local_write_req signal assertion to
ddr_cs_n signal assertion.
T2
Command Output
ddr_cs_n signal assertion to mem_cs_n signal assertion.
T3
CAS or WL
Read command to DQ data from the memory or write command to DQ
data to the memory.
T4
ALTMEMPHY
read data input
Read data appearing on the local interface.
T2 + T3
Write data latency
Write data appearing on the memory interface.
From Figure 8–1, the read latency in the high-performance controllers is made up of
four components:
Read latency = controller latency + command output latency + CAS latency +
PHY read data input latency = T1 + T2 + T3 + T4
Similarly, the write latency in the high-performance controllers is made up of three
components:
Write latency = controller latency + write data latency = T1 + T2 + T3
You can separate the controller and ALTMEMPHY read data input latency into
latency that occurred in the I/O element (IOE) and latency that occurred in the FPGA
fabric.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 8: Latency
8–3
Table 8–2 shows the minimum and maximum supported CAS latency for the DDR
and DDR2 SDRAM high-performance controllers (HPC and HPC II).
Table 8–2. Supported CAS Latency (Note 1)
Minimum Supported
CAS Latency
Device Family
Maximum Supported CAS
Latency
DDR
DDR2
DDR
DDR2
Arria GX
3.0
3.0
3.0
6.0
Arria II GX
3.0
3.0
3.0
6.0
Cyclone III
2.0
3.0
3.0
6.0
Cyclone IV
2.0
3.0
3.0
6.0
HardCopy III
3.0
3.0
3.0
6.0
HardCopy IV
3.0
3.0
3.0
6.0
Stratix II
3.0
3.0
3.0
6.0
Stratix III
3.0
3.0
3.0
6.0
Stratix IV
3.0
3.0
3.0
6.0
Note to Table 8–2:
(1) The registered DIMMs, where supported, effectively introduce one extra cycle of CAS latency. For the registered
DIMMs, you need to subtract 1.0 from the CAS figures to determine the minimum supported CAS latency, and add
1.0 to the CAS figures to determine the maximum supported CAS latency.
Table 8–3 through Table 8–6 show a typical latency that can be achieved in Arria GX,
Arria II GX, Cyclone III, Cyclone IV, Stratix IV, Stratix III, Stratix II, and Stratix II GX
devices. The exact latency for your memory controller depends on your precise
configuration. You can obtain precise latency from simulation, but this figure can vary
slightly in hardware because of the automatic calibration process.
The actual memory CAS and write latencies shown are halved in half-rate designs as
the latency calculation is based on the local clock.
The read latency also depends on your board trace delay. The latency found in
simulation can be different from that found in board testing as functional simulation
does not take into account the board trace delays. For a given design on a given board,
the latency may change by one clock cycle (for full-rate designs) or two clock cycles
(for half-rate designs) upon resetting the board. Different boards could also show
different latencies even with the same design.
The CAS and write latencies are different between DDR and DDR2 SDRAM
interfaces. To calculate latencies for DDR SDRAM interfaces, use the numbers from
DDR2 SDRAM listed below and replace the CAS and write latency with the DDR
SDRAM values.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
8–4
Chapter 8: Latency
Table 8–3. Typical Read Latency in HPC (Note 1), (2)
Address and
Command
Latency
Device
Interface
Controller
Latency
(3)
FPGA
233
Half-rate
5
167
Full-rate
233
Frequency
(MHz)
Arria GX
Arria II GX
Read Data
Latency
I/O
CAS
Latency
(4)
FPGA
3
1
2
4
2
1
Half-rate
5
3
Total Read
Latency (5)
I/O
Local
Clock
Cycles
Time
(ns)
4.5
1
17
154
4
5
1
17
108
1
2.5
5.5
1
18
154
167
Full-rate
4
2
1
4
6
1
18
114
Cyclone III and
Cyclone IV
200
Half-rate
5
3
1
2
4.5
1
17
180
167
Full-rate
4
2
1
4
5
1
17
108
Stratix II and
Stratix II GX
333
Half-rate
5
3
1
2
4.5
1
17
108
267
Half-rate
5
3
1
2
4.5
1
17
135
200
Full-rate
4
2
1
4
5
1
17
90
400
Half-rate
5
3
1
2.5
7.125
1.5
21
100
267
Full-rate
4
2
1.5
4
7
1
20
71
Stratix III and
Stratix IV
Notes to Table 8–3:
(1) These are typical latency values using the assumptions listed in the beginning of the section. Your actual latency may be different than shown.
Perform your own simulation for your actual latency.
(2) Numbers shown may have been rounded up to the nearest higher integer.
(3) The controller latency value is from the Altera high-performance controller.
(4) CAS latency is per memory device specification and is programmable in the MegaWizard Plug-In Manager.
(5) Total read latency is the sum of controller, address and command, CAS, and read data latencies.
Table 8–4. Typical Read Latency in HPC II (Note 1), (2) (Part 1 of 2)
Address and
Command
Latency
Controller
Latency
(3)
FPGA
I/O
1
2
4.5
1
18
154
1
4
5
1
19
114
1
2.5
5.5
1
18
154
2
1
4
6
1
20
120
5
3
1
2
4.5
1
18
180
Full-rate
5
2
1
4
5
1
19
114
333
Half-rate
5
3
1
2
4.5
1
18
108
267
Half-rate
5
3
1
2
4.5
1
18
135
200
Full-rate
5
2
1
4
5
1
19
95
Interface
233
Half-rate
5
3
167
Full-rate
5
2
233
Half-rate
5
3
167
Full-rate
5
Cyclone III and
Cyclone IV
200
Half-rate
167
Stratix II and
Stratix II GX
Arria GX
Arria II GX
Total Read
Latency (5)
CAS
Latency
(4)
Frequency
(MHz)
Device
Read Data
Latency
FPGA
I/O
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Local
Clock
Cycles
Time
(ns)
© February 2010 Altera Corporation
Chapter 8: Latency
8–5
Table 8–4. Typical Read Latency in HPC II (Note 1), (2) (Part 2 of 2)
Address and
Command
Latency
Device
Interface
Controller
Latency
(3)
FPGA
400
Half-rate
5
267
Full-rate
4
Frequency
(MHz)
Stratix III and
Stratix IV
Read Data
Latency
I/O
CAS
Latency
(4)
FPGA
3
1
2.5
2
1.5
4
Total Read
Latency (5)
I/O
Local
Clock
Cycles
Time
(ns)
7.125
1.5
20
100
7
1
20
75
Notes to Table 8–3:
(1) These are typical latency values using the assumptions listed in the beginning of the section. Your actual latency may be different than shown.
Perform your own simulation for your actual latency.
(2) Numbers shown may have been rounded up to the nearest higher integer.
(3) The controller latency value is from the Altera high-performance controller.
(4) CAS latency is per memory device specification and is programmable in the MegaWizard Plug-In Manager.
(5) Total read latency is the sum of controller, address and command, CAS, and read data latencies.
Table 8–5. Typical Write Latency in HPC
(Note 1), (2)
Address and
Command Latency
Total Write
Latency (5)
I/O
Memory
Write
Latency
(4)
Local
Clock
Cycles
Time
(ns)
Frequency
(MHz)
Interface
Controller
Latency
(3)
233
Half-rate
5
3
1
1.5
12
103
167
Full-rate
4
2
1
3
11
66
233
Half-rate
5
3
1
2.5
12
103
167
Full-rate
4
2
1
4
11
66
Cyclone III and
Cyclone IV
200
Half-rate
5
3
1
1.5
12
120
167
Full-rate
4
2
1
3
11
66
Stratix II and
Stratix II GX
333
Half-rate
5
3
1
1.5
12
72
267
Half-rate
5
3
1
1.5
12
90
Device
Arria GX
Arria II GX
Stratix III and
Stratix IV
FPGA
200
Full-rate
4
2
1
3
11
55
400
Half-rate
5
3
1
2
12
60
267
Full-rate
4
2
1.5
3
12
44
Notes to Table 8–5:
(1) These are typical latency values using the assumptions listed in the beginning of the section. Your actual latency may be different than shown.
Perform your own simulation for your actual latency.
(2) Numbers shown may have been rounded up to the nearest higher integer.
(3) The controller latency value is from the Altera high-performance controller.
(4) Memory write latency is per memory device specification. The latency from when you provide the command to write to when you need to
provide data at the memory device.
(5) Total write latency is the sum of controller, address and command, and memory write latencies.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
8–6
Chapter 8: Latency
Table 8–6. Typical Write Latency in HPC II (Note 1), (2)
Address and
Command Latency
Total Write
Latency (5)
I/O
Memory
Write
Latency
(4)
Local
Clock
Cycles
Time
(ns)
Frequency
(MHz)
Interface
Controller
Latency
(3)
233
Half-rate
5
3
1
1.5
12
103
167
Full-rate
5
2
1
3
12
72
233
Half-rate
5
3
1
2.5
12
103
167
Full-rate
5
2
1
4
12
72
Cyclone III and
Cyclone IV
200
Half-rate
5
3
1
1.5
12
120
167
Full-rate
5
2
1
3
12
72
Stratix II and
Stratix II GX
333
Half-rate
5
3
1
1.5
12
72
267
Half-rate
5
3
1
1.5
12
90
200
Full-rate
5
2
1
3
12
60
400
Half-rate
5
3
1
2
12
60
267
Full-rate
5
2
1.5
3
13
49
Device
Arria GX
Arria II GX
Stratix III and
Stratix IV
FPGA
Notes to Table 8–5:
(1) These are typical latency values using the assumptions listed in the beginning of the section. Your actual latency may be different than shown.
Perform your own simulation for your actual latency.
(2) Numbers shown may have been rounded up to the nearest higher integer.
(3) The controller latency value is from the Altera high-performance controller.
(4) Memory write latency is per memory device specification. The latency from when you provide the command to write to when you need to
provide data at the memory device.
(5) Total write latency is the sum of controller, address and command, and memory write latencies.
f
To see the latency incurred in the IOE for both read and write paths for ALTMEMPHY
variations in Stratix IV and Stratix III devices refer to the IOE figures in the External
Memory Interfaces in Stratix III Devices chapter of the Stratix III Device Handbook and the
External Memory Interfaces in Stratix IV Devices chapter of the Stratix IV Device
Handbook.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
9. Timing Diagrams
This chapter details the timing diagrams for the DDR and DDR2 SDRAM
high-performance controllers (HPC) and high-performance controllers II (HPC II).
DDR and DDR2 High-Performance Controllers
This section discusses the following timing diagrams for HPC in AFI mode:
© February 2010
■
“Auto-Precharge”
■
“User Refresh”
■
“Full-Rate Read”
■
“Half-Rate Read”
■
“Full-Rate Write”
■
“Half Rate Write”
■
“Initialization Timing”
■
“Calibration Timing”
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–2
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
Auto-Precharge
The auto-precharge read and auto-precharge write commands allow you to indicate
to the memory device that this read or write command is the last access to the
currently open row. The memory device automatically closes (auto-precharges) the
page it is currently accessing so that the next access to the same bank is quicker. This
command is particularly useful for applications that require fast random accesses.
Figure 9–1. Auto-Precharge Operation for HPC
[1] [2]
[3]
phy_clk
Local Interface
local_autopch_req
local_ready
local_write_req
local_read_req
local_row_addr[13:0]
0003
0002
local_col_addr[9:0]
004
008
00C
010
000
004
008
00C
010
000
local_bank_addr[2:0]
mem_local_addr[24:0]
0C00200
0C00100
AFI Memory Interface
Memory Command[2:0]
NOP
WR
mem_addr[13:0]
0003
0000
NOP
0004 0008 000C 0410
WR
NOP
0000
WR
0004 0008 000C
NOP
0410
mem_clk
mem_clk_n
mem_cs_n
mem_dq[7:0]
00
00
mem_dqs
mem_dqsn
Notes to Figure 9–1:
(1) The auto-precharge request goes high.
(2) The local_ready signal is asserted and remains high until the auto-precharge request goes low.
(3) A new row address begins.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–3
User Refresh
Figure 9–2 shows the user refresh control interface. This feature allows you to control
when the controller issues refreshes to the memory. This feature allows better control
of worst case latency and allows refreshes to be issued in bursts to take advantage of
idle periods.
Figure 9–2. User-Refresh Operation for HPC
[1]
[2]
global_reset_n
phy_clk
Local Interface
mem_local_refresh_req
local_init_done
local_refresh_ack
local_refresh_req
local_refresh_ack
local_ready
Controller - AFI
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ddr_cke_h
ddr_cke_l
ddr_ras_n
ddr_cas_n
ddr_we_n
AFI Memory Interface
NOP
Mem Command[2:0]
ARF
NOP
[3]
Notes to Figure 9–2:
(1) The local refresh request signal is asserted.
(2) The controller asserts the local_refresh_ack signal.
(3) The auto-refresh (ARF) command on the command bus.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–4
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Full-Rate Read
Figure 9–3. Full-Rate Read Operation for HPC Using Native and Avalon-MM Interfaces
[8]
[1] [2] [3]
phy_clk
Local Interface
local_read_req
local_write_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[25:0]
local_size[1:0]
local_burst_begin
local_rdata[15:0]
local_rdata_valid
0001
0002
000
004
010
000
0000200
0000202
0000208
0000400
004
0
0B01
1602
0000402
2C04
5808
B010
7D20
FA40
E980
CF1D
local_read_req
local_ready
Controller - AFI
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ctl_addr[13:0]
ctl_ba[2:0]
ctl_cke
ctl_cs_n
ctl_odt
ctl_rdata[15:0]
ctl_rdata_valid
ctl_doing_rd
ctl_dqs_burst
ctl_rlat[4:0]
DDR Command[2:0]
7
0
7
0
0000
0004
0000 0010
0000
0001
0000
0004
0000
0000
0004
0000 0010
0000
0001
0000
0004
0000
0B01
WR
NOP
NOP
BT
RD
NOP
NOP
RD
NOP
RD
RD
00
0000
[4]
NOP
NOP
ACT
NOP
RD
NOP
PCH
NOP
01 0B 02 16 04 2C 08 58 10 B0 20 7D 40 FA 80 E9 1D CF 3A 83
000C
[5]
PCH
2C04
0000
0010
0000
[6]
5808
B010
NOP
BT
7D20
FA40
E980
CF1D
RD
NOP
RD
NOP
NOP
0001
RD
0000
[7]
NOP
00
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
© February 2010 Altera Corporation
AFI Memory Interface
Mem Command[2:0]
NOP
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_addr[13:0]
0000
mem_ba[2:0]
0
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
1602
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–5
The following sequence corresponds with the numbered items in Figure 9–3:
1. The local read request signal is asserted.
2. The controller accepts the request, the local_ready signal is asserted.
3. The controller asserts the ctl_doing_rd to tell the PHY how many clock cycles
of read data to expect.
4. The read command (RD) on the bus.
5. The mem_dqs signal has the read data.
6. These are the data to the controller with the valid signal.
7. The controller returns the valid read data to the user logic by asserting the
local_rdata_valid signal when there is valid local read data.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–6
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Half-Rate Read
Figure 9–4. Half-Rate Read Operation for HPC Using Native and Avalon-MM Interfaces
[3]
[1] [2]
[7]
phy_clk
Local Interface
local_read_req
local_write_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[24:0]
local_size
local_rdata[31:0]
burst_begin
local_rdata_valid
0000
000
000
0000000
0000100
0000101
0002
008
00C
000
0000102
0004
0008
0010004
0020008
000C
[4]
0000
0001
0000
0000000
0004001
0000000
1
3
1
3
00C
0000203
0000204
3E2A1602
7C542C04
0008
000C
0010
0000
0010004 0020008
003000C
0040010
0000000
1F150B01
3E2A1602
0004
3
0C
3F
0C
NOP
PCH
NOP
[5]
0010
0000
[6]
3
7C542C04
3
NOP
1
F8A85808 ED4DB010
RD
01 0B 15 1F 02 16 2A 3E 04 2C 54 7C 08 58 A8 F8 10 B0 4DED
000C
F8A85808 ED4DB010
1
0
RD
010
1F150B01
3
NOP
0000
008
0
0000201 0000202
0000200
1
00
004
00
0000
0004
20 7D 9A C7
0008
000C
[8]
0010
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
© February 2010 Altera Corporation
local_read_req
local_ready
Controller - AFI Interface
ddr_a[13:0]
0000
0000
0000
ddr_ba[2:0]
0
0
7
ddr_cs_n
ctl_addr[27:0]
0000000
0000000
0000000
ctl_ba[5:0]
00
00
3F
ctl_cke[1:0]
ctl_cs_n[1:0]
3
3
1
3
ctl_odt[1:0]
0
ctl_rdata[31:0]
ctl_rdata_valid[1:0]
ctl_doing_rd[1:0]
3
ctl_dqs_burst[1:0]
2
0
ctl_rlat[4:0]
DDR Command [1:0]
3F
0C
3F
AFI Memory Interface
7
Mem Command[2:0]
NOP
ACT
ACT
mem_ras_n
mem_cas_n
mem_we_n
mem_dq[7:0]
55 6D 25 1D AA DA 4A 3A 49 A9
00
mem_dqs
mem_dqsn
mem_addr[13:0]
000C
0010
0000
0003
mem_ba[2:0]
0
0
7
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
0001
004
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–7
The following sequence corresponds with the numbered items in Figure 9–4:
1. The local read request signal is asserted.
2. The controller accepts the request, the local_ready signal is asserted.
3. The controller asserts the ctl_doing_rd to tell the PHY how many clock cycles
of read data to expect.
4. The read command (RD) on the bus.
5. The mem_dqs signal has the read data.
6. These are the data to the controller with the valid signal.
7. The controller returns the valid read data to the user logic by asserting the
local_rdata_valid signal when there is valid local read data.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–8
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
Full-Rate Write
Figure 9–5. Full-Rate Write Operation for HPC Using Native and Avalon-MM Interfaces
[1]
[4]
[2]
phy_clk
Local Interface
local_read_req
local_write_req
0000 0001
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
0002
0010
0020
000
004
008
040
080
0
1
2
5
0800202 1000404
mem_local_addr[25:0]
6
2802020
3004040
local_size[1:0]
1
local_be[1:0]
local_wdata[15:0]
F6AE
F141 FF82 E319
620E
C41C
9538
local_write_req
local_ready
Controller - AFI
ddr_a[13:0]
ddr_ba[2:0]
0000
0
1
0
1
0
2
NOP
ddr_cs_n
ctl_addr[13:0]
ctl_ba[2:0]
0000
0
ctl_cke
ctl_cs_n
ctl_odt
F6AE F141
ctl_wdata[15:0]
ctl_wdata_valid
ctl_wlat[4:0]
control_dm[1:0]
ctl_dqs_burst
control_be[1:0]
2
DDR Command[2:0]
1
NOP
AFI Memory Interface
NOP
Mem Command[2:0]
WR
2
NOP
00
mem_dq[7:0]
AE F6 41 F1
mem_dqs
mem_dqsn
0000
mem_addr[13:0]
mem_ba[2:0]
1
0
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
mem_dm
[3]
[5]
[6]
The following sequence corresponds with the numbered items in Figure 9–5:
1. The local write request signal is asserted.
2. The local_ready signal is high at the time of the write request.
3. The date is written to the memory for this write command.
4. The write command (WR) on the command bus.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–9
5. The valid write data on the ctl_wdata signal. The ctl_wdata_valid is 1.
6. Data on the mem_dqs signal goes to the controller.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–10
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Half Rate Write
Figure 9–6. Half-Rate Write Operation for HPC Using Native and Avalon-MM Interfaces
[1]
phy_clk
Local Interface
local_write_req
local_read_req
local_row_addr[13:0]
local_col_addr[9:0]
local_bank_addr[2:0]
mem_local_addr[24:0]
local_size
local_be[3:0]
local_wdata[31:0]
local_wdata_req
local_write_req
local_ready
Controller - AFI
ddr_a[13:0]
ddr_ba[2:0]
ddr_cs_n
ctl_addr[27:0]
ctl_ba[5:0]
ctl_cke[1:0]
ctl_cs_n[1:0]
ctl_odt[1:0]
ctl_wdata[31:0]
ctl_wdata_valid[1:0]
ctl_wlat[4:0]
control_dm[3:0]
ctl_dqs_burst[1:0] 2
control_be[3:0]
Control command [1:0]
3
[3]
[2]
0000
000
0
0000000
6
1BFFFFF
0001
004
1
0400101
0010
040
5
1401010
1
2D9F54E6
0000
0020
080
6
1802020
2
C90A5291
0
3BFF
1
0000
0
03EC
1
0000
0
0
09
00
EFFFBFF
09
0000000
00
0FB03EC
09
0000000
00
00
3
1
3
1
1
1
0
0
09
00
00
1
3
0000000
3
3
0
0
0
2D9F54E6
0
3
3
0
3
3
461EF6AE
0
E
3
0
2
3
2
2
3
D
2
0
0
1
0
NOP
3
0
PCH
3
NOP
00
ACT
NOP
WR
NOP
00
0000
1
0
NOP
NOP
00
3BFF
1
0000
0
03EC
1
0000
0
0
WR
2
2
3
E654 9F 2D
0000
0
3
3
3
NOP
00
WR
00
NOP
AEF6 1E 46
0
[6]
6]
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
© February 2010 Altera Corporation
AFI Memory Interface
Memory command[2:0]
WR
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_addr[13:0] 03F4
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_odt
mem_dm
2
28E7AB64
0000
3
0
0
461EF6AE
0000000
3
3
0010
040
5
1401010
0000
3
0
0000
000
0
1
0000000
4
8F14A43F
1
0000000
3
[5]
[5
[4]
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–11
The following sequence corresponds with the numbered items in Figure 9–6:
1. The user logic requests write by asserting the local_write_req signal.
2. The local_ready signal is asserted, indicating that the controller has accepted
the request.
3. The data written to the memory for the write command.
4. The controller requests the user logic for the write data and byte-enables for the
write by asserting the local_wdata_req signal, (only for native interface).
5. The valid write data on the ctl_wdata signal.
6. The valid data on the mem_dq signal goes to the controller.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–12
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Initialization Timing
Figure 9–7. Initialization Timing for HPC
[3]
command[2:0]
global_reset_n
phy_clk
NOP
local_rdata[31:0]
local_rdata_valid
local_ready
mem_local_addr[24:0]
mem_local_col_addr[9:0]
local_col_addr[9:0]
mem_local_write_req
local_write_req
mem_local_wdata[31:0]
local_wdata[31:0]
mem_local_size
local_size
mem_local_be[3:0]
local_be[3:0]
ARF
[5]
LMR
ARF
WR
ARF
WRF
ARF
RD
FFFF0000
00000000
0000000
000
000
1F150B01
1F150B01
mem_command[2:0]
mem_addr[13:0]
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_dm
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_odt
NOP
0000
ARF
LMR
0400
0
ARF
0A62
0044
0
00
ARF
002C
00
FF
0400
WRF
0028
001C
ARF
0014
RD
0400
0014
00
00
1
00
00
FF
0
pnf
pnf_per_byte[3:0]
test_complete
[1]
[2]
[4]
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
© February 2010 Altera Corporation
pll_locked
pll_ref_clk
seq_pll_select[3:0]
seq_pll_start_reconfig
seq_pll_inc_dec_n
phs_shft_busy
pll_measure_clk_index[3:0]
ctl_cal_fail
ctl_cal_req
ctl_cal_success
local_init_done
ctl_cal_byte_lane_sel_n
WR
0018
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–13
The following sequence corresponds with the numbered items in Figure 9–7:
1. The pll_locked signal goes high.
2. The mem_cke signal is asserted.
3. The first sequence of the initialization commands: PCH, LMR, PCH, ARF, LMR.
4. Write training data.
5. The first read command to read back training pattern.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–14
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Calibration Timing
Figure 9–8. Calibration Timing for HPC
[6]
command[2:0]
local_rdata[31:0]
local_rdata_valid
local_ready
mem_local_addr[24:0]
mem_local_col_addr[9:0]
local_col_addr[9:0]
mem_local_write_req
local_write_req
mem_local_wdata[31:0]
local_wdata[31:0]
mem_local_size
local_size
mem_local_be[3:0]
local_be[3:0]
mem_command[2:0]
mem_addr[13:0]
mem_ba[2:0]
mem_cke
mem_clk
mem_clk_n
mem_cs_n
mem_dm
mem_dq[7:0]
mem_dqs
mem_dqsn
mem_odt
RD
PCH
ARF
[8]
RD
PCH
RD
[9]
PCH
FFFFFFFF
ARF
RD
00FF00FF
[11]
[13]
LMR
PCH
1
NOP NOP
00FF00FF
0000100
000
000 000 000
000
000 000 000
C79A7D20
C79A7D20
RD
PCH
ARF
0400
RD
PCH
0400
RD
PCH
ARF
RD
0400
PCH
LMR
NOP
0A62 0000
0400
23 1
00
00
00
pll_locked
pll_ref_clk
seq_pll_select[3:0]
00
NOP
0
00
00
00
00
5
© February 2010 Altera Corporation
[7]
[9]
[10]
[12]
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
seq_pll_start_reconfig
seq_pll_inc_dec_n
phs_shft_busy
pll_measure_clk_index[3:0]
ctl_cal_fail
ctl_cal_req
ctl_cal_success
local_init_done
ctl_cal_byte_lane_sel_n
pnf
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers
9–15
The following sequence corresponds with the numbered items in Figure 9–8:
1. The first read calibration at zero degrees.
2. The PPL phase.
3. The second read calibration after the PLL phase.
4. The final read calibration and final PLL phase.
5. The burst of the PLL phase to center the clock.
6. The second initialization sequence (LMR) to load the settings.
7. The ctl_cal_success signal goes high.
8. The functional memory stage.
© February 2010
Altera Corporation
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
9–16
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
DDR and DDR2 High-Performance Controllers II
This section discusses the following timing diagrams for HPC II:
■
“Half-Rate Read”
■
“Half-Rate Write”
■
“Full-Rate Read”
■
“Full-Rate Write”
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Figure 9–9. Half-Rate Read Operation for HPC II
[1]
[2]
[3]
[4]
[7]
Altera Corporation
phy_clk
Local Interface
local_address[25:0]
0000000
local_size[4:0]
local_ready
local_burstbegin
local_read_req
local_rdata[31:0]
local_rdata_valid
local_be[3:0]
0000002 0000004
0000000
2
AABBCCDD EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
© February 2010
Half-Rate Read
Controller - AFI
0000000 0000000 0000008 0000000 0000010
0
B
RD
F
NOP
B
RD
F
0000000
F
B
RD
NOP
F
3
AABBCCDD EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011
3
AFI Memory Interface
mem_cke[1:0]
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
0000
NOP
RD
0000
NOP
0008
RD
0
0000
NOP
0010
RD
NOP
DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE
[5]
[6]
9–17
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
afi_addr[27:0]
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_doing_rd[1:0]
afi_rdata[31:0]
afi_rdata_valid[1:0]
9–18
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
The following sequence corresponds with the numbered items in Figure 9–9:
1. The user logic requests the first read by asserting the local_read_req signal,
and the size and address for this read. In this example, the request is a burst of
length of 2 to the local address 0×000000. This local address is mapped to the
following memory address in half-rate mode:
mem_row_address = 0×000000
mem_col_address = 0×0000
mem_bank_address = 0×00
2. The user logic initiates a second read to a different memory column within the
same row. The request for the second write is a burst length of 2. In this example,
the user logic continues to accept commands until the command queue is full.
When the command queue is full, the controller deasserts the local_ready
signal. The starting local address 0x000002 is mapped to the following memory
address in half-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×0002<<2 = 0×0008
mem_bank_address = 0×00
3. The controller issues the first read memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
4. The controller asserts the afi_doing_rd signal to indicate to the ALTMEMPHY
megafunction the number of clock cycles of read data it must expect for the first
read. The ALTMEMPHY megafunction uses the afi_doing_rd signal to enable
its capture registers for the expected duration of memory burst.
5. The ALTMEMPHY megafunction issues the first read command to the memory
and captures the read data from the memory.
6. The ALTMEMPHY megafunction returns the first data read to the controller after
resynchronizing the data to the phy_clk domain, by asserting the
afi_rdata_valid signal when there is valid read data on the afi_rdata bus.
7. The controller returns the first read data to the user by asserting the
local_rdata_valid signal when there is valid read data on the local_rdata
bus. If the ECC logic is disabled, there is no delay between the afi_rdata and the
local_rdata buses. If there is ECC logic in the controller, there is one or three
clock cycles of delay between the afi_rdata and local_rdata buses.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Figure 9–10. Half-Rate Write Operation for HPC II
[1]
[2]
[3]
[4]
[5]
[6]
Altera Corporation
phy_clk
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_be[3:0]
local_write_req
local_wdata[31:0]
0000000
0000002
2
0000004
0000000
AABBCCDD EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
© February 2010
Half-Rate Write
Controller - AFI
AFI Memory Interface
mem_cke[1:0]
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
0000000
B
ACT
F
NOP
0000000
B
WR
F
2
0000000 0000000 0000008 0000000 0000010
F
NOP
B
WR
0
F
NOP
F
3
0
B
WR
F
NOP
B
WR
0000000
F
NOP
0
F
AABBCCDD EEFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011
0000
NOP
ACT
NOP
WR
3
0000
NOP
00
0000
0000
0008
0000
0010
WR
NOP
WR
NOP
WR
00
NOP
DD CC BB AA11 00 FF EE DD CC BB AA11 00 FF EE DD CC BB AA11 00 FF EE
9–19
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
afi_addr[27:0]
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_wdata[31:0]
afi_wdata_valid[1:0]
9–20
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
The following sequence corresponds with the numbered items in Figure 9–10:
1. The user logic asserts the first write request to row 0 so that row 0 is open before
the next transaction.
2. The user logic asserts a second local_write_req signal with size of 2 and
address of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is
asserted along with the local_write_req signal, which indicates that the
controller has accepted this request, and the user logic can request another read or
write in the following clock cycle. If the local_ready signal was not asserted, the
user logic must keep the write request, size, and address signals asserted until the
local_ready signal is registered high.
3. The controller issues the necessary memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
4. The controller asserts the afi_wdata_valid signal to indicate to the
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
5. The controller asserts the afi_dqs_burst signals to control the timing of the
DQS signal that the ALTMEMPHY megafunction issues to the memory.
6. The ALTMEMPHY megafunction issues the write command, and sends the write
data and write DQS to the memory.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Figure 9–11. Full-Rate Read Operation for HPC II
[1]
[2]
[3]
[6]
Altera Corporation
phy_clk
Local Interface
local_address[23:0]
000000 000002
local_size[2:0]
local_ready
local_burstbegin
local_read_req
local_rdata_valid
local_rdata[15:0]
local_be[1:0]
AFI Memory Interface
mem_cke
mem_clk
mem_ba[1:0]
mem_addr[12:0]
mem_cs_n
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt
2
FFFF
ABCD
EF01
ABCD
EF01
ABCD
EF01
ABCD
EF01
3
000000
NOP
RD
000004
NOP
0000
0
RD
NOP
3
FFFF
0000
NOP
RD
0
0000
0004
NOP
00
RD
NOP
CD AB 01 EF CD AB 01 EF
[4]
00
[5]
9–21
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Controller - AFI
afi_addr[12:0]
afi_ba[1:0]
afi_cs_n
AFI Command[2:0]
afi_dm[1:0]
afi_dqs_burst
afi_doing_rd
afi_rdata[15:0]
afi_rdata_valid
000000
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
© February 2010
Full-Rate Read
9–22
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
The following sequence corresponds with the numbered items in Figure 9–11:
1. The user logic requests the first read by asserting local_read_req signal, and
the size and address for this read. In this example, the request is a burst length of 2
to a local address 0x000000. This local address is mapped to the following
memory address in full-rate mode:
mem_row_address = 0×0000
mem_col_address = 0×0000<<2 = 0×0000
mem_bank_address = 0×00
2. The controller issues the first read memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
3. The controller asserts the afi_doing_rd signal to indicate to the ALTMEMPHY
megafunction the number of clock cycles of read data it must expect for the first
read. The ALTMEMPHY megafunction uses the afi_doing_rd signal to enable
its capture registers for the expected duration of memory burst.
4. The ALTMEMPHY megafunction issues the first read command to the memory
and captures the read data from the memory.
5. The ALTMEMPHY megafunction returns the first data read to the controller after
resynchronizing the data to the phy_clk domain, by asserting the
afi_rdata_valid signal when there is valid read data on the afi_rdata bus.
6. The controller returns the first read data to the user by asserting the
local_rdata_valid signal when there is valid read data on the local_rdata
bus. If the ECC logic is disabled, there is no delay between the afi_rdata and the
local_rdata buses. If there is ECC logic in the controller, there is one or three
clock cycles of delay between the afi_rdata and local_rdata buses.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Altera Corporation
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
© February 2010
Full-Rate Write
Figure 9–12. Full-Rate Write Operation for HPC II
[1]
[2]
[3]
[5]
phy_clk
Local Interface
local_address[23:0]
local_size[2:0]
local_ready
local_burstbegin
local_be[1:0]
local_write_req
local_rdata[15:0]
local_wdata[15:0]
AFI Memory Interface
mem_cke
mem_clk
mem_ba[1:0]
mem_addr[12:0]
mem_cs_n
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt
000004
000008
000000
2
3
0000
ABCD
EF01
ABCD
EF01
FFFF
ABCD
EF01
0000
0008
0000
0000
0010
0000
0
NOP
ACT
NOP
WR
NOP
WR
NOP
WR
NOP
3
0
3
WR
NOP
0
3
04
0000
ABCD
EF01
ABCD
EF01
ABCD
EF01
0
0000
NOP
ACT
0008
NOP
WR
NOP
WR
NOP
00
WR
0000
NOP
0010
WR
CD AB
[6]
0000
NOP
01
EF CD AB
01
EF CD AB
01
EF
[4]
9–23
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
Controller - AFI
afi_addr[12:0]
afi_ba[1:0][1:0]
afi_cs_n
AFI Command[2:0]
afi_dm[1:0]
afi_wlat[4:0]
afi_dqs_burst
afi_wdata[15:0]
afi_wdata_valid
000000
9–24
Chapter 9: Timing Diagrams
DDR and DDR2 High-Performance Controllers II
The following sequence corresponds with the numbered items in Figure 9–12:
1. The user logic asserts the first write request to row 0 so that row 0 is open before
the next transaction.
2. The user logic asserts a second local_write_req signal with a size of 2 and
address of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is
asserted along with the local_write_req signal, which indicates that the
controller has accepted this request, and the user logic can request another read or
write in the following clock cycle. If the local_ready signal was not asserted, the
user logic must keep the write request, size, and address signals asserted until the
local_ready signal is registered high.
3. The controller issues the necessary memory command and address signals to the
ALTMEMPHY megafunction for it to send to the memory device.
4. The controller asserts the afi_wdata_valid signal to indicate to the
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
5. The controller asserts the afi_dqs_burst signals to control the timing of the
DQS signal that the ALTMEMPHY megafunction issues to the memory.
6. The ALTMEMPHY megafunction issues the write command, and sends the write
data and write DQS to the memory.
DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Section II. DDR3 SDRAM High-Performance Controller
and ALTMEMPHY IP User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
EMI_DDR3_UG-1.3
Document Version:
Document Date:
1.3
February 2010
Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
About This Section
Revision History
The following table shows the revision history for this section.
Date
Version
Changes Made
February 2010
1.3
Corrected typos.
February 2010
1.2
■
Full support for Stratix IV devices.
■
Added information for Register Control Word parameters.
■
Added descriptions for mem_ac_parity, mem_err_out_n, and
parity_error_n signals.
■
Added timing diagrams for initialization and calibration stages for HPC.
November 2009
1.1
Minor corrections.
November 2009
1.0
First published.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
iv
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
About This Section
Revision History
© February 2010 Altera Corporation
1. About This IP
The Altera® DDR3 SDRAM High-Performance Controller MegaCore® function
provides simplified interfaces to industry-standard DDR3 SDRAM. The
ALTMEMPHY megafunction is an interface between a memory controller and the
memory devices, and performs read and write operations to the memory. The
MegaCore function works in conjunction with the Altera ALTMEMPHY
megafunction.
The DDR3 SDRAM High-Performance Controller MegaCore function and
ALTMEMPHY megafunction offer half-rate DDR3 SDRAM interfaces. The DDR3
SDRAM High-Performance Controller MegaCore function offers two controller
architectures: the high-performance controller (HPC) and the high-performance
controller II (HPC II). HPC II provides higher efficiency and more advanced features.
1
DDR3 SDRAM high-performance controller denotes both HPC and HPC II unless
indicated otherwise.
Figure 1–1 on page 1–1 shows a system-level diagram including the example top-level
file that the DDR3 SDRAM High-Performance Controller MegaCore function creates
for you.
Figure 1–1. System-Level Diagram
Example Top-Level File
ALTMEMPHY
External
Memory
Device
DLL
PLL
(1)
HighPerformance
Controller
Example
Driver
Pass or Fail
Note to Figure 1–1:
(1) When you choose Instantiate DLL Externally, delay-locked loop (DLL) is instantiated outside the ALTMEMPHY
megafunction.
The MegaWizard™ Plug-In Manager generates an example top-level file, consisting of
an example driver, and your DDR3 SDRAM high-performance controller custom
variation. The controller instantiates an instance of the ALTMEMPHY megafunction
which in turn instantiates a phase-locked loop (PLL) and DLL. You can optionally
instantiate the DLL outside the ALTMEMPHY megafunction to share the DLL
between multiple instances of the ALTMEMPHY megafunction. You cannot share a
PLL between multiple instances of the ALTMEMPHY megafunction, but you may
share some of the PLL clock outputs between these multiple instances.
The example top-level file is a fully-functional design that you can simulate,
synthesize, and use in hardware. The example driver is a self-test module that issues
read and write commands to the controller and checks the read data to produce the
pass or fail, and test complete signals.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
1–2
Chapter 1: About This IP
Release Information
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller. The megafunction is available as a stand-alone product or
can be used in conjunction with Altera high-performance memory controllers. As a
stand-alone product, use the ALTMEMPHY megafunction with either custom or
third-party controllers.
Release Information
Table 1–1 provides information about this release of the DDR3 SDRAM
High-Performance Controllers and ALTMEMPHY intellectual property (IP).
Table 1–1. Release Information
Item
Version
Release Date
Ordering Codes
Description
9.1 SP1
February 2010
IP-SDRAM/DDR3 (HPC)
IP-HPMCII (HPC II)
Product IDs
00C2 (DDR3 SDRAM)
00CO (ALTMEMPHY Megafunction)
Vendor ID
6AF7
Altera verifies that the current version of the Quartus® II software compiles the
previous version of each MegaCore function. The MegaCore IP Library Release Notes
and Errata report any exceptions to this verification. Altera does not verify
compilation with MegaCore function versions older than one release. For information
about issues on the ALTMEMPHY megafunction in a particular Quartus II version,
refer to the Quartus II Software Release Notes.
Device Family Support
The MegaCore functions provide either full or preliminary support for target Altera
device families:
■
Full support means the megafunction meets all functional and timing
requirements for the device family and can be used in production designs.
■
Preliminary support means the megafunction meets all functional requirements,
but can still be undergoing timing analysis for the device family.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Features
1–3
Table 1–2 shows the level of support offered by the DDR3 SDRAM high-performance
controllers to each of the Altera device families.
Table 1–2. Device Family Support
Device Family
Support
Arria II GX
Preliminary
HardCopy III
Preliminary
HardCopy IV E
Preliminary
HardCopy IV GX
Preliminary
Stratix III
Full
Stratix IV
Full
Other device families
No support
Features
The ALTMEMPHY megafunction offers the following features:
■
Simple setup
■
Support for the Altera PHY Interface (AFI) for DDR3 SDRAM on all supported
devices.
■
Automated initial calibration eliminating complicated read data timing
calculations
■
VT tracking that guarantees maximum stable performance for DDR3 SDRAM
interface
■
Self-contained datapath that makes connection to an Altera controller or a
third-party controller independent of the critical timing paths
■
Easy-to-use MegaWizard interface
The ALTMEMPHY megafunction supports DDR3 SDRAM DIMMs with leveling and
DDR3 SDRAM components without leveling:
■
■
ALTMEMPHY with leveling is for unbuffered DIMMs (including SODIMM and
MicroDIMM) or DDR3 SDRAM components up to 80-bit total data bus width with
a layout like a DIMM that target Stratix III and Stratix IV devices:
■
Supports a fully-calibrated DDR3 SDRAM PHY for DDR3 SDRAM unbuffered
DIMM with ×4 and ×8 devices with 300-MHz to 533-MHz frequency targets.
■
Deskew circuitry is enabled automatically for interfaces higher than 400 MHz
■
Supports single and multiple chip selects
ALTMEMPHY supports DDR3 SDRAM components without leveling for
Arria II GX, Stratix III, and Stratix IV devices using T-topology for clock, address,
and command bus:
■
■
© February 2010
Supports multiple chip selects
The DDR3 SDRAM PHY with leveling fMAX is 533 MHz; without leveling fMAX is
400 MHz for single chip selects.
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
1–4
Chapter 1: About This IP
Features
■
No support for data-mask (DM) pins for ×4 DDR3 SDRAM DIMMs or
components, so select No for Drive DM pins from FPGA when using ×4 devices
■
The ALTMEMPHY megafunction supports half-rate DDR3 SDRAM interfaces
only.
Table 1–3 shows the features provided by the DDR3 SDRAM HPC and HPC II.
Table 1–3. DDR3 SDRAM HPC and HPC II Features
Controller Architecture
Features
HPC
HPC II
Half-rate controller
v
v
Support for AFI ALTMEMPHY
v
v
Support for Avalon®Memory Mapped (MM) local interface
v
v
Support for Native local interface
v
—
Configurable command look-ahead bank management with in-order reads and
writes
—
v
Additive latency
—
v(1)
Optional support for multi-cast write for tRC mitigation
—
v
Support for arbitrary Avalon burst length
—
v
Built-in flexible memory burst adapter
—
v
Configurable Local-to-Memory address mappings
—
v
Integrated half-rate bridge for low latency option
—
v
Optional run-time configuration of size and mode register settings, and memory
timing
—
v
Partial array self refresh (PASR)
—
v
Support for industry-standard DDR3 SDRAM devices; and DIMMs
v
v
Optional support for self-refresh command
v
v
Optional support for user-controlled power-down command
v
—
Optional support for automatic power-down command with programmable
time-out
—
v
Optional support for auto-precharge read and auto-precharge write commands
v
v
Optional support for user-controller refresh
v
v
Optional multiple controller clock sharing in SOPC Builder Flow
v
v
Integrated error correction coding (ECC) function 72-bit
v
v
Integrated ECC function 40-bit
—
v
Support for partial-word write with optional automatic error correction
—
v
SOPC Builder ready
v
v
Support for OpenCore Plus evaluation
v
—
Support for the Quartus II IP Advisor
v
—
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulator
v
v
Notes to Table 1–3:
(1) HPC II supports additive latency values greater or equal to tRCD –1, in clock cycle unit (tCK).
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Unsupported Features
1–5
Unsupported Features
The DDR3 SDRAM high-performance controllers do not support the following
features:
■
Timing simulation
■
Partial burst and unaligned burst in ECC and non-ECC mode when DM pins are
disabled.
MegaCore Verification
MegaCore verification includes simulation testing. Altera performs extensive
random, directed tests with functional test coverage using industry-standard Denali
models to ensure the functionality of the DDR3 SDRAM high-performance
controllers.
Resource Utilization
The following sections show the resource utilization data for the ALTMEMPHY
megafunction, and the high-performance controllers.
ALTMEMPHY Megafunction
Table 1–4 and Table 1–5 show the typical size of the ALTMEMPHY megafunction with
the AFI in the Quartus II software version 9.1 for the following devices:
■
Arria II GX (EP2AGX260FF35C4) devices
■
Stratix III (EP3SL110F1152C2) devices
■
Stratix IV (EP4SGX230HF35C2) devices
Table 1–4. Resource Utilization in Arria II GX Devices
Memory Type
DDR3 SDRAM (without
leveling)
PHY
Rate
Half
Memory
Width
(Bits)
(Note 1)
Combinational
ALUTS
Logic Registers
M9K
Blocks
Memory
ALUTs
8
1,431
1,189
2
18
16
1,481
1,264
4
2
64
1,797
1,970
12
22
72
1,874
2,038
13
2
Note to Table 1–4:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory controller overhead is
additional.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
1–6
Chapter 1: About This IP
Resource Utilization
Table 1–5. Resource Utilization in Stratix III and Stratix IV Devices
Memory Type
DDR3 SDRAM
(400 MHz, without leveling
only)
(Note 1)
PHY
Rate
Memory
Width
(Bits)
Combinational
ALUTS
Logic Registers
M9K
Blocks
Memory
ALUTs
Half
8
1,359
1,047
1
40
16
1,426
1,196
1
80
64
1,783
2,080
1
320
72
1,871
2,228
1
360
8
3,724
2,723
2
80
16
4,192
3,235
2
160
64
6,835
6,487
5
640
72
7,182
6,984
5
720
8
4,098
2,867
2
80
16
4,614
3,391
2
160
64
7,297
6,645
5
640
72
7,641
7,144
5
720
DDR3 SDRAM
(400 MHz, with leveling only)
DDR3 SDRAM
(533 MHz with read and write
deskew, with leveling only)
Note to Table 1–5:
(1) The listed resource utilization refers to resources used by the ALTMEMPHY megafunction with AFI only. Memory controller overhead is
additional.
High-Performance Controller (HPC)
Table 1–6 and Table 1–7 show the typical sizes for the DDR3 SDRAM HPC (including
ALTMEMPHY) for Stratix III and Stratix IV devices.
Table 1–6. Resource Utilization in Stratix III Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32
8
1,891
1,558
2
64
16
1,966
1,707
3
256
64
2,349
2,591
9
288
72
2,442
2,739
10
Table 1–7. Resource Utilization in Stratix IV Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32
8
1,924
1,580
2
64
16
1,987
1,724
3
256
64
2,359
2,584
9
288
72
2,449
2,728
10
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
System Requirements
1–7
High-Performance Controller II (HPC II)
Table 1–9 through Table 1–10 show the typical sizes for the DDR3 SDRAM HPC II
(including ALTMEMPHY) for Arria II GX, Stratix III, and Stratix IV devices.
Table 1–8. Resource Utilization in Arria II GX Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32
8
3,258
2,150
3
64
16
3,354
2,304
5
256
64
3,842
3,224
17
288
72
3,949
3,378
18
Table 1–9. Resource Utilization in Stratix III Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32
8
3,106
1,984
2
64
16
3,178
2,133
3
256
64
3,564
3,017
9
288
72
3,660
3,165
10
Table 1–10. Resource Utilization in Stratix IV Devices
Local Data Width
(Bits)
Memory Width
(Bits)
Combinational
ALUTs
Dedicated Logic
Registers
Memory
(M9K)
32
8
3,160
2,008
2
64
16
3,204
2,153
3
256
64
3,013
3,013
9
288
72
3,694
3,157
10
System Requirements
The DDR3 SDRAM High-Performance Controller MegaCore function is a part of the
MegaCore IP Library, which is distributed with the Quartus II software and
downloadable from the Altera website, www.altera.com.
f
© February 2010
For system requirements and installation instructions, refer to Altera Software
Installation & Licensing.
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
1–8
Chapter 1: About This IP
Installation and Licensing
Installation and Licensing
Figure 1–2 shows the directory structure after you install the DDR3 SDRAM
High-Performance Controller MegaCore function, where <path> is the installation
directory. The default installation directory on Windows is c:\altera\<version>; on
Linux it is /opt/altera<version>.
Figure 1–2. Directory Structure
<path>
Installation directory.
ip
Contains the Alterar MegaCore IP Library and third-party IP cores.
altera
Contains the Altera MegaCore IP Library.
common
Contains shared components.
ddr3_high_perf
Contains the DDR3 SDRAM High-Performance Controllern files.
doc
Contains the documentation for the DDR3 SDRAM High-Performance Controller.
lib
Contains encypted lower-level design files and other support files.
You need a license for the MegaCore function only when you are completely satisfied
with its functionality and performance, and want to take your design to production.
To use the DDR3 SDRAM HPC, you can request a license file from the Altera web site
at www.altera.com/licensing and install it on your computer. When you request a
license file, Altera emails you a license.dat file. If you do not have Internet access,
contact your local representative.
To use the DDR3 SDRAM HPC II, contact your local sales representative to order a
license.
OpenCore Evaluation
Altera's OpenCore Plus evaluation feature is only applicable to the DDR3 SDRAM
HPC. With the OpenCore Plus evaluation feature, you can perform the following
actions:
■
Simulate the behavior of a megafunction (Altera MegaCore function or AMPPSM
megafunction) within your system
■
Verify the functionality of your design, as well as evaluate its size and speed
quickly and easily
■
Generate time-limited device programming files for designs that include
MegaCore functions
■
Program a device and verify your design in hardware
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 1: About This IP
Installation and Licensing
1–9
OpenCore Plus Time-Out Behavior
OpenCore Plus hardware evaluation can support the following two modes of
operation:
■
Untethered—the design runs for a limited time
■
Tethered—requires a connection between your board and the host computer. If
tethered mode is supported by all megafunctions in a design, the device can
operate for a longer time or indefinitely
All megafunctions in a device time-out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction's time-out behavior may be masked by the time-out behavior of
the other megafunctions.
1
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
1–10
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
Chapter 1: About This IP
Installation and Licensing
© February 2010 Altera Corporation
2. Getting Started
Design Flow
You can implement the DDR3 SDRAM High-Performance Controller MegaCore
function using either one of the following flows:
■
SOPC Builder flow
■
MegaWizard Plug-In Manager flow
You can only instantiate the ALTMEMPHY megafunction using the MegaWizard
Plug-In Manager flow.
Figure 2–1 shows the stages for creating a system in the Quartus II software using
either one of the flows.
Figure 2–1. Design Flow
Select Design Flow
SOPC Builder
Flow
MegaWizard
Flow
Specify Parameters
Specify Parameters
Complete
SOPC Builder System
Optional
Perform
Functional Simulation
Does
Simulation Give
Expected Results?
Yes
Add Constraints
and Compile Design
IP Complete
Debug Design
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
2–2
Chapter 2: Getting Started
SOPC Builder Flow
The SOPC Builder flow offers the following advantages:
■
Generates simulation environment
■
Creates custom components and integrates them via the component wizard
■
Interconnects all components with the Avalon-MM interface
The MegaWizard Plug-In Manager flow offers the following advantages:
■
Allows you to design directly from the DDR3 SDRAM interface to peripheral
device or devices
■
Achieves higher-frequency operation
SOPC Builder Flow
The SOPC Builder flow allows you to add the DDR3 SDRAM high-performance
controller directly to a new or existing SOPC Builder system.
You can also easily add other available components to quickly create an SOPC Builder
system with the DDR3 SDRAM high-performance controller, such as the Nios II
processor and scatter-gather direct memory access (DMA) controllers. SOPC Builder
automatically creates the system interconnect logic and system simulation
environment.
f
For more information about SOPC Builder, refer to volume 4 of the Quartus II
Handbook. For more information about how to use controllers with SOPC Builder,
refer to the DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the
External Memory Interface Handbook. For more information on the Quartus II software,
refer to the Quartus II Help.
Specify Parameters
To specify the parameters for the DDR3 SDRAM high-performance controllers using
the SOPC Builder flow, perform the following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard.
2. On the Tools menu, click SOPC Builder.
3. For a new system, specify the system name and language.
4. Add DDR3 SDRAM High-Performance Controller to your system from the
System Contents tab.
1
The DDR3 SDRAM High-Performance Controller is in the SDRAM folder
under the Memories and Memory Controllers folder.
5. Specify the required parameters on all s in the Parameter Settings tab.
f
For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1.
6. Click Finish to complete parameterizing the DDR3 SDRAM high-performance
controller and add it to the system.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
SOPC Builder Flow
2–3
Complete the SOPC Builder System
To complete the SOPC Builder system, perform the following steps:
1. In the System Contents tab, select Nios II Processor and click Add.
2. On the Nios II Processor, in the Core Nios II tab, select altmemddr for Reset
Vector and Exception Vector.
3. Change the Reset Vector Offset and the Exception Vector Offset to an Avalon
address that is not written to by the ALTMEMPHY megafunction during its
calibration process.
c The ALTMEMPHY megafunction performs memory interface calibration
every time it is reset, and in doing so, writes to a range of addresses. If you
want your memory contents to remain intact through a system reset, you
should avoid using these memory addresses. This step is not necessary if
you reload your SDRAM memory contents from flash every time you reset
your system.
If you are upgrading your Nios system design from version 8.1 or previous,
ensure that you change the Reset Vector Offset and the Exception Vector
Offset to AFI mode.
To calculate the Avalon-MM address equivalent of the memory address range 0×0
to 0×47, multiply the memory address by the width of the memory interface data
bus in bytes. Refer to Table 2–1 for more Avalon-MM addresses.
Table 2–1. Avalon-MM Addresses for AFI Mode
External Memory Interface
Width
Reset Vector Offset
Exception Vector Offset
8
0×60
0×80
16
0×A0
0×C0
32
0×120
0×140
64
0×240
0×260
4. Click Finish.
5. On the System Contents tab, expand Interface Protocols and expand Serial.
6. Select JTAG UART and click Add.
7. Click Finish.
1
If there are warnings about overlapping addresses, on the System menu,
click Auto Assign Base Addresses.
If you enable ECC and there are warnings about overlapping IRQs, on the
System menu click Auto Assign IRQs.
8. For this example system, ensure all the other modules are clocked on the
altmemddr_sysclk, to avoid any unnecessary clock-domain crossing logic.
9. Click Generate.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
2–4
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
1
Among the files generated by SOPC Builder is the Quartus II IP File (.qip).
This file contains information about a generated IP core or system. In most
cases, the .qip file contains all of the necessary assignments and
information required to process the MegaCore function or system in the
Quartus II compiler. Generally, a single .qip file is generated for each SOPC
Builder system. However, some more complex SOPC Builder components
generate a separate .qip file. In that case, the system .qip file references the
component .qip file.
10. Compile your design, refer to “Compile and Simulate” on page 4–1.
MegaWizard Plug-In Manager Flow
The MegaWizard Plug-In Manager flow allows you to customize the DDR3 SDRAM
high-performance controller or ALTMEMPHY megafunction, and manually integrate
the function into your design.
1
f
You can alternatively use the IP Advisor to help you start your DDR3 SDRAM
high-performance controller design. On the Quartus II Tools menu, point to Advisors,
and then click IP Advisor. The IP Advisor guides you through a series of
recommendations for selecting, parameterizing, evaluating, and instantiating a DDR3
SDRAM high-performance controller into your design. It then guides you through a
complete Quartus II compilation of your project.
For more information about the MegaWizard Plug-In Manager and the IP Advisor,
refer to the Quartus II Help.
Specify Parameters
To specify parameters using the MegaWizard Plug-In Manager flow, perform the
following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard.
2. On the Tools menu, click MegaWizard Plug-In Manager to start the MegaWizard
Plug-In Manager.
■
The DDR3 SDRAM High-Performance Controller is in the Interfaces folder
under the External Memory folder.
■
The ALTMEMPHY megafunction is in the I/O folder.
1
The <variation name> must be a different name from the project name and
the top-level design entity name.
3. Specify the parameters on all s in the Parameter Settings tab.
f
For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
2–5
4. On the EDA tab, turn on Generate simulation model to generate an IP functional
simulation model for the MegaCore function in the selected language.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
c Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional
design.
1
Some third-party synthesis tools can use a netlist that contains only the
structure of the MegaCore function, but not detailed logic, to optimize
performance of the design that contains the MegaCore function. If your
synthesis tool supports this feature, turn on Generate netlist.
When targeting a VHDL simulation model, the MegaWizard Plug-In
Manager still generates the <variation_name>_alt_mem_phy.v file for the
Quartus II synthesis. Do not use this file for simulation. Use the
<variation_name>.vho file for simulation instead.
The ALTMEMPHY megafunction only supports functional simulation. You
cannot perform timing or gate-level simulation when using the
ALTMEMPHY megafunction.
5. On the Summary tab, select the files you want to generate. A gray checkmark
indicates a file that is automatically generated. All other files are optional.
6. Click Finish to generate the MegaCore function and supporting files. A generation
report appears.
7. If you generate the MegaCore function instance in a Quartus II project, you are
prompted to add the .qip files to the current Quartus II project. When prompted to
add the .qip files to your project, click Yes. The addition of the .qip files enables
their visibility to Nativelink. Nativelink requires the .qip files to include libraries
for simulation.
1
The .qip file is generated by the MegaWizard interface, and contains
information about the generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore function or system in the Quartus II compiler. The MegaWizard
interface generates a single .qip file for each MegaCore function.
8. After you review the generation report, click Exit to close the MegaWizard Plug-In
Manager.
9. For the high-performance controller (HPC or HPC II), set the <variation
name>_example_top.v or .vhd file to be the project top-level design file.
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
2–6
Chapter 2: Getting Started
Generated Files
Generated Files
Table 2–2 shows the ALTMEMPHY generated files.
Table 2–2. ALTMEMPHY Generated Files (Part 1 of 2)
File Name
Description
alt_mem_phy_defines.v
Contains constants used in the interface. This file is
always in Verilog HDL regardless of the language you
chose in the MegaWizard Plug-In Manager.
<variation_name>.html
Lists the top-level files created and ports used in the
megafunction.
<variation_name>.ppf
Pin planner file for your ALTMEMPHY variation.
<variation_name>.qip
Quartus II IP file for your ALTMEMPHY variation,
containing the files associated with this megafunction.
<variation_name>.v/.vhd
Top-level file of your ALTMEMPHY variation, generated
based on the language you chose in the MegaWizard
Plug-In Manager.
<variation_name>.vho
Contains functional simulation model for VHDL only.
<variation_name>_alt_mem_phy_delay.vhd
Includes a delay module for simulation. This file is only
generated if you choose VHDL as the language of your
MegaWizard Plug-In Manager output files.
<variation_name>_alt_mem_phy_dq_dqs.vhd or .v
Generated file that contains DQ/DQS I/O atoms
interconnects and instance. Arria II GX devices only.
<variation_name>_alt_mem_phy_dq_dqs_clearbox.txt
Specification file that generates the
<variation_name>_alt_mem_phy_dq_dqs file using
the clearbox flow. Arria II GX devices only.
<variation_name>_alt_mem_phy_pll.qip
Quartus II IP file for the PLL that your ALTMEMPHY
variation uses that contains the files associated with
this megafunction.
<variation_name>_alt_mem_phy_pll.v/.vhd
The PLL megafunction file for your ALTMEMPHY
variation, generated based on the language you chose
in the MegaWizard Plug-In Manager.
<variation_name>_alt_mem_phy_pll_bb.v/.cmp
Black box file for the PLL used in your ALTMEMPHY
variation. Typically unused.
<variation_name>_alt_mem_phy_seq.vhd
Contains the sequencer used during calibration. This
file is always in VHDL language regardless of the
language you chose in the MegaWizard Plug-In
Manager.
<variation_name>_alt_mem_phy_seq_wrapper.v/.vhd
A wrapper file, for compilation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
<variation_name>_alt_mem_phy_seq_wrapper.vo/.vho
A wrapper file, for simulation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
Generated Files
2–7
Table 2–2. ALTMEMPHY Generated Files (Part 2 of 2)
File Name
Description
<variation_name>_alt_mem_phy.v
Contains all modules of the ALTMEMPHY variation
except for the sequencer. This file is always in Verilog
HDL language regardless of the language you chose in
the MegaWizard Plug-In Manager. The DDR3 SDRAM
sequencer is included in the
<variation_name>_alt_mem_phy_seq.vhd file.
<variation_name>_bb.v/.cmp
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
<variation_name>_ddr_pins.tcl
Contains procedures used in the
<variation_name>_ddr_timing.sdc and
<variation_name>_report_timing.tcl files.
<variation_name>_ddr_timing.sdc
Contains timing constraints for your ALTMEMPHY
variation.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable
grouping, DQ/DQS grouping, and termination
assignments for your ALTMEMPHY variation. If your
top-level design pin names do not match the default
pin names or a prefixed version, edit the assignments
in this file.
<variation_name>_report_timing.tcl
Script that reports timing for your ALTMEMPHY
variation during compilation.
Table 2–3 shows the modules that are instantiated in the
<variation_name>_alt_mem_phy.v/.vhd file. A particular ALTMEMPHY variation
may or may not use any of the modules, depending on the memory standard that you
specify.
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 1 of 2)
Module Name
Usage
Description
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
addr_cmd
Generates the address and command structures.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
clk_reset
Instantiates PLL, DLL, and reset logic.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
dp_io
Generates the DQ, DQS, DM, and QVLD I/O pins.
<variation_name>_alt_mem_phy_ DDR3 SDRAM ALTMEMPHY
mimic
variation
Creates the VT tracking mechanism for DDR3
SDRAM PHYs.
<variation_name>_alt_mem_phy_
oct_delay
Generates the proper delay and duration for the
OCT signals.
DDR3 SDRAM ALTMEMPHY
variation when dynamic OCT is
enabled.
<variation_name>_alt_mem_phy_ DDR3 SDRAM ALTMEMPHY
postamble
variations
Generates the postamble enable and disable
scheme for DDR3 PHYs.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
read_dp
(unused for Stratix III or
Stratix IV devices)
Takes read data from the I/O through a read path
FIFO buffer, to transition from the
resyncronization clock to the PHY clock.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
2–8
Chapter 2: Getting Started
Generated Files
Table 2–3. Modules in <variation_name>_alt_mem_phy.v File (Part 2 of 2)
Module Name
Usage
Description
<variation_name>_alt_mem_phy_ DDR3 SDRAM ALTMEMPHY
read_dp_group
variations (Stratix III and
Stratix IV devices only)
A per DQS group version of
<variation_name>_alt_mem_phy_read_dp.
<variation_name>_alt_mem_phy_ DDR3 SDRAM ALTMEMPHY
rdata_valid
variations
Generates read data valid signal to sequencer and
controller.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
seq_wrapper
Generates sequencer for DDR3 SDRAM.
<variation_name>_alt_mem_phy_ All ALTMEMPHY variations
write_dp
Generates the demultiplexing of data from
half-rate to full-rate DDR data.
Table 2–4 through Table 2–6 show the additional files generated by the
high-performance controllers, that may be in your project directory. The names and
types of files specified in the MegaWizard Plug-In Manager report vary based on
whether you created your design with VHDL or Verilog HDL.
1
In addition to the files in Table 2–4 through Table 2–6, the MegaWizard also generates
the ALTMEMPHY files in Table 2–2, but with a _phy prefix. For example,
<variation_name>_alt_mem_phy_delay.vhd becomes
<variation_name>_phy_alt_mem_phy_delay.vhd.
Table 2–4. Controller Generated Files—All High Performance Controllers (Part 1 of 2)
Filename
Description
<variation name>.bsf
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
<variation name>.html
MegaCore function report file.
<variation name>.v or .vhd
A MegaCore function variation file, which defines a
VHDL or Verilog HDL top-level description of the
custom MegaCore function. Instantiate the entity
defined by this file inside of your design. Include this
file when compiling your design in the Quartus II
software.
<variation name>.qip
Contains Quartus II project information for your
MegaCore function variations.
<variation name>.ppf
XML file that describes the MegaCore pin attributes to
the Quartus II Pin Planner. MegaCore pin attributes
include pin direction, location, I/O standard
assignments, and drive strength. If you launch IP
Toolbench outside of the Pin Planner application, you
must explicitly load this file to use Pin Planner.
<variation name>_example_driver.v or .vhd
Example self-checking test generator that matches
your variation.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 2: Getting Started
Generated Files
2–9
Table 2–4. Controller Generated Files—All High Performance Controllers (Part 2 of 2)
Filename
Description
<variation name>_example_top.v or .vhd
Example top-level design file that you should set as
your Quartus II project top level. Instantiates the
example driver and the controller.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable
grouping, and termination assignments for your
ALTMEMPHY variation. If your top-level design pin
names do not match the default pin names or a
prefixed version, edit the assignments in this file.
Table 2–5. Controller Generated Files—DDR3 High Performance Controller (HPC)
Filename
Description
<variation name>_auk_ddr_hp_controller_wrapper.vo or .vho
VHDL or Verilog HDL IP functional simulation model.
<variation_name>_auk_ddr_hp_controller_ecc_wrapper.vo or .vho ECC functional simulation model.
.
Table 2–6. Controller Generated Files—DDR3 High Performance Controller II (HPC II) (Part 1 of 2)
Filename
Description
<variation name>_alt_ddrx_controller_wrapper. A controller wrapper which instantiates the alt_ddrx_controller.v file
v or .vho
and configures the controller accordingly by the wizard.
alt_ddrx_addr_cmd.v
Decodes the state machine outputs into the memory address and
command signals.
alt_ddrx_afi_block.v
Generates the read and write control signals for the AFI.
alt_ddrx_bank_tracking.v
Tracks which row is open in which memory bank.
alt_ddrx_clock_and_reset.v
Contains the clock and reset logic.
alt_ddrx_cmd_queue.v
Contains the command queue logic.
alt_ddrx_controller.v
The controller top-level file that instantiates all the sub-blocks.
alt_ddrx_csr.v
Contains the control and status register interface logic.
alt_ddrx_ddr3_odt_gen.v
Generates the on-die termination (ODT) control signal for DDR3 memory
interfaces.
alt_ddrx_avalon_if.v
Communicates with the Avalon-MM interface.
alt_ddrx_decoder_40.v
Contains the 40 bit version of the ECC decoder logic.
alt_ddrx_decoder_72.v
Contains the 72 bit version of the ECC decoder logic.
alt_ddrx_decoder.v
Instantiates the appropriate width ECC decoder logic.
alt_ddrx_encoder_40.v
Contains the 40 bit version of the ECC encoder logic.
alt_ddrx_encoder_72.v
Contains the 72 bit version of the ECC encoder logic.
alt_ddrx_encoder.v
Instantiates the appropriate width ECC encoder logic.
alt_ddrx_input_if.v
Instantiates the input interface block. It instantiates the
alt_ddrx_cmd_queue.v, alt_ddrx_wdata_fifo.v, and
alt_ddrx_avalon_if.v files.
alt_ddrx_odt_gen.v
Instantiates the alt_ddrx_ddr3_odt_gen.v file selectively. It also controls
the ODT addressing scheme.
alt_ddrx_state_machine.v
The main state machine of the controller.
alt_ddrx_timers_fsm.v
The state machine that tracks the per-bank timing parameters.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
2–10
Chapter 2: Getting Started
Generated Files
Table 2–6. Controller Generated Files—DDR3 High Performance Controller II (HPC II) (Part 2 of 2)
Filename
Description
alt_ddrx_timers.v
Instantiates alt_ddrx_timers_fsm.v and contains the rank specific
timing tracking logic.
alt_ddrx_wdata_fifo.v
The write data FIFO logic. This logic buffers the write data and byte
enables from the Avalon interface.
alt_avalon_half_rate_bridge_constraints.sdc
Contains timing constraints if your design has the Enable Half Rate
Bridge option turned on.
alt_avalon_half_rate_bridge.v
The integrated half-rate bridge logic block.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
3. Parameter Settings
ALTMEMPHY Parameter Settings
The ALTMEMPHY Parameter Settings page in the ALTMEMPHY MegaWizard
interface (Figure 3–1) allows you to parameterize the following settings:
■
Memory Settings
■
PHY Settings
■
Board Settings
■
Controller Interface Settings
Figure 3–1. ALTMEMPHY Parameter Settings Page
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–2
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
The text window at the bottom of the MegaWizard Plug-In Manager displays
information about the memory interface, warnings, and errors if you are trying to
create something that is not supported. The Finish button is disabled until you correct
all the errors indicated in this window.
The following sections describe the four tabs of the Parameter Settings page in more
detail.
Memory Settings
In the Memory Settings tab, you can select a particular memory device for your
system and choose the frequency of operation for the device. Under General Settings,
you can choose the device family, speed grade, and clock information. In the middle
of the page (left-side), you can filter the available memory device listed on the right
side of the Memory Presets page, refer to Figure 3–1. If you cannot find the exact
device that you are using, choose a device that has the closest specifications, then
manually modify the parameters to match your actual device by clicking Modify
parameters, next to the Selected memory preset field.
Table 3–1 describes the General Settings available on the Memory Settings page of
the ALTMEMPHY MegaWizard interface.
Table 3–1. General Settings
Parameter Name
Description
Device family
Targets device family (for example, Stratix III). Table 1–2 on page 1–3 shows supported device
families. The device family selected here must match the device family selected on the MegaWizard
page 2a.
Speed grade
Selects a particular speed grade of the device (for example, 2, 3, or 4 for the Stratix III device
family).
PLL reference clock
frequency
Determines the clock frequency of the external input clock to the PLL. Ensure that you use three
decimal points if the frequency is not a round number (for example, 166.667 MHz or 100 MHz) to
avoid a functional simulation or a PLL locking problem.
Memory clock
frequency
Determines the memory interface clock frequency. If you are operating a memory device below its
maximum achievable frequency, ensure that you enter the actual frequency of operation rather than
the maximum frequency achievable by the memory device. Also, ensure that you use three decimal
points if the frequency is not a round number (for example, 333.333 MHz or 400 MHz) to avoid a
functional simulation or a PLL locking issue.
Controller data rate
Selects the data rate for the memory controller. Sets the frequency of the controller to equal to
either the memory interface frequency (full-rate) or half of the memory interface frequency
(half-rate). The full-rate option is not available for DDR3 SDRAM devices.
Enable half rate bridge This option is only available for HPC II full-rate controller.
Turn on to keep the controller in the memory full clock domain while allowing the local side to run
at half the memory clock speed, so that latency can be reduced.
Local interface clock
frequency
Value that changes with the memory device that you choose from the Memory Presets list.
Local interface width
Value that depends on the memory clock frequency and controller data rate, and whether or not
you turn on the Enable Half Rate Bridge option.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–3
Table 3–2 describes the options available to filter the Memory Presets that are
displayed. This set of options is where you indicate whether you are creating a
datapath for DDR3 SDRAM.
Table 3–2. Memory Presets List
Parameter Name
Description
Memory type
You can filter the type of memory to display, for example, DDR3 SDRAM.
Memory vendor
You can filter the memory types by vendor. JEDEC is also one of the options, allowing you to
choose the JEDEC specifications. If your chosen vendor is not listed, you can choose JEDEC for the
DDR3 SDRAM interfaces. Then, pick a device that has similar specifications to your chosen device
and check the values of each parameter. Make sure you change the each parameter value to match
your device specifications.
Memory format
You can filter the type of memory by format, for example, discrete devices or DIMM packages.
Maximum frequency
You can filter the type of memory by the maximum operating frequency.
Use the Preset Editor to Create a Custom Memory Preset
Pick a device in the Memory Presets list that is closest or the same as the actual
memory device that you are using. Then, click the Modify Parameters button to
parameterize the following settings in the Preset Editor dialog box:
1
■
Memory attributes—These are the settings that determine your system's number
of DQ, DQ strobe (DQS), address, and memory clock pins.
■
Memory initialization options—These settings are stored in the memory mode
registers as part of the initialization process.
■
Memory timing parameters—These are the parameters that create and
time-constrain the PHY.
Even though the device you are using is listed in Memory Presets, ensure that the
settings in the Preset Editor dialog box are accurate, as some parameters may have
been updated in the memory device datasheets.
You can change the parameters with a white background to reflect your system. You
can also change the parameters with a gray background so the device parameters
match the device you are using. These parameters in gray background are
characteristics of the chosen memory device and changing them creates a new custom
memory preset. If you click Save As (at the bottom left of the page) and save the new
settings in the <quartus_install_dir>\quartus\common\ip\altera\altmemphy\lib\
directory, you can use this new memory preset in other Quartus II projects created in
the same version of the software.
When you click Save, the new memory preset appears at the bottom of the Memory
Presets list in the Memory Settings tab.
1
© February 2010
If you save the new settings in a directory other than the default directory, click Load
Preset in the Memory Settings tab to load the settings into the Memory Presets list.
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–4
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Figure 3–2 shows the Preset Editor dialog box for a DDR3 SDRAM.
Figure 3–2. DDR3 SDRAM Preset Editor
The Advanced option is only available for Arria II GX and Stratix IV devices. This
option shows the percentage of memory specification that is calibrated by the FPGA.
The percentage values are estimated by Altera based on the process variation.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–5
Table 3–3 through Table 3–5 describe the DDR3 SDRAM parameters available for
memory attributes, initialization options, and timing parameters.
Table 3–3. DDR3 SDRAM Attributes Settings (Part 1 of 2)
Parameter Name
Range (1)
Units
Description
Output clock pairs from FPGA
1–6
pairs
Defines the number of differential clock pairs driven from
the FPGA to the memory. Memory clock pins use the
signal splitter feature in Arria II GX, Stratix III and
Stratix IV devices for differential signaling.
The ALTMEMPHY MegaWizard Plug-In Manager displays
an error on the bottom of the window if you choose more
than one for DDR3 SDRAM interfaces.
Total Memory chip selects
1, 2, 4, or 8
bits
Sets the number of chip selects in your memory
interface. The depth of your memory in terms of number
of chips. You are limited to the range shown as the local
side binary encodes the chip select address.
Memory interface DQ width
4–288
bits
Defines the total number of DQ pins on the memory
interface. If you are interfacing with multiple devices,
multiply the number of devices with the number of DQ
pins per device. Even though the GUI allows you to
choose 288-bit DQ width, DDR3 SDRAM variations are
only supported up to 80-bit width due to restrictions in
the board layout which affects timing at higher data
width. Furthermore, the interface data width is limited by
the number of pins on the device. For best performance,
have the whole interface on one side of the device.
—
—
On multiple rank DDR3 SDRAM DIMMs address signals
are routed differently to each rank (referred to in the
JEDEC specification as address mirroring).
Mirror addressing
Enter ranks with mirrored addresses in this field. There is
one bit per chip select. For example, for four chip selects,
enter 1011 to mirror the address on chip select #3, #1,
and #0.
Register Control Word 0–15
for Registered DIMMs
—
bits
Register Control Word values for the Registered DIMMs.
The values are available in the memory data sheet of the
respective Registered DIMMs.
Memory vendor
Elpida, JEDEC,
Micron,
Samsung, Hynix,
Nanya, other
—
Lists the name of the memory vendor for all supported
memory standards.
Memory format
Discrete Device,
Unbuffered
DIMM
—
Specifies whether you are interfacing with devices or
modules. SODIMM and MicroDIMM are supported under
unbuffered DIMMs. The ALTMEMPHY megafunction for
DDR3 SDRAM interfaces does not support registered
DIMM format. Arria II GX devices only support DDR3
SDRAM components without leveling, for example,
Discrete Device memory format.
Maximum memory frequency
See the memory
device datasheet
MHz
Sets the maximum frequency supported by the memory.
10–12
bits
Defines the number of column address bits for your
interface.
Column address width
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–6
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–3. DDR3 SDRAM Attributes Settings (Part 2 of 2)
Parameter Name
Range (1)
Units
Description
Row address width
12–16
bits
Defines the number of row address bits for your
interface. If your DDR3 SDRAM device’s row address bus
is 12-bit wide, set the row address width to 13 and set the
13th bit to logic-level low (or leave the 13th bit
unconnected to the memory device) in the top-level file.
Bank address width
3
bits
Defines the number of bank address bits for your
interface.
Chip selects per DIMM
1 or 2
bits
Defines the number of chip selects on each DIMM in your
interface. Currently, calibration is done with all ranks but
you can only perform timing analysis with one
single-rank DIMM.
DQ bits per DQS bit
4 or 8
bits
Defines the number of data (DQ) bits for each data strobe
(DQS) pin.
Yes or No
—
Specifies whether you are using DM pins for write
operation. Altera devices do not support DM pins with ×4
mode.
80–700
MHz
Specifies the frequency limits from the memory data
sheet per given CAS latency. The ALTMEMPHY
MegaWizard Plug-In Manager generates a warning if the
operating frequency with your chosen CAS latency
exceeds this number. The lowest frequency supported by
DDR3 SDRAM devices is 300 MHz.
Drive DM pins from FPGA
Maximum memory frequency
for CAS latency 5.0
Maximum memory frequency
for CAS latency 6.0
Maximum memory frequency
for CAS latency 7.0
Maximum memory frequency
for CAS latency 8.0
Maximum memory frequency
for CAS latency 9.0
Maximum memory frequency
for CAS latency 10.0
Note to Table 3–3:
(1) The range values depend on the actual memory device used.
Table 3–4. DDR3 SDRAM Initialization Options (Part 1 of 2)
Parameter Name
Range
Units
Memory burst length
4, 8, on-the-fly
Beats
Sets the number of words read or written per transaction.
Sequential or
Interleaved
—
Controls the order in which data is transferred between
memory and the FPGA during a read transaction. For more
information, refer to the memory device datasheet.
DLL precharge power
down
Fast exit or Slow
exit
—
Sets the mode register setting to disable (Slow exit) or enable
(Fast exit) the memory DLL when CKE is disabled.
Enable the DLL in the
memory devices
Yes or No
—
Enables the DLL in the memory device when set to Yes. You
must always enable the DLL in the memory device as Altera
does not guarantee any ALTMEMPHY operation when the DLL
is turned off. All timings from the memory devices are invalid
when the DLL is turned off.
Memory burst
ordering
Description
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–7
Table 3–4. DDR3 SDRAM Initialization Options (Part 2 of 2)
Parameter Name
Range
Units
Description
ODT disable,
RZQ/4, RZQ/2,
RZQ/6
Ω
RZQ in DDR3 SDRAM interfaces are set to 240 Ω . Sets the
on-die termination (ODT) value to either 60 Ω (RZQ/4), 120 Ω
(RZQ/2), or 40 Ω (RZQ/6). Set this to ODT disable if you are
not planning to use ODT. For a single-ranked DIMM, set this to
RZQ/4.
Dynamic ODT
(Rtt_WR) value
Dynamic ODT off,
RZQ/4, RZQ/2
Ω
RZQ in DDR3 SDRAM interfaces are set to 240 Ω . Sets the
memory ODT value during write operations to 60 Ω (RZQ/4)
or 120 Ω (RZQ/2). As ALTMEMPHY only supports single rank
DIMMs, you do not need this option (set to Dynamic ODT off).
Output driver
impedance
RZQ/6 (Reserved)
or RZQ/7
Ω
RZQ in DDR3 SDRAM interfaces are set to 240 Ω . Sets the
output driver impedance from the memory device. Some
devices may not have RZQ/6 available as an option. Be sure to
check the memory device datasheet before choosing this
option.
Memory CAS latency
setting
5.0, 6.0, 7.0, 8.0,
9.0, 10.0
Cycles
Sets the delay in clock cycles from the read command to the
first output data from the memory.
Memory additive CAS
latency setting
Disable, CL – 1,
Cycles
Allows you to add extra latency in addition to the CAS latency
setting.
Memory write CAS
latency setting (CWL)
5.0, 6.0, 7.0, 8.0
Cycles
Sets the delay in clock cycles from the write command to the
first expected data to the memory.
Memory partial array
self refresh
Full array, Half
array
{BA[2:0]=000,001,
010,011},
—
Determine whether you want to self-refresh only certain arrays
instead of the full array. According to the DDR3 SDRAM
specification, data located in the array beyond the specified
address range are lost if self refresh is entered when you use
this. This option is not supported by the DDR3 SDRAM
High-Performance Controller MegaCore function, so set to
Full Array if you are using the Altera controller.
Manual SR
reference (SRT) or
ASR enable
(Optional)
—
Sets the auto self-refresh method for the memory device. The
DDR3 SDRAM High-Performance Controller MegaCore
function currently does not support the ASR option that you
need for extended temperature memory self-refresh.
Normal or
Extended
—
Determines the temperature range for self refresh. You need to
also use the optional auto self refresh option when using this
option. The Altera controller currently does not support the
extended temperature self-refresh operation.
ODT Rtt nominal
value
CL – 2
Quarter array
{BA[2:0]=000,001},
Eighth array
{BA[2:0]=000},
Three Quarters
array
{BA[2:0]=010,011,
100,101,110,111},
Half array
{BA[2:0]=100,101,
110,111},
Quarter array
{BA[2:0]=110,
111}, Eighth array
{BA[2:0]=111}
Memory auto self
refresh method
Memory self refresh
range
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–8
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–5. DDR3 SDRAM Timing Parameter Settings (Part 1 of 2)
Parameter
Name
(Note 1)
Range
Units
Description
0–1000000
µs
Minimum time to hold the reset after a power cycle before issuing the MRS
commands during the DDR3 SDRAM device initialization process.
tINIT
0.001–
1000
µs
Minimum memory initialization time. After reset, the controller does not
issue any commands to the memory during this period.
tMRD
2–39
ns
Minimum load mode register command period. The controller waits for this
period of time after issuing a load mode register command before issuing
any other commands.
Time to hold
memory reset
before beginning
calibration
tMRD is specified in ns but in terms of tCK cycles in Micron's device datasheet.
Convert tMRD to ns by multiplying the number of cycles specified in the
datasheet times tCK, where tCK is the memory operation frequency and not the
memory device's tCK.
tRAS
8–200
ns
Minimum active to precharge time. The controller waits for this period of
time after issuing an active command before issuing a precharge command
to the same bank.
tRCD
4–65
ns
Minimum active to read-write time. The controller does not issue read or
write commands to a bank during this period of time after issuing an active
command.
tRP
4–65
ns
Minimum precharge command period. The controller does not access the
bank for this period of time after issuing a precharge command.
tREFI
1–65534
µs
Maximum interval between refresh commands. The controller performs
regular refresh at this interval unless user-controlled refresh is turned on.
tRFC
14–1651
ns
Minimum autorefresh command period. The length of time the controller
waits before doing anything else after issuing an auto-refresh command.
tWR
4–65
ns
Minimum write recovery time. The controller waits for this period of time
after the end of a write transaction before issuing a precharge command.
tWTR
1–6
tCK
Minimum write-to-read command delay. The controller waits for this period
of time after the end of a write command before issuing a subsequent read
command to the same bank. This timing parameter is specified in clock
cycles and the value is rounded off to the next integer.
tAC
0–750
ps
DQ output access time.
tDQSCK
50–750
ps
DQS output access time from CK/CK# signals.
tDQSQ
50–500
ps
The maximum DQS to DQ skew; DQS to last DQ valid, per group, per access.
tDQSS
0–0.3
tCK
Positive DQS latching edge to associated clock edge.
10–600
ps
DQ and DM input hold time relative to DQS, which has a derated value
depending on the slew rate of the differential DQS and DQ/DM signals.
Ensure that you are using the correct number and that the value entered is
referenced to VREF(dc), not VIH(dc) min or VIL(dc) max. Refer to “Derate
Memory Setup and Hold Timing” on page 3–9 for more information about
how to derate this specification.
tDH
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–9
Table 3–5. DDR3 SDRAM Timing Parameter Settings (Part 2 of 2)
Parameter
Name
(Note 1)
Range
Units
Description
tDS
10–600
ps
DQ and DM input setup time relative to DQS, which has a derated value
depending on the slew rate of the differential DQS signals and DQ/DM
signals. Ensure that you are using the correct number and that the value
entered is referenced to VREF(dc), not VIH(ac) min or VIL(ac) max. Refer to
“Derate Memory Setup and Hold Timing” on page 3–9 for more information
about how to derate this specification.
tDSH
0.1–0.5
tCK
DQS falling edge hold time from CK.
tDSS
0.1–0.5
tCK
DQS falling edge to CK setup.
tIH
50–1000
ps
Address and control input hold time, which has a derated value depending on
the slew rate of the CK and CK# clocks and the address and command
signals. Ensure that you are using the correct number and that the value
entered is referenced to VREF(dc), not VIH(dc) min or VIL(dc) max. Refer to
“Derate Memory Setup and Hold Timing” on page 3–9 for more information
about how to derate this specification.
tIS
65–1000
ps
Address and control input setup time, which has a derated value depending
on the slew rate of the CK and CK# clocks and the address and command
signals. Ensure that you are using the correct number and that the value
entered is referenced to VREF(dc), not VIH(ac) min or VIL(ac) max. Refer to
“Derate Memory Setup and Hold Timing” on page 3–9 for more information
about how to derate this specification.
tQHS
0–700
ps
The maximum data hold skew factor.
tQH
0.1–0.6
tCK
DQ output hold time.
tRRD
2.06–64
ns
The activate to activate time, per device, RAS to RAS delay timing parameter.
tFAW
7.69–256
ns
The four-activate window time, per device.
tRTP
2.06–64
ns
Read to precharge time.
Note to Table 3–5:
(1) See the memory device data sheet for the parameter range. Some of the parameters may be listed in a clock cycle (tCK) unit. If the MegaWizard
Plug-In Manager requires you to enter the value in a time unit (ps or ns), convert the number by multiplying it with the clock period of your
interface (and not the maximum clock period listed in the memory data sheet).
Derate Memory Setup and Hold Timing
Because the base setup and hold time specifications from the memory device
datasheet assume input slew rates that may not be true for Altera devices, derate and
update the following memory device specifications in the Preset Editor dialog box:
1
© February 2010
■
tDS
■
tDH
■
tIH
■
tIS
For Arria II GX and Stratix IV devices, you need not derate using the Preset Editor.
You only need to enter the parameters referenced to VREF , and the deration is done
automatically when you enter the slew rate information on the Board Settings tab.
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–10
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
After derating the values, you then need to normalize the derated value because
Altera input and output timing specifications are referenced to VREF. When the
memory device setup and hold time numbers are derated and normalized to VREF,
update these values in the Preset Editor dialog box to ensure that your timing
constraints are correct.
The following memory device specifications and update the Preset Editor dialog box
with the derated value:
For example, according to JEDEC, 533-MHz DDR3 SDRAM has the following
specifications, assuming 1V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn
slew rate:
■
Base tDS = 25
■
Base tDH = 100
■
VIH(ac) = VREF + 0.175 V
■
VIH(dc) = VREF + 0.100 V
■
VIL(ac) = VREF – 0.175 V
■
VIL(dc) = VREF – 0.100 V
The VREF referenced setup and hold signals for a rising edge are:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 25 + 0 + 175 = 200 ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 100 + 0 + 100 =
200 ps
If the output slew rate of the write data is different from 1V/ns, you have to first
derate the tDS and tDH values, then translate these AC/DC level specs to VREF
specification.
For a 2V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn slew rate:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 25 + 88 + 87.5 = 200.5
ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 100 + 50 + 50 = 200
ps
For a 0.5V/ns DQ slew rate rising signal and 1V/ns DQS-DQSn slew rate:
tDS (VREF) = Base tDS + delta tDS + (VIH(ac) – VREF)/slew_rate = 25 + 5 + 350 = 380 ps
tDH (VREF) = Base tDH + delta tDH + (VIH(dc) – VREF)/slew_rate = 100 + 10 + 200 =
310 ps
PHY Settings
Click Next or the PHY Settings tab to set the options described in Table 3–6. The
options are available if they apply to the target Altera device.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
3–11
Table 3–6. ALTMEMPHY PHY Settings (Part 1 of 2)
Parameter Name
Applicable Device Families
Description
Use dedicated PLL
outputs to drive
memory clocks
HardCopy II and Stratix II
(prototyping for
HardCopy II)
This option is disabled for DDR3 SDRAM.
Dedicated memory
clock phase
HardCopy II and Stratix II
(prototyping for
HardCopy II)
This option is disabled for DDR3 SDRAM.
Use differential DQS
Arria II GX, Stratix III, and
Stratix IV
This option is disabled for DDR3 SDRAM.
Enable external access
to reconfigure PLL
prior to calibration
HardCopy II and Stratix II
(prototyping for
HardCopy II)
This option is disabled for DDR3 SDRAM.
Instantiate DLL
externally
All supported device
families.
Use this option with Stratix III, Stratix IV, HardCopy III, or
HardCopy IV devices, if you want to apply a non-standard phase
shift to the DQS capture clock. The ALTMEMPHY DLL offsetting I/O
can then be connected to the external DLL and the Offset Control
Block.
Enable dynamic parallel Stratix III and Stratix IV
on-chip termination
(OCT)
This option provides I/O impedance matching and termination
capabilities. The ALTMEMPHY megafunction enables parallel
termination during reads and series termination during writes with
this option checked. Only applicable for DDR3 SDRAM interfaces
where DQ and DQS are bidirectional. Using the dynamic
termination requires that you use the OCT calibration block, which
may impose a restriction on your DQS/DQ pin placements
depending on your RUP/RDN pin locations.
For more information, refer to either the External Memory
Interfaces in Stratix III Devices chapter in volume 1 of the Stratix III
Device Handbook or the External Memory Interfaces in Stratix IV
Devices chapter in volume 1 of the Stratix IV Device Handbook.
Clock phase
Arria II GX
Adjusting the address and command phase can improve the
address and command setup and hold margins at the memory
device to compensate for the propagation delays that vary with
different loadings. You have a choice of 0°, 90°, 180°, and 270°,
based on the rising and falling edge of the phy_clk and
write_clk signals. In Stratix IV and Stratix III devices, the clock
phase is set to dedicated.
Dedicated clock phase
Stratix III and Stratix IV
When you use a dedicated PLL output for address and command,
you can choose any legal PLL phase shift to improve setup and
hold for the address and command signals. You can set this value
to between 180° and 359° (the default is 240°). However, generally
PHY timing requires a value of greater than 240° for half-rate
designs.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–12
Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
Table 3–6. ALTMEMPHY PHY Settings (Part 2 of 2)
Parameter Name
Applicable Device Families
Description
Board skew
All supported device
families except Arria II GX
and Stratix IV devices
Maximum skew across any two memory interface signals for the
whole interface from the FPGA to the memory (either a discrete
memory device or a DIMM). This parameter includes all types of
signals (data, strobe, clock, address, and command signals). You
need to input the worst-case skew, whether it is within a DQS/DQ
group, or across all groups, or across the address and command
and clocks signals. This parameter generates the timing constraints
in the .sdc file.
Autocalibration
simulation options
All supported device
families
Choose between Full Calibration (long simulation time), Quick
Calibration, or Skip Calibration.
For more information, refer to the Simulation section in volume 4 of
the External Memory Interface Handbook.
Board Settings
Click Next or the Board Settings tab to set the options described in Table 3–7. The
board settings parameters are set to model the board level effects in the timing
analysis. The options are available if you choose Arria II GX or Stratix IV device for
your interface. Otherwise, the options are disabled.
Table 3–7. ALTMEMPHY Board Settings (Part 1 of 2)
Parameter Name
Number of slots/discrete devices
Units
—
Description
Sets the single-rank or multirank configuration.
CK/CK# slew rate (differential)
V/ns
Sets the differential slew rate for the CK and CK# signals.
Addr/command slew rate
V/ns
Sets the slew rate for the address and command signals.
DQ/DQS# slew rate (differential)
V/ns
Sets the differential slew rate for the DQ and DQS# signals.
DQ slew rate
V/ns
Sets the slew rate for the DQ signals.
Addr/command eye reduction
(setup)
ns
Sets the reduction in the eye diagram on the setup side due to the
ISI on the address and command signals.
Addr/command eye reduction
(hold)
ns
Sets the reduction in the eye diagram on the hold side due to the ISI
on the address and command signals.
DQ eye reduction
ns
Sets the total reduction in the eye diagram on the setup side due to
the ISI on the DQ signals.
Delta DQS arrival time
ns
Sets the increase of variation on the range of arrival times of DQS
due to ISI.
Min CK/DQS skew to DIMM
ns
Sets the minimum skew between the CK signal and any DQS signal
when arriving at the same DIMM over all DIMMs.
Max CK/DQS skew to DIMM
ns
Sets the maximum skew between the CK signal and any DQS signal
when arriving at the same DIMM over all DIMMs.
Max skew between
DIMMs/devices
ns
Sets the largest skew or propagation delay on the DQ signals
between ranks, especially true for DIMMs in different slots.
Max skew within DQS groups
ns
Sets the largest skew between the DQ pins in a DQS group.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
DDR3 SDRAM High-Performance Controller Parameter Settings
3–13
Table 3–7. ALTMEMPHY Board Settings (Part 2 of 2)
Parameter Name
Units
Description
Max skew between DQS group
ns
Sets the largest skew between DQS signals in different DQS groups.
Addr/command to CK skew
ns
Sets the skew or propagation delay between the CK signal and the
address and command signals. The positive values represent the
address and command signals that are longer than the CK signals,
and the negative values represent the address and command signals
that are shorter than the CK signals.
Controller Interface Settings
The Controller Interface Settings tab allows you to specify the native interface or the
default Avalon-MM interface for your local interface as required by the
ALTMEMPHY megafunction for DDR or DDR2 SDRAM. The options are disabled
when you are creating an ALTMEMPHY megafunction for DDR3 SDRAM interface.
DDR3 SDRAM High-Performance Controller Parameter Settings
The DDR3 SDRAM High-Performance Controller Parameter Settings page in the
DDR3 SDRAM High-Performance Controller MegaWizard interface (Figure 3–3)
allows you to parameterize the following settings:
■
Memory Settings
■
PHY Settings
■
Board Settings
■
Controller Settings
The Memory Settings, PHY Settings, and Board Settings tabs provide the same
options as in the ALTMEMPHY Parameter Settings page.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–14
Chapter 3: Parameter Settings
DDR3 SDRAM High-Performance Controller Parameter Settings
Figure 3–3. DDR3 SDRAM High-Performance Controller Settings
Controller Settings
Table 3–8 shows the options provided on the Controller Settings tab.
Table 3–8. Controller Settings (Part 1 of 3)
Parameter
Controller architecture
Controller Architecture
—
Description
Specifies the controller architecture.
Enable self-refresh controls
Both
Turn on to enable the controller to allow you to have control on
when to place the external memory device in self-refresh mode,
refer to “User-Controlled Self-Refresh Logic” on page 7–7
(HPC II).
Enable power down controls
HPC
Turn on to enable the controller to allow you to have control on
when to place the external memory device in power-down mode.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 3: Parameter Settings
DDR3 SDRAM High-Performance Controller Parameter Settings
3–15
Table 3–8. Controller Settings (Part 2 of 3)
Parameter
Controller Architecture
Description
Enable auto power down
HPC II
Turn on to enable the controller to automatically place the
external memory device in power-down mode after a specified
number of idle controller clock cycles is observed in the
controller. You can specify the number of idle cycles after which
the controller powers down the memory in the Auto Power
Down Cycles field, refer to “Automatic Power-Down with
Programmable Time-Out” on page 7–7.
Auto power down cycles
HPC II
Determines the desired number of idle controller clock cycles
before the controller places the external memory device in a
power-down mode. The legal range is 1 to 65,535.
The auto power-down mode is disabled if you set the value to 0
clock cycles.
Enable user auto-refresh
controls
Both
Turn on to enable the controller to allow you to have control on
when to place the external memory device in refresh mode.
Enable auto-precharge
control
Both
Turn on if you need fast random access.
Local-to-memory address
mapping
HPC II
Allows you to control the mapping between the address bits on
the Avalon interface and the chip, row, bank, and column bits on
the memory interface.
If your application issues bursts that are greater than the
column size of the memory device, choose the
Chip-Row-Bank-Column option. This option allows the
controller to use its look-ahead bank management feature to
hide the effect of changing the currently open row when the
burst reaches the end of the column.
On the other hand, if your application has several masters that
each use separate areas of memory, choose the
Chip-Bank-Row-Column option. This option allows you to use
the top address bits to allocate a physical bank in the memory to
each master. The physical bank allocation avoids different
masters accessing the same bank which is likely to cause
inefficiency, as the controller must then open and close rows in
the same bank.
Command queue look-ahead
depth
HPC II
This option allows you to select a command queue look-ahead
depth value to control the number of read or writes requests the
look-ahead bank management logic examines, refer to
“Command Queue” on page 7–4.
Local maximum burst count
HPC II
Specifies a burst count to configure the maximum Avalon burst
count that the controller slave port accepts.
Enable configuration and
status register interface
HPC II
Turn on to enable run-time configuration and status retrieval of
the memory controller. Enabling this option adds an additional
Avalon-MM slave port to the memory controller top level that
allows run-time reconfiguration and status retrieving for
memory timing parameters, memory address size and mode
register settings, and controller features. If Error Detection and
Correction Logic option is enabled, the same slave port also
allows you to control and retrieve the status of this logic. Refer
to “Configuration and Status Register (CSR) Interface” on
page 7–7.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
3–16
Chapter 3: Parameter Settings
DDR3 SDRAM High-Performance Controller Parameter Settings
Table 3–8. Controller Settings (Part 3 of 3)
Parameter
Enable error detection and
correction logic
Controller Architecture
Description
Both
Turn on to enable error correction coding (ECC) for single-bit
error correction and double-bit error detection. Refer to “Error
Correction Coding (ECC)” on page 6–5 for HPC, and “Error
Correction Coding (ECC)” on page 7–7 for HPC II.
Enable auto error correction
HPC II
Turn on to allow the controller to perform auto correction when
the ECC logic detects a single-bit error. Alternatively, you can
turn off this option and schedule the error correction at a
desired time for better system efficiency. Refer to “Error
Correction Coding (ECC)” on page 7–7.
Enable multi-cast write
control
HPC II
Turn on to enable the multi-cast write control on the controller
top level. Asserting the multi-cast write control when requesting
a write burst causes the write data to be written to all the chip
selects in the memory system. Multi-cast write is not supported
for registered DIMM interfaces or if the ECC logic is enabled.
Multiple controller clock
sharing
Both
This option is only available in SOPC Builder Flow. Turn on to
allow one controller to use the Avalon clock from another
controller in the system that has a compatible PLL. This option
allows you to create SOPC Builder systems that have two or
more memory controllers that are synchronous to your master
logic.
Local interface protocol
HPC
Specifies the local side interface between the user logic and the
memory controller. The Avalon-MM interface allows you to
easily connect to other Avalon-MM peripherals.
The HPC II architecture supports only the Avalon-MM interface.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
4. Compile and Simulate
After setting the parameters for the MegaCore function, you can now integrate the
MegaCore function variation into your design, and compile and simulate your design.
The following sections detail the steps you need to perform to compile and simulate
your design:
■
Compile the Design
■
Simulate the Design
Compile the Design
Figure 4–1 shows the top-level view of the Altera high-performance controller design
as an example of how your final design looks after you integrate the controller and the
user logic.
Figure 4–1. High-Performance Controller System-Level Diagram
Example Top-Level File
ALTMEMPHY
External
Memory
Device
DLL
PLL
(1)
HighPerformance
Controller
Example
Driver
Pass or Fail
Note to Figure 4–1:
(1) When you choose Instantiate DLL Externally, DLL is instantiated outside the controller.
Before compiling a design with the ALTMEMPHY variation, you must edit some
project settings, include the .sdc file, and make I/O assignments. I/O assignments
include I/O standard, pin location, and other assignments, such as termination and
drive strength settings. Some of these tasks are listed at the ALTMEMPHY
Generation window. For most systems, Altera recommends that you use the
Advanced I/O Timing feature by using the Board Trace Model command in the
Quartus II software to set the termination and output pin loads for the device.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
4–2
Chapter 4: Compile and Simulate
Compile the Design
To compile the example top-level file in the Quartus II software and perform
post-compilation timing analysis, perform the following steps:
1. Set up the TimeQuest timing analyzer:
a. On the Assignments menu, click Timing Analysis Settings, select Use
TimeQuest Timing Analyzer during compilation, and click OK.
b. Add the Synopsys Design Constraints (.sdc) file,
<variation name>_phy_ddr_timing.sdc, to your project. On the Project menu,
click Add/Remove Files in Project and browse to select the file.
c. Add the .sdc file for the example top-level design,
<variation name>_example_top.sdc, to your project. This file is only required if
you are using the example as the top-level design.
2. You can either use the <variation_name>_pin_assignments.tcl or the
<variation_name>.ppf file to apply the I/O assignments generated by the
MegaWizard Plug-In Manager. Using the .ppf file and the Pin Planner gives you
the extra flexibility to add a prefix to your memory interface pin names. You can
edit the assignments either in the Assignment Editor or Pin Planner. Use one of the
following procedures to specify the I/O standard assignments for pins:
■
If you have a single SDRAM interface, and your top-level pins have default
naming shown in the example top-level file, run
<variation name>_pin_assignments.tcl.
or
■
If your design contains pin names that do not match the design, edit the
<variation name>_pin_assignments.tcl file before you run the script. To edit the .tcl
file, perform the following steps:
a. Open <variation name>_pin_assignments.tcl file.
b. Based on the flow you are using, set the sopc_mode value to Yes or No.
■
SOPC Builder System flow:
if {![info exists sopc_mode]} {set sopc_mode YES}
■
MegaWizard Plug-In Manager flow:
if {![info exists sopc_mode]} {set sopc_mode NO}
c. Type your preferred prefix in the pin_prefix variable. For example, to add
the prefix my_mem, do the following:
if {![info exists set_prefix}{set pin_prefix “my_mem_”}
After setting the prefix, the pin names are expanded as shown in the following:
■
SOPC Builder System flow:
my_mem_cs_n_from_the_<your instance name>
■
MegaWizard Plug-In Manager flow:
my_mem_cs_n[0]
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Compile the Design
4–3
1
If your top-level design does not use single bit bus notation for the
single-bit memory interface signals (for example, mem_dqs rather than
mem_dqs[0]), in the Tcl script you should change set single_bit
{[0]} to set single_bit {}.
or
■
Alternatively, to change the pin names that do not match the design, you can add a
prefix to your pin names by performing the following steps:
a. On the Assignments menu, click Pin Planner.
b. On the Edit menu, click Create/Import Megafunction.
c. Select Import an existing custom megafunction and navigate to
<variation name>.ppf.
d. Type the prefix you want to use in Instance name. For example, change
mem_addr to core1_mem_addr.
3. Set the top-level entity to the top-level design.
a. On the File menu, click Open.
b. Browse to your SOPC Builder system top-level design or <variation
name>_example_top if you are using MegaWizard Plug-In Manager, and click
Open.
c. On the Project menu, click Set as Top-Level Entity.
4. Assign the DQ and DQS pin locations.
a. You should assign pin locations to the pins in your design, so the Quartus II
software can perform fitting and timing analysis correctly.
b. Use either the Pin Planner or Assignment Editor to assign the clock source pin
manually. Also choose which DQS pin groups should be used by assigning
each DQS pin to the required pin. The Quartus II Fitter then automatically
places the respective DQ signals onto suitable DQ pins within each group.
1
To avoid no-fit errors when you compile your design, ensure that you place
the mem_clk pins to the same edge as the mem_dq and mem_dqs pins, and
set an appropriate I/O standard for the non-memory interfaces, such as the
clock source and the reset inputs, when assigning pins in your design. For
example, for DDR3 SDRAM select 1.5 V. Also select in which bank or side
of the device you want the Quartus II software to place them.
The ×4 DIMM has the following mapping between DQS and DQ pins:
■
DQS[0] maps to DQ[3:0]
■
DQS[9] maps to DQ[7:4]
■
DQS[1] maps to DQ[11:8]
■
DQS[10] maps to DQ[15:12]
The DQS pin index in other ×4 DIMM configurations typically increases
sequentially with the DQ pin index (DQS[0]: DQ[3:0]; DQS[1]: DQ[7:4]; DQS[2]:
DQ[11:8])
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
4–4
Chapter 4: Compile and Simulate
Simulate the Design
5. For Stratix III and Stratix IV designs, if you are using advanced I/O timing, specify
board trace models in the Device & Pin Options dialog box. If you are using any
other device and not using advanced I/O timing, specify the output pin loading
for all memory interface pins.
6. Select your required I/O driver strength (derived from your board simulation) to
ensure that you correctly drive each signal or ODT setting and do not suffer from
overshoot or undershoot.
7. To compile the design, on the Processing menu, click Start Compilation.
After you have compiled the example top-level file, you can perform RTL simulation
or program your targeted Altera device to verify the example top-level file in
hardware.
Simulate the Design
During system generation, SOPC Builder optionally generates a simulation model
and testbench for the entire system, which you can use to easily simulate your system
in any of Altera's supported simulation tools. The MegaWizard also generates a set of
ModelSim® Tcl scripts and macros that you can use to compile the testbench, IP
functional simulation models, and plain-text RTL design files that describe your
system in the ModelSim simulation software (refer to “Generated Files” on page 2–6).
f
For more information about simulating SOPC Builder systems, refer to volume 4 of
the Quartus II Handbook and AN 351: Simulating Nios II Embedded Processor Designs. For
more information about simulation, refer to the Simulation section in volume 4 of the
External Memory Interface Handbook. For more information about how to include your
board simulation results in the Quartus II software and how to assign pins using pin
planners, refer to DDR, DDR2, and DDR3 Design Tutorials section in volume 6 of the
External Memory Interface Handbook.
In ALTMEMPHY variations for DDR3 SDRAM with leveling and without
leveling interfaces, you have the following three simulation options:
■
Skip calibration—Performs a static setup of the ALTMEMPHY megafunction to
skip calibration and go straight into user mode.
Available for ×4 and ×8 DDR3 SDRAM. Skip calibration simulation is supported
for 300 MHz through 533 MHz. There is no calibration in this simulation mode. As
no phase calibration is performed, there must be no delays in the testbench.
The ALTMEMPHY megafunction is statically configured to provide the correct
write and read latencies. Skip calibration provides the fastest simulation time for
DDR3 SDRAM interfaces. Use the generated or vendor DDR3 SDRAM simulation
models for this simulation option.
Skip calibration simulation between 300 MHz and 400 MHz supports CAS latency
of 6 and a CAS write latency of 5. Skip calibration simulation between 400 MHz
and 533 MHz supports CAS latency of 7 and a CAS write latency of 6.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
■
4–5
Quick calibration—Performs a calibration on a single pin and chip select.
Available for ×4 and ×8 DDR3 SDRAM. In quick calibration simulation mode, the
sequencer only does clock cycle calibration. So there must be no delays (DDR3
DIMM modeling for example) in the testbench, because no phase calibration is
performed. Quick calibration mode can be used between 300 MHz and 533 MHz.
Both the generated or vendor DDR3 SDRAM simulation models support burst
length on-the-fly changes during the calibration sequence.
■
Full calibration—Across all pins and chip selects. This option allows for longer
simulation time.
Available for ×4 and ×8 DDR3 SDRAM between 300 MHz and 533 MHz. You
cannot use the wizard-generated memory model, if you select Full Calibration.
You must use a memory-vendor provided memory model that supports write
leveling calibration.
Simulating Using NativeLink
To set up simulation in the Quartus II software using NativeLink for the DDR3
high-performance controllers (HPC and HPC II), perform the following steps:
1. Create a custom variation with an IP functional simulation model, refer to step 4 in
the “Specify Parameters” section on page 2–4.
2. Set the top-level entity to the example project.
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
3. Set up the Quartus II NativeLink.
a. On the Assignments menu, click Settings. In the Category list, expand EDA
Tool Settings and click Simulation.
b. From the Tool name list, click on your preferred simulator.
1
Check that the absolute path to your third-party simulator executable is set.
On the Tools menu, click Options and select EDA Tools Options.
c. In NativeLink settings, select Compile test bench and click Test Benches.
d. Click New at the Test Benches to create a testbench.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
4–6
Chapter 4: Compile and Simulate
Simulate the Design
4. In the New Test Bench Settings dialog box, do the following:
a. Enter a name for the Test bench name.
b. In Top level module in test bench, enter the name of the automatically
generated testbench, <variation name>_example_top_tb.
c. In Design instance in test bench, enter the name of the top-level instance, dut.
d. Under Simulation period, set End simulation at to 600 µs.
e. Add the testbench files and automatically-generated memory model files. In
the File name field, browse to the location of the memory model and the
testbench, click Open and then click Add. The testbench is
<variation name>_example_top_tb.v; memory model is
<variation name>_mem_model.v.
f
The auto generated generic SDRAM model may be used as a placeholder
for a specific memory vendor supplied model.
f. Select the files and click OK.
5. On the Processing menu, point to Start and click Start Analysis & Elaboration to
start analysis.
6. On the Tools menu, point to Run EDA Simulation Tool and click EDA RTL
Simulation.
1
f
Ensure that the Quartus II EDA Tool Options are configured correctly for
your simulation environment. On the Tools menu, click Options. In the
Category list, click EDA Tool Options and verify the locations of the
executable files.
If your Quartus II project appears to be configured correctly but the example
testbench still fails, check the known issues on the Knowledge Database before filing a
service request.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
4–7
IP Functional Simulations
For VHDL simulations with IP functional simulation models, perform the following
steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool from this directory and create the following libraries:
■
altera_mf
■
lpm
■
sgate
■
<device name>
■
altera
■
ALTGXB
■
<device name>_hssi
■
auk_ddr3_hp_user_lib
3. Compile the files into the appropriate library (AFI mode) as shown in Table 4–1.
The files are in VHDL93 format.
Table 4–1. Files to Compile—VHDL IP Functional Simulation Models (Part 1 of 2)
Library
File Name
altera_mf
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf_components.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.vhd
lpm
/eda/sim_lib/220pack.vhd
/eda/sim_lib/220model.vhd
sgate
eda/sim_lib/sgate_pack.vhd
eda/sim_lib/sgate.vhd
<device name>
eda/sim_lib/<device name>_atoms.vhd
eda/sim_lib/<device name>_ components.vhd
eda/sim_lib/<device name>_hssi_atoms.vhd (1)
altera
eda/sim_lib/altera_primitives_components.vhd
eda/sim_lib/altera_primitives.vhd
ALTGXB (1)
<device name>_mf.vhd
<device name>_mf_components.vhd
<device name>_hssi (1)
<device name>_hssi_components.vhd
<device name>_hssi_atoms.vhd
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
4–8
Chapter 4: Compile and Simulate
Simulate the Design
Table 4–1. Files to Compile—VHDL IP Functional Simulation Models (Part 2 of 2)
Library
File Name
auk_ddr3_hp_user_lib
<QUARTUS ROOTDIR>/
libraries/vhdl/altera/altera_europa_support_lib.vhd
<project directory>/<variation name>_phy_alt_mem_phy_delay.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vho
<project directory>/<variation name>_phy.vho
<project directory>/<variation name>.vhd
<project directory>/<variation name>_example_top.vhd
<project directory>/<variation name>_controller_phy.vhd
<project directory>/<variation name>_phy_alt_mem_phy_pll.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq.vhd
<project directory>/<variation name>_example_driver.vhd
<project directory>/<variation name>_ex_lfsr8.vhd
testbench/<variation name>_example_top_tb.vhd
testbench/<variation name>_mem_model.vhd
<project directory>/<variation name>_auk_ddr3_hp_controller_wrapper.vho (HPC)
<project directory>/<variation name>_alt_ddrx_controller_wrapper.vho (HPC II)
Note to Table 4–1:
(1) Applicable only for Stratix IV devices.
1
If you are targeting Stratix IV devices, you need both the Stratix IV and
Stratix III files (stratixiv_atoms and stratixiii_atoms) to simulate in your
simulator, unless you are using NativeLink.
4. Load the testbench in your simulator with the timestep set to picoseconds.
For Verilog HDL simulations with IP functional simulation models, perform the
following steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool from this directory and create the following libraries:
■
altera_mf_ver
■
lpm_ver
■
sgate_ver
■
<device name>_ver
■
altera_ver
■
ALTGXB_ver
■
<device name>_hssi_ver
■
auk_ddr3_hp_user_lib
3. Compile the files into the appropriate library (AFI mode) as shown in Table 4–2 on
page 4–9.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 4: Compile and Simulate
Simulate the Design
4–9
Table 4–2. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 1 of 2)
Library
File Name
altera_mf_ver
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v
lpm_ver
/eda/sim_lib/220model.v
sgate_ver
eda/sim_lib/sgate.v
<device name>_ver
eda/sim_lib/<device name>_atoms.v
eda/sim_lib/<device name>_hssi_atoms.v (1)
altera_ver
eda/sim_lib/altera_primitives.v
ALTGXB_ver (1)
<device name>_mf.v
<device name>_hssi_ver (1)
<device name>_hssi_atoms.v
auk_ddr3_hp_user_lib
alt_mem_phy_defines.v
<project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vo
<project directory>/<variation name>.v
<project directory>/<variation name>_example_top.v
<project directory>/<variation name>_phy.v
<project directory>/<variation name>_controller_phy.v
<project directory>/<variation name>_phy_alt_mem_phy_pll.v
<project directory>/<variation name>_phy_alt_mem_phy.v
<project directory>/<variation name>_example_driver.v
<project directory>/<variation name>_ex_lfsr8.v
testbench/<variation name>_example_top_tb.v
testbench/<variation name>_mem_model.v
<project directory>/<variation name>_auk_ddr3_hp_controller_wrapper.vo (HPC)
<project directory>/<variation name>_alt_ddrx_controller_wrapper.v (HPC II)
<project directory>/alt_ddrx_addr_cmd.v (HPC II)
<project directory>/alt_ddrx_afi_block.v (HPC II)
<project directory>/alt_ddrx_bank_tracking.v (HPC II)
<project directory>/alt_ddrx_clock_and_reset.v (HPC II)
<project directory>/alt_ddrx_cmd_queue.v (HPC II)
<project directory>/alt_ddrx_controller.v (HPC II)
<project directory>/alt_ddrx_csr.v (HPC II)
<project directory>/alt_ddrx_ddr3_odt_gen.v (HPC II)
<project directory>/alt_ddrx_avalon_if.v (HPC II)
<project directory>/alt_ddrx_decoder_40.v (HPC II)
<project directory>/alt_ddrx_decoder_72.v (HPC II)
<project directory>/alt_ddrx_decoder.v (HPC II)
<project directory>/alt_ddrx_encoder_40.v (HPC II)
<project directory>/alt_ddrx_encoder_72.v (HPC II)
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
4–10
Chapter 4: Compile and Simulate
Simulate the Design
Table 4–2. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 2 of 2)
Library
File Name
<project directory>/alt_ddrx_encoder.v (HPC II)
<project directory>/alt_ddrx_input_if.v (HPC II)
<project directory>/alt_ddrx_odt_gen.v (HPC II)
<project directory>/alt_ddrx_state_machine.v (HPC II)
<project directory>/alt_ddrx_timers_fsm.v (HPC II)
<project directory>/alt_ddrx_timers.v (HPC II)
<project directory>/alt_ddrx_wdata_fifo.v (HPC II)
<project directory>/alt_avalon_half_rate_bridge.v (HPC II)
Note to Table 4–2:
(1) Applicable only for Stratix IV devices.
1
If you are targeting Stratix IV devices, you need both the Stratix IV and
Stratix III files (stratixiv_atoms and stratixiii_atoms) to simulate in your
simulator, unless you are using NativeLink.
Configure your simulator to use transport delays, a timestep of picoseconds, and to
include all the libraries in Table 4–2.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
5. Functional Description—ALTMEMPHY
The ALTMEMPHY megafunction creates the datapath between the memory device
and the memory controller, and user logic in various Altera devices. The
ALTMEMPHY megafunction GUI helps you configure multiple variations of a
memory interface. You can then connect the ALTMEMPHY megafunction variation
with either a user-designed controller or with an Altera high-performance controller.
In addition, the ALTMEMPHY megafunction and the Altera high-performance
controllers are available for half-rate DDR3 SDRAM interfaces.
1
If the ALTMEMPHY megafunction does not meet your requirements, you can also
create your own memory interface datapath using the ALTDLL and ALTDQ_DQS
megafunctions, available in the Quartus II software. However, you are then
responsible for every aspect of the interface, including timing analysis and
debugging.
This chapter describes the DDR3 SDRAM ALTMEMPHY megafunction, which uses
AFI as the interface between the PHY and the controller.
Block Description
Figure 5–1 on page 5–2 shows the major blocks of the ALTMEMPHY megafunction
and how it interfaces with the external memory device and the controller. The
ALTPLL megafunction is instantiated inside the ALTMEMPHY megafunction, so that
you do not need to generate the clock to any of the ALTMEMPHY blocks.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
5–2
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–1. Major Blocks of the ALTMEMPHY Megafunction Interfacing with the Controller and the
External Memory
FPGA
ALTMEMPHY
Write
Datapath
Address
and
Command
Datapath
External
Memory
Device
Memory
Controller
User
Logic
Clock
and Reset
Management
DLL
PLL
Read
Datapath
Sequencer
The ALTMEMPHY megafunction comprises the following blocks:
■
Write datapath
■
Address and command datapath
■
Clock and reset management, including DLL and PLL
■
Sequencer for calibration
■
Read datapath
The major advantage of the ALTMEMPHY megafunction is that it supports an initial
calibration sequence to remove process variations in both the Altera device and the
memory device. In Arria series and Stratix series devices, the DDR3 SDRAM
ALTMEMPHY calibration process centers the resynchronization clock phase into the
middle of the captured data valid window to maximize the resynchronization setup
and hold margin. During the user operation, the VT tracking mechanism eliminates
the effects of VT variations on resynchronization timing margin.
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
5–3
Calibration
This section describes the calibration that the sequencer performs, to find the optimal
clock phase for the memory interface. The calibration sequence is similar across
families, but different depending on the following target memory interface:
■
DDR3 SDRAM (without leveling)
■
DDR3 SDRAM (with leveling)
DDR3 SDRAM (without leveling)
The calibration process for the DDR3 SDRAM without leveling PHY includes the
following steps:
f
© February 2010
■
“Step 1: Memory Device Initialization”
■
“Step 2: Write Training Patterns”
■
“Step 3: Read Resynchronization (Capture) Clock Phase”
■
“Step 4: Read and Write Datapath Timing”
■
“Step 5: Address and Command Clock Cycle”
■
“Step 6: Postamble”
■
“Step 7: Prepare for User Mode”
For detailed information on each calibration step, refer to the Debugging section in
volume 4 of the External Memory Interface Handbook.
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
5–4
Chapter 5: Functional Description—ALTMEMPHY
Block Description
Figure 5–2 shows the calibration flow.
Figure 5–2. Calibration Flow—Without Leveling
Memory Device
and PHY Initialization
Write Training
Patterns
Read Resynchronization
Clock Phase
Read and Write
Datapath Timing
Address and Command
Clock Cycle
Postamble
Prepare for User Mode
VT Tracking
User Mode
Step 1: Memory Device Initialization
This step initializes the memory device according to the DDR3 SDRAM specification.
The initialization procedure includes resetting the memory device, specifying the
mode registers and memory device ODT setting, and initializing the memory device
DLL. Calibration requires overriding some of the user-specified mode register
settings, which are reverted in “Step 7: Prepare for User Mode”.
Step 2: Write Training Patterns
In this step, a pattern is written to the memory to be read in later calibration stages.
The matched trace lengths to DDR3 SDRAM devices mean that after memory
initialization, write capture works. The pattern is 0x30F5 and comprises the
following separately written patterns:
■
All 0: ‘b0000 - DDIO high and low bits held at 0
■
All 1: ‘b1111 - DDIO high and low bits held at 1
■
Toggle: ‘b0101 - DDIO high bits held at 0 and DDIO low bits held at 1
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
© February 2010 Altera Corporation
Chapter 5: Functional Description—ALTMEMPHY
Block Description
■
5–5
Mixed: ‘b0011 - DDIO high and low bits have to toggle
Loading a mixed pattern is complex, because write latency is unknown at this time.
Two sets of write and read operations (single pin resynchronization (capture) clock
phase sweeps, (“Step 3: Read Resynchronization (Capture) Clock Phase”) are required
to accurately write the mixed pattern to memory.
1
Memory bank 0, row 0, and column addresses 0 to 55 store calibration data.
Step 3: Read Resynchronization (Capture) Clock Phase
This step adjusts the phase of the resynchronization clock to determine the optimal
phase that gives the greatest margin. The resynchronization clock captures the
outputs of DQS capture registers (DQS is the capture clock).
To correctly calibrate resynchronization clock phase, based on a data valid window,
requires 720° of phase sweep.
Step 4: Read and Write Datapath Timing
In this step, the sequencer calculates the calibrated write latency (the ctl_wlat
signal) between write commands and write data. The sequencer also calculates the
calibrated read latency (the ctl_rlat signal) between the issue of a read command
and valid read data. Both read and write latencies are output to a controller. In
addition to advertising the read latency, the sequencer calibrates a read data valid
signal to the delay between a controller issuing a read command and read data
returning. The controller can use the read data valid signal in place of the advertised
read latency, to determine when the read data is valid.
Step 5: Address and Command Clock Cycle
This step optionally adds an additional memory clock cycle of delay from the address
and command path. This delay aligns the write data to the memory commands given
in the controller clock domain. If you require this delay, this step reruns the calibration
(“Step 2: Write Training Patterns” to “Step 4: Read and Write Datapath Timing”) to
calibrate to the new setting.
Step 6: Postamble
This step sets the correct clock cycle for the postamble path. The aim of the postamble
path is to eliminate false DQ data capture because of postamble glitches on the DQS
signal, through an override on DQS. This step ensures the correct clock cycle timing of
the postamble enable (override) signal.
Step 7: Prepare for User Mode
In this step, the PHY applies user mode register settings and performs periodic VT
tracking.
VT Tracking
VT tracking is a background process that tracks the voltage and temperature
variations to maintain the relationship between the resynchronization or capture
clock and the data valid window that are achieved at calibration.
When the data calibration phase is completed, the sequencer issues the mimic
calibration sequence every 128 ms.
© February 2010
Altera Corporation
DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide
5–6
Chapter 5: Functional Description—ALTMEMPHY
Block Description
During initial calibration, the mimic path is sampled using the measure clock
(measure_clk has a _1x or _2x suffix, depending whether the ALTMEMPHY is a
full-rate or half-rate design). The sampled value is then stored by the sequencer. After
a sample value is stored, the sequencer uses the PLL reconfiguration logic to change
the phase of the measure clock by one VCO phase tap. The control sequencer then
stores the sampled value for the new mimic path clock phase. This sequence
continues until all mimic path clock phase steps are swept. After the control
sequencer stores all the mimic path sample values, it calculates the phase which
corresponds to the center of the high period of the mimic path waveform. This
reference mimic path sampling phase is used during the VT tracking phase.
In user mode, the sequencer periodically performs a tracking operation as defined in
the tracking calibration description. At the end of the tracking calibration operation,
the sequencer compares the most recent optimum tracking phase against the reference
sampling phase. If the sampling phases do not match, the mimic path delays have
changed due to voltage and temperature variations.
When the sequencer detects that the mimic path reference and most recent sampling
phases do not match, the sequencer uses the PLL reconfiguration logic to change the
phase of the resynchronization clock by the VCO taps in the same direction. This
allows the tracking process to maintain the near-optimum capture clock phase setup
during data tracking calibration as voltage and temperature vary over time.
The relationship between the resynchronization or capture clock and the data valid
window is maintained by measuring the mimic path variations due to the VT
variations and applying the same v