2048mb ddr3 – sdram dimm
Data Sheet
Rev.1.1
12.11.2010
2048MB DDR3 – SDRAM DIMM
240 Pin UDIMM
Features:
SGU02G64B1BF2SA-CCR

2GB PC3-10600 in FBGA Technology
RoHS compliant
Options:

Data Rate / Latency
DDR3 1333 MT/s CL9
DDR3 1066 MT/s CL7
Marking
-CC
-BB

Module Density
2048MB with 16 dies and 2 ranks

Standard Grade
(TA)
(Tc)
0°C to 70°C
0°C to 85°C












Environmental Requirements:

Operating temperature (ambient)
Standard Grade
0°C to 70°C

Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C







240-pin 64-bit DDR3 Dual-In-Line Double Data Rate
Synchronous DRAM module for industrial applications
Module organization: dual rank 256M x 64
VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
1.5V I/O ( SSTL_15 compatible)
serial presence-detect (SPD) EEPROM
Gold-contact pads
This module is fully pin and functional compatible to the
JEDEC PC3-10600 spec. and JEDEC- Standard MO-269.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
DDR3 - SDRAM component Samsung K4B1G0846F
128Mx8 DDR3 SDRAM in PG-TFBGA-78 package
8-bit pre-fetch architecture
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
ZQ Calibration for output driver and ODT.
System Level Timing Calibration Support via Write Leveling
and Multi Purpose Register (MPR) Read Pattern.
Figure: mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 1
of 14
Data Sheet
Rev.1.1
12.11.2010
This Swissbit module is an industry standard 240-pin 8-byte DDR3 SDRAM Dual-In-line Memory Module
(UDIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally configured
octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed
operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses
to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several
timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR3 SDRAMs used
Row
Addr.
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
256M x 64bit
16 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
10
8k
S0#, S1#
Module Dimensions
in mm
133.35 (long) x 30(high) x 4.00 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SGU02G64B1BF2SA-BBR
2048 MB
8.5 GB/s
1.87ns/1066MT/s
7-7-7
SGU02G64B1BF2SA-CCR
2048 MB
10.6 GB/s
1.5ns/1333MT/s
9-9-9
Pin Name
A0-9, A11 – A13
Address Inputs
A10/AP
Address Input / Autoprecharge Bit
BA0 – BA2
Bank Address Inputs
DQ0 – DQ63
Data Input / Output
DM0-DM7
Input Data Mask
DQS0 – DQS7#
Data Strobe, positive line
DQS0# - DQS7#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
S0#, S1#
Chip Select
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
CKE0 – CKE1
Clock Enable
ODT0, ODT1
On-Die Termination
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Page 2
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Data Sheet
Rev.1.1
12.11.2010
CK0 – CK1
Clock inputs, positive line
CK0# - CK1#
Clock inputs, negative line
VDD
Supply Voltage (1.5V± 0.075V)
VREFDQ
Reference voltage: DQ, DM (VDD/2)
VREFCA
Reference voltage: Control, command, and address (VDD/2)
VSS
Ground
VTT
Termination voltage: Used for control, command, and address (VDD/2).
VDDSPD
Serial EEPROM Positive Power Supply
SCL
Serial Clock for Presence Detect
SDA
Serial Data Out for Presence Detect
SA0 – SA2
Presence Detect Address Inputs
Event#
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
NC
No Connection
Pin Configuration
Frontside
PIN
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
Pin 15
Pin 16
Pin 17
Pin 18
Pin 19
Pin 20
Pin 21
Pin 22
Pin 23
Pin 24
Pin 25
Pin 26
Symbol
VREFDQ
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
PIN
Pin 27
Pin 28
Pin 29
Pin 30
Pin 31
Pin 32
Pin 33
Pin 34
Pin 35
Pin 36
Pin 37
Pin 38
Pin 39
Pin 40
Pin 41
Pin 42
Pin 43
Pin 44
Pin 45
Pin 46
Pin 47
Pin 48
Symbol
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
NC(CB0)
NC(CB1)
VSS
NC(DQS8#)
NC(DQS8)
VSS
NC(CB2)
NC(CB3)
VSS
NC(VTT)
PIN
Symbol
PIN
Pin 49
NC(VTT)
Pin 75
Pin 50
CKE0
Pin 76
Pin 51
VDD
Pin 77
Pin 52
BA2
Pin 78
Pin 53 NC(Err_Out#) Pin 79
Pin 54
VDD
Pin 80
Pin 55
A11
Pin 81
Pin 56
A7
Pin 82
Pin 57
VDD
Pin 83
Pin 58
A5
Pin 84
Pin 59
A4
Pin 85
Pin 60
VDD
Pin 86
Pin 61
A2
Pin 87
Pin 62
VDD
Pin 88
Pin 63
CK1
Pin 89
Pin 64
CK1#
Pin 90
Pin 65
VDD
Pin 91
Pin 66
VDD
Pin 92
Pin 67
VREFCA
Pin 93
Pin 68
NC(Par_In)
Pin 94
Pin 69
VDD
Pin 95
Pin 70
A10/ AP
Pin 96
Pin 71
BA0
Pin 97
Pin 72
VDD
Pin 98
Pin 73
WE#
Pin 99
Pin 74
CAS#
Pin 100
Symbol
VDD
S1#
ODT1
VDD
NC(S2#)
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
PIN
Pin 101
Pin 102
Pin 103
Pin 104
Pin 105
Pin 106
Pin 107
Pin 108
Pin 109
Pin 110
Pin 111
Pin 112
Pin 113
Pin 114
Pin 115
Pin 116
Pin 117
Pin 118
Pin 119
Pin 120
Symbol
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 3
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Data Sheet
Rev.1.1
12.11.2010
Backside
Pin
Pin 121
Pin 122
Pin 123
Pin 124
Pin 125
Pin 126
Pin 127
Pin 128
Pin 129
Pin 130
Pin 131
Pin 132
Pin 133
Pin 134
Pin 135
Pin 136
Pin 137
Pin 138
Pin 139
Pin 140
Pin 141
Pin 142
Pin 143
Pin 144
Pin 145
Pin 146
Symbol
VSS
DQ4
DQ5
VSS
DM0(DQS9)
NC(DQS9#)
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1(DQS10)
NC(DQS10#)
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2(DQS11)
NC(DQS11#)
VSS
DQ22
Pin
Pin 147
Pin 148
Pin 149
Pin 150
Pin 151
Pin 152
Pin 153
Pin 154
Pin 155
Pin 156
Pin 157
Pin 158
Pin 159
Pin 160
Pin 161
Pin 162
Pin 163
Pin 164
Pin 165
Pin 166
Pin 167
Pin 168
Symbol
DQ23
VSS
DQ28
DQ29
VSS
DM3(DQS12)
NC(DQS12#)
VSS
DQ30
DQ31
VSS
NC(CB4)
NC(CB5)
VSS
DM8(DQS17)
NC(DQS17#)
VSS
NC(CB6)
NC(CB7)
VSS
NC(TEST)
RESET#
Pin
Pin 169
Pin 170
Pin 171
Pin 172
Pin 173
Pin 174
Pin 175
Pin 176
Pin 177
Pin 178
Pin 179
Pin 180
Pin 181
Pin 182
Pin 183
Pin 184
Pin 185
Pin 186
Pin 187
Pin 188
Pin 189
Pin 190
Pin 191
Pin 192
Pin 193
Pin 194
Symbol
CKE1
VDD
NC(A15)
NC(A14)
VDD
A12, BC#
A9
VDD
A8
A6
VDD
A3
A1
VDD
VDD
CK0
CK0#
VDD
EVENT#
A0
VDD
BA1
VDD
RAS#
S0#
VDD
Pin
Pin 195
Pin 196
Pin 197
Pin 198
Pin 199
Pin 200
Pin 201
Pin 202
Pin 203
Pin 204
Pin 205
Pin 206
Pin 207
Pin 208
Pin 209
Pin 210
Pin 211
Pin 212
Pin 213
Pin 214
Pin 215
Pin 216
Pin 217
Pin 218
Pin 219
Pin 220
Symbol
ODT0
A13
VDD
NC(S3#)
VSS
DQ36
DQ37
VSS
DM4(DQS13)
NC(DQS13#)
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5(DQS14)
NC(DQS14#)
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
Pin
Symbol
Pin 221 DM6(DQS15)
Pin 222 NC(DQS15#)
Pin 223
VSS
Pin 224
DQ54
Pin 225
DQ55
Pin 226
VSS
Pin 227
DQ60
Pin 228
DQ61
Pin 229
VSS
Pin 230 DM7(DQS16)
Pin 231 NC(DQS16#)
Pin 232
VSS
Pin 233
DQ62
Pin 234
DQ63
Pin 235
VSS
Pin 236
VDDSPD
Pin 237
SA1
Pin 238
SDA
Pin 239
VSS
Pin 240
VTT
Signals in brackets (…) may be connected at the DIMM socket, but are not used on the DIMM
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 4
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Data Sheet
Rev.1.1
12.11.2010
FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR3 SDRAM DIMM,
2 RANKS AND 16 COMPONENTS
S1
S0
DQS4
DQS4
DM4
DQS0
DQS0
DM0
DM
DQ0
DQ1
DQ2
I/O 0
I/O 1
I/O 2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
CS
I/O 0
I/O 1
I/O 2
D0
ZQ
DQ32
DQ33
DQ34
I/O 0
I/O 1
I/O 2
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D4
ZQ
CS
DQS DQS
D12
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS5
DQS5
DM5
DQS1
DQS1
DM1
DM
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
CS
I/O 0
I/O 1
I/O 2
D1
D9
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
DQS DQS
ZQ
CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D5
ZQ
CS
DQS DQS
D13
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS6
DQS6
DM6
DQS2
DQS2
DM2
DM
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D2
CS
D10
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
DQS DQS
ZQ
CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D6
ZQ
CS
DQS DQS
D14
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS7
DQS7
DM7
DQS3
DQS3
DM3
DM
I/O 0
I/O 1
I/O 2
DQ24
DQ25
DQ26
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ27
DQ28
DQ29
DQ30
DQ31
BA0-BA2
A0-A13
RAS
CAS
WE
ODT0
ODT1
CKE0
CKE1
CK0,CK1
CK0,CK1
RESET
DM
D8
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQS DQS
CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D3
ZQ
DM
DQS DQS
D11
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
BA0-BA2: SDRAM D0-D15
A0-A13: SDRAM D0-D15
RAS: SDRAM D0-D15
CAS: SDRAM D0-D15
WE: SDRAM D0-D15
ODT: SDRAM D0-D7
ODT: SDRAM D8-D15
CKE: SDRAM D0-D7
CKE: SDRAM D8-D15
CK: SDRAM D0-D15
CK: SDRAM D0-D15
RESET: SDRAM D0-D15
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
CS
ZQ
VDDSPD
VDD/VDDQ
SPD
D0-D15
VREFDQ
D0-D15
VREFCA
D0-D15
VSS
D0-D15
Fon: +41 (0) 71 913 03 03
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CS
DM
DQS DQS
I/O 0
I/O 1
I/O 2
D7
ZQ
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D15
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
6. Refer to associated figure for SPD details.
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Page 5
of 14
Data Sheet
Rev.1.1
12.11.2010
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
SYMBOL
VDD
VDDQ
VDDL
Vin, Vout
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
MIN
-0.4
-0.4
-0.4
-0.4
MAX
1.975
1.975
1.975
1.975
II
UNITS
V
V
V
V
µA
Command/Address
-16
16
IOZ
-16
-2
-5
16
2
5
µA
IVREF
-8
8
µA
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
MIN
VDD
1.425
VDDQ
1.425
VDDL
1.425
VREF
0.49 x VDDQ
VTT
0.49 x VDDQ-20mV
VIH (DC)
VREF + 0.1
VIL (DC)
-0.3
NOM
1.5
1.5
1.5
0.50 x VDDQ
0.50 x VDDQ
MAX
1.575
1.575
1.575
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
VREF – 0.1
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.175
-
MAX
VREF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 6
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Data Sheet
Rev.1.1
12.11.2010
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
Parameter
& Test Condition
Symbol
OPERATING CURRENT *) :
One device bank Active-Precharge;
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
Fast Exit
PRECHARGE POWER-DOWN
CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit
Address bus inputs are not changing; DQ’s
are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit AG
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CH-9552 Bronschhofen
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Fax: +41 (0) 71 913 03 15
max.
Unit
10600-999
8500-777
IDD0
480
440
mA
IDD1
560
520
mA
IDD2P
320
320
mA
160
160
IDD2Q
400
400
mA
IDD2N
400
400
mA
IDD3P
400
400
mA
IDD3N
800
720
mA
IDD4R
880
760
mA
www.swissbit.com
eMail: [email protected]
Page 7
of 14
Data Sheet
Parameter
& Test Condition
Rev.1.1
Symbol
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
max.
12.11.2010
Unit
10600-999
8500-777
IDD4W
920
800
mA
IDD5
1840
1840
mA
IDD6
160
160
mA
IDD7
1480
1240
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
10600-999
8500-777
9
7
CL (IDD)
13.5
13.125
tRCD (IDD)
49.5
50.625
tRC (IDD)
6
7.5
tRRD (IDD)
1.5
1,87
tCK (IDD)
36
37.5
tRAS MIN (IDD)
70,200
70,200
tRAS MAX (IDD)
13.5
13.125
tRP (IDD)
110
110
tRFC (IDD)
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
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Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 8
of 14
Data Sheet
Rev.1.1
12.11.2010
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
CK high-level width
CK low-level width
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS
SYMBOL
tCK (10)
tCK (9)
tCK (8)
tCK (7)
tCK (6)
tCK (5)
tCH
tCL
tHZ
tLZ
10600-999
MIN
MAX
1.5
<1.875
1.5
<1.875
1.875
<2.5
1.875
<2.5
2.5
3.3
8500-777
Min
MAX
1.875
<2.5
2.5
3.3
0.47
0.47
0.53
0.53
0.25
0.47
0.47
0.53
0.53
0.3
Unit
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
-0.5
0.25
-0.6
0.3
ns
tDS(Base)
30
25
ps
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS VREF=1V/ns
tDH(Base)
65
100
ps
tDS1V
180
200
ps
DQ and DM input hold time
relative to DQS VREF=1V/ns
DQ and DM input pulse width
( for each input )
DQS, DQS# to DQ skew, per
access
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
CK#
DQS, DQS# rising to/from CK,
CK# when DLL disabled
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
Address and control input pulse
width ( for each input )
CTRL, CMD, Addr setup to CK,
CK#
CTRL, CMD, Addr setup to CK,
CK#
VREF @ 1V/ns
tDH1V
165
200
ps
tDIPW
0.4
0.49
ns
1
2
125
tDQSQ
0.38
tQH
150
0.38
ps
tCK
(AVG)
tDQSH
tDQSL
tDQSCK
0.45
0.45
-255
0.55
0.55
+255
0.45
0.45
-300
0.55
0.55
300
tCK
tCK
ps
tDQSCK
1
10
1
10
ns
DLL_DIS
tDSS
0.2
0.2
tCK
tDSH
0.2
0.2
tCK
tRPRE
tRPST
tWPRE
tWPST
tDQSS
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
tCK
tCK
tCK
tCK
tCK
tIPW
620
780
ps
tIS(Base)
65
125
ps
tIS(1V)
240
300
ps
The maximum preamble is bound by tLZDQS (MAX)
The maximum postamble is bound by tHZDQS (MAX)
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 9
of 14
Data Sheet
Rev.1.1
12.11.2010
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
CTRL, CMD, Addr hold to CK,
tIH(Base)
CK#
CTRL, CMD, Addr hold to CK,
tIH(1V)
CK#
VREF @ 1V/ns
CAS# to CAS# command delay
tCCD
ACTIVE to ACTIVE (same bank)
tRC
command period
ACTIVE bank a to ACTIVE bank
tRRD
b command
ACTIVE to READ or WRITE
tRCD
delay
Four bank
1K Page size
tFAW
Activate period
2K Page size
ACTIVE to PRECHARGE
tRAS
command
Internal READ to precharge
tRTP
command delay
Write recovery time
tWR
Auto precharge write recovery +
tDAL
precharge time
Internal WRITE to READ
tWTR
command delay
PRECHARGE command period
tRP
LOAD MODE command cycle
tMRD
time
REFRESH to ACTIVE or
REFRESH to REFRESH
tRFC
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
RTT turn-on from ODTL on
reference
RTT turn-on from ODTL off
reference
Asynchronous RTT turn-on
delay (power Down with DLL off)
Asynchronous RTT turn-off
delay (power Down with DLL off)
RTT dynamic change skew
Exit self refresh to commands
not requiring a locked DLL
Write levelling setup from rising
CK, CK# crossing to rising DQS,
DQS# crossing
Write levelling setup from rising
DQS, DQS# crossing to rising
CK, CK# crossing
First DQS, DQS# rising edge
DQS, DQS# delay
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
10600-999
MIN
MAX
8500-777
MIN
MAX
140
200
ps
240
300
ps
4
4
tCK
49.5
50.625
ns
6
7.5
ns
13.5
13.125
ns
30
45
37.5
50
ns
36
70,200
37.5
70,200
Unit
ns
7.5
7.5
ns
15
15
tWR +
tRP/tCK
ns
7.5
7.5
ns
15
13.125
ns
4
4
tCK
tWR + tRP/tCK
110
70,200
110
7.8
3.9
tREFI
ns
70,200
ns
7.8
3.9
µs
tAON
-250
250
-300
300
ps
tAOF
0.3
0.7
0.3
0.7
tCK
tAONPD
1
9
1
9
ns
tAOFPD
1
9
1
9
ns
tADC
0.3
0.7
0.3
0.7
tCK
tXS
120
120
ns
tWLS
195
245
ps
tWLH
195
245
ps
tWLMRD
tWLDQSEN
40
25
40
25
tCK
tCK
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 10
of 14
Data Sheet
Rev.1.1
12.11.2010
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Exit reset from CKE HIGH to a
valid command
Begin power supply ramp to
power supplies stable
RESET# LOW to power supplies
stable
RESET# LOW to I/O and RTT
High-Z
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
10600-999
MIN
MAX
120
8500-777
Min
MAX
120
Unit
ns
tVDDPR
200
200
ms
tRPS
200
200
ms
tIOz
20
20
ns
SYMBOL
tXPR
tXP
6
7.5
ns
tCKE
5.625
5.625
tCK
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 11
of 14
Data Sheet
Rev.1.1
12.11.2010
SERIAL PRESENCE-DETECT MATRIX
Byte
Byte Description
10600-999
8500-777
0
CRC RANGE, EEPROM BYTES, BYTES USED
0x92
1
SPD REVISON
0x10
2
DRAM DEVICE TYPE
0x0B
3
MODULE TYPE (FORM FACTOR)
0x02
4
SDRAM DEVICE DENSITY & BANKS
0x02
5
SDRAM DEVICE ROW & COLUMN COUNT
0x11
6
BYTE 6 RESERVED
0x00
7
MODULE RANKS & DEVICE DQ COUNT
0x09
8
ECC TAG & MODULE MEMORY BUS WIDTH
0x03
9
FINE TIMEBASE DIVIDEND/DIVISOR
0x52
10
MEDIUM TIMEBASE DIVIDEND
0x01
11
MEDIUM TIMEBASE DIVISOR
0x08
12
MIN SDRAM CYCLE TIME (tCK MIN)
13
BYTE 13 RESERVED
14
CAS LATENCIES SUPPORTED (CL4 => CL11)
15
CAS LATENCIES SUPPORTED (CL12 => CL18)
0x00
16
MIN CAS LATENCY TIME (tAA MIN)
0x69
17
MIN WRITE RECOVERY TIME (tWR MIN)
0x78
18
MIN RAS# TO CAS# DELAY (tRCD MIN)
0x69
19
MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)
20
MIN ROW PRECHARGE DELAY (tRP MIN)
0x69
21
UPPER NIBBLE FOR tRAS & tRC
0x11
22
MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)
0x20
0x2C
23
MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)
0x89
0x95
24
MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB
0x70
25
MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB
0x03
26
MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)
0x3C
27
MIN INTERNAL READ TO PRECHARGE CMD DELAY
(tRTPMIN)
0x3C
28
MIN FOUR ACTIVE WINDOW DELAY (tFAW
MIN)
MSB
0x00
0x01
29
MIN FOUR ACTIVE WINDOW DELAY (tFAW
MIN)
LSB
0xF0
0x2C
30
SDRAM DEVICE OUTPUT DRIVERS SUPPORTED
0x83
31
SDRAM DEVICE THERMAL & REFRESH OPTIONS
0x01
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
0x0C
0x0F
0x00
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
0x3C
0x1C
0x30
www.swissbit.com
eMail: [email protected]
0x3C
Page 12
of 14
Data Sheet
Byte
32-59
Rev.1.1
Byte Description
10600-999
8500-777
BYTES 32-59 RESERVED
0x00
60
MODULE HEIGHT (NOMINAL)
0x0F
61
MODULE THICKNESS (MAX)
0x11
62
REFERENCE RAW CARD ID
0x01
63
ADDRESS MAPPING EDGE CONECTOR TO DRAM
0x01
BYTES 64-116 RESEVED
0x00
117
MODULE MFR ID (LSB)
0x83
118
MODULE MFR ID (MSB)
0Xda
119
MODULE MFR LOCATION ID
120
MODULE MFR YEAR
X
121
MODULE MFR WEEK
X
122-125
MODULE SERIAL NUMBER
X
126-127
CRC
128-145
MODULE PART NUMBER
64-116
12.11.2010
0x01
0x02
0x03
(Swizerland)
(Germany)
(USA)
0x626C
0x20C5
"SGU02G64B1BF2SA-xx"
146
MODULE DIE REV
X
147
MODULE PCB REV
X
148
DRAM DEVICE MFR ID (LSB)
0x80
149
DRAM DEVICE MFR (MSB)
0xCE
150-175
MFR RESERVED BYTES 150-175
0xFF
176-255
CUSTOMER RESERVED BYTES 176-255
0xFF
Part Number Code
S
G
U
02G
64
B1
B
F
2
SA
1
2
3
4
5
6
7
8
9
10
-
CC
*
R
11
12
13
*RoHs compl.
DDR3-1333MT/s
Swissbit AG
SDRAM DDR3
240 Pin DIMM 1.5V
Depth (2GB)
Width
PCB-Type (B63URCB 0.70)
Chip Vendor (Samsung)
2 Module Ranks
Chip Rev. F
Chip organisation x8
* optional / additional information
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 13
of 14
Data Sheet
Rev.1.1
12.11.2010
Locations
Swissbit AG
Industriestrasse 4 – 8
CH – 9552 Bronschhofen
Switzerland
Phone:
+41 (0)71 913 03 03
Fax:
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
+49 (0)30 93 69 54 – 0
Fax:
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
14 Willett Avenue, Suite 301A
Port Chester, NY 10573
USA
Phone:
+1 914 935 1400
Fax:
+1 914 935 9865
_____________________________
Swissbit NA, Inc.
3913 Todd Lane, Suite – 307
Austin, TX 78744
USA
Phone:
+1 512 302 9001
Fax:
+1 512 302 4808
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
+81 3 5356 3511
Fax:
+81 3 5356 3512
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 14
of 14
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