TS128MSQ64V6U - uri=media.digikey

TS128MSQ64V6U - uri=media.digikey
200PIN DDR2 667 SO-DIMM
1GB With 128Mx8 CL5
TS128MSQ64V6U
Description
Placement
The TS128MSQ64V6U is a 128M x 64bits DDR2-667
SO-DIMM. The TS128MSQ64V6U consists of 8pcs
128Mx8bits DDR2 SDRAMs and a 2048 bits serial
EEPROM on a 200-pin printed circuit board. The
D
TS128MSQ64V6U is a Dual In-Line Memory Module and
B A
is intended for mounting into 200-pin edge connector
sockets.
E
Synchronous design allows precise cycle control with the
C
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
G
programmable latencies allow the same device to be
H
useful for a variety of high bandwidth, high performance
I
memory system applications.
J
Features
• RoHS compliant products.
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 333MHZ; 667Mb/s/Pin.
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency :0, 1, 2, 3 and 4
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4, 8(Interleave/nibble sequential)
• Programmable sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
• Off-Chip Driver (OCD) Impedance Adjustment
• MRS cycle with address key programs.
• On Die Termination
• Serial presence detect with EEPROM
Transcend Information Inc.
1
F
K
200PIN DDR2 667 SO-DIMM
1GB With 128Mx8 CL5
TS128MSQ64V6U
Dimensions
Side
Pin Identification
Millimeters
Inches
Symbol
Function
A
67.6±0.15
2.661±0.006
A0~A13, BA0~BA2
Address input
B
63.6
2.503
DQ0~DQ63
Data Input / Output.
C
11.4
0.449
DQS0~DQS7
Data strobe
D
47.4
1.866
E
4.2
0.1650
/DQS0~/DQS7
Differential Data strobe
F
2.15±0.15
0.085±0.006
G
6
0.236
H
18
0.709
I
4
J
K
CK0, /CK0
CK1, /CK1
Clock Input.
CKE0, CKE1
Clock Enable Input.
0.157
ODT0, ODT1
On-die termination control line
30
1.181
/CS0, /CS1
Chip Select Input.
1.0±0.075
0.039±0.003
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DM0~DM7
Data-in Mask
VDD
+1.8 Voltage power supply
(Refer Placement)
VDDQ
VREF
VDDSPD
Transcend Information Inc.
2
+1.8 Voltage Power Supply for
DQS
Power Supply for Reference
Serial EEPROM Positive Power
Supply
SA0~SA2
Address select for EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
VSS
Ground
NC
No Connection
200PIN DDR2 667 SO-DIMM
1GB With 128Mx8 CL5
TS128MSQ64V6U
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
VREF
69
NC
03
VSS
71
VSS
05
DQ0
73
DQ26
07
DQ1
75
DQ27
09
VSS
77
VSS
11
/DQS0
79
CKE0
13
DQS0
81
VDD
15
VSS
83
*/CS2
17
DQ2
85
*BA2
19
DQ3
87
VDD
21
VSS
89
A12
23
DQ8
91
A9
25
DQ9
93
A8
27
VSS
95
VDD
29
/DQS1
97
A5
31
DQS1
99
A3
33
VSS
101
A1
35
DQ10
103
VDD
37
DQ11
105
A10/AP
39
VSS
107
BA0
41
VSS
109
/WE
43
DQ16
111
VDD
45
DQ17
113
/CAS
47
VSS
115
*/CS1
49
/DQS2
117
VDD
51
DQS2
119
*ODT1
53
VSS
121
VSS
55
DQ18
123
DQ32
57
DQ19
125
DQ33
59
VSS
127
VSS
61
DQ24
129
/DQS4
63
DQ25
131
DQS4
65
VSS
133
VSS
67
DM3
135
DQ34
* Please refer Block Diagram
Transcend Information Inc.
Pin
No
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Pin
Pin
Name
No
DQ35
02
VSS
04
DQ40
06
DQ41
08
VSS
10
DM5
12
VSS
14
DQ42
16
DQ43
18
VSS
20
DQ48
22
DQ49
24
VSS
26
NC, TEST 28
VSS
30
/DQS6
32
DQS6
34
VSS
36
DQ50
38
DQ51
40
VSS
42
DQ56
44
DQ57
46
VSS
48
DM7
50
VSS
52
DQ58
54
DQ59
56
VSS
58
SDA
60
SCL
62
VDDSPD 64
66
68
3
Pin
Name
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
/CK0
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
/DQS3
Pin
No
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
Pin
Name
DQS3
VSS
DQ30
DQ31
VSS
*CKE1
VDD
*A15
*A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
/RAS
/CS0
VDD
ODT0
*A13
VDD
*/CS3
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
Pin
No
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Pin
Name
VSS
DQ44
DQ45
VSS
/DQS5
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
/CK1
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
/DQS7
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
Block Diagram
/CS0
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
DM /CS DQS /DQS
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
U1
/DQS1
DQS1
DM1
/DQS5
DQS5
DM5
DM /CS DQS /DQS
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
U3
/DQS2
DQS2
DM2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM /CS DQS /DQS
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
U5
/DQS3
DQS3
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0~A13
BA0~BA2
CKE0
/RAS
/CAS
/WE
ODT0
U6
/DQS7
DQS7
DM7
DM /CS DQS /DQS
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
U4
/DQS6
DQS6
DM6
DM /CS DQS /DQS
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
U2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U7
U1~U8
U1~U8
U1~U8
U1~U8
U1~U8
U1~U8
U1~U8
DM /CS DQS /DQS
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
CK0,/CK0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U8
EEPROM
4 loads
SCL
SDA
A0 A1 A2
CK1,/CK1
4 loads
SA0 SA1
VDDSPD
Note:
1.DQ,DM,DQS & /DQS resistors :22 Ohms±5%
2.Bx,Ax,CKEx,ODTx,CSx,/RAS,
/CAS&/WEresistors :3 Ohms±5%
EEPROM
VDD/VDDQ
U1~U8
VREF
U1~U8
VSS
U1~U8
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
Absolute Maximum DC Ratings
Parameter
Symbol
Value
Unit
Notes
Voltage on VDD relative to Vss
VDD
-1.0 ~ 2.3
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
-0.5 ~ 2.3
V
1
Voltage on VDDL pin relative to Vss
VDDL
-0.5 ~ 2.3
V
1
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 2.3
V
1
Storage temperature
TSTG
-55~+100
°C
1,2
Note: 1.Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
stress rating only and functional operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2.Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC operating conditions (SSTL –1.8)
Parameter
Symbol
Rating
Min
Typ.
Max
Unit Notes
Supply voltage
VDD
1.7
1.8
1.9
V
Supply voltage for DLL
VDDL
1.7
1.8
1.9
V
4
Supply voltage for Output
VDDQ
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49*VDDQ 0.50*VDDQ
0.51*VDDQ
V
1,2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
DC Input logic high
VIH(DC)
VREF+0.125
VDDQ+0.3
V
DC Input logic low
VIL(DC)
-0.3
VREF-0.125
V
Note: There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all
conditions VDDQ must be less than or equal to VDD.
1.The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track
variations in VDDQ.
2.Peak to peak AC noise on VREF may not exceed +/-2% VREF (DC).
3.VTT of transmitting device must track VREF of receiving device.
4.AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Operating Temperature Condition
Parameter
Symbol
Rating
Unit
Note
Operating Temperature
TOPER
0 to 85
°C
1,2
Note: 1.Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the
measurement conditions, please refer to JESD51.2 standard.
2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be supported.
IDD Specification parameters Definition
( IDD values are for full operating range of voltage and Temperature)
Parameter
Symbol
Max.
Unit
IDD0
280
mA
IDD1
320
mA
IDD2P
80
mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2Q
152
mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
176
mA
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Active power - down current; All banks open; tCK
Fast PDN Exit MRS(12) = 0mA IDD3P-F
144
= tCK(IDD); CKE is LOW; Other control and address
mA
bus inputs are STABLE; Data bus inputs are
Slow PDN Exit MRS(12) = 1mA IDD3P-S
136
FLOATING
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control
IDD3N
240
mA
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
IDD4R
520
mA
tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
IDD4W
440
mA
HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING IDD4R
Burst Auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and
IDD5
680
mA
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current; CK and CK\ at 0V; CKE ≒ 0.2V; Other control and address
IDD6
80
mA
bus inputs are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid
IDD7
1000
mA
commands; Address bus inputs are STABLE during Deselects; Data pattern is same
as IDD4R; Refer to the following page for detailed timing conditions
Note: 1. Module IDD was calculated on the specific brand DRAM(3Xnm) component I DD and can be differently
measured according to DQ loading capacitor.
Note
Input AC Logic Level
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Symbol
VIH(AC)
VIL(AC)
Min
VREF + 0.200
Max
Unit
VREF - 0.200
V
V
Note
AC Input Test Condition
Condition
Input reference voltage
Input signal maximum peak to peak swing
Symbol
Value
Unit
Note
VREF
0.5*VDDQ
V
1
VSWING(MAX)
1.0
V
1
1.0
V/ns
2,3
Input signal minimum slew rate
SLEW
Note: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising
edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions
and VIH(AC) to VIL(AC) on the negative transitions.
VDD
VIH(AC)min
VIH(DC)min
VREF
VIL(DC)max
VIL(AC)max
VSS
VSWING(MAX)
delta TR
delta TF
Falling Slew= VREF-VIL(AC)max
delta TF
Rising Slew= VIH(AC)min-VREF
delta TR
AC Input Test Signal Waveform
Input/Output Capacitance (VDD = 1.8V, VDDQ = 1.8V, TA = 25°C)
Parameter
Input capacitance (CK0 and /CK0)
Input capacitance (CK1 and /CK1)
Input capacitance (CKE0 and /CS)
Input capacitance (A0~A15, BA0~BA2, /RAS, /CAS, /WE)
Input capacitance (DQ, DM, DQS, /DQS)
Note:
Symbol
Min
Max
Unit
CCK0
CCK1
CI1
CI2
CIO
-
32
32
42
42
5.5
pF
pF
pF
pF
pF
DM is internally loaded to match DQ and DQS identically.
Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter
Symbol
tAC
Min
-450
Max
+450
Unit
ps
tDQSCK
-400
+400
ps
CK high-level width
tCH
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
tCK
CK half period
tHP
min(tCL,tCH)
X
ps
Clock cycle time, CL=x
tCK
3000
8000
ps
DQ and DM input hold time
tDH
175
x
ps
DQ and DM input setup time
tDS
100
X
ps
Control & Address input pulse width for each input
tIPW
0.6
x
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
X
tCK
Data-out high-impedance time from CK/CK
tHZ
X
tAC max
ps
tLZ(DQS)
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tACmin
tACmax
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
X
240
ps
tQHS
X
340
ps
tQH
tHP - tQHS
X
ps
Write command to first DQS latching transition
tDQSS
-0.25
0.25
tCK
DQS input high pulse width
tDQSH
0.35
X
tCK
DQS input low pulse width
tDQSL
0.35
X
tCK
DQS falling edge to CK setup time
tDSS
0.2
X
tCK
DQS falling edge hold time from CK
tDSH
0.2
X
tCK
Mode register set command cycle time
tMRD
2
X
tCK
Write postamble
tWPST
0.4
0.6
tCK
Write preamble
tWPRE
0.35
X
tCK
Address and control input hold time
tIH
275
X
ps
Address and control input setup time
tIS
200
X
ps
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
Active to active command period for 1KB page size
products
Active to active command period for 2KB page size
products
Four Activate Window for 1KB page size products
tRPST
0.4
0.6
tCK
tRRD
7.5
X
ns
tRRD
10
X
ns
tFAW
37.5
ns
Four Activate Window for 2KB page size products
tFAW
50
ns
/CAS to /CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
DQ output access time from CK & /CK
DQS output access time from CK & /CK
DQS low-impedance time from CK/CK
DQ hold skew factor
DQ/DQS output hold time from DQS
X
ns
Note
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
Internal write to read command delay
tWTR
7.5
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read command
tXP
Exit active power down to read command
Exit active power down to read command (Slow exit,
Lower power)
CKE minimum pulse width (high and low pulse width)
tXARD
2
2
tXARDS
7 - AL
tCK
tCKE
3
tCK
ODT turn-on delay
tAOND
2
2
tCK
tAON
tAC(min)
ns
tAONPD
tAC(min)+2
tAOFD
2.5
tAC(max)+0.7
2tCK+
tAC(max)+1
2.5
tAOF
tAC(min)
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
tOIT
0
tDelay
tIS+tCK+tIH
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
X
X
X
X
tAC(max)+ 0.6
2.5tCK+
tAC(max)+1
12
tCK
ns
tCK
tCK
ns
tCK
ns
ns
ns
ns
SERIAL PRESENCE DETECT SPECIFICATION
Serial Presence Detect
Byte No.
0
1
2
3
4
Function Described
# of Serial PD Bytes written during module production
Total # of Bytes of S.P.D Memory Device
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
5
# of Module Rows on this Assembly
6
7
8
Data Width of this Assembly
Reserved
VDDQ and Interface Standard of this Assembly
DDR2 SDRAM cycle time at Max. Supported CAS
latency=X
DDR2 SDRAM Access time from clock at CL=X
DIMM configuration type (non-parity, Parity, ECC)
Refresh Rate
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Width
Reserved
DDR2 SDRAM device attributes: Burst lengths
supported
DDR2 SDRAM device attributes: # of banks on each
DDR2 SDRAM device
DDR2 SDRAM device attributes:CAS Latency
supported
9
10
11
12
13
14
15
16
17
18
19
20
DIMM Mechanical characteristics; thickness
DIMM type information
21
DDR2 SDRAM Module Attributes
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DDR2 SDRAM Device Attributes: General
DDR2 SDRAM Cycle Time CL=X-1
DDR2 SDRAM Access from Clock CL=X-1
DDR2 SDRAM Cycle Time CL=X-2
DDR2 SDRAM Access from Clock CL=X-2
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Activate delay (tRRD)
Minimum RAS to CAS Delay (tRCD)
Minimum active to Precharge time (tRAS)
Module ROW density
Command and address setup time before clock(=tIS)
Command and address hold time after clock(=tIH)
Data input setup time before strobe(=tDS)
Data input hold time after strobe(=tDH)
Write recovery time(=tWR)
Internal write to read command delay(=tWTR)
Internal read to precharge command delay(=tRTP)
Standard Specification
128bytes
256bytes
DDR2 SDRAM
14
10
1 ROW, Planar,
30.0mm
64bits
SSTL 1.8V
Vendor Part
80
08
08
0E
0A
3.0ns
30
±0.45ns
Non ECC
7.8us
X8
N/A
-
45
00
82
08
00
00
4,8
0C
8 banks
08
5,4,3
38
≤ 3.80mm
SODIMM
Analysis probe not
installed, FET switch
external not enable
Supports weak driver
3.75ns
±0.5ns
5.0ns
±0.6ns
15ns
7.5ns
15ns
45ns
1GB
0.20ns
0.27ns
0.10ns
0.17ns
15ns
7.5ns
7.5ns
01
60
40
00
05
04
00
07
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
39
40
41
42
43
44
45
46
47~61
62
63
64-71
72
Memory analysis probe characteristics
Reserved
DDR2 SDRAM Minimum Active to Active/Auto Refresh
Time(tRC)
DDR2 SDRAM Minimum Auto-Refresh to Active/AutoRefresh Command Period (tRFC)
DDR2 SDRAM Maximum Device Cycle Time (tCK
max)
DDR2 SDRAM DQS-DQ Skew for DQS and associated
DQ signals (tDQSQ max)
DDR2 SDRAM Read Data Hold Skew Factor (tQHS)
PLL Relock Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID
Manufacturing Location
-
00
06
60ns
3C
127.5ns
7F
8ns
80
0.24ns
18
0.34ns
REV 1.2
Transcend
T
22
00
00
12
18
7F, 4F
54
54 53 31 32 38 4D
73-90
91-92
93-94
95-98
99-127
128~255
Manufacturers Part Number
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Open for customer use
TS128MSQ64V6U
By Manufacturer
By Manufacturer
Undefined
53 51 36 34 56
36
55 20 20 20 20
20
Variable
Variable
-
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