LM27966 White LED Driver with I2C Compatible

LM27966 White LED Driver with I2C Compatible
LM27966
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SNVS448B – JULY 2006 – REVISED MAY 2013
LM27966 White LED Driver with I2C Compatible Interface
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FEATURES
DESCRIPTION
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The LM27966 is a highly integrated charge-pumpbased display LED driver. The device can drive up to
6 LEDs in parallel with a total output current of
180mA. Regulated internal current sources deliver
excellent current and brightness matching in all LEDs.
1
2
91% Peak LED Drive Efficiency
No Inductor Required
0.3% Current Matching
Drives 6 LEDs with up to 30mA per LED
180mA of total driver current
I2C Compatible Brightness Control Interface
Adaptive 1×- 3/2× Charge Pump
Resistor-Programmable Current Settings
External Chip RESET Pin (RESET)
Extended Li-Ion Input: 2.7V to 5.5V
Small low profile industry standard leadless
package, WQFN 24 : (4mm x 4mm x 0.8mm)
The LED driver current sources are split into two
independently controlled groups. The primary group,
which can be configured with 4 or 5 LEDs, can be
used to backlight the main phone display. An
additional, independently controlled led driver is
provided for driving an indicator or other general
purpose LED function. The LM27966 has an I2C
compatible interface that allows the user to
independently control the brightness on each bank of
LEDs.
The device provides excellent efficiency without the
use of an inductor by operating the charge pump in a
gain of 3/2, or in Pass-Mode. The proper gain for
maintaining current regulation is chosen, based on
LED forward voltage, so that efficiency is maximized
over the input voltage range.
APPLICATIONS
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Mobile Phone Display Lighting
PDAs Backlighting
General LED Lighting
The LM27966 is available in a small 24-pin Leadless
Leadframe WQFN-24 package.
Typical Application Circuit
AUXILIARY
LED
MAIN DISPLAY
D1
VIN
+
CIN
-
VIN
1 PF
D2
D3
D4
D5
DAUX
POUT
COUT
C1
1 PF
1 PF
LM27966
C2
1 PF
ISET
GND
RSET
SCL
2
I C
Compatible
Interface
SDIO
VIO
RESET
Capacitors: TDK C1608X5R1A105K
or equivalent
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM27966
SNVS448B – JULY 2006 – REVISED MAY 2013
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Connection Diagram
24 Pin Quad WQFN Package
See Package Number RTW0024A
6
5
4
3
2
1
1
2
3
4
5
6
7
24
24
7
8
23
23
8
9
9
22
22
10
21
21
10
11
20
20
11
19
19
DAP
DAP
12
13
14
15
16
17
18
12
18
17
Top View
16
15
14
13
Bottom View
Pin Descriptions
Pin Name
Pin No.
VIN
24
Input voltage. Input range: 2.7V to 5.5V.
Description
POUT
23
Charge Pump Output Voltage
C1, C2
19, 22 (C1)
20, 21 (C2)
Flying Capacitor Connections
D5, D4, D3, D2, D1
12, 13, 14, 15, 16
LED Drivers - Main Display
DAUX
3
LED Driver - Indicator LED
ISET
17
Placing a resistor (RSET) between this pin and GND sets the full-scale LED current for Dx ,
and DAUX LEDs.
LED Current = 200 × (1.25V ÷ RSET)
SCL
1
Serial Clock Pin
SDIO
2
Serial Data Input/Output Pin
VIO
7
Serial Bus Voltage Level Pin
RESET
10
Harware Reset Pin. High = Normal Operation, Low = RESET
GND
9, 18, DAP
NC
4, 5, 6, 8, 11
Ground
No Connect
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1) (2) (3)
VIN pin voltage
-0.3V to 6.0V
SCL, SDIO, VIO, RESET pin voltages
-0.3V to (VIN+0.3V)w/ 6.0V max
IDx Pin Voltages
-0.3V to (VPOUT+0.3V)w/ 6.0V max
Continuous Power Dissipation
Internally Limited
(4)
Junction Temperature (TJ-MAX)
150ºC
Storage Temperature Range
-65ºC to +150º C
(5)
Maximum Lead Temperature (Soldering)
(6)
ESD Rating
Human Body Model
(1)
(2)
(3)
(4)
(5)
(6)
2.0kV
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 170°C (typ.) and
disengages at TJ = 165°C (typ.).
For detailed soldering specifications and information, please refer to Application Note 1187: Leadless Leadframe Package (AN-1187).
The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7)
Operating Rating
(1) (2)
Input Voltage Range
2.7V to 5.5V
LED Voltage Range
2.0V to 4.0V
Junction Temperature (TJ) Range
-30°C to +100°C
Ambient Temperature (TA) Range (3)
(1)
(2)
(3)
-30°C to +85°C
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
All voltages are with respect to the potential at the GND pin.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =
100°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).
Thermal Properties
Juntion-to-Ambient Thermal
Resistance (θJA), RTW0024A Package
(1)
41.3°C/W
(1)
Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design. For more information, please refer to
Application Note 1187: Leadless Leadframe Package (AN-1187).
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Electrical Characteristics
(1) (2)
Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = 3.6V; VRESET = VIN; VIO = 1.8V VDx = 0.4V; VDAUX = 0.4V; RSET = 16.9kΩ; Dx = DAUX =
Fullscale Current; EN-MAIN, EN-D5 Bits = “1”; C1=C2=1.0µF, CIN=COUT=1.0µF; Specifications related to output current(s) and
current setting pins (IDx and ISET) apply to Main Display and Auxiliary LED. (3)
Parameter
Output Current Regulation
Main Display or Auxiliary LED Enabled
IDx
Maximum Output Current Regulation
Main Display and Auxiliary LED Enabled
(4)
IDx-MATCH
LED Current Matching
ROUT
Open-Loop Charge Pump Output
Resistance
VDxTH
VDx 1x to 3/2x Gain Transition Threshold
VHR
Current Source Headroom Voltage
Requirement
IQ
ISD
Min
Typ
Max
Units
3.0V ≤ VIN ≤ 5.5V
EN-AUX= '0'
Test Conditions
18.2 (-9.5%)
20.1
22.0 (+9.5%)
mA
(%)
3.0V ≤ VIN ≤ 5.5V
EN-AUX = '1' and EN-MAIN = EN-D5 = '0'
19.2 (-7.7%)
20.8
22.4 (+7.7%)
mA
(%)
30
Dx
3.2V ≤ VIN ≤ 5.5V
RSET = 8.33kΩ
VLED = 3.6V
EN-MAIN = EN-D5 = EN-AUX = “1”
mA
30
DAUX
(5)
0.3
Gain = 3/2
1.7
2.75
Gain = 1
%
Ω
1
VDx Falling
RSET = 16.9kΩ
175
mV
IDxx = 95% ×IDxx (nom.)
(IDxx (nom) ≈ 15mA)
Gain = 3/2
EN-MAIN = EN-D5 and/or EN-AUX= "1"
110
mV
Quiescent Supply Current
Gain = 1.5x, No Load
2.90
3.32
mA
Shutdown Supply Current
All EN-x bits = "0"
3.4
5.4
µA
VSET
ISET Pin Voltage
2.7V ≤ VIN ≤ 5.5V
1.25
IDx/
ISET
Output Current to Current Set Ratio Main
Display, DAUX
fSW
Switching Frequency
tSTART
Start-up Time
fPWM
Internal Diode Current PWM Frequency
VRESET
Reset Voltage Thresholds
(6)
V
200
0.89
POUT = 90% steady state
2.7V ≤ VIN ≤ 5.5V
Reset
Normal Operation
1.27
1.57
MHz
250
µs
20
kHz
0
0.45
1.2
VIN
1.4
VIN
V
V
V
I2C Compatible Interface Voltage Specifications (SCL, SDIO, VIO)
VIO
Serial Bus Voltage Level
2.7V ≤ VIN ≤ 5.5V (7)
VIL
Input Logic Low "0"
2.7V ≤ VIN ≤ 5.5V, VIO = 3.0V
0
0.3 × VIO
VIH
Input Logic High "1"
2.7V ≤ VIN ≤ 5.5V, VIO = 3.0V
0.7 × VIO
VIO
V
VOL
Output Logic Low "0"
ILOAD = 3mA
400
mV
I2C Compatible Interface Timing Specifications (SCL, SDIO, VIO) (8)
t1
SCL (Clock Period)
2.5
µs
t2
Data In Setup Time to SCL High
100
ns
t3
Data Out stable After SCL Low
0
ns
t4
SDIO Low Setup Time to SCL Low (Start)
100
ns
t5
SDIO High Hold Time After SCL High
(Stop)
100
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
4
All voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most
likely norm.
CIN, CPOUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics
The maximum total output current for the LM27966 should be limited to 180mA. The total output current can be split among any of the
three banks (IDxA = IDxC = 30mA Max.). Under maximum output current conditions, special attention must be given to input voltage and
LED forward voltage to ensure proper current regulation. See the Maximum Output Current section of the datasheet for more
information.
For the Main Display group of outputs on a part, the following are determined: the maximum output current in the group (MAX), the
minimum output current in the group (MIN), and the average output current of the group (AVG). Two matching numbers are calculated:
(MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure for the bank. The
typical specification provided is the most likely norm of the matching figure for all parts.
For each IDxx output pin, headroom voltage is the voltage across the internal current sink connected to that pin. For Main and Aux
outputs, VHR = VOUT -VLED. If headroom voltage requirement is not met, LED current regulation will be compromised.
SCL and SDIO signals are referenced to VIO and GND for minimum VIO voltage testing.
SCL and SDIO should be glitch-free in order for proper brightness control to be realized.
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BLOCK DIAGRAM
1 PF
C1+
VIN
2.7V to 5.5V
COUT
1 PF
1 PF
C1-
C2+
C2-
POUT
DAUX
D1 D2 D3 D4 D5
3/2X and 1X
Regulated Charge Pump
1 PF
Main Display Current
Sinks
GAIN
CONTROL
AUX Current
Sink
VLED
SENSE
LM27966
SoftStart
1.25MHz.
Switch
Frequency
1.25V
Ref.
Brightness
Control
Brightness
Control
20kHz PWM
Current Clock
RESET
General Purpose Register
SCL
2
SDIO
I C Interface
Block
VIO
Brightness Control Register
Main Display
Brightness Control Register
Auxiliary
ISET
GND
RSET
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified: TA = 25°C; VIN = 3.6V; VRESET = VIN; VLEDx = VLEDAUX = 3.6V; RSET = 16.9kΩ; C1=C2= CIN = CPOUT =
1µF; EN = EN5 = '1'.
6
LED Drive Efficiency
vs
Input Voltage
Input Current
vs
Input Voltage
Figure 1.
Figure 2.
Main Bank Current Regulation
vs
Input Voltage
DAUX Current Regulation
vs
Input Voltage
Figure 3.
Figure 4.
Main Bank Current Matching
vs
Input Voltage
Main Bank Diode Current
vs
Brightness Register Code
Figure 5.
Figure 6.
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CIRCUIT DESCRIPTION
OVERVIEW
The LM27966 is a white LED driver system based upon an adaptive 1.5×/1× CMOS charge pump capable of
supplying up to 180mA of total output current. With two controlled banks of constant current sinks (Main and
AUX), the LM27966 is an ideal solution for platforms requiring a single white LED driver for main display and
indicator lighting. The tightly matched current sinks ensure uniform brightness from the LEDs across the entire
small-format display.
Each LED is configured in a common anode configuration, with the peak drive current being programmed
through the use of an external RSET resistor. An I2C compatible interface is used to enable the device and vary
the brightness within the individual current sink banks. For Main Display LEDs, 32 levels of brightness control are
available. The brightness control is achieved through a mix of analog and pulse width modulated (PWM)
methods. DAUX has 4 analog brightness levels available.
CIRCUIT COMPONENTS
Charge Pump
The input to the 1.5x/1x charge pump is connected to the VIN pin, and the regulated output of the charge pump is
connected to the VOUT pin. The recommended input voltage range of the LM27966 is 3.0V to 5.5V. The device’s
regulated charge pump has both open loop and closed loop modes of operation. When the device is in open
loop, the voltage at VOUT is equal to the gain times the voltage at the input. When the device is in closed loop,
the voltage at VOUT is regulated to 4.6V (typ.). The charge pump gain transitions are actively selected to maintain
regulation based on LED forward voltage and load requirements. This allows the charge pump to stay in the
most efficient gain (1x) over as much of the input voltage range as possible, reducing the power consumed from
the battery.
LED Forward Voltage Monitoring
The LM27966 has the ability to switch converter gains (1x or 1.5x) based on the forward voltage of the LED load.
This ability to switch gains maximizes efficiency for a given load. Forward voltage monitoring occurs on all diode
pins within Main Display. At higher input voltages, the LM27966 will operate in pass mode, allowing the POUT
voltage to track the input voltage. As the input voltage drops, the voltage on the DX pins will also drop (VDX =
VPOUT – VLEDx). Once any of the active Dx pins reaches a voltage approximately equal to 175mV, the charge
pump will then switch to the gain of 1.5x. This switchover ensures that the current through the LEDs never
becomes pinched off due to a lack of headroom on the current sources.
Diode pin D5 can have the diode sensing circuity disabled through the general purpose register if D5 is not going
to be used.
DAUX is not a monitored LED current sink.
RESET Pin
The LM27965 has a hardware reset pin (RESET) that allows the device to be disabled by an external controller
without requiring an I2C write command. Under normal operation, the RESET pin should be held high (logic ’1’)
to prevent an unwanted reset. When the RESET is driven low (logic ’0’), all internal control registers reset to the
default states and the part becomes disabled. Please see the Electrical Characteristics section of the datasheet
for required voltage thresholds.
I2C Compatible Interface
DATA VALIDITY
The data on SDIO line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
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SCL
SDIO
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 7. Data Validity Diagram
A pull-up resistor between VIO and SDIO must be greater than [(VIO-VOL) / 3mA] to meet the VOL requirement
on SDIO. Using a larger pull-up resistor results in lower switching current with slower edges, while using a
smaller pull-up results in higher switching currents with faster edges.
START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the end of the I2C session. A START condition is
defined as SDIO signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as
the SDIO transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and
STOP conditions. The I2C bus is considered to be busy after a START condition and free after a STOP condition.
During data transmission, the I2C master can generate repeated START conditions. First START and repeated
START conditions are equivalent, function-wise. The data on SDIO line must be stable during the HIGH period of
the clock signal (SCL). In other words, the state of the data line can only be changed when CLK is LOW.
SDIO
SCL
S
P
START condition
STOP condition
Figure 8. Start and Stop Conditions
TRANSFERING DATA
Every byte put on the SDIO line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDIO line (HIGH) during the acknowledge clock pulse. The LM27966
pulls down the SDIO line during the 9th clock pulse, signifying an acknowledge. The LM27966 generates an
acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LM27966 address is 36h. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
8
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ack from slave
ack from slave
ack from slave
start
msb Chip Address lsb
w
ack
msb Register Add lsb
ack
msb DATA lsb
ack
stop
start
Id = 36h
w
ack
addr = 10h
ack
DGGUHVV K¶06 data
ack
stop
SCL
SDIO
Figure 9. Write Cycle
w = write (SDIO = "0")
r = read (SDIO = "1")
ack = acknowledge (SDIO pulled down by either master or slave)
rs = repeated start
id = chip address, 36h for LM27966
I2C COMPATIBLE CHIP ADDRESS
The chip address for LM27966 is 0110110, or 36h.
MSB
LSB
ADR6
bit7
ADR5
bit6
ADR4
bit5
ADR3
bit4
ADR2
bit3
ADR1
bit2
ADR0
bit1
0
1
1
0
1
1
0
R/W
bit0
2
I C Slave Address (chip address)
Figure 10. Chip Address
INTERNAL REGISTERS OF LM27966
Register
Internal Hex Address
Power On Value
General Purpose Register
10h
0010 0000
Main Display Brightness Control Register
A0h
1110 0000
Auxiliary LED Brightness Control Register
C0h
1111 1100
MSB
0
bit7
LSB
0
bit6
1
bit5
T1
bit4
EN-D5
bit3
EN-AUX
bit2
T0
bit1
EN-MAIN
bit0
Figure 11. General Purpose Register Description
Internal Hex Address: 10h
NOTE
EN-MAIN: Enables Dx LED drivers (Main Display)
T0: Must be set to '0'
EN-AUX: Enables DAUX LED driver (Indicator Lighting)
EN-D5: Enables D5 LED voltage sense
T1: Must be set to '0'
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Main Display Brightness Control
Register Address: 0xA0
MSB
1
bit7
1
bit6
1
bit5
Dx4
bit4
Dx3
bit3
LSB
Dx2
bit2
Dx1
bit1
Dx0
bit0
DAUX Brightness Control
Register Address: 0xC0
MSB
1
bit7
1
bit6
1
bit5
1
bit4
1
bit3
LSB
1
bit2
DAUX-1
bit1
DAUX-0
bit0
Figure 12. Brightness Control Register Description
Internal Hex Address: 0xA0 (Main Display), 0xC0 (DAUX)
NOTE
Dx4-Dx0: Sets Brightness for Dx pins (Main Display). 11111=Fullscale
Bit7 to Bit 5: Not Used
DAUX1-DAUX0: Sets Brightness for DAUX pin. 11 = Fullscale
Bit7 to Bit2:Not Used
Full-Scale Current set externally by the following equation:
IDx = 200 × 1.25V / RSET
Table 1. Brightness Level Control Table (Main Display)
10
Brightness Code (hex)
Analog Current
(% of Full-Scale)
Duty Cycle (%)
Perceived Brightness Level (%)
00
20
1/16
1.25
01
20
2/16
2.5
02
20
3/16
3.75
03
20
4/16
5
04
20
5/16
6.25
05
20
6/16
7.5
06
20
7/16
8.75
07
20
8/16
10
08
20
9/16
11.25
09
20
10/16
12.5
0A
20
11/16
13.75
0B
20
12/16
15
0C
20
13/16
16.25
0D
20
14/16
17.5
0E
20
15/16
18.75
0F
20
16/16
20
10
40
10/16
25
11
40
11/16
27.5
12
40
12/16
30
13
40
13/16
32.5
14
40
14/16
35
15
40
15/16
37.5
16
40
16/16
40
17
70
11/16
48.125
18
70
12/16
52.5
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Table 1. Brightness Level Control Table (Main Display) (continued)
Brightness Code (hex)
Analog Current
(% of Full-Scale)
Duty Cycle (%)
Perceived Brightness Level (%)
56.875
19
70
13/16
1A
70
14/16
61.25
1B
70
15/16
65.625
1C
70
16/16
70
1D
100
13/16
81.25
1E
100
15/16
93.75
1F
100
16/16
100
DAUX Brightness Levels (%of Full-Scale) = 20%, 40%, 70%, 100%
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APPLICATION INFORMATION
SETTING LED CURRENT
The current through the LEDs connected to Dx can be set to a desired level simply by connecting an
appropriately sized resistor (RSET) between the ISET pin of the LM27966 and GND. The Dx currents are
proportional to the current that flows out of the ISET pin and are a factor of 200 times greater than the ISET current.
The feedback loops of the internal amplifiers set the voltage of the ISET pin to 1.25V (typ.). The statements above
are simplified in the equations below:
IDx= 200 × (VISET / RSET)
RSET = 200 × (1.25V / IDx)
(1)
Once the desired RSET value has been chosen, the LM27966 has the ability to internally dim the LEDs using a
mix of Pulse Width Modulation (PWM) and analog current scaling. The PWM duty cycle is set through the I2C
compatible interface. LEDs connected to Main Display current sinks (Dx) can be dimmed to 32 different
levels/duty-cycles. The internal PWM frequency for Main Display is a fixed 20kHz. DAUX has 4 analog current
levels.
Please refer to the I2C Compatible Interface section of this datasheet for detailed instructions on how to adjust
the brightness control registers.
MAXIMUM OUTPUT CURRENT, MAXIMUM LED VOLTAGE, MINIMUM INPUT VOLTAGE
The LM27966 can drive 6 LEDs at 30mA each (Main Display and DAUX) from an input voltage as low as 3.2V, so
long as the LEDs have a forward voltage of 3.6V or less (room temperature).
The statement above is a simple example of the LED drive capabilities of the LM27966. The statement contains
the key application parameters that are required to validate an LED-drive design using the LM27966: LED
current (ILEDx), number of active LEDs (Nx), LED forward voltage (VLED), and minimum input voltage (VIN-MIN).
The equation below can be used to estimate the maximum output current capability of the LM27966:
ILED_MAX = [(1.5 x VIN) - VLED - (IDAUX × ROUT)] / [(NMAIN x ROUT) + kHR] (eq. 1)
ILED_MAX = [(1.5 x VIN ) - VLED - (IDAUX × 2.75Ω)] / [(NMAIN x 2.75Ω) + kHR]
(2)
(3)
IDAUX is the additional current that could be delivered to the AUX LED.
ROUT – Output resistance. This parameter models the internal losses of the charge pump that result in voltage
droop at the pump output POUT. Since the magnitude of the voltage droop is proportional to the total output
current of the charge pump, the loss parameter is modeled as a resistance. The output resistance of the
LM27966 is typically 2.75Ω (VIN = 3.6V, TA = 25°C). In equation form:
VPOUT = (1.5 × VIN) – [NMAIN× ILED-MAIN × ROUT]
(eq. 2)
(4)
kHR – Headroom constant. This parameter models the minimum voltage required to be present across the current
sources for them to regulate properly. This minimum voltage is proportional to the programmed LED current, so
the constant has units of mV/mA. The typical kHR of the LM27966 is 8mV/mA. In equation form:
(VPOUT – VLEDx) > kHR × ILEDx
(eq. 3)
Typical Headroom Constant Value kHR = 8mV/mA
(5)
(6)
The "ILED-MAX" equation (eq. 1) is obtained from combining the ROUT equation (eq. 2) with the kHR equation (eq. 3)
and solving for ILEDx. Maximum LED current is highly dependent on minimum input voltage and LED forward
voltage. Output current capability can be increased by raising the minimum input voltage of the application, or by
selecting an LED with a lower forward voltage. Excessive power dissipation may also limit output current
capability of an application.
Total Output Current Capability
The maximum output current that can be drawn from the LM27966 is 180mA. Each driver bank has a maximum
allotted current per Dx sink that must not be exceeded.
MAXIMUM Dx CURRENT
30mA
12
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The 180mA load can be distributed in many different configurations. Special care must be taken when running
the LM27966 at the maximum output current to ensure proper functionality.
PARALLEL CONNECTED AND UNUSED OUTPUTS
Outputs D1-5 may be connected together to drive one or two LEDs at higher currents. In such a configuration, all
five parallel current sinks (Main Display) of equal value can drive a single LED. The LED current programmed for
Main Display should be chosen so that the current through each of the outputs is programmed to 20% of the total
desired LED current. For example, if 60mA is the desired drive current for a single LED, RSET should be selected
such that the current through each of the current sink inputs is 12mA.
Connecting the outputs in parallel does not affect internal operation of the LM27966 and has no impact on the
Electrical Characteristics and limits previously presented. The available diode output current, maximum diode
voltage, and all other specifications provided in the Electrical Characteristics table apply to this parallel output
configuration, just as they do to the standard 5-LED application circuit.
Main Display utilizes LED forward voltage sensing circuitry on each Dxx pin to optimize the charge-pump gain for
maximum efficiency. Due to the nature of the sensing circuitry, it is not recommended to leave any of the Dx (D1D4) pins unused if either diode bank is going to be used during normal operation. Leaving Dx pins unconnected
will force the charge-pump into 1.5× mode over the entire VIN range negating any efficiency gain that could be
achieve by switching to 1× mode at higher input voltages.
If D5 is not used, it is recommended that the driver pin be grounded and the general purpose register bit EN-D5
be set to 0 to ensure proper gain transitions.
Care must be taken when selecting the proper RSET value. The current on any Dx pin must not exceed the
maximum current rating for any given current sink pin.
POWER EFFICIENCY
The efficiency of LED drivers is commonly taken to be the ratio of power consumed by the LEDs (PLED) to the
power drawn at the input of the part (PIN). With a 1.5x/1x charge pump, the input current is equal to the charge
pump gain times the output current (total LED current). The efficiency of the LM27966 can be predicted as
follows:
PLEDTOTAL = (VLED-MAIN × NMAIN × ILED-MAIN) + (VLED-AUX × ILED-AUX)
PIN = VIN × IIN
PIN = VIN × (GAIN × ILEDTOTAL + IQ)
E = (PLEDTOTAL ÷ PIN)
(7)
(8)
(9)
(10)
It is also worth noting that efficiency as defined here is in part dependent on LED voltage. Variation in LED
voltage does not affect power consumed by the circuit and typically does not relate to the brightness of the LED.
For an advanced analysis, it is recommended that power consumed by the circuit (VIN x IIN) be evaluated rather
than power efficiency.
POWER DISSIPATION
The power dissipation (PDISS) and junction temperature (TJ) can be approximated with the equations below. PIN is
the power generated by the 1.5x/1x charge pump, PLED is the power consumed by the LEDs, TA is the ambient
temperature, and θJA is the junction-to-ambient thermal resistance for the WQFN-24 package. VIN is the input
voltage to the LM27966, VLED is the nominal LED forward voltage, N is the number of LEDs and ILED is the
programmed LED current.
PDISS = PIN - PLEDA
PDISS= (GAIN × VIN × ILEDA ) - (VLEDA × NA × ILEDA) - (VLED × IDAUX)
TJ = TA + (PDISS x θJA)
(11)
(12)
(13)
The junction temperature rating takes precedence over the ambient temperature rating. The LM27966 may be
operated outside the ambient temperature rating, so long as the junction temperature of the device does not
exceed the maximum operating rating of 100°C. The maximum ambient temperature rating must be derated in
applications where high power dissipation and/or poor thermal resistance causes the junction temperature to
exceed 100°C.
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LM27966
SNVS448B – JULY 2006 – REVISED MAY 2013
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THERMAL PROTECTION
Internal thermal protection circuitry disables the LM27966 when the junction temperature exceeds 170°C (typ.).
This feature protects the device from being damaged by high die temperatures that might otherwise result from
excessive power dissipation. The device will recover and operate normally when the junction temperature falls
below 165°C (typ.). It is important that the board layout provide good thermal conduction to keep the junction
temperature within the specified operating ratings.
CAPACITOR SELECTION
The LM27966 requires 4 external capacitors for proper operation (C1 = C2 = 1µF, CIN = COUT = 1µF). Surfacemount multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and have very
low equivalent series resistance (ESR <20mΩ typ.). Tantalum capacitors, OS-CON capacitors, and aluminum
electrolytic capacitors are not recommended for use with the LM27966 due to their high ESR, as compared to
ceramic capacitors.
For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with
the LM27966. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value over
temperature (X7R: ±15% over -55°C to 125°C; X5R: ±15% over -55°C to 85°C).
Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the
LM27966. Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%, 20%) and vary significantly over temperature (Y5V: +22%, -82% over -30°C to +85°C range; Z5U: +22%, -56%
over +10°C to +85°C range). Under some conditions, a nominal 1µF Y5V or Z5U capacitor could have a
capacitance of only 0.1µF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet
the minimum capacitance requirements of the LM27966.
The minimum voltage rating acceptable for all capacitors is 6.3V. The recommended voltage rating for the input
and output capacitors is 10V to account for DC bias capacitance losses.
PCB LAYOUT CONSIDERATIONS
The WQFN is a leadframe based Chip Scale Package (CSP) with very good thermal properties. This package
has an exposed DAP (die attach pad) at the center of the package measuring 2.6mm x 2.5mm. The main
advantage of this exposed DAP is to offer lower thermal resistance when it is soldered to the thermal land on the
PCB. For PCB layout, National highly recommends a 1:1 ratio between the package and the PCB thermal land.
To further enhance thermal conductivity, the PCB thermal land may include vias to a ground plane. For more
detailed instructions on mounting WQFN packages, please refer to Application Note AN-1187.
14
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REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
LM27966SQ/NOPB
ACTIVE
Package Type Package Pins Package
Drawing
Qty
WQFN
RTW
24
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-30 to 85
L27966S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM27966SQ/NOPB
Package Package Pins
Type Drawing
WQFN
RTW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
178.0
12.4
Pack Materials-Page 1
4.3
B0
(mm)
K0
(mm)
P1
(mm)
4.3
1.3
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM27966SQ/NOPB
WQFN
RTW
24
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RTW0024A
SQA24A (Rev B)
www.ti.com
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