Memory Module Specifications

Memory Module Specifications

KVR667D2S4F5/2GI

2GB 256M x 72-Bit PC2-5300

CL5 ECC 240-Pin FBDIMM

Description:

This document describes ValueRAM's 2GB (256M x 72-bit) PC2-5300 CL5 SDRAM (Synchronous DRAM) "fully buffered" ECC "single rank" (Intel ® Compatibility Tested) memory module. This module is based on eighteen 256M x 4-bit 667MHz DDR2 FBGA components. The module also includes an AMB device (Advanced Memory Buffer).

The electrical and mechanical specifications are as follows:

Feature:

· FBDIMM Module: 240-pin

· JEDEC Standard: R/C H

· Memory Organization: 2 rank of x4 devices

· DDR2 DRAM Interface: SSTL_18

· DDR2 Speed Grade: 667 Mbps

· CAS Latency: 5-5-5

· Module Bandwidth: 5.3 GB/s

· FBDIMM Channel Peak Throughput: 8.0 GB/s

· DRAM: VDD = VDDQ = 1.8V

· AMB: VCC = VCCFBD = 1.5V

· EEPROM: VDDSPD = 3.3V (typical)

· Heat Spreader: FDHS

· PCB Height: 30.35mm, double-side

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T E C H N O L O G Y

DDR2 240-pin FBDIMM Pinout:

Pin

#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

22

23

24

25

26

27

28

29

30

Front

Side

V

DD

V

SS

V

CC

V

CC

V

SS

V

TT

VID1

V

DD

V

DD

V

SS

V

CC

V

CC

V

DD

V

SS

V

DD

V

DD

PN1

V

SS

PN2

PN2

V

SS

PN0

PN0

V

SS

PN1

Pin

#

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

18 V

SS

138

19 RFU ** 139

20 RFU ** 140

21 V

SS

141

142

143

144

145

146

147

148

149

150

Back

Side

V

DD

V

SS

V

CC

V

CC

V

SS

V

TT

VID0

V

DD

V

DD

V

SS

V

CC

V

CC

V

DD

V

SS

V

DD

V

DD

SN1

V

SS

SN2

SN2

V

SS

V

SS

RFU **

RFU **

V

SS

SN0

SN0

V

SS

SN1

Pin

#

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

17 RESET 137 DNU/M_Test 47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

Side

PN3

PN3

V

SS

PN4

PN4

V

SS

PN5

PN5

V

SS

PN13

PN13

V

SS

V

SS

RFU*

RFU*

V

SS

V

SS

PN12

PN12

V

SS

PN6

PN6

V

SS

PN7

PN7

V

SS

PN8

PN8

V

SS

PN9

Pin

#

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

Side

SN3

SN3

V

SS

SN4

SN4

V

SS

SN5

SN5

V

SS

SN13

SN13

V

SS

V

SS

RFU*

RFU*

V

SS

V

SS

SN12

SN12

V

SS

SN6

SN6

V

SS

SN7

SN7

V

SS

SN8

SN8

V

SS

SN9

Pin

#

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

Front

Side

PN9

V

SS

PN10

PN10

V

SS

PN11

PN11

V

SS

V

SS

PS0

PS0

V

SS

PS1

PS1

V

SS

PS2

PS2

V

SS

PS3

PS3

V

SS

PS4

PS4

V

SS

V

SS

RFU*

RFU*

V

SS

V

SS

PS9

Pin

181

182

183

184

185

186

187

188

KEY

#

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

Back

Side

SN9

V

SS

SN10

SN10

V

SS

SN11

SN11

V

SS

V

SS

SS0

SS0

V

SS

SS1

SS1

V

SS

SS2

SS2

V

SS

SS3

SS3

V

SS

SS4

SS4

V

SS

V

SS

RFU*

RFU*

V

SS

V

SS

SS9

Pin

#

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

Front

Side

PS9

V

SS

PS5

PS5

V

SS

PS6

PS6

V

SS

PS7

PS7

V

SS

PS8

V

SS

V

DD

V

DD

V

DD

V

SS

V

DD

V

DD

V

TT

SA2

SDA

SCL

Pin

#

211

212

213

214

215

216

217

218

219

220

221

222

PS8

V

SS

223

224

RFU ** 225

RFU ** 226

V

SS

V

DD

V

DD

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

Side

SS9

V

SS

SS5

SS5

V

SS

SS6

SS6

V

SS

SS7

SS7

V

SS

SS8

SS8

V

SS

RFU **

RFU **

V

SS

SCK

SCK

V

SS

V

DD

V

DD

V

DD

V

SS

V

DD

V

DD

V

TT

VDDSPD

SA0

SA1

90 210

RFU = Reserved Future Use.

* These pin positions are reserved for forwarded clocks to be used in future module implementations

** These pin positions are reserved for future architecture flexibility

1) The following signals are CRC bits and thus appear out of the normal sequence: PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN13,

PS9/PS9, SS9/SS9

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DIMM Connector Pin Description:

Pin Name

SCK

SCK

PN[13:0]

PN[13:0]

PS[9:0]

PS[9:0]

SN[13:0]

SN[13:0]

SS[9:0]

SS[9:0]

SCL

SDA

SA[2:0]

VID[1:0]

RESET

V

RFU

V

V

V

CC

DD

TT

DDSPD

V

SS

DNU/M_Test

Pin Description

System Clock Input, positive line 1

System Clock Input, negative line 1

Primary Northbound Data, positive lines

Primary Northbound Data, negative lines

Primary Southbound Data, positive lines

Primary Southbound Data, negative lines

Secondary Northbound Data, positive lines

Secondary Northbound Data, negative lines

Secondary Southbound Data, positive lines

Secondary Southbound Data, negative lines

Serial Presence Detect (SPD) Clock Input

SPD Data Input / Output

SPD Address Inputs, also used to select the DIMM number in the AMB

Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs

VID[0] is V

DD

value: OPEN = 1.8 V, GND = 1.5 V; VID[1] is V

CC

value: OPEN = 1.5 V, GND = 1.2 V

AMB reset signal

Reserved for Future Use

2

AMB Core Power and AMB Channel Interface Power (1.5 Volt)

DRAM Power and AMB DRAM I/O Power (1.8 Volt)

DRAM Address/Command/Clock Termination Power (V

DD

/2)

SPD Power

Ground

The DNU/M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module. It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time.

1

Total

1. System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency

2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility

Count

1

1

10

14

14

14

14

10

1

1

10

10

3

2

4

1

80

1

16

8

24

1

240

T E C H N O L O G Y

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Functional Block Diagram:

DQ32

DQ33

DQ34

DQ35

DQS5

DQS5

DQ40

DQ41

DQ42

DQ43

DQS6

DQS6

DQ48

DQ49

DQ50

DQ51

DQS7

DQS7

DQ56

DQ57

DQ58

DQ59

DQS8

DQS8

VSS

S0

DQS0

DQS0

DQ0

DQ1

DQ2

DQ3

DQS1

DQS1

DQ8

DQ9

DQ10

DQ11

DQS2

DQS2

DQ16

DQ17

DQ18

DQ19

DQS3

DQS3

DQ24

DQ25

DQ26

DQ27

DQS4

DQS4

PN0-PN13

PN0-PN13

PS0-PS9

PS0-PS9

DQ0-DQ63

CB0-CB7

DQS0-DQS17

DQS0-DQS17

SCL

SDA

SA1-SA2

SA0

RESET

SCK/SCK

CB0

CB1

CB2

CB3

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D0

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D1

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D2

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D3

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D4

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D5

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D6

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D7

A

M

B

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D8

SN0-SN13

SN0-SN13

SS0-SS9

SS0-SS9

S0 -> CS (all SDRAMs)

CKE0 -> CKE (all SDRAMs)

ODT -> ODT (all SDRAMs)

BA0-BA2 (all SDRAMs)

A0-A15 (all SDRAMs)

RAS (all SDRAMs)

CAS (all SDRAMs)

WE (all SDRAMs)

CK/CK (all SDRAMs)

DQS9

DQS9

DQ4

DQ5

DQ6

DQ7

DQS10

DQS10

DQ36

DQ37

DQ38

DQ39

DQS14

DQS14

DQ44

DQ45

DQ46

DQ47

DQS15

DQS15

DQ12

DQ13

DQ14

DQ15

DQS11

DQS11

DQ20

DQ21

DQ22

DQ23

DQS12

DQS12

DQ28

DQ29

DQ30

DQ31

DQS13

DQS13

DQ52

DQ53

DQ54

DQ55

DQS16

DQS16

DQ60

DQ61

DQ62

DQ63

DQS17

DQS17

CB4

CB5

CB6

CB7

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D9

CS DQS DQS

D10

CS DQS DQS

D11

CS DQS DQS

D12

CS DQS DQS

D13

CS DQS DQS

D14

CS DQS DQS

D15

CS DQS DQS

D16

SCL

Serial PD

WP A0 A1 A2

SA0 SA1 SA2

SDA

V

TT

V

CC

V

DDSPD

V

DD

Terminators

AMB

SPD, AMB

D0-D17, AMB

V

REF

V

SS

All address/command/control/clock

D0-D17

D0-D17,SPD,

AMB

V

TT

DM

I/O 0

I/O 1

I/O 2

I/O 3

CS DQS DQS

D17

Notes:

1 . DQ-to-I/O wiring may be changed within a nibble.

2.

There are two physical copies of each address/command/control/clock

T E C H N O L O G Y

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T E C H N O L O G Y

Architecture:

Advanced Memory Buffer Pin Description:

Pin Name

SCK

SCK

PN[13:0]

PN[13:0]

PS[9:0]

PS[9:0]

SN[13:0]

SN[13:0]

SS[9:0]

SS[9:0]

FBDRES

Pin Description

FB-DIMM Channel Signals

System Clock Input, positive line

System Clock Input, negative line

Primary Northbound Data, positive lines

Primary Northbound Data, negative lines

Primary Southbound Data, positive lines

Primary Southbound Data, negative lines

Secondary Northbound Data, positive lines

Secondary Northbound Data, negative lines

Secondary Southbound Data, positive lines

Secondary Southbound Data, negative lines

To an external precision calibration resistor connected to Vcc

DDR2 Interface Signals

Count

99

175

DQS[8:0]

DQS[8:0]

Data Strobes, positive lines

Data Strobes, negative lines

DQS[17:9]/DM[8:0] Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8 DRAM on writes.

DQS[17:9] Data Strobes (x4 DRAM only), negative lines

DQ[63:0] Data

CB[7:0] Checkbits

A[15:0]A, A[15:0]B Addresses. A10 is part of the pre-charge command

BA[2:0]A, BA[2:0]B Bank Addresses

RASA, RASB Part of command, with CAS, WE, and CS[1:0].

CASA, CASB Part of command, with RAS, WE, and CS[1:0].

WEA, WEB

ODTA, ODTB

Part of command, with RAS, CAS, and CS[1:0].

On-die Termination Enable

CKE[1:0]A, CKE[1:0]B Clock Enable (one per rank)

CS[1:0]A, CS[1:0]B Chip Select (one per rank)

CLK[3:0]

CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs. CLK[3:2] should be output disabled when not in use.

4

4

6

2

2

2

2

4

9

9

9

9

64

8

32

CLK[3:0]

DDRC_C14

DDRC_B18

DDRC_C18

DDRC_B12

Negative lines for CLK[3:0]

DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18.

DDR Compensation: Resistor connected to common return pin DDRC_C14

DDR Compensation: Resistor connected to common return pin DDRC_C14

DDR Compensation: Resistor connected to V

SS

1

1

4

1

1

14

14

10

10

1

1

1

14

14

10

10

DDRC_C12 DDR Compensation: Resistor connected to V

DD

1

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Advanced Memory Buffer Pin Description:

SCL

SDA

SA[2:0]

PLLTSTO

VCCAPLL

VSSAPLL

TEST_pin#

TESTLO_pin#

BFUNC

RESET

NC

RFU

V

CC

V

CCFBD

V

DD

V

DDSPD

V

SS

SPD Bus Interface Signals

Serial Presence Detect (SPD) Clock Input

SPD Data Input / Output

SPD Address Inputs, also used to select the DIMM number in the AMB

Miscellaneous Signals

PLL Clock Observability Output

Analog VCC for the PLL. Tied with low pass filter to VCC.

Analog VSS for the PLL. Tied to ground on the AMB die. Do not tie to ground on the DIMM.

Leave floating on the DIMM

Tie to ground on the DIMM

2

Tie to ground to set functionality as “buffer on DIMM.”

AMB reset signal

No connect. Many NC are connected to VDD on the DIMM, to lower the impedance of the VDD power islands.

Reserved for Future Use

Power/Ground Signals

AMB Core Power (1.5 Volt)

AMB Channel I/O Power (1.5 Volt)

AMB DRAM I/O Power (1.8 Volt)

SPD Power (3.3 Volt)

Ground

Total

System Clock Signals SCK and SCK switch at one half the DRAM CK/CK frequency.

5

1

1

3

163

5

1

1

1

1

1

6

129

18

213

24

8

24

1

156

655

T E C H N O L O G Y

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Page 6

Package Dimensions:

AMB

Advanced Memory Buffer

T E C H N O L O G Y

(Units = millimeters)

0.346 (8.8)

MAX with heat sink

Units: inches (millimeters)

0.054 (1.37)

0.046 (1.17)

45°x 0.0071(0.18)

0.047 (1.19)

0.042 (1.06)

Detail A

0.042 (1.06)

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