512MB DDR SDRAM SoDIMM
Data Sheet
512MB DDR
Features:
SDN06464D1BJ1SA-xx(W)R

512MByte in FBGA Technology







RoHS compliant
Options:

Data Rate / Latency
DDR 400 MT/s CL3
DDR 333 MT/s CL2.5

Module density
512MB with 8 dies and 1 rank

Standard Grade
W-Grade
(TA)
(TA)
Marking
-50
-60
0°C to 70°C
-40°C to 85°C
Environmental Requirements:
 Operating temperature (ambient)
Standard Grade
0°C to 70°C
W-Grade
-40°C to 85°C



200-pin 64-bit DDR1 Small Outline Dual-In-Line Double
Data Rate Synchronous DRAM module
Module organization: single rank 64M x 64
VDD = 2.5V ±0.2V, VDDQ 2.5V ±0.2V
VDD = 2.6V ±0.1V, VDDQ 2.6V ±0.1V (DDR400)
2.5V I/O ( SSTL_2 compatible)
Serial Presence Detect with EEPROM
Gold-contact pads
This module is fully pin and functional compatible to the
JEDEC PC-3200 spec. and JEDEC- Standard MO-224.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]

*) The refresh rate has to be doubled when 85°C<TC<95°C*)

28.11.2012
SDRAM SoDIMM
200 PIN SO-DIMM

Rev.1.1
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C






DDR1 - SDRAM component Samsung K4H510838J
64Mx8 DDR1 SDRAM in 60-ball FBGA package
Internal, pipelined double-data-rate (DDR)
2n pre-fetch architecture
DLL to align DQ and DQS transitions with CK
Bidirectional data strobe (DQS) transmitted/received with
data, source-synchronous data capture
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
Four internal banks for concurrent operation
Data mask (DM) for masking write data
Programmable burst length: 2,4 or 8
Adjustable data-output drive strength
Auto Refresh (CBR) and Self Refresh, 8k Refresh every
64ms







Figure: mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
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Page 1
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Data Sheet
Rev.1.1
28.11.2012
This Swissbit module family is industry standard 200-pin 8-byte Double Date rate synchronous SDRAM Small
Outline Dual-In-line Memory Modules (So-DIMMs), which are organized as x64 high speed memory arrays
designed for use in non-parity applications. These So-DIMMs are assembled in FBGA Technology. The passive
devices and the EEPROM are SMD components.
2
The So-DIMMs use serial presence detects (SPD) implemented via serial EEPROM using the two-pin-I C protocol.
The first 128 bytes are utilized by the So-DIMM manufacturer and the second 128 bytes are available to the end
user.
All Swissbit DDR1 So-DIMMs provide a high performance, flexible 8-byte interface in a 67.6 mm long footprint.
All modules of the extended temperature grade have seen special tests during the manufacturing process to
ensure proper operation according to the field of operation as stated in the environmental conditions.
Module Configuration
Organization
64M x 64
DDR SDRAMs
used
Row
Addr.
Bank
Select
Col.
Addr.
Refresh
8 x 64M x 8
13
BA0, BA1
11
8k
Module Dimensions
in mm
67.60 x 25,4 x 3.80 max
Product Spectrum
Part Number
Module Density
Transfer Rate
Clock Cycle/Data bit rate
Latency
SDN06464D1BJ1SA-50[W]R
512MB
3.2 GB/s
5.0ns/400MT/s
3.0-3-3
SDN06464D1BJ1SA-60[W]R
512MB
2.7 GB/s
6.0ns/333MT/s
2.5-3-3
Pin Name
A0-9, A11 – A12
Address Inputs
A10/AP
Address Input/Autoprecharge
BA0, BA1
Bank Selects
DQ0 – DQ63
Data Input/Output
DM0-DM7
Data Masks
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Read / Write Enable
CKE0
Clock Enable
CK0
Clock Inputs, positive line
CK0#
Clock Inputs, negative line
DQS0- DQS7
Data strobes
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Page 2
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Data Sheet
Rev.1.1
S0#
Chip Select
VDD
Power (2.5V± 0.2V)
VDDQ
Power (2.5V±0.2V)
VDDID
VDD, VDDQ level detection
VDDSPD
SPD Power
VREF
Input/Output Reference
Vss
Ground
SCL
Clock for Serial Presence Detect
SDA
Serial Data Out for Serial Presence Detect
NC
No Connection
28.11.2012
Pin Configuration
PIN #
Front Side
PIN #
Back Side
PIN #
Front Side
PIN #
Back Side
1
VREF
2
VREF
101
A9
102
A8
3
VSS
4
VSS
103
VSS
104
VSS
5
DQ0
6
DQ4
105
A7
106
A6
7
DQ1
8
DQ5
107
A5
108
A4
9
VDD
10
VDD
109
A3
110
A2
11
DQS0
12
DM0
111
A1
112
A0
13
DQ2
14
DQ6
113
VDD
114
VDD
15
VSS
16
VSS
115
A10/AP
116
BA1
17
DQ3
18
DQ7
117
BA0
118
RAS#
19
DQ8
20
DQ12
119
WE#
120
CAS#
21
VDD
22
VDD
121
S0#
122
NC/S1#
23
DQ9
24
DQ13
123
NC/(A13)
124
NC
25
DQS1
26
DM1
125
VSS
126
VSS
27
VSS
28
VSS
127
DQ32
128
DQ36
29
DQ10
30
DQ14
129
DQ33
130
DQ37
31
DQ11
32
DQ15
131
VDD
132
VDD
33
VDD
34
VDD
133
DQS4
134
DM4
35
CK0
36
VDD
135
DQ34
136
DQ38
37
CK0#
38
VSS
137
VSS
138
VSS
39
VSS
40
VSS
139
DQ35
140
DQ39
41
DQ16
42
DQ20
141
DQ40
142
DQ44
43
DQ17
44
DQ21
143
VDD
144
VDD
45
VDD
46
VDD
145
DQ41
146
DQ45
47
DQS2
48
DM2
147
DQS5
148
DM5
49
DQ18
50
DQ22
149
VSS
150
VSS
51
VSS
52
VSS
151
DQ42
152
DQ46
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Page 3
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Data Sheet
PIN #
Front Side
PIN #
Back Side
Rev.1.1
PIN #
Front Side
PIN #
28.11.2012
Back Side
53
DQ19
54
DQ23
153
DQ43
154
DQ47
55
DQ24
56
DQ28
155
VDD
156
VDD
57
VDD
58
VDD
157
VDD
158
CK1#
59
DQ25
60
DQ29
159
VSS
160
CK1
61
DQS3
62
DM3
161
VSS
162
VSS
63
VSS
64
VSS
163
DQ48
164
DQ52
65
DQ26
66
DQ30
165
DQ49
166
DQ53
67
DQ27
68
DQ31
167
VDD
168
VDD
69
VDD
70
VDD
169
DQS6
170
DM6
71
NC/CB0
72
NC/(CB4)
171
DQ50
172
DQ54
73
NC/CB1
74
NC/(CB5)
173
VSS
174
VSS
75
VSS
76
VSS
175
DQ51
176
DQ55
77
NC/(DQS8)
78
NC/(DM8)
177
DQ56
178
DQ60
79
NC/(CB2)
80
NC/(CB6)
179
VDD
180
VDD
81
VDD
82
VDD
181
DQ57
182
DQ61
83
NC/(CB3)
84
NC/(CB7)
183
DQS7
184
DM7
85
NC
86
NC/(RESET)
185
VSS
186
VSS
87
VSS
88
VSS
187
DQ58
188
DQ62
89
NC/(CK2)
90
VSS
189
DQ59
190
DQ63
91
NC/(CK2#)
92
VDD
191
VDD
192
VDD
93
VDD
94
VDD
193
SDA
194
SA0
95
NC/(CKE1)
96
CKE0
195
SCL
196
SA1
97
NC
98
NC/(BA2)
197
VDD_SPD
198
SA2
99
A12
100
A11
199
VDD_ID
200
NC
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Page 4
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Data Sheet
Rev.1.1
28.11.2012
FUNCTIONAL BLOCK DIAGRAMM 512MB DDR SDRAM SODIMM 1RANK; NON-ECC
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Page 5
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Data Sheet
Rev.1.1
28.11.2012
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤1.35V
SYMBOL
VDD
VDDQ
VREF
VTT
VIH (DC)
VIL (DC)
MIN
2.3
2.3
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
-0.3
MAX
2.7
2.7
0.51x VDDQ
VREF + 0.04
VDD + 0.3
VREF – 0.15
UNITS
V
V
V
V
V
V
II
-16
16
µA
IOZ
-40
40
µA
IOH
-16.8
-
mA
IOL
16.8
-
mA
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQS are disabled; 0V ≤ VOUT ≤ VDDQ)
OUTPUT LEVELS:
High Current (VOUT = VDDQ-0.373V,minimum VREF,
minimum VTT )
Low Current (VOUT =0.373V, maximum VREF,
maximum VTT )
AC INPUT OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
SYMBOL
VIH (AC)
VIL (AC)
VREF(AC)
MIN
VREF + 0.310
0.49 x VDDQ
MAX
VREF - 0.310
0.51x VDDQ
UNITS
V
V
V
MAX
5.0
27.0
27.0
14.0
27.0
UNITS
pF
pF
pF
pF
pF
CAPACITANCE
PARAMETER
Input/Output Capacitance: DQ, DQS
Input Capacitance: Command and Address
Input Capacitance: /S 0,1
Input Capacitance: CK, /CK
Input Capacitance: CKE
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SYMBOL
C10
C11
C11
C12
C13
MIN
4.0
18.0
18.0
10.0
18.0
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Page 6
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Data Sheet
Rev.1.1
28.11.2012
IDD Specifications AND CONDITIONS
(0°C ≤ TA ≤ + 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
Parameter
& Test Condition
OPERATING CURRENT; *) : One device bank; ActivePrecharge;
tRC= tRC (Min); tCK = tCK (Min); DQ, DM and DQS inputs changing
once per clock cycle; Address and control inputs changing once
every two clock cycles
OPERATING CURRENT;*)
One device bank; Active-Read-Precharge;
Burst = 2; tRC= tRC (Min);
tCK = tCK (Min);IOUT = 0mA;
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT;
All device banks idle;
Power-down mode;
tCK = tCK (Min); CKE = (LOW)
IDLE STANDBY CURRENT; CS# = HIGH; All device banks
idle;
tCK = tCK (Min); CKE= HIGH; Address and other control inputs
changing once per clock cycle.
VIN = VREF for DQ, DQS, and DM
PRECHARGE QUIET STANDBY CURRENT;
CS# > VIH(min); All banks idle;
CKE >= VIH(min); tCK=6ns for DDR333, 5ns for DDR400;
Address and other control iputs stable at >=VIH(min) or =<
VIL(max); VIN=VREF for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT; One device
bank active; Power-down mode; tCK = tCK (Min);CKE = LOW
ACTIVE STANDBY CURRENT; CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge; tRC= tRAS (Max); tCK = tCK
(Min); DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
OPERATING CURRENT;
Burst = 2; Reads; Continous burst; One bank active; Address
and control inputs changing once per clock cycle; tCK = tCK
(Min);
IOUT = 0mA
OPERATING CURRENT; Burst = 2; Writes; Continuous burst;
One device bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (Min); DQ, DM, and DQS inputs
changing twice per clock cycle
AUTO REFRESH CURRENT; tRC = tRC (Min)
SELF REFRESH CURRENT; CKE ≤ 0.2V;External clock on;
Tck=6ns for DDR333, 5ns for DDR400
OPERATING CURRENT – FOUR BANK OPERATION; Four
bank interleaving with BL=4
Symbol
max.
3200-3.033
2700-2.533
Unit
IDD0
520
480
mA
IDD1
600
560
mA
IDD2P
40
40
mA
IDD2F
184
184
mA
IDD2Q
160
160
mA
IDD3P
120
120
mA
IDD3N
280
280
mA
IDD4R
800
720
mA
IDD4W
720
640
mA
IDD5
960
800
mA
IDD6(normal)
40
40
mA
IDD6(Low power)
24
24
mA
IDD7A
1600
1440
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
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Page 7
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Data Sheet
Rev.1.1
28.11.2012
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TA ≤ + 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9
AC CHARACTERISTICS
PARAMETER
SYMBOL
Access window of DQS CK/CK#
tAC
CK high-level width
tCH
CK low-level width
tCL
Clock cycle time CL=2.0
tCK (2.0)
CL=2.5
tCK(2.5)
CL=3.0
tCK (3.0)
DQ and DM input hold time relative
tDH
to DQS
DQ and DM input setup time relative
tDS
to DQS
DQ and DM input pulse width
tDIPW
( for each input )
Access window of DQS from
tDQSCK
CK/CK#
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS –DQ skew, DQS to last DQ
tDQSQ
valid, per group, per access
Write command to first DQS latching
tDQSS
transition
DQS falling edge to CK rising- setup
tDSS
time
DQS falling edge from CK risingtDSH
hold time
Half clock period
tHP
Data-out high-impedance window
from CK/CK#
Data-out low-impedance window
from CK/CK#
Address and control input hold time
( fast slew rate )
Address and control input setup time
( fast slew rate )
Address and control input hold time
( slow slew rate )
Address and control input setup time
( slow slew rate )
LOAD MODE REGISTER command
cycle time
Adress and control input pulse width
(for each input)
DQ-DQS hold, DQS to first DQ to go
non-valid, per access
Data hold skew factor
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3200-3.0-3-3
MIN
MAX
-0.65
+0.65
0.45
0.55
0.45
0.55
7.5
13.0
6.0
13.0
5.0
13.0
2700-2.5-3-3
MIN
MAX
-0.65
+0.65
0.45
0.55
0.45
0.55
7.5
13.0
6.0
13.0
0.40
-
0.45
-
ns
0.40
-
0.45
-
ns
1.75
-
1.75
-
ns
-0.6
+0.6
-0.6
+0.6
ns
0.35
0.35
-
0.35
0.35
-
tCK
tCK
0.40
-
0.45
ns
0.72
1.28
0.75
1.25
tCK
0.2
-
0.2
-
tCK
0.2
-
0.2
-
tCK
tch,
tcl
-
tch,
tcl
-
ns
tHZ
-0.7
+0.7
-0.7
+0.7
ns
tLZ
-0.7
+0.7
-0.7
+0.7
ns
tIHF
0.6
-
0.75
-
ns
tISF
0.6
-
0.75
-
ns
tIHS
0.7
-
0.8
-
ns
tISS
0.6
-
0.8
-
ns
tMRD
10
-
12
-
ns
tIPW
2.2
-
2.2
-
ns
tQH
tQHS
tHP - tQHS
-
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0.5
tHP - tQHS
-
0.6
Unit
ns
tCK
tCK
ns
ns
ns
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Page 8
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Data Sheet
AC CHARACTERISTICS
PARAMETER
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto
precharge
command
ACTIVE to ACTIVE/AUTO
REFRESH
command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b
command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command
delay
Data valid output window
REFRESH to REFRESH command
interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
SYMBOL
tRAS
tRAP
3200-3.0-3-3
MIN
MAX
40
70.000
Rev.1.1
2700-2.5-3-3
MIN
MAX
42
70.000
28.11.2012
Unit
ns
15
-
15
-
ns
55
-
60
-
ns
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
70
15
15
0.9
0.4
1.1
0.6
72
18
18
0.9
0.4
1.1
0.6
10
-
12
-
ns
ns
ns
tCK
tCK
ns
tWPREH
tWPRES
tWPST
tWR
tWTR
0.25
0
0.4
15
0.6
-
0.25
0
0.4
15
0.6
-
2
-
1
-
tRC
N/A
tREFC
tREFI
85 °C < TCASE ≤ 95°C
tREFI (IT)
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ
command
Exit SELF REFRESH to READ
command
tVTD
tXSNR
tXSRD
tQH - tDQSQ
tCK
ns
tCK
ns
tCK
tQH - tDQSQ
-
70.3
-
70.3
-
7.8
-
7.8
0
3.9
-
0
3.9
-
70
-
75
-
200
-
200
-
ns
µs
µs
ns
ns
tCK
Note 1: Values for AC timing, IDD, and electrical AC and DC characteristics might have been collected within the
standard temperature range and at nominal reference/supply voltage levels, but the related specifications and
device operation are guaranteed for the full voltage range specified and for the corresponding field of operation
according to the actual temperature grade of the module (extended E, I or W; refer to the environmental conditions
for more details).
Swissbit AG
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Page 9
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Data Sheet
Rev.1.1
28.11.2012
SERIAL PRESENCE-DETECT MATRIX
BYTE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
DESCRIPTION
NUMBER OF SPD BYTES USED
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
NUMBER OF ROW ADDRESSES ON ASSEMBLY
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
NUMBER OF PHYSICAL BANKS ON DIMM
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS (VDDQ)
SDRAM CYCLE TIME, (tCK )
(CAS LATENCY =2.5 (2700, 2100) ; CL=3* (3200)
SDRAM ACCESS FROM CLOCK, (tAC)
(CAS LATENCY =2.5 (2700, 2100); CL=3* (3200))
MODULE CONFIGURATION TYPE
REFRESH RATE/ TYPE
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK- TO- BACK
RANDOM COLUMN ACCESS
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: GENERAL
SDRAM CYCLE TIME, (tCK)
(CAS LATENCY=2(2700, 2100) CL=2,5*(3200))
SDRAM ACCESS FROM CK, (tAC)
(CAS LATENCY=2(2700, 2100) CL=2.5*(3200)
SDRAM CYCLE TIME, (tCK)
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200))
SDRAM ACCESS FROM CK, (tAC)
(CAS LATENCY=1.5(2700, 2100) CL=2*(3200)
MINIMUM ROW PRECHARGE TIME, (tRP)
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)
MINIMUM RAS# TO CAS# DELAY, (tRCD)
MINIMUM RAS# PULSE WIDTH, (tRAS)
MODULE BANK DENSITY
ADDRESS AND COMMAND SETUP TIME, (tIS)
ADDRESS AND COOMAND HOLD TIME, (tIH)
DATA/DATA MASK INPUT SETUP TIME, (tDS)
DATA/DATA MASK INPUT HOLD TIME, (tDH)
RESERVED
MIN ACTIVE AUTO REFRESH TIME (tRC)
MINIMUM AUTO REFRESH TO ACTIVE/
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME (tCKMAX)
SDRAM DEVICE MAX DQS-DQ SKEW TIME
(tDQSQ)
SDRAM DEVICE MAX READ DATA HOLD SKEW FACTOR
(tQHS)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
3200-3.0-3-3
2700-2.5-3-3
0x80
0x08
0x07
0x0D
0x0B
0x01
0x40
0x00
0x04
0x50
0x60
0x65
0x00
0x82
0x08
0x00
0x01
0x0E
0x04
0x1C
0x0C
0x01
0x02
0x20
0xC1
0x60
0x75
0x70
0x75
0x00
0x75
0x00
0x3C
0x28
0x3C
0x28
0x48
0x30
0x48
0x2A
0x80
0x60
0x60
0x40
0x40
0x75
0x75
0x45
0x45
0x00
0x37
0x3C
0x46
0x48
0x28
0x30
0x28
0x2D
0x50
0x55
www.swissbit.com
email: [email protected]
Page 10
of 14
Data Sheet
Rev.1.1
28.11.2012
SERIAL PRESENCE-DETECT MATRIX (continued)
BYTE
46-61
62
63
64
65
66
67
72
73-90
91
92
93
94
95-98
99-127
DESCRIPTION
RESERVED
SPD REVISION
CHECKSUM FOR BYTES 0-62
MANUFACTURER`S JEDEC ID CODE
MANUFACTURER`S JEDEC ID CODE(continued)
MANUFACTURER`S JEDEC ID CODE(continued)
MANUFACTURER`S JEDEC ID CODE(continued)
MANUFACTURING LOCATION
MODULE PART NUMBER (ASCII)
PCB IDENTIFICATION CODE
PCB IDENTIFICATION CODE (continued)
YEAR OF MANUFACTURE IN BCD
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
MANUFACTURER-SPECIFIC DATA (RSVD)
3200-3.0-3-3
2700-2.5-3-3
0x00
0x11
0xAE
0x48
7F
7F
7F
DA
0x01 = CH
0x02 = GE
0x03 = USA
“SDN06464D1BJ1SA-xx”
X
X
X
X
X
X
Part Number Code
S
D
N
064
64
D1
B
J
1
SA
1
2
3
4
5
6
7
8
9
10
-
50
*
R
11
12
13
*RoHs compl.
DDR-400MT/s
Swissbit AG
SDRAM DDR
200 Pin Unbuffered 2.5V
Depth (512MB)
Width
PCB-Type (S1D3E1.00)
Chip Vendor (Samsung)
1 Module Rank
Chip Rev. J
Chip organisation x8
* optional / additional information
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
email: [email protected]
Page 11
of 14
Data Sheet
Rev.1.1
28.11.2012
Revision History
Revision
Changes
Date
1.0
Initial Revision
31.10.2012
1.1
New IDD-Values added, Extended Temperature-Grade (W-Grade) added
20.11.2012
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
email: [email protected]
Page 12
of 14
Data Sheet
Rev.1.1
28.11.2012
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
+41 (0)71 913 03 03
Fax:
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
+49 (0)30 93 69 54 – 0
Fax:
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
1117 E Plaza Drive Unit E Suites 105/205
Eagle, ID 83616
USA
Phone:
+1 208 258-6254
Fax:
+1 208 938-4525
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
+81 3 5356 3511
Fax:
+81 3 5356 3512
________________________________
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
email: [email protected]
Page 13
of 14
Data Sheet
Rev.1.1
28.11.2012
Declaration of Conformity
We
Manufacturer:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
declare under our sole responsibility that the product
Product Type:
Brand Name:
Product Series:
Part Number:
512MB DDR1 SODIMM
SWISSMEMORY™
DDR1 SODIMM
SDN06464D1BJ1SA-xxxR
to which this declaration relates is in conformity with the following directives:
2002/96/EC Category 3 (WEEE)
following the provisions of Directive
Restriction of the use of certain hazardous substances
2011/65/EU
Swissbit AG, November 2012
Manuela Kögel
Head of Quality Management
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
email: [email protected]
Page 14
of 14
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Swissbit:
SDN06464D1BJ1SA-50WR SDN06464D1BJ1SA-50R
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