512mb ddr2 sdram so-dimm

512mb ddr2 sdram so-dimm
Apacer Memory Product Specification
512MB DDR2 SDRAM SO-DIMM
512MB DDR2 SDRAM SO-DIMM based on 64Mx8, 4Banks, 1.8V DDR2 SDRAM with SPD
Features
( Bandwidth: 5.3 GB/sec )
ΘPerformance range
Part No.
Max Freq. (Clock)
78.92G63.402
333MHz([email protected])
Speed Grade
667 Mbps
‧JEDECstandard 1.8V ± 0.1V Power Supply
‧VDDQ = 1.8V± 0.1V
‧Internal Bank: 8 Bank
‧Posted CAS
‧Programmable CAS Latency: 3, 4, 5
‧Programmable Additive Latency: 0, 1 , 2 , 3 and 4
‧Write Latency(WL) = Read Latency(RL) -1
‧Burst Length: 4 , 8(Interleave/nibble sequential)
‧Programmable Sequential / Interleave Burst Mode
‧Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
‧Off-Chip Driver(OCD) Impedance Adjustment
‧On Die Termination
‧Refresh and Self Refresh
Average Refesh Period 7.8us
‧Serial presence detect with EEPROM
‧Compliance with RoHS
‧Compliance with CE
‧Operating Temperature Rang:
‧Commercial 0°C ≦ TC ≦ 85°C
‧Industrial -40°C ≦ TC ≦ 85°C
‧Refresh: auto-refresh, self-refresh
‧─Average refresh period
7.8us at 0°C ≦ TC ≦ 85°C
3.9us at 85°C ≦ TC ≦ 95°C
Description
This module is 64M bit x 64 x1Bank Double Data Rate SDRAM high density memory modules based on first
generation of 512MB DDR2 SDRAM respectively.
It consists of eight CMOS 64M x 8 bit with 4banks Double Data Rate SDRAMs in 60Ball FBGA packages
mounted on a 200pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR2 SDRAM.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
Apacer Memory Product Specification
Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
VREF
2
VSS
51
DQS2
52
DM2
101
A1
102
A0
151
DQ42
152
DQ46
3
VSS
4
DQ4
53
VSS
54
VSS
103
VDD
104
VDD
153
DQ43
154
DQ47
5
DQ0
6
DQ5
55
DQ18
56
DQ22
105
A10/AP
106
BA1
155
VSS
156
VSS
7
DQ1
8
VSS
57
DQ19
58
DQ23
107
BA0
108
RAS
157
DQ48
158
DQ52
DQ53
9
VSS
10
DM0
59
VSS
60
VSS
109
WE
110
S0
159
DQ49
160
11
DQS0
12
VSS
61
DQ24
62
DQ28
111
VDD
112
VDD
161
VSS
162
VSS
13
14
DQ6
63
CAS
114
ODT0
163
CK1
65
66
115
NC/S1
116
A13
165
NC, TEST
VSS
164
DQ7
DQ29
VSS
113
16
DQ25
VSS
64
15
DQS0
VSS
166
CK1
17
DQ2
18
VSS
67
DM3
68
DQS3
117
VDD
118
VDD
167
DQS6
168
VSS
19
20
DQ12
69
121
122
171
DQS6
VSS
170
72
NC
VSS
169
71
NC/ODT1
VSS
120
DQ13
DQS3
VSS
119
22
NC
VSS
70
21
DQ3
VSS
DM6
VSS
23
DQ8
24
VSS
73
DQ26
74
DQ30
123
DQ32
124
DQ36
173
DQ50
174
DQ54
25
26
DQ31
VSS
125
DQ37
VSS
175
177
DQ51
VSS
176
127
DQ33
VSS
126
77
DQ27
VSS
76
28
DM1
VSS
75
27
DQ9
VSS
178
DQ55
VSS
29
DQS1
30
CK0
79
80
DQS4
130
DQ56
180
DQ60
32
CK0
81
82
131
DQS4
132
DM4
VSS
179
DQS1
NC/CKE1
VDD
129
31
CKE0
VDD
181
DQ57
182
DQ61
33
VSS
34
VSS
83
NC
84
NC
133
VSS
134
DQ38
183
VSS
184
VSS
35
DQ10
36
DQ14
85
86
DQ34
136
DQS7
DQ15
87
88
137
DQ35
138
187
DM7
VSS
186
38
DQ39
VSS
185
DQ11
NC
VDD
135
37
BA2
VDD
188
DQS7
39
VSS
40
VSS
89
A12
90
A11
139
VSS
140
DQ44
189
DQ58
190
VSS
41
VSS
42
VSS
91
A9
92
A7
141
DQ40
142
DQ45
191
DQ59
192
DQ62
DQ63
78
128
172
43
DQ16
44
DQ20
93
A8
94
A6
143
DQ41
144
VSS
193
VSS
194
45
DQ17
46
DQ21
95
VDD
96
VDD
145
VSS
146
DQS5
195
SDA
196
VSS
47
VSS
48
VSS
97
A5
98
A4
147
DM5
148
DQS5
197
SCL
198
SA0
49
DQS2
50
NC
99
A3
100
A2
149
VSS
150
VSS
199
VDDSPD
200
SA1
Pin Description
Pin Name
CK0,CK1
CK0,CK1
CKE0,CKE1
Function
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Pin Name
SDA
SA1,SA0
Function
SPD Data Input/Output
SPD address
DQ0~DQ63
Data Input/Output
RAS
Row Address Strobe
DM0~DM7
Data Masks
CAS
Column Address Strobe
DQS0~DQS7
Data strobes
WE
Write Enable
DQS0~DQS7
Data strobes complement
S0,S1
Chip Selects
TEST
A0~A9, A11~A13
A10/AP
BA0,BA1
ODT0,ODT1
SCL
Logic Analyzer specific test pin (No connect on
So-DIMM)
Address Inputs
VDD
Core and I/O Power
Address Input/Autoprecharge
VSS
Ground
SDRAM Bank Address
VREF
Input/Output Reference
On-die termination control
Serial Presence Detect(SPD) Clock Input
VDDSPD
NC
SPD Power
Spare pins, No connect
Apacer Memory Product Specification
Input/Output Functional Description
Symbol
Type
Function
CK0-CK1
CK0-CK1
Input
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge
of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output
timing for read operations is synchronized to the input clock.
CKE0-CKE1
Input
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refesh mode.
S0-S1
Input
Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but previous operations
continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called “Physical banks”.
RAS, CAS, WE
Input
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
BA0~BA1
Input
Selects which DDR2 SDRAM internal bank is activated.
ODT0~ODT1
Input
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended
Mode Register Set (EMRS).
A0~A9,
A10/AP,
A11~A13
Input
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the
rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the
column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle.
If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low,
autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn
to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of
BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ0~DQ63
In/Out
Data Input/Output pins.
DM0~DM7
Input
The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. In
Read mode, DM lines have no effect.
DQS0~DQS7
DQS0~DQS7
In/Out
The data strobes, associated with one data byte, sourced with data transfers. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read mode,
the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data
window. DQS signals are complements, and timing is relative to the crosspoint of respective
DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals
must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately.
VDD,VDD
SPD,VSS
Supply
Power supplies for core, I/O, Serial Presence Detect, and ground for the module.
SDA
In/Out
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to VDD to act as a pull up.
SCL
Input
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL
to VDD to act as a pull up.
SA0~SA1
Input
Address pins used to select the Serial Presence Detect base address.
TEST
In/Out
The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SODIMMs).
Apacer Memory Product Specification
Functional Block Diagram
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1
DM1
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQS5
DQS5
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQS2
DQS2
DM2
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQS6
DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3
DM3
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQS7
DQS7
DM7
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
NU/ CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
D3
Serial PD
SCL
SDA
WP
A0
SA0
BA0 - BA1
A0 - A13
A1
SA1
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A2
SA2
VDDSPD
Serial PD
VDD/VDDQ
D0 - D7
VREF
VSS
BA0-BA1 : DDR2 SDRAMs D0 - D7
A0-A13 : DDR2 SDRAMs D0 - D7
RAS
RAS : DDR2 SDRAMs D0 - D7
CAS
CAS : DDR2 SDRAMs D0 - D7
CKE0
CKE : DDR2 SDRAMs D0 - D7
WE
ODT0
WE : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D0 - D7
D0 - D7
D0 - D7
CS DQS DQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
* Clock Wiring
Clock
Input
DDR2 SDRAMs
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
1. DQ,DM, DQS/DQS resistors : 22 Ohms " 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms " 5%.
Apacer Memory Product Specification
Physical Dimensions
3.8 mm
max
20.00 mm
30 mm
67.60 mm
SPD
1.1mm
max
1.8 mm
2.7 mm
4.0 mm
0.60 mm
1.00 mm
Left key position :
Reserved
Tolerances:+-0.15mm unless otherwise specified
Right key position :
VDD = VDDQ = 1.8 V
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement