PCS/W-CDMA dual-band MMIC power amplifier

PCS/W-CDMA dual-band MMIC power amplifier
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 9, SEPTEMBER 2002
PCS/W-CDMA Dual-Band MMIC Power Amplifier
With a Newly Proposed Linearizing Bias Circuit
Youn Sub Noh, Student Member, IEEE, and Chul Soon Park, Member, IEEE
Abstract—A personal communications service/wide-band code
division multiple access (PCS/W-CDMA) dual-band monolithic
microwave integrated circuit (MMIC) power amplifier with a
single-chip MMIC and a single-path output matching network is
demonstrated by adopting a newly proposed on-chip linearizer.
The linearizer is composed of the base–emitter diode of an active
bias transistor and a capacitor to provide an RF short at the
base node of the active bias transistor. The linearizer enhances
the linearity of the power amplifier effectively for both PCS and
W-CDMA bands with no additional dc power consumption, and
has negligible insertion power loss with almost no increase in die
area. It improves the input 1-dB gain compression point by 18.5
(20) dB and phase distortion by 6.1 (12.42 ) at an output power
of 28 (28) dBm for the PCS (W-CDMA) band while keeping the
base bias voltage of the power amplifier as designed. A PCS and
W-CDMA dual-band InGaP heterojunction bipolar transistor
MMIC power amplifier with single input and output and no switch
for band selection is embodied by implementing the linearizer and
by designing the amplifier to have broad-band characteristics.
The dual-band power amplifier exhibits an output power of 30
(28.5) dBm, power-added efficiency of 39.5% (36%), and adjacent
channel power ratio of 46 ( 50) dBc at the output power of
28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA)
applications.
Index Terms—Dual band, HBT, linearizer, MMIC, PCS, power
amplifiers, W-CDMA.
I. INTRODUCTION
T
HE POWER amplifier is one of the key components in mobile communication handsets determining the power consumption and, thus, the battery life of the handsets, and has seen
a reduction in module size, supply voltage, and quiescent current. Moreover, in order to accommodate higher data rate and
global roaming around the multistandard communication environments, linearity and multimode/multiband capability are
being highlighted as the most significant issues of power amplifiers for recent mobile handsets.
As a modulation technique, quadrature phase shift keying
(QPSK)/hybrid phase shift keying (HPSK) has been adopted for
personal communications service/wide-band code division multiple access (PCS/W-CDMA) and inevitably has a nonconstant
Manuscript received January 29, 2002; revised April 22, 2002. This work
was supported by the Ministry of Science and Technology of Korea and Korea
Institute of S&T Evaluation and Planning.
Y. S. Noh is with the School of Engineering, Information and Communications University, Yusong, Taejon 305-732, Korea.
C. S. Park is with the School of Engineering, Information and Communications University, Yusong, Taejon 305-732, Korea. He is also with the Electronics
and Telecommunications Research Institute (ETRI), Yusong, Taejon 305-350,
Korea (email: parkcs@icu.ac.kr).
Publisher Item Identifier 10.1109/JSSC.2002.801169.
Fig. 1. Schematic diagram of the two-stage dual-band power amplifier.
envelope, therefore, power amplifiers with high linearity are required in the transmitter system. To obtain both high output
power and low nonlinear distortions, several methods of on-chip
linearization techniques, keeping the bias of the amplifier as designed up to an input power as large as possible, have been reported [1], [2]. These linearization techniques have improved
output power around 0.5 dB, phase distortion by 2.2 , and adjacent channel power ratio (ACPR)/adjacent channel leakage
power ratio (ACLR) around 3.6 dB. Also, the demand for multistandard services requires multimode/multiband power amplifiers with low cost and small size. For multimode/multiband
handsets applications, several dual-band power amplifier architectures including one and two amplifier solutions with one or
two input, two separate output matching networks have been
proposed [3]. For compact multimode/multiband handset, the
final goal of the power amplifier is to accomplish one amplifier
with one input/output matching network.
In this work, we propose a new linearization technique applicable to both PCS and W-CDMA bands for a InGaP heterojunction bipolar transistor (HBT) monolithic microwave integrated
circuit (MMIC) power amplifier, and devised a PCS/W-CDMA
dual-band MMIC power amplifier of single-input and singleoutput architecture without any modification for switching from
band to band. The linearized amplifier improves the input 1-dB
gain compression point by 18.5 (20) dB, phase distortion by 6.1
(12.42 ) at the output power of 28 (28) dBm, and ACPR by up
to 15.3 (15.7) dB for the PCS (W-CDMA) band. This remarkable improvement was realized by controlling the base bias of
the amplifier simply by adding a linearizing shunt capacitor to
a novel active bias circuit, and more importantly without almost
any increase in chip size.
0018-9200/02$17.00 © 2002 IEEE
NOH AND PARK: PCS/W-CDMA DUAL-BAND MMIC POWER AMPLIFIER
Fig. 2. Simulated V
of HBT1 and insertion power to the linearizer as a
function of the input power to the two-stage power amplifier.
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Fig. 3. Simulated gain compression and phase deviation of the two-stage
power amplifier.
II. LINEARIZATION: AMPLIFIER BIAS COMPENSATION
For highly linear power amplifiers, it is necessary to compensate AM–AM and AM–PM distortions that provide negative
amplitude and positive phase deviations with the increase
of input power. To compensate the distortions effectively,
we devised a new on-chip linearizer that is composed of the
base–emitter diode of an active bias transistor (HBT2) and a
capacitor Cb for shorting the inserted RF signal (Fig. 1). The
linearizing shunt capacitor with the base–emitter diode of the
transistor (HBT2) compensates the decreased base bias voltage
of the RF amplifier (HBT1) caused by the increased input
power level according to the following procedures.
1) The impedance to the linearizer is decreased by the
capacitor Cb at the RF frequency.
2) The amount of RF power leak to the linearizer is
increased.
3) The rectified dc current to the linearizer makes the voltage
drop between the base and emitter of the HBT2.
4) The voltage drop compensates the decreased base bias of
the HBT1.
Because the impedance of the parallel connection of a
resistor R and two series diodes D1/D2 is much higher than
the impedance of capacitor Cb at the RF frequency, all the RF
signal at node P1 passes through the capacitor Cb, fixing the
voltage at point P1. With the increased input power, HBT1
needs more collector current, and, therefore, the base current
of HBT1 must be increased. In this case, the voltage at P1 is
fixed constantly, in a dc sense, because the current to the diode
D1/D2 is much higher than the base current of HBT2. So all
the voltage drop between the base and emitter of the HBT2
compensates the base bias drop of the HBT1.
Fig. 2 describes the effect of the capacitor in the linearizer
of the RF amplifier (HBT1) at PCS and W-CDMA
on the
bands simulated as a function of input power, where the
capacitance value was predetermined as 6 pF. For simulation,
we used an InGaP–GaAs HBT technology, and employed
Gummel–Poon as a large signal model.
at an input power of 5 dBm increases
With the capacitor,
slightly rather than decreases for both bands while that without
the capacitor decreases by 0.24 V. The RF insertion power to
the linearizer is also simulated and described in Fig. 2. The
input impedance to the linearizer from the RF amplifier (HBT1)
decreases with the addition of capacitor Cb, so there is an
increase of RF power to the linearizer. However, the lost power
is simulated to be as small as 7/9.7 dBm for the PCS/W-CDMA
band, which is a very small amount when considering the
first-stage output power of 20.6/20.02 dBm, at an input power
of 5 dBm. The lost signal affects the gain decrease of 0.4 dB
at low output power level for both PCS and W-CDMA bands,
which is very small insertion power loss (Fig. 4).
Fig. 3 shows the simulated gain compressions and phase deviations of the two-stage power amplifier for both PCS and
W-CDMA bands. Without the capacitor Cb, the 1-dB compression point is simulated at an input power of 13 ( 13) dBm at
the PCS (W-CDMA) band. With the linearizing capacitor, the
input 1-dB gain compression point of 18.5 (20) dB and the phase
deviation of 6.1 (12.42 ) at the output power of 28 (28) dBm
for the PCS (W-CDMA) band are improved relative to the case
without the capacitor.
Fig. 4 shows the simulated output power and ACPR of the
power amplifier for both the PCS and W-CDMA bands. ACPR
is simulated at a 1.25 (5) MHz offset frequency for the PCS
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 9, SEPTEMBER 2002
Fig. 6. Photograph of the two-stage dual-band power amplifier.
Fig. 4. Simulated output power and adjacent channel power ratio of the
two-stage power amplifier.
Fig. 7. Measured output power and power added efficiency of the two-stage
dual-band power amplifier.
Fig. 5. Simplified block diagram of the two-stage PCS/W-CDMA dual-band
power amplifier.
(W-CDMA) band. With the capacitor, the maximum output
power of 10.7 (12.8) dBm and ACPR up to 15.3 (15.7) dB at the
input power of 5 dBm are improved for the PCS (W-CDMA)
band.
III. PCS/W-CDMA DUAL-BAND POWER AMPLIFIER AND
MEASURED RESULTS
A PCS and W-CDMA dual-band MMIC power amplifier
of single-input/output architecture by designing the MMIC to
have broadband characteristics without any modification for
switching from band to band is designed. Fig. 5 is a simplified
schematic diagram of the two-stage dual-band power amplifier.
We used low-pass matching structures in the input, output, and
interstage for broad-band characteristics, and used a series RC
network between the collector and base for the driver stage and
a parallel RC network at the base for the power stage to reduce
less
low-frequency gain and increase stability. To obtain
than 10 dB and power gain more than 25 dB simultaneously,
the input was matched to 50 more closely at the W-CDMA
band because the transistor gain decreases as the frequency
increases.
The InGaP–GaAs HBT MMIC power amplifier was demonstrated using multiple fingers of a unit transistor of 60 m
(emitter area: 2880 m for the power stage and 720 m for the
driver stage). The fabricated MMIC power amplifier is shown
in Fig. 6. The total chip size of the MMIC is as small as 840
1100 m including input matching, interstage matching, bias
networks, and the capacitor linearizer (depicted in the figure).
NOH AND PARK: PCS/W-CDMA DUAL-BAND MMIC POWER AMPLIFIER
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IV. CONCLUSION
A new on-chip linearizer composed of the base–emitter diode
of an active bias transistor and a linearizing capacitor has been
described. The linearizer improves the 1-dB gain compression
point by 18.5 (20) dB and phase distortion by 6.1 (12.42 ) for
the PCS (W-CDMA) band. A PCS/W-CDMA dual-band power
amplifier is successfully fabricated with only one MMIC power
amplifier having broad-band characteristics. The fabricated
dual-band two-stage HBT MMIC power amplifier exhibits an
output power of 30 (28.5) dBm, PAE of 39.5 (36)%, and ACPR
of 46 ( 50) dBc at an output power of 28 (28) dBm under
3.4-V operation voltage, and consumes a quiescent current of
95 (95) mA for PCS (W-CDMA) applications.
REFERENCES
Fig. 8. Measured ACPR of the two-stage PCS/W-CDMA dual-band power
amplifier.
[1] T. Yoshimasu, M. Akagi, N. Tanba, and S. Hara, “An HBT MMIC
power amplifier with an integrated diode linearizer for low-voltage
portable phone applications,” IEEE J. Solid-State Circuits, vol. 33, pp.
1290–1296, Sept. 1998.
[2] H. Kawamura, K. Sakuno, T. Hasegawa, M. Hasegawa, H. Koh, and H.
Sato, “A miniature 44% efficiency GaAs HBT power amplifier for the
W-CDMA application,” in IEEE GaAs IC Symp. Tech. Dig., 2000, pp.
25–28.
[3] A. Adar, J. DeMoura, H. Balshem, and J. Lott, “A high-efficiency singlechain GaAs MESFET MMIC dual-band power amplifier for GSM/DCS
handsets,” in IEEE GaAs IC Symp. Tech. Dig., 1998, pp. 69–72.
TABLE I
MEASURED PERFORMANCES OF THE TWO-STAGE PCS/W-CDMA
DUAL-BAND POWER AMPLIFIER
Figs. 7 and 8, respectively, show the measured output
power/power-added efficiency (PAE) and ACPR of the MMIC
power amplifier at PCS and W-CDMA bands. The dual-band
power amplifier exhibits an output power of 30 (28.5) dBm and
a PAE of 39.5% (36%) at PCS (W-CDMA). For measurement,
a supply voltage of 3.4 V is used and the quiescent current of
the power amplifier is 95 mA (30 mA for the driver stage and 65
mA for the power stage). The ACPR is measured for a 1.2288
(3.84) Mc/s QPSK (HPSK) modulated signal in 1.25 (5) MHz
offset frequency bands, and is 46 ( 50) dBc at the output
power of 28 (28) dBm for PCS (W-CDMA) applications.
The measured performances show good agreement with the
simulated results for both bands, and the discrepancy between
simulations (Fig. 4) and measurements (Figs. 7 and 8) is even
in the worst case as small as 2 dB in output power and 5 dB in
ACPR at 28-dBm output power. The measured performances
of the two-stage PCS/W-CDMA dual-band power amplifier are
summarized in Table I.
Youn Sub Noh (S’00) received the B.S. degree
in electronics from Chunbuk National University,
Jeonju, Korea, in 2000 and the M.S. degree in
electronic engineering from the Information and
Communications University (ICU), Taejon, Korea,
in 2001. He is currently working toward the Ph.D.
degree in the Information Technology Engineering
School, ICU.
His research interests include analysis of nonlinearities of microwave amplifiers, MMIC power amplifiers, and their three-dimensional integration for
wireless communications.
Chul Soon Park (M’97) received the B.S. degree
in metallurgical engineering from Seoul National
University, Seoul, Korea, in 1980 and the M.S. and
Ph.D. degrees in materials science from the Korea
Advanced Institute of Science and Technology
(KAIST), Taejon, Korea, in 1982 and 1985, respectively.
He joined the Electronics and Telecommunications Research Institute (ETRI). Taejon, in 1985,
where he was involved in the development of semiconductor devices and circuits. Between 1987 and
1989, he studied the initial growth of group-IV semiconductors during a visit to
the AT&T Bell Laboratories, Murray Hill, NJ. Since 1989, he has been involved
in the development of compound semiconductor devices and their application
to microwave and high-speed integrated circuits as a Principal Investigator
with the ETRI. He is currently an Associate Professor with the Information
Technology Engineering School, Information and Communications University,
Taejon.
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