OPAx171 36-V, Single-Supply, SOT553
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OPA171, OPA2171, OPA4171
SBOS516E – SEPTEMBER 2010 – REVISED JUNE 2015
OPAx171 36-V, Single-Supply, SOT553, General-Purpose Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
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•
The OPA171, OPA2171, and OPA4171 (OPAx171)
are a family of 36-V, single-supply, low-noise
operational amplifiers with the ability to operate on
supplies ranging from 2.7 V (±1.35 V) to 36 V (±18
V). These devices are available in micro-packages
and offer low offset, drift, and bandwidth with low
quiescent current. The single, dual, and quad
versions all have identical specifications for maximum
design flexibility.
1
•
Supply Range: 2.7 to 36 V, ±1.35 V to ±18 V
Low Noise: 14 nV/√Hz
Low Offset Drift: ±0.3 µV/°C (Typical)
RFI Filtered Inputs
Input Range Includes the Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
Gain Bandwidth: 3 MHz
Low Quiescent Current: 475 µA per Amplifier
High Common-Mode Rejection: 120 dB (Typical)
Low-Input Bias Current: 8 pA
Industry-Standard Packages:
– 8-Pin SOIC
– 8-Pin MSOP
– 14-Pin TSSOP
microPackages:
– Single in SOT553
– Dual in VSSOP-8
2 Applications
•
•
•
•
•
•
•
•
•
Unlike most operational amplifiers, which are
specified at only one supply voltage, the OPAx171
family is specified from 2.7 to 36 V. Input signals
beyond the supply rails do not cause phase reversal.
The OPAx171 family is stable with capacitive loads
up to 300 pF. The input can operate 100 mV below
the negative rail and within 2 V of the top rail during
normal operation. These devices can operate with full
rail-to-rail input 100 mV beyond the top rail, but with
reduced performance within 2 V of the top rail.
The OPAx171 series of operational amplifiers are
specified from –40°C to 125°C.
Device Information(1)
PART NUMBER
Tracking Amplifier in Power Modules
Merchant Power Supplies
Transducer Amplifiers
Bridge Amplifiers
Temperature Measurements
Strain Gauge Amplifiers
Precision Integrators
Battery-Powered Instruments
Test Equipment
SPACE
Offset Voltage vs Common-Mode Voltage
1000
BODY SIZE (NOM)
SOT23 (5)
1.60 mm × 2.90 mm
OPA2171
SOIC (8)
3.90 mm × 4.90 mm
TSSOP (14)
4.40 mm × 5.00 mm
SOIC (14)
3.90 mm × 8.65 mm
OPA4171
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Offset Voltage vs Power Supply
10 Typical Units Shown
800
PACKAGE
OPA171
350
600
VSUPPLY = ±1.35V to ±18V
10 Typical Units Shown
250
150
200
VOS (mV)
VOS (mV)
400
0
-200
50
-50
-400
-150
-600
-800
-250
VCM = -18.1V
-1000
-20
-15
-10
-5
0
VCM (V)
5
10
15
20
-350
0
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA171, OPA2171, OPA4171
SBOS516E – SEPTEMBER 2010 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
5
6
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information: OPA171 ..................................
Thermal Information: OPA2171 ................................
Thermal Information: OPA4171 ................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 18
8
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................ 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2012) to Revision E
Page
•
Changed device title (removed "Value Line Series").............................................................................................................. 1
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision C (June 2011) to Revision D
•
Page
Added "Value Line Series" to title........................................................................................................................................... 1
Changes from Revision B (November 2010) to Revision C
Page
•
Added MSOP-8 package to device graphic ........................................................................................................................... 1
•
Added MSOP-8 package to Features bullets ......................................................................................................................... 1
•
Added MSOP-8 package to Product Family table.................................................................................................................. 1
•
Updated pinout configurations for OPA2171 and OPA4171 .................................................................................................. 3
•
Updated format of thermal information tables ........................................................................................................................ 6
•
Added MSOP-8 package to OPA2171 Thermal Information table ......................................................................................... 6
•
Added new row for Voltage Output Swing from Rail parameter to Output subsection of Electrical Characteristics.............. 7
•
Changed Voltage Output Swing from Rail parameter to over temperature in Output subsection of Electrical
Characteristics ........................................................................................................................................................................ 7
•
Changed Figure 9................................................................................................................................................................. 10
Changes from Revision A (November, 2010) to Revision B
Page
•
Changed input offset voltage specification ............................................................................................................................. 7
•
Changed input offset voltage, over temperature specification ............................................................................................... 7
•
Changed quiescent current per amplifier, over temperature specification ............................................................................. 8
2
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SBOS516E – SEPTEMBER 2010 – REVISED JUNE 2015
5 Pin Configuration and Functions
DRL Package: OPA171
SOT-553
Top View
IN+
1
V-
2
IN-
3
5
4
D, DCU, and DGK Packages: OPA2171
SO-8, VSSOP-8, and MSOP-8
Top View
V+
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
OUT
DBV Package: OPA171
SOT23-5
Top View
OUT
1
V-
2
+IN
3
D and PW Packages: OPA4171
SO-14 and TSSOP-14
Top View
5
V+
4
-IN
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
D PACKAGE: OPA171
SO-8
Top View
1
8
NC
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
NC
(1)
(1)
(1)
No internal connection.
Pin Functions: OPA171
PIN
NAME
I/O
DESCRIPTION
DRL
DBV
D
+IN
1
3
3
I
Noninverting input
–IN
3
4
2
I
Inverting input
OUT
4
1
6
O
Output
V+
5
5
7
—
Positive (highest) supply
V–
2
2
4
—
Negative (lowest) supply
NC
—
—
1, 5, 8
—
No internal connection (can be left floating)
Pin Functions: OPA2171
PIN
I/O
DESCRIPTION
NAME
DCU
DGK
D
+IN A
3
3
3
I
Noninverting input
+IN B
5
5
5
I
Noinverting input
–IN A
2
2
2
I
Inverting input
–IN B
6
6
6
O
Inverting input
OUT A
1
1
1
O
Output
OUT B
7
7
7
—
Output
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Pin Functions: OPA2171 (continued)
PIN
NAME
I/O
DESCRIPTION
DCU
DGK
D
V+
8
8
8
—
Positive (highest) supply
V–
4
4
4
—
Negative (lowest) supply
Pin Functions: OPA4171
PIN
I/O
DESCRIPTION
NAME
DCU
DGK
+IN A
3
3
I
Noninverting input
+IN B
5
5
I
Noninverting input
+IN C
10
10
I
Noninverting input
+IN D
12
12
I
Noninverting input
–IN A
2
2
I
Inverting input
–IN B
6
6
I
Inverting input
–IN C
9
9
I
Inverting input
–IN D
13
13
I
Inverting input
OUT A
1
1
O
Output
OUT B
7
7
O
Output
OUT C
8
8
O
Output
OUT D
14
14
O
Output
V+
4
4
—
Positive (highest) supply
V–
11
11
—
Negative (lowest) supply
4
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SBOS516E – SEPTEMBER 2010 – REVISED JUNE 2015
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range, unless otherwise noted. (1)
MIN
Supply voltage
Signal input terminals
MAX
V
Voltage
(V–) – 0.5
(V+) + 0.5
V
Current
–10
10
mA
150
°C
150
°C
150
°C
Output short circuit (2)
Continuous
Operating temperature
–55
Junction temperature
Storage temperature
(1)
(2)
UNIT
±20
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Specified temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
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6.4 Thermal Information: OPA171
OPA171
THERMAL METRIC (1)
D (SO)
DBV (SOT23)
DRL (SOT553)
8 PINS
5 PINS
5 PINS
UNIT
208.1
°C/W
RθJA
Junction-to-ambient thermal resistance
149.5
245.8
RθJC(top)
Junction-to-case(top) thermal resistance
97.9
133.9
0.1
°C/W
RθJB
Junction-to-board thermal resistance
87.7
83.6
42.4
°C/W
ψJT
Junction-to-top characterization parameter
35.5
18.2
0.5
°C/W
ψJB
Junction-to-board characterization parameter
89.5
83.1
42.2
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: OPA2171
OPA2171
THERMAL METRIC (1)
D (SO)
DGK (MSOP)
DCU (VSSOP)
8 PINS
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
134.3
175.2
195.3
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
72.1
74.9
59.4
°C/W
RθJB
Junction-to-board thermal resistance
60.6
22.2
115.1
°C/W
ψJT
Junction-to-top characterization parameter
18.2
1.6
4.7
°C/W
ψJB
Junction-to-board characterization parameter
53.8
22.8
114.4
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information: OPA4171
OPA4171
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS516E – SEPTEMBER 2010 – REVISED JUNE 2015
6.7 Electrical Characteristics
at TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
OFFSET VOLTAGE
Input offset voltage
VOS
Over temperature
0.25
±1.8
TA = –40°C to 125°C
0.3
±2
mV
0.3
±2
µV/°C
±3
µV/V
Drift
dVOS/dT
TA = –40°C to 125°C
vs power supply
PSRR
VS = 4 to 36 V, TA = –40°C to 125°C
1
DC
5
Channel separation, dc
µV/V
INPUT BIAS CURRENT
Input bias current
IB
Over temperature
Input offset current
±8
TA = –40°C to 125°C
IOS
Over temperature
±15
pA
±3.5
nA
±4
pA
TA = –40°C to 125°C
±3.5
nA
NOISE
Input voltage noise
Input voltage noise density
f = 0.1 Hz to 10 Hz
en
3
µVPP
f = 100 Hz
25
nV/√Hz
f = 1 kHz
14
nV/√Hz
INPUT VOLTAGE
Common-mode voltage
range (1)
Common-mode rejection
ratio
VCM
CMRR
(V–) – 0.1 V
(V+) – 2 V
V
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to 125°C
90
104
dB
VS = ±18V, (V–) – 0.1V < VCM < (V+) – 2 V,
TA = –40°C to 125°C
104
120
dB
INPUT IMPEDANCE
Differential
MΩ ||
pF
100 || 3
Common-mode
6 || 3
1012Ω ||
pF
130
dB
3.0
MHz
1.5
V/µs
OPEN-LOOP GAIN
Open-loop voltage gain
AOL
VS = 4 V to 36 V, (V–) + 0.35 V < VO < (V+) –
0.35 V, TA = –40°C to 125°C
110
FREQUENCY RESPONSE
Gain bandwidth product
GBP
Slew rate
SR
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
Settling time
tS
Overload recovery time
Total harmonic distortion +
noise
To 0.01% (12 bit), VS = ±18V, G = +1, 10V
step
VIN × Gain > VS
THD+N
G = +1, f = 1kHz, VO = 3VRMS
VO
VS = 5V, RL = 10kΩ
6
µs
10
µs
2
µs
0.0002%
OUTPUT
Voltage output swing from
rail
RL = 10 kΩ, AOL ≥ 110 dB, TA = –40°C to
125°C
Over temperature
Short-circuit current
ISC
Capacitive load drive
CLOAD
Open-loop output resistance
RO
(1)
30
(V–) + 0.35
mV
(V+) – 0.35
+25/–35
See Typical Characteristics
f = 1MHz, IO = 0A
150
V
mA
pF
Ω
The input range can be extended beyond (V+) – 2V up to V+. See Typical Characteristics and Application and Implementation for
additional information.
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Electrical Characteristics (continued)
at TA = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Specified voltage range
VS
Quiescent current per
amplifier
IQ
Over temperature
2.7
IO = 0A
475
IO = 0 A, TA = –40°C to 125°C
36
V
595
µA
650
µA
TEMPERATURE
Specified range
–40
125
°C
Operating range
–55
150
°C
8
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6.8 Typical Characteristics
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 5
Offset Voltage vs Power Supply
Figure 6
IB and IOS vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to Input)
Figure 10
CMRR vs Temperature
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
Figure 14
THD+N Ratio vs Frequency
Figure 15
THD+N vs Output Amplitude
Figure 16
Quiescent Current vs Temperature
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Open-Loop Gain and Phase vs Frequency
Figure 19
Closed-Loop Gain vs Frequency
Figure 20
Open-Loop Gain vs Temperature
Figure 21
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 22
Figure 23, Figure 24
No Phase Reversal
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
Small-Signal Step Response (100 mV)
Figure 28, Figure 29
Large-Signal Step Response
Figure 30, Figure 31
Large-Signal Settling Time (10-V Positive Step)
Figure 32
Large-Signal Settling Time (10-V Negative Step)
Figure 33
Short-Circuit Current vs Temperature
Figure 34
Maximum Output Voltage vs Frequency
Figure 35
Channel Separation vs Frequency
Figure 36
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
Distribution Taken From 3500 Amplifiers
Distribution Taken From 110 Amplifiers
14
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
16
12
10
8
6
4
2
0
20
15
10
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 2. Offset Voltage Drift Distribution
Figure 1. Offset Voltage Production Distribution
1000
600
5 Typical Units Shown
10 Typical Units Shown
800
400
400
VOS (mV)
Offset Voltage (mV)
600
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-800
VCM = -18.1V
-1000
-75
-50
-25
0
25
50
75
100
125
150
-20
-15
-10
0
-5
Figure 3. Offset Voltage vs Temperature
10000
5
10
15
20
VCM (V)
Temperature (°C)
Figure 4. Offset Voltage vs Common-Mode Voltage
350
10 Typical Units Shown
8000
VSUPPLY = ±1.35V to ±18V
10 Typical Units Shown
250
6000
150
2000
VOS (mV)
VOS (mV)
4000
0
-2000
-4000
Normal
Operation
-250
-8000
-10000
15.5
-50
-150
VCM = +18.1V
-6000
50
-350
16
16.5
17
17.5
18
18.5
0
2
4
VCM (V)
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8
10
12
14
16
18
20
VSUPPLY (V)
Figure 5. Offset Voltage vs Common-Mode Voltage (Upper
Stage)
10
6
Figure 6. Offset Voltage vs Power Supply
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10000
IB+
-IB
+IB
-IOS
VCM = -18.1V
IB-
1000
Input Bias Current (pA)
IB and IOS (pA)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
IB
IOS
100
10
IOS
1
VCM = 16V
0
-20
-18
-12
0
-6
6
12
18
20
-75
-50
0
-25
VCM (V)
Figure 7. IB and IOS vs Common-Mode Voltage
75
100
125
150
Figure 8. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
17
Output Voltage (V)
50
140
18
16
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
2
4
6
8
10
12
14
1
16
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Output Current (mA)
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 10. CMRR and PSRR vs Frequency (Referred-to
Input)
30
3
Power-Supply Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
25
Temperature (°C)
20
10
0
-10
VS = 2.7V
-20
VS = 4V
VS = 36V
-30
2
1
0
-1
-2
VS = 2.7V to 36V
VS = 4V to 36V
-3
-75
-50
-25
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 11. CMRR vs Temperature
Figure 12. PSRR vs Temperature
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1mV/div
Voltage Noise Density (nV/ÖHz)
1000
100
10
1
Time (1s/div)
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 13. 0.1-Hz to 10-Hz Noise
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
10
100
1k
10k
-140
20k
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
-100
0.001
0.1
BW = 80kHz
0.01
-100
0.001
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
0.01
-140
0.1
1
10
20
Output Amplitude (VRMS)
Frequency (Hz)
Figure 15. THD+N Ratio vs Frequency
Figure 16. THD+N vs Output Amplitude
0.65
0.6
0.6
0.55
0.5
IQ (mA)
0.55
IQ (mA)
-80
Total Harmonic Distortion + Noise (dB)
-80
VOUT = 3VRMS
BW = 80kHz
Total Harmonic Distortion + Noise (dB)
0.01
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
0.5
0.45
0.45
0.4
0.35
0.4
0.3
0.35
0.25
Specified Supply-Voltage Range
-75
-50
-25
0
25
50
75
100
125
150
0
4
8
Figure 17. Quiescent Current vs Temperature
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16
20
24
28
32
36
Supply Voltage (V)
Temperature (°C)
Figure 18. Quiescent Current vs Supply Voltage
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
180
180
25
Gain
20
135
135
15
Phase
45
45
Gain (dB)
90
Phase (°)
Gain (dB)
10
90
5
0
-5
-10
0
0
G = 10
G=1
G = -1
-15
-45
10M
-45
1
10
100
1k
10k
100k
1M
-20
10k
100k
1M
Figure 19. Open-Loop Gain and Phase vs Frequency
3
Figure 20. Closed-Loop Gain vs Frequency
5 Typical Units Shown
VS = 2.7V
VS = 4V
VS = 36V
100k
10k
ZO (W)
2
1.5
1
1k
100
10
0.5
1
0
1m
-75
-50
-25
0
25
50
75
100
150
125
1
10
100
Temperature (°C)
50
100k
1M
10M
50
ROUT = 0W
40
40
ROUT = 25W
35
35
ROUT = 50W
30
25
20
10
ROUT = 25W
5
ROUT = 50W
G = +1
+18V
ROUT = 0W
Overshoot (%)
45
15
10k
Figure 22. Open-Loop Output Impedance vs Frequency
RL = 10kW
45
1k
Frequency (Hz)
Figure 21. Open-Loop Gain vs Temperature
Overshoot (%)
100M
1M
2.5
AOL (mV/V)
10M
Frequency (Hz)
Frequency (Hz)
30
25
20
RI = 10kW
15
ROUT
-18V
RF = 10kW
G = -1
+18V
OPA171
RL
CL
10
ROUT
OPA171
CL
5
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 23. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 24. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
+18V
Output
VOUT
OPA171
VIN
5V/div
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
20kW
+18V
2kW
OPA171
Output
VOUT
VIN
-18V
G = -10
Time (5ms/div)
Time (100ms/div)
Figure 25. No Phase Reversal
Figure 26. Positive Overload Recovery
RL = 10kW
CL = 100pF
+18V
OPA171
RL
CL
20mV/div
-18V
VIN
5V/div
G = +1
20kW
+18V
2kW
OPA171
VOUT
VIN
VOUT
-18V
G = -10
Time (1ms/div)
Time (5ms/div)
Figure 27. Negative Overload Recovery
Figure 28. Small-Signal Step Response (100 mV)
G = +1
RL = 10kW
CL = 100pF
RI
= 2kW
RF
2V/div
20mV/div
CL = 100pF
= 2kW
+18V
OPA171
CL
-18V
G = -1
Time (20ms/div)
Time (5ms/div)
Figure 29. Small-Signal Step Response (100 mV)
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Figure 30. Large-Signal Step Response
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10
G = -1
RL = 10kW
CL = 100pF
G = -1
2V/div
D From Final Value (mV)
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
-10
Time (4ms/div)
0
4
8
12
16
20
24
28
32
36
Time (ms)
Figure 31. Large-Signal Step Response
10
50
G = -1
8
45
6
40
4
35
12-Bit Settling
2
ISC (mA)
D From Final Value (mV)
Figure 32. Large-Signal Settling Time (10-V Positive Step)
0
-2
(±1/2LSB = ±0.024%)
ISC, Sink
30
25
20
-4
15
-6
10
-8
5
ISC, Source
0
-10
0
4
8
12
16
20
24
28
32
36
-75
-50
-25
0
25
50
75
100
125
150
Time (ms)
Temperature (°C)
Figure 33. Large-Signal Settling Time (10-V Negative Step)
Figure 34. Short-Circuit Current vs Temperature
15
-60
VS = ±15V
10
Channel Separation (dB)
Output Voltage (VPP)
12.5
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5V
5
2.5
-70
-80
-90
-100
-110
VS = ±1.35V
0
-120
10k
100k
1M
10M
10
100
Frequency (Hz)
Figure 35. Maximum Output Voltage vs Frequency
1k
10k
100k
Frequency (Hz)
Figure 36. Channel Separation vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx171 family of operational amplifiers provide high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
7.2 Functional Block Diagram
OPA172
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
Output
Stage
2nd Stage
OUT
-IN
NCH
Input Stage
7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx171 family of amplifiers is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the
specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics.
7.3.2 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 2.
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Feature Description (continued)
7.3.3 Phase-Reversal Protection
The OPAx171 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond its linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx171 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown
in Figure 37.
+18V
Output
OPA171
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
Output
Time (100ms/div)
Figure 37. No Phase Reversal
Table 2. Typical Performance Range
PARAMETER
Input Common-Mode Voltage
MIN
TYP
(V+) – 2
Offset voltage
vs Temperature
MAX
UNIT
(V+) + 0.1
V
7
mV
12
µV/°C
Common-mode rejection
65
dB
Open-loop gain
60
dB
GBW
0.7
MHz
Slew rate
0.7
V/µs
Noise at f = 1kHz
30
nV/√Hz
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx171-Q1 family of devices have been optimized for commonly
encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases
the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive
loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for
example, ROUT equal to 50 Ω) in series with the output. Figure 38 and Figure 39 show small-signal overshoot
versus capacitive load for several values of ROUT. Also, for details of analysis techniques and application circuits,
refer to the Applications Bulletin AB-028 (SBOA015), available for download from TI.com.
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50
50
RL = 10kW
ROUT = 0W
40
40
ROUT = 25W
35
35
ROUT = 50W
30
25
20
10
ROUT = 25W
5
ROUT = 50W
G = +1
+18V
ROUT = 0W
15
Overshoot (%)
45
45
Overshoot (%)
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30
25
20
RI = 10kW
15
ROUT
-18V
RF = 10kW
G = -1
+18V
OPA171
RL
CL
10
ROUT
OPA171
CL
5
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 38. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 39. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx171 family of devices extends 100 mV below the negative
rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 2.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx171 operational amplifier provides high overall performance, making it ideal for many general-purpose
applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire temperature
range. In addition, the device offers very-good overall performance with high CMRR, PSRR, and AOL. As with all
amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the
device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins
or even the output pin. Each of these different pin functions have electrical stress limits determined by the
voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits
connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to
protect them from accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10mA as stated in the Absolute Maximum Ratings. Figure 40 shows how a series input resistor may be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10mA max
OPA171
VOUT
VIN
5kW
Figure 40. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk
that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The Zener voltage must be selected such that the diode does not turn on during
normal operation.
However, its Zener voltage should be low enough so that the zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.
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8.2 Typical Application
+VS
VOUT
RISO
+
CLOAD
+
±
VIN
-VS
Figure 41. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 42 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 42. Not shown in Figure 42 is the open-loop output resistance of the operational amplifier, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 42 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
2 u Πu RISO R o
Gain (dB)
80
60
uC
LOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 42. Unity-Gain Amplifier With RISO Compensation
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Typical Application (continued)
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA171, refer to the
Precision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
Table 3. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.2.1 Capacitive Load and Stability
The dynamic characteristics of the OPAx171 have been optimized for commonly encountered operating
conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of
the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated
from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to
50 Ω) in series with the output. Figure 38 and Figure 39 illustrate graphs of small-signal overshoot versus
capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available for
download from the TI website for details of analysis techniques and application circuits.
50
45
ROUT = 0W
40
40
ROUT = 25W
35
35
ROUT = 50W
30
25
20
15
ROUT = 0W
10
ROUT = 25W
5
ROUT = 50W
G = +1
+18V
Overshoot (%)
Overshoot (%)
50
RL = 10kW
45
30
25
20
RI = 10kW
15
ROUT
-18V
RF = 10kW
G = -1
+18V
OPA171
RL
CL
10
ROUT
OPA171
CL
5
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 43. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 44. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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8.2.3 Application Curve
The OPA171 meets the supply voltage requirements of 30 V. The OPA171 is tested for various capacitive loads
and RISO is adjusted to get an overshoot corresponding to Table 3. The results of the these tests are
summarized in Figure 45.
10000
Isolation Resistor, RISO (:)
45q Phase Margin
60q Phase Margin
1000
100
10
1
0.01
0.1
1
10
Capacitive Load (nF)
100
1000
D001
Figure 45. RISO vs CLOAD
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9 Power Supply Recommendations
The OPAx171 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many
specifications apply from –40°C to 125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Specifications section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see the Layout Guidelines
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, good printed--circuit board (PCB) layout practices are
recommended. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to singlesupply applications.
10.2 Layout Example
RIN
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
NC
NC
±IN
V+
+IN
OUT
V±
NC
RG
GND
VIN
GND
RIN
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 46. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA171
Click here
Click here
Click here
Click here
Click here
OPA2171
Click here
Click here
Click here
Click here
Click here
OPA4171
Click here
Click here
Click here
Click here
Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2010–2015, Texas Instruments Incorporated
Product Folder Links: OPA171 OPA2171 OPA4171
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA171AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O171A
OPA171AIDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OSUI
OPA171AIDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OSUI
OPA171AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O171A
OPA171AIDRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
DAP
OPA171AIDRLT
ACTIVE
SOT-5X3
DRL
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
DAP
OPA2171AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2171A
OPA2171AIDCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPOC
OPA2171AIDCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
OPOC
OPA2171AIDGK
ACTIVE
VSSOP
DGK
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OPMI
OPA2171AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
OPMI
OPA2171AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
2171A
OPA4171AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4171
OPA4171AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OPA4171
OPA4171AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4171
OPA4171AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA4171
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2017
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA171, OPA2171, OPA4171 :
• Automotive: OPA171-Q1, OPA2171-Q1, OPA4171-Q1
• Enhanced Product: OPA2171-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-May-2017
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
OPA171AIDBVR
SOT-23
DBV
5
3000
180.0
8.4
3.17
1.37
4.0
8.0
Q3
OPA171AIDBVT
SOT-23
DBV
5
250
179.0
8.4
3.2
OPA171AIDBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.2
1.4
4.0
8.0
Q3
3.17
1.37
4.0
8.0
OPA171AIDR
SOIC
D
8
2500
330.0
12.4
6.4
Q3
5.2
2.1
8.0
12.0
OPA171AIDRLR
SOT-5X3
DRL
5
4000
180.0
8.4
Q1
1.98
1.78
0.69
4.0
8.0
Q3
3.23
W
Pin1
(mm) Quadrant
OPA171AIDRLT
SOT-5X3
DRL
5
250
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
OPA2171AIDCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
OPA2171AIDCUT
VSSOP
DCU
8
250
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
OPA2171AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2171AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
OPA4171AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
OPA4171AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA171AIDBVR
SOT-23
DBV
5
3000
213.0
191.0
35.0
OPA171AIDBVT
SOT-23
DBV
5
250
195.0
200.0
45.0
OPA171AIDBVT
SOT-23
DBV
5
250
223.0
270.0
35.0
OPA171AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA171AIDRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
OPA171AIDRLT
SOT-5X3
DRL
5
250
202.0
201.0
28.0
OPA2171AIDCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
OPA2171AIDCUT
VSSOP
DCU
8
250
202.0
201.0
28.0
OPA2171AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2171AIDR
SOIC
D
8
2500
367.0
367.0
35.0
OPA4171AIDR
SOIC
D
14
2500
367.0
367.0
38.0
OPA4171AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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