SN74LVC1GX04 Crystal Oscillator Driver

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SN74LVC1GX04
SCES581D – JULY 2004 – REVISED OCTOBER 2015
SN74LVC1GX04 Crystal Oscillator Driver
1 Features
3 Description
•
The SN74LVC1GX04 device is designed for 1.65-V to
5.5-V VCC operation. This device incorporates the
SN74LVC1GU04 (inverter with unbuffered output)
and the SN74LVC1G04 (inverter) functions into a
single device. The LVC1GX04 is optimized for use in
crystal oscillator applications.
1
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•
•
•
•
•
•
•
•
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Available in Texas Instruments NanoStar™ and
NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
One Unbuffered Inverter (SN74LVC1GU04) and
One Buffered Inverter (SN74LVC1G04)
Suitable for Commonly Used Clock Frequencies:
– 15 kHz, 3.58 MHz, 4.43 MHz, 13 MHz,
25 MHz, 26 MHz, 27 MHz, 28 MHz
Maximum tpd of 2.4 ns at 3.3 V
Low Power Consumption, 10-μA Maximum ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
X1 and X2 can be connected to a crystal or resonator
in oscillator applications. The device provides an
additional buffered inverter (Y) for signal conditioning
(see Figure 5). The additional buffered inverter
improves the signal quality of the crystal oscillator
output by making it rail to rail.
NanoStar and NanoFree package technology is a
major breakthrough in IC packaging concepts, using
the die as the package.
This device is fully specified for partial-power-down
applications using Ioff (Y output only). The Ioff circuitry
disables the outputs, preventing damaging current
backflow through the device when it is powered
down.
Device Information(1)
2 Applications
•
•
PART NUMBER
Crystal Oscillators
Clock Generation
PACKAGE
BODY SIZE (NOM)
SN74LVC1GX04DB
V
SOT-23 (6)
2.90 mm × 1.60 mm
SN74LVC1GX04DC
K
SC70 (6)
2.00 mm × 1.25 mm
SN74LVC1GX04DR
L
SOT (6)
1.60 mm × 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
SN74LVC1GU04
Portion
SN74LVC1G04
Portion
Y
X2
X1
CLOAD
RLOAD
RF ≅ 2.2 MΩ
CL ≅ 16 pF
C1 ≅ 32 pF
Rs ≅ 1 kΩ
C2 ≅ 32 pF
a) Logic Diagram View
SN74LVC1GX04 includes both dotted portions
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74LVC1GX04
SCES581D – JULY 2004 – REVISED OCTOBER 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
4
5
5
6
6
6
6
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, SN74LVC1GX04.............
Switching Characteristics, SN74LVC1GX04.............
Switching Characteristics, SN74LVC1GX04.............
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision C (December 2013) to Revision D
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Pin Configuration and Functions
DBV Package
6-Pin SOT-23
Top View
DCK Package
6-Pin SC70
Top View
DRL Package
6-Pin SOT
Top View
See mechanical drawings for dimensions.
NC – No internal connection.
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
2
–
Ground
NC
1
–
No internal connection
VCC
5
–
Supply power
X1
3
I
Amplifier input
X2
4
O
Amplifier output
Y
6
O
Main output to other logic
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
6.5
V
(2)
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to Y output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
(3)
Continuous current through VCC or GND
±100
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±1000
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions (1)
Operating
VCC
Supply voltage
Data retention only
High-level input voltage
VCC = 1.65 V to 5.5 V
VIL
Low-level input voltage
VCC = 1.65 V to 5.5 V
VI
Input voltage
VO
Output voltage
V
0
VCC
Y output only, Power-down mode, VCC = 0 V
0
5.5
VCC = 3 V
VCC = 3 V
VCC = 4.5 V
4
V
X2, Y
VCC = 2.3 V
(1)
0.75 × VCC
V
VCC = 1.65 V
Low-level output current
V
2
5.5
VCC = 4.5 V
IOL
UNIT
0.25 × VCC
VCC = 2.3 V
High-level output current
5.5
0
VCC = 1.65 V
IOH
MAX
1.5
Crystal oscillator use
VIH
MIN
1.65
V
–4
–8
–16
mA
–24
–32
4
8
16
mA
24
32
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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Recommended Operating Conditions(1) (continued)
MIN
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
MAX
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ±0.5 V
UNIT
ns/V
10
–40
125
°C
6.4 Thermal Information
SN74LVC1GX04
THERMAL METRIC (1)
RθJA
(1)
Junction-to-ambient thermal resistance
DBV (SOT-23)
DCK (SC70)
DRL (SOT)
6 PINS
6 PINS
6 PINS
165
259
142
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 μA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
VI = 5.5 V or GND
TA = –40°C to 125°C
3V
IOH = –24 mA
TYP (1)
MAX
V
2.4
2.3
IOH = –32 mA
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
1.65 V
0.45
2.3 V
0.3
IOL = 4 mA
TA = –40°C to 125°C
IOL = 8 mA
IOL = 16 mA
VI = 5.5 V or GND
IOL = 24 mA
TA = –40°C to 125°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 85°C
IOL = 32 mA
TA = –40°C to 125°C
UNIT
VCC – 0.1
IOH = –4 mA
IOH = –16 mA
VOL
MIN
3.8
3V
0.4
0.55
3V
V
0.63
0.55
4.5 V
0.7
II
X1
VI = 5.5 V or GND
TA = –40°C to 125°C
0 to 5.5 V
±5
μA
Ioff
X1, Y
VI or VO = 5.5 V
TA = –40°C to 125°C
0
±10
μA
ICC
VI = 5.5 V or GND, IO =
0
TA = –40°C to 125°C
1.65 V to 5.5 V
10
μA
Ci
VI = VCC or GND
(1)
3.3 V
7
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
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6.6 Switching Characteristics, SN74LVC1GX04
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
X2
tpd
TEMPERATURE
–40°C to 85°C
X1
Y (1)
–40°C to 85°C
VCC
MIN
VCC = 1.8 V ± 0.15 V
1
4
VCC = 2.5 V ± 0.2 V
0.8
2.6
VCC = 3.3 V ± 0.3 V
0.6
2.4
VCC = 5 V ± 0.5 V
0.5
2
VCC = 1.8 V ± 0.15 V
3.5
10
VCC = 2.5 V ± 0.2 V
2.2
6
VCC = 3.3 V ± 0.3 V
2
5
1.5
3.5
VCC = 5 V ± 0.5 V
(1)
MAX
UNIT
ns
X2 – no external load
6.7 Switching Characteristics, SN74LVC1GX04
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
X2
tpd
–40°C to 85°C
X1
Y (1)
(1)
TEMPERATURE
–40°C to 85°C
VCC
MIN
MAX
VCC = 1.8 V ± 0.15 V
1.1
7
VCC = 2.5 V ± 0.2 V
0.8
4
VCC = 3.3 V ± 0.3 V
0.8
3.7
VCC = 5 V ± 0.5 V
0.8
3
VCC = 1.8 V ± 0.15 V
3.8
18
VCC = 2.5 V ± 0.2 V
2
7.4
VCC = 3.3 V ± 0.3 V
2
7.8
VCC = 5 V ± 0.5 V
2
5
UNIT
ns
X2 – no external load
6.8 Switching Characteristics, SN74LVC1GX04
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
X2
tpd
–40°C to 125°C
X1
Y (1)
(1)
TEMPERATURE
–40°C to 125°C
VCC
MIN
MAX
VCC = 1.8 V ± 0.15 V
1.1
8
VCC = 2.5 V ± 0.2 V
0.8
5
VCC = 3.3 V ± 0.3 V
0.8
4.3
VCC = 5 V ± 0.5 V
0.8
3.5
VCC = 1.8 V ± 0.15 V
3.8
20
VCC = 2.5 V ± 0.2 V
2
8.4
VCC = 3.3 V ± 0.3 V
2
8.8
VCC = 5 V ± 0.5 V
2
5.5
UNIT
ns
X2 – no external load
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST
CONDITIONS
f = 10 MHz
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VCC
TYP
VCC = 1.8 V
22
VCC = 2.5 V
22
VCC = 3.3 V
24
VCC = 5 V
35
UNIT
pF
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6.10 Typical Characteristics
30
Gain − dBV
25
20
15
VCC = 5 V
VCC = 3.3 V
VCC = 2.7 V
10
5
0
VCC = 2 V
−5
VCC = 1.8 V
−10
0.1
1
10
100
Frequency − MHz
Figure 1. Open-Loop Gain Characteristics of Oscillator Amplifier
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7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1GX04 is optimized for creating a crystal oscillator circuit with a buffered square-wave output. This
device is fully specified for partial-power-down applications using Ioff (Y output only). The Ioff circuitry disables the
outputs, preventing damaging current back-flow through the device when it is powered down.
8.2 Functional Block Diagram
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The first inverter is used as a linear amplifier for crystal oscillator.
The last three inverters ensure a fast edge square-wave at the Y output.
8.4 Device Functional Modes
The only intended device use is to generate a square-wave output using a crystal to set the operating frequency.
Table 1. Function Table
INPUT X1
10
OUTPUTS
X2
Y
H
L
H
L
H
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1GX04 contains a buffered and unbuffered inverter for the specific purpose of creating a crystal
oscillator and driver with limited external components.
9.2 Typical Application
Figure 5 shows a typical application of the SN74LVC1GX04 in a Pierce oscillator circuit. The buffered inverter
(SN74LVC1G04 portion) produces a rail-to-rail voltage waveform. The recommended load for the crystal shown
in this example is 16 pF. The value of the recommended load (CL) can be found in the crystal manufacturer's
data sheet.
Values of C1 and C2 are chosen to calculate CL in Equation 1 where C1 ≡ C2.
C 1C2
CL +
C1 ) C 2
(1)
Rs is the current-limiting resistor, and the value depends on the maximum power dissipation of the crystal.
Generally, the recommended value of Rs is specified in the crystal manufacturer's data sheet and, usually, this
value is approximately equal to the reactance of C2 at resonance frequency, that is seen in Equation 2.
Rs + XC
(2)
2
RF is the feedback resistor that is used to bias the inverter in the linear region of operation. Usually, the value is
chosen to be within 1 MΩ to 10 MΩ.
SN74LVC1GU04
Portion
SN74LVC1G04
Portion
Y
X2
X1
CLOAD
RLOAD
RF ≅ 2.2 MΩ
CL ≅ 16 pF
C1 ≅ 32 pF
Rs ≅ 1 kΩ
C2 ≅ 32 pF
a) Logic Diagram View
Figure 5. Oscillator Circuit
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Typical Application (continued)
6
1
NC
Y
CLOAD
GND
X1
2
5
3
4
RLOAD
VCC
X2
RF ≅ 2.2 MΩ
CL = 16 pF
Rs ≅ 1 kΩ
C2 ≅ 32 pF
C1 ≅ 32 pF
b) Oscillator Circuit in DBV or DCK Pinout
Figure 6. Oscillator Circuit (Continued)
9.2.1 Design Requirements
The open-loop gain of the unbuffered inverter decreases as power-supply voltage decreases. This decreases the
closed-loop gain of the oscillator circuit. The value of Rs can be decreased to increase the closed-loop gain, while
maintaining the power dissipation of the crystal within the maximum limit.
Rs and C2 form a low-pass filter and reduce spurious oscillations. Component values can be adjusted, based on
the desired cutoff frequency.
C2 can be increased over C1 to increase the phase shift and help in start-up of the oscillator. Increasing C2 may
affect the duty cycle of the output voltage.
At high frequency, phase shift due to Rs becomes significant. In this case, Rs can be replaced by a capacitor to
reduce the phase shift.
9.2.2 Detailed Design Procedure
After the selection of proper component values, the oscillator circuit should be tested using these components.
To ensure that the oscillator circuit performs within the Recommended Operating Conditions (1) , follow these
steps:
1. Without a crystal, the oscillator circuit should not oscillate. To check this, the crystal can be replaced by its
equivalent parallel-resonant resistance.
2. When the power-supply voltage drops, the closed-loop gain of the oscillator circuit reduces. Ensure that the
circuit oscillates at the appropriate frequency at the lowest VCC and highest VCC.
3. Ensure that the duty cycle, start-up time, and frequency drift over time is within the system requirements.
(1)
12
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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SCES581D – JULY 2004 – REVISED OCTOBER 2015
Typical Application (continued)
9.2.3 Application Curve
5
4
VO − V
VCC = 3.3 V
3
2
VCC = 5 V
VCC = 2.7 V
VCC = 2 V
VCC = 1.8 V
1
0
0
1
2
VI − V
3
4
Figure 7. VO vs VI Characteristics of Oscillator Amplifier
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13
SN74LVC1GX04
SCES581D – JULY 2004 – REVISED OCTOBER 2015
www.ti.com
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions (1) table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC terminals then 0.01-μF or 0.022-μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
14
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SN74LVC1GX04
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SCES581D – JULY 2004 – REVISED OCTOBER 2015
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 8. Layout Diagram
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SN74LVC1GX04
SCES581D – JULY 2004 – REVISED OCTOBER 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
NanoStar, NanoFree, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC1GX04DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CX45 ~ CX4R)
74LVC1GX04DCKRE4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(D25 ~ D2K ~ D2R)
74LVC1GX04DCKTG4
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(D25 ~ D2R)
SN74LVC1GX04DBVR
ACTIVE
SOT-23
DBV
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CX45 ~ CX4R)
SN74LVC1GX04DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CX45 ~ CX4R)
SN74LVC1GX04DCKR
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(D25 ~ D2K ~ D2R)
SN74LVC1GX04DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(D25 ~ D2R)
SN74LVC1GX04DRLR
ACTIVE
SOT-OTHER
DRL
6
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(D27 ~ D2R)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
28-Feb-2017
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1GX04 :
• Enhanced Product: SN74LVC1GX04-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74LVC1GX04DBVR
SOT-23
3000
180.0
8.4
DBV
6
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1GX04DBVT
SOT-23
DBV
6
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1GX04DCKR
SC70
DCK
6
3000
180.0
9.2
2.3
2.55
1.2
4.0
8.0
Q3
SN74LVC1GX04DCKR
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1GX04DCKT
SC70
DCK
6
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1GX04DCKT
SC70
DCK
6
250
180.0
8.4
2.41
2.41
1.2
4.0
8.0
Q3
SN74LVC1GX04DRLR
SOTOTHER
DRL
6
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
SN74LVC1GX04DRLR
SOTOTHER
DRL
6
4000
180.0
9.5
1.78
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1GX04DBVR
SOT-23
DBV
6
3000
202.0
201.0
28.0
SN74LVC1GX04DBVT
SOT-23
DBV
6
250
202.0
201.0
28.0
SN74LVC1GX04DCKR
SC70
DCK
6
3000
205.0
200.0
33.0
SN74LVC1GX04DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74LVC1GX04DCKT
SC70
DCK
6
250
180.0
180.0
18.0
SN74LVC1GX04DCKT
SC70
DCK
6
250
202.0
201.0
28.0
SN74LVC1GX04DRLR
SOT-OTHER
DRL
6
4000
202.0
201.0
28.0
SN74LVC1GX04DRLR
SOT-OTHER
DRL
6
4000
184.0
184.0
19.0
Pack Materials-Page 2
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