GIGALIGHT 56Gb/s QSFP+ SR4 GQS-MPO560-SR4C

GIGALIGHT 56Gb/s QSFP+ SR4
GQS-MPO560-SR4C
Features

Four-channel full-duplex transceiver modules

Transmission data rate up to 14.025Gbit/s per channel

4 channels 850nm VCSEL array

4 channels PIN photo detector array

Low power consumption <1.5W

Housing isolated from connector ground

Operating case temperature 0°C to +70°C

3.3V power supply voltage

RoHS 6 compliant

Hot Pluggable QSFP form factor

Maximum link length of 100m on OM3 Multimode Fiber (MMF)and 150m on OM4 MMF

Single MPO connector receptacle

Built-in digital diagnostic function
Applications

InfiniBand FDR

16x Fibre Channel

PCI-e3.0

Proprietary High Speed Interconnections

SAS 3.0
Description
The Gigalight Technologies GQS-MP560-SR4C is a Four-Channel, Pluggable, Parallel, Fiber-Optic
QSFP+ Transceiver for InfiniBand FDR/QDR/DDR/SDR,16G/10G/8G/4G/2G fiber channel , PCIe and SAS
Applications. This transceiver is a high performance module for short-range multi-lane data communication
and interconnect applications. It integrates four data lanes in each direction with 56 Gbps bandwidth. Each
lane can operate at 14.025 Gbps up to 100 m using OM3 fiber or 150 m using OM4 fiber. These modules are
Page 1 of 13
Rev.B
05 / 2012
designed to operate over multimode fiber systems using a nominal wavelength of 850nm. The electrical
interface uses a 38 contact edge type connector. The optical interface uses an 12 fiber MTP (MPO)
connector. This module incorporates Gigalight Technologies proven circuit and VCSEL technology to provide
reliable long life, high performance, and consistent service.QSFP+ SR4 is one kind of parallel transceiver.
VCSEL and PIN array package is key technique, through I2C system can contact with module.
Figure1. Module Block Diagram
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Supply Voltage
Vcc
-0.3
3.6
V
Input Voltage
Vin
-0.3
Vcc+0.3
V
Storage Temperature
Tst
-20
85
ºC
Case Operating Temperature
Top
0
70
ºC
Humidity(non-condensing)
Rh
5
95
%
Recommended Operating Conditions
Parameter
Symbol
Min
Typical
Max
Unit
Supply Voltage
Vcc
3.13
3.3
3.47
V
Operating Case temperature
Tca
0
70
ºC
Page 2 of 13
Rev.B
05 / 2012
Data Rate Per Lane
fd
2.5
14.025
Gbps
Humidity
Rh
5
85
%
Power Dissipation
Pm
1.5
W
Fiber Bend Radius
Rb
3
Parameter
Symbol
Min
Typical
Max
Unit
Differential input impedance
Zin
90
100
110
ohm
Differential Output impedance
Differential input voltage amplitude
A lit d
Differential output voltage amplitude
Zout
90
100
110
ohm
ΔVin
300
1100
mVp-p
ΔVout
500
800
mVp-p
Skew
Sw
300
ps
Bit Error Rate
BR
E-12
Input Logic Level High
VIH
2.0
VCC
V
Input Logic Level Low
VIL
0
0.8
V
Output Logic Level High
VOH
VCC-0.5
VCC
V
Output Logic Level Low
VOL
0
0.4
V
cm
Electrical Specifications
Note:
1. BER=10^-12; PRBS 2^31-1@10.3125Gbps.
2.
3.
Differential input voltage amplitude is measured between TxNp and TxNn.
Differential output voltage amplitude is measured between RxNp and RxNn.
Optical Characteristics
Table 3 - Optical Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Transmitter
Centre Wavelength
λc
840
850
860
nm
-
RMS spectral width
∆λ
-
-
0.65
nm
-
Average launch power, each lane
Pout
-7.5
-
2.5
dBm
-
4
dB
-
-
dB
-
4
dBm
-
3.5
dB
-
-30
dB
-
Difference in launch power
between any two lanes (OMA)
Extinction Ratio
ER
3
-
Peak power, each lane
ransmitter and dispersion
penalty (TDP), each lane
Average launch power of OFF
transmitter, each lane
Eye Mask coordinates:
X1, X2, X3, Y1, Y2, Y3
TDP
Hit Ratio =
5x10-5
SPECIFICATION VALUES
0.23, 0.34, 0.43, 0.27, 0.35, 0.4
Page 3 of 13
Rev.B
05 / 2012
Receiver
Centre Wavelength
λc
840
850
860
nm
-
-5.4
dBm
1
2.4
dBm
-
Receiver Reflectance
-12
dB
-
Peak power, each lane
4
dBm
-
dBm
-
dBm
-
dB
-
Stressed receiver sensitivity in
OMA,
each lane
Average power at receiver
input, each lane
-9.5
LOS Assert
-30
LOS De-Assert – OMA
-7.5
LOS Hysteresis
0.5
Note:
1.Measured with conformance test signal at TP3 for BER = 10e-12
Pin Descriptions
Pin
Logic
1
Symbol
Name/Description
Ref.
1
GND
Module Ground
2
CML-I
Tx2-
Transmitter inverted data input
3
CML-I
Tx2+
Transmitter non-inverted data input
GND
Module Ground
4
1
5
CML-I
Tx4-
Transmitter inverted data input
6
CML-I
Tx4+
Transmitter non-inverted data input
GND
Module Ground
1
8
LVTTL-I
MODSEIL
Module Select
2
9
LVTTL-I
ResetL
Module Reset
2
VCCRx
+3.3v Receiver Power Supply
SCL
2-wire Serial interface clock
2
7
10
11
LVCMOS-I
12
LVCMOS-I/O
13
SDA
2-wire Serial interface data
2
GND
Module Ground
1
14
CML-O
RX3+
Receiver non-inverted data output
15
CML-O
RX3-
Receiver inverted data output
GND
Module Ground
16
17
CML-O
RX1+
Receiver non-inverted data output
18
CML-O
1
RX1-
Receiver inverted data output
19
GND
Module Ground
1
20
GND
Module Ground
1
RX2-
Receiver inverted data output
21
CML-O
Page 4 of 13
Rev.B
05 / 2012
22
CML-O
23
RX2+
Receiver non-inverted data output
GND
Module Ground
24
CML-O
RX4-
Receiver inverted data output
25
CML-O
RX4+
Receiver non-inverted data output
GND
Module Ground
26
1
1
27
LVTTL-O
ModPrsL
Module Present, internal pulled down to GND
28
LVTTL-O
IntL
Interrupt output, should be pulled up on host board
29
VCCTx
+3.3v Transmitter Power Supply
30
VCC1
+3.3v Power Supply
LPMode
Low Power Mode
2
GND
Module Ground
1
31
LVTTL-I
32
33
CML-I
Tx3+
Transmitter non-inverted data input
34
CML-I
Tx3-
Transmitter inverted data input
GND
Module Ground
35
36
CML-I
Tx1+
Transmitter non-inverted data input
37
CML-I
Tx1-
Transmitter inverted data input
GND
Module Ground
38
2
1
1
Notes:
1. Module circuit ground is isolated from module chassis ground within the module.
2. Open collector; should be pulled up with 4.7k – 10k ohms on host board to a voltage between 3.15Vand 3.6V.
Figure2. Electrical Pin-out Details
ModSelL Pin
The ModSelL is an input pin. When held low by the host, the module responds to 2-wire serial communication
Page 5 of 13
Rev.B
05 / 2012
commands. The ModSelL allows the use of multiple QSFP modules on a single 2-wire interface bus. When
the ModSelL is “High”, the module will not respond to any 2-wire interface communication from the host.
ModSelL has an internal pull-up in the module.
ResetL Pin
Reset. LPMode_Reset has an internal pull-up in the module. A low level on the ResetL pin for longer than the
minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to
their default state. Module Reset Assert Time (t_init) starts on the rising edge after the low level on the
ResetL pin is released. During the execution of a reset (t_init) the host shall disregard all status bits until the
module indicates a completion of the reset interrupt. The module indicates this by posting an IntL signal with
the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module will post this
completion of reset interrupt without requiring a reset.
LPMode Pin
Gigalight QSFP+ SR4 operate in the low power mode (less than 1.5 W power consumption)
This pin active high will decrease power consumption to less than 1W.
ModPrsL Pin
ModPrsL is pulled up to Vcc on the host board and grounded in the module. The ModPrsL is asserted “Low”
when the module is inserted and deasserted “High” when the module is physically absent from the host
connector.
IntL Pin
IntL is an output pin. When “Low”, it indicates a possible module operational fault or a status critical to the
host system. The host identifies the source of the interrupt by using the 2-wire serial interface. The IntL pin is
an open collector output and must be pulled up to Vcc on the host board.
Power Supply Filtering
The host board should use the power supply filtering shown in Figure3.
Figure3. Host Board Power Supply Filtering
Optical Interface Lanes and Assignment
The optical interface port is a male MPO connector .The four fiber positions on the left as
shown in Figure 4, with the key up, are used for the optical transmit signals (Channel 1 through
Page 6 of 13
Rev.B
05 / 2012
4). The fiber positions on the right are used for the optical receive signals (Channel 4 through 1).
The central four fibers are physically present.
Figure 4. Optical Receptacle and Channel Orientation
DIAGNOSTIC MONITORING INTERFACE
Digital diagnostics monitoring function is available on all Gigalight QSFP+ SR4. A 2-wire serial interface
provides user to contact with module.
The structure of the memory is shown in Figure 5. The memory space is arranged into a lower, single
page, address space of 128 bytes and multiple upper address space pages. This structure permits timely
access to addresses in the lower page, such as Interrupt Flags and Monitors. Less time critical time entries,
such as serial ID information and threshold settings, are available with the Page Select function.
The interface address used is A0xh and is mainly used for time critical data like interrupt handling in order
to enable a one-time-read for all data related to an interrupt situation. After an interrupt, IntL, has been
asserted, the host can read out the flag field to determine the affected channel and type of flag.
Page 7 of 13
Rev.B
05 / 2012
Figure5. QSFP Memory Map
Page 8 of 13
Rev.B
05 / 2012
Figure6. Low Memory Map
Figure7. Page 03 Memory Map
Page 9 of 13
Rev.B
05 / 2012
Figure8. Page 00 Memory Map
Page 10 of 13
Rev.B
05 / 2012
Page02 is User EEPROM and its format decided by user.
The detail description of low memory and page00.page03 upper memory please see SFF-8436 document.
Timing for Soft Control and Status Functions
Parameter
Symbol
Max
Unit
Conditions
Initialization Time
t_init
2000
ms
Time from power on1, hot plug or rising edge of
Reset until the module is fully functional2
Reset Init Assert Time
t_reset_init
2
μs
t_serial
2000
ms
t_data
2000
ms
Reset Assert Time
t_reset
2000
ms
LPMode Assert Time
ton_LPMode
100
μs
IntL Assert Time
ton_IntL
200
ms
IntL Deassert Time
toff_IntL
500
μs
Rx LOS Assert Time
ton_los
100
ms
Tx Fault Assert Time
ton_Txfault
200
ms
Flag Assert Time
ton_flag
200
ms
Mask Assert Time
ton_mask
100
ms
Mask Deassert Time
toff_mask
100
ms
ModSelL Assert Time
ton_ModSelL
100
μs
100
μs
Serial Bus Hardware
Ready Time
Monitor Data Ready
Time
ModSelL Deassert Time
toff_ModSelL
A Reset is generated by a low level longer than
the minimum reset pulse time present on the
ResetL pin.
Time from power on1 until module responds to
data transmission over the 2-wire serial bus
Time from power on1 to data not ready, bit 0 of
Byte 2, deasserted and IntL asserted
Time from rising edge on the ResetL pin until the
module is fully functional2
Time from assertion of LPMode (Vin:LPMode =
Vih) until module power consumption enters
lower Power Level
Time from occurrence of condition triggering IntL
until Vout:IntL = Vol
Time from clear on read3 operation of associated
flag until Vout:IntL = Voh. This includes deassert
times for Rx LOS, Tx Fault and other flag bits.
Time from Rx LOS state to Rx LOS bit set and
IntL asserted
Time from Tx Fault state to Tx Fault bit set and
IntL asserted
Time from occurrence of condition triggering flag
to associated flag bit set and IntL asserted
Time from mask bit set4 until associated IntL
assertion is inhibited
Time from mask bit cleared4 until associated IntlL
operation resumes
Time from assertion of ModSelL until module
responds to data transmission over the 2-wire serial
bus
Time from deassertion of ModSelL until the module
does not respond to data transmission over the 2-wire
serial bus
Power_over-ride or
Power-set Assert Time
ton_Pdown
100
ms
Time from P_Down bit set 4 until module power
consumption enters lower Power Level
Power_over-ride or
Power-set Deassert
Time
toff_Pdown
300
ms
Time from P_Down bit cleared4 until the module
is fully functional3
Page 11 of 13
Rev.B
05 / 2012
Note:
1. Power on is defined as the instant when supply voltages reach and remain at or above the minimum specified value.
2. Fully functional is defined as IntL asserted due to data not ready bit, bit 0 byte 2 deasserted.
3. Measured from falling clock edge after stop bit of read transaction.
4. Measured from falling clock edge after stop bit of write transaction.
Figure9. Timing Specifications
Mechanical Dimensions
Figure10. Mechanical Specifications
Page 12 of 13
Rev.B
05 / 2012
Ordering information
Part Number
Product Description
GQS-MPO560-SR4C
56Gb/s QSFP+ SR4, 100m on OM3 Multimode Fiber (MMF)and 150m on OM4 MMF
References
1. SFF-8436 QSFP+
2. Infiniband IB-4x-SX, IB-4x-DDR-SX, IB-4x-QDR-SX,56G-IB-FDR,
3. Ethernet 40GBASE-SR4
Important Notice
Performance figures, data and any illustrative material provided in this data sheet are typical and must be
specifically confirmed in writing by GIGALIGHT before they become applicable to any particular order or
contract. In accordance with the GIGALIGHT policy of continuous improvement specifications may change
without notice.
The publication of information in this data sheet does not imply freedom from patent or other protective rights
of GIGALIGHT or others. Further details are available from any GIGALIGHT sales representative.
E-mail: sales@gigalight.com.cn
Web : http://www.gigalight.com.cn
Page 13 of 13
Rev.B
05 / 2012
Download PDF