Tracking/Termination Synchronous PWM Switcher w/ Integrated

Typical Size
(6,4 mm X 9,7 mm )
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005

FEATURES
D Tracks Externally Applied Reference Voltage
D 30-mΩ, 12-A Peak MOSFET Switches for High
D
D
D
D
Efficiency at 6-A Continuous Output Source
or Sink Current
6% to 90% VIN Output Tracking Range
PWM Frequency Range:
Fixed 350 kHz or Adjustable 280 to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
D DDR Memory Termination Voltage
D Active Termination of GTL and STL
D
D
High-Speed Logic Families
DAC Controlled High Current Output Stage
Precision Point of Load Power Supply
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators, the
TPS54672 active bus termination synchronous PWM
converter integrates all required active components.
Included on the substrate with the listed features are a true,
high performance, voltage error amplifier that enables
maximum performance and flexibility in choosing the
output filter L and C components; an under-voltagelockout circuit to prevent start-up until the input voltage
reaches 3 V; a slow-start control to limit in-rush currents;
and a status output to indicate valid operating conditions.
The TPS54672 is available in a thermally enhanced 28-pin
TSSOP (PWP) PowerPAD package, which eliminates
bulky heatsinks. TI provides evaluation modules and the
SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet
aggressive equipment development cycles.
SIMPLIFIED SCHEMATIC
Typical DDR Memory Termination Regulator Circuit
Input Voltage
3V−6V
0.56 µH
VIN
CIN
CIN
VTTQ
PH
ENA
LOAD TRANSIENT RESPONSE
Output Voltage
(50 mV/div AC Coupled)
COUT
BOOT
CBOOT
PGND
VDDQ
TPS54672
REFIN
VBIAS VSENSE
AGND COMP
Output Current
(2A/div)
CBIAS
10 µs/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
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Copyright  2001−2005, Texas Instruments Incorporated
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
REFIN VOLTAGE
PACKAGE
PART NUMBER
Plastic HTSSOP (PWP)(1)
0.2 V to 1.75 V
TPS54672PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54672PWPR). See the application section
of the data sheet for PowerPAD drawing and layout information.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54672
Input voltage range, VI
Output voltage range, VO
Source current, IO
VIN, ENA
−0.3 V to 7 V
RT
−0.3 V to 6 V
VSENSE, REFIN
−0.3 V to 4 V
BOOT
−0.3 V to 17 V
VBIAS, COMP, STATUS
−0.3 V to 7 V
PH
−0.3 V to 10 V
PH
Internally Limited
COMP, VBIAS
Sink current, IS
6 mA
PH
12 A
COMP
6 mA
STATUS
10 mA
±0.6 V
Voltage differential, AGND to PGND
Operating virtual junction temperature range, TJ
−40°C to 125°C
Storage temperature, Tstg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28 Pin PWP with solder
18.2 °C/W
5.49 W(3)
3.02 W
2.20 W
1.36 W
0.99 W
28 Pin PWP without solder
40.5 °C/W
2.48 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
ADDITIONAL 6A SWIFT DEVICES, (REFER TO SLVS398 AND SLVS400)
2
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
DEVICE
OUTPUT VOLTAGE
TPS54611
0.9 V
TPS54614
1.8 V
TPS54610
Adjustable
TPS54612
1.2 V
TPS54615
2.5 V
TPS54673
Disabled sink during
startup
TPS54613
1.5 V
TPS54616
3.3 V
TPS54680
Sequencing
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
VID
I(Q)
Differential voltage, AGND to PGND
Quiescent current
3.0
6.0
V
−0.30
0.30
V
Switching freq. = 350 kHz, RT open
10
Switching freq. = 500 kHz, RT = 100 kΩ
16
24
1
1.4
2.95
3.00
Shutdown, SS/ENA = 0 V
16
mA
UNDERVOLTAGE LOCKOUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO(1)
V
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Cumulative regulation accuracy (relative to
REFIN)
IO = − 6A to 6A,
Switching frequency = 350 kHz,
REFIN = 1.25 V(1)
−1.5%
1.5%
OSCILLATOR
Internally set—free running frequency
RT open
280
Externally set—free running frequency range
RT = 68 kΩ to 180 kΩ
280
Externally set—free running frequency
accuracy
RT = 100 kΩ (1% resistor to AGND)
460
Ramp valley
350
500
420
kHz
700
kHz
540
kHz
0.75
Ramp amplitude (peak-to-peak)
Minimum controllable on time(1)
V
1
V
200
Maximum duty cycle (1)
ns
90%
Error amplifier open loop voltage gain
1 kΩ COMP to AGND (1)
Error amplifier unity gain bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (1)
Error amplifier common mode input voltage
range(1)
90
110
3
5
0
Error amplifier common mode rejection ratio(1)
dB
MHz
2.85
65
V
dB
Input bias current, VSENSE
VSENSE = REFIN = 1 V
60
250
nA
Input bias current, REFIN
VSENSE = REFIN = 1.25 V
60
250
nA
Input offset voltage, REFIN
VSENSE = REFIN = 1.25 V
mV
−1.5
1.5
Input voltage range, REFIN(1)
0
1.8
Output voltage slew rate (symmetric), COMP
1
Common mode output voltage range, COMP
IO = 3 mA
IO = −3 mA
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
10-mV overdrive (1)
Enable threshold voltage, ENA
Leakage current, ENA
(1) Ensured by design
(2) Static resistive loads only
VI= 5.5 V
V
V/µs
2.65
0.2
0.82
Enable hysteresis voltage, ENA (1)
Falling edge deglitch, ENA (1)
1.4
V
70
85
ns
1.20
1.40
V
0.03
V
2.5
µs
1
µA
3
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
ELECTRICAL CHARACTERISTICS Continued
TJ = –40°C to +125°C, VI = 3 V to 6 V over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OSCILLATOR (CONTINUED)
Output saturation voltage, STATUS
Leakage current, STATUS
Current limit trip point
I(sink) = 2.5 mA
VI = 5.5 V
VIN = 3 V (1)
0.18
VIN = 6 V (1)
7
10
10
12
Current limit leading edge blanking time
(1) Ensured by design
(2) Static resistive loads only
(3) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) ensured by design
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
4
A
ns
150
ns
165
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
ENA
REFIN
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
°C
°C
10
IO = 6A, VI = 3 V (3)
IO = 6A, VI = 6 V (3)
AGND
VSENSE
COMP
STATUS
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
µA
200
135
Thermal shutdown hysteresis (1)
Low/high-side N-MOSFET
V
1
100
Current limit total response time
Thermal shutdown trip point (1)
rDS(on)
0.3
36
65
26
47
mΩ
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, VBIAS capacitor, and RT resistor. Connect PowerPAD to
AGND.
BOOT
5
Bootstrap output. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
ENA
27
Enable input. Logic high enables oscillator, PWM control and MOSFET driver circuits. Logic low disables operation and
places device in low quiescent current state.
PGND
15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to
AGND is recommended.
PH
6−14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
REFIN
26
External reference input. High impedance input to slow-start and error amplifier circuits.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
STATUS
4
Open drain output. Asserted low when VIN < UVLO threshold, VBIAS and internal reference are not settled or thermal
shutdown active. Otherwise STATUS is high.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high-quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE
20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high-quality, low-ESR 10-µF ceramic capacitor.
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
Enable
Comparator
Falling
Edge
Deglitch
ENA
1.2 V
Hysteresis: 0.03
V
2.5 µs
VIN UVLO
Comparator
2.95 V
Hysteresis: 0.16
V
VDDQ
VIN
ILIM
Comparator
Thermal
Shutdown
150°C
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
VIN
REG
VBIAS
SHUTDOWN
100 ns
BOOT
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
PH
REFIN
Slow-start
(0.25 V/ms minimum)
+
−
R Q
Error
Amplifier
S
PWM
Comparator
LOUT
CO
Adaptive Dead-Time
and
Control Logic
VIN
30 mΩ
PGND
OSC
TPS54672
STATUS
SS_DIS
VSENSE
RELATED DC/DC PRODUCTS
D TPS54372
D TPS54972
D TPS54872
6
COMP
RT
Vtt
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
IO = 6 A
50
40
IO = 3 A
30
20
10
0
25
85
TJ − Junction Temperature − °C
f − Internally Set Oscillator Frequency − kHz
VIN = 3.3 V
0
−40
VIN = 5 V
50
IO = 6 A
40
30
IO = 3 A
20
10
0
−40
125
0
25
85
TJ − Junction Temperature − °C
Figure 1
125
600
500
400
300
1.255
1.250
1.245
85
1
2
3
4
5
3.5
Gain
−140
−160
0
6
9
Slow-Start Time − ms
−80
−120
40
5.5
SLOW-START TIME
vs
JUNCTION TEMPERATURE
−40
−100
60
4
4.5
5
IO − Input Voltage − V
10
Phase − Degrees
Gain − dB
1.248
−20
−60
20
1.249
Figure 6
0
Phase
125
1.250
3
6
ERROR AMPLIFIER OPEN LOOP RESPONSE
RL = 10 kΩ,
CL = 160 pF,
TA = 25°C
85
1.251
Figure 5
140
25
TA = 85°C
REFIN = 1.25 V,
IO = 3 A
1.252
IO − Output Current − A
Figure 4
80
0
1.247
0
125
TJ − Junction Temperature − °C
100
250
−40
1.253
TA = 85°C
REFIN = 1.25 V
1.240
120
300
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
VO − Output Voltage Regulation − V
VO − Output Voltage Regulation − V
700
25
350
Figure 3
1.260
0
400
TJ − Junction Temperature − °C
OUTPUT VOLTAGE REGULATION
vs
OUTPUT CURRENT
800
200
−40
450
Figure 2
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
f − Externally Set Oscillator Frequency − kHz
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
60
60
Drain Source On-State Resistance − m Ω
Drain Source On-State Resistance − m Ω
DRAIN-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
8
7
6
−180
−20
1
10
100
−200
1 k 10 k 100 k 1 M 10 M
f − Frequency − Hz
Figure 7
5
−40
0
25
85
125
TJ − Junction Temperature − °C
Figure 8
7
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
FEEDBACK CIRCUIT
Figure 9 shows the schematic diagram for a typical DDR
memory or GTL bus termination application using the
TPS54672. The TPS54672 (U1) can provide greater than
6 A of output current. For proper operation, the exposed
thermal PowerPAD underneath the integrated circuit
package needs to be soldered to the printed-circuit board.
R1, R2, R3, C1, C2 and C3 form the loop compensation
network for the circuit. For this design, a Type 3 topology
is used. The compensation network, along with the output
filter inductor and capacitor delivers a crossover frequency
of 135 kHz with 50° of phase margin.
COMPONENT SELECTION
OPERATING FREQUENCY
The values for the components used in this design
example were selected for best load transient and tracking
response. Additional design information is available at
www.ti.com.
In the application circuit, RT is grounded through a 71.5-kΩ
resistor to select the maximum frequency of 700 kHz. To
set a different frequency, place a 68-kΩ to 180-kΩ resistor
between RT (pin 28) and analog ground or leave RT
floating to select the default 350 kHz. The resistance can
be calculated using the following equation:
INPUT VOLTAGE
The input voltage range is 3 to 5.5 VDC. The input filter
(C4) is a 10-µF ceramic capacitor (Taiyo Yuden). C8, also
a 10-µF ceramic capacitor (Taiyo Yuden) that provides
high frequency decoupling of the TPS54672 from the input
supply, must be located as close as possible to the device.
Ripple current is carried in both C8 and C4, and the return
path to PGND should avoid the current circulating in the
output capacitors C7 and C10.
VI
C4
10 µF
2
3
4
5
4.75 kΩ
C2
2700 pF
6
C6
0.047 µF
C1
100 pF
7
8
9
10
R1
10 kΩ
R3
182 Ω
11
12
13
14
C3
0.01 µF
500 kHz
SwitchingFrequency
U1
TPS54672
1
R2
R+
AGND
(1)
VDDQ
RT
28
R6
10 kΩ
27
VSENSE
ENA
26
REFIN
COMP
25
STATUS
VBIAS
24
BOOT
VIN
23
PH
VIN
22
PH
VIN
21
PH
VIN
20
PH
VIN
19
PH
PGND
18
PH
PGND
17
PH
PGND
16
PH
PGND
15
PH
PGND
PwrPad
L1
0.56 µH
100 [kW]
C9
0.1 µF
R7
10 kΩ
C8
10 µF
VTTQ
+
C7
150 µF
+
C10
150 µF
C11
1 µF
Figure 9. Application Circuit Optimized For Size And Performance
8
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
OUTPUT FILTER
The output filter is composed of a 0.56-µH Coilcraft
inductor (D01813P−561HC) and two 150-µF Cornell
Dublier capacitors (ESRD151M06R). The inductor is a low
dc resistance type. The capacitors used are 4 V POSCAP
types with a maximum ESR of 0.040 Ω.
PCB LAYOUT
Figure 10 shows a generalized PCB layout guide for the
TPS54672. The VIN pins should be connected together on
the printed circuit board (PCB) and bypassed with a low
ESR ceramic bypass capacitor. Minimize the loop area
formed by the bypass capacitor connections, the VIN pins,
and the TPS54672 ground pins. The minimum
recommended bypass capacitance is 10 µF ceramic with
a X5R or X7R dielectric and the optimum placement is
closest to the VIN pins and the PGND pins.
The TPS54672 has two internal grounds (analog and
power). Inside the TPS54672 the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. Noise injected between the
two grounds can degrade the performance of the
TPS54672, particularly at higher output currents. Ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground traces are
recommended. There should be an area of ground on the
top layer under the IC, with an exposed area for connection
to the PowerPAD. Use vias to connect this ground area to
any internal ground planes. Use additional vias at the
ground side of the input and output filter capacitors as well.
The AGND and PGND pins should be tied to the PCB
ground by connecting them to the ground area under the
device as shown. The only components that should tie
directly to the power ground plane are the input capacitors,
the output capacitors, the input voltage decoupling
capacitor, and the PGND pins of the TPS54672. Use a
separate wide trace for the analog ground signal path. This
analog ground should be used for the voltage set point
divider, timing resistor RT, and bias capacitor grounds.
Connect this trace directly to AGND (pin 1).
The PH pins should be tied together and routed to the
output inductor. Since the PH connection is the switching
node, the inductor should be located very close to the PH
pins and the area of the PCB conductor minimized to
prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node and
the BOOT pin as shown. Keep the boot capacitor close to
the IC and minimize the conductor trace lengths.
Connect the output filter capacitor(s) as shown between
the VOUT trace and PGND. It is important to keep the loop
formed by the PH pins, Lout, Cout, and PGND as small as
practical.
Place the compensation components from the VOUT trace
to the VSENSE, and COMP pins. Do not place these
components too close to the PH trace. Due to the size of
the IC package and the device pin out, the components
must be routed somewhat close, however maintaining as
much separation as possible while still keeping the layout
compact.
Connect the bias capacitor from the VBIAS pin to analog
ground using the isolated analog ground trace. If an RT
resistor is used, connect it to this trace as well.
9
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
ANALOG GROUND TRACE
AGND
RT
COMPENSATION
NETWORK
TRACKING VOLTAGE
ENA
VSENSE
COMP
REFIN
RESISTOR DIVIDER
BIAS CAPACITOR
PWRGD
BOOT
CAPACITOR
BOOT
PH
VOUT
PH
OUTPUT INDUCTOR
OUTPUT
FILTER
CAPACITOR
VBIAS
VIN
EXPOSED
POWERPAD
AREA
VIN
PH
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
PH
PGND
PH
PGND
VIN
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 10. TPS54672 PCB Layout
10
NETWORK
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SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
8 PL Ø 0.0130
4 PL
Ø 0.0180
any area available should be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the twelve recommended
that enhance thermal performance should be included in
areas not under the device package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.06
0.0150
0.0339
0.0650
0.0500
0.3820 0.3478 0.0500
0.0500
0.2090
0.0256
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
Larger Area
0.1700
0.1340
Minimum Recommended Top
Side Analog Ground Area
0.0630
0.0400
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
EFFICIENCY
vs
OUTPUT CURRENT
LOAD TRANSIENT RESPONSE
95
VI = 3.3 V, VO = 1.25 V, L = 2.2 uH
Output Voltage
(50 mV/div AC Coupled)
90
Efficiency − %
85
Output Current
(2A/div)
80
75
VI = 3.3 V,
VO = 0.9 V,
L = 0.56 uH
70
65
VI = 5 V,
VO = 1.75 V,
L = 0.56 uH
60
55
50
0
10 µs/div
Figure 12
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54672 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
1
2
3
4
5
6
7
IO − Output Current − A
Figure 13
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
11
www.ti.com
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
2.8 V. Note that hysteresis in the UVLO comparator and a
2.5-µs rising and falling edge deglitch circuit reduce the
likelihood of shutting the device down due to noise on VIN.
Enable (ENA)
The enable pin, ENA, provides a digital control to enable
or disable (shutdown) the TPS54672. An input voltage of
1.4 V or greater ensures that the TPS54672 is enabled. An
input of 0.82 V or less ensures that device operation is
disabled. These are not standard logic thresholds, even
though they are compatible with TTL outputs.
When ENA is low, the oscillator, slow-start, PWM control
and MOSFET drivers are disabled and held in an initial
state ready for device start-up. On an ENA transition from
low to high, device start-up begins with the output starting
from 0 V.
Slow-Start
The slow-start circuit provides start-up slope control of the
output voltage to limit in-rush currents. The nominal
internal slow-start rate is 0.25 V/ms with the maximum rate
being 0.35 V/ms. When the voltage on REFIN rises faster
than the internal slope or is present when device operation
is enabled, the output rises at the internal rate. If the
reference voltage on REFIN rises more slowly, then the
output rises at about the same rate as REFIN.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.7 V, and
that loads with ac or digital switching noise may degrade
performance. The VBIAS pin may be useful as a reference
voltage for external circuits.
Oscillator Frequency (RT)
The oscillator frequency can be set to an internally fixed
value of 350 kHz by leaving the RT pin unconnected
(floating). If a different frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor to the RT pin to ground. The operating frequency
is approximated by the following equation, where R is the
resistance from RT to AGND:
Switching Frequency + 100 kW
R
12
500 [kHz]
(2)
The following table summarizes the frequency selection
configurations:
FREE RUNNING FREQUENCY
RT PIN
350 kHz, internally set
Float
Externally set 280 kHz to 700 kHz
R = 68 k to 180 k
Error Amplifier (REFIN, VSENSE, COMP)
The high performance voltage error amplifier, with wide
5MHz bandwidth, low 1.5 mV-max offset, 1.4 V/µs slew
rate, and ground rail input range differentiates the
TPS54672 from most dc/dc converters. The user is given
the flexibility to use a wide range of output L and C filter
components to suit the particular application needs. Type
2 or type 3 compensation can be employed using external
compensation components.
The REFIN input range includes ground which allows 0%
duty cycle during transient conditions. The user should
note that steady state regulation accuracy of voltages less
than 0.84 V is limited by the minimum controllable ON
time.
PWM Control
Signals from the error amplifier output, oscillator and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch
and portions of the adaptive dead time and control logic
block. During steady state operation below the current limit
threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as REFIN. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54672 is capable of sinking current continuously
until the output reaches the regulation set-point.
www.ti.com
SLVS397C − JULY 2001 − REVISED FEBRUARY 2005
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET on to decrease the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the gate drive voltage to the low-side
FET is below 2 V, while the low-side driver does not turn
on until the voltage at the junction of the power MOSFETs
(PH pin) is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and internal 2.5-Ω bootstrap switch connected
between the VIN and BOOT pins. The bootstrap switch is
turned on when the low-side FET is on to charge the BOOT
capacitor. The low resistance of the bootstrap switch
improves drive efficiency and reduces external component
count.
Overcurrent Protection
The cycle by cycle current limiting is achieved using a
sense-FET on the high-side MOSFET and differential
amplifier with preset overcurrent threshold. The high-side
MOSFET is turned off within 200 ns of the voltage on the
sense-FET exceeding the current limit threshold. A 100-ns
leading edge blanking circuit prevents false tripping of the
current limit when the high-side switch is turning on.
Current limit detection occurs only when current flows from
VIN to PH when current is being sourced to the output filter.
Load protection during current sink operation is provided
by thermal shutdown.
Thermal Shutdown
Thermal shutdown turns off the power MOSFETs and
disables the control circuits if the junction temperature
exceeds the 150°C. The device is released from shutdown
automatically when the junction temperature decreases to
10°C, and starts up under control of the slow-start circuit.
Status (STATUS)
The status pin is an open drain output that indicates when
internal conditions are sufficient for proper operation.
STATUS can be coupled back to a system controller or
monitor circuit to indicate that the termination or tracking
regulator is ready for start up. STATUS is high impedance
when the TPS54672 is operating or ready to be enabled.
STATUS is active low if any of the following occur:
D VIN < UVLO threshold
D VBIAS or internal reference have not settled.
D Thermal shutdown is active.
13
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPS54672PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54672
TPS54672PWPG4
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54672
TPS54672PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54672
TPS54672PWPRG4
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54672
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54672PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
28
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.2
1.8
12.0
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54672PWPR
HTSSOP
PWP
28
2000
367.0
367.0
38.0
Pack Materials-Page 2
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