Capacitor-Free, 150-mA, LDO With Foldback Current Limit for

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TLV713P-Q1
SBVS266 – MAY 2015
TLV713P-Q1 Capacitor-Free, 150-mA, Low-Dropout Regulator
With Foldback Current Limit for Portable Devices
1 Features
3 Description
•
The TLV713P-Q1 series of low-dropout (LDO) linear
regulators are low quiescent current LDOs with
excellent line and load transient performance and are
designed for power-sensitive applications. These
devices provide a typical accuracy of 1%.
1
•
•
•
•
•
•
•
•
•
•
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
Input Voltage Range: 1.4 V to 5.5 V
Stable Operation With or Without Capacitors
Foldback Overcurrent Protection
Package: 5-Pin SOT-23
Very Low Dropout: 230 mV at 150 mA
Accuracy: 1%
Low IQ: 50 µA
Available in Fixed-Output Voltages:
– 1 V to 3.3 V
High PSRR: 65 dB at 1 kHz
Active Output Discharge
2 Applications
•
•
•
•
•
•
•
Automotive Head Units
Audio Amplifiers
DI Clusters
ADAS ECUs
Microprocessor Rails
USBs
Body Electronics
The TLV713P-Q1 series of devices is designed to be
stable without an output capacitor. The removal of the
output capacitor allows for a very small solution size.
However, the TLV713P-Q1 series is also stable with
any output capacitor if an output capacitor is used.
The TLV713P-Q1 also provides inrush current control
during device power-up and enabling. The TLV713PQ1 limits the input current to the defined current limit
to avoid large currents from flowing from the input
power source. This functionality is especially
important in battery-operated devices.
The TLV713P-Q1 series is available in a standard
DBV package and provides an active pulldown circuit
to quickly discharge output loads. The TLV713P-Q1
is suited for automotive applications because the
device is qualified for AEC-Q100 grade 1.
Device Information(1)
PART NUMBER
PACKAGE
TLV713P-Q1
SOT-23 (5)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Typical Application Circuit
Dropout Voltage vs Output Current
350
IN
VOUT = 1.8V
VOUT = 3.3V
OUT
Device
CIN
EN
Optional
ON
OFF
COUT
GND
Optional
Dropout Voltage (mV)
300
250
200
150
100
50
0
0
15
30
45
60
75
90 105
Output Current (mA)
120
135
150
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV713P-Q1
SBVS266 – MAY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
8
8.1 Application Information............................................ 13
8.2 Typical Application .................................................. 14
8.3 Do's and Don'ts ....................................................... 15
9 Power-Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
10.3 Power Dissipation ................................................. 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 13
10
10
11
12
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
19
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
2
DATE
REVISION
NOTES
May 2015
*
Initial release.
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5 Pin Configurations and Functions
DBV Package
5-Pin SOT-23
Top View
IN
1
GND
2
EN
3
5
OUT
4
NC
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
SOT-23
Enable pin. Driving EN over 0.9 V turns on the regulator.
Driving EN below 0.4 V puts the regulator into shutdown mode.
EN
3
I
GND
2
—
IN
1
I
NC
4
—
No internal connection
OUT
5
O
Regulated output voltage pin. For best transient response, a small 1-μF ceramic capacitor is
recommended from this pin to ground. See the Input and Output Capacitor Considerations section in
the Feature Description for more details.
—
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
Ground pin
Input pin. A small capacitor is recommended from this pin to ground. See the Input and Output
Capacitor Considerations section in the Feature Description for more details.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (TJ = 25°C), unless otherwise noted. All voltages are with respect to GND. (1)
Voltage
Current
MIN
MAX
UNIT
Input, VIN
–0.3
6
V
Enable, VEN
–0.3
VIN + 0.3
V
Output, VOUT
–0.3
3.6
V
Maximum output, IOUT(max)
Internally limited
Output short-circuit duration
Total power dissipation
Temperature
(1)
Indefinite
Continuous, PD(tot)
See the Thermal Information
Storage, Tstg
–55
150
°C
Junction, TJ
–55
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
NOM
MAX
5.5
UNIT
VIN
Input voltage
1.4
V
VEN
Enable range
0
VIN
V
IOUT
Output current
0
150
mA
CIN
Input capacitor
0
1
COUT
Output capacitor
0
0.1
TJ
Operating junction temperature range
µF
–40
100
µF
125
°C
6.4 Thermal Information
TLV713P-Q1
THERMAL METRIC
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
249
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
172.7
°C/W
RθJB
Junction-to-board thermal resistance
76.7
°C/W
ψJT
Junction-to-top characterization parameter
49.7
°C/W
ψJB
Junction-to-board characterization parameter
75.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
4
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6.5 Electrical Characteristics
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is
greater), IOUT = 1 mA, VEN = VIN, and COUT = 0.47 µF, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VIN
Input voltage range
VOUT
Output voltage
range
DC output accuracy
TEST CONDITIONS
TYP
MAX
UNIT
1.4
5.5
V
1
3.3
V
VOUT ≥ 1.8 V; TJ, TA = 25°C
–1%
1%
VOUT < 1.8 V; TJ, TA = 25°C
–20
20
VOUT ≥ 1.2 V; –40°C ≤ TJ, TA ≤ 125°C
–1.5%
1.5%
VOUT < 1.2 V; –40°C ≤ TJ, TA ≤ 125°C
–50
50
mV
5
mV
10
30
mV
1 V ≤ VOUT < 1.8 V, IOUT = 150 mA
600
900
mV
1.8 V ≤ VOUT < 2.1 V, IOUT = 30 mA
70
1.8 V ≤ VOUT < 2.1 V, IOUT = 150 mA
350
Line regulation
Max [VOUT(nom) + 0.5 V, VIN = 2.0 V] ≤ VIN ≤ 5.5 V
ΔVOUT(ΔIOUT)
Load regulation
0 mA ≤ IOUT ≤ 150 mA
VOUT = 0.98 × VOUT(nom);
TJ, TA = –40°C to 85°C
Dropout voltage
VOUT = 0.98 × VOUT(nom);
TJ, TA = –40°C to 125°C
mV
1
ΔVOUT(ΔVIN)
VDO
MIN
mV
575
mV
2.5 V ≤ VOUT < 3 V, IOUT = 30 mA
50
2.5 V ≤ VOUT < 3 V, IOUT = 150 mA
246
3 V ≤ VOUT < 3.6 V, IOUT = 30 mA
46
3 V ≤ VOUT < 3.6 V, IOUT = 150 mA
230
420
mV
1 V ≤ VOUT < 1.8 V, IOUT = 150 mA
600
1020
mV
1.8 V ≤ VOUT < 2.1 V, IOUT = 150 mA
350
695
mV
2.5 V ≤ VOUT < 3 V, IOUT = 150 mA
246
600
mV
3 V ≤ VOUT < 3.6 V, IOUT = 150 mA
230
560
mV
mV
445
mV
mV
IGND
Ground pin current
IOUT = 0 mA
50
75
µA
ISHUTDOWN
Shutdown current
VEN ≤ 0.4 V; 2.0 V ≤ VIN ≤ 5.5 V; TJ, TA = 25°C
0.1
1
µA
PSRR
Power-supply
rejection ratio
VIN = 3.3 V,
VOUT = 2.8 V,
IOUT = 30 mA
f = 100 Hz
70
dB
f = 10 kHz
55
dB
f = 1 MHz
55
dB
73
µVRMS
100
µs
Vn
Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA
tSTR
Start-up time
VHI
Enable high
(enabled)
VLO
Enable low
(disabled)
IEN
EN pin current
EN = 5.5 V
0.01
RPULLDOWN
Pulldown resistor
VIN = 4 V
120
ILIM
ISC
TSD
Output current limit
Short-circuit current
Thermal shutdown
COUT = 1.0 μF, IOUT = 150 mA
0.9
VIN
V
0
0.4
V
µA
Ω
VIN = 3.8 V, VOUT = 3.3 V
175
mA
VIN = 3.0 V, VOUT = 2.5 V
175
mA
VIN = 2.3 V, VOUT = 1.8 V
175
mA
VIN = 2.0 V, VOUT = 1.2 V
175
mA
VIN = 2.0 V, VOUT = 1.0 V
175
mA
VOUT = 0 V
40
mA
Shutdown, temperature increasing
158
°C
Reset, temperature decreasing
140
°C
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6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
1.8
1.802
Output Voltage (V)
1.8
1.799
1.798
1.797
1.796
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.798
Output Voltage (V)
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.801
1.796
1.794
1.792
1.79
1.795
1.788
1.794
1.786
1.793
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
0
5.5
Figure 1. 1.8-V Line Regulation vs
VIN and Temperature
40
60
80
100
Output Current (mA)
120
140
160
Figure 2. 1.8-V Load Regulation vs
IOUT and Temperature
1.798
500
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
1.7975
400
Dropout Voltage (mV)
1.797
Output Voltage (V)
20
1.7965
1.796
1.7955
1.795
300
200
100
1.7945
1.794
-40
0
-20
0
20
40
60
80
Temperature (qC)
100
120
140
0
Figure 3. 1.8-V Output Voltage vs Temperature
Dropout Voltage (mV)
Ground Pin Current (PA)
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
300
250
200
150
100
50
0
0
25
50
75
100
Output Current (mA)
125
150
65
62.5
60
57.5
55
52.5
50
47.5
45
42.5
40
37.5
35
32.5
30
125
150
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
2
Figure 5. 3.3-V Dropout Voltage vs
IOUT and Temperature
6
50
75
100
Output Current (mA)
Figure 4. 1.8-V Dropout Voltage vs
IOUT and Temperature
400
350
25
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2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
Figure 6. Ground Pin Current vs
VIN and Temperature
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Typical Characteristics (continued)
80
500
75
300
200
70
65
60
55
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
50
45
40
Ground Pin Current (nA)
Ground Pin Current (PA)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
100
50
30
20
10
TJ = -40qC
TJ = 0qC
TJ = 25qC
TJ = 85qC
TJ = 125qC
5
3
2
1
35
0
20
40
60
80
100
Output Current (mA)
120
140
2
160
2.5
Figure 7. Ground Pin Current vs
IOUT and Temperature
90
80
60
PSRR (dB)
PSRR (dB)
70
50
40
30
COUT = 0 PF, IOUT = 150 mA
COUT = 0 PF, IOUT = 30 mA
COUT = 1 PF, IOUT = 150 mA
COUT = 1 PF, IOUT = 30 mA
10
0
-10
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
Figure 9. Power-Supply Rejection Ratio vs Frequency and
COUT
Voltage Noise (PV/—Hz)
5
3
2
3.5
4
Input Voltage (V)
4.5
5
5.5
1E+6
1E+7
Figure 8. Shutdown Current vs
VIN and Temperature
100
20
3
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
1E+1
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
Figure 10. Power-Supply Rejection Ratio vs Frequency and
IOUT
COUT = 0 PF
COUT = 1 PF
VIN
Channel 1
1 V/div
1
0.5
0.3
0.2
0.1
0.05
0.03
0.02
Channel 3
200 mV/div
VOUT
0.01
0.005
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
Time (200 ms/div)
VIN = 3 V to 4 V , IOUT = 0 mA, VOUT = 1.8 V, CIN = COUT = 0 µF
Figure 11. Output Spectral Noise Density
Figure 12. Line Transient
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
VIN
Channel 1
1 V/div
Channel 1
20 mV/div
VOUT
Channel 3
0.5 V/div
VOUT
IOUT
Channel 4
20 mA/div
Time (200 ms/div)
Time (200 ms/div)
VIN = 3 V to 4 V, IOUT = 150 mA, VOUT = 1.8 V, CIN = COUT = 0 µF
VIN = 5 V, VOUT = 1.8 V, CIN = COUT = 1 µF
Figure 13. Line Transient
Figure 14. 0-mA to 20-mA Load Transient
3.5
Output Voltage (V)
3
Channel 3
200 mV/div
VOUT
IOUT
Channel 4
20 mA/div
2.5
2
1.5
1
0.5
0
0
50
Time (200 ms/div)
100
150
200
Output Current (mA)
250
300
VIN = 5 V, VOUT = 1.8 V, CIN = COUT = 0 µF
Figure 16. 3.3-V Output Voltage vs Output Current
(Foldback Current Limit)
Figure 15. 0-mA to 20-mA Load Transient
2
Output Voltage (V)
1.75
Channel 3
0.5 V/div
VOUT
IOUT
Channel 4
50 mA/div
1.5
1.25
1
0.75
0.5
0.25
0
0
Time (200 ms/div)
50
100
150
200
250
Output Current (mA)
300
350
VIN = 5 V, VOUT = 1.8 V, CIN = COUT = 0 µF
Figure 17. 0-mA to 100-mA Load Transient
8
Figure 18. 1.8-V Output Voltage vs Output Current
(Foldback Current Limit)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT =
10 mA, VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V, unless otherwise noted. Typical values are at TJ = 25°C.
4
VIN
VOUT
Channel 3
200 mV/div
3
Voltage (V)
VOUT
IOUT
Channel 4
50 mA/div
2
1
0
0
0.5
1
Time (s)
Time (200 ms/div)
2
IOUT = 150 mA
VIN = 5 V, VOUT = 1.8 V, CIN = COUT = 0 µF
Figure 20. VIN Power-Up and Power-Down
Figure 19. 10-mA to 150-mA Load Transient
Channel 1
2 V/div
1.5
Channel 1
100 mV/div
VIN
VIN
EN
Channel 2
2 V/div
Channel 3
1 V/div
Channel 2
1 V/div
Channel 3
1 V/div
VOUT
IOUT
EN
VOUT
Channel 4
50 mA/div
Channel 4
50 mA/div
ILOAD
Time (50 ms/div)
Time (100 ms/div)
VIN = 3 V, IOUT = 150 mA, VOUT = 1.8 V, CIN = COUT = 0 µF
VIN = 2.3 V, IOUT = 90 mA, COUT = 10 µF, VOUT = 1.8 V,
CIN = 1 µF
Figure 21. Start-Up With EN
Figure 22. Start-Up With EN
Channel 1
2 V/div
Channel 2
2 V/div
VIN
EN
VOUT
Channel 3
1 V/div
Channel 4
100 mA/div
IOUT
Time (50 ms/div)
VIN = 3 V, IOUT = 0 mA, VOUT = 1.8 V, CIN = COUT = 1 µF
Figure 23. Shutdown Response With Enable
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7 Detailed Description
7.1 Overview
These devices belong to a family of low-dropout (LDO) regulators that consume low quiescent current and
deliver excellent line and load transient performance. These characteristics, combined with low noise and very
good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for RF portable applications.
This family of regulators offers current limit and thermal protection. Device operating junction temperature is
–40°C to 125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
EN
120 W
Bandgap
Logic
GND
10
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV713P-Q1 uses a UVLO circuit that disables the output until the input voltage is greater than the rising
UVLO voltage. This circuit ensures that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry, VIN(min). During UVLO disable, the output of
the TLV713P-Q1 is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
The TLV713P-Q1 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1.
t=
120 · RL
120 + RL
· COUT
(1)
7.3.3 Foldback Current Limit
The TLV713P-Q1 has an internal foldback current limit that helps protect the regulator during fault conditions.
The current supplied by the device is gradually reduced when the output voltage decreases. When the output is
shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in
current limit, and is calculated by Equation 2:
VOUT = ILIMIT × RLOAD
(2)
The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device
turns off. The device is turned on by the internal thermal shutdown circuit during cool down. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section
for more details.
The TLV713P-Q1 PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated,
external limiting to 5% of the rated output current is recommended.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, protecting the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin
of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection
is triggered; use worst-case loads and signal conditions.
The TLV713P-Q1 internal protection circuitry is designed to protect against overload conditions. This circuitry is
not intended to replace proper heatsinking. Continuously running the TLV713P-Q1 into thermal shutdown
degrades device reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage is at least as high as VIN(min).
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
IOUT < ILIM
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(high)
—
TJ < 125°C
—
VEN < VEN(low)
—
TJ > 158°C
Disabled mode
(any true condition disables the
device)
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Considerations
The TLV713P-Q1 uses an advanced internal control loop to obtain stable operation both with and without the use
of input or output capacitors. The TLV713P-Q1 dynamic performance is improved with the use of an output
capacitor. An output capacitance of 0.1 μF or larger generally provides good dynamic response. X5R- and X7Rtype ceramic capacitors are recommended because these capacitors have minimal variation in value and
equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. An input capacitor is recommended if the source impedance is more than
0.5 Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the
device is located several inches from the input power source.
8.1.2 Dropout Voltage
The TLV713P-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(on) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are
degraded when (VIN – VOUT) approaches dropout.
8.1.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
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8.2 Typical Application
Several versions of the TPS713P-Q1 are ideal for powering the MSP430 microcontroller.
Figure 24 shows a diagram of the TLV713P-Q1 powering an MSP430 microcontroller. Table 2 shows potential
applications of some voltage versions.
VO
(1.8 V to 3.6 V)
VI
IN
0.1 mF
MSP430
OUT
0.1 mF
EN
GND
Figure 24. TLV713P-Q1 Powering a Microcontroller
Table 2. Typical MSP430 Applications
DEVICE
VOUT (Typ)
TLV71318P-Q1
1.8 V
Allows for lowest power consumption with many MSP430s
APPLICATION
TLV71325P-Q1
2.5 V
2.2-V supply required by many MSP430s for flash programming and erasing
8.2.1 Design Requirements
Table 3 lists the design requirements.
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
4.2 V to 3 V (Lithium Ion battery)
Output voltage
1.8 V, ±1%
DC output current
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
No output capacitor allows for the minimal possible inrush current during start-up, ensuring the 180-mA
maximum input current limit is not exceeded.
14
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8.2.3 Application Curves
5
3
2
100
90
COUT = 0 PF
COUT = 1 PF
80
60
50
40
30
20
10
0
-10
1E+1
COUT = 0 PF, IOUT = 150 mA
COUT = 0 PF, IOUT = 30 mA
COUT = 1 PF, IOUT = 150 mA
COUT = 1 PF, IOUT = 30 mA
1E+2
1
Voltage Noise (PV/—Hz)
PSRR (dB)
70
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
0.005
1E+1
Figure 25. Power-Supply Rejection Ratio vs Frequency
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
1E+7
Figure 26. Output Spectral Noise Density
4
VIN
VOUT
Voltage (V)
3
2
1
0
0
0.5
1
Time (s)
1.5
2
IOUT = 150 mA
Figure 27. VIN Power Up and Power Down
8.3 Do's and Don'ts
For best transient performance, place at least one 0.1-µF ceramic capacitor as close as possible to the OUT pin
of the regulator and at least one 1-uF capacitor as close as possible to the IN pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not continuously operate the device in current limit or near thermal shutdown.
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9 Power-Supply Recommendations
These devices are designed to operate from an input voltage supply range from 1.4 V to 5.5 V. The input voltage
range must provide adequate headroom for the device to have a regulated output. This input supply must be
well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve
the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin. High-ESR capacitors may
degrade PSRR performance.
10.2 Layout Example
VOUT
VIN
IN
CIN(1)
OUT
COUT(1)
GND
EN
NC
GND PLANE
Represents via used for
application-specific connections
(1)
Not required.
Figure 28. SOT-23 Layout Example
16
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10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the
table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 3.
PD = (VIN – VOUT) × IOUT
(3)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, as discussed in the
table. These metrics are a more accurate representation of the heat transfer characteristics of the die and the
package than RθJA. The junction temperature can be estimated with Equation 4.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by Equation 3,
TT is the temperature at the center-top of the device package,
TB is the PCB temperature measured 1 mm away from the device package on the PCB surface.
(4)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see application note Using New Thermal Metrics (SBVA025),
available for download at www.ti.com.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
Three evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the
TLV713P-Q1:
• TLV71312PEVM-171
• TLV71318PEVM-171
• TLV71333PEVM-171
These EVMs come populated with the commercial version of the device in the DQN package; however, they can
be used for parametric evaluation. These EVMs can be requested at the Texas Instruments website through the
device product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TLV713P-Q1 is available through the product folders under
Tools & Software.
11.1.2 Device Nomenclature
Table 4. Ordering Information (1)
(1)
(2)
(2)
PRODUCT
VOUT
TLV713PxxPQyyyzQ1
xx is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in
the ordering number (for example, 28 = 2.8 V).
P is optional; devices with P have an LDO regulator with an active output discharge.
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
• Using New Thermal Metrics, SBVA025
• TLV713xxEVM-171 User's Guide, SLVU771
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
18
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11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLV71310PQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZBGW
TLV71312PQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZBHW
TLV71318PQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZBIW
TLV71325PQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZBJW
TLV71333PQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
ZBKW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV713P-Q1 :
• Catalog: TLV713P
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TLV71310PQDBVRQ1
SOT-23
DBV
5
3000
178.0
9.0
TLV71312PQDBVRQ1
SOT-23
DBV
5
3000
178.0
TLV71318PQDBVRQ1
SOT-23
DBV
5
3000
178.0
TLV71325PQDBVRQ1
SOT-23
DBV
5
3000
TLV71333PQDBVRQ1
SOT-23
DBV
5
3000
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV71310PQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71312PQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71318PQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71325PQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
TLV71333PQDBVRQ1
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45 MAX
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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