Si8460/61/62/63
L O W P O W E R S I X - C H A N N E L D I G I TA L I S O L A T O R
Features

High-speed operation
DC

Up to 2500 VRMS isolation
to 150 Mbps
 60-year life at rated working
No start-up initialization required
voltage
 Wide Operating Supply Voltage:  Precise timing (typical)
2.70–5.5 V
<10 ns worst case
 Wide Operating Supply Voltage:
1.5 ns pulse width distortion
2.70–5.5V
0.5 ns channel-channel skew
2 ns propagation delay skew
 Ultra low power (typical)
6 ns minimum pulse width
5 V Operation:
 Transient Immunity 25 kV/µs
< 1.6 mA per channel at 1 Mbps
< 6 mA per channel at 100 Mbps  Wide temperature range
2.70 V Operation:
–40 to 125 °C at 150 Mbps
< 1.4 mA per channel at 1 Mbps
 RoHS-compliant packages

<

4 mA per channel at 100 Mbps
SOIC-16
Ordering Information:
See page 29.
narrow body
High electromagnetic immunity
Applications

Industrial automation systems
 Hybrid electric vehicles
 Isolated switch mode supplies

Isolated ADC, DAC
 Motor control
 Power inverters
 Communications systems
Safety Regulatory Approvals

UL 1577 recognized
Up

to 2500 VRMS for 1 minute
CSA component notice 5A
approval

VDE certification conformity
IEC
60747-5-2
(VDE0884 Part 2)
IEC
60950-1, 61010-1
(reinforced insulation)
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. All products are
safety certified by UL, CSA, and VDE and support withstand voltages
of up to 2.5 kVrms. These devices are available in a 16-pin narrowbody SOIC package.
Rev. 1.4 12/11
Copyright © 2011 by Silicon Laboratories
Si8460/61/62/63
Si8460/61/62/63
2
Rev. 1.4
Si8460/61/62/63
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1. Power Supply Bypass Capacitors (Revision A and Revision B) . . . . . . . . . . . . . . . . 27
3.2. Latch Up Immunity (Revision A Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Rev. 1.4
3
Si8460/61/62/63
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TA
150 Mbps, 15 pF, 5 V
–40
25
125
°C
VDD1
2.70
—
5.5
V
VDD2
2.70
—
5.5
V
Ambient Operating Temperature*
Supply Voltage
*Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings1
Parameter
Storage Temperature
Symbol
Min
Typ
Max
Unit
TSTG
–65
—
150
°C
2
Ambient Temperature Under Bias
TA
–40
—
125
°C
3
VDD1, VDD2
–0.5
—
5.75
V
Supply Voltage (Revision B)3
VDD1, VDD2
–0.5
—
6.0
V
Input Voltage
VI
–0.5
—
VDD + 0.5
V
Output Voltage
VO
–0.5
—
VDD + 0.5
V
Output Current Drive Channel
IO
—
—
10
mA
Lead Solder Temperature (10 s)
—
—
260
°C
Maximum Isolation Voltage (1 s)
—
—
3600
VRMS
Supply Voltage (Revision A)
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
3. See "5. Ordering Guide" on page 29 for more information.
4
Rev. 1.4
Si8460/61/62/63
Table 3. Electrical Characteristics
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
4.8
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

Input Leakage Current
1
Output Impedance
DC Supply Current (All inputs 0 V or at Supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
5
Si8460/61/62/63
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—
4.7
4.0
7.1
6.0
mA
Si8461Ax, Bx
VDD1
VDD2
—
—
4.7
4.5
7.1
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
—
—
4.7
4.3
7.1
6.5
mA
Si8463Ax, Bx
VDD1
VDD2
—
—
4.7
4.7
7.1
7.1
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
4.7
5.5
7.1
7.7
mA
Si8461Bx
VDD1
VDD2
—
—
5.0
5.7
7.2
8
mA
Si8462Bx
VDD1
VDD2
—
—
5.2
5.4
7.3
7.6
mA
Si8463Bx
VDD1
VDD2
—
—
5.5
5.5
7.7
7.7
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.4
Si8460/61/62/63
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
5.0
28.8
7.5
36
mA
Si8461Bx
VDD1
VDD2
—
—
9.0
25
11.3
30
mA
Si8462Bx
VDD1
VDD2
—
—
13.3
20.8
16.6
26
mA
Si8463Bx
VDD1
VDD2
—
—
17.2
17.2
21.5
21.5
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si846xAx
Propagation Delay
tPHL, tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Si846xBx
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
7
Si8460/61/62/63
Table 3. Electrical Characteristics (Continued)
(VDD1 = 5 V±10%, VDD2 = 5 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise Time
tr
CL = 15 pF
See Figure 1
—
3.8
5.0
ns
Output Fall Time
tf
CL = 15 pF
See Figure 1
—
2.8
3.7
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
All Models
Common Mode Transient
Immunity
Start-up Time3
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
1.4 V
Typical
Input
tPLH
tPHL
90%
90%
10%
10%
1.4 V
Typical
Output
tr
tf
Figure 1. Propagation Delay Timing
8
Rev. 1.4
Si8460/61/62/63
Table 4. Electrical Characteristics
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
3.1
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

Input Leakage Current
Output Impedance
1
DC Supply Current (All inputs 0 V or at supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
mA
mA
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
9
Si8460/61/62/63
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—
4.7
4.0
7.1
6.0
mA
Si8461Ax, Bx
VDD1
VDD2
—
—
4.7
4.5
7.1
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
—
—
4.7
4.3
7.1
6.5
mA
Si8463Ax, Bx
VDD1
VDD2
—
—
4.7
4.7
7.1
7.1
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
4.7
5.5
7.1
7.7
mA
Si8461Bx
VDD1
VDD2
—
—
5.0
5.7
7.2
8.0
mA
Si8462Bx
VDD1
VDD2
—
—
5.2
5.4
7.3
7.6
mA
Si8463Bx
VDD1
VDD2
—
—
5.5
5.5
7.7
7.7
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
10
Rev. 1.4
Si8460/61/62/63
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
4.8
20
7.2
25
mA
Si8461Bx
VDD1
VDD2
—
—
7.4
17.7
9.3
22.1
mA
Si8462Bx
VDD1
VDD2
—
—
10.2
15
12.8
18.8
mA
Si8463Bx
VDD1
VDD2
—
—
12.7
12.7
15.9
15.9
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si846xAx
Propagation Delay
tPHL,tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
Si846xBx
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew2
Channel-Channel Skew
tPHL, tPLH
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
11
Si8460/61/62/63
Table 4. Electrical Characteristics (Continued)
(VDD1 = 3.3 V±10%, VDD2 = 3.3 V±10%, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise Time
tr
CL = 15 pF
See Figure 1
—
4.3
6.1
ns
Output Fall Time
tf
CL = 15 pF
See Figure 1
—
3.0
4.3
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
All Models
Common Mode Transient
Immunity at Logic Low Output
Start-up Time3
tSU
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
12
Rev. 1.4
Si8460/61/62/63
Table 5. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2.0
—
—
V
Low Level Input Voltage
VIL
—
—
0.8
V
High Level Output Voltage
VOH
loh = –4 mA
VDD1,VDD2 – 0.4
2.3
—
V
Low Level Output Voltage
VOL
lol = 4 mA
—
0.2
0.4
V
IL
—
—
±10
µA
ZO
—
85
—

Input Leakage Current
Output Impedance
2
DC Supply Current (All inputs 0 V or at supply)
Si8460Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
3.3
7.7
3.5
2.6
5.0
11.6
5.3
Si8461Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.1
3.4
7.1
4.5
3.2
5.1
10.7
6.8
Si8462Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.5
3.0
6.5
5.0
3.8
4.5
9.8
8.3
Si8463Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
2.8
2.8
6.0
6.0
4.2
4.2
9.0
9.0
mA
mA
mA
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
13
Si8460/61/62/63
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
Si8460Ax, Bx
VDD1
VDD2
—
—
4.7
4.0
7.1
6.0
mA
Si8461Ax, Bx
VDD1
VDD2
—
—
4.7
4.5
7.1
6.8
mA
Si8462Ax, Bx
VDD1
VDD2
—
—
4.7
4.3
7.1
6.5
mA
Si8463Ax, Bx
VDD1
VDD2
—
—
4.7
4.7
7.1
7.1
mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
4.7
5.5
7.1
7.7
mA
Si8461Bx
VDD1
VDD2
—
—
5.0
5.7
7.2
8.0
mA
Si8462Bx
VDD1
VDD2
—
—
5.2
5.4
7.3
7.6
mA
Si8463Bx
VDD1
VDD2
—
—
5.5
5.5
7.7
7.7
mA
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.4
Si8460/61/62/63
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs)
Si8460Bx
VDD1
VDD2
—
—
4.8
15.8
7.2
19.8
mA
Si8461Bx
VDD1
VDD2
—
—
6.7
14.2
8.4
17.8
mA
Si8462Bx
VDD1
VDD2
—
—
8.7
12.2
10.9
15.3
mA
Si8463Bx
VDD1
VDD2
—
—
10.5
10.5
13.1
13.1
mA
Maximum Data Rate
0
—
1.0
Mbps
Minimum Pulse Width
—
—
250
ns
Timing Characteristics
Si846xAx
Propagation Delay
tPHL,tPLH
See Figure 1
—
—
35
ns
PWD
See Figure 1
—
—
25
ns
tPSK(P-P)
—
—
40
ns
tPSK
—
—
35
ns
Maximum Data Rate
0
—
150
Mbps
Minimum Pulse Width
—
—
6.0
ns
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew3
Channel-Channel Skew
Si846xBx
Propagation Delay
Pulse Width Distortion
|tPLH - tPHL|
Propagation Delay Skew3
Channel-Channel Skew
tPHL, tPLH
See Figure 1
3.0
6.0
9.5
ns
PWD
See Figure 1
—
1.5
2.5
ns
tPSK(P-P)
—
2.0
3.0
ns
tPSK
—
0.5
1.8
ns
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.4
15
Si8460/61/62/63
Table 5. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 ºC; applies to narrow-body SOIC package)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Rise Time
tr
CL = 15 pF
See Figure 1
—
4.8
6.5
ns
Output Fall Time
tf
CL = 15 pF
See Figure 1
—
3.2
4.6
ns
CMTI
VI = VDD or 0 V
—
25
—
kV/µs
—
15
40
µs
All Models
Common Mode Transient
Immunity at Logic Low Output
Start-up Time4
tSU
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the
same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 130 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 560 Vpeak for basic insulation working voltage.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 2500 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
For more information, see "5. Ordering Guide" on page 29.
16
Rev. 1.4
Si8460/61/62/63
Table 7. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
NB SOIC-16
Unit
Nominal Air Gap (Clearance)1
L(IO1)
3.9 min
mm
Nominal External Tracking (Creepage)1
L(IO2)
3.9 min
mm
0.008
mm
600
VRMS
Minimum Internal Gap (Internal Clearance)
Tracking Resistance
(Proof Tracking Index)
PTI
Erosion Depth
ED
0.019
mm
RIO
1012

2.0
pF
4.0
pF
Resistance
(Input-Output)2
Capacitance (Input-Output)2
Input
CIO
Capacitance3
IEC60112
f = 1 MHz
CI
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “6. Package Outline:
16-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16
package. UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the
clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 are shorted
together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter
Basic Isolation Group
Installation Classification
Test Conditions
Material Group
Specification
I
Rated Mains Voltages < 150 VRMS
I-IV
Rated Mains Voltages < 300 VRMS
I-III
Rated Mains Voltages < 400 VRMS
I-II
Rated Mains Voltages < 600 VRMS
I-II
Rev. 1.4
17
Si8460/61/62/63
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxB*
Parameter
Symbol
Test Condition
Characteristic
Unit
560
V peak
VIORM
Maximum Working Insulation Voltage
Input to Output Test Voltage
Transient Overvoltage
V peak
VPR
Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm = 1 sec,
Partial Discharge < 5 pC)
1050
VIOTM
t = 60 sec
4000
2
Pollution Degree (DIN VDE 0110, Table 1)
>109
RS
Insulation Resistance at TS, VIO = 500 V
V peak

*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter
Symbol
Case Temperature
TS
Safety input, output, or
supply current
IS
Device Power Dissipation2
PD
Test Condition
JA = 105 °C/W (NB SOIC-16),
VI = 5.5 V, TJ = 150 °C, TA = 25 °C
Max
Min
Typ
—
—
150
°C
—
—
215
mA
—
—
415
mW
NB SOIC-16
Unit
Notes:
1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 2.
2. The Si846x is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 ºC, CL = 15 pF, input a 150 Mbps 50% duty cycle square
wave.
18
Rev. 1.4
Si8460/61/62/63
Table 11. Thermal Characteristics
Parameter
Symbol
Test Condition
Min
JA
IC Junction-to-Air Thermal
Resistance
Typ
NB SOIC-16
—
105
Max
Unit
—
ºC/W
Safety-Limiting Current (mA)
500
430
VDD1, VDD2 = 2.70 V
400
360
VDD1, VDD2 = 3.6 V
300
215
200
VDD1, VDD2 = 5.5 V
100
0
0
50
100
Temperature (ºC)
150
200
Figure 2. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.4
19
Si8460/61/62/63
2. Functional Description
2.1. Theory of Operation
The operation of an Si846x channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si846x channel is shown in
Figure 3.
Transmitter
Receiver
RF
OSCILLATOR
A
MODULATOR
SemiconductorBased Isolation
Barrier
DEMODULATOR
B
Figure 3. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 4 for more details.
Input Signal
Modulation Signal
Output Signal
Figure 4. Modulation Scheme
20
Rev. 1.4
Si8460/61/62/63
2.2. Eye Diagram
Figure 5 illustrates an eye-diagram taken on an Si8460. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8460 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 5. Eye Diagram
Rev. 1.4
21
Si8460/61/62/63
2.3. Device Operation
Device behavior during startup, normal operation, and shutdown is shown in Table 12.
Table 12. Si846x Logic Operation Table
VI
Input1,2
VDDI
State1,3,4
VDDO
State1,3,4
VO Output1,2
H
P
P
H
L
P
P
L
X5
UP
P
L
Upon transition of VDDI from unpowered to powered, VO
returns to the same state as VI in less than 1 µs.
X5
P
UP
Undetermined
Upon transition of VDDO from unpowered to powered, VO
returns to the same state as VI within 1 µs.
Comments
Normal operation.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance.
3. “Powered” state (P) is defined as 2.70 V < VDD < 5.5 V.
4. “Unpowered” state (UP) is defined as VDD = 0 V.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
22
Rev. 1.4
Si8460/61/62/63
2.4. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 16 and Table 7 on page 17 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, etc.)
requirements before starting any design that uses a digital isolator.
The following sections detail the recommended bypass and decoupling components necessary to ensure robust
overall performance and reliability for systems using the Si84xx digital isolators.
2.4.1. Supply Bypass
Digital integrated circuit components typically require 0.1 µF (100 nF) bypass capacitors when used in electrically
quiet environments. However, digital isolators are commonly used in hazardous environments with excessively
noisy power supplies. To counteract these harsh conditions, it is recommended that an additional 1 µF bypass
capacitor be added between VDD and GND on both sides of the package. The capacitors should be placed as
close as possible to the package to minimize stray inductance. If the system is excessively noisy, it is
recommended that the designer add 50 to 100  resistors in series with the VDD supply voltage source and 50 to
300  resistors in series with the digital inputs/outputs (see Figure 6). For more details, see "3. Errata and Design
Migration Guidelines" on page 27.
All components upstream or downstream of the isolator should be properly decoupled as well. If these components
are not properly decoupled, their supply noise can couple to the isolator inputs and outputs, potentially causing
damage if spikes exceed the maximum ratings of the isolator (6 V). In this case, the 50 to 300  resistors protect
the isolator's inputs/outputs (note that permanent device damage may occur if the absolute maximum ratings are
exceeded). Functional operation should be restricted to the conditions specified in Table 1, “Recommended
Operating Conditions,” on page 4.
2.4.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
2.4.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination
of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving
loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces. The series termination resistor values should be scaled appropriately while keeping in
mind the recommendations described in “2.4.1. Supply Bypass” above.
V Source 2
V Source 1
R1 (50 – 100 )
R2 (50 – 100 )
VDD1
C1
VDD2
50 – 300 
0.1 F
A1
0.1 F
B1
C2
1 F
C4
50 – 300 
C3
Input/Output
Input/Output
1 F
Bx
Ax
50 – 300 
50 – 300 
GND1
GND2
Figure 6. Recommended Bypass Components for the Si84xx Digital Isolator Family
Rev. 1.4
23
Si8460/61/62/63
2.5. Typical Performance Characteristics
45
40
35
30
25
20
15
10
5
0
Current (mA)
Current (mA)
The typical performance characteristics depicted in the following diagrams are for information purposes only. Refer
to Tables 3, 4, and 5 for actual specification limits.
5V
3.3V
2.70V
0
45
40
35
30
25
20
15
10
5
0
5V
3.3V
2.70V
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Figure 10. Si8460 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
5V
Current (mA)
Current (mA)
Figure 7. Si8460 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
45
40
35
30
25
20
15
10
5
0
3.3V
2.70V
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Data Rate (Mbps)
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
45
40
35
30
25
20
15
10
5
0
5V
3.3V
2.70V
0
Data Rate (Mbps)
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
45
40
35
30
25
20
15
10
5
0
5V
3.3V
2.70V
0
Figure 11. Si8461 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Current (mA)
Current (mA)
Figure 8. Si8461 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
45
40
35
30
25
20
15
10
5
0
5V
3.3V
2.70V
0
Data Rate (Mbps)
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 9. Si8462 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
24
Figure 12. Si8462 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Rev. 1.4
Current (mA)
Si8460/61/62/63
45
40
35
30
25
20
15
10
5
0
5V
3.3V
2.70V
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbps)
Figure 13. Si8463 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
10
Falling Edge
Delay (ns)
9
8
7
Rising Edge
6
5
-40
-20
0
20
40
60
80
100
120
Temperature (Degrees C)
Figure 14. Propagation Delay vs. Temperature
Rev. 1.4
25
Si8460/61/62/63
Figure 15. Si84xx Time-Dependent Dielectric Breakdown
26
Rev. 1.4
Si8460/61/62/63
3. Errata and Design Migration Guidelines
When using the new Si846x products, or when migrating from Silicon Labs' legacy isolators, designers must
consider and adhere to the following requirements.
3.1. Power Supply Bypass Capacitors (Revision A and Revision B)
When using the Si846x isolators with power supplies > 4.5 V, sufficient VDD bypass capacitors must be present on
both the VDD1 and VDD2 pins to ensure the VDD rise time is less than 0.5 V/µs (which is > 9 µs for a > 4.5 V
supply). Although rise time is power supply dependent, > 1 µF capacitors are required on both power supply pins
(VDD1, VDD2) of the isolator device.
3.1.1. Resolution
For recommendations on resolving this issue, see "2.4.1. Supply Bypass" on page 23. Additionally, refer to "5.
Ordering Guide" on page 29 for current ordering information.
3.2. Latch Up Immunity (Revision A Only)
Latch up immunity generally exceeds ± 200 mA per pin. Exceptions: Certain pins provide < 100 mA of latch-up
immunity. To increase latch-up immunity on these pins, 100  of equivalent resistance must be included in series
with all of the pins listed in Table 13. The 100  equivalent resistance can be comprised of the source driver's
output resistance and a series termination resistor.
3.2.1. Resolution
This issue has been corrected with Revision B of the device. Refer to "5. Ordering Guide" on page 29 for more
information.
Table 13. Affected Ordering Part Numbers (Revision A Only)
Affected Ordering Part Numbers*
SI8460SV-A-IS/IS1, SI8461SV-A-IS/IS1,
SI8462SV-A-IS/IS1, SI8463SV-A-IS/IS1
Device
Revision
A
Pin#
Name
Pin Type
2
A1
Input
6
A5
Input or Output
10
B6
Input or Output
14
B2
Output
*Note: SV = Speed Grade/Isolation Rating (AA, AB, BA, BB).
Rev. 1.4
27
Si8460/61/62/63
4. Pin Descriptions
VDD1
A1
A2
RF
XMITR
A3
RF
XMITR
A4
RF
XMITR
A5
RF
XMITR
A6
RF
XMITR
GND1
28
VDD1
VDD2
RF
XMITR
I
s
o
l
a
t
i
o
n
VDD2
RF
RCVR
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
XMITR
RF
RCVR
B5
A5
RF
XMITR
RF
RCVR
B6
A6
RF
RCVR
Si8460
GND2
GND1
I
s
o
l
a
t
i
o
n
VDD1
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
XMITR
RF
RCVR
B5
A5
RF
RCVR
RF
XMITR
B6
A6
RF
RCVR
GND2
Si8461
GND1
VDD1
VDD2
RF
RCVR
I
s
o
l
a
t
i
o
n
B1
A1
RF
XMITR
RF
RCVR
B2
A2
RF
XMITR
RF
RCVR
B3
A3
RF
XMITR
RF
RCVR
B4
A4
RF
RCVR
RF
XMITR
B5
A5
RF
RCVR
RF
RF
XMITR
RCVR
B6
A6
RF
RCVR
Si8462
GND2
GND1
Name
SOIC-16 Pin#
Type
Description
VDD1
1
Supply
A1
2
Digital Input
Side 1 digital input.
A2
3
Digital Input
Side 1 digital input.
A3
4
Digital Input
Side 1 digital input.
A4
5
Digital I/O
Side 1 digital input or output.
A5
6
Digital I/O
Side 1 digital input or output.
A6
7
Digital I/O
Side 1 digital input or output.
GND1
8
Ground
Side 1 ground.
GND2
9
Ground
Side 2 ground.
B6
10
Digital I/O
Side 2 digital input or output.
B5
11
Digital I/O
Side 2 digital input or output.
B4
12
Digital I/O
Side 2 digital input or output.
B3
13
Digital Output
Side 2 digital output.
B2
14
Digital Output
Side 2 digital output.
B1
15
Digital Output
Side 2 digital output.
VDD2
16
Supply
Side 2 power supply.
Side 1 power supply.
Rev. 1.4
VDD2
RF
RCVR
I
s
o
l
a
t
i
o
n
RF
RCVR
B1
RF
RCVR
B2
RF
RCVR
B3
RF
XMITR
B4
RF
XMITR
B5
RF
RF
XMITR
RCVR
B6
Si8463
GND2
Si8460/61/62/63
5. Ordering Guide
Revision B devices are recommended for all new designs.
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number (OPN)
Number of
Number of
Inputs VDD1 Inputs VDD2
Side
Side
Maximum
Data Rate
(Mbps)
Isolation
Rating
Temp Range
Package Type
1 kVrms
–40 to 125 °C
NB SOIC-16
2.5 kVrms
–40 to 125 °C
NB SOIC-16
Revision B Devices2
Si8460AA-B-IS1
6
0
1
Si8460BA-B-IS1
6
0
150
Si8461AA-B-IS1
5
1
1
Si8461BA-B-IS1
5
1
150
Si8462AA-B-IS1
4
2
1
Si8462BA-B-IS1
4
2
150
Si8463AA-B-IS1
3
3
1
Si8463BA-B-IS1
3
3
150
Si8460AB-B-IS1
6
0
1
Si8460BB-B-IS1
6
0
150
Si8461AB-B-IS1
5
1
1
Si8461BB-B-IS1
5
1
150
Si8462AB-B-IS1
4
2
1
Si8462BB-B-IS1
4
2
150
Si8463AB-B-IS1
3
3
1
Si8463BB-B-IS1
3
3
150
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C
according to the JEDEC industry standard classifications and peak solder temperature.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
Rev. 1.4
29
Si8460/61/62/63
Table 14. Ordering Guide for Valid OPNs1
Ordering Part
Number (OPN)
Number of
Number of
Inputs VDD1 Inputs VDD2
Side
Side
Maximum
Data Rate
(Mbps)
Isolation
Rating
Temp Range
Package Type
1 kVrms
–40 to 125 °C
NB SOIC-16
2.5 kVrms
–40 to 125 °C
NB SOIC-16
Revision A Devices2
Si8460AA-A-IS1
6
0
1
Si8460BA-A-IS1
6
0
150
Si8461AA-A-IS1
5
1
1
Si8461BA-A-IS1
5
1
150
Si8462AA-A-IS1
4
2
1
Si8462BA-A-IS1
4
2
150
Si8463AA-A-IS1
3
3
1
Si8463BA-A-IS1
3
3
150
Si8460AB-A-IS1
6
0
1
Si8460BB-A-IS1
6
0
150
Si8461AB-A-IS1
5
1
1
Si8461BB-A-IS1
5
1
150
Si8462AB-A-IS1
4
2
1
Si8462BB-A-IS1
4
2
150
Si8463AB-A-IS1
3
3
1
Si8463BB-A-IS1
3
3
150
Notes:
1. All packages are RoHS-compliant. Moisture sensitivity level is MSL2A with peak reflow temperature of 260 °C
according to the JEDEC industry standard classifications and peak solder temperature.
2. Revision A devices are supported for existing designs, but Revision B is recommended for all new designs.
30
Rev. 1.4
Si8460/61/62/63
6. Package Outline: 16-Pin Narrow Body SOIC
Figure 16 illustrates the package details for the Si846x in a 16-pin narrow-body SOIC (SO-16). Table 15 lists the
values for the dimensions shown in the illustration.
Figure 16. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Dimension
Min
Max
A
—
1.75
A1
0.10
0.25
A2
1.25
—
b
0.31
0.51
c
0.17
0.25
D
9.90 BSC
E
6.00 BSC
E1
3.90 BSC
e
1.27 BSC
L
0.40
L2
1.27
0.25 BSC
Rev. 1.4
31
Si8460/61/62/63
Table 15. Package Diagram Dimensions (Continued)
h
0.25
0.50
θ
0°
8°
aaa
0.10
bbb
0.20
ccc
0.10
ddd
0.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012,
Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
32
Rev. 1.4
Si8460/61/62/63
7. Land Pattern: 16-Pin Narrow Body SOIC
Figure 17 illustrates the recommended land pattern details for the Si846x in a 16-pin narrow-body SOIC. Table 16
lists the values for the dimensions shown in the illustration.
Figure 17. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 16. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
C1
Pad Column Spacing
5.40
E
Pad Row Pitch
1.27
X1
Pad Width
0.60
Y1
Pad Length
1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Rev. 1.4
33
Si8460/61/62/63
8. Top Marking: 16-Pin Narrow Body SOIC
8.1. 16-Pin Narrow Body SOIC Top Marking
e3
Si84XYSV
YYWWTTTTTT
8.2. Top Marking Explanation
Line 1 Marking:
Line 2 Marking:
34
Base Part Number
Ordering Options
(See Ordering Guide for more
information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (6, 5, 4, 3, 2, 1)
Y = # of reverse channels (3, 2, 1, 0)
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A = 1 kV; B = 2.5 kV
Circle = 1.2 mm Diameter
“e3” Pb-Free Symbol
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to the
year and work week of the mold date.
TTTTTT = Mfg code
Manufacturing Code from Assembly Purchase Order
form.
Circle = 1.2 mm diameter
“e3” Pb-Free Symbol.
Rev. 1.4
Si8460/61/62/63
DOCUMENT CHANGE LIST
Revision 1.3 to Revision 1.4

Revision 0.1 to Revision 0.2
Updated "4. Pin Descriptions" on page 28.
Removed

Updated all specs to reflect latest silicon.
 Added "3. Errata and Design Migration Guidelines"
on page 27.
 Added "8. Top Marking: 16-Pin Narrow Body SOIC"
on page 34.
Revision 0.2 to Revision 1.0
note for narrow-body devices.

Updated "2.4.1. Supply Bypass" on page 23.
 Added Figure 6, “Recommended Bypass
Components for the Si84xx Digital Isolator Family,”
on page 23.
 Updated "3.1. Power Supply Bypass Capacitors
(Revision A and Revision B)" on page 27.

Updated document to reflect availability of Revision
B silicon.
 Updated Tables 3,4, and 5.
Updated

Updated

all supply currents and channel-channel skew.
Updated Table 2.
absolute maximum supply voltage.
Updated Table 7.
Updated
clearance and creepage dimensions.

Updated "3. Errata and Design Migration Guidelines"
on page 27.
 Updated "5. Ordering Guide" on page 29.
Revision 1.0 to Revision 1.1

Updated Tables 3, 4, and 5.
Updated
notes in tables to reflect output impedance of
85 .
Updated rise and fall time specifications.
Updated CMTI value.
Revision 1.1 to Revision 1.2

Updated document throughout to include MSL
improvements to MSL2A.
 Updated "5. Ordering Guide" on page 29.
Updated
Note 1 in ordering guide table to reflect
improvement and compliance to MSL2A moisture
sensitivity level.
Revision 1.2 to Revision 1.3

Updated " Features" on page 1.
Moved Tables 1 and 2 to page 4.
 Updated Tables 6, 7, 8, and 9.
 Updated Table 12 footnotes.
 Added Figure 15, “Si84xx Time-Dependent
Dielectric Breakdown,” on page 26.

Rev. 1.4
35
Si8460/61/62/63
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
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36
Rev. 1.4