LMC1983 Digitally-Controlled Stereo Tone and Volume Circuit with

LMC1983
Digitally-Controlled Stereo Tone and Volume
Circuit with Three Selectable Stereo Inputs
General Description
The LMC1983 is a monolithic integrated circuit that provides
volume, balance, tone (bass and treble), loudness controls
and selection between three pairs of stereo inputs. These
functions are digitally controlled through a three-wire communication interface. There are two digital inputs for easy
interface to other audio peripherals such as stereo decoders. The LMC1983 is designed for line level input signals
(300 mV – 2V) and has a maximum gain of b0.5 dB. Volume
is set at minimum and tone controls are flat when supply
voltage is first applied.
Low noise and distortion result from using analog switches
and poly-silicon resistor networks in the signal path.
Additional tone control can be achieved using the LMC835
stereo 7-band graphic equalizer connected to the
LMC1983’s SELECT OUT/SELECT IN external processor
loop.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Loudness compensation
40 position 2 dB/step volume attenuator plus mute
Independent left and right volume controls
Low noise-suitable for use with DNRÉ and DolbyÉ
noise reduction
External processor loop
Signal handling suitable for compact discs
Pop-free switching
Serially programmable: INTERMETAL bus (IM) interface
6V to 12V single supply operation
28 Pin DIP or PLCC Package
Applications
Y
Y
Y
Y
Y
Features
Y
Y
Stereo television
Music reproduction systems
Sound reinforcement systems
Electronic music (MIDI)
Personal computer audio control
Low noise and distortion
Three pairs of stereo inputs
Block Diagram
TL/H/11279 – 1
DNRÉ is a registered trademark of National Semiconductor Corporation.
DolbyÉ is a registered trademark of Dolby Labs.
C1995 National Semiconductor Corporation
TL/H/11279
RRD-B30M75/Printed in U. S. A.
LMC1983 Digitally-Controlled Stereo Tone and
Volume Circuit with Three Selectable Stereo Inputs
February 1995
Absolute Maximum Ratings (Notes 1 and 2)
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 65§ C to a 150§ C
Lead Temperature
N Package, (Soldering, 10 Seconds)
V Package, (Vapor Phase, 60 Seconds)
Infrared, (15 Seconds)
Supply Voltage (V a b GND)
15V
Voltage at any Pin
GND b 0.2V to V a a 0.2V
Input Current at any Pin (Note 3)
5 mA
Package Input Current (Note 3)
20 mA
Power Dissipation (Note 4)
500 mW
a 125§ C
Junction Temperature
a 260§ C
215§ C
220§ C
ESD Susceptability (Note 5)
2 kV
Operating Ratings (Notes 1 and 2)
Temperature Range
TMIN s TA s TMAX
b 40§ C s TA s a 85§ C
LMC1983CIN, LMC1983CIV
6V to 12V
Supply Voltage Range (V a b Vb)
Electrical Characteristics The following specifications apply for V a e 9V, fIN e 1 kHz, input signal
(300 mV) applied to INPUT 1, volume e 0 dB, bass e 0 dB, treble e 0 dB, and loudness is off unless otherwise specified. All
limits apply for TA e TJ e a 25§ C.
Symbol
Parameter
Conditions
IS
Supply Current
VIN
Input Voltage
Clipping Level (1.0% THD),
Select Out (Pins 7, 22)
THD
Total Harmonic Distortion
Left and Right channels;
Output Pins 13, 16
VIN e 0.3 Vrms;
fIN e 100 Hz, 1 kHz, 10 kHz
VIN e 2.0 Vrms;
fIN e 100 Hz, 1 kHz
VIN e 2.0 Vrms;
fIN e 10 kHz
VIN e 0.5 Vrms; Bass and Treble
Tone Controls Set at Maximum
VIN e 0.3 Vrms; Volume
Attenuator at b20 dB, Bass and Treble
Tone Controls Set at Maximum
DC Shifts
VIN e 0.3 Vrms; between Any
Two Adjacent Control Settings
VIN e 0.3 Vrms;
All Mode and Input Positions
Typical
(Note 6)
Limit
(Note 7)
Unit
(Limit)
15
25
mA (max)
2.3
2.0
Vrms (min)
0.008
0.1
% (max)
0.4
1.0
% (max)
0.5
1.0
% (max)
0.07
0.5
% (max)
0.06
0.15
% (max)
2.0
4.0
mV (max)
18
20
mV (max)
ROUT
AC Output Impedance
Pins 7, 22, (470X to Ground at Input)
Pins 13, 16
150
26
200
40
X (max)
X (max)
RIN
AC Input Impedance
Pins 4, 5, 23, 24, 25
50
72
35
kX (max)
kX (min)
Volume Attenuator Range
Pins 13, 16; Volume
Attenuation at 0100010XXX000000 (0 dB)
0100010XXX101XXX (80 dB);
(Relative to Attenuation at
the 0 dB Setting)
0.5
1.5
dB (max)
80
78
82
dB (min)
dB (max)
2.0
1.5
2.5
dB (min)
dB (min)
g 0.1
g 1.5
dB (min)
g 2.0
dB (min)
86
dB (max)
Volume Step Size
Channel-to-Channel
Tracking Error
Mute Attenuation
All Volume Attenuation Settings
from 0100010XXX101XXX (80 dB) to
0100010XXX000000 (0 dB) (Note 9)
All Volume Attenuation Settings
from 0100010XXX100110 (76 dB) to
0100010XXX000000 (0 dB)
from 0100010XXX101XXX (80 dB) to
0100010XXX100111 (78 dB)
VIN e 1.0 Vrms
105
2
Electrical Characteristics The following specifications apply for V a e 9V, fIN e 1 kHz, input signal (300 mV)
applied to INPUT 1, volume e 0 dB, bass e 0 dB, treble e 0 dB, and loudness is off unless otherwise specified. All limits apply
for TA e TJ e a 25§ C. (Continued)
Symbol
Typical
(Note 6)
Limit
(Note 7)
Unit
(Limit)
fIN e 100 Hz, Pins 13, 16
g 12
g 10.0
g 14.0
dB (min)
dB (max)
Bass Tracking Error
fIN e 100 Hz, Pins 13, 16
g 0.1
g 1.5
dB (max)
Bass Step Size
fIN e 100 Hz, Pins 13, 16
(Relative to Previous Level)
2.0
1.5
2.5
dB (min)
dB (max)
Treble Gain Range
fIN e 10 kHz, Pins 13, 16
g 12
g 10.0
g 14.0
dB (min)
dB (max)
Treble Tracking Error
fIN e 10 kHz, Pins 13, 16
g 0.1
g 1.5
dB (max)
Treble Step Size
fIN e 10 kHz, Pins 13, 16
(Relative to Previous Level)
2.0
1.5
2.5
dB (min)
dB (max)
Frequency Response
VIN Applied to Input 1 and Input 2;
fIN e 20 Hz b 20 kHz
(Relative to Signal Amplitude at 1 kHz)
g 0.1
g 1.0
dB (max)
11.5
13.5
9.5
8.5
4.5
dB (max)
dB (min)
dB (max)
dB (min)
Parameter
Bass Gain Range
Loudness
Conditions
Volume Attenuator e 40 dB, Loudness
on (See Figure 5 )
Gain at 100 Hz (Referenced
to Gain at 1 kHz)
Gain at 10 kHz (Referenced
to Gain at 1 kHz)
6.5
Signal-to-Noise Ratio
VIN e 1.0 Vrms, A Weighted,
Measured at 1 kHz, RS e 470X
95
90
dB (min)
Channel Balance
All Volume Settings
0.2
1.0
dB (max)
Channel Separation
Input Pins 4, 25: Output Pins 13, 16;
VIN e 1.0 Vrms (Note 8)
80
60
dB (min)
Input-Input Isolation
470X to AC Ground on Unused Input
95
60
dB (min)
PSSR
Power Supply Rejection Ratio
V a e 9 VDC; 200 mVrms, 100 Hz
Sinewave Applied to Pin 26
32
28
dB (min)
fCLK
Clock Frequency
5.0
1.0
MHz (max)
VIN(1)
Logic ‘‘1’’ Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
1.3
2.9
2.0
5.5
V (min)
V (min)
VIN(0)
Logic ‘‘0’’ Input Voltage
Pins 1, 27, 28 (IM Bus)
Pins 2, 3
0.4
1.2
0.8
3.5
V (max)
V (max)
VOUT(1)
Logic ‘‘1’’ Output Voltage
Pin 28 (IM Bus)
VOUT(0)
Logic ‘‘0’’ Output Voltage
Pin 28 (IM Bus)
0.4
2.0
V (min)
0.8
V (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the deivce may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are specified with respect to ground.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply voltages (VIN k Vb or VIN l V a ) the absolute value of the current at that pin should be
limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply voltages with 5 mA current limit to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, iJA, and the ambient temperature TA. The maximum
allowable power dissipation is PD e (TJMAX b TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For the LMC1983CIN, TJMAX e
a 125§ C, and the typical junction-to-ambient thermal resistance, when board mounted, is 67§ C/W.
Note 5: Human body model; 100 pF discharged through a 1.5 kX resistor.
Note 6: Typicals are at TJ e a 25§ C and represent the most likely parametric norm.
Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8: The Input-Input Isolation is tested by driving one input and measuring the output when the undriven input are selected.
Note 9: The Volume Step Size is defined as the change in attenuation between any two adjacent volume attenuation settings. The nominal Volume Step Size is
2 dB.
3
Typical Performance Characteristics
Supply Current
vs Supply Voltage
Output Voltage
vs Supply Voltage
THD vs
Load Impedance
THD vs
Load Impedance
CCIR Output Noise
vs Volume Setting
Channel Separation
vs Frequency
THD vs VIN
(VOUT Constant)
THD vs Frequency
Mute Gain
vs Frequency
Tone Control Response
with Equal Bass and
Treble Control Settings
Loudness Response
vs Frequency
Select Input Impedance
vs Frequency
TL/H/11279 – 9
4
Connection Diagram
TL/H/11279 – 2
Top View
Order Number LMC1983CIN
See NS Package Number N28B
TL/H/11279 – 10
Top View
Order Number LMC1983CIV
See NS Package Number V28A
Pin Description
TONE IN
(9, 20)
CLK (1)
The INTERMETAL (IM) Bus clock is applied to the CLOCK pin. This input accepts a TTL or CMOS level signal. The
input is used to clock the DATA signal. A
data bit must be valid on the rising clock
edge.
DIGITAL INPUT Internally tied high to V a through a
1 & 2 (2, 3)
30 kX pull-up resistor, these inputs allow
a peripheral device to place any singlebit, active low digital information onto the
IM Bus. It is then sent out to the controlling device through the DATA pin. Examples of such information could include indication of the presence of a Second Audio Program (SAP) or an FM stereo carrier.
INPUTS 1, 2 & 3 These are the LMC1983’s three stereo
(4, 25; 5, 24;
input pairs.
6, 23)
SELECT OUT
The selected INPUT signal is available
(7, 22)
at this output. This feature allows external signal processors such as noise reduction or graphic equalizers to be used.
This output can typically sink 1 mA.
These pins should be capacitively coupled to pins 8 and 21, respectively, if no
external processor is used.
SELECT IN
These are the inputs that an external sig(8, 21)
nal processor uses to return a signal to
the LMC1983. These pins should be capacitively coupled to pins 7 and 22, respectively, if no external processor is
used.
TONE OUT
(10, 19)
OP AMP
OUT (11, 18)
LOUDNESS
(12, 17)
MAIN
OUTPUT
(13, 16)
BYPASS (14)
GROUND (15)
V a (26)
ID (27)
5
These are the inputs to the tone control
amplifier. See the Application Information section titled ‘‘Tone Control Response’’.
Tone control amplifier output. See the
Application Information section titled
‘‘Tone Control Response’’.
These outputs are used with external
tone control capacitors. Internally, this
output is applied to the volume attenuators.
The output signal on these pins is a voltage taken from the volume attenuator’s
b 40 dB tap point. An external R – C network is connected to these pins.
The output signal from these pins drives
a stereo power amplifier. The output can
typically sink 1 mA.
A 10 mF capacitor is connected between
this pin and ground to provide an AC
ground for the internal half-supply voltage reference.
This pin is connected to analog ground.
This is the power supply connection. The
LMC1983 is operational with supply voltages from 6V to 12V. This pin should be
bypassed to ground through a 1.0 mF capacitor.
This is the IDENTITY digital input that,
when low, signals the LMC1983 to receive, from a controlling device, a device
address (40H –47H), present on the
DATA line.
op amps, and poly-silicon resistors make it possible to
achieve an order of magnitude quality improvement over
other bipolar circuits that use analog multipliers to accomplish gain adjustment. Internal circuits set the volume to
minimum, tone controls to flat, the mute to on, and all other
functions off when power is first applied. Individual left and
right volume controls are software programmed to achieve
the stereo balance function. Figure 1 shows the connection
diagram of a typical LMC1983 application.
The LMC1983 has internal decoding logic that allows a
microprocessor (mP) or microcontroller (mC) to communicate directly to the audio control circuitry through an
INTERMETAL (IM) Bus interface. This three-wire interface
consists of a bi-directional DATA line, a Clock (CLK) input
line, and an Identity (ID) line. Address and function selection
data (8 bits) are serially shifted from the controller to the
LMC1983. This is followed by 8 bits of function value data.
Data present in the internal shift register is latched and the
instruction is executed.
Pin Description (Continued)
DATA (28) This is the serial data input for communications
sent by a controller. The controller must have
open drain outputs used with external pull-up
resistors. The data rate has a maximum frequency of 1 MHz. The LMC1983 requires 16
bits of data to control or change a function: the
first 8 bits select the LMC1983 and one of eight
functions. The final eight bits set the function to
a desired value. The data must be valid on the
rising edge of the CLOCK input signal.
General Information
The LMC1983 is a CMOS/bipolar building block intended
for high fidelity audio signal processing. It is designed for
line level inputs signals (300 mV b 2V) and has a maximum
gain of b0.5 dB. While the LMC1983 is manufactured with
CMOS processing, NPN transistors are used to build low
noise op amps. The combination of CMOS switches, bipolar
TL/H/11279 – 3
FIGURE 1. Typical Application
6
Application Information
couple the SELECT OUT signals directly to pins 8 and 21,
respectively.
INPUT SELECTOR
The LMC1983’s input selector and mode control are shown
in Figure 2 . The input selector selects one of three stereo
signal sources or a mute function with typical attenuation of
100 dB. The selected signals are then sent to a mode control matrix. As shown in Table I, the matrix provides normal
stereo or can direct any given channel to both LEFT or
RIGHT SELECT OUTPUTs. The third matrix mode is normal
stereo. The control matrix output is buffered and appears on
each channel’s respective SELECT OUT pin (7, 22). Switching noise is kept to a minimum when mute is selected by
using a 50 kX bias resistor.
Noise performance is optimized through the use of emitter
followers in the mode control matrix’s output. Internal 50 kX
resistors are connected to each input selector pin to provide
the proper bias point for the emitter follower buffers. Each
internal 50 kX bias resistor is connected to a common halfsupply (V a /2) source. This produces a voltage at pins 7
and 22 (SELECT OUT) that is 1.4V below V a /2 (typically
3.1V with V a e 9V). Since a DC voltage is present at the
input pins (4, 5, 6, 23, 24, and 25), input signals should be
AC coupled through a 1 mF capacitor.
The output signal at pins 7 and 22 can be used to drive
exteral audio processing circuits such as noise reduction
(LM1894 –DNR or Dolby) or graphic equalizers (LMC835). It
is important that if any noise reduction is used it be placed
ahead of any tone controls or equalizers in the external circuit path to preserve the frequency spectrum of the selected input signal. Otherwise, any frequency equalization could
prevent the proper operation of the noise reduction circuit. If
no external processor is used, a capacitor should be used to
MINIMUM LOAD IMPEDANCE
The LMC1983 employs emitter-followers to buffer the selected stereo channels. The buffered signals are available
at pins 7 and 22 (SELECT OUT). The SELECT OUT buffers
operate with a typical bias current of 1 mA.
The Electrical Specifications table lists a maximum input signal of 2.0 Vrms (2.8 Vpeak) for 1% THD at the SELECT OUT
pins. This distortion level is achieved when the minimum AC
load impedance seen by the SELECT OUT pins is 2.5 kX
(2.5V/1 mA). Using lower load impedances results in clipping at lower output levels. If the load impedance is DC-coupled, an increased quiescent current can flow. Latch-up may
occur if the total emitter current exceeds 5 mA. Thus, maximum output voltage can be increased and much lower distortion levels can be achieved using load impedances of at
least 25 kX.
INPUT IMPEDANCE
The input impedance of pins 4, 5, 6, 23, 24 and 25 is defined
by internal bias resistors and is typically 50 kX.
The SELECT IN pins have an input impedance that varies
with the BASS and TREBLE control settings. The input impedance is 100 kX at DC and 19 kX at 1 kHz when the
controls are set at 0 dB. Minimum input impedance of
30.4 kX at DC and 16 kX at 1 kHz occurs when maximum
boost is selected. At 10 kHz the minimum input impedance,
with the tone controls flat, is 6.8 kX and, with the tone controls at maximum boost, is 2.5 kX.
TL/H/11279 – 4
FIGURE 2. Input and Mode Select Circuitry
7
Application Information (Continued)
TABLE I. IM Bus Programming Codes for LMC1983
Address
(A7 – A0)
Function
Data
Function
Selected
01000000
Input Select a Mute
XXXXXX00
XXXXXX01
XXXXXX10
XXXXXX11
INPUT1
INPUT2
INPUT3
MUTE
01000001
Loudness
XXXXXXX0
XXXXXXX1
Loudness OFF
Loudness ON
01000010
Bass
XXXX0000
XXXX0011
XXXX0110
XXXX1001
XXXX11XX
b 12 dB
b 6 dB
XXXX0000
XXXX0011
XXXX0110
XXXX1001
XXXX11XX
b 12 dB
b 6 dB
01000011
01000100
01000101
Treble
Left Volume
Right Volume
FLAT
a 6 dB
a 12 dB
FLAT
a 6 dB
a 12 dB
XX000000
XX010100
XX101XXX
XX11XXXX
b 40 dB
b 80 dB
b 80 dB
0 dB
XX000000
XX010100
XX101XXX
XX11XXXX
b 40 dB
b 80 dB
b 80 dB
0 dB
01000110
Mode Select
XXXXX100
XXXXX101
XXXXX11X
Left Mono
Stereo
Right Mono
01000111
Read Digital Input 1
or
Digital Input 2
on IM Bus
XXXXXXD1D0
D0 e Digital Input 1
D1 e Digital Input 2
8
Application Information (Continued)
response is achieved when C2 e C3. However, with
C2 e 2(C3) and the tone controls set to ‘‘flat’’, the frequency response will be flat at 20 Hz and 20 kHz, and a 6 dB at
1 kHz.
The frequency where a tone control begins to deviate from
a flat response is referred to as the turn-over frequency.
With C e C2 e C3, the LMC1983’s treble turn-over frequency is nominally
EXTERNAL SIGNAL PROCESSING
The SELECT OUT pins (7 and 22) enable greater system
design flexibility by providing a means to implement an external processing loop. This loop can be used for noise reduction circuits such as DNR (LM1894) or multi-band graphic equalizers (LMC835). If both are used, it is important to
ensure that the noise reduction circuitry precede the equalization circuits. Failure to do so results in improper operation
of the noise reduction circuits. The system shown in Figure
3 utilizes the external loop to include DNR and a multi-band
equalizer.
1
2qC(14 kX)
The bass turn-over frequency is nominally
1
fBT e
2qC(30.4 kX)
when maximum boost is chosen. The inflection points (the
frequencies where the boost or cut is within 3 dB of the final
value) are for treble and bass
fTT e
TONE CONTROL RESPONSE
Bass and treble tone controls are included in the LMC1983.
The tone controls use just two external capacitors for each
stereo channel. Each has a corner frequency determined by
the value of C2 and C3 (see Figure 4 ) and internal resistors
in the feedback loop of the internal tone amplifier. The maximum-boost or cut is determined by the data sent to the
LMC1983 (see Table I).
The typical tone control response shown in Typical Performance Curves were generated with C2 e C3 e 0.0082 mF
and show the response for each step. When modifying the
tone control response it is important to note that the ratio of
C3 and C2 sets the mid-frequency gain. Symmetrical tone
1
2qC(1.9 kX)
1
fBI e
2qC(169.6 kX)
fTI e
TL/H/11279 – 5
FIGURE 3. System Block Diagram Utilizing the External Processing Loop (One Channel Shown)
9
Application Information (Continued)
of boost is dependent on the volume attenuator’s setting.
The loudness characteristic, with the volume attenuator set
at 40 dB, has a transfer function of
VO
(sC5R2 a 1)[sC4(R1 a 156k) a 1]
e
VI
(s2)C4C5R2(163k) a s[C4(156k) a C5(4.9R2 a 156k)] a 1
The external components R1 and C4 can be eliminated and
pin 11(18) left open if bass boost is the only desired loudness characteristic.
TL/H/11279–6
FIGURE 4. The Tone Control Amplifier
Increasing the values of C2 and C3 decreases the turnover
and inflection frequencies: i.e., the Tone Control Response
Curves shown in Typical Performance Curves will shift left
when C2 and C3 are increased and shift right when C2 and
C3 are decreased. With C2 e C3 e 0.0082, 2 dB steps are
achieved at 100 Hz and 10 kHz. Changing C2 and C3 to
0.01 mF shifts the 2 dB per step frequency to 72 Hz and
8.3 kHz. If the tone control capacitors’ size is decreased
these frequencies will increase. With C2 e C3 e 0.0068 mF
the 2 dB steps take place at 130 Hz and 11.2 kHz.
TL/H/11279 – 7
FIGURE 5. Loudness Control Circuit
SERIAL DATA COMMUNICATION
The LMC1983 uses the INTERMETAL serial bus (IM Bus)
standard. Serial data information is sent to the LMC1983
over a three wire IM Bus consisting of Clock (CLK), Data
(DATA), and Identity (ID). The DATA line is bidirectional and
the CLK and ID lines are unidirectional from the microprocessor or micontroller to the LMC1983. The LMC1983’s bidirectional capability is accomplished by using an open drain
output on the DATA line and an external 1 kX pull-up resistor.
The LMC1983 responds to address values from 01000000
(40H) through 01000111 (47H). The addresses select one of
the eight available functions (see Table I). The IM Bus’ lines
have a logic high standby state when using TTL logic levels.
As shown in Figure 6 , data transmission is initiated by low
levels on CLK and ID. Next, eight address bits are sent. This
address information includes the code to select one of the
LMC1983’s desired functions. Each address bit is clocked in
on the rising edge of CLK. The ID line is taken high after the
eight bits of address data are received by the LMC1983.
LOUDNESS
The human ear has less sensitivity to high and low frequencies relative to its sensitivity to mid-range frequencies between 2 kHz and 6 kHz for any given acoustic level. The low
and high frequency sensitivity decreases faster than the
sensitivity to the mid-range frequencies as the acoustic level
drops. The LMC1983’s loudness function can be used to
help compensate for the decreased sensitivity by boosting
the gain at low and high frequencies as the volume control
attenuation increases (see the curve labeled ‘‘Gain vs Frequency with Loudness Active’’).
The LMC1983’s loudness function uses external components R1, R2, C4 and C5, as shown in Figure 5 , to select the
frequencies where bass and treble boost begin. The amount
TL/H/11279 – 8
FIGURE 6. LMC1983’s INTERMETAL Serial Bus Timing
10
Application Information (Continued)
change a function’s operating point. CLK must be stopped
when the final 8 data bits are received. The data stored in
the internal data latch remains unchanged until the ID is
pulsed, signifying the end of data transmission. When ID is
pulsed, the new data in the data shift register is latched into
the data latch and the selected function takes on a new
operating point.
A complete description and more information concerning
the IM Bus is given in the appendix of ITT’s CCU2000 datasheet.
The controlling system continues toggling the CLK line eight
more times. Data that determines the selected function’s
operating point is written into, or single bit information on
DIGITAL INPUT 1 or DIGITAL INPUT 2 is read from, the
LMC1983. Finally, the end of transmission is signaled by
pulsing the ID line low for a minimum of 3 ms. The transmitted function data is latched and the function changes to its
new setting.
Table I also details the serial data structure, range, and bit
assignments that sets each function’s operating point. The
volume and tone controls’ function control data binarily increments from zero to maximum as the function’s operating
point changes from 80 dB attenuation to 0 dB attenuation
(volume) or b12 dB to a 12 dB (tone controls). Note that
not all data bits are needed by each function. The extra bits
shown as ‘‘X’’s (‘‘don’t cares’’) are position holders and
have no affect on a respective control. They are necessary
to properly position the data in the LMC1983’s internal data
shift register. Unexpected results may take place if these
bits are not sent.
The LMC1983’s internal data shift register can handle either
a 16-bit word or two 8-bit serial data transmissions. It is the
final 8 bits of data received before the ID line goes high that
are used as the LMC1983 selection and function addresses.
The final eight bits after the ID line returns high are used to
DIGITAL I/O
The LMC1983’s two Digital Input pins, 2 and 3, provide single-bit communication between a peripheral device and the
controller over the IM Bus. Each pin has an internal 30 kX
pull-up resistor. Therefore, these pins should be connected
to open collector/drain outputs. The type of information that
could be received on these lines and retrieved by a controller include FM stereo pilot indication, power on/off, Secondary Audio Program (SAP), etc.
According to Table I, the logic state of DIGITAL INPUT 1
and DIGITAL INPUT 2 is latched and can be retrieved over
the IM Bus using the read command (47H). The single-bit
information sent on the IM Bus is active low since these
lines are internally pulled high.
11
LMC1983 Digitally-Controlled Stereo Tone and
Volume Circuit with Three Selectable Stereo Inputs
Physical Dimensions inches (millimeters)
Order Number LMC1983CIN
NS Package Number N28B
Order Number LMC1983CIV
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Tel: (043) 299-2300
Fax: (043) 299-2500
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Telex: 391-1131931 NSBR BR
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Tel: (3) 558-9999
Fax: (3) 558-9998
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.