(4.8 GHz) CARD CAGE CIRCUIT - NRAO Library

NATIONAL RADIO ASTRONOMY OBSERVATORY
Socorro, New Mexico
VLBA TECHNICAL REPORT NO. 30
FRONT-END F105 (4.8 GHz) CARD CAGE CIRCUITRY
Addendum to VLBA TECHNICAL REPORT NO. 3
Gerry Petencin and David W eber
January 15 1995
Table o f Contents
1.0
INTRODUCTION ...........................................................................................................................................1
2.0
THEORY OF O P E R A T IO N ........................................................................................................................ 1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
Front-End Block Diagram .............................................................................................................. 1
Front-End Interface Signals and Characteristics ....................................................................... 3
Front-End Modes and Cryogenics S t a t e s ....................................................................................4
Cryogenic Control E q u a tio n s .........................................................................................................4
Control Card D e sc rip tio n ................................................................................................................ 5
M onitor Card Description ..............................................................................................................9
Sensor Card Description ..............................................................................................................11
Bias Card D e sc rip tio n ................................................................................................................... 19
RF Card D e sc rip tio n ......................................................................................................................23
Dewar DC Interface Description .............................................................................................. 23
AC Circuitry Description ........................................................................................................... 24
DVM Readout Values and Tolerances .................................................................................... 25
Monitor and Control System Monitor Readout Values ....................................................... 26
Band, Serial Number, and Modification Level E n c o d in g .....................................................27
Front-End DC Power and Quality G ro u n d ...............................................................................27
3.0
LIST OF RELEVANT NRAO D R A W IN G S ......................................................................................... 29
4.0
COMPONENT DATA SHEETS .............................................................................................................. 31
5.0
A P P E N D IX ......................................................................................................................................................33
5.1
5.2
List of Relevant NRAO Technical Reports and Memoranda .............................................33
Vacuum Sensor Field Calibration Procedure ..........................................................................33
ii
List o f Illustrations
Figure 1 M onitor P a n e l .......................................................................................................................................... 9
Figure 2 DV-6R Vacuum Sensor Connections
............................................................................................11
Figure 3 DT-500 Cryogenic Sensor Response C u rv e .................................................................................... 16
Figure 4 Dewar Feedthrough L a b e l................................................................................................................... 24
Figure 5 VLBA F I 05 Electronics Screen
...................................................................................................... 26
Figure 6 VLBA F I05 Cryogenics Screen
...................................................................................................... 26
iii
1.0 IN T R O D U C T IO N
Technical Report No. 30 is an addendum to VLBA TECHNICAL REPORT NO. 3 (F105, 4.8
GHz, 6 cm). This report augments the RF, thermal and physical descriptions contained TECHNICAL
REPORT NO. 3 (TR 3) by describing the card cage circuitry and its interfaces with the RF amplifiers,
vacuum and temperature sensors, vacuum valve, refrigerator, heater, calibration circuitry, and the Monitor
and Control system. The temperature and pressure transducer characteristics are also described. Since
the Front-End's RF and thermal characteristics are described in TR 3, these topics are not included in this
report
An important graphic feature of the Theory of Operation (Section 2.0) is a detailed Front-End
block diagram that shows all Front-End interconnect and interface circuitry. Reduced scale copies of the
schematic and assembly drawings for the four card types and the associated BOMs are included. The card
descriptions include alignment procedures.
Section 3 contains a list of relevant NRAO Technical Reports and memoranda.
Section 4 contains data sheets for special-purpose components used in the card cage circuitry.
Since TR 3 contains many assembly and BOM drawings and the card cage wire list, they are not
included in this report. These drawings are referenced in the circuitry descriptions as required.
2.0 T H E O R Y O F O PE R A T IO N
2.1 F ro n t-E n d Block D iagram
Drawing C53205K002, following this text, is the F105 block diagram and provides a functional
overview of the F105 circuitry. It shows the card cage, dewar, RF Plate, pressure and temperature
transducers, vacuum valve, refrigerator control, and Monitor and Control interface circuitry. The five card
types are shown in block form; the card's schematic, assembly and BOM drawings are included for
reference in the circuit card descriptions.
I/O connector pins and signals are tabulated in section 2.3. The card cage assembly drawing is
D53206A005 and is shown on Appendix page 11-19 in TR 3. This is the F106, 8.4 GHz card cage
assembly and was used for F I 05 fabrication because the F I05 and F I 06 card cage packaging requirements
were identical. This drawing shows the card cage, I/O connectors, card connectors, power resistors, P I 2,
P13, P14, P15, and P16 cable connectors and chassis ground lugs.
1
2
3
4
1
2
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2.2 Front-End Interface Signals and Characteristics
C ard Cage Panel C onnectors
J5-PUR, Control & ID
J2-Honitor
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
Function/Type
VP
PUMP VAC Mon/analog
VD
DEWAR VAC Mon/analog
15K
15K TEMP Mon/analog
50K
50K TEMP Mon/analog
300K
300K TEMP Mon/analog
AC I
AC CURRENT Mon/analog
RF1
RCP STAGE 1 Mon/analog
RF2
OTHER STAGES Mon/analog
LF1
LCP STAGE 1 Mon/analog
LF2
OTHER STAGES Mon/analog
LED
LED VOLTAGE Mon/analog
Not Used
QGND
QUALITY GND/analog
SENS
TEMP SENSE A Mon/analog
Not Used
Not Used
Not Used
Not Used
Not Used
S
SOLENOID MON/TTL
P
PUMP REQUEST MON/TTL
M
MANUAL MON/TTL
X
CONTROL
MON/TTL
C
MOOE
MON/TTL
H
MONITOR
MON/TTL
Pin
Name
Function/Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
POWER GROUND
+15
+15V/FE Power
-15
-15V/FE Power
Not Used
Not Used
X
CONTROL BIT/TTL
C
CONTROL BIT/TTL
H
CONTROL BIT/TTL
PA
FE PARITY/TTL
Not Used
CAL +28V DRIVE/CMD
HI CAL +28V DR IVE/CMD
GND Not Used*
F0
LSB
/TTL
F1
FREQUENCY /TTL
F2
ID
/TTL
F3
MSB
/TTL
SO
LSB
/TTL
S1
LSB
/TTL
S2
SERIAL
/TTL
S3
NUMBER
/TTL
S4
ID
/TTL
S5
MSB
/TTL
M0
MOO IFICATION/TTL
M1
MSB
/TTL
J4-Auxiliary
J1- AC Power Interface
Pin
Pin
Name Function/Type
1
2
3
01 SHIFTED PHASE/150 VAC
02 LINE PHASE/150 VAC
RETURN
Name Function/Type
AC+
1
AC2
P
3
GND
4
5 through
CURRENT MON/analog
CURRENT MON/analog
PUMP REQUEST CMD/TTL
GROUND PUMP REQ RET/GND
9, Not Used
J3- Dewar Bias, LED & Tenp
Pin
Name
Function/Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TSA Ret (15K) Ret/analog
TSA Sig (15K) Sig/analog
TSB Ret (50K) Ret/analog
TSB Sig (50K) Sig/analog
LCP GATE 1 BIAS/analog
LCP DRAIN 1 BIAS/analog
LCP GATE 2 BIAS/ananlog
LCP DRAIN 2 BIAS/ana log
LCP GATE 4 BIAS/ana log
LCP DRAIN 3 BIAS/analog
LCP GATE 4 BIAS/analog
LCP DRAIN 4 BIAS/analog
RCP GATE 1 BIAS/analog
RCP DRAIN 1 BIAS/analog
RCP GATE 2 BIAS/analog
RCP DRAIN 2 BIAS/analog
RCP GATE 3 BIAS/analog
RCP DRAIN 3 BIAS/analog
RCP GATE 4 BIAS/analog
RCP DRAIN 4 BIAS/analog
DEWAR GND Not Used*
LED DRIVE/analog
LED
Not Used
DEWAR HEATER/150 VAC
DEWAR HEATER RET/AC
Dewar DC Feedthrough - See Figure 4 in Section 2.10.
RF I/O Connectors:
J6-RCP RF Out;
J7-LCP RF Out; J8-Phase Cal Input
AC Power Cables: P12 Refrigerator AC Power J12; P13 AC power to Elapsed Time Indicator J13; P14 AC drive to
Solenoid J14.
See Wire List A53206W001, Sheet 8 (TR 3 Appendix page 11-37), and 4.8 GHz FE Block Diagram
C53205K002 for connections.
Vacuum Sensor Cables: Pi5 Punp Vacuum Sense to Pump DV-R6 J15; P16 Dewar Vacuum Sense to Dewar DV-R6 J16
See Wire List A53206W001, Sheet 7 (TR 3Appendix page 11-36) and 4.8 GHz FE Block Diagram C53205K002 for
connections.
* Although VLBA Front-End manuals typically designate this pin as Ground, it is not wired in F105; see (Wire
List Sheet 12, TR 3 Appendix page 11-41).
3
2.3 Front-End Modes and Cryogenics Control States
The F105 Front-End operates in two Modes: Local (manual) and C PU (remote). The mode is
manually selected by S 1, the Heat, Pump, Off, Load, Cool, CPU manual selector switch on the card cage
Control-M onitor panel. When the switch pointer is in the CPU position, the mode is computer-remote;
if the pointer is in any other position, the mode is Local-manual. W hen the switch is in the Local mode,
the control computer cannot override the mode switch setting.
In both modes, there are five Cryogenic States selected by either the manual selector switch in
the Local mode or by the control computer in the CPU mode. These five states are: Heat, Pump, Off,
Load, and Cool. The table below briefly describes the operations performed by the cryogenic components
as a function of the Cryogenic State. The three control discretes X, C, and H (described in the Monitor
Card description) determine the operation of the refrigerator, vacuum valve and pump request drive
circuitry in the Control Card (described below).
State
X
c
H
Cryogenic Functions
OFF
1
0
1
No refrigerator power, heater power or vacuum pumping.
COOL
1
1
1
Normal cooled operation.
STRESS
1
0
0
COOL with a small added heat load to stress-test the cryogenic
system.
HEAT
1
1
0
Fast warm-up of the dewar with 35 watts of heat added. PUMP
REQ goes high when dewar vacuum is greater than 10
microns.
PUMP
0
1
0
No refrigerator or heater power. PUMP REQ is high. The
vacuum solenoid is open when the manifold pressure is less than
the dewar pressure.
In the CPU mode, three computer-commanded X , C, and H control discretes from the FI 17
(VLBA) or the F14 (VLA) control the cryogenic state. H is the standard terminology for this term and
the bar on top does not imply logic negation. The * suffix denotes a logic negation; thus H is true and
H* is false.
2.4 C ryogenic C ontrol E quations
From the table above, it would appear that when the X, C and H control bits are set to the state
appropriate for a desired cryogenic state, the cryogenic functions are automatically activated. This implied
automatic activation is not the case; the commanded action will happen only if TA (15 °K stage
temperature), VD (dewar vacuum), and VP (pump vacuum) parameters are in ranges appropriate for these
actions and the relationship between VD and VP is correct. Control logic equations for these cryogenic
functions contain discrete terms which are a function of the parameter level and an associated threshold
value. If the parameter is within the specified range, the term is true and is an enabling factor in the
activation of the function. If a parameter is outside the specified range, it is false and the term inhibits
the activation of the function. With the exception of the OFF state, which is unconditional, all equation
4
terms must be true to activate the selected action. The + symbol denotes an OR function and the •
symbol denotes an AND function. Parenthesis brackets delimit an AND term and a * suffix denotes a
logic negation.
W hen the logic equations are true, they activate the following:
L—
P—
Q—
R—
S—
activates a 1/2 W dewar power load to stress-test the refrigerator.
the Pump Request activates the vacuum pump.
activates a 30 W power load to heat the dewar.
activates refrigerator AC power.
activates the solenoid valve to enable the vacuum pump to reduce dewar pressure.
The equations are:
L = C *«H *«(TA <360 °K)
P = (C+C *«H *)*(V D >3nm )
Q = (X *+C *)«H «n;A <360 °K)
R = ( O H * + C* • H) • (VD<50 n m)
S = (C +C **H *)»{(V D >5^m )«(V P<V D )«(TA >30 °K) + (V D >50^m )«(TA >280 °K)}
These equations are implemented on the Control Card, schematic D53200S003, described below.
The X, C and H control discretes come from the Monitor Card, schematic D53200S005, described below.
The TA, VD and VP analog signals come from the Sensor Card, schematic DD53200S002, described
below.
2.5 C ontrol C a rd D escription
The Control Card (schematic D53200S003) is installed in slot 7 and implements the cryogenic
control logic equations described above. During the following discussion, refer to the reduced copy of
this drawing following this text. A description of the implementation of these control equations follows
a description of the card inputs and outputs.
The card inputs are the TTL level X, C and H control terms from the Monitor Card and the TA,
VD and VP analog signals from the Sensor Card. TA is the 15 °K stage dewar temperature, VD is dewar
vacuum and VP is the pump vacuum.
The card outputs are P, the pump request discrete, and 150 VAC power to the refrigerator, vacuum
solenoid, 760 Q dewar heater resistor and the 5 kQ dewar heater limiting resistor. The AC power outputs
are switched by relays K1 through K5. During the following discussion refer to Figure 1.3.3 on page 18
(in TR 3), which shows the Front-End AC wiring. Note that a PCB track connects the 150 VAC unshifted
phase input on pin X (designated 150V A on the schematic) to pins Y, W and S. Also note that a PCB
track connects the 150 VAC shifted phase input on pin U (designated 150V C on the schematic) to pin
V. The AC circuitry is described in Section 2.11.
See Block Diagram C53205K002 for the Control Card connections. Wire list A53206W 001,
Appendix page 11-37 (in TR 3), also describes the Control Card wiring connections.
5
The control equations are implemented in LS-TTL digital logic. The analog signals are thresholdcompared and the comparator outputs are compatible with TTL logic. The comparator threshold levels
are described below.
Three LM339N analog comparator outputs change state at three preset levels of TA. The U l-1,
U l-2 and U l-14 outputs switch states when TA>30 K, TA>280 K and TA<360 K, respectively.
Three LM339N analog comparator outputs change state at three preset levels of VD. The U2-1,
U2-2 and U2-14 outputs switch states when V D >3|im , VD>5jxm and VD <50nm , respectively. One
LM339N comparator, U2-13, compares VD with VP and switches high when VP<VD.
An analog comparator is a form of operational amplifier whose output makes large level changes
for small differences in the two input terminals. Typically, one of the inputs, either the + or - input, is
connected to a preset reference level. When the other input slightly exceeds or is slighdy less than the
reference input, the output makes a large change.
The LM339N comparator output is high when the voltage on the negative (-) input is more
negative than the voltage on the positive (+) input Comparators can be either inverting or non-inverting
depending upon the choice of inputs for reference level and input signal. U l-14 is an inverting
comparator because the + input is connected to a reference voltage and the negative (-) input is connected
to the variable signal. The output swings low if the variable signal is more positive than the reference
level. The operation is analagous to an inverting operational amplifier. The non-inverting comparator has
the - input connected to the reference level and the variable signal is connected to the + input The output
swings high (positive) when the variable signal is more positive than the reference level. The operation
is analagous to a non-inverting operational amplifier. U l-1, U l-2, U2-1, U2-2 and U2-14 are non­
inverting comparators. U2-13 is a basic comparator because both inputs are variable levels. An LM339
data sheet is included in Section 4.
The comparator outputs have positive feedbacks so that the comparator's switching thresholds
exhibit hysterisis. The hysterisis effect (or signal overdrive requirement) requires that the variable analog
signal swing past the level that would cause the output to switch if hysterisis were not a factor. The
hysteresis property applies to both positive-going and negative-going levels of the variable signal.
Hysterisis is often used in analog comparator circuits to eliminate noise-induced switching when the
variable level is near the reference level. Low-level noise is generally present in analog signals and
comparator hysterisis prevents noise-induced switching in this situation.
TA scaling is 10 mV/°K. The TA comparator reference levels and associated temperatures are:
U l-1, +0.297 V (29.7 °K); U l-2, +2.816 V (282 °K); U l-14, +3.602 V (360 °K). The VD comparator
reference levels and associated vacuums are: U2-1, +0.745 V (3 nm); U2-2, +1.334 V (5 |im ) and U2-14,
+4.521 V (50 nm ). These vacuum levels are based upon the chart of vacuum monitor voltage versus
vacuum on page 15, TR 3.
The TA comparator hysterisis values are: U l-1, 50 mV (5 °K); U l-2 , 50 mV (5 °K), U l-14, 10
mV (10 °K). The VD comparator hysterisis values are: U2-1, 278 mV (« 1.8 n); U2-2, 350 mV (« 3
^m ); U2-14, 10 mV (* 0.4 [im) and U2-13, 50 mV (* 2 \im).
U10, an Analog Devices AD581JH precision voltage reference, provides a +10 volt DC reference
for the comparator reference voltage dividers. Since the load on the AD581 does not vary and the Front6
Ends operate at about 25 °C, the +10 reference is stable within a few millivolts. An AD581 data sheet
is included in Section 4.
Refer to the equations above. Examination of the equations shows that the terms O H * and
C*«H are used in four of the five equations. These two terms are formed in OR-gates U6-6 and U 6-11
and are combined as required in the equations. Since the^X, C, and H control discretes are used in all the
equations, the yellow CR6 (X), red CR8 (C) and CR9 (H) LEDs are provided to make it easier to check
the card logic.
The solid-state relays K l, K2, K3 and K4 and their associated LEDs are driven by 75452 dual
peripheral drivers. Each driver has a two input AND gate that drives an open-collector, high current
sinking capacity output transistor. K l through K5 are all solid-state relays with an LED input optically
coupled to a solid-state AC switch.
L, the 1/2 watt load equation L = C*®H»(TA<360K), causes a 5 kQ limiting resistor to be
inserted in series with the 760 Q dewar heater resistor. The resistor is inserted by closing relay K2; K3
is open in this state. (See the Front-End AC wiring schematic on page 20 in TR 3.) The term T3
(TA<360 °K) from comparator U l-14 is AND-ed with H in U6-4. This is AND-ed with C* in U7-3 (a
75452) and the output is low when all three terms are high-true. The low-true output sinks current from
+ 15 V through the coil of relay K2 and CR4, a yellow LED (5 kQ ). The relay's output switch connects
the lower end of the 5 KQ resistor to AC low.
Q, the dewar heater equation Q = (X*+C*)»H»(TA<360K), uses the T 3«H product from U6-6.
It is AND-ed with X* + C* from U 11-1 in gate U8-5 (a 75452). The output is low-true when all three
terms are high-true and sinks current from +15 V through the LED of relay K3 and the red LED
(HEATER), CR3. K3's output applies 150 VAC to the 760 Q dewar heater resistor.
P is the pump request equation P = (C +C *«H )«(V D >3|im ). AND gate U6-3 uses the C + C*»H
term from U5-3 (mentioned above) and the VI term from comparator U2-1 (VD>3 fim). The output is
high-true if both input terms are high-true. This P (pump request) output goes to the auxiliary connector
pin J4-3 to drive an external vacuum pump control circuit. It is also connected to the monitor connector
J2-21 to enable the monitor and control system to read the P state. CR7 (PUMP), a yellow LED, sinks
current through inverter U3-2 from +5 volts when P is high.
R, the refrigerator power equation R = ( O H * + C *«H )«(V D < 50^m ), uses the ( O H * + C*«H )
term from U5-6 (described above). This term is inverted to low-true by U3-8, which drives a 74LS32 gate
U5-8. In this application, the 74LS32 functions as a low-true AND. The U5-8 output is low-true only
if both inputs are low. V3, VD>50 \im is the other U5 input. This term is high when VD>50 jam and
low when VD<50 \im. Thus the U5-8 output is low when ( O H * + C*«H )#(V D <50 ^m). U8 is a
75452. The pin 1 input is connected to +5 through a 4.7 KQ resistor so that output U8-3 is high when
the equation is true. The U8-3 output sinks current from +15 V through K4's LED and a 750 Q resistor.
When K5 is actuated, it connects the 150 VAC return (or common) to the refrigerator. Note from the
block diagram above that card pin X is connected to 150 VAC, Phase 1, the unshifted phase. This line
drives a rectifier-divider-filter circuit consisting of CR2 (1N4007), R35 (lOkQ), R36 (lk Q ) and C9 (100
|iF). When the 150 VAC, Phase 1 power is present at the filter input, C9 charges to about 19.3 volts.
Note that K4's contacts are connected to the junction of the 10 kQ and 1 kQ resistors and to the low side
of the capacitor so that when K4 is actuated, the filter input is shorted. W hen the equation is true, K4
7
is not actuated, its contacts are open, and the capacitor is charged to .about 19 volts. This DC voltage
drives K5's LED, which closes its output contacts to pass the 150 VAC return (or common) to the
refrigerator. Section 4 has data sheets for the 75452 and the relays.
S, the solenoid equation, is the most complicated and is the OR sum of two sets of AND products.
S = (C +C **H )»{(V D >5|im )*(V P<V D )«(TA >30K ) + (VD>50|im )«(TA>280K)}. TJieterm D(C+C*H )
is common to both products. Consider the first set of products. The first term, C+C*H, is formed by U53. The second term, V2 (VD>5^m ), is the output of comparator U2-1. The third term, V4 (VP<VD),
is the output of comparator U2-13. The fourth term T l, (TA>30 °K), is the output of comparator Ul-1.
(VD>5 fim), (VP<VD) and ((TA>30 °K) are AND-ed in gate U4-6. The output is ORR-ed in gate U 5-11,
a 75452 driver, with the second product. The second product is formed in U4-12, which has the inputs
V3 (VD>50|im ) and T2 (TA>280 °K). The U 5-11 output drives one input on U7-5. The other input is
the D (C +C*H) term from U5-3. U7-5 sinks current through K l's LED and CR1 (SOL), a yellow LED.
The SMON term, a monitor discrete, is formed in gate U4-8 by the output of U 5-11 and D. The Solenoid
valve is an inductive device and if it does not actuate, the solenoid's AC current demand can be as high
as 0.40 amperes. To protect K 1 from current-induced voltage surges, an MOV and series RC circuit are
connected across K l's output. The MOV clips voltage peaks and the RC circuit provides additional surge
protection to K l.
For convenience in maintenance, the card LEDs mentioned above and circuit level test jacks are
placed on the card edge for easy access. LED and test jack labels are silkscreened on the card. See the
card assembly drawing D53200A004 for the locations.
The card's +5 volt logic power is derived from +15 volt power by U9, a MC7805, 5-volt DC
regulator.
C ontrol C a rd A lignm ent
The Control Card does not have any alignment adjustments. There is not a Control Card tester
or formal card alignment procedure but the circuit operations can be evaluated using the card's
maintenance features, the Monitor Panel DVM and the Monitor Panel State Select switch, SI. The levels
of four analog signals, TA (15 °K), VD, VP and ACI (AC current load), can be measured using the DVM.
The states of the comparator outputs (via card test jacks) can be related to these analog signal levels.
LEDs on the X, C and H control discretes enable verification of the control inputs from the Monitor Card.
LEDs on the outputs of the five equation's logic circuits indicate the state of the equation's logic output.
The Monitor Panel's State switch SI can be set to select any of the five possible manual-mode states. This
will cause the X, C and H states to activate the logic equations as described above. In most cases, the
card circuitry can be evaluated by selecting a cryogenic state, noting the TA, VD, VP, and ACI analog
levels, the associated comparator outputs, and the response of the solenoid, the refrigerator, vacuum pump,
dewar heater, and 1/2 watt load to these signal levels and control states.
I/ 6 U 3
,3 l\
,2
R37
390 b'/.
rO
&§
cyre7
l pump
2 ty,------ a ,
+5
T I TA >30K
Tl TJI
SOLB
4 7 b'/.'
k
U MOVI
| 970-2
150 VAC
rC 8
'
D47»jf
600V
y~T2 TA>280K
'— <T2tj2
MREF B
T3 TA<360K
-------< T 3 t j 3
1815K RES.
191HEATER
V I VD>3>j
V I TJ4
NOTES
1. UI-U2 -LM339N
2. U3-74LS04
3. U4--J&VLSU
4. U5-74LS32
5. U6-74LS08
6. U7-U8-75452
7 U9-7805CT
8 UI0-AD58IJH
9. ALL CARS ARE 50V UNLESS OTHERWISE MARKED.
IQ ALL RES. AS FOLLOWS:
I y. I/8WATT
5 x 1/4 WMT
11. KI-K3-645-2
12.UII-74LS02
-is fc T IT -J ^
V2 VD>5p
V2 TJ5
{ x ] l50v A
VD
DEWAR VAC
Y REF A
W HTR A
V3 V0>50(j
<V3TJ6
SOL A
^{U] 150V C
13. K4 - 643-1
VP
CONTROL
X c
1 1
1 0
1 0
0 1
1 1
0 0
0 0
0 1
BIT
H
1
0
1
0
0
0
1
1
SYSTEM
MODE
NORMAL
1/2 W LOAD
NO COOL, HEAT OR PUMP
PUMP ONLY
PUMP AND HEAT (30W)
LOAD
OFF
COOL
OCTAL
VALUE
7
4
5
2
.6
0
1
3
.
14. K5- MP240D4
V REFC
STATE
COOL
LOAD
OFF ’
PUMP
HEAT
UNUSED
UNUSED
UNUSED
TTL LOGIC
1=CN =H I LEVEL
0=0FF=L0 LEVEL
CONTROL LOGIC*
LINE VAC
V4 VP<VO
< V 4 TJ7
1
<GND
TJ8
o
L=1/2 W Load
=C»H»(TA<360K)
P=Pump Request
= ( C+^C*H) • ( VD>3 |x)
Q=Heater 30 W
= (X+C‘)«H«(TA<360K)
R=Refrigerator FWR
=(C«H+C*H)*(VD<50 jO
ADOEft TO’ NOTtV. *
V/VJKLtrP
c
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A
Rf«
DATE MMM §Y
FRONT ENDS
ii+fn'B rr
CQ-B40&I7-2D
octcwmoN
NATIONAL RADIO
ASTRONOMY
OBSERVATORY
CHARLOTTtSVtlLC, VA. IHO«
S=Valve Open (Sol. On) = ( C*C*H) • ( VD>5fO • ( VP<VD) • (TA>30K) + ( VD>50 n) • (TA>280K)
CONTROL CARD rff.Riu.
K&no
REV
C
DATE
ORAWN BY APPRVt) BY
9 -9 4 TATE
DESCRIPTION
PETENCIN REVISED AND REDRAWN
(8J7)
■ M l
U9
(O)
-
C5
- ♦
C6
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(450)
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H R36 h
COMPONENT SIDE
ACAD
53200A04
C9
—
R55
—
58
NUT.HEX.SS.4-40UNC-2B
1
57
1
WASHER. LOCK. #4
56
1
55
AUGAT
SOCKET. 8 -P IN
U 7 -U 8
608-CG 1
2 .
54
U1-U6.U11 AUGAT
SOCKET. 1 4 - PIN
7
614-C G 1
U 11
53
GATE. NOR. QUAD INPUT
TEXAS INSTRUMENTS SN74LS02N
1
52
U10
REFERENCE. VOLTAGE
1
ANALOG DEVICES AD581JH
51
U9
MOTOROLA
MC7805CT
REGULATOR. POSITNE
1
50
U7.U8
TEXAS INSTRUMENTS SN75452BP
GATE. NAND
2
49
U6
TEXAS INSTRUMENTS SN74LS08N
GATE. AND. 2-INPUT
1
48
U5
1
TEXAS INSTRUMENTS SN74LS32N
GATE. OR. 2-INPUT
U4
47
TEXAS INSTRUMENTS SN74LS11N
GATE. AND. 3-INPUT
1
46
U3
TEXAS INSTRUMENTS SN74LS04N
1
INVERTER. HEX
45
MOTOROLA
U1.U2
LM339N
COMPARATOR. OUAD
2
44
TJ8
E.F. JOHNSON 105-0751-001 TEST JACK. BLACK
1
43
TJ6
E.F. JOHNSON 105-0751-001 TEST JACK. WHITE
1
42
TJ5
E.F. JOHNSON 105-0751-001 TEST JACK. RED
1
41
TJ3
E.F. JOHNSON 105-0751-001 TEST JACK. GREEN
1
40
TJ2.TJ4
E.F. JOHNSON 105-0751-001 TEST JACK. YELLO*
2
39
TJ1.TJ7
E.F. JOHNSON 105-0751-001 TEST JACK. BLUE
2
38
RV1
1
TELEDYNE
VARISTOR. METAL OXBE
9 7 0 -2
37
R45
ALLEN-BRADLEY RC07GF751J RESIST0R.750.1/4W.5X
1
36
ALLEN-BRADLEY RC07GF391J
RESIST0R.390.1/4W.5X 4
35
ALLEN-BRADLEY RC07GF102J
R36
1
RESISTOR. 1K.1/4W.3X
34
ALLEN-BRADLEY RC42GF103J
R35
RESISTOR. 10tC2W.5%
1
33
R34
ALLEN-BRADLEY RC07GF470J RESIST0R.47.1/4W.5X
1
32
R32
ALLEN-BRADLEY RC07GF434J RESJST0R.430K.1/4WJ5X
1
31
R31.R43 ALLEN-BRADLEY RC07GF473K RESISTOR.47K. 1/ 4W.5X 2
30
R28
ALLEN-BRADLEY RC07GF22RJ RESIST0R.220K.1 /4WJ5X
1
29
R26
DALE
RN55C4532F RESIST0R.45JK . 1/8W.1X
1
28
R25
DALE
RN55C5492F RESIST0R.54.9K.1 /8W.1X
1
27
R23
ALLEN-BRADLEY RC07GF433J
RESIST0R.43K. 1/ 4WJ5X 1
26
R21
DALE
RN55C1542F RESISTOR. 15.4K.1/8C1X
1
25
R19
ALLEN-BRADLEY RC07GF683J
RESIST0R.68K. 1/4WJ5X 1
24
R16
DALE
RN55C8061F RESIST0R.8.06K.1 /8W.1X
1
23
R13
ALLEN-BRADLEY RC07GF334J RESIST0RJS30K.1/4WJ5X
1
22
R12
DALE
RN55C6341F REStSTOR.6J4K. 1/M.1X
1
21
R11
DALE
RN55C3571F RESJST0R.3.57K.1/WUX
1
20
R6
DALE
RN55C3922F RESIST0R.39.2K.1/8C1X
1
19
R5.R9
ALLEN-BRADLEY RC07GF474J RESIST0R.470K.1/4W5C
2
18
ALLEN-BRADLEY RC07GF472J RESIST0R.4.7K.1 /4WJ5X
10
17
ALLEN-BRADLEY RC07GF512J
RESIST0R.5.1K.1/4WJSS
6
16
DALE
4
RN55C1003F RESISTOR. 100K.1/8W.IX
r?^ r5q
15
R1
DALE
1
RN55C3091F RESKT0RJ.09K.1/8H1X
14
K5
NTE ELECTRONICS R S I-ID 4 -2 I
1
RELAY
K4
13
1
TELEDYNE
RELAY
6 4 3 -1
12
K 1 -K 3
TELEDYNE
RELAY
3
6 4 5 -2
11
CR8
GENERAL INSTRUMENT CMD5274C
1
LED. GREEN
10
CR5
HEWLETT PACKARD 1N5711
DIODE. SCHOTTKY
1
9
CR3.CR9 GENERAL MSTRUMENT CMD5774C
2
LED. RED
8
CR2
MOTOROLA
1N4007
1
DIODE
7
4
LED. YELLOW
w - .. GENERAL MSTRUMENT CMD5374C
C9
6
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CSR13E107KP CAPAClT0R.TANT_100uL5W
C8
5
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CAPACITC>R.47uf.600V 1
4
C7
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CSR13E226KP CAPACIT0R.TANT-22ufJ0V
1
3
C 4 -C 6
MALLORY
CSR13E156KP CAPAOTOR.TANT«15uUOV 3
2
C 1 -C 3
KEMET
C330C104M5U5CA CAPACITOR., luf.50V
3
1
NRAO
1
D53200Q003 BOARD. CIRCUIT
ITEM NO. REF. DES. MANUFACTURER PART NUMBER
DESCRIPTION
QTY
p
UNLESS OTHERWISE SPECIFIED V
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DIMENSIONS ARE IN MCHES
L j COMMON FRONT END
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ARTWORK
MATERIAL :
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IhumboT D53200A004
I** C f*** 2/1
2.6 Monitor Card Description
The M onitor Card is installed in Slot 3 and has two functions: mode-state control via SI (the
Monitor Panel Mode-State switch) and its associated logic and local analog monitoring using the Monitor
Panel DVM and S2, the M onitor Select Switch. Drawing C53200S005 shows the Monitor Card circuitry.
Section 4 contains a data sheet for the DVM, a Texmate PM-45XU 4 1/2 digit panel meter.
The M onitor Panel is attached to the Monitor Card so that the card and panel are a single
assembly. Figure 1 shows the Monitor Panel.
Figure 2 Monitor Panel
See Block Diagram C53205K002 for the Monitor Card connections. W ire list A53206W001,
Sheet 4, Appendix page 11-33 (in TR 3), also describes the Monitor Card wiring connections.
S I,
the mode-state selector switch, has six positions: HEAT, PUMP, OFF, LOAD, COOL and
CPU. When the switch is in the CPU position, the Front-End is controlled by the control computer via
FI 17 (VLBA) or F14 (VLA). In the other five positions, the Front-End cryogenic state is controlled by
the setting of S 1 as shown in the table in Section 2.3 above.
The M onitor mode-state logic is simple encoding and multiplexing logic. S I, the mode-state
switch wiper, is connected to ground. The HEAT, PUMP, OFF, STRESS and COOL contacts are
connected to +5 volt pull-up resistors and the inputs of U l, a 74LS148,_8-line to 3-line priority encoder.
The sixth position, CPU AO, A1 and A2 outputs are the X, C, and H control discretes, respectively.
Since SI has physical stops and the encoder inputs are low-true, the other three encoder inputs can safely
float
The X, C, and H encoder outputs are connected to_the B inputs of U2, a 74LS157 quad 2-input
multiplexer. The m ultiplexer A inputs are the X, C, and H* cryogenic state command inputs from the
CPU (via F14 or FI 17). The multiplexer outputs drive the X, C, and H* inputs of the Control Card
described in Section 2.5 above. The multiplexer A/B input selection is controlled by S I. W hen SI is in
the CPU position, the 2 kQ pull-up resistor to +5 volts causes the mulitiplexer to select the A inputs; in
any of the other five positions, the encoder outputs are selected. The three m ultiplexer outputs are
9
connected to the Control Card.
The choice of encoder states is rather important. If through some mischance or malfunction the
C and H* bits are stuck high or low, the Control Card will assume either the COOL or LOAD states, the
desired default cryogenic states.
Three OR gates in U3, a 74LS32, are used as isolating buffers on the X, C, and H lines to J2, the
cryogenic state monitor outputs to FI 17 or F14 via J2. In the event of an inadvertant short on these lines,
the buffers protect the X, C, and H inputs to the Control Card.
Gate U4-8 decodes the COOL state to sink current from a M onitor Panel red LED, CR2. When
SI is in the CPU position, gate U4-12 sinks current from a Monitor Panel red LED, CR1. The state of
U4-12 is output to FI 17 and F14 via J2.
Five volt logic and DVM power is provided by U5, a 7805CT series regulator.
DVM signal ground reference is Quality Ground from J2-13.
Note that the
The Texmate PM-45-XU has jum per connectors to control its mode and the decimal point is
selected by section 1 of the Monitor Select switch, S2. A pair of test jacks on the panel permits an
external meter to be connected to the DVM input if there is some question about the DVM values. Since
a DVM data sheet is included in Section 4, it is not described here.
Typical values and tolerances for the analog parameters measured by the DVM are described in
Section 2.12.
There are no alignment adjustments for the Monitor Card. The card logic is so simple that it can
be checked by setting the mode-state switch to the six positions and noting the states of the Monitor Panel
LEDs (COOL and MAN) and the Control Card X, C, and H LEDs.
10
REV.
MON
A
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DATE
II-6 ^
DRAWN BY
DESCRIPTION
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6 .ALL CAPS.ARE 50V UNLESS NOTED OTHERWISE,
UNLESS O TH ER W IS E SPECIFIED
DIMENSIONS ARE IN INCHES
r ROn T END
TOLERANCES: ANCLES ±.
J PLACE DECIMALS (.XXX): ±
NATIONAL RADIO
ASTRONOMY
OBSERVATORY
2 PLACE DECIMALS CXX): ±
1 PLACE DECIMALS (JO : ±
M ATERIAL:
DRAWN BY
MONITOR BOARD
„ „
DATE
DESIGNED BY
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NUMBER
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PART
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CAP lt|f 50V
CAP I5uf 20V TANT.
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2.7 Sensor Card Description
The Sensor Card, slot 6, contains the interface circuitry for two Teledyne-Hastings DV-6R vacuum
guages and two Lake Shore DT-500-KL diode temperature sensors. The vacuum guages sense dewar
vacuum (VD) and the pump or manifold vacuum (VP) and the two diodes sense the 15 °K (TA) and 50
°K (TB) dewar temperature stages.
The conditioned VD, VP, and TA outputs of the Sensor Card are connected to the Control Card,
slot 7, for use in controlling the Front-End's cryogenic states. They are also connected to the Monitor
Card for local monitor readout on the DVM and to J2 for readout by the Monitor and Control System.
A non-linear form of TA is also connected to J2 for M onitor and Control System readout This signal
has a higher sensitivity and potentially greater accuracy because it is not subjected to linearizing
corrections. TB is not used by the Control Card but is connected to the M onitor Card for DVM readout
and is also connected to J2 for M onitor and Control System readout See Block Diagram C53205K002
for the Sensor Card connections. Wire list A53206W001, Appendix page 11-36 (in TR 3), also describes
the Sensor Card wiring connections. The Sensor Card schematic is D53200S002 and the assembly
drawing is D53200A003.
Teledyne-Hastings DV-R6 Vacuum Guages
The Hastings DV-6R vacuum gauge is a ruggedized, precision vacuum sensing guage with a
specified range of 0 to 1000 |im o f Hg (sea-level atmospheric pressure is 760,000 nm of Hg.). The DV6R is a thermopile consisting of three identical noble-metal alloy thermocouples; see Figure 2 which
shows the sensor and its connections to the VD interface amplifier. The + symbol indicates the thermal
EMF polarity.
The thermocouple alloys are Gold/Platinum and Platinum/Rhodium.
All three
thermocouples sense the gas pressure and the - (negative thermal EMF polarity) sides of all three are
connected to DV-6R pin 8, which is simply a tie-point that is not connected to any external circuitry. The
+ sides of two thermocouples are connected to pins 3 and 5 and are heated by the AC excitation. The
+ side of the third thermocouple is connected to pin 7, is not heated by the AC excitation, and is
analagous to the reference junction in a conventional thermocouple circuit. The thermal EMF of this third
thermocouple is determined by the temperature of the
sensed gas, is very small, and its polarity is in
opposition to the thermal EMF of the heated
thermocouples.
The vacuum-sensing properties of the DV-6R
are a function o f the sensed ail's thermal conductivity,
which decreases when the air pressure is decreased
A decreasing thermal conductivity increases the hot
junction's temperatures, which increases the thermopile
DC output. A t a high vacuum, the hot junction
temperature is about 300 °C. In the dewar and
manifold vacuum-sensing applications, the DV-6R
sensitivity is determined by the AC heating power
delivered to the thermocouple junction; the Sensor
Card VD ZERO and VP ZERO adjustments determine
this power level. Hastings does not have an explicit
11
Figure 2 DV-6R Connections
mathematical expression for DC output as a function of the sensed air pressure but the DV-6R's output
is roughly a logarithmic function of pressure. Hastings states that the DV-6R accuracy is about ± 2 %
at a high vacuum (~ 1 |im ).
Page 17 (in TR 3) shows a graph of the Sensor Card vacuum interface circuit readout voltage
versus dewar pressure. At a vacuum of 1 |im Hg, and with the appropriate AC excitation, the nominal
DV-6R sensitivity (output voltage change /vacuum change) is -161 mV/}im; this is the DV-6R's highest
sensitivity. As pressure increases, the sensitivity rapidly decreases. At 1000|im the interface circuit
output is +9652 mV and at sea level atmospheric pressure, the interface circuit output is +10,000 mV.
The nominal sensitivity of -161 m V /|im at 1 [im is the value used in Sensor Card alignment.
Hastings' vacuum thermopile interface circuit uses a center-tapped transformer secondary that
drives pins 3 and 5 with a 0.38 volt, P-P square wave; this heats the two thermocouples connected backto-back across pins 3 and 5. The primary is driven by a 5 kHz power oscillator. The thermopile's DC
output connections are pin 7 (the + side of the unheated thermocouple) and the transformer center-tap.
Relative to pin 7, the heated thermocouple's DC voltages on pins 3 and 5 are identical because the two
heated thermocouples are in parallel. Hastings typically connects the DC output to an analog current
meter with a 40 Q current limiting resistor. The Hasting's interface's meter scale is calibrated for the
sensor's working range.
The DV-6R interface circuits are aligned by substituting a Hastings DB-20 reference tube for the
DV-6R. The DB-20 simulates the DV-6R at some high vacuum level, typically 2|im . In a recent lab test,
a Hastings DB-20 Reference Tube marked 2 pm was substituted for the DV-6R. The DB-20 DC output
measured on pin L of the Sensor Card was -287 mV. Although this was slightly under the expected 322
mV, the Sensor Card circuit aligned normally. The vacuum interface alignment procedure is described
below. A Hastings DV-6R data sheet is included in Section 4.
The vacuum guage interface circuitry is shown on the left half of the Sensor Card schematic
drawing, D53200S002. Note that there are three connections to the DV-6R.
V acuum G uage In terface C ircu itry
The DV-6R vacuum gauges require an AC excitation. An oscillator and two power buffers
provide the AC power to drive the thermopiles. The oscillator is U4-8, a TI TL084BCN operational
amplifier used in an RC relaxation oscillator circuit. The oscillation results from an alternating sequence
of capacitor charge-discharge ramps. One output cycle consists of a capacitor charge period and a
capacitor discharge period; therefore the capacitor's voltage waveform is a sawtooth and the oscillator's
output is a square wave. The amplifier's negative (-) input is connected to the capacitor-resistor junction.
The amplifier's positive (+) input is connected to a center-tapped 48 kQ resistive voltage divider,
connected to the amplifier's output; therefore, the amplifier's + input voltage is always half the output
voltage. Capacitor C14 is charged (or discharged) through resistor R81 until a switching threshold is
reached; at the threshold, the amplifier's output switches to the opposite polarity. This causes the charging
current polarity to reverse so the capacitor begins to discharge (or charge). The TL084's two output levels
are the positive and negative saturation limits, about +13.5 and -13.5 volts. The two switching thresholds
are the levels at which the voltage difference between the two amplifier inputs is zero. Since the
amplifier's + input is connected to the midpoint of the 48 kQ resistive voltage divider, the switching
thresholds are +6.25 and -6.25 volts.
12
The oscillator period is 2.2R81C 14, which is 52.8 |iS, so the frequency is about 18.9 kHz.
The + input connected to the voltage divider experiences positive feedback, which adds hysterisis
to the switching thresholds. This prevents spurious noise-induced switching that might otherwise occur
when the differential voltage between the inputs is very small. Low level noise is always present in
virtually any analog circuit.
The voltage on the TL084 inputs are ±6.5 volts above or below ground. This could be a problem
in a conventional operational amplifier. The TL084 has JFET-inputs and is capable of operating with a
differential input voltage of ±30 volts and an input voltage of ±15 volts. Section 4 has a data sheet for
the TL084.
The oscillator output is clipped to a ± 6.2 volt square wave by a zenar diode clipping circuit.
R79, a 2 kQ resistor, isolates the amplifier from the clipper to prevent clipper overload. A pair of
paralleled 1N821, 6.2 volt zenar diodes make a precise + and - 6.2 volt square wave that is nearly
independent of temperature. The 1N821 has a temperature coefficient of 0.01 %/°C. The 1N823, which
may be used as an alternate zenar, has the same zenar voltage but a 0.005 % /°C temperature coefficient.
Since there are two vacuum sensors, two independent sets of DV-R6 drivers and conditioning
amplifiers are required. The driver circuits are power buffers and the conditioning amplifiers are a
differential amplifier driving an inverting amplifier. The Hastings catalog does not specify a resistance
value for the thermopile but it's reasonable to assume that it is small, probably less than an ohm. This
low resistance requires a low impedance, high current drive.
We first consider the VD power buffer, driven by the clipper circuit described above. The power
buffer is U8-1, an inverting operational amplifier with Q l, an emitter-follower power transistor in the
feedback loop. The transistor provides the low impedance, high current drive required by the DV-6R.
The DV-6R must be driven by an AC signal. Therefore, the buffer amplifier input and output are
both AC-coupled. The input is AC-coupled via Q (0.01 nF). At 18.9 kHz, C /s impedance is about 800
Q, small in comparison to R7 (130 kQ ) and R3 (50 kQ). The amplifier output drive to the DV-6R is ACcoupled via C2, 10 ^F. Q 's impedance is about 0.8 Q, small in comparison to the DV-6R impedance.
Note that Q l's collector is connected to ground; a 0.3 mA offset current from +10 volts into U8-2,
the summing junction, shifts Q l's emitter Q-point to about -3.0 volts. This avoids clipping the DV-6R
drive. Diode CR5 across the transistor base-emitter junction prevents base-emitter reverse voltage
protection.
The am plifier gain is controlled by the ratio of feedback to input resistance. The feedback resistor
is R l5 (10 kQ ) and the input resistance is R7 (130 kQ ), and R3, (a 50 kQ pot). The maximum and
minimum gains are 0.076 and 0.055, respectively, as a function of R 3's setting. The clipper output is a
12.4 volt, P-P signal; with these two gain extremes, the corresponding Q l output is about 0.95 volts P-P,
and 0.69 volts, P-P. With R3 set mid-range, the buffer output is about 0.79 volts P-P. Hastings uses a
0.38 volt drive across pins 5 and 3.
The drive is AC-coupled to the DV-6R pin 5 and the thermopile heating current flows through
the two thermocouples to ground via DV-6R pin 3. The 100 pF capacitor across the 10 kQ feedback
resistor R 19 provides some high frequency pre-emphasis.
13
The DV-6R pin 7 output is amplified by cascaded amplifiers, U5-13 (noninverting) and U6-6
(inverting). The DV-6R thermal EMF output on pins 5 and 7 is a DC output that is connected to the
inputs of differential amplifier U6-13. Note from Figure 2 that the two heated thermocouple's thermal
EMFs are in opposition, thus pin 5 is actually at DC ground; this was verified in a recent measurement.
The DV-6R's negative polarity, thermal EMF output on pin 7, drives U5-4, the amplifier's
noninverting (+) input. Since the noninverting input is driven and the noninverting input is static at DC
ground, the amplifier's output signal polarity is the same as the DV-6R pin 7 polarity.
Note that the DV-6R AC excitation is also a normal-mode input to U5-13. The AC level on DV6R pin 7 is half the AC excitation voltage. The normal-mode component is reduced by resistor R86 so
that the AC level on U5-3 is also half the excitation level. The normal-mode component of the AC
excitation is also reduced by the two amplifier's low-pass filtering.
U5-13's gain is 50, determined by the RgfRs5 ratio. The 19.8 kHz AC signal on U5-13's inputs
is filtered by capacitor C4 across U5-13's feedback path. This capacitor in conjunction with RM forms a
single-pole, low-pass filter having a -3 dB frequency of about 3 Hz. Inverting amplifier U5-6 has a gain
of 10, and capacitor C8 provides additional AC filtering. U5-6's -3dB frequency is about 32 Hz.
W hen the pressure is 1 [im, the U5-13's output is - 8.050 volts (50 x -0.161). When the air
pressure is high, U5-13's output is very small.
The next amplifier stage, U5-6, is an inverting amplifier with a gain of 10. Note that the + input
of U5-6 is biased to about +1 volt by the resistive voltage divider to +10 volts. This also causes the input to be biased to the same +1 volt level. If the U5-13 output is about zero volts, which is the
atmospheric pressure level output of the DV-6R, the U5-6 output is +10 volts. If the U5-13 output is 8.050 volts, the result of a 1 ^m pressure in the DV-6R, the U5-6 output is zero volts.
The VD amplifier output may be measured at TJ-5; TJ7 is analog ground. The amplifier's three
outputs (MON OUT, METER, and VD) have isolation resistors R16 (2 kQ ), R 17 (10 kQ ) and R18 (100 Q),
respectively. The METER OUT signal could be used to drive an analog meter but is not used in F I03.
The MON OUT is also not used in F103. The VD output is connected to the Control Card (slot 7), the
Monitor Card (slot 3), and to J2-2 for readout by the Monitor and Control System.
The VP power buffer (U8-14 and Q2) is similar to the VD power buffer but provides a slightly
lower drive for its DV-6R; R7 in the series attenuator is 200 kQ. The maximum and minimum drives as
a function of the R7 setting are 0.49 and 0.30 volts, P-P respectively. With R21 set mid-range, the AC
drive is 0.40 volts, P-P, close to Hastings drive level.
Vacuum Sensor Interface Circuit Alignment
This alignment procedure was abstracted from VLBA Technical Report No. 1.
The two DV-6R interface circuits are aligned by using a Sensor Card Tester. The tester contains
a Hastings DB-20 Reference Tube, which simulates the output of a DV-6R at a specified vacuum level,
typically 2 to 3 |im , printed on the side of the Reference Tube. The vacuum interface circuitry in the
tester has a VD/VP selector switch to connect the DB-20 to either interface circuit and a ZERO/ATMOS
toggle switch for the two adjustments. The DV-6R interface circuits have two alignment adjustments, VP
14
ZERO (or VD ZERO) and VP ATMOS (or VD ATMOS). The VP ZERO adjustment determines the AC
drive level to the buffer circuit and the VP ATMOS adjustment determines the DC offset to the U6-6 (or
U5-6) output amplifiers. In aligning the card's two DV-6R interface circuits, the tester's ZERO/ATMOS
switch is first set to the ZERO position and the card's VP (or VD) ZERO potentiometer is adjusted to
produce an output of 161 mV times the DB-20 reference pressure value. The output can be measured at
TJ6 (or TJ5) on the tester on the EXT DVM jack or by the Monitor Panel DVM. Next, the
ZERO/ATMOS is set to the ATMOS position and the VP (or VD) ATMOS potentiometer is adjusted to
produce an output of +10230 mV (about positive full-scale on a 5 mV/LSB, 12-bit A/D converter). In
the ATMOS position, the tester presents an open circuit to the interface circuit in place of the DV-6R; this
causes the full-scale output Section 4 contains a Hastings DB-20 data sheet. A field calibration
procedure for the DV-6R vacuum sensors is included in the Appendix, Section 5.
DT-500 Temperature Sense Diodes, TSA and TSB
The temperatures of the dewar 15 °K and 50 °K stations is sensed by two Lake Shore DT-500-KL
diode temperature sensors, TSA and TSB. The 15 °K stage conditioned signal is TA and TB is the 50
°K stage conditioned signal. Section 4 contains a data sheet for a similar Lake Shore diode temperature
sensor. The 300 °K temperature is measured by a National Semiconductor LM335 chip and is described
in the RF Card description, Section 2.9, below. Figure 3, on the next page, shows a plot of the DT-500
diode voltage vs. temperature. This plot was abstracted from NRAO EDIR Report No. 204, May 1980
by Michael Balister.
qV
The diode's characteristics are determined by the diode equation: IF = Is (e kT - 1). IF is the diode
forward current and Is is the reverse-bias saturation current. Constants are: Is, e, the electronic charge,
and k, Boltzman's constant. Variables are IF, V, the diode voltage, and T, the diode temperature, °K. If
IF is maintained at a constant value, there are only two variables, V and T. By using a suitable conversion
table and holding IF at a constant value, T may be determined by measuring V. Note from the Lake Shore
data sheets that if IF is 10 |iA , V is 1.345 volts at 13 °K and 0.519 volts at 300 °K.
Diode Interface Circuitry
Block Diagram C53205K002 shows the TSA and TSB diode wiring connections to the Sensor
Card, which has two identical temperature interface circuits. The diode anodes are connected to analog
ground (pins E and F) and the cathodes are connected to the current sources and temperature sense
interface circuit inputs (pins 4 and H). The TA and TB diode interface circuits are shown in the right half
of Schematic diagram D53200S002.
Implementation of a two-segment linearization circuit is suggested by the character of the DT-500
thermal response curve shown in Figure 2. The Sensor Card's diode interface circuitry is an adaptation
of the design described in EDIR No. 204. 1
Consider the TA circuit. Transistor Q3 and associated components are the 10 nA current sources
for TSA. The base of Q3 is held at -8.8 volts by zenar diode CRt (Vz = 6.2 volts). Q3's collector current
is determined by VCE and the resistance between the emitter and -15 volts. Potentiometer R39 adjusts the
1 Page 37, VLB A TECHNICAL REPORT NO. 1, August 29, 1984
15
diode current to the 10 |iA value.
Noninverting, unity-gain voltage
followers U l-1 and U2-1 isolate the
diode's current source circuitry from the
linearization circuitry. Since they simply
buffer the diode's voltage, the amplifier's
outputs are a nonlinear function of
temperature.
The TSA signal is
connected to its linearization circuitry
and to J2-14 for readout by the Monitor
and Control System.
R87, a 1 kQ
resistor, isolates the TA amplifier from
the test point terminal TP1 and the
nonlinear TA output on pin S. The
nonlinear form of TA is not used by the „
3 DT_5(X)
Control Card and is not available to the
Monitor Card DVM. The nonlinear TSB
signal is only used by the TB linearization circuitry.
TEMPERATURE, K
Xemperature Response
Note from the Lake Shore data sheets in Section 4 that at 13 °K, the nonlinear TA signal has a
sensitivity (slope) of 21.9 mV/°K. The sensitivity decreases to 15.9 m V /°K at 24 °K. In this 11 degree
region, the nonlinear TSA signal is more sensitive than the linearized TA and TB signals, which have a
sensitivity of 10 m V/°K. In addition, in this region the nonlinear TA is more accurate than the linearized
TA because the linearized signals are segmented approximations to the diode curve.
The TA and TB linearization circuitry approximates the diode's V versus T curve with two
straight-line segment approximations, only one of which is operative at any given time. When the sensed
temperature changes from one segment's range to the other segment's range, it crosses a segment transition
temperature which causes the other segment's output signal to be selected for output. The segment
amplifier's gains and offsets are adjusted for the best fit for its portion of the diode's V-T curve. The
segment transition temperature is 27 °K. The linearized TA and TB signals can be adjusted to be in exact
agreement with the diode V-T curves at 13, 18, 50 and 300 °K. Since TSB monitors the 50 °K stage,
the lower temperature segment is never operative.
The linearization implementation consists of two independent segment gain paths with gain and
offset adjustments appropriate for the segment, a segment signal level comparator, and a segment selector
switch driven by the comparator.
The TA and TB linearization circuits are identical.
In each circuit both paths are driven by the input, unity-gain voltage follower, U l-1 or U2-1. The
circuitry consists of two parallel-path independent, inverting operational amplifiers with different gains,
an analog comparator that compares the two amplifier's outputs, an analog switch driven by the comparator
that selects the most appropriate amplifier for output, and an inverting output amplifier.
Note from the schematic that one TA path is a HI GAIN path used for the higher temperature
segment and the other path is the LO GAIN path used for the lower temperature segm ent From the
16
paragraph above describing the nonlinear TA signal, note that in the 13 to 24° K range, the diode's
sensitivity is greater than 10 mV/°K so the lower segment amplifier's gain must be less than 1. Also note
that for temperatures greater than 25 degrees, the upper segment amplifier's gain must be greater than 1.
20 kQ gain control potentiometers R43 and
control the gain of the two TA amplifiers U l-7 and U l-8.
For extreme settings of these two potentiometers, the resultant gains are: 4.02 and 3.29, HI GAIN and 0.21
and 0.16, LO GAIN.
Both amplifiers use an offset current from an Analog Devices, AD581JH precision +10.000
reference voltage source. This chip was described in the Control Card description, Section 2.5.
Potentiometers R ^ and R47, 100 kQ , and 50 kQ , respectively, are the offset current adjustments.
Comparator U3-1, a National Semiconductor LM393AN, compares the levels of the high and low
gain amplifiers. If the HI GAIN level on the negative input (-) is more positive than the LO GAIN
positive input (+), the output is low. In the converse case, the output is high. The comparator output is
an open-collector transistor; a 22 kQ pull-up resistor to +15 makes the output levels 0 and +15 volts. The
LM393 features a very low input offset, typically 1 mV, important in this application.
U4 is an Analog Devices AD7512DIKN, dual-channel analog switch that selects either the HI
GAIN signal or the LO GAIN signal as a function of the address (select control) input, pin 4. If pin 4
is high, the HI GAIN amplifier input on pin 9 is connected to the output, pin 10; if low, the LO GAIN
signal on pin 11 is connected to the output. R74 provides isolation from the comparator for the control
input and diode CR4 protects it in the event of a negative control input The AD7512 features a low
"ON" resistance, 75 Q, and low leakage currents. Section 4 contains an AD7512DI data sheet.
Unity-gain, inverting amplifier U 1-14 provides output buffering for the TA output on card pin D.
R56, a 100 Q resistor, provides short-circuit protection for this output. The EX T MON output on pin 6
is not used in F I04.
0 .4 7 .n F Capacitors across the operational amplifiers provide low-frequency filtering of the
temperature signals.
TJ1 and TJ3 enable measurement of the LO GAIN amplifier outputs and TJ2 and TJ4 enable
measurement of the TA and TB outputs, respectively. TP2 and TP3 terminals enable measurement of the
HI GAIN amplifier's outputs.
The Sensor Card Tester uses potentiometers and a buffer amplifier sim ulates the diode temperature
sensors. Using this tester, the TA and TB interface circuits are aligned as follows:
1. Set the DVM switch to TA.
2. Set the Mode switch to A -10 \iA and adjust the A-10 [iA potentiometer for a reading of 1000
on the DVM.
3. Set the MODE switch to TA/TB and the TEMP switch to SHORT and adjust the TA HI GAIN
potentiometer for 4350 mV on the DVM. Adjust the TA LO GAIN potentiometer for 445 mV,
on the A LO GAIN test terminal, read by an external DVM.
4. Set the TEMP switch at 50 and adjust the TA HI GAIN potentiometer for 500 mV on the
tester DVM.
5. Set the TEM P switch at 300 and readjust the TA HI GAIN potentiom eter for a reading of 3000
mV on the tester DVM. Repeat steps 4 and 5 until 500 mV and 3000 mV readings are
17
obtained.
6. Set the TEM P switch at 13 and adjust the TA LO GAIN potentiometer for 130 mV on the
tester DVM.
7. Set the TEM P switch at 18 and readjust the TA LO GAIN potentiometer for 180 mV on the
tester DVM. Repeat steps 6 and 7 until 130 mV and 180 mV readings are obtained.
8. Repeat steps 1 through 7 for the TB circuit.
18
ASENSOR
TPl
R86
10.OK \'/.
UK
0—
MON OUT
M METER(0-l
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< T A OUT TJ2
D TAOUT
mA)
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R78
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EXT. MON.
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+15
1.
2.
3.
4.
5.
6.
7.
NOTES
UI.U2.U8 - TL084BCN
U3-LM393AN
U4-AD75I2DIKN
U5-U6-0PI0CY
U7 -AD58IJH
ALL CAPS. ARE 50V UNLESS NOTED OTHERWISE.
ALL RES. AS FOLLOWS UNLESS NOTED OTHERWISE.
I/. 1/8 WATT
5'/. 1/4 WATT
I-&t, C».i^oe?>5
c o a co o iv ^ -o T
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FRONT ENDS
C O -84-0617-3.0
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ASTRONOMY
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DESCRIPTION
ADD TEMP SENSOR HOLES
CHG ORDER 8 7 0 2 1 8 -5
PETENCIN REVISED AND REDRAWN
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SOCKET. 8 -P IN
57
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MOTOROLA
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TL084CN
1C. 14-PIN
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51
T F -T P 4
TURRET. TEST POINT
4
50
KEYSTONE
1 5 6 2 -2
TEST JACK. BLACK
1
TJ7
49
TEST JACK. GREEN
1
48
TJ6
TEST JACK. GRAY
1
47
TJ5
TEST JACK. ORANGE
1
46
TJ3
TEST JACK. RED
1
45
TJ2
44
TEST JACK. WHITE
2
TJ1.TJ3
43
R 8 0 -R 8 2 ALLEN-BRADLEY RC07GF243J RESISTOR.24K. 1/4W.5X 3
RN55C1003F RESISTOR.100K.1/8W.1%
4
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R52.R73 ALLEN-BRADLEY RC07GF223J RESISTOR.22K.1 /4W.5X 2
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40
R49.R70 DALE
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39
RN55C3653F RESIST0R.356K.1 /8W.1X
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2
RN55C2943F RESIST0R.294K. 1/8W. 1X
37
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1
29
R22
519
ALLEN-BRADLEY RC07GF101J
RESISTOR. 100.1 / 4W.5X 4
28
fli
RNC55C1002F RESISTOR. 10K. 1/8W.1X 7
27
DALE
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RESIST0R.2K.1 /4W.5X
5
26
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RN55C4752F RESIST0R.47.5K. 1/8W. 1X
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4
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15
0 3.04
MOTOROLA
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7
KEMET
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C330C104U5U5CA CAPACITOR.. 1uf.50V
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1
1
NRAO
D53200Q002 BOARD. CIRCUIT
ITEM NO. REF. DES. MANUFACTURER PART NUMBER
DESCRIPTION
QTY
UNLESS OTHERWISE SPEOfltO
N ATIO N AL RADIO
DIMENSIONS ARE IN INCHES
ASTRON OM Y .
COMMON FRONT END
.005
O B SERVATORY
B
rnWE
wBtZi
COMPONENT SIDE
SOCORRO. NEW MDjjCO 87801
ACAD : 53200A03
D53200S002
D53200Q002
D532Q0P002
D53200I013
■SCHEMATIC
D53200IQQ7
■SOLDER MASK
NEXT ASSEMBLY
A
RTW
QRK.
DRILL DWG
.SILKSCBELN.
DWG. TYPE
I
MATERIAL :
FINISH
k
FRONT END
SENSOR PCB
A S SEM B LY____________________
1 or 1 1SS5P D 53200A003
ISCALE
2/1
2.8 Bias Card Description
The dewar RCP and LCP amplifiers each use three HEMT (high electron mobility transistor)
GASFET amplifiers. The amplifier's RF gain and noise performance can be optimized by providing each
HEMT stage an empirically-determined, optimum pair of DC drain voltage and DC drain current values.
The amplifier stages are AC-coupled; therefore, each stage can have a distinct DC drain voltage and
current. The FET Bias Card performs two functions: 1) it provides the optimal HEMT drain voltages and
2) it controls the gate voltages to maintain the optimal drain currents.
During the test phase of F I05 fabrication, optimum VD and ID values at both 15 °K and 300 °K
temperatures are determined. These values and the resultant VG are recorded on an amplifier data sheet
for future reference. Appendix I, sheet 5 (in TR 3) is a copy of the F105, dewar S/N 501 data sheet.
These data sheets are maintained in the AOC Front-End Laboratory file and the VG values are entered
into the VLA and VLBA Data Checker programs for fault monitoring. In order to permit replacement
of FET Bias Cards without adjustment, all new or spare cards are adjusted to produce a VD of +3 volts
and an ID of 1 mA; these values should enable the HEMT to function until the optimum settings are
determined.
Each FET Bias Card contains four identical sets of bias control circuits. Since the F I05 uses three
HEMTs in each channel, two FET Bias Cards are used, one card for each channel. The RCP bias card
is installed in slot 4 and the LCP bias card is installed in slot 5. Each card has an unused bias circuit that
is wired to the dewar DC Feedthrough panel for potential future use. The spare bias circuit is thus
immediately available in the event that a future dewar amplifier requires a fourth HEMT stage. Dewar
ground is the return for these sixteen signals. Block Diagram C53205K002 shows the Bias Card-Dewar
wiring connections and D53200S001 is the Bias Card Schematic. D53200A002 is the Bias Card assembly
drawing.
Each bias circuit has a HEMT drain voltage (VD) and drain current (ID), adjustment potentiometer
accessible on the edge of the card. HEMT sources are connected to dewar ground.
All four VD voltages can be measured on card-edge test jacks but cannot be measured by the
DVM or the Monitor and Control System.
All four drain currents (ID) can be measured as voltages on card-edge test jacks. The ID voltage
scaling factor is 1 mA/100 mV. The drain currents cannot be measured by the DVM or by the Monitor
and Control System.
All four gate voltages (VG) can be measured on card-edge test jacks. The first stage VG can also
be measured by the M onitor Card DVM (with the selector switch S2 in the LF1 and RF1 positions) and
by the Monitor and Control System via J2-7 (RF1 signal) and J2-9 (LF1 signal). Second and third stage
VG voltages cannot be individually measured by the DVM or Monitor and Control System but a
composite form of these two VG signals can be measured. Note that the block diagram shows that the
stage 2 and 3 VG m onitor signals on pins 5 and 6 are connected together and to the DVM selector switch
S2. This connection sums the two signals and the composite signal level is intermediate between the VG2
and VG3 levels. The DVM measures the composite VG signals in selector switch positions LF2 and RF2.
These two composite VG signals are also connected to J2-8 (RF2) and J2-10 (LF2) for readout by the
Monitor and Control System. Since the composite VG readout level is the sum of the stage 2 and stage
19
3 VG levels, its level will differ from the actual VG2 and VG3 levels and its level will be approximately
intermediate between the two. It is important to remember this VG monitoring configuration when
comparing the am plifier S/N data sheet VG2 and VG 3 values (e.g., TR 3 Appendix I, Sheet 5
example values) with the composite VG values read w jf as RF2 and LF2.
The normal range o f VG is between 0 and -1 volts and is a function o f temperature with a typical
change o f 100 to 300 mV from 300 ° K to 15 °K . A t 15 ° K the V G value should be within ±20 mV o f
the data sheet value. An open in the drain circuit will force the measured V G to the VG bias amplifier's
positive limit, about +13.5 volts. In this condition, the forward gate current is limited to about 7 mA by
a series resistor. A short in the drain or gate circuit (perhaps the result o f insulation cold-flow on a dewar
wire) will force the measured V G to the amplifier's negative limit, about -13.5 volts. In this condition,
the actual H EM T gate voltage is limited to about -5 volts by the 1N821 protection diode.
Consider the first FET bias stage in the upper left quarter o f D53200S001. Mentally picture the
associated H EM T stage with the source connected to DC (dewar) ground, the gate connected to pin H
(V G ), and the drain connected to pin N (VD ). Also assume that both the gate RF input and drain RF
output are AC-coupled.
The bias circuit consists o f a set o f four interconnected operational amplifiers U1 (a TL084BCN
quad operational amplifier) and a transistor Q1 (2N2219). The circuit descripton can be simplified if it
is considered to consist o f three sub-circuits: a VD driver circuit (U l-1 , Q1 and Ul-14), an ID sense
circuit (U l-8 ), and a VG driver circuit (U l-7). The VD driver and ID sense circuit are described first
because the VG driver circuit is a control loop that is dependent upon the outputs o f the VD driver and
ID sense circuits.
The bias circuit's first function is to set the V D voltage; this is the function o f the VD driver,
which consists o f Ul-1 and transistor Q1 (2N2219). This circuit is a voltage follower (noninverting
operational amplifier with a gain o f 1) with a Q1 emitter follower included in the feedback loop.
Potentiometer R 14 is the V D set point adjustment and provides a DC bias to U l-2, the + input. Since Q1
is inside the follower loop, U l's output is Q1 's V BE drop above the VD 1 set point so the V D level is that
set on R u. Diode CR1 is a protective diode across Q l's emitter-base junction. The diode protects Q1 in
the event that the Ul-14 output ever swings negative (perhaps due to an accidental short while probing
the board with a D VM , etc.). CR2 has a zenar voltage o f 6.8 volts to protect the HEM T drain in the event
o f some malfunction or open in the operational amplifier circuit. U l-14 is a voltage follower used to
isolate the drain from the VD1 test jack, TJ13. It also drives the ID sense circuit. R b the 2 kQ series
resistor between Ul-14 and the VD1 test jack, protects Ul-14 in the event that TJ13 is inadvertantly
shorted to ground. Finally, Q , a 1.0 }iF capacitor filters the driver circuit's DC bias value to keep the
output noise free.
The ID sense circuit consists o f Ul-14, a voltage follower and U l-8, a differential amplifier.
H E M T drain current flows from the +15 volt power source through Q l, through R g (200 Q), out pin N
to the H E M T drain, and through the H EM T to dewar ground. ID is sensed as a voltage drop across R8
and amplified by differential amplifier Ul-8, which has a gain o f 0.5. U l-8 is a differential amplifier
because VD1 is a common-mode voltage on both Ul-8's inputs. U l-8's output is scaled at 100 mV per
mA o f ID current. 2 kQ resistor R2isolates Ul-8's output from TJ12 in the event o f an inadvertani short
to ground.
The second function o f the FET bias circuit is to control VG so that ID is a constant, preset value;
20
this is done by the VG drive circuit that closes the loop on ID. The VG driver consists o f U l-7 with two
summing junction (U l-6 ) inputs: 1) a positive ID current input from U l-8 and 2) a negative offset
current flowing to R 15, the ID1 adjustment potentiometer. Ul-8's output is a positive voltage that is an
analog o f ID and is scaled at 100 mV/mA. A current proportional to this voltage is input to the U l-7
summing junction (the - input) via R7, 100 kQ. When the loop is closed, the ID current into U l-6 is
equal to the offset current through R 12, and the op-amp's output U l-7 is proportional to the offset current
through R 12. Although it's not obvious, the H E M Ts drain-source impedance is a factor in the feedback
path.
Tw o DC reference voltages are used by the bias circuits: -10 volts and +6 volts, derived from a
pair o f AD581JH +10 volt precision reference voltage sources. Four 10 kQ V D adjustment pots are
connected in parallel and to resistor R^, 1.5 kQ, which drops four volts to produce the +6 volts for the
VD adjustment potentiometers. Data sheets for the AD581JH and TL084BCN are included in Section 4.
The 6 volt relay circuit on the right side o f the schematic diagram is not used.
The FET Bias Card is tested on a Bias Card Tester that contains + and - 15 volt power supplies
and four FETs with characteristics similar to cooled GASFETs. The card is plugged into the tester and
a D V M is plugged into the card's ground (TJ1), VD, ID and VG test jacks. The four sets o f VD and ID
potentiometers are adjusted to produce a VD o f +3 volts, an ID o f 1 mA, and V G is measured to verify
that it is about -400 mV with these VD and ID values.
21
22
D
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NOTES
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TL084B C N
0 U 5 - 6 AD58IJH
S ALL CAPS. ARE 50V UNLESS OTHERWISE MARKED.
® ALL RES. AS FOLLOWS;
57.
1/4 WATT
17. 1/8 WATT
® SEE CR3 FOR FOR INTERNAL SCHEMATIC.
(6) KI-MAGNECRAFT WI 7IDIP-I 4
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REPRESENTS AMPLIFIED
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R
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DESCRIPTION
1
2
3
4
5
6
7
8
»
10
11
12
13
14
1
2
3
4
S
6
7
8
9
10
11
12
13
1
1
2
3
4
1
2
3
4
S
6
7
8
9
10
11
12
13
14
15
1C
17
11
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
3<
37
38
39
40
41
42
43
44
45
4(
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
1
2
3
4
5
6
7
CAP. O .lu f 50v
CAP. l.O u f 50v
CAP. O .lu f 50v
CAP. l.O u f 50v
CAP. O .lu f 50v
CAP. l.O u f 50v
CAP. O .lu f 50v
CAP. l.O u f 50v
CAP. 15uf 20v taint.
CAP. 15uf 20v t » n t .
CAP. l.O u f 50v
CAP. l.O u f 50v
CAP. l.O u f 50v
CAP. l.O u f 50v
DIODE 1N914
DIODE 1N40 99
DIODE 1N821
DIODE 1N914
DIODE 1N4099
DIODE 1N821
DIODE 1N914
DIODE 1N4099
DIODE 1N821
DIODE 1N914
DIODE 1N4099
DIODE 1N821
DIODE 1N914
SPST REED RELAY
TRAM. 2N2219
TRJH. 2N2219
TRAN. 2N2219
V A N . 2N2219
RES. 2K 1/4W 5%
RES. 2K 1/4W 5*
RES. 2K 1/4H 5%
RES. 100 1/4W 5*
RES. 4 9 .9K 1/8W I t
RES. 100K 1/8W 1%
RES. 100K 1/8W i%
ICS. 2 0 0 i / m I t
RES. 100* 1/8W I t
RES. 4 9 .»K 1/8W I t
RES. IK 1/4W St
RES. 33 2* 1/8W I t
RES. 100K 1/4M 5t
TRIM POT 10* 15T
TRIM POT 10* 1ST
RES. 2K 1/4W 5t
RES. 2K 1/4W 5t
RES. 2K 1/4W St
RES. 100 1/4H 5t
RES. 49.9K 1/8W i t
RES. 100K 1/8W I t
RES. 100K 1/8H I t
RES. 200 V8W I t
RES. 100K 1/8H I t
RES. 4 9 .9K 1/8W I t
RES. IK 1/4W 5t
RES. 332K 1/8W I t
RES. 100K 1/4H St
TRIM POT 10K 15T
TRIM POT 10K 15T
RES. 2K 1/4H St
RES. 2K 1 / 4W 5t
RES. 2K 1 / 4 W St
RES. 100 1/4W St
RES. 4 9 .9K 1/8W I t
RES. 10 OK 1 / 8 W I t
RES. 100K 1/8W I t
RES. 200 1/8W I t
RES. 100K 1/8W I t
RES. 49.9K 1/8W I t
RES. IK 1/4W St
RES. 33 2K 1/8W I t
RES. 100K 1/4W St
TRIM POT 10K 1ST
TRIM POT 10K 1ST
RES. 2K 1/4W 5t
RES. 2K 1/4W 5t
RES. 2K 1/4W 5t
RES. 100 1/4W 5t
RES. 49.9K 1/8W I t
RES. 100K 1/8W I t
RES. 100K 1/8W 1«
RES. 200 1/8W I t
RES. 10OK 1/8W I t
RES. 4 9 .9K 1/8W I t
RES. IK 1/4W 5t
RES. 332K 1/8W I t
RES. 100K 1/4H St
TRIM POT 10K 1ST
TRIM POT 10* 15T
RES. 4*70 1/4W 5t
RES. l.S K 1/8W I t
RES. 2 40 1/4W St
RES. 5K 1/4W 5t
RES. 5K 1/4W St
RES. SK 1/4W 5t
RES. 5X 1/4W 5t
TEST JACK BLACK
TEST JACK WHITE
TEST JACK BROWN
TEST JACK GREEN
IS ST JACK WHITE
TEST JACK BRCWN
TEST JACK GREEN
8 TEST JACK WHITE
9 TEST JACK BROWN
10 TEST JACK GREEN
11 TEST JACK WHITE
12 TEST JACK BRCWN
13 TEST JACK GREEN
1 IC TL084BCN
2 IC TL084BCN
3 IC TL084BCN
4 IC TL084 BQi
5 IC ADS81JH
6 IC AD581JH
PART
NUMBER
C330C104M5USCA
C330C105M5U5CA
C33 0C104H5U5CA
C33UClu5M5U5CA
C330C104M5USCA
C330C105M5U5CA
C33 0C104M5U5CA
C330C105M5U5CA
CSR13E156KP
C5R13E1 56KP
C330C105M5 USCA
C330C105M5U5CA
C3J0C105M5U5CA
C330C105M5U5CA
1N914
1N40 99
1N821
1N914
1N4099
1N821
1N914
1H4099
1N821
1N914
1 N4099
1N821
1N914
W171DIP-14
2N2219
2N2219
2N2219
2N2219
RC07GF202J
RC07GF202J
RC07GF202J
RC07GF101J
RN55C4992F
RN55C1003F
RN55C1003F
RN55C2000F
RN55C1003F
RM5SC4992F
RC07GF102J
RN55C3323F
RC07CF104J
CERMET 30U4P 1UK
CERMET 3006P 10*
RC07GF202J
RC07GF202J
RC07GF202J
RC07GF101J
RN5SC4992F
RK5C1003F
RNS5C1003F
RN5SC2000F
RN55C10UJF
RN55C4 992F
RC07GF102J
RI65C3323F
RC07GF104J
CERMET 3006P 10K
CERMET 3UU6P 1UK
RC07GF202J
RC07GF20 2J
RC07GF202J
RC07GF101J
RN55C4992F
RN55C1003F
RI65C1003F
R165C20U0F
RI6SC1003F
RN55C4 992F
RC07GF102J
RN55C3323F
RC07GF104J
CERMET 30U6P 1UK
CERMET 3006P 10K
RC07GF202J
RC07GF202J
RC07GF202J
RC07GF101J
RN55C4 992F
RN55C1003P
RN55C10U3F
RNS5C2000F
RNS5C10U3F
RN55C499 2F
RC07GF102J
RN55C3323F
RC07GF10 4J
CERMET 3006P 10*
CERMET 30U6P 10*
RC07GF4H3
RN55C1301F
RC07GF241J
RC07GF5U2J
RC07GF502J
RC07GF502J
RC07GF502J
105-07 53-001
105-0751-001
105-0758-001
105-0754-001
10S-07 51-001
105-0758-001
105-07 54-001
105-07 51-001
105-07 58-001
105-0754-001
105-07 51-001
105-0758-001
105-0754-001
TL0 84BCN
TL084BCN
TL0 84BCN
TL084BCN
ADS SUB
AD5H1JH
ITEM#
5
6
5
6
5
6
5
6
7
7
6
6
6
6
8
9
10
8
9
10
8
9
10
8
9
10
8
30
24
24
24
24
18
18
18
13
19
20
20
14
20
19
15
22
21
23
23
18
18
18
13
19
20
20
14
20
19
15
22
21
23
23
18
18
18
13
19
20
20
14
20
19
15
22
21
23
23
18
18
18
13
19
20
20
14
20
19
15
22
21
23
23
16
1/
31
32
32
32
32
25
28
27
26
2V
27
26
28
27
26
28
27
26
11
11
11
11
12
12
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2.9 R F C ard Description
The RF Card is installed in card slot 1 and performs the room-temperature amplification, bandpass
filtering, calibration and 300 ° K temperature measurement functions shown on the F105 Block Diagram
C53205K001, page 2 (in T R 3). These are: amplification o f the LC P and RCP signals from the cooled
amplifiers in the dewar, the generation o f low and high noise calibration signals, injection o f a phase
calibration signal, and measurement o f the RF Card temperature.
The RF Card Assembly drawing is A53205A005 and is shown on T R 3 Appendix pages II-9
through 11-11. The associated BOM is A53205B005 and Appendix page 11-12 lists the RF Card
components. Although an RF Card schematic, (?)53205S002 is listed in the RF Card BOM, A53205B005,
it does not exist.
The F I05 Block Diagram and RF Card Assembly drawings show a High Calibration noise source
as an optional F I 05 feature. Although it may not be installed in all FI05s, provisions have been made
for its installation.
Block Diagram C53205K002 shows the RF Card functions in the context o f this addendum's
description. Since the emphasis o f this addendum is on the theory o f operation o f the card cage circuitry,
the RF Card functions are not described here. Refer to TR 3 pages 32 and 36 for a description o f the RF
Card's noise calibration circuitry. The room temperature post amplifiers are described in specification
A53205N001 (not part o f this manual). The specifications on pages 5 through 8 encompass the RF Card's
performance.
The RF Card has a National Semiconductor LM335Z Precision Temperature Sensor to measure
the plate's temperature. The sensor output is designated 300 ° K and connected to the Monitor Card for
measurement by the D V M and to the Monitor and Control System via J2-5. The LM335 operates as a
two-terminal zenar and has a breakdown voltage directly proportional to absolute temperature with a
scaling o f +10 mV/°K. Section 4 contains a LM335Z data sheet.
2.10 D ew ar D C Interface Description
The DC Feedthrough is the interface for the connection o f DC power and H E M T bias lines to the
dewar RF amplifiers, A C power to the heater, and signal lines to temperature sensing diodes, and the LED
circuitry. The DC Feedthrough cable assembly B53206A012, is shown on Appendix page 11-26, in T R
3. Wire list A53206W001 does not include the wiring between the card cage J3 and the DC Feedthrough.
This wiring is shown on C53205K002, the 4.8 GHz FE Block Diagram.
The B53206A012 dewar DC Feedthrough is a hermetically-sealed interface panel that uses RFI
feedthrough terminals soldered into a brass plate attached to the dewar inspection cover. Feedthrough
terminal designations are shown on the artwork o f a printed circuit board installed on the outside o f the
feedthrough. These designations are those used in C53205K002. Figure 4 on the next page shows the
PC board terminal designations.
The sixteen H EM T drain (V D ) and gate (V G ) bias lines pass through the DC Feedthrough and
are connected to the dewar amplifiers via two small 7-pin Micro-Tech connectors. Since the emphasis
o f this report is the card cage circuitry, for simplicity, these connectors are not shown on the block
diagram. The H E M T source lines are connected to dewar ground.
23
The 15 ° K stage temperature sensor diode (T S A ) is
connected to terminals A + and A-.
The diode anode is
connected to A + and the cathode to A-. Similarly, the 50 ° K
stage temperature sensor diode (TSB ) anode and cathode are
connected to terminals B+ and B-.
H E M T sources and the ground end of the LED circuits
are connected to J3-21, Dewar Ground. The dewar ground
line is also connected to the dewar internal metal structure.
A s shown on C53205K002, the dewar LEDs circuit
consists o f two series strings, each consisting o f three LEDs
and a 300 Q limiting resistor. The bottom o f the strings are
connected to dewar ground and the tops are connected to
terminal X I. Outside the dewar, X I is connected to P3-22.
J3-22 is connected to pin T on the Monitor Card, the LED
monitor input for the DVM . A 510 Q limiting resistor is
connected between pin T and Pin X. Pin X is not connected
to any Monitor Card circuitry and simply serves as a convenient mounting terminal for the resistor. Pin
X is jumpered to Pin 2 and B, the +15 volt bus. This resistor is shown on the Card Cage Assembly
Drawing, D53206A005, Appendix page 11-19, (in TR 3). The typical F105 LED monitor voltage is +5.0
volts but it can range between +4.5 to +5.5 volts. If one o f the LED strings opens, the LED monitor
voltage is +11 volts and if both open, the monitor readout is +15 volts. This value can be read on the
D V M but will be full-scale in the Monitor and Control system readout because it exceeds the working
range o f the Standard Interface Board's A/D converter in FI 17.
The dewar heater A C power is connected to terminals H I and H2.
terminals are connected to two 750 Q, 75 watt, 240 volt heaters.
Inside the dewar, these
2.11 A C Circuitry Description
The dewar's cryogenic functions are powered by two-phase, 150 volts A C power. Figure 1.3-3
on page 20 (in T R 3) shows the Front-End's A C wiring. Page 18 lists the cryogenic function's A C loads.
Because the F105 A C power is peculiar to the refrigerator's requirements, it does not have an internal DC
power supply for the card cage circuitry. DC + and - 15 volt power is provided by the control interface
via J5. This DC power is described in Section 2.15.
Note that the 150 volt, two-phase power is supplied by a Model P i l l power supply, which is
described in 2.9, page 36 (in T R 3). Figure 2.9-1, page 38, shows the power supply schematic. An
important P i l l power supply output is the A C current monitor, which is a DC signal scaled at 10
amperes/volt. This is input to the Front-End on J4-1 (signal) and J4-2 (return) and the signal polarity is
positive. This signal, designated AC I, is connected to the Monitor Panel for D V M measurement and to
J2-6 for readout by the Monitor and Control System.
On page 20, note the vacuum solenoid current limiting resistor R ls 300 Q, 20 watts, which is
installed on the card cage connector mounting plate. This resistor is pictured in the card cage assembly
drawing, D53206A005, Appendix page 11-19 (in T R 3). If the vacuum solenoid is actuated for a long
time, the plate will become quite hot from the resistor's power dissipation. Also note that a stuck vacuum
24
solenoid will draw 0.40 amperes. The dewar heater limiter resistor R2 5 kQ, 10 watts, is also installed
on the card cage connector mounting plate; it too is pictured on the card cage assembly drawing.
The cryogenic control equations were described in Section 2.4 and Section 2.5, (Control Card)
described the implementation o f the control equations. Note that the R, S, H and X contacts shown on
the Front-End Wiring schematic (Figure 1.3-3, T R 3 page 20) are the Control Card relay contacts.
The dewar heater is two 750 Q, 75 watt, 240 volt Hotwatt heaters installed on the 15 °K stage.
Heater current is 0.45 amperes and dissipation is 60 watts. Note from the Front-End A C wiring schematic
on page 20 that the heater has an internal thermostat that opens at a high temperature level. This feature
prevents overheating in the event o f a Control Card failure.
2.12 D V M Readout Values and Tolerances
The table below shows the D V M analog selector switch position Label, Function, Scaling, Normal
Value and acceptable Tolerance Range.
DVM S2 Label
Function
1 volt =
+10.0002
+9.950 to +10.000
VP
Pump Vacuum
VD
Dewar Vacuum^
0.000
-0.200 to +0.200
15K
15 °K Stage
+0.150
+0.100 to +0.200
50K
50 °K Stage
+0.550
+0.400 to +0.700
300K
300 °K Station
o
o
Tolerance Range
o
o
Normal Value
O
o
i
+2.900
+2.000 to +3.000
AC CURR
AC Current^
10 Amps
RF 1
RCP Gate 1
1 Volt
-0.604
-1.00 to +1.00
RF2
RCP Gates 2+35
1 Volt
-0.604
-1.00 to +1.00
L F1
LCP Gate 1
1 Volt
-0.604
-1.00 to +1.00
LF2
LCP Gates 2+35
1 Volt
-0.604
-1.00 to +1.00
LED
LED Voltage
1 Volt
+5.06
+4.500 to +5.500
EXT
Spare Mon
1 Volt
N/A
Notes:
1
Nonlinear vacuum readout scale, see page 17 in TR 3.
2
Readout when pump manifold is at sea level atmospheric pressure.
3
AC current depends upon cryogenic state, see page 18 in TR 3.
4
Typical value.
5
Approximate sum of Stage 2 and 3 Gate voltages.
6
If one LED string opens, the LED readout voltage is about +11 volts; if both strings open, the LED readout
is +15 volts.
Large changes indicate a dewar amplifier problem.
25
2.13 M onitor and Control System Readout Values
The Telescope Operator Front-End Cryogenic and Electronics displays show F I05 status; Figures
5 and 6 are similar to these displays. Figure 5 shows the calibration mode, monitored calibration current
and voltage, and the three HEMT gate bias voltages. Figure 6 shows the commanded cryogenics mode,
monitored mode, state, discretes, and selected analog monitor values.
____________ ______ _
F R O N T END C R Y O G E N IC S 6CM
C M D CO O L M A N U A L S T A T E COOL
A C 1 0.43
P U M P R E Q OFF
15K 15.6
V A L V E CLOSED
50K 22.5
P U M P V A C 9846
300K 307
DEW AR VAC 0
F R O N T END E L E C T R O N IC S 6CM
C A L M O D E LO W SW ITCHING
C A L I 5.86 V 27.823 H E M T 4.75
GRD -0.010
7.5 V 7.500
R T FET#1 -0.337
L F FET#1 -0.415
R T FET#2 -0.752
L F FET#2 -1.006
Figure 5 V L B A F I 05 Electronics Screen
Figure 6 V L B A F I05 Cryogenics Screen
The V L B A control interface is FI 17. It controls F105, reads F105 discretes, and converts F105
analog signals to digital values for input to the Antenna control computer via the Monitor and Control bus.
The first V L B A screen shows that the calibration level is LO W and is SW ITCHING. FI 17
measures some additional Front-End analog parameters: (C A L I) cal current, cal voltage, the FI 17 +7.5
volt reference (7.5V), and FI 17 ground reference (GRD). The example values show a calibration current
o f 5.86 mA and a cal voltage of 27.832 volts. The HEM T 4.75 voltage is the LED measurement
described in Section 2.10. The FET voltages are the Bias Card HEM T gate voltages described in Section
2 . 8.
The second V L B A screen shows that the Front-End is commanded to the COOL state, is in the
M A N U A L mode, and the X, C and H monitor discretes show the CO O L state. The PUM P REQ(uest)
is OFF and the (vacuum) V A L V E is CLOSED. The 150 volt A C current load is 0.43 amperes. PUM P
(V P ) V A C is 9846 because the vacuum manifold is at the antenna's atmospheric pressure (see the vacuum
vs. monitor voltage curve on TR 3 page 17). DEW AR VAC(uum) is 0 |im (or less than 1 fim. Note that
this value has been converted from the voltage readout value to the corresponding vacuum level. The 15K
(T A ), 50K (TB ), and 300K temperatures are shown degrees Kelvin. The SENS temperature (non-linear
form o f T A ) is not shown.
If F I 05 is installed on the V L A , the control interface would probably be F I4.
26
2.14 Band, Serial N um ber, and Modification Level Encoding
F I05 has provisions to identify its serial number, frequency band and modification level as hard­
wired binary codes on the J5 connector. These codes are implemented by connecting the appropriate J5
pins to ground lugs near the connector. Grounded pins are 0's and floating pins are l's. The control
interfaces (such as F I 4, V L A or F I 17, V L B A ) have pull-up resistors to +5 volts for input to T T L logic.
Drawing C53205K002 shows the code bit assignments on J5.
The F105 band code is 4H and the associated parity bit is a 1. Page 15 in T R 3, describes the
band, serial number and modification level encoding.
2.15 Front-End D C power and Quality Ground
The F105 card cage DC power is + and - 15 volts from J5, provided by the associated control
interface, FI 17. The -15 volt power demand is 100 mA and the +15 volt power demand is 500 mA. The
+ 15 volt current demand is dependent upon F105's cryogenic state. The Control and Monitor card's LST T L logic is powered by on-card +5 volt regulators from +15 volt inputs.
Bus-bars running through the card cage PC board connectors (including spare card slot 2) provide
+ 15 and -15 and power from J5-2 (+15) and J5-3 (-15), respectively. Like some other VLBA-style FrontEnds, the F105 has protective 1N5355A 18 volt zenar diodes installed in the card cage +15 and -15 volt
bus bars. The Ground bus bar is connected to chassis ground at slot 1, the RF Card Card. DC power
distribution is shown in C53205K002.
Quality Ground is an analog ground reference that does not carry power currents. This reference
is supplied to the Monitor Panel D V M and to the control interface via J2-13. The Quality Ground is
connected to chassis ground lugs GL2 and GL6, near the RF Card connector, slot 1. The Quality Ground
string is shown on C53205K002.
Dewar ground on J3-21 is connected to GL6 and also to the dewar internal metal structure. This
is the return path for the H EM T sources and the LED strings.
Note that Table II, page 13 (in TR 3) shows that J5-13 is a ground pin. This pin is floating as
shown on the card cage wire list A53206W001, Sheet 12, T R 3 Appendix page 11-41.
27
28
3.0 R E L E V A N T N R A O D R A W IN G S
Title:
Number:
Notes:
4.8 GHz FE Block Diagram C53205K002
System Block Diagram
Front-End Assembly
Front-End BOM
C53205K001
D53205A001
A53205B001
TR 3 Appendix page 11 -1
TR 3 Appendix page 11-2
Card Cage Assembly*
Card Cage BOM*
Card Cage Wire List*
D53206A005
A53206B005
A53206U001
TR 3 Appendix page 11-19
TR 3 Appendix page 11-20
TR 3 Appendix page 11-30
RF Card Assembly
RF Card BOM
C53205A005
A53205B005
TR 3 Appendix page 11 -9
TR 3 Appendix page 11-12
Sensor Card Schematic
Sensor Card Assembly
Sensor Card BOM
D53200S002
D53200A003
Control Card Schematic
Control Card Assembly
Control Card BOM
D53200S002
D53200A004
A53200B004
Monitor Card Schematic
Monitor Card Assembly
Monitor Card BOM
C53200S005
D53200A006
A53200B006
FET Bias Card Schematic
FET Bias Card Assembly
FET Bias Card BOM
D53200S001
D53200S002
A53200B002
No BOM, parts are on the
* These are F106 drawings.
29
30
4.0 C O M P O N E N T D A T A SHEETS
Data sheets for:
Lake Shore Cryotronics DT-500
Hastings DV-6R
Hastings DB-20
Texas Instruments TL084
Texmate PM-45XU
Analog Devices AD581JH
National Semiconductor LM339N
Texas Instruments 75452
Teledyne 643-1
Teledyne 645-2
National Semiconductor LM 393AN
Analog Devices AD7512DIKN
National Semiconductor LM335Z
Precision Monolithics OP-IOCY
31
32
Standard Curve 10: M easu rem en t Current = 10 jiA ±0.05°/
DT-500-DRC (B ) V o l t a g e - T e m p e r a tu r e C h a r a c t e r i s t i c
d V /d T
(m V /K )
T
(K)
d V /d T
(m V /K )
T
(K)
V o lta g e
d V /d T
(m V /K )
1.40
1.60
1.80
2.00
2.20
1.69812
1.69521
1.69177
1.68786
1.68352
-13.1
-15 9
-18.4
-20.7
-22.7
16.0
16.5
17.0
175
18.0
1.28527
1.27607
1.26702
1.25810
1.24928
•18.6
-18.2
-18.0
-17.7
-17.6
95.0
100.0
110.0
120.0
130.0
0.98564
0.97550
0.95487
0.93383
0.91243
-2.02
-2.04
-2.08
-2.12
-2.16
2 40
2.60
2.80
3.00
3.20
1.67880
1 67376
1.66845
1.66292
1.65721
-24.4
-25.9
-27.1
-28.1
-29.0
18.5
19.0
19.5
20.0
21.0
1.24053
1.23184
1.22314
1.21440
1.19645
-17.4
-17.4
-17.4
-17.6
-18.5
140.0
150.0
160.0
170.0
180.0
0.89072
0.86873
0.84650
0.82404
0.80138
-2.19
-2.21
-2.24
-2.28
-2.28
3.40
3.60
3.80
4.00
4 20
1.65134
1.64529
1.63905
1 63263
1.62602
-29.8
-30.7
-31.6
-32.7
-33.6
22.0
23.0
2 40
25.0
26.0
1.17705
1.15558
1.13598
1.12463
1.11896
-20.6
-21.7
•15.9
-7.72
-43 4
190.0
200i)
210.0
220.0
230.0
0.77855
0.75554
0.73238
0.70908
0.68564
-2.29
-231
-2 3 2
-2.34
-2.35
4.40
4.60
4.80
5.00
5.50
1.61920
1.61220
1.60506
1.59782
1.57928
-346
-35.4
-36.0
-36.5
-37.6
27.0
28.0
29.0
30.0
32.0
1.11517
1.11212
1.10945
1.10702
1.10263
-3.34
-2.82
-2.53
-2.34
-2.08
240.0
250.0
260.0
270.0
280.0
0.66208
0.63841
0.61465
0.59080
0.56690
-2 3 6
-2 3 7
-2 3 8
-2 3 9
-2.39
6.00
6.50
7.00
7.50
8.00
1.56027
1.54097
1.52166
1 50272
1.48443
-38.4
-38.7
-38.4
-37.3
-35.8
34.0
36.0
38.0
40.0
42.0
1.09864
1.09490
1.09131
1.08781
1.08436
-1.92
-1.83
-1.77
-1.74
-1.72
290.0
300.0
310J)
320.0
330.0
0.54294
0.51892
0.49484
0.47069
0.44647
-2.40
-2.40
-2.41
-2.42
-2.42
8.50
900
9.50
10.0
10.5
1.46700
1.45048
1 43488
1.42013
1.40615
-34.0
-32.1
-30.3
-28.7
-27 2
44.0
46.0
48.0
50.0
52.0
1.08093
1.07748
1.07402
1.07053
1.06700
-1.72
-1.73
-1.74
-1.75
-1.77
340.0
350.0
360.0
370J)
380J)
0.42221
0.39783
037337
034881
032416
-2.43
-2.44
-2.45
-2.46
-2.47
11.0
11.5
12.0
12.5
13.0
1.39287
1.38021
1.36809
1.35647
1.34530
-25.9
-24.8
-23.7
-22.8
-21.9
54.0
56.0
58.0
60.0
65.0
1.06346
1.05988
1.05629
1.05267
1.04353
•1.78
•1.79
-1.80
-1.81
-1.84
390.0
400.0
410.0
420.0
430.0
0.29941
0.27456
0.24963
0.22463
0.19961
-2 m
13.5
14.0
14.5
15.0
15.5
1.33453
1.32412
1.31403
1.30422
1.29464
-21.2
-20.5
-19.9
-19.4
-18.9
70.0
75.0
80.0
85.0
90.0
1.03425
1.02482
1.01525
1.00552
0.99565
-1.87
•1.91
•1.93
-1.96
-1.99
440.0
450.0
460.0
470.0
475.0
0.17464
0.14985
0.12547
0.10191
0.09062
-2.49
-2.46
-2.41
-2.30
-2.22
T
(K)
V o lta g e
V o lta g e
T, K e lv in
-2.48
-2.49
-1 5 0
-2.50
Shaded portion highlights truncated portion ol Standard Curve 10 corresponding to the reduced temperature rang, of OT-471 diode sensors.
The 1.4 K to 325 K portion of Curve 10 is applicable to the QT-450 miniature silicon diode sensor.
Lake Shore Cryotronics.lnc.
64 East Walnut Street • Westerville, Ohio 43081-2399
Fax: (614) 891-1392 • Tel: (614) 891-2243
1.0
1 .5
1 .6
1.7
1. 8
1 .9
2.0
2.2
2 .A
2.6
2 .8
3 .0
3. 2
3 .A
3. 6
3.8
A. 0
A .2
A.A
A .6
A .8
5.0
5.5
6.0
6. 5
7. 0
7.5
8.0
8.5
9.0
9. 5
10 .0
11 .0
12.0
13 .0
1A.0
15 .0
16 .0
17 .0
18 .0
aeusui
V oltage
—
2.66A7
2.6622
2.6593
2.6562
2.6528
2.6A91
2.6A10
2.6321
2.6223
2.6117
2.6005
2.5886
2.5762
2.5633
2.5A99
2.5361
2.5220
2.5075
2 . A928
2.A780
2.A631
2.A25A
2.3877
2.3505
2.31A2
2. 2790
2.2A52
2.2127
2.1818
2.152A
2.12A6
2.0731
2. 0236
1.9730
1.9186
1.8561
1.79A2
1.7325
1.6651
T, K e l v i n
19 .0
2 0. 0
2 1 .0
22 .0
23 .0
2A.0
25 .0
26 .0
27.0
28.0
29 .0
30 .0
32 .0
3A.0
36 .0
38 .0
AO. 0
A5.0
50 .0
55.0
60 .0
65 .0
70.0
75 .0
80 .0
85 .0
90 .0
95 .0
10 0.0
105.0
110.0
115.0
12 0. 0
12 5. 0
130.0
135.0
1A0.0
1A5.0
150.0
155.0
oeiisui.
V oltage
1.59AA
1. 5159
1.A389
1.3575
1. 2895
1.2378
1.1955
1.16A5
1.1A3A
1.1293
1.1192
1.1115
1.1003
1.0923
1.0859
1.080A
1.0752
1.0632
1.0515
1.0397
1.0276
1.0151
1.002A
0.98933
0.97610
0.96277
0.9A939
0.93591
0.92238
0.90881
0.89520
0.88156
0.86788
0.85A12
0.8A035
0.82652
0.81265
0.79873
0.78A78
0.77081
T,
K e lvin
160. 0
165. 0
17 0.0
17 5. 0
180.0
185.0
190 .0
195.0
2 00 .0
2 05 .0
210. 0
21 5. 0
22 0. 0
225.0
230. 0
23 5.0
2A0.0
2A5.0
250.0
25 5. 0
26 0. 0
26 5. 0
270.0
27 5. 0
28 0. 0
28 5. 0
290. 0
295. 0
300.0
305.0
310. 0
315. 0
320. 0
325. 0
330. 0
335. 0
3A0.0
3A5.0
3 5 0. 0
35 5. 0
3 6 0. 0
36 5. 0
37 0. 0
37 5.0
38 0. 0
sensor
V o ltag e
0 . 75 68 0
0. 7A276
0. 72868
0.71A57
0.700A1
0.686 22
0. 67 201
0.657 77
0.6A353
0.6 2 92 8
0.6150A
0.6008A
0. 58 672
0 . 57 26 8
0 . 55 88 0
0.5A508
0.53 152
0. 51 81 0
0.50 A79
0.A9151
0.A7 818
0. A6A83
O.A5137
0. A3773
0 . A2388
0 . A0988
0.3957A
0. 38 155
0. 36 72 9
0.3529A
0.338A3
0. 32 375
0.308 93
0.29A07
0.27919
0.26A32
0.2A9A3
0.23A58
0.2197A
0. 20 500
0.190 37
0. 17 59 6
0.16 19 2
0.1A8A6
0.135 97
HASTINGS
INSTRUMENTS
:
:
•
Product
I
VACUUM GAUGE :
TUBES
:
Product Bulletin •
339
HASTINGS VACUUM
GAUGE TUBES
For Economy and Reliability in Vacuum Measurement
!
•
•
•
•
Corrosion-Resistant
Non-Contaminating
Stable Calibration
Rugged Under Demanding Conditions
Ui
^ •a m r id E '
T5J(»<GS-IUT»
Standard Metal Type
^fT E LE D Y N E
BROWN ENGINEERING
H astings Instrum ents
Design Features
Hastings Vacuum Gauge Tubes are precision sensing devices de­
signed to provide maximum accuracy in the measurement and control
of vacuum. Fully compensated tor both temperature and rate of
temperature change, the tubes are renowned worldwide for their
dependability, and boast a history of success that has endured for over
40 years.
Hastings Gauge Tubes use the rugged but sensitive, time-tested
Hastings thermopile sensor. Short, firmly connected thermocouples
have no suspended weld to an external heater.
The unique Model DV-760 uses a piezo-resistive strain gauge on a
silicon chip. The chip includes a sealed vacuum reference, a resistive
bridge circuit, and a temperature compensation network.
Hastings Gauge Tubes are color-coded for matching to the appropri­
ate vacuum gauge or controller.
CHARACTERISTICS OF HASTINGS VACUUM GAUGE TUBES
Metal Tube
DV-4D
DV-5M
DV-6M
DV-8
FT Series
DV-4R
—
DV-6R
—
Jtainlees/Ceramlc
DV-34
—
DV-36
—
Pyrex
Metal w/VCR Connection
DV-23
DV-24
DV-760
—
DV-16D
DV-18
DV-20
DV-31
DV-43
DV-44
DV-4D-VCR
DV-5M-VCR
DV-6M-VCR
—
DV-23-VCR
—
—
DV-4D-KF-16
—
DV-6M-KF-16
—
DV-23-KF-16
DV-24-KF-16
—
Best Sensitivity Range
0.2 • 5 torr
0.1 -5 mbar
2 - 20 mtorr
0.002 - .05 mbar
10 -200 mtorr
.01 - .2 mbar
0.1 • 10 mtorr
—
5 mtorr -1 torr
.01 • 2 mbar
.1 -5to rr
.1 -5 mbar
1 -800 torr
1 -1100 mbar
Usable Range
0.1 -2 0 torr
0.1 - 20 mbar
0.2 - 100 mtorr
0.001 - .1 mbar
1 -1000 mtorr
.01 -1 mbar
0.1 -1 0 mtorr
—
5 mtorr • 5 torr
.01 • 5 mbar
.1 -2 0 torr
.1 -10 mbar
1 -800 torr
1 -1100 mbar
nternal Volume of
iauge Tube
1/20"3
O.Scc
1/2*3
8.2oc
1/2*3
8.2oc
1/2*3
8.2cc
1/2-3
8.2oo
1/2-3
8.2cc
1/20*3
0.8oc
Thermopile Temperature
In a High Vacuum
At Atmosphere
250°C
30°C
48°C
1.5°C
300°C
6°C
120°C
10°C
400°C
10°C
400°C
35°C
N/A
N/A
0.029
0.03
0.021
0.053
04/.04
03/.04
N/A
vtotal w/KF-16 Connection
\ -C
Ampheres Through Tube
VC Volts Across Tube
0.32
0.20
0.38
0.32
.20/.20
.19/.19
N/A
•Vatts Required by Tube
0.009
0.006
0.008
0.017
.016
.11
.018
10
11
2
6
10
18
2
6
13
5/6
13
6.S/7.5
Response Time
Zero to ATM • seconds
ATM to Zero • seconds
0.04
0.16
0.8
25
0.06
2.9
0.8
25
0.07
3.0
0.05
.2
.002
.002
vC Connection Pin #
3-5
3-5
3-5
3-5
2-4,6-8
2-4,6-8
—
7
7
7
7
Purple
Red
Yellow
Qreen
Orange
White
Li. Blue
)utput at
High Vacuum mv D-C
nternal Resistance - ohms
O-C Connection Pin #
Color of Base
Metal Tube
_
—
The above information includes nominal values only. Not to be used for design purposes or aooeptanoe tests.
PRESSURE AND TEMPERATURE DATA
rube Type
Max. Pressure
Metal: DV-4D, DVMD-VCR, DV-4D-KF-16 150 psig
All other metal (except Model DV-760) 50 psig
Max. Temperature
100°C
100°C
R- Series
250 Ps,9
150°C
Stainless/Ceramic
600 psig
300°C
Pyrex
15 psig
400°C
M o del D V-760
15 p3lg
40°C
/D
The gauge tubes can be expected to withstand the listed pressure and
temperature without rupture but they are not warranted as safe under
these conditions. For critical conditions or special testing, oontact factory.
TELEDYNE HASTINGS-RAYDIST, Hampton, Virginia
January 1991
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RE: DV-6R A ccu racy
h
Mr. W illiam C. B aker, H astings Sales M anager, specifies the
DV-6R accu racy a s ± 0.2 inV (± 2% o f FS) o ver the 0 to 10
tJ nJ
O o
rH
t=t P
3 9
f-l 4_>
mV (1 [iin to 1000 |im ) range. A t 1 ^ m the D V -6R
sensitivity is 161 m V /iam ; h erefo re the accuracy in this region
is ± 0.2 m V X 1 n m / 161 m V , o r ± 0 .0 0 12 \im.
During prod u ctio n , H astings ch eck s the D V -6R output at zero
scale (zero volts), h a lf scale (60 [im) and at atm ospheric
pressure.
M ! i Mr. Baker also sta te d that this calib ratio n curve, the tabulated
■ • 1•
characteristics an d the ± 2 % accu racy only apply w hen the
DV-6R is u sed in their circuitry.
D. W eber 1/8/95
c
J 3E. I l l Ml
f
HASTINGS
REFERENCE TUBE
A Quick Calibration Device for
Hastings Vacuum Gauges
•
•
•
•
Instant Calibration Check
Recalibration of Hastings Gauges
Adjusts Gauge for Any Length Cable
Stable, Accurate, Rugged, and Reliable
Application
Construction
Hastings Vacuum Gauge Indicators, Controllers, or Recorders can be
checked or recalibrated in seconds by merely plugging the gauge tube
cable into the reference tube. If calibration adjustment is necessary,
the "Current Set" potentiometer is adjusted until the instrument
indicates the pressure marked on the reference tube. The customer
now knows his instrument Is correctly calibrated.
Hastings Reference Tubes employ the same
Hastings noble metal thermopile used in all
Hastings Vacuum Gauge Tubes. The thermo­
pile is sealed in a glass capsule that has been
evacuated, baked, outgassed, sealed, and then
aged to ensure stability over long periods of
time. The sealed capsule is then housed in a
protective metal shell to provide a rugged,
trouble-free assembly.
Whenever cable lengths between gauge tube and instrument are
changed, some error may be introduced, requiring that the instrument
be readjusted to compensate for any losses involved. By plugging the
Reference Tube into the new cable and readjusting the instrument for
a correct reading, this “error" is eliminated.
Selection
Choose the reference tube that is equivalent to the glass or metal
Hastings Gauge Tube you are now using. The Reference Tube will be
matched and sealed at a pressure falling on the lower portion of the
scale and calibrated accurately at this exact pressure. For example, if
an Instrument uses a DV-6M Gauge Tube, a DB-20 Reference Tube is
ordered. The customer receives a tube marked, possibly, 10 microns.
This Is the exact pressure to which the indicator should be adjusted
when plugged Into the reference tube.
Selection Chart
Equivalent Gaoge Tab* and Range
Reference Tube
^CTELEDYNE
BROWN ENGINEERING
Hastings Instruments
Metal
•OV-3M
DV-40
•DV-5M
DV-6M
DV-8M
DV-23
DV-24
DV-310
G ian
DV-20
Range
0-10 ( % Hg
0-20mm Hg
0-100(i Hg
0-1000n Hg
0.01-10*1 Hg
0-5000u Hg
0-50 Torr
0-1000 mTorr and
0-1400 mbar
Reference Tabe
Model No. Stock No.
DB-16D
* DB-18
DB-20
DB-31
DB-33
DB-44
DB-300
55-100
55-103
55-104
55-105
55-106
55-107
55-252
Calibration
Considerable care and time are required in the
manufacture to obtain the high degree of
precision and stability required for the refer­
ence tube.
The thermopile Is matched to the reference
letter of the customer's tubes and maintains
its calibration overlong periods oftime. How­
ever, for applications requiring the highest
possible degree of accuracy, a periodic return
of the reference tube to the factory for a check
and recalibration may be desirable. An annual
or semiannual check assures the customer of
an accurate and reliable reference at all times.
IMPORTANT NOTE:
These reference tubes are designed specifi­
cally for use with instruments employing
Hastings circuitry and are NOT interchange­
able with instruments using other circuitry.
Connection to another manufacturer's instru­
ment may result in burnout.
Hastings Instruments reserves the right to change or
mollify tt ii design of Its equipment without any obligation
to provide notifiation ot change or intent to change.
*St»t« rtltrm ci tfflir of your Gtugi Tub* typ« for matching purpom.
D V -6 R
General
The H astings Reference Tube is an evacuated, sealed vacuum gauge
tube accurately calibrated to precisely simulate a gauge tube at a given
operating pressure. It is electrically equivalent to the metal and glass
gauge tubes used with Hastings Instrum ents. It perm its quick and
easy recalibration of H astings Vacuum Gauge Indicators by merely
plugging the instrum ent into the reference and adjusting the calibra­
tion "current set” potentiom eter until the instrum ent reads the exact
pressure noted on the reference.
Hastings Reference Tubes are
available equivalent to m ost Hastings Gauge Tubes.
^TTELEDYNE
BROWN ENGINEERING
Hastings Instruments
P.O. Box 1436 • Hampton, VA 23661
TL080, TL081, TL082, TL084, TL081A, TL082A, TLQ84A
TL081B, TL082B, TL084B
JFET-INPUT OPERATIONAL AMPLIFIERS
02297. FEBRUARY 1977-REVISED OCTOBER 1 M 0
2 4 DEVICES COVER M ILITA R Y . IN D U S TR IA L A N D C O M M E R C IA L TEM PER A TU R E RANGES
absolute m axim um ratings o v er operating free-air tem p eratu re rang e (unlesa o th e rw is e n o te d )
•
Low -Pow er Consumption
High Input Im pedence . . . JFET-lnput S ta g *
•
W ide Com mon-Mode and D ifferential
Voltage Ranges
Internal Frequency Com pensation (Except
TL080, TL080A)
•
Low Input Blaa and O ffset C urrent*
Latch-U p-Free O peretion
•
Output Short-Circuit Protection
•
Low Total Harmonic
Distortion . . . 0 .0 0 3 % Typ
TL080
D.
n i/c o m p Q i
IN-Q22
IN+ L 3
vcc-C 4
C om m on-M ode Input V oltage Range
Includes V c c +
TL082. TL082A. TL082B
0. JO. OR P PACKAGE
D. JG. OR P PACKAGE
U e h
OFFSET N l £
com p
IN-C
IN+C 3
Vcc-C
7IIVco
6D o u t
5 i U OFFSET N 2
O U TO
H i1 U
U
OUT
18
18
18
V
-1 8
-1 8
V
D iffe re ntia l in pu t voltag e (see N ote 2)
±30
±30
±30
V
Input voltage Isee N otes 1 and 3)
±15
±15
±15
V
unlim ited
unlim ited
u n lim ite d
C ontinuous to ta l dissip atio n
S
iNtC>
c
vcc - C
2 OUT
2 OFFSET N2
V rr - C 4
fro m case fo r 6 0 seconds
Lead tem perature 1,6 m m (1 /1 6 inch)
,,
NOTES:
Z O Z
'U U U
Z
U
PARAMETER
V jo
Z
1T
<
Input offset voltage
Temperature
NC
<ryiQ
>?[ Vcc +
coefficient ol input
offset voltage
I,a
Input bias current *
Ta - - 55*C to 125*C
V0 - 0,
Rs - 50 0.
Ta -
MIN
5
TA - 25*C
Common-mode
V|CR
input voltage range
TL084M . . . FK CHIP CARRIER PACKAGE
Maximum peak
(TOP VIEW)
Vnu
output voltage swing
TL084. TL084A. TL084B
.- •-
O. J. OR N PACKAGE
(J
30
TA - 25*C
(TOP VIEW)
L J l_J L J L J L-3"
3
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POST O ffic e BOX 86* 3 03 • DALLAS. TEXAS 7 M 6 6
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- 5 5 °C to 125®C
± 1 0 V.
Large-signal differential
Ta - 25*C
voltage amplification
V0 -
6
100
30
200
±11
to
± 10 V.
±12
±12
±12
RL X 2 kQ
±10
±12
±10
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25
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26
200
±13.6
3
3
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Common-mode
VIC " VICR min'
RS - 50 0,
v0 “ °’
Ta - 25*C
V c c * ± 15 V to ± 9 V, V0 - 0.
Rs - son.
Ta - 25*C
Supply current
No load.
V q ■ 0.
(per amplilierl
Ta - 2 5 #C
A v d - 100,
pA
50
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V
16
15
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200
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RL £ 2 kO.
TA - 25°C
(AVCC t ,4V|01
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V
Ta - 25*C
Supply voltage
rejection ratio
20
±12
Input resistance
kSVR
100
±13.6
Rl - 10 kQ
Unity-gein bandwidth
rejection ratio
aV/*C
to
Bj
CMRR
mV
16
Rl £ 10 kQ
Rl i 2 kO,
untt
-1 2
r,
V0 i/V 02 Crosstalk attenuation
C opyrigh
o p y n g n ti
Ta -
9
18
16
TA - 25*C.
MAX
3
50
±11
Ta - - 5 5 °C to 125*C
1 t- O H
2■r 3o oz 2- z
n
PRODUCTION OAT* < K » w t i eeetala leferwtiee
c«rT««t >i ef p b lk tllM
PrWacts cwri»f» »
speclficetiees per tke terms el T u n lettr»»eets
staadartf warranty. Predectlea pfiC*ui*| m m eat
necessarily inclaee testlni ef all fa raM l art.
AvD
2 0 T9
18[ #4 IN+
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16[ vcc«C NC
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9 r1-10(—i
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TA - 25*C
TYP
16
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V0 -
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o
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o
Input offset current*
Rs - 50 0
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14[1 NC
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o
OUT
TEST CONDmONS*
o
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10 I I
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260
260
± 15 V (unless otherw ise noted)
V0 - 0,
>
NC ]«
IN- ]s
NC ]«
IN+ V
NC ]8
- 6 5 to 1 50
A ll voltag e values, e xcep t d iffe re n tia l voltages, are w ith respect to the m idp oint b etw e en V c c + • n<* V CC - •
D iffe re ntia l vo ltag es are a t tha n on in verting in p u t term inal w ith respect to the in verting in p u t term in al.
The m a g nitu de o f th e in p u t vo lta g e m uat never exceed the m agnitude o f the supply voltag e o r 16 V , w h ic h e v e r ia leas.
The o u tp u t m ay be sh orte d to gro un d o r to either supply. Tem perature and/or supply vo ltag es m u st be lim ite d to eneure th a t
tha dissipation ra tin g is n o t exceeded.
electrical characteristics, V q c ± *
o
3 2 1 2019
9
1.
2.
3.
4.
l_ J L J I— I U J L J ■
u. U O O
•c
D, N, or P package
fro m case fo r 10 seconds
o
•- o ou
z * z > z
U
300
- 5 5 to 1 25
5 ]IN + J
(TOP VIEW)
<->
260
J or JG package
- 4 0 to 8 5
- 6 8 to 1 60 - 6 5 to 1 50
Casa tem perature fo r 6 0 seconds
TL082M . . . FK CHIP CARRIER PACKAGE
(TOP VIEW)
FK package
•c
•c
•c
0 to 70
S torage tem perature range
c
Dvcc +
TL081M . . . FK CHIP CARRIER PACKAGE
See D issipation R ating Table
O perating free-air tem pe ra ture range
8e p v c c +
UNIT
TL0S_M
-1 8
N o t* 1 >
Lead tem perature 1 .6 m m (1 /1 6 inch)
1 UilHNC
TL08_I
TL08_BC
D uration o f o u tp u t sh ort c irc u it Isee N ote 4)
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
T L 0 8 __AC
Supply voltag e, V c c -
TL081. TL081A. TL081B
JO. OR P PACKAGE
TL08_C
Supply voltag e, V c c + (see N ote 1)
High S le w R ate . . . 1 3 V /* a Typ
•
TL080, TL081, TL082, TL084. TL081A, TL082A, TL084A
TL081B, TL082B, TL084B
JFET-INPUT OPERATIONAL AMPLIFIERS
Ta - 25°C
MHx
0
80
88
80
88
dB
80
88
80
86
dB
1.4
120
2.8
1.4
120
2.8
mA
dB
f A ll characteristics are m easurod under open-loop cond itio ns w ith le ro com m on-m ode in p u t vo lta g e unlaaa o th e rw ise sp ecifie d .
* Input bias currents of a FET-input ope ra tion a l am plifier are normal ju nctio n reverse currents, w h ic h are tem pe ra ture sensitive aa sh ow n
in Figure 18. Pulse techniques m ust be used tha t w ill maintain the junction tem peratures as close to the am bient tem perature as is posa!b'/».
9 # m s v x a i 's v n v o • cocas# xos
16C-J
io>no xscm
TL080, TL081, TL082, TL084, TL081A, TL082A, TL084A
TL081B, TL082B, TL084B
JFET INPUT OPERATIONAL AMPLIFIERS
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Total harm onic d istortion
f -
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TL081 ONLY
UNIT
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THO
MAX
13
Rise tim e
schematic (each amplifier)
^
8
55
s
TL082M
- 5 5 ° C to 1 2 5 °C
f -
1 kHz
"O n pro du cts co m p lia nt to M IL-S TD -883. Class B, this parameter is n o t p ro d u ctio n tested.
1
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± 1 5 V , T a ■■ 2 5 ° C (unless o th e rw is e noted)
TEST CONDITIONS
V| -
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PARAMETER
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PM -45X S
PM-45XU
4 1/2 DIGIT
PANEL METERS
ACCURACY LCD METERS WITH 10^iV RESOLUTION, TRUE DIFFERENTIAL INPUTS, ULTRA LOW
POWER <25mW AT +5VDC, AND STANDARD MUX-BCD OR OPTIONAL PARALLEL BCD OUTPUTS
DESCRIPTION
SPECIFICATIONS
The PM-45X and PM-45XU are truly unique and extrem ely versatile in­
strum ents. Believed to be the w orld's sm allest and most energy
efficient 4 1/2 Digit LCD Panel Meters, they nevertheless offer more
high perform ance features than most larger and more expensive
DPM's.
I n p u t C o n f ig u r a t io n :
T ru e d iffe re n tia l a n d s in g le -e n d e d
F u ll S c a le R a n g e s :
±1 99 99m VD C
±1 9 9 9 9 V D C (s ta n d a rd )
± 1 9 .9 9 9 V D C
± 1 9 9 .9 9 V D C
± 1 2 0 0 .0 V D C (m a x . Input S ig n a l: h ig h e r
Both meters incorporate a crystal controlled 100KHz clock that pro­
vides an exceptionally high normal mode rejection of 120dB at m ul­
tiples fo 50/60Hz. Bipolar differential and single-ended DC voltages
from ±199.99m V to ±1200.0V full scale can be m easured and scaled
in alm ost any known engineering unit. Provision has been made for
signal offsetting and the capability of attenuating both high and low
signal inputs. Resolution is 10uV over ±19999 counts, and errors due
to zero drift are virtually elim inated by autozeroing. O ther modes of
operation, selectable by the user, include an ohm m eter mode, current
m eter mode and ratiom etric mode.
v o lta g e s c a n b e m e a s u re d if v o lta g e d i v i n g
re s is to rs a re lo c a te d e x te rn a lly )
In p u t Im p e d a n c e :
E x c e e d s 1 0 0 0 M Q o n 2 0 0 m V a n d 2 V ra n g e s
I n p u t P r o t e c tio n :
± 1 7 0 V D C o r 1 2 0 V A C on 2 0 0 m V a n d 2 V ra n g e s .
1 0 M Q o n all o th e r ra n g e s
± 1 2 0 0 V D C o r 8 5 0 V A C on all o th e r ra n g e s
N o r m a l M o d e R e je c tio n :
1 2 0 d B a t m u ltip le s o f 5 0 /6 0 H z
C o m m o n M o d e R e je c tio n
8 6 d B a t D C : g re a te r th a n 1 2 0 d B a t m u ltip le s of
50/60HZ
C o m m o n M o d e V o lta g e :
-2 .8 V to + 2 .8 V (s ta n d a rd )
± 2 .8 V o r m o re if d iffe re n tia l d iv id e rs a re u s e d
{s e e T y p ic a l A p p lic a tio n C irc u its a n d
M ultiplexed BCD data is available internally from a row of auxiliary
solder pads. Both m eters may be ordered with an internally mounted
Tri-state Buffered Parallel BCD Output Board. This option, which is
described in detail on a separate data sheet, can also be purchased for
field retrofit.
C o n n e c tio n In s tru c tio n s )
A c c u ra c y :
P M -4 5 X ± ( 0 .0 1 % o f re a d in g + 1 d ig it)
± (0 .0 1 5 % o f re a d in g + 2 d ig its ) fo r 2 0 0 m V ra n g e .
P M -4 5 X U ± (0 .0 1 5 % o f re a d in g + 2 d ig its ). = (0 .0 2 %
o f re a d in g + 3 d ig its ) fo r 2 0 0 m V ra n g e
M a x im u m R e s o lu t io n :
The PM -45X features an ultra stable tem perature com pensated refer­
ence with selected low TC com ponents. The PM -45XU is a derated
econom y priced m odel that provides all the features of the PM -45X but
utilizes a standard reference, and com ponents with less stringent
specifications.
10^xV o v e r ± 1 9 9 9 9 c o u n ts in 2 0 0 m V
ra n g e . 1 0 0 |iV o v e r ± 1 9 9 9 9 c o u n ts in 2 V ra n g e
T e m p e r a t u r e C o e ff ic ie n t :
P M -4 5 X : 5 P P M /° C ra tio m e tric .
2 0 P P M /° C u s in g in te rn a l a d ju s ta b le T .C . R e fe re n c e
P M -4 5 X U : 5 P P M /° C ra tio m e tric . 5 0 P P M /CC u s in g
in te rn a l re fe re n c e
Z e r o S t a b ilit y :
The true differential input capabilities and high 86dB com m on mode
rejection ratio, com bined with their low signal m easurem ent range and
high noise im m unity, m ake these m eters ideal for m easuring various
balanced transducers and bridge inputs. W hen m easuring bridge
circuits, long term drift of the excitation voltage can be com pensated by
using the ratiom etric voltm eter mode of operation.
± 1 |iV /° C T y p ic a l
C o n v e r s io n R a te :
C lo c k F r e q u e n c y :
2.5 r e a d in g s p e r s e c o n d
1 0 0 K H z s y s te m c lo c k d e riv e d fro m 2 0 0 K H z q u a rtz
c ry s ta l c o n tro lle d o s c illa to r of 0 .0 5 % a c c u ra c y
D is p la y :
0 .4 8 " L C D
P o la r it y :
A u to m a tic : d is p la y s b o th “ +" a n d
s ig n s : p o la rity
s y m b o ls m ay b e b la n k e d (s e e p ag e 6)
O v e r lo a d I n d ic a t io n :
The proprietary high contrast, long life liquid crystal display provides
excellent readability under high and low am bient light conditions. Since
the m eters norm ally draw only a small constant current (<25mW ),
operation from alm ost any DC power supply is sim plified. If the supply
has a stability of only 10%, a voltage dropping resistor in series with the
m eter is often sufficient. (See Application notes.)
A u to z e ro e d ± 1 0 |iV at all ra n g e s ;
W h e n in p u t e x c e e d s fu ll s c a le on any ra n g e b e in g
u s e d , th e m o s t s ig n ific a n t “ 1" d ig it a n d
or
s y m b o l is d is p la y e d w ith a ll o th e r d ig its b la n k
P o w e r R e q u ir e m e n t s :
L o w rip p le + 4 .5 V to + 5 .5 V D C at 3 m A to 5 m A
W a r m u p T im e :
10 s e c o n d s to s p e c ifie d a c c u ra c y
O p e r a tin g T e m p e r a t u r e :
0 ° C to +60~C
ORDERING INFORMATION
S t a n d a r d H ig h A c c u r a c y 4 1/2 D ig it P a n e l M e te r (2 V R a n g e )
O r d e r P a rt N o .
P M -4 5 X
S t a n d a r d U t il it y V e r s io n 4 1/2 D ig it P a n e l M e te r (2 V R a n g e )
P M -4 5 X U
P M -4 5 X W /T r i- S ta t e P a r a lle l B C D O u tp u t
P M - 4 5 X U W /T r i- S ta t e P a r a lle l B C D O u tp u t
R e t r o f it T r i- S t a t e P a r a lle l B C D B o a r d f o r P M -4 5 X /P M -4 5 X U
A c c e s s o r i e s : E d g e C o n n e c t o r (2 0 pm s o ld e r ta b s )
P M -4 5 X B C D
P M -4 5 X U B C D
P M -4 5 X B C D O
C N -L 1 0
O p t i o n s : F a c t o r y I n s ta lle d 2 0 0 m V R a n g e
V G -2 0 0 M V F I
O r d e r P a rt N o .
R a n g e C h a n g e K i t s : (m a tc h e d r e s is to rs fo r u s e r in s ta lla tio n )
200m V R ange
20V Range
200V R ange
1200V R ange
O p tio n a l C a s e s * : (s e e b a c k p a g e fo r d e ta ils )
V G -2 0 0 M V
V K A -0 0 2 0 V
V K A -0 2 0 0 V
V K A -1 2 0 0 V
E n d M o u n t C a s e (tw in m e te r m o u n tin g )
E M - C A S E C IR
F a c t o r y I n s t a lle d 2 0 V R a n g e
V F A -0 0 2 0 V
F a c t o r y I n s t a lle d 2 0 0 V R a n g e
V F A -0 2 0 0 V
F a c t o r y I n s t a lle d 1 2 0 0 V R a n g e
V F A -1 2 0 0 V
F a c t o r y I n s t a lle d S p e c ia l S c a lin g (S p e c ify in p u t s ig n a l, th e s p a n , a n d d ig ita l re a d in g
C e n te r M o u n t C a s e (m u ltip le a rra y m o u n tin g )
S lim B e z e l C a s e ( s u p p lie d as s ta n d a rd )
C M -C A S E C L R
S L -C A S E C L R
re q u ire d , e .g . 1 to 5 V in p u t to d is p la y 0 to 1 0 .0 0 0 : 4 to 2 0 m A in p u t to d is p la y 0 to
the rear sid e of th e le ns To ord er the se c a se s, use the follow ing p an ~^m Ders
E M -C A S E L C D ; C M -C A S E L C D ; S L -C A S E L C D .
1 5 .0 0 0 : 0 to 5 0 m A in p u t to d is p la y -1 .0 0 0 to + 8 .0 0 0 .)
V S -4 5
‘ M e ters p u rch a se d p rio r to A ugust 1989 re q u ire c a s e s w ith a p o la riz e ' oonaed to
CONNECTOR PINOUTS
The Texmate Model PM -45XIPM -45XU is interconnected by means of a standard PC
board edge connector having two rows of 10 pins, spaced on 0 .1 5 6 ' centers. The op­
tional parallel BCD Output is interconnected by a standard PC board edge connector hav
mg two rows of 13 pins spaced on 0.1 'centers. (A standard 26 pin, PCB to Ribbon
Cable Connector is recommended.) Connectors are available from Texmate, or from
almost any connector manufacturer.
A B C 0 E F H J —
K L -
Reference Output
Signal High Input
Analog Common
Decimal Select 11XXX.X)
Decimal Select (1.XXXX)
Oecimal Select {. 1XXXX)
Back Plane Output
Clock Output
-^5VDC System Power Input
Power Ground Input
1
2
3
4
5
6
7
8
9
10
—
—
—
—
Reference Input
Offset Voltage Output
Signal Low Input
Oecimal Select (1XX.XX)
Decimal Select Common
Decimal Select (1X.XXX)
Back Plane Input/Display Test
Clock Input
Busy Output
Run/Hold
f u n c t io n a l d ia g r a m
SINGLE ENDED METER - > 2 V RANGES W ITH VOLTAGE DIVIDER
1) High single ended voltages, up to 1200V max. can be measured andior scaled by install
mg the appropriate voltage dividing resistors in R1A and R2A positions Matched dividing
resistors for the 20V 11,101. 200V I 1,1 001. and 1200V 111 0001 ranges are available from
Texmate 2i Connect Pm 3 to the nearest end of the signal source ground to avoid possible
errors caused bv ground loop currents
CAUTION: This meter employs high impedance CMOS inputs. Although internal protection has been
provided for several hundred uoit overloads, the meter will be destroyed if subiected to the high
kilovolts of static discharge that can be produced m low humidity environments. Always handle the
meter with ground protection.
C>£C*M*w SEi»ECT
PIN DESCRIPTIONS
Pin A - Reference Output: Internal precision voltage reference. Standard output is
1.00 00V , adjustable ± 5 % by R10 potentiometer. Usable voltages from 0.05 V to 2.49V
for special high impedance scaling can be obtained by changing the value of internal
dividing resistors R8 and R9. The primary reference voltage of the PM -45X is trimmed by
potentiometer R20 to obtain the optimum compensated temperature coefficient. This
temperature compensation network is omitted on the PM 45XU utility meter. Please read
CALIBRATION PROCEDURE (Page 7).
Pin B - Signal High Input: Pin B is the signal high input for all input signal ranges. When
attenuation is not required the resistor position R 1A must be shorted by a jumper. Dividing
resistors may be mounted internally in R 1A and R2A positions to attentuate voltages up
to 120 0V max. Matched dividing resistors for the 20V (1 110), 20 0 V (1 1100) and 1200V
( M 0 0 0 ) ranges are available from Texmate. Shunt resistors for current measurements
up to 200m A may also be internally mounted in the R2A position. The current loop is then
applied to Pin B and returned through Analog Common Pin C.
Pin C - Analog Common: Pin C is signal return common for differential inputs,
ratiometric inputs, or external reference inputs. For single ended inputs, Signal Low Input
Pin 3 must be connected to Analog Common Pin C. To minimize any errors caused by
ground loop currents it is recommended that this connection be made as close as possible
to the input signal source ground. (See Typical Application Circuits and Connection In­
structions, Pages 4-6.)
Pins D. E. F, 4 and 6 — Decimal Select: Decimal points may be displayed as required by
connecting the appropriate pin to Decimal Select Common Pin 5. Any number of decimal
points can be turned on at the same time. An open circuit will turn off the decimal points.
However, static current pickup and/or PCB leakage of more than 100nA can cause
decimal points to turn on undesirably. Therefore, it is recommended that the unused
decimal points be connected to Back Plane Output Pin H either directly or by a resistor of
less than 5 M Q to insure an off condition. CAUTION: Any DC component introduced to the
display drive circuitry can, in time, cause permanent damage. PLEASE READ PAGES 7
AND 8 FOR A DETAILE0 EXPLANATION OF LCD OPERATION.
Pin H - Back Plane O utput: Liquid crystal displays are operated from an AC signal.
Back Plane Output Pm H provides a square ware signal of 6 0 ~ 160H Z that must be con­
nected by the user to back plane input Pin 7 for normal operation. Pin 7 is internally con­
nected to the LCD back plane which is the common base of the LCD capacitance struc­
ture. Those segments that are driven 18 0° out of-phase with the back plane will turn on.
Those segments that are driven in phase with the back plane will turn off. PLEASE READ
PAGES 7 AND 8 FOR A DETAILED EXPLANATION OF LCD OPERATION.
Pin J — Clock O utput: A quartz crystal controlled oscillator provides a stable clock
signal output of 100KHz.
Pin K - +5 V O C System P ow er Input: The meter requires a low ripple DC power supply
of 4.5V to 5.5VDC at 3mA to 5mA. The low power consumption of only 25mW enables
the meter to be easily operated from various power sources with simple voltage regulating
circuitry. The positive terminal of the power supply should be connected to Pin K.
Pin L - P ow er Ground Input: Negative terminal of the +5V D C power supply should be
connected to Pin L. All digital signals, Display Test, and Run/Hold should be returned to
this ground point. Pin L is internally connected to Analog Common Pin C.
Pin 1 — Reference Input: Reference voltage input for A to D converter. Normally sup­
plied from Pin A. An external reference source referred to Pin C may be used instead. Pin 1
may be used as an input for ratiometric measurements. Minimum usable voltage is
05VDC, with a maximum voltage of 4.0V. For ratiometric operation; Displayed Reading
= 1 0 0 0 0 X (Signal Input Voltage -r Reference Input Voltage). The maximum signal input
voltage is ± 4 V . Higher voltagesmust be scaled down through a voltage divider. Reference
input voltage must remain stable during measurement period.
Pin 2 - O ffset Voltage Output: 0 to + 2 . 49 0 V is available with the addition of a h ",
20 K Q to 10 0 K Q pot in the R 15 position on the printed circuit board. The offset voltage
is derived from the internal precision voltage reference and is available for applications re­
quiring a zero offset such as 4 ~ 2 0 m A receiver and temperature measurements.
Pin 3 - Signal Low Input: Pin 3 is the signal low input for all input signals. A special
feature of the meter is the provision for dividing resistors to be mounted internally in the
R IB and R2B positions. This enables low signal inputs up to 12 00V max to be at
tenuated, which is particularly useful when measuring small differential signals with a
large common mode voltage. Matched dividing resistors for the 20V 11/10), 200V
(1 /1 0 0 ) and 1200V (1 /1 0 0 0 ) ranges are available from Texmate. Differential current
measurements up to 200m A may also be made by internally mounting shunt resistors in
the R2B position. The current loop is then applied to Pin B and returned through Analog
Common Pin C. When attenuation is not required the resistor position R IB must be
shorted by a jumper.
Pin 5 — Oecim al Select Common: Pin 5 is 1 8 0 ° out-of-phase with back plane output
Pm H. Thus it serves as a common for the decimal select Pins 0, E, F, 4 and 6. To turn on
any required decimal point, connect the appropriate Oecimal Select Pin to Decimal Select
Common Pin 5.
Pin 7 - Back Plane Input/D isplay Test: Pin 7 is connected to the display's back plane
which forms the common base of the LCD capacitance structure. Join Pin 7 to back plane
output Pin H for normal operation. For Display Test connect Pin 7 instead to Power
Ground Pin L and all operative segments will turn on, indicating + 1 8 8 8 8 . CAUTION: The
Display Test function is only intended for momentary operation. Continuous application of
Display Test will, in time, damage the display. SEE PAGES 7 AND 8 FOR A DETAILED EX
PLANATI0N OF LCD OPERATION.
Pin 8 - Clock Input: Normally Pin 8 is connected to the 100KHz clock output from Pin
J. thereby providing the optimum rejection of 50160 Hz noise. However, an external clock
source may be used instead (5 V referenced to power ground with a recommended duty cy
cle of 50% ). Minimum frequency is lOKHz, and maximum frequency is 1MHz (1 2.5
readings per sec.). For inputs below 10OKHz or above 300K H z, changes to the integrator
time constant and some component values are necessary.
Pin 9 - Busy O utput: Pin 9 goes to logic " 1 " at the beginning of the signal integration
and remains at " 1 " until the first clock pulse after the zero-crossing is detected at the
completion of deintegration. In addition to its use as a Busy or End-of-Conversion signal,
the output on Pin 9 can be used in some control applications to indicate the digital reading
of the meter as a function of time or clock pulses. Oisplayed Reading is equal to the total
clock pulses during Busy less 1 0 ,0 0 0 , or total elapsed time during Busy, less 100 milli­
seconds if the clock frequency is lOOKHz.
Pin 10 - RunlHold: If Pin 10 is left open (or connected to +5V D C System Power Input
Pin K for logic control purposes), the meter will operate in a free-running mode. Under
contrcf of the internal 10OKHz quartz crystal clock, readings will be updated every
400m S (2.5 per sec.). If Pin 10 is connected to Power Ground Input Pin L (logic low),
the meter will continue the measurement cycle that it is doing, then latch up and con
tinuously hold the reading obtained as long as Pin 10 is held low. If Pin 10 is released
from Pin L (Pin 10 then goes logic high) for more than 300ns and returned to Pin L (logic
low), the meter will complete one conversion, update, and then hold the new reading. For
all practical purposes, a manually actuated normally closed pushbutton switch will pro
vide sufficient timing for "press-to-update" operation.
ANALOG
DEVICES
□
FEATURES
L*Mr-Trimm«d to High Accurtcy:
10.000 Volts ±5mV (L and U)
Trimmed Tamparatura Coefficient:
5ppm/°C max, 0 to +70'C (L)
10ppm/°C max. -65#C to +126°C (U)
Excallant Long-Term Stability:
2Sppm/1000 hrs. (Noncumulative)
Negative 10 Volt Reference Capability
Low Quiescent Currant: 1.0mA max
10mA Currant Output Capability
3-Tarminal TO-5 Packaga
High Precision10V 1C Reference
AD581*
A D 581 F U N C T IO N A L B L O C K D IA G R A M
■’ ......
t
The band-gap circuit design used in the AD581 offers several
advantages over classical Zener breakdown diode techniques.
Most important, no external components are required to
achieve full accuracy and stability o f significance to low power
systems. In addition, total supply current to the device, includ­
ing the output buffer amplifier (which can supply up to 10mA)
is typically 750>iA. The long-term stability o f the band-gap
design is equivalent or superior to selected Zener reference
diodes.
A D S ilj
Typ
O U T P U T VO LTAG E TO LER ANC E
(Error from nominal 10,000Voutput)
O U T P U T V O LTAG E CHANCE
Maximum Deviation from ♦ 2VC
Value, T m , to T m
( Temperature Coefficient)
U V * V n , * l5 V
BOTTOM VIEW
age reference.
Mk
(@ V « *
L IN E R EG U LATIO N
IJ V * V ,N»J 0 V
TO-J
PRODUCT DESCRIPTION
The AD581 is a three-terminal, temperature compensated,
monolithic band-gap voltage reference which provides a pre­
cise 10.00 volt output from an unregulated input level from
12 to 30 volts. Laser Wafer Trimming (L W T ) is used to trim
both the initial error at +25°C as well as the temperature
coefficient, which results in high precision performance pre­
viously available only in expensive hybrids or oven-regulated
modules. The 5mV initial error tolerance and 5ppm/ C guar­
anteed temperature coefficient of the AD581L represent the
best performance combination available in a monolithic volt­
SPECIFICATIONS
M oM
;
" " " '.f t
PRODUCT H IG H LIG H TS--------------------------- -Vjjf
1. Laser trimming o f both initial accuracy and temperature
coefficient results in very low errors over temperature'with*
out the uae o f external componentarThe A D 5 e H r h * » * - ~ jj
maximum deviation from J0.000 volt* o f ±7.25mV from
0 to * 70*C, whiteth eA D 58!U ,gn»i\i|t t t >:fr|3roy y iX iWUnT
total error without external trim* fr o m - l J
2. Since the laser trimming is done on t M ’*kVelr'p^of
'
ration into individual chips, thfe A D 581 will be tx^remely .
valuable to hybrid designers for its ease o f uee.lackflt-.iv
required external trims, and inherent high perform a m x a V - ,
3. The AD581 can also be operated in a two-terminal "Zen er"
mode to provide a precision negative 10 volt reference with
just one external resistor to the unregulated supply. The per.,
formance in this mode is nearly equal to that o f the stand­
ard three-terminal configuration.
4. Advanced circuit design using the band-gap concept allows
. the AD581 to give full performance with an unregulated in­
put voltage down to 13 volts. With an external resistor, the
device will operate with a supply as low as 11.4 volt*.
+15V wn6 2STt)
Mu
ADSI1K
T r?
Mm
A D S flL
Typ
M ia
Maa
Ua*a
± »
± 1#
±5
mV
±11.5
± 6.75
±2.25
mV
50
13
5
ppmTC
l.l
(0 0 0 2 )
IJ
(0 005)
)J
(0 .002)
1J
(0 005)
IJ
(0.002)
IJ
(0.005)
mV
H/V
mV
%/V
'
LO A D R EG U LATIO N
0 s lo iT * 3 m A
200
QUIESCENT CU RR EN T
0 73
TUR N-O N SE T T L IN G T IM E TOO. 1 * '
200
200
200
NOISEIO Ito lO H i)
50
50
50
*V/p-p
LONG-TERM S TA B ILIT Y
25
25
23
ppm/1000 hr«.
SHORT -CIRCUIT CU RR EN T
*>
30
M>
mA
O U T P U T CU RR EN T
Source (" ♦ l i 'C
Source T ,** to T w ,
Sink T mi* 10 T m i
Sink - 55*Cio ♦ H"C
10
5
5
-
TEM PERATURE RANGE
Specified
Operating
0
-65
IJ
200
5M
200
5M
nV/mA
0.75
IJ
0.75
IJ
mA
♦ 70
♦ 150
Mbs
*70
♦ 150
65
Maa
O U T P U T VO LTAG E TO LER ANC E
(Error from nominal 10,000Voutput)
Mia
AD 5S IT
T yp
•c
*C
>70
♦ 150
A D 5 IIL H
Maa
A D M IU
T yp
Mia
UaHa
Maa
± 1«
±M
O U T P U T VO LT AG E CHANGE
Maximum Deviation from ♦ 25*C
Value, T ^ to T M ,
(Temperature Coefficient)
U V * V , n * I5 V
0
-6 5
A D 5 IIK H
ADS6 IS
Typ
LIN E R E G U LAT IO N
15V*V, n s )0V
mA
mA
hA
mA
-
0
AD5IIJH
Modal
_______________
10
5
5
10
5
5
PACKAGE O P TIO N *
TO-J(H-OJB)
mV
*5
±M
±15
* lt
50
13
10
IJ
(0 0 0 2 )
IJ
(0005)
IJ
(0 .002)
IJ
(0005)
1
- ■ V /•
.*».
ppmrd
IJ
(0.002)
IJ
(0.005)
mV
%/V
mv
-* w
>
LO AD R EG U LATIO N
200
0 *l< H .T *5mA
SOt
0 75
IJ
200
.
.
0.75
S*
,.i
IJ
laV'mA
mA
0.75
TL'R N-QN S E T T LIN G TIM E TOO. 1V
200
200
200
M
NOISE (0.1 to 10Hz)
50
50
50
liV/p-p
LONG TER M S T A B IL IT Y
25
23
23
ppm/1000 hn.
SHORT-CIRCUIT CU RRENT
JO
JO
M>
mA
O UTPUTCURRENT
Source 0i ♦ 25*C
Source T mill to T mi,
Sink T W1„ to T m .
Sink 5 5 C io » * 5 ,C
grating designs, and in general can offer better performance
than that provided by standard self-contained references.
TEM PERATURE RANGE
Specified
Operating
The AD581J, K, and L are specified for operation froinO to
+70°C; the AD581S, T, and U are specified for the -55 C to
+ 125°C range. All grades are packaged in a hermetically-
PACKAGE OPTIO N *
TO 5(H 0JB)
IJ
200
QUIESCENT CU RRENT
The AD581 is recommended for use as a reference for 8-, 10or 12-bit D/A converters which require an external precision ref­
erence. The device is also ideal for all types o f A/D converters
up to 14 bit accuracy, either successive approximation or inte­
200
5
55
65
i 125
• 150
AD58ISH
•Covered by Patent No». 3,887.863; RE 30,586
Specifications shown m boldface are tested on all production units at final electri­
cal test Results from those tests art used to calculate outgoing quality levels All
mm and mai specifications are guaranteed, although only thuae shown in
boldface are tested on all production units
VOLTAGE REFERENCES &-9
8 -1 0
VOLTAGE REFERENCES
mA
mA
10
3
200
5
10
10
5
200
5
NOTF.S
'See Figure 7
'See Section I ) for package outline information
Specifications suhiect to change without nonce
sealed three-terminal TO-5 metal can.
M ia
55
65
• 125
• 150
A D 5 IIT H
4
mA
53
65
♦ 123
♦ 150
•c
•c
AD5SIUH
A B S O LU TE M A X R A T IN G S
Input Voltage V|N to G ro u n d ......................................... 40V
Power Dissipation (i i + 2 5 ° C ................................... 600mW
Operating Junction Temperature Range . . - 55°C to +150°C
Lead Temperature (Soldering lO s e c )........................ +300°C
Thermal Resistance
Junction-to-Ambient .............................................150°CyW
VOLTAGB VARIATION *». TEM PERATURE
Some confuiion exist* in the tret o f defining and specifying
reference voltage error over temperature. Historictlly, refer
ences have been characterized using a maximum deviation per
degree Centigrade; i.e., 10ppm/°C. However, because o f nonlinearities in temperature characteristics, which originated in
standard Zener references (such as “ S” type characteristics)
most manufacturers have begun to use a maximum limit error
band approach to specify devices. This technique involves
measurement o f the output at 3, 5 or more different temperttures to gutrantee that the output voltage will fall within the
given error band. The temperature characteristic o f the AD 58I
consistently follows the S-curve shown in Figure 4. Five-point
measurement o f each device guarantees the error band over the
-55 C to +125°C range; threeyoint measurement guarantees
the error band from 0 to +70 C.
rent i* positive. Note thtt the short circuit current (i.e., zero '
volts output) it about 28mA; when shorted to +13 volt*, the i
sink current goes to about 20mA.
,
D YN A M IC PERFORMANCE
Mtny low power instrument manufacturers are becoming in­
creasingly concerned with the turn-on chartcteristics o f the
component* being used in their system*. P u t turn-on compo­
nents often entble the end u»er to keep power o ff when not
needed, tnd yet respond quickly when the power is turned on
for operation. Figure 6 display* the tum-ort characteristic o f
the AD581. Thi* characteristic i* generated from cold-sttrt
operation tnd represent* the true turn-on waveform after an
extended period with the supplies off. The figure show* both
the cotrte tnd fine transient characteristics o f the devicei the
total settling time to within ±1 millivolt i* about 18tyis, and
there i* no long thermal tail appearing tfter the point.
Applying the AD581
A PPLY IN G THE A D J8I
The AD581 is etsy to use in virtutlly til precision reference
applications. The three terminals are simply primary supply,
ground, and output, with the case grounded. No external com­
ponents are required even for high precision applications; the
degree o f desired absolute accuracy is achieved simply by
selecting the required device grade. The AD581 requires less
than 1mA quiescent current from ah operating supply range
o f 12 to 30 volts.
The error band which is guaranteed with the AD581 is the
maximum deviation from the initial value at +2J°C; this error
band is o f more use to a designer than one which simply guar­
antees the maximum total change over the entire range (i.e.,
An external fine trim may be deaired to tet the output level
to extctly 10.000 volt* within le*t thtn t millivolt (calibrated
to t mtin system reference). System calibration m ty tlso re­
quire t reference slightly different from 10.00 volu . In either
ctse, the optiontl trim circuit shown in Figure 2 ctn offset the
output by up to *3 0 millivolts (with the 2212 resistor), if
needed, with minimtl effect on other device chtrtcterisdcs.
ft
2
12
2fi0
un
in the latter definition,-all o f the change* could occur in the
positive direction). Thus, with a given grade o f the ADJ81, the
designer can easily determine the maximum total error from
initial tolerance plus temperature variation (e.g., for the
AD581T, the initial tolerance is ±10mV, the temperature error
band is ±15mV, thus the unit is guaranteed to be 10.000 volts
±25mV from -55#C to + 125°C).
Figure 1. A DBS 1 Pin Configuration (Top View)
;; j
.- p T'H--
R
U
KI A
M
AC
X*
RT
A
M
Q
T
UOm
V 2JppW
*C
lO
m
.0
*p
W
0J
Vp
m
/*C
C
ttfc
w
VV 2
Figure 2. Optional Firm Ttlm Configuration
■t
-pa
x
M l m u*. N N *r r w
•
Figure 4. Typical Temperature Characteristic
nc
tyr
MOUM
r
h
OUTPUT CURRENT CHARACTERISTICS
The AD581 has the capability to either source or sink current
and provide good load regulation in either direction, although
it has better characteristics in the source mode (positive c u r ­
re n t into the load). The circuit is protected for shorts to either
positive supply or ground. The output voltage vs. output cur­
rent characteristics of the device are shown in Figure 5. Source
current is displayed as negative current in the figure; sink cur­
fmqu<hcv - m
Figure 7. Spectral Noise Density and Total rm s Noise
vs. Frequency
OUTnjTCURRENT- m
A
Figure 5. A D 5 8 1 Output Voltage v s. Sink and Source Current
Figure 8. Quiescent Current vs. Temperature
VOLTAGE REFERENCES 9-11
8-12 VOLTAGE REFERENCES
TYPES SN S5452B , S N 75452B
DUAL PERIPHERAL POSITIVE-NAND DRIVERS
PRECISION HIGH CURRENT SUPPLY
The A0581 can be e»*ily connected with power pnp or power
darlington pnp devices to provide much greater output current
capability. The circuit shown in Figure 9 delivers a precision
10 volt output with up to 4 amperes supplied to the load. The
0. l^F capacitor is required only if the load has a significant
capacitive component. If the load is purely resistive, improved
high frequency supply rejection results from removing the
capacitor.
ia
SN66462B . . . JQ
SN76462B . . . JQ OR P
D U A L -IN LINE PACKAGE (TOP VIEW|
*.7*mA
vcc ll
Figure 11. A Two-Component Precision C urrent Lim iter
.Vi .;
Figure 10. 12-Volt Supply Connection
THE AD581 AS A CURRENT LIMITER
The AD581 represents an alternative to current limiter diodes
which require factory selection to achieve a desired current.
T his approach often results in temperature coefficients of
1%/°C. The AD581 approach is not limited to a defined
set current limit; it can be programmed from 0.75 to 5mA
with the insertion o f a single external resistor. O f course, the
minimum voltage required to drive the connection is 13 volts.
The AD580, which is a 2.5 volt reference, can be used in this
type o f circuit with compliance voltage down to 4.5 volts.
H (o ff stata)
Y
L
H
H (o ff itata)
H
L
H (o ff itata)
H
H . L J o n jt a t a ^
T Uj u1ft n ITmG*Dr
M * high laval, L ■ low laval
positive logic: Y • AB
schematic (each driver)
electrical characteristics over recom m ended operating free-air tem perature range (unless otherw ise noted)
.
The ADS 81 can also be used in a two-terminal m od* t o develop
a positive reference. V w and V g y r are tied together and t#
the positive supply through an appropriate supply resiftor. The
performance characteristics will be similar to those o f the neg­
a tive two-terminal connection.'The only advantage o f this con­
nection over the standard three-terminal connection it t h it a
lower primary supply can be used, as low as 10.5 volts. This
type o f operation will require considerable attention to load
and primary supply regulation to be sure the AD581 always
remains within its regulating range o f 1 to SmA.
L
V |H
High-laval Input voltaga
V lL
Low-laval Input voltaga
V|K
In p u t dam p voltaga
'O H
SN76462B
SNB6462B
PARAM ETER
M IN
TYPt
MAX
M IN
TYPt
High-laval o u tp u t currant
I| - - 1 2 m A
Vcc
* M IN.
V q h -3 0 V
V |L * 0.8 V,
Vcc ‘ M'N.
V |h - 2 V ,
- 1 .2
-1 . 2
- 1 .6
U N IT
V
0B
0.8
V cc *
MA X
2
2
300
V
- 1 .6
V
106
nA
Q.26
0.S
O Jtt
0.4
0.6
OS
0.6
0.7
I q l ■ 100 mA
VOL
Low-laval o utp ut voltaga
'I
Inp u t currant at m axim um in p u t voltaga
V cc " m ax,
V | -6 J 5 V
1
1
•IH
Hlgh-toval Input currant
Vc c -
V |-2 .4 V
4$
40
mA
'I L
Low-laval Input currant
V CC - M A X ,
V| -0 .4 V
- 1 .6
mA
•CCH
Supply currant, o utputs h ljfi
VCc * MAX.
<
S
t o +85 C.
■ I
L
•CCL
Supply currant, o u tp u t! lo w
v Cc * m a x .
V, -6 V
V CC - M I N ,
V |H “ 2 V,
lO L • 300 m A
m ax
.
-1 .1
<
NE G ATIV E lO-VOLT REFERENCE
The AD581 can also be used in a two-terminal ,'Zener” mode ’
to provide a precision -10.00 volt reference. A* shown in Fig­
ure 13, the Vjn and V q u t terminals are connected together
to the high supply (in this case, ground}. Th e ground pin it
connected through a resistor to the negative supply* The out­
put is now taken from the ground pin instead q f VQUT. With
1mA flowing through the AD581 in thi» mode, 1 typical unit
will show a 2mV increase in output level 6 m that produced
in the.three-terminal mode.'Note also thaT tMTtffeclive output
impedance in this connection increases fro n f0 ;2 fity p ic a lto
2 ohms. It is essential to arrange the oiftpucload aod the sup­
ply resistor, R j, so that the net current through the AD581 is
always between 1 and 5m A.The tempcratun^chanctcristica
and long-term stability o f the device:will.bdeSifchfitfly jthc.,KI
same as that o f a unit used in the standard three-tcrminuvV|#.
mode. The operating temperature range is limited to -55 C
A
o
CONNECTION FOR REDUCED PR IM A R Y SUPPLY
While line regulation is specified down to 13 volts, the typical
AD581 will work as specified down to 12 volts or below. The
current sink capability allows even lower supply voltage capa­
bility such as operation from 12V ±J% as shown in Figure 10.
The 560f2 resistor reduces the current supplied by the ADS 81
to a manageable level at full SmA load. Note that the other
bandgap references, without current sink capability, may be
damaged by use in this circuit configuration.
JV
>•
FUNCTION TA BLE
(EACH D R IV E R )
=*1.1
-1 .6
mA
11
14
11
14
mA
66
71
66
71
mA
TYP
MAX
* For oondltlons shown es MIN or M A X , use the appropriate value ipeclf led under recommended operating conditions.
t A ll typlcel values ere et V c c ■ 6 V, T ^ * 26°C.
switching characteristics, Vcc ■ 5 V, T a ~ 25eC_____________________________________
PAR AM ETER
Propagation dairy tlm a, low-to-hi(fi-taval o u tp u t
»PHL
Propagation dalay tlm a, hi(fi-to-low -laval o u tp u t
lO " 200 m A ,
C l - 16 pF,
*TLH
Transition tlm a, low-«o-hl(^-laval o utp ut
R l - 60 n ,
Saa Figura 3
»THL
Tranrition tlm a, hlgh-to-low-4eval o utp ut
v OH
VOLTAGE REFERENCES 8-13
TEST CO NDITIO NS
*PLH
V $ - 2 0 V,
Saa F iflu rt 4
exas
In
s t r u m e n t s
IN C O H P O R A T tD
* o s t o m c r eox son • D a l l a s
t ix a s
?sa»a
lO •» 300 mA,
V s - 6 .6
U N IT
ra
24
36
36
6
8
n«
7
12
26
Hlgh-I«val o utp ut voltaga aftar switching
T
MIN
m
ns
mV
82-S
Voltage Comparators
£ 2 National
Sem iconductor
LM139/239/339, LM139A/239A/339A, LM2901.LM3302
Low Power Low Offset Voltage Quad Comparators
General Description
■ E lim in a te s need fo r d u a l sup plie s
The L M 1 3 9 series consists o f fo u r in d e p e n d e n t
p re cis io n voltaqe co m p a ra to rs w ith an o ffs e t v o lt ­
age s p e c ific a tio n as lo w as 2 m V m a x fo r a ll fo u r
c o m p a ra to rs. These w e re designed s p e c ific a lly to
ope ra te fro m a single p o w e r s u p p ly o ve r a w id u
range o f voltages. O p e ra tio n fro m s p lit p o w e r
supplies is also possible and the lo w p o w e r s u p p ly
c u rre n t d ra in is in d e p e n d e n t o f th e m a g n itu d e o f
the p o w e r supply volta g e. These c o m p a ra to rs also
have a u n iq u e c h a ra c te ris tic in th a t th e in p u t
c o m m o n -m o d e voltage range in clu d e s g ro u n d ,
even th o u g h operated fro m a single p o w e r s u p p ly
voltage.
■ A llo w s sensing near g nd
■ C o m p a tib le w ith a ll fo rm s o f lo g ic
■ P ow er
d ra in
su ita b le
fo r
b a tte ry
■ W ide sin g le s u p p ly v o lta g e range o r d u a l s u p ­
plie s
L M 1 3 9 series,
2 V q c to 3 6 V q c o r
L M 1 3 9 A series, L M 2 9 0 1 i l V q c to ± 18 V q c
LM 3302
2 V D C to 2 8 V p c
o r i l V q c to ±14 V q c
■ V e ry lo w s u p p ly c u rre n t d ra m (0 .8 m A ) in d e p e n d e n t o f s u p p ly vo lta g e (2 m W /c o m p a ra to r a t +5 V D C )
A p p lic a tio n areas in clu d e lim it c o m p a ra to rs , s im p le
analog to d ig ita l co n ve rte rs; pulse, sq uarew ave a nd
tim e d e la y generators; w id e range V C O , M O S c lo c k
tim e rs ; m u ltiv ib ra to rs a nd high vo lta g e d ig ita l lo g ic
gates. T h e LM 139 series was designed to d ire c tly
in te rfa c e w ith T T L and C M O S. W hen o p e ra te d
fro m b o th plus and m in u s p o w e r su p plie s, th e y
w ill d ire c tly interface w ith M O S lo g ic - w h e re th e
lo w p o w e r drain o f th e L M 3 3 9 is a d is tin c t a d v a n ­
tage o ve r standard co m p a ra to rs.
■ L o w in p u t b ia s in g c u rre n t
25 n A
■ L o w in p u t o ffs e t c u rre n t
and o ffs e t vo lta g e
±5 n A
±3 m V
•
In p u t c o m m o n -m o d e vo lta g e range in clu d e s g nd
■ D iffe r e n tia l in p u t vo lta g e range e q u a l to th e
p o w e r s u p p ly vo lta g e
■ L o w o u tp u t
s a tu ra tio n vo lta g e
Advantages
2 5 0 m V at 4 m A
■ O u tp u t vo lta g e c o m p a tib le w ith T T L , D T L ,
E C L, M O S and C M O S lo g ic system s
H ig h precision c o m p a ra to rs
R educed Vqs d rift over te m p e ra tu re
Schem atic and Connection D iagram s
Dual-In-Lina and F lit Packaga
LM 239J, LM 239AJ, LM339J,
LM 339AJ, LM2901J or LM3302J
Sm NS Packaga J14A
Ordar Numbar LM 339N, LM 339AN ,
LM 2901N or LM 3302N
Saa NS Packaga N14A
Typical Applications
B a n c C om p ara tor
o p e ra tio n
Features
<v+ = 5.0 v DC)
D riv in g C M O S
5 27
D riv in g T T L
62-S
T y p ic a l
I
|
I
2
9
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= 3
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t ■8i l3 ;S. ?S i-
§ < i O o
| S
x
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~ ^
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Output Saturation Voltage
1.0
(C o n tin u e d )
u? * o
(i i ! r ;
I =•2 w£
£g *•
p ? Ii I I I I
i?:H i|
a * 3 3- e » r
lm i3 9 / lm 2 3 9 /lm 3 3 9 , lm i3 9 a / lm 2 3 9 a / lm 3 3 9 a , L M 3 3 0 2
Supply Current
SUPPLY VOLTAGE (V qc )
' A ~ ^ <♦*ft5 tt2 '
3 < o < 9-. -
C h a r a c te r is tic s
C h a r a c t e r is tic s
if tf| IlffIII!
tfO o
S ^ O
I
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1
E le c t r ic a l
■i r>*
a j.*
P e rfo rm a n c e
V * - SUPPLY VOLTAGE (Voc)
Response Tima for Various
Input Ovardrivas — Positiva
Transition
Response Tima for Various
Input Overdrives — Negative
Transition
Sr • < •t 5 =• *
5 ~
=
S s
- sr *
5
* 5
S 5 I
$ - ~ r
3^2
c 3
:s ?
10
l 0 - OUTPUT SINK CURRENT (mA)
> -
i
>0
8 ? 5
“
¥ 2 9- - * £ S
8
o
=?s l i g l
§■I f I § - “
S « I
5. s 8. ?
■2 i l
d ? - •
nil***
05
1.0
15
2.0
05
1.0
15
20
TIME («^c|
8
<=>
T y p ic a l P e r fo r m a n c e
C h a r a c te r is tic s
LM 2 9 0 1
f i l l 11s
Output Saturation Voltaga
- I sIs f-
I I
| J * !
2
J H
!!,§
1
| |
gfti :fa
1
s i 1 1 fi Sf
3 S' 3
*
C O ft
H! I i! 1
-
c
I= *O2-*•
.
. =5
10
g C •
20
31
40
V*. SUPPLY VOLTAGE (V *-)
V*. SUPPLY VOLTAGE IV0c>
til
H
* “
Response Tima for Various
Input Overdrives-Positive
T ransition
Response Tima for Various
Input Overdrives-Negative
T ransition
i
9
? 2
15
? ! I S
ex
o
S£ l ? O fa. ! i |
n
<
r
m
3£
i t |
3 0 ?
$ 5 8-
8
o*
i5
05
10
IS
70
I*
d *
2 O
l 0 . OUTPUT SINK CURRENT ImA)
5 30
SER IES C 45
TELEDYNE SOLID STATE
CHARACTERISTIC CURVES
SERENDIP®
AC SOLID STATE RELAY
|
|
J-- j
!
1
|1
|
£ s
Cel*13,' fn.-3i.-43l
!
OPTICALLY ISOLATED
1.0 Arms
l
V -« rc
*5
31*
31
ac
‘—■I— r —
3
VOLTS
TYPICAL CONTROL CURRENT VS. VOLTAGE
FIGURE 1
FEATURES/BENEFITS
• Optical Isolation Itolitos control elements (ram load tramlonti.
P/UtT
NUM KR
RELAY DCtCfflFTNM
C45
Solid State Relay with Terminals For Through Hole Mount
SC45
Solid State Relay with Terminals For Surface Mount
• Low off stata laakaga currant For high off stats Impadanca.
• Switches high and low voltages and currants Switches voltagas from 20 to 250 Vrms
Switches currants from 10 to 1000 mArms
• High nolsa immunity Control circuit cannot be triggered by output
switching noise.
• High dielectric strength For safety and for protection of control and signal level
circuits.
• Meets design requirements of UL, CSA, and VOE 0884Hlghest quality for commorelal/tnduatrial part.
Approval pending.
• Switches resistive or reactive loads to 0.2 P.F. Broad Load Switching Capability.
DESCRIPTION
(2S*C UNLESS OTHERWISE SPECIFIED)
in p u t s p e c if ic a t io n s i s m
Input Currrent (See Note 4)
Input Voltage (See Note 4)
Turn Oft Current
Turn On Current
nn™ « 1 » *)
MM
MAX
C45-11,-21
5.0
500
mi
C45-12. -22
100
500
me
C45-13. -23
N/A
VOLTS
C45-11.-21
N/A
C45-12. -22
N/A
TYPICAL CONTROL CURRENT VS. VOLTAGE
FIGURE 2
C45-13, -23
35
C45-11,-21
C45-12, -22
7.0
m m
U<
me
50.0
C45-12,-22
100
50.0
ma
0.5
VOltl
Turn On Voltage
C45-13,-23
3.5
m
s,
volts
1.0
Arms
280
Vrm*
47
S50
Hz
On State Voltage Drop at Rated Current
1.5
Vrm*
Zero Voltage Turn On
10
Load Voltage Rating
Frequency Range
Surge Current Rating (non-repetttlve 20 ms
maximum) (See Figure 3 4 Note 1)
8
1.0 mArms
Turn-On Time
1/2
1/2
Over Voltage Rating
m ounting with minim um space utilization.
Thermal Resistance
C45-11.-12. -13
400
C45-21.-22. -23
500
Dielectric Strength (Input to Output)
Isolation (Input to Output)
Capacitance (Input to Output)
0(1
Vnns
10»
Ohms
Pf
50
A*S
Output SCR's Dissipation Factor
1.0
Watt/A
125
•c
•c/w
•c/w
Temoerature (Ti Maximum)
60
eJA
..
-
35
70
SO
90
100
110
"y
(H /W S
“ J#
*y
Series retWw required
•USE THE TABLE BELOW FOR SELECTION Of PROPtR METAL OXIOI
VARISTOR (MOV)
cycle
Fusing l*T (1 ms)
D niniit KHR
Operating Temperature Rang# -40*C to 100*C
Storage Temperature Rang* -40*C to 100*C
Lite t0 '° operations fuM rated load. 25*C
Vibration 20 g Level. 10 to 2.000 Hz
Shock: Meet* or exceeds MIL-STD-202
Weight 2 0 grams max
Case 18 ptn dual inline (TO-116)
Case Material Filled epoxy - sett-extlnguttMng
Vpeak
100 V/psec
Stale dv/dt
vtt
*LU
cycle
4000
10
't
A
Oft State Leakage at Maximum Operating Voltage
Turn-Oft Time
«0
TYPICAL INTERFACE TO SV LOGIC
(with suggested transient voltaga
and dv/dt suppression, If required)
• r-o o w ’ SI!
________ Stl
>»' T E L E D Y N E
S O L ID S T A T E
M B
0.01
Load Current (See Figure 4)
SO
LOAD CURRENT VS. TEMPERATURE
FIGURE 4
MECHANICAL SPECIFICATIONS
volte
-7
Reverse Voltage Protection
OUTPUT SPECIflCATIONS ( S e e lM a e t l
40
AMBIENT TEMPIAATURE (*C)
-OATtcoa
50
C45-13. -23
30
volts
10.0
C45-11. -21
Turn Oft Voltage
The C45 Series employs back-to-back photo SCRs and a
patented zero crossing circuit. The tight zero switch w indow
ensures reliable transient tree switching of AC loads and very
low EMI and noise generation. Optical isolation of control
from output prevents sw itching noise from coupling into
signal, power and ground distribution system s fo r noise free
power switching. This series of solid state relays will switch
from 10 ma to 1.0 amp rm s at 280 Vrm s. The C45 is
packaged in a low profile 16 pin Dual In-Line package lo r PC
DIMENSIONS
ARE SHOWN
IN INCHES
(MIlllMCTtR)
• Tolerances
(unless otherwi
specified)
. 015(38)
MAXMUM
CONTINUOUS
LINEVOLTAflC
RATMS
TWUMNT
(P*AK)
RATMSOf
RELAY
miirrwr.f
MOV i
rm
140Vac
250Vac
400
600
970-1
970-2
(SEE 970 SERIES DATA SHEET FOR FURTHER INFORMATION ON MOV S)
FIGURE 5
NOTES:
1 SCR may lose blocking capability during and after surge until Tj falls below 100*C maximum
2 RC snubber is recommended but is not required
3 Minimum Load Power Factor - 0 2 (Capacitive or Inductive) Lower power factors will damage relay
4 Operation load frequencies above 70 H/ requires increased input signal Minimum input voltage is 5 Vdc for C45-13. -23
Minimum input current is 7 5 ma lor C45-11 -21 and minimum input current is 15 ma for C45 12. 22
6 /9 3
6 /9 3
SURGE CURRENT VS. DURATION
FIG U R E !
/ ~ 'A
ELECTRICAL SPECIFICATIONS
• Floating output Ellmlnitat ground loop* and signal ground nolto.
• Zaro voltaga turn on, Zero currant turn oft Minimum switching translant nolaa and extremely low
EMI.
'
SP EC IFIC ATIO NS ARE SU BJE C T TO CHANQE W ITHO UT NOTICE.
© 1993
-JtCTELEDYNE SOUD STATE
IHI J
Mow4yvr» Lolilo't'o WJ50
(713) 177 OOII
Voltage Comparators
^ 3 National
muiSem iconductor
LM193/LM293/LM393, LM193A/LM293A/LM393A, LM2903
Low Power Low Offset Voltage Dual Comparators
General Description
E lim in a te s need fo r d u a l su p plie s
T he L M 1 9 3 series con sists o f tw o in d e p e n d e n t p re cis io n
voltage co m p ara to rs w ith an o ffset vo lta g e s p e c ific a tio n
as lo w as 2.0 m V m a x fo r tw o c o m p a ra to rs w h ic h w ere
designed sp e c ific a lly to operate fr o m a single p o w e r
s u p p ly o ve r a w id e range o f voltages. O p e ra tio n fro m
s p lit p o w e r supplies is also possible and th e lo w p o w e r
s u p p ly c u rre m d ra in is in dependent o f th e m a g n itu d e
o f th e p o w e r s u p p ly voltage. These co m p a ra to rs also
have a u n iq u e c h a ra c te ris tic in th a t th e in p u t c o m m o n ­
m ode voltage range includes g ro u n d , even th o u g h
o pe ra te d fro m a single p o w e r supply vo lta g e .
A llo w s sensing near g ro u n d
C o m p a tib le w ith all fo rm s o f lo g ic
P ow e r d ra in s u ita b le fo r b a tte r y o p e ra tio n
Features
*
A p p lic a tio n areas in c lu d e lim it c o m p a ra to rs , sim p le
analog to d ig ita l co n ve rte rs; pulse, squarew ave and tim e
d ela y generators; w id e range V C O ; M O S c lo c k tim e rs ;
m u ltiv ib ra to rs and h ig h voltage d ig ita l lo g ic gates. The
L M 1 9 3 series was designed to d ire c tly in te rfa c e w ith
T T L a nd CMOS. W hen operated fro m b o th p lu s and
m in u s p o w e r su p plie s, th e L M 1 9 3 series w ill d ire c tly
in te rfa c e w ith M O S lo g ic where th e ir lo w p o w e r d ra in
is a d is tin c t advantage o v e r standard c o m p a ra to rs .
W id e single s u p p ly
V o lta g e range
o r d u a l su p plie s
2 .0 V DC to 3 6 V DC
± 1 .0 V DC to ± 1 8 V DC
■ V e ry lo w s u p p ly c u rre n t d ra in (0 .8 m A ) —in d e p e n ­
d e n t o f s u p p ly v o lta g e (1 .0 m W /c o m p a ra to r a t
5 .0 V D C )
■ L o w in p u t b ia s in g c u r re n t
25 n A
■ L o w in p u t o ffs e t c u rre n t
and m a x im u m o ffs e t vo lta g e
■ In p u t c o m m o n -m o d e vo lta g e range in c lu d e s g ro u n d
■ D iffe r e n tia l in p u t v o lta g e range equal to th e p o w e r
s u p p ly vo lta g e
■ L o w o u tp u t
2 5 0 m V at 4 m A
s a tu ra tio n v o lta g e
■ O u tp u t v o lta g e c o m p a tib le w ith T T L , D T L , E C L ,
M O S and C M O S lo g ic system s
A dvantages
■ H igh pre cisio n co m p a ra to rs
■ Reduced V o s d r if t over tem p e ra tu re
Schem atic and Connection D iagram s
Typical Applications
Basic Comparator
±5 n A
±3 m V
iv + = 5 o v oc)
Driving CMOS
5 41
Driving TTL
CfrS__________
'
£
z
<
O
!
"
i
I
\
1
8
'
.
f
-
1
° <
1
°
♦
2
f
s
5
t
10
R n p o n u T im * fo r Various
In p u t O vardrivat - Nagaliva
Transition
TYP
MAX
40
300
TYP
MAX
40
400
1150
700
V+-2 0
LM293A. LM393A
MIN
Typical Perform ance C h aracteristics LM2903
O u tp u t S aturation Voltaga
MIN
K
— <o
8
8
MAX
w
LM19J
TYP
<
|*
^
0
10
M
)•
40
V . SUPPLY VOLTAGE (Vocl
0
9
400
1150
700
V *-2 .0
36
10
Ratponaa Tim a fo r Various
In p u t O vardrivat—Nagativa
T ra n titto n
l a . OUTPUT SINK CURRENT ImAI
Ratponaa Tim a fo r V a rio u t
In p u t O vardrivat—P otitiva
T ra n titio n
MIN
15
MAX
3
3
B
o
o
>
o
o
<
o
o
:
05
1.0
II
2.0
UNITS
TYP
>
200
o
o
9
<
500
o
o
200
700
<
V * -20
o
o
50
400
o
o
r
1
I
i
z
> >
X
0
28
10
<
9
V , SUPPLY VOLTAGE (Voc)
z
5
t
>
Ratponta Tim a fo r Various
In p u t O vardrivat — P otitiva
Transition
>—
0
"j
8
l0 - OUTPUT SINK CURRENT ImAI
5>
•100
700
—
O
V* - SUPPLY VOLTAGE (Voc)
1
V *-2 0
10
36
°>
10
LM193A
36
1
Inp u t Currant
V ’ - SUPPLY VOLTAGE (Voc)
1
O
CJ
Supply Currant
MIN
8
o
_
0
1
5
2
Typical Perform ance C haracteristics LM193/LM293/LM393. lmi93a/lm293a/lm393a
(C o n tin u e d )
0
?
CONDITIONS
-
5
IV
Electrical Characteristics
»
PARAMETER
5
Input Offset Voltage
3
00 >
Input Offset Current
f
Input B>as Current
5 £ 2 • •
Input Cotnmon-Mode Voltage Range
|< +8 f f
Saturation Voltage
& •
Differential Input Voltage
£ •
Output I edkage Current
f?
5-44
□
01 CMOS
ANALOG
DEVICES
SPE C IF IC A T IO N S On* +1
P r o t e c t e d A n a lo g S w itc h e s
M ODEL
V E R SIO N
*2J*C
(N , P. Q, E)
A ll
A ll
J .K
J .K
7 5 ft typ, 100ft max
20% typ
R o n D rift
R q i ^ Mttch
A ll
A ll
J. K
J .K
♦0.5%/*C typ
1% typ
Rq h Drift
Match
A ll
J .K
0.01%/*C typ
I d (I s k jp p 1
A ll
J .K
0.5nA typ, 5nA max
Id d s to N 1
AU
J .K
lOnA max
lOUTl
AD7512DI
J. K
15nA
AU
AI1
AII
AII
J .K
AU
AII
J .K
A D 7 ] 10DI
AD7511DI
AD7S10DI
AD 7511DI
J .K
J .K
J .K
J .K
ISOns
150ns
550ns
180ns
't r a n s it io n
A D 7 5 IZ D I
J .K
500ns typ
Cj CCd XJFF
All
AU
J .K
J .K
8pF typ
17pF typ
A ll
J .K
J .K
J .K
lp F typ
0.5pF typ
!7 p F typ
PA R A M E TE R
A D 7 5 1 0 D I/ A D 7 5 1 1 DI/AD7512DI
‘
R0 N "
V -
At [T
«E
-E
m
[T
mc(T
AO 711001
Aomen
01
r3 '
- J—ill1 I
,L“C
> V u—1].
;
vw w
I inm«*
rn .
i .. vr 3 '
W
,
v in h '
VdoE
NC - NOCONMCT
NC - NOCOMNfCT
VlMAHYU
CO N TRO L LOGIC
AD7510DI: Switch "O N ” for A ddraji “ HIGH”
t*y
W *'
w '
*ON
AD7J12DI: Addresa “ HIG H ” make* S I to O u t l^ O ^ J J jy ,
lOPP
° ut2
~
P IN C O N F IG U R A T IO N S
LCCC
/(V
............* v j -
•.„<
' ^
/rr1
Cj (C pJO N
c ds
i
(C s - o ir r *
Cdd (Css)
5
5
cout
Temperature Range and Package
- 25*C to
+ 85*C
- 55*C to
+ 125°C
Plastic D IP
Hermetic
Hermetic
AD7510DIJN
A D 7510 D IK N
AD 7511DIJN
A D 7511 D IK N
AD7512D1JN
A D 7 5 I2 D IK N
AD7510DIJQ
AD 7510DIKQ
AD7511DIJQ
AD 7511DIKQ
AD7512DIJQ
AD 7512DIKQ
AD7510DISQ
A D 7510D ITQ
A D 7511D ITQ
AD7512DISQ
A D 7512D ITQ
Oto +70*C
PLCC*
LCCC*
AD7510D1JP
AD 7510D IKP
AD7511DIJP
AD 7511D IKP
AD7512DIJP
AD 7512D IKP
AD7510D1SE
AD7511DISE
AD 7511D ITE
AD7512D1SE
AD 7512D ITE
1? 01
17 NC
I t NC
II M
I I S3
I I NC
max
500nA max
>DS * 10 m A
V „ - -1 0 V , V , - *1 0 V and
v D - + 10V, Vs • -10V
V j ■ v D ■ ♦10V
V S - V D • -1 0 V
ISOOnA
max
VS1 ■ v o ir r ■ ±1 0 V - v s i ’ * l o v
and V „ - VOVT - ±10V , V „ - *1 0 V
14 03
14 OUT ;
j I n »
s
0.8V
5.0V
2.4V
J
K
max
min
min
7pFtyp
max
max
J .K
lO nA
lO nA
J. K
AU
AD 7512D I
J .K
typ
typ
typ
typ
vw -
o to V i.o y , iV’ ■;
”
:'o
... V 1 i...
..
•
VD ( V , ) .
v '- K *
'<*13
■..•*.»! •t :
* y*>
;i G
r;:q-f!
j » v «»(
1oV
V ' M il)
n b
tfC M .)
1?
Measured at S or D terminal.. , , u i ‘
- lOOOpF, V M • 0 to 5V,
VD <VS) • ♦ lO V to .- IO V .
30pC typ
i
n r>rn
t ;.v t
POWER SU PPLY
*d q '
V
i
VD ‘
AII
II n
ORD ER ING IN F O R M A T IO N 1
4)5 ” 1.0mA
D Y N A M IC
C H A R A C T E R IS T IC S
AD7511DI: Switch “ O N " for Address "L O W ” '
>*
-1 0 V < v D < + 10V
D IG IT A L C O N T R O L
tot
§
175ft max
■ 1
Very low power dissipation, overvoltage protection and TTL/
CMOS direct interfacing are achieved by combining a unique
circuit design and a dielectrically isolated CMOS process.
Silicon nitride passivation ensures long term stability while
monolithic construction provides reliability.
dNoQT
V D <VS>
O
> °o
The AD7J10DI and AD7J11DI consist o f four independent
SPST analog switches packaged in either a 16-pin DIP or a
20-terminal surface mount package. They differ only in
that the digital control logic is inverted. The AD7512DI
has two independent SPDT switches packaged in either a
14-pin DIP or a 20-terminal surface mount package.
v.G L-IS
T E ST C O N D ITIO N S
>2 >2
G EN ERAL DESCRIPTION
The AD7310DI, AD7511DI and AD7512DI are a family o f
latch-proof dielectrically isolated CMOS switches featuring
overvoltage protection up to ±25V above the power supplies.
These benefits are obtained without sacrificing the low “ O N ”
resistance (7 5 ft) or low leakage current (JOOpA), the main
features o f an analog switch.
DIP
0 to +70*C (N , P)
-25*C to t a s ' c (Q )
A N A L O G SWITCH
ron
FEATURES
Latch-Proof
Ovarvol tag*-Proof: ± 2 6V
Low R o n : 7 5 fl
Low Dissipation: 3m W
T T L /C M O S Diract Intarfaca
M onolithic D ielectrically Isolated CM O S
Standard 14/16-pln D IP * and 20-Term inal
Surfaca M ount Packagat
AD7510DI/AD7511DI/AD7512DI
F U N C T IO N A L B LO C K D IA G R A M S
A N D P IN C O N F IG U R A T IO N S
-ISVunlMtatNnitniiaMQ
COM MERCIAL A ND IN D U STR IA L VERSIONS (J. K )
■on'
■ss
A ll
A ll
J .K
JIOOjzA max
800*iA max
800pA max
J. K
All
J. K
J. K
500jiA max
500»iA max
500|iA max
500^A max
AII
A ll d ifiu l inputs •
Vg^
All digital inputs •
VWL
r
SOOfiA max
NC - NO CONNfCt
NC • NOCONNICT
PLCC
P AC K A G E O P T IO N S 1
Plastic (N -14)
Plastic (N -16)
Cerdip (Q -14)
Cetdip (Q 16)
Pl.CC (P 20A)
AD7512DIJN/KN
AD7510DIJN/KN
AD7511DIJN/KN
AD7J12DIJCVKQ
AD75 10DIJQ/KQ
AD75 11DIJQ/KQ
AD7510DIJP/KP
A D 7 5 1 1DIJP/KP
AD75 12DIJP/KP
NOTES
1 100% to ted .
*See Section 13 for package outline inform ttion.
Specification! lubject to change without notice.
r A im n N *
NOTES
'T o order MIL-STD-883, C l»u B proccsjtd parts, add/883B to
p in number. See Analog Devices’ 1987 Military Product Databook
ESD (Electro-Static-Discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subjected to high energy electrosta­
tic fields. Unused devices must be stored in conductive foam or shunts. The foam should be dis­
charged lo the destination socket before devices are removed.
military data sheet.
’ PLCC: Plastic Leaded Chip Carrier.
'LCCC: Leadleas Ceramic Chip Carrier.
CMOS SWITCHES & MULTIPLEXERS 7-9
7 -1 0
C M O S S W IT C H E S 8t M U L T IP L E X E R S
WARNING!
11
y SO 'if NS'TIVI 01 V'»
1
Typical Performance Characteristics
EXTENDED VERSIONS (S, T )
-JJ*C to ♦ I2 J*C
♦2J*C
TEST CONDITIONS
MODEL
VERSION
Ro n '
All
S. T
100(1 max
17511 max
-1 0 V < v D < *1 0V
’ d ( i j >o p f '
All
S. T
JnA max
200nA max
VD - -10V, V , - +10V and
V0 • *1 0V . V , • -1 0 V
I d Os )ON‘
All
S. T
10
1
I
' out
AD7512DI
S. T
9nA max
arameter
NALOG SWITCH
*DS "
V , • V „ ■ *1 0V and
v , ■ v D - -1 0 V
AOOnA max
VS1 ■ VOUT • ±10V
V , j - T10V and
v „ - v 0UT - ±10V
V „ - *10V
DIGITAL CONTROL
All
S. T
0.8V max
AD7J10DI
AD7J1101
AD7512DI
AD751101
AD7S120I
All
All
S
T
T
S
2.4V
2.4V
2.4V
).0 V
).0 V
S, T
S. T
lOnA max
lOnA max
VW ■ VDD
vw -o
AD7J10DI
AD7511DI
AD7510DI
AD7511DI
AD7512DI
S,
S,
S.
S,
S,
1 .0*11 max
10(11 max
1.0(11 max
v w - o Vo * j v
All
All
S, T
S, T
800(iA max
800(iA max
A ll digital in p u ti •
&
All
All
S. T
S. T
5 00(1A max
500(1A max
A ll digital in p u ti •
&
VINL*
W
1’
'(NH,
1 ■
INL
s
r ON • * • Function o f Vq (Vs )
'TRANSITION as • Function o f Digital Input Voltage
min
min
min
min
min
YNAMIC
HARACTERISTICS
tON*
to rr*
'TRANSmON*
T
T
T
T
1 0 (ii max
1.0(ii max
O W E R SUPPLY
'
A C K A G E O P T IO N S 4
C e rd ip (Q -1 4 )
C e rd ip ( Q 1 6 )
l.C C C (E -2 0 A )
A D 7 5 1 0 D IS Q
A D 7 S 1 1 D IS Q /T Q
A D 7 5 1 2 D IS Q /T Q
A D 7 5 1 0 D IS E
A D 7 5 1 1 D IS E /T E
A D 7 5 1 2 D IS E /T E
RON a* a Function o f Vq (V$)
tQ/y t g p p as a Function o f Temperature
S8 8 85
1
■-
OTES
100\ tested.
A pullup resistor, typically l-2kfl is required to make AD 7S11D ISQ and AD 7512D ISQ T T L compatible.
Guaranteed, not production tested.
See Section 13 for package outline information,
pecifications subject to change without notice.
ABSOLUTE M A X IM U M R A T IN G S *
' d d w G N D .......................................................................
+17V
' s s t o G N D ...................................................................................
-1 7 V
)vervoltageat V D (V S)
(1 second surge) ..................................................
V Dn + 25V
o rV s s -2 5 V
(Continuous)
.........................................................
V p o + 20V
o rV s s - 2 0 V
Switch Current (Ins> C ontinuous)......................................50mA
iwitch Current ( I DS>Surge)
1ms Duration, 10% Duty Cycle ...................................150mA
digital Input Voltage Range ........................ CV to V n n + 0 .3 V
’ ower Dissipation (Any Package)
Up to + 7 5 ° C ........................................................ 450mW
Derates above + 7 5 ^ b y .......................................6mW/°C
Lead Temperature (Soldering, lO s e c )........................ + 300°C
Storage T em p eratu re.................................-65*C to + 150°C
Operating Temperature
Commercial (JN, K N , JP, KP Versions) . . . .
0 to +70°C
Industrial (JQ, KQ Versions).................. -2 5 “C to +85°C
Extended (SQ, T Q , SE, TE Versions) . . -55°C to + U S X
,S’ ^D^OFF w VS
•Streiiet tbove thoie lilted under "Abiofu te Maximum Ratings" miy
c iu x permanent damage to the device. Thil ii • itreti rating only and
functional operation o f the device at theie or any other conditioni above
those indicated in the operational lectioni o f thil ipeciflcation ii not
implied. Expoiure to absolute maximum rating conditioni for extended
period* may affect device reliability.
CMOS SWITCHES & MUL VPLEXERS 7-11
7^12 CMOS SWITCHES A MULTIPLEXERS
*TRANSITION as a Function o f Temperature
Industrial Blocks
Sem iconductor
LM135/LM235/LM335, LM135A/LM235A/LM335A
Precision Temperature Sensors
General Description
to + 1 2 5 ° C te m p e ra tu re range. T h e L M 3 3 5 ope ra te s
fr o m —4 0 ° C to + 100 °C . T he L M 1 3 5 /L M 2 3 5 /L M 3 3 5
are a v a ila b le packaged in h e rm e tic T O -4 6 tra n s is to r
packages w h ile th e L M 3 3 5 is also a va ila b le In p la s tic
T O -9 2 packages.
The L M 1 3 5 series are precision, e a s ily -c a lib ra te d , in te ­
gra ted c ir c u it te m p e ra tu re sensors. O p e ra tin g as a
2 -te rm in a l zener, th e L M 1 3 5 has a b re a k d o w n v o lta g e
d ire c tly p ro p o rtio n a l to absolute te m p e ra tu re at +1 0 m V /
° K . W ith less th a n 1f2 dyn am ic im p ed a nce th e device
operates over a c u rre n t range o f 4 0 0 p A to 5 m A w ith
v ir tu a lly no change in p erform a nce. W hen c a lib ra te d
at 2 5 °C th e L M 1 3 5 has ty p ic a lly less than 1°C e rro r
over a 100°C te m p e ra tu re range. U n lik e o th e r sensors
th e L M 1 3 5 has a lin e a r o u tp u t.
T O -4 6 Package
T O -9 2 Package
S p e c ifie d O p e ra tin g T e m p e ra tu re Range
C o n tin u o u s
LM 135, LM 135A
~ 5 5 ° C to + 1 5 0 ° C
LM 235, LM 235A
- 4 0 ^ to + 1 2 5 °C
LM 335, LM 335A
- 4 0 ° C to + 1 0 0 ° C
Lead T e m p e ra tu re (S o ld e rin g , 10 seconds)
- 6 0 ° C to + 1 8 0 °C
- 6 0 ° C to + 1 5 0 ° C
In te r m itte n t (N o te 2)
150°C to 2 0 0 ° C
125°C to 1 50°C
100 °C to 1 2 5 ° C
300° C
T em peratu re A c c u ra c y LM135/LM235, lmi35a/lm235a (Note d
L M 1 3 5 A /L M 2 3 5 A
C O N D IT IO N S
M IN
D ir e c tly c a lib ra te d in “ K e lv in
O perating O u tp u t Voltage
T c ■ 25 C, I r * 1 m A
1°C in itia l a ccu racy a va ila b le
U n ca lib ra te d Tem perature E rro r
T c * 25°C , I r * 1 m A
U n ca lib ra te d Tem perature E rror
Tem perature E rro r w ith 25°C
O p e ra te s fr o m 4 0 0 m A to 5 m A
Less th a n 1f2 d y n a m ic im p e d a n c e
The L M 1 3 5 ope ra te s over a - 5 5 ° C to + 1 5 0 °C te m p e r ­
a tu re range w h ile th e LM 23 5 ope ra te s over a —4 0 ° C
15 m A
10 m A
PARAM ETER
Features
A p p lic a tio n s fo r th e L M 1 3 5 in clu d e a lm o s t a ny ty p e o f
te m p e ra tu re sensing o ve r a -5 5 ° C to + 1 5 0 °C te m p e r­
a tu re range. T he lo w im pedance a nd lin e a r o u tp u t
m a ke in te rfa c in g to rea d o ut o r c o n tro l c ir c u itr y espe­
c ia lly easy.
Absolute Maximum Ratings
Reverse C u rre n t
F o rw a rd C u rre n t
S to ra g e T e m p e ra tu re
E a s ily c a lib ra te d
W id e o p e ra tin g te m p e ra tu re range
C a lib ra tio n
2 0 0 ° C overrange
C alibrated E rro r at Extended
L o w cost
Tem peratures
N o n -L in e a rity
Sch em atic Diagram
2.97
TY P
MAX
L M 1 3 5 /L M 2 3 5
U N IT S
M IN
TY P
MAX
2.95
2.98
3.01
1
3
2.98
2.99
0.5
1
Tm IN < T C < T MA X .IR “ 1 mA
1.3
2.7
2
5
T m IN < T c < T m a x , I r => 1 m A
0.3
1
0.5
1.5
0.3
0.5
0.3
T C * T M A X (In te rm itte n t)
Ir * 1 mA
°C
T em peratu re A c c u ra c y LM335, LM335A (Noteu
PARAM ETER
LM 335A
C O N D IT IO N S
L M 33 5
U N IT S
M IN
TYP
MAX
2.95
2.98
3.01
2.98
3.04
1
3
2
6
°C
M IN
TY P
M AX
O perating O u tp u t Voltage
T c * 25°C ,
U n ca lib ra te d Tem perature E rror
T c * 25°C , I r * 1 mA
U n ca lib ra te d Tem perature E rror
TmiN<Tc<TmaX.'R" 1mA
2
5
4
9
°C
Tem perature E rro r w ith 25°C
T M I N < T c < T M a X . I r * 1 mA
0.5
1
1
2
°C
T c * T m a x (Interm ittent!
2
I r * 1 mA
0.3
Ir
“ 1 mA
2.92
V
C a lib ra tio n
C alibrated E rro r at Extended
2
°C
0.3
°C
Tem peratures
N o n -L in e a rity
Electrical C haracteristics
(N o te 1)
PARAM ETER
Basic T e m p e ra tu re Sensor
C O N D IT IO N S
L M 1 3 5 /L M 2 3 5
LM 3 3 5
L M 1 3 5 A /L M 2 3 5 A
LM 335A
TYP
Typical Applications
W ide O p e ra tin g S u p p ly
C a lib ra te d Sensor
O perating O u tp u t Voltage
4 00 *j A < I r < 5 m A
Change w ith C urrent
A t C onstant Tem perature
D yn a m ic Im pedance
Ir
IV-M V
T im e C onstant
-v m
f
t
T im e S ta b ility
* C a lib ra te t o r 2 9 8 2 V a t 25' C
MAX
TY P
U N IT S
MAX
2.5
0.5
* 1 mA
O u tp u t V oltage Tem perature
D r ift
OUTPUT n
1.5
0.6
+ 10
m V /°C
S till A ir
80
80
sec
100 ft/M in A ir
10
10
see
S tirre d O il
1
1
T C * 125‘ C
0 2
Not# 1: A c c u r a c y m e a s u re m e n ts are m a d e in a w e ll- s tirre d o il b a th F o r o th e r c o n d itio n s , s e ll h e a tin g m u s t be c o n s id e re d
N ot* 2: C o n tin u o u s o p e ra tio n a t the se te m p e ra tu re s f o r 1 0 ,0 0 0 h o u rs f o r H p a cka g e a n d 5 .0 0 0 h o u rs fo r 2 p a cka g e m a y decrease
a n c y o f th e d e v ic e
9-25
n
+ 10
__
sec
° C /k h r
OP-IO
DUAL MATCHED INSTRUMENTATION
OPERATIONAL AMPLIFIER
is p rovid ed betw een ch a n n e ls of the dua l o p e ra tio n a l
am plifier.
FEATURES
. Extrem ely T ig h t M a tc h in g
• E x c e l le n t In d iv id u a l A m p lifie r P a r a m e te r *
.
•
.
•
•
0 « » * ‘ V o lta g e M a t c h .......................
O flM « V o lta g * M a tc h v * T a m p .
c o m m o n -M o d * R * |* c tlo n M a tc h
Pow er S u p p ly R e je c tio n M a tc h
B lat C u rre n t M a tc h ........................
The exce lle n t s p e c ific a tio n s of the in d iv id u a l am p lifie rs
and tig h t m a tc h in g over tem p era ture enable c o n s tru c tio n of
h ig h -p e rfo rm a n c e in s tru m e n ta tio n am p lifie rs. The designer
can achieve the guaran teed s p e c ific a tio n s because the
comnpon package e lim inates tem p e ra tu re d iffe re n tia ls w h ic h
o c c u r in designs using separately housed am plifiers.
.. 0.18mV M a x
0.8*»V/°C M a x
. . . 114d8 M in
. . . 100dB M in
. . . 3 .0 n A M a x
. O.B^Vp.p M a x
. . . 3 .0 n A M a x
. . 2 0 0 0 (1 T y p
• Low N o l a e .............................................
• l o w B laa C u rre n t ...............................
• High C o m m o n -M o d e In p u t Im p e d a n c e
• Excellent C h a n n e l S e p a ra tio n ............................. 1 2 6 d B M in
M atch ing between c h an nels is provid ed on all c ritic a l param ­
eters in c lu d in g offset voltage, tra c k in g o f offse t voltage vs.
tem p era ture, non in ve rtin g bias curre nts, and c om m o n -m o d e
and p ow er-sup ply re je c tio n ratios. The in d iv id u a l am plifiers
feature extre m ely low offset voltage, offset voltage d rift, low
noise voltage, low bias c u rre n t, in te rn a l c om pensa tion and
in p u t/o u tp u t protection.
ORDERING INFORM ATION?
V0 8 MAX
(mV)
H E R M E T IC
D IP
14-P IN
O P E R A T IN G
T E M P E R A TU R E
RANGE
0.5
0.5
0.5
05
OPIOAY’
OPIOEY
O P IO V
QP10CY
MIL
COM
MIL
COM
Ta » 2 5 ‘ C
t
P IN C O N N E C T I O N S
OP-tO DUAL MATCHED INSTRUMENTATION O PERATIONAL AMPLIFIER
A B S O L U T E M A X IM U M R A T IN G S
PAR AM ETER
SYMBOL
In p u t O ffs e t V o ltag e
v os
L o n g -T e rm In p u t O ffset
number. Con»ult factory lor 883 d a ta sheet,
Burn-in is a vailable on com mercial and Industrial te m p eratu re ran g e parts In
CerOIP. plastic DIP. and TO -ca n p a ck ag e s For ordering Inform ation, see
7T] *in iai
v - i.. [7
To] - in iai
out
1990/91 Data BooK, Section 2
iai [ T
v .ie > ( T
3
14-PIN C E RA M IC DIP
( Y - S u f f lx )
n u l l iai
AV o s /T im e
G E N E R A L D E S C R IP T IO N
The OP-IO series ol dua l-m atched in stru m e n ta tio n ope ra­
tional am plifiers consists of tw o in d e p e n d e n t m o n o lith ic
high-performance operational a m p lifie rs in a s in gle 14-pin
dual-in-line package. T ight m atch ing of c ritic a l param eters
D e v ic e m a y tw o p e ra te d ev e n II In s e rtio n I t reversed: th is I t d u e to
in h e re n t s y m m e try of pin lo c a tio n ! of a m p lifie r * A an d B.
M IN
-
.N o te s 1 .2
O P -IO A
TYP
02
MAX
05
0 25
1.0
M IN
-
O P -IO
TYP
02
MAX
U N IT S
05
mV
M\J, M o
025
10
-
10
28
-
10
28
nA
In p u t B ias C u rre n t
>»
-
11
23
-
11
23
nA
In p u t N o lte V o ltag e
®np-p
■Note 2 0 1H z to 10Hz
-
0 35
06
-
0 35
06
A*Vp. p
103
180
—
103
18 0
•n
f G * 10Hz
iN o te 2 i 10 * 100H z
100
13 0
11 0
100
96
13 0
f0 - 1000H z
'np-p
D e n tlty
In
" in
In p u t R e t lt t t n c e —
C o m m o n -M o d e
R|NCM
In p u t V o ltag e R a n g e
IV R
C o m m o n -M o d e R e je c tio n
R a tio
P o w e r S u p p ly R eje c tio n
R a tio
O u tp u t V o ltag e S w in g
iN o te 2 1 0 1H z to 10Hz
-
iN o te 2 1 f o ” 100H z
l 0 * 1000H z
(N o te 3i
VC„ - ± 1 3 V
PSR R
V s = ± 3 V to 1 1 8 V
Avo
Vo
14
30
0 .32
0.14
080
0 12
20
60
113
110
-
-
14
30
0 80
023
0 17
0.12
0.17
-
20
-
114
-
113
126
-
110
126
200
500
150
500
112 5
4
10
60
0 23
p A /v / H z
MO
200
-
0 (1
114
-
V
4
dB
10
200
500
R L £ 5 0 0 II. V0 = 1 0 5V.
Vs « i 3 V i N o te 3
150
5 00
R l 2 10 M )
R L > 2 k ()
± 1 2 .5
113 0
113 0
_
112 0
112 8
-
2 120
2 12 8
-
R l £ 1k (l
110 5
1 1 2 .0
-
110 5
2 12 0
-
_
PA p-p
-
R t > 2 k (l, V0 « 1 10V
-
n W v"H T
11 0
032
0.14
200
CMRR
L a rg e -S ig n a l V o ltag e
G am
96
10 « 10Hz
In p u t N o lte C u rre n t
In p u t R e t lt t t n c e —
D iffe re n tia l-M o d e
T | n u l l iai
•C/W
16
'o s
V o ltag e S ta b ility
In p u t N o l t t C u rre n t
T j] OUT 1*1
]7] v- i*i
• IN (A) ( T
UNITS
" |C
108
NOTES:
1 For supply voltages less than +22V. the absolute m axim um input voltage is equal to
the supply voltage
2 0 A is specified for worst case m ounting conditions, i e 0 A is specified for devtce
In socket for C erO IP package
C O N D IT IO N S
u ] V . 1*1
-IN I * ) ( T
e |A (NOTE 2)
1 4-P in H e rm e tic D IP (Y )
In p u t O ffs e t C u rre n t
D e n tlty
NULL 1*1 ( T
PACKAGE TYPE
I N D I V I D U A L A M P L IF IE R C H A R A C T E R IS T IC S at Vs = * 15V TA = 25°C . unless otherw ise noted
In p u t N o lte V o ltag e
N U L L ,.! ( T
DICE Junction Tem perature ( T ) .....................-6 5 °C to +150°C
Lead Tem perature Range (Soldering, 60 s e c ) ............ +300°C
Supply V o lta g e ..........................................................................±22V
Differential Input V o lta g e ....................................................... ±30V
Input Voltage (Note 1 ) ............................................................. ±22V
Output Short-Circuit D u ra tio n........................................ Indefinite
Storage Tem perature R a n g e ...........................-6 5 °C to +150°C
O perating Tem perature Range
OP-IO A, O P -IO ............................................... -5 5 °C to +125°C
OP-1QE, O P -IO C ...................................................0°C to +70°C
#iV/V
V /m V
-
V
S le w R ate
SR
R l £ 2 k fI
-
0 17
-
-
0 17
_
V /* s
C lo te d -L o o p B an d w id th
BW
AyC l = + 1 0
-
06
-
-
06
-
MH2
R0
Vo - 0 . l o * 0
60
-
60
-
0
E ach A m p lilie r
90
4
120
6
-
90
4
120
-
14
-
-
14
-
mV
-
0
-
-
-
pf
O p e n -L o o p O u tp u t
R esista n ce
P ow er C o n s u m p tio n
Pd
O ffset A d ju stm en t R an g e
In p u t C a p a c ita n c e
VS - 1 3 V
R P * 20k 11
C|N
B
6
mW
NOTES:
1.
5-101
7 /8 9 , R e v . A 2
L o n g -T e rm In p u t O ffs e t V o ltag e S ta b ility refers to th e a v e ra g e d tre n d lin e
0fV0svt. T im e o ver e x te n d e d p e rio d s a fte r th e first 3 0 d a y s of o p e ra tio n
E x c lu d in g th e In itial h o u r of o p e ra tio n , c h a n g e s in V o s d u rin g the first 30
o p e ra tin g days are ty p ic a lly 2.5#iV — re fe r to ty p ic a l p e rfo rm a n c e curves
2
3.
5-102
S a m p le tested
G u a ra n te e d by d esign
7 /8 9 , R e v . A 2
5.0 A P P E N D IX
List o f Relevant N R A O Technical Reports and Technical Memoranda.
V L B A Technical Report No. 1, Low-Noise, 8.4 GHz Cryogenic G ASFE T Front-End, S. Weinreb, H.
Dill and R. Harris, August 29, 1984.
Electronics Division Internal Report No. 204, Temperature Readout Unit for Lake Shore Cryotronics
Silicon Diode Sensors (DT-500 Series), Michael Balister, May 1980.
V L B A Technical Report No. 22, FRO NT-END C O N TR O L M ODULE, Module Type F I 17, Paul Lilie,
Larry May and David Weber, January 1993.
V L A Technical Report No. 68, FRONT-END C O N TR O L INTERFACE, Module Type F14, David Weber,
5/15/93.
Electronics Division Internal Report No. 259, 4.8 GHz 3-stage FET Amplifier.
Calibration o f the vacuum sensors on V L B A and JPL Front-Ends,
memorandum follows this list.)
Post Am plifier Specification N53205N001.
33
Harry Dill, Jan 26, 1987. (This
NOV-14-94 HON 11:20
NRAO VLA SITE
FAX NO. 5057724243
P. 01
Post-It“ brand fax transmittal memo 7671 *<*«>•«•• ►^
tom C P
errv/ f c d r t .
Z> • C7r4yS<7»%t—
Co.
f
Co.
Dept.
Phon##
flu#
Fax#
1
NATIONAL RADIO ASTROI
S o c o r r o , Haw Mexico
J anuary 2 6 ,
TO:
VLBA F r o n t End Maintenance Pe r so nne l
FROM:
Hsrry D ill
SUBJECT*
C alibration
cf
1987
the vacuum s e n s o r s on VLBA and JPL f r o n t
ends*
TOOLS REQD:
Small
flat
b l a d e d screw d r i v e r .
The vacuum s e n s o r c i r c u i t s in the f i e l d have a t endency
to d r i f t
upward o v e r t i m e .
The? cause o-r t h i s i s p o s s i b l y c o n t a m i n a t i o n o f
th e thermocouple.
The e x t en t
of
this
pr ob le m
nee ds
t o be
determined,
and
can
be
dons by keeping a c c u r a t e f i e l d r e p a i r
records.
Two c i r c u i t s e x i s t t e r
s e n s i n g vacuum.
V d - de w ar vacuum
and V p pump vacuum.
J’he.se ( c i r c u i t s are. jcn tha s e n s o r c a r d , which i s th o
s eco nd f r om t h » top i n the- card:; cage.
Each
circu it
h a s two
potentiometers fo r
s e t t i n g a 2 c f u p oi n t and an atmosphere p o i n t .
T he se two s e t p o i n t s *r & coupl ed
t o g e t h e r so
t h a t c ha n g i n g one,
w i l l *lt€?r t h e other' s l i g h t l y .
Outlined
here
is
a
p r o c ed u r e
for
calibration
o f t h e vacuum
s e n so rs in th e -field.
I f t h e s e do not work, than t h e u n i t s h o u l d
be returned
t,o maintenance.
When e ve r t h i s f i e l d c a l i b r a t i o n i s
p e r f o r m e d ft p r o p e r maintenance r e p o r t form s h o u l d be f i l e d .
This
i s t h e o n l y way t h a t d a t a on t h i s problem can b e a c c u m u l a t e d .
PROCEDURE.
1)
The Vp
and Vd thermocouple g a u g e s on t h e f r o n t end w i l l
b e u,sed as t h e r e f e r e n c e p a i n t s f o r ATM and ZERO.
Fo r
t h i s : t o work t h e f r o n t end must be c o l d , T13<25K.
Nnte th e
r e a d i n g s of
Vd, V p,
T15, T50,
T30G) from th e
r e a d o u t panel and r e c o r d them on
t h e mai ntenance s h e e t .
3^
To e h s u r e t h a t t h e s o l e n o i d or t h e r e f r i g e r a t o r w i l l not
be disturbed
during
the
calibration
process,
t h e AC
p o we r
plug,
connected
to
J-l ,
should
be
connected
d i r e c t l y t o t he
refrigerator
power
r e c e p t a c 1o .
This
r e m o v e s power
t o the s o l e n o i d , and b y p a s s e s tho c o n t r o l
c a r d f u r powering t h e r e f r i g c r a t o r .
NOV-14-94 HON 11:20
NRAO VLA SITE
FAX NO. 5057724243
4)
Di sc on nwct t h e vacuum hose -from the
f r o n t wnd and s e a l
if. o f f
.;\f. t h e
pump end
such t ha t o t h e r f r o n t ends can
u s e t h o pump i f r e q u i r e d .
( Dur ing t h e
c a l i b r a t i o n the
pump w i l l t u r n on an o f f depending t h o Vd r e a d i n g . )
5/
Removm t h e
cover
to
th e
car d c « g e (two thumb screw®
l o c a t e d on e i t h e r s i d e
o f the r e a d o u t p a n e l ) a n d l o c a t e
t h e s e n s o r c a r d ( s ec ond from the t o p ) .
Then l o c a t e f o u r
t r i m p o t s l a b e l e d D ZERO, D ATM,
P ZERO and P ATM.
Do
no t
turn
any
other
trim pots
as
t h e y may e f f e c t t h e
c a l i b r a t i o n c«-ftfcthe r e c e i v e r .
6)
With t h e Vx , V>i i s e i t h e r Vd or Vp depe nd ing
upon which
circu it is
being c a l ib r a t e d ,
p l u g connected
t o the Vp
t h e r m o c o u p l e t h e r e a d i n g f o r Vx .should be 10.0.
Tur ning
t h e muLtjUfurn ~~trimpot X ATM, a g a i n X i * w i t h e r P o r D,
s h o u l d b r i n g the r e a d o u t t o 10.0 i f r e q u i r e d .
Note t h a t
the
readout
makers
several
s ec on d s t o s t a b i l i z e a f t e r
t u r n i n g t h e t r i m p a t , s o tu r n i t s l o w l y .
7)
Connect t h e Vx p l u g t o t h e Vd t h e rm o co u pl e .
The r e a d i n g
for
Vx
should
be
0.0.
A d j u s t X ZERO to b r i n g t h i s
r e a d i n g t o £5. £•+-/~ . 0 03 .
8>
Recheck t h e
ATM r e a d i n g
sstspis 6 and v .
9)
Rec onnect t h e
vacuum l i n e .
reconnect.
p l u g s Vp and Vd
properly.
R e p l a c e t h e c ar d cage c o v e r *nd re co nnec t t h e
AC power t o J —1 and t h e r e f r i g e r a t o r AC power t o i t s e l f .
and ZERO
r e a d i n g by r e p e a t i n g
NOTES
ci>
A r e a d i n g o f Vd
>. 430
will
activate
a pump r e q u e s t .
This
will
be
activated
at
all
ti mes u n l e s s th© f r o n t end i a
commanded t o t h e OFF mode.
I f the
f r o n t end
i s issuing
a pump
r e q u e s t and i s c o l d and r u n n i n g p r o p e r l y then t h i s i n d i c a t e * t h a t
t h e v a c u u m sransnr has drifted upward.