RTL8309G-GR
SINGLE-CHIP 9-PORT 10/100MBPS
SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
18 Dec 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8309G
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for use by the software engineer when programming for Realtek RTL8309G
switch controller chips.
Though every effort has been made to assure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
1.2
Release Date
2008/08/12
2008/08/22
2009/12/18
Summary
First release.
Correct operating temperature.
Update thermal characteristics.
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Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................4
3.
SYSTEM APPLICATIONS...............................................................................................................................................5
4.
BLOCK DIAGRAM ...........................................................................................................................................................6
5.
PIN ASSIGNMENTS .........................................................................................................................................................7
6.
7.
5.1.
PACKAGE IDENTIFICATION ...........................................................................................................................................7
5.2.
PIN ASSIGNMENTS TABLE ............................................................................................................................................8
PIN DESCRIPTIONS.......................................................................................................................................................10
6.1.
MEDIA CONNECTION PINS .........................................................................................................................................10
6.2.
MII PORT MAC INTERFACE PINS...............................................................................................................................11
6.3.
MISCELLANEOUS PINS ...............................................................................................................................................12
6.4.
PORT LED PINS .........................................................................................................................................................13
6.5.
SERIAL EEPROM AND SMI PINS ..............................................................................................................................16
6.6.
STRAPPING PINS .........................................................................................................................................................16
6.7.
POWER PINS ...............................................................................................................................................................19
EEPROM REGISTER DESCRIPTION.........................................................................................................................20
7.1.
GLOBAL CONTROL REGISTERS...................................................................................................................................20
7.1.1.
Global Control Register0 .....................................................................................................................................20
7.1.2.
Global Control Register1 .....................................................................................................................................21
7.1.3.
Global Control Register2 .....................................................................................................................................21
7.1.4.
Global Control Register3 .....................................................................................................................................22
7.1.5.
Global Control Register4 .....................................................................................................................................22
7.1.6.
Global Control Register5 .....................................................................................................................................23
7.1.7.
Global Control Register6 .....................................................................................................................................23
7.1.8.
Global Control Register7 .....................................................................................................................................23
7.2.
PORT 0~7 CONTROL PINS ...........................................................................................................................................24
7.2.1.
Port 0 Control 0 ...................................................................................................................................................24
7.2.2.
Port 0 Control 1 ...................................................................................................................................................24
7.2.3.
Port 0 Control 2 ...................................................................................................................................................25
7.2.4.
Port 0 Control 3 ...................................................................................................................................................25
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7.2.5.
Port 0 Control 4 ...................................................................................................................................................26
7.2.6.
IP Address ............................................................................................................................................................26
7.2.7.
Port 1 Control 0 ...................................................................................................................................................27
7.2.8.
Port 1 Control 1 ...................................................................................................................................................28
7.2.9.
Port 1 Control 2 ...................................................................................................................................................28
7.2.10.
Port 1 Control 3...............................................................................................................................................29
7.2.11.
Port 1 Control 4...............................................................................................................................................29
7.2.12.
IP Mask............................................................................................................................................................30
7.2.13.
Port 2 Control 0...............................................................................................................................................30
7.2.14.
Port 2 Control 1...............................................................................................................................................31
7.2.15.
Port 2 Control 2...............................................................................................................................................31
7.2.16.
Port 2 Control 3...............................................................................................................................................32
7.2.17.
Port 2 Control 4...............................................................................................................................................32
7.2.18.
Switch MAC Address .......................................................................................................................................33
7.2.19.
Port 3 Control 0...............................................................................................................................................33
7.2.20.
Port 3 Control 1...............................................................................................................................................34
7.2.21.
Port 3 Control 2...............................................................................................................................................34
7.2.22.
Port 3 Control 3...............................................................................................................................................35
7.2.23.
Port 3 Control 4...............................................................................................................................................35
7.2.24.
ISP MAC Address ............................................................................................................................................36
7.2.25.
Port 4 Control 0...............................................................................................................................................36
7.2.26.
Port 4 Control 1...............................................................................................................................................37
7.2.27.
Port 4 Control 2...............................................................................................................................................37
7.2.28.
Port 4 Control 3...............................................................................................................................................38
7.2.29.
Port 4 Control 4...............................................................................................................................................38
7.3.
MII PORT CONTROL PINS ...........................................................................................................................................39
7.3.1.
MII Port Control 0................................................................................................................................................39
7.3.2.
MII Port Control 1................................................................................................................................................39
7.3.3.
MII Port Control 2................................................................................................................................................40
7.3.4.
CPU Port and WAN Port .....................................................................................................................................40
7.4.
PORT 5~7 CONTROL PINS ...........................................................................................................................................41
7.4.1.
Port 5 Control 0 ...................................................................................................................................................41
7.4.2.
Port 5 Control 1 ...................................................................................................................................................41
7.4.3.
Port 5 Control 2 ...................................................................................................................................................42
7.4.4.
Port 5 Control 3 ...................................................................................................................................................42
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8.
7.4.5.
Port 5 Control 4 ...................................................................................................................................................43
7.4.6.
Port 6 Control 0 ...................................................................................................................................................43
7.4.7.
Port 6 Control 1 ...................................................................................................................................................44
7.4.8.
Port 6 Control 2 ...................................................................................................................................................44
7.4.9.
Port 6 Control 3 ...................................................................................................................................................45
7.4.10.
Port 6 Control 4...............................................................................................................................................45
7.4.11.
Port 7 Control 0...............................................................................................................................................46
7.4.12.
Port 7 Control 1...............................................................................................................................................46
7.4.13.
Port 7 Control 2...............................................................................................................................................47
7.4.14.
Port 7 Control 3...............................................................................................................................................47
7.4.15.
Port 7 Control 4...............................................................................................................................................48
PHY REGISTERS DESCRIPTION ...............................................................................................................................49
8.1.
PHY 0 REGISTERS......................................................................................................................................................49
8.1.1.
PHY 0 Register 0: Control ...................................................................................................................................49
8.1.2.
PHY 0 Register 1: Status ......................................................................................................................................50
8.1.3.
PHY 0 Register 4: Auto-Negotiation Advertisement.............................................................................................51
8.1.4.
PHY 0 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................52
8.1.5.
PHY 0 Register 16: Global Control 0...................................................................................................................53
8.1.6.
PHY 0 Register 17: Global Control 1...................................................................................................................54
8.1.7.
PHY 0 Register 18: Global Control 2...................................................................................................................55
8.1.8.
PHY 0 Register 19: Global Control 3...................................................................................................................56
8.1.9.
PHY 0 Register 22: Port 0 Control 0....................................................................................................................56
8.1.10.
PHY 0 Register 23: Port 0 Control 1...............................................................................................................57
8.1.11.
PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]................................................................................58
8.1.12.
PHY 0 Register 25: VLAN Entry [A] ...............................................................................................................58
8.2.
PHY 1 REGISTERS......................................................................................................................................................59
8.2.1.
PHY 1 Register 0: Control ...................................................................................................................................59
8.2.2.
PHY 1 Register 1: Status ......................................................................................................................................59
8.2.3.
PHY 1 Register 4: Auto-Negotiation Advertisement.............................................................................................59
8.2.4.
PHY 1 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................59
8.2.5.
PHY 1 Register 16~17: IP Priority Address [A] ..................................................................................................59
8.2.6.
PHY 1 Register 18~19: IP Priority Address [B] ..................................................................................................59
8.2.7.
PHY 1 Register 22: Port 1 Control 0....................................................................................................................60
8.2.8.
PHY 1 Register 23: Port 1 Control 1....................................................................................................................60
8.2.9.
PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B] ....................................................................................60
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8.2.10.
8.3.
PHY 1 Register 25: VLAN Entry [B] ...............................................................................................................60
PHY 2 REGISTERS......................................................................................................................................................61
8.3.1.
PHY 2 Register 0: Control ...................................................................................................................................61
8.3.2.
PHY 2 Register 1: Status ......................................................................................................................................61
8.3.3.
PHY 2 Register 4: Auto-Negotiation Advertisement.............................................................................................61
8.3.4.
PHY 2 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................61
8.3.5.
PHY 2 Register 16~17: IP Priority Mask [A] ......................................................................................................61
8.3.6.
PHY 2 Register 18~19: IP Priority Mask [B] ......................................................................................................61
8.3.7.
PHY 2 Register 22: Port 2 Control 0....................................................................................................................62
8.3.8.
PHY 2 Register 23: Port 2 Control 1....................................................................................................................62
8.3.9.
PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C] ....................................................................................62
8.3.10.
8.4.
PHY 2 Register 25: VLAN Entry [C]...............................................................................................................62
PHY 3 REGISTERS......................................................................................................................................................63
8.4.1.
PHY 3 Register 0: Control ...................................................................................................................................63
8.4.2.
PHY 3 Register 1: Status ......................................................................................................................................63
8.4.3.
PHY 3 Register 4: Auto-Negotiation Advertisement.............................................................................................63
8.4.4.
PHY 3 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................63
8.4.5.
PHY 3 Register 16~18: Switch MAC Address ......................................................................................................63
8.4.6.
PHY 3 Register 22: Port 3 Control 0....................................................................................................................63
8.4.7.
PHY 3 Register 23: Port 3 Control 1....................................................................................................................64
8.4.8.
PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D] ....................................................................................64
8.4.9.
PHY 3 Register 25: VLAN Entry [D] ...................................................................................................................64
8.5.
PHY 4 REGISTERS......................................................................................................................................................65
8.5.1.
PHY 4 Register 0: Control ...................................................................................................................................65
8.5.2.
PHY 4 Register 1: Status ......................................................................................................................................65
8.5.3.
PHY 4 Register 4: Auto-Negotiation Advertisement.............................................................................................65
8.5.4.
PHY 4 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................65
8.5.5.
PHY 4 Register 16~18: ISP MAC Address...........................................................................................................65
8.5.6.
PHY 4 Register 22: Port 4 Control 0....................................................................................................................65
8.5.7.
PHY 4 Register 23: Port 4 Control 1....................................................................................................................66
8.5.8.
PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E] ....................................................................................66
8.5.9.
PHY 4 Register 25: VLAN Entry [E]....................................................................................................................66
8.6.
PHY 5 REGISTERS......................................................................................................................................................67
8.6.1.
PHY 5 Register 0: Control ...................................................................................................................................67
8.6.2.
PHY 5 Register 1: Status ......................................................................................................................................67
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Datasheet
8.6.3.
PHY 5 Register 4: Auto-Negotiation Advertisement.............................................................................................67
8.6.4.
PHY 5 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................67
8.6.5.
PHY 5 Register 16: MII Port Control 0................................................................................................................67
8.6.6.
PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]..................................................................................68
8.6.7.
PHY 5 Register 18: VLAN Entry [I] .....................................................................................................................69
8.6.8.
PHY 5 Register 19: CPU Port & WAN Port ........................................................................................................69
8.6.9.
PHY 5 Register 22: Port 5 Control 0....................................................................................................................69
8.6.10.
PHY 5 Register 23: Port 5 Control 1...............................................................................................................69
8.6.11.
PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]................................................................................70
8.6.12.
PHY 5 Register 25: VLAN Entry [F] ...............................................................................................................70
8.7.
PHY 6 REGISTERS......................................................................................................................................................71
8.7.1.
PHY 6 Register 0: Control ...................................................................................................................................71
8.7.2.
PHY 6 Register 1: Status ......................................................................................................................................71
8.7.3.
PHY 6 Register 4: Auto-Negotiation Advertisement.............................................................................................71
8.7.4.
PHY 6 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................71
8.7.5.
PHY 6 Register 22: Port 6 Control 0....................................................................................................................71
8.7.6.
PHY 6 Register 23: Port 6 Control 1....................................................................................................................71
8.7.7.
PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G] ....................................................................................72
8.7.8.
PHY 6 Register 25: VLAN Entry [G] ...................................................................................................................72
8.8.
PHY 7 REGISTERS......................................................................................................................................................73
8.8.1.
PHY 7 Register 0: Control ...................................................................................................................................73
8.8.2.
PHY 7 Register 1: Status ......................................................................................................................................73
8.8.3.
PHY 7 Register 4: Auto-Negotiation Advertisement.............................................................................................73
8.8.4.
PHY 7 Register 5: Auto-Negotiation Link Partner Ability ...................................................................................73
8.8.5.
PHY 7 Register 16: Indirect Access Control ........................................................................................................73
8.8.6.
PHY 7 Register 17~20: Indirect Access Data ......................................................................................................74
8.8.7.
PHY 7 Register 22: Port 7 Control 0....................................................................................................................74
8.8.8.
PHY 7 Register 23: Port 7 Control 1....................................................................................................................74
8.8.9.
PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H] ....................................................................................75
8.8.10.
8.9.
PHY 7 Register 25: VLAN Entry [H]...............................................................................................................75
PHY 8 REGISTERS......................................................................................................................................................76
8.9.1.
PHY 8 Register 0: Control ...................................................................................................................................76
8.9.2.
PHY 8 Register 1: Status ......................................................................................................................................76
8.9.3.
PHY 8 Register 4: Auto-Negotiation Advertisement.............................................................................................77
8.9.4.
MII Port NWay Mode ...........................................................................................................................................78
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8.9.5.
9.
MII Port Force Mode ...........................................................................................................................................78
FUNCTIONAL DESCRIPTION.....................................................................................................................................79
9.1.
PHYSICAL LAYER TRANSCEIVER FUNCTIONAL OVERVIEW ........................................................................................79
9.1.1.
Auto Negotiation for UTP ....................................................................................................................................79
9.1.2.
100Base-Tx Transmit Function ............................................................................................................................79
9.1.3.
100Base-Tx Receive Function ..............................................................................................................................80
9.1.4.
10Base-T Transmit Function ................................................................................................................................80
9.1.5.
10Base-T Receive Function ..................................................................................................................................80
9.1.6.
Link Monitor.........................................................................................................................................................80
9.1.7.
Power-Down Mode...............................................................................................................................................81
9.1.8.
Auto Crossover Detection.....................................................................................................................................81
9.2.
SWITCH CORE FUNCTIONAL OVERVIEW ....................................................................................................................82
9.2.1.
Address Search, Learning, and Aging ..................................................................................................................82
9.2.2.
Flow Control ........................................................................................................................................................82
9.2.3.
Half Duplex Operation .........................................................................................................................................83
9.2.4.
Backpressure ........................................................................................................................................................83
9.2.5.
UTP Port Status Configuration ............................................................................................................................84
9.2.6.
MII Port (The 9th Port) ........................................................................................................................................84
9.3.
ADVANCED FUNCTIONALITY OVERVIEW ...................................................................................................................88
9.3.1.
Port-Based VLAN .................................................................................................................................................88
9.3.2.
IEEE 802.1Q Tagged VID-based VLAN...............................................................................................................90
9.3.3.
QoS Operation......................................................................................................................................................91
9.3.4.
Insert/Remove VLAN Priority Tag .......................................................................................................................93
9.3.5.
Port VID (PVID) ..................................................................................................................................................94
9.3.6.
Port Trunking .......................................................................................................................................................94
9.3.7.
ISP MAC Address Translation .............................................................................................................................94
9.3.8.
Lookup Table Access ............................................................................................................................................96
9.3.9.
Serial Management Interface (SMI) .....................................................................................................................96
9.3.10.
Broadcast Storm Control.................................................................................................................................97
9.3.11.
Broadcast In/Out Drop ....................................................................................................................................97
9.3.12.
EEPROM Configuration Interface ..................................................................................................................98
9.3.13.
24LC02 Device Operation ...............................................................................................................................98
9.3.14.
Head-of-Line Blocking...................................................................................................................................100
9.3.15.
MII Port Diagnostic Loopback ......................................................................................................................100
9.3.16.
Loop Detection ..............................................................................................................................................101
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9.3.17.
9.4.
LEDs (Light Emitting Diodes) .......................................................................................................................101
GREEN ETHERNET ....................................................................................................................................................104
9.4.1.
Link-On and Cable Length Power Saving ..........................................................................................................104
9.4.2.
Link-Down Power Saving...................................................................................................................................104
10.
CHARACTERISTICS...............................................................................................................................................105
10.1.
ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................105
10.2.
OPERATING RANGE ..................................................................................................................................................105
10.3.
DC CHARACTERISTICS .............................................................................................................................................106
10.4.
AC CHARACTERISTICS .............................................................................................................................................107
10.5.
DIGITAL TIMING CHARACTERISTICS ........................................................................................................................108
10.6.
THERMAL CHARACTERISTICS...................................................................................................................................110
11.
DESIGN AND LAYOUT...........................................................................................................................................111
12.
MECHANICAL DIMENSIONS...............................................................................................................................115
12.1.
13.
NOTES FOR MECHANICAL DIMENSIONS ...................................................................................................................116
ORDERING INFORMATION .................................................................................................................................116
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List of Tables
TABLE 1. PIN ASSIGNMENTS ..........................................................................................................................................................8
TABLE 2. MEDIA CONNECTION PINS............................................................................................................................................10
TABLE 3. MII PORT MAC INTERFACE PINS .................................................................................................................................11
TABLE 4. MISCELLANEOUS PINS .................................................................................................................................................12
TABLE 5. PORT LED PINS............................................................................................................................................................13
TABLE 6. SERIAL EEPROM AND SMI PINS .................................................................................................................................16
TABLE 7. STRAPPING PINS ...........................................................................................................................................................16
TABLE 8. POWER PINS .................................................................................................................................................................19
TABLE 9. GLOBAL CONTROL REGISTER0.....................................................................................................................................20
TABLE 10. GLOBAL CONTROL REGISTER1 ....................................................................................................................................21
TABLE 11. GLOBAL CONTROL REGISTER2 ....................................................................................................................................21
TABLE 12. GLOBAL CONTROL REGISTER3 ....................................................................................................................................22
TABLE 13. GLOBAL CONTROL REGISTER4 ....................................................................................................................................22
TABLE 14. GLOBAL CONTROL REGISTER5 ....................................................................................................................................23
TABLE 15. GLOBAL CONTROL REGISTER6 ....................................................................................................................................23
TABLE 16. GLOBAL CONTROL REGISTER7 ....................................................................................................................................23
TABLE 17. PORT 0 CONTROL 0 ......................................................................................................................................................24
TABLE 18. PORT 0 CONTROL 1 ......................................................................................................................................................24
TABLE 19. PORT 0 CONTROL 2 ......................................................................................................................................................25
TABLE 20. PORT 0 CONTROL 3 ......................................................................................................................................................25
TABLE 21. PORT 0 CONTROL 4 ......................................................................................................................................................26
TABLE 22. IP ADDRESS .................................................................................................................................................................26
TABLE 23. PORT 1 CONTROL 0 ......................................................................................................................................................27
TABLE 24. PORT 1 CONTROL 1 ......................................................................................................................................................28
TABLE 25. PORT 1 CONTROL 2 ......................................................................................................................................................28
TABLE 26. PORT 1 CONTROL 3 ......................................................................................................................................................29
TABLE 27. PORT 1 CONTROL 4 ......................................................................................................................................................29
TABLE 28. IP MASK ......................................................................................................................................................................30
TABLE 29. PORT 2 CONTROL 0 ......................................................................................................................................................30
TABLE 30. PORT 2 CONTROL 1 ......................................................................................................................................................31
TABLE 31. PORT 2 CONTROL 2 ......................................................................................................................................................31
TABLE 32. PORT 2 CONTROL 3 ......................................................................................................................................................32
TABLE 33. PORT 2 CONTROL 4 ......................................................................................................................................................32
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TABLE 34. SWITCH MAC ADDRESS ..............................................................................................................................................33
TABLE 35. PORT 3 CONTROL 0 ......................................................................................................................................................33
TABLE 36. PORT 3 CONTROL 1 ......................................................................................................................................................34
TABLE 37. PORT 3 CONTROL 2 ......................................................................................................................................................34
TABLE 38. PORT 3 CONTROL 3 ......................................................................................................................................................35
TABLE 39. PORT 3 CONTROL 4 ......................................................................................................................................................35
TABLE 40. ISP MAC ADDRESS .....................................................................................................................................................36
TABLE 41. PORT 4 CONTROL 0 ......................................................................................................................................................36
TABLE 42. PORT 4 CONTROL 1 ......................................................................................................................................................37
TABLE 43. PORT 4 CONTROL 2 ......................................................................................................................................................37
TABLE 44. PORT 4 CONTROL 3 ......................................................................................................................................................38
TABLE 45. PORT 4 CONTROL 4 ......................................................................................................................................................38
TABLE 46. MII PORT CONTROL 0..................................................................................................................................................39
TABLE 47. MII PORT CONTROL 1..................................................................................................................................................39
TABLE 48. MII PORT CONTROL 2..................................................................................................................................................40
TABLE 49. CPU PORT AND WAN PORT ........................................................................................................................................40
TABLE 50. PORT 5 CONTROL 0 ......................................................................................................................................................41
TABLE 51. PORT 5 CONTROL 1 ......................................................................................................................................................41
TABLE 52. PORT 5 CONTROL 2 ......................................................................................................................................................42
TABLE 53. PORT 5 CONTROL 3 ......................................................................................................................................................42
TABLE 54. PORT 5 CONTROL 4 ......................................................................................................................................................43
TABLE 55. PORT 6 CONTROL 0 ......................................................................................................................................................43
TABLE 56. PORT 6 CONTROL 1 ......................................................................................................................................................44
TABLE 57. PORT 6 CONTROL 2 ......................................................................................................................................................44
TABLE 58. PORT 6 CONTROL 3 ......................................................................................................................................................45
TABLE 59. PORT 6 CONTROL 4 ......................................................................................................................................................45
TABLE 60. PORT 7 CONTROL 0 ......................................................................................................................................................46
TABLE 61. PORT 7 CONTROL 1 ......................................................................................................................................................46
TABLE 62. PORT 7 CONTROL 2 ......................................................................................................................................................47
TABLE 63. PORT 7 CONTROL 3 ......................................................................................................................................................47
TABLE 64. PORT 7 CONTROL 4 ......................................................................................................................................................48
TABLE 65. PHY 0 REGISTER 0: CONTROL .....................................................................................................................................49
TABLE 66. PHY 0 REGISTER 1: STATUS ........................................................................................................................................50
TABLE 67. PHY 0 REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT........................................................................................51
TABLE 68. PHY 0 REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY .............................................................................52
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TABLE 69. PHY 0 REGISTER 16: GLOBAL CONTROL 0 ..................................................................................................................53
TABLE 70. PHY 0 REGISTER 17: GLOBAL CONTROL 1 ..................................................................................................................54
TABLE 71. PHY 0 REGISTER 18: GLOBAL CONTROL 2 ..................................................................................................................55
TABLE 72. PHY 0 REGISTER 19: GLOBAL CONTROL 3 ..................................................................................................................56
TABLE 73. PHY 0 REGISTER 22: PORT 0 CONTROL 0 ....................................................................................................................56
TABLE 74. PHY 0 REGISTER 23: PORT 0 CONTROL 1 ....................................................................................................................57
TABLE 75. PHY 0 REGISTER 24: PORT 0 CONTROL 2 & VLAN ENTRY [A] ..................................................................................58
TABLE 76. PHY 0 REGISTER 25: VLAN ENTRY [A] .....................................................................................................................58
TABLE 77. PHY 1 REGISTER 16~17: IP PRIORITY ADDRESS [A]...................................................................................................59
TABLE 78. PHY 1 REGISTER 18~19: IP PRIORITY ADDRESS [B] ...................................................................................................59
TABLE 79. PHY 1 REGISTER 24: PORT 1 CONTROL 2 & VLAN ENTRY [B] ..................................................................................60
TABLE 80. PHY 1 REGISTER 25: VLAN ENTRY [B]......................................................................................................................60
TABLE 81. PHY 2 REGISTER 16~17: IP PRIORITY MASK [A] ........................................................................................................61
TABLE 82. PHY 2 REGISTER 18~19: IP PRIORITY MASK [B] ........................................................................................................61
TABLE 83. PHY 2 REGISTER 24: PORT 2 CONTROL 2 & VLAN ENTRY [C] ..................................................................................62
TABLE 84. PHY 2 REGISTER 25: VLAN ENTRY [C]......................................................................................................................62
TABLE 85. PHY 3 REGISTER 16~18: SWITCH MAC ADDRESS ......................................................................................................63
TABLE 86. PHY 3 REGISTER 24: PORT 3 CONTROL 2 & VLAN ENTRY [D] ..................................................................................64
TABLE 87. PHY 3 REGISTER 25: VLAN ENTRY [D] .....................................................................................................................64
TABLE 88. PHY 4 REGISTER 16~18: ISP MAC ADDRESS .............................................................................................................65
TABLE 89. PHY 4 REGISTER 24: PORT 4 CONTROL 2 & VLAN ENTRY [E]...................................................................................66
TABLE 90. PHY 4 REGISTER 25: VLAN ENTRY [E]......................................................................................................................66
TABLE 91. PHY 5 REGISTER 16: MII PORT CONTROL 0 ................................................................................................................67
TABLE 92. PHY 5 REGISTER 17: MII PORT CONTROL 1 & VLAN ENTRY [I]................................................................................68
TABLE 93. PHY 5 REGISTER 18: VLAN ENTRY [I].......................................................................................................................69
TABLE 94. PHY 5 REGISTER 19: CPU PORT & WAN PORT ..........................................................................................................69
TABLE 95. PHY 5 REGISTER 24: PORT 5 CONTROL 2 & VLAN ENTRY [F]...................................................................................70
TABLE 96. PHY 5 REGISTER 25: VLAN ENTRY [F] ......................................................................................................................70
TABLE 97. PHY 6 REGISTER 24: PORT 6 CONTROL 2 & VLAN ENTRY [G] ..................................................................................72
TABLE 98. PHY 6 REGISTER 25: VLAN ENTRY [G] .....................................................................................................................72
TABLE 99. PHY 7 REGISTER 16: INDIRECT ACCESS CONTROL ......................................................................................................73
TABLE 100. PHY 7 REGISTER 17~20: INDIRECT ACCESS DATA ....................................................................................................74
TABLE 101. PHY 7 REGISTER 24: PORT 7 CONTROL 2 & VLAN ENTRY [H] ................................................................................75
TABLE 102. PHY 7 REGISTER 25: VLAN ENTRY [H] ...................................................................................................................75
TABLE 103. PHY 8 REGISTER 0: CONTROL ...................................................................................................................................76
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
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Datasheet
TABLE 104. PHY 8 REGISTER 1: STATUS ......................................................................................................................................76
TABLE 105. PHY 8 REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT......................................................................................77
TABLE 106. MII PORT NWAY MODE ............................................................................................................................................78
TABLE 107. MII PORT FORCE MODE.............................................................................................................................................78
TABLE 108. 802.1Q VLAN TAG FRAME FORMAT ........................................................................................................................92
TABLE 109. IPV4 FRAME FORMAT ................................................................................................................................................92
TABLE 110. SMI READ/WRITE CYCLES ........................................................................................................................................96
TABLE 111. LOOP FRAME FORMAT .............................................................................................................................................101
TABLE 112. SPEED AND BI-COLOR LINK/ACT TRUTH TABLE .....................................................................................................102
TABLE 113. ABSOLUTE MAXIMUM RATINGS ..............................................................................................................................105
TABLE 114. OPERATING RANGE .................................................................................................................................................105
TABLE 115. DC CHARACTERISTICS.............................................................................................................................................106
TABLE 116. AC CHARACTERISTICS.............................................................................................................................................107
TABLE 117. DIGITAL TIMING CHARACTERISTICS ........................................................................................................................108
TABLE 118. THERMAL OPERATING RANGE .................................................................................................................................111
TABLE 119. THERMAL RESISTANCE ............................................................................................................................................111
TABLE 120. ORDERING INFORMATION ........................................................................................................................................116
Single-Chip 9-Port 10/100Mbps Switch Controller
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RTL8309G
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM ..........................................................................................................................................................6
FIGURE 2. PIN ASSIGNMENTS ........................................................................................................................................................7
FIGURE 3. MII PORT APPLICATION ..............................................................................................................................................85
FIGURE 4. MII PORT OPERATING MODE OVERVIEW....................................................................................................................86
FIGURE 5. VLAN GROUPING EXAMPLE.......................................................................................................................................89
FIGURE 6. TAGGED AND UNTAGGED PACKET FORWARDING WHEN 802.1Q TAG AWARE VLAN IS DISABLED ..........................90
FIGURE 7. ISP MAC OUTBOUND PROCESS ..................................................................................................................................95
FIGURE 8. ISP MAC INBOUND PROCESS .....................................................................................................................................95
FIGURE 9. INPUT DROP VS. OUTPUT DROP...................................................................................................................................98
FIGURE 10. START AND STOP DEFINITION .....................................................................................................................................99
FIGURE 11. OUTPUT ACKNOWLEDGE ............................................................................................................................................99
FIGURE 12. SEQUENTIAL READ ...................................................................................................................................................100
FIGURE 13. MII PORT LOOPBACK ...............................................................................................................................................100
FIGURE 14. LOOP EXAMPLE ........................................................................................................................................................101
FIGURE 15. FLOATING AND PULL-DOWN OF LED PINS ...............................................................................................................102
FIGURE 16. TWO-PIN BI-COLOR LED FOR SPD FLOATING OR PULL-HIGH .................................................................................103
FIGURE 17. TWO-PIN BI-COLOR LED FOR SPD PULL-DOWN......................................................................................................103
FIGURE 18. BI-COLOR LED REFERENCE SCHEMATIC .................................................................................................................104
FIGURE 19. RECEPTION DATA TIMING OF MII/SNI/SMI INTERFACE ..........................................................................................108
FIGURE 20. TRANSMISSION DATA TIMING OF MII/SNI/SMI INTERFACE ....................................................................................108
FIGURE 21. CROSS-SECTION OF 128-PIN PQFP ...........................................................................................................................110
FIGURE 22. APPLICATION FOR TRANSFORMER WITH CONNECTED CENTRAL TAP .......................................................................113
FIGURE 23. BOB SMITH TERMINATION ........................................................................................................................................114
Single-Chip 9-Port 10/100Mbps Switch Controller
xiv
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
1.
General Description
The RTL8309G is a 128-pin, ultra-low-power, high-performance 8-port Fast Ethernet single-chip switch
with one extra MII port for specific applications. It integrates all the functions of a high-speed switch
system—including SRAM for packet buffering, non-blocking switch fabric, address management, one
general use MII interface, eight 10/100Base-TX transceivers, and nine Media Access Controllers—into a
single 0.16µm CMOS device. It provides compatibility with all industry standard Ethernet and Fast
Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs.
The embedded packet storage SRAM in the RTL8309G features superior memory management
technology to efficiently utilize the memory space. An integrated 1024-entry look-up table stores MAC
address and associated information in a 10-bit direct mapping scheme. The table provides read/write
access from the SMI interface, and each of the entries can be configured as a static entry. A static entry
indicates that this entry is controlled by the external management processor and automatic aging and
learning of the entry will not take place. To prevent MAC address mapping collisions, the embedded 16entry Content-Addressable Memory (CAM) offers another memory space for recording the MAC address
when the mapped entry in the lookup table is occupied. For each incoming packet, the RTL8309G
searches the entries in the lookup table and the 16-entry CAM simultaneously. Then it obtains the correct
destination port information to determine which output port the packet should be forwarded to. The aging
time of the RTL8309G is around 300 seconds (this may be sped up to 800µs via EEPROM configuration).
The ninth port of the RTL8309G implements a MAC module without a PHY transceiver to provide an
MII interface for connection with an external PHY or MAC in specific applications. This MII interface
may be set to MII PHY mode, SNI PHY mode, or MII MAC mode to work with an external MAC
module in a routing engine application, PHY module in a HomePNA application, or other physical layer
transceivers. In order to operate correctly, both sides of the connection must be configured to the same
speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This
interface should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO
of this interface.
The RTL8309G is capable of preventing broadcast storms by setting strapping pins upon system reset.
When this function is enabled, it will drop broadcast packets after receiving 64 continuous broadcast
packets. This counter will be reset to 0 every 800ms or when the RTL8309G receives a non-broadcast
packet.
Single-Chip 9-Port 10/100Mbps Switch Controller
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
The RTL8309G displays the port status via four LED indicators (with optional blinking time setting).
These LEDs blink for diagnostic purposes at system reset time. The RTL8309G provides various type of
LED combinations to fit different applications. Eight combinations of link, activity, speed, duplex, and
collision, are available. Bi-color LED mode is also supported on the Link/Act LED.
The RTL8309G supports standard 802.3x flow control frames for full duplex, and optional backpressure
for half duplex. It determines when to invoke the flow control mechanism by checking the availability of
system resources, including the packet buffers and transmitting queues. If one of the forwarding ports is
blocked, or system resources are unavailable, broadcast frames will be dropped according to the system
configuration. The RTL8309G support two types of dropping methods. The input dropping method will
not forward broadcast packets to any output ports and will drop these packets directly. The output
dropping method will forward broadcast packets to non-blocked ports only.
To improve real-time and multimedia networking applications, the RTL8309G supports four types of
QoS (Quality of Service). These are based on (1) Port-based priority, (2) 802.1p/Q VLAN priority tag, (3)
TOS field in IPv4 header, (4) Specific IP address. Each output port supports a weighted ratio of highpriority and low-priority queues to fit bandwidth requirements in different applications.
The RTL8309G provides 802.1Q port-based VLAN operation to separate logical connectivity from
physical connectivity. Each port may be set to any topology via EEPROM upon reset or SMI after reset.
The RTL8309G also provides options to meet special application requirements. The first option is the
ARP VLAN function, which is used to select to broadcast ARP frames to all VLANs or only forward
ARP frames to the originating VLAN. The second option is the Leaky VLAN function, which is used to
select to send unicast frames to other VLANs or only forward unicast frames to the originating VLAN.
The VLAN tags can be inserted or removed on a per-port basis.
In router applications, the router may want to know which input port this packet came from. The
RTL8309G supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. In this
function, the VID information carried in the VLAN tag will be changed to PVID. The RTL8309G also
provides an option to admit VLAN tagged packet with a specific PVID only. If this function is enabled, it
will drop non-tagged packets and packets with an incorrect PVID.
Each physical layer channel consists of a 4B5B encoder/decoder, Manchester encoder/decoder, transmit
output driver, scrambler/descrambler, output wave shaping, filters, digital adaptive equalizer, PLL circuit,
and DC restoration circuit for clock/data recovery. This integrated chip benefits from low power
consumption and offers advanced functions with flexible configuration for a small workgroup switch,
multimedia, or real-time traffic mixed with other data type traffic, and other applications.
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Green Ethernet features include:
Link-On and Cable Length Power Saving
The RTL8309G provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
Link-Down Power Saving
The RTL8309G implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected.
Single-Chip 9-Port 10/100Mbps Switch Controller
3
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
2.
„
Features
Integrates eight 10/100 transceivers and nine
MAC units for 10Base-T and 100Base-TX
„
Fully compliant with IEEE 802.3/802.3u.
„
Optional Forwarding/Filtering reserved
control frames
(DID=0180C2000003~0180C200000F)
„
Embedded SRAM for packet storage
„
On-chip 1024-entry look-up table in direct
mapping mode
„
Embedded 16-entry CAM for hash collision
mapping
Optional Broadcast Input/Output Drop flow
control
„
Provides read/write access to look-up table
entries via SMI interface
Optional maximum packet length
1536/1552 Bytes
„
Green Ethernet Features
„
„
„
Provides non-blocking wire speed reception
and transmission
„
Flow control fully supported:
‹
Half-duplex: backpressure flow control
‹
Full-duplex: IEEE 802.3x flow control
„
Support for 4 LEDs per-port in various
combinations for comprehensive
applications
„
Optional loop detection function with an
LED to indicate the existence of a loop
„
LEDs blink upon reset for LED diagnostics
„
Flexible system configuration by strapping
pins, EEPROM, or SMI interface
„
Optional crossover detection and auto
correction for plug-and-play
Single-Chip 9-Port 10/100Mbps Switch Controller
„
„
4
‹
Link-On and Cable Length Power
Saving
‹
Link-Down Power Saving
Supports two Power Reduction methods:
‹
Power saving mode (automatic cable
detection)
‹
Power down mode (via PHY
register 0.11)
Supports QoS function:
‹
QoS based on: (1) Port-based priority (2)
802.1p VLAN tag (3) DiffServ/TOS
field in TCP/IP header (4) IP address
‹
Supports two-level priority queues with
various weighting ratios
‹
Queue service rate based on weighted
round robin algorithm
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
‹
„
„
Supports MII interface connection to
external MAC or PHY via 3 modes:
‹
PHY mode MII for router applications
‹
PHY mode SNI for router applications
‹
MAC mode MII for HomePNA or other
PHY applications
Flexible 802.1Q port/tag-based VLAN.
‹
Optional 802.1Q tag-VID aware function
‹
Optional VLAN Ingress Tag Admit
Control
‹
3.
Optional auto turn off Flow Control for
1~2 sec to avoid head-of-line blocking
Optional VLAN Ingress Member set
filtering
‹
Optional ARP VLAN for broadcast
packet
‹
Optional Leaky VLAN for unicast
packet
„
Optional 802.1P/Q tag insertion or removal
on per-port basis (egress)
„
25MHz crystal input
„
0.16µm, CMOS technology
„
128-pin PQFP package
„
1.8V core voltage
„
Independent power options for 2.5V or 3.3V
MII interface
System Applications
„
Broadband gateway/firewall/VPN
„
Wireless LAN access point + gateway
„
Home networking expansion
„
Standalone 10/100 switch
„
Small workgroup switch
„
VoIP infrastructure switch
Single-Chip 9-Port 10/100Mbps Switch Controller
5
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
4.
Block Diagram
Figure 1. Block Diagram
Single-Chip 9-Port 10/100Mbps Switch Controller
6
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
5.
Pin Assignments
Figure 2. Pin Assignments
5.1. Package Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Single-Chip 9-Port 10/100Mbps Switch Controller
7
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
5.2. Pin Assignments Table
Type codes used in the following tables: ‘A’ stands for analog; ‘D’ stands for digital, ‘I’ stands for input;
‘O’ stands for output.
Table 1. Pin Assignments
Name
VDDA
VSSA
TXON[1]
TXOP[1]
VSSA
RXIP[1]
RXIN[1]
VDDA
RXIN[2]
RXIP[2]
VSSA
TXOP[2]
TXON[2]
VDDA
TXON[3]
TXOP[3]
VSSA
RXIP[3]
RXIN[3]
VDDA
RXIN[4]
RXIP[4]
VSSA
TXOP[4]
TXON[4]
VDDA
TXON[5]
TXOP[5]
VSSA
RXIP[5]
RXIN[5]
VDDA
RXIN[6]
RXIP[6]
VSSA
TXOP[6]
TXON[6]
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Single-Chip 9-Port 10/100Mbps Switch Controller
Type
AVDD
AGND
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
AVDD
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
AVDD
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
Name
VDDA
RXIN[7]
RXIP[7]
VSSA
TXOP[7]
TXON[7]
VDDA
NC
NC
RESET#
MII_FCTRL_STA
MII_SPD_STA
MII_DUP_STA
MII_LNK_STA#
VDDD
VSSD
SCL_MDC
SDA_MDIO
MTXC/PRXC
MTXEN/PRXDV
MTXD[0]/PRXD[0]
MTXD[1]/PRXD[1]
MTXD[2]/PRXD[2]
MTXD[3]/PRXD[3]
VDDIO
VSSIO
MCOL/PCOL
MRXC/PTXC
MRXDV/PTXDV
MRXD[0]/PTXD[0]
MRXD[1]/PTXD[1]
MRXD[2]/PTXD[2]
MRXD[3]/PTXD[3]
VDDD
VSSD
P7_LED[3]/Dis_FC_AutoOff
P7_LED[2]/Port_LED_LOC
8
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
Type
AVDD
AI
AI
AGND
AO
AO
AVDD
I*
I*
I*
I*
I*
DVDD
DGND
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
I/O
I
I
I
I
I
DVDD
DGND
I/O*
I/O*
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Name
P7_LED[1]/LED_BLNK_TIME
P7_LED[0]/Dis_ARPVLAN
P6_LED[3]/Dis_LeakyVLAN
P6_LED[2]/Dis_VLAN
VDDD
VSSD
P6_LED[1]/QWeight[1]
P6_LED[0]/QWeight[0]
P5_LED[3]/Dis_DS_Pri
P5_LED[2]/Dis_VLAN_Pri
P5_LED[1]/Sel_PortPri[1]
P5_LED[0]/Sel_PortPri[0]
VDDD
VSSD
P4_LED[3]/Max_Pause_Count
P4_LED[2]/Max_Pkt_Len
P4_LED[1]/En_Agrs_Back
P4_LED[0]/En_48pass1
P3_LED[3]/En_Defer
P3_LED[2]/En_Forward
VDDD
VSSD
P3_LED[1]/Dis_Trunk
P3_LED[0]/LED_MODE[2]
P2_LED[3]/LED_MODE[1]
P2_LED[2]/LED_MODE[0]
P2_LED[1]/MII_MODE[1]
Pin No.
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
Single-Chip 9-Port 10/100Mbps Switch Controller
Type
I/O*
I/O*
I/O*
I/O*
DVDD
DGND
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
DVDD
DGND
I/O*
I/O*
I/O*
I/O*
I/O*
I/O*
DVDD
DGND
I/O*
I/O*
I/O*
I/O*
I/O*
Name
Pin No.
P2_LED[0]/MII_MODE[0]
102
P1_LED[3]/En_AutoXover
103
P1_LED[2]/En_ANEG
104
P1_LED[1]/En_FCTRL
105
P1_LED[0]/En_BKPRS
106
VDDD
107
VSSD
108
P0_LED[3]/Force_Duplex
109
P0_LED[2]/Force_Speed
110
P0_LED[1]/En_BRD_CTRL
111
P0_LED[0]/En_RST_BLNK
112
LoopLED#,/EnEEPROM
113
VDDD
114
VSSD
115
NC
116
VSSPLL
117
X1
118
X2
119
VDDPLL
120
NC
121
IBREF
122
VDDA
123
TXON[0]
124
TXOP[0]
125
VSSA
126
RXIP[0]
127
RXIN[0]
128
Note: ‘*’ indicates voltage level is 1.8V.
9
Type
I/O*
I/O*
I/O*
I/O*
I/O*
DVDD
DGND
I/O*
I/O*
I/O*
I/O*
I/O*
DVDD
DGND
AGND
I*
O*
AVDD
AO
AVDD
AO
AO
AGND
AI
AI
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
6.
Pin Descriptions
‘Type’ codes used in the following tables.
A: Analog
I/O: Input/Output
D: Digital
IPU: Internal Pull-Up
I: Input
IPD: Internal Pull-Down
O: Output
All internal pull-up and pull-down resistors are 31K ohm resistors.
Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
6.1. Media Connection Pins
Table 2. Media Connection Pins
Pin Name
RXIP[7:0]
RXIN[7:0]
TXOP[7:0]
TXON[7:0]
Pin No.
40, 34, 30, 22, 18, 10,
6, 127, 39, 33, 31, 21,
19, 9, 7, 128
42, 36, 28, 24, 16, 12,
4, 125, 43, 37, 27, 25,
15, 13, 3, 124
Type
AI
Description
Differential Receive Data Input shared by 100Base-TX, 10Base-T for
connection to a transformer.
AO
Differential Transmit Data Output shared by 100Base-TX, 10Base-T
for connection to a transformer.
Single-Chip 9-Port 10/100Mbps Switch Controller
10
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
6.2. MII Port MAC Interface Pins
The external device can be either 2.5V or 3.3V compatible depending on the power supplied to VDDIO.
The input and input/output pins listed below do not implement an internal pull-high resistor. An external
pull-high resistor is required for these floating input pins to reduce power consumption.
Table 3. MII Port MAC Interface Pins
Pin Name
MRXD[3:0]
/PTXD[3:0]
Pin No.
70, 69,
68, 67
MRXDV/PTXEN
66
MRXC/PTXC
65
MCOL/PCOL
64
MTXD[3:0]
/PRXD[3:0]
61, 60,
59, 58
MTXEN/PRXDV
57
MTXC/PRXC
56
MII_MODE[1:0]
/P2_LED[1:0]
101, 102
Type Description
I
For MII MAC mode, these pins are MRXD[3:0], MII receive data
nibble.
For MII PHY mode, these pins are PTXD[3:0], MII transmit data
nibble.
For SNI PHY mode, PTXD[0] is serial transmit data.
I
For MII MAC mode, this pin represents MRXDV, MII receive data
valid.
For MII PHY mode, this pin represents PTXEN, MII transmit enable.
For SNI PHY mode, this pin represents PTXEN, transmit enable.
I/O For MII MAC mode, this pin represents MRXC/MII receive clock
(acts as input).
For MII/SNI PHY mode, this pin represent PTXC/MII transmit clock
(acts as output).
I/O For MII MAC mode, this pin represents MCOL, MII collision detect
(acts as input).
For MII/SNI PHY mode, this pin represents PCOL, MII collision
detect (acts as output).
O
Output After Reset.
For MII MAC mode, these pins are MTXD[3:0], MII transmit data of
MAC.
For MII PHY mode, these pins are PRXD[3:0], MII receive data of
MAC.
For SNI PHY mode, PRXD[0] is SNI serial receive data. PRXD[3:1]
are unused.
O
For MII MAC mode, this pin represents MTXEN, MII transmit
enable.
For MII PHY mode, this pin represents PRXDV, MII receive data
valid.
For SNI PHY mode, this pin represents PRXDV, SNI receive data
valid.
I/O For MII MAC mode, this pin represents MTXC, MII transmit clock
(acts as input).
For MII/SNI PHY mode, this pin represents MRXC, MII/SNI receive
clock (acts as output).
Ipu* Input Upon Reset.
Select MII port (9th port) operating mode.
11: Tri-state MII output
10: MII MAC mode
01: MII PHY mode
00: SNI PHY mode
Single-Chip 9-Port 10/100Mbps Switch Controller
11
Default
-
-
-
-
-
-
-
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
MII_LNK_STA#
Pin No.
51
Type Description
Ipu* Provides MII port (9th port) Link Status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time.
This pin sets the link status of the MII port MAC module in real-time.
MII_DUP_STA
50
Ipu* Provides MII port (9th port) duplex status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time.
1: MII port operates in full duplex mode
0: MII port operates in half duplex mode
MII_SPD_STA
49
Ipu* Provides MII port (9th port) speed status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time.
1: MII port operates at 100Mbps speed
0: MII port operates at 10Mbps speed
In the applications outlined below, this pin should be left floating:
For HomePNA (MII MAC mode), speed is determined by RXC and
TXC from PHY of HomePNA running at 1Mbps.
For SNI PHY mode, speed is fixed at 10MHz clock rate.
MII_FCTRL_STA
48
Ipu* Provides MII port (9th port) flow control status for MAC module at
MII MAC/MII PHY/SNI PHY operation mode in real time.
1: MII port has flow control ability
0: MII port does not have flow control ability
Note: ‘*’ indicates voltage level is 1.8V.
Default
1
1
1
1
6.3. Miscellaneous Pins
Table 4. Miscellaneous Pins
Pin Name
X1
Pin No.
118
Type
I*
X2
RESET#
119
47
O*
I*
IBREF
122
A
NC
45, 46,
116, 121
Note: ‘*’ indicates voltage level is 1.8V.
Description
25MHz Crystal Input.
The clock tolerance is ±50ppm.
When crystal is not used, the pin accepts 25MHz clock with 1.8V
amplitude.
25MHz Crystal Output.
Active Low Reset Signal.
To complete the reset function, this pin must be asserted for at least
10ms. After reset, about 30ms is needed for the RTL8309G to
complete the internal test function and initialization.
Note: This pin is a Schmitt input pin.
Control Transmit Output Waveform Vpp.
This pin should be grounded through a 2.0K ohm resistor.
Not Connected. Floating in normal operation.
Single-Chip 9-Port 10/100Mbps Switch Controller
12
Default
-
-
-
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
6.4. Port LED Pins
Each port supports four LED pins for status indication. The indicated status of these four LED pins may
be changed by setting different values for strapping pin LED_MODE[2:0].
Note 1: All LED statuses are represented as active-low or high depending on input strapping, except Bicolor Link/Act in Bi-color LED mode, whose polarity depends on Bi-color Speed status.
Note 2: Those pins are dual function pins: output for LED and input for strapping.
Table 5. Port LED Pins
Pin Name
P0_LED[0]
P1_LED[0]
P2_LED[0]
P3_LED[0]
P4_LED[0]
P5_LED[0]
P6_LED[0]
P7_LED[0]
P0_LED[1]
P1_LED[1]
P2_LED[1]
P3_LED[1]
P4_LED[1]
P5_LED[1]
P6_LED[1]
P7_LED[1]
Pin No. Type Description
112
Ipu/O* Output After Reset = Used for the 1st LED.
106
Mode 7: Speed (On =100 Mbps, Off =10Mbps)
102
Mode 6: Activity (Flash=Tx or Rx activity)
Mode 5: Speed (On =100 Mbps, Off =10Mbps)
98
92
Mode 4: Collision (Flash=Collision)
86
Mode 3: Reserved for internal use
82
Mode 2: RxAct+10/100 (Flash every 120ms=10Mbps Rx activity, Flash
every 43ms = 100Mbps Rx activity).
76
Mode 1: Duplex+Collision
(On=Full, Off=Half with no collision, Flash = Collision)
Mode 0: Bi-color Speed. Polarity depends on Bi-color Link+Activity
LED status. Refer to section 9.3.17 LEDs, page 101, for detailed
information.
Ipu/O* Output After Reset = Used for the 2nd LED.
111
Mode 7: Duplex+Collision
105
101
(On=Full, Off=Half with no collision, Flash = Collision)
97
Mode 6: Speed (On =100 Mbps, Off =10Mbps)
91
Mode 5: Duplex (On=Full, Off=Half)
85
Mode 4: Duplex (On=Full, Off=Half)
81
Mode 3: Duplex+Collision
75
(On=Full, Off=Half with no collision, Flash = Collision)
Mode 2: TxAct+10/100 (Flash every 120ms = 10Mbps Tx activity,
Flash every 43ms = 100Mbps Tx activity)
Mode 1: 10Link+Act (On=Link on 10Mbps, Off=No link on 10Mbps,
Flash=10Mbps Tx or Rx activity)
Mode 0: Duplex+Collision
(On=Full, Off=Half with no collision, Flash = Collision)
Single-Chip 9-Port 10/100Mbps Switch Controller
13
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
P0_LED[2]
P1_LED[2]
P2_LED[2]
P3_LED[2]
P4_LED[2]
P5_LED[2]
P6_LED[2]
P7_LED[2]
P0_LED[3]
P1_LED[3]
P2_LED[3]
P3_LED[3]
P4_LED[3]
P5_LED[3]
P6_LED[3]
P7_LED[3]
LED_MODE[2]
/P3_LED[0]
LED_MODE[1]
/P2_LED[3]
LED_MODE[0]
/P2_LED[2]
Pin No. Type Description
110
Ipu/O* Output After Reset = Used for the 3rd LED.
104
Mode 7: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity)
100
Mode 6: Link (On=Link, Off=No link)
94
Mode 5: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity)
90
Mode 4: Link+Act+Speed (On=Link, Off=No link, Flash every
120ms=10Mbps activity, flash every 43ms=100Mbps)
84
Mode 3: Link+Act+Speed (On=Link, Off=No link, Flash every
78
120ms=10Mbps activity, flash every 43ms=100Mbps)
74
Mode 2: Link (On=Link, Off=No link)
Mode 1: 100Link+Act (On=Link on 100Mbps, Off=No link on
100Mbps, Flash=100Mbps Tx or Rx activity)
Mode 0: Bi-color Speed. Polarity depends on Bi-color Link+Activity
LED status. Refer to section 9.3.17 LEDs, page 101, for detailed
information.
Ipu/O* Output After Reset = Used for the 4th LED.
109
103
Mode 7: Reserved for internal use
99
Mode 6: Reserved for internal use
93
Mode 5: Bi-color Link+Act
89
Mode 4: Reserved for internal use
83
Mode 3: 10/100 (On =100 Mbps, Off =10Mbps)
77
Mode 2: Reserved for internal use
73
Mode 1: Reserved for internal use
Mode 0: Reserved for internal use
98
I/O* Input Upon Reset = Select LED display mode upon reset.
LED_MODE[2:0]=111 -> Mode 7: Speed, Duplex+Collision,
Link+Act, Reserved
99
LED_MODE[2:0]=110 -> Mode 6: Activity, Speed, Link, Reserved
LED_MODE[2:0]=101 -> Mode 5: Speed, Duplex, Link+Act, Bi-color
100
Link+Act
LED_MODE[2:0]=100 -> Mode 4: Collision, Duplex,
Link+Act+Speed, Reserved
LED_MODE[2:0]=011 -> Mode 3: Reserved, Duplex+Collision,
Link+Act+Speed, 10/100
LED_MODE[2:0]=010 -> Mode 2: RxAct+10/100, TxAct+10/100,
Link, Reserved
LED_MODE[2:0]=001 -> Mode 1: Duplex+Collision, 10Link+Act,
100Link+Act, Reserved.
LEDM_ODE[2:0]=000 -> Mode 0: Bi-color Speed, Duplex+Collision,
Bi-color Link+Act, Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
14
Default
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
Port_LED_LOC
/P7_LED[2]
Pin No. Type Description
74
Ipu/O* Input Upon Reset = Per port LED pin location reversed.
1: For designs where LEDs are placed at the opposite side to the phone
jack
Port 0 LEDs are assigned at pins 109~112
Port 1 LEDs are assigned at pins 103~106
Port 2 LEDs are assigned at pins 99~102
Port 3 LEDs are assigned at pins 93, 94, 97, 98
Port 4 LEDs are assigned at pins 89~92
Port 5 LEDs are assigned at pins 83~86
Port 6 LEDs are assigned at pins 77, 78, 80, 81
Port 7 LEDs are assigned at pins 73~76
0: Suitable for designs where LEDs are placed on the same side as the
phone jack
Port 0 LEDs are assigned at pins 73~76
Port 1 LEDs are assigned at pins 77, 78, 80, 81
Port 2 LEDs are assigned at pins 83~86
Port 3 LEDs are assigned at pins 89~92
Port 4 LEDs are assigned at pins 93, 94, 97, 98
Port 5 LEDs are assigned at pins 99~102
Port 6 LEDs are assigned at pins 103~106
Port 7 LEDs are assigned at pins 109~112
LoopLED#
113
Ipu/O* Output After Reset = LoopLED# used for LED.
/EnEEPROM
If Loop detection is enabled, this pin indicates whether a Network loop
is detected or not. Otherwise, this pin has no function.
Note: The LED statuses are represented as active-low or high
depending on input strapping.
=> If Input=1: Output 0=Network loop is detected. 1=No loop.
=> If Input=0: Output 1=Network loop is detected. 0= No loop.
Note: ‘*’ indicates voltage level is 1.8V.
Single-Chip 9-Port 10/100Mbps Switch Controller
15
Default
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
6.5. Serial EEPROM and SMI Pins
Table 6. Serial EEPROM and SMI Pins
Pin Name
EnEEPROM
/LoopLED#
Pin No.
113
Type Description
Ipu/O* Input Upon Reset = Enable loading of serial EEPROM upon reset.
1: Enable Serial EEPROM load upon reset
0: Disable Serial EEPROM load upon reset
SCL_MDC
54
I/O
EEPROM Serial Clock or MDC.
This pin is three state when pin RESET#=0.
When the RTL8309G detects an EEPROM connected to it, this pin
becomes SCL (output) to load the serial EEPROM upon reset. Then the
pin changes to MDC (input) after reset. In this case, this pin should be
pulled high (VDDIO 2.5V/3.3V) by external register.
When the RTL8309G does not detect an EEPROM connected to it, this
pin is MDC (input). In this case, it needs an external pull-high resistor,
unless it is floated.
SDA_MDIO
55
I/O
EEPROM Serial Data Input/Output or MDIO.
This pin is three state when pin RESET#=0.
When the RTL8309G detects an EEPROM connected to it, this pin
becomes SDA (input/output) to load the serial EEPROM upon reset.
The pin changes to MDIO (input/output) after reset.
When the RTL8309G does not detect an EEPROM connected to it, this
pin is MDIO (input/output). It should be pulled high by an external
resistor.
Note: ‘*’ indicates voltage level is 1.8V.
Default
1
-
-
6.6. Strapping Pins
Note: All strapping pins are dual function pins: output for LED and input for strapping. The table below
covers strapping only. See Port LED Pins, on page 13, for LED pin settings.
Table 7. Strapping Pins
Pin Name
En_ANEG
/P1_LED[2]
Pin No.
104
Type
Ipu*
En_FCTRL
/P1_LED[1]
105
Ipu*
Description
Input Upon Reset = Enable Auto-negotiation function.
1: Enable the auto-negotiation function (NWay mode) and set PHY
register 0.12
0: Disable the auto-negotiation function (force mode) and deselect
PHY register 0.12
Output after reset = used for LED.
Input Upon Reset = Enable flow control ability in full duplex mode.
1: In NWay mode, this pin sets PHY register 4.10, but the flow
control function is finally enabled based on the auto negotiation
result. In force mode, this pin will always enable the flow control
function
0: Disable the flow control function
Output after reset = used for LED.
Single-Chip 9-Port 10/100Mbps Switch Controller
16
Default
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
En_BKPRS
/P1_LED[0]
Pin No.
106
Type
Ipu*
Force_Duplex
/P0_LED[3]
109
Ipu*
Force_Speed
/P0_LED[2]
110
Ipu*
En_BRD_CTRL
/P0_LED[1]
111
Ipu*
En_RST_BLNK
/P0_LED[0]
112
Ipu*
En_AutoXover
/P1_LED[3]
103
Ipu*
Dis_FC_AtuoOff
/P7_LED[3]
73
Ipu*
En_Forward
/P3_LED[2]
94
Ipu*
En_Defer
/P3_LED[3]
93
Ipu*
Description
Input Upon Reset = Enable backpressure ability in half duplex
mode.
1: Enable backpressure
0: Disable backpressure
Output after reset = used for LED.
Force Duplex Mode.
This pin sets PHY Reg.0.8 and influences the contents of PHY
Reg.4.
1: Force full duplex if auto-negotiation is disabled
0: Force half duplex if auto-negotiation is disabled
Output after reset = used for LED.
Force Operating Speed.
This pin sets PHY Reg.0.13 and influences the contents of PHY
Reg.4.
1: Force 100Mbps speed if auto-negotiation is disabled
0: Force 10Mbps speed if auto-negotiation is disabled
Output after reset = used for LED.
Input Upon Reset = Disable Broadcast Storm Control.
1: Disable Broadcast Storm Control
0: Enable Broadcast Storm Control
Output after reset = used for LED.
Input Upon Reset = Enable blinking of LEDs upon reset.
1: Enable power-on LED blinking for diagnosis
0: Disable power-on LED blinking
Output after reset = used for LED.
Input Upon Reset = Enable Auto crossover detection.
1: Enable auto crossover detection
0: Disable auto crossover detection. MDI only
Output after reset = used for LED.
Disable Auto Turn Off of Flow Control Ability.
1: Disable
0: Enable auto turn off flow control ability on the low priority queue
for 1~2 seconds whenever the port receives a high priority frame.
The flow control ability will be re-enabled if this port does not
receive another high priority frame during this 1~2 second duration.
Output after reset = used for LED.
Input Upon Reset = Enable forwarding of 802.1D specified reserved
group MAC address frames.
1: Forward reserved control packets with DID=01-80-C2-00-00-03
to 01-80-C2-00-00-0F
0: Filter reserved control packets with DID=01-80-C2-00-00-03 to
01-80-C2-00-00-0F
Output after reset = used for LED.
Input Upon Reset = Enable carrier sense defering function.
1: Enable carrier sense deferring function for half duplex
backpressure
0: Disable carrier sense deferring function for half duplex
backpressure
Output after reset = used for LED.
Single-Chip 9-Port 10/100Mbps Switch Controller
17
Default
1
1
1
1
1
1
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
En_48pass1
/P4_LED[0]
Pin No.
92
Type
Ipu*
En_Agrs_Back
/P4_LED[1]
91
Ipu*
Max_Pkt_Len
/P4_LED[2]
90
Ipu*
Max_Pause_Count
/P4_LED[3]
89
Ipu*
Dis_Trunk
/P3_LED[1]
97
Ipu*
Sel_PortPri[1:0]
/P5_LED[1:0]
85, 86
Ipu*
Dis_VLAN_Pri
/P5_LED[2]
84
Ipu*
Dis_DS_Pri
/P5_LED[3]
83
Ipu*
Description
Enable 48 Pass 1 Mechanism.
1: 48 pass 1. Continuously collides 48 input packets then passes 1
packet to retain system resources and avoid repeater partition when
buffer is full
0: Continuously collides input packets to avoid packet loss when
buffer is full
Output after reset = used for LED.
Input Upon Reset = Enable aggressive back-off mechanism.
1: Enable more aggressive back-off mechanism in half duplex mode
for performance enhancement. The back-off limitation will become
3 in this mode (default is 10)
0: Disable aggressive back-off mechanism in half duplex mode
Output after reset = used for LED.
Input Upon Reset = Select maximum frame length.
1: 1536 bytes
0: 1552 bytes
Output after reset = used for LED.
Input Upon Reset = Select the max Pause frame count during a
congested event.
1: Generates maximum of 32 pause frames, even if congestion still
exists
0: Continuously generates pause frames until congestion is resolved
Output after reset = used for LED.
Disable Two-Port Trunking Function.
1: Disable two-port trunking function
0: Port 0 and port 1 are combined as one trunk
Output after reset = used for LED.
Input Upon Reset = Select high priority port for port-based priority
QoS.
11: Disable port-based priority function
10: Select port 0 as high-priority port
01: Select port 2 as high-priority port
00: Select port 3 as high-priority port
Output after reset = used for LED.
Input Upon Reset = Disable 802.1p VLAN tag priority based QoS.
1: Disable 802.1p priority classification for ingress packets on each
port
0: Enable 802.1p priority classification for ingress packets on each
port. A User priority field in the VLAN tag greater or equal to 4 will
be considered a high priority packet
Output after reset = used for LED.
Input Upon Reset = Disable Diffserv priority based QoS.
1: Disable diffserv priority classification for ingress packets on each
port
0: Enable diffserv priority classification for ingress packets on each
port
Output after reset = used for LED.
Single-Chip 9-Port 10/100Mbps Switch Controller
18
Default
1
1
1
1
1
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Pin Name
QWeight[1:0]
/P6_LED[1:0]
Pin No.
81, 82
Type
Ipu*
Dis_VLAN
/P6_LED[2]
78
Ipu*
Dis_LeakyVLAN
/P6_LED[3]
77
Ipu*
Dis_ARPVLAN
/P7_LED[0]
76
Ipu*
LED_BLNK_TIME
/P7_LED[1]
75
Ipu*
Description
Default
1
Input Upon Reset = Weighted round robin ratio priority queue.
The frame service ratio between the high priority queue and low
priority queue is:
11: 16:1
10: Always high priority queue first
01: 8:1
00: 4:1
Output after reset = used for LED.
1
Input Upon Reset = Disable VLAN.
1: Disable VLAN
0: Enable VLAN. The default VLAN membership configuration is
MII port overlapped with all the other ports to form 8 individual
VLANs. The default membership configuration may be modified by
setting internal registers via the SMI interface or EEPROM
Output after reset = used for LED.
1
Input Upon Reset = Disable Leaky VLAN.
1: Disable forwarding of unicast frames to other VLANs
0: Enable forwarding of unicast frames to other VLANs
Note: Broadcast and multicast frames adhere to the VLAN
configuration.
Output after reset = used for LED.
1
Input Upon Reset = Disable ARP broadcast to all VLANs.
1: Disable broadcast of ARP broadcast packets to all VLANs
0: Enable broadcast of ARP broadcast packets to all VLANs
Output after reset = used for LED.
1
Input Upon Reset = Select blinking speed of activity and collision
LED.
1: On 43ms then Off 43ms
0: On 120ms then Off 120ms
Note: This pin only affects LEDs that are configured in LED mode 1,
5, and 7.
Output after reset = used for LED.
Note: ‘*’ indicates voltage level is 1.8V.
6.7. Power Pins
Table 8. Power Pins
Pin Name
VDDD
VSSD
VDDIO
Pin No.
52, 71, 79, 87, 95, 107, 114
53, 72, 80, 88, 96, 108, 115
62
Type
P
G
P
VSSIO
VDDPLL
VSSPLL
VDDA
63
120
117
1, 8, 14, 20, 26, 32, 38, 44, 123
G
P
G
P
VSSA
2, 5, 11, 17, 23, 29, 35, 41, 126
G
Single-Chip 9-Port 10/100Mbps Switch Controller
Description
1.8V Digital Power. Maximum current consumption is 0.2A.
Digital Ground.
2.5/3.3V Digital VDD for MII Interface.
Maximum current consumption is 0.003A.
Digital Ground for MII Interface.
1.8V Analog Power for PLL.
1.8V Analog Ground for PLL.
1.8V Analog Power (Used for Transmitters and Equalizers).
Maximum current consumption (VDDA+VDDPLL) is 0.7A.
Analog Ground.
19
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.
EEPROM Register Description
7.1. Global Control Registers
7.1.1.
Global Control Register0
Table 9. Global Control Register0
Name
EEPROM Existence
Accept Error Disable
IEEE 802.3x Transmit Flow
Control Enable
IEEE 802.3x Receive Flow
Control Enable
Broadcast Input or Output Drop
Aging Enable
Fast Aging Enable
Enable ISP MAC Address
Translation
Byte.bit Description
0.7
1: EEPROM does not exist
0: EEPROM exists
0.6
1: Filter bad packets in normal operation
0: Switch all packets including bad ones
0.5
1: Invoke transmit flow control based on auto-negotiation result
0: Switch will not enable transmit flow control
0.4
1: When the switch receives a pause control frame, it has the
ability to stop the next transmission of a normal frame until the
timer has expired based on the auto negotiation result
0: Receive flow control not enabled
0.3
1: Broadcast input drop is selected
0: Broadcast output drop is selected
0.2
1: Enable aging function in the switch
0: Disable aging function in the switch
0.1
1: An entry learned in the lookup table will be aged out if it is not
updated within an 800µs period
0: Disable fast aging function. The normal aging time of the
RTL8309G is around 200~300 seconds
0.0
1: Enable ISP MAC Address Translation
0: Disable ISP MAC Address Translation
Single-Chip 9-Port 10/100Mbps Switch Controller
20
Default
0
1
1
1
1
1
0
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.1.2.
Global Control Register1
Table 10. Global Control Register1
Name
LED Mode
Reserved
Disable VLAN
Disable 802.1Q Tag
Aware VLAN
Disable VLAN
Member Set Ingress
Filtering
Disable VLAN Tag
Admit Control
7.1.3.
Byte.bit Description
Default
111
1.7~1.5 111: Mode 7: Speed, Duplex+Collision, Link+Act, SQI
110: Mode 6: Activity, Speed, Link, SQI
101: Mode 5: Speed, Duplex, Link+Act, Bi-color Link+Act
100: Mode 4: Collision, Duplex, Link+Act+Speed, SQI
011: Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100
010: Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI
001: Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI
000: Mode 0: Duplex+Collision, Bi-color Speed, Bi-color Link+Act, SQI
1.4
Reserved
1
1.3
1: Disable VLAN
1
0: Enable VLAN
1.2
1: Disable the 802.1Q tagged-VID Aware function
0
0: Use tagged-VID VLAN mapping for tagged frames but still use
Port-Based VLAN mapping for priority-tagged and untagged frame
1.1
1
1: The switch will not drop the received frame if the ingress port of this
packet is not included in the matched VLAN member set
0: The switch will drop the received frame if the ingress port of this packet is
not included in the matched VLAN member set
1.0
1: The switch accepts all frames received
1
0: The switch will only accept tagged frames and will drop untagged frames
Global Control Register2
Table 11. Global Control Register2
Name
Enable Default High
Priority DiffServ
Code Point
Reserved
Byte.bit Description
2.7
1: The default DiffServ code point listed below will be considered a high
priority code point if DiffServ priority function is enabled
EF – 101110
AF – 001010, 010010, 011010, 100010
Network Control – 111000, 110000
0: The default DiffServ code point will be considered low priority
2.6~2.0 Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
21
Default
1
1111
111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.1.4.
Global Control Register3
Table 12. Global Control Register3
Name
802.1p Base Priority
Byte.bit Description
3.7~3.5 Used to classify priority for incoming 802.1Q packets when 802.1p priority
classification is enabled. ‘User priority’ compares against this value.
≥: Classify as high priority
<: Classify as low priority
3.4
Trunking Port
1: Combine port 0 and 1 as one trunking port, if trunking is enabled by
Assignment
strapping pin ‘Dis_Trunk’
0: Combine port 6 and 7 as one trunking port, if trunking is enabled by
strapping pin ‘Dis_Trunk’
Queue Weight
3.3~3.2 The frame service ratio between the high priority queue and low priority
queue is:
11: 16:1
10: Always high priority queue first
01: 8:1
00: 4:1
3.1
Disable IP Priority for
1: The switch will compare both the source and destination IP addresses of
IP Address [A]
an incoming packet against the value, IP address [A] AND IP mask [A], to
classify priority for the packet
0: The switch will not compare the source or destination IP addresses of an
incoming packet against the value, IP address [A] AND IP mask [A]
3.0
Disable IP Priority for
1: The switch will compare both the source and destination IP addresses of
IP Address [B]
an incoming packet against the value, IP address [B] AND IP mask [B], to
classify priority for the packet
0: The switch will not compare the source and destination IP addresses of
an incoming packet against the value, IP address [B] AND IP mask [B]
7.1.5.
Default
100
1
11
0
0
Global Control Register4
Table 13. Global Control Register4
Name
Enable Differential
Service Code Point [B]
Reserved
Differential Service
Code Point [B]
Byte.bit Description
4.7
1: If Differential Service Priority is enabled, this bit specifies differential
service code point [B] is high priority
0: If Differential Service Priority is enabled, this bit specifies differential
service code point [B] is low priority
4.6
Reserved
4.5~4.0 Used to specify a high priority differential service code point B. For
example, if these bits are set to ‘000000’, all incoming packets with a TOS
field equal to ‘000000’ will be considered high priority packets.
Single-Chip 9-Port 10/100Mbps Switch Controller
22
Default
0
1
111111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.1.6.
Global Control Register5
Table 14. Global Control Register5
Name
Enable Differential Service
Code Point [A]
Reserved
Differential Service Code
Point [A]
7.1.7.
Byte.bit Description
5.7
1: If Differential Service Priority is enabled, this bit specifies
differential service code point [A] is high priority
0: If Differential Service Priority is enabled, this bit specifies
differential service code point [A] is low priority
5.6
Reserved
5.5~5.0 Used to specify a high priority differential service code point A. For
example, if these bits are set to ‘111111’, all incoming packets with a
TOS field equal to ‘000000’ will be considered high priority packets.
Default
0
1
111111
Global Control Register6
Table 15. Global Control Register6
Name
Reserved
7.1.8.
Byte.bit Description
6.7~6.0 Reserved
Default
0000
0001
Global Control Register7
Table 16. Global Control Register7
Name
Enable Drop for 48 Pass 1
Reserved
TX IPG Compensation
Disable Loop Detection
Reserved
Lookup Table Accessible
Enable
Reserved
Byte.bit Description
7.7
1: Enable drop packet when SRAM full for 48 pass 1
0: Disable drop packet when SRAM full for 48 pass 1. This will result
in SRAM run out
7.6
Reserved
7.5
1: 90ppm TX IPG compensation
0: 65ppm TX IPG compensation
7.4
1: Disable loop detection function
0: Enable loop detection function
7.3
Reserved
7.2
1: Lookup table is accessible via indirect access registers
0: Lookup table is not accessible
7.1~7.0 Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
23
Default
1
1
1
1
1
0
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2. Port 0~7 Control Pins
7.2.1.
Port 0 Control 0
Table 17. Port 0 Control 0
Name
Reserved
Speed and Duplex Ability
Reserved
Backpressure Enable
VLAN Tag Insertion and
Removal
7.2.2.
Byte.bit Description
8.7~8.6 Reserved
8.5~8.4 In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
8.3
Reserved
8.2
1: Enable port 0 half duplex backpressure
0: Disable port 0 half duplex backpressure
8.1~8.0 11: Do not insert or remove VLAN tags to/from packet
10: Insert PVID to non-tagged packets
01: Remove tag from tagged packets
00: Replace the VID with a PVID for tagged packets and insert a
PVID to non-tagged packets
Default
11
11
1
1
11
Port 0 Control 1
Table 18. Port 0 Control 1
Name
Reserved
Local Loopback
Null VID Replacement
Discard Non PVID Packets
Disable 802.1p Priority
Disable Diffserv Priority
Disable Port-Based Priority
Byte.bit Description
9.7~9.6 Reserved
9.5
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to TX
0: Normal operation
9.4
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
9.3
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
9.2
1: Disable 802.1p priority classification for ingress packets on port 0
0: Enable 802.1p priority classification on port 0
9.1
1: Disable Diffserv priority classification for ingress packets on port 0
0: Enable Diffserv priority classification on Port 0
9.0
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 0 will be
classified as high priority
Single-Chip 9-Port 10/100Mbps Switch Controller
24
Default
11
0
0
0
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.3.
Port 0 Control 2
Table 19. Port 0 Control 2
Name
Reserved
7.2.4.
Byte.bit
10.7~10.0
Description
Reserved
Default
1111
1000
Port 0 Control 3
Table 20. Port 0 Control 3
Name
Reserved
Transmission Enable
Byte.bit
11.7~11.4
11.3
Reception Enable
11.2
Learning Enable
11.1
Reserved
11.0
VLAN ID [A]
Membership Bit [7:0]
12.7~12.0
Description
Reserved
1: Enable packet transmission on port 0
0: Disable packet transmission on port 0
1: Enable packet reception on port 0
0: Disable packet reception on port 0
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [A]
This register along with byte 13.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this
VLAN.
Single-Chip 9-Port 10/100Mbps Switch Controller
25
Default
1111
1
1
1
1
0000
0001
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.5.
Port 0 Control 4
Table 21. Port 0 Control 4
Name
Port 0 VLAN Index
[3:0]
Byte.bit
13.7~13.4
Reserved
VLAN ID [A]
Membership Bit [8]
13.3~13.1
13.0
VLAN ID [A] [7:0]
14.7~14.0
Reserved
VLAN ID [A] [11:8]
15.7~15.4
15.3~15.0
7.2.6.
Description
In a port-based VLAN configuration, this register indexes port 0’s ‘Port
VLAN Membership’, which may be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 0 can
only communicate within the membership. This register also indexes to
a default Port VID (PVID) for each port. The PVID is used in tag
insertion and filtering if the tagged VID is not the same as the PVID.
Reserved
This register along with byte 12.7~12.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this
VLAN.
VLAN Entry [A]
This register along with byte 15.3~15.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN A.
Reserved
This register along with byte 14.7~14.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN A.
Default
0000
111
1
0000
0000
1111
0000
IP Address
Table 22. IP Address
Name
Byte.bit
IP Address [A] [16:23]
16.7~16.0
IP Address [A] [31:24]
17.7~17.0
IP Address [A] [7:0]
18.7~18.0
IP Address [A] [15:8]
19.7~19.0
IP Address [B] [16:23]
20.7~20.0
Description
Default
IP Address [A]
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
IP Address [B]
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet.
Single-Chip 9-Port 10/100Mbps Switch Controller
26
0xff
0xff
0xff
0xff
0xff
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Name
IP Address [B] [31:24]
Byte.bit
21.7~21.0
IP Address [B] [7:0]
22.7~22.0
IP Address [B] [15:8]
23.7~23.0
7.2.7.
Description
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet.
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet.
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet.
Default
0xff
0xff
0xff
Port 1 Control 0
Table 23. Port 1 Control 0
Name
Reserved
Speed and Duplex
Ability
Byte.bit
24.7~24.6
24.5~24.4
Reserved
Backpressure Enable
24.3
24.2
VLAN Tag Insertion
and Removal
24.1~24.0
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 1 half duplex backpressure
0: Disable port 1 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packets.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and insert a PVID
to non-tagged packets.
Single-Chip 9-Port 10/100Mbps Switch Controller
27
Default
11
11
1
1
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.8.
Port 1 Control 1
Table 24. Port 1 Control 1
Name
Reserved
Local Loopback
Byte.bit Description
Default
25.7~25.6 Reserved
11
25.5
1: Perform ‘local loopback’, i.e. loop back MAC’s RX back to TX
0
0: Normal operation
Null VID Replacement
25.4
1: The switch will replace a NULL VID with a port VID (12 bits)
0
0: No replacement for a NULL VID
Discard Non PVID Packets
25.3
0
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
Disable 802.1p Priority
25.2
1: Disable 802.1p priority classification for ingress packets on port 1
1
0: Enable 802.1p priority classification
Disable Diffserv Priority
25.1
1: Disable Diffserv priority classification for ingress packets on port 1
1
0: Enable Diffserv priority classification
Disable Port-Based Priority
25.0
1: Disable port priority function
1
0: Enable port priority function. Ingress packets from port 1 will be
classified as high priority
7.2.9.
Port 1 Control 2
Table 25. Port 1 Control 2
Name
Reserved
Byte.bit Description
26.7~26.0 Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
Default
1111
1000
28
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.10.
Port 1 Control 3
Table 26. Port 1 Control 3
Name
Reserved
Transmission Enable
Byte.bit Description
27.7~27.4 Reserved
27.3
1: Enable packet transmission on port 1
0: Disable packet transmission on port 1
Reception Enable
27.2
1: Enable packet reception on port 1
0: Disable packet reception on port 1
Learning Enable
27.1
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
27.0
Reserved
VLAN Entry [B]
VLAN ID [B] Membership 28.7~28.0 This register along with byte 29.0 forms a 9-bit field that specifies
Bit [7:0]
which ports are members of the VLAN. If a destination address look
up fails, packets associated with this VLAN will be forwarded to
ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are
in this VLAN.
7.2.11.
Default
1111
1
1
1
1
0000
0010
Port 1 Control 4
Table 27. Port 1 Control 4
Name
Port 1 VLAN Index [3:0]
Byte.bit Description
Default
29.7~29.4 In a port-based VLAN configuration, this register indexes port 1’s
0001
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 1 can only communicate within the membership.
This register also indexes to a default Port VID (PVID) for each port.
The PVID is used in tag insertion and filtering if the tagged VID is
not the same as the PVID.
Reserved
29.3~29.1 Reserved
111
29.0
1
VLAN ID [B] Membership
This register along with byte 28.7~28.0 forms a 9-bit field that
Bit [8]
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001 means
port 8 and 0 are in this VLAN.
VLAN Entry [B]
VLAN ID [B] [7:0]
30.7~30.0 This register along with byte 31.3~31.0 defines the IEEE 802.1Q 120000
bit VLAN identifier of VLAN B.
0001
Reserved
31.7~31.4 Reserved
1111
VLAN ID [B] [11:8]
31.3~31.0 This register along with byte 30.7~30.0 defines the IEEE 802.1Q 120000
bit VLAN identifier of VLAN B.
Single-Chip 9-Port 10/100Mbps Switch Controller
29
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.12.
IP Mask
Table 28. IP Mask
Name
Byte.bit
IP Mask [A] [16:23]
32.7~32.0
IP Mask [A] [31:24]
33.7~33.0
IP Mask [A] [7:0]
34.7~34.0
IP Mask [A] [15:8]
35.7~35.0
IP Mask [B] [16:23]
36.7~36.0
IP Mask [B] [31:24]
37.7~37.0
IP Mask [B] [7:0]
38.7~38.0
IP Mask [B] [15:8]
39.7~39.0
7.2.13.
Description
Default
IP Mask [A]
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [A]
AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [A]
AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [A]
AND IP mask [A], to classify priority for the packet.
If IP priority for IP address [A] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [A]
AND IP mask [A], to classify priority for the packet.
IP Mask [B]
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [B]
AND IP mask [B], to classify priority for the packet.
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [B]
AND IP mask [B], to classify priority for the packet.
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [B]
AND IP mask [B], to classify priority for the packet.
If IP priority for IP address [B] is enabled, the switch will compare the
source IP address of an incoming packet against the value, IP address [B]
AND IP mask [B], to classify priority for the packet.
0xff
0xff
0xff
0xff
0xff
0xff
0xff
0xff
Port 2 Control 0
Table 29. Port 2 Control 0
Name
Reserved
Speed and Duplex
Ability
Byte.bit
40.7~40.6
40.5~40.4
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Single-Chip 9-Port 10/100Mbps Switch Controller
30
Default
11
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Name
Reserved
Backpressure Enable
Byte.bit
40.3
40.2
VLAN Tag Insertion
and Removal
40.1~40.0
7.2.14.
Description
Reserved
1: Enable port 2 half duplex backpressure
0: Disable port 2 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packets.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace VID with PVID for tagged packets and insert PVID to nontagged packets.
Default
1
1
11
Port 2 Control 1
Table 30. Port 2 Control 1
Name
Reserved
Local Loopback
Byte.bit
41.7~41.6
41.5
Null VID Replacement
41.4
Discard Non PVID
Packets
41.3
Disable 802.1p Priority
41.2
Disable Diffserv
Priority
41.1
Disable Port-Based
Priority
41.0
7.2.15.
Description
Reserved
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to TX
0: Normal operation
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
1: Disable 802.1p priority classification for ingress packets on port 2
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on port 2
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 2 will be
classified as high priority
Default
11
0
0
0
1
1
1
Port 2 Control 2
Table 31. Port 2 Control 2
Name
Reserved
Byte.bit
42.7~42.0
Description
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
Default
1111
1000
31
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.16.
Port 2 Control 3
Table 32. Port 2 Control 3
Name
Reserved
Transmission Enable
Byte.bit
43.7~43.4
43.3
Reception Enable
43.2
Learning Enable
43.1
Reserved
43.0
VLAN ID [C]
Membership Bit [7:0]
7.2.17.
44.7~44.0
Description
Reserved
1: Enable packet transmission on port 2
0: Disable packet transmission on port 2
1: Enable packet reception on port 2
0: Disable packet reception on port 2
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [C]
This register along with byte 45.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look
up fails, packets associated with this VLAN will be forwarded to
ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are
in this VLAN.
Default
1111
1
1
1
1
0000
0100
Port 2 Control 4
Table 33. Port 2 Control 4
Name
Port 2 VLAN Index [3:0]
Byte.bit
45.7~45.4
Reserved
VLAN ID [C]
Membership Bit [8]
45.3~45.1
45.0
VLAN ID [C] [7:0]
46.7~46.0
Reserved
VLAN ID [C] [11:8]
47.7~47.4
47.3~47.0
Description
In a port-based VLAN configuration, this register indexes port 2’s
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I] Membership’.
Port 2 can only communicate within the membership. This register
also indexes to a default Port VID (PVID) for each port. The PVID is
used in tag insertion and filtering if the tagged VID is not the same as
the PVID.
Reserved
This register along with byte 44.7~44.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001 means
port 8 and 0 are in this VLAN.
VLAN Entry [C]
This register along with byte 47.3~47.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN C.
Reserved
This register along with byte 46.7~46.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN C.
Single-Chip 9-Port 10/100Mbps Switch Controller
32
Default
0010
111
1
0000
0010
1111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.18.
Switch MAC Address
The Switch MAC address is used as the source address in MAC pause control frames.
Table 34. Switch MAC Address
Name
Switch MAC Address [47:40]
Switch MAC Address [39:32]
Switch MAC Address [31:24]
Switch MAC Address [23:16]
Switch MAC Address [15:8]
Switch MAC Address [7:0]
7.2.19.
Byte.bit
48.7~48.0
49.7~49.0
50.7~50.0
51.7~51.0
52.7~52.0
53.7~53.0
Description
Switch MAC Address Byte 5.
Switch MAC Address Byte 4.
Switch MAC Address Byte 3.
Switch MAC Address Byte 2.
Switch MAC Address Byte 1.
Switch MAC Address Byte 0.
Default
0x52
0x54
0x4C
0x83
0x09
0xB0
Port 3 Control 0
Table 35. Port 3 Control 0
Name
Reserved
Speed and Duplex Ability
Reserved
Backpressure Enable
VLAN Tag Insertion and Removal
Byte.bit
54.7~54.6
54.5~54.4
54.3
54.2
54.1~54.0
Single-Chip 9-Port 10/100Mbps Switch Controller
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 3 half duplex backpressure.
0: Disable port 3 half duplex backpressure.
11: Do not insert or remove VLAN tags to/from packets.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and
insert a PVID to non-tagged packets.
33
Default
11
11
1
1
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.20.
Port 3 Control 1
Table 36. Port 3 Control 1
Name
Reserved
Local Loopback
Byte.bit
55.7~55.6
55.5
Null VID Replacement
55.4
Discard Non PVID Packets
55.3
Disable 802.1p Priority
55.2
Disable Diffserv Priority
55.1
Disable Port-Based Priority
55.0
7.2.21.
Description
Reserved
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to
TX
0: Normal operation
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard
packets whose VID does not match the ingress port’s PVID
0: No packets will be dropped
1: Disable 802.1p priority classification for ingress packets on
port 3
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on
port 3
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 3 will
be classified as high priority
Default
11
0
0
0
1
1
1
Port 3 Control 2
Table 37. Port 3 Control 2
Name
Reserved
Byte.bit
56.7~56.0
Description
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
Default
1111
1000
34
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.22.
Port 3 Control 3
Table 38. Port 3 Control 3
Name
Reserved
Transmission Enable
Byte.bit
57.7~57.4
57.3
Reception Enable
57.2
Learning Enable
57.1
Reserved
57.0
VLAN ID [D] Membership
Bit [7:0]
7.2.23.
58.7~58.0
Description
Reserved
1: Enable packet transmission on port 3
0: Disable packet transmission on port 3
1: Enable packet reception on port 3
0: Disable packet reception on port 3
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [D]
This register along with byte 59.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001
means port 8 and 0 are in this VLAN.
Default
1111
1
1
1
1
0000
1000
Port 3 Control 4
Table 39. Port 3 Control 4
Name
Port 3 VLAN Index [3:0]
Byte.bit
59.7~59.4
Reserved
VLAN ID [D] Membership
Bit [8]
59.3~59.1
59.0
VLAN ID [D] [7:0]
60.7~60.0
Reserved
VLAN ID [D] [11:8]
61.7~61.4
61.3~61.0
Description
In a port-based VLAN configuration, this register indexes port
3’s ‘Port VLAN Membership’, which may be defined in one of
the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 3 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
This register along with byte 58.7~58.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001
means port 8 and 0 are in this VLAN.
VLAN Entry [D]
This register along with byte 61.3~61.0 defines the IEEE 802.1Q
12-bit VLAN identifier of VLAN D.
Reserved
This register along with byte 60.7~60.0 defines the IEEE 802.1Q
12-bit VLAN identifier of VLAN D.
Single-Chip 9-Port 10/100Mbps Switch Controller
35
Default
0011
111
1
0000
0011
1111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.24.
ISP MAC Address
The ISP MAC address is used as the source address in MAC address translation.
Table 40. ISP MAC Address
Name
ISP MAC Address [47:40]
ISP MAC Address [39:32]
ISP MAC Address [31:24]
ISP MAC Address [23:16]
ISP MAC Address [15:8]
ISP MAC Address [7:0]
7.2.25.
Byte.bit
62.7~62.0
63.7~63.0
64.7~64.0
65.7~65.0
66.7~66.0
67.7~67.0
Description
ISP MAC Address Byte 5.
ISP MAC Address Byte 4.
ISP MAC Address Byte 3.
ISP MAC Address Byte 2.
ISP MAC Address Byte 1.
ISP MAC Address Byte 0.
Default
0x05
0x42
0x2F
0x21
0x91
0x5C
Port 4 Control 0
Table 41. Port 4 Control 0
Name
Reserved
Speed and Duplex Ability
Reserved
Backpressure Enable
VLAN Tag Insertion and Removal
Byte.bit
68.7~68.6
68.5~68.4
68.3
68.2
68.1~68.0
Single-Chip 9-Port 10/100Mbps Switch Controller
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 4 half duplex backpressure
0: Disable port 4 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packet.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and
insert a PVID to non-tagged packets.
36
Default
11
11
1
1
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.26.
Port 4 Control 1
Table 42. Port 4 Control 1
Name
Reserved
Local Loopback
Byte.bit
69.7~68.6
69.5
Null VID Replacement
69.4
Discard Non PVID
Packets
69.3
Disable 802.1p Priority
69.2
Disable Diffserv Priority
69.1
Disable Port-Based
Priority
69.0
7.2.27.
Description
Reserved
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to TX
0: Normal operation
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
1: Disable 802.1p priority classification for ingress packets on port 4
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on port 4
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets on port 4 will be
classified as high priority
Default
11
0
0
0
1
1
1
Port 4 Control 2
Table 43. Port 4 Control 2
Name
Reserved
Byte.bit
70.7~70.0
Description
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
Default
1111
1000
37
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.2.28.
Port 4 Control 3
Table 44. Port 4 Control 3
Name
Reserved
Transmission Enable
Byte.bit
71.7~71.4
71.3
Reception Enable
71.2
Learning Enable
71.1
Reserved
71.0
VLAN ID [E]
Membership Bit[7:0]
7.2.29.
72.7~72.0
Description
Reserved
1: Enable packet transmission on port 4
0: Disable packet transmission on port 4
1: Enable packet reception on port 4
0: Disable packet reception on port 4
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [E]
This register along with byte 73.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look
up fails, packets associated with this VLAN will be forwarded to
ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are
in this VLAN.
Default
1111
1
1
1
1
0001
0000
Port 4 Control 4
Table 45. Port 4 Control 4
Name
Port 4 VLAN Index [3:0]
Byte.bit
73.7~73.4
Reserved
VLAN ID [E]
Membership Bit[8]
73.3~73.1
73.0
VLAN ID [E] [7:0]
74.7~74.0
Reserved
VLAN ID [E] [11:8]
75.7~75.4
75.3~75.0
Description
In a port-based VLAN configuration, this register indexes port 4’s
‘Port VLAN Membership’, which could be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I] Membership’.
Port 4 can only communicate within the membership. This register
also indexes to a default Port VID (PVID) for each port. The PVID is
used in tag insertion and filtering if the tagged VID is not the same as
the PVID.
Reserved
This register along with byte 72.7~72.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001 means
port 8 and 0 are in this VLAN.
VLAN Entry [E]
This register along with byte 75.3~75.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN E.
Reserved
This register along with byte 74.7~74.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN E.
Single-Chip 9-Port 10/100Mbps Switch Controller
38
Default
0100
111
1
0000
0100
1111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.3. MII Port Control Pins
7.3.1.
MII Port Control 0
Table 46. MII Port Control 0
Name
Reserved
Byte.bit
76.7~76.2
Description
Reserved
VLAN Tag Insertion and
Removal
76.1~76.0
11: Do not insert or remove VLAN tags to/from packets.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and insert a
PVID to non-tagged packets.
7.3.2.
Default
1111
11
11
MII Port Control 1
Table 47. MII Port Control 1
Name
Transmission Enable
Byte.bit
77.7
Reception Enable
77.6
Learning Enable
77.5
Reserved
Disable 802.1p Priority
77.4
77.3
Disable Diffserv Priority
77.2
Disable Port-Based Priority
77.1
Reserved
77.0
VLAN ID [I] Membership
Bit [7:0]
78.7~78.0
Description
1: Enable packet transmission on MII interface
0: Disable packet transmission on MII interface
1: Enable packet reception on MII interface
0: Disable packet reception on MII interface
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
1: Disable 802.1p priority classification for ingress packets on
MII port
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on
MII port
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets from the MII
port will be classified as high priority
Reserved
VLAN Entry [I]
This register along with byte 79.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001
means port 8 and 0 are in this VLAN.
Single-Chip 9-Port 10/100Mbps Switch Controller
39
Default
1
1
1
0
1
1
1
0
1111
1111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.3.3.
MII Port Control 2
Table 48. MII Port Control 2
Name
Null VID Replacement
Discard Non PVID
Packets
Reserved
Port 8 VLAN Index [3:0]
Byte.bit
79.7
79.6
79.5
79.4~79.1
VLAN ID [I]
Membership Bit [8]
79.0
VLAN ID [I] [7:0]
80.7~80.0
Reserved
VLAN ID [I] [11:8]
81.7~81.4
81.3~81.0
7.3.4.
Description
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard packets
with a VID that does not match the ingress port default VID, which is
indexed by port 8’s ‘Port-based VLAN index’
0: No packets will be dropped
Reserved
In a port-based VLAN configuration, this register indexes port 8’s
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I] Membership’.
Port 8 can only communicate within the membership. This register
also indexes to a default Port VID (PVID) for each port. The PVID is
used in tag insertion and filtering if the tagged VID is not the same as
the PVID.
This register along with byte 78.7~78.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001 means
port 8 and 0 are in this VLAN.
VLAN Entry [I]
This register along with byte 81.3~81.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN I.
Reserved
This register along with byte 80.7~80.0 defines the IEEE 802.1Q 12bit VLAN identifier of VLAN I.
Default
0
0
1
1000
1
0000
1000
1111
0000
CPU Port and WAN Port
Table 49. CPU Port and WAN Port
Name
WAN Port
Byte.bit
82.7~82.4
CPU Port
82.3~82.0
Description
Specifies the WAN port on the RTL8309G.
1000: MII Port is WAN Port
0111: Port 7 is WAN Port
0110: Port 6 is WAN Port
0101: Port 5 is WAN Port
0100: Port 4 is WAN Port
0011: Port 3 is WAN Port
0010: Port 2 is WAN Port
0001: Port 1 is WAN Port
0000: Port 0 is WAN Port
Specifies the CPU port on the RTL8309G.
1000: MII Port is CPU Port
0111: Port 7 is CPU Port
0110: Port 6 is CPU Port
0101: Port 5 is CPU Port
0100: Port 4 is CPU Port
0011: Port 3 is CPU Port
0010: Port 2 is CPU Port
0001: Port 1 is CPU Port
0000: Port 0 is CPU Port
Single-Chip 9-Port 10/100Mbps Switch Controller
40
Default
0111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4. Port 5~7 Control Pins
7.4.1.
Port 5 Control 0
Table 50. Port 5 Control 0
Name
Reserved
Speed and Duplex
Ability
Byte.bit
83.7~83.6
83.5~83.4
Reserved
Backpressure Enable
83.3
83.2
VLAN Tag Insertion
and Removal
83.1~83.0
7.4.2.
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 5 half duplex backpressure
0: Disable port 5 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packet.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
Default
11
11
1
1
11
Port 5 Control 1
Table 51. Port 5 Control 1
Name
Reserved
Local Loopback
Byte.bit
84.7~84.6
84.5
Null VID Replacement
84.4
Discard Non PVID
Packets
84.3
Disable 802.1p Priority
84.2
Disable Diffserv Priority
84.1
Disable Port-Based
Priority
84.0
Description
Reserved
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to TX
0: Normal operation
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
1: Disable 802.1p priority classification for ingress packets on port 5
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on port 5
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 5 will be
classified as high priority
Single-Chip 9-Port 10/100Mbps Switch Controller
41
Default
11
0
0
0
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.3.
Port 5 Control 2
Table 52. Port 5 Control 2
Name
Reserved
7.4.4.
Byte.bit
85.7~85.0
Description
Reserved
Default
1111
1000
Port 5 Control 3
Table 53. Port 5 Control 3
Name
Reserved
Transmission Enable
Byte.bit
86.7~86.4
86.3
Reception Enable
86.2
Learning Enable
86.1
Reserved
86.0
VLAN ID [F]
Membership Bit [7:0]
87.7~87.0
Description
Reserved
1: Enable packet transmission on port 5
0: Disable packet transmission on port 5
1: Enable packet reception on port 5
0: Disable packet reception on port 5
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [F]
This register, along with byte 88.0, forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this
VLAN.
Single-Chip 9-Port 10/100Mbps Switch Controller
42
Default
1111
1
1
1
1
0010
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.5.
Port 5 Control 4
Table 54. Port 5 Control 4
Name
Port 5 VLAN Index
[3:0]
Reserved
VLAN ID [F]
Membership Bit [8]
VLAN ID [F] [7:0]
Reserved
VLAN ID [F] [11:8]
7.4.6.
Byte.bit Description
88.7~88.4 In a port-based VLAN configuration, this register indexes port 5’s ‘Port
VLAN Membership’, which may be defined in one of the registers
‘VLAN ID [A] Membership’ to ‘VLAN ID [I] Membership’. Port 5 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
88.3~88.1 Reserved
88.0
This register along with byte 87.7~87.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this
VLAN.
VLAN Entry [F]
89.7~89.0 This register along with byte 90.3~90.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN F.
90.7~90.4 Reserved
90.3~90.0 This register along with byte 89.7~89.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN F.
Default
0101
111
1
0000
0101
1111
0000
Port 6 Control 0
Table 55. Port 6 Control 0
Name
Reserved
Speed and Duplex
Ability
Byte.bit
91.7~91.6
91.5~91.4
Reserved
Backpressure Enable
91.3
91.2
VLAN Tag Insertion
and Removal
91.1~91.0
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 6 half duplex backpressure
0: Disable port 6 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packet.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and insert a PVID
to non-tagged packets.
Single-Chip 9-Port 10/100Mbps Switch Controller
43
Default
11
11
1
1
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.7.
Port 6 Control 1
Table 56. Port 6 Control 1
Name
Reserved
Local Loopback
Byte.bit
92.7~92.6
92.5
Null VID Replacement
92.4
Discard Non PVID
Packets
92.3
Disable 802.1p Priority
92.2
Disable Diffserv Priority
92.1
Disable Port-Based
Priority
92.0
7.4.8.
Description
Reserved
1: Perform ‘local loopback’, i.e., loop back MAC’s RX back to TX
0: Normal operation
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
1: If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID
0: No packets will be dropped
1: Disable 802.1p priority classification for ingress packets on port 6
0: Enable 802.1p priority classification
1: Disable Diffserv priority classification for ingress packets on port 6
0: Enable Diffserv priority classification
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 6 will be
classified as high priority
Default
11
0
0
0
1
1
1
Port 6 Control 2
Table 57. Port 6 Control 2
Name
Reserved
Byte.bit
93.7~93.0
Description
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
Default
1111
1000
44
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.9.
Port 6 Control 3
Table 58. Port 6 Control 3
Name
Reserved
Transmission Enable
Reception Enable
Learning Enable
Reserved
VLAN ID [G]
Membership Bit [7:0]
7.4.10.
Byte.bit Description
94.7~94.4 Reserved
94.3
1: Enable packet transmission on port 6
0: Disable packet transmission on port 6
94.2
1: Enable packet reception on port 6
0: Disable packet reception on port 6
94.1
1: Enable switch address learning capability
0: Disable switch address learning capability
94.0
Reserved
VLAN Entry [G]
95.7~95.0 This register along with byte 96.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified
in this field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
1111
1
1
1
0
0100
0000
Port 6 Control 4
Table 59. Port 6 Control 4
Name
Port 6 VLAN Index
[3:0]
Reserved
VLAN ID [G]
Membership Bit [8]
VLAN ID [G] [7:0]
Reserved
VLAN ID [G] [11:8]
Byte.bit Description
96.7~96.4 In a port-based VLAN configuration, this register indexes port 6’s ‘Port
VLAN Membership’, which may be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 6 can
only communicate within the membership. This register also indexes to
a default Port VID (PVID) for each port. The PVID is used in tag
insertion and filtering if the tagged VID is not the same as the PVID.
96.3~96.1 Reserved
96.0
This register along with byte 95.7~95.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0 are in this
VLAN.
VLAN Entry [G]
97.7~97.0 This register along with byte 98.3~98.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN G.
98.7~98.4 Reserved
98.3~98.0 This register along with byte 97.7~97.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN C.
Single-Chip 9-Port 10/100Mbps Switch Controller
45
Default
0110
111
1
0000
0110
1111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.11.
Port 7 Control 0
Table 60. Port 7 Control 0
Name
Reserved
Speed and Duplex
Ability
Byte.bit
99.7~99.6
99.5~99.4
Reserved
Backpressure Enable
99.3
99.2
VLAN Tag Insertion
and Removal
99.1~99.0
7.4.12.
Description
Reserved
In Auto Negotiation Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force Mode:
11: MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10: MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01: MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00: MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
Reserved
1: Enable port 7 half duplex backpressure
0: Disable port 7 half duplex backpressure
11: Do not insert or remove VLAN tags to/from packet.
10: Insert PVID to non-tagged packets.
01: Remove tag from tagged packets.
00: Replace the VID with a PVID for tagged packets and insert a PVID
to non-tagged packets.
Default
11
11
1
1
11
Port 7 Control 1
Table 61. Port 7 Control 1
Name
Reserved
Local Loopback
Null VID
Replacement
Discard Non PVID
Packets
Disable 802.1p
Priority
Disable Diffserv
Priority
Disable Port-Based
Priority
Byte.bit
Description
100.7~100.6 Reserved
100.5
1: Perform ‘local loopback’, i.e. loop back MAC’s RX back to TX
0: Normal operation
100.4
1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
100.3
1: If the received packets are tagged, the switch will discard packets
whose VID does not match ingress port’s PVID
0: No packets will be dropped
100.2
1: Disable 802.1p priority classification for ingress packets on port 7
0: Enable 802.1p priority classification
100.1
1: Disable Diffserv priority classification for ingress packets on port 7
0: Enable Diffserv priority classification
100.0
1: Disable port priority function
0: Enable port priority function. Ingress packets from port 7 will be
classified as high priority
Single-Chip 9-Port 10/100Mbps Switch Controller
46
Default
11
0
0
0
1
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.13.
Port 7 Control 2
Table 62. Port 7 Control 2
Name
Reserved
7.4.14.
Byte.bit
101.7~101.0
Description
Reserved
Default
1111
1000
Port 7 Control 3
Table 63. Port 7 Control 3
Name
Reserved
Transmission Enable
Byte.bit
102.7~102.4
102.3
Reception Enable
102.2
Learning Enable
102.1
Reserved
102.0
VLAN ID [H]
Membership Bit [7:0]
103.7~103.0
Description
Reserved
1: Enable packet transmission on port 7
0: Disable packet transmission on port 7
1: Enable packet reception on port 7
0: Disable packet reception on port 7
1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
VLAN Entry [H]
This register along with byte 104.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look
up fails, packets associated with this VLAN will be forwarded to
ports specified in this field. E.g., 1 0000 0001 means port 8 and 0 are
in this VLAN.
Single-Chip 9-Port 10/100Mbps Switch Controller
47
Default
1111
1
1
1
1
1000
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
7.4.15.
Port 7 Control 4
Table 64. Port 7 Control 4
Name
Port 7 VLAN Index
[3:0]
Byte.bit
104.7~104.4
Reserved
VLAN ID [H]
Membership Bit [8]
104.3~104.1
104.0
VLAN ID [H] [7:0]
105.7~105.0
Reserved
VLAN ID [H] [11:8]
106.7~106.4
106.3~106.0
Description
In a port-based VLAN configuration, this register indexes port 7’s
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I] Membership’.
Port 7 can only communicate within the membership. This register
also indexes to a default Port VID (PVID) for each port. The PVID is
used in tag insertion and filtering if the tagged VID is not the same as
the PVID.
Reserved
This register along with byte 103.7~103.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g., 1 0000 0001 means
port 8 and 0 are in this VLAN.
VLAN Entry [H]
This register along with byte 106.3~106.0 defines the IEEE 802.1Q
12-bit VLAN identifier of VLAN H.
Reserved
This register along with byte 105.7~105.0 defines the IEEE 802.1Q
12-bit VLAN identifier of VLAN H.
Single-Chip 9-Port 10/100Mbps Switch Controller
48
Default
0111
111
1
0000
0111
1111
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.
PHY Registers Description
Mode codes used in the following tables:
RO: Read Only
LH: Latch High Until Clear
RW: Read/Write
LL: Latch Low Until Clear
SC: Self Clearing
8.1. PHY 0 Registers
8.1.1.
PHY 0 Register 0: Control
PHY address (Port 0 ~ port 7) = 0x0 ~ 0x7. PHY address (MII port) = 0x8
Table 65. PHY 0 Register 0: Control
Reg.bit Name
Mode Description
Default
0.15
Reset
RW/SC 1: PHY reset. This bit is self-clearing.
0
0.14
Loopback
RW
0
1: Enable loopback. This will loopback TXD to RXD and ignore all
activity on the cable media
(digital loopback)
0: Normal operation
0.13
Speed Select
RW
1
1: 100Mbps
0: 10Mbps
When NWay is enabled, this bit reflects the result of autonegotiation (Read only).
When NWay is disabled, this bit is strap option ‘Force_Speed’ and
can be configured through SMI (Read/Write).
0.12
RW
Auto Negotiation
1: Enable auto-negotiation process
Pin
Enable
0: Disable auto-negotiation process
En_ANEG
This bit can be set through SMI (Read/Write).
strap option
0.11
Power Down
RW
0
1: Power down. All functions will be disabled except SMI function
0: Normal operation
0.10
Isolate
RW
0
1: Electrically isolates the PHY from RMII/SMII. PHY is still able
to respond to MDC/MDIO
0: Normal operation
0.9
RW/SC 1: Restart Auto-Negotiation process
0
Restart Auto
Negotiation
0: Normal operation
0.8
Duplex Mode
RW
1
1: Full duplex operation
0: Half duplex operation
When NWay is enabled, this bit reflects the result of autonegotiation (Read only).
When NWay is disabled, this bit is strap option ‘Force_Duplex’ and
can be configured through SMI (Read/Write).
0.[7:0] Reserved
Reserved
0
Single-Chip 9-Port 10/100Mbps Switch Controller
49
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.2.
PHY 0 Register 1: Status
Table 66. PHY 0 Register 1: Status
Reg.bit
1.15
1.14
Name
100Base_T4
100Base_TX_FD
Mode
RO
RO
1.13
100Base_TX_HD
RO
1.12
10Base_T_FD
RO
1.11
10Base_T_HD
RO
1.[10:7]
1.6
Reserved
MF Preamble
Suppression
RO
RO
1.5
Auto-Negotiate
Complete
RO
1.4
Remote Fault
1.3
1.2
Auto-Negotiation
Ability
Link Status
RO/LL
1.1
Jabber Detect
RO/LH
1.0
Extended
Capability
RO/LH
RO
RO
Single-Chip 9-Port 10/100Mbps Switch Controller
Description
0: No 100Base-T4 capability
1: 100Base-TX full duplex capable
0: Not 100Base-TX full duplex capable
1: 100Base-TX half duplex capable
0: Not 100Base-TX half duplex capable
1: 10Base-TX full duplex capable
0: Not 10Base-TX full duplex capable
1: 10Base-TX half duplex capable
0: Not 10Base-TX half duplex capable
Reserved
The RTL8309G will accept management frames with
preamble suppressed.
The RTL8309G accepts management frames without
preamble. 32 minimum preamble bits are required for the first
SMI read/write transaction after reset. One idle bit is required
between any two management transactions as defined in the
IEEE 802.3u specifications.
1: Auto-negotiation process completed. MII Reg.4, 5 are valid
if this bit is set
0: Auto-negotiation process not completed
1: Remote fault condition detected
0: No remote fault
1: NWay auto-negotiation capable (permanently=1)
Default
0
1
1: Link is established. If the link fails, this bit will be 0 until
after reading this bit again
0: Link has failed
1: Jabber detect enabled
0: Jabber detect disabled
The jabber function is disabled in 100Base-TX operation.
Jabber occurs when a predefined excessively long packet is
detected for 10Base-T. When the duration of TXEN exceeds
the jabber timer (21ms), the transmission and loopback
function are disabled and the COL LED starts blinking. After
TXEN goes low for more than 500 ms, the transmitter will be
re-enabled and the COL LED will stop blinking. Jabber detect
is supported only in 10Base-T operation.
1: Extended register capable (permanently=1)
0
50
1
1
1
0
1
0
0
1
0
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.3.
PHY 0 Register 4: Auto-Negotiation Advertisement
Note: Whenever the link ability of the RTL8309G is reconfigured, the auto-negotiation process should be
executed again to allow the configuration to take effect.
Table 67. PHY 0 Register 4: Auto-Negotiation Advertisement
Reg.bit
4.15
4.14
4.13
4.[12:11]
4.10
Name
Next Page
Acknowledge
Remote Fault
Mode
RO
RO
RW
Reserved
Pause
RO
RW
4.9
4.8
100Base-T4
100Base-TX-FD
RO
RW
4.7
100Base-TX
RW
4.6
10Base-T-FD
RW
4.5
10Base-T
RW
Selector Field
RO
4.[4:0]
Description
Default
0: Next Page disabled (Permanently=0)
0
Permanently=0.
0
1: Advertises that the RTL8309G has detected a remote fault
0
0: No remote fault detected
Reserved
0
1: Advertises that the RTL8309G possesses 802.3x flow control
Pin
capability
En_FCTRL
strap option
0: No flow control capability
Technology not supported (Permanently=0).
0
1: 100Base-TX full duplex capable
1
0: Not 100Base-TX full duplex capable
1: 100Base-TX half duplex capable
1
0: Not 100Base-TX half duplex capable
1: 10Base-TX full duplex capable
1
0: Not 10Base-TX full duplex capable
1: 10Base-TX half duplex capable
1
0: Not 10Base-TX half duplex capable
[00001]=IEEE 802.3.
00001
Single-Chip 9-Port 10/100Mbps Switch Controller
51
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.4.
PHY 0 Register 5: Auto-Negotiation Link Partner Ability
Table 68. PHY 0 Register 5: Auto-Negotiation Link Partner Ability
Reg.bit
5.15
Name
Next Page
5.14
Acknowledge
5.13
Remote Fault
5.[12:11]
5.10
Reserved
Pause
5.9
100Base-T4
5.8
100Base-TX-FD
5.7
100Base-TX
5.6
10Base-T-FD
5.5
10Base-T
5.[4:0]
Selector Field
Mode Description
RO 1: Link partner desires Next Page transfer
0: Link partner does not desire Next Page transfer
RO
1: Link Partner acknowledges reception of Fast Link Pulse (FLP)
words
0: Not acknowledged by Link Partner
RO 1: Remote Fault indicated by Link Partner
0: No remote fault indicated by Link Partner
RO
Reserved
RO 1: Flow control supported by Link Partner
0: Flow control not supported by Link Partner
RO 1: 100Base-T4 supported by Link Partner
0: 100Base-T4 not supported by Link Partner
RO 1: 100Base-TX full duplex supported by Link Partner
0: 100Base-TX full duplex not supported by Link Partner
Note: If auto negotiation is disabled and this bit is set, Reg0.13
and Reg0.8 will be set to 1 after link is established.
RO 1: 100Base-TX half duplex supported by Link Partner
0: 100Base-TX half duplex not supported by Link Partner
Note: If auto negotiation is disabled and this bit is set, Reg0.13
will be set to 1 and Reg0.8 will be set to 0 after link is
established.
RO 1: 10Base-TX full duplex supported by Link Partner
0: 10Base-TX full duplex not supported by Link Partner
Note: If auto negotiation is disabled and this bit is set, Reg0.13
will be set to 0 and Reg0.8 will be set to 1 after link is
established.
RO 1: 10Base-TX half duplex supported by Link Partner
0: 10Base-TX half duplex not supported by Link Partner
Note: If auto negotiation is disabled and this bit is set, Reg0.13
and Reg0.8 will be set to 0 after a link is established.
RO [00001]=IEEE802.3.
Single-Chip 9-Port 10/100Mbps Switch Controller
52
Default
0
0
0
0
0
0
0
0
0
0
00001
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.5.
PHY 0 Register 16: Global Control 0
Table 69. PHY 0 Register 16: Global Control 0
Reg.bit
16.[15:13]
Name
LED Mode
16.12
Software Reset
16.11
Disable VLAN
16.10
Disable 802.1Q
Tag Aware
VLAN
16.9
Disable VLAN
Member Set
Ingress Filtering
16.8
Disable VLAN
Tag Admit
Control
Mode Description
RW 111: Mode 7: Speed, Duplex+Collision, Link+Act, SQI
110: Mode 6: Activity, Speed, Link, SQI
101: Mode 5: Speed, Duplex, Link+Act, Bi-color Link+ActSpeed,
Duplex, Link+Act, SQI
100: Mode 4: Collision, Duplex, Link+Act+Speed, SQI
011: Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100.
010: Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI
001: Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI
000: Mode 0: Duplex+Collision, Bi-color Speed, Bi-color
Link+Act, SQI.
RW/ 1: Soft reset. This bit is self-clearing
SC
If this bit is set to 1, the RTL8309G will reset all registers in it
except PHY registers and will not load configurations from
EEPROM or strapping pins. Software reset is designed to provide a
convenient way for users to change the configuration via SMI. After
changing register values in the RTL8309G (except PHY registers)
via SMI, the external device must execute a soft reset in order to
update the configuration by setting this bit to 1.
RW 1: Disable VLAN
0: Enable VLAN. The default VLAN membership configuration by
internal register is MII port overlapped with all the other ports to
form 8 individual VLANs. This default membership configuration
may be modified by setting internal registers via the SMI interface
or EEPROM.
RW 1: Disable 802.1Q tagged-VID Aware function. The RTL8309G will
not check the tagged VID on received frames to perform taggedVID VLAN mapping. Under this configuration, the RTL8309G only
uses the per port VLAN index register to perform Port-Based VLAN
mapping
0: Enable the Member Set Filtering function of VLAN Ingress Rule.
The RTL8309G checks the tagged VID on received frames with the
VIDA[11:0]~VIDH[11:0] to index to a member set, then performs
VLAN mapping. The RTL8309G uses tagged-VID VLAN mapping
for tagged frames but still uses port-based VLAN mapping for
priority-tagged and untagged frames
RW 1: The switch will not drop a received frame if the ingress port of
this packet is not included in the matched VLAN member set. It will
still forward the packet to the VLAN members specified in the
matched member set. This setting works on both port-based and tagbased VLAN configurations
0: The switch will drop the received frame if the ingress port of this
packet is not included in the matched VLAN member set
RW 1: The switch accepts all frames it receives whether tagged or
untagged
0: The switch will only accept tagged frames and will drop untagged
frames
Single-Chip 9-Port 10/100Mbps Switch Controller
53
Default
111
0
1
0
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
16.7
Name
EEPROM
Existence
16.6
Accept Error
Disable
16.5
IEEE 802.3x
Transmit Flow
Control Enable
16.4
IEEE 802.3x
Receive Flow
Control Enable
16.3
Broadcast Input
or Output Drop
Aging Enable
16.2
16.1
Fast Aging
Enable
16.0
Enable ISP MAC
Address
Translation
8.1.6.
Mode Description
RO 1: EEPROM does not exist (pin EnEEPROM=0 or pin
EnEEPROM=1 but EEPROM does not exist)
0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists)
RW 1: Filter bad packets in normal operation
0: Switch all packets including bad ones. This bit is intended for
debugging purposes only
RW 1: Determines when to invoke flow control based on
auto negotiation results
0: Will not enable transmit flow control no matter what the
auto negotiation result is
RW 1: When the RTL8309G receives a pause control frame, it has the
ability to stop the next transmission of a normal frame until the
timer is expired based on the auto negotiation result
0: Will not receive flow control no matter what the auto negotiation
result is
RW 1: Broadcast input drop is selected
0: Broadcast output drop is selected
RW 1: Enable aging function
0: Disable aging function. The addresses learned in the lookup table
will not be aged out. If the table is full, the last entry in the table will
be deleted to make room for the new entry
RW 1: Enable fast aging function. The entry learned in the lookup table
will be aged out if it is not updated within an 800µs period
0: Disable fast aging function
RW 1: Enable ISP MAC Address Translation function
0: Disable ISP MAC Address Translation function
Default
0
1
1
1
1
1
0
0
PHY 0 Register 17: Global Control 1
Table 70. PHY 0 Register 17: Global Control 1
Reg.bit
17.[15:13]
Name
802.1p Base
Priority
17.12
Trunking Port
Assignment
17.[11:10]
Queue Weight
Mode Description
RW Classifies priority for incoming 802.1Q packets, if 802.1p priority
classification is enabled. ‘User priority’ is compared against this
value.
≥: Classify as high priority
<: Classify as low priority
RW 1: Combine port 0 and 1 as one trunking port, if trunking is
enabled via strapping pin ‘Dis_Trunk’
0: Combine port 6 and 7 as one trunking port, if trunking is
enabled via strapping pin ‘Dis_Trunk’
RW The frame service ratio between the high priority queue and low
priority queue is:
11: 16:1
10: Always high priority queue first
01: 8:1
00: 4:1
Single-Chip 9-Port 10/100Mbps Switch Controller
54
Default
100
1
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
17.9
Name
Disable IP
Priority for IP
Address [A]
17.8
Disable IP
Priority for IP
Address [B]
17.[7:0]
8.1.7.
Reserved
Mode Description
RW 1: Compare both the source and destination IP address of
incoming packets against the value, IP address [A] AND IP mask
[A], to classify packet priority
0: Do not compare the source or destination IP address of
incoming packets against the value ‘IP address [A] AND IP mask
[A]’
RW 1: Compare both the source and destination IP address of
incoming packets against the value, IP address [B] AND IP mask
[B], to classify packet priority
0: Do not compare the source or destination IP address of
incoming packets against the value ‘IP address [B] AND IP mask
[B]’
Reserved
Default
0
0
00000000
PHY 0 Register 18: Global Control 2
Table 71. PHY 0 Register 18: Global Control 2
Reg.bit
18.15
Name
Enable Differential
Service Code Point
[A]
18.14
Reserved
18.[13:8] Differential Service
Code Point [A]
18.7
Enable Differential
Service Code Point
[B]
18.6
18.[5:0]
Reserved
Differential Service
Code Point [B]
Mode Description
RW 1: If differential service priority is enabled, this bit specifies
differential service code point [A] is high priority
0: If differential service priority is enabled, this bit specifies
differential services code point [A] is low priority
Reserved
RW Used to specify the high priority differential service code
point A. For example, if these bits are set to 111111, incoming
packets with a TOS field equal to 111111 will be considered
high priority packets.
RW 1: If differential service priority is enabled, this bit specifies
differential services code point [B] is high priority
0: If differential service priority is enabled, this bit specifies
differential services code point [B] is low priority
Reserved
RW Used to specify a high priority differential service code point B.
For example, if these bits are set to 000000, incoming packets
with a TOS field equal to 000000 will be considered high
priority packets.
Single-Chip 9-Port 10/100Mbps Switch Controller
55
Default
0
1
111111
0
1
111111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.8.
PHY 0 Register 19: Global Control 3
Table 72. PHY 0 Register 19: Global Control 3
Reg.bit
19.15
Name
Enable Drop for 48
Pass 1
19.14
19.13
Reserved
TX IPG
Compensation
19.12
Disable Loop
Detection
Lookup Table
Accessible Enable
Reserved
Reserved
19.11
19.10
19.[9:0]
8.1.9.
Mode Description
RW 1: Enable drop packet after SRAM full for 48 pass 1
0: Disable drop packet after SRAM full for 48 pass 1. This will
result in SRAM run out
Reserved
RW 1: 90ppm TX IPG (InterPacket Gap) compensation
0: 65ppm TX IPG (InterPacket Gap) compensation
RW 1: Disable loop detection function
0: Enable loop detection function
RW 1: Lookup table is accessible via indirect access registers
0: Lookup table is not accessible
Reserved
Reserved
Default
1
1
1
1
0
1
11 1100 0001
PHY 0 Register 22: Port 0 Control 0
Table 73. PHY 0 Register 22: Port 0 Control 0
Reg.bit
22.[15:14]
22.13
Name
Reserved
Local Loopback
22.12
Null VID
Replacement
22.11
Discard Non
PVID Packets
22.10
Disable 802.1p
Priority
22.9
Disable Diffserv
Priority
22.8
Disable PortBased Priority
22.[7:2]
Reserved
Mode Description
RW Reserved.
RW 1: Perform ‘local loopback’, i.e., loop MAC’s RX back
to TX
0: Normal operation
RW 1: The switch will replace a NULL VID with a port VID
(12 bits)
0: No replacement for a NULL VID
RW 1: If the received packets are tagged, the switch will
discard packets with a VID that does not match the
ingress port default VID, which is indexed by port 0’s
‘Port-based VLAN index’
0: No packets will be dropped
RW 1: Disable 802.1p priority classification for ingress
packets on port 0
0: Enable 802.1p priority classification
RW 1: Disable Diffserv priority classification for ingress
packets on port 0
0: Enable Diffserv priority classification
RW 1: Disable port priority function
0: Enable port priority function. Ingress packets from
port 0 will be classified as high priority
RW Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
56
Default
11
0
0
0
Pin Dis_VLAN_Pri
strap option
Default = 1
Pin Dis_DS_Pri
strap option
Default = 1
Pin Sel_Port_Pri
strap option
Default = 1
1111111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
22.[1:0]
8.1.10.
Name
VLAN Tag
Insertion and
Removal
Mode Description
RW 11: Do not insert or remove VLAN tags to/from packets
sent out from this port.
10: The switch will add VLAN tags to packets if they are
not tagged. The switch will not add tags to packets
already tagged. The inserted tag is the ingress port’s
‘Default tag’, which is indexed by port 0’s ‘Port-based
VLAN index’.
01: The switch will remove VLAN tags from packets, if
they are tagged when these packets are send out from
port 0. The switch will not modify packets received
without tags.
00: The switch will remove VLAN tags from packets
then add new tags to them. The inserted tag is the ingress
port’s ‘Default tag’, which is indexed by port 0’s ‘Portbased VLAN index’. This is a replacement processing for
tagged packets and an insertion for untagged packets.
Default
11
PHY 0 Register 23: Port 0 Control 1
Table 74. PHY 0 Register 23: Port 0 Control 1
Reg.bit
23.[15:12]
23.11
23.10
Name
Reserved
Transmission
Enable
Reception Enable
23.9
Learning Enable
23.8
Loop Status
23.[7:4]
Link Quality
23.[3:0]
Reserved
Mode Description
Reserved
RW 1: Enable packet transmission on port 0
0: Disable packet transmission on port 0
RW 1: Enable packet reception on port 0
0: Disable packet reception on port 0
RW 1: Enable switch address learning capability
0: Disable switch address learning capability
RO 1: A loop has been detected on port 0
0: No loop exists on port 0
RO 4-bit field indicating the link quality of the receive twisted-pair or
fiber link.
0000: Highest link quality
1111: Lowest link quality
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
57
Default
1111
1
1
1
0
-
1000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.1.11.
PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]
Table 75. PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]
Reg.bit
24.[15:12]
Name
Port 0 VLAN
Index [3:0]
24.[11~9]
24.[8:0]
Reserved
VLAN ID [A]
Membership Bit
[8:0]
8.1.12.
Mode Description
In a port-based VLAN configuration, this register indexes port 0’s
‘Port VLAN Membership’, which can be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 0 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN A. If a
destination address look up fails, the packet associated with this
VLAN will be broadcast to ports specified in this field. Bit 0 stands
for port 0, bit 1 stands for port 8.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
0000
111
1
0000
0001
PHY 0 Register 25: VLAN Entry [A]
Table 76. PHY 0 Register 25: VLAN Entry [A]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [A]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A.
Single-Chip 9-Port 10/100Mbps Switch Controller
58
Default
1111
0000
0000
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.2. PHY 1 Registers
8.2.1.
PHY 1 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.2.2.
PHY 1 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.2.3.
PHY 1 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.2.4.
PHY 1 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.2.5.
PHY 1 Register 16~17: IP Priority Address [A]
Table 77. PHY 1 Register 16~17: IP Priority Address [A]
Reg.bit
16
Name
IP Address [A]
[31:16]
17
IP Address [A]
[15:0]
8.2.6.
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
RW The switch will both compare the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
Default
0xFFFF
0xFFFF
PHY 1 Register 18~19: IP Priority Address [B]
Table 78. PHY 1 Register 18~19: IP Priority Address [B]
Reg.bit
18
Name
IP Address [B]
[31:16]
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
Single-Chip 9-Port 10/100Mbps Switch Controller
59
Default
0xFFFF
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
19
8.2.7.
Name
IP Address [B]
[15:0]
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
Default
0xFFFF
PHY 1 Register 22: Port 1 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 1. Default value for 22.8 is 1.
8.2.8.
PHY 1 Register 23: Port 1 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
8.2.9.
PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Table 79. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Reg.bit
Name
24.[15~12] Port 1 VLAN
Index [3:0]
24.[11:9]
24.[8:0]
8.2.10.
Reserved
VLAN ID [B]
Membership Bit
[8:0]
Mode Description
RW In a port-based VLAN configuration, this register indexes port
1’s ‘Port VLAN Membership’, which could be defined in one of
the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 1 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN B.
If a destination address look up fails, packets associated with
this VLAN will be forwarded to ports specified in this field.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
0001
111
1
0000
0010
PHY 1 Register 25: VLAN Entry [B]
Table 80. PHY 1 Register 25: VLAN Entry [B]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [B]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN B.
Single-Chip 9-Port 10/100Mbps Switch Controller
60
Default
1111
0000
0000
0001
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.3. PHY 2 Registers
8.3.1.
PHY 2 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.3.2.
PHY 2 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.3.3.
PHY 2 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.3.4.
PHY 2 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.3.5.
PHY 2 Register 16~17: IP Priority Mask [A]
Table 81. PHY 2 Register 16~17: IP Priority Mask [A]
Reg.bit
16
17
8.3.6.
Name
IP Mask [A]
[31:16]
IP Mask [A] [15:0]
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet.
Default
0xFFFF
0xFFFF
PHY 2 Register 18~19: IP Priority Mask [B]
Table 82. PHY 2 Register 18~19: IP Priority Mask [B]
Reg.bit
18
Name
IP Mask [B] [31:16]
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
Single-Chip 9-Port 10/100Mbps Switch Controller
61
Default
0xFFFF
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
19
8.3.7.
Name
IP Mask [B] [15:0]
Mode Description
RW The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
Default
0xFFFF
PHY 2 Register 22: Port 2 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is pin Sel_PortPri strap option for port 2. Default value for 22.8 is 1.
8.3.8.
PHY 2 Register 23: Port 2 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
8.3.9.
PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Table 83. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Reg.bit
24.[15:12]
Name
Port 2 VLAN
Index [3:0]
24.[11~9]
24.[8:0]
Reserved
VLAN ID [C]
Membership Bit
[8:0]
8.3.10.
Mode Description
RW In a port-based VLAN configuration, this register indexes port 2’s
‘Port VLAN Membership’, which can be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 2 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN C. If
a destination address look up fails, packets associated with this
VLAN will be forwarded to ports specified in this field. E.g., 1
0000 0001 means port 8 and 0 are in this VLAN.
Default
0010
111
1
0000
0100
PHY 2 Register 25: VLAN Entry [C]
Table 84. PHY 2 Register 25: VLAN Entry [C]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [C]
Mode
RW
Description
Reserved
Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C.
Single-Chip 9-Port 10/100Mbps Switch Controller
62
Default
1111
0000
0000
0010
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.4. PHY 3 Registers
8.4.1.
PHY 3 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.4.2.
PHY 3 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.4.3.
PHY 3 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.4.4.
PHY 3 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.4.5.
PHY 3 Register 16~18: Switch MAC Address
The Switch MAC address is used as the source address in MAC pause control frames.
Table 85. PHY 3 Register 16~18: Switch MAC Address
Reg.bit
16
17
18
8.4.6.
Name
Switch MAC
Address [47:32]
Switch MAC
Address [31:16]
Switch MAC
Address [15:0]
Mode Description
RW 16.[15:8] = Switch MAC Address Byte 4.
16.[7:0] = Switch MAC Address Byte 5.
RW 17.[15:8] = Switch MAC Address Byte 2.
17.[7:0] = Switch MAC Address Byte 3.
RW 18.[15:8] = Switch MAC Address Byte 0.
18.[7:0] = Switch MAC Address Byte 1.
Default
0x5452
0x834C
0xB009
PHY 3 Register 22: Port 3 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is pin Sel_PortPri strap option for port 3. Default value for 22.8 is 1.
Single-Chip 9-Port 10/100Mbps Switch Controller
63
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.4.7.
PHY 3 Register 23: Port 3 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
8.4.8.
PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]
Table 86. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]
Reg.bit
24.[15:12]
Name
Port 3 VLAN
Index [3:0]
Mode
RW
24.[11~9]
24.[8:0]
Reserved
VLAN ID [D]
Membership
Bit [8:0]
RW
8.4.9.
Description
In a port-based VLAN configuration, this register indexes
port 3’s ‘Port VLAN Membership’, which may be defined in
one of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID
[I] Membership’. Port 3 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
This 9-bit field specifies which ports are members of VLAN D.
If a destination address look up fails, packets associated with
this VLAN will be forwarded to ports specified in this field.
E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
0011
111
1
0000
1000
PHY 3 Register 25: VLAN Entry [D]
Table 87. PHY 3 Register 25: VLAN Entry [D]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [D]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D.
Single-Chip 9-Port 10/100Mbps Switch Controller
64
Default
1111
0000
0000
0011
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.5. PHY 4 Registers
8.5.1.
PHY 4 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.5.2.
PHY 4 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.5.3.
PHY 4 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.5.4.
PHY 4 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.5.5.
PHY 4 Register 16~18: ISP MAC Address
The ISP’s MAC address is used as the source address in MAC address translation functions.
Table 88. PHY 4 Register 16~18: ISP MAC Address
Reg.bit
16
17
18
8.5.6.
Name
ISP MAC Address
[15:0]
ISP MAC Address
[31:16]
ISP MAC Address
[47:32]
Mode Description
RW 16.[15:8] = ISP MAC Address Byte 1.
16.[7:0] = ISP MAC Address Byte 0.
RW 17.[15:8] = ISP MAC Address Byte 3.
17.[7:0] = ISP MAC Address Byte 2.
RW 18.[15:8] = ISP MAC Address Byte 5.
18.[7:0] = ISP MAC Address Byte 4.
Default
0x4205
0x212F
0x5C91
PHY 4 Register 22: Port 4 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 4. Default value for 22.8 is 1.
Single-Chip 9-Port 10/100Mbps Switch Controller
65
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.5.7.
PHY 4 Register 23: Port 4 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
8.5.8.
PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]
Table 89. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]
Reg.bit
24.[15:12]
Name
Port 4 VLAN Index
24.[11~9]
24.[8:0]
Reserved
VLAN ID [E]
Membership Bit
[8:0]
8.5.9.
Mode Description
RW In a port-based VLAN configuration, this register indexes
port 4’s ‘Port VLAN Membership’, which may be defined in
one of the registers ‘VLAN ID [A] Membership’ to ‘VLAN
ID [I] Membership’. Port 4 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of
VLAN E. If a destination address look up fails, packets
associated with this VLAN will be forwarded to ports
specified in this field. E.g., 1 0000 0001 means port 8 and 0
are in this VLAN.
Default
0100
111
1
0001
0000
PHY 4 Register 25: VLAN Entry [E]
Table 90. PHY 4 Register 25: VLAN Entry [E]
Reg.bit
25.[15:12]
Name
Reserved
25.[11:0]
VLAN ID [E]
Mode Description
Reserved
RW
Default
1111
Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E.
Single-Chip 9-Port 10/100Mbps Switch Controller
66
0000
0000
0100
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.6. PHY 5 Registers
8.6.1.
PHY 5 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.6.2.
PHY 5 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.6.3.
PHY 5 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.6.4.
PHY 5 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.6.5.
PHY 5 Register 16: MII Port Control 0
Table 91. PHY 5 Register 16: MII Port Control 0
Reg.bit
16.15
Name
Transmission Enable
16.14
Reception Enable
16.13
Learning Enable
16.12
16.11
Reserved
Disable 802.1p
Priority
16.10
Disable Diffserv
Priority
16.9
Disable Port-Based
Priority
16.8
Reserved
Mode Description
RW 1: Enable packet transmission on MII interface
0: Disable packet transmission on MII interface
RW 1: Enable packet reception on MII interface
0: Disable packet reception on MII interface
RW 1: Enable switch address learning capability
0: Disable switch address learning capability
Reserved
RW 1: Disable 802.1p priority classification for ingress
packets on port 8
0: Enable 802.1p priority classification
RW 1: Disable Diffserv priority classification for ingress
packets on port 8
0: Enable Diffserv priority classification
RW 1: Disable port priority function
0: Enable port priority function. Ingress packets from
port 8 will be classified as high priority
Reserved
Single-Chip 9-Port 10/100Mbps Switch Controller
67
Default
1
1
1
0
Pin Dis_VLAN_Pri
strap option
Default = 1
Pin Dis_DS_Pri
strap option
Default = 1
Pin Sel_Port_Pri
strap option
Default = 1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
16.[7:2]
16.[1:0]
8.6.6.
Name
Reserved
VLAN Tag Insertion
and Removal
Mode Description
Reserved
RW 11: Do not insert or remove VLAN tags to/from
packets sent out from this port.
10: The switch will add VLAN tags to packets if they
are not tagged. The switch will not add tags to packets
already tagged. The inserted tag is the ingress port’s
‘Default tag’, which is indexed by the MII port’s
‘Port-based VLAN index’.
01: The switch will remove VLAN tags from packets,
if they are tagged when these packets are send out
from MII port. The switch will not modify packets
received without tags.
00: The switch will remove VLAN tags from packets
then add new tags to them. The inserted tag is the
ingress port’s ‘Default tag’, which is indexed by MII
port’s ‘Port-based VLAN index’. This is a
replacement processing for tagged packets and an
insertion for untagged packets.
Default
111111
11
PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]
Table 92. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]
Reg.bit
17.15
17.14
17.13
17.[12~9]
17.[8:0]
Name
Null VID
Replacement
Discard NonPVID Packets
Reserved
Port 8 VLAN
Index [3:0]
VLAN ID [I]
Membership Bit
[8:0]
Mode Description
RW 1: The switch will replace a NULL VID with a port VID (12 bits)
0: No replacement for a NULL VID
RW 1: If the received packets are tagged, the switch will discard packets
with a VID that does not match the ingress port default VID, which
is indexed by the MII port’s ‘Port-based VLAN index’
0: No packets will be dropped
Reserved
In port-based VLAN configuration, this register indexs to port 8’s
‘Port VLAN Membership’, which can be defined in register ‘VLAN
ID [A] Membership’ to ‘VLAN ID [I] Membership’. Port 8 can only
communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag
insertion and filtering if the tagged VID is not the same as the PVID.
RW This 9-bit field specifies which ports are members of VLAN I. If a
destination address look up fails, packets associated with this VLAN
will be forwarded to ports specified in this field. E.g., 1 0000 0001
means port 8 and 0 are in this VLAN.
Single-Chip 9-Port 10/100Mbps Switch Controller
68
Default
0
0
1
1000
1
1111
1111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.6.7.
PHY 5 Register 18: VLAN Entry [I]
Table 93. PHY 5 Register 18: VLAN Entry [I]
Reg.bit
18.[15:12]
18.[11:0]
8.6.8.
Name
Reserved
VLAN ID [I]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN I.
Default
1111
0000
0001
0000
PHY 5 Register 19: CPU Port & WAN Port
Table 94. PHY 5 Register 19: CPU Port & WAN Port
Reg.bit
19.[15:8]
19.[7:4]
Name
Reserved
WAN Port
19.[3:0]
CPU Port
8.6.9.
Mode Description
Reserved
RW Specify the WAN Port on the RTL8309G.
1000: MII Port is WAN Port
0111: Port 7 is WAN Port
0110: Port 6 is WAN Port
0101: Port 5 is WAN Port
0100: Port 4 is WAN Port
0011: Port 3 is WAN Port
0010: Port 2 is WAN Port
0001: Port 1 is WAN Port
0000: Port 0 is WAN Port
RW Specify the CPU Port on the RTL8309G.
1000: MII Port is CPU Port
0110: Port 6 is CPU Port
0111: Port 7 is CPU Port
0101: Port 5 is CPU Port
0100: Port 4 is CPU Port
0011: Port 3 is CPU Port
0010: Port 2 is CPU Port
0001: Port 1 is CPU Port
0000: Port 0 is CPU Port
Default
0xFF
0111
0000
PHY 5 Register 22: Port 5 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 5. Default value for 22.8 is 1.
8.6.10.
PHY 5 Register 23: Port 5 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
Single-Chip 9-Port 10/100Mbps Switch Controller
69
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.6.11.
PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]
Table 95. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]
Reg.bit
24.[15:12]
Name
Port 5 VLAN
Index [3:0]
24.[11~9]
24.[8:0]
Reserved
VLAN ID [F]
Membership Bit
[8:0]
8.6.12.
Mode Description
RW In a port-based VLAN configuration, this register indexes port 5’s
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 5 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN F. If a
destination address look up fails, packets associated with this
VLAN will be forwarded to ports specified in this field. E.g., 1
0000 0001 means port 8 and 0 are in this VLAN.
Default
0101
111
1
0010
0000
PHY 5 Register 25: VLAN Entry [F]
Table 96. PHY 5 Register 25: VLAN Entry [F]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [F]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN F.
Single-Chip 9-Port 10/100Mbps Switch Controller
70
Default
1111
0000
0000
0101
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.7. PHY 6 Registers
8.7.1.
PHY 6 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.7.2.
PHY 6 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.7.3.
PHY 6 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.7.4.
PHY 6 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.7.5.
PHY 6 Register 22: Port 6 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 6. Default value for 22.8 is 1.
8.7.6.
PHY 6 Register 23: Port 6 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
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RTL8309G
Datasheet
8.7.7.
PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]
Table 97. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]
Reg.bit
24.[15:12]
Name
Port 6 VLAN
Index [3:0]
24.[11~9]
24.[8:0]
Reserved
VLAN ID [G]
Membership Bit
[8:0]
8.7.8.
Mode Description
RW In a port-based VLAN configuration, this register indexes port 6’s
‘Port VLAN Membership’, which may be defined in one of the
registers ‘VLAN ID [A] Membership’ to ‘VLAN ID [I]
Membership’. Port 6 can only communicate within the membership.
This register also indexes to a default Port VID (PVID) for each
port. The PVID is used in tag insertion and filtering if the tagged
VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN G. If a
destination address look up fails, packets associated with this VLAN
will be forwarded to ports specified in this field. E.g., 1 0000 0001
means port 8 and 0 are in this VLAN.
Default
0110
111
1
0100
0000
PHY 6 Register 25: VLAN Entry [G]
Table 98. PHY 6 Register 25: VLAN Entry [G]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [G]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN G.
Single-Chip 9-Port 10/100Mbps Switch Controller
72
Default
1111
0000
0000
0110
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.8. PHY 7 Registers
8.8.1.
PHY 7 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 49.
8.8.2.
PHY 7 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 50.
8.8.3.
PHY 7 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 51.
8.8.4.
PHY 7 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability,
page 52.
8.8.5.
PHY 7 Register 16: Indirect Access Control
PHY 7 register 16 is used for reading or writing data to the MAC address table.
Table 99. PHY 7 Register 16: Indirect Access Control
Reg.bit Name
16.[15:2] Reserved
Mode Description
Reserved
16.1
Command Execution
RW
16.0
Read or Write Operation
RW
Single-Chip 9-Port 10/100Mbps Switch Controller
1: Trigger a command to read or write the lookup table
0: Indicates this command has completed
1: Read cycle
0: Write cycle
73
Default
1111
1111
1111
11
0
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.8.6.
PHY 7 Register 17~20: Indirect Access Data
Table 100. PHY 7 Register 17~20: Indirect Access Data
Reg.bit
17
Name
Indirect Data [63:48]
18
Indirect Data [47:32]
19
Indirect Data [31:16]
20
Indirect Data [15:0]
8.8.7.
Mode Description
RW Bit 63~48 of Indirect Data.
Indirect Data [54] = If this bit is 1, indicates this entry is static
and will never be aged out. If this bit is 0, indicates this entry is
dynamically learned, aged, updated, and deleted.
Indirect Data [53:52] = 2-bit counter for internal aging.
Indirect Data [51:48] = The source port of this Source MAC
Address is learned.
RW Bit 47~32 of Indirect Data.
Indirect Data [47:40] = Source MAC Address [7:0].
Indirect Data [39:32] = Source MAC Address [15:8].
RW Bit 31~16 of Indirect Data.
Indirect Data [31:24] = Source MAC Address [23:16].
Indirect Data [23:16] = Source MAC Address [31:24].
RW Bit 15~0 of Indirect Data.
Indirect Data [15:8] = Source MAC Address [39:32].
Indirect Data [7:0] = Source MAC Address [47:40].
Bits 1~0 and Bits 15~8 of this register also determine the
address of data in the lookup table.
In a write cycle: Bits 1~0 and Bits 15~8 indirectly map to an
entry in the lookup table. The written data should be filled in
Indirect Data [63:0]
In a read cycle: Bits 1~0 and Bits 15~8 indirectly map to an
entry in the lookup table. The read back data will be shown in
Indirect Data [63:0].
Default
0x00
0x00
0x00
0x00
PHY 7 Register 22: Port 7 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 56.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 7. Default value for 22.8 is 1.
8.8.8.
PHY 7 Register 23: Port 7 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 57.
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Datasheet
8.8.9.
PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Table 101. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Reg.bit
24.[15:12]
Name
Port 7 VLAN Index
[3:0]
24.[11~9]
24.[8:0]
Reserved
VLAN ID [H]
Membership Bit [8:0]
8.8.10.
Mode Description
RW In a port-based VLAN configuration, this register indexes
port 7’s ‘Port VLAN Membership’, which can be defined in
one of the registers ‘VLAN ID [A] Membership’ to ‘VLAN ID
[I] Membership’. Port 7 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
Reserved
RW This 9-bit field specifies which ports are members of VLAN
H. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g., 1 0000 0001 means port 8 and 0 are in this VLAN.
Default
0111
111
1
1000
0000
PHY 7 Register 25: VLAN Entry [H]
Table 102. PHY 7 Register 25: VLAN Entry [H]
Reg.bit
25.[15:12]
25.[11:0]
Name
Reserved
VLAN ID [H]
Mode Description
Reserved
RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN H.
Single-Chip 9-Port 10/100Mbps Switch Controller
75
Default
1111
0000
0000
0111
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
8.9. PHY 8 Registers
8.9.1.
PHY 8 Register 0: Control
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have
no meaning.
Table 103. PHY 8 Register 0: Control
Reg.bit
0.15
0.14
0.13
Name
Reset
Loopback
(digital loopback)
Speed Select
0.12
Auto Negotiation Enable
RW
0.11
0.10
0.9
0.8
Power Down
Isolate
Restart Auto Negotiation
Duplex Mode
RO
RO
RO
RW
0.[7:0]
8.9.2.
Reserved
Mode Description
RO 0: No reset allowed (permanently=0)
RO 0: Normal operation (permanently=0)
RW
-
Default
0
0
1: 100Mbps
0: 10Mbps
When NWay is enabled, this bit reflects the result of
auto-negotiation (Read only).
When NWay is disabled, this bit can be set through
SMI (Read/Write).
1: Enable auto-negotiation process
0: disable auto-negotiation process
This bit can be set through SMI (Read/Write).
0: Normal operation (permanently=0)
0: Normal operation (permanently=0)
0: Normal operation (permanently=0)
1: Full duplex operation
0: Half duplex operation
When NWay is enabled, this bit reflects the result of
auto-negotiation (Read only).
When NWay is disabled, this bit may be set through
SMI (Read/Write).
Reserved
Pin MII_SPD
_STA strap
option
1
0
0
0
Pin MII_DUP
_STA strap
option
0
PHY 8 Register 1: Status
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have
no meaning.
Table 104. PHY 8 Register 1: Status
Reg.bit
1.15
1.14
1.13
Name
100Base_T4
100Base_TX_FD
100Base_TX_HD
Mode
RO
RO
RO
Single-Chip 9-Port 10/100Mbps Switch Controller
Description
0: No 100Base-T4 capability
1: 100Base-TX full duplex capable (permanently=1)
1: 100Base-TX half duplex capable (permanently=1)
76
Default
0
1
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Reg.bit
1.12
1.11
1.[10:7]
1.6
Name
10Base_T_FD
10Base_T_HD
Reserved
MF Preamble Suppression
Mode
RO
RO
RO
RO
1.5
Auto-Negotiate Complete
RO
1.4
1.3
1.2
Remote Fault
Auto-Negotiation Ability
Link Status
RO
RO
RO
1.1
1.0
Jabber Detect
Extended Capability
RO
RO
8.9.3.
Description
1: 10Base-TX full duplex capable (permanently=1)
1: 10Base-TX half duplex capable (permanently=1)
Reserved
The RTL8309G will accept management frames with
preamble suppressed (permanently=1)
1: Auto-negotiation process completed. MII Reg.4, 5
are valid if this bit is set (permanently=1)
0: No remote fault (permanently=0)
1: NWay auto-negotiation capable (permanently=1)
1: Link is established. If the link should fail, this bit
will be 0 until after reading this bit again
0: Link failed
0: No Jabber detected (permanently=0)
1: Extended register capable (permanently=1)
Default
1
1
0
1
1
0
1
Pin MII_LNK
_STA# strap
option
0
1
PHY 8 Register 4: Auto-Negotiation Advertisement
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have
no meaning.
Table 105. PHY 8 Register 4: Auto-Negotiation Advertisement
Reg.bit
4.15
4.14
4.13
Name
Next Page
Acknowledge
Remote Fault
4.[12:11] Reserved
4.10
Pause
4.9
4.8
100Base-T4
100Base-TX-FD
4.7
100Base-TX
4.6
10Base-T-FD
4.5
10Base-T
4.[4:0]
Selector Field
Mode Description
Default
RO 1: Next Page enabled
0
0: Next Page disabled (Permanently=0)
RO Permanently=0
0
RO 1: Advertises that the RTL8309G has detected a remote fault
0
0: No remote fault detected
RO Reserved
0
RW 1: Advertises that the RTL8309G possesses 802.3x flow
Pin MII_FCTRL
control capability
_STA strap option
0: No flow control capability
RO Technology not supported (Permanently=0).
0
RW 1: 100Base-TX full duplex capable
1
0: Not 100Base-TX full duplex capable
RW 1: 100Base-TX half duplex capable
1
0: Not 100Base-TX half duplex capable
RW 1: 10Base-TX full duplex capable
1
0: Not 10Base-TX full duplex capable
RW 1: 10Base-TX half duplex capable
1
0: Not 10Base-TX half duplex capable
RO [00001]=IEEE 802.3.
00001
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8.9.4.
MII Port NWay Mode
Table 106. MII Port NWay Mode
Condition
Upon Reset
After Reset
8.9.5.
Description
Strapping MII_SPD_STA=1 and MII_DUP_STA=1 Æ Reg0.13=1, Reg0.8=1
Strapping MII_SPD_STA=1 and MII_DUP_STA=0 Æ Reg0.13=1, Reg0.8=0
Strapping MII_SPD_STA=0 and MII_DUP_STA=1 Æ Reg0.13=0, Reg0.8=1
Strapping MII_SPD_STA=0 and MII_DUP_STA=0 Æ Reg0.13=0, Reg0.8=0
Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA
Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down Æ Reg1.2=1.
MII_LNK_STA# pulled up Æ Reg1.2=0.
If PHY 8 register 4 is configured as Reg4.8=1, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309G will
reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309G will
reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=0.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=1, Reg4.5=1, the RTL8309G will
reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8309G will
reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0.
If the CPU polls register 5, the RTL8309G replies with the contents in register 4.
If the CPU polls register 4, the RTL8309G replies with the contents in register 4.
MII Port Force Mode
Table 107. MII Port Force Mode
Condition
Upon Reset
After Reset
Description
Strapping MII_SPD_STA=1 and MII_DUP_STA=1 Æ Reg0.13=1, Reg0.8=1
Strapping MII_SPD_STA=1 and MII_DUP_STA=0 Æ Reg0.13=1, Reg0.8=0
Strapping MII_SPD_STA=0 and MII_DUP_STA=1 Æ Reg0.13=0, Reg0.8=1
Strapping MII_SPD_STA=0 and MII_DUP_STA=0 Æ Reg0.13=0, Reg0.8=0
Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA.
Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down Æ Reg1.2=1.
MII_LNK_STA# pulled up Æ Reg1.2=0.
The CPU only writes register 0.13 and 0.8 to configure a link status, then reads register 1.2 to
determine whether the link partner can link with this status.
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Datasheet
9.
Functional Description
9.1. Physical Layer Transceiver Functional Overview
9.1.1.
Auto Negotiation for UTP
The RTL8309G obtains the states of duplex, speed, and flow control ability for each port in UTP mode
through the auto-negotiation mechanism defined in the IEEE 802.3u specifications. During autonegotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8309G advertises full capabilities (100Full, 100Half,
10Full, 10Half) together with flow control ability.
If the link partner to the RTL8309G is forced to bypass auto negotiation, or auto negotiation is not
supported, the link status of the RTL8309G is determined by observing the signal at the receiver.
9.1.2.
100Base-Tx Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also benefits EMI emission.
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Datasheet
9.1.3.
100Base-Tx Receive Function
The 100Base-TX receive mechanism includes an adaptive equalizer, DC restoration, MLT3 to NRZI
conversion, data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding, and
serial to parallel conversion. The process starts with the adaptive equalizer and DC restoration circuits to
compensate for the distortion in the MLT-3 signal. This variable equalizer makes an estimate by
comparing the received signal strength against some known cable characteristic, then tunes itself for
optimization. This on-going process allows the RTL8309G to adjust itself to environmental changes such
as temperature variations. The equalized data then goes through a DC restoration circuit to compensate
for the effects of base line wander in order to improve the dynamic range.
After restoration, the MLT-3 to NRZI, NRZI to NRZ converters then convert the analog signal to a digital
bit-stream. The clock recovery circuit extracts the 125MHz clock from the edges of the NRI signal. A Descrambler, 5B/4B decoder and serial-to-parallel conversion circuits follow. Finally, the converted parallel
data is fed into the MAC.
9.1.4.
10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven into the network media with a
typical 2.3V amplitude. The internal filter shapes the driven signals to reduce EMI emission, eliminating
the need for an external filter. The harmonic contents are at least 27dB below the fundamental when the
RTL8309G drives an all-ones Manchester-encoded signal.
9.1.5.
10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
9.1.6.
Link Monitor
The 10Base-T link pulse detection circuit continually monitors the RXIP/RXIN pins for the presence of
valid link pulses. Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN
signal pairs.
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RTL8309G
Datasheet
9.1.7.
Power-Down Mode
The RTL8309G implements power-down mode on a per-port basis. Setting MII Reg.0.11 forces the
corresponding port of the RTL8309G to enter power-down mode. This disables all transmit/receive
functions, except SMI (Serial Management Interface: MDC/MDIO, also known as MII Management
Interface).
9.1.8.
Auto Crossover Detection
During the link setup phase, the RTL8309G checks whether it receives active signals on every port in
order to determine if a connection can be established. In cases where the receiver data pin pair is
connected to the transmitter data pin pair of the peer device and vice versa, the RTL8309G will
automatically change its configuration to swap receiver data pins with transmitter data pins. In other
words, the RTL8309G adapts automatically to a peer device’s configuration. If a port is connected with a
crossover cable to a NIC with an MDI-X interface, the RTL8309G will reconfigure the port to ensure
proper connection. This effectively replaces the DIP switch commonly used for reconfiguring a port on a
hub or switch.
By pulling-up EN_AUTOXOVER, the RTL8309G identifies the type of connected cable and sets the port
to MDI or MDIX. When switching to MDI mode, the RTL8309G uses TXOP/N as transmit pairs; when
switching to MDIX mode, the RTL8309G uses RXIP/N as transmit pairs. This function is port-based.
Pulling-down EN_AUTOXOVER disables this function and the RTL8309G operates in MDI mode, in
which TXOP/N represents transmit pairs and RXIP/N represents receive pairs.
IEEE 802.3 compliant forced mode 100M ports with auto crossover have link issues with NWay (AutoNegotiation) ports. It is recommended to not use auto crossover for forced 100M.
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Datasheet
9.2. Switch Core Functional Overview
9.2.1.
Address Search, Learning, and Aging
When a packet is received, the RTL8309G uses the least 10 bits of the destination MAC address to index
the 1024-entry look-up table, and at the same time compares the destination MAC address with the
contents of the 16-entry CAM. If the indexed entry is valid or the CAM comparison is matched, the
received packet will be forwarded to the corresponding destination port. Otherwise, the RTL8309G will
broadcast the packet. This is the ‘Address Search’.
The RTL8309G then extracts the least 10 bits of the source MAC address to index the 1024-entry look-up
table. If the entry is not already in the table it will record the source MAC address and add switching
information. If this is an occupied entry, it will update the entry with new information. This is called
‘Learning’. If the indexed location has been occupied by a different MAC address (hash collision), the
new source MAC address will be recorded into the 16-entry CAM. The 16-entry CAM reduces address
hash collisions and improves switching performance.
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the RTL8309G
is around 300 seconds.
9.2.2.
Flow Control
The RTL8309G supports standard IEEE 802.3x full duplex flow control ability on both transmit and
receive sides. If the RTL8309G recognizes that the resources of the destination port of this packet are
being used up, it will issue a ‘pause on’ frame to the source port of this packet with a maximum time as
defined in IEEE 802.3x. Once the resource is available, the RTL8309G sends a ‘pause off’ frame with
zero pause time to turn on transmissions.
On the receive side, when the RTL8309G receives a pause control packet on a port, it stops transmitting
any packets to this port, except flow control packets, for a period of time specified in the received pause
control frame. If it receives another pause control packet in this period of time on the same port, the timer
will be updated with the new value specified in the latest pause control packet. The RTL8309G will restart transmitting packets on this port after the timer has expired.
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Datasheet
9.2.3.
Half Duplex Operation
In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. A
controlled randomization process called ‘truncated binary exponential backoff’ determines the scheduling
of the retransmissions. At the end of enforcing a collision (jamming), the switch delays before attempting
to retransmit the frame. The delay is an integer multiple of slotTime (512 bit times). The number of slot
times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer
‘r’ in the range:
0 ≤ r < 2k
where:
k =min (n, backoffLimit). IEEE 802.3 defines the backoffLimit as 10.
9.2.4.
Backpressure
The RTL8309G provides two methods of preventing packet congestion when resources are about to be
used up. The first is by colliding incoming packets when the packets are going to a congested port. The
second is by sending preambles to defer other station’s transmissions.
Backpressure: When the switch is overloaded it will assert a jam pattern to collide incoming packets until
the congestion condition of the destination port is resolved. The 48 pass 1 mechanism prevents the port
being partitioned by excessive collisions. The RTL8309G will forward one packet successfully after 48
forced collisions. This method carries some risk since the resource may not be available after 48 forced
collisions. If the 48 pass 1 function is turned off, the RTL8309G will always collide incoming packets
with a jam pattern.
By deferring, the RTL8309G sends preambles to defer other stations’ transmissions. To avoid jabber and
excessive deference as defined in IEEE 803.3, the RTL8309G will pull down the carrier sense signal for a
short time and then raise it up it quickly. This short silence time is to prevent other stations seizing the
medium and sending packets out. If there are packets to send out during the carrier sense rising up period,
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Datasheet
carrier sense flow control will be replaced by those packets. After the packets are sent, carrier sense rises
up again, repeating the pattern until the system is available.
9.2.5.
UTP Port Status Configuration
The RTL8309G supports flexible status configuration via strapping pins for each PHY, En_ANEG,
En_FCTRL, Force_Duplex, and Force_Speed, on a group basis. These pins are used to assign the initial
values to PHY register 0 and 4 upon reset. The configuration parameters set by these four strapping pins
globally control the abilities of each port. For advanced applications requiring configuration on a per-port
basis, a serial EEPROM should be attached.
If auto negotiation is enabled by strapping pin ‘En_ANEG’, the link status is determined by the result of
the auto negotiation process. The default configuration of the RTL8309G is all abilities enabled (the
content of the PHY registers will be Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and
Reg4.10=1). If auto negotiation is disabled by EN_ANEG, the link speed and duplex mode is forced by
strapping pins, Force_Duplex and Force_Speed. These two pins have no effect if auto negotiation is
enabled.
9.2.6.
MII Port (The 9th Port)
The RTL8309G is an 8-port Fast Ethernet switch with one extra MII port for specific applications. It
integrates embedded SRAM for packet storage, nine MAC, and eight physical layer transceivers for
10Base-T and 100Base-TX, into a single chip.
9.2.6.1
MII Port Operating Mode
The MII port only provides a MAC part to support the MII interface for connection with an external
MAC or PHY. Two strapping pins, MII_MODE[1:0], are used to configure this interface to act as MII
PHY mode, SNI PHY mode, or MII MAC mode to work with the external MAC of a routing engine,
PHY of a HomePNA, or other physical layer transceivers.
If the MII port connects with an external MAC, such as the processor of a router application, it will act as
a PHY. This is PHY mode MII, or PHY mode SNI. In PHY mode MII or PHY mode SNI, the MII port
uses the MAC part only, and provides an external MAC interface to connect MACs of external devices.
In order to connect both MACs, the MII of the switch MAC should be reversed into PHY mode.
If the MII port connects with an external PHY, such as the PHY of a HomePNA application, it will act as
a MAC. This is MAC mode MII. In MAC mode MII, the MII port uses its MAC to connect to an external
PHY and ignores the internal PHY part.
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The following figures illustrate various utilizations of the ninth port by setting strapping pins. They
consist of the following general system applications:
General standalone 8-port switch applications.
HomePNA applications.
Router applications.
Other PHY applications.
Router Application
HomePNA or Other PHY Application
RTL8309G
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 0
RX+-[1]
TX+-[1]
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 1
RX+-[7]
TX+-[7]
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 7
Mode
Select
PHY
Mode
10/100
MAC 8
8 LAN
Ports
RX+-[0]
TX+-[0]
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 0
RX+-[1]
TX+-[1]
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 1
RX+-[7]
TX+-[7]
10Base-T or
100Base-TX
PHYceiver
10/100
MAC 7
Mode
Select
MAC
Mode
Interface
ADSL or Cable
Modem
(MII Interface PHY)
MAC
Mode
Interface
13
13
/
MAC
13
/
MAC
1 WAN
Interface
Router
/
1 WAN
Interface
10/100
MAC 8
PHY
Mode
Sw itch Fabric, V LAN, QoS, Trunking
RX+-[0]
TX+-[0]
Sw itch Fabric, V LA N , QoS, Trunking
8 LAN
Ports
RTL8309G
HomePNA or
Other PHYs
Figure 3. MII Port Application
9.2.6.2
MII Interface
In order to act as a PHY when the MII port is in PHY mode, some pins of the external MAC interface
must be changed. For example, TXC are input pins for MAC but output pins for PHY; so the pin
MTXC/PRXC is input for MAC mode and output for PHY mode. Refer to Figure 4, on page 86 to check
the relationship between the RTL8309G and the external device.
Note: Connect the input of the RTL8309G to the output of the external device. The RTL8309G has no
RXER, TXER, and CRS pins for MII signaling. As the RTL8309G does not support pin CRS, it is
necessary to connect the MTXEN/PRXDV (output) of PHY mode to both CRS and RXDV (input) of the
external device.
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9.2.6.3
MII Port Status Pins
Four signaling pins (MII_LNK_STA#, MII_SPD_STA, MII_DUP_STA, MII_FCTRL_STA) are used to
provide operating status to the MII port MAC in real time after reset. This means the external MAC or
PHY must be forced to the same port status as the MII port. The MII port automatically detects the link
status both from the TXC of the external PHY and MII_LNK_STA#.
Note 1: Pulled high or floating sets the speed to 100Mbps. Pulled down sets the speed to 10Mbps.
Note 2: Pulled high or floating enables full duplex. Pulled down sets half duplex.
Note 3: Pulled high or floating enables flow control or backpressure. Pulled down disables flow control
or backpressure.
Figure 4. MII Port Operating Mode Overview
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9.2.6.4
MII PHY Mode/SNI PHY Mode
In routing applications, the RTL8309G cooperates with a routing engine to communicate with the WAN
(Wide Area Network) through MII/SNI.
In MII PHY mode, pulling MII_SPD_STA up results in the MII port operating at 100Mbps with MTXC,
and MRXC running at 25MHz. Pulling MII_SPD_STA down results in the MII port operating at 10Mbps
with MTXC, and MRXC running at 2.5MHz.
In SNI PHY mode, MII_SPD_STA has no effect and should be pulled down. SNI mode operates at
10Mbps only, with MTXC and MRXC running at 10MHz. In SNI mode, the RTL8309G does not loop
back a RXDV signal as a response to TXEN and does not support the heartbeat function (asserting COL
signal for each complete TXEN signal). This interface is a bit-wide data interface used with some
controllers to function as a network layer protocol in half duplex operation.
9.2.6.5
MII MAC Mode
In HomePNA or other PHY applications, the RTL8309G provides an MII interface to the underlying
HomePNA or other physical devices so as to communicate with other types of LAN media. In such
applications, MII_MODE[1:0] should be pulled high or be floated upon reset.
In HomePNA applications, MII_DUP_STA must be pulled down since HomePNA is half-duplex only.
The link speed of the RTL8309G is determined by RXC and TXC from the PHY of the HomePNA
(running at 1Mbps). Thus, the MII_SPD_STA has no effect and should be pulled down for compatibility
with HomePNA’s PHY. The link state of HomePNA is unstable (a characteristic of the HomePNA 1.0
standard) such that MII_LNK_STA# must be pulled down instead of being wired to the LINK LED pin
of the HomePNA.
Because the HomePNA PHY physical layer is half duplex and can only detect a collision event during the
AID header interval (the time when transmitting the Ethernet preamble), the backpressure flow control
algorithm is not suitable for a HomePNA network and MII_FCTRL_STA should be pulled down.
For other PHY applications, the strap status set by MII_SPD_STA, MII_DUP_STA, and
MII_FCTRL_STA depends on the particular application.
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9.2.6.6
MII Port PHY Register
The external MAC automatically polls and accesses the internal PHY registers in the RTL8309G when
the MII port is operated in MII PHY mode with auto negotiation enabled. For the auto negotiation process
in the CPU to function properly, the RTL8309G provides PHY register 0, 1, and 4, to virtually provide
the MII port’s PHY status to the external MAC. Because the MII port of the RTL8309G does not have a
true PHY in it, it does not process the auto negotiation. The contents of PHY registers 4 and 5 should be
the same for both terminals of the MII bus when operating on the same link status. Thus, the RTL8309G
does not provide PHY register 5; it only emulates it. If the CPU polls PHY register 5, the RTL8309G
returns the contents of PHY register 4 since it cannot execute the auto negotiation process. If the CPU
polls PHY register 4, the RTL8309G returns the contents of PHY register 4.
9.3. Advanced Functionality Overview
9.3.1.
Port-Based VLAN
If the VLAN function is enabled by pulling down the Dis_VLAN strapping pin, the default VLAN
membership configuration by internal register is the MII port overlapped with all the other ports to form
nine individual VLANs. Via an attached serial EEPROM or via SMI, the default configuration may be
modified to allow the input ports to join any of the nine VLAN groups: VLAN A, B, C, D, E, F, G, H,
and I. Each input port can be a member of more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each incoming frame is assigned to a
VLAN based on the input port into which it arrived at the switch. It is not necessary to parse and inspect
frames in real-time to determine their VLAN mapping. All frames received on a given input port will be
forwarded to members of that port’s VLAN group. The RTL8309G supports nine VLAN indexes to
individually index received packets to one of the nine VLAN membership registers. These nine groups of
VLAN membership registers, VLAN ID [A] membership bit [8:0] ~ VLAN ID [I] membership bit [8:0],
determine which ports are members of this VLAN. The RTL8309G forwards frames to members of this
VLAN only (excluding the input port of this frame). VLAN membership registers descript which port are
members in a VLAN member set. A port that is not specified in this port’s member set should generally
not be receiving and/or transmitting frames for that VLAN.
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Figure 5 illustrates a typical application. VLAN indexes and VLAN member definitions are set to form
three different VLAN groups.
VL A N 1
Port 0 VLAN index=0000
P0
Port 1 VLAN index=0000
P1
Port 2 VLAN index=0000
P2
VLAN 2
P3
000000111
MemberB
000111000
MemberC
011000000
MemberD
111000000
MemberE
110000000
MemberF
000000000
MemberG
000000000
MemberH
000000000
MemberI
000000000
Port 3 VLAN index=0001
P4
Port 4 VLAN index=0001
P5
Port 5 VLAN index=0001
P6
MemberA
Port 6 VLAN index=0010
P7
Port 7 VLAN index=0011
VLAN 3
P8
Port 8 VLAN index=0100
RTL8309G
VLAN 4
Figure 5. VLAN Grouping Example
In cases where VLAN and trunking are both enabled at the same time, a situation may occur where a
packet is forwarded to a trunk but one of the members of this trunk is not in the same VLAN group
associated with the source port. In this situation, the VLAN function has higher priority than the trunking
operation. The packet will not be forwarded to the port of this trunk.
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For non-VLAN tagged frames, the RTL8309G performs port-based VLAN. It will use Port n VLAN
index [3:0] to index to a VLAN membership. The VLAN ID associated with this indexed VLAN
membership is the Port VID (PVID) of this port.
9.3.2.
IEEE 802.1Q Tagged VID-based VLAN
IEEE 802.1Q tagged-VID based VLAN mapping uses a 12-bit explicit identifier in the VLAN tag to
associate received packets with a VLAN. Nine groups of VLAN membership registers, VLAN ID [A]
membership [8:0] ~ VLAN ID [I] membership [8:0], consist of ports that are in the same VLAN
corresponding to the registers defined in VLAN ID [A] [11:0] ~ VLAN ID [I] [11:0]. If the VID of a
VLAN-tagged frame does not hit the VLAN ID [A] [11:0] ~ VLAN ID [I] [11:0], then the RTL8309G
will drop the VLAN-tagged frame. Otherwise, the RTL8309G compares the explicit identifier in the
VLAN tag with the nine VLAN registers to determine the VLAN association of this frame, then forwards
it to the member set of this VLAN. Two VIDs are reserved for special purposes. One of them is all ones
and is currently unused. The other is all zeros and indicates a priority tag, which is treated as an untagged
frame.
When 802.1Q tag aware VLAN is enabled, the RTL8309G performs 802.1Q tag-based VLAN mapping
for tagged frames, but performs port-based VLAN mapping for untagged frames. If 802.1Q tag-aware
VLAN is disabled, the RTL8309G performs only port-based VLAN mapping both for non-tagged and
tagged frames. Figure 6 illustrates the processing flow when 802.1Q tag aware VLAN is disabled.
------
Un-tagged
Tagged
------
Length/Type
SA
DA
Length/Type 802.1Q Tag
SA
DA
P0
P0VLANIndex=0000
P1
P2
P3
Search
VID table
P4
P5
P6
VIDA=12'h001
MemberA 1 0 0 0 0 0 0 0 1
VIDB=12'h0ff
MemberB 1 0 0 0 0 0 0 1 0
VIDC=12'h1ff
MemberC 1 0 0 0 0 0 1 0 0
VIDD=12'h2ff
MemberD 1 0 0 0 0 1 0 0 0
VIDE=12'h3ff
MemberE 1 0 0 0 1 0 0 0 0
VIDF=12'h4ff
MemberF 1 0 0 1 0 0 0 0 0
VIDG=12'h5ff
MemberG 1 0 1 0 0 0 0 0 0
VIDH=12'h6ff
MemberH 1 1 0 0 0 0 0 0 0
VIDI=12'h7ff
MemberI 1 1 1 1 1 1 1 1 1
P7
------
Length/Type
SA
DA
Length/Type 802.1Q Tag
SA
DA
RTL8309G
P8
------
Figure 6. Tagged and Untagged Packet Forwarding When 802.1Q Tag Aware VLAN is Disabled
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Two VLAN ingress filtering functions are supported by the RTL8309G in registers. One is the ‘admit
VLAN tagged frame’ function, which provides the ability to receive VLAN-tagged frames only.
Untagged or priority tagged (VID=0) frames will be dropped. The other is the ‘ingress member set
filtering’, which will drop frames if the receive port is not in the member set.
There are also two optional egress filtering functions supported by the RTL8309G through strapping. One
is ‘Leaky VLAN’, which enables inter-VLAN unicast packet forwarding. That is, if the layer 2 look-up
table search has a hit, then the unicast packet will be forwarded to the egress port, ignoring the egress rule.
The other is ‘ARP VLAN’, which broadcasts ARP packets to all other ports, ignoring the egress rule.
9.3.3.
QoS Operation
The RTL8309G can recognize the QoS priority information of incoming packets to give a different egress
service priority. The RTL8309G identifies the packets as high priority based on several types of QoS
priority information:
Port-based priority
802.1p/Q VLAN priority tag
TCP/IP's TOS/DiffServ (DS) priority field
IP Address
There are two priority queues; a high-priority queue and a low-priority queue. The queue service rate is
based on the Weighted Round Robin algorithm. The packet-based service weight ratio of the high-priority
queue and low-priority queue can be set to 4:1, 8:1, 16:1 or ‘Always high priority first’ by hardware pins
upon reset, or internal register via SMI after reset.
9.3.3.1
Port-Based Priority
When port-based priority is applied, packets received from the high-priority port are sent to the highpriority queue of the destination port. High priority ports can be partially set by hardware pins, and
wholly configured in internal registers.
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9.3.3.2
802.1p-Based Priority
When 802.1p VLAN tag priority applies, the RTL8309G recognizes the 802.1Q VLAN tag frames and
extracts the 3-bit User Priority information from the VLAN tag. The RTL8309G sets the threshold of
User Priority as 3. Therefore, VLAN tagged frames with User Priority value = 4~7 will be treated as high
priority frames, other User Priority values (0~3) as low priority frames (follows 802.1p standard). The
threshold value can be modified in internal registers via an SMI interface or configured in EEPROM.
9.3.3.3
DiffServ-Based Priority
When TCP/IP’s TOS/DiffServ(DS) based priority is applied, the RTL8309G recognizes TCP/IP
Differential Services Code Point (DSCP) priority information from the DS-field defined in RFC2474. The
DS field byte for the IPv4 is a Type-of-Service (TOS) octet. The recommended DiffServ Code Point is
defined in RFC2597 to classify the traffic into different service classes. The RTL8309G extracts the
codepoint value of DS-fields from IPv4 packets and identifies the priority of the incoming IP packet
following the definition below:
High priority: where the DS-field = (EF, Expected Forwarding:) 101110
(AF, Assured Forwarding:) 001010; 010010; 011010; 100010
(Network Control:) 110000 and 111000
Differential service code point [A] specified in internal register;
Differential service code point [B] specified in internal register;
Low priority: where the DS-field = other values.
The VLAN tagged frame and 6-bit DS-field in the IPv4 frame format are shown below:
Table 108. 802.1Q VLAN Tag Frame Format
6 bytes
DA
6 bytes
SA
2 bytes
81-00
3 bits
User-Priority (0~3:Low-pri; 4~7: High-pri)
---
Table 109. IPv4 Frame Format
6 bytes
DA
6 bytes
SA
4 bytes
802.1Q Tag (optional)
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08-00
4 bits
Version IPv4= 0100
92
4 bits
IHL
6 bits
TOS[0:5] = DS-field
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9.3.3.4
IP-Based Priority
When IP-based based priority is applied, any incoming packets with IP priority equal to IP address [A]
AND IP mask [A] or IP address [B] AND IP mask [B] will be treated as high priority packets. IP priority
[A] and IP priority [B] may be enabled or disabled independently.
9.3.3.5
Flow Control Auto Turn Off
The RTL8309G can be configured to turn off 802.3x flow control and backpressure flow control for 1~2
seconds whenever the port receives VLAN-tagged or TOS/DS high priority frames. Flow control is reenabled when no priority frame is received for a 1~2 second duration. The purpose of this function is to
avoid head-of-line blocking on priority classification.
9.3.4.
Insert/Remove VLAN Priority Tag
The RTL8309G supports four types of insertion/removal of VLAN tags in packet, controlled by internal
registers on a per-port basis. They are classified as follows:
Type 11
Do not change packets (Default).
Type 10
Insert input port’s PVID for non-tagged packets. Do not change packets if they are already tagged.
Type 01
Remove VLAN tags from tagged packets. Do not change packets if they are not tagged.
Type 00
Remove VLAN tags from tagged packets then insert the input port’s PVID. For non-tagged packets,
insert the input port’s PVID.
In Type 10, if Null VID replacement is enabled, this function has higher priority than type 10. If both type
10 is selected and Null VID replacement is enabled, the RTL8309G inserts a PVID to non-tagged packets
and replaces a null VID with a PVID for tagged packets, and does nothing in tagged packets with a nonnull VID.
If the tag removed frame is less than 64 bytes, it will be padded with an 0x20 pattern before the packet’s
CRC field to fit the 64-byte minimum packet length of the IEEE 802.3 spec. The RTL8309G will
recalculate the FCS (Frame Check Sequence) if the frame has been changed.
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9.3.5.
Port VID (PVID)
In a router application, the router may want to know which input port this packet came from. The
RTL8309G supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on an egress
packet. The VID information carried in the VLAN tag will be changed to a PVID. The RTL8309G also
provides an option to admit VLAN-tagged packets with a specific PVID only. When this function is
enabled, packets with an incorrect PVID and non-tagged packets will be dropped.
The RTL8309G uses an internal register, ‘Port n VLAN index [3:0]’ to index to a VLAN membership.
The VLAN ID associated with this indexed VLAN membership is the PVID for this port. Users may
select VLAN insert/remove type 10 or 00 to insert a PVID on egress packets.
On 802.1Q tag-based VLANs, do not use a port-based VLAN in PVID applications, as the VID
information carried in the VLAN tag will be replaced with a PVID.
9.3.6.
Port Trunking
The RTL8309G can combine two UTP ports into one trunking port (with a balancing mechanism). The
default configuration is to combine port 0 and 1 as one trunk, even if they are operating with different
duplex or speed settings. If port 0 and/or port 1 are assigned as a high priority port, this trunk will also be
considered as a high priority trunk when the trunking function is enabled. The RTL8309G also provides
the option to set port 6 and port 7 as a trunk by configuring the ‘trunking port assignment’ bit in the
internal register.
9.3.7.
ISP MAC Address Translation
Some Internet Service Providers only provide service to a single pre-registered MAC address. To share
the Internet Service with more than one station, the RTL8309G translates the MAC address of multiple
NICs to the ISP registered MAC address.
Figure 7, page 95, illustrates an outbound process. When station G tries to send a packet to the WAN, it
broadcasts or unicasts this packet to the CPU port with a NIC MAC address. After the CPU receives this
packet, it translates this MAC address to the ISP registered MAC address and stores this information in its
mapping table. It then forwards this packet to the WAN port through the CPU port. The RTL8309G will
not learn this packet into it’s forwarding table. This is a special learning mechanism, which states that any
frame coming from the CPU port with a source MAC address equal to internal register ‘ISP MAC [47:0]’
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will not be learned. This function must be correctly configured in the VLAN configuration, otherwise the
RTL8309G will drop such packets.
Figure 7. ISP MAC Outbound Process
In the inbound process, when the RTL8309G receives a packet from the WAN port, it will be directly
forwarded to the CPU port according to the VLAN 1 configuration. The CPU looks up the mapping table
to reverse translate the destination MAC address from the ISP MAC to the MAC address of the station G
NIC. Figure 8 illustrates this inbound process.
Figure 8. ISP MAC Inbound Process
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9.3.8.
Lookup Table Access
The RTL8309G supports registers for the CPU to read/write to an internal 1024-entry lookup table via the
SMI interface. Before reading/writing from/to the internal forwarding table, the contents of internal
register ‘Indirect Access Control [15:0]’ should be filled correctly.
In a write cycle, the user must assign the write data in register ‘Indirect Access Data [63:0]’ first. Bits 1~0
along with bits 15~8 form a 10-bit field that indirectly maps to an entry in the lookup table. To execute a
write access, bit 0 in the ‘Indirect Access Control’ register should be set to 0, and bit 1 should be set to 1.
The CPU will poll bit 1 in ‘Indirect Access Control’ to determine whether the write access is complete or
not.
The 10-bit field composed of bits 1~0 and bits 15~8 in PHY7 Reg.20 indirectly maps to an entry in the
lookup table for reading. The read back data is shown in PHY7 Reg.17~20. To execute read access, bit 0
in the ‘Indirect Access Control’ register should be set to 1, and bit 1 should be set to 1 to trigger this
command. The CPU will poll bit 1 in ‘Indirect Access Control’ to determine whether read access is
complete or not.
9.3.9.
Serial Management Interface (SMI)
SMI is also known as the MII Management Interface. It consists of two signals (MDIO and MDC) that
allow an external device in SMI master mode (MDC is output) to control the state of PHY, and in SMI
slave mode (MDC is input) to control the internal register. MDC is an input clock for the RTL8309G to
latch MDIO on its rising edge. The clock can run from 0MHz to 25MHz. MDIO is a bi-directional signal
that is used to write data to, or read data from, the RTL8309G. Table 110 shows the read and write cycle
format of the RTL8309G.
Table 110. SMI Read/Write Cycles
Preamble
Start
OP Code
PHYAD
REGAD
Turn Around
Data
(32 bits)
(2 bits)
(2 bits)
(5 bits)
(5 bits)
(2 bits)
(16 bits)
1……..1
01
10
A4A3A2A1A0
R4R3R2R1R0
Z0
D15…….D0
Read
1……..1
01
01
A4A3A2A1A0
R4R3R2R1R0
10
D15…….D0
Write
Note: high-impedance. During idle time, an external 1.5KΩ pull-up resistor determines MDIO state.
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The RTL8309G supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles
without preamble bits. The RTL8309G can accept MDIO commands after a 1 bit preamble. However, for
the first cycle of MII management after power-on reset, a 32-bit preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, an external device should delay at
least 1 second before issuing the first SMI Read/Write Cycle relative to the rising edge of reset. The
output voltage level of the RTL8309G is configurable by supplying different voltages to pin VDDIO.
VDDIO can be supplied with either 2.5V or 3.3V power.
9.3.10.
Broadcast Storm Control
After 64 consecutive broadcast packets (DID=FFFF-FFFF-FFFF) have been received by a particular port,
any following incoming broadcast packets will be discarded by this port for approximately 800ms. Any
non-broadcast packet can reset the time window and broadcast counter such that the scheme restarts.
Note: Trigger condition is consecutive 64 DID = FFFF-FFFF-FFFF packets. Release condition: receive
non-broadcast packet on or after 800ms.
9.3.11.
Broadcast In/Out Drop
If some destination ports are blocking and the buffer is full, broadcast frames are dropped according to
the internal configuration. There are two options:
Broadcast Input Drop
Forwards any broadcast packet to any output port and will drop packets at the source port directly.
Although this function effectively reduces the loading on the RTL8309G, packets broadcast to noncongested ports will also be dropped.
Broadcast Output Drop
Only forwards broadcast packets to non-congested ports. But if a dropped packet is re-transmitted by a
higher protocol in the congested port, the non-congested port will receive duplicate packets. Figure 9,
page 98 illustrates this concept.
1. Input Drop: Drop the frame directly. Do not forward to any port
2. Output Drop: Forward only to non-blocking ports (broadcast becomes multicast)
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1. Broadcast packet from Port 0
2. Buffer of Port 7 is full, others are not full
Output Drop:
Input Drop:
Port 0
1
2
3
4
5
6
Port 0
7
1
2
3
4
5
6
7
Full
Full
Rx:
Rx:
Figure 9. Input Drop vs. Output Drop
9.3.12.
EEPROM Configuration Interface
The EEPROM interface is a 2-wire serial EEPROM interface providing 2Kbits of storage space. The
external device connected to the RTL8309G should be 2.5V or 3.3V depending on the VDDIO setting.
9.3.13.
24LC02 Device Operation
Clock and Data transitions: The SDA pin is normally pulled high with an external resistor. Data on the
SDA pin may change only during SCL low periods. Data changes during SCL high periods will indicate a
start or stop condition as defined below.
Start Condition
A high-to-low transition of SDA with SCL high is the start condition and must precede any other
command.
Stop Condition
A low-to-high transition of SDA with SCL high is a stop condition.
Acknowledge
All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The 24LC02
sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Random Read
A random read requires a ‘dummy’ byte write sequence to load in the data word address.
Sequential Read
For the RTL8309G, the sequential reads are initiated by a random address read. After the 24LC02
receives a data word, it responds with an acknowledgement. As long as the 24LC02 receives an
acknowledgement, it will continue to increment the data word address and clock out sequential data
words in series.
SDA
SCL
Start
Stop
Figure 10. Start and Stop Definition
Figure 11. Output Acknowledge
Single-Chip 9-Port 10/100Mbps Switch Controller
99
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Read
ACK
Stop
ACK
Device
Address
SDA
Data n
R/W
Data n+1
ACK
ACK
Data n+x
ACK
NO ACK
Figure 12. Sequential Read
9.3.14.
Head-of-Line Blocking
The RTL8309G incorporates an advanced mechanism to prevent Head-Of-Line blocking problems when
flow control is disabled. When the flow control function is disabled, the RTL8309G first checks the
destination address of the incoming packet. If the destination port is congested, the RTL8309G will
discard this packet to avoid blocking the next packet, which is going to a non-congested port.
9.3.15.
MII Port Diagnostic Loopback
The RTL8309G provides a MAC loopback function on the MII port to detect cable problems or far end
existence. When this function is enabled, the RTL8309G will forward local and broadcast packets from
the input of the MII port to the output of the MII port, and drop unicast packets from the input of the MII
port. The other port can still forward broadcast or unicast packets to the MII port. This is especially useful
for router application mass production tests.
Figure 13. MII Port Loopback
Single-Chip 9-Port 10/100Mbps Switch Controller
100
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
9.3.16.
Loop Detection
Loops should be avoided between switch applications. The simplest loop as shown below results in: 1)
Unicast frame duplication; 2) Broadcast frame multiplication; 3) Address table non-convergence. Frames
may be transmitted from Switch1 to Switch2 via Link1, then returned to Switch1 via Link2.
Switch 1
Link1
Link2
Switch 2
Figure 14. Loop Example
When the loop detection function is enabled, the RTL8309G periodically sends out a broadcast packet
every 3~5 minutes and automatically detects whether there is a network loop (or bridge loop). If a loop is
detected the LoopLED# will be ON (active low or high). The LED goes out when the network loop no
longer exists. The Loop frame length is 64 bytes and its format is shown below.
Table 111. Loop Frame Format
FFFF FFFF FFFF
SID
8899
0300 000…0000
CRC
In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If
the EEPROM is not used, a unique SID should be assigned via SMI after reset, and the default SID (0x52
54 4c83 09 b0) should not be used.
9.3.17.
LEDs (Light Emitting Diodes)
The RTL8309G supports four parallel LEDs for each port, and one special LED (LOOPLED#). Each port
has four LED indicator pins. Each pin may have different indicator meanings set by pins
LED_MODE[2:0]. Refer to the pin descriptions for details (see
Port LED Pins, on page 13). Upon reset, the RTL8309G supports chip diagnostics and LED functions by
blinking all LEDs once for 320ms. This function can be disabled by asserting EN_RST_BLNK to 0.
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
LED_BLNK_TIME determines the LED blinking period for activity and collision (1 = 43ms and 0 =
120ms).
All LED pins are dual function pins: input operation for configuration upon reset, and output operation
for LED after reset. If the pin input is floating upon reset, the pin output is active low after reset.
Otherwise, if the pin input is pulled down upon reset, the pin output is active high after reset. Below is an
example circuit for LEDs. The typical value for pull-down resistors is 10KΩ.
Floating
Pull-down
1.8V
LED Pin
RTL8309G
10K
ohm
RTL8309G
LED Pin
Figure 15. Floating and Pull-Down of LED Pins
For two-pin Bi-color LED mode, Bi-color Link/Act and Speed can be used for one Bi-color LED package,
which is a single LED package with two LEDs connected in parallel with opposite polarity. As all LED
pins are dual function pins, strapping LED pins to high or low will affect their active status. In Bi-color
LED mode, the Link/Act and Speed LED pins may both be strapped to high or low but their active status
will be opposed.
Note: For Bi-color LEDs, the 1.8V supply voltage may not be sufficient to turn the LED on. The
application schematic in Figure 18, on page 104, illustrates how to directly utilize 7.5 ~ 12V from the DC
adapter as the power source for Bi-color LEDs.
Table 112. Speed and Bi-Color Link/Act Truth Table
Indication
No Link
100M Link
10M Link
100M Act
10M Act
Bi-Color State
Both Off
Green On
Yellow On
Green Flash
Yellow Flash
Speed:Input=Floating, Active Low.
Bi-Color Link/Act: the active status of
LED_ADD is the opposite of LED_SPD
and does not interact with input upon
reset.
Speed
Link/Act
1
1
0
1
1
0
0
Flash
1
Flash
Single-Chip 9-Port 10/100Mbps Switch Controller
102
Speed:Input=Pull-down, Active High.
Bi-Color Link/Act: the active status of
LED_ADD is the opposite of LED_SPD
and does not interact with input upon
reset.
Speed
Link/Act
0
0
1
0
0
1
1
Flash
0
Flash
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Y ellow
Speed
LED
Link/A ct
LED
G reen
Figure 16. Two-Pin Bi-Color LED for SPD Floating or Pull-high
Y ellow
Speed
LED
Link/A ct
LED
G reen
Figure 17. Two-Pin Bi-Color LED for SPD Pull-down
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
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Datasheet
Strapping High
Strapping Low
7.5 ~12V
0.5K
7.5 ~12V
0.5K
0.5K
Bi-color LED
Speed
LED
BJT
BJT
0.5K
Bi-color LED
Link/Act
LED
Speed
LED
BJT
BJT
Link/Act
LED
50
Figure 18. Bi-Color LED Reference Schematic
9.4. Green Ethernet
9.4.1.
Link-On and Cable Length Power Saving
The RTL8309G provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
9.4.2.
Link-Down Power Saving
The RTL8309G implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected.
Single-Chip 9-Port 10/100Mbps Switch Controller
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Datasheet
10. Characteristics
10.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability may be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 113. Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage Referenced to GND: VDDD, VDDA, and 1.8V VDDIO
Supply Voltage Referenced to GND: 2.5V VDDIO
Supply Voltage Referenced to GND: 3.3V VDDIO
Digital Input Voltage
DC Output Voltage
Min
-55
GND-0.5
GND-0.5
GND-0.5
GND-0.5
GND-0.5
Max
150
+2.16
+3.00
+3.96
VDDD
VDDD
Units
°C
V
V
V
V
V
Max
70
1.95
2.625
3.45
Units
°C
V
V
V
10.2. Operating Range
Table 114. Operating Range
Parameter
Ambient Operating Temperature (Ta)
1.8V VDDD, VDDA, and VDDIO Supply Voltage Range
2.5V VDDIO Supply Voltage Range
3.3V VDDIO Supply Voltage Range
Single-Chip 9-Port 10/100Mbps Switch Controller
Min
0
1.71
2.375
3.15
105
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
10.3. DC Characteristics
Table 115. DC Characteristics
Parameter
TTL Input High Voltage
SYM
Vih
Condition
VDDIO = 1.8V
VDDIO = 3.3V
TTL Input Low Voltage
Vil
VDDIO = 1.8V
VDDIO = 3.3V
TTL Input Current
Iin
TTL Input Capacitance
Cin
Output High Voltage
Voh VDDIO = 1.8V
VDDIO = 3.3V
Output Low Voltage
Vol
VDDIO = 1.8V
VDDIO = 3.3V
Output Three State Leakage Current
|IOZ| Transmitter, 100Base-TX (1:1 Transformer Ratio)
TX+/- Output Current High
IOH
TX+/- Output Current Low
IOL
Transmitter, 10Base-T (1:1 Transformer Ratio)
TX+/- Output Current High
IOH
TX+/- Output Current Low
IOL
Receiver, 100Base-TX
RX+/- Common-Mode Input Voltage
RX+/- Differential Input Resistance
Receiver, 10Base-T
Differential Input Resistance
-
Single-Chip 9-Port 10/100Mbps Switch Controller
106
Min
1.5
2.0
-10
1.7
2.6
0.0
0.0
-
Typical
3
-
Max
0.8
0.8
10
3.6
0.4
0.4
10
Units
V
V
V
V
µA
pF
V
V
V
V
µA
0
-
40
-
mA
µA
0
-
100
-
mA
µA
-
1.8
2.4
-
V
kΩ
-
2.4
-
kΩ
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
10.4. AC Characteristics
Table 116. AC Characteristics
Parameter
Differential Output Voltage, Peak-to-Peak
Differential Output Voltage Symmetry
Differential Output Overshoot
Rise/Fall Time
Rise/Fall Time Imbalance
Duty Cycle Distortion
Timing Jitter
Differential Output Voltage, Peak-to-Peak
TP_IDL Silence Duration
TD Short Circuit Fault Tolerance
TD Differential Output Impedance
(Return Loss)
TD Common-Mode Output Voltage
Transmitter Output Jitter
RD Differential Output Impedance
(Return Loss)
Harmonic Content
SYM Condition
Transmitter, 100Base-TX
VOD 50Ω from each output to Vcc,
Best-fit over 14 bit times
VOS 50Ω from each output to Vcc,
|Vp+|/ |Vp-|
VOO Percent of Vp+ or Vptr ,tf 10-90% of Vp+ or Vp|tr - tf| Deviation from best-fit timegrid, 010101 … Sequence
Idle pattern
Transmitter, 10Base-T
VOD 50Ω from each output to Vcc,
all pattern
Period of time from start of
TP_IDL to link pulses or period
of time between link pulses
Peak output current on TD
short circuit for 10 seconds.
Return loss from 5MHz to
10MHz for reference resistance
of 100Ω.
Ecm Terminate each end with 50Ω
resistive load.
Return loss from 5MHz to
10MHz for reference resistance
of 100Ω.
dB below fundamental, 20
cycles of all ones data
Single-Chip 9-Port 10/100Mbps Switch Controller
107
Min
Typical
Max
Units
0.997
1.002
1.008
V
100.8
101.3
101.9
%
3.20
3.61
10
20
3.68
3.73
30
40
4.31
3.82
80
90
%
ns
ps
ps
675
825
900
ns
2.30
2.31
2.32
V
15.72
15.73
15.76
ms
245
254
273
mA
24.0
24.5
25.0
dB
40.2
44.3
45.1
mV
6.4
24.0
8.5
24.5
11.5
25.0
ns
dB
28.0
28.3
28.5
dB
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
10.5. Digital Timing Characteristics
M R X C /PTX C ,
M DC
M
M
M
M
Th
Ts
R X D /PTX D [3:0],
R X D V /PTX EN ,
C O L,
D IO
Figure 19. Reception Data Timing of MII/SNI/SMI Interface
M R X C /PTX C ,
M DC
T cyc
M
M
M
M
T os
T oh
R X D /PTX D [3:0],
R X D V /PTX EN ,
C O L,
D IO
Figure 20. Transmission Data Timing of MII/SNI/SMI Interface
Table 117. Digital Timing Characteristics
Parameter
SYM
100BaseT MTXC/MRXC,
MRXC/PTXC
10BaseT MTXC/MRXC,
MRXC/PTXC
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Setup Time
Tcyc
Tcyc
Tos
Condition
MAC Mode MII Timing
MTXC/MRXC, MRXC/PTXC clock
cycle time
MTXC/MRXC, MRXC/PTXC clock
cycle time
Output Setup time from REFCLK rising
edge to MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV
Single-Chip 9-Port 10/100Mbps Switch Controller
108
I/O
Min
Type
I
-
I
-
O
22
40±50
ppm
400±50
ppm
24
Max Units
-
ns
-
ns
26
ns
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Parameter
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Hold Time
MRXD[3:0]/PTXD[3:0],
MRXDV/PTXEN,
MCOL/PCOL Setup Time
MRXD/PTXD,
MRXDV/PTXEN,
MCOL/PCOL Hold Time
SYM
Toh
100BaseT MTXC/MRXC,
MRXC/PTXC,
Tcyc
10BaseT
MTXC/PRXC,
MRXC/PTXC,
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output Setup
Time
Tcyc
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output Hold
Time
MRXD/PTXD[3:0],
MRXDV/PTXEN, Setup
Time
MRXD/PTXD[3:0],
MRXDV/PTXEN, Hold Time
Toh
MTXC/MRXC,
MRXC/PTXC
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output Setup
Time
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output Hold
Time
MRXD/PTXD[0],
MRXDV/PTXEN Setup Time
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Hold Time
Tcyc
LED On Time
LED Off Time
Ts
Th
Tos
Ts
Th
Tos
Condition
Output Hold time from REFCLK rising
edge to MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV
MTXD[3:0]/PRXD[3:0],
MRXDV/PTXEN to REFCLK rising
edge setup time
MTXD[3:0]/PRXD[3:0],
MRXDV/PTXEN to REFCLK rising
edge hold time
PHY Mode MII Timing
MTXC/MRXC, MRXC/PTXC,
PHY2PTXC, PHY2PRXC clock cycle
time
MTXC/MRXC, MRXC/PTXC,
PHY2PTXC, PHY2PRXC clock cycle
time
Output Setup time from REFCLK rising
edge to MTXD[3:0]/PRXD[3:0],
PHY2PRXD[3:0], MTXEN/PRXDV,
PHY2PRXDV MCOL/PCOL,
PHY2PCOL
Output Hold time from REFCLK rising
edge to MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV, MCOL/PCOL
I/O
O
Min
14
Type
16
Max Units
18
ns
I
4
-
-
ns
I
2
-
-
ns
O
-
40±50
ppm
-
ns
O
-
400±50
ppm
-
ns
O
14
16
18
ns
O
22
24
26
ns
MTXD[3:0]/PRXD[3:0],
MRXDV/PTXEN to REFCLK rising
edge setup time
MTXD[3:0]/PRXD[3:0],
MRXDV/PTXEN to REFCLK rising
edge hold time
PHY Mode SNI Timing
MTXC/PRXC, MRXC/PTXC clock
cycle time
Output Setup time from REFCLK rising
edge to MTXD[0]/PRXD[0],
MTXEN/PRXDV, MCOL/PCOL
I
4
-
-
ns
I
2
-
-
ns
O
-
-
ns
O
28
100±50
ppm
30
32
ns
Toh
Output Hold time from REFCLK rising
edge to MTXD[0]/PRXD[0],
MTXEN/PRXDV, MCOL/PCOL
O
68
70
72
ns
Ts
MTXD[0]/PRXD[0], MRXDV/PTXEN
to REFCLK rising edge setup time
MTXD[0]/PRXD[0], MRXDV/PTXEN
to REFCLK rising edge hold time
I
4
-
-
ns
I
2
-
-
ns
O
O
43
43
-
120
120
ms
ms
Th
LED Timing
tLEDon While LED blinking
tLEDoff While LED blinking
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
10.6. Thermal Characteristics
Heat generated by the chip causes a temperature rise of the package. If the temperature of the chip (Tj,
junction temperature) is beyond the design limits, there will be negative effects on operation and the life
of the IC package. Heat dissipation, either through a heat sink or electrical fan, is necessary to provide a
reasonable environment (Ta, ambient temperature) in a closed case. As power density increases, thermal
management becomes more critical. A method to estimate the possible Ta is outlined below.
Thermal parameters are defined as below according to JEDEC standard JESD 51-2, 51-6:
θja (Thermal resistance from junction to ambient), represents resistance to heat flow from the chip to
ambient air. This is an index of heat dissipation capability. A lower θja means better thermal performance.
θja = (Tj - Ta) / Ph
Where Tj is the junction temperature
Ta is the ambient temperature
Ph is the power dissipation
ψJT (Thermal resistance from junction to case), represents resistance to heat flow from the chip to the
package top case.
ψJT = (Tj - Tc) / Ph, where Tj is the junction temperature.
Ta
Tc
Tj
Figure 21. Cross-section of 128-Pin PQFP
Single-Chip 9-Port 10/100Mbps Switch Controller
110
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Table 118. Thermal Operating Range
Parameter
Junction Operating Temperature
Ambient Operating Temperature
SYM
Tj
Ta
Condition
-
Min
0
0
Typical
25
25
Max
125
55
Units
°C
°C
Min
-
Typical
36.7
Max
-
Units
°C/W
-
6.1
-
°C/W
Table 119. Thermal Resistance
Parameter
Thermal Resistance: Junction to Ambient
SYM
θja
Condition
2 layer PCB, 0 ft/s airflow,
ambient temperature 25°C
Thermal Resistance: Junction to Case
ψJT 2 layer PCB, 0 ft/s airflow,
ambient temperature 25°C
Note: PCB conditions. Dimensions: 85 x 110mm. Thickness: 1.6mm.
11. Design and Layout
In order to achieve maximum performance using the RTL8309G, good design attention is required
throughout the design and layout process. The following are some recommendations on how to
implement a high-performance system.
General Guidelines
Provide a good power source, minimizing noise from switching power supply circuits (<50mV).
Keep power and ground noise levels below 50mV.
Verify the ability of critical components, e.g., clock source and transformer, to meet application
requirements.
Use bulk capacitors (4.7μF-10μF) between the power and ground planes.
Use 0.1μF de-coupling capacitors to reduce high-frequency noise on the power and ground planes.
Keep de-coupling capacitors as close as possible to the RTL8309G.
Differential Signal Layout Guidelines
Keep differential pairs as close as possible and route both traces as identically as possible.
Avoid vias and layer changes if possible.
Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane.
Keep each different pair on the same plane.
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Clock Circuit
The clock should be 25M 100ppm with jitter less than 0.5ns.
If possible, surround the clock by ground trace to minimize high-frequency emissions.
Power Planes
Divide the power plane into 1.8V digital, 1.8V analog.
Use 0.1μF decoupling capacitors and bulk capacitors between each power plane and ground plane.
Place two 47μF bulk capacitors on the device-side (primary) center tap of the transformer.
Ground Plane
Keep the system ground region as one continuous, unbroken plane that extends from the primary side of
the transformer to the rest of the board.
Place a moat (gap) between the system ground and chassis ground.
Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis
ground area.
Transformer Options
The RTL8309G can use a transformer that supports auto crossover detection and auto correction with a
1:1 turn ratio on both transmit and receive paths. There are many venders improving their transformer
design to meet the RTL8309G’s requirement.
Vendor
Pulse
Magnetic 1
BothHand
Macronics
Single-Chip 9-Port 10/100Mbps Switch Controller
Quad
H1164
ML164
40ST1041AX
HS2275
112
Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
The center taps on the primary side of the transmit and receive paths in the transformer should be
connected together inside the transformer and provide one common external pin (Figure 22). This
common pin should connect to 1.8V directly and connect to ground via a 0.1μF capacitor as shown in
Figure 22. This schematic will force the signal on the primary side to bias at 1.8V.
X
X
X
X
RXIP
RXIN
Transformer
1:1
50Ω
1%
50Ω
1%
RJ-45
1
2
0.1µF
AGND
3
1.8V
4
RTL8309G
TXOP
TXON
5
0.1µF
AGND
1:1
50Ω
1%
6
7
0.1µF
50Ω
1% AGND
8
75Ω
IBREF
75Ω
75Ω
2ΚΩ, 1%
0.01µF/1KV
AGND
Chassis GND
Figure 22. Application for Transformer with Connected Central Tap
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
Bob Smith Termination
‘Bob Smith’ termination is often provided for the unused signal pairs of RJ-45 pins 4 & 5, and 7 & 8 to
minimize the common mode noise induced from RJ-45 pins 1 & 2, and 3 & 6.
RJ-45
1:1
1
2
3
4
5
1:1
6
7
8
75Ω
75Ω
75Ω
0.1µF/3KV
Chassis GND
Figure 23. Bob Smith Termination
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
12. Mechanical Dimensions
See the Mechanical Dimensions notes on the next page.
Single-Chip 9-Port 10/100Mbps Switch Controller
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Track ID: JATR-1076-21 Rev. 1.2
RTL8309G
Datasheet
12.1. Notes for Mechanical Dimensions
Symbol
A
A1
A2
b
c
D
D1
E
E1
e
B
B
B
B
L
L1
y
θ
B
Dimensions in mm
Min Typical Max
3.40
0.25
2.50
2.72
2.97
0.10
0.20
0.30
0.09
0.23
23.2 BSC
20.00 BSC
17.20 BSC
14.00 BSC
0.5 BSC
Dimensions in inch
Min Typical Max
0.134
0.01
0.101 0.107 0.117
0.004 0.008 0.012
0.004
0.008
0.913 BSC
0.787 BSC
0.677 BSC
0.551 BSC
0.20 BSC
0.65
0.026
0.88
1.03
1.60 BSC
0.10
12°
B
0°
0°
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar
rotrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. Should be based on final
visual inspection.
TITLE: -CU L/F, FOOTPRINT 3.2 mm
LEADFRAME MATERIAL:
APPROVE
DOC. NO.
VERSION
0.035 0.041
0.063 BSC
0.004
12°
PAGE
DATE
REALTEK SEMICONDUCTOR CORP.
13. Ordering Information
Table 120. Ordering Information
Part Number
Package
RTL8309G-GR
128-Pin PQFP with ‘Green’ Package
Note: See page 7 for package identification information.
X
Status
Production
X
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Single-Chip 9-Port 10/100Mbps Switch Controller
116
Track ID: JATR-1076-21 Rev. 1.2
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