ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU
with Integrated Power Management Hardware
Reference
Revision 0.3, October 2017
Part Number
82-100132-01
Analog Devices, Inc.
One Technology Way
Norwood, MA 02062-9106
Notices
Copyright Information
© 2017 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form
without prior, express written consent from Analog Devices, Inc.
Printed in the USA.
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use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under the patent rights of Analog Devices, Inc.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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Contents
Introduction
ADuCM4050 MCU Features ........................................................................................................................ 1–1
ADuCM4050 Functional Description ........................................................................................................... 1–2
ADuCM4050 Block Diagram..................................................................................................................... 1–2
Memory Architecture.................................................................................................................................. 1–3
SRAM Region ............................................................................................................................................ 1–3
System Region ............................................................................................................................................ 1–4
Flash Controller.......................................................................................................................................... 1–5
Cache Controller ........................................................................................................................................ 1–5
ARM Cortex-M4F Memory Subsystem ...................................................................................................... 1–5
Booting ...................................................................................................................................................... 1–5
Security Features......................................................................................................................................... 1–6
Safety Features............................................................................................................................................ 1–6
Multi Parity Bit Protected SRAM............................................................................................................... 1–6
Programmable GPIOs ................................................................................................................................ 1–6
Timers ........................................................................................................................................................ 1–6
Power Management .................................................................................................................................... 1–7
Clocking ..................................................................................................................................................... 1–7
Real-Time Clock (RTC) ............................................................................................................................. 1–8
System Debug ............................................................................................................................................ 1–9
Beeper Driver ........................................................................................................................................... 1–10
Cryptographic Accelerator (Crypto) ......................................................................................................... 1–10
CRC Accelerator....................................................................................................................................... 1–10
True Random Number Generator (TRNG).............................................................................................. 1–11
Serial Ports (SPORTs) .............................................................................................................................. 1–11
Serial Peripheral Interface (SPI) Ports....................................................................................................... 1–11
UART Ports.............................................................................................................................................. 1–12
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Inter-Integrated Circuit (I2C) ................................................................................................................... 1–12
Analog-to-Digital Converter (ADC) Subsystem........................................................................................ 1–12
Reference Designs..................................................................................................................................... 1–12
Development Tools................................................................................................................................... 1–12
ADuCM4050 Peripheral Memory Map ....................................................................................................... 1–13
Debug (DBG) and Trace Interfaces
Debug and Trace Features.............................................................................................................................. 2–1
DBG Functional Description......................................................................................................................... 2–1
Serial Wire Interface ................................................................................................................................... 2–1
DBG Operating Modes ................................................................................................................................. 2–2
Serial Wire Protocol.................................................................................................................................... 2–2
Debug Access Port (DAP).............................................................................................................................. 2–4
Debug Port .................................................................................................................................................... 2–5
ADuCM4050 SYS Register Descriptions ...................................................................................................... 2–5
ADI Identification ..................................................................................................................................... 2–6
Chip Identifier ........................................................................................................................................... 2–7
Serial Wire Debug Enable .......................................................................................................................... 2–8
Events (Interrupts and Exceptions)
Events Features .............................................................................................................................................. 3–1
Events Interrupts and Exceptions................................................................................................................... 3–1
Cortex Exceptions....................................................................................................................................... 3–1
Nested Vectored Interrupt Controller ......................................................................................................... 3–2
Handling Interrupt Registers...................................................................................................................... 3–4
External Interrupt Configuration................................................................................................................ 3–5
ADuCM4050 XINT Register Descriptions .................................................................................................. 3–5
External Interrupt Configuration ............................................................................................................... 3–7
External Interrupt Clear .......................................................................................................................... 3–10
External Wakeup Interrupt Status ............................................................................................................ 3–11
Non-maskable Interrupt Clear ................................................................................................................. 3–13
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Power Management (PMG)
Power Management Features ......................................................................................................................... 4–1
Power Management Functional Description .................................................................................................. 4–1
Power-up Sequence..................................................................................................................................... 4–1
Operating Modes ........................................................................................................................................... 4–2
Active Mode ............................................................................................................................................... 4–2
Flexi Mode.................................................................................................................................................. 4–3
Hibernate Mode ......................................................................................................................................... 4–4
Shutdown Mode ......................................................................................................................................... 4–5
Programming Sequence ................................................................................................................................. 4–6
Configuring Hibernate Mode ..................................................................................................................... 4–6
Configuring Shutdown Mode..................................................................................................................... 4–7
Wake-up Sequence ......................................................................................................................................... 4–8
Fast Wake-up from Shutdown Mode.............................................................................................................. 4–8
Monitor Voltage Control ............................................................................................................................... 4–8
ADuCM4050 PMG Register Descriptions ................................................................................................. 4–10
HPBUCK Control ................................................................................................................................... 4–12
Power Supply Monitor Interrupt Enable .................................................................................................. 4–13
Trimming Bits ......................................................................................................................................... 4–15
Power Supply Monitor Status .................................................................................................................. 4–16
Key Protection for PMG_PWRMOD and PMG_SRAMRET ................................................................ 4–19
Power Mode Register ............................................................................................................................... 4–20
Reset Status ............................................................................................................................................. 4–21
Shutdown Status Register ........................................................................................................................ 4–23
Control for Retention SRAM in Hibernate Mode ................................................................................... 4–24
ADuCM4050 PMG_TST Register Descriptions ........................................................................................ 4–24
Clear GPIO After Shutdown Mode ......................................................................................................... 4–26
Fast Shutdown Wake-up Enable .............................................................................................................. 4–27
Scratch Pad Saved in Battery Domain ...................................................................................................... 4–28
Scratch Pad Image ................................................................................................................................... 4–29
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Control for SRAM Parity and Instruction SRAM .................................................................................... 4–30
Initialization Status Register .................................................................................................................... 4–32
General-Purpose I/O (GPIO)
GPIO Features............................................................................................................................................... 5–1
GPIO Functional Description........................................................................................................................ 5–1
GPIO Block Diagram................................................................................................................................. 5–1
ADuCM4050 GPIO Multiplexing ............................................................................................................. 5–3
GPIO Operating Modes ................................................................................................................................ 5–5
IO Pull-Up or Pull-Down Enable ............................................................................................................... 5–5
IO Data In ................................................................................................................................................. 5–5
IO Data Out............................................................................................................................................... 5–5
Bit Set......................................................................................................................................................... 5–5
Bit Clear ..................................................................................................................................................... 5–5
Bit Toggle ................................................................................................................................................... 5–5
IO Data Output Enable.............................................................................................................................. 5–5
Interrupts ................................................................................................................................................... 5–5
Interrupt Polarity........................................................................................................................................ 5–6
Interrupt A Enable...................................................................................................................................... 5–6
Interrupt B Enable...................................................................................................................................... 5–6
Interrupt Status .......................................................................................................................................... 5–6
GPIO Programming Model ........................................................................................................................... 5–7
ADuCM4050 GPIO Register Descriptions .................................................................................................. 5–7
Port Configuration .................................................................................................................................... 5–8
Port Data Out Clear ................................................................................................................................ 5–10
Port Drive Strength Select ....................................................................................................................... 5–11
Port Input Path Enable ............................................................................................................................ 5–14
Port Interrupt A Enable ........................................................................................................................... 5–15
Port Interrupt B Enable ........................................................................................................................... 5–16
Port Registered Data Input ...................................................................................................................... 5–17
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Port Interrupt Status ................................................................................................................................ 5–18
Port Output Enable ................................................................................................................................. 5–19
Port Data Output .................................................................................................................................... 5–20
Port Output Pull-up/Pull-down Enable ................................................................................................... 5–21
Port Interrupt Polarity ............................................................................................................................. 5–22
Port Data Out Set .................................................................................................................................... 5–23
Port Pin Toggle ........................................................................................................................................ 5–24
System Clocks
System Clock Features ................................................................................................................................... 6–1
System Clock Functional Description ............................................................................................................ 6–2
System Clock Block Diagram ..................................................................................................................... 6–2
Clock Muxes ........................................................................................................................................... 6–3
Clock Dividers ........................................................................................................................................ 6–3
Clock Gating........................................................................................................................................... 6–4
PLL Settings .................................................................................................................................................. 6–4
PLL Interrupts............................................................................................................................................ 6–6
PLL Programming Sequence ...................................................................................................................... 6–6
Crystal Programming..................................................................................................................................... 6–7
Oscillator Programming ................................................................................................................................ 6–7
Switching System Clock to Greater than 26 MHz ......................................................................................... 6–8
Oscillators...................................................................................................................................................... 6–8
System Clock Interrupts and Exceptions...................................................................................................... 6–12
Setting the System Clocks............................................................................................................................ 6–12
Set System Clock to PLL Input Source ..................................................................................................... 6–12
Set System Clock to XTAL ....................................................................................................................... 6–15
Changing System Clock Source ................................................................................................................ 6–17
ADuCM4050 CLKG_OSC Register Descriptions ...................................................................................... 6–18
Oscillator Control ................................................................................................................................... 6–19
Key Protection for OSCCTRL ................................................................................................................ 6–25
ADuCM4050 CLKG_CLK Register Descriptions ...................................................................................... 6–25
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Misc Clock Settings ................................................................................................................................. 6–26
Clock Dividers ......................................................................................................................................... 6–29
HF Oscillator Divided Clock Select ......................................................................................................... 6–31
System PLL ............................................................................................................................................. 6–33
User Clock Gating Control ...................................................................................................................... 6–35
Clocking Status ....................................................................................................................................... 6–38
Reset (RST)
ADuCM4050 Reset Register Description ...................................................................................................... 7–2
Reset Status ............................................................................................................................................... 7–3
Flash Controller (FLASH)
Flash Features ................................................................................................................................................ 8–1
Supported Commands................................................................................................................................ 8–1
Protection and Integrity Features................................................................................................................ 8–2
Flash Functional Description ......................................................................................................................... 8–2
Organization .............................................................................................................................................. 8–2
Flash Access ................................................................................................................................................ 8–6
Reading Flash .......................................................................................................................................... 8–8
Erasing Flash ........................................................................................................................................... 8–8
Writing Flash........................................................................................................................................... 8–8
Protection and Integrity............................................................................................................................ 8–13
Integrity of Info Space........................................................................................................................... 8–13
User Space Protection............................................................................................................................ 8–13
Runtime Configuration ......................................................................................................................... 8–14
Meta Data Configuration ...................................................................................................................... 8–15
Signatures.............................................................................................................................................. 8–16
Key Register .......................................................................................................................................... 8–17
ECC ...................................................................................................................................................... 8–17
Clock and Timings................................................................................................................................ 8–19
Flash Operating Modes................................................................................................................................ 8–19
Clock Gating ............................................................................................................................................... 8–20
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Flash Interrupts and Exceptions................................................................................................................... 8–20
Flash Programming Model........................................................................................................................... 8–20
Programming Guidelines.......................................................................................................................... 8–20
ADuCM4050 FLCC Register Descriptions ................................................................................................ 8–21
IRQ Abort Enable (Upper Bits) ............................................................................................................... 8–22
IRQ Abort Enable (Lower Bits) ............................................................................................................... 8–23
Flash Security .......................................................................................................................................... 8–24
Volatile Flash Configuration .................................................................................................................... 8–25
Command ............................................................................................................................................... 8–26
ECC Status (Address) .............................................................................................................................. 8–30
ECC Configuration ................................................................................................................................. 8–31
Interrupt Enable ...................................................................................................................................... 8–32
Key .......................................................................................................................................................... 8–33
Write Address .......................................................................................................................................... 8–34
Write Lower Data .................................................................................................................................... 8–35
Write Upper Data .................................................................................................................................... 8–36
Lower Page Address ................................................................................................................................. 8–37
Upper Page Address ................................................................................................................................. 8–38
Signature ................................................................................................................................................. 8–39
Status ....................................................................................................................................................... 8–40
Time Parameter 0 .................................................................................................................................... 8–46
Time Parameter 1 .................................................................................................................................... 8–49
User Configuration .................................................................................................................................. 8–51
Write Protection ...................................................................................................................................... 8–53
Write Abort Address ................................................................................................................................ 8–55
Static Random Access Memory (SRAM)
SRAM Features .............................................................................................................................................. 9–1
SRAM Configuration .................................................................................................................................... 9–1
Instruction SRAM vs Data SRAM.............................................................................................................. 9–1
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SRAM Retention in Hibernate Mode ......................................................................................................... 9–2
SRAM Programming Model .......................................................................................................................... 9–2
SRAM Parity ................................................................................................................................................. 9–2
SRAM Initialization....................................................................................................................................... 9–3
Initialization in Cache ................................................................................................................................ 9–4
Kernel Code: SRAM Bank 0 Initialization Before User Code Execution..................................................... 9–4
ADuCM4050 SRAM Register Description.................................................................................................... 9–4
Initialization Status Register ...................................................................................................................... 9–5
Control for SRAM Parity and Instruction SRAM ...................................................................................... 9–7
Control for Retention SRAM in Hibernate Mode ..................................................................................... 9–9
Cache
Cache Programming Model ......................................................................................................................... 10–1
Programming Guidelines.......................................................................................................................... 10–1
ADuCM4050 FLCC_CACHE Register Descriptions ................................................................................. 10–1
Cache Key Register .................................................................................................................................. 10–2
Cache Setup Register ............................................................................................................................... 10–3
Cache Status Register .............................................................................................................................. 10–4
Direct Memory Access (DMA)
DMA Features ............................................................................................................................................. 11–1
DMA Functional Description ...................................................................................................................... 11–2
DMA Architectural Concepts ................................................................................................................... 11–3
DMA Operating Modes............................................................................................................................... 11–3
Channel Control Data Structure............................................................................................................... 11–3
Source Data End Pointer .......................................................................................................................... 11–5
Destination Data End Pointer .................................................................................................................. 11–5
Control Data Configuration ..................................................................................................................... 11–5
DMA Priority ........................................................................................................................................... 11–8
DMA Transfer Types ................................................................................................................................ 11–9
Invalid ................................................................................................................................................... 11–9
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Basic...................................................................................................................................................... 11–9
Auto-Request....................................................................................................................................... 11–10
Ping-Pong ........................................................................................................................................... 11–10
Memory Scatter-Gather....................................................................................................................... 11–12
Peripheral Scatter-Gather .................................................................................................................... 11–14
DMA Interrupts and Exceptions............................................................................................................. 11–16
Error Management .............................................................................................................................. 11–16
Address Calculation............................................................................................................................. 11–16
Address Decrement.............................................................................................................................. 11–17
Endian Operation................................................................................................................................... 11–18
DMA Channel Enable/Disable ............................................................................................................... 11–19
DMA Master Enable .............................................................................................................................. 11–20
Power-down Considerations ................................................................................................................... 11–20
DMA Programming Model........................................................................................................................ 11–20
Programming Guidelines........................................................................................................................ 11–20
ADuCM4050 DMA Register Descriptions ............................................................................................... 11–21
DMA Channel Alternate Control Database Pointer .............................................................................. 11–22
DMA Channel Primary Alternate Clear ................................................................................................ 11–23
DMA Channel Primary Alternate Set .................................................................................................... 11–24
DMA Channel Bytes Swap Enable Clear ............................................................................................... 11–25
DMA Channel Bytes Swap Enable Set ................................................................................................... 11–26
DMA Configuration .............................................................................................................................. 11–27
DMA Channel Destination Address Decrement Enable Clear ............................................................... 11–28
DMA Channel Destination Address Decrement Enable Set ................................................................... 11–29
DMA Channel Enable Clear .................................................................................................................. 11–30
DMA Channel Enable Set ..................................................................................................................... 11–31
DMA per Channel Error Clear .............................................................................................................. 11–32
DMA Bus Error Clear ........................................................................................................................... 11–33
DMA per Channel Invalid Descriptor Clear .......................................................................................... 11–34
DMA Channel Primary Control Database Pointer ................................................................................ 11–35
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DMA Channel Priority Clear ................................................................................................................ 11–36
DMA Channel Priority Set .................................................................................................................... 11–37
DMA Controller Revision ID ................................................................................................................ 11–38
DMA Channel Request Mask Clear ...................................................................................................... 11–39
DMA Channel Request Mask Set .......................................................................................................... 11–40
DMA Channel Source Address Decrement Enable Clear ....................................................................... 11–41
DMA Channel Source Address Decrement Enable Set ........................................................................... 11–42
DMA Status .......................................................................................................................................... 11–43
DMA Channel Software Request ........................................................................................................... 11–44
Cryptography (CRYPTO)
Crypto Features ........................................................................................................................................... 12–2
Crypto Functional Description .................................................................................................................... 12–2
Crypto Block Diagram ............................................................................................................................. 12–3
Crypto Operating Modes............................................................................................................................. 12–3
Crypto Data Transfer................................................................................................................................... 12–4
Crypto Data Rate ..................................................................................................................................... 12–4
Data Pipeline............................................................................................................................................ 12–5
DMA Capability....................................................................................................................................... 12–5
Core Transfer............................................................................................................................................ 12–5
Data Formatting .......................................................................................................................................... 12–5
Interrupts..................................................................................................................................................... 12–7
Crypto Error Conditions ............................................................................................................................. 12–8
Crypto Status Bits........................................................................................................................................ 12–8
Crypto Keys............................................................................................................................................... 12–10
Key Length ............................................................................................................................................. 12–10
Key Programming .................................................................................................................................. 12–10
Key Wrap-Unwrap Register .................................................................................................................... 12–11
Key Register Attributes........................................................................................................................... 12–11
Crypto Power Saver Mode ......................................................................................................................... 12–11
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Registers with Mode Specific Roles............................................................................................................ 12–11
Protected Key Storage (PrKStor)................................................................................................................ 12–13
Operation ............................................................................................................................................... 12–14
Protected Key Storage Configuration...................................................................................................... 12–15
Command Fail Status ............................................................................................................................. 12–18
HMAC ...................................................................................................................................................... 12–19
HMAC Algorithm .................................................................................................................................. 12–19
Programming Model .............................................................................................................................. 12–20
CCM/CCM* Mode ................................................................................................................................... 12–21
Programming Flow for Block Modes of operation ..................................................................................... 12–23
Payload and Authenticated Data Formatting .......................................................................................... 12–25
Programming Flow for SHA-Only Operation............................................................................................ 12–25
Retention in Hibernate Mode .................................................................................................................... 12–26
ADuCM4050 CRYPT Register Descriptions ............................................................................................ 12–26
AES Key Bits [31:0] ............................................................................................................................... 12–29
AES Key Bits [63:32] ............................................................................................................................. 12–30
AES Key Bits [95:64] ............................................................................................................................. 12–31
AES Key Bits [127:96] ........................................................................................................................... 12–32
AES Key Bits [159:128] ......................................................................................................................... 12–33
AES Key Bits [191:160] ......................................................................................................................... 12–34
AES Key Bits [223:192] ......................................................................................................................... 12–35
AES Key Bits [255:224] ......................................................................................................................... 12–36
NUM_VALID_BYTES ......................................................................................................................... 12–37
Configuration Register .......................................................................................................................... 12–38
Counter Initialization Vector ................................................................................................................. 12–41
Payload Data Length ............................................................................................................................. 12–42
Input Buffer .......................................................................................................................................... 12–43
Interrupt Enable Register ...................................................................................................................... 12–44
Key Wrap Unwrap Register 0 ................................................................................................................ 12–45
Key Wrap Unwrap Register 1 ................................................................................................................ 12–46
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Key Wrap Unwrap Register 10 .............................................................................................................. 12–47
Key Wrap Unwrap Register 11 .............................................................................................................. 12–48
Key Wrap Unwrap Register 12 .............................................................................................................. 12–49
Key Wrap Unwrap Register 13 .............................................................................................................. 12–50
Key Wrap Unwrap Register 14 .............................................................................................................. 12–51
Key Wrap Unwrap Register 15 .............................................................................................................. 12–52
Key Wrap Unwrap Register 2 ................................................................................................................ 12–53
Key Wrap Unwrap Register 3 ................................................................................................................ 12–54
Key Wrap Unwrap Register 4 ................................................................................................................ 12–55
Key Wrap Unwrap Register 5 ................................................................................................................ 12–56
Key Wrap Unwrap Register 6 ................................................................................................................ 12–57
Key Wrap Unwrap Register 7 ................................................................................................................ 12–58
Key Wrap Unwrap Register 8 ................................................................................................................ 12–59
Key Wrap Unwrap Register 9 ................................................................................................................ 12–60
Key Wrap Unwrap Validation String [63:32] ......................................................................................... 12–61
Key Wrap Unwrap Validation String [31:0] ........................................................................................... 12–62
Nonce Bits [31:0] .................................................................................................................................. 12–63
Nonce Bits [63:32] ................................................................................................................................ 12–64
Nonce Bits [95:64] ................................................................................................................................ 12–65
Nonce Bits [127:96] .............................................................................................................................. 12–66
Output Buffer ........................................................................................................................................ 12–67
Authentication Data Length .................................................................................................................. 12–68
PRKSTOR Configuration ..................................................................................................................... 12–69
SHA Bits [31:0] ..................................................................................................................................... 12–70
SHA Bits [63:32] ................................................................................................................................... 12–71
SHA Bits [95:64] ................................................................................................................................... 12–72
SHA Bits [127:96] ................................................................................................................................. 12–73
SHA Bits [159:128] ............................................................................................................................... 12–74
SHA Bits [191:160] ............................................................................................................................... 12–75
SHA Bits [223:192] ............................................................................................................................... 12–76
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SHA Bits [255:224] ............................................................................................................................... 12–77
SHA Last Word and Valid Bits Information ........................................................................................... 12–78
Status Register ....................................................................................................................................... 12–79
True Random Number Generator (TRNG)
TRNG Features ........................................................................................................................................... 13–1
TRNG Functional Description .................................................................................................................... 13–1
TRNG Block Diagram ............................................................................................................................. 13–1
TRNG Oscillator Counter ....................................................................................................................... 13–2
TRNG Entropy and Surprisal................................................................................................................... 13–4
Oscillator Count Difference ..................................................................................................................... 13–5
ADuCM4050 RNG Register Descriptions .................................................................................................. 13–5
RNG Control Register ............................................................................................................................. 13–7
RNG Data Register ................................................................................................................................. 13–8
RNG Sample Length Register .................................................................................................................. 13–9
Oscillator Count .................................................................................................................................... 13–10
Oscillator Difference .............................................................................................................................. 13–11
RNG Status Register ............................................................................................................................. 13–12
Cyclic Redundancy Check (CRC)
CRC Features............................................................................................................................................... 14–1
CRC Functional Description ....................................................................................................................... 14–1
CRC Block Diagram................................................................................................................................. 14–1
CRC Operating Modes ................................................................................................................................ 14–2
Polynomial ............................................................................................................................................... 14–3
Reset and Hibernate Modes...................................................................................................................... 14–5
Input Data Length....................................................................................................................................... 14–5
CRC Data Transfer ...................................................................................................................................... 14–6
CRC Interrupts and Exceptions ................................................................................................................... 14–6
CRC Programming Model........................................................................................................................... 14–6
Mirroring Options.................................................................................................................................... 14–8
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ADuCM4050 CRC Register Descriptions .................................................................................................. 14–9
CRC Control ......................................................................................................................................... 14–10
Input Data Bits ...................................................................................................................................... 14–12
Input Data Byte ..................................................................................................................................... 14–13
Input Data Word ................................................................................................................................... 14–14
Programmable CRC Polynomial ............................................................................................................ 14–15
CRC Result ........................................................................................................................................... 14–16
Serial Peripheral Interface (SPI)
SPI Features................................................................................................................................................. 15–1
SPI Functional Description.......................................................................................................................... 15–2
SPI Block Diagram................................................................................................................................... 15–2
MISO (Master In, Slave Out) Pin............................................................................................................. 15–3
MOSI (Master Out, Slave In) Pin............................................................................................................. 15–3
SCLK (Serial Clock I/O) Pin .................................................................................................................... 15–3
Chip Select (CS I/O) Pin.......................................................................................................................... 15–3
SPI Operating Modes .................................................................................................................................. 15–4
Wired-OR Mode (WOM) ........................................................................................................................ 15–4
General Instructions.............................................................................................................................. 15–4
Power-down Mode ................................................................................................................................... 15–4
SPI2 vs SPI0/SPI1.................................................................................................................................... 15–5
Interfacing with SPI Slaves ....................................................................................................................... 15–5
Flow Control ............................................................................................................................................ 15–6
Three-Pin Mode ....................................................................................................................................... 15–8
SPI Data Transfer ........................................................................................................................................ 15–8
Transmit Initiated Transfer....................................................................................................................... 15–9
Receive Initiated Transfer ......................................................................................................................... 15–9
Transfers in Slave Mode.......................................................................................................................... 15–10
SPI Data Underflow and Overflow......................................................................................................... 15–11
SPI Interrupts and Exceptions ................................................................................................................... 15–11
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Transmit Interrupt.................................................................................................................................. 15–12
Receive Interrupt .................................................................................................................................... 15–12
Underflow/Overflow Interrupts.............................................................................................................. 15–13
SPI Programming Model ........................................................................................................................... 15–13
SPI DMA ............................................................................................................................................... 15–13
ADuCM4050 SPI Register Descriptions ................................................................................................... 15–15
Transfer Byte Count .............................................................................................................................. 15–17
Chip Select Control for Multi-slave Connections .................................................................................. 15–18
Chip Select Override ............................................................................................................................. 15–19
SPI Configuration ................................................................................................................................. 15–20
SPI Baud Rate Selection ........................................................................................................................ 15–23
SPI DMA Enable ................................................................................................................................... 15–24
FIFO Status ........................................................................................................................................... 15–25
Flow Control ......................................................................................................................................... 15–26
SPI Interrupts Enable ............................................................................................................................ 15–28
Read Control ......................................................................................................................................... 15–31
Receive .................................................................................................................................................. 15–33
Status ..................................................................................................................................................... 15–34
Transmit ................................................................................................................................................ 15–37
Wait Timer for Flow Control ................................................................................................................. 15–38
Serial Port (SPORT)
SPORT Features .......................................................................................................................................... 16–1
Signal Description ....................................................................................................................................... 16–2
SPORT Functional Description................................................................................................................... 16–3
SPORT Block Diagram ............................................................................................................................ 16–3
SPORT Transfer....................................................................................................................................... 16–4
Multiplexer Logic ..................................................................................................................................... 16–5
Serial Clock .............................................................................................................................................. 16–7
Frame Sync ............................................................................................................................................... 16–8
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Frame Sync Options .............................................................................................................................. 16–9
Sampling Edge........................................................................................................................................ 16–11
Premature Frame Sync Error Detection .................................................................................................. 16–12
Serial Word Length................................................................................................................................. 16–13
Number of Transfers............................................................................................................................... 16–13
SPORT Power Management................................................................................................................... 16–14
SPORT Operating Modes ......................................................................................................................... 16–14
Mode Selection ....................................................................................................................................... 16–14
SPORT Data Transfer ............................................................................................................................... 16–16
Single Word (Core) Transfers.................................................................................................................. 16–16
DMA Transfers....................................................................................................................................... 16–16
SPORT Data Buffers ................................................................................................................................. 16–17
Data Buffer Status .................................................................................................................................. 16–17
Data Buffer Packing ............................................................................................................................... 16–17
SPORT Interrupts and Exceptions............................................................................................................. 16–18
Error Detection ...................................................................................................................................... 16–18
System Transfer Interrupts ..................................................................................................................... 16–19
Transfer Finish Interrupt (TFI)............................................................................................................... 16–19
SPORT Programming Model .................................................................................................................... 16–19
ADuCM4050 SPORT Register Descriptions ............................................................................................ 16–20
Half SPORT 'A' Control Register ......................................................................................................... 16–21
Half SPORT 'B' Control Register ......................................................................................................... 16–26
Half SPORT 'A' Divisor Register .......................................................................................................... 16–30
Half SPORT 'B' Divisor Register .......................................................................................................... 16–31
Half SPORT A's Interrupt Enable register ............................................................................................ 16–32
Half SPORT B's Interrupt Enable register ............................................................................................ 16–34
Half SPORT A Number of transfers register ......................................................................................... 16–36
Half SPORT B Number of transfers register ......................................................................................... 16–37
Half SPORT 'A' Rx Buffer Register ....................................................................................................... 16–38
Half SPORT 'B' Rx Buffer Register ....................................................................................................... 16–39
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Half SPORT 'A' Status register ............................................................................................................. 16–40
Half SPORT 'B' Status register ............................................................................................................. 16–42
Half SPORT 'A' CNV width ................................................................................................................. 16–44
Half SPORT 'B' CNV width register .................................................................................................... 16–45
Half SPORT 'A' Tx Buffer Register ...................................................................................................... 16–46
Half SPORT 'B' Tx Buffer Register ...................................................................................................... 16–47
Universal Asynchronous Receiver/Transmitter (UART)
UART Features ............................................................................................................................................ 17–1
UART Functional Description ..................................................................................................................... 17–2
UART Block Diagram .............................................................................................................................. 17–2
UART Operations........................................................................................................................................ 17–2
Serial Communications ............................................................................................................................ 17–2
UART Operating Modes.............................................................................................................................. 17–5
IO Mode .................................................................................................................................................. 17–5
DMA Mode.............................................................................................................................................. 17–5
UART Interrupts ......................................................................................................................................... 17–5
FIFO Mode (16550) .................................................................................................................................... 17–6
Auto Baud Rate Detection (ABD)................................................................................................................ 17–6
RS485 Half-Duplex Mode ........................................................................................................................... 17–8
Receive Line Inversion ................................................................................................................................. 17–8
Clock Gating ............................................................................................................................................... 17–9
UART and Power-Down Modes .................................................................................................................. 17–9
ADuCM4050 UART Register Descriptions .............................................................................................. 17–10
Auto Baud Control ................................................................................................................................ 17–11
Auto Baud Status (High) ....................................................................................................................... 17–13
Auto Baud Status (Low) ......................................................................................................................... 17–14
UART Control Register ......................................................................................................................... 17–15
Baud Rate Divider ................................................................................................................................. 17–16
Fractional Baud Rate ............................................................................................................................. 17–17
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xix
FIFO Control ........................................................................................................................................ 17–18
Interrupt Enable .................................................................................................................................... 17–20
Interrupt ID .......................................................................................................................................... 17–21
Line Control .......................................................................................................................................... 17–22
Second Line Control .............................................................................................................................. 17–24
Line Status ............................................................................................................................................. 17–25
Modem Control ..................................................................................................................................... 17–27
Modem Status ....................................................................................................................................... 17–28
RX FIFO Byte Count ............................................................................................................................ 17–30
RS485 Half-duplex Control ................................................................................................................... 17–31
Receive Buffer Register .......................................................................................................................... 17–32
Scratch Buffer ........................................................................................................................................ 17–33
TX FIFO Byte Count ............................................................................................................................ 17–34
Transmit Holding Register .................................................................................................................... 17–35
Inter-Integrated Circuit (I2C) Interface
I2C Features ................................................................................................................................................ 18–1
I2C Functional Description ......................................................................................................................... 18–1
I2C Block Diagram .................................................................................................................................. 18–1
I2C Operating Modes.................................................................................................................................. 18–2
Master Transfer Initiation......................................................................................................................... 18–2
Slave Transfer Initiation............................................................................................................................ 18–2
Rx/Tx Data FIFOs ................................................................................................................................... 18–3
No Acknowledge from Master .................................................................................................................. 18–4
No Acknowledge from Slave ..................................................................................................................... 18–5
General Call ............................................................................................................................................. 18–5
Generation of Repeated Starts by Master.................................................................................................. 18–5
DMA Requests ......................................................................................................................................... 18–6
I2C Reset Mode ....................................................................................................................................... 18–6
I2C Test Modes ........................................................................................................................................ 18–6
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
I2C Low-Power Mode .............................................................................................................................. 18–6
I2C Bus Clear Operation.......................................................................................................................... 18–6
Power-down Considerations ..................................................................................................................... 18–7
I2C Data Transfer........................................................................................................................................ 18–7
I2C Interrupts and Exceptions..................................................................................................................... 18–8
ADuCM4050 I2C Register Descriptions .................................................................................................... 18–8
Master Address Byte 1 ............................................................................................................................. 18–9
Master Address Byte 2 ........................................................................................................................... 18–10
Hardware General Call ID ..................................................................................................................... 18–11
Automatic Stretch SCL .......................................................................................................................... 18–12
Start Byte ............................................................................................................................................... 18–14
Serial Clock Period Divisor .................................................................................................................... 18–15
First Slave Address Device ID ................................................................................................................ 18–16
Second Slave Address Device ID ............................................................................................................ 18–17
Third Slave Address Device ID .............................................................................................................. 18–18
Fourth Slave Address Device ID ............................................................................................................ 18–19
Master Control ...................................................................................................................................... 18–20
Master Current Receive Data Count ...................................................................................................... 18–22
Master Receive Data .............................................................................................................................. 18–23
Master Receive Data Count ................................................................................................................... 18–24
Master Status ......................................................................................................................................... 18–25
Master Transmit Data ............................................................................................................................ 18–28
Slave Control ......................................................................................................................................... 18–29
Shared Control ...................................................................................................................................... 18–31
Slave Receive .......................................................................................................................................... 18–32
Slave I2C Status/Error/IRQ ................................................................................................................... 18–33
Master and Slave FIFO Status ................................................................................................................ 18–36
Slave Transmit ....................................................................................................................................... 18–38
Timing Control Register ....................................................................................................................... 18–39
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxi
Beeper Driver (BEEP)
Beeper Features............................................................................................................................................ 19–1
Beeper Functional Description..................................................................................................................... 19–1
Beeper Block Diagram.............................................................................................................................. 19–1
Beeper Operating Modes ............................................................................................................................. 19–2
Pulse Mode............................................................................................................................................... 19–3
Sequence Mode......................................................................................................................................... 19–3
Tones........................................................................................................................................................ 19–4
Clocking and Power.................................................................................................................................. 19–4
Power-down Considerations ..................................................................................................................... 19–5
Beeper Interrupts and Events ....................................................................................................................... 19–5
Beeper Programming Model ........................................................................................................................ 19–5
Timing Diagram....................................................................................................................................... 19–5
Programming Guidelines.......................................................................................................................... 19–6
ADuCM4050 BEEP Register Descriptions ................................................................................................. 19–7
Beeper Configuration .............................................................................................................................. 19–8
Beeper Status ......................................................................................................................................... 19–10
Tone A Data .......................................................................................................................................... 19–12
Tone B Data .......................................................................................................................................... 19–13
ADC Subsystem
ADC Features .............................................................................................................................................. 20–1
ADC Functional Description ....................................................................................................................... 20–2
ADC Subsystem Block Diagram............................................................................................................... 20–2
ADC Subsystem Components ..................................................................................................................... 20–2
ADC Voltage Reference Selection ............................................................................................................. 20–2
Digital Offset Calibration......................................................................................................................... 20–4
Powering the ADC ................................................................................................................................... 20–4
Hibernate ................................................................................................................................................. 20–5
Sampling and Conversion Time ............................................................................................................... 20–6
xxii
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Operation ................................................................................................................................................. 20–8
Programming Flow................................................................................................................................. 20–10
Temperature Sensor ................................................................................................................................ 20–13
Battery Monitoring................................................................................................................................. 20–14
Oversampling ......................................................................................................................................... 20–15
Averaging Function................................................................................................................................. 20–15
ADC Digital Comparator....................................................................................................................... 20–17
ADuCM4050 ADC Register Descriptions ................................................................................................ 20–19
Alert Indication ..................................................................................................................................... 20–21
Averaging Configuration ....................................................................................................................... 20–22
Battery Monitoring Result ..................................................................................................................... 20–23
Calibration Word ................................................................................................................................... 20–24
ADC Configuration ............................................................................................................................... 20–25
Reference Buffer Low Power Mode ........................................................................................................ 20–27
Conversion Result Channel 0 ................................................................................................................ 20–28
Conversion Result Channel 1 ................................................................................................................ 20–29
Conversion Result Channel 2 ................................................................................................................ 20–30
Conversion Result Channel 3 ................................................................................................................ 20–31
Conversion Result Channel 4 ................................................................................................................ 20–32
Conversion Result Channel 5 ................................................................................................................ 20–33
Conversion Result Channel 6 ................................................................................................................ 20–34
Conversion Result Channel 7 ................................................................................................................ 20–35
ADC Conversion Configuration ............................................................................................................ 20–36
ADC Conversion Time .......................................................................................................................... 20–37
DMA Output Register ........................................................................................................................... 20–38
Channel 0 Hysteresis ............................................................................................................................. 20–39
Channel 1 Hysteresis ............................................................................................................................. 20–40
Channel 2 Hysteresis ............................................................................................................................. 20–41
Channel 3 Hysteresis ............................................................................................................................. 20–42
Interrupt Enable .................................................................................................................................... 20–43
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxiii
Channel 0 High Limit ........................................................................................................................... 20–44
Channel 0 Low Limit ............................................................................................................................ 20–45
Channel 1 High Limit ........................................................................................................................... 20–46
Channel 1 Low Limit ............................................................................................................................ 20–47
Channel 2 High Limit ........................................................................................................................... 20–48
Channel 2 Low Limit ............................................................................................................................ 20–49
Channel 3 High Limit ........................................................................................................................... 20–50
Channel 3 Low Limit ............................................................................................................................ 20–51
Overflow of Output Registers ................................................................................................................ 20–52
ADC Power-up Time ............................................................................................................................. 20–54
ADC Status ........................................................................................................................................... 20–55
Temperature Result 2 ............................................................................................................................ 20–57
Temperature Result ............................................................................................................................... 20–58
Real-Time Clock (RTC)
RTC Features............................................................................................................................................... 21–1
RTC Functional Description........................................................................................................................ 21–2
RTC Block Diagram................................................................................................................................. 21–2
RTC Operating Modes ................................................................................................................................ 21–3
Initial RTC Power-Up .............................................................................................................................. 21–3
Persistent, Sticky RTC Wake-Up Events ................................................................................................... 21–3
RTC Capacity to Accommodate Posted Writes by CPU ........................................................................... 21–4
Realignment of RTC Count to Packet Defined Time Reference ............................................................... 21–4
RTC Recommendations: Clocks and Power................................................................................................. 21–4
RTC Interrupts and Exceptions ................................................................................................................... 21–5
RTC Programming Model ........................................................................................................................... 21–5
Programming Guidelines.......................................................................................................................... 21–5
RTC SensorStrobe ....................................................................................................................................... 21–5
RTC Input Capture ................................................................................................................................... 21–13
RTC Power Modes Behavior...................................................................................................................... 21–17
xxiv
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions ................................................................................................. 21–19
RTC Alarm 0 ......................................................................................................................................... 21–22
RTC Alarm 1 ......................................................................................................................................... 21–23
RTC Alarm 2 ......................................................................................................................................... 21–24
RTC Count 0 ........................................................................................................................................ 21–25
RTC Count 1 ........................................................................................................................................ 21–26
RTC Count 2 ........................................................................................................................................ 21–27
RTC Control 0 ...................................................................................................................................... 21–28
RTC Control 1 ...................................................................................................................................... 21–32
RTC Control 2 for Configuring Input Capture Channels ...................................................................... 21–35
RTC Control 3 for Configuring SensorStrobe Channel ......................................................................... 21–40
RTC Control 4 for Configuring SensorStrobe Channel ......................................................................... 21–44
RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling ............................................... 21–48
RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge ...................................... 21–50
RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity .................................. 21–53
RTC Freeze Count ................................................................................................................................. 21–55
RTC GPIO Pin Mux Control Register 0 ............................................................................................... 21–56
RTC GPIO Pin Mux Control Register 1 ............................................................................................... 21–57
RTC Gateway ........................................................................................................................................ 21–58
RTC Input Capture Channel 2 .............................................................................................................. 21–59
RTC Input Capture Channel 3 .............................................................................................................. 21–60
RTC Input Capture Channel 4 .............................................................................................................. 21–61
RTC Modulo ......................................................................................................................................... 21–62
RTC SensorStrobe Channel 1 ................................................................................................................ 21–64
RTC Auto-Reload High Duration for SensorStrobe Channel 1 ............................................................. 21–65
RTC Auto-Reload Low Duration for SensorStrobe Channel 1 ............................................................... 21–66
RTC SensorStrobe Channel 1 Target ..................................................................................................... 21–67
RTC SensorStrobe Channel 2 ................................................................................................................ 21–68
RTC Auto-Reload High Duration for SensorStrobe Channel 2 ............................................................. 21–69
RTC Auto-Reload Low Duration for SensorStrobe Channel 2 ............................................................... 21–70
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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RTC SensorStrobe Channel 2 Target ..................................................................................................... 21–71
RTC SensorStrobe Channel 3 ................................................................................................................ 21–73
RTC Auto-Reload High Duration for SensorStrobe Channel 3 ............................................................. 21–74
RTC Auto-Reload Low Duration for SensorStrobe Channel 3 ............................................................... 21–75
RTC SensorStrobe Channel 3 Target ..................................................................................................... 21–76
RTC SensorStrobe Channel 4 ................................................................................................................ 21–78
RTC Mask for SensorStrobe Channel .................................................................................................... 21–79
RTC Masks for SensorStrobe Channels on Time Control ...................................................................... 21–81
RTC Snapshot 0 .................................................................................................................................... 21–82
RTC Snapshot 1 .................................................................................................................................... 21–83
RTC Snapshot 2 .................................................................................................................................... 21–84
RTC Status 0 ......................................................................................................................................... 21–85
RTC Status 1 ......................................................................................................................................... 21–90
RTC Status 2 ......................................................................................................................................... 21–93
RTC Status 3 ......................................................................................................................................... 21–98
RTC Status 4 ....................................................................................................................................... 21–103
RTC Status 5 ....................................................................................................................................... 21–107
RTC Status 6 ....................................................................................................................................... 21–112
RTC Status 7 ....................................................................................................................................... 21–115
RTC Status 8 ....................................................................................................................................... 21–117
RTC Status 9 ....................................................................................................................................... 21–122
RTC Trim ............................................................................................................................................ 21–126
Timer (TMR)
TMR Features.............................................................................................................................................. 22–1
TMR Functional Description ...................................................................................................................... 22–2
TMR Block Diagram................................................................................................................................ 22–2
TMR Operating Modes ............................................................................................................................... 22–3
Free Running Mode.................................................................................................................................. 22–3
Periodic Mode .......................................................................................................................................... 22–3
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Toggle Mode............................................................................................................................................. 22–4
Match Mode............................................................................................................................................. 22–4
PWM Modulation ....................................................................................................................................... 22–6
PWM Demodulation................................................................................................................................... 22–6
Clock Select ................................................................................................................................................. 22–7
Capture Events............................................................................................................................................. 22–7
TMR Interrupts and Exceptions .................................................................................................................. 22–9
ADuCM4050 TMR Register Descriptions ................................................................................................. 22–9
16-bit Load Value, Asynchronous .......................................................................................................... 22–10
16-bit Timer Value, Asynchronous ........................................................................................................ 22–11
Capture ................................................................................................................................................. 22–12
Clear Interrupt ...................................................................................................................................... 22–13
Control .................................................................................................................................................. 22–14
Timer Event Selection Register .............................................................................................................. 22–17
16-bit Load Value .................................................................................................................................. 22–18
PWM Control Register ......................................................................................................................... 22–19
PWM Match Value ................................................................................................................................ 22–20
Status ..................................................................................................................................................... 22–21
16-bit Timer Value ................................................................................................................................ 22–23
RGB Timer
RGB Timer Features .................................................................................................................................... 23–1
RGB Timer Functional Description............................................................................................................. 23–1
RGB Timer Block Diagram ......................................................................................................................... 23–1
RGB Timer Operation................................................................................................................................. 23–2
PWM Modulation.................................................................................................................................... 23–4
PWM Demodulation................................................................................................................................ 23–4
Clock Select .............................................................................................................................................. 23–5
Capture Events ......................................................................................................................................... 23–5
ADuCM4050 TMR_RGB Register Descriptions ........................................................................................ 23–7
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxvii
16-bit load value, asynchronous ............................................................................................................... 23–8
16-bit timer value, asynchronous ............................................................................................................. 23–9
Capture ................................................................................................................................................. 23–10
Clear interrupt ....................................................................................................................................... 23–11
Control .................................................................................................................................................. 23–12
Timer Event selection Register .............................................................................................................. 23–15
16-bit load value .................................................................................................................................... 23–16
PWM0 Control Register ....................................................................................................................... 23–17
PWM0 Match Value .............................................................................................................................. 23–18
PWM1 Control Register ....................................................................................................................... 23–19
PWM1 Match Value .............................................................................................................................. 23–20
PWM2 Control Register ....................................................................................................................... 23–21
PWM2 Match Value .............................................................................................................................. 23–22
Status ..................................................................................................................................................... 23–23
16-bit timer value .................................................................................................................................. 23–25
Watchdog Timer (WDT)
WDT Features ............................................................................................................................................. 24–1
WDT Functional Description...................................................................................................................... 24–1
WDT Block Diagram ............................................................................................................................... 24–1
WDT Operating Modes .............................................................................................................................. 24–2
Watchdog Synchronization ....................................................................................................................... 24–3
Watchdog Power Modes Behavior ............................................................................................................ 24–3
ADuCM4050 WDT Register Descriptions ................................................................................................. 24–3
Current Count Value ............................................................................................................................... 24–4
Control .................................................................................................................................................... 24–5
Load Value ............................................................................................................................................... 24–7
Clear Interrupt ........................................................................................................................................ 24–8
Status ....................................................................................................................................................... 24–9
ADuCM4050 Register List
xxviii
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Preface
Thank you for purchasing and developing systems using an ADuCM4050 Micro Controller Unit (MCU) from Analog Devices, Inc.
Purpose of This Manual
The ADuCM4050 Ultra Low Power ARM® Cortex®-M4F MCU with Integrated Power Management Hardware Reference provides architectural information about the ADuCM4050 microcontrollers. This hardware reference provides
the main architectural information about the microcontroller.
For programming information, visit the ARM Information Center at: http://infocenter.arm.com/help/
The applicable documentation for programming the ARM Cortex-M4F processor include:
• ARM Cortex-M4F Devices Generic User Guide
• ARM Cortex-M4F Technical Reference Manual
For timing, electrical, and package specifications, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F
MCU with Integrated Power Management Data Sheet.
Intended Audience
The primary audience for this manual is a programmer who is familiar with the Analog Devices processors. The
manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts, such as programming reference books and data sheets, that describe their target architecture.
What's New in This Manual?
This is the third preliminary revision (0.3) of the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference. This revision updates the Events (Interrupts and Exceptions), General-Purpose I/O (GPIO), System Clocks, Static Random Access Memory (SRAM), Universal Asynchronous Receiver/
Transmitter (UART), ADC Subsystem, and Real-Time Clock (RTC) chapters.
Technical or Customer Support
You can reach customer and technical support for processors from Analog Devices in the following ways:
• Post your questions in the analog microcontrollers support community at EngineerZone:
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxix
http://ez.analog.com/community/analog-microcontrollers
• Submit your questions to technical support at Connect with ADI Specialists:
http://www.analog.com/support
• E-mail your questions about software/hardware development tools to:
processor.tools.support@analog.com
• E-mail your questions about processors to:
iot_support@analog.com (world wide support)
• Phone questions to 1-800-ANALOGD (USA only)
• Contact your Analog Devices sales office or authorized distributor. Locate one at:
http://www.analog.com/adi-sales
• Send questions by mail to:
Analog Devices, Inc.
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106 USA
Product Information
Product information can be obtained from the Analog Devices Web site and the online help system.
Analog Devices Web Site
The Analog Devices Website (http://www.analog.com) provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
To access a complete technical library for each processor family, go to http://www.analog.com/processors/technical_library. The manuals selection opens a list of current manuals related to the product as well as a link to the
previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the
title that leads to the current correction report against the manual.
MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display
only the latest information about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your e-mail address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxx
EngineerZone
EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing
and DSP design questions.
Use EngineerZone to connect with other MCU developers who face similar design challenges. You can also use this
open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://
ez.analog.com to sign up.
Notation Conventions
Text conventions used in this manual are identified and described as follows. Additional conventions, which apply
only to specific chapters, may appear throughout this document.
Example
Description
File > Close
Titles in reference sections indicate the location of an item within the CrossCore
Embedded Studio IDE's menu system (for example, the Close command appears
on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly brackets and
separated by vertical bars; read the example as this or that. One or the other
is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by
vertical bars; read the example as an optional this or that.
[this, …]
Optional item lists in syntax descriptions appear within brackets delimited by
commas and terminated with an ellipse; read the example as an optional commaseparated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with Letter
Gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
NOTE:
NOTE: For correct operation, ...
A note provides supplementary information on a related topic. In the online version of this book, the word NOTE: appears instead of this symbol.
CAUTION:
CAUTION: Incorrect device operation may result if ...
CAUTION: Device damage may result if ...
A caution identifies conditions or inappropriate usage of the product that could
lead to undesirable results or product damage. In the online version of this book,
the word CAUTION appears instead of this symbol.
ATTENTION:
ATTENTION: Injury to device users may result if ...
A warning identifies conditions or inappropriate usage of the product that could
lead to conditions that are potentially hazardous for devices users. In the online
version of this book, the word ATTENTION appears instead of this symbol.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxxi
Register Diagram Conventions
Register diagrams use the following conventions:
• The descriptive name of the register appears at the top, followed by the short form of the name in parentheses.
• If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name. Read/write is the default and is not noted. Additional descriptive text may follow.
• If any bits in the register do not follow the overall read/write convention, this is noted in the bit description
after the bit name.
• If a bit has a short name, the short name appears first in the bit description, followed by the long name in
parentheses.
• The reset value appears in binary in the individual bits and in hexadecimal to the right of the register.
• Bits marked X have an unknown reset value. Consequently, the reset value of registers that contain such bits is
undefined or dependent on pin values at reset.
• Shaded bits are reserved.
NOTE: To ensure upward compatibility with future implementations, write back the value that is read for reserved
bits in a register, unless specified.
Register description tables use the following conventions:
• Each bit's or bit field's access type appears beneath the bit number in the table in the form (read-access/writeaccess). The access types include:
• R = read, RC = read clear, RS = read set, R0 = read zero, R1 = read one, Rx = read undefined
• W = write, NW = no write, W1C = write one to clear, W1S = write one to set, W0C = write zero to clear, W0S
= write zero to set, WS = write to set, WC = write to clear, W1A = write one action.
• Several bits and bit field descriptions include enumerations, identifying bit values and related functionality. Unless indicated (with a prefix), these enumerations are decimal values.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
xxxii
Introduction
1 Introduction
The ADuCM4050 MCU is an ultra low power microcontroller system with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM Cortex-M4F processor. The MCU also
has a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides
clocking, reset, and power management capability in addition to an analog-to-digital converter (ADC) subsystem.
The ADuCM4050 MCU provides a collection of power modes and features such as dynamic and software controlled clock gating and power gating to support extremely low dynamic and hibernate power.
ADuCM4050 MCU Features
The ADuCM4050 MCU supports the following features:
• Up to 52 MHz ARM Cortex-M4F processor
• 512 KB of embedded flash memory with ECC
• 128 KB system SRAM with parity
• 32 KB user configurable instruction/data SRAM with parity
4 KB of SRAM may be used as cache memory to reduce active power consumption by reducing access to flash
memory
• Power Management Unit (PMU)
• Power-on-Reset (POR) and Power Supply Monitor (PSM)
• A buck converter for improved efficiency during active and Flexi™ states
• A multilayer AMBA bus matrix
• A multi-channel central direct memory access (DMA) controller
• Programmable GPIOs
• Two UART peripheral interfaces
• One I2C interface
• Three SPI interfaces capable of interfacing gluelessly with a range of sensors and converters
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
1–1
ADuCM4050 Functional Description
• A serial port (SPORT) capable of interfacing with a wide range of radios and converters. Two single direction
half SPORT or one bidirectional full SPORT
• A beeper driver to produce single and multi-tone playback options
• A real-time clock (RTC) capable of maintaining accurate wall clock time
• A flexible real-time clock (FLEX_RTC) that supports a wide range of wake-up times
• Three general-purpose timers and one watchdog timer
• Crypto hardware supporting AES-128, AES-256 along with various modes (ECB, CBC, CTR, CBC-MAC,
CCM, CCM*) and SHA-256, and HMAC mode
• Protected key Storage with key wrap-unwrap
• Keyed HMAC with key unwrap
• True Random Number Generator (TRNG)
• Hardware CRC with programmable generator polynomial
• Multi parity-bit-protected SRAM
• A 12-bit, 1.8 MSPS, SAR ADC
• RGB timer for driving RGB LED
ADuCM4050 Functional Description
This section provides information on the function of the ADuCM4050 MCU.
ADuCM4050 Block Diagram
The ARM Cortex-M4F core is a 32-bit reduced instruction set computer (RISC) offering up to 66 MIPS of peak
performance at 52 MHz. A central DMA controller is used to efficiently move data between peripherals and memory.
1–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Functional Description
Serial Wire
ITM trace
PLL
HFXTAL
LFXTAL
HFOSC
LFOSC
Ref Buffer
Temp
Sensor
ADC
ADC Controller
CRYPTO
(AES 128/256,
SHA 256)
Keyed HMAC
Key Wrap-unwrap
Protected
Key Storage
ARM
Cortex-M4F
NVIC
WIC
MPU
FPU
HP Buck
Multi
Layer
AMBA
Bus
Matrix
UART0
Power
Management
Data SRAM/Instruction SRAM/Cache (128 KB)
DMA
SPORT
Flash (512 KB)
UART1
TMR0
TMR1
RTC0
RTC1
TMR2
RGB
TMR
WDT
Beeper
AHB-APB
Bridge
Programmable
CRC Polynomial
SPI0
SPI1
SPIH
I2C
TRNG
GPIO
Figure 1-1: ADuCM4050 Block Diagram
Memory Architecture
The ADuCM4050 MCU incorporates 512 KB of embedded flash memory for program code and nonvolatile data
storage, 96 KB of data SRAM, 32 KB of SRAM (configured as instruction space or data space). For added robustness and reliability, ECC can be enabled for the flash memory and multi bit parity can be used to detect random soft
errors in SRAM
SRAM Region
This memory space contains the application instructions and literal (constant) data which must be accessed in realtime. It supports read/write access by the ARM Cortex M4F core and read/write DMA access by system peripherals.
SRAM is divided into data SRAM of 96 KB and instruction SRAM of 32 KB. If instruction SRAM is not enabled,
then the associated 32 KB can be mapped as data SRAM, resulting in 128 KB of data SRAM.
Internal SRAM Data Region
This space can contain read/write data. Internal SRAM can be partitioned between code and data (SRAM region in
M4F space) in 32 KB blocks. Access to this region occurs at core clock speed, with no wait states. It supports read/
write access by the Cortex-M4F core and read/write DMA access by system devices.
The figure shows the address map of the SRAM for various user selectable configurations. For information about the
configuration, refer to Static Random Access Memory (SRAM).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
1–3
ADuCM4050 Functional Description
MODE0
SRAM
BANK
MODE1
MODE2
MODE3
ISRAM Enabled
Cache OFF
32 KB ISRAM
96 KB DSRAM
ISRAM Enabled
4 KB Cache
28 KB ISRAM
96 KB DSRAM
ISRAM Disabled
Cache OFF
0 KB ISRAM
128 KB DSRAM
ISRAM Disabled
4 KB Cache
0 KB ISRAM
124 KB DSRAM
512 KB Flash
512 KB Flash
512 KB Flash
512 KB Flash
16 KB DSRAM
16 KB DSRAM
Bank1
12 KB DSRAM
12 KB DSRAM
Bank2
4 KB DSRAM
INI ADDR
END ADDR
0x0000_0000
0x0007_FFFF
0x1000_0000
0x1000_2FFF
Bank1
12 KB ISRAM
12 KB ISRAM
0x1000_3000
0x1000_6FFF
Bank7
16 KB ISRAM
16 KB ISRAM
0x1000_7000
0x1000_7FFF
Bank2
4 KB ISRAM
0x2000_0000
0x2000_3FFF
Bank0
16 KB DSRAM
0x2000_4000
0x2000_6FFF
0x2000_7000
0x2000_7FFF
0x2004_0000
0x2004_3FFF
Bank3
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
0x2004_4000
0x2004_7FFF
Bank4
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
0x2004_8000
0x2004_FFFF
Bank5
32 KB DSRAM
32 KB DSRAM
32 KB DSRAM
32 KB DSRAM
0x2005_0000
0x2005_3FFF
Bank6
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
0x2005_4000
0x2005_7FFF
Bank7
16 KB DSRAM
16 KB DSRAM
16 KB DSRAM
Always Retained
Retained if SRAM_RET.RET1 is set
Retained if SRAM_RET.RET2 is set
Retained if SRAM_RET.RET3 is set
Retained if SRAM_RET.RET4 is set
Not Retained
Not Implemented
Figure 1-2: Selectable Configuration
System Region
The ARM Cortex-M4F processor accesses the system region on its SYS interface and is handled within the CortexM4F platform.
CoreSight™ ROM: The ROM table entries point to the debug components of the processor.
ARM APB Peripherals: This space is defined by ARM and occupies the bottom 256 KB of the SYS region. The
space supports read/write access by the M4F core to the ARM core’s internal peripherals (SCS, NVIC, WIC) and
the CoreSight ROM. It is not accessible by system DMA.
Platform Control Registers: This space has registers within the Cortex-M4F platform component that control the
ARM core, its memory, and the code cache. It is accessible by the M4F core (but not accessible by system DMA).
1–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Functional Description
Flash Controller
The ADuCM4050 MCU includes 512 KB of embedded flash memory, which is accessed using a flash controller.
The flash controller is coupled with a cache controller. A prefetch mechanism is implemented in the flash controller
to optimize code performance. Flash writes are supported by a key hole mechanism via APB writes to memory-mapped registers. The flash controller provides support for DMA-based key hole writes.
The flash controller supports:
• A fixed user key required for running protected commands including mass erase and page erase.
• An optional and user definable user failure analysis key (FAA key). Analog Devices personnel needs this key
while performing failure analysis.
• An optional and user definable write protection for user accessible memory.
• An optional 8-bit error correction code (ECC). This code may be enabled by user code (off by default).
Cache Controller
The ADuCM4050 MCU has an optional 4 KB instruction cache. In certain applications, enabling the cache and
executing the code can result in lower power consumption than operating directly from flash. When the cache controller is enabled, 4 KB of instruction SRAM is reserved as cache memory. In hibernate mode, the cache memory is
not retained.
ARM Cortex-M4F Memory Subsystem
The memory map of the ADuCM4050 MCU is based on the Cortex-M4F model from ARM. By retaining the
standardized memory mapping, it becomes easier to port applications across M4F platforms. ADuCM4050 application development is typically based on memory blocks across code/SRAM regions. Sufficient internal memory is
available via internal SRAM and internal flash.
Booting
The MCU supports the following boot modes:
• Booting from internal flash
• Upgrading software through UART download
If the SYS_BMODE0 pin (GPIO17) is pulled low during power-up or a hard reset, the MCU enters into serial
download mode. In this mode, an on-chip loader routine is initiated in the kernel, which configures the UART port
and communicates with the host to manage the firmware upgrade via a specific serial download protocol.
Table 1-1: Boot Modes
Boot Mode
Description
0
UART download mode.
1
Flash boot. Boot from integrated flash memory.
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ADuCM4050 Functional Description
Security Features
The ADuCM4050 MCU provides a combination of hardware and software protection mechanisms that lock out
access to the part in secure mode, but grant access in open mode. These mechanisms include password-protected
slave boot modes (UART), as well as password-protected SWD debug interfaces. During boot, the system is clocked
from an internal on-chip oscillator. Reset computes a hardware checksum of the information area and then permit
the CPU to execute the Analog Devices boot loader in the flash information area if the checksum passes. The Analog Devices boot loader inspects the GPIO boot pin (GPIO17) which determines if user code or a UART download
is executed.
There is a mechanism to protect the device contents (flash, SRAM, CPU registers, and peripheral registers) from
being read through an external interface by an unauthorized user. This is referred to as read protection.
It is possible to protect the device from being reprogrammed in-circuit with unauthorized code. This is referred to as
in-circuit write protection.
The device can be configured with no protection, read protection, or read and in-circuit write protection. It is not
necessary to provide in-circuit write protection without read protection.
Safety Features
The ADuCM4050 MCU provides several features that help achieve certain levels of system safety and reliability.
While the level of safety is mainly dominated by system considerations, the following features are provided to enhance robustness.
Multi Parity Bit Protected SRAM
In the MCU's SRAM and cache memory space, each word is protected by multiple parity bits to allow detection of
random soft errors.
Programmable GPIOs
The ADuCM4050 MCU has 44/51 GPIO pins in the LFCSP/WLCSP packages, which have multiple, configurable
functions defined by the user code. They can be configured as I/O pins and have programmable pull-up resistors
(SWD_CLK has a pull-down). All I/O pins are functional over the full supply range.
In deep sleep modes, GPIO pins retain state. On reset, they tristate.
Timers
General-Purpose Timers
The ADuCM4050 MCU has three identical general-purpose timers, each with a 16-bit up/down counter. The up/
down counter can be clocked from one of four user-selectable clock sources. Any selected clock source can be scaled
down using a prescaler of 1, 16, 64, or 256.
Watchdog Timer (WDT)
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Functional Description
The watchdog timer is a 16-bit count-down timer with a programmable prescaler. The prescaler source is selectable
and can be scaled by a factor of 1, 16, or 256. The watchdog timer is clocked by the 32 kHz on-chip oscillator
(LFOSC) and used to recover from an illegal software state. The WDT requires periodic servicing to prevent it from
forcing a reset or interrupt to the MCU.
RGB Timer
The ADuCM4050 MCU has one RGB Timer that supports common anode RGB LED. It has a timer counter and
three compare registers. It can generate three distinct PWM waveforms on three ports/pins simultaneously so that
different colors can be realized on the common anode RGB LED.
When the RGB timer is in operation, the other three general-purpose timers are available for user software.
All timers support event capture feature, where they can take 40 different interrupts.
Power Management
The ADuCM4050 MCU includes power management and clocking features.
Power Modes
The PMU provides control of the ADuCM4050 MCU power modes and allows the ARM Cortex-M4F to control
the clocks and power gating to reduce the dynamic power and hibernate power.
Several power modes are available. Each mode provides an additional low power benefit with a corresponding reduction in functionality.
• Active Mode: All peripherals can be enabled. Active power is managed by optimized clock management.
• Flexi Mode: The core is clock-gated, but the remainder of the system is active. No instructions can be executed
in this mode, but DMA transfers can continue between peripherals and memory.
• Hibernate Mode: This mode provides configurable SRAM and port pin retention, a limited number of wakeup interrupts, and (optionally) an active RTC.
• Shutdown Mode: This mode is the deepest sleep mode, in which all the digital and analog circuits are powered
down with an option to wake from four possible wake-up sources. The RTC can be (optionally) enabled in this
mode, and the device can be periodically woken up by the RTC interrupt.
• Shutdown Mode - Fast wake-up: The functionality is same as that of the shutdown mode, but with a faster
wake-up time (at the expense of high power consumption).
Clocking
The ADuCM4050 MCU has the following clocking options:
26 MHz
• Internal oscillator: HFOSC (26 MHz)
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ADuCM4050 Functional Description
• External crystal oscillator : HFXTAL (26 MHz or 16 MHz)
• GPIO clock in: SYS_CLK_IN
32 kHz
• Internal oscillator: LFOSC
• External crystal oscillator: LFXTAL
Clock Fail Detection
The LFOSC clock continuously monitors LFXTAL in active, Flexi, and hibernate modes. If LFXTAL stops running, there is an option to detect and generate an interrupt and/or automatically switch to LFOSC without software
intervention. The HFOSC clock monitors HFXTAL, GPIO CLK, and PLL CLK. If any of these clocks is used as
the system clock, and they fail to toggle, it can be detected through an interrupt. Also, there is an option to automatically switch to the HFOSC.
Real-Time Clock (RTC)
The ADuCM4050 MCU has two real-time clock blocks, RTC0 and RTC1 (also called FLEX_RTC).
The clock blocks share a low-power crystal oscillation circuit that operates in conjunction with a 32,768 Hz external
crystal or LFOSC.
The RTC has an alarm that interrupts the core when the programmed alarm value matches the RTC count. The
software enables and configures the RTC and correlates the count to the time of day.
The RTC also has a digital trim capability to allow a positive or negative adjustment to the RTC count at fixed
intervals.
The FLEX_RTC supports SensorStrobe™ mechanism, via the SensorStrobe pins (SSx). Using this mechanism, the
ADuCM4050 MCU can be used as a programmable clock generator in all power modes except shutdown mode. In
this way, the external sensors can have their timing domains mastered by the ADuC4050 MCU, as SensorStrobe can
output a programmable divider from the FLEX_RTC, which can operate up to a resolution of 30.7 μs. The sensors
and microcontroller are in sync, which removes the need for additional resampling of data to time align it.
In the absence of this mechanism,
• The external sensor uses an RC oscillator (~ ±30% typical variation). The MCU has to sample the data and
resample it on the MCU’s time domain before using it.
Or
• The MCU remains in a higher power state and drives each data conversion on the sensor side.
This mechanism allows the ADuCM4050 MCU to be in hibernate mode for a long duration and also avoids unnecessary data processing which extends the battery life of the product.
The following table shows the key differences between RTC0 and RTC1.
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ADuCM4050 Functional Description
Table 1-2: RTC Features
Features
RTC0
RTC1 (FLEX_RTC)
Resolution of time base
(prescaling)
Counts time at 1 Hz in units of seconds. Operationally, always prescales to 1 Hz (for example, divide by 32,768) and always counts real
time in units of seconds.
Can prescale the clock by any power of two from 0 to 15. It
can count time in units of any of these 16 possible prescale
settings. For example, the clock can be prescaled by 1, 2, 4,
8, …, 16384, or 32768.
Wake-up time
Time is specified in units of seconds.
Supports alarm times down to a resolution of 30.7 μs, i.e.,
where the time is specified down to a specific 32 kHz clock
cycle.
Number of alarms
One alarm only. Uses an absolute, non-repeating alarm time, specified in units of one second.
Two alarms. One absolute alarm time and one periodic
alarm, repeating every 60 prescaled time units.
SensorStrobe mechanism
Not available
Four independent SensorStrobe channels with fine control
on duty cycle and frequency (0.5 Hz to 16 kHz). SensorStrobe is an alarm mechanism in the RTC which causes an
output pulse to be sent via SSx pins to an external device to
instruct that device to take a measurement or perform some
action at a specific time. SensorStrobe events are scheduled
at a specific target time relative to the real-time count of the
RTC. This feature can be enabled in active, Flexi, and hibernate modes.
Input capture
Not available
Input capture takes a snapshot of the RTC real-time count
when an external device signals an event via a transition on
one of the GPIO inputs to the ADuCM4050 MCU. Typically, an input capture event is triggered by an autonomous
measurement or action on such a device, which then signals
to the ADuCM4050 MCU that the RTC must take a snapshot of time corresponding to the event. The taking of this
snapshot can wake up the ADuCM4050 MCU and cause
an interrupt to its CPU. The CPU can subsequently obtain
information from the RTC on the exact 32 kHz cycle on
which the input capture event occurred.
Input sampling
Not available
Each SensorStrobe channel has up to 3 separate GPIO inputs from an external device, which can be sampled based
on the output pulse sent to the external device. Each SensorStrobe channel can be configured to interrupt the
ADuCM4050 MCU when any activity happens on these
GPIO inputs from the external device. These inputs can
broadcast sensor states such as FIFO full, switch open, and
threshold crossed. This feature allows the MCU to remain
in hibernate mode and wakeup to process the data only
when a specific programmed sequence from an external device is detected.
System Debug
The ADuCM4050 MCU supports serial wire debug and trace via a single wire viewer port.
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ADuCM4050 Functional Description
Beeper Driver
The ADuCM4050 MCU has an integrated audio driver for a beeper.
The beeper driver module in the ADuCM4050 MCU generates a differential square wave of programmable frequency. It drives an external piezoelectric sound component whose two terminals connect to the differential square
wave output. The beeper driver consists of a module that can deliver frequencies from 8 kHz to ~0.25 kHz. It operates on a fixed independent 32 kHz (32,768 Hz) clock source that is unaffected by changes in system clocks.
It allows for programmable tone durations from 4 ms to 1.02 s in 4 ms increments. Single-tone (pulse) and multitone (sequence) modes provide versatile playback options.
In sequence mode, the beeper can be programmed to play any number of tone pairs from 1 to 254 (2 to 508 tones)
or be programmed to play forever (until stopped by the user). Interrupts are available to indicate the start or end of
any beep, the end of a sequence, or that the sequence is nearing completion.
Cryptographic Accelerator (Crypto)
Crypto is a 32-bit APB DMA-capable peripheral. There are two 128-bit buffers provided for data I/O operations.
These buffers are read in or read out as 4 data accesses. Big-endian and little-endian data formats are supported, as
are the following modes:
• Electronic Code Book (ECB) mode - Advanced Encryption Standard (AES) mode
• Counter (CTR) mode
• Cipher Block Chaining (CBC) mode
• Message Authentication Code (MAC) mode
• Cipher Block Chaining-Message Authentication Code (CCM/CCM*) mode
• SHA-256 mode
• Protected key storage with key wrap-unwrap
• HMAC signature generation
CRC Accelerator
The CRC accelerator can be used to compute the CRC for a block of memory locations. The exact memory location
can be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a
checksum that can be used to compare it with an expected signature.
The following are the features of the CRC:
• Generate a CRC signature for a block of data
• Supports programmable polynomial length of up to 32 bits
• Operates on 32 bits of data at a time, and generates CRC for any data length
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Functional Description
• Supports MSB-first and LSB-first CRC implementations
• Various data mirroring capabilities
• Initial seed to be programmed by user
• DMA controller (memory to memory transfer) can be used for data transfer to offload the MCU
True Random Number Generator (TRNG)
The TRNG is used during operations where nondeterministic values are required. This may include generating challenges for secure communication or keys used for an encrypted communication channel. The generator can be run
multiple times to generate a sufficient number of bits for the strength of the intended operation. The TRNG can be
used to seed a deterministic random bit generator.
Serial Ports (SPORTs)
The synchronous serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices' audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a
clock, and a frame sync. The data lines can be programmed to either transmit or receive, and each data line has a
dedicated DMA channel. Serial port data can be automatically transferred to and from on-chip memory/external
memory via dedicated DMA channels. The frame sync and clock are shared. Some of the ADCs/DACs require two
control signals for their conversion process. To interface with such devices, an extra signal (SPT_CNV) is provided.
To use this signal, enable the timer enable mode. In this mode, a PWM timer inside the module is used to generate
the programmable SPT_CNV signal.
SPORT can operate in two modes:
• Standard DSP serial mode
• Timer enable mode
Serial Peripheral Interface (SPI) Ports
The ADuCM4050 MCU provides three SPIs. SPI is an industry standard, full-duplex, synchronous serial interface
that allows eight bits of data to be synchronously transmitted and simultaneously received. Each SPI incorporates
two DMA channels that interface with the DMA controller. One DMA channel is used for transmit and the other is
used for receive. The SPI on the MCU eases interfacing to external serial flash devices.
The SPI features available include the following:
• Serial clock phase mode and serial clock polarity mode
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation (Tx followed by Rx)
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ADuCM4050 Functional Description
• Flow control support
• Multiple CS line support
• CS software override support
• Support for 3-pin SPI
UART Ports
The ADuCM4050 MCU provides two full-duplex UART ports, which are fully compatible with PC-standard
UARTs.
The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMAsupported, asynchronous transfers of serial data. The UART port includes support for five to eight data bits, and
none, even, or odd parity. A frame is terminated by one, one and a half, or two stop bits.
Inter-Integrated Circuit (I2C)
The ADuCM4050 MCU provides an I2C interface. The I2C bus peripheral has two pins for data transfer. SCL is a
serial clock pin, and SDA is a serial data pin. The pins are configured in a Wired-AND format that allows arbitration in a multi-master system. A master device can be configured to generate the serial clock.
The frequency is programmed by the user in the serial clock divisor register. The master channel can be set to operate in fast mode (400 kHz) or standard mode (100 kHz).
Analog-to-Digital Converter (ADC) Subsystem
The ADuCM4050 MCU integrates a 12-bit SAR ADC with up to eight external channels. Conversions can be performed in single or auto cycle mode. In single mode, the ADC can be configured to convert on a particular channel
by selecting one of the channels. Auto cycle mode is provided to convert over multiple channels with reduced MCU
overhead of sampling and reading individual channel registers. The ADC can also be used for temperature sensing
and measuring battery voltage using dedicated channels. Temperature sensing and battery monitoring cannot be included in auto cycle mode.
Reference Designs
The Circuit from the Lab® provides information on the following:
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications
• Links for components in each chain to selection guides and application information
• Reference designs applying best practice design techniques
Development Tools
In addition to this Hardware reference document, the development support for the ADuCM4050 MCU includes
evaluation hardware and development software tools.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Peripheral Memory Map
Hardware
The ADZS-U4050LF-EZKIT® (for 64-lead LFCSP) and ADZS-U4050WL-EZKIT® (for 72-ball WLCSP) are
available to prototype sensor configuration with the ADuCM4050 MCU.
Software
The ADZS-U4050LF-EZKIT (for 64-lead LFCSP) and ADZS-U4050WL-EZKIT (for 72-ball WLCSP) include a
complete development and debug environment for the ADuCM4050 MCU. The Board Support Package (BSP) for
the ADuCM4050 MCU is provided for the IAR Embedded Workbench for ARM, Keil™, and CrossCore® Embedded Studio (CCES) environments.
The BSP also includes operating system (OS) aware drivers and example code for all the peripherals on the device.
ADuCM4050 Peripheral Memory Map
Table 1-3: Instance Summary
Name
Module
Address
TMR0
General-Purpose Timer
0x40000000
TMR1
General-Purpose Timer
0x40000400
TMR2
General-Purpose Timer
0x40000800
TMR3
RGB Timer
0x40000C00
RTC0
Real-Time Clock
0x40001000
RTC1
Real-Time Clock
0x40001400
SYS
System
0x40002000
WDT0
Watchdog Timer
0x40002C00
I2C0
I2C Interface
0x40003000
SPI0
SPI Interface
0x40004000
SPI1
SPI Interface
0x40004400
UART0
UART Interface
0x40005000
UART1
UART Interface
0x40005400
BEEP0
Beeper
0x40005C00
ADC0
ADC
0x40007000
DMA0
DMA
0x40010000
FLCC0
Flash/Cache Controller
0x40018000
GPIO0
GPIO
0x40020000
GPIO1
GPIO
0x40020040
GPIO2
GPIO
0x40020080
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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ADuCM4050 Peripheral Memory Map
Table 1-3: Instance Summary (Continued)
Name
Module
Address
SPI2
SPI
0x40024000
SPORT0
SPORT
0x40038000
CRC0
CRC Accelerator
0x40040000
RNG0
Random Number Generator
0x40040400
CRYPT0
Cryptographic Module
0x40044000
PMG0
PMG
0x4004C000
XINT0
External Interrupt Module
0x4004C080
CLKG0
Clocking Subsystem
0x4004C100
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Debug (DBG) and Trace Interfaces
2 Debug (DBG) and Trace Interfaces
The ADuCM4050 MCU supports the 2-wire serial wire debug (SWD) interface and trace feature via a single-wire
viewer port
Debug and Trace Features
The ADuCM4050 MCU supports trace feature for Cortex-M4F via single wire viewer port. It contains several system debug components that facilitate low-cost debug, trace and profiling, breakpoints, watch-points, and code
patching.
This product is intended to be a lightweight implementation of the ARM Cortex-M4F processor.
The following are the supported system debug and trace components:
• Flash Patch and Breakpoint (FPB) unit to implement two breakpoints. Flash patching is not supported.
• Data Watchpoint and Trace (DWT) unit to implement one watch-point, trigger resources, and system profiling. The DWT does not support data matching for watchpoint generation because it only has one comparator.
• Instruction Trace Macrocell (ITM) unit that supports printf style debugging to trace operating system and application events, and generates diagnostic system information. ITM generates trace packets that originate from
one of the four available sources.
• Trace Port Interface Unit (TPIU) that acts as a bridge between on-chip trace data from ITM to a data stream.
DBG Functional Description
This section provides information on the function of the SWD interface used by the ADuCM4050 MCU.
Serial Wire Interface
The serial wire interface consists of two pins:
• SWCLK: SWCLK is driven by the debug probe.
• SWDIO: SWDIO is a bidirectional signal which may be driven by the debug probe or target depending on the
protocol phase. A non-driving idle turnaround cycle is inserted on the bus whenever data direction changes to
avoid contention.
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2–1
DBG Operating Modes
SWD Pull-up
There must be a pull-up resistor on the SWDIO pin. The default state of this pin is pull-up.
The SWCLK pin must be pulled to a defined state (high or low). It is recommended to pull this pin low, which is
the default state of this pin.
SWD Timing
The target samples and drives SWDIO data on posedge SWCLK.
For optimum timing, the debug probe should drive SWDIO on negedge SWCLK and sample SWDIO on posedge
SWCLK.
Probe Driving
Target Sampling
Target Driving
Probe Sampling
SWCLK
SWCLK
SWDIO
SWDIO
Probe
Target
Drives
Samples
Neg Edge Pos Edge
Target
Drives
Pos Edge
Probe
Samples
Pos Edge
Target to Probe
Bus Turnaround
Probe to Target
Bus Turnaround
SWCLK
SWCLK
SWDIO
SWDIO
Probe
Target
Tristates
Drives
Neg Edge Pos Edge
delay
delay
Target
Tristates
Pos Edge
Probe
Drives
Neg Edge
Figure 2-1: SWD Timing
DBG Operating Modes
Serial Wire Protocol
The Serial Wire Protocol consists of three phases:
• Packet Request
• Acknowledge Response
• Data Transfer
The debug probe always sends the packet request.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DBG Operating Modes
The target always sends the acknowledge response.
The data transfer direction depends on the packet request and acknowledge response.
Packet Request
The packet request sent by the debug probe is 8 bits and is always followed by a turnaround bit.
Table 2-1: Packet Request
Bit
Description
Start
Always High: Logic 1
APnDP
Access Port: 1 or Data Port: 0
RnW
Read: 1 or Write: 0
A[2:3]
Address sent LSB first
Parity
Parity = APnDP + RnW + A[2] + A[3]
Stop
Always Low: Logic 0
Park
Always High: Logic 1
Turn
High Impedance / Non-Driving
Acknowledge Response
The acknowledge response sent by the target is 3 bits. If the target sends data for a read (RnW=1), it is followed
directly by the data transfer, there is no turnaround bit. If the debug probe sends the data transfer for a write
(RnW=0), acknowledge is followed by a turnaround bit.
Table 2-2: Acknowledge Response
Bit
Description
ACK[0:2]
Acknowledge Sent LSB first
100: Ok
010: Wait
001: Fault
Data Transfer
The data transfer phase consists of 32 bits of data sent LSB-first [0:31], followed by a single parity bit. If the number
of bits set in the data field is odd, the parity bit is set to 1.
For reads where data is sent by the target, the data transfer is followed by a turnaround bit. For writes where data is
sent by the debug probe, there is no turnaround bit.
The data transfer phase is omitted for Wait/Fault responses unless the CTRL/STAT ORUNDETECT bit is set. If
the ORUNDETECT bit is set, the data transfer phase is always sent and STICKYORUN is set if a Wait/Fault response occurs.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
2–3
Debug Access Port (DAP)
Protocol Format
The figure shows the protocol format.
Stop
Park
Turn
A[2:3]
Parity
Stop
Park
Turn
ACK[0:2]
A[2:3]
Parity
Stop
Park
Turn
ACK[0:2]
Parity
Turn
Parity
ACK[0:2]
Turn
RnW
A[2:3]
RnW
Start
APnDP
Write
WDATA[0:31]
Turn
RDATA[0.31]
Parity
Start
APnDP
Read
Turn
RnW
Start
APnDP
Wait/Fault
Figure 2-2: Protocol Format
Debug Access Port (DAP)
The DAP is split into two ports:
• Debug Port (DP)
• Access Port (AP)
There is a single Debug Port. There may be multiple Access Ports.
The Debug Port has a 2-bit (4-word) address space which is separate from the system memory address space. These
registers can only be accessed through the serial wire debug interface, they cannot be accessed by the CPU.
Each Access-Port has a separate 6-bit address space allowing up to 64-word registers per access port. This address
space is separate from the debug port and system CPU address spaces. It can only be accessed by the serial wire
interface through the debug port.
On this device, there is an Access Port. The Memory Access Port is selected by setting APSEL= 00.
Table 2-3: Access Ports
APSEL [7:0]
Access Port
00
Memory Access Port
2–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Debug Port
Debug Port
The Debug Port has four 32-bit read write register locations. These are used to identify and configure the interface
and to select and communicate with a particular Access Port.
Table 2-4: Debug Port Registers
Address [3:2]
Read
Write
DPBANKSEL
00
DPIDR
ABORT
X
01
CTRL/STAT
0x0
DLCR
0x1
TARGET ID
0x2
DLPIDR
0x3
EVENTSTAT
0x4
10
RESEND
SELECT
X
11
RDBUFF
TARGETSEL
X
ADuCM4050 SYS Register Descriptions
System Identification and Debug Enable (SYS) contains the following registers.
Table 2-5: ADuCM4050 SYS Register List
Name
Description
SYS_ADIID
ADI Identification
SYS_CHIPID
Chip Identifier
SYS_SWDEN
Serial Wire Debug Enable
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
2–5
ADuCM4050 SYS Register Descriptions
ADI Identification
ADI Cortex device identification.
15 14 13 12 11 10 9
0
1
0
0
0
0
0
8
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
0
0
VALUE (R)
Reads a fixed value of 0x4144 to indicate
to debuggers that they are connected
to an Analog Devices implemented
Cortex based part
Figure 2-3: SYS_ADIID Register Diagram
Table 2-6: SYS_ADIID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
2–6
Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an
Analog Devices implemented Cortex based part.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SYS Register Descriptions
Chip Identifier
Chip identification.
15 14 13 12 11 10 9
0
0
0
0
0
0
1
8
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
1
PARTID (R)
Part identifier
REV (R)
Silicon revision
Figure 2-4: SYS_CHIPID Register Diagram
Table 2-7: SYS_CHIPID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:4 PARTID
Part identifier.
(R/NW)
3:0 REV
(R/NW)
Silicon revision.
0 Silicon revision
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
2–7
ADuCM4050 SYS Register Descriptions
Serial Wire Debug Enable
The SYS_SWDEN register is used to enable the Serial Wire Debug (SWD) interface. This register is reset upon an
internal POR or external pin reset. It is not affected by a software reset.
15 14 13 12 11 10 9
0
1
1
1
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
1
0
0
1
0
VALUE (W)
To enable SWD interface
Figure 2-5: SYS_SWDEN Register Diagram
Table 2-8: SYS_SWDEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
2–8
To enable SWD interface.
Writing the SYS_SWDEN register with "en" (0x6E65) or "EN" (0x4E45) enables the
SWD interface. Writing the SYS_SWDEN register with "rp" (0x7072) or "RP"
(0x5052) disables the SWD interface. Writes of any other value are ignored. The
SYS_SWDEN register cannot be modified once written with "EN" or "RP". This register is reset by a POR or PIN reset, but not software or WDT reset.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Events (Interrupts and Exceptions)
3 Events (Interrupts and Exceptions)
The ADuCM4050 MCU supports a number of system exceptions and peripheral interrupts.
Events Features
The ADuCM4050 Events have the following features:
• 15 system exceptions with highest priority.
• 72 system interrupts with programmable priority.
• Four external interrupts which can be configured separately to wake up the core from low power modes.
Events Interrupts and Exceptions
Cortex Exceptions
Exceptions 1 to 15 are system exceptions.
Table 3-1: System Exceptions
Exception
Number
IRQ
Number
Exception Type
Priority
Description
1
−
Reset
-3 (highest)
Any reset
2
-14
NMI
-2
Non-maskable interrupt connected to a combination of (logical OR) of VREG under or VBAT (under 1.8 V)
3
-13
Hard fault
-1
All fault conditions, if the corresponding fault handler is not
enabled
4
-12
MemManagement fault
Programmable
Memory management fault; access to illegal locations
5
-11
Bus fault
Programmable
Prefetch fault, memory access fault, and other address/ memory related faults
6
-10
Usage fault
Programmable
Exceptions such as undefined instruction executed or illegal
state transition attempt
7 to 10
−
Reserved
Not applicable
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–1
Events Interrupts and Exceptions
Table 3-1: System Exceptions (Continued)
Exception
Number
IRQ
Number
Exception Type
Priority
Description
11
-5
SVCALL
Programmable
System service call with SVC instruction
12
-4
Debug monitor
Programmable
Debug monitor (breakpoint, watchpoint, or external debug
requests)
13
−
Reserved
Not applicable
14
-2
PENDSV
Programmable
Pendable request for system service
15
-1
SYSTICK
Programmable
System tick timer
Nested Vectored Interrupt Controller
Interrupts are controlled by the Nested Vectored Interrupt Controller (NVIC), and eight levels of priority are available. Only a limited number of interrupts can wake up the device from hibernate mode. When the device is woken
up from Flexi, hibernate, or shutdown modes, it always returns to active mode.
Table 3-2: Interrupt Sources
Exception
Number
IRQ
Vector
Number
Wake-up From
Flexi
Hibernate
Shutdown
16
0
Real Time Clock 1/Wakeup Timer/Hibernate
RTC/ LFXTAL Clock Failure
Yes
Yes
No
17
1
External Interrupt 0
Yes
Yes
Yes
18
2
External Interrupt 1
Yes
Yes
Yes
19
3
External Interrupt 2
Yes
Yes
Yes
20
4
External Interrupt 3/ UART0_RX_Wakeup
Yes
Yes
No
21
5
Watchdog Timer
Yes
No
No
22
6
VREG Over
Yes
No
No
23
7
Battery Voltage Range
Yes
Yes
No
24
8
Real Time Clock 0
Yes
Yes
Yes
25
9
GPIO IntA
Yes
No
No
26
10
GPIO IntB
Yes
No
No
27
11
General Purpose Timer 0
Yes
No
No
28
12
General Purpose Timer 1
Yes
No
No
29
13
Flash Controller
Yes
No
No
30
14
UART0
Yes
No
No
31
15
SPI0
Yes*
No
No
3–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Events Interrupts and Exceptions
Table 3-2: Interrupt Sources (Continued)
Exception
Number
IRQ
Vector
Number
Wake-up From
Flexi
Hibernate
Shutdown
32
16
SPI2
Yes*
No
No
33
17
I2C0 Slave
Yes*
No
No
34
18
I2C0 Master
Yes*
No
No
35
19
DMA Error
Yes
No
No
36
20
DMA Channel 0 Done
Yes
No
No
37
21
DMA Channel 1 Done
Yes
No
No
38
22
DMA Channel 2 Done
Yes
No
No
39
23
DMA Channel 3 Done
Yes
No
No
40
24
DMA Channel 4 Done
Yes
No
No
41
25
DMA Channel 5 Done
Yes
No
No
42
26
DMA Channel 6 Done
Yes
No
No
43
27
DMA Channel 7 Done
Yes
No
No
44
28
DMA Channel 8 Done
Yes
No
No
45
29
DMA Channel 9 Done
Yes
No
No
46
30
DMA Channel 10 Done
Yes
No
No
47
31
DMA Channel 11 Done
Yes
No
No
48
32
DMA Channel 12 Done
Yes
No
No
49
33
DMA Channel 13 Done
Yes
No
No
50
34
DMA Channel 14 Done
Yes
No
No
51
35
DMA Channel 15 Done
Yes
No
No
52
36
SPORT0A
Yes
No
No
53
37
SPORT0B
Yes
No
No
54
38
Crypto
Yes
No
No
55
39
DMA Channel 24 Done
Yes
No
No
56
40
General Purpose Timer 2
Yes
No
No
57
41
Crystal Oscillator
Yes
No
No
58
42
SPI1
Yes
No
No
59
43
PLL
Yes
No
No
60
44
Random Number Generator
Yes
No
No
61
45
Beeper
Yes
No
No
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–3
Events Interrupts and Exceptions
Table 3-2: Interrupt Sources (Continued)
Exception
Number
IRQ
Vector
Number
Wake-up From
Flexi
Hibernate
Shutdown
62
46
ADC
Yes
No
No
63-71
47-55
Reserved
-
-
-
72
56
DMA Channel 16 Done
Yes
No
No
73
57
DMA Channel 17 Done
Yes
No
No
74
58
DMA Channel 18 Done
Yes
No
No
75
59
DMA Channel 19 Done
Yes
No
No
76
60
DMA Channel 20 Done
Yes
No
No
77
61
DMA Channel 21 Done
Yes
No
No
78
62
DMA Channel 22 Done
Yes
No
No
79
63
DMA Channel 23 Done
Yes
No
No
80
64
Reserved
Yes
No
No
81
65
Reserved
Yes
No
No
82
66
UART1
Yes
No
No
83
67
DMA Channel 25 Done
Yes
No
No
84
68
DMA Channel 26 Done
Yes
No
No
85
69
Timer RGB
Yes
No
No
86
70
Reserved
Yes
No
No
87
71
Root Clock Failure
Yes
No
No
* Corresponding PCLK is required to generate the interrupt.
Internally, the highest user-programmable priority (0) is treated as the fourth priority, after a reset, NMI, and a hard
fault. Note that 0 is the default priority for all programmable priorities.
If the same priority level is assigned to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the MCU activates them. For example, if both SPI0 and SPI1 are Priority Level
1, SPI0 has higher priority.
For more information on the exceptions and interrupts, refer to Chapter 5 (Exceptions) and Chapter 8 (Nested Vectored Interrupt Controller) in the ARM Cortex-M4F Technical Reference Manual.
Handling Interrupt Registers
In the Interrupt Service Routine (ISR) for any interrupt source, the first action usually taken is clearing of the interrupt source. In case of write-1-to-clear interrupts, the interrupt status register should be written to clear the interrupt
source. Due to internal delays in the bus-matrix, this write may be delayed before it reaches the destination. Meanwhile, the ISR execution might have been completed and there is a possibility of mistaking the previous interrupt for
3–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Events Interrupts and Exceptions
a second one. Therefore, it is always recommended to ensure that the interrupt source has been cleared before exiting the ISR. This can be done by reading the interrupt status again at the end of the ISR.
External Interrupt Configuration
Four external interrupts are implemented, identified as SYS_WAKEx (x = 0, 1, 2, 3). These external interrupts can
be separately configured to detect any combination of the following types of events:
• Rising edge: The logic detects a transition from low to high and generates a pulse. Only one pulse is sent to the
Cortex-M4F per rising edge.
• Falling edge: The logic detects a transition from high to low and generates a pulse. Only one pulse is sent to the
Cortex-M4F per falling edge.
• Rising or falling edge: The logic detects a transition from low to high or high to low and generates a pulse.
Only one pulse is sent to the Cortex-M4F per edge.
• High level: The logic detects a high level. The appropriate interrupt is asserted and sent to the Cortex-M4F.
The interrupt line is held asserted until the external source deasserts. The high level needs to be maintained for
one core clock cycle minimum to be detected.
• Low level: The logic detects a low level. The appropriate interrupt is asserted and sent to the Cortex-M4F. The
interrupt line is held asserted until the external source deasserts. The low level needs to be maintained a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is always on and allows external interrupt to wake up the device when in
hibernate mode.
Apart from the four external interrupts, activity (any combination of events listed above) on the UART0_RX pin
can also be configured to wake up the device from Flexi or hibernate modes.
Interrupt No. 4 is assigned to both External Interrupt 3 and UART0_RX pin. Both pins can be configured to generate Interrupt No.4. The XINT_CFG0.UART_RX_EN bit must be set to enable UART0_RX pin based wake-up.
XINT_EXT_STAT.STAT_UART_RXWKUP bit is set whenever Interrupt No. 4 is asserted due to an event on the
UART0_RX pin.
NOTE: To use the external interrupt on the corresponding pads, the pads must be configured as GPIOs and the
corresponding GPIO input enable must be set high. For example, when using the pad P0_15 as external interrupt,
set GP0CON[31:30] to 2'b00 and GP0IE[15] to 1'b1.
ADuCM4050 XINT Register Descriptions
External interrupt configuration (XINT) contains the following registers.
Table 3-3: ADuCM4050 XINT Register List
Name
Description
XINT_CFG0
External Interrupt Configuration
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–5
ADuCM4050 XINT Register Descriptions
Table 3-3: ADuCM4050 XINT Register List (Continued)
Name
Description
XINT_CLR
External Interrupt Clear
XINT_EXT_STAT
External Wakeup Interrupt Status
XINT_NMICLR
Non-maskable Interrupt Clear
3–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 XINT Register Descriptions
External Interrupt Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IRQ3EN (R/W)
External Interrupt 3 Enable
IRQ0MDE (R/W)
External Interrupt 0 Mode Registers
IRQ3MDE (R/W)
External Interrupt 3 Mode Registers
IRQ0EN (R/W)
External Interrupt 0 Enable
IRQ2EN (R/W)
External Interrupt 2 Enable
IRQ1MDE (R/W)
External Interrupt 1 Mode Registers
IRQ2MDE (R/W)
External Interrupt 2 Mode Registers
IRQ1EN (R/W)
External Interrupt 1 Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
UART_RX_MDE (R/W)
External Interrupt Using UART_RX Wakeup
Mode Registers
0
0
0
0
0
0
1
0
0
0
0
0
UART_RX_EN (R/W)
External Interrupt Using UART_RX Enable
Bit
Figure 3-1: XINT_CFG0 Register Diagram
Table 3-4: XINT_CFG0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:21 UART_RX_MDE
(R/W)
External Interrupt Using UART_RX Wakeup Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
20 UART_RX_EN
(R/W)
External Interrupt Using UART_RX Enable Bit.
This bit enables 'UART_RX' pin to generate interrupt on interrupt (IRQ) number 4.
Refer to the Interrupt Sources table in Events (Interrupt and Exceptions) chapter.
Note: UART RX interrupt is ORed with external interrupt 3. Both interrupts can be
separately configured to generate interrupt on IRQ number 4. To distinguish the cause
of the interrupt on IRQ number 4, use the XINT_EXT_STAT register
0 UART_RX wakeup interrupt is disabled
1 UART_RX wakeup interrupt is enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–7
ADuCM4050 XINT Register Descriptions
Table 3-4: XINT_CFG0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
15 IRQ3EN
(R/W)
External Interrupt 3 Enable.
0 External Interrupt 3 disabled
1 External Interrupt 3 enabled
14:12 IRQ3MDE
(R/W)
External Interrupt 3 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
11 IRQ2EN
(R/W)
External Interrupt 2 Enable.
0 External Interrupt 2 disabled
1 External Interrupt 2 enabled
10:8 IRQ2MDE
(R/W)
External Interrupt 2 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
7 IRQ1EN
(R/W)
External Interrupt 1 Enable.
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled
6:4 IRQ1MDE
(R/W)
External Interrupt 1 Mode Registers.
0 Rising edge
1 Falling edge
3–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 XINT Register Descriptions
Table 3-4: XINT_CFG0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
3 IRQ0EN
(R/W)
External Interrupt 0 Enable.
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled
2:0 IRQ0MDE
(R/W)
External Interrupt 0 Mode Registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–9
ADuCM4050 XINT Register Descriptions
External Interrupt Clear
This register has W1C bits that are used to clear the corresponding EXT_STAT bits
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
UART_RX_CLR (R/W)
External Interrupt Clear for UART_RX
WAKEUP Interrupt
IRQ0 (R/W)
External Interrupt 0
IRQ1 (R/W)
External Interrupt 1
IRQ3 (R/W)
External Interrupt 3
IRQ2 (R/W)
External Interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-2: XINT_CLR Register Diagram
Table 3-5: XINT_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 UART_RX_CLR
(R/W)
3 IRQ3
(R/W)
2 IRQ2
(R/W)
1 IRQ1
(R/W)
0 IRQ0
(R/W)
3–10
External Interrupt Clear for UART_RX WAKEUP Interrupt.
Set to 1 to clear an interrupt STATUS flag. Cleared automatically by hardware.
External Interrupt 3.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 2.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 1.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External Interrupt 0.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 XINT Register Descriptions
External Wakeup Interrupt Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STAT_UART_RXWKUP (R)
Interrupt Status Bit for UART RX WAKEUP
Interrupt
STAT_EXTINT0 (R)
Interrupt Status Bit for External Interrupt 0
STAT_EXTINT1 (R)
Interrupt Status Bit for External Interrupt 1
STAT_EXTINT3 (R)
Interrupt Status Bit for External Interrupt 3
STAT_EXTINT2 (R)
Interrupt Status Bit for External Interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-3: XINT_EXT_STAT Register Diagram
Table 3-6: XINT_EXT_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 STAT_UART_RXWKUP
(R/NW)
3 STAT_EXTINT3
(R/NW)
2 STAT_EXTINT2
(R/NW)
1 STAT_EXTINT1
(R/NW)
Interrupt Status Bit for UART RX WAKEUP Interrupt.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - UART_RX Wakeup did not generate
the interrupt 1 - UART_RX Wakeup generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.UART_RX_CLR bit Note : Interrupt No. 4 is shared with External Interrupt 3, UART RX Wakeup.
Interrupt Status Bit for External Interrupt 3.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 3 did not generate
the interrupt 1 - External interrupt 3 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ3 bit
Interrupt Status Bit for External Interrupt 2.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 3 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 2 did not generate
the interrupt 1 - External interrupt 2 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ2 bit
Interrupt Status Bit for External Interrupt 1.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 2 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 1 did not generate
the interrupt 1 - External interrupt 1 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ1 bit
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–11
ADuCM4050 XINT Register Descriptions
Table 3-6: XINT_EXT_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 STAT_EXTINT0
(R/NW)
3–12
Interrupt Status Bit for External Interrupt 0.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 1 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 0 did not generate
the interrupt 1 - External interrupt 0 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ0 bit
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 XINT Register Descriptions
Non-maskable Interrupt Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLR (R/W)
NMI Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-4: XINT_NMICLR Register Diagram
Table 3-7: XINT_NMICLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 CLR
(R/W)
NMI Clear.
Set to 1 to clear an interrupt status flag when the NMI interrupt is set. Cleared automatically by hardware.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
3–13
Power Management (PMG)
4 Power Management (PMG)
This chapter provides an overview of the functional architecture and implementation of power management and
power modes used in the ADuCM4050 MCU.
Power Management Features
The features include:
• High efficiency buck converters to reduce power.
• Buck converter for active mode (External flying capacitors needed).
• Customized clock gating for active modes.
• Power gating to reduce leakage in sleep modes.
• Voltage monitoring.
• Flexible sleep modes with smart peripherals.
• Deep sleep modes with and without retention.
Power Management Functional Description
This section provides information on the power management function of the ADuCM4050 MCU.
The system has two voltage domains:
• VBAT: Input voltage with a range from 1.74 V - 3.6 V
• VREG: Internally generated voltage with a range of 1.2 V ± 10%
Power-up Sequence
The system powers up when the battery voltage is more than 1.6 V. The buck converter is disabled during the power
up sequence, so the system starts in LDO mode. The user can switch to Buck mode if required. The buck provides
the lowest dynamic power at the expense of five extra pins and two flying caps. User can tradeoff between external
components and active power. The buck can be enabled by writing to bit 0 of the PMG_CTL1 register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–1
Operating Modes
Operating Modes
The ADuCM4050 MCU supports the following power modes:
• Active Mode: Cortex-M4F executes from flash/SRAM.
• Flexi Mode: Cortex-M4F is disabled. User selects the peripherals to be enabled: DMA/SPI, DMA/I2C and so
on.
• Hibernate Mode: System power gated. 16 KB of SRAM is always retained. In addition to this, up to 108 KB
SRAM can be selected and retained.
• Shutdown Mode: Non-retain state. Pins retain values.
Active Mode
In this mode, the device is up and running. The Cortex-M4F executes instructions from flash and/or SRAM.
The system is not only clock gated using automatic clock gating techniques, but also clock gates can be selected
using the CLKG_CLK_CTL5 register. Most of the peripherals are automatically clock gated when disabled. The
clock runs only when the peripheral is enabled. Exceptions to this are I2C, UART, Timer_RGB, and general purpose
timer. These blocks must be manually clock gated using the CLKG_CLK_CTL5 register.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral. After the
clock stops, if the user/software accesses any register in that peripheral, the clock is auto enabled. Also, writing 0 to
the bit in the CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The CLKG_CLK_CTL5.PERCLKOFF bit can be used to disable all peripherals. This is useful when the CortexM4F processor is executing exclusively from SRAM or Flash, and no other peripherals are required.
When the CLKG_CLK_CTL5.PERCLKOFF bit is 1, the clock is gated. The clock is reenabled if the MCU or
DMA is accessing the register of any gated peripherals.
The chips power-up with the LDO. Buck can be enabled to save power consumption, by writing to the PMG_CTL1
register.
HPBUCK Load Mode Selection
Set the PMG_CTL1.HPBUCK_LD_MODE bit as per the HPBUCK Load Mode Selection table. Set this bit at the
start of the software execution flow.
Table 4-1: HPBUCK Load Mode Selection
System Clock Frequency
HPBUCK Load Mode
≤ 26 MHz
0
> 26 MHz
1
4–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Operating Modes
Flexi Mode
In this mode, the Cortex-M4F is always disabled. The core can be switched to this mode by setting the
PMG_PWRMOD.MODE bit to 0 and executing WFI instruction.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral.
If the user/software accesses any register in that peripheral after the clock stops, the clock is auto enabled. Also, writing 0 to the bit in CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The clock for all other blocks in the system runs if the peripheral is enabled.
This mode adds flexibility to the user to determine the blocks that are enabled while the Cortex is sleeping. For
example, the user can perform DMA transactions through SPI or I2C, or ADC conversions to DMA without MCU
interaction. This mode can be used to reduce active power when an activity is expected to complete (for example,
reading a certain number of bytes from a sensor, and so on) before the MCU can be woken up for processing the
data.
Low Power Mode in Flexi
It can be achieved by reducing the HFOSC frequency and by configuring appropriate bits.
This method requires the system clock (Root Clk) to source from the HFOSC (clock setting).
The low power mode entry sequence is as follows:
1. Program the CLKG_CLK_CTL2.HFOSCDIVCLKSEL bit to 5.
2. Enable the PMG_CTL1.HPBUCK_LOWPWR_MODE bit.
If PMG_CTL1.HPBUCK_LOWPWR_MODE bit is set, the load current is minimal.
Therefore, the following conditions must be met.
1. Select the HFOSC clock divider such that the divided HFOSC frequency is less than 1.2 MHz.
2. The following peripherals are only operational:
a. GPTs, where source for GPT blocks must be low frequency clocks
b. Beeper
c. GPIO
d. External interrupt source
This feature can be used in conjunction with fast wake-up from Flexi mode. In this case, the
CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit can be set to 1 to enable the fast wake-up. On wake up from Flexi
mode, the HFOSC divided clock automatically reverts to 26 MHz. To resume normal operation after wake up from
Flexi mode, clear the PMG_CTL1.HPBUCK_LOWPWR_MODE bit.
Wake-up time from Flexi to active is one clock cycle of the divided HFOSC clock.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–3
Operating Modes
Hibernate Mode
In this mode, the Cortex-M4F and all digital peripherals are off. The SRAM can retain up to 124 KB of total 128
KB. Important information must be kept on the lower SRAM before entering into hibernate mode.
User can select:
1. The SRAM to be retained using the control bits. These control bits can be used to retain three 32 KB regions
and one 12 KB region. This is in addition to the 16 KB of SRAM always retained in hibernate mode.
The SRAM retention control bits are as follows:
PMG_SRAMRET.RET1: Enable retention of Bank1 (12 KB)
PMG_SRAMRET.RET2: Enable retention of Bank3 and Bank4 (32 KB)
PMG_SRAMRET.RET3: Enable retention of Bank5 (32 KB)
PMG_SRAMRET.RET4: Enable retention of Bank6 and Bank7 (32 KB)
2. The RTC with a 32 kHz crystal or internal 32 kHz oscillator. The crystal provides a higher accuracy clock.
However, the power consumption is high.
3. Control battery monitoring in hibernate mode.
4. The regulated 1.2 V supply is always monitored to guarantee data is not corrupted by the supply going below
the minimum retention voltage. If the regulated supply falls below 1 V, the chip resets before any data is corrupted. Though the regulated supply is always monitored, there is an option to also monitor the battery in
hibernate mode. This is done by using the PMG_PWRMOD register.
Memory Configuration
While entering into hibernate mode, user can retain 124 KB out of 128 KB. This is controlled by the
PMG_SRAMRET register.
The lowest 16 KB is always retained in hibernate mode irrespective of the configuration set in the PMG_SRAMRET
register.
For more information, refer to SRAM Region.
SRAM Hibernate Load Mode
Select the PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE bit as per the following table.
Wait for 3 ms after setting this bit to 0, before entering into hibernate mode.
Table 4-2: SRAM Load Mode Selection
SRAM Size
SRAM Hibernate Load Mode
28 KB
1
48 KB
1
4–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Operating Modes
Table 4-2: SRAM Load Mode Selection (Continued)
SRAM Size
SRAM Hibernate Load Mode
60 KB
TBD
92 KB
TBD
124 KB
TBD
Hibernate Mode Transitions with PLL as Source
The PMU monitors power-down and power-up requests and enables seamless switching of the Root clock mux.
This ensures a safe hibernate mode entry and exit.
It performs the following operations during hibernate mode transitions.
Hibernate Mode Entry:
1. Switches Root clock mux to HFOSC, when power-down request is detected.
2. Disables the PLL.
3. Waits for PLL disable acknowledge.
4. Asserts the power-down acknowledge.
Hibernate Mode Exit:
1. Enables the PLL, when power-up request is detected.
If the PLL input is set to HFXTAL, PLL is enabled after HFXTAL lock is detected.
2. Waits for PLL lock.
3. Switches Root clock mux to PLL clock.
Shutdown Mode
This is the deepest sleep mode where all the digital and analog circuits are powered down except for a wake up controller and a fail safe. These circuits are powered from the battery voltage. The LDOs are off, so the 1.2 V region is
shutdown.
The state of the digital core is not retained and the SRAM memory content is not preserved. When the part wakes
up from shutdown mode, it follows the POR sequence and the code execution starts from the beginning. The user
can read the PMG_SHDN_STAT register to see the wake up source from this mode. There are four possible wake-up
sources:
• External interrupts, limited to three external interrupts to save power.
• External reset.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–5
Programming Sequence
• Battery falling below 1.6 V.
• RTC Timer (if the option is enabled). Only available with the crystal oscillator. The LF oscillator is off during
shutdown.
During this mode, the state of the pads and the wakeup interrupt configuration are preserved.
The configuration of the pads is preserved, but it is also locked after waking up from shutdown mode. The user
needs to unlock the state of the PADS by writing the value 0x58FA to register PMG_TST_CLR_LATCH_GPIOS.
It is recommended to perform the write inside the ISR routine.
The user can only go to shutdown with the HFOSC. It will not go to shutdown mode if running from PLL, external clock or HF XTAL. The user needs to switch to HFOSC before going to shutdown mode.
There is also a scratch pad available for the user during shutdown mode. The scratch pad consists of a 32-bit register.
The intention of the scratch pad is for the user to save some data on 3 V before all the information is lost in shutdown mode.
The user can write to the PMG_TST_SCRPAD_IMG register at any time. This is a read-write register. The information saved in this register is copied to an area in VBAT before going to shutdown mode. This information in VBAT
can be accessed through PMG_TST_SCRPAD_3V_RD register, which is a read-only register.
NOTE: Switch to HFOSC before going to shutdown mode if running from PLL, external clock, or HF XTAL.
For more information, refer to Configuring Shutdown Mode.
Programming Sequence
Configuring Hibernate Mode
This is the lowest power-down mode with state retention. Digital information and SRAM 0 are always retained, but
retaining SRAM 1, SRAM3 to SRAM7 is optional. Refer to SRAM Region.
It is also optional to monitor the battery in hibernate mode. The PMG_CTL1 register provides information about
the battery state. These bits also generate interrupts. Therefore, the battery is within the safe margin.
• When PMG_CTL1.HPBUCK_LOWPWR_MODE bit is low:
The battery is within safe margin voltages 3.6 V and 2.80 V. The battery voltage between 2.80 V and 2.19 V in
the BG1 region can also be considered a safe region, but is an indication that the battery is decaying. In the
BG2 region, the battery voltage below 2.19 V is an indication that the battery is dying.
• When PMG_CTL1.HPBUCK_LOWPWR_MODE bit is high:
The battery is within safe margin voltages 3.6 V and 2.93 V. The battery voltage between 2.93 V and 2.39 V in
the BG1 region can also be considered a safe region, but is an indication that the battery is decaying. In the
BG2 region, the battery voltage below 2.39 V is an indication that the battery is dying.
NOTE: If the battery voltage is in Safe or BG1 region, stop monitoring the battery when entering into hibernate
mode.
4–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Programming Sequence
The following steps describe the sequence to enter this mode:
1. Select PMG_PWRMOD_MODE = 2.
2. Select SLEEPDEEP bit in the Cortex-M4F.
3. Enable the desired wake-up interrupt.
4. If a wake-up from RTC1 is required, select the desired clock source (LFOSC or crystal).
5. If battery monitor is required, set the PMG_PWRMOD.MONVBATN bit to 0.
6. Execute the WFI/WFE instruction.
Now, the chip is in hibernate mode.
When a wake-up interrupt arrives, the part exits hibernate mode and serves the interrupt routine.
Configuring Shutdown Mode
This is the deepest power-down mode. State information is not retained in this mode, and the chip restarts from
reset after waking up.
The wake-up sources available are external reset, external interrupts limited only to three and RTC0 with the crystal
oscillator if the application needs periodic wake-up. The internal low frequency oscillator is disabled during this
mode. The only clock available in this mode is the low frequency crystal (optional).
The following steps describe the sequence to enter this mode:
1. Select PMG_PWRMOD_MODE = 3.
2. Set the SLEEPDEEP bit in the Cortex-M4F.
3. Enable the desired wake up interrupt.
4. If a wake up from RTC0 is required, enable LFXTAL.
5. Execute the WFI instruction.
Now, the chip is in shutdown mode.
NOTE: Switch to HFOSC before going to shutdown mode if running from PLL, external clock, or HFXTAL.
When a wake-up interrupt arrives, the device exits shutdown mode and the chip wakes up to a POR scenario.
The sequence is as follows:
1. Read the PMG_SHDN_STAT register.
2. Enable the interrupt routine that caused the wake-up event.
3. The chip jumps to the enabled ISR and served the interrupt routine.
NOTE: Write PMG_PWRMOD back to 0 in the ISR after waking up from shutdown mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–7
Wake-up Sequence
Wake-up Sequence
Wake-up is triggered by an interrupt or a reset. The sequence for the wake-up is different depending on the power
mode.
If the wake-up is triggered by a coming interrupt, then the system first executes the interrupt routine.
The wake-up sequence is different for shutdown mode. The information is not retained, and therefore the system
will always start from reset state after waking up. The interrupt triggering the wake-up sequence remains pending in
the Cortex-M4F until interrupt routine is enabled at the restart of the code. The status register can be read after
waking up from shutdown and the interrupt routine can be enabled.
For more information about interrupts and wake-up sources for power modes, refer to Table 3-2 Interrupt Sources.
Fast Wake-up from Shutdown Mode
In this mode, the device wakes up faster than the shutdown mode.
When this feature is enabled, the wake-up time is reduced to 1 ms (in shutdown mode, it is 75 ms).
The wake-up time is period between the wake-up interrupt assertion and start of execution of first instruction in the
user code.
This feature is enabled by setting bit 0 of the PMG_FAST_SHT_WAKEUP register. This register field content is
retained in all power modes. This register field is cleared when the PMG_RST_STAT.EXTRST or
PMG_RST_STAT.PORSRC bit is reset.
Monitor Voltage Control
Voltage supervisory circuits are enabled at all times to guarantee that the battery and the regulated supply are always
within operating levels. The circuit monitoring these supplies is called Power Management (PMG).
The following are the main features of PMG in active mode:
• Monitors battery voltage
• Generates an alarm to the MCU if battery supply is below 1.83 V
• Generates a reset to the chip if battery supply is below 1.6 V
• Monitors the state of the battery.
When the PMG_CTL1.HPBUCK_LOWPWR_MODE bit is low, it generates interrupts as per the following
voltage ranges:
Battery between 3.6 V - 2.8 V
Battery between 2.8 V - 2.19 V. Generates interrupt BR1
Battery between 2.19 V - 1.6 V. Generates interrupt BR2
4–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Monitor Voltage Control
When the PMG_CTL1.HPBUCK_LOWPWR_MODE bit is high, it generates interrupts as per the following voltage ranges:
Battery between 3.6 V - 2.93 V
Battery between 2.93 V - 2.39 V. Generates interrupt BR1
Battery between 2.39 V - 1.6 V. Generates interrupt BR2
• Monitors regulated supply
• Generates an interrupt if the regulated supply is above 1.32 V (over voltage)
• Generates an interrupt if the regulated supply is below 1.1 V (under voltage)
• Generates a reset if the regulated supply is below 1.08 V
The following are the main features of PMG in hibernate mode:
• Monitors battery voltage
• Generates an alarm to the MCU if supply is below 1.83 V (optional)
• Generates a reset to the chip if supply is below 1.6 V (optional)
• Monitors the state of the battery (optional)
When the PMG_CTL1.HPBUCK_LOWPWR_MODE bit is low, it generates interrupts as per the following
voltage ranges:
Battery between 3.6 V - 2.8 V
Battery between 2.8 V - 2.19 V. Generates interrupt BR1
Battery between 2.19 V - 1.6 V. Generates interrupt BR2
When the PMG_CTL1.HPBUCK_LOWPWR_MODE bit is high, it generates interrupts as per the following voltage ranges:
Battery between 3.6 V - 2.93 V
Battery between 2.93 V - 2.39 V. Generates interrupt BR1
Battery between 2.39 V - 1.6 V. Generates interrupt BR2
• Monitors regulated supply
• Generates a reset if the regulated supply is below 1.08 V
The battery and VREG supply monitors are shown below.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–9
ADuCM4050 PMG Register Descriptions
2.93/2.8 V 2.39/2.19 V 1.6 V
Figure 4-1: Battery Supply Monitor
VREG
1V
0V
1.1V
1.0V
1.0V 1.1V
VREG INT
VBAT RESET
Figure 4-2: VREG Supply Monitor
ADuCM4050 PMG Register Descriptions
Power Management Registers (PMG) contains the following registers.
Table 4-3: ADuCM4050 PMG Register List
Name
Description
PMG_CTL1
HPBUCK Control
PMG_IEN
Power Supply Monitor Interrupt Enable
PMG_TRIM
Trimming Bits
PMG_PSM_STAT
Power Supply Monitor Status
PMG_PWRKEY
Key Protection for PMG_PWRMOD and PMG_SRAMRET
4–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Table 4-3: ADuCM4050 PMG Register List (Continued)
Name
Description
PMG_PWRMOD
Power Mode Register
PMG_RST_STAT
Reset Status
PMG_SHDN_STAT
Shutdown Status Register
PMG_SRAMRET
Control for Retention SRAM in Hibernate Mode
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–11
ADuCM4050 PMG Register Descriptions
HPBUCK Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HPBUCK_LOWPWR_MODE (R/W)
HP Buck Low Power Mode
HPBUCKEN (R/W)
Enable HP Buck
HPBUCK_LD_MODE (R/W)
HP Buck Load Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
Figure 4-3: PMG_CTL1 Register Diagram
Table 4-4: PMG_CTL1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
2 HPBUCK_LOWPWR_M
(R/W) ODE
HP Buck Low Power Mode.
This bit can be used to choose Low power mode for the HPBUCK. The HPBUCK
Low Power mode can be selected, when the chip is in Flexi power mode and low power
modules such as Timer, Beeper only are enabled.
0 HPBUCK Low power mode is disabled
1 HPBUCK Low power mode is enabled
1 HPBUCK_LD_MODE
(R/W)
HP Buck Load Mode.
Used to choose the loading capability of the HPBUCK. User can select the HPBUCK
load mode for different use cases.
0 HPBUCK Low load mode is enabled This bit shall be
set to 0, if the maximum system clock (HCLK) frequency is 26 MHz.
1 HPBUCK High load mode is enabled This bit shall be
set to 1, if the system clock (HCLK) frequency is greater
than 26 MHz.
0 HPBUCKEN
Enable HP Buck.
(R/W)
4–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Power Supply Monitor Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IENBAT (R/W)
Interrupt Enable for VBAT Range
VBAT (R/W)
Enable Interrupt for VBAT
RANGEBAT (R/W)
Battery Monitor Range
VREGUNDR (R/W)
Enable Interrupt When VREG Under
Voltage (Below 1V)
VREGOVR (R/W)
Enable Interrupt When VREG Over
Voltage (Above 1.32V)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-4: PMG_IEN Register Diagram
Table 4-5: PMG_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10 IENBAT
(R/W)
Interrupt Enable for VBAT Range.
Set this bit if interrupt needs to be generated for appropriate PMG_IEN.RANGEBAT.
Configure the appropriate PMG_IEN.RANGEBAT for which interrupt to be generated and then set this bit. An Interrupt is generated if VBAT falls in the
PMG_IEN.RANGEBAT.
For example, if battery is good, to monitor the battery, configure in
PMG_PSM_STAT.RANGE2 or PMG_PSM_STAT.RANGE3, clear all
PMG_PSM_STAT flags and then enable this interrupt. Otherwise,
PMG_PSM_STAT.RANGE1 of battery will keep firing the interrupt.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–13
ADuCM4050 PMG Register Descriptions
Table 4-5: PMG_IEN Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 RANGEBAT
(R/W)
Battery Monitor Range.
Configure appropriate PMG_IEN.RANGEBAT for which interrupt has to be generated
0 Configure to generate interrupt if VBAT in Region1
VBAT Range1 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT > 2.80 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT > 2.93 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
1 Configure to generate interrupt if VBAT in Region2
VBAT Range2 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT is between 2.8 V and 2.19 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT is between 2.93 V and 2.39 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
2 Configure to generate interrupt if VBAT in Region3
VBAT Range3 varies with respect to the
PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT is between 2.19 V and 1.6 V, when
PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT is between 2.39 V and 1.6 V, when
PMG_CTL1.HPBUCK_LD_MODE=1.
3 NA
2 VREGOVR
Enable Interrupt When VREG Over Voltage (Above 1.32V).
(R/W)
1 VREGUNDR
(R/W)
0 VBAT
(R/W)
4–14
Enable Interrupt When VREG Under Voltage (Below 1V).
If enabled, the irq connects to NMI (non-maskable interrupt)
Enable Interrupt for VBAT.
If enabled, the irq connects to NMI (non-maskable interrupt). if enabled, it generates
an interrupt if VBAT < 1.83 V
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Trimming Bits
Trimming bits for power management.
15 14 13 12 11 10 9
1
0
1
0
0
0
1
8
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
hibernate_load_mode (R/W)
Hibernate Mode Load Mode Control
Figure 4-5: PMG_TRIM Register Diagram
Table 4-6: PMG_TRIM Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:29 HIBER(R/W) NATE_LOAD_MODE
Hibernate Mode Load Mode Control.
Configured in conjunction with the
PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE.
It is not recommended to change this bitfield dynamically between two hibernates as
this would result on a reconfiguration delay. If there is a low hibernate load (SRAM
retained is 60 KB or less), set PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE
and use 3b111 for this bit field.
If there is a high hibernate load (i.e. the SRAM retained is higher than 60 KB), reset
PMG_SRAMRET.HIBERNATE_SRAM_LOAD_MODE and use 3b000 for this bit
field.
0 High hibernate load
7 Low hibernate load
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–15
ADuCM4050 PMG Register Descriptions
Power Supply Monitor Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RORANGE3 (R)
VBAT Range3
VBATUNDR (R/W1C)
Status Bit Indicating an Alarm That
Battery is Below 1.8V
RORANGE2 (R)
VBAT Range2
VREGUNDR (R/W1C)
Status Bit for Alarm Indicating VREG
is Below 1V
RORANGE1 (R)
VBAT Range1
RANGE3 (R/W1C)
VBAT Range3
VREGOVR (R/W1C)
Status Bit for Alarm Indicating Over
Voltage for VREG
RANGE2 (R/W1C)
VBAT Range2
WICENACK (R)
WIC Enable Acknowledge from Cortex
RANGE1 (R/W1C)
VBAT Range1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-6: PMG_PSM_STAT Register Diagram
Table 4-7: PMG_PSM_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RORANGE3
(R/NW)
VBAT Range3.
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified
14 RORANGE2
(R/NW)
VBAT Range2.
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified
13 RORANGE1
(R/NW)
VBAT Range1.
Read-only status bit.
0 VBAT NOT in the range specified
1 VBAT in the range specified
4–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Table 4-7: PMG_PSM_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 RANGE3
(R/W1C)
VBAT Range3.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after '1' is written (to clear the flag) to the
flag, if VBAT falls in the range specified.
VBAT Range3 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range3 Values:
Between 2.19 V and 1.6 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
Between 2.39 V and 1.6 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified
9 RANGE2
(R/W1C)
VBAT Range2.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after 1 is written (to clear the flag) to the
flag, if VBAT falls in the range specified.
VBAT Range2 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range2 Values:
Between 2.80 V and 2.19 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
Between 2.93 V and 2.39 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified
8 RANGE1
(R/W1C)
VBAT Range1.
Indicates relevant VBAT range. Generates VBAT range interrupt if
PMG_IEN.IENBAT is set.
Note : The status bit will be set again even after '1' is written (to clear the flag) to the
flag, if VBAT falls in the range specified.
VBAT Range1 varies with respect to the PMG_CTL1.HPBUCK_LD_MODE bit.
VBAT Range1 Values:
VBAT > 2.80 V, when PMG_CTL1.HPBUCK_LD_MODE=0.
VBAT > 2.93 V, when PMG_CTL1.HPBUCK_LD_MODE=1.
0 VBAT NOT in the range specified
1 VBAT in the range specified
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–17
ADuCM4050 PMG Register Descriptions
Table 4-7: PMG_PSM_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
7 WICENACK
WIC Enable Acknowledge from Cortex.
(R/NW)
2 VREGOVR
(R/W1C)
Status Bit for Alarm Indicating Over Voltage for VREG.
Set if VREG (LDO out) > 1.32 V Generates an interrupt if PMG_IEN.VREGOVR is
set.
Note : The status bit will be set again even after '1' is written (to clear the flag) to the
flag, if VREG > 1.32 V.
1 VREGUNDR
(R/W1C)
Status Bit for Alarm Indicating VREG is Below 1V.
Generates an interrupt if PMG_IEN.VREGUNDR is set. This bit will be set if VREG <
1 V.
Note : The status bit will be set again even after '1' is written (to clear the flag) to the
flag, if VREG < 1 V.
0 VBATUNDR
(R/W1C)
Status Bit Indicating an Alarm That Battery is Below 1.8V.
Generates an interrupt if PMG_IEN.VBAT is set. This bit will be set if VBAT < 1.83
V.
Note : The status bit will be set again even after '1' is written (to clear the flag) to the
flag, if VBAT < 1.83 V.
4–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Key Protection for PMG_PWRMOD and PMG_SRAMRET
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Power Control Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-7: PMG_PWRKEY Register Diagram
Table 4-8: PMG_PWRKEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Power Control Key.
The PMG_PWRMOD and PMG_SRAMRET registers are key-protected. One write to the
key is necessary to change the value in the PMG_PWRMOD and PMG_SRAMRET registers. Key to be written is 0x4859. These registers should then be written. A write to
any other register on the APB bus before writing to PMG_PWRMOD or
PMG_SRAMRET will return the protection to the lock state.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–19
ADuCM4050 PMG Register Descriptions
Power Mode Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MONVBATN (R/W)
Monitor VBAT During Hibernate Mode
MODE (R/W)
Power Mode Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-8: PMG_PWRMOD Register Diagram
Table 4-9: PMG_PWRMOD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 MONVBATN
(R/W)
Monitor VBAT During Hibernate Mode.
Monitors VBAT by Default. VDD Monitoring cannot be disabled.
0 VBAT monitor enabled in PMG block
1 VBAT monitor disabled in PMG block
1:0 MODE
(R/W)
Power Mode Bits.
0 Flexi Mode
1 Reserved
2 Hibernate Mode
3 Shutdown Mode
4–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Reset Status
This register is recommended to be read at the beginning of the user-code to determine the cause of the reset. Default values of this register is unspecified as the cause of reset can be any source.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
0
0
0
X X X X X X
4
3
2
1
0
PORSRC (R)
Power on Reset Source
POR (R/W)
Power-on Reset
SWRST (R/W)
Software Reset
EXTRST (R/W)
External Reset
WDRST (R/W)
Watchdog Timeout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-9: PMG_RST_STAT Register Diagram
Table 4-10: PMG_RST_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 PORSRC
(R/NW)
Power on Reset Source.
This bit contains additional details after a power-on-reset occurs.
0 POR triggered because VBAT drops below Fail Safe
1 POR trigger because VBAT supply (VBAT < 1.7 V)
2 POR triggered because VDD supply (VDD < 1.08 V)
3 POR triggered because VREG drops below Fail Safe
3 SWRST
(R/W)
2 WDRST
(R/W)
1 EXTRST
(R/W)
Software Reset.
Software reset. Set automatically to 1 when the Cortex system reset is generated.
Cleared by writing 1 to any field of the PMG_RST_STAT register. This bit is also
cleared when power-on-reset is triggered
Watchdog Timeout.
Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to any
field of the PMG_RST_STAT register. This bit is also cleared when power-on-reset is
triggered
External Reset.
Set automatically to 1 when an external reset occurs. Cleared by writing 1 to any field
of the PMG_RST_STAT register. This bit is also cleared when power-on-reset is triggered
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–21
ADuCM4050 PMG Register Descriptions
Table 4-10: PMG_RST_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 POR
(R/W)
4–22
Power-on Reset.
Set automatically when a power-on reset occurs. Cleared by writing 1 to any field of
the PMG_RST_STAT register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG Register Descriptions
Shutdown Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTC (R)
Interrupt from RTC
EXTINT0 (R)
Interrupt from External Interrupt 0
EXTINT2 (R)
Interrupt from External Interrupt 2
EXTINT1 (R)
Interrupt from External Interrupt 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-10: PMG_SHDN_STAT Register Diagram
Table 4-11: PMG_SHDN_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 RTC
Interrupt from RTC.
(R/NW)
2 EXTINT2
Interrupt from External Interrupt 2.
(R/NW)
1 EXTINT1
Interrupt from External Interrupt 1.
(R/NW)
0 EXTINT0
Interrupt from External Interrupt 0.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–23
ADuCM4050 PMG Register Descriptions
Control for Retention SRAM in Hibernate Mode
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RET4 (R/W)
Enable Retention Bank 6 and Bank
7 (32 KB)
RET1 (R/W)
Enable Retention Bank 1 (12 KB)
RET2 (R/W)
Enable Retention Bank 3 and Bank
4 (32 KB)
RET3 (R/W)
Enable Retention Bank 5 (32 KB)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
HIBERNATE_SRAM_LOAD_MODE (R/W)
Hibernate Mode SRAM Load Mode Control
Figure 4-11: PMG_SRAMRET Register Diagram
Table 4-12: PMG_SRAMRET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23 HIBER(R/W) NATE_SRAM_LOAD_M
ODE
9 RET4
Hibernate Mode SRAM Load Mode Control.
Used to configure appropriate load current support in hibernate mode.
Enable Retention Bank 6 and Bank 7 (32 KB).
(R/W)
8 RET3
Enable Retention Bank 5 (32 KB).
(R/W)
1 RET2
Enable Retention Bank 3 and Bank 4 (32 KB).
(R/W)
0 RET1
Enable Retention Bank 1 (12 KB).
(R/W)
ADuCM4050 PMG_TST Register Descriptions
Power Management Registers (PMG_TST) contains the following registers.
Table 4-13: ADuCM4050 PMG_TST Register List
Name
Description
PMG_TST_CLR_LATCH_GPIOS
Clear GPIO After Shutdown Mode
PMG_TST_FAST_SHT_WAKEUP
Fast Shutdown Wake-up Enable
4–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG_TST Register Descriptions
Table 4-13: ADuCM4050 PMG_TST Register List (Continued)
Name
Description
PMG_TST_SCRPAD_3V_RD
Scratch Pad Saved in Battery Domain
PMG_TST_SCRPAD_IMG
Scratch Pad Image
PMG_TST_SRAM_CTL
Control for SRAM Parity and Instruction SRAM
PMG_TST_SRAM_INITSTAT
Initialization Status Register
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–25
ADuCM4050 PMG_TST Register Descriptions
Clear GPIO After Shutdown Mode
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Clear the Latches for GPIOs
Figure 4-12: PMG_TST_CLR_LATCH_GPIOS Register Diagram
Table 4-14: PMG_TST_CLR_LATCH_GPIOS Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
4–26
Clear the Latches for GPIOs.
when 0x58FA is written, the GPIO releases the latched values after shutdown mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG_TST Register Descriptions
Fast Shutdown Wake-up Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FAST_SHT_WAKEUP (R/W)
Enables Fast Shutdown Wake-up
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-13: PMG_TST_FAST_SHT_WAKEUP Register Diagram
Table 4-15: PMG_TST_FAST_SHT_WAKEUP Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 FAST_SHT_WAKEUP
(R/W)
Enables Fast Shutdown Wake-up.
If enabled, the shut down wake-up time will be reduced to 1 ms from the normal shutdown wake-up time of 75 ms.
This register field content will be retained in all Power modes. This register field will
be cleared to 0 only during External reset or Fail Safe VBAT POR reset. The default
value is 0.
0 Fast shutdown wakeup is disabled
1 Fast shutdown wakeup is enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–27
ADuCM4050 PMG_TST Register Descriptions
Scratch Pad Saved in Battery Domain
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DATA[15:0] (R)
Reading the Scratch Pad Stored in Shutdown
Mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA[31:16] (R)
Reading the Scratch Pad Stored in Shutdown
Mode
Figure 4-14: PMG_TST_SCRPAD_3V_RD Register Diagram
Table 4-16: PMG_TST_SCRPAD_3V_RD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 DATA
(R/NW)
4–28
Reading the Scratch Pad Stored in Shutdown Mode.
Read Only register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG_TST Register Descriptions
Scratch Pad Image
Useful in Shutdown mode. The GPIO configuration, OUT registers lose its contents when in shutdown mode. 32bit scratch register can be used to store the GPIO configuration. Note that the bits are not wide enough to store all
GPIO related configuration and output values. User has only few combination of shutdown port configurations.
Therefore, these combination can be remembered by storing an equivalent encoded data in the scratch 32-bit registers. User after reading back the SCRATCHPAD_3V_READ register (wake up from shutdown) can determine the
GPIO configuration. The content in the Scratch register is lost in shutdown mode if VBAT < 1.54 V
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DATA[15:0] (R/W)
Scratch Image
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA[31:16] (R/W)
Scratch Image
Figure 4-15: PMG_TST_SCRPAD_IMG Register Diagram
Table 4-17: PMG_TST_SCRPAD_IMG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 DATA
(R/W)
Scratch Image.
Value written to this register is saved in 3 V when going to shutdown mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–29
ADuCM4050 PMG_TST Register Descriptions
Control for SRAM Parity and Instruction SRAM
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ABTINIT (R/W)
Abort Current Initialization. Self-cleared
BNK1EN (R/W)
Enable Initialization
AUTOINIT (R/W)
Automatic Initialization on Wake up
from Hibernate Mode
BNK2EN (R/W)
Enable Initialization
BNK7EN (R/W)
Enable Initialization
STARTINIT (R/W)
Start Manual Initialization
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INSTREN (R/W)
Enables 32kB Instruction SRAM
PENBNK0 (R/W)
Enable Parity Check
PENBNK7 (R/W)
Enable Parity Check
PENBNK1 (R/W)
Enable Parity Check
PENBNK6 (R/W)
Enable Parity Check
PENBNK2 (R/W)
Enable Parity Check
PENBNK5 (R/W)
Enable Parity Check
PENBNK3 (R/W)
Enable Parity Check
PENBNK4 (R/W)
Enable Parity Check
Figure 4-16: PMG_TST_SRAM_CTL Register Diagram
Table 4-18: PMG_TST_SRAM_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 INSTREN
Enables 32kB Instruction SRAM.
(R/W)
23 PENBNK7
Enable Parity Check.
(R/W)
22 PENBNK6
Enable Parity Check.
(R/W)
21 PENBNK5
Enable Parity Check.
(R/W)
20 PENBNK4
Enable Parity Check.
(R/W)
19 PENBNK3
Enable Parity Check.
(R/W)
4–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG_TST Register Descriptions
Table 4-18: PMG_TST_SRAM_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
18 PENBNK2
Enable Parity Check.
(R/W)
17 PENBNK1
Enable Parity Check.
(R/W)
16 PENBNK0
Enable Parity Check.
(R/W)
15 ABTINIT
Abort Current Initialization. Self-cleared.
(R/W)
14 AUTOINIT
Automatic Initialization on Wake up from Hibernate Mode.
(R/W)
13 STARTINIT
(R/W)
7 BNK7EN
Start Manual Initialization.
Write one to trigger initialization. Self-cleared.
Enable Initialization.
(R/W)
2 BNK2EN
Enable Initialization.
(R/W)
1 BNK1EN
Enable Initialization.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–31
ADuCM4050 PMG_TST Register Descriptions
Initialization Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BNK7DONE (R)
Bank 7 Initialization Status
BNK0DONE (R)
Bank 0 Initialization Status
BNK6DONE (R)
Bank 6 Initialization Status
BNK1DONE (R)
Bank 1 Initialization Status
BNK5DONE (R)
Bank 5 Initialization Status
BNK2DONE (R)
Bank 2 Initialization Status
BNK4DONE (R)
Bank 4 Initialization Status
BNK3DONE (R)
Bank 3 Initialization Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-17: PMG_TST_SRAM_INITSTAT Register Diagram
Table 4-19: PMG_TST_SRAM_INITSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 BNK7DONE
(R/NW)
Bank 7 Initialization Status.
0 Bank 7 not initialized
1 Bank 7 initialized
6 BNK6DONE
(R/NW)
Bank 6 Initialization Status.
0 Bank 6 not initialized
1 Bank 6 initialized
5 BNK5DONE
(R/NW)
Bank 5 Initialization Status.
0 Bank 5 not initialized
1 Bank 5 initialized
4 BNK4DONE
(R/NW)
Bank 4 Initialization Status.
0 Bank 4 not initialized
1 Bank 4 initialized
3 BNK3DONE
(R/NW)
Bank 3 Initialization Status.
0 Bank 3 not initialized
1 Bank 3 initialized
4–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 PMG_TST Register Descriptions
Table 4-19: PMG_TST_SRAM_INITSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 BNK2DONE
(R/NW)
Bank 2 Initialization Status.
0 Bank 2 not initialized
1 Bank 2 initialized
1 BNK1DONE
(R/NW)
Bank 1 Initialization Status.
0 Bank 1 not initialized
1 Bank 1 initialized
0 BNK0DONE
(R/NW)
Bank 0 Initialization Status.
0 Bank 0 not initialized
1 Bank 0 initialized
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
4–33
General-Purpose I/O (GPIO)
5 General-Purpose I/O (GPIO)
This section describes the general-purpose input/output (GPIO) functionality.
GPIO Features
The GPIO ports include the following features:
• Input and output modes of GPIO operation.
• Port multiplexing controlled by individual pin-per-pin base.
• All port pins provide interrupt functionality.
• Programmable pull-up/pull-down drive compatibility.
GPIO Functional Description
The ADuCM4050 MCU controls the GPIO pins through a set of Memory Mapped Registers (MMR). These
MMRs are implemented as part of an APB32 peripheral. Multiple functions are mapped on most of the GPIO pins.
These functions can be selected by appropriately configuring the corresponding ports of the GPIO_CFG registers.
The ADuCM4050 MCU has up to 51 GPIO bidirectional pins. Most of the GPIO pins have multiple functions,
configurable by user code, when multiplexed at the top-level. The GPIOs are grouped into four ports: P0, P1, P2,
and P3. P0, P1, and P2 contain 16 GPIOs. P3 contains 4 GPIOs.
GPIO Block Diagram
The figures show the block diagrams of the GPIO pins with pull-up and pull-down resistors.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–1
GPIO Functional Description
Output Enable
IOVDD
Pull-up Enable
GPIO_PE
GPIO_OEN
Output Data
GPIO_OUT, GPIO_SET,
GPIO_CLR, GPIO_TGL
GPIO
Input Data
GPIO_IEN
Input Data
GPIO_IN
Figure 5-1: GPIO Pins with Pull-up Resistor
Output Enable
GPIO_OEN
Output Data
GPIO
GPIO_OUT, GPIO_SET,
GPIO_CLR, GPIO_TGL
Pull-down Enable
GPIO_PE
Input Data
GPIO_IEN
Input Data
IOGND
GPIO_IN
Figure 5-2: GPIO Pins with Pull-down Resistor
In applications where the input is not controlled by the system, the input voltage may exceed the maximum voltage
rating of the device. When the external overvoltage conditions are applied to the ADuCM4050 MCU, ESD diodes
must be used between the amplifier and electrical over stress.
All GPIOs have a diode clamping circuit to protect against overvoltage and ESD.
The following figure shows the equivalent circuit of diode clamping.
5–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
GPIO Functional Description
PAD
Figure 5-3: Diode Clamping Circuit
ADuCM4050 GPIO Multiplexing
The following tables show the pin functions that are multiplexed on the general-purpose I/O pins of the package
Table 5-1: Signal Muxing - Port 0
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
P0_00
P0_00
SPI0_CLK
SPT0_BCLK
P0_01
P0_01
SPI0_MOSI
SPT0_BFS
P0_02
P0_02
SPI0_MISO
SPT0_BD0
P0_03
P0_03
SPI0_CS0
SPT0_BCNV
P0_04
P0_04
I2C0_SCL
P0_05
P0_05
I2C0_SDA
P0_06
SWD0_CLK
P0_06
P0_07
SWD0_DATA
P0_07
P0_08
P0_08
BEEP0_TONE
P0_09
P0_09
BEEP0_TONE
P0_10
P0_10
UART0_TX
P0_11
P0_11
UART0_RX
P0_12
P0_12
SPT0_AD0
P0_13/SYS_WAKE2
P0_13
P0_14
P0_14
P0_15/SYS_WAKE0
P0_15
Multiplexed
Function 3
SPI2_RDY
SPI2_CS1
UART_SOUT_
EN
TMR0_OUT
SPI1_RDY
Multiplexed
Function 1
Multiplexed
Function 2
Table 5-2: Signal Muxing - Port 1
Signal Name
Multiplexed
Function 0
P1_00/SYS_WAKE1
P1_00
P1_01
SYS_BMODE0
P1_01
P1_02
P1_02
SPI2_CLK
Multiplexed
Function 3
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–3
GPIO Functional Description
Table 5-2: Signal Muxing - Port 1 (Continued)
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
P1_03
P1_03
SPI2_MOSI
P1_04
P1_04
SPI2_MISO
P1_05
P1_05
SPI2_CS0
P1_06
P1_06
SPI1_CLK
RGB_TMR0_1
P1_07
P1_07
SPI1_MOSI
RGB_TMR0_2
P1_08
P1_08
SPI1_MISO
RGB_TMR0_3
P1_09
P1_09
SPI1_CS0
SWV
P1_10
P1_10
SPI0_CS1
P1_11
P1_11
TMR1_OUT
P1_12
P1_12
RTC1_SS2
P1_13
P1_13
P1_14
P1_14
P1_15
P1_15
SYS_CLKIN
Multiplexed
Function 3
SPI1_CS3
TMR2_OUT
SPI0_RDY
SPT0_ACLK
UART1_TX
Table 5-3: Signal Muxing - Port 2
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
P2_00
P2_00
SPT0_AFS
UART1_RX
P2_01/SYS_WAKE3
P2_01
P2_02
P2_02
SPT0_ACNV
P2_03
P2_03
ADC0_VIN0
P2_04
P2_04
ADC0_VIN1
P2_05
P2_05
ADC0_VIN2
P2_06
P2_06
ADC0_VIN3
P2_07
P2_07
ADC0_VIN4
SPI2_CS3
P2_08
P2_08
ADC0_VIN5
SPI0_CS2
P2_09
P2_09
ADC0_VIN6
SPI0_CS3
P2_10
P2_10
ADC0_VIN7
SPI2_CS2
P2_11
P2_11
SPI1_CS1
SYS_CLKOUT
5–4
Multiplexed
Function 3
TMR2_OUT
SPI1_CS2
RTC1_SS3
RTC1_SS1
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
GPIO Operating Modes
GPIO Operating Modes
IO Pull-Up or Pull-Down Enable
All GPIO pins can be grouped into two categories: GPIO pins with a pull-up resistor and GPIO pins with a pulldown resistor. Each GPIO port has a corresponding GPIO_PE register. Using the GPIO_PE registers, it is possible
to enable/disable pull-up/pull-down registers on the pins when they are configured as inputs.
IO Data In
When configured as an input using the GPIO_IEN register, the GPIO input levels are available in the GPIO_IN
register.
IO Data Out
When the GPIOs are configured as outputs using the GPIO_OEN register, the values in the GPIO_OUT register are
reflected on the GPIOs.
Bit Set
Each GPIO port has a corresponding bit set register, GPIO_SET. Use the bit set register to set one or more GPIO
data outs without affecting others within the port. Only the GPIO corresponding with the write data bit equal to
one is set, the remaining GPIOs are unaffected.
Bit Clear
Each GPIO port has a corresponding bit clear register, GPIO_CLR. Use the bit clear register to clear one or more
GPIO data outs without affecting others within the port. Only the GPIO corresponding with the write data bit
equal to one is cleared, the remaining GPIOs are unaffected.
Bit Toggle
Each GPIO port has a corresponding bit toggle register, GPIO_TGL. Using the bit toggle register, it is possible to
invert one or more GPIO data outs without affecting others within the port. Only the GPIO corresponding with
the write data bit equal to one is toggled, the remaining GPIOs are unaffected.
IO Data Output Enable
Each GPIO port has a data output enable (GPIO_OEN) register, by which the data output path is enabled. When
the data output enable register bits are set, the values in GPIO_OUT are reflected on the corresponding GPIO pins.
Interrupts
Each GPIO pin can be associated with an interrupt. Interrupts can be independently enabled for each GPIO pin
and are always edge detect; only one interrupt will be generated with each GPIO pin transition. The polarity of the
detected edge can be positive (low-to-high) or negative (high-to-low). Each GPIO interrupt event can be mapped to
one of two interrupts (INTA or INTB). This allows the system more flexibility in terms of how GPIO interrupts are
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–5
GPIO Operating Modes
grouped for servicing, and how interrupt priorities are set. The interrupt status of each GPIO pin can be determined
and cleared by accessing the associated status registers.
Interrupt Polarity
The polarity of the interrupt determines if the interrupt is accepted on the rising or the falling edge. Each GPIO
port has a corresponding interrupt register (GPIO_POL) by which the interrupt polarity of each pin is configured.
When set to 0, an interrupt event will be latched on a high-to-low transition on the corresponding pin. When set to
1, an interrupt event will be latched on a low-to-high transition on the corresponding pin.
Interrupt A Enable
Each GPIO port has an Interrupt Enable A register (GPIO_IENA) that is enabled or masked for each pin in the
port. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt A) or be
masked. In either case, the occurrence of the event will be captured in the corresponding bit of the GPIO_INT
status register. When set to 0, Interrupt A is not enabled (masked). No interrupts to the core will be generated by
this GPIO pin. When set to 1, Interrupt A is enabled. On a valid detected edge, an interrupt source to the core will
be generated.
Interrupt B Enable
Each GPIO port has a corresponding Interrupt Enable B (GPIO_IENB) register that is enabled or masked for each
pin in the port. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt B) or be masked. In either case, the occurrence of the event will be captured in the corresponding bit of the
GPIO_INT status register. When set to 0, Interrupt B is not enabled (masked). No interrupts to the core will be
generated by this GPIO pin. When set to 1, Interrupt B is enabled. On a valid detected edge, an interrupt source to
the core will be generated.
Interrupt Status
Each GPIO port has an interrupt status register (GPIO_INT) that captures the interrupts occurring on its pins.
These register bits indicate that the appropriately configured rising or falling edge has been detected on the corresponding GPIO pin.
Once an event is detected, GPIO_INT will remain set until cleared; this is true even if the GPIO pin transitions
back to a nonactive state. Out of reset, pull ups combined with falling edge detect can result in the GPIO_INT
status being cleared; however, this may not be the case based on pin activity. It is therefore recommended that the
status of GPIO_INT be checked before enabling interrupts (GPIO_IENA and GPIO_IENB) initially as well as
anytime GPIO pins are configured.
Interrupt bits are cleared by writing a 1 to the appropriate bit location. Writing a 0 has no effect. If interrupts are
enabled to the core (GPIO_IENA, GPIO_IENB), an interrupt (GPIO_INT) value of 1 will result in an interrupt
to the core. This bit should be cleared during servicing of the interrupt. When read as 0, a rising or falling edge was
not detected on the corresponding GPIO pin because this bit was last cleared. When read as 1, a rising or falling
edge (GPIO_POL selectable) was detected on the corresponding GPIO pin. This bit can be software cleared by
5–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
GPIO Programming Model
writing a 1 to this bit location. This bit can only be subsequently set again after the pin returns to its nonasserted
state and then returns to an asserted state.
GPIO Programming Model
Programming Sequence for output functionality:
1. Program the GPIO_OEN register for the appropriate GPIO pins.
2. The data on the selected pin is driven high or low by writing to the GPIO_SET/GPIO_CLR/GPIO_TGL
registers.
Programming Sequence for input functionality:
1. Program the GPIO_IEN register for the appropriate port pins.
2. The data latched by the input port pin is registered in the GPIO_IN register. Interrupts can be enabled by
writing to the GPIO_IENA or GPIO_IENB register.
ADuCM4050 GPIO Register Descriptions
General-Purpose Input/Output (GPIO) contains the following registers.
Table 5-4: ADuCM4050 GPIO Register List
Name
Description
GPIO_CFG
Port Configuration
GPIO_CLR
Port Data Out Clear
GPIO_DS
Port Drive Strength Select
GPIO_IEN
Port Input Path Enable
GPIO_IENA
Port Interrupt A Enable
GPIO_IENB
Port Interrupt B Enable
GPIO_IN
Port Registered Data Input
GPIO_INT
Port Interrupt Status
GPIO_OEN
Port Output Enable
GPIO_OUT
Port Data Output
GPIO_PE
Port Output Pull-up/Pull-down Enable
GPIO_POL
Port Interrupt Polarity
GPIO_SET
Port Data Out Set
GPIO_TGL
Port Pin Toggle
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–7
ADuCM4050 GPIO Register Descriptions
Port Configuration
The GPIO_CFG register is reserved for top-level pin muxing for the GPIO block.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PIN07 (R/W)
Pin 7 configuration bits
PIN00 (R/W)
Pin 0 configuration bits
PIN06 (R/W)
Pin 6 configuration bits
PIN01 (R/W)
Pin 1 configuration bits
PIN05 (R/W)
Pin 5 configuration bits
PIN02 (R/W)
Pin 2 configuration bits
PIN04 (R/W)
Pin 4 configuration bits
PIN03 (R/W)
Pin 3 configuration bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PIN15 (R/W)
Pin 15 configuration bits
PIN08 (R/W)
Pin 8 configuration bits
PIN14 (R/W)
Pin 14 configuration bits
PIN09 (R/W)
Pin 9 configuration bits
PIN13 (R/W)
Pin 13 configuration bits
PIN10 (R/W)
Pin 10 configuration bits
PIN12 (R/W)
Pin 12 configuration bits
PIN11 (R/W)
Pin 11 configuration bits
Figure 5-4: GPIO_CFG Register Diagram
Table 5-5: GPIO_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:30 PIN15
Pin 15 configuration bits.
(R/W)
29:28 PIN14
Pin 14 configuration bits.
(R/W)
27:26 PIN13
Pin 13 configuration bits.
(R/W)
25:24 PIN12
Pin 12 configuration bits.
(R/W)
23:22 PIN11
Pin 11 configuration bits.
(R/W)
5–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Table 5-5: GPIO_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
21:20 PIN10
Pin 10 configuration bits.
(R/W)
19:18 PIN09
Pin 9 configuration bits.
(R/W)
17:16 PIN08
Pin 8 configuration bits.
(R/W)
15:14 PIN07
Pin 7 configuration bits.
(R/W)
13:12 PIN06
Pin 6 configuration bits.
(R/W)
11:10 PIN05
Pin 5 configuration bits.
(R/W)
9:8 PIN04
Pin 4 configuration bits.
(R/W)
7:6 PIN03
Pin 3 configuration bits.
(R/W)
5:4 PIN02
Pin 2 configuration bits.
(R/W)
3:2 PIN01
Pin 1 configuration bits.
(R/W)
1:0 PIN00
Pin 0 configuration bits.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–9
ADuCM4050 GPIO Register Descriptions
Port Data Out Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Set the output low for the port pin
Figure 5-5: GPIO_CLR Register Diagram
Table 5-6: GPIO_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
5–10
Set the output low for the port pin.
Each bit is set to drive the corresponding GPIO pin low. Clearing this bit has no effect.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Drive Strength Select
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PIN15 (R/W)
Drive Strength Pin 15
PIN00 (R/W)
Drive Strength Pin 00
PIN14 (R/W)
Drive Strength Pin 14
PIN01 (R/W)
Drive Strength Pin 01
PIN13 (R/W)
Drive Strength Pin 13
PIN02 (R/W)
Drive Strength Pin 02
PIN12 (R/W)
Drive Strength Pin 12
PIN03 (R/W)
Drive Strength Pin 03
PIN11 (R/W)
Drive Strength Pin 11
PIN04 (R/W)
Drive Strength Pin 04
PIN10 (R/W)
Drive Strength Pin 10
PIN05 (R/W)
Drive Strength Pin 05
PIN09 (R/W)
Drive Strength Pin 09
PIN06 (R/W)
Drive Strength Pin 06
PIN08 (R/W)
Drive Strength Pin 08
PIN07 (R/W)
Drive Strength Pin 07
Figure 5-6: GPIO_DS Register Diagram
Table 5-7: GPIO_DS Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 PIN15
Drive Strength Pin 15.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
14 PIN14
Drive Strength Pin 14.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
13 PIN13
Drive Strength Pin 13.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
12 PIN12
(R/W)
Drive Strength Pin 12.
0 Single Drive Strength
1 Double Drive Strength
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–11
ADuCM4050 GPIO Register Descriptions
Table 5-7: GPIO_DS Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 PIN11
Drive Strength Pin 11.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
10 PIN10
Drive Strength Pin 10.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
9 PIN09
Drive Strength Pin 09.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
8 PIN08
Drive Strength Pin 08.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
7 PIN07
Drive Strength Pin 07.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
6 PIN06
Drive Strength Pin 06.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
5 PIN05
Drive Strength Pin 05.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
4 PIN04
Drive Strength Pin 04.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
3 PIN03
Drive Strength Pin 03.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
2 PIN02
(R/W)
Drive Strength Pin 02.
0 Single Drive Strength
1 Double Drive Strength
5–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Table 5-7: GPIO_DS Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 PIN01
Drive Strength Pin 01.
(R/W)
0 Single Drive Strength
1 Double Drive Strength
0 PIN00
(R/W)
Drive Strength Pin 00.
0 Single Drive Strength
1 Double Drive Strength
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–13
ADuCM4050 GPIO Register Descriptions
Port Input Path Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Input path enable
Figure 5-7: GPIO_IEN Register Diagram
Table 5-8: GPIO_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
5–14
Input path enable.
Each bit is set to enable the input path and cleared to disable the input path for the
GPIO pin.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Interrupt A Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt A enable
Figure 5-8: GPIO_IENA Register Diagram
Table 5-9: GPIO_IENA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Interrupt A enable.
Determines if a latched edge event should be allowed to interrupt the core (INTERRUPT A) or be masked. In either case the occurrence of the event will be captured in
the GPIO_INT status register. When cleared, Interrupt A is not enabled (masked).
When set Interrupt A is enabled.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–15
ADuCM4050 GPIO Register Descriptions
Port Interrupt B Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt B enable
Figure 5-9: GPIO_IENB Register Diagram
Table 5-10: GPIO_IENB Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
5–16
Interrupt B enable.
Determines if a latched edge event must be allowed to interrupt the core (INTERRUPT B) or be masked. In either case, the occurrence of the event is captured in the
GPIO_INT status register. When set to 0, Interrupt B is not enabled (masked). When
set to 1, Interrupt A is enabled.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Registered Data Input
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE (R)
Registered data input
Figure 5-10: GPIO_IN Register Diagram
Table 5-11: GPIO_IN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
Registered data input.
Each bit reflects the state of the GPIO pin if the corresponding input buffer is enabled.
If the pin input buffer is disabled, the value seen is zero.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–17
ADuCM4050 GPIO Register Descriptions
Port Interrupt Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W1C)
Interrupt Status
Figure 5-11: GPIO_INT Register Diagram
Table 5-12: GPIO_INT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W1C)
5–18
Interrupt Status.
Indicates that the appropriately configured rising or falling edge has been detected on
the corresponding GPIO pin. Once an event is detected, GPIO_INT.VALUE bit remains set until cleared. This is true even if the GPIO pin transitions back to a non
active state. GPIO_INT.VALUE bits are cleared by writing 1 to the appropriate bit
location. Writing 0 has no effect.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Output Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Pin Output Drive enable
Figure 5-12: GPIO_OEN Register Diagram
Table 5-13: GPIO_OEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Pin Output Drive enable.
Each bit is set to enable the output for that particular pin. It is cleared to disable the
output for each pin.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–19
ADuCM4050 GPIO Register Descriptions
Port Data Output
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Data out
Figure 5-13: GPIO_OUT Register Diagram
Table 5-14: GPIO_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
5–20
Data out.
Set by user code to drive the corresponding GPIO high. Cleared by user to drive the
corresponding GPIO low.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Output Pull-up/Pull-down Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
0
VALUE (R/W)
Pin Pull enable
Figure 5-14: GPIO_PE Register Diagram
Table 5-15: GPIO_PE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Pin Pull enable.
Each bit is set to enable the pull-up/pull-down for that particular pin. It is cleared to
disable the pull-up/pull-down for each pin. The values shown in the Register Diagram
are for GPIO Port 0.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–21
ADuCM4050 GPIO Register Descriptions
Port Interrupt Polarity
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt polarity
Figure 5-15: GPIO_POL Register Diagram
Table 5-16: GPIO_POL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
5–22
Interrupt polarity.
Determines if the interrupts are generated on the rising or falling edge of the corresponding GPIO pin. When cleared, an interrupt event is latched on a high-to-low
transition. When set, an interrupt event is latched on a low-to-high transition.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 GPIO Register Descriptions
Port Data Out Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Set the output HIGH for the pin
Figure 5-16: GPIO_SET Register Diagram
Table 5-17: GPIO_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Set the output HIGH for the pin.
Set by user code to drive the corresponding GPIO high. Clearing this bit has no effect.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
5–23
ADuCM4050 GPIO Register Descriptions
Port Pin Toggle
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Toggle the output of the port pin
Figure 5-17: GPIO_TGL Register Diagram
Table 5-18: GPIO_TGL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
5–24
Toggle the output of the port pin.
Each bit is set to invert the corresponding GPIO pin. Clearing this bit has not effect.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
System Clocks
6 System Clocks
The ADuCM4050 MCU is integrated with two on-chip oscillators and the circuitry for two external crystals.
System Clock Features
The System Clock features include the following:
• LFOSC is a 32 kHz internal oscillator.
• HFOSC is a 26 MHz internal oscillator.
• LFXTAL is a 32 kHz external crystal oscillator.
• HFXTAL is a 16 / 26 MHz external crystal oscillator.
• External clock input through SYS_CLKIN.
• An on-chip phase-locked loop (PLL) is available, system PLL (SPLL). PLL can use HFOSC, HFXTAL, or
SYS_CLKIN as an input clock.
• The high frequency oscillators (HFOSC and HFXTAL), SYS_CLKIN along with the output of the SPLL can
be used to generate the root clock.
• The 32 kHz clock (LF_CLK) is generated from either LFXTAL or LFOSC to drive certain blocks.
• The general purpose timers have their own multiplexers to select their clock source.
• The RTC1 works from LFXTAL or LFOSC in hibernate and active modes. The RTC0 always works from
LFXTAL in shutdown/hibernate/active modes.
• Watchdog timer always works on LFOSC oscillator. It cannot be run using LFXTAL to avoid reliability issues.
It does not work in hibernate or shutdown modes.
• LFXTAL clock failure detection in all modes other than shutdown mode.
• Automatic switching of LFMUX clock to LFOSC during LFXTAL clock failure.
• Root clock failure detection in active mode.
• Automatic switching of Root clock to HFOSC clock during root clock failure.
• The Root clock is divided into several internal clocks.
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System Clock Functional Description
• RCLK clocks the reference timer (counter) in flash controller. This is used to time flash erase, write operations.
By default, it is connected to 13 MHz clock source. This is generated by ½ divider connected to HFOSC (26
MHz). So, the default values of flash timer registers correspond to 13 MHz clock.
If CLKG_CLK_CTL0.RCLKMUX = 11 (HFXTAL = 16 MHz), the ½ DIV (divider) is automatically bypassed
and HFXTAL (16 MHz) is directly connected to the RCLK. Therefore, if HFXTAL (16 MHz) is used, flash
timer registers need to be programmed to 16 MHz before any flash erase/write operations.
• HP_BUCK_CLK clocks the HP Buck module. The default HPBUCK clock frequency, if enabled, is 200 kHz.
There is another option available for HPBUCK clock frequency with 400 kHz frequency generation as high
load mode.
• ACLK clocks the ADC.
System Clock Functional Description
This section provides information on the clocks and the clock gates required for power management.
System Clock Block Diagram
The clocking diagram is shown below.
SPLL mux
SYS_CLKIN
GPIOCLKOFF
PLL
ACLKDIV
ADC
52 MHz
SPLL
PERCLKOFF
root_clock
HFXTAL
16/26 MHz
HFOSC
26 MHZ
ACLK
UCLKI2COFF
PCLK_I2C
PCLK
HFOSC
DIV
I2C
PCLKDIV
PCLK self-gated peripherals
AHB sub system clock
HCLKDIV
DIV /2
or DIV/1
RCLK
Flash
RHP_CLK
400/200 kHz
clock
RTC0
LFCLK mux
LFXTAL
32 kHz
lf_clk
RTC1
Beeper
LFOSC
32 kHz
HP_BUCK_CLK
HPBuck
GPT_CLK Mux /
Timer_RGB_CLK Mux
LFXTAL
LFOSC
PCLK
HFOSC divided
GPTCLKxOFF/
TMRRGBCLKOFF
RGB timer/
TMR
WDT
Figure 6-1: Clocking Diagram
Operation
On power-up, the core executes from a 6.5 MHz system clock. User can program a clocking scheme by setting approriate values in the clocking registers.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
System Clock Block Diagram
Clock Muxes
As shown in the Clocking Diagram, there are four clock source multiplexers:
• Root clock selection Mux (Root clock Mux)
• Low frequency clock Mux (LFCLK Mux)
• SPLL input Mux (SPLL Mux)
• RCLK Mux controlled using MMRs
The multiplexer for general purpose timers are controlled through registers within the Timer block.
NOTE: Ensure that the desired clock input is available and stable for the clock selection made for the clock mux.
Else, the system can be locked out of a stable clock.
If RCLK Mux is configured as a non-SPLL clock, SPLL must be disabled by the user.
Table 6-1: Clock Muxes
Clocks
Registers
Selection
Root Clock Mux
CLKG_CLK_CTL0.CLKMUX
00: HFOSC
01: HFXTAL
10: SPLL
11: External clock through SYS_CLKIN GPIO
SPLL Mux
CLKG_CLK_CTL0.PLL_IPSEL
0: HFOSC
1: HFXTAL
LFCLK Mux
CLKG_OSC_CTL.LFCLK_MUX
0: LFOSC
1: LFXTAL
2: External clock through SYS_CLKIN GPIO
3: External clock through SYS_CLKIN GPIO
RCLK Mux
CLKG_CLK_CTL0.RCLKMUX
00: HFOSC
01: Reserved
10: HFXTAL 26 MHz
11: HFXTAL 16 MHz
GPT_CLK Mux
TMR_CTL.CLK
Controlled by Timer 0/Timer 1/Timer 2/Timer_RGB
Timer_RGB_Clk Mux
CLKG_CLK_CTL5.
TMRRGBCLKOFF
00: PCLK (Output from PDIV (PCLK Divider))
01: HFOSC 26 MHz (Internal high frequency)
10: LFOSC 32 kHz (Internal low frequency oscillator)
11: LFXTAL 32 kHz
Clock Dividers
Three programmable clock dividers are available to generate the clocks in the system. A clock divider integer divides
the input clock down to a new clock. The division range is from 1 to 32 for HCLK and PCLK dividers, and 1 to
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System Clock Block Diagram
511 for ACLK divider. Division selection can be made on-the-fly. The output remains glitch free and stretches the
high time, never creating a high time shorter than the pre or post value of the clock period.
Two clock dividers use the root clock as an input and generate the core and peripheral synchronized clocks. The
clock dividers are cascaded in such a way that each stage initially releases its divided clock in a sequence. The last
stage informs all other stages that its divided clock is ready to be output. The effect of this cascading is that divided
clocks are released synchronously when new divider values are programmed. Initial edges of each clock are mutually
aligned.
The Clock Dividers table summarizes the inputs and outputs of each clock divider along with the register bits to
program them.
Table 6-2: Clock Dividers
Divider
Input Clock
Output Clocks
Bit Field
Retained in Hibernate Mode
0
Root clock
HCLK_CORE, HCLK_BUS,
FCLK
CLKG_CLK_CTL1.HCLKDIVCNT
Yes
1
Root clock
PCLK, all peripheral clocks
CLKG_CLK_CTL1.PCLKDIVCNT
Yes
2
Root clock
ACLK (for ADC)
CLKG_CLK_CTL1.ACLKDIVCNT
No
As the ADC clock requires a clean start, the user must program the CLKG_CLK_CTL1.ACLKDIVCNT field after
waking from hibernate (CLKG_CLK_CTL1.ACLKDIVCNT is not retained in hibernate mode). Also, the user
must re-enable the ADC, as the ADC_CFG.EN bit is not retained in hibernate mode.
Only certain divider ratios are legal between PCLK and HCLK. The frequency of PCLK must be less than or equal
to the frequency of HCLK, and the ratio of the dividers must be an integer.
In general, clock division can be changed on the fly during normal operation.
Clock Gating
In the case of certain clocks, clocks can be individually gated depending on the power mode or register settings. For
more information about clock gating and power modes, refer to Power Management (PMG).
The clock gates of the peripheral clocks are user controllable in certain power modes. The CLKG_CLK_CTL5 register can be programmed to turn off certain clocks, depending on user application. To disable the clock, set the respective bits in the CLKG_CLK_CTL5 register to 1.
PLL Settings
The PLL Diagram shows the abstract PLL structure for SPLL. It has the multiplier coefficient N and divider coefficient M to decide the output clock ratio of N/M. There is an optional DIV2 built in the PLL to either divide down
the PLL output clock by 2 or directly output it. This is also an optional MUL2 built-in to PLL to multiply the clock
out of PLL by 2 to increase the range of the PLL.
The PLL must always switch away from ROOT_CLK when changing any coefficients or clock sources.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
PLL Settings
When the reference clock for the phase frequency detector (PFD) has a 2 MHz input, the PLL has its best phase
margin. Therefore, it is recommended that for a 26 MHz crystal clock input, configure M as 13, and for a 16 MHz
crystal clock input, configure M as 8.
1/M
Phase Frequency
Detector
VCO
1/N
DIV2
Clock Out
1/MUL2
Figure 6-2: PLL Diagram
PLL Output Frequency = Clock in * (MUL2*N)/ (DIV2*M)
The PLL Settings table shows the recommend PLL settings for a variety of input and output clocks. The PLL settings can be programmed using the CLKG_CLK_CTL3 register.
To enable the SPLL, the CLKG_CLK_CTL3.SPLLEN bit must be set. The SPLL N multiplier can be set using the
CLKG_CLK_CTL3.SPLLNSEL bits.
The M divider can also be set using the CLKG_CLK_CTL3.SPLLMSEL bits. SPLL MUL2 is controlled by the
CLKG_CLK_CTL3.SPLLMUL2 bit. DIV2 is controlled by the CLKG_CLK_CTL3.SPLLDIV2 bit.
MUL2 = CLKG_CLK_CTL3.SPLLMUL2+1 and DIV2 = CLKG_CLK_CTL3.SPLLDIV2+ 1.
Table 6-3: PLL Settings for 26 MHz and 52 MHz
PLL
Input Clock (MHz)
M
MUL2
N
DIV2
Output Clock (MHz)
SPLL
26
13
1
26
2
26
SPLL
16
8
1
26
2
26
SPLL
26
13
1
26
1
52
SPLL
16
8
1
26
1
52
The recommended VCO output range is 32 MHz to 60 MHz and the PLL output range is 16 MHz to 60 MHz.
The minimum value of N is 8 (if MUL2=2) and maximum is 31. The recommended output frequency from 1/M
divider is 2 MHz and the minimum value of M = 2.
PLL Output Frequency = Clock in* ((MUL2*NSEL)/ (DIV2*MSEL))
Where,
MUL2 = CLKG_CLK_CTL3.SPLLMUL2+1
DIV2 = CLKG_CLK_CTL3.SPLLDIV2 + 1
DIV2 = CLKG_CLK_CTL3.SPLLNSEL
MSEL = CLKG_CLK_CTL3.SPLLMSEL
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PLL Settings
PLL Interrupts
The PLL can interrupt the core when it locks or when it loses its lock. To enable the SPLL interrupts, the
CLKG_CLK_CTL3.SPLLIE bit must be set. The CLKG_CLK_STAT0.SPLLUNLK bit indicates that the SPLL
unlock event has happened.
The CLKG_CLK_STAT0.SPLLLK bit indicates that a SPLL lock event has happened. Both the bits are used to
interrupt the core when PLL interrupts are enabled. Both bits are sticky and must write a 1 to be cleared. These bits
are different from the CLKG_CLK_STAT0.SPLL bit, which mirrors the value of the SPLL lock signal (1: Locked,
0: Unlocked).
PLL Programming Sequence
The following sequence shows how to configure a 26 MHz input clock from HFXTAL to 26 MHz SPLL output,
and use the PLL output as Root clock. The HCLK is set to 26 MHz and PCLK to 6.5 MHz.
1. Enable PLL interrupts by setting CLKG_CLK_CTL3.SPLLIE to 0x1.
2. Set HFXTAL as input to PLL by setting CLKG_CLK_CTL0.PLL_IPSEL to 0x1.
3. Enable HFXTAL by setting CLKG_OSC_CTL.HFXTALEN to 0x1.
4. Set the clock dividers consistent with the intended system clock rates by setting
CLKG_CLK_CTL1.PCLKDIVCNT to 0x04 and CLKG_CLK_CTL1.HCLKDIVCNT to 0x01.
5. Enable the PLL and configure the PLL M and N values by setting CLKG_CLK_CTL3.SPLLEN to 0x1,
CLKG_CLK_CTL3.SPLLMSEL to 0xD, and CLKG_CLK_CTL3.SPLLNSEL to 0x1A.
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, also check that the crystal is stable
at this stage, even though the PLL should not lock if the crystal is not stable.
7. Clear the PLL interrupt and select PLL as the system clock source by setting CLKG_CLK_STAT0.SPLLLK
to 0x1 and CLKG_CLK_CTL0.CLKMUX to 0x2.
The following sequence shows how to configure a 26 MHz input clock from HFOSC to 16 MHz SPLL output, and
use the PLL output as Root clock. HCLKDIV and PCLKDIV are set to 0x1.
1. Enable PLL interrupts by setting CLKG_CLK_CTL3.SPLLIE to 0x1.
2. Set HFOSC as input to PLL by setting CLKG_CLK_CTL0.PLL_IPSEL to 0x0.
3. Disable the PLL by setting CLKG_CLK_CTL3.SPLLEN to 0x0.
4. Program appropriate MSEL, NSEL to get PLL clock out as 16 MHz by setting
CLKG_CLK_CTL3.SPLLMSEL to 0xD and CLKG_CLK_CTL3.SPLLNSEL to 0x10.
5. Enable the PLL by setting CLKG_CLK_CTL3.SPLLEN to 0x1.
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, check if the crystal is stable at this
stage.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Crystal Programming
7. Clear the PLL interrupt and select PLL as the system clock source by setting CLKG_CLK_STAT0.SPLLLK
to 0x1 and CLKG_CLK_CTL0.CLKMUX to 0x2.
Crystal Programming
The crystals are disabled by default and can be programmed using the CLKG_OSC_CTL register. The crystals can
be enabled by setting the CLKG_OSC_CTL.HFX_EN or CLKG_OSC_CTL.LFX_EN bits. The stable signal status
bits are also mirrored in this register.
NOTE: The CLKG_OSC_CTL.HFOSC_EN bit must be set before issuing a SYSRESETREQ and allowing the
Cortex-M4F to assert a reset request signal to the systems reset generator. This ensures that all system components
are reset properly. This is independent of the Root clock mux and SPLL clock mux settings.
Interrupts
Each crystal can interrupt the core when its output clock becomes stable. The interrupts are enabled by setting the
CLKG_CLK_CTL0.HFXTALIE and CLKG_CLK_CTL0.LFXTALIE bits.
The CLKG_CLK_STAT0.HFXTAL and CLKG_CLK_STAT0.LFXTAL bits contain the current state of the stable signals of the crystals. The CLKG_CLK_STAT0.HFXTALOK or CLKG_CLK_STAT0.LFXTALOK bits are set
when an event is detected on the stable signals of the crystals.
The CLKG_CLK_STAT0.HFXTALOK/ CLKG_CLK_STAT0.HFXTALNOK and
CLKG_CLK_STAT0.LFXTALOK/ CLKG_CLK_STAT0.LFXTALNOK bits are sticky and must be cleared by
writing to 1.
NOTE: CLKG_CLK_STAT0.HFXTALNOK and CLKG_CLK_STAT0.LFXTALNOK bits are not continuous
XTAL monitors and are only set as a confirmation that the corresponding XTAL has been properly disabled.
PLL Clock Protection
In the event the clock source to the PLL is lost, the PLL will maintain operation at a reduced VCO output frequency of approximately 20 MHz, for approximately 3 to 5 ms, this clock will be active/running until PLL is disabled.
This behavior allows PLL interrupt sources such as CLKG_CLK_STAT0.SPLLUNLK to be serviced and enables
the appropriate action to be taken by the core. This feature protects the core from an indefinite stall due to broken
or short leads of the XTAL circuit.
Oscillator Programming
Both the internal oscillators are enabled by default.
Before issuing a SYSRESETREQ and allowing the Cortex-M4F to assert a reset request signal to the systems reset
generator, the CLKG_OSC_CTL.HFOSC_EN bit must be set. This ensures that all system components are reset
properly. This is independent of Root clock mux and SPLL clock mux settings.
HFOSC is enabled by using the CLKG_OSC_CTL.HFOSC_EN bit.
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Switching System Clock to Greater than 26 MHz
NOTE: Before stopping the HFOSC internal oscillator, the HFXTAL should be running the system. Otherwise, the
part locks because its clock has been stopped by the user without possibility of recovery. Peripherals driven with a 32
kHz clock should be switched over to the LFXTAL external crystal oscillator only after ensuring that LFXTAL is
stable and running. LFOSC internal oscillator cannot be disabled.
Switching System Clock to Greater than 26 MHz
The system frequency can be made 52 MHz only using the PLL clock output.
When changing the PLL output from 26 MHz to 52 MHz, the flash wait state has to be changed from 0 to 1. The
maximum ACLK frequency that can drive ADC is 26 MHz. If the Root clock is 52 MHz, change the ACLK frequency such that the frequency is limited to the maximum allowed frequency.
If the PCLK frequency is 52 MHz, the respective clock setting registers of SPI, UART, SPORT, and I2C modules
are also programmed with the appropriate values. Ensure that the ADC power-up wait count specified in ADC
PWRUP register is also programmed with respect to the PCLK frequency.
The PMG_CTL1.HPBUCK_LD_MODE bit has to be set to 1, when the system clock is greater than 26 MHz.
The following steps show how to change the PLL clock out frequency from 26 MHz to 52 MHz.
Assume that CLKG_CLK_CTL1.HCLKDIVCNT and CLKG_CLK_CTL1.PCLKDIVCNT are programmed to divide by 1. and PLL input source is HFXTAL (26 MHz):
1. Enable the PLL interrupts by setting the CLKG_CLK_CTL3.SPLLIE bit to 0x1.
2. Select HFOSC (26 MHz) as Root clock instead of PLL clock (CLKG_CLK_CTL0.CLKMUX = 0x0).
3. Disable PLL by setting the CLKG_CLK_CTL3.SPLLEN bit to 0x0.
4. To get PLL clock out as 52 MHz, set CLKG_CLK_CTL3.SPLLMSEL = 0xD, and
CLKG_CLK_CTL3.SPLLNSEL = 0x1A.
5. Set CLKG_CLK_CTL3.SPLLMUL2 = 0x0 and CLKG_CLK_CTL3.SPLLDIV2 = 0x0
6. Enable PLL by setting the CLKG_CLK_CTL3.SPLLEN bit to 0x1.
7. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, check if the crystal is stable. The
PLL must not lock if the crystal is not stable.
8. Clear the PLL interrupt and select PLL as the system clock source by setting the
CLKG_CLK_STAT0.SPLLLK bit to 0x1 and the CLKG_CLK_CTL0.CLKMUX bit to 0x2.
Oscillators
HF Oscillator
The 26 MHz high frequency oscillator is enabled by the CLKG_OSC_CTL.HFOSC_EN bit. The oscillator accuracy is ±3%. The divider values are 1, 2, 4, 8, 16, and 32. The HFOSC divider value can be selected using the
CLKG_CLK_CTL2 register.
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Oscillators
When the HFOSC divider value selected is 1 or 2, the RCLK divider is automatically selected to generate the 13
MHz clock. When the HFOSC divide value is above 2, the RCLK frequency is below 13 MHz, and during this
conditions. Flash erase and write operations are not possible. Read operation is possible.
The CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit to enable the fast wake up from Flexi mode by automatically
selecting the 26 MHz HFOSC clock during the wakeup.
The CLKG_CLK_CTL2 register must not be written for 3 μs after the CLKG_CLK_CTL2.HFOSCDIVCLKSEL
value is updated.
Fast Wake-Up from Flexi Mode
During the Cortex wake up from Flexi mode, the HF oscillator divider can be automatically loaded with divided by
1 value to enable the fast wake-up, provided the CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit is set to 1.
When divided by 1 clock is selected, the 26 MHz HFOSC clock itself will be used during the wakeup for enabling
the fast wake up. This updated divided by 1 select value remains the same until the new divider value is written to
the HFOSC divider select register.
If the CLKG_CLK_CTL2.HFOSCAUTODIV_EN bit is 0, this fast wake-up feature is disabled and HFOSC divider
register remains unchanged during the wake up.
LF Oscillator
The 32.768 kHz low frequency oscillator is enabled always, it cannot be disabled, and it is disabled automatically in
shutdown mode. The oscillator accuracy is ± 5%.
HFXTAL Oscillator
The high frequency oscillator is enabled by the CLKG_OSC_CTL.HFX_EN bit. Lock time is the time the XTAL
takes to give stable clock out after it is enabled. The locking of the oscillator to the correct frequency is signified by
the setting of CLKG_CLK_STAT0.HFXTALOK status bit.
LFXTAL Oscillator
The LFXTAL oscillator is the clock source for the RTC. It is used to keep the time of the system. It provides a
32.768 kHz output clock. This is enabled by setting the CLKG_OSC_CTL.LFX_EN bit.
Once the oscillator is enabled, it remains ON (in hibernate and shutdown modes).
LFXTAL Robust Mode
The robust mode enables the LFXTAL oscillator to work when an additional resistive load is placed between the
crystal and GND. This feature is capable of tolerating impurities on the PCB, where these impurities allow a high
resistance leakage path from the crystal pins to GND, which can cause problems to the circuit operation. This mode
can be enabled using the CLKG_OSC_CTL.LFX_ROBUST_EN bit.
Robust mode load can be selected using the CLKG_OSC_CTL.LFX_ROBUST_LD bits.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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Oscillators
LFXTAL Bypass Feature
LF crystal can be bypassed and external clock supplied on SYS_LFXTAL_IN and used as LFXTAL clock. This functionality is available in all modes other than shutdown mode. LFXTAL lock is automatically generated synchronous
to external clock provided. This feature has to be disabled before entering into shutdown.
Enable LFXTAL Bypass Mode
1. Disable LFXTAL by writing key to the CLKG_OSC_KEY.VALUE and then clearing the
CLKG_OSC_CTL.LFX_EN bit.
2. Wait for the CLKG_OSC_CTL.LFX_OK bit to be de-asserted.
3. Write key to the CLKG_OSC_KEY.VALUE and set the CLKG_OSC_CTL.LFX_BYP bit.
4. Wait for the CLKG_OSC_CTL.LFX_OK bit to be asserted. External clock is connected to LFXTAL at this
stage.
Disable LFXTAL Bypass Mode
1. Write key to the CLKG_OSC_KEY.VALUE and set the CLKG_OSC_CTL.LFX_BYP bit.
2. Wait for the CLKG_OSC_CTL.LFX_OK bit to be de-asserted. External clock is disconnected from LFXTAL
clock.
LFXTAL Clock Failure
Inactivity in LFXTAL clock can be monitored and interrupt/wakeup can be generated once clock failure is observed.
LFOSC clock (32 kHz) is used to monitor and report failure on LFXTAL clock. This feature is supported for
LFXTAL clock frequencies greater than or equal to 1 kHz. Interrupt/wakeup source is available with RTC1 interrupt source.
Clock failure is reported as active high status bit CLKG_OSC_CTL.LFX_FAIL_STA. This status bit has to be
cleared to de-assert the interrupt source.
Enable LFXTAL Clock Failure
1. Write proper key to the CLKG_OSC_KEY.VALUE.
2. Set the CLKG_OSC_CTL.LFX_MON_EN bit.
3. Enable interrupt source for RTC1.
Disable LFXTAL Clock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Clear the CLKG_OSC_CTL.LFX_MON_EN bit.
Clear Status Bit
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Oscillators
1. Disable LFXTAL clock failure feature.
2. Write key to CLKG_OSC_KEY.VALUE.
3. Set the CLKG_OSC_CTL.LFX_FAIL_STA bit to clear the status.
4. Wait until the CLKG_OSC_CTL.LFX_FAIL_STA bit is cleared. This clears both status and interrupt.
LFMUX Auto Switch to LFOSC During LFXTAL Failure
This feature provides the automatic switching of the LFMUX output clock to LFOSC clock, during the LFXTAL
clock failure when the LFMUX is set to use the LFXTAL clock. The LFXTAL clock monitor feature must also be
enabled.
Auto Switch Feature
1. Set CLKG_OSC_CTL.LFX_MON_EN = 1 and CLKG_OSC_CTL.LFX_AUTSW_STA =1. This enables both
the monitor and auto-switch features.
2. Monitor block tracks the LFXTAL and raises an error interrupt, in case of a failure.
3. If CLKG_OSC_CTL.LFCLKMUX = LFXTAL and LFXTAL monitor error is raised, auto switching logic is
triggered and LFMUX switches to LFOSC clock.
4. Once the switch to LFOSC is complete, hardware sets the CLKG_OSC_CTL.LFX_AUTSW_STA bit.
5. Once original source of LFMUX is revived, to switch back, set CLKG_OSC_CTL.LFX_FAIL_STA to 1.
This clears the interrupt.
6. Once interrupt is cleared, write 1 to CLKG_OSC_CTL.LFX_AUTSW_STA to switch back to original clock
source.
Root Clock Failure
Inactivity in root clock can be monitored and interrupt can be generated once clock failure is observed. The
HFOSC clock is used to monitor and report failure on root clock. Clock failure is reported as active high sticky
status bit CLKG_OSC_CTL.ROOT_FAIL_STA. This status bit has to be cleared to de-assert the interrupt source.
Enable Root Clock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Set the CLKG_OSC_CTL.ROOT_MON_EN bit.
3. Enable Interrupt source IRQ71.
Disable LFXTAL Cock Failure
1. Write proper key to CLKG_OSC_KEY.VALUE.
2. Clear the CLKG_OSC_CTL.ROOT_MON_EN bit.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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System Clock Interrupts and Exceptions
Clear Status Bit
1. Disable the Root clock failure feature.
2. Write key to CLKG_OSC_KEY.VALUE register.
3. Set the CLKG_OSC_CTL.ROOT_FAIL_STA bit to clear the status.
4. Wait until the CLKG_OSC_CTL.ROOT_FAIL_STA bit is cleared. This clears both status and interrupt.
Root CLKMUX Auto Switch to HFOSC during Root Clock Failure
This feature provides the automatic switching of the root clock to HFOSC clock, during the Root clock failure. The
Root clock monitor feature must also be enabled.
Auto Switch Feature
1. Set CLKG_OSC_CTL.ROOT_MON_EN =1 and CLKG_OSC_CTL.ROOT_AUTSW_EN =1. This enables
both monitor and auto-switch features.
2. Monitor block tracks the Root clock. In case of a failure, it raises an error interrupt on line 71.
3. If Root clock monitor error is raised, auto-switching logic is triggered and Root clock switches to HFOSC
clock.
4. Once the switch to HFOSC is complete, hardware sets the CLKG_OSC_CTL.ROOT_AUTSW_STA bit.
5. Once original source of Root clock is revived, to switch back, set the CLKG_OSC_CTL.ROOT_FAIL_STA
bit to 1. This clears the interrupt.
6. Once interrupt is cleared, write 1 to the CLKG_OSC_CTL.ROOT_AUTSW_STA bit to switch back to original clock source.
System Clock Interrupts and Exceptions
Refer to Events (Interrupts and Exceptions), for more information.
Setting the System Clocks
Set System Clock to PLL Input Source
The following timing diagrams describe the sequence of events to change system clock from internal oscillator to
PLL input source based. XTAL refers to HFXTAL (26 MHz or 16 MHz crystal oscillator). Timers (GPT) have following expiry periods.
HFXTAL lock timer expiry: 20 ms
LFXTAL lock timer expiry: 1.5 s
If the oscillators are not locked beyond the expiry period, it indicates that there are issues in the XTAL.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Setting the System Clocks
1. Set System Clock to
oscillator (default)
PLL input
source?
XTAL
2. Turn On XTAL
3. Setup Timer
4. Poll XTAL lock bit
No
OSC
5. Xtal Locked?
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
7. Select Xtal as PLL
source
8. Setup Timer
9. Program PLL
10. Poll PLL lock bit
No
Timer ISR: Error, the
PLL has not locked
11. PLL Locked?
12. Disable Timer
13. Change System
Clock to PLL
Figure 6-3: Change System Clock to PLL (POLL)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–13
Setting the System Clocks
1. Set System Clock to
oscillator (default)
PLL input source?
XTAL
2. Select XTAL as PLL
source
3. Turn On XTAL
osc
4. Program PLL
5. Setup Timer
6. Poll XTAL lack bit
No
XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
7. Poll PLL lack bit
No
PLL Locked?
Timer ISR: Error, the
PLL has not locked
8. Disable Timer
9. Change System
Clock to PLL
Figure 6-4: Change System Clock to PLL (POLL Alternative)
6–14
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
PLL input
source?
XTAL
2. Select XTAL
as PLL source
3. Turn On XTAL
osc
4. Program PLL
w/irq
5. Setup Timer
6. Go to Sleep
GPT ISR: The PLL
has not locked
7. PLL ISR.
The PLL has locked.
Clear interrupt
XTAL
PLL input
source?
8. XTAL Locked?
(sanity check)
Error, PLL is locked
but XTAL is not
(unlikely)
osc
Yes
9. Change System
Clock to PLL
Figure 6-5: Change System Clock to PLL (IRQ Method)
Set System Clock to XTAL
The following figures show the sequence of events to change system clock from internal oscillator based to XTAL
based source.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–15
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
2. Turn On XTAL
3. Setup Timer
4. Poll XTAL lock bit
No
5. XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
7. Change System
Clock to XTAL source
Figure 6-6: Change System Clock To XTAL (Poll Method)
6–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
2. Turn On XTAL with
IRQ
3. Setup Timer
4. Go to Sleep
GPT ISR: The XTAL
has not locked
XTAL ISR. The XTAL
has locked
5. Change System
Clock to XTAL source
Figure 6-7: Change System Clock to XTAL (IRQ Method)
Changing System Clock Source
The figure shows the sequence to change the system clock source from oscillator to either XTAL input or PLL based
input source.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–17
ADuCM4050 CLKG_OSC Register Descriptions
1. Set System Clock
to oscillator
(default)
14. Turn On XTAL
XTAL
15. Setup Timer
16. Poll XTAL lock bit
Switch HF Clock?
PLL
PLL input
source?
XTAL
2. Turn On XTAL
3. Setup Timer
GPIO
13. Enable GPIO
clock input
4. Poll XTAL lock bit
No
No
OSC
5. XTAL Locked?
17. XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
18. Disable Timer
7. Select XTAL as
PLL source
8. Program PLL
9. Setup Timer
10. Poll PLL lock bit
No
Timer ISR: Error, the
PLL has not locked
11. PLL Locked?
12. Disable Timer
19. Change System
Clock Source
Figure 6-8: Changing System Clock
ADuCM4050 CLKG_OSC Register Descriptions
Clocking registers (CLKG_OSC) contains the following registers.
Table 6-4: ADuCM4050 CLKG_OSC Register List
Name
Description
CLKG_OSC_CTL
Oscillator Control
CLKG_OSC_KEY
Key Protection for OSCCTRL
6–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_OSC Register Descriptions
Oscillator Control
The CLKG_OSC_CTL register is key-protected. To unlock this protection, 0xCB14 should be written to
CLKG_OSC_KEY before writing to CLKG_OSC_CTL. A write to any other register on the APB bus before writing
to CLKG_OSC_CTL will return the protection to the lock state.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
LFX_ROBUST_LD[0] (R/W)
LFXTAL Robust Mode Load select
LFCLK_MUX (R/W)
32 kHz clock select mux
LFX_ROBUST_EN (R/W)
LFXTAL Mode select
HFOSC_EN (R/W)
High frequency internal oscillator enable
LFX_AUTSW_STA (R/W1C)
Status of automatic switching of the
LF Mux to LFOSC upon detection of
LFXTAL failure
LFX_EN (R/W)
Low frequency crystal oscillator enable
HFX_EN (R/W)
High frequency crystal oscillator enable
LFX_AUTSW_EN (R/W)
Enables automatic Switching of the
LF Mux to LFOSC on LFXTAL Failure
LFX_BYP (R/W)
Low frequency crystal oscillator Bypass
HFX_OK (R)
Status of HFXTAL oscillator
LFX_MON_EN (R/W)
LFXTAL clock monitor and Clock FAIL
interrupt enable
LFX_OK (R)
Status of LFXTAL oscillator
LFOSC_OK (R)
Status of LFOSC oscillator
HFOSC_OK (R)
Status of HFOSC oscillator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
LFX_FAIL_STA (R/W)
LF XTAL (crystal clock) Not Stable
LFX_ROBUST_LD[1] (R/W)
LFXTAL Robust Mode Load select
ROOT_FAIL_STA (R/W)
Root clock (crystal clock) Not Stable
ROOT_MON_EN (R/W)
ROOT clock monitor and Clock FAIL
interrupt enable
ROOT_AUTSW_STA (R/W1C)
Status of automatic switching of the
Root clock to HFOSC upon detection
of Root clock failure
ROOT_AUTSW_EN (R/W)
Enables automatic Switching of the
Root clock to HFOSC on Root clock
Failure
Figure 6-9: CLKG_OSC_CTL Register Diagram
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–19
ADuCM4050 CLKG_OSC Register Descriptions
Table 6-5: CLKG_OSC_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 LFX_FAIL_STA
(R/W)
LF XTAL (crystal clock) Not Stable.
This is a sticky bit. If set, it generates interrupt on the RTC1 IRQ line. It can generate
interrupt during Hibernate or Active modes. If the flag is set in Hibernate mode, the
part will wakeup from Hibernate mode by asserting interrupt on RTC1 IRQ line.
The interrupt and this bit can be cleared by writing 1 to this bit.
1 - LFXTAL (low frequency XTAL clock) is not running. The Crystal connection in
the board to the chip has possible snapped. Or the External clock driver has stopped
giving out clock.
0 - LFXTAL is running fine.
30 ROOT_FAIL_STA
(R/W)
Root clock (crystal clock) Not Stable.
This is a sticky bit. If set, it generates interrupt on the IRQ 71 line. It can generate
interrupt during Active mode. The interrupt and this bit can be cleared by writing 1 to
this bit.
1 - Root clock is not running.
0 - Root clock is running fine.
22 ROOT_AUTSW_STA
(R/W1C)
Status of automatic switching of the Root clock to HFOSC upon detection of Root
clock failure.
This is a sticky bit.This bit indicates whether HW automatically switched Root clock
to HFOSC upon detection of Root clock failure. This bit can be cleared by writing 1
to this bit.
1 - Root clock switched to HFOSC
0 - Root clock not switched to HFOSC
0 Indicates HW is not automatically switched to HFOSC
upon detection of Root clock failure
1 Indicates HW automatically switched to HFOSC upon
detection of Root clock failure
21 ROOT_AUTSW_EN
(R/W)
Enables automatic Switching of the Root clock to HFOSC on Root clock Failure.
This bit is used to enable the Automatic Switching of the Root clock to HF OSC on
Root clock Failure. This feature is valid only when the ROOT clock monitor is enabled.The ROOTCLK_MON_EN bit of the OSCCTRL register should also be set to
1, for the proper functionality of the automatic switching of Root clock to HF OSC
clock.
0 Disables Automatic Switching of the Root clock to HF
OSC on Root clock Failure
1 Enables Automatic Switching of the Root clock to HF
OSC on Root clock Failure
6–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_OSC Register Descriptions
Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
20 ROOT_MON_EN
ROOT clock monitor and Clock FAIL interrupt enable.
(Access)
(R/W)
If set, the Root clock will be monitored using the 26 MHz HF Oscillator This clock
will be monitored in Active mode. If the Root clock stops toggling for 2.5 us the
ROOTCLK_MON_FAIL flag is set and interrupt is generated on the Root Clock
Failure IRQ line.
If cleared, the Monitor circuit is reset and the Root clock FAIL interrupt is not generated.
0 Root clock Monitor and clock FAIL interrupt disabled
1 Root clock Monitor and clock FAIL interrupt enabled
16:15 LFX_ROBUST_LD
(R/W)
LFXTAL Robust Mode Load select.
This bits selects the amount of loading tolerated when LFXTAL robust mode is selected, i.e. when CLKG_OSC_CTL.LFX_ROBUST_EN bit is set to 1.
Note: Level 3 supports higher load than level 2, and level 2 supports higher load than
level 1
0 No trim, default lowest power mode
1 Robustness to leakage on XTAL pins - level 1
2 Robustness to leakage on XTAL pins - level 2
3 Robustness to leakage on XTAL pins - level 3
14 LFX_ROBUST_EN
(R/W)
LFXTAL Mode select.
This bit selects Normal Mode or Robust Mode of LFXTAL.
0 Selects Normal mode
1 Selects Robust mode
13 LFX_AUTSW_STA
(R/W1C)
Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL
failure.
This bit indicates if hardware is automatically switched to using LFOSC upon detection of LFXTAL failure.
0 Hardware is not automatically switched to LFOSC
upon detection of LFXTAL failure
1 Hardware automatically switched to LFOSC upon detection of LFXTAL failure
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–21
ADuCM4050 CLKG_OSC Register Descriptions
Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 LFX_AUTSW_EN
(R/W)
Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure.
This bit is used to enable the Automatic Switching of the LF Mux to LFOSC on
LFXTAL Failure.
0 Disables Automatic Switching of the LF Mux to
LFOSC on LFXTAL Failure
1 Enables Automatic Switching of the LF Mux to LFOSC
on LFXTAL Failure
11 HFX_OK
(R/NW)
Status of HFXTAL oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
10 LFX_OK
(R/NW)
Status of LFXTAL oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
9 HFOSC_OK
(R/NW)
Status of HFOSC oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
8 LFOSC_OK
(R/NW)
Status of LFOSC oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
6–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_OSC Register Descriptions
Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 LFX_MON_EN
(R/W)
LFXTAL clock monitor and Clock FAIL interrupt enable.
If set, the LFXTAL clock will be monitored using the on chip 32 kHz low frequency
OSCILLATOR. This clock will be monitored in both Hibernate and Active/Flexi
modes. If the LFXTAL clock stops toggling for 2 ms the LFXTAL_MON_FAIL flag is
set and interrupt is generated on the RTC1 IRQ line.
If cleared, the Monitor circuit is reset and the LFXTAL clock FAIL interrupt is not
generated.
0 LFXTAL Clock Monitor and clock FAIL interrupt disabled
1 LFXTAL Clock Monitor and clock FAIL interrupt enabled
4 LFX_BYP
(R/W)
Low frequency crystal oscillator Bypass.
This bit is used to bypass the low frequency crystal oscillator, and if a clock is supplied
externally on one of the LFXTAL pin. The oscillator must be disabled before setting
this bit.
Disabling LFXTAL can take a while. Ensure that the oscillator is disabled by reading
the LFXTALEN bit and it reads 0.
0 LFXTAL oscillator is disabled and placed in a low power
state
1 LFXTAL oscillator is enabled
3 HFX_EN
(R/W)
High frequency crystal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use.
0 HFXTAL oscillator is disabled and placed in a low power state
1 HFXTAL oscillator is enabled
2 LFX_EN
(R/W)
Low frequency crystal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use.
0 LFXTAL oscillator is disabled and placed in a low power
state
1 LFXTAL oscillator is enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–23
ADuCM4050 CLKG_OSC Register Descriptions
Table 6-5: CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 HFOSC_EN
(R/W)
High frequency internal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use. This bit must be set before the SYSRESETREQ system reset can be initiated.
0 HFOSC oscillator is disabled and placed in a low power
state
1 HFOSC oscillator is enabled
0 LFCLK_MUX
(R/W)
32 kHz clock select mux.
This clock connects to beeper, RTC.
Note: This bit is not reset to default value when soft reset is asserted. Other bits will be
reset. This bit will be reset during other reset such as Power-Up, external reset. Program appropriate value when software executes after a soft reset. Soft reset is generated
by setting the AIRCR.SYSRESETREQ bit in the Cortex register .
0 Internal 32 kHz oscillator is selected
1 External 32 kHz crystal is selected
6–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_OSC Register Descriptions
Key Protection for OSCCTRL
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Oscillator key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-10: CLKG_OSC_KEY Register Diagram
Table 6-6: CLKG_OSC_KEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Oscillator key.
The CLKG_OSC_CTL register is key-protected with value 0xCB14. The
CLKG_OSC_CTL register should be written after proper key value entered. A write to
any other register on the APB bus before writing to CLKG_OSC_CTL will return the
protection to the lock state.
ADuCM4050 CLKG_CLK Register Descriptions
Clocking registers (CLKG_CLK) contains the following registers.
Table 6-7: ADuCM4050 CLKG_CLK Register List
Name
Description
CLKG_CLK_CTL0
Misc Clock Settings
CLKG_CLK_CTL1
Clock Dividers
CLKG_CLK_CTL2
HF Oscillator Divided Clock Select
CLKG_CLK_CTL3
System PLL
CLKG_CLK_CTL5
User Clock Gating Control
CLKG_CLK_STAT0
Clocking Status
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–25
ADuCM4050 CLKG_CLK Register Descriptions
Misc Clock Settings
Clock Control 0 is used to configure clock sources used by various systems such as the core and memories and peripherals. All unused bits are read only returning a value of 0. Writing unused bits has no effect.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
0
0
0
HFXTALIE (R/W)
High frequency crystal interrupt enable
CLKMUX (R/W)
Clock mux select
LFXTALIE (R/W)
Low frequency crystal interrupt enable
CLKOUT (R/W)
GPIO clock out select
PLL_IPSEL (R/W)
SPLL source select mux
RCLKMUX (R/W)
Flash reference clock and HPBUCK
clock source mux
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-11: CLKG_CLK_CTL0 Register Diagram
Table 6-8: CLKG_CLK_CTL0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 HFXTALIE
(R/W)
High frequency crystal interrupt enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.HFXTALOK or
CLKG_CLK_STAT0.HFXTALNOK status or if no interrupt should be generated.
This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a HFXTALOK or HFXTALNOK.
1 An interrupt to the core is generated on a HFXTALOK
or HFXTALNOK.
14 LFXTALIE
(R/W)
Low frequency crystal interrupt enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.LFXTALOK or
CLKG_CLK_STAT0.LFXTALNOK status or if no interrupt should be generated.
This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a LFXTALOK or LFXTALNOK.
1 An interrupt to the core is generated on a LFXTALOK
or LFXTALNOK.
6–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-8: CLKG_CLK_CTL0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12:11 PLL_IPSEL
(R/W)
SPLL source select mux.
CLKG_CLK_CTL0.PLL_IPSEL selects which source clock is feed to the SPLL.
The selection should be made before the SPLL is enabled. Selection should not be
changed after the SPLL is enabled.
0 Internal HF oscillator is selected
1 External HF XTAL oscillator is selected
2 GPIO_CLK input is selected
3 GPIO_CLK input is selected
9:8 RCLKMUX
(R/W)
Flash reference clock and HPBUCK clock source mux.
These bits are to be programmed, when both external crystal and HF oscillator are stable and running. The clock muxed output supplies Flash reference clock and HP buck
clock (200 kHz).
If option 11 is programmed, the clock-out is 16 MHz instead of 26 MHz, the dividers
of following clocks get auto-configured.
RCLK - divider is bypassed. RCLK = 16 MHz
HPBUCK clock - divider is auto-configured to generate 200 kHz clock
Note: If external XTAL clock is 16 MHz instead of 26 MHz. Then HP Buck nonoverlapping phases increases. This is not recommended if HP buck is enabled.
0 Sourcing from HFOSCCLK - 26 MHz.
Set CLKG_CLK_CTL0.RCLKMUX = 00 if HFOSC
(26 MHz) to be the source for HPBUCK divider and
flash-reference clock generators.
1 Reserved.
2 Sourcing from external HFXTAL (26 MHz).
Set CLKG_CLK_CTL0.RCLKMUX = 10 if HFXTAL
to be the source for HPBUCK divider and flash reference clock generators and HFXTAL frequency connected to chip is 26 MHz.
3 Sourcing from external HFXTAL (16 MHz).
Set CLKG_CLK_CTL0.RCLKMUX = 11 if HFXTAL
to be the source for HPBUCK divider and flash-reference clock generators and HFXTAL frequency connected to chip is 16 MHz.
6:3 CLKOUT
(R/W)
GPIO clock out select.
Selects the clock to be rooted to the GPIO clock out pin.
0 ROOT_CLK
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–27
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-8: CLKG_CLK_CTL0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 LF_CLK
2 ACLK
3 HCLK_BUS
4 HCLK_CORE
5 PCLK
6 RCLK (Ref clock for flash controller timer)
7 RHP_CLK (mux of HF OSC, HF XTAL clock)
8 GPT0_CLK
9 GPT1_CLK
10 HCLK_P (Connects to peripherals operating on
HCLK)
11 PLL out clock
12 RTC0 1 Hz generated clock
13 HPBUCK_CLK
14 HPBUCK_Non_overlap_clk
15 RTC1 1Hz generated clock
1:0 CLKMUX
(R/W)
Clock mux select.
Determines which single shared clock source is used by the PCLK and HCLK dividers.
Ensure that an enabled active stable clock source is selected
(AON_CORE_MUX_SEL).
0 High frequency internal oscillator is selected
1 High frequency external crystal oscillator is selected
2 System PLL is selected
3 External GPIO port is selected
6–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
Clock Dividers
Clock Control 1 is used to set the divide rates for the HCLK, and PCLK and ACLK dividers. This register can be
written to at any time. All unused bits are read only, returning a value of 0. Writing to unused bits has no effect.
15 14 13 12 11 10 9
0
0
0
0
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
PCLKDIVCNT (R/W)
PCLK divide count
HCLKDIVCNT (R/W)
HCLK divide count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
ACLKDIVCNT (R/W)
ACLK Divide Count
Figure 6-12: CLKG_CLK_CTL1 Register Diagram
Table 6-9: CLKG_CLK_CTL1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
24:16 ACLKDIVCNT
(R/W)
ACLK Divide Count.
Determines the ACLK rate based on the following equation:
ACLK = ROOT_CLK/CLKG_CLK_CTL1.ACLKDIVCNT
For example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.ACLKDIVCNT =
0x1, ACLK operates at 26 MHz.
The value of CLKG_CLK_CTL1.ACLKDIVCNT takes effect after a write access to
this register and typically takes one ACLK cycle. This register can be read at any time
and can be written to at any time. The reset divider count is 0x4.
Value range is from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1
have the same results as divide by 1.
Default value of this register is configured such that ACLK is 6.5 MHz.
13:8 PCLKDIVCNT
(R/W)
PCLK divide count.
Determines the PCLK rate based on the following equation:
PCLK = ROOT_CLK/CLKG_CLK_CTL1.PCLKDIVCNT
For example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.PCLKDIVCNT =
0x2, PCLK operates at 13 MHz.
The value of CLKG_CLK_CTL1.PCLKDIVCNT takes effect after a write access to
this register and typically takes 2-to-4 PCLK cycles. This register can be read at any
time and can be written to at any time. The reset divider count is 0x4.
Value range is from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1
have the same results as divide by 1.
The default value of this register is configured such that PCLK is 6.5 MHz.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–29
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-9: CLKG_CLK_CTL1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5:0 HCLKDIVCNT
(R/W)
HCLK divide count.
Determines the HCLK rate based on the following equation:
HCLK = ROOT_CLK/CLKG_CLK_CTL1.HCLKDIVCNT
For example, if ROOT_CLK is 26 MHz and CLKG_CLK_CTL1.HCLKDIVCNT =
0x1, HCLK operates at 26 MHz.
The value of CLKG_CLK_CTL1.HCLKDIVCNT takes effect after a write access to
this register and typically takes 2 to 4 PCLK cycles (not HCLK cycles). This register
can be read at any time and can be written to at any time. The reset divider count is
0x4.
Value range is from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1
have the same results as divide by 1.
Default value of this register is configured such that HCLK is 6.5 MHz.
6–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
HF Oscillator Divided Clock Select
Clock Control 2 is used to select the clock from the frequency divided clocks derived from the hf oscillator clock. All
unused bits are read only, returning a value of 0. Writing to unused bits has no effect.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HFOSCDIVCLKSEL (R/W)
HF Oscillator divided clock select
HFOSCAUTODIV_EN (R/W)
HF Oscillator auto divide by one clock
selection during wakeup from Flexi
power mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-13: CLKG_CLK_CTL2 Register Diagram
Table 6-10: CLKG_CLK_CTL2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:1 HFOSCDIVCLKSEL
(R/W)
HF Oscillator divided clock select.
Used to select the clock from the frequency divided clocks derived from HFOSC
clock. All unused bits are read only, returning a value of 0. Writing to unused bits has
no effect.
Note: Setting the values for HFOSCDIVCLKSEL from 3'b010 to 3'b101 changes the
flash reference clock RCLK to be less than 13 MHz.
0 Selects the HFOSC/1 clock
1 Selects the HFOSC/2 clock
2 Selects the HFOSC/4 clock
3 Selects the HFOSC/8 clock
4 Selects the HFOSC/16 clock
5 Selects the HFOSC/32 clock
6 Reserved
7 Reserved
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–31
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-10: CLKG_CLK_CTL2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 HFOSCAUTODIV_EN
(R/W)
HF Oscillator auto divide by one clock selection during wakeup from Flexi power
mode.
Used to enable the fast wakeup from Flexi power mode.
1: Fast wake-up from Flexi mode is enabled
0: Fast wake-up from Flexi mode is disabled
When the fast wakeup from Flexi mode is enabled, the frequency undivided 26 MHz
HFOSC clock itself will be used during the wake up.
The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL bit, which selects the HFOSC/1 clock. This updated divided by 1 clock
selection remains same until the new divider value is written to this register.
If this bit is 0, fast wake-up feature will be disabled and the HFOSCDIVCLKSEL bit
remains unchanged during wake up.
0 Auto select HFOSC/1 clock during wakeup from Flexi
mode is disabled
1 Auto select HFOSC/1 clock during wakeup from Flexi
mode is enabled
6–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
System PLL
Clock Control 3 is used to control the system PLL. This register should be written to only when the PLL is not
selected as the clock source (ROOT_CLK). All unused bits are read only, returning a value of 0. Writing to unused
bits has no effect.
15 14 13 12 11 10 9
0
1
1
0
1
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
0
SPLLMSEL (R/W)
System PLL M Divider
SPLLNSEL (R/W)
System PLL N multiplier
SPLLIE (R/W)
System PLL interrupt enable
SPLLDIV2 (R/W)
System PLL division by 2
SPLLEN (R/W)
System PLL enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPLLMUL2 (R/W)
System PLL multiply by 2
Figure 6-14: CLKG_CLK_CTL3 Register Diagram
Table 6-11: CLKG_CLK_CTL3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
16 SPLLMUL2
(R/W)
System PLL multiply by 2.
Used to configure if the VCO clock frequency is multiplied by 2 or 1.
0 PLL out frequency = SPLLNSEL * 1 / ((SPLLDIV2+1)
* SPLLMSEL)
1 PLL out frequency = SPLLNSEL * 2 / ((SPLLDIV2+1)
* SPLLMSEL)
14:11 SPLLMSEL
(R/W)
System PLL M Divider.
System PLL M Divider. Sets the M value used to obtain the multiplication factor N/M
of the PLL. if CLKG_CLK_CTL3.SPLLMSEL <= 2, Divider M value = 2
For example,
0000: M set to 2 (Div by 2)
0001: M set to 2 (Div by 2)
0010: M set to 2 (Div by 2)
0011: M set to 3 (Div by 3)
0100: M set to 4 (Div by 4)
1111: M set to 15 (Div by 15)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–33
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-11: CLKG_CLK_CTL3 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 SPLLIE
(R/W)
System PLL interrupt enable.
Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt
generated. This bit should not be cleared while a core interrupt is pending.
0 An interrupt to the core will not be generated on a PLL
lock or PLL unlock
1 An interrupt to the core will be generated on a PLL lock
or PLL unlock
9 SPLLEN
(R/W)
System PLL enable.
Controls if the PLL should be enabled or placed in its low power state. This bit should
only be set while the System PLL is not selected as the system clock source
(CLKG_CLK_CTL0.CLKMUX).
0 PLL is disabled and in power down state
1 PLL is enabled. Initially the PLL will not run at the selected frequency. After a stabilization period the PLL
will lock onto the selected frequency at which time it
can be selected as a system clock source (CLKMUX
bits)
8 SPLLDIV2
(R/W)
System PLL division by 2.
Controls if an optional divide by two is placed on the PLL output. This will guarantee
a balanced output duty cycle output at the cost of doubling the PLL frequency (power). This bit should not be modified after CLKG_CLK_CTL3.SPLLEN is set. This
bit can be written at the same time CLKG_CLK_CTL3.SPLLEN is set.
This bit is set or reset based on the following constraints:
1. VCO output range is 32 MHz to 60 MHz
2. SPLL output range is 16 MHz to 60 MHz
It is set by default.
0 The System PLL is not divided. Its output frequency
equals that selected by the N/M ratio
1 The System PLL is divided by two. Its output frequency
equals that selected by the N/M ratio with an additional /2 divide
4:0 SPLLNSEL
(R/W)
6–34
System PLL N multiplier.
Sets the N value used to obtain the multiplication factor N/M of the PLL. The default
value is 0b011010 (Mult by 26). Minimum valid value is 8 and writing any value less
than 8 will force it to be 8. Maximum valid value is 31. Do not program the SPLL to
an output clock lower than 16 MHz or higher than 60 MHz.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
User Clock Gating Control
Clock Control 5 is used to control the gates of the peripheral UCLKs.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
0
1
1
1
1
1
TMRRGBCLKOFF (R/W)
Timer RGB user control
GPTCLK0OFF (R/W)
GP Timer 0 user control
PERCLKOFF (R/W)
This bit is used to disable all clocks
connected to all peripherals
GPTCLK1OFF (R/W)
GP Timer 1 user control
GPTCLK2OFF (R/W)
GP Timer 2 user control
GPIOCLKOFF (R/W)
GPIO clock control
UCLKI2COFF (R/W)
I2C clock user control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-15: CLKG_CLK_CTL5 Register Diagram
Table 6-12: CLKG_CLK_CTL5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
6 TMRRGBCLKOFF
(R/W)
Timer RGB user control.
This bit disables the Timer RGB (muxed version). It controls the gate on the Timer
RGB clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the
Timer RGB clock is always off, and this bit has no effect.
Note: Automatically clear this bit if Timer RGB is accessed via the APB bus.
0 TMRRGB clock is enabled
1 TMRRGB clock is disabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–35
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-12: CLKG_CLK_CTL5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 PERCLKOFF
(R/W)
This bit is used to disable all clocks connected to all peripherals.
This is useful to save power during following cases:
(i) Processor is not working with any peripherals for a given time.
(ii) DMA transactions like SRAM to SRAM copy or FLASH to SRAM copy (or vice
versa).
When this bit is set, following blocks are active:
GPIO, Flash, DMA, Cortex, and SRAM
System status registers for supply monitors, Clock source monitors:
0: Clocks to peripherals are active.
1: Clocks to following peripherals are gated off: SPI, SPORT, CRC, AES, SPI, I2C,
UART, Timers, APB16 bridges, PCLK divider, PM, and CLK register map.
After setting this bit, any read/write to any of the above module register will automatically reset the PERCLKOFF to 0, and that read/write transaction is honored.
Only exception is, after setting this bit to 1, user can read CLKG_CLK_CTL5 register.
This bit will not be automatically cleared in this case.
Recommended usage before setting PERCLKOFF bit:
1. Ensure that DMA transactions are done and no more transaction is expected from
DMA.
2. Ensure that this bit write is last write. And no write/read to any of above module
registers is done after setting this bit. Otherwise, this bit will be cleared.
0 Clocks to peripherals are active
1 Clocks to following peripherals are gated off: SPI,
SPORT, CRC, AES, I2C, UART,Timers, APB16
bridges, PCLK divider, PM and CLK register map.
4 GPIOCLKOFF
(R/W)
GPIO clock control.
This bit disables the ACLK. It controls the gate on the ACLK out from ACLK Divider. This ACLK control is in Active and Flexi modes. In Hibernate and Shutdown
modes, the ACLK is always off, and this bit has no effect.
Note: The bit is not automatically cleared. User has to explicitly enable or disable this
bit to control ACLK out.
Before programming CLKG_CLK_CTL1.ACLKDIVCNT register, this bit
(CLKG_CLK_CTL5.GPIOCLKOFF) needs to be cleared to 0. Otherwise, the
CLKG_CLK_CTL1.ACLKDIVCNT is not taken into effect.
0 GPIO Clock is enabled
1 GPIO Clock is disabled
6–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-12: CLKG_CLK_CTL5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 UCLKI2COFF
(R/W)
I2C clock user control.
This bit disables the I2C UCLK. It controls the gate on the I2C UCLK in Active and
Flexi modes. In Hibernate and Shutdown modes the I2C UCLK is always off, and this
bit has no effect. Note: will automatically clear this bit if I2C is accessed via the APB
bus.
0 I2C Clock is enabled
1 I2C Clock is disabled
2 GPTCLK2OFF
(R/W)
GP Timer 2 user control.
This bit disables the gptclk2 (muxed version). It controls the gate on the GP Timer 2
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT2 is accessed via the APB bus.
0 TMR2 clock is enabled
1 TMR2 clock is disabled
1 GPTCLK1OFF
(R/W)
GP Timer 1 user control.
This bit disables the gptclk1 (muxed version). It controls the gate on the GP Timer 1
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT1 is accessed via the APB bus.
0 TMR1 clock is enabled
1 TMR1 clock is disabled
0 GPTCLK0OFF
(R/W)
GP Timer 0 user control.
This bit disables the gptclk0 (muxed version). It controls the gate on the GP Timer 0
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect.
Note: Automatically this bit is cleared, if GPT0 is accessed via the APB bus.
0 TMR0 clock is enabled
1 TMR0 clock is disabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–37
ADuCM4050 CLKG_CLK Register Descriptions
Clocking Status
Clock Status is used to monitor PLL and Oscillator status. With interrupts enabled the user is free to continue to
run initialization code or idle the core while clock components stabilize.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HFXTALNOK (R/W1C)
HF crystal not stable
SPLL (R)
System PLL status
HFXTALOK (R/W1C)
HF crystal stable
SPLLLK (R/W1C)
System PLL lock
HFXTAL (R)
HF crystal status
SPLLUNLK (R/W1C)
System PLL unlock
LFXTALNOK (R/W1C)
LF crystal not stable
LFXTAL (R)
LF crystal status
LFXTALOK (R/W1C)
LF crystal stable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-16: CLKG_CLK_STAT0 Register Diagram
Table 6-13: CLKG_CLK_STAT0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 HFXTALNOK
(R/W1C)
HF crystal not stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, an
interrupt can be associated with this bit.
0 HF crystal stable signal has not been de-asserted.
1 HF crystal stable signal has been de-asserted.
13 HFXTALOK
(R/W1C)
HF crystal stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 HF crystal stable signal has not been asserted.
1 HF crystal stable signal has been asserted.
6–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-13: CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 HFXTAL
(R/NW)
HF crystal status.
This bit assists in determining when the XTAL is initially stable and ready to use. This
bit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 HF crystal is not stable or not enabled.
1 HF crystal is stable.
10 LFXTALNOK
(R/W1C)
LF crystal not stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, an
interrupt can be associated with this bit.
0 LF crystal stable signal has not been de-asserted.
1 LF crystal stable signal has been de-asserted.
9 LFXTALOK
(R/W1C)
LF crystal stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 LF crystal stable signal has not been asserted.
1 LF crystal stable signal has been asserted.
8 LFXTAL
(R/NW)
LF crystal status.
This bit assists in determining when the XTAL is initially stable and ready to use. This
bit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 LF crystal is not stable or not enabled.
1 LF crystal is stable
2 SPLLUNLK
(R/W1C)
System PLL unlock.
This bit is sticky. CLKG_CLK_STAT0.SPLLUNLK is set when the PLL looses its
lock. CLKG_CLK_STAT0.SPLLUNLK is used as the interrupt source to signal the
core that a lock was lost. Writing a one to this bit clears it.
CLKG_CLK_STAT0.SPLLUNLK will not set again unless the System PLL gains a
lock and subsequently loses again.
0 No loss of PLL lock is detected
1 A PLL loss of lock is detected
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
6–39
ADuCM4050 CLKG_CLK Register Descriptions
Table 6-13: CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 SPLLLK
(R/W1C)
System PLL lock.
This bit is sticky. CLKG_CLK_STAT0.SPLLLK is set when the PLL locks.
CLKG_CLK_STAT0.SPLLLK is used as the interrupt source to signal the core that a
lock is detected. Writing a one to this bit clears it. CLKG_CLK_STAT0.SPLLLK
will not set again unless the System PLL looses lock and subsequently locks again.
0 No PLL lock event is detected
1 A PLL lock event is detected
0 SPLL
(R/NW)
System PLL status.
Indicates the current status of the PLL. Initially the System PLL will be unlocked. After a stabilization period the PLL will lock and be ready for use as the system clock
source. This is a read only bit. A write has no effect.
0 PLL is not locked or not properly configured. The PLL
is not ready for use as the system clock source.
1 PLL is locked and is ready for use as the system clock
source.
6–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Reset (RST)
7 Reset (RST)
The ADuCM4050 MCU has the following resets:
• External
• Power-on
• Watchdog timeout
• Software system
The software system reset is provided as part of the Cortex-M4F core.
To generate a system reset through software, the application interrupt/reset control register must be set to a value of
0x05FA0004. This register is part of the NVIC subsystem and is located at address 0xE000ED0C.
For more information about software reset, refer to the ARM Cortex-M4F Technical Reference Manual.
A hardware reset is performed by toggling the SYS_HWRST pin, which is active low.
The PMG_RST_STAT register indicates the source of the last reset. The register can be used during a reset exception service routine to identify the source of the reset.
Table 7-1: Reset Types
Reset
Reset External Pins
to Default
State
Execute
Kernel
Reset All MMRs Except
PMG_RST_STAT
Reset All Pe- Valid SRAM
ripherals
Software
Yes*1
Yes
Yes
Yes
Yes/no*2
PMG_RST_STAT.SWRST = 1
Watchdog
Yes
Yes
Yes
Yes
Yes/no*2
PMG_RST_STAT.WDRST = 1
External reset pin Yes
Yes
Yes
Yes
Yes/no*2
PMG_RST_STAT.EXTRST = 1
POR
Yes
Yes
Yes
No
PMG_RST_STAT.POR = 1
Yes
PMG_RST_STAT After Reset
Event
PMG_RST_STAT.PORSRC has
info on cause of POR reset
*1
GPIOx returns to its default state, that is, same as a POR event.
*2
RAM is not valid in the case of a reset following a UART download.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
7–1
ADuCM4050 Reset Register Description
ADuCM4050 Reset Register Description
Table 7-2: ADuCM4050 Reset Register List
Name
Description
Reset
Access
PMG_RST_STAT
Reset Status
0x000000XX
R/W
7–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 Reset Register Description
Reset Status
This register is recommended to be read at the beginning of the user code to determine the cause of the reset. Default values of this register is unspecified as the cause of reset can be any source.
15 14 13 12 11 10
9
8
7
6
5
0
0
0
0
0
X X X X X X
0
0
0
0
0
4
3
2
1
0
PORSRC (R)
Power on reset Source
POR (R/W)
Power-on reset
SWRST (R/W)
Software reset
EXTRST (R/W)
External reset
WDRST (R/W)
Watchdog timeout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-1: PMG_RST_STAT Register Diagram
Table 7-3: PMG_RST_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 PORSRC
(R/NW)
Power-on-Reset Source.
This bit contains additional details after a Power-on-Reset occurs.
0 POR triggered because VBAT drops below Fail Safe
1 POR trigger because VBAT supply (VBAT < 1.7 V)
2 POR triggered because VDD supply (VDD < 1.08 V)
3 POR triggered because VREG drops below Fail Safe
3 SWRST
(R/W)
2 WDRST
(R/W)
1 EXTRST
(R/W)
0 POR
(R/W)
Software Reset.
Set automatically to 1 when the system reset is generated. Cleared by writing 1 to the
bit. This bit is also cleared when power-on-reset is triggered.
Watchdog Time-out Reset.
Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to the
bit. This bit is also cleared when power-on-reset is triggered
External Reset.
Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit.
This bit is also cleared when power-on-reset is triggered
Power-on-Reset.
Set automatically when a Power-on-Reset occurs. Cleared by writing one to the bit.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
7–3
Flash Controller (FLASH)
8 Flash Controller (FLASH)
The ADuCM4050 MCU includes 512 KB of embedded flash memory available for access through the flash controller. The embedded flash has a 72-bit wide data bus providing two 32-bit words of data and one corresponding 8bit ECC byte per access.
The flash controller is coupled with a cache controller module, which provides two AHB ports:
• DCode for reading data
• ICode for reading instructions
A prefetch mechanism is implemented in the flash controller to optimize ICode read performance.
Flash writes are supported by a key hole mechanism through APB writes to memory mapped registers. The flash
controller includes support for DMA based key hole writes.
Flash Features
The flash memory used by the ADuCM4050 MCU has the following features:
• Prefetch buffer provides optimal performance when reading consecutive addresses on the ICode interface.
• Simultaneous ICode and DCode read accesses (DCode has priority on contention; simultaneous reads are possible if ICode returns buffered data from prefetch).
• DMA based key hole writes (including address auto-increment for sequential accesses).
• ECC for error detection and/or correction. Errors and corrections may be reported as Bus Errors (on the
ICode/DCode buses), interrupts, or ignored.
Supported Commands
• Read: Supported through the ICode and DCode interfaces.
• Write: Provided by a key-hole mechanism through memory mapped registers.
• Mass erase: Clears all user data and program code.
• Page erase: Clears user data and/or program code from a 2 KB page in flash.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–1
Flash Features
• Signature: Generate and verify signatures for any set of contiguous whole pages of user data and/or program
code.
• Abort: Terminate a command in progress.
Protection and Integrity Features
• Fixed user key required for running protected commands including mass erase and page erase.
• Optional and user definable Write protection for user accessible memory.
• Optional 8-bit Error Correction Code (ECC): May be enabled by user code (off by default).
Flash Functional Description
This section provides information on the flash memory functions used by the ADuCM4050 MCU.
Organization
The flash IP provides a 64-bit data bus and 8 bits for ECC meta data corresponding to that data. The memory is
organized as a number of pages, each 2 KB in size plus 256 bytes reserved for ECC.
One Page
ECC
256B
Data
2KB
8 bits
64 bits
256
Figure 8-1: One Page of Flash Memory
These pages of memory are categorically divided into two sections: Info Space and User Space. Total device storage
is generally described as the size of User Space.
8–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Flash Functional Description
Info Space
4 KB
2 pages
User Space
512 KB
256 Pages
Figure 8-2: Flash Info and User Spaces
Info Space is reserved for use by Analog Devices and generally stores a boot loader (kernel), several trim and calibration values, and other device specific meta data. Most of info space is left readable by user code but attempted erasures and writes are denied.
User Space is the portion of flash memory intended for user data and program code. Several small address ranges in
user space are used by the flash controller as meta data to enable various protection and integrity features.
Info Space
User Accessible Data
While Info space is generally reserved for use only by Analog Devices, all but the top 256 bytes of info space are
readable by user code. A 64-bit Manufacture ID is located at the address 0x80EE4 . The ADI secure bootloader is
responsible to place the Manufacture ID on this location. Other potential read-only data may be made available to
the user within the scope of the info space. Such meta data is software defined, therefore the addresses and data types
are not defined by the flash controller.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–3
Flash Functional Description
Info Space
32
0xFFC
Reserved
0xFFC
...
...
...
...
Reserved
Reserved
Range
0xFF0
128 bytes of protected data in info space.
All other info space addresses are read-only.
0x000
Figure 8-3: User Readable Locations in Info Space
The top 256 bytes of info space are protected and cannot be read by user code (attempted reads return bus errors).
The remainder of the info space is freely readable by user code. None of info space may be programmed or erased by
the user (command is denied).
Bus errors are generated if user code attempts to read the protected range of info space. Writes and Erases targeting
info space are denied and appropriate bits are set in the FLCC_STAT register.
User code may perform a Mass Erase command on the part without affecting the content of the Info Space. This
provides a mechanism to upload new user firmware and data to a device without affecting ADIs secure boot loader.
User Space
User Space is the portion of flash memory intended for user data and program code. Several small address ranges in
user space are used by the flash controller as meta-data to enable various protection and integrity features.
Protected Key Storage
The top two pages of User Space are reserved for use as a Protected Key Storage region. These two pages exist inside
the physical User Space but are neither directly accessible to the user nor controlled by any of the user facing flash
controller features (such as Write Protection).
8–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Flash Functional Description
Protected Key Space
4 KB
2 pages
Available User Space
508 KB
254 Pages
Figure 8-4: Dedicated Pages Reserved for Protected Key Storage (Parts with 512 KB User Space)
All user access and control functions for the Protected Key Storage region are provided by the Cryptographic module.
Any attempts to access this region, directly generates appropriate failures:
• Commands: Command issued which targets this region will result in a command failure code in the status register and will have no effect on the flash memory.
• ICode: Any attempt to branch to this memory region as instruction code will result in bus faults and will otherwise not cause the flash controller to access the requested address.
• DCode: Any attempt to read this region as direct AHB memory reads will result in bus faults and will otherwise not cause the flash controller to access the requested address.
Meta Data
ADI secure bootloader enforces various security features which are controlled by the user through writing metadata
into software defined locations of User Space.
There are two types of metadata that specifically affect the flash controller: CRC checksums and Write Protection
settings.
• Write Protection: Flash address 0x0000_019C
ADI secure bootloader defines a single address from which it will consume a value and store it into the
FLCC_WRPROT register of the flash controller prior to user code executing. User may populate this flash location with whatever default FLCC_WRPROT value is desired.
Avoid corrupting the ECC byte associated with the FLCC_WRPROT word in flash by refraining from writing
the adjacent flash word at 0x0000_0198.
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Flash Functional Description
• CRC Checksums: Flash address 0x0000_07FC
The most significant word of each flash page may be used to store a CRC Checksum, also known as a Signature. The flash controller implements a sign checking feature such that software may request the signature for
any contiguous set of whole pages to be verified; the expected signature must be stored by user code in the most
significant word of the region over which the signature is calculated.
ADI secure bootloader enforces signature checking from page zero through a user defined end-page prior to
executing user code. The bootloader consumes metadata from page zero of user space to determine the endpage used in signature verification. This value is known as User Code Length and is stored at address
0x0000_0194.
Store a value in the range 0 through 127 to the User Code Length address, indicating the end-page used for
signature generation. User must also populate the required signature value in the most significant word of the
end-page indicated.
The signature address is calculated as:
SIG_ADR=[(PageID+1)*(0x800)-4]
where, PageID is the value stored to User Code Length.
For example, if PageID=0, SIG_ADR is 0x7FC.
Avoid corrupting the ECC byte associated with signature values by refraining from writing the adjacent flash
word at [SIG_ADR-4].
Flash Access
Two pages of flash memory are reserved as a dedicated protected key storage region. All access to this region is performed indirectly through the cryptographic block. Access to all other regions of flash memory are performed directly through the flash controller through one of three interfaces: ICode, DCode, and APB.
These two access methods (direct and indirect) only affect the APB interface and are implemented in a mutually
exclusive manner to maintain coherency in software and provide required security features for the protected key storage region.
Table 8-1: Indirect Access Vs Direct Access
Register
Direct Access
Indirect Access
Status Register
R/W
Read-only
Other Registers
R/W
No access
In indirect access mode, user code may read the status register but register writes or reads of other registers are not
enabled. Attempt to write to any register has no effect. Read to any register other than the status register returns a
static data not related to the flash controller.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Flash Functional Description
ICode and DCode interfaces are not affected by active access mode. These interfaces are logically part of direct access mode but normally continue servicing direct access reads at all times.
When IDLE, the flash controller is effectively in direct access mode. Indirect accesses are requested by user code
through register writes in the Cryptographic block. The flash controller switches between direct and indirect access
modes only. It is otherwise IDLE (at the completion of any pending command). Therefore, indirect access requests
are stalled when the flash controller is busy executing a direct access command.
User code must treat indirect accesses as a critical software region only to be executed when the flash controller.
Otherwise, it is not be expected to service any APB traffic (reads or writes of memory mapped registers including the
command register used to write, program, or erase flash memory). The most significant bit of the Status register
indicates the current access mode (0x0=Direct).
Indirect Access: Protected Key Storage
User Space includes a pair of pages reserved for use as a protected key storage region. User access to these pages is
provided only indirectly via the Cryptographic module. User code may perform any of the following operations in
this region:
• WRITE: Store a key to the dedicated key storage region
• DESTROY: Destroy a single key in the dedicated key storage region
• READ: Retrieve a single key from the dedicated key storage region
• ERASE: Perform a page erase operation on either page in this dedicated region
While the cryptographic module services any of the above requests, the flash controller continues to service ICode
and DCode requests, stalling as required while the flash memory is busy and therefore enabling user code to transparently execute from flash memory while interacting with the key storage region.
If indirect access is made to the protected key storage region while the flash controller is in sleep mode, the flash
controller automatically wakes up to process the request. User code has to return the flash controller to sleep mode,
if required.
While indirect protected key storage accesses are being serviced the flash controller ignores the ABORT_EN register
settings. Indirect flash accesses cannot be aborted by user code or interrupts. It is suggested that user code utilize
semaphores or equivalents to treat indirect flash accesses as critical code segments during which no other flash accesses is attempted. ICode and DCode direct accesses are serviced during indirect accesses but performance may be
reduced.
The flash controller’s status register is automatically cleared while servicing indirect accesses.
Direct Access
Flash memory may be read, written, and erased by user code. Read access is provided through dedicated instruction
and data memory busses via the cache controller. Write access is provided through key hole writes via memory mapped registers including support for DMA based writes.
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Flash Access
Read Path
AHB icode
AHB dcode
Cache
Controller
Custom Interface
Flash
Controller
APB
Write Path
Figure 8-5: Read and Write Data Paths
Bus errors are generated if user code reads from a protected or out of bounds address. Writes or Erasures of protected
addresses result in appropriate error flags set in the FLCC_STAT register. Address setup for writes and erasures is
automatically constrained to the flash address range.
Reading Flash
The flash controller provides two interfaces for reading non-volatile storage: ICode and DCode.
The ICode and DCode interfaces are accessed through the cache controller module through AHB. The flash controller includes a prefetch buffer for ICode. Due to this prefetch buffer, it is possible to return data on both ICode
and DCode interfaces in the same cycle.
Flash memory is available to be read only after an automatic initialization process. Attempts to read during the flash
controller initialization will stall. Reads also stall if the flash controller is already busy performing another command
(for example, writing the flash) unless those reads are satisfied by the prefetch buffer.
Erasing Flash
The flash controller provides page-level granularity when erasing user space (ERASEPAGE command). Alternatively,
user code may erase the entirety of user space at once (MASSERASE command). The two commands have the same
execution time.
Write protected pages cannot be erased; the command would be denied. If any pages are write protected, a mass
erase command is also be denied. Users wishing to write protect user space and planning to perform mass erases (for
example, for future firmware upgrades) must take this into consideration.
Writing Flash
Flash memory operates by setting bits to 1 when erased, and clearing them to 0 when writing data. Any generalized
write accesses must be prefixed by an Erase operation.
Initial uploading of user content generally occurs immediately following a Mass Erase operation.
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Flash Access
Subsequent modifications of already-written locations in the flash involve the following operations by the user code:
• Copying a full page to SRAM
• Erasing the affected page
• Modifying the in-memory content
• Writing the page back to flash
User Space protections may prevent a page erase operation. For more information about this, refer to Protection and
Integrity.
All User Space protections are cleared automatically after a successful Mass Erase or Blank Check (a blank check
passes only if the entire user space is already erased). In these two cases, there is no user space content to protect.
Key Hole Writes
A key hole write is an indirect write operation where the user code programs the memory mapped registers with
target Address and Data values, then commands the flash controller to perform a write operation in the background.
The flash controller supports Write access to the flash memory only through key hole writes. This constraint on
Write access enables the flash controller to guarantee that writes occur properly as atomic DWORD (64-bit) operations with an associated ECC byte, if ECC is enabled. For more information about this, refer to ECC.
If ECC is enabled, multiple writes to a single DWORD (64-bit) location cannot be performed without erasing the
affected page between writes else ECC errors are reported.
A maximum of two total writes are permitted to a single flash location (64-bit DWORD) between erasures (regardless of ECC or data values), as per the flash IP specifications. Writing any location more than twice per erasure may
damage the non-volatile memory or reduce its life. If multiple writes per location are required, user code must disable ECC for some region of flash and target that region for these write operations.
Key hole operations consist of writes to:
• FLCC_KH_ADDR.VALUE: The target address in flash (for example, 0x104). The flash controller automatically trims the lower bits to make the address DWORD aligned.
• FLCC_KH_DATA0.VALUE: Bits [31:0] of the 64-bit DWORD to be written (for example, 0x7654_3210).
• FLCC_KH_DATA1.VALUE: Bits [63:32] of the 64-bit DWORD to be written (for example,
0xFEDC_BA98).
• FLCC_CMD.VALUE: Assert the write command (0x4) in the flash.
After the write command is asserted, the flash controller initiates a 64-bit dual word write to the address provided in
FLCC_KH_ADDR.VALUE.
Word (32-bit), Halfword (16-bit), and Byte (8-bit) writes are not supported. As only 0s are written to the flash,
masking may be used to write individual bits or bytes (as per ECC and flash IP specifications).
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Flash Access
User code must not write to any of these key hole registers when DMA access is enabled (FLCC_UCFG.KHDMAEN
is set). Writing to these registers manually when DMA is enabled may result in spurious flash writes and can put the
DMA and flash controller out of sync, potentially hanging the DMA controller for long duration (~20 to 40 μs).
Burst Writes
Each 2 KB page of flash memory consists of eight rows, 256 bytes each. Design constraints for programming the
flash IP enable back-to-back writes within a single row to complete more quickly than the equivalent writes across
row boundaries. For optimizing writes, user code must attempt to write flash memory in (aligned) blocks of up to
256 bytes.
Table 8-2: Flash Addressing by Rows
0x7FFFC
0x7FFF8
...
0x7FF04
0x7FF00
...
...
...
...
...
0xFC
0xF8
...
0x4
0x0
To benefit from this write-performance gain, the second (and subsequent) 64-bit write must be requested before the
flash controller completes the first write. The flag FLCC_STAT.WRALCOMP is set when the first 64-bit write operation is nearing completion (~20 μs remaining in the write cycle). This provides user code with a manageable window of time in which to assert the next write request. This flag may be polled or an interrupt may optionally be
generated when it is asserted.
The following status flags are also available:
• FLCC_STAT.CMDBUSY: High when the controller is processing a command from the FLCC_CMD register.
• FLCC_STAT.WRCLOSE: High during the first half of a write command, cleared when key hole registers are
free to be programmed for a subsequent write command.
• FLCC_STAT.CMDCOMP: Sticky flag, set when a command is completed (write, erase and so on). Write one
to clear.
• FLCC_STAT.WRALCOMP: Sticky flag, set when ~20-40 μs remains for an ongoing write command. Write
one to clear.
The following steps describe how to perform multiple writes with the potential to burst within a row:
• Wait for command busy flag to clear (to ensure on prior command is ongoing).
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1,
and FLCC_CMD registers are not interrupted by an ISR which might also have flash writes.
• Request first 64-bit write through the key hole access.
• The flash controller starts the write process after the write command is written to the FLCC_CMD register.
• Check if the write command is accepted (read FLCC_STAT register to see if any error flags are set. If the command results in an error, the write is not performed).
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Flash Access
• Set the FLCC_IEN.WRALCMPLT bit (to enable interrupt generation when WrAlComp is asserted) and reenable other interrupts.
• Continue the user program. WrAlComp interrupt will vector to an interrupt service routine to request the next
write at appropriate time.
• Burst Write ISR: Interrupt service routine (ISR) called when n interrupt is generated by WrAlComp.
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1,
and FLCC_CMD registers are not interrupted by another ISR which may also have flash writes.
• Read the FLCC_STAT register to verify the state of several status flags. Clear the flags by writing back the
same value:
• FLCC_STAT.WRALCOMP: The flag must be set indicating that there is still time for the next write to
occur for a Burst Write.
• FLCC_STAT.CMDBUSY: The flag must be set indicating that the current write operation is still on-going.
• FLCC_STAT.CMDCOMP: The flag must not be set. This bit indicates that a command had already completed and therefore the command currently in progress is not the earlier write command (another function has initiated a new command).
• FLCC_STAT.WRCLOSE: The flag must not be set. If set, the key hole registers are closed and cannot be
written. This flag must clear when FLCC_STAT.WRALCOMP is asserted.
• If no further writes are required, wait for FLCC_STAT.CMDCOMP to be set, clear it, and then exit the subroutine.
• Request the next 64-bit dualword write through the key hole access (write FLCC_KH_ADDR,
FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD registers).
• Check if the write command was accepted (read the FLCC_STAT register to see if any error flags are set).
• Re-enable interrupts.
• Exit the ISR.
If possible, user code with several write accesses to flash must be executed from SRAM to prevent thrashing the
flash. Write operations cause ICode reads to stall, resulting in degraded performance when ICode access is required
to fetch the next instruction (this may be partially alleviated by the cache controller).
Note that during a Burst Write, the flash controller overlaps the write operations and therefore any reported write
failures (for example, access denied due to write protection) may reflect the status of either of the two overlapped
writes. User code must interpret a Burst Write failure as a failure for both writes being overlapped (that is, both the
current and the prior write requests).
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Flash Access
DMA Writes
Key hole writes generally require writing four memory-mapped registers per flash write access. An optional address
auto-increment feature may reduce the APB traffic required per flash write transaction to three register writes
(FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD) for all but the first in a series of sequential writes (first
write requires setting up the start address). DMA Writes reduces the number of APB transactions to two: every pair
of FLCC_KH_DATA0 and FLCC_KH_DATA1 registers writes results in a single flash write command executing
and the address automatically incrementing to the next DWORD (regardless of the value of auto-increment, DMA
writes always increment in the address this manner).
To perform DMA based writes, user code must first configure the DMA controller (a separate peripheral module)
for basic access (this DMA mode supports transferring data to/from peripherals, including the flash controller).
Once the DMA controller module has been it will sit IDLE until a DMA_REQ signal is asserted by the flash controller.
The user code must manually write FLCC_KH_ADDR to setup the initial target address for DMA writes. The DMA
controller must be configured to write all output data to FLCC_KH_DATA1. Each pair of DMA writes to
FLCC_KH_DATA1 execute a single flash write command and wait for a corresponding delay before the next
DMA_REQ is made.
To start the flash controller process of requesting data from the DMA controller, the flash controller must be configured for DMA access. To enable DMA mode, user code must set the FLCC_UCFG.KHDMAEN bit.
Once the DMA mode is enabled (and flash controller is IDLE), the flash controller drives the DMA_REQ signal to
the DMA module. DMA_REQ is driven at the appropriate time to support Burst Writes (new requests are made
once the current write operation is nearly complete).
For more information about DMA functionality, refer to Direct Memory Access (DMA).
Command Abort
Some flash commands result in long-duration processes. For example, erasures may take 20-40 ms (depends on the
FLCC_TIME_PARAM0 register). A critical or time-sensitive event, such as a low-voltage alarm, may occur while
the flash controller is busy processing such a long-duration command. In such scenarios, it may be necessary for the
user to abort an ongoing flash command to properly handle the critical event.
Command abort should be used sparingly and as a last resort to satisfy critical time-sensitive events. Aborting any
flash command results in prematurely ending the current flash access and may result in corrupted flash data or, in
rare cases, damage to the flash array itself. The flash controller attempts to minimize the opportunity for data corruption of flash damage by aborting commands at opportune moments and such that internal high voltage is safely
drained prior to subsequent flash accesses. For this reason a command may complete successfully despite an attempt
to abort it.
Two mechanisms are provided to abort ongoing flash commands:
• Command Register
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Flash Functional Description
An abort command may be issued by writing the command register in the same manner used to issue any other
flash command. Once the abort command has been issued any ongoing command will be aborted at the next
opportune moment.
• System Interrupt Abort
The flash controller is sensitive to the system interrupt bus. User code may write to the IRQ Abort Enable
registers to program the flash controller to automatically abort any ongoing command in the event of a matching interrupt. The IRQ Abort Enable registers enable selecting any system IRQ from 0 through 63.
Protection and Integrity
Integrity of Info Space
User Code does not have any control over the content of Info Space. If this integrity check fails on a Power-onReset, it will be attempted repeatedly until a preset number of attempts has occurred or the integrity check passes
(this provides some recoverability from power faults occurring during device power-up). For all other resets (except
software reset which does not re-initialize the flash controller), the integrity check is attempted just once.
In the event of an info space integrity check failure, it is expected that the part has failed and will either be disposed
of or returned to ADI for failure analysis. If the Info Space integrity check does not pass, the flash controller enters a
special purpose debugging mode. In this mode, User Space protection is automatically asserted and the flash controller's local JTAG protection is set to allow JTAG (or other Serial Wire type interface) to interact with the ICode,
DCode and APB interfaces.
In this special purpose debugging mode:
• All ICode reads return Bus Errors (code is not executed from the flash memory without passing the integrity
check).
• All DCode reads to User Space returns Bus Errors.
• All DCode reads to Info Space except the top 256 bytes are permitted. Reads of the top 256 bytes return Bus
Errors.
• All write commands are denied (write attempts set the appropriate error bits in the FLCC_STAT register).
• User Space protections may be bypassed only by satisfying the security requirements.
The status of the signature check after reset is read from the FLCC_STAT.SIGNERR bit. The status of ECC during signature check is available in the FLCC_STAT.ECCINFOSIGN bit. These values are read through a normal
JTAG read if the JTAG interface is enabled.
User Space Protection
Two layers of user space protections are provided:
• Access Protection: Protects user space from all read or write operations. This protection mechanism may be
manually triggered but is typically automatically asserted in the event of system failure and/or the Serial Wire
Debug interface being enabled.
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Protection and Integrity
• Write Protection: User facing feature enabling blocks of user space pages to be protected against all write or
erase commands. May be set by user at runtime or by ADIs secure bootloader (user would store the desired
value in flash for the boot loader to consume during boot).
Access Protection
Access Protection is meant to prevent third parties from reading or tampering user data and program code through
JTAG or Serial Wire. Access Protection applies to the entirety of User Space. Access Protection is enabled by one of
the following events:
• Serial Wire Debug is enabled
• Flash Initialization (info space sign check) fails
The first two enabling mechanisms are automatic features; user code does not have to configure or enable anything
for these mechanisms to enable/enforce Access Protection.
While Access Protection is enabled all User Space reads return Bus Errors, writes are denied, and erases are subject to
the FLCC_WRPROT.WORD bit.
Access Protection may be bypassed by successfully executing a MASSERASE or BLANKCHECK command. Note
that the MASSERASE command is disallowed in the event that the FLCC_WRPROT (Write Protection) register has
been modified from its reset value. BLANKCHECK command is always permitted to execute but will only pass
successfully if all of User Space is already in an erased state.
Write Protection
User definable regions of User Space may be configured such that the flash controller will deny any attempts to
modify them (this affects both WRITE and ERASE commands). Write Protection may be configured at runtime or
may be stored in User Space meta-data to be loaded by the ADI secure bootloader during device boot.
NOTE: MASSERASE command is disallowed if any of the bits in the FLCC_WRPROT register have been modified
from the default value.
Runtime Configuration
Write Protection is configured by modifying the FLCC_WRPROT memory mapped register.
FLCC_WRPROT.WORD is a 32-bit wide bit field representing the Write Protection state for 32 similar size blocks of
User Space pages. For 512 KB parts the flash memory is divided into 256 pages of User Space storage. For Write
Protection, these are logically divided into 32 blocks of 8 pages (16 KB) each. Write Protection is independently
controlled for each of these 32 blocks; each bit of FLCC_WRPROT.WORD controls the protection mechanism for a
unique block of 8 pages of User Space. The least significant bits of FLCC_WRPROT.WORD correspond to the least
significant pages of User Space.
For parts with less User Space flash memory each bit of FLCC_WRPROT.WORD reflects a smaller number of pages,
always corresponding to 1/32 of the overall flash user space. A 256 KB part, for example, is divided into 32 blocks of
4 pages each with one bit of FLCC_WRPROT.WORD implementing write protection for each block.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Protection and Integrity
The bits in the FLCC_WRPROT register are active low. 0 represents active Write Protection and 1 represents no
protection for the corresponding block of pages. The FLCC_WRPROT register is sticky at 0. Once protection is enabled, it cannot be disabled without resetting the device.
User code may assert write protection for any block of pages by clearing the appropriate bit of
FLCC_WRPROT.WORD at any time. User must assert write protection as early as possible in user code. User must
also write-protect block zero (that is, flash pages 0-3) and place user boot and integrity checking code in this block
to fully control the write protection scheme without relying on ADI bootloader to setup the FLCC_WRPROT register.
Meta Data Configuration
User Space contains a single 32-bit field representing a set of 1-bit Write Protect flags for each of these 32 logical
blocks (see User Space), matching the functionality of the FLCC_WRPROT register.
These Write Protection bits are read from the flash by ADIs secure bootloader and stored in the FLCC_WRPROT
register after a reset operation. The default (erased) state of flash memory is all 1s, therefore the default
FLCC_WRPROT register value is to disable protection for all pages in User Space. Each bit of
FLCC_WRPROT.WORD corresponds to the protection state for one block of four User Space pages.
User code may clear bits in the write protection word from the user flash address (address 0x0000019C), also known
as WrProt meta data word at run time, or this word may be included in the initial upload of user data and program
code. Writing the WrProt meta data word at run time does not immediately affect the Write Protection state; if
immediate protection is required, user code should also write the same values to the FLCC_WRPROT register. When
writing the WrProt meta data the user should consider including Write Protection of the most significant page (thus
protecting the meta data from a page erase or other modification). As with all flash locations, repeated writes (without intermediate erasures) are discouraged and will likely cause ECC errors during read back.
Once protection has been enabled (corresponding bit has been cleared in FLCC_WRPROT.WORD) it cannot be disabled without resetting the device. For this reason, once Write Protection has been enabled for any block of pages
through the User Space meta data, it cannot be disabled without erasing the most significant page of User Space (the
page hosting the relevant meta-data) or otherwise affecting the flow of ADIs secure bootloader.
The following sequence outlines the process of programming the Write Protection meta data word in flash:
• Ensure that the FLCC_WRPROT address of the user space has been erased since the last time the meta-data is
written.
• Write the desired value for the WrProt meta-data word directly to flash (write '0' to a particular bit to enable
protection for the corresponding block). In 256 KB flash, this word is available at the address 0x3FFF0.
• Verify that the write completed successfully by polling the status register.
• If using CRC signature checking on the affected page, user code must program the signature
• Reset the device. The WrProt bits will automatically be uploaded by the ADI secure bootloader from user space
to the FLCC_WRPROT register and used to enforce the protection scheme.
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Protection and Integrity
Signatures
Signatures are used to check the integrity of the flash device contents. Signature calculations do not include the ECC
portion of the flash data bus nor the most significant word read from the set of pages being signed (this word is
considered meta data and is meant to hold the expected signature value for the given set of pages).
The flash controller implements its own stand-alone CRC engine for generating and verifying signatures. Note however that this implementation matches the CRC Accelerator peripheral (with an initial value of 0xFFFF_FFFF). For
more information about the CRC algorithm used, refer to Cyclic Redundancy Check (CRC).
Signatures may be included in the initial upload of user data and program code (generated before being uploaded),
or may be generated and stored to flash at runtime. Generation at runtime may utilize either the CRC Accelerator or
call the flash controller's signature generation logic.
ECC bytes correspond to 64-bit DWORDS in the flash memory, therefore if ECC is enabled the most significant
64 bits (including the 32-bit signature word) must be written all at once (else the ECC byte gets corrupted by the
second write). If using the flash controller to generate the signature value, leave the unused 32 bits paired with the
signature word in their erased state (0xFFFF_FFFF). Else, it may result in spurious ECC errors after device reset
(depending on FLCC_WRPROT configuration) and the device may become unusable.
The Sign command generates a signature for all data from the start page to the end page (excluding the signature
meta-data word). User code must define the start and end pages by writing FLCC_PAGE_ADDR0.VALUE and
FLCC_PAGE_ADDR1.VALUE respectively.
The following procedure must be followed to generate or verify a signature:
• Write to FLCC_PAGE_ADDR0.VALUE: Start address of a contiguous set of pages (if out of bounds, the command is denied).
• Write to FLCC_PAGE_ADDR1.VALUE: End address of a contiguous set of pages (if out of bounds, the command is denied).
• Write to FLCC_KEY.VALUE: Write the User Key value (0x676C7565) to the FLCC_KEY register.
• Write to FLCC_CMD.VALUE: Write the SIGN command (0x3) to the FLCC_CMD register.
• WAIT: When the command is completed, FLCC_STAT.CMDCOMP bit is set.
• If using the flash controller to generate a signature to write into the flash meta-data, the signature value
may be read from the FLCC_SIGNATURE register.
• The generated signature is automatically compared with the data stored in the most significant 32-bit
word of the region being signed. If the generated result does not match the stored value, a fail is reported
in the FLCC_STAT register by asserting verify error in the FLCC_STAT.CMDFAIL bit field (0x2).
While the signature is being computed all other accesses to the flash are stalled. Generating/verifying the signature
for a 512 KB block (full User Space) results in a stall duration of 64 KB flash reads (64 bits per read operation) or
approximately 128k HCLK periods.
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Protection and Integrity
NOTE: FLCC_PAGE_ADDR0.VALUE and FLCC_PAGE_ADDR1.VALUE addresses may be written as byte addresses but are consumed by the flash controller as page addresses (the lower 10 address bits are ignored). SIGN
command is denied if FLCC_PAGE_ADDR1.VALUE is less than FLCC_PAGE_ADDR0.VALUE. Signatures are
always performed at a page-level granularity over continuous address ranges.
Key Register
To prevent spurious and potentially damaging flash accesses, some commands and registers are key protected. The
User Key is not a security element and is not meant to be a secret. Instead, this key protects users from negative
consequences of software bugs (especially during early software development).
User Key
It prevents accidental access to some flash features and addresses. The key value is 0x676C_7565. This key must be
entered to run protected user commands (ERASEPAGE, SIGN, MASSERASE, and ABORT), or to enable write
access to the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers. Once entered, the
key remains valid until an incorrect value is written to the key register, or a command is written to the FLCC_CMD
register when any command is requested this key is automatically cleared. If this key is entered to enable write access
to the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers, clear the key immediately
after updating the register(s).
ECC
The flash controller provides ECC based error detection and correction for flash reads. ECC is enabled by default
for Info Space, and thus provides assurance that flash initialization functions work properly (info space signature
check unconditionally takes ECC into account).
The flash controller uses an 8-bit Hamming-modified code to correct 1-bit errors or detect 2-bit errors for any dualword (64-bit) flash data access.
When enabled, the ECC engine is active during signature checks (refer to Signatures section). User code may request
a signature check of the entirety of User Space then check the FLCC_STAT.ECCERRCMD bit to determine if any
single or dual bit data corruptions are present in User Space.
Defaults and Configuration
In User Space, ECC is off by default but may be selectively enabled by using the User code. Enabling ECC requires
setting the FLCC_ECC_CFG.EN bit. When enabled, ECC may apply to the entirety of User Space or may be configured to apply only to a limited range. A single page address pointer (FLCC_ECC_CFG.PTR) is used to define
the start address for ECC; all flash addresses from the start page through the top of User Space (inclusive) will have
ECC enabled when the FLCC_ECC_CFG.EN is set.
ECC errors may be optionally reported as bus errors for ICode or DCode reads, or may generate interrupts. Independent error reporting options are available for 1-bit corrections and 2-bit error detections by writing the
FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_CORRECT bits.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–17
Protection and Integrity
Error Handling
The impact of ECC errors during the information space signature check is described in Signatures. On any read
operation, if the ECC engine observes a 1 bit error it will be corrected automatically (the 1-bit error could be in the
ECC byte itself, or in the 64-bit dualword being read by the user). If a 2-bit error is observed the ECC engine can
only report the detection event (2-bit errors cannot be corrected).
Depending on when the read happens (for example, during an ICode or DCode read, or as part of a built-in command such as a signature check) appropriate flags are set in the status register (FLCC_STAT.ECCERRCMD,
FLCC_STAT.ECCRDERR, FLCC_STAT.ECCINFOSIGN, and so on).
If interrupt generation is enabled in the FLCC_IEN.ECC_ERROR/ FLCC_IEN.ECC_CORRECT bits, the source
address of the ECC error causing the interrupt are available in the FLCC_ECC_ADDR register for the interrupt
service routine to read.
ECC Errors during Sign Command Execution
ECC errors observed during signature checks generate the appropriate status register flags after completion but will
not populate the FLCC_ECC_ADDR register.
Concurrent Errors
If ECC errors occur on DCODE and ICODE simultaneously (for example, from an ICODE prefetch match and a
DCODE flash read), ECC error status information is prioritized as follows:
• First Priority: 2-bit ECC errors are given priority over 1bit ECC errors/corrections.
For example, if a 2-bit ECC error is observed on a DCODE read in the same cycle as a 1-bit ECC error/correction on an ICODE read, the ECC error status is updated for DCODE only.
• Second Priority: ICODE is given priority over DCODE.
For example, if a 2-bit error is observed on an ICODE read and a DCODE read in the same cycle, the ECC
error status is updated for ICODE only.
Read of Erased Location
When erased, the flash memory holds a value of all 1s, including the ECC byte appended to every 64-bit DWORD.
The proper ECC meta-data for 64 ONES is not 0xFF, therefore in its erased state the flash memory holds data and
ECC meta-data representing some number of bit errors.
For this reason any flash reads of erased locations will automatically bypass the ECC engine. If user code reads a
location with all 1s in both 64-bit DWORD and ECC byte, the read returns the data without indicating any ECC
errors.
8–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Protection and Integrity
Clock and Timings
The flash controller is preconfigured to provide safe timing parameters for all flash operations for core clock frequencies of 26 MHz (+/- 3%) or less and reference clock frequency of 13 MHz (+/- 3%).
If the reference and/or core clock is not within 3% of the mentioned frequencies user code must adjust the timing
parameters accordingly.
Flash accesses performed while core clock frequency is faster than 26 MHz (for example, 52 MHz) require user code
to first write to the FLCC_TIME_PARAM1 register to increase the WAITSTATES value from the default (0x0) to
0x1 or greater. This adjustment inserts one (or more) wait states into the read path of the flash memory. Failure to
add at least one wait state to the read path results in undefined behavior of the flash memory during reads at core
clock frequencies above 26 MHz (+/- 3%).
Flash Operating Modes
The flash memory used by the ADuCM4050 MCU supports the following power optimizing features:
Sleep Mode
The user code may put the flash IP into a low power sleep mode by writing the SLEEP command (0x2) to the
FLCC_CMD register. The flash controller wakes the flash IP from sleep automatically on the first flash access following a SLEEP command. The user code may observe the sleep state of flash by reading the
FLCC_STAT.SLEEPING bit.
NOTE: The cache controller, DMA reads, other peripheral, or user code may attempt to read flash memory at any
time, any of which will trigger a flash wakeup event; it is advisable that user code occasionally poll the
FLCC_STAT.SLEEPING bit to verify that the flash IP is still sleeping when the user expects it to be.
The flash controller does not honor new commands (WRITE, ERASE, and so on) while the flash IP is in sleep
mode; the only supported commands in this mode are IDLE and ABORT. DMA write requests will be stalled automatically by entering sleep mode.
System Interrupt based aborts (as configured through the FLCC_ABORT_EN_LO and FLCC_ABORT_EN_HI
registers) are generally used to abort any ongoing flash commands in the event of an enabled system interrupt. However, such an interrupt will not wake the flash from sleep mode. If the system interrupt can be serviced with accessing the flash, it remains in sleep mode; if servicing the interrupt requires accessing the flash then the flash access
itself will serve to wake the flash IP.
Waking from sleep incurs a ~5 μs latency before executing any reads or commands (this is a requirement of the flash
IP). User code may wake the flash IP early by executing an IDLE command. This will wake the flash IP without any
other effect on the controller.
For consistency, the ABORT command can also be used to wake the flash IP. Waking with the ABORT command
differs from waking by the IDLE command only in that the status register will report FLCC_STAT.CMDFAIL bit
(0x3) to match the expected user code checks for status register values.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–19
Clock Gating
Power-down Mode
The ADuCM4050 MCU automatically powers down the flash IP when the device hibernates. To support this feature, the flash controller interoperates with the power management unit and delays hibernation until any ongoing
flash accesses are completed. User code is responsible for reading and evaluating flash status registers prior to entering hibernate (status registers are not retained in hibernate). The abort command may be used to abruptly end an
ongoing flash command but must be used sparingly to avoid eventual damage to the flash array.
Clock Gating
A series of clock gates have been inserted into the flash controller to automatically gate off unused components of
the module. User configuration or control is not required. Unused portions of the flash controller is automatically
gated off when appropriate (for example, while in sleep mode the majority of the flash controller is gated off to save
power).
Flash Interrupts and Exceptions
The flash controller may selectively generate interrupts for several events. The following table outlines the events
that may generate interrupts and bit fields of FLCC_IEN used to control interrupt generation for each event.
Table 8-3: Interrupts and Bit fields
Name (Bit field)
Description
CMDFAIL
IRQ generated when a command or write operation completes with an error status.
WRALCOMP
IRQ generated when an active flash write is nearly complete and the key-hole registers are open
for another write (if fulfilled on-time, a Burst write occurs).
CMDCMPLT
IRQ generated when a command or flash write operation completes.
ECC_ERROR
IRQ generated when 2-bit ECC errors are observed when this field is set to 2.
ECC_CORRECT
IRQ generated when 1-bit ECC corrections are observed when this field is set to 2.
Flash Programming Model
The following section provides an example sequence to execute the Page erase command using the flash controller.
The same sequence can be used for other commands with some modifications.
Programming Guidelines
Here are the programming guidelines:
1. Program the FLCC_PAGE_ADDR0 or FLCC_PAGE_ADDR1 register with the address of the page which
needs to be erased.
2. Write the Flash User Key (0x676C7565) to the FLCC_KEY.VALUE bits.
3. Write the command to be executed into the FLCC_CMD register.
8–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
4. Poll for the FLCC_STAT.CMDCOMP bit to be set.
ADuCM4050 FLCC Register Descriptions
Flash Controller (FLCC) contains the following registers.
Table 8-4: ADuCM4050 FLCC Register List
Name
Description
FLCC_ABORT_EN_HI
IRQ Abort Enable (Upper Bits)
FLCC_ABORT_EN_LO
IRQ Abort Enable (Lower Bits)
FLCC_POR_SEC
Flash Security
FLCC_VOL_CFG
Volatile Flash Configuration
FLCC_CMD
Command
FLCC_ECC_ADDR
ECC Status (Address)
FLCC_ECC_CFG
ECC Configuration
FLCC_IEN
Interrupt Enable
FLCC_KEY
Key
FLCC_KH_ADDR
Write Address
FLCC_KH_DATA0
Write Lower Data
FLCC_KH_DATA1
Write Upper Data
FLCC_PAGE_ADDR0
Lower Page Address
FLCC_PAGE_ADDR1
Upper Page Address
FLCC_SIGNATURE
Signature
FLCC_STAT
Status
FLCC_TIME_PARAM0
Time Parameter 0
FLCC_TIME_PARAM1
Time Parameter 1
FLCC_UCFG
User Configuration
FLCC_WRPROT
Write Protection
FLCC_WR_ABORT_ADDR
Write Abort Address
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–21
ADuCM4050 FLCC Register Descriptions
IRQ Abort Enable (Upper Bits)
Upper bits of IRQ abort enable.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[47:32] (R/W)
Sys IRQ Abort Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[63:48] (R/W)
Sys IRQ Abort Enable
Figure 8-6: FLCC_ABORT_EN_HI Register Diagram
Table 8-5: FLCC_ABORT_EN_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
8–22
Sys IRQ Abort Enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign) write a 1 to the bit in this register corresponding with the desired system
IRQ number. Only the first 64 system IRQs are supported by this feature.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
IRQ Abort Enable (Lower Bits)
Lower bits of IRQ abort enable.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Sys IRQ Abort Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Sys IRQ Abort Enable
Figure 8-7: FLCC_ABORT_EN_LO Register Diagram
Table 8-6: FLCC_ABORT_EN_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
Sys IRQ Abort Enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign) write a 1 to the bit in this register corresponding with the desired system
IRQ number. Only the first 64 system IRQs are supported by this feature.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–23
ADuCM4050 FLCC Register Descriptions
Flash Security
Controls the flash security features.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SECURE (R/W1S)
Set this bit to prevent read or write
access to User Space (sticky when
set)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-8: FLCC_POR_SEC Register Diagram
Table 8-7: FLCC_POR_SEC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 SECURE
(R/W1S)
Set this bit to prevent read or write access to User Space (sticky when set).
Requires User key.
Once set, it cannot be cleared without resetting the device (POR or PIN reset only) or
erasing/verifying erased state of User Space (Blank Check or Mass Erase running successfully to completion).
It plays a direct role in User Space security enforcement. Once set, this bit prevents
access to User Space:
DCode Reads: Returns bus faults with the data bus == 0
ICode Reads: Returns bus faults with the data bus == 0
APB Writes: command will be denied, flash content unchanged
When set, user code may still perform Mass Erase and Page Erase operations.
Note: FLCC_WRPROT register still applies. Only unprotected pages may be erased
(Mass Erase is disallowed if any page is protected).
8–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Volatile Flash Configuration
This register resets on any/all resets (POR/PIN/SW/WDT). The User Key must be written to the KEY Register
prior to writing this register.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
INFO_REMAP (R/W1C)
Alias the info space to the base address
of user space
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-9: FLCC_VOL_CFG Register Diagram
Table 8-8: FLCC_VOL_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 INFO_REMAP
(R/W1C)
Alias the info space to the base address of user space.
When this bit is set, the boot loader is mirrored at address 0. This bit is automatically
cleared by the boot loader.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–25
ADuCM4050 FLCC Register Descriptions
Command
Write this register to execute a specified command. The user key must first be written to the FLCC_KEY register for
most command requests to be honored.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Commands
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-10: FLCC_CMD Register Diagram
Table 8-9: FLCC_CMD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 VALUE
(R/W)
Commands.
Write command values to this register to begin a specific operation. All commands but
write and idle require first writing the User Key to the FLCC_KEY register
0 IDLE
No key is required.
No command executed. If flash IP is in the sleep state,
this command wakes the flash (returns command complete and no error codes).
8–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-9: FLCC_CMD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 ABORT [User Key] is required.
ABORT command must be used sparingly as a last resort mechanism to gain access to the flash IP during
time-sensitive events. For example a low voltage alarm
may be cause to abort an ongoing flash write or erase
command to enable user code to shutdown the part
gracefully. Note that the flash array may be damaged by
over use of the ABORT command.
If this command is issued, any command currently in
progress will be abruptly stopped (if possible). The status will indicate command completed with an error of
ABORT.
ABORT is the only command that can be issued while
another command is already in progress (An exception is
that user code may stack one write command on top of
a single on-going write command. All other overlapping
command combinations are invalid unless the new command is an ABORT).
If a write or erase is aborted then some flash IP timing
requirements may be violated and it is not possible to
determine if the write or erase completed successfully.
User code should read the affected locations to determine the outcome of the aborted commands. Note that
an aborted command may result in a weakly programmed flash: it is always advisable to erase the affected region and reprogram it.
Depending on how far along the flash controller is in
the process of performing a command, an ABORT is
not always possible (some flash IP timing parameters
must not be violated). This is difficult (if not impossible) to predict in software, therefore, aborts must be
considered a request which may have no affect on actual
command duration.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–27
ADuCM4050 FLCC Register Descriptions
Table 8-9: FLCC_CMD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 Requests flash to enter Sleep mode [User Key] is required.
Requests the flash controller to put the flash to sleep (a
low power mode).
When in sleep, any ICode, DCode, or DMA transaction will wake the flash automatically.
Wake-up process takes ~5 us (configurable in
FLCC_TIME_PARAM1 register). If user code can predict ~5 us ahead of time that the flash will be required,
user may write an IDLE command to the FLCC_CMD
register to manually wake the flash. An ABORT command is also respected for waking the part (and will return appropriate status indicating that the sleep command was aborted).
Once awoken, the part remains awake until user code
once again asserts a SLEEP command.
3 SIGN [User Key] is required.
Use this command to generate a signature for a block of
data. Signatures may be generated for blocks of whole
pages only. The address of the start page should be written to the FLCC_PAGE_ADDR0 register, the address of
the end page written to the FLCC_PAGE_ADDR1 register, and then write this code to the FLCC_CMD register to start the signature generation. When the command has complete the signature will be readable from
the FLCC_SIGNATURE register.
4 WRITE No key is required.
This command takes the address and data from the
FLCC_KH_ADDR, FLCC_KH_DATA0, and
FLCC_KH_DATA1 registers and executes a single 64bit WRITE operation targeting the specified address.
8–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-9: FLCC_CMD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 Checks all of User Space; fails if any bits in user space
are cleared [User Key] is required.
Performs a blank check on all of user space. If any bits
in user space are cleared the command will fail with a
READ VERIFY status. If all of user space is FFs the
command will pass.
This command is intended to support early customer
software development. When an unprogrammed part
boots with security features preventing reads and writes
of user space, this command may be used to verify that
the user space contains no proprietary information. If
this command passes read and write protection of user
space will be cleared.
6 ERASEPAGE [User key] is required.
Write the address of the page to be erased to the
FLCC_PAGE_ADDR0 register, then write this code to
the FLCC_CMD register. When the erase has completed
the full page will be verified (read) automatically to ensure a complete erasure. If there is a read verify error this
will be indicated in the FLCC_STAT register. To erase
multiple pages wait until a previous page erase has completed check the status then issue a command to start
the next page erase.
7 MASSERASE [User key] is required.
Erase all of flash user space. When the erase has completed the full user space will be verified (read) automatically to ensure a complete erasure. If there is a read verify error this will be indicated in the Status register.
8 Reserved
9 Reserved
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–29
ADuCM4050 FLCC Register Descriptions
ECC Status (Address)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
This register has the address for which
ECC error is detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[19:16] (R)
This register has the address for which
ECC error is detected
Figure 8-11: FLCC_ECC_ADDR Register Diagram
Table 8-10: FLCC_ECC_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:0 VALUE
(R/NW)
8–30
This register has the address for which ECC error is detected.
This register is updated on ECC errors or corrections as selected to generate interrupts
(IRQ) in the FLCC_IEN register. this register is not updated in the event of an ECC
error or correction which instead generates a bus fault. This register records the address
of the first ECC error or correction event to generate an interrupt since the last time
the ECC status bits were cleared (or since reset). If the status bits are cleared in the
same cycle as a new ECC event (selected to generate an IRQ), a new address will be
recorded and the status bits will remain set. Errors have priority over corrections (2 or
more bits corrupt = ERROR; a correction results in proper data being returned after a
single bit is corrected). If an error and a correction occur in the same cycle, this register
will report the ERROR address. When two of the same priority ECC events occur
(both ERROR or both CORRECTION) the ICODE bus has priority over DCODE.
Therefore, if both ICODE and DCODE buses generate the same type of ECC event
in the same cycle, the ICODE address will be stored in this register. The register cannot be cleared except by reset. It will always hold the address of the most recently reported ECC correction or error.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
ECC Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
PTR[7:0] (R/W)
ECC start page pointer
EN (R/W)
ECC Enable
INFOEN (R/W)
Info space ECC Enable bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTR[23:8] (R/W)
ECC start page pointer
Figure 8-12: FLCC_ECC_CFG Register Diagram
Table 8-11: FLCC_ECC_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:8 PTR
(R/W)
ECC start page pointer.
User should write bits [31:8] of the start page address into bits [31:8] of this register.
A byte-address for any page in flash User Space. The bottom bits of this address will be
ignored by the flash controller, forming a Page Address.
When ECC is enabled and user code reads any address from within the page specified
or any more significant page, ECC functions will be performed. Reads from less significant pages will bypass ECC entirely.
1 INFOEN
(R/W)
0 EN
(R/W)
Info space ECC Enable bit.
ECC is enabled by default for Info Space. Clearing this bit disables ECC in info space.
This bit is not key protected.
ECC Enable.
Set this bit to enable ECC on User Space. ECC will be enabled on all future flash reads
in user space from any address between ECC_CFG:POINTER through the top of
User Space (inclusive).
When cleared (or accessing addresses outside the enabled range), the flash controller
will return the raw data in response to both ICode and DCode reads of User Space; no
error corrections will be made or reported.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–31
ADuCM4050 FLCC Register Descriptions
Interrupt Enable
Used to specify when interrupts is generated.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
0
ECC_ERROR (R/W)
Control whether to generate bus errors,
interrupts, or neither in response to
2-bit ECC Error events
CMDCMPLT (R/W)
Command complete interrupt enable
WRALCMPLT (R/W)
Write almost complete interrupt enable
ECC_CORRECT (R/W)
Control whether to generate bus errors,
interrupts, or neither in response to
1-bit ECC Correction events
CMDFAIL (R/W)
Command fail interrupt enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-13: FLCC_IEN Register Diagram
Table 8-12: FLCC_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 ECC_ERROR
(R/W)
Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC
Error events.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events
5:4 ECC_CORRECT
(R/W)
Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC
Correction events.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events
2 CMDFAIL
(R/W)
1 WRALCMPLT
Command fail interrupt enable.
If this bit is set, an interrupt is generated when a command or flash write completes
with an error status.
Write almost complete interrupt enable.
(R/W)
0 CMDCMPLT
(R/W)
8–32
Command complete interrupt enable.
If this bit is set, an interrupt is generated when a command or flash write completes.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Key
When user code must write a key to access protected features, the key value must be written to this register.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key register
Figure 8-14: FLCC_KEY Register Diagram
Table 8-13: FLCC_KEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
Key register.
Unlock protected features by writing the appropriate key value to this register
1735161189 USERKEY Write the UserKey to enable certain registers
to be modified or to allow certain commands to be executed. This key is used as a sanity check to prevent accidental modification of settings or flash content. It is not
a security component and is not intended to be secret
information.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–33
ADuCM4050 FLCC Register Descriptions
Write Address
Write the byte address of any byte of a 64-bit dual-word flash location to be targeted by a WRITE command. All
writes target 64-bit dual-word elements in the flash array. User code may byte-mask data to emulate byte, hword, or
word writes. Flash IP specifications warn that no location should be written more than twice between erasures.
When writing a location more than once, user should be aware that ECC meta-data cannot be updated appropriately; user code should disable ECC for the relevant region of flash. Writing any address above the valid range of flash
memory will saturate the address to prevent aliasing; user code should take care to target valid flash address locations.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[12:0] (R/W)
Address to be written on a WRITE command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[16:13] (R/W)
Address to be written on a WRITE command
Figure 8-15: FLCC_KH_ADDR Register Diagram
Table 8-14: FLCC_KH_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:3 VALUE
Address to be written on a WRITE command.
(R/W)
8–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Write Lower Data
The lower half of 64-bit dual word data to be written to flash.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE[15:0] (R/W)
Lower half of 64-bit dual word data
to be written on a Write command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VALUE[31:16] (R/W)
Lower half of 64-bit dual word data
to be written on a Write command
Figure 8-16: FLCC_KH_DATA0 Register Diagram
Table 8-15: FLCC_KH_DATA0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Lower half of 64-bit dual word data to be written on a Write command.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–35
ADuCM4050 FLCC Register Descriptions
Write Upper Data
Upper half of 64-bit dual word data to be written to flash.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE[15:0] (R/W)
Upper half of 64-bit dual word data
to be written on a Write command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VALUE[31:16] (R/W)
Upper half of 64-bit dual word data
to be written on a Write command
Figure 8-17: FLCC_KH_DATA1 Register Diagram
Table 8-16: FLCC_KH_DATA1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
8–36
Upper half of 64-bit dual word data to be written on a Write command.
If DMA is enabled, then this register acts as a FIFO. Writes to this register will push
the old data to lower 32 bit of 64 bit data (FLCC_KH_DATA0). When this register is
written twice (in DMA mode) the FIFO becomes full and a flash write command will
automatically be executed.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Lower Page Address
Write a byte address to this register to select the page in which that byte exists. The selected page may be used for a
ERASEPAGE command (selecting which page to erase) or for a SIGN command (selecting the start page for a block
on which a signature should be calculated) For commands using both FLCC_PAGE_ADDR0 and
FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always less than or equal to
FLCC_PAGE_ADDR1, else the command will be denied. (Writing any address above the valid range of flash memory will saturate the address register to prevent aliasing in the flash memory space)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[5:0] (R/W)
Lower address bits of the page address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[9:6] (R/W)
Lower address bits of the page address
Figure 8-18: FLCC_PAGE_ADDR0 Register Diagram
Table 8-17: FLCC_PAGE_ADDR0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:10 VALUE
Lower address bits of the page address.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–37
ADuCM4050 FLCC Register Descriptions
Upper Page Address
Write a byte address to this register to select the page in which that byte exists. The selected page may be used for a
SIGN command (selecting the end page for a block on which a signature should be calculated) For commands using
both FLCC_PAGE_ADDR0 and FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always
less than or equal to FLCC_PAGE_ADDR1, else the command will be denied.
Writing any address above the valid range of flash memory will saturate the address register to prevent aliasing in the
flash memory space.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[5:0] (R/W)
Upper address bits of the page address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[9:6] (R/W)
Upper address bits of the page address
Figure 8-19: FLCC_PAGE_ADDR1 Register Diagram
Table 8-18: FLCC_PAGE_ADDR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:10 VALUE
Upper address bits of the page address.
(R/W)
8–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Signature
Provides read access to the most recently generated signature.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE[15:0] (R)
Read signature
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)
Read signature
Figure 8-20: FLCC_SIGNATURE Register Diagram
Table 8-19: FLCC_SIGNATURE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Read signature.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–39
ADuCM4050 FLCC Register Descriptions
Status
Provides information on current command states and error detection/correction.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ECCINFOSIGN[0] (R)
ECC status of flash initialization
CMDBUSY (R)
Command busy
INIT (R)
Flash controller initialization in progress
WRCLOSE (R)
WRITE registers are closed
SIGNERR (R)
Signature check failure during initialization
CMDCOMP (R/W1C)
Command complete
OVERLAP (R/W1C)
Overlapping Command
WRALCOMP (R/W1C)
Write almost complete
ECCRDERR (R/W1C)
ECC IRQ cause
CMDFAIL (R/W1C)
Provides information on command failures
ECCERRCMD (R/W1C)
ECC errors detected during user issued
SIGN command
SLEEPING (R)
Flash array is in low power (sleep)
mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACCESS_MODE (R)
Access Mode
ECCINFOSIGN[1] (R)
ECC status of flash initialization
CACHESRAMPERR (R)
SRAM parity errors in Cache Controller
ECCERRCNT (R/W1C)
ECC correction counter
ECCDCODE (R/W1C)
DCode AHB Bus Error ECC status
ECCICODE (R/W1C)
ICode AHB Bus Error ECC status
Figure 8-21: FLCC_STAT Register Diagram
Table 8-20: FLCC_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 ACCESS_MODE
(R/NW)
Access Mode.
Indicates whether the controller is in Direct Access (default) or Indirect Access (servicing crypto commands) mode of operation
0 Flash controller is currently in Direct Access mode; user
access to all registers is enabled
1 Flash Controller is currently in Indirect Access mode;
user access to registers is limited to read-only access of
the status register. Full register access will be restored
when the Cryptographic module releases control of the
flash controller (crypto completes the ongoing operation
within the protected key storage region)
8–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
29 CACHESRAMPERR
(R/NW)
28:27 ECCDCODE
(R/W1C)
SRAM parity errors in Cache Controller.
This register provides details for AHB Errors generated due to cache SRAM parity error on the ICODE bus.
DCode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the DCODE bus.
0 No Error No errors or corrections reported since reset or
the register was last cleared
1 2-bit Error 2-bit ECC error has been detected and reported on AHB read access
2 1-bit Correction 1-bit ECC correction has been detected and reported on AHB read access
26:25 ECCICODE
(R/W1C)
ICode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the ICODE bus.
0 No Error No errors or corrections reported since reset or
the register was last cleared
1 2-bit Error 2-bit ECC error has been detected and reported on AHB read access
2 1-bit Correction 1-bit ECC correction has been detected and reported on AHB read access
19:17 ECCERRCNT
(R/W1C)
ECC correction counter.
This counter keeps track of overlapping ECC 1-bit correction reports. When configured to generate IRQs or AHB Bus Errors in the event of an ECC correction event,
this field counts the number of ECC corrections that occur after the first reported correction. The counter remains at full scale when it overflows and clears automatically
when clearing either FLCC_STAT.ECCICODE or FLCC_STAT.ECCDCODE status
bits.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–41
ADuCM4050 FLCC Register Descriptions
Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
16:15 ECCINFOSIGN
(R/NW)
ECC status of flash initialization.
ECC status after the end of automatic signature check on Info space.
0 No Error No errors reported.
1 2-bit error 1 or more 2-bit ECC Errors detected during
signature check (signature check has failed)
2 1-bit error 1 or more 1-bit ECC Corrections performed
during signature check. (signature check will pass if
checksum still matches)
3 1- and 2-bit error At least one of each ECC event (1-bit
Correction and 2-bit Error) were detected during signature check (signature check will fail).
14 INIT
(R/NW)
13 SIGNERR
(R/NW)
11 OVERLAP
(R/W1C)
8–42
Flash controller initialization in progress.
Flash controller initialization is in progress. Until this bit de-asserts, AHB accesses will
stall and APB commands are ignored.
Signature check failure during initialization.
Indicates an automatic signature check has failed during flash controller initialization.
The register value is valid only after the signature check has completed.
Overlapping Command.
This bit is set when a command is requested while another command is busy (overlapping commands are ignored).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10:9 ECCRDERR
(R/W1C)
ECC IRQ cause.
This field reports the cause of recently generated interrupts. The controller may be
configured to generate interrupts for 1- or 2-bit ECC events by writing the appropriate
values to FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_ERROR. These bits are
sticky high until cleared by user code.
0 No Error
1 2-bit Error ECC engine detected a non-correctable 2-bit
error during AHB read access
2 1-bit Correction ECC engine corrected a 1-bit error
during AHB read access
3 1- and 2-bit Events ECC engine detected both 1- and 2bit data corruptions which triggered IRQs (note that a
single read can only report one type of event. This status
indicates that a subsequent AHB read access incurred
the alternate ECC error event).
By default, 1-bit ECC corrections are reported as IRQs
and 2-bit ECC errors are reported as bus faults. It is not
recommended to report both types as IRQs else the status bits become ambiguous when trying to diagnose
which fault came first.
8:7 ECCERRCMD
(R/W1C)
ECC errors detected during user issued SIGN command.
ECC errors, if produced during signature commands, are reported by these bits. To
generate interrupts base on these bits user code should set the corresponding bits in
FLCC_IEN register.
0 success no error, successful flash read operation during
signature check
1 2-bit error During signature commands, 2 bit error is
detected on one or more flash locations, not corrected.
2 1-bit error 1 bit error is corrected for one or more flash
locations while doing signature commands
3 1 or 2 bit error During signature commands, 1 bit error
and 2 bit errors are detected on one or more flash locations
6 SLEEPING
(R/NW)
Flash array is in low power (sleep) mode.
Indicates that the flash array is in a low power (sleep) mode. The flash controller automatically wakes the flash when required for another data transaction. User may wake
the flash at any time by writing the IDLE command to the FLCC_CMD register. Flash
wake-up times vary but are typically ~5 us. User must wake the flash ~5 us before it is
used as a performance optimization.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–43
ADuCM4050 FLCC Register Descriptions
Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 CMDFAIL
(R/W1C)
Provides information on command failures.
This field indicates the status of a command upon completion. If multiple commands
are executed without clearing these bits then only the first error encountered is stored.
0 Success. Successful completion of a command (For example, WRITE)
1 Ignored. Attempted access of a protected or out of
memory location (such a command is ignored).
2 Verify error. Read verify error occurred. This status will
be returned for either of 2 causes; Failed erasures and/or
failed signature checks. Failed Erasure: After erasing
flash page(s) the controller reads the corresponding
word(s) to verify that the erasure completed successfully.
If data still persists, the erasure has failed and this field
reports the failure.
Failed signature check: If the Sign command is executed
and the resulting signature does not match the data stored in the most significant 32-bit word of the signchecked block, the sign check has failed and this field
reports the failure.
3 Abort. Indicates a command is aborted by user code
(abort command issued) or system interrupt.
3 WRALCOMP
(R/W1C)
Write almost complete.
WRITE data registers are re-opened for access as an ongoing write nears completion.
Requesting another write operation before FLCC_STAT.CMDCOMP asserts will result
in a burst write. Burst writes take advantage of low level protocols of the Flash memory
and result in significant performance gains (~15 us saved from each write operation).
Note: Performance gain of a Burst Write only applies to back-to-back writes within the
same row of the flash array.
2 CMDCOMP
(R/W1C)
Command complete.
This bit asserts when a command completes. (Automatically clears when a new command is requested).
Note: Following a power-on-reset, the flash controller performs a number of operations (for example, verifying the integrity of code in info space). At the conclusion of
this process the controller sets the FLCC_STAT.CMDCOMP bit to indicate that the
process has completed.
8–44
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-20: FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 WRCLOSE
(R/NW)
0 CMDBUSY
(R/NW)
WRITE registers are closed.
The WRITE data/address registers and the command register are closed for access.
This bit is asserted part of the time while a write is in progress. If this bit is high, the
related registers are in use by the flash controller and cannot be written. This bit clears
when FLCC_STAT.WRALCOMP flag goes high, indicating that the ongoing write
command has consumed the associated data and these registers may now be overwritten with new data.
Command busy.
This bit is asserted when the flash block is actively executing any command entered via
the command register.
Note: There is a modest delay between requesting a command and having this bit assert; user code polling for command completion should watch for
FLCC_STAT.CMDCOMP bit rather than FLCC_STAT.CMDBUSY.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–45
ADuCM4050 FLCC Register Descriptions
Time Parameter 0
[User Key] is required to write this register. This register should not be modified while a flash write or erase command is in progress. This register defines a set of parameters used to control the timing of signals driven to the Flash
Memory. The default values are appropriate for a system clock of 26MHz and a reference clock (driven by the internal oscillator) operating within 10% of 13MHz. The value of each timing parameter consists of a user programmable nibble (4 bits) as well as some number of hard-coded bits. User programmable bits are the most significant bits
for each parameter.
Time parameters describe the number of ref-clk periods to wait when meeting the associated timing constraint of
the flash memory itself. Note that clock-domain-crossings and the constraints of signals not described by these parameters will increase the effective delays by a small margin. When programming the time parameter registers the
user should select a value approaching the minimum time for each constraint.
Note: Improper programming of this register may result in damage to the flash memory during PROGRAM or
ERASE operations.
15 14 13 12 11 10 9
0
1
0
0
1
0
0
8
7
6
5
4
3
2
1
0
1
0
1
0
1
0
0
0
0
TPROG (R/W)
Program time
DIVREFCLK (R/W)
Divide Reference Clock (by 2)
TPGS (R/W)
NVSTR to Program setup time
TNVS (R/W)
PROG/ERASE to NVSTR setup time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
1
1
0
0
0
1
0
0
1
0
1
0
1
TNVH1 (R/W)
NVSTR Hold time during Mass Erase
TNVH (R/W)
NVSTR Hold time
TERASE (R/W)
Erase Time
TRCV (R/W)
Recovery time
Figure 8-22: FLCC_TIME_PARAM0 Register Diagram
Table 8-21: FLCC_TIME_PARAM0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 TNVH1
(R/W)
NVSTR Hold time during Mass Erase.
Determines the upper 4 bits of an 11-bit value loaded into the timer. The lower bits
are hard-coded to 0x14.
With an ideal refclk at 13 MHz:
Min [0x0] = 1.5 us
Default [0xB] = 110 us
Max [0xF] = 149 us
8–46
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Table 8-21: FLCC_TIME_PARAM0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
27:24 TERASE
(R/W)
Erase Time.
Determines the upper 4 bits of a 19-bit value loaded into the timer. The lower bits are
hard-coded to 0x2000.
With an ideal refclk at 13 MHz:
Min [0x0] = 0.6 ms
Default [0x8] = 20.8 ms
Max [0xF] = 38.4 ms
23:20 TRCV
(R/W)
Recovery time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x2.
With an ideal refclk at 13 MHz:
Min [0x0] = 154 ns
Default [0x9] = 1.1 us
Max [0xF] = 18.6 us
19:16 TNVH
(R/W)
NVSTR Hold time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x1.
With an ideal refclk at 13 MHz:
Min [0x0] = 77 ns
Default [0x5] = 5.5 us
Max [0xF] = 18.5 us
15:12 TPROG
(R/W)
Program time.
Determines the upper 4 bits of a 10-bit value loaded into the timer. The lower bits are
hard-coded to 0x0D.
With an ideal refclk at 13 MHz:
Min [0x0] = 1 us
Default [0x4] = 20.7 us
Max [0xF] = 75.3 us
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–47
ADuCM4050 FLCC Register Descriptions
Table 8-21: FLCC_TIME_PARAM0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 TPGS
(R/W)
NVSTR to Program setup time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x2.
With an ideal refclk at 13 MHz:
Min [0x0] = 154 ns
Default [0x9] = 1.1 us
Max [0xF] = 18.6 us
7:4 TNVS
(R/W)
PROG/ERASE to NVSTR setup time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0x1.
With an ideal refclk at 13 MHz:
Min [0x0] = 77 ns
Default [0x5] = 5.5 us
Max [0xF] = 18.5 us
0 DIVREFCLK
(R/W)
Divide Reference Clock (by 2).
If set to 1, the reference clock is divided by 2. All time parameters are relative to the
reference clock; dividing the clock enables the selection of long time periods, if necessary.
Note: It is unlikely that user code should ever need to modify the time parameters.
Support is provided in the unlikely event that a user finds it necessary.
8–48
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Time Parameter 1
[User Key] is required to write this register. This register should not be modified while a flash write or erase command is in progress. This register defines a set of parameters used to control the timing of signals driven to the Flash
Memory. The default values are appropriate for a system clock of 26MHz and a reference clock (driven by the internal oscillator) operating within 10% of 13MHz. The value of each timing parameter consists of a user programmable nibble (4 bits) as well as some number of hard-coded bits. User programmable bits are the most significant bits
for each parameter.
Time parameters describe the number of ref-clk periods to wait when meeting the associated timing constraint of
the flash memory itself. Note that clock-domain-crossings and the constraints of signals not described by these parameters will increase the effective delays by a small margin. When programming the time parameter registers the
user should select a value approaching the minimum time for each constraint.
Note: Improper programming of this register may result in damage to the flash memory during PROGRAM or
ERASE operations.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
CURWAITSTATES (R)
Current wait states [2:0]
TWK (R/W)
Wake up time
WAITSTATES (R/W)
Number of wait states to access flash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-23: FLCC_TIME_PARAM1 Register Diagram
Table 8-22: FLCC_TIME_PARAM1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10:8 CURWAITSTATES
(R/NW)
Current wait states [2:0].
When WaitStates is modified, it may take a number of clock ticks for the modification
to take effect. The controller waits until all currently active reads or writes or erases
have completed before changing the number of wait states. These bits can be used to
verify that the change to WaitStates[2:0] has taken effect and it is safe to modify the
clock frequency.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–49
ADuCM4050 FLCC Register Descriptions
Table 8-22: FLCC_TIME_PARAM1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
6:4 WAITSTATES
(R/W)
Number of wait states to access flash.
This field is read only until the ADI Key is provided.
This determines the number of wait states required on a read it depends on the flash
access time and the hclk frequency into the flash core. When WaitStates[2:0] is modified: poll CurrWaitStates until it is the same value, only then it is safe to change the
system clock frequency.
This can be programmed only till 3'b100, if any attempt is made to program more
than 3'b100 then this register will not be updated.
3:0 TWK
(R/W)
Wake up time.
Determines the upper 4 bits of an 8-bit value loaded into the timer. The lower bits are
hard-coded to 0xB.
With an ideal refclk at 13 MHz:
Min [0x0] = 847 ns
Default [0x4] = 5.7 us
Max [0xF] = 19.3 us
8–50
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
User Configuration
User key is required. Write to this register to enable user control of DMA and Auto-increment features. When user
code has finished accessing this register, garbage data should be written to the FLCC_KEY register to re-assert protection.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
AUTOINCEN (R/W)
Auto Address Increment for Key Hole
Access
KHDMAEN (R/W)
Key hole DMA enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-24: FLCC_UCFG Register Diagram
Table 8-23: FLCC_UCFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 AUTOINCEN
(R/W)
Auto Address Increment for Key Hole Access.
When this bit is set, FLCC_KH_ADDR automatically increments by 0x8 during each
write command or after each read command. This enables user code to write a series of
sequential flash locations without having to manually set the flash address for each
write.
The FLCC_KH_ADDR is incremented, and may be observed by user code, when
FLCC_STAT.WRALCOMP is asserted during a write command, or when
FLCC_STAT.WRALCOMP is asserted after a READ command.
When this bit is set, user code may not directly modify FLCC_KH_ADDR.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–51
ADuCM4050 FLCC Register Descriptions
Table 8-23: FLCC_UCFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 KHDMAEN
(R/W)
Key hole DMA enable.
The flash controller interacts with the DMA controller, when this bit is set.
Prior to setting this bit, user code must:
- Write the starting address to FLCC_KH_ADDR
- Configure the DMA controller to write data to FLCC_KH_DATA1 (address must be
DWORD aligned)
- Configure the DMA controller to always write pairs of 32 bit words (R Power = 1)
- Configure the DMA controller to write an integer number of data pairs (for an odd
number of words user code must write one word manually without the help of DMA)
Note: All DMA writes will automatically increment the target address (similar to the
behavior of FLCC_UCFG.AUTOINCEN). The DMA controller may only be used to
write sequential addresses starting from the value of FLCC_KH_ADDR
The flash controller automatically begins write operations each time the DMA controller provides a pair of words to write. Interaction with the DMA controller has been
designed to use burst writes which may significantly reduce overall programming time.
8–52
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Write Protection
User Key is required to modified this register. The FLCC_WRPROT register may be automatically configured during
device boot up. In this event, the boot loader reads data from user space and loads that data into this register.
User code may affect non-volatile write protection by writing to the appropriate location in the flash memory. By
default, the relevant location in flash is 0x3FFF0 (the 4th most significant word in user space), but may be relocated
by ADI's secure boot loader.
User code may alternatively assert protection at runtime for any unprotected blocks by directly writing this register.
Blocks may have protection added but cannot have protection removed; changes will be lost on reset. This approach
is suggested especially during user code development.
All write protection is cleared on a power-on-reset but note that the ADI secure boot loader will reassert write protection as defined by the FLCC_WRPROT word in user space before enabling user access to the flash array. Therefore removing write protection can only be performed by an ERASEPAGE command of the most significant page in
user space (provided that page is not currently protected) or by a MASSERASE command. Following a successful
MASSERASE command all protection of pages in user space is immediately cleared (user may write to user space
immediately following such an erase without a device reset required).
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
WORD[15:0] (R/W0C)
Clear bits to write protect related groups
of user space pages
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WORD[31:16] (R/W0C)
Clear bits to write protect related groups
of user space pages
Figure 8-25: FLCC_WRPROT Register Diagram
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–53
ADuCM4050 FLCC Register Descriptions
Table 8-24: FLCC_WRPROT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 WORD
(R/W0C)
Clear bits to write protect related groups of user space pages.
Once cleared, these bits can only be set again by resetting the part.
Each bit of this 32-bit word represents a 32nd of the total available user space.
For 512 KB parts consisting of 2 KB pages (256 pages) each bit represents the write
protection state of a group of 8 pages.
For 256 KB parts consisting of 2 KB pages (128 pages) each bit represents the write
protection state of a group of 4 pages.
for 128 KB parts consisting of 2 KB pages (64 pages) each bit represents the write protection state of a group of 2 pages.
The most significant bit of this register corresponds to the most significant group of
pages in user space.
8–54
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC Register Descriptions
Write Abort Address
Address of recently aborted write command. This address is only populated if the aborted write command was started. If the command is aborted early enough to have no affect on the flash IP this address is not updated.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE[15:0] (R)
Address of recently aborted write command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)
Address of recently aborted write command
Figure 8-26: FLCC_WR_ABORT_ADDR Register Diagram
Table 8-25: FLCC_WR_ABORT_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
Address of recently aborted write command.
This register holds the address targeted by an ongoing write command and retains its
value after an abort event. User code may read this register to determine the flash location(s) affected a write abort.
The register value is not guaranteed to persist once a new flash command is requested,
therefore user code should read this value immediately following an aborted write.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
8–55
Static Random Access Memory (SRAM)
9 Static Random Access Memory (SRAM)
This chapter provides an overview of the SRAM functionality of the ADuCM4050 MCU.
SRAM Features
The SRAM used by the ADuCM4050 MCU supports the following features:
• Low power controller for data SRAM, instruction SRAM and cache SRAM.
• Total available memory: 128 KB
• Maximum retained memory in hibernate mode: 124 KB
• Data SRAM is composed of 128 KB. 16 KB is always retained in hibernate mode. Maximum retained memory
in hibernate mode is 124 KB
• If instruction SRAM is enabled, 32 KB of data SRAM is mapped to instruction SRAM, and data SRAM can
only access 96 KB. Instruction SRAM has option to retain 0 KB, 12 KB, 16 KB, or 28 KB in hibernate mode.
• When cache controller is enabled, 4 KB of the instruction SRAM is reserved for cache data. The 4 KB cache
data is not retained in hibernate mode.
• Parity bit error detection (optional) is available on all SRAM memories. Parity check can be configured to be
enabled/disabled in different memory regions.
• Byte, Half-word, and Word accesses are supported.
For more information, refer to SRAM Region.
SRAM Configuration
Instruction SRAM vs Data SRAM
If the PMG_TST_SRAM_CTL.INSTREN bit is asserted, 32 KB of SRAM is mapped at start address 0x1000_0000
as Instruction SRAM (see MODE0 in memory map). 96 KB of data SRAM is mapped in two sections, the first
starting at 0x2000_0000 and second starting at 0x2004_0000. If cache memory feature is used, only 28 KB is available for instruction SRAM (see MODE1 in memory map).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
9–1
SRAM Configuration
If PMG_TST_SRAM_CTL.INSTREN bit is 0 and cache is disabled, the 128 KB of SRAM is mapped as data
SRAM. The memory is arranged in two sections, the first one (32 KB) is mapped at start address 0x2000_0000 and
the second one (96 KB) at 0x2004_0000 (see MODE2 in memory map). If cache memory feature is used, the first
section only maps 28 KB, so the total data SRAM available is 124 KB (see MODE3 in memory map).
By default, at power up and hardware reset, the 32 KB of SRAM is made available as instruction SRAM. If the user
needs to exercise the option of using a total of 128 KB data SRAM, the PMG_TST_SRAM_CTL.INSTREN bit
must be programmed to zero at the start of the user code.
When cache controller is enabled, SRAM bank 2 is not accessible. A bus error (unmapped address) is generated if an
access is attempted.
For more information, refer to the SRAM Region
SRAM Retention in Hibernate Mode
In terms of the amount of SRAM being retained in hibernate mode, different configurations are available to the
user.
The content of the first 16 KB (Bank0) of data SRAM mapped at 0x2000_0000 is always retained. The SRAM
bank 2 (4 KB) is not retained in hibernate mode. It may be mapped to data SRAM, instruction SRAM, or cache
based on the mode of operation.
When PMG_SRAMRET.RET1 bit is enabled, 12 KB of data SRAM mapped from 0x2000_4000 to 0x2000_6FFF
(Bank1) is retained in hibernate mode. If instruction SRAM is enabled, this is mapped to 0x1000_0000 to
0x1000_2FFF.
When PMG_SRAMRET.RET2 bit is enabled, 32 KB of data SRAM mapped from 0x2000_4000 to 0x2004_7FFF
(Bank3, Bank4) is retained.
When PMG_SRAMRET.RET3 bit is enabled, 32 KB of data SRAM mapped from 0x2004_8000 to 0x2004_FFFF
(Bank5) is retained.
When PMG_SRAMRET.RET4 bit is enabled, 32 KB of data SRAM mapped from 0x2005_0000 to 0x2005_7FFF
(Bank6, Bank7) is retained. If instruction SRAM is enabled, Bank7 is mapped 0x1000_3000 to 0x1000_6FFF.
The PMG_SRAMRET.RET1, PMG_SRAMRET.RET2, PMG_SRAMRET.RET3, and PMG_SRAMRET.RET4
bits are write protected with the PWRKEY.
SRAM Programming Model
The start address of the data SRAM and instruction SRAM are set to 0x2000_0000 and 0x1000_0000 respectively.
SRAM Parity
For robustness, parity check can be enabled on all or a user selected group of SRAM banks. Parity check can detect
up to two errors per word for banks Bank0, Bank1 and Bank2. Data read back is done before performing byte and
9–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SRAM Initialization
halfword data. Parity check can detect up to four errors per word for banks Bank3 to Bank7, and the memories
support byte wise write in one cycle. Therefore, read back is not done for these banks for byte and halfword writes.
Parity check feature can be enabled by asserting the PMG_TST_SRAM_CTL.PENBNK0 to
PMG_TST_SRAM_CTL.PENBNK5 bits for each SRAM bank. User must configure these bits at the beginning of
the program code.
Parity is checked when data is read. It is also checked when byte or halfword data is written to Bank0, Bank1, and
Bank2. Parity is not checked when word (32 bits) write is performed. If a parity error is detected, a bus error is
generated. Even if parity error is detected when writing a byte or halfword, the write operation is completed and
parity bits are updated according to the new data. User must manage the parity error in the bus fault interrupt routine.
SRAM Initialization
If parity check is enabled, SRAM contents have to be initialized to avoid false parity errors while performing byte or
halfword write for Bank0, Bank1 and Bank2. Other banks support byte and halfword write in single cycle. They
need not be initialized. If Bank7 is used as instruction SRAM, it must be initialization when parity check is enabled
on the bank. A dedicated hardware can automatically initialize the selected SRAM banks and the process takes 2048
HCLK cycles to complete. This hardware is fully programmable by the user so initialization can be started automatically or manually.
As initialization overwrites the contents of the selected SRAM banks, this process must be performed before writing
to those SRAMs. During the initialization sequence, if a write or read access to a SRAM bank being initialized is
detected, bus error response is issued until the initialization sequence is completed. SRAMs banks that are not selected to be initialized can be accessed as usual during the initialization process of the rest of the banks.
The initialization for a particular SRAM bank can be monitored for its completion by polling the appropriate
PMG_TST_SRAM_INITSTAT.BNK0DONE to PMG_TST_SRAM_INITSTAT.BNK7DONE bits. Every time a
particular SRAM bank is initialized, the associated PMG_TST_SRAM_INITSTAT.BNK0DONE to
PMG_TST_SRAM_INITSTAT.BNK7DONE bits bits are cleared and remain low until initialization is completed.
After power-up, SRAM Bank0, Bank1, Bank2, and Bank7 are automatically initialized. SRAM Bank0 (16 KB) is
always retained and contains the stack pointer and critical information. The content is not overwritten as initialization is already been performed. User must avoid initializing the SRAM banks that are already initialized, as they may
already contain user information.
After hibernate, the content in the non-retained SRAM banks is lost. If Bank1 (if not retained), Bank2 and Bank7
(if not retained and mapped to instruction SRAM) have parity enabled, initialization is required.
There are two options to initialize the required SRAM banks after hibernate mode:
1. Initialize by writing to PMG_TST_SRAM_CTL.STARTINIT register after coming out of hibernate mode.
SRAMs banks (PMG_TST_SRAM_CTL.BNK0EN to PMG_TST_SRAM_CTL.BNK7EN bits) that are set to
1 are initialized.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
9–3
SRAM Initialization
2. Automatic initialization after hibernate mode. No write to PMG_TST_SRAM_CTL is required each time we
come back from hibernate mode. To select this automatic mode, the user has to previously set the
PMG_TST_SRAM_CTL.AUTOINIT bit. SRAMs selected for initialization in this register are automatically
initialized after coming back from hibernate mode.
Initialization resets the contents of the selected memory banks. User must properly select the memory banks that are
initialized so that user information is not lost.
The initialization sequence can be aborted at any time by writing to the PMG_TST_SRAM_CTL.ABTINIT bit.
This bit is self-cleared after it has been written.
Initialization in Cache
When cache memory is used, parity can also be enabled on its associated SRAM bank (Bank 2). In this case, (when
SRAM Bank 2 is used as cache memory) initialization is not required. Initialization is required only when we perform byte or halfword accesses to SRAM with parity check enabled. When SRAM Bank 2 is used as cache memory,
all the accesses are word accesses.
As initialization is not required for the cache memory, the cache feature is available after coming back from hibernate mode (no initialization time penalty). To prevent undesired bus errors, the controller ignores any initialization
of SRAM Bank 2 when cache is enabled.
Kernel Code: SRAM Bank 0 Initialization Before User Code Execution
As SRAM Bank0 is initialized on power-up, ensure that initialization is completed before user code starts execution.
Poll the status of the PMG_SRAM_INIT_STAT.BNK0DONE bit at the end of the kernel code. When this bit is 1
(initialization is completed), exit the polling loop and continue with the program execution.
ADuCM4050 SRAM Register Description
Table 9-1: ADuCM4050 SRAM Register List
Name
Description
Reset
Access
PMG_TST_SRAM_INITSTAT
Initialization Status Register
0x00000000
R/W
PMG_TST_SRAM_CTL
Control for SRAM Parity and Instruction
SRAM
0x80000000
R/W
PMG_SRAMRET
Control for Retention SRAM in Hibernate Mode
0x00000000
R/W
9–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SRAM Register Description
Initialization Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BNK7DONE (R)
Bank 7 initialization status
BNK0DONE (R)
Bank 0 initialization status
BNK6DONE (R)
Bank 6 initialization status
BNK1DONE (R)
Bank 1 initialization status
BNK5DONE (R)
Bank 5 initialization status
BNK2DONE (R)
Bank 2 initialization status
BNK4DONE (R)
Bank 4 initialization status
BNK3DONE (R)
Bank 3 initialization status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-1: PMG_TST_SRAM_INITSTAT Register Diagram
Table 9-2: PMG_TST_SRAM_INITSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 BNK7DONE
Bank 7 initialization status.
(R/NW)
0 Bank 7 not initialized
1 Bank 7 initialized
6 BNK6DONE
Bank 6 initialization status.
(R/NW)
0 Bank 6 not initialized
1 Bank 6 initialized
5 BNK5DONE
Bank 5 initialization status.
(R/NW)
0 Bank 5 not initialized
1 Bank 5 initialized
4 BNK4DONE
Bank 4 initialization status.
(R/NW)
0 Bank 4 not initialized
1 Bank 4 initialized
3 BNK3DONE
(R/NW)
Bank 3 initialization status.
0 Bank 3 not initialized
1 Bank 3 initialized
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
9–5
ADuCM4050 SRAM Register Description
Table 9-2: PMG_TST_SRAM_INITSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 BNK2DONE
Bank 2 initialization status.
(R/NW)
0 Bank 2 not initialized
1 Bank 2 initialized
1 BNK1DONE
Bank 1 initialization status.
(R/NW)
0 Bank 1 not initialized
1 Bank 1 initialized
0 BNK0DONE
(R/NW)
Bank 0 initialization status.
0 Bank 0 not initialized
1 Bank 0 initialized
9–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SRAM Register Description
Control for SRAM Parity and Instruction SRAM
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ABTINIT (R/W)
Abort current initialization. Self-cleared
BNK1EN (R/W)
Enable initialization
AUTOINIT (R/W)
Automatic initialization on wake up
from hibernate mode
BNK2EN (R/W)
Enable initialization
BNK7EN (R/W)
Enable initialization
STARTINIT (R/W)
Write one to trigger initialization. Self-cleared
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INSTREN (R/W)
Enables 32 KB instruction SRAM
PENBNK0 (R/W)
Enable parity check
PENBNK7 (R/W)
Enable parity check
PENBNK1 (R/W)
Enable parity check
PENBNK6 (R/W)
Enable parity check
PENBNK2 (R/W)
Enable parity check
PENBNK5 (R/W)
Enable parity check
PENBNK3 (R/W)
Enable parity check
PENBNK4 (R/W)
Enable parity check
Figure 9-2: PMG_TST_SRAM_CTL Register Diagram
Table 9-3: PMG_TST_SRAM_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 INSTREN
Enables 32 KB instruction SRAM.
(R/W)
23 PENBNK7
Enable parity check.
(R/W)
22 PENBNK6
Enable parity check.
(R/W)
21 PENBNK5
Enable parity check.
(R/W)
20 PENBNK4
Enable parity check.
(R/W)
19 PENBNK3
Enable parity check.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
9–7
ADuCM4050 SRAM Register Description
Table 9-3: PMG_TST_SRAM_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
18 PENBNK2
Enable parity check.
(R/W)
17 PENBNK1
Enable parity check.
(R/W)
16 PENBNK0
Enable parity check.
(R/W)
15 ABTINIT
Abort current initialization. Self-cleared.
(R/W)
14 AUTOINIT
Automatic initialization on wake up from hibernate mode.
(R/W)
13 STARTINIT
Write one to trigger initialization. Self-cleared.
(R/W)
7 BNK7EN
Enable initialization.
(R/W)
2 BNK2EN
Enable initialization.
(R/W)
1 BNK1EN
Enable initialization.
(R/W)
9–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SRAM Register Description
Control for Retention SRAM in Hibernate Mode
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RET4 (R/W)
Enable retention bank 6 and bank 7
(32 KB)
RET1 (R/W)
Enable retention bank 1 (12 KB)
RET2 (R/W)
Enable retention bank 3 and bank 4
(32 KB)
RET3 (R/W)
Enable retention bank 5 (32 KB)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
HIBERNATE_SRAM_LOAD_MODE (R/W)
Hibernate mode SRAM load mode control
Figure 9-3: PMG_SRAMRET Register Diagram
Table 9-4: PMG_SRAMRET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23 HIBER(R/W) NATE_SRAM_LOAD_M
ODE
9 RET4
Hibernate mode SRAM load mode control.
Used to configure appropriate load current support in hibernate mode.
Enable retention bank 6 and bank 7 (32 KB).
(R/W)
8 RET3
Enable retention bank 5 (32 KB).
(R/W)
1 RET2
Enable retention bank 3 and bank 4 (32 KB).
(R/W)
0 RET1
Enable retention bank 1 (12 KB).
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
9–9
Cache
10 Cache
Enabling Cache increases the performance of applications executing from flash. Cache memory coexists with
SRAM. When Cache is enabled, part of the SRAM is allocated to Cache. Therefore, Cache cannot be used for other
purposes. Instruction Cache (I-Cache) is of size is 4 KB. On wake up from hibernate, I-Cache contents are not retained.
Cache Programming Model
Instruction Cache is disabled on power-up.
Programming Guidelines
The sequence to enable cache is as follows:
1. Read FLCC_CACHE_STAT.ICEN bit to make sure that Cache is disabled. Poll until this bit is cleared.
2. Write USER KEY (0xF123F456) to FLCC_CACHE_KEY register.
3. Set FLCC_CACHE_SETUP.ICEN bit to enable the cache.
ADuCM4050 FLCC_CACHE Register Descriptions
Cache Controller (FLCC_CACHE) contains the following registers.
Table 10-1: ADuCM4050 FLCC_CACHE Register List
Name
Description
FLCC_CACHE_KEY
Cache Key Register
FLCC_CACHE_SETUP
Cache Setup Register
FLCC_CACHE_STAT
Cache Status Register
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
10–1
ADuCM4050 FLCC_CACHE Register Descriptions
Cache Key Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Cache Key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Cache Key
Figure 10-1: FLCC_CACHE_KEY Register Diagram
Table 10-2: FLCC_CACHE_KEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
10–2
Cache Key.
Enter 0xF123_F456 to set the UserKey. Returns 0x0 if read. The key is cleared automatically after writing to FLCC_CACHE_SETUP register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 FLCC_CACHE Register Descriptions
Cache Setup Register
Cache User key is required to enable a write to this location. Key will be cleared after a write to this Register.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
LCKIC (R/W)
If this bit is set, I-Cache contents are
locked
ICEN (R/W)
If this bit set, I-Cache is enabled for
AHB accesses
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-2: FLCC_CACHE_SETUP Register Diagram
Table 10-3: FLCC_CACHE_SETUP Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 LCKIC
(R/W)
0 ICEN
(R/W)
If this bit is set, I-Cache contents are locked.
New misses are not replaced in I-Cache.
If this bit set, I-Cache is enabled for AHB accesses.
If 0, I-Cache is disabled, and all AHB accesses will be via Flash memory. This bit is
cleared when Init bit is set.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
10–3
ADuCM4050 FLCC_CACHE Register Descriptions
Cache Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ICEN (R)
If this bit is set, I-Cache is enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-3: FLCC_CACHE_STAT Register Diagram
Table 10-4: FLCC_CACHE_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 ICEN
(R/NW)
10–4
If this bit is set, I-Cache is enabled.
If this bit is cleared, I-Cache is disabled.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Direct Memory Access (DMA)
11 Direct Memory Access (DMA)
The direct memory access (DMA) controller is used to perform data transfer tasks and offload these from the
ADuCM4050 MCU. DMA is used to provide high speed data transfer between peripherals and memory. Data can
be quickly moved by the DMA without any CPU actions. This keeps the CPU resources free for other operations.
DMA Features
The DMA supports the following features:
• 27 independent DMA channels
• Two programmable priority levels for each DMA channel
• Each priority level arbitrates using a fixed priority that is determined by the DMA channel number
• Each DMA channel can access a primary, and/or alternate channel control data structure
• Supports the following multiple transfer types:
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
• Supports the following multiple DMA cycle types:
• Basic
• Auto request
• Ping-Pong
• Scatter-Gather
• Supports multiple DMA transfer data widths (8-bit, 16-bit, and 32-bit)
• Each DMA channel can have independent source and destination increment/decrement controls
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–1
DMA Functional Description
DMA Functional Description
The DMA has 27 channels in total, each dedicated to managing memory access requests from peripherals. DMA
Channels shows the assignments.
Each DMA channel is connected to dedicated hardware DMA requests, and the software trigger is also supported on
each channel. This configuration is done by software. Each DMA channel has a programmable priority level default
or high. Each priority level arbitrates using a fixed priority that is determined by the DMA channel number.
The DMA controller supports multiple DMA transfer data widths. However, the source and destination transfer
sizes must be the same. Also, always align the source and destination addresses to the data transfer size. It has a single
output to indicate when an error condition occurs: DMA error interrupt. An error condition can occur when a bus
error happens while doing a DMA transfer, or when the DMA controller reads an invalid cycle control. The DMA
controller supports memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers and has access
to flash or SRAM as source and destination.
Table 11-1: DMA Channels
Channel Node
Peripheral
0
SPI2 Tx
1
SPI2 Rx
2
SPORT0A
3
SPORT0B
4
SPI0 Tx
5
SPI0 Rx
6
SPI1 Tx
7
SPI1 Rx
8
UART0 Tx
9
UART0 Rx
10
I2C Slave Tx
11
I2C Slave Rx
12
I2C Master
13
Crypto IN
14
Crypto OUT
15
Flash
16 to 23
Software DMA
24
ADC Rx
25
UART1 Tx
26
UART1 Rx
11–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Functional Description
DMA Architectural Concepts
The DMA channel provides a means to transfer data between memory spaces or between memory and a peripheral
using the system interface. The DMA channel provides an efficient means of distributing data throughout the system, freeing up the core for other operations. Each peripheral that supports DMA transfers has a dedicated DMA
channel or channels with its register set that configures and controls the operating modes of the DMA transfers.
DMA Operating Modes
The DMA controller has two buses where one is connected to the system bus shared with the Cortex-M4F core and
the other bus is connected to 16-bit peripherals. The DMA request may stop the CPU access to the system bus for
some bus cycles, such as when the CPU and DMA target the same destination (memory or peripheral).
The DMA controller fetches channel control data structures located in the system memory to perform data transfers. The DMA-capable peripherals, when enabled to use DMA, can request the DMA controller for a transfer. At
the end of the programmed number of DMA transfers for a channel, the DMA controller generates a single cycle
dma_done interrupt corresponding to that channel. This interrupt indicates the completion of the DMA transfer.
Separate interrupt enable bits are available in the NVIC for each of the DMA channels.
Channel Control Data Structure
Every channel has two control data structures associated with it: a primary data structure and an alternate data structure. For simple transfer modes, the DMA controller uses either the primary or alternate data structure. For more
complex data transfer modes, such as Ping-Pong or Scatter-Gather, the DMA controller uses both the primary and
alternate data structures. Each control data structure (primary or alternate) occupies four 32-bit locations in the
memory as shown in the Channel Control Data Structure table.
Table 11-2: Channel Control Data Structure
Offset
Name
Description
0x00
SRC_END_PTR
Source End Pointer
0x04
DST_END_PTR
Destination End Pointer
0x08
CHNL_CFG
Control Data Configuration
0x0C
RESERVED
Reserved
Memory Map for Primary DMA Structure figure shows an example of the entire channel control data structure for
eight DMA channel case. It uses 512 bytes of system memory.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–3
DMA Operating Modes
0x070
0x0FC
Control
0x078
Control
0x0F8
Destination End Pointer
0x074
Destination End Pointer
0x0F4
Source End Pointer
0x070
Source End Pointer
0x0F0
0x060
0x0EC
Control
0x068
Control
0x0E8
Destination End Pointer
0x064
0x060
Destination End Pointer
0x0E4
Source End Pointer
0x0E0
Source End Pointer
0x0DC
0x050
Control
0x058
Control
0x0D8
Destination End Pointer
0x054
0x050
Destination End Pointer
0x0D4
Source End Pointer
0x0D0
Source End Pointer
0x040
0x0CC
Control
0x048
Control
0x0C8
Destination End Pointer
0x044
Destination End Pointer
0x0C4
Source End Pointer
0x040
Source End Pointer
0x0C0
0x030
0x0BC
Control
0x038
Control
0x0B8
Destination End Pointer
0x034
Destination End Pointer
0x0B4
0x030
Source End Pointer
0x0B0
Source End Pointer
0x0AC
0x020
Control
0x028
Control
0x0A8
Destination End Pointer
0x024
Destination End Pointer
0x0A4
Source End Pointer
0x020
0x010
Source End Pointer
0x0A0
Control
0x018
Control
0x098
Destination End Pointer
0x014
0x010
Destination End Pointer
0x094
Source End Pointer
0x090
Source End Pointer
0x090
0x00C
0x08C
Control
0x008
Control
0x088
Destination End Pointer
0x004
Destination End Pointer
0x084
Source End Pointer
0x000
Source End Pointer
0x080
Figure 11-1: Memory Map for Primary DMA Structure
Before the controller can perform a DMA transfer, the data structure related to the DMA channel needs to be written to the designated location in system memory. The Source End Pointer memory location contains the end address of the source data. The Destination End Pointer memory location contains the end address of the destination
data. The Control memory location contains the channel configuration control data. This determines the source
and destination data size, number of transfers, and the number of data transfers for each arbitration.
When the DMA controller receives a request for a channel, it reads the corresponding data structure from the system memory into its internal cache. Any update to the descriptor in the system memory until dma_done interrupt
does not guarantee expected behavior. It is recommended that the user not update the descriptor before receiving
dma_done.
11–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Operating Modes
Source Data End Pointer
The SRC_END_PTR memory location stores the address of the last location from where data will be read as part of
DMA transfer. This memory location must be programmed with the end address of the source data before the controller can perform a DMA transfer. The controller reads this memory location when it starts the first DMA data
transfer. DMA controller does not write to this memory location.
Table 11-3: Source Data End Pointer
Bit
Name
Description
[31:0]
SRC_END_PTR
The end address of the source data.
Destination Data End Pointer
The DST_END_PTR memory location stores the address of the last location where data will be written to as part of
DMA transfer. This memory location must be programmed with the end address of the destination data before the
controller can perform a DMA transfer. The controller reads this memory location when it starts the first DMA data
transfer. DMA controller does not write to this memory location.
Table 11-4: Destination Data End Pointer
Bit
Name
Description
[31:0]
DST_END_PTR
The end address of the destination data.
Control Data Configuration
For each DMA transfer, the control data configuration (CHNL_CFG) memory location provides the control information for the DMA transfer to the controller.
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11–5
DMA Operating Modes
Table 11-5: Destination Data End Pointer
Bits
Name
Description
31:30
DST_INC
Destination address increment. The address increment depends on the source data
width as follows:
SRC_SIZE: Byte
00: byte
01: half-word
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
SRC_SIZE: Half-word
00: reserved
01: halfword
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
SRC_SIZE: Word
00: reserved
01: reserved
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
29:28
11–6
RESERVED
Undefined. Write as zero
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Operating Modes
Table 11-5: Destination Data End Pointer (Continued)
Bits
Name
Description
27:26
SRC_INC
Source address increment. The address increment depends on the source data width
as follows:
SRC_SIZE: Byte
00: byte
01: half-word
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
SRC_SIZE: Half-word
00: reserved
01: halfword
10: word.
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
SRC_SIZE: Word
00: reserved
01: reserve
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
25:24
SRC_SIZE
Size of the source data.
00: byte
01: half-word
10: word
11: reserved
23:18
RESERVED
Undefined. Write as zero.
17:14
R_Power
R_Power arbitrates after x DMA transfers.
0000: x = 1
0001: x = 2
0010: x = 4
0011: x = 8
0100: x = 16
0101: x = 32
0110: x = 64
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–7
DMA Operating Modes
Table 11-5: Destination Data End Pointer (Continued)
Bits
Name
Description
0111: x = 128
1000: x = 256
1001: x = 512
1010 to 1111: x = 1024
NOTE: Software DMA transfers can use any value from 0000 to 1111. DMA
transfers that involve peripherals should always use 0000 with the exception of the
Crypto block, see Crypto chapter for further details. The operation of the DMA
will be indeterminate if a value other than 0000 is programmed for the DMA transfers involving peripherals.
13:4
N_minus_1
Total number of transfers in the current DMA cycle - 1.
This value indicates the total number of transfers in the DMA cycle and not the
total number of bytes.
The possible values are 0 - 1023.
3
RESERVED
Undefined. Write as zero.
2:0
Cycle_ctrl
The operating mode of the DMA cycle.
000: Stop (Invalid)
001: Basic
010: Auto-Request
011: Ping-Pong
100: Memory Scatter-Gather Primary
101: Memory Scatter-Gather Alternate
110: Peripheral Scatter-Gather Primary
111: Peripheral Scatter-Gather Alternate
During the DMA transfer process, if any error occurs during the data transfer, CHNL_CFG is written back to the
system memory, with N_minus_1 field updated to reflect the number of transfers yet to be completed. When a full
DMA cycle is complete, cycle_ctrl bits are made invalid to indicate the completion of transfer.
DMA Priority
The priority of a channel is determined by its number and priority level. Each channel can have two priority levels:
default or high. All channels at the high priority level have higher priority than all channels at the default priority
level. At the same priority level, a channel with a lower channel number has a higher priority than a channel with a
higher channel number. The DMA channel priority levels can be changed by writing into the appropriate bit in the
DMA_PRI_SET register.
11–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Operating Modes
DMA Transfer Types
The DMA controller supports various types of DMA transfers based on the primary and alternate control data
structure and number of requests required to complete a DMA transfer. The DMA transfer type is configured by
programming the appropriate values to the cycle_ctrl bits in the CHNL_CFG location of the control data
structure.
Based on the cycle_ctrl bits, the following DMA transfer types are supported:
• Invalid
• Basic
• Auto request
• Ping-Pong
• Memory Scatter-Gather
• Peripheral Scatter-Gather
DMA Transfer Type Usage table shows the various DMA transfer types that should be used by the peripherals and
software DMA. Use of software DMA transfer types for peripherals and vice versa is not recommended.
Table 11-6: DMA Transfer Type Usage
Software
Peripheral
Basic
Auto Request
Ping-Pong
Ping-Pong*1
Peripheral Scatter-Gather
Memory Scatter-Gather
*1
Software Ping-Pong DMA transfer operation is different from Peripheral Ping-Pong DMA transfer operation.
Invalid
This means that no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets the
cycle type to invalid to prevent it from repeating the same DMA cycle. Reading an invalid descriptor for any channel
generates a DMA error interrupt and the corresponding bit in DMA_INVALIDDESC_CLR is set.
Basic
In this mode, the controller can be configured to use either primary or alternate data structure by programming
DMA_ALT_CLR register for the corresponding channel. This mode is used for peripheral DMA transfers. While
using this mode for peripherals, the R_Power in CHNL_CFG must be set to 0, which means the peripheral needs to
present a request for every data transfer.
Once the channel is enabled, when the controller receives a request, it performs the following operations:
1. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–9
DMA Transfer Types
2. The controller arbitrates:
a. If a higher priority channel is requesting service, the controller services that channel, or
b. If the peripheral or software signals a request to the controller, it continues at Step 1.
3. At the end of the transfer, the controller interrupts the MCU using dma_done interrupt for the corresponding channel.
Auto-Request
In this mode, the controller must receive single request to enable the DMA controller to complete the entire DMA
cycle. This allows a large data transfer to occur, without significantly increasing the latency for servicing higher priority requests, or requiring multiple requests from the MCU or peripheral. This mode is useful for a memory-tomemory copy application using software DMA requests.
In this mode, the controller can be configured to use either primary or alternate data structure by programming the
DMA_ALT_CLR register for the corresponding channel.
After the channel is enabled, when the controller receives a request, it performs the following operations.
1. The controller performs, min (2R _ Power, N) transfers for the channel. If the number of transfers remaining is
zero, the flow continues at Step 3.
2. A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest
priority, the DMA cycle continues at Step 1.
3. At the end of the transfer, the controller interrupts the MCU using the dma_done interrupt for that channel.
Ping-Pong
In this mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle
using the other data structure. The controller continues to switch between primary and alternate, until it either reads
a data structure that is basic/auto-request, or the MCU disables the channel.
This mode is useful for transferring data using different buffers in the memory. In a typical application, the MCU is
required to configure both primary and alternate data structure before starting the transfer. As the transfer progresses, the host can subsequently configure primary or alternate control data structures in the interrupt service routine
when corresponding transfer ends.
The DMA controller interrupts the MCU using the dma_done interrupt after the completion of transfers associated
with each control data structure. The individual transfers using either the primary or the alternate control data
structures work exactly the same as a basic DMA transfer.
Software Ping-Pong DMA Transfer
In this mode, if the DMA request is from software, request will be generated automatically after each arbitration
cycle until completion of primary or alternate descriptor tasks. This final descriptor must use an auto-request transfer type.
11–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Transfer Types
Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
SW Request
Task A
dma_done[C]
Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Task B
SW Request
AutoReqs
dma_done[C]
Task C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
SW Request
Task C
dma_done[C]
Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
SW Request
Task D
AutoReq
dma_done[C]
Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
SW Request
Task E
Auto Reqs
dma_done[C]
End : Alternate, cycle_ctrl = 000
Auto Request
Figure 11-2: Software Ping-Pong DMA Transfer
Peripheral Ping-Pong DMA Transfer
In this mode, if the DMA request is from a peripheral, it needs to send DMA requests after every data transfer to
complete primary or alternate descriptor tasks and the final descriptor must be programmed to use a basic transfer
type.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–11
DMA Transfer Types
Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
Requests
Task A
dma_done[C]
Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Reqs
Task B
dma_done[C]
Task C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
Req
Task C
dma_done[C]
Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
Reqs
Task D
dma_done[C]
Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
Reqs
Task E
dma_done[C]
End : Alternate, cycle_ctrl = 000
Invalid
Figure 11-3: Peripheral Ping-Pong DMA Transfer
Memory Scatter-Gather
In this mode, the DMA controller needs to be configured to use both primary and alternate data structures. It uses
the primary data structure to program the control configuration for alternate data structure. The alternate data
structure is used for data transfers using a transfer similar to an auto-request DMA transfer. The controller arbitrates
after every primary transfer. The controller only needs one request to complete the entire transfer. This mode is used
when performing multiple memory-to-memory copy tasks. The MCU can configure all of them together and is not
required to intervene. The DMA controller interrupts the MCU using the dma_done interrupt when the entire
Scatter-Gather transaction is completed using a basic cycle.
In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data
structure to program the control structure of the alternate data structure. After this transfer is completed, it starts a
11–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Transfer Types
DMA cycle using the alternate data structure. After the cycle is completed, the controller performs another four
DMA transfers using the primary data structure.
The controller continues to switch from primary to alternate to primary, until:
• The MCU configures the alternate data structure for a basic cycle,
Or
• The DMA reads an invalid data structure.
Table 11-7: CHNL_CFG for Primary Data Structure in Memory Scatter-Gather Mode
Bit
Name
Value
Description
31:30
DST_INC
10
Configures the controller to use word increments for the address.
29:28
RESERVED
00
Undefined. Write as zero.
27:26
SRC_INC
10
Configures the controller to use word increments for the address.
25:24
SRC_SIZE
10
Configures the controller to use word transfers.
23:18
RESERVED
00
Undefined. Write as zero.
17:14
R_power
0010
Indicates that the DMA controller performs four transfers.
13:4
N_minus_1
User
Configures the controller to perform N DMA transfers, where N is a multiple of 4.
3
RESERVED
00
Undefined. Write as zero.
2:0
Cycle_ctrl
100
Configures the controller to perform a memory Scatter-Gather DMA cycle.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–13
DMA Transfer Types
Primary
Request
Alternate
Copy from A in
memory to
Alternate
Auto Req
Task A
Auto Req
N = 3, 2R = 4
Copy from B in
memory to
Alternate
Auto Req
Auto Reqs
Copy from C in
memory to
Alternate
Task B
N = 8, 2R = 2
Auto Req
Auto Req
Task C
Auto Req
N = 5, 2R = 8
Copy from D in
memory to
Alternate
Auto Req
Task D
N = 4, 2R = 4
dma_done[C]
Figure 11-4: Memory Scatter-Gather Transfer Process
Peripheral Scatter-Gather
In this mode, the DMA controller should be configured to use both primary and alternate data structures. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate
data structure is used for actual data transfers and each transfer takes place using the alternate data structure with a
basic DMA transfer. The controller does not arbitrate after every primary transfer. This mode is used when there are
multiple peripheral-to-memory DMA tasks to be performed. The MCU can configure all of them at the same time
and need not intervene in between.
This mode is similar to memory Scatter-Gather mode except for arbitration and request requirements. The DMA
controller interrupts the MCU using the dma_done interrupt when the entire Scatter-Gather transaction is completed using a basic cycle.
In peripheral Scatter-Gather mode, the controller receives an initial request from a peripheral and then performs
four DMA transfers using the primary data structure to program the alternate control data structure. It then immediately starts a DMA cycle using the al-ternate data structure, without re-arbitrating.
11–14
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Transfer Types
After this cycle is completed, the controller re-arbitrates and if it receives a request from the peripheral and this has
the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the al-ternate data structure without re-arbitrating.
The controller continues to switch from primary to alternate to primary until:
• The MCU configures the alternate data structure for a basic cycle,
Or
• The DMA reads an invalid data structure
Table 11-8: CHNL_CFG for Primary Data Structure in Peripheral Scatter-Gather Mode
Bit
Name
Value
Description
31:30
DST_INC
10
Configures the controller to use word increments for the address.
29:28
RESERVED
00
Undefined. Write as zero.
27:26
SRC_INC
10
Configures the controller to use word increments for the address.
25:24
SRC_SIZE
10
Configures the controller to use word transfers.
23:18
RESERVED
00
Undefined. Write as zero.
17:14
R_power
0010
Indicates that the DMA controller performs four transfers.
13:4
N_minus_1
user
Configures the controller to perform N DMA transfers, where N is a multiple of four.
3
RESERVED
00
Undefined. Write as zero.
2:0
Cycle_ctrl
110
Configures the controller to perform a memory Scatter-Gather DMA cycle.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–15
DMA Operating Modes
Primary
Request
Alternate
Copy from A in
memory to
Alternate
Req
Task A
For all primary to alternate transitions,
the controller does not enter the
arbitration process and immediately
perorms the DMA transfer that the
alternate channel control data structure
specifies.
N = 3, 2R = 4
Copy from B in
memory to
Alternate
Reqs
Task B
N = 8, 2R = 2
Copy from C in
memory to
Alternate
Task C
N = 5, 2R = 8
Task D
N = 4, 2R = 4
Req
Copy from D in
memory to
Alternate
dma_done[C]
Figure 11-5: Peripheral Scatter-Gather Transfer Process
DMA Interrupts and Exceptions
Error Management
The DMA controller generates an error interrupt to the core when a DMA error occurs. A DMA error can occur
due to a bus error or an invalid descriptor fetch. A bus error occurs while fetching the descriptor or performing a
data transfer. A bus error can occur when a read from or write to a reserved address location happens.
When a bus error occurs, the faulty channel is automatically disabled, and the corresponding status bit in the
DMA_ERRCHNL_CLR is set. If the DMA error is enabled in the NVIC, the error will also generate an interrupt. In
addition, the CHNL_CFG data structure for the corresponding channel will be updated with the latest n_count.
User can check this to know the number of successful data transfers before the bus error.
When the controller fetches an invalid descriptor, the faulty channel is automatically disabled, and the corresponding status bit in the DMA_INVALIDDESC_CLR register is set. If the DMA error is enabled in NVIC, the error also
generates an interrupt.
Address Calculation
The DMA controller calculates the source read address based on the SRC_END_PTR, the source address increment
setting in CHNL_CFG, and the current value of the N_Minus_1.
11–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Interrupts and Exceptions
Similarly, the destination write address is calculated based on the DST_END_PTR, destination address increment
setting in CHNL_CFG, and the current value of the N_Minus_1.
N_minus_1 is the current count of transfers to be done.
Address Decrement
Address decrement can be enabled to source and destination addresses. Source address decrement can be enabled for
channels by setting appropriate bits in the DMA_SRCADDR_SET register. Similarly, destination address decrement
can be enabled for channels by setting the required bits in the DMA_DSTADDR_SET register. The values written
into the source data end pointer (SRC_END_PTR) and destination data end pointer (DST_END_PTR) are still
used as the addresses for the last transfer as part of the DMA cycle. However, the start address will be computed
differently to the address increment scheme for either source read or destination write.
If the source decrement bit is set in the DMA_SRCADDR_SET register for a channel, its source address is computed
as follows:
If the destination decrement bit is set in the DMA_DSTADDR_SET register for a channel, its source address is computed as follows:
NOTES:
N_minus_1 is the current count of transfers to be done.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
Image Decrement figure shows all the combinations of source and destination decrement with their data movement
direction.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–17
DMA Operating Modes
Figure 11-8: Image Decrement
Endian Operation
The DMA controller does the transfer by default using a little-endian approach; however, this default behavior can
be changed by setting the corresponding channel bit in the DMA_BS_SET register. The endian operation is referred
to as byte swap.
Byte Swap Disabled
Byte swap is disabled by default. In this case, the data transfer is considered to be little-endian. Data arriving from a
peripheral is placed in sequence starting from the LSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 ... 0x0F, 0x10, it is stored by the
DMA in memory as follows:
1. 04_03_02_01
2. 08_07_06_05
3. 0C_0B_0A_09
4. 10_0F_0E_0D
11–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
DMA Operating Modes
Byte Swap Enabled
Byte swap is enabled on any channel by setting the corresponding bit in the DMA_BS_SET register. By setting the
bit, big-endian data transfers will occur. Data arriving from the peripheral will be placed in sequence starting from
the MSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 ... 0x0F, 0x10, it will be stored by
the DMA in memory as follows:
1. 01_02_03_04
2. 05_06_07_08
3. 09_0A_0B_0C
4. 0D_0E_0F_10
NOTES:
Byte swap happens on 32-bit data boundaries. The transfer size must be a multiple of 4.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
When using byte swap, care must be taken to ensure that the source data address is constant for the full data transfer. For example, SPI where the data source is always from the same location (a FIFO).
Byte swap functionality is independent of DMA transfer size and can be 8-bit, 16-bit, or 32-bit.
DMA Channel Enable/Disable
Before issuing a DMA request, the DMA channel should be enabled, otherwise, the DMA request for the corresponding channel is driven as DONE interrupt. Any DMA channel can be enabled by writing the corresponding bit
in the DMA_EN_SET register. DMA controller disables the channel when the corresponding dma_done interrupt is
generated. However, you can also disable any channel by writing to the corresponding bit in the DMA_EN_CLR
register.
Whenever a channel is disabled, based on the current state of the DMA controller, it does the following:
• If the user disables the channel and there is no request pending for that channel, it is disabled immediately.
• If the user disables the channel that is not getting serviced, but its request is posted, its pending request will be
cleared, and the channel is disabled immediately.
• If the user disables a channel that has been selected after arbitration but yet to start transfers, the controller
completes the arbitration cycle and then disables channel.
• If the user disables the channel when it is getting serviced, controller completes the current arbitration cycle
and then disables the channel.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–19
DMA Operating Modes
DMA Master Enable
The DMA_CFG.MEN bit acts as a soft reset to the DMA controller. Any activity in the DMA controller can be
performed only when this bit is set to 1. Clearing this bit to 0, clears all cached descriptors within the controller and
resets the controller.
Power-down Considerations
Finish all the on-going DMA transfers before powering down the chip to hibernate. However, if the user decides to
hibernate as early as possible (current data transfers are ignored), the DMA controller should be disabled by clearing
the DMA_CFG.MEN bit before going into hibernate.
NOTE: If hibernate mode is selected when a DMA transfer is in progress, the transfer discontinues on resuming
from hibernate. The DMA returns to the disabled state.
After hibernate (or POR), the DMA must be enabled again by setting the DMA_CFG.MEN bit.
The following registers are retained in hibernate mode:
• DMA_PDBPTR
• DMA_ADBPTR
• DMA_RMSK_SET
• DMA_RMSK_CLR
• DMA_PRI_SET
• DMA_PRI_CLR
• DMA_BS_SET
• DMA_BS_CLR
• DMA_SRCADDR_SET
• DMA_SRCADDR_CLR
• DMA_DSTADDR_SET
• DMA_DSTADDR_CLR
DMA Programming Model
The following section describes the programming sequence to configure the DMA.
Programming Guidelines
1. Enable the DMA controller in the DMA_CFG register.
2. Enable the desired DMA channel.
11–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
3. Setup the DMA base pointer.
4. Setup the DMA descriptor for data transmission.
5. Generate the software DMA request in the DMA_SWREQ register.
ADuCM4050 DMA Register Descriptions
DMA (DMA) contains the following registers.
Table 11-9: ADuCM4050 DMA Register List
Name
Description
DMA_ADBPTR
DMA Channel Alternate Control Database Pointer
DMA_ALT_CLR
DMA Channel Primary Alternate Clear
DMA_ALT_SET
DMA Channel Primary Alternate Set
DMA_BS_CLR
DMA Channel Bytes Swap Enable Clear
DMA_BS_SET
DMA Channel Bytes Swap Enable Set
DMA_CFG
DMA Configuration
DMA_DSTADDR_CLR
DMA Channel Destination Address Decrement Enable Clear
DMA_DSTADDR_SET
DMA Channel Destination Address Decrement Enable Set
DMA_EN_CLR
DMA Channel Enable Clear
DMA_EN_SET
DMA Channel Enable Set
DMA_ERRCHNL_CLR
DMA per Channel Error Clear
DMA_ERR_CLR
DMA Bus Error Clear
DMA_INVALIDDESC_CLR
DMA per Channel Invalid Descriptor Clear
DMA_PDBPTR
DMA Channel Primary Control Database Pointer
DMA_PRI_CLR
DMA Channel Priority Clear
DMA_PRI_SET
DMA Channel Priority Set
DMA_REVID
DMA Controller Revision ID
DMA_RMSK_CLR
DMA Channel Request Mask Clear
DMA_RMSK_SET
DMA Channel Request Mask Set
DMA_SRCADDR_CLR
DMA Channel Source Address Decrement Enable Clear
DMA_SRCADDR_SET
DMA Channel Source Address Decrement Enable Set
DMA_STAT
DMA Status
DMA_SWREQ
DMA Channel Software Request
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–21
ADuCM4050 DMA Register Descriptions
DMA Channel Alternate Control Database Pointer
The DMA_ADBPTR read-only register returns the base address of the alternate channel control data structure. This
register removes the necessity for application software to calculate the base address of the alternate data structure.
This register cannot be read when the DMA controller is in the reset state.
15 14 13 12 11 10 9
0
0
0
0
0
0
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ADDR[15:0] (R)
Base Address of the Alternate Data
Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR[31:16] (R)
Base Address of the Alternate Data
Structure
Figure 11-7: DMA_ADBPTR Register Diagram
Table 11-10: DMA_ADBPTR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 ADDR
Base Address of the Alternate Data Structure.
(R/NW)
11–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Primary Alternate Clear
The DMA_ALT_CLR write-only register enables the user to configure the appropriate DMA channel to use the primary control data structure. Each bit of the register represents the corresponding channel number in the DMA controller.
Note: The DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather
and peripheral scatter-gather transfers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Select Primary Data Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Select Primary Data Structure
Figure 11-8: DMA_ALT_CLR Register Diagram
Table 11-11: DMA_ALT_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Select Primary Data Structure.
Set the appropriate bit to select the primary data structure for the corresponding DMA
channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_ALT_CLR.CHAN[C] = 0, No effect. Use the DMA_ALT_SET register to select
the alternate data structure.
DMA_ALT_CLR.CHAN[C] = 1, Selects the primary data structure for channel C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–23
ADuCM4050 DMA Register Descriptions
DMA Channel Primary Alternate Set
The DMA_ALT_SET register enables the user to configure the appropriate DMA channel to use the alternate control data structure. Reading the register returns the status of which data structure is in use for the corresponding
DMA channel. Each bit of the register represents the corresponding channel number in the DMA controller.
Note: The DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather
and peripheral scatter-gather transfers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Control Structure Status / Select Alternate
Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Control Structure Status / Select Alternate
Structure
Figure 11-9: DMA_ALT_SET Register Diagram
Table 11-12: DMA_ALT_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
Control Structure Status / Select Alternate Structure.
Returns the channel control data structure status, or selects the alternate data structure
for the corresponding DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Read:
DMA_ALT_SET.CHAN[C] = 0, DMA channel C is using the primary data structure.
DMA_ALT_SET.CHAN[C] = 1, DMA channel C is using the alternate data structure.
When Written:
DMA_ALT_SET.CHAN[C] = 0, No effect. Use the DMA_ALT_CLR register to set bit
[C] to 0.
DMA_ALT_SET.CHAN[C] = 1, Selects the alternate data structure for channel C.
11–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Bytes Swap Enable Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable Byte Swap
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Disable Byte Swap
Figure 11-10: DMA_BS_CLR Register Diagram
Table 11-13: DMA_BS_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Disable Byte Swap.
The DMA_BS_CLR write-only register enables the user to configure a DMA channel
to not use byte swapping and use the default operation. Each bit of the register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to
DMA channel and bit M-1 corresponds to DMA channel M-1.
When Written:
DMA_BS_CLR.CHAN[C] = 0, No effect. Use the DMA_BS_SET register to enable
byte swap on channel C.
DMA_BS_CLR.CHAN[C] = 1, Disables Byte Swap on channel C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–25
ADuCM4050 DMA Register Descriptions
DMA Channel Bytes Swap Enable Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Byte Swap Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Byte Swap Status
Figure 11-11: DMA_BS_SET Register Diagram
Table 11-14: DMA_BS_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
11–26
Byte Swap Status.
This register is used to configure a DMA channel to use byte swap. Each bit of the
register represents the corresponding channel number in the DMA controller. Bit 0
corresponds to DMA channel 0 and bit M-1 corresponds to DMA channel M-1 When
Read: DMA_BS_SET.CHAN[C] = 0, Channel C Byte Swap is disabled.
DMA_BS_SET.CHAN[C] = 1, Channel C Byte Swap is enabled. When Written:
DMA_BS_SET.CHAN[C] = 0, No effect. Use the DMA_BS_CLR register to disable
byte swap on channel C DMA_BS_SET.CHAN[C] = 1, Enables Byte Swap on channel
C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MEN (W)
Controller Enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-12: DMA_CFG Register Diagram
Table 11-15: DMA_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 MEN
(RX/W)
Controller Enable.
0 Disable controller
1 Enable controller
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–27
ADuCM4050 DMA Register Descriptions
DMA Channel Destination Address Decrement Enable Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable Destination Address Decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Disable Destination Address Decrement
Figure 11-13: DMA_DSTADDR_CLR Register Diagram
Table 11-16: DMA_DSTADDR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Disable Destination Address Decrement.
The DMA_DSTADDR_CLR write-only register enables the user to configure a DMA
channel to use the default destination address in increment mode. Each bit of the register represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_DSTADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_SET register to enable destination address decrement on channel C.
DMA_DSTADDR_CLR.CHAN[C] = 1, Disables destination address decrement on
channel C.
11–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Destination Address Decrement Enable Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Destination Address Decrement Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Destination Address Decrement Status
Figure 11-14: DMA_DSTADDR_SET Register Diagram
Table 11-17: DMA_DSTADDR_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
Destination Address Decrement Status.
The DMA_DSTADDR_SET register is used to configure the destination address of a
DMA channel to decrement the address instead of incrementing the address after each
access. Each bit of the register represents the corresponding channel number in the
DMA controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to
DMA channel M-1.
When Read:
DMA_DSTADDR_SET.CHAN[C] = 0, Channel C destination address decrement is
disabled.
DMA_DSTADDR_SET.CHAN[C] = 1, Channel C destination address decrement is
enabled.
When Written:
DMA_DSTADDR_SET.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_CLR register to disable destination address decrement on channel C.
DMA_DSTADDR_SET.CHAN[C] = 1, Enables destination address decrement on
channel C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–29
ADuCM4050 DMA Register Descriptions
DMA Channel Enable Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Disable DMA Channels
Figure 11-15: DMA_EN_CLR Register Diagram
Table 11-18: DMA_EN_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Disable DMA Channels.
This register allows for the disabling of DMA channels. This register is write only.
Each bit of the register represents the corresponding channel number in the DMA
controller. Note: The controller disables a channel automatically, by setting the appropriate bit, when it completes the DMA cycle. Set the appropriate bit to disable the corresponding channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_EN_CLR.CHAN[C] = 0, No effect. Use the DMA_EN_SET register to enable
the channel.
DMA_EN_CLR.CHAN[C] = 1, Disables channel C.
11–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Enable Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Enable DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Enable DMA Channels
Figure 11-16: DMA_EN_SET Register Diagram
Table 11-19: DMA_EN_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
Enable DMA Channels.
This register allows for the enabling of DMA channels. Reading the register returns the
enable status of the channels. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to enable the corresponding channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M -1
When Read:
DMA_EN_SET.CHAN[C] = 0, Channel C is disabled.
DMA_EN_SET.CHAN[C] = 1, Channel C is enabled.
When Written:
DMA_EN_SET.CHAN[C] = 0, No effect. Use the DMA_EN_CLR register to disable
the channel.
DMA_EN_SET.CHAN[C] = 1, Enables channel C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–31
ADuCM4050 DMA Register Descriptions
DMA per Channel Error Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Per Channel Bus Error Status/Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W1C)
Per Channel Bus Error Status/Clear
Figure 11-17: DMA_ERRCHNL_CLR Register Diagram
Table 11-20: DMA_ERRCHNL_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W1C)
Per Channel Bus Error Status/Clear.
This register is used to read and clear the per channel DMA bus error status. The error
status is set if the controller encountered a bus error while performing a transfer. If a
bus error occurs on a channel, that channel is automatically disabled by the controller.
The other channels are unaffected. Write one to clear bits.
When Read:
0: No bus error occurred.
1: A bus error control is pending.
When Written:
0: No effect.
1: Bit is cleared.
11–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Bus Error Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Bus Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W1C)
Bus Error Status
Figure 11-18: DMA_ERR_CLR Register Diagram
Table 11-21: DMA_ERR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W1C)
Bus Error Status.
This register is used to read and clear the DMA bus error status. The error status is set
if the controller encountered a bus error while performing a transfer or when it reads
an invalid descriptor (whose cycle control is 3'b000). If a bus error occurs or invalid
cycle control is read on a channel, that channel is automatically disabled by the controller. The other channels are unaffected. Write one to clear bits.
When Read:
0: No bus_error/invalid cycle control occurred.
1: A bus_error/invalid cycle control is pending.
When Written:
0: No effect.
1: Bit is cleared.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–33
ADuCM4050 DMA Register Descriptions
DMA per Channel Invalid Descriptor Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Per Channel Invalid Descriptor Status/Clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W1C)
Per Channel Invalid Descriptor Status/Clear
Figure 11-19: DMA_INVALIDDESC_CLR Register Diagram
Table 11-22: DMA_INVALIDDESC_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W1C)
Per Channel Invalid Descriptor Status/Clear.
This register is used to read and clear the per channel DMA invalid descriptor status.
The per channel invalid descriptor status is set if the controller reads an invalid descriptor (cycle control is 3'b000). If it reads invalid cycle control for a channel, that
channel is automatically disabled by the controller. The other channels are unaffected.
Write one to clear bits.
When Read:
0: No invalid cycle control occurred.
1: An invalid cycle control is pending.
When Written:
0 No effect.
1 Bit is cleared.
11–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Primary Control Database Pointer
The DMA_PDBPTR register must be programmed to point to the primary channel control base pointer in the system memory. The amount of system memory that must be assigned to the DMA controller depends on the number
of DMA channels used and whether the alternate channel control data structure is used. This register cannot be read
when the DMA controller is in the reset state.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ADDR[15:0] (R/W)
Pointer to the Base Address of the
Primary Data Structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR[31:16] (R/W)
Pointer to the Base Address of the
Primary Data Structure
Figure 11-20: DMA_PDBPTR Register Diagram
Table 11-23: DMA_PDBPTR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 ADDR
(R/W)
Pointer to the Base Address of the Primary Data Structure.
5 + log(2) M LSBs are reserved and must be written 0. M is number of channels.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–35
ADuCM4050 DMA Register Descriptions
DMA Channel Priority Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHPRICLR[15:0] (W)
Configure Channel for Default Priority
Level
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHPRICLR[26:16] (W)
Configure Channel for Default Priority
Level
Figure 11-21: DMA_PRI_CLR Register Diagram
Table 11-24: DMA_PRI_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHPRICLR
(RX/W)
Configure Channel for Default Priority Level.
The DMA_PRI_CLR write-only register enables the user to configure a DMA channel
to use the default priority level. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to select the default
priority level for the specified DMA channel.
Bit 0 corresponds to DMA channel and bit M-1 corresponds to DMA channel M-1.
When Written:
DMA_PRI_CLR.CHPRICLR[C] = 0, No effect. Use the DMA_PRI_SET register to
set channel C to the high priority level.
DMA_PRI_CLR.CHPRICLR[C] = 1, Channel C uses the default priority level.
11–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Priority Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Configure Channel for High Priority
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Configure Channel for High Priority
Figure 11-22: DMA_PRI_SET Register Diagram
Table 11-25: DMA_PRI_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Configure Channel for High Priority.
This register enables the user to configure a DMA channel to use the high priority level. Reading the register returns the status of the channel priority mask. Each bit of the
register represents the corresponding channel number in the DMA controller. Returns
the channel priority mask status, or sets the channel priority to high.
Bit 0 corresponds to DMA channel 0, bit M-1 corresponds to DMA channel M-1.
When Read:
DMA_PRI_SET.CHAN[C] = 0, DMA channel C is using the default priority level.
DMA_PRI_SET.CHAN[C] = 1, DMA channel C is using a high priority level.
When Written:
DMA_PRI_SET.CHAN[C] = 0, No effect. Use the DMA_PRI_CLR register to set
channel C to the default priority level.
DMA_PRI_SET.CHAN[C] = 1, Channel C uses the high priority level.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–37
ADuCM4050 DMA Register Descriptions
DMA Controller Revision ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
VALUE (R)
DMA Controller Revision ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-23: DMA_REVID Register Diagram
Table 11-26: DMA_REVID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
DMA Controller Revision ID.
(R/NW)
11–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Request Mask Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Clear Request Mask Set Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Clear Request Mask Set Bits
Figure 11-24: DMA_RMSK_CLR Register Diagram
Table 11-27: DMA_RMSK_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Clear Request Mask Set Bits.
This register enables DMA requests from peripherals by clearing the mask set in
DMA_RMSK_SET register. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate bit to clear the corresponding
DMA_RMSK_SET.CHAN bit.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_RMSK_CLR.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register to
disable DMA requests.
DMA_RMSK_CLR.CHAN[C] = 1, Enables peripheral associated with channel C to
generate DMA requests.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–39
ADuCM4050 DMA Register Descriptions
DMA Channel Request Mask Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Mask Requests from DMA Channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Mask Requests from DMA Channels
Figure 11-25: DMA_RMSK_SET Register Diagram
Table 11-28: DMA_RMSK_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
Mask Requests from DMA Channels.
This register disables DMA requests from peripherals. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate
bit to mask the request from the corresponding DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Read:
DMA_RMSK_SET.CHAN[C] = 0, Requests are enabled for channel C.
DMA_RMSK_SET.CHAN[C] = 1, Requests are disabled for channel C.
When Written:
DMA_RMSK_SET.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register to enable DMA requests.
DMA_RMSK_SET.CHAN[C] = 1, Disables peripheral associated with channel C from
generating DMA requests.
11–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Channel Source Address Decrement Enable Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable Source Address Decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Disable Source Address Decrement
Figure 11-26: DMA_SRCADDR_CLR Register Diagram
Table 11-29: DMA_SRCADDR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Disable Source Address Decrement.
The DMA_SRCADDR_CLR write-only register enables the user to configure a DMA
channel to use the default source address in increment mode. Each bit of the register
represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_SRCADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_SRCADDR_SET register to enable source address decrement on channel C.
DMA_SRCADDR_CLR.CHAN[C] = 1, Disables Address source decrement on channel
C.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–41
ADuCM4050 DMA Register Descriptions
DMA Channel Source Address Decrement Enable Set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Source Address Decrement Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (R/W)
Source Address Decrement Status
Figure 11-27: DMA_SRCADDR_SET Register Diagram
Table 11-30: DMA_SRCADDR_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(R/W)
Source Address Decrement Status.
The DMA_SRCADDR_SET register is used to configure the source address of a DMA
channel to decrement the address instead of incrementing the address after each access.
Each bit of the register represents the corresponding channel number in the DMA
controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to DMA
channel M-1.
When Read:
DMA_SRCADDR_SET.CHAN[C] = 0, Channel C Source Address decrement is disabled.
DMA_SRCADDR_SET.CHAN[C] = 1, Channel C Source Address decrement is enabled.
When Written:
DMA_SRCADDR_SET.CHAN[C] = 0, No effect. Use the DMA_SRCADDR_CLR register to disable source address decrement on channel C.
DMA_SRCADDR_SET.CHAN[C] = 1, Enables source address decrement on channel
C.
11–42
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 DMA Register Descriptions
DMA Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MEN (R)
Enable Status of the Controller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
CHANM1 (R)
Number of Available DMA Channels
Minus 1
Figure 11-28: DMA_STAT Register Diagram
Table 11-31: DMA_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
20:16 CHANM1
(R/NW)
0 MEN
(R/NW)
Number of Available DMA Channels Minus 1.
With 27 channels available, the register will read back 0x1A.
Enable Status of the Controller.
0 Controller is disabled
1 Controller is enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
11–43
ADuCM4050 DMA Register Descriptions
DMA Channel Software Request
The DMA_SWREQ register enables the generation of software DMA request. Each bit of the register represents the
corresponding channel number in the DMA controller. M is the number of DMA channels
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Generate Software Request
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[26:16] (W)
Generate Software Request
Figure 11-29: DMA_SWREQ Register Diagram
Table 11-32: DMA_SWREQ Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26:0 CHAN
(RX/W)
Generate Software Request.
Set the appropriate bit to generate a software DMA request on the corresponding
DMA channel.
Bit 0 corresponds to DMA channel 0
Bit M-1 corresponds to DMA channel M-1
When Written:
DMA_SWREQ.CHAN[C] = 0, Does not create a DMA request for channel C.
DMA_SWREQ.CHAN[C] = 1, Generates a DMA request for channel C.
These bits are automatically cleared by the hardware after the corresponding software
request completes.
11–44
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Cryptography (CRYPTO)
12 Cryptography (CRYPTO)
Crypto is a hardware accelerator block that encloses the AES Cipher, NIST Block modes of operation, SHA-256
hash function generator, Keyed HMAC accelerator, Key wrap and unwrap module, and a protected key storage.
Advanced Encryption Standard (AES) is the specification for a symmetric key algorithm to encrypt electronic data
announced by the National Institute of Standards and Technology (NIST) in the year 2001 to replace the older
DES Standard. The AES algorithm operates on a fixed data block of 128 bits.
Block modes of operation are confidential and authentication modes of operation for use with a symmetric key
block cipher algorithm. In this block, the supported symmetric key cipher is AES.
Secure Hash Algorithm (SHA) is a hashing algorithm that works on messages parsed into 512-bit data blocks and
generates a digest.
Keyed HMAC is a SHA-256 based algorithm to generate a Message Authentication Code (MAC) in combination
with a secret cryptographic key.
Key wrap and unwrap module is a NIST approved key encryption-decryption algorithm for secure storage and
transport of keys.
Protected key storage is a dedicated space accessible only by the crypto module for secure non-volatile storage of
cryptographic keys.
This document assumes familiarity with the operation of the AES standard, NIST block cipher modes of operation,
SHA-256 algorithm, SHA-256 based Keyed HMAC, and Key wrap-unwrap algorithms. For more information, refer
to the following publications.
Table 12-1: NIST Publication List
AES standard
Federal Information Processing Standard (FIPS) 197
NIST Block Modes of Operation
Special Publication-800-38A, B & C
SHA
FIPS 180-4
HMAC
FIPS 198-1 (Keyed HMAC)
Key Wrap
SP800-38F (Methods for Key Wrapping)
CCM*
Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–1
Crypto Features
Crypto Features
The ADuCM4050 MCU supports the following features:
• 32-bit APB Slave
• Two 128-bit buffers:
• Input buffer
• Output buffer
• One 512-bit buffer to store input data for HMAC and SHA modes
• Two DMA channels:
• Input buffer
• Output buffer
• AES Cipher Key Lengths supported:
• 128-bit
• 256-bit
• AES Cipher Key Source
• Programmable through MMR
• Not readable (read as zero in software)
• Supported Modes:
• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher MAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
• SHA - 256 Mode
• Protected key storage with key wrap and unwrap
• HMAC signature generation
Crypto Functional Description
This section provides information on the function of the Crypto block used by the ADuCM4050 MCU.
12–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Crypto Functional Description
Crypto Block Diagram
The figure shows the Crypto block used by the ADuCM4050 MCU.
Figure 12-1: Crypto Block
Crypto is a 32-bit APB DMA capable peripheral. There are two buffers provided for data I/O operations. These
buffers are 32-bit wide and will read in or read out 128-bits in four data accesses. Input data and output data byte
swapping is supported using CRYPT_CFG.AES_BYTESWAP and CRYPT_CFG.SHA_BYTESWAP configuration
bits. Additionally, the CRYPT_CFG.KEY_BYTESWAP bit allows software to byte swap key when programming
them to MMR.
When enabled, the block takes the data from its input buffer and gives out the processed data through the output
buffer. DMA can be used for performing these data operations, which is critical to save power. Ensure that the configuration bits, keys and other relevant registers are set to the desired values before the block is enabled and data
transfer is initiated.
Crypto Operating Modes
The following block modes of operation are supported:
• CTR mode: Counter mode
• CBC mode: Cipher Block Chaining mode
• MAC mode: Message Authentication Code
• CCM mode: Cipher Block Chaining-Message Authentication Code mode
• ECB mode: Electronic Code Book mode
• CCM* mode: Modified CCM for WPAN Standard
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–3
Crypto Data Transfer
Crypto also supports the following modes of operation:
• PrKStor Mode: Protected Key Storage with hardware accelerators for Key wrap and unwrap in a secure setting
• SHA-256: Hash generating using SHA-256 algorithm
• Keyed HMAC: SHA-256 based authentication mode
Mode enable bit fields in the CRYPT_CFG register must be set to enable the desired mode of operation. A particular block mode is enabled by setting the appropriate bit field to 1.
Enable only one block mode of operation at a given time.
The following are the bit fields to enable different modes of operation: CRYPT_CFG.ECBEN,
CRYPT_CFG.CTREN, CRYPT_CFG.CBCEN, CRYPT_CFG.CCMEN, CRYPT_CFG.CMACEN,
CRYPT_CFG.SHA256EN, CRYPT_CFG.PRKSTOREN, and CRYPT_CFG.HMACEN.
Enabling multiple block modes causes unpredictable results. No error or warning is flagged. CCM* mode is enabled
by using the CRYPT_CFG.CCMEN bit.
Encryption/Decryption
The CRYPT_CFG.ENCR bit is used to select encryption/decryption operation for the different block modes involving the AES cipher. When decryption is enabled, the key schedule value for the final round is calculated and
written back into the AESKEY register set by overwriting the original AESKEY values. Therefore, for a new encryption operation, the AESKEY values must be programmed again.
Crypto Data Transfer
The input buffer and the output buffer hold 128-bits of data. Being a peripheral on a 32-bit APB bus, the block is
accessed by a 32-bit data bus. Therefore, four reads/writes are required to empty/fill the output/input buffer.
In SHA256 mode, the results are updated in the CRYPT_SHAH0.SHAHASH0 to CRYPT_SHAH7.SHAHASH7
registers, and are not given out in the output buffer. Results for block modes of operation are streamed out of the
output buffer.
Crypto Data Rate
Depending on the block mode and key length chosen for the AES Cipher, the rate at which data is processed
changes.
The following list shows the computation time involved in different block modes of operation. The numbers do not
include the buffer read and write time which are controlled by the DMA or core data rates. The rates are written for
128/256 key length cases.
• ECB Mode: 40/56 clock cycles
• CBC Mode: 40/56 clock cycles
12–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Crypto Data Transfer
• CTR Mode: 40/56 clock cycles
• MAC Mode: 40/56 clock cycles
• CCM Mode: 80/102 clock cycles
If input buffer is provided with data at the rate of one word per clock cycle, SHA-256 computation takes 64 clock
cycles. Input data rate is less than one word per 2 clock cycles as Crypto input data buffer supports APB protocol.
Data Pipeline
In block mode of operation, as soon as 128 bits of data (say block B1) is written into the input buffer, the data is
copied internally for computation and the next 128 bits of data (say block B2) may be written into the input buffer.
By the time block B2 is written, if computation on the block B1 is not complete, the input buffer will remain full
and further writes will not be permitted. Appropriate interrupts and status registers are updated. As soon as block B1
processing is completed the results are moved to the output buffer and computation begins on the B2. If B1 is not
read out of the output buffer by the time processing on B2 is completed, the block stalls. Appropriate interrupt and
status registers are set.
DMA Capability
The block supports use of DMA to transfer data to or from the buffers. The DMA is expected to do four word
transfers per DMA request on both the input and output buffers. The DMA requesting for the buffers can be enabled by setting the CRYPT_CFG.INDMAEN and CRYPT_CFG.OUTDMAEN bits. The block raises the input buffer DMA request line high till the input buffer is filled. Similarly, the DMA request on the output buffer is held
high till the output buffer is emptied.
The programmer must not change the configuration bits in the middle of a data transaction. Else, it may result in
wrong output, and no error or warning is raised.
Core Transfer
If DMA is not used, then the software is expected to keep track of the number of words that are to be transferred to
the block and read back from the block. The bit-fields that indicate the status and error conditions are available in
the CRYPT_STAT register. The interrupts for different conditions can be enabled in the CRYPT_INTEN register.
DMA based data transfer is recommended as it is performance efficient and power efficient.
Data Formatting
This section explains how to map the input data and keys to the Crypto registers, and the format in which data can
be expected from the output buffer.
Consider the following key, input data, and output data. The key, plain text, and cipher text are taken from the data
mentioned in the NIST standard.
Key[0:15]: 2b7e151628aed2a6abf7158809cf4f3c
Plain text[0:15]: 6bc1bee22e409f96e93d7e117393172a
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–5
Data Formatting
Cipher Text[0:15]: 3ad77bb40d7a3660a89ecaf32466ef97
This 128-bit key is mapped to the AESKEY registers as follows:
AESKEYi = Key[i*4+3:i*4];
For the above example,
AESKEY0[31:0] = 0x16157e2b;
AESKEY1[31:0] = 0xa6d2ae28;
AESKEY2[31:0] = 0x8815f7ab;
AESKEY3[31:0] = 0x3c4fcf09;
The plain text must be fed to the input buffer via APB writes using DMA/Core as follows:
for (i=0; i<4; i++)
{
Input_buffer = plain_text[i*4+3:i*4];
}
The example plain text can be mapped to input buffer writes as follows:
write(Input_buffer,
write(Input_buffer,
write(Input_buffer,
write(Input_buffer,
0xe2bec16b);
0x 969f402e);
0x117e3de9);
0x2a179373);
The ciphertext block can be read from the output buffer in four consecutive reads.
for (i=0; i<4; i++)
{
cipher_text [i*4+3:i*4] = read(output_buffer);
}
Byte-Swap Configuration
Three configuration bits have been provided for byte swapping the data written to the crypto buffers and key registers.
A byte swap operation is defined as:
Input String: 0xB3B2B1B0
Ouput String: 0xB0B1B2B3
AES_BYTESWAP
This bit when set, byte swaps the data written to input buffer for block modes of operation and also the expected
data out of the output buffer.
SHA_BYTESWAP
This bit when set, byte swaps the data written to input buffer for SHA and HMAC operations.
12–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Interrupts
KEY_BYTESWAP
Additional flexibility has been provided to byte swap the data written to CRYPT_AESKEY0-CRYPT_AESKEY7 ,
CRYPT_KUW0-CRYPT_KUW15, CRYPT_KEYValStr1, and CRYPT_KEYValStr2 registers.
Interrupts
INRDY
This interrupt indicates that the input buffer is not full. If enabled, this triggers interrupts as long as the input buffer
is not filled. As this interrupt is used when the data buffer is being written by the core, fill the input buffer from the
ISR.
This interrupt must be used to feed data to the Crypto accelerators for all AES based operations. This interrupt
must not be used for any SHA based operation or HMAC accelerator.
OUTRDY
This interrupt indicates that the output buffer holds data and is waiting to be read. This will remain set as long as
the output buffer is not empty. As this interrupt is used when the data buffer is being read by the core, read the
entire 128-bits in the ISR.
This interrupt is to be used with AES block cipher modes only and not with SHA.
SHADONE
This interrupt indicates that the SHA computation is completed. New data may be written into the input buffer or
that the hash results may be read out of the CRYPT_SHAH0 to CRYPT_SHAH7 registers.
INOVR
This interrupt indicates that the input buffer overflow event has occurred. The causes for this may be:
• The output buffer has not been read. This stalls the block.
• The input data rate is higher than the rate the Crypto block can process.
When the DMA or core program is programmed as recommended, this interrupt must not be raised.
Crypto operation is not reliable if input overflows.
HMACDONE
This interrupt indicates that the final step in the HMAC operation is complete. The result of the HMAC operation
can be read from the SHARES register set.
HMACMSGRDY
This status bit indicates that the HMAC block has finished hashing the KEY IPAD and is ready to take data input.
The corresponding status bit must be cleared in the interrupt routine. Once the HMAC controller has finished
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–7
Crypto Error Conditions
hashing the current data block this interrupt will trigger again is enabled. For the last message data block, the software must indicate it using CRYPT_SHA_LAST_WORD.O_LAST_WORD and
CRYPT_SHA_LAST_WORD.O_BITS_VALID bits.
PRKSTOR_CMD_DONE
This bit indicates that the protected key store operation is done. Support for several operations including key wrapunwrap and storing the keys in a secure area in the flash is provided.
Crypto Error Conditions
If a read is attempted from the output buffer when the output data buffer is empty, there is an underflow error. The
block does not generate a DMA request on the Output buffer channel when the output buffer is empty.
If the Crypto block is disabled at any stage during the computation, the data output is no longer reliable. The state
machine is reset.
If a write is attempted to the input buffer when it is full, there will be an overflow error. The block does not generate
a DMA request on the Input buffer channel when the Input buffer is full.
The input and output buffers can be flushed by writing 1 to the corresponding flush bits in the CRYPT_CFG register.
Interrupts can be enabled by writing 1 into the corresponding bits in the CRYPT_INTEN register.
Clearing interrupts is to be done by writing 1 to the respective bits in the CRYPT_STAT register.
The protected key store mode (CRYPT_CFG.PRKSTOREN or CRYPTO_CFG.BLKEN bit) must not be disabled
by the software if the CRYPT_STAT.PRKSTORBUSY bit is set.
Crypto Status Bits
INWORDS/OUTWORDS
These fields hold information about the number of words the input and output Buffers contain at that moment.
This information can be used in situations when the Input/output Buffers are not empty/full to know the number
words which need to be written or read.
SHADONE
This field indicates that the hash computation on the currently provided data is complete.
SHABUSY
This field indicates that hash computation is on-going. When this signal goes low, it is an indication that hash computation is complete and that the user can read out the hash result.
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Crypto Status Bits
INOVR
This field indicates that an overflow event has occurred on the input buffer. The status bit is sticky and can be
cleared by writing 1 into the bit field.
HMACDONE
This bit indicates that the HMAC operation on the current message input is complete and the result can be read out
of the SHARES register set.
HMACBUSY
This bit indicates that HMAC accelerator is currently busy. If this bit is set, the result in the SHARES register set is
an intermediate result and is read as zero.
HMACMSGRDY
This bit indicates that the HMAC block is ready to take message input from the user, that is, the first stage of
SHA256 computation with key xor ipad is done. This bit further goes low while SHA256 is processing the current
message input block.
PRKSTOR_CMD_DONE
This bit when set indicates that the current PrKStor command has finished and further commands can be issued to
PrKStor.
PRKSTOR_CMD_FAIL
This nit when set along with the CRYPT_STAT. PRKSTOR_CMD_DONE bit indicates that the current PrKStor
command has failed.
The following are the reasons for the failure:
• Unwrap Command: It may fail when the validation string obtained after unwrap does not match any of the
three validation strings specified in the document.
• RETRIEVE_KEY: This command can fail due to no response from flash controller or the key being corrupted
due to ECC errors. In this case, the retrieved key is zeroed in the KUW registers.
• Erase and Destroy commands: They may fail due to no response from flash as flash may be busy in some operation when the commands were issued.
PRKSTOR_RET_STATUS
These status bits indicates the ECC status from flash reads which is similar to the ECC status in flash.
CMD_ISSUED
This retains the last command issued until the mode or block is disabled or a new command is issued.
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Crypto Keys
PRKSTOR_BUSY
This status bit indicates that a command is in progress and PrKStor should not disabled during this stage. An ongoing PrKStor command must be allowed to complete before going to hibernate to maintain the integrity of the
PrKStor.
Crypto Keys
User must program the key used for the AES Cipher in the key registers from CRYPT_AESKEY0 to
CRYPT_AESKEY7.
Key Length
The AES Cipher can be used with two different ley lengths: 128 and 256 bits. It is selected by setting the
CRYPT_CFG.KEYLEN bit. The registers CRYPT_AESKEY0 to CRYPT_AESKEY7 hold the key to be used in
the AES Cipher.
CRYPT_CFG.KEYLEN when set to 0x2 indicates that a 256-bit key is used. When reset to 0x0, it indicates that a
128-bit key is used for Crypto operation.
Key Programming
The key registers can be programmed in any order. Registers that are used for key length 256 must not be programmed when the selected key length is 128 bits.
The following list shows how the key (K) used for the AES Cipher operations are constructed from the AESKEY
register set:
CRYPT_AESKEY0 = K[31:0]
CRYPT_AESKEY1 = K[63:32]
CRYPT_AESKEY2 = K[95:64]
CRYPT_AESKEY3 = K[127:96]
CRYPT_AESKEY4 = K[159:128]. Used only in case of Key Length 256.
CRYPT_AESKEY5 = K[191:160]. Used only in case of Key Length 256.
CRYPT_AESKEY6 = K[223:192]. Used only in case of Key Length 256.
CRYPT_AESKEY7 = K[255:224]. Used only in case of Key Length 256.
NOTE: Partial writes to the key registers are not allowed. To use a new key (same or different lengths), all the key
registers must be updated, even if the previous or new values for a given AESKEY register is same.
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Crypto Keys
Key Wrap-Unwrap Register
The CRYPT_KUW0 - CRYPT_KUW15 register set stores the wrapped/unwrapped key that is to be unwrapped/
wrapped, respectively.
The result of the wrap/unwrap operation is stored in the same register set. Additionally, CRYPT_KUWVALSTR1
and CRYPT_KUWVALSTR2 registers store the additional content that is generated by the virtue of the validation
string used to wrap the key. While wrapping a key, the validation string needed for the wrap operation is stored in
these registers.
The validation strings registers are readable only post an unwrap operation. A secure software may use this validation
string to implement a software based key validation.
Key Register Attributes
This field indicates that an overflow event has occurred on the input buffer. The status bit is sticky and can be
cleared by writing 1 into the bit field.
Key registers refer to the CRYPT_AESKEY0 - CRYPT_AESKEY7 register set, CRYPT_KUW0- CRYPT_KUW15
register set, CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers.
The following features are implemented to ensure secure usage of cryptographic key:
• The key registers are not readable by software.
• The validation string register used in a wrap-unwrap operation are only readable in a specific read window
which extends post an unwrap command to the issue of next PrKStor command or block disable, whichever is
earlier. The read value can be used to associate key-usage validation metadata with a given key.
• The key registers except validation string registers are reset on partial writes. The software must program full
key when a new key is to be used with the hardware accelerator.
• Any changes in the key length, resets the key registers and key validation registers to default values.
Crypto Power Saver Mode
Enabling the power saver mode in the CRYPT_CFG.BLKEN register enables an automatic clock gating function.
This reduces the clocking activity in the block to the barest minimum possible. It is recommended to keep this on as
there is not performance hit by having this enabled.
Registers with Mode Specific Roles
DATALEN
The CRYPT_DATALEN register is used to specify the length of the payload data. This information is used in CCM
and MAC modes of operation.
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Registers with Mode Specific Roles
• CCM Mode: Program the number of 128-bit data blocks in the resulting aligned payload. CRYPT_DATALEN
[15:0] is provided for this purpose. CCM supports data lengths which are not a multiples of 16 bytes. The
number of blocks must be rounded off to the next integer. For example, if the number of blocks in data is 4.5,
the data length must be programmed to 5.
• CMAC Mode: Pad the payload data to ensure that the total number of bits is an integral multiple of 128. Program the number of 128-bit blocks in the aligned payload data. CRYPT_DATALEN [19:0] is provided for
this purpose. For example, if the data length is 56 bytes, the data length must be programmed to 4.
PREFIXLEN
The CRYPT_PREFIXLEN register is used to specify the length of the associated data that is only authenticated.
This information is used in CCM mode of operation.
CCM Mode: Pad the associated data enough zeroes with to ensure that the total number of bits is an integral multiple of 128. Then, program the number of 128-bit blocks in the resulting aligned payload data.
CRYPT_PREFIXLEN.VALUE bits are provided for this purpose.
NONCEx
The CRYPT_NONCE0 to CRYPT_NONCE3 registers are used to program the nonce for CTR, CBC, and CCM
Modes of operation.
The Nonce is constructed in the following way:
Nonce[127:0] = {CRYPT_NONCE3[31:0], CRYPT_NONCE2[31:0], CRYPT_NONCE1[31:0],
CRYPT_NONCE0[31 :0]}
Different lengths of Nonce are used in different block modes of operation:
• CTR Mode: This mode uses a 108-bit long Nonce. In this mode, the encryption operation is performed in the
following format:
Ciphertext_Block = Ciph ({Nonce[107:0], CRYPT_CNTRINIT[19:0] ) xor Payload_Block
• CBC Mode: In this mode, 128 bits of the Nonce are used. The nonce is used as the initialization vector.
Initialization_Vector = Nonce[127:0]
• CCM Mode: In this mode, 112 bits are used. The nonce is used in the Counter mode computation. The data
is constructed in the following format:
Ciphertext_Block = Ciph ({Nonce[111:0], Counter[15:0]} ) xor Payload_Block
SHARESx
The results from the SHA hash operations are to be read out of the SHARES register set in the following format:
HASH[255:0] = {SHARES7[31:0], SHARES6[31:0], SHARES5[31:0], SHARES4[31:0],
SHARES3[31:0], SHARES2[31:0], SHARES1[31:0], SHARES0[31:0]}
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Protected Key Storage (PrKStor)
CNTRINIT
This value initializes the counter generating function. The counter generating function implemented in this block is
an incrementing function, i.e. this function counts up by 1 for every new data block. The initialization value for the
counters can be programmed in the CRYPT_CNTRINIT register.
Counter widths for CTR mode and CCM modes are:
• CTR Mode: 20-bit counter. If counter starts from zero, then 16 GB of data will be processed before the counter overflows. A 20-bit register for initializing the counter is provided.
• CCM Mode: 16-bit counter. If counter starts from zero, then 1 GB of data will be processed before the counter
overflows. A 16-bit counter initialization register is provided.
The fixed bit width of the counter implies that there is a limit to the maximum length of data that can be
encrypted without repeating the same counter values. This is 16 MB of Payload data in CTR Mode and 1 MB
of confidentiality data in CCM mode.
NOTE: When the counters reach the maximum value, the next data input causes them to rollover back to zero.
SHAINIT
This is an auto-clear register field. The control signal is to be used to initialize the SHA computation registers to
reset value when a new computation is initiated
SHA_LAST_WORD
SHA-256 module is updated to include a length counter and padding mask. Software does not need to append the
padding and bit length at the end of a message.
SHA control register has the following fields:
• last_word
• bits_valid [4:0]
Software loads the input data as a word (32 bits) to the crypto accelerator input buffer. The input data may or may
not be a multiple of 32 bits. User must set the last_word bit, bits_valid bit to number of bits valid in the last word
(0-31), and write the last word to the crypto accelerator. The LSBs of this word are ignored (replaced with padding)
according to the SHA standard. If data length is a multiple of 32 bits, user must write a dummy word to complete
the final operation (all bits are replaced with padding).
NOTE: For the last word in the message, last_word must be asserted and bits_valid must reflect the number of valid
bits in last_word. If all the bits are valid, the word must be written first, and a dummy word (which is the last word)
is written with no bits valid. Invalid bits are ignored.
Protected Key Storage (PrKStor)
This platform provides a secure nonvolatile location for the storage of cryptographic keys in the form of a Protected
Key Storage (PrKStor) region of flash memory. PrKStor consists of two 2 KB pages and provides protected storage
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Protected Key Storage (PrKStor)
for up to 51 keys per page (102 keys in total). Each key record supports keys of size 320 bits and is identified by a
Page and Index value. Software can store a 128-bit or 256-bit wrapped and unwrapped key into this 320-bit space.
All metadata for key usage policy has to be maintained by software. The module provides a command interface for
various key related operations and a secure key-update policy can be designed using this module in conjunction with
the Key wrap-unwrap module.
The PrKStor module is implemented as a slave to the Crypto module. All interactions with the PrKStor are performed through register access within the register address space of the Crypto module. Flash memory reserved for
use by the PrKStor is not user configurable and cannot be accessed through the flash controller.
Key Wrap-Unwrap
This functionality is added to the PrKStor to support encryption/decryption of keys. This wrapped key along with
the validation prefix is stored in the KUW register set. CRYPT_KUW0 - CRYPT_KUW15 register set and
CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers. These registers are selectively readable via the software. This read window opens post unwrap operation and before the next PrKStor command is issued.
Key Validation
Given that a secure bootloader is inbuilt to prevent any unwarranted change in the software, a secure key validation
policy can be implemented in software. To enable this secure validation, the CRYPT_KUWVALSTR1 and
CRYPT_KUWVALSTR2 registers are readable in a read window post the unwrap command and before any other
PrKStor command is issued or the block/mode is disabled. Software may read this register and store any metadata
related to key validation policy along with other metadata related to the key. The software may wipe the AESKEY
and KUW register sets if the validation key does not meet the current crypto operation requirement.
Protection and Integrity
• Key Wrap: The keys stored in flash can be encrypted with any random key that should be programmed in the
AESKEY register set before any wrap or unwrap operation.
• Read protection: When targeting the PrKStor flash memory only the Crypto data path is enabled (flash controller data paths are pulled to FFs).
• Write/Erase protection: When targeting PrKStor flash memory only commands from the Crypto command interface are allowed (all other flash operations are stalled). Avoid mass erase operations (by write protecting any
set of pages in user space).
• Data integrity using ECC: 1-bit error corrections and multi-bit error detections are provided by the underlying
flash controller.
Operation
PrKStor physically resides in the two most significant pages of the user space in the flash memory. These two pages
are inaccessible via normal flash memory access methods and instead made accessed using a dedicated bus/protocol
to the Cryptographic module.
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Protected Key Storage (PrKStor)
Figure 12-2: PrKStor Organization
Each of the two pages of PrKStor provides a storage up to 51 cryptographic keys. A single DWORD of slack space
exists in each PrKStor page and reserved. The Crypto module may index into any arbitrary dword of either PrKStor
page. For safety, the Crypto module provides a more abstract interface to the user. User code may atomically reference individual keys by page number and index (for example, [0.0] for the least significant key of page zero; [1.50]
for the most significant key of page one).
Metadata is not stored within the PrKStor region. User must maintain own metadata to track the location of the
keys stored and validity of the keys for a particular use.
Protected Key Storage Configuration
Configuration Bits
The configuration bit fields are available in the CRYPT_PRKSTORCFG and CRYPT_CFG registers.
• Device Key: The device key is a 256-bit fixed key in RTL. This key is provided to wrap/unwrap keys locally
before storing it to the PrKStor flash storage. The device key is not known to software but can be loaded to
AESKEY register set using a PrKStor command LD_DEVICE_KEY. The software may use any other for wrap
or unwrap operation by loading the same to the AESKEY register set.
• PRKSTOREN: This bit must be set before issuing any PrKStor command.
• KEY_INDEX [6:0]: Indicates the index of the key on which the operation suggested by the PrKStor command.
The MSB suggests the page id and the remaining bits suggest the key location in the corresponding page.
• CMD [3:0]: Indicates the command to be executed in the PrKStor. These bits are auto cleared once the command is executed. The last command issued can be viewed by reading the CRYPT_STAT.CMD_ISSUED
bits.
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Protected Key Storage (PrKStor)
• KUW0 to KUW7, KUWValStr1 and KUWValStr2 registers: Write-only registers. They hold the key from user
on which wrap or unwrap operation needs to be performed. For example, if a 256 + 64 bit key needs to be
unwrapped, it must be loaded to the KUW0 to KUW7 register set and KUWValStr1 and KUWValStr2 registers.
• KUWKEYLEN [2:0]: Indicate the length of the wrapped key in terms of 64-bit blocks.
If KUWKEYLEN = 0x3, the key length is 512 bits. 512-bit key is only supported for HMAC calculation and
cannot be stored in the PrKStor flash storage.
For a key length of 256 bits, KUWKEYLEN must be programmed to 0x2.
For a 128-bit key, KUWKEYLEN must be programmed to 0x1.
Status Bits
The status bits are available in the CRYPT_STAT register.
• PRKSTOR_BUSY: This bit when set indicates that the PrKStor is busy in executing a command and cannot
receive a new command.
• PRKSTOR_CMD_DONE: This bit when set indicates the PrKStor has finished executing the last issued command.
• PRKSTOR_CMD_FAIL: This bit when set indicates that the last issued command has failed. Some of these
commands depend on flash operations. If they repeatedly fail, attempt a normal flash operation and debug the
issues (if any) within the flash controller.
• PRKSTOR_RET_STATUS [1:0]: If the status is 0x2, it indicates that at least one 1-bit ECC error is observed
for a RETRIVE_KEY operation but corrected. If the status is 0x1, it indicates that at least one multi-bit ECC
error during read back in a RETRIEVE_KEY operation. The resultant key may be invalid.
• CMD_ISSUED [3:0]: This field records the last command issued to the PrKStor. As the CMD field is auto
cleared after the command completes, this is provided as an option to the software to read the last command
issued.
Interrupt Enable
PRKSTRCMDONEEN: This bit when set interrupts the core on completion of any PRKSTOR command.
Protected Key Storage Commands
The following commands are supported by the PrKStor module:
• WRAP: CMD = 0x1. This command indicates that a wrap operation has to be performed for the key stored in
the CRYPT_KUW0 - CRYPT_KUW7 register set.
• UNWRAP: CMD = 0x2. This command indicates that an unwrap operation is required to be performed for
the wrapped key stored in the CRYPT_KUW0 - CRYPT_KUW15 register set and CRYPT_KUWVALSTR1 and
CRYPT_KUWVALSTR2 registers. Post unwrap, the validation string is readable to software before any other
PrKStor command is issued or the mode/block is disabled.
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Protected Key Storage (PrKStor)
The default value of the validation string is the NIST Standard validation string: 0xA6A6A6A6A6A6A6A6
• RST_DECRYPTED_KEY: CMD = 0x3. The contents of the CRYPT_KUW0 - CRYPT_KUW15 register set
can be cleared by issuing this command. Once the usage of the decrypted/unwrapped key is complete. It is
recommended that this bit is set.
• USE_DECRYPTED_KEY: CMD = 0x4. The decrypted/unwrapped key can be used for further crypto operations by issuing this command. This command loads the content of the KUW registers to the AESKEY registers. The CRYPT_CFG.AESKEYLEN is updated with the value stored in CRYPT_CFG.KUWKEYLEN once
this command is executed. No partial modification to this key is allowed by the design. Software must not program a 512-bit key in the KUW before executing this command, as AES supports only 128-bit and 256-bit key
lengths.
• LD_DEV_KEY: CMD = 0x5. This command loads the device key to the CRYPT_AESKEY0 CRYPT_AESKEY7 register set. The CRYPT_CFG.AESKEYLEN bits must be set to a 256-bit option, as Device Key is a 256-bit key. This device key can be used to wrap-unwrap any key in the CRYPT_KUW0 CRYPT_KUW15 register set.
• RETRIEVE_KEY: CMD = 0x8. The location specified by the CRYPT_PRKSTORCFG.KEY_INDEX bits is
read from flash and is loaded into the CRYPT_KUW0 - CRYPT_KUW15 register set and
CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers.
• STOR_KEY: CMD = 0x9. This command when issued stores the content of the CRYPT_KUW0 CRYPT_KUW15 register set and CRYPT_KUWVALSTR1 and CRYPT_KUWVALSTR2 registers at a location
specified by the CRYPT_PRKSTORCFG.KEY_INDEX bits in flash.
• DESTROY_KEY: CMD = 0xA. This command when issued, overwrites the key with zeroes at the index specified by the CRYPT_PRKSTORCFG.KEY_INDEX field.
• ERASE_PAGE: CMD = 0xB. This command when issued, does a page erase for the page specified by the
CRYPT_PRKSTORCFG.KEY_INDEX [6] field.
Programming Flow
PrKStor is recommended to be used in core mode.
• Programming a valid KUW key: For KUW key only complete key writes are allowed. Partially modifying the
KUW key is not possible, as all the KUW key registers are reset to zero when any KUW key register is overwritten. Before programming the KUW key, theCRYPT_CFG.KUWKEYLEN field must be set to the appropriate value and all the relevant key registers must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b001: KUW key length is 512 and all the registers from CRYPT_KUW0 CRYPT_KUW15 must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b010: KUW key length is 256 and all the registers from CRYPT_KUW0 CRYPT_KUW7 must be progammed.
CRYPT_CFG.KUWKEYLEN = 3'b100: KUW key length is 128 and all the registers from CRYPT_KUW0 CRYPT_KUW3 must be progammed
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Protected Key Storage (PrKStor)
To implement wrap or unwrap command on a KUW key programmed via MMR the KUW validation strings
must be programmed. No partial changes to the validation string are supported and the complete 64-bit must
be programmed at once.
When executing the USE_DECRYPTED_KEY command, the CRYPT_CFG.KUWKEYLEN must be programmed correctly. Once the command is executed the CRYPT_CFG.AESKEYLEN bit field is updated with
the value stored in CRYPT_CFG.KUWKEYLEN.
• For executing any PrKStor command, the CRYPT_CFG.PRKSTOREN and CRYPT_CFG.BLKEN bits must
be set. The configuration register is programmed first and then the block is enabled before issuing any command to PrKStor.
• Once the PrKStor is enabled it can execute a series of commands.
• When using the USE_DECRYPTED_KEY and LD_DEV_KEY commands, the CRYPT_CFG.AESKEYLEN
bit field is internally modified by the design. The decrypted key can be of length 128-bit or 256-bit only for
the USE_DECRYPTED_KEY command. The Device Key is a fixed 256-bit key. When LD_DEV_KEY is executed, the CRYPT_CFG.AESKEYLEN field is modified to a 256-bit value.
• Before going to hibernate, all PrKStor commands must be allowed to complete. The integrity of PrKStor storage cannot be guranteed if a command is stopped midway. The CRYPT_STAT.PRKSTOR_BUSY bit when
set, indicates that a command is being executed.
• The status of a command can be retrieved using the CRYPT_STAT.PRKSTOR_CMD_DONE bit. The software must also verify the pass/fail status of a command using the CRYPT_STAT.PRKSTOR_CMD_FAIL bit.
If this bit is set along with CRYPT_STAT.PRKSTOR_CMD_DONE bit, it indicates that the PrKStor command has failed.
• For a RETRIEVE_KEY operation, if there is an ECC error (correctable or not) and the KEY_CORRUPT_INT_EN bit is set, interrupts the core. It is recommended that the key location be re-written with the
correct key and reverified.
• If the commands continue to fail after multiple retries, flash debug must be initiated.
Command Fail Status
The CRYPT_STAT.PRKSTOR_CMD_FAIL bit when set along with the
CRYPT_STAT.PRKSTOR_CMD_DONE bit, it indicates that the last issued command has failed.
PrKStor Disabled
If PrKStor is disabled due to tampering with the PrKStor pages, the following commands fail:
RETRIEVE_KEY, STOR_KEY, DESTROY_KEY, and ERASE_PAGE
Non Zero ECC Status
If any of the data retrieved from flash when a RETRIEVE_KEY command is issued has a non-zero ECC status the
RETRIEVE command fails.
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HMAC
Flash Write Corrupted
When flash is not able to execute the write command properly, the STOR_KEY command fails.
Metadata Maintenance
Software must track which keys are stored at what indices and what they should be used for. This metadata must be
updated on Destory Key commands and Bad Key status (incorrectable ECC error). It is recommended that all commands should have their start and end reflected in the metadata. If some command cannot exit cleanly, this is reflected in the metadata indicating that the corresponding PrKStor index may not behave as expected, if reused.
Key Verification
Post any PrKStor operation, the key can be verified by encrypting/decrypting a known plain text-cipher text pair
with the key.
HMAC
HMAC generation mode is added as a more secure data authentication method. For additional security, a 512-bit
key/wrap unwrap mode is also added. This facilitates the encryption/decryption of HMAC secret key K using a key
encryption key.
This module supports any length of user key K. When using a wrapped HMAC key K, the key K0 must be processed and provided by software as the maximum key wrap length supported is 512.
K: Secret key shared between the originator and intended receiver.
K0: The key K after any necessary pre-processing to form a B byte key.
HMAC Algorithm
Input Specifications
• HMAC key: 512-bit preprocessed key.
If key_len < 512, HMAC key = [Key, {512 - key_len}'b0]
If key_len > 512, HMAC key = [SHA256(KEY), {512 – 256}'b0}]
• Message as plain text.
Output Specifications
HMAC authentication string. Same as SHA256 result.
o_key_pad = [0x5c * blocksize] ⊕ key // Blocksize = 256
i_key_pad = [0x36 * blocksize] ⊕ key // ⊕ represents XOR operation
HMAC_Output = SHA256(o_key_pad ∥SHA256 (i_key_pad ∥ message))// ∥ represents concatenation
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HMAC
Programming Model
Configuration Bits
• HMACEN: Enables HMAC mode in Crypto accelerator.
• KEY_BYTESWAP: Enables byte swapping the data that is being loaded in the key registers.
The HMAC key is assumed to be 512 bits long. This must be preprocessed as per NIST specification document. Padding of zeros is done by hardware automatically.
• SHA_BYTESWAP: If the message input needs to be byteswapped before feeding it to the HMAC accelerator.
SHA_BYTESWAP can be reused for the same.
Status Bits
• HMACMSGRDY: Indicates that Crypto is ready to take in the text that needs to be hashed.
• HMACDONE: Indicates that the current HMAC operation is done.
• HMACBUSY: Indicates that HMAC operation is in progress.
Operation
HMAC must be enabled in the configuration register by setting the CRYPT_CFG.HMACEN bit. As the design supports preprocessed HMAC key, if the length of HMAC key is greater than 512 bits, software must perform a hashing of the key to produce an output of 256 bits, which is appended with 256 zeroes to create the HMAC key K0.
Core Mode
1. Load a valid key Ko in the KUW registers.
2. Enable HMAC.
3. Software must wait for the CRYPT_STAT.HMACMSGRDY bit or CRYPT_INTEN.HMACMSGRDYEN (interrupt mode) before the message text is input to design.
4. Software must clear the CRYPT_STAT.HMACMSGRDY bit and input one block of data (512 bits to the
HMAC accelerator).
5. After providing a full block of message to the HMAC accelerator, the software has to wait for the next
CRYPT_INTEN.HMACMSGRDYEN to feed the next block of data to the HMAC accelerator.
6. For the last block of data, similar procedure as is done for SHA needs to be done. Once all data but last word is
provided to design, CRYPT_SHA_LAST_WORD must be set and
CRYPT_SHA_LAST_WORD.O_BITS_VALID must provide the information about number of valid bits in
the last word.
7. After data is fed to HMAC accelerator, software must wait for the HMACDONE interrupt, which indicates that
the HMAC operation is complete.
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CCM/CCM* Mode
DMA Mode
1. Load key K0 in the KUW registers.
2. Configure DMA for the required data transfer (except last word).
3. Enable HMAC and DMA.
4. Enable Crypto.
5. Disable the CRYPT_INTEN.HMACMSGRDYEN. DMA transfers all requisite data without any interruption
from core.
6. For last word input to SHA, same procedure as described for core mode of operation has to be followed.
7. Software must wait for CRYPT_STAT.HMACDONE bit either through polling or interrtupt.
NOTE: Text data can be input in the same way as a normal SHA operation. Once the text data is input, software
must check for the CRYPT_STAT.HMACDONE bit, which indicates that the hash operation is done and the final
result can be read from the SHARES register set. For message lengths that are not a multiple of 512 bits, similar
operation with CRYPT_SHA_LAST_WORD and CRYPT_SHA_LAST_WORD.O_BITS_VALID is required as
done in SHA calculations, to enable the hardware to start processing the message input for the last block of data.
CCM/CCM* Mode
The diagrams use the following color code.
Output
Input
Software
Operation
Figure 12-3: Color Codes
The NIST Standard for CCM mode has the following description of the CCM operation.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–21
CCM/CCM* Mode
CCM Mode Standard (NIST SP800 - 38c) Description
Encrypt - Generate
Formatted
Plaintext
Cipher text
CCM
Enc(MAC)
Decrypt - Validate
Formatted
Cipher text
CCM
Plaintext
MAC
Enc(MAC)
Decryption
==
MAC
VALID/INVALID
Figure 12-4: CCM Mode Standard Description
The hardware implementation for the CCM mode is shown in the figure:
CCM Mode Hardware Implementation
Encrypt - Generate
Formatted
Plaintext
CCM
Cipher text
Enc(MAC)
Decrypt - Validate
Formatted
Cipher text
Enc(MAC)
CCM
Plaintext
Enc(MAC)
==
VALID/INVALID
Figure 12-5: CCM Mode Hardware Implementation
12–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Programming Flow for Block Modes of operation
Hardware to Standard Equivalence
During Encrypt-Generate
Enc(MAC) = MAC xor AES (Counter 0)
During Decrypt-Validate
Enc(MAC’) = MAC ’ xor AES (Counter 0)
Validation of authenticity is specified in the standard to be the
following check:
VALID = (MAC = = MAC’)
The hardware implementaion flow generatesVALID by the
comparison:
VALID = (Enc(MAC) = = Enc(MAC’))
Clearly, both the comparisons are mathematically equivalent.
Figure 12-6: Hardware to Standard Equivalence
The following are the reasons for the difference in the implementation flow adopted for generation of VALID signal
in Decrypt-Validate phase:
• CMAC mode provides the MAC results and does not check the result against the received reasonable to do the
same in CCM mode.
• This approach is faster. When the system receives data that needs decryption, it receives an encrypted MAC. In
out implementation it is not necessary to decrypt the received MAC.
• The length of the MAC is selectable. If the hardware has to compare internally, information regarding the
length of the MAC output has to be programmed. This adds an additional control parameter and also increases
the hardware complexity by having a variable length comparator.
• The comparison operation is simple and involves very few operations. It does not require a hardware accelerator.
• MAC is not expected as an output from CCM operation. Only a VALID or INVALID signal is necessary.
Programming Flow for Block Modes of operation
Block modes of operation require the software to perform the following operations:
• Crypto Block Configuration
• Input Data Preparation
• Data Retrieval
Configuring the Crypto block
Crypto key configuration: The complete key must be programmed in the key registers before every operation. Partial key configuration is not allowed.
Crypto must be configured in following order:
1. Configure the parameters such as key length, encrypt/decrypt, mode and so on. Do not enable the block.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–23
Programming Flow for Block Modes of operation
2. Program the key into key registers. Ensure that only relevant key registers for a given key length are programmed.
3. Enable the block by doing a read-modfiy-write to the configuration register.
Encrypt or Decrypt
CRYPT_CFG.ENCR field
Data Transfer
1. Endianness in CRYPT_CFG.ENDIAN
2. CRYPT_CFG.INDMAEN/CRYPT_CFG.OUTDMAEN field
Block Mode of Operation
The Crypto block supports the following block modes of operation:
• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher CMAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
NOTE: Only one mode must be enabled at a time.
Mode Specific Parameters
CTR Mode
• CRYPT_CNTRINIT
• CRYPT_NONCE0 to CRYPT_NONCE3
CCM/CCM* Mode
• CRYPT_DATALEN
• CRYPT_PREFIXLEN
• CRYPT_CNTRINIT
• CRYPT_NONCE0 to CRYPT_NONCE3
CBC Mode
12–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Programming Flow for Block Modes of operation
Initialization Vector in the CRYPT_NONCE0 to CRYPT_NONCE3 registers.
CMAC Mode
CRYPT_DATALEN: This information is used by the block to determine when the CMAC results must be provided
on the output buffer.
Enabling Crypto
CRYPT_CFG.BLKEN field.
Ensure that this bit is enabled only when the block is completely configured.
Payload and Authenticated Data Formatting
In every mode of operation (other than CMAC) it is necessary to pad the payload and/or authenticated data with
sufficient number of zeros so as to make the length a multiple of 128 bits. In the case of CMAC mode, user needs to
pad and XOR the last message block differently.
Mode Specific Data Format
• CBC Mode: Initialize the CRYPT_NONCE0 to CRYPT_NONCE3 registers with the Initialization Vector.
• CMAC Mode: The block always gives out a 128-bit MAC result on the output buffer in the selected data format (Big_Endian or Little_Endian). The software needs to ensure that the desired number of bits is used.
Subkey Generation: The values of K1 and K2 are used to generate the final message DataBlock. Software handles the generation of K1 and K2, padding higher bits with 'b10....j (j = number of zeroes that on padding
make the final message data block 128-bit long), and XOR operation to generate last message data block.
• CCM/CCM* Mode: Refer to the CCM/CCM* Mode section.
Programming Flow for SHA-Only Operation
Core Mode
Configuration
1. Configure SHA.
2. Enable the CRYPT_CFG.SHA256EN bit.
3. Program the first block of data.
4. Wait for the CRYPT_STAT.SHADONE interrupt bit to be set.
5. Program any consecutive 512-bit data block to the input buffer.
6. For the last word in the data block, set the CRYPT_SHA_LAST_WORD.O_LAST_WORD bit and program
the number of valid bits in that word. For example, if 12 bits are valid, the
CRYPT_SHA_LAST_WORD.O_BITS_VALID bit must be loaded with 12.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–25
Retention in Hibernate Mode
If all the bits are valid, the last write must be a dummy write.
7. For a fresh SHA calculation, initialize SHA using the CRYPT_CFG.SHAINIT bit.
Complete the ongoing SHA operation before starting another SHA operation.
DMA Mode
Configuration
The following parameters must be programmed:
1. DMA for input buffer (CRYPT_CFG.INDMAEN field).
2. Enable desired SHA mode (CRYPT_CFG.SHA256EN field).
3. Enable the Crypto block (CRYPT_CFG.BLKEN field).
4. Initialize SHA operation (CRYPT_CFG.SHAINIT field).
When a new data block is to be computed and a fresh start is needed, the data block needs to be initialized
using this auto-clear bit provided in the CRYPT_CFG register.
Data Preparation
SHA accelerator does not require any software padding of data to make it a multiple of block size.
Data Retrieval
When the data operation is complete, the message digest can be read out of the SHAH register set.
After the message digest for a particular block is complete, re-initialize the internal SHAH registers by writing 1 to
the CRYPT_CFG.SHAINIT bit.
Retention in Hibernate Mode
The CRYPT_CFG register except CRYPT_CFG.BLKEN are retained in hibernate mode. The AESKEY register set
are also retained. All other register fields including the KUW register set are reset.
If the part goes into hibernate mode in the middle of a transaction, it cannot be retrieved. All the internal registers
except CRYPT_CFG and AESKEY register set are reset.
If the PrKStor is busy, part must not be allowed to hibernate. The PrKStor command needs to be completed before
allowing the part to hibernate.
ADuCM4050 CRYPT Register Descriptions
Register Map for the Crypto Block (CRYPT) contains the following registers.
12–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Table 12-2: ADuCM4050 CRYPT Register List
Name
Description
CRYPT_AESKEY0
AES Key Bits [31:0]
CRYPT_AESKEY1
AES Key Bits [63:32]
CRYPT_AESKEY2
AES Key Bits [95:64]
CRYPT_AESKEY3
AES Key Bits [127:96]
CRYPT_AESKEY4
AES Key Bits [159:128]
CRYPT_AESKEY5
AES Key Bits [191:160]
CRYPT_AESKEY6
AES Key Bits [223:192]
CRYPT_AESKEY7
AES Key Bits [255:224]
CRYPT_CCM_NUM_VALID_BYTES
NUM_VALID_BYTES
CRYPT_CFG
Configuration Register
CRYPT_CNTRINIT
Counter Initialization Vector
CRYPT_DATALEN
Payload Data Length
CRYPT_INBUF
Input Buffer
CRYPT_INTEN
Interrupt Enable Register
CRYPT_KUW0
Key Wrap Unwrap Register 0
CRYPT_KUW1
Key Wrap Unwrap Register 1
CRYPT_KUW10
Key Wrap Unwrap Register 10
CRYPT_KUW11
Key Wrap Unwrap Register 11
CRYPT_KUW12
Key Wrap Unwrap Register 12
CRYPT_KUW13
Key Wrap Unwrap Register 13
CRYPT_KUW14
Key Wrap Unwrap Register 14
CRYPT_KUW15
Key Wrap Unwrap Register 15
CRYPT_KUW2
Key Wrap Unwrap Register 2
CRYPT_KUW3
Key Wrap Unwrap Register 3
CRYPT_KUW4
Key Wrap Unwrap Register 4
CRYPT_KUW5
Key Wrap Unwrap Register 5
CRYPT_KUW6
Key Wrap Unwrap Register 6
CRYPT_KUW7
Key Wrap Unwrap Register 7
CRYPT_KUW8
Key Wrap Unwrap Register 8
CRYPT_KUW9
Key Wrap Unwrap Register 9
CRYPT_KUWVALSTR1
Key Wrap Unwrap Validation String [63:32]
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–27
ADuCM4050 CRYPT Register Descriptions
Table 12-2: ADuCM4050 CRYPT Register List (Continued)
Name
Description
CRYPT_KUWVALSTR2
Key Wrap Unwrap Validation String [31:0]
CRYPT_NONCE0
Nonce Bits [31:0]
CRYPT_NONCE1
Nonce Bits [63:32]
CRYPT_NONCE2
Nonce Bits [95:64]
CRYPT_NONCE3
Nonce Bits [127:96]
CRYPT_OUTBUF
Output Buffer
CRYPT_PREFIXLEN
Authentication Data Length
CRYPT_PRKSTORCFG
PRKSTOR Configuration
CRYPT_SHAH0
SHA Bits [31:0]
CRYPT_SHAH1
SHA Bits [63:32]
CRYPT_SHAH2
SHA Bits [95:64]
CRYPT_SHAH3
SHA Bits [127:96]
CRYPT_SHAH4
SHA Bits [159:128]
CRYPT_SHAH5
SHA Bits [191:160]
CRYPT_SHAH6
SHA Bits [223:192]
CRYPT_SHAH7
SHA Bits [255:224]
CRYPT_SHA_LAST_WORD
SHA Last Word and Valid Bits Information
CRYPT_STAT
Status Register
12–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [31:0]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [3:0]
Figure 12-7: CRYPT_AESKEY0 Register Diagram
Table 12-3: CRYPT_AESKEY0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [3:0].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–29
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [63:32]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [7:4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [7:4]
Figure 12-8: CRYPT_AESKEY1 Register Diagram
Table 12-4: CRYPT_AESKEY1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [7:4].
(RX/W)
12–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [95:64]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [11:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [11:8]
Figure 12-9: CRYPT_AESKEY2 Register Diagram
Table 12-5: CRYPT_AESKEY2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [11:8].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–31
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [127:96]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [15:12]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [15:12]
Figure 12-10: CRYPT_AESKEY3 Register Diagram
Table 12-6: CRYPT_AESKEY3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [15:12].
(RX/W)
12–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [159:128]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [19:16]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [19:16]
Figure 12-11: CRYPT_AESKEY4 Register Diagram
Table 12-7: CRYPT_AESKEY4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [19:16].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–33
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [191:160]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [23:20]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [23:20]
Figure 12-12: CRYPT_AESKEY5 Register Diagram
Table 12-8: CRYPT_AESKEY5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [23:20].
(RX/W)
12–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [223:192]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [27:24]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [27:24]
Figure 12-13: CRYPT_AESKEY6 Register Diagram
Table 12-9: CRYPT_AESKEY6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [27:24].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–35
ADuCM4050 CRYPT Register Descriptions
AES Key Bits [255:224]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [31:28]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [31:28]
Figure 12-14: CRYPT_AESKEY7 Register Diagram
Table 12-10: CRYPT_AESKEY7 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [31:28].
(RX/W)
12–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
NUM_VALID_BYTES
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
NUM_VALID_BYTES (R/W)
Number of Valid Bytes in CCM Last
Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-15: CRYPT_CCM_NUM_VALID_BYTES Register Diagram
Table 12-11: CRYPT_CCM_NUM_VALID_BYTES Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 NUM_VALID_BYTES
Number of Valid Bytes in CCM Last Data.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–37
ADuCM4050 CRYPT Register Descriptions
Configuration Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PRKSTOREN (R/W)
Enable PRKSTOR Commands
BLKEN (R/W)
Enable Bit for Crypto Block
KEY_BYTESWAP (R/W)
Use Key Unwrap Before HMAC
ENCR (R/W)
Encrypt or Decrypt
SHA_BYTESWAP (R/W)
Enable Key Wrap
INDMAEN (R/W)
Enable DMA Channel Request for Input
Buffer
AES_BYTESWAP (R/W)
Byteswap for AES Input
OUTDMAEN (R/W)
Enable DMA Channel Request for Output
Buffer
KUWKeyLen (R/W)
Key Length Key Wrap Unwrap
INFLUSH (W)
Input Buffer Flush
AESKEYLEN (R/W)
Select Key Length for AES Cipher
OUTFLUSH (W)
Output Buffer Flush
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
RevID (R)
Rev ID for Crypto
ECBEN (R/W)
Enable ECB Mode Operation
SHAINIT (R0/W)
Restarts SHA Computation
CTREN (R/W)
Enable CTR Mode Operation
SHA256EN (R/W)
Enable SHA-256 Operation
CBCEN (R/W)
Enable CBC Mode Operation
HMACEN (R/W)
HMAC Enable
CCMEN (R/W)
Enable CCM/CCM* Mode Operation
CMACEN (R/W)
Enable CMAC Mode Operation
Figure 12-16: CRYPT_CFG Register Diagram
Table 12-12: CRYPT_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 REVID
(R/NW)
26 SHAINIT
(R0/W)
12–38
Rev ID for Crypto.
The revision id is set to 0x2 for this version.
Restarts SHA Computation.
Initialize SHA module for fresh SHA calculation on a new data block. This bit resets
the SHA result registers to their default state. This auto-clears after reseting the SHA
result registers.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Table 12-12: CRYPT_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
25 SHA256EN
Enable SHA-256 Operation.
(R/W)
21 HMACEN
(R/W)
20 CMACEN
HMAC Enable.
Enable HMAC mode. At the end of HMAC calculation, this bit is auto-reset. To restart a fresh HMAC calculation this bit should be set again by software
Enable CMAC Mode Operation.
(R/W)
19 CCMEN
Enable CCM/CCM* Mode Operation.
(R/W)
18 CBCEN
Enable CBC Mode Operation.
(R/W)
17 CTREN
Enable CTR Mode Operation.
(R/W)
16 ECBEN
Enable ECB Mode Operation.
(R/W)
15 PRKSTOREN
(R/W)
14 KEY_BYTESWAP
(R/W)
13 SHA_BYTESWAP
(R/W)
12 AES_BYTESWAP
(R/W)
11:10 KUWKEYLEN
(R/W)
Enable PRKSTOR Commands.
This bit should be enabled to execute any command in the Protected Key Storage.
Use Key Unwrap Before HMAC.
The input word to the AES Key, KUW Key, and KUW validating strings register is
byte-swapped once this bit is set.
Enable Key Wrap.
Enable byte-swap for each word input to the SHA module. Data that is input as {B3,
B2, B1, B0} will be recorded as {B1, B2, B3, B4}.
Byteswap for AES Input.
Enable byte-swap for each word input to the Input Buffer. Data that is input as {B3,
B2, B1, B0} will be recorded as {B1, B2, B3, B4}.
Key Length Key Wrap Unwrap.
Specify the length of the key in KUW registers in terms of 64 bit blocks. These are the
registers that hold the wrapped or unwrapped key in respective modes. They support a
maximum key length of 512 bits. Any change in the key length will reset the KUW
registers.
1 The key size of KUW key is 128 bits
2 The key size of KUW key is 256 bits
3 The key size of KUW key is 512 bits
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–39
ADuCM4050 CRYPT Register Descriptions
Table 12-12: CRYPT_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 AESKEYLEN
(R/W)
Select Key Length for AES Cipher.
Specify the length of AES key. Supported key lengths are 128 and 256 bits. Any
change in the key length will reset the AES key.
0 Uses 128-bit long key
2 Uses 256-bit long key
5 OUTFLUSH
Output Buffer Flush.
(RX/W)
4 INFLUSH
Input Buffer Flush.
(RX/W)
3 OUTDMAEN
Enable DMA Channel Request for Output Buffer.
(R/W)
0 Disable DMA Requesting for Output Buffer
1 Enable DMA Requesting for Output Buffer
2 INDMAEN
Enable DMA Channel Request for Input Buffer.
(R/W)
0 Disable DMA Requesting for Input Buffer
1 Enable DMA Requesting for Input Buffer
1 ENCR
(R/W)
Encrypt or Decrypt.
Select Encryption/Decryption for a given mode. This bit need not be set/reset for
Wrap/Unwrap operation in Protected Key Storage.
0 Decrypt
1 Encrypt
0 BLKEN
(R/W)
Enable Bit for Crypto Block.
Enable Crypto hardware accelerator. This bit is intended to be used as a start of operation for all Crypto modes. Unless this bit is enabled, no Crypto mode shall function.
0 Enable Crypto Block
1 Disable Crypto Block
12–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Counter Initialization Vector
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Counter Initialization Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[19:16] (R/W)
Counter Initialization Value
Figure 12-17: CRYPT_CNTRINIT Register Diagram
Table 12-13: CRYPT_CNTRINIT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:0 VALUE
(R/W)
Counter Initialization Value.
This is the initialization value used in the internal counter generating functions that
are used in some modes of operation.
1. CCM/CCM* Mode: Only CRYPT_CNTRINIT.VALUE[15:0] are used in this
mode for initializing the counter initialization vector. The higher bits are ignored.
2. CTR Mode: CRYPT_CNTRINIT.VALUE[19:0] are used in to initialize the counter initialization vector. When the block is reset, the counters are initialized to the value programmed in this register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–41
ADuCM4050 CRYPT Register Descriptions
Payload Data Length
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Length of Payload Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[19:16] (R/W)
Length of Payload Data
Figure 12-18: CRYPT_DATALEN Register Diagram
Table 12-14: CRYPT_DATALEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:0 VALUE
(R/W)
Length of Payload Data.
Program the length of the Payload that needs to be encrypted with the following values:
1. MAC Mode: CRYPT_DATALEN.VALUE[19:0] should be used to program the
number of 128-bit blocks in the Payload.
2. CCM/CCM* Mode: CRYPT_DATALEN.VALUE[15:0] should be used to program the number of 128-bit blocks in the Payload.
12–42
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Input Buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Input Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Input Buffer
Figure 12-19: CRYPT_INBUF Register Diagram
Table 12-15: CRYPT_INBUF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Input Buffer.
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–43
ADuCM4050 CRYPT Register Descriptions
Interrupt Enable Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PRKSTRCMDONEEN (R/W)
PRKSTOR CMD DONE INTEN
INRDYEN (R/W)
Enable Input Ready Interrupt
HMACMSGRDYEN (R/W)
Status Bit for HMAC Message Input
Ready
OUTRDYEN (R/W)
Enables the Output Ready Interrupt
INOVREN (R/W)
Enable Input Overflow Interrupt
HMACDONEEN (R/W)
Interrupt Enable for HMAC Done
SHADONEN (R/W)
Enable SHA_Done Interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-20: CRYPT_INTEN Register Diagram
Table 12-16: CRYPT_INTEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 PRKSTRCMDONEEN
(R/W)
7 HMACMSGRDYEN
(R/W)
6 HMACDONEEN
(R/W)
5 SHADONEN
(R/W)
2 INOVREN
(R/W)
1 OUTRDYEN
(R/W)
0 INRDYEN
(R/W)
12–44
PRKSTOR CMD DONE INTEN.
This bit when set interrupts the core on completion of any PRKSTOR command
Status Bit for HMAC Message Input Ready.
This bit when set interrupts the core when HMAC accelerator is ready to take in the
user data. For the last block of user input data, the SHA_LAST_WORD register
should be programmed as described in the SHA_LAST_WORD section below.
Interrupt Enable for HMAC Done.
This bit when set interrupts the core when HMAC computation is done
Enable SHA_Done Interrupt.
This bit when set interrupts the core when SHA has finished processing the current
data block.
Enable Input Overflow Interrupt.
This bit when set interrupts the core in case input buffer overflows.
Enables the Output Ready Interrupt.
This bit when set interrupts the core when output buffer is ready to provide more data.
Once the output buffer is empty, this bit resets.
Enable Input Ready Interrupt.
This bit when set interrupts the core when input buffer is ready for more data. Once
the input buffer is full, this bit resets.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 0
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW0[15:0] (W)
KUW [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW0[31:16] (W)
KUW [31:0]
Figure 12-21: CRYPT_KUW0 Register Diagram
Table 12-17: CRYPT_KUW0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW0
KUW [31:0].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–45
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 1
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW1[15:0] (W)
KUW [63:32]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW1[31:16] (W)
KUW [63:32]
Figure 12-22: CRYPT_KUW1 Register Diagram
Table 12-18: CRYPT_KUW1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW1
KUW [63:32].
(RX/W)
12–46
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 10
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW10[15:0] (W)
KUW [351:320]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW10[31:16] (W)
KUW [351:320]
Figure 12-23: CRYPT_KUW10 Register Diagram
Table 12-19: CRYPT_KUW10 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW10
KUW [351:320].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–47
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 11
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW11[15:0] (W)
KUW [383:352]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW11[31:16] (W)
KUW [383:352]
Figure 12-24: CRYPT_KUW11 Register Diagram
Table 12-20: CRYPT_KUW11 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW11
(RX/W)
12–48
KUW [383:352].
Reg 11 of KUW Registers
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 12
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW12[15:0] (W)
KUW [415:384]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW12[31:16] (W)
KUW [415:384]
Figure 12-25: CRYPT_KUW12 Register Diagram
Table 12-21: CRYPT_KUW12 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW12
KUW [415:384].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–49
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 13
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW13[15:0] (W)
KUW [447:416]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW13[31:16] (W)
KUW [447:416]
Figure 12-26: CRYPT_KUW13 Register Diagram
Table 12-22: CRYPT_KUW13 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW13
KUW [447:416].
(RX/W)
12–50
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 14
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW14[15:0] (W)
KUW [479:448]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW14[31:16] (W)
KUW [479:448]
Figure 12-27: CRYPT_KUW14 Register Diagram
Table 12-23: CRYPT_KUW14 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW14
KUW [479:448].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–51
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 15
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW15[15:0] (W)
KUW [511:480]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW15[31:16] (W)
KUW [511:480]
Figure 12-28: CRYPT_KUW15 Register Diagram
Table 12-24: CRYPT_KUW15 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW15
KUW [511:480].
(RX/W)
12–52
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 2
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW2[15:0] (W)
KUW [95:64]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW2[31:16] (W)
KUW [95:64]
Figure 12-29: CRYPT_KUW2 Register Diagram
Table 12-25: CRYPT_KUW2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW2
KUW [95:64].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–53
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 3
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW3[15:0] (W)
KUW [127:96]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW3[31:16] (W)
KUW [127:96]
Figure 12-30: CRYPT_KUW3 Register Diagram
Table 12-26: CRYPT_KUW3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW3
KUW [127:96].
(RX/W)
12–54
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 4
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW4[15:0] (W)
KUW [159:128]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW4[31:16] (W)
KUW [159:128]
Figure 12-31: CRYPT_KUW4 Register Diagram
Table 12-27: CRYPT_KUW4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW4
KUW [159:128].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–55
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 5
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW5[15:0] (W)
KUW [191:160]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW5[31:16] (W)
KUW [191:160]
Figure 12-32: CRYPT_KUW5 Register Diagram
Table 12-28: CRYPT_KUW5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW5
KUW [191:160].
(RX/W)
12–56
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 6
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW6[15:0] (W)
KUW [223:192]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW6[31:16] (W)
KUW [223:192]
Figure 12-33: CRYPT_KUW6 Register Diagram
Table 12-29: CRYPT_KUW6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW6
KUW [223:192].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–57
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 7
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW7[15:0] (W)
KUW [255:224]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW7[31:16] (W)
KUW [255:224]
Figure 12-34: CRYPT_KUW7 Register Diagram
Table 12-30: CRYPT_KUW7 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW7
KUW [255:224].
(RX/W)
12–58
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 8
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW8[15:0] (W)
KUW [287:256]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW8[31:16] (W)
KUW [287:256]
Figure 12-35: CRYPT_KUW8 Register Diagram
Table 12-31: CRYPT_KUW8 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW8
KUW [287:256].
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–59
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Register 9
This register holds part of the wrapped or unwrapped key in respective modes.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KUW9[15:0] (W)
KUW [319:288]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
KUW9[31:16] (W)
KUW [319:288]
Figure 12-36: CRYPT_KUW9 Register Diagram
Table 12-32: CRYPT_KUW9 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 KUW9
KUW [319:288].
(RX/W)
12–60
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Validation String [63:32]
KUW Validation String [31:0]
15 14 13 12 11 10 9
1
0
1
0
0
1
1
8
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
1
0
InitialValue0[15:0] (W)
Initial Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
InitialValue0[31:16] (W)
Initial Value
Figure 12-37: CRYPT_KUWVALSTR1 Register Diagram
Table 12-33: CRYPT_KUWVALSTR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 INITIALVALUE0
(RX/W)
Initial Value.
Key wrap/unwrap initial value string. In wrap mode this will be integrity check string
and can be used by software to attach integrity check to the key being wrapped. In
unwrap mode, the resulting string should be matched by the software to ensure the
integrity of key
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–61
ADuCM4050 CRYPT Register Descriptions
Key Wrap Unwrap Validation String [31:0]
15 14 13 12 11 10 9
1
0
1
0
0
1
1
8
7
6
5
4
3
2
1
0
0
1
0
1
0
0
1
1
0
InitialValue1[15:0] (W)
Initial Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
InitialValue1[31:16] (W)
Initial Value
Figure 12-38: CRYPT_KUWVALSTR2 Register Diagram
Table 12-34: CRYPT_KUWVALSTR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 INITIALVALUE1
(RX/W)
12–62
Initial Value.
Key wrap/unwrap initial value string. In wrap mode this will be integrity check string
and can be used by software to attach integrity check to the key being wrapped. In
unwrap mode, the resulting string should be matched by the software to ensure the
integrity of key
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Nonce Bits [31:0]
Nonce is used in some modes of operations. Depending on the mode, different nonce lengths will be used.
1. CTR mode: This takes a 108-bit nonce. This nonce is formed as follows:
{CRYPT_NONCE3[11:0], CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
2. CBC mode: This takes a 128-bit nonce. This nonce is formed as follows:
{CRYPT_NONCE3, CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
3. CTR mode: This takes a 108-bit nonce. This nonce is formed as follows:
{CRYPT_NONCE3[15:0], CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0}
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 0: Nonce Bits [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 0: Nonce Bits [31:0]
Figure 12-39: CRYPT_NONCE0 Register Diagram
Table 12-35: CRYPT_NONCE0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 0: Nonce Bits [31:0].
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–63
ADuCM4050 CRYPT Register Descriptions
Nonce Bits [63:32]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 1: Nonce Bits [63:32]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 1: Nonce Bits [63:32]
Figure 12-40: CRYPT_NONCE1 Register Diagram
Table 12-36: CRYPT_NONCE1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 1: Nonce Bits [63:32].
(R/W)
12–64
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Nonce Bits [95:64]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 2: Nonce Bits [95:64]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 2: Nonce Bits [95:64]
Figure 12-41: CRYPT_NONCE2 Register Diagram
Table 12-37: CRYPT_NONCE2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 2: Nonce Bits [95:64].
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–65
ADuCM4050 CRYPT Register Descriptions
Nonce Bits [127:96]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 3: Nonce Bits [127:96]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 3: Nonce Bits [127:96]
Figure 12-42: CRYPT_NONCE3 Register Diagram
Table 12-38: CRYPT_NONCE3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 3: Nonce Bits [127:96].
(R/W)
12–66
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Output Buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Output Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Output Buffer
Figure 12-43: CRYPT_OUTBUF Register Diagram
Table 12-39: CRYPT_OUTBUF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Output Buffer.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–67
ADuCM4050 CRYPT Register Descriptions
Authentication Data Length
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Length of Associated Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-44: CRYPT_PREFIXLEN Register Diagram
Table 12-40: CRYPT_PREFIXLEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Length of Associated Data.
Program the length of the Associated that needs to be encrypted with the following
values:
CCM/CCM* Mode: 20 bits are provided to program the number of 128-bit blocks of
the associated data. The higher 4 bits are be ignored.
12–68
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
PRKSTOR Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CMD (R/W)
Command Input for PRKSTOR
KEY_INDEX (R/W)
Index of Key in PRKSTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-45: CRYPT_PRKSTORCFG Register Diagram
Table 12-41: CRYPT_PRKSTORCFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10:7 CMD
Command Input for PRKSTOR.
(R/W)
6:0 KEY_INDEX
Index of Key in PRKSTOR.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–69
ADuCM4050 CRYPT Register Descriptions
SHA Bits [31:0]
15 14 13 12 11 10 9
1
1
1
0
0
1
1
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
1
SHAHASH0[15:0] (R)
Word 0: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
1
0
1
0
1
0
0
0
0
0
1
0
0
1
SHAHASH0[31:16] (R)
Word 0: SHA Hash
Figure 12-46: CRYPT_SHAH0 Register Diagram
Table 12-42: CRYPT_SHAH0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH0
Word 0: SHA Hash.
(R/NW)
12–70
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
SHA Bits [63:32]
15 14 13 12 11 10 9
1
0
1
0
1
1
1
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
1
0
1
SHAHASH1[15:0] (R)
Word 1: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
1
1
0
1
1
0
1
1
0
0
1
1
1
SHAHASH1[31:16] (R)
Word 1: SHA Hash
Figure 12-47: CRYPT_SHAH1 Register Diagram
Table 12-43: CRYPT_SHAH1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH1
Word 1: SHA Hash.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–71
ADuCM4050 CRYPT Register Descriptions
SHA Bits [95:64]
15 14 13 12 11 10 9
1
1
1
1
0
0
1
8
7
6
5
4
3
2
1
0
1
0
1
1
1
0
0
1
0
SHAHASH2[15:0] (R)
Word 2: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
SHAHASH2[31:16] (R)
Word 2: SHA Hash
Figure 12-48: CRYPT_SHAH2 Register Diagram
Table 12-44: CRYPT_SHAH2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH2
Word 2: SHA Hash.
(R/NW)
12–72
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
SHA Bits [127:96]
15 14 13 12 11 10 9
1
1
1
1
0
1
0
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
0
1
0
SHAHASH3[15:0] (R)
Word 3: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
SHAHASH3[31:16] (R)
Word 3: SHA Hash
Figure 12-49: CRYPT_SHAH3 Register Diagram
Table 12-45: CRYPT_SHAH3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH3
Word 3: SHA Hash.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–73
ADuCM4050 CRYPT Register Descriptions
SHA Bits [159:128]
15 14 13 12 11 10 9
0
1
0
1
0
0
1
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
1
SHAHASH4[15:0] (R)
Word 4: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
0
SHAHASH4[31:16] (R)
Word 4: SHA Hash
Figure 12-50: CRYPT_SHAH4 Register Diagram
Table 12-46: CRYPT_SHAH4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH4
Word 4: SHA Hash.
(R/NW)
12–74
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
SHA Bits [191:160]
15 14 13 12 11 10 9
0
1
1
0
1
0
0
8
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
0
0
SHAHASH5[15:0] (R)
Word 5: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
0
1
1
0
1
1
0
0
0
0
0
1
0
1
SHAHASH5[31:16] (R)
Word 5: SHA Hash
Figure 12-51: CRYPT_SHAH5 Register Diagram
Table 12-47: CRYPT_SHAH5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH5
Word 5: SHA Hash.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–75
ADuCM4050 CRYPT Register Descriptions
SHA Bits [223:192]
15 14 13 12 11 10 9
1
1
0
1
1
0
0
8
7
6
5
4
3
2
1
0
1
1
0
1
0
1
0
1
1
SHAHASH6[15:0] (R)
Word 6: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
SHAHASH6[31:16] (R)
Word 6: SHA Hash
Figure 12-52: CRYPT_SHAH6 Register Diagram
Table 12-48: CRYPT_SHAH6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH6
Word 6: SHA Hash.
(R/NW)
12–76
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
SHA Bits [255:224]
15 14 13 12 11 10 9
1
1
0
0
1
1
0
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
0
1
SHAHASH7[15:0] (R)
Word 7: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
SHAHASH7[31:16] (R)
Word 7: SHA Hash
Figure 12-53: CRYPT_SHAH7 Register Diagram
Table 12-49: CRYPT_SHAH7 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH7
Word 7: SHA Hash.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–77
ADuCM4050 CRYPT Register Descriptions
SHA Last Word and Valid Bits Information
This register is to be written before writing the last word to SHA input register. This is to inform the SHA engine
that last word is about to be written by writing to the CRYPT_SHA_LAST_WORD.O_LAST_WORD. Also, the
number of valid bits has to be programmed in the CRYPT_SHA_LAST_WORD.O_BITS_VALID.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
O_Bits_Valid (R/W)
Bits Valid in SHA Last Word Input
O_Last_Word (R/W)
Last SHA Input Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 12-54: CRYPT_SHA_LAST_WORD Register Diagram
Table 12-50: CRYPT_SHA_LAST_WORD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:1 O_BITS_VALID
(R/W)
0 O_LAST_WORD
(R/W)
12–78
Bits Valid in SHA Last Word Input.
Indicates the number of valid bits in the last input word to SHA. This should auto
clear when CRYPT_STAT.SHADONE is set
Last SHA Input Word.
This should be set to indicate that last word is about to be written to the SHA engine.
This should auto clear when CRYPT_STAT.SHADONE is set.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRYPT Register Descriptions
Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
HMACMSGRDY (R/W)
Status Bit Indicates HMAC is Message
Ready
INRDY (R)
Input Buffer Status
OUTRDY (R)
Output Data Ready
HMACDONE (R/W)
Status Bit Indicates HMAC Done
INOVR (R/W1C)
Overflow in the Input Buffer
HMACBUSY (R)
Status Bit Indicates HMAC Busy
SHADONE (R/W)
SHA Computation Complete
OUTWORDS (R)
Number of Words in the Output Buffer
SHABUSY (R)
SHA Busy. in Computation
INWORDS (R)
Number of Words in the Input Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRKSTOR_BUSY (R)
Indicates PrKSTOR is Busy
PRKSTOR_CMD_DONE (R/W)
Indicates Command Done for PrKStor
CMD_ISSUED (R)
Last Command Issued to PrKStor
PRKSTOR_CMD_FAIL (R/W)
Indicates Last Command Issued Failed
PRKSTOR_RET_STATUS (R)
ECC Errors in the PRKSTOR_RETRIEVE
Command
Figure 12-55: CRYPT_STAT Register Diagram
Table 12-51: CRYPT_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 PRKSTOR_BUSY
(R/NW)
30:27 CMD_ISSUED
(R/NW)
Indicates PrKSTOR is Busy.
This bit when set indicates that the protected key storage is busy executing a command. All the writes to the protected key store configuration register are ignored while
this bit is set
Last Command Issued to PrKStor.
This field records the last command issued to Protected Key Storage. It is cleared when
block is disabled.
26:25 PRKSTOR_RET_STATUS ECC Errors in the PRKSTOR_RETRIEVE Command.
(R/NW)
24 PRKSTOR_CMD_FAIL
This field indicates whether there has been an ECC error
Indicates Last Command Issued Failed.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
12–79
ADuCM4050 CRYPT Register Descriptions
Table 12-51: CRYPT_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
23 PRKSTOR_CMD_DONE
Indicates Command Done for PrKStor.
(R/W)
15 HMACMSGRDY
Status Bit Indicates HMAC is Message Ready.
(R/W)
14 HMACDONE
Status Bit Indicates HMAC Done.
(R/W)
13 HMACBUSY
Status Bit Indicates HMAC Busy.
(R/NW)
12:10 OUTWORDS
Number of Words in the Output Buffer.
(R/NW)
9:7 INWORDS
Number of Words in the Input Buffer.
(R/NW)
6 SHABUSY
(R/NW)
5 SHADONE
(R/W)
2 INOVR
SHA Busy. in Computation.
Indicates that computation is ongoing for recent data. While this is set, values in the
CRYPT_SHAHx registers are invalid.
SHA Computation Complete.
Indicates that hash computation is complete for current data. When hash computation
is complete, the current value of the hash may be read out or new data may be written
into the input buffer to proceed with further computation.
Overflow in the Input Buffer.
(R/W1C)
1 OUTRDY
(R/NW)
0 INRDY
(R/NW)
12–80
Output Data Ready.
Output Data ready to be read
Input Buffer Status.
Input buffer requires more data before computation can begin. Remains set till the
buffer is filled.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
True Random Number Generator (TRNG)
13 True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is used during operations where non-deterministic values are required.
This may include generating challenges for secure communication or keys used for an encrypted communication
channel. The generator can be run multiple times to generate a sufficient number of bits for the strength of the
intended operation. The true random number generator can be used to seed a deterministic random bit generator
such as one described by NIST CRC SP-800-90A.
TRNG Features
The following are the features of TRNG:
• Programmable length to obtain sufficient entropy.
• Includes an oscillator counter to characterize the sampling jitter.
• Cannot generate any interrupts.
TRNG Functional Description
This section provides information on the function of the TRNG used by the ADuCM4050 MCU.
TRNG Block Diagram
The figure shows the block diagram of the TRNG used by the ADuCM4050 MCU.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
13–1
TRNG Functional Description
Previous
Oscillator Count
Ring
Oscillator
TEST
EN
6-bit Oscillator
Ripple Counter
Oscillator
Count
Difference
22-bit Synchronous
Counter
8-bit CRC
Accumulator
Sample
22-bit Sample
Counter
32-bit Data
Buffer
TRNG DATA
Ready
Peripheral
Clock
TRNG LEN
Figure 13-1: TRNG Block Diagram
The TRNG is based on a sampled asynchronous clock (in this implementation a ring oscillator). A CRC is used as a
compaction function to reduce a large amount of low entropy bits into a smaller amount of high entropy bits. The
CRC will accumulate a programmable number of samples determined by the sample length register.
The TRNG is enabled through the control register. The length register specifies the number of samples for which
the TRNG should run to accumulate sufficient entropy. One sample is obtained on each peripheral clock and compacted by the CRC. Once the TRNG has accumulated the programmed number of samples, the accumulated 8-bit
CRC result can be read. Software can poll a status bit (RNG_STAT.RNRDY) or be interrupted when the TRNG is
ready.
Any number of iterations can be run. For example, 112 bits of entropy can be obtained by reading the 8-bit TRNG
result at least 14 times.
TRNG Oscillator Counter
The TRNG peripheral includes an oscillator counter. This on-chip counter can be used to characterize the sampling
jitter which is difficult to measure off-chip. The sample jitter is the source of entropy for the random number generator.
By counting the number of ring oscillator clocks over a given sampling period, the frequency ratio of the ring oscillator to peripheral sampling clock can be determined (and the ring oscillator frequency can be determined if the peripheral clock frequency is known).
fOSCCLK
=
fPCLK
OSCCNT
X
SAMPCNT
where,
13–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
TRNG Functional Description
OSCCNT is the oscillator count (RNG_OSCCNT.VALUE).
SAMPCNT (length of sampling time) used by the sample counter can be determined from the RNG_LEN register.
The sample jitter can be determined by calculating the standard deviation of multiple oscillator count values.
A pseudo-code for an efficient loop across N values to determine the average oscillator count and jitter is shown
below:
sum=0; sum_sqr=0;
for(i=0;i<N;i++)
{
gen_rng();
sum += osc_cnt;
sum_sqr += osc_cnt*osc_cnt;
}
avg=sum/N;
std=sqrt((sum_sqr-avg*sum)/(N-1));
The code has been simplified for clarity. If implemented in C:
• The sum and sum_sqr variables must be integer data types. Floating point variables could lose precision if the
sums accumulate for a sufficient length to overflow the fractional portion of the variable truncating the result.
It is desirable to keep the entire fractional portion, so the exponent of a floating point data type can be excluded.
• The sum variable needs log2(osc_cnt) + log2(N) bits of storage.
• The sum_sqr variable needs 2 × log2(osc_cnt) + log2(N) bits of storage.
• The squaring operation (osc_cnt × osc_cnt and avg × avg) requires a cast to a type with size at least 2 ×
log2(osc_cnt).
• The avg and std variables can take fractional values (real or fixed point data types).
• The division needs a cast to a fractional data type.
For accurate jitter measurements, the standard deviation of RNG_OSCCNT should be at least one. If it is less than
one, then SAMPCNT must be increased.
The jitter of the oscillator counter encapsulates both jitter of the ring oscillator and jitter of the peripheral clock.
This can be used to determine sample jitter. If the jitter of the peripheral clock is known, the jitter of the oscillator
clock can be determined using the following equation.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
13–3
TRNG Functional Description
OSCCNT
SAMPCNT
SAMPCNT
OSCCNT
1
f PCLK
2
PCLK
SAMPLE
+
2
OSCCLK
OSCCNT
SAMPCNT
TRNG Entropy and Surprisal
The jitter of the sampling clocks is the source of entropy for the random number generator. Noise in the transistors
of the oscillator contributes to jitter. Accumulated long-term jitter increases with the square root of time or the
number of clocks.
TOTAL
N
CLK
The number of samples that need to be accumulated to achieve ideal entropy of 1.0/bit depends on the amount of
jitter in the system. Entropy is calculated as follows:
average entropy =
p i lo g2(pi )
minimum entropy = min(-log2(pi ) )
The probability of each number occurring should be the same or uniform for all numbers for an ideal generator. A
deficient generator would output some numbers more frequently than others. This random number generator was
designed to retain no state such that entropy can be measured and quantified in this manner. For each random number generated, the CRC is reset and the ring oscillator starts up in the same phase. If there is insufficient entropy in
the system, then the generator will output the same number more frequently. This is by design and makes entropy
assessment possible. Insufficient entropy can be observed by setting SAMPCNT to a low value in which case some
random numbers will appear more frequently than others. SAMPCNT should be increased until the probability of
seeing each number is uniform.
The minimum entropy of the TRNG can be computed by tallying a histogram of generated random numbers and
calculating the probability of the most frequent number occurring. The minimum entropy equation should be used
when determining how many true random numbers to seed to a deterministic random number generator.
The minimum value for SAMPCNT (set by RNG_LEN register) needed to obtain ideal minimum surprisal for the
8-bit accumulator can be determined using the following equation. A conservative design will set SAMPCNT at
least as large as this, if not greater (to account for variations in jitter across various operating conditions).
SAMPCNT min
1
f
2
2
SAMPLE OSC
If an attacker can physically tamper the system and has control of the peripheral clock, the jitter due to the peripheral clock must be removed from the sample jitter in the previous calculation. This assumes an attacker can replace the
crystal with a low jitter clock source. A physical attacker may also use better voltage supplies that can minimize the
amount of noise in the system. If an attacker can remove or minimize the peripheral clock jitter, then the entropy
13–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
TRNG Functional Description
source of the random number generator is reduced. The system should rely solely on the jitter of the ring oscillator,
and conservatively, assume the jitter of the peripheral clock to be zero.
Oscillator Count Difference
There is logic built into the random number generator to calculate the difference between subsequent oscillator
count values. This can be used to calculate the variance and quantify the amount of jitter and thus entropy in the
system. This provides a measure of health of the random number generator entropy source.
The statistical sample variance is typically calculated as follows:
S
2
1
n-1
n
(xi — x)2
i=1
The on-chip circuit calculates the difference in oscillator count between the current and previous sample. Since the
samples are independent and identically generated, this removes the mean.
E[X] — E[X] = 0
E[(X — X)2] = 2 2
The variance can be computed by averaging half of the square of the difference between oscillator count values.
The average can be replaced with a low pass IIR filter to track changes in the variance over time.
ADuCM4050 RNG Register Descriptions
Random Number Generator (RNG) contains the following registers.
Table 13-1: ADuCM4050 RNG Register List
Name
Description
RNG_CTL
RNG Control Register
RNG_DATA
RNG Data Register
RNG_LEN
RNG Sample Length Register
RNG_OSCCNT
Oscillator Count
RNG_OSCDIFF[n]
Oscillator Difference
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
13–5
ADuCM4050 RNG Register Descriptions
Table 13-1: ADuCM4050 RNG Register List (Continued)
Name
Description
RNG_STAT
RNG Status Register
13–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RNG Register Descriptions
RNG Control Register
The RNG_CTL register is used to enable the random number generator.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SINGLE (R/W)
Generate a Single Number
EN (R/W)
RNG Enable
Figure 13-2: RNG_CTL Register Diagram
Table 13-2: RNG_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 SINGLE
(R/W)
Generate a Single Number.
By default the RNG will generate and buffer four 8-bit values to provide a 32-bit random number. Setting this bit will cause the RNG to only generate a single 8-bit random number.
0 Buffer Word
1 Single Byte
0 EN
(R/W)
RNG Enable.
When RNG_CTL.EN is set and RNG_STAT.RNRDY is clear, the ring oscillator will
be powered up and the number of samples defined by RNG_LEN will be accumulated
in the RNG_DATA register.
0 Disable the RNG
1 Enable the RNG
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
13–7
ADuCM4050 RNG Register Descriptions
RNG Data Register
RNG_DATA register provides the CPU with read-only access of the entropy accumulator (8-bit CRC) and data buffer. When the data buffer is not enabled, an 8-bit result is provided. When the data buffer is enabled, 32-bits (four
8-bit values) are provided. The contents of this register are valid when the RNG_STAT.RNRDY bit is set. This register is reset when the RNG_STAT.RNRDY bit is cleared. The RNG_STAT.RNRDY bit is automatically cleared
when this register is read and the CPU is not in debug halt. Reading this register by the CPU when RNG_CTL.EN
is set will cause a new random number to be generated.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BUFF[7:0] (RC)
Buffer for RNG Data
VALUE (RC)
Value of the CRC Accumulator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUFF[23:8] (RC)
Buffer for RNG Data
Figure 13-3: RNG_DATA Register Diagram
Table 13-3: RNG_DATA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:8 BUFF
(RC/NW)
7:0 VALUE
(RC/NW)
13–8
Buffer for RNG Data.
When configured to generate 32-bit values, RNG_DATA.BUFF stores the previous
three numbers generated.
Value of the CRC Accumulator.
This register provides data from the entropy compaction function (8-bit CRC accumulator).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RNG Register Descriptions
RNG Sample Length Register
The RNG_LEN register defines the number of samples to accumulate in the CRC register when generating a random number. The number of samples accumulated is RNG_LEN.RELOAD scaled by 2^RNG_LEN.PRESCALE.
15 14 13 12 11 10 9
0
0
1
1
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PRESCALE (R/W)
Prescaler for the Sample Counter
RELOAD (R/W)
Reload Value for the Sample Counter
Figure 13-4: RNG_LEN Register Diagram
Table 13-4: RNG_LEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:12 PRESCALE
(R/W)
11:0 RELOAD
(R/W)
Prescaler for the Sample Counter.
The sample counter reload value RNG_LEN.RELOAD is scaled by
2^RNG_LEN.PRESCALE. The prescaler is a 10-bit counter. Valid values for the prescaler are 0 to 10. Values greater than 10 will saturate at the maximum prescaler value.
Reload Value for the Sample Counter.
Defines the number of samples to accumulate in the CRC when generating a random
number.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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ADuCM4050 RNG Register Descriptions
Oscillator Count
The oscillator counter counts the number of ring oscillator cycles which occur during the generation of a random
number. The oscillator counter is 28-bits. The oscillator counter will saturate at the maximum value to prevent overflow.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Oscillator Count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[27:16] (R)
Oscillator Count
Figure 13-5: RNG_OSCCNT Register Diagram
Table 13-5: RNG_OSCCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
27:0 VALUE
(R/NW)
13–10
Oscillator Count.
This register is only valid when RNG_STAT.RNRDY is set.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RNG Register Descriptions
Oscillator Difference
The oscillator difference register stores the difference in RNG_OSCCNT from the current value compared to the previous value (RNG_OSCCNT[n] - RNG_OSCCNT[n-1]). This difference is represented as a signed 8-bit value. It saturates at the maximum and minimum values. This can be used to reconstruct RNG_OSCCNT for the values currently
in the RNG_DATA buffer. This information can be used to compute the RNG_OSCCNT variance to check the
health of the random number generator and ensure there is adequate entropy.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DELTA (R)
Oscillator Count Difference
Figure 13-6: RNG_OSCDIFF[n] Register Diagram
Table 13-6: RNG_OSCDIFF[n] Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 DELTA
Oscillator Count Difference.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
13–11
ADuCM4050 RNG Register Descriptions
RNG Status Register
The RNG_STAT register indicates when the RNG has finished generating a random number.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STUCK (R/W1C)
Sampled Data Stuck High or Low
RNRDY (R/W1C)
Random Number Ready
Figure 13-7: RNG_STAT Register Diagram
Table 13-7: RNG_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 STUCK
(R/W1C)
0 RNRDY
(R/W1C)
Sampled Data Stuck High or Low.
When a random number is generated, a circuit monitors the output of the sampled
ring oscillator. This circuit checks to ensure the ring oscillator output has been sampled both high and low and is not stuck at a constant value. This bit is sticky once set
and is write one to clear.
Random Number Ready.
This bit indicates when the value in RNG_DATA is ready to be read. An interrupt is
generated when this bit is set. The ring oscillator is stopped when this bit is set to conserve power. This bit is automatically cleared when the RNG_DATA register is read and
the CPU is not stopped in Debug Halt. This bit can also be written with one to clear.
0 Data register not ready
1 Data register is ready to be read
13–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Cyclic Redundancy Check (CRC)
14 Cyclic Redundancy Check (CRC)
The CRC accelerator is used to compute the CRC for a block of memory locations. The exact memory location can
be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a checksum that can be used to compare with an expected signature. The ADuCM4050 MCU is responsible for the final
CRC comparison.
CRC Features
The CRC used by the ADuCM4050 MCU supports the following features:
• Generate a CRC signature for a block of data.
• Programmable polynomial length of up to 32 bits.
• Operates on 32 bits of data at a time and also supports data lengths from 1-8 bits.
• MSB-first and LSB-first CRC implementations.
• Various data mirroring capabilities.
• Initial seed to be programmed by user.
• DMA controller (using software DMA) can be used for data transfer to offload the MCU.
CRC Functional Description
This section provides information on the function of the CRC accelerator used by the ADuCM4050 MCU. Control for address decrement/increment options for computing the CRC on a block of memory is in the DMA controller.
For more information about these options, refer to Direct Memory Access (DMA).
CRC Block Diagram
The CRC block diagram is shown below.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–1
CRC Operating Modes
CRC Polynomial
CRC
Computation
Mirror Options
CRC Control
CRC Input Data
APB Interface
CRC Result
Figure 14-1: CRC Block Diagram
The CRC accelerator works on 32-bit data words which are fed to the block through the DMA channel dedicated to
the CRC accelerator or directly by the MCU and the CRC accelerator guarantees immediate availability of the CRC
output.
CRC Operating Modes
The accelerator calculates CRC on the data stream it receives, typically 32 bits at a time, which is written into the
block either using the DMA engine or the MCU directly.
This accelerator also supports data lengths from 1 to 8 bits, which implies that CRC can be calculated on any data
lengths. For example, to calculate CRC on 23 data bytes, the data must be fed to the CRC accelerator as 5 words
and 3 bytes. The data can also be fed as 23 separate byte writes, but, it requires more number of cycles and may not
be an efficient way to perform this operation. If the data length is 23 bits, it can be entered as 2 bytes and 7 bits.
The CRC accelerator provides flexibility to process any length data with all polynomial lengths from 1-32 bits,
MSB-first or LSB-first
Data mirroring on the input can be performed at bit-, byte-, and word level before the CRC engine uses it by setting
the CRC_CTL.BITMIRR, CRC_CTL.BYTMIRR, and CRC_CTL.W16SWP bits respectively. Mirroring option is
not applicable on any data that is less than a byte. Byte mirroring and word swap options do not work on byte data.
Only bit mirroring is applicable for byte data.
CRC algorithm runs on the incoming data stream written to the CRC_IPDATA register. For every new word of
data received, the CRC is computed and the CRC_RESULT register is updated with the calculated CRC. The CRC
14–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
CRC Operating Modes
Accelerator guarantees the immediate availability of CRC result up to the current data in the CRC Result register
and the same can be read by the MCU.
The CRC engine uses the current CRC_RESULT for generating the next CRC_RESULT when a new data-word is
received. The CRC_RESULT register can be programmed with an initial seed. The bit-width of the seed value for
an n-bit polynomial must be n. The seed must be justified in the CRC_RESULT register.
Polynomial
The CRC Accelerator supports the calculation of the CRC using any length polynomial. The polynomial has to be
written to the CRC_POLY register. For MSB first implementation the highest power is omitted while programming
the CRC polynomial register and the polynomial is left justified. For LSB, first implementation the polynomial is
right justified and the LSB is omitted. The CRC_RESULT register contains n-bit MSBs as checksum for an n-bit
CRC polynomial.
The following examples illustrate the CRC polynomial.
16-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = (1) 0001 0000 0010 0001 = 0x1021
The largest exponent (x16 term) is implied, so it is 0001 0000 0010 0001
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0001 0000
0010 0001
8b0
8b0
CRC Result Register (CRC_RESULT)
CRC
Result
8b0
8b0
Initial seed programmed in CRC Result Register (CRC_RESULT)
CRC
SEED
8b0
8b0
16-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = 1000 0100 0000 1000 (1) = 0x8408
The smallest exponent (x0 term) is implied, so it is 1000 0100 0000 1000
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0
8b0
1000 0100
0000 1000
CRC Result Register (CRC_RESULT)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–3
CRC Operating Modes
8b0
8b0
CRC
Result
Initial seed programmed in CRC Result Register (CRC_RESULT)
8b0
8b0
CRC
SEED
8-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = (1) 0000 0111= 0x07
The largest exponent (x8 term) is implied, so it is 0000 0111
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0000 0111
8b0
8b0
8b0
8b0
8b0
CRC Result Register (CRC_RESULT)
CRC RESULT
8b0
Initial seed programmed in CRC Result Register (CRC_RESULT)
CRC SEED
8b0
8b0
8b0
8-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = 1000 0011 (1) = 0x83
The smallest exponent (x0 term) is implied, so it is 1000 0011
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0
8b0
8b0
1000 0011
CRC Result Register (CRC_RESULT)
8b0
8b0
8b0
CRC RESULT
Initial seed programmed in CRC Result Register (CRC_RESULT)
8b0
8b0
8b0
CRC SEED
The CRC engine uses the following 32-bit CRC polynomial as default (IEEE 802.3):
g(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
14–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
CRC Operating Modes
This is programmed for MSB First Calculation by default as shown below
0x04
0xC1
0x1D
0xB7
Reset and Hibernate Modes
1. The CRC configuration bits are retained except the block enable bit (CRC_CTL.EN). The block needs to be
enabled again after coming out of the Hibernate mode.
2. The CRC polynomial and CRC result registers are retained after coming out of the Hibernate mode.
Table 14-1: Reset and Hibernate Modes
Register
Reset
Hibernate
CRC_CTL
0x0
Apart from BLKEN, all other bits retained
CRC_POLY
0x04C11DB7
Retained
CRC_IPDATA
0x0
Not retained (0x0)
0x0
Retained
CRC_IPBYTE
CRC_IPBITS[n]
CRC_RESULT
Input Data Length
The following examples show how to use the CRC accelerator for different data lengths and mirroring options.
1. Data length is a multiple of word(4 bytes)
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 512 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.
The data length is 16 words. The DMA can be setup to transfer these 16 words to the CRC_IPDATA register.
The result can be read by the core after the channel_done interrupt is received from the DMA.
2. Data Length is a multiple of byte but not a multiple of word
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 496 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–5
CRC Data Transfer
The data length is 15 words and 2 bytes. The DMA can be setup to transfer these 15 words to the
CRC_IPDATA register. The core can write the remaining two bytes to the CRC_IPBYTE register after receiving the dma_done interrupt. The result can be read immediately after core finishes writing the last two bytes.
To feed data to the CRC accelerator, the DMA can be configured in byte transfer mode, where it transfers data
to the CRC_IPBYTE register one byte at a time. This mode is not the recommended as the CRC accelerator
must be active for about four time when compared with the other method. Also, only bit mirroring option is
applicable for CRC calculation on byte data.
3. Data length is not a multiple of byte or word
Polynomial: Any length up to 32 bits, MSB-first or LSB-first CRC calculation
Data Length: 51 bits
The CRC_CTL register must be configured with appropriate options.
The polynomial must be programmed as described in the Polynomial section.
The data length is 1 word, 2 bytes and 3 bits. The data must be fed to the CRC accelerator in the following
order: One word write to the CRC_IPDATA register, followed by two byte writes to the CRC_IPBYTE register and then a write to the CRC_IPBIT3 register. If the residual data is n-bit (where n ɛ [1,7]), it must be
written to the CRC_IPBITS[n] register.
If the CRC calculation is MSB-first, the n-bit data must be aligned to the MSB of the input data and vice
versa.
Consider an example where the residual data is 3-bit data (say 3'b101). For MSB-first calculation, the input
byte must be packed as 8’b101_00000. For LSB-first, it must be packed as 8'b00000_101. This byte must be
written to the CRC_IPBIT3 register. Mirroring options is not applicable for the residual data.
CRC Data Transfer
The data stream can be written to the block using DMA controller or by the MCU directly.
CRC Interrupts and Exceptions
DMA channel generates an interrupt upon completion of data transfer to the CRC block.
CRC Programming Model
This block is provided to calculate CRC signature over block of data in the background while the core can perform
other tasks.
The CRC block supports two modes of CRC calculation: Core access and DMA access.
14–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
CRC Programming Model
Core Access
1. Program the CRC_POLY register with the required polynomial justified as shown in the examples in the Polynomial section.
2. Program the CRC_RESULT register with initial seed. The seed must be justified and written to the
CRC_RESULT register, as described in Polynomial.
3. Kick in the CRC Accelerator block by writing into the CRC_CTL register:
a. Set the CRC_CTL.EN bit high.
b. Modify the CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits, which configure the application with different mirror options. For more information about this, refer to Mirroring
Options.
c. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
NOTE: The sub-steps in Step 3 require only a single write to the CRC_CTL register.
The core can now start sending data to the CRC block by writing into the CRC_IPDATA register. The
CRC accelerator continues to calculate the CRC as long as data is written to the CRC_IPDATA register.
It is the responsibility of the application to count the number of words written to the CRC block. Once
all the words are written, the application can read the CRC_RESULT register.
4. Read the CRC_RESULT register. It contains the n-bit result in n MSB bits for MSB first and in n LSB bits for
LSB first CRC calculation.
5. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Steps 1-4.
6. Disable the CRC accelerator block by clearing the CRC_CTL.EN bit. This ensure that the block is in the lowpower state.
DMA Access
The CRC accelerator block supports software DMA.
1. Program the CRC_POLY register with the required polynomial left justified as shown in the example in the
Polynomial section.
2. Program the CRC_RESULT register with initial seed value. The seed should be justified and written to the
CRC_RESULT register, as described in Polynomial.
3. Enable accelerator function by writing into CRC_CTL register.
a. Set the CRC_CTL.EN bit high.
b. Modify the CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits, which configure the application with different mirror options. For more information about this, refer to Mirroring
Options.
c. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–7
CRC Programming Model
NOTE: The sub-steps in Step 3 require only a single write to the CRC_CTL register.
The DMA starts sending the CRC data by writing into the CRC_IPDATA. The CRC Accelerator block
continues to calculate the CRC as long as the data is written to the CRC_IPDATA.
4. Setup the DMA channels as required. DST_END_PNTR value is CRC_IPDATA register address. Data size is
word. Use the destination no increment option for the channel used. For more information about programming the DMA, refer to Programming Guidelines.
5. A dma_done interrupt signal of the DMA channel indicates the completion of data transfer to the CRC
block.
6. Repeat Steps 1-4 until all the data has been sent to the accelerator block.
7. Read the CRC_RESULT register. It contain the n-bit result in n MSB bits for MSB first and in n LSB bits for
LSB first CRC calculations.
8. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat Steps 1-5.
9. Disable the CRC accelerator block by clearing the CRC_CTL.EN bit. This ensures that the block is in lowpower state.
Mirroring Options
The CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BYTMIRR bits determine the sequence of the
bits in which the CRC is calculated.
Mirroring Options for 32-bit Input Data with 32-bit Polynomial table shows the details of all the mirroring options
used within this block for a 32-bit polynomial.
Assume that DIN[31:0] is the data being written to the CRC_IPDATA register, and CIN[31:0] is the data after the
mirroring of the data. The serial engine calculates CIN[31:0] starting with the MSB bit and ending with LSB bit in
sequence, that is, CIN[31], CIN[30], ... CIN[1], CIN[0] in order.
Table 14-2: Mirroring Options for 32-bit Input Data with 32-bit Polynomial
W16SWP BYTMIRR
BITMIRR Input Data
DIN[31:0]
CRC Input Data (CIN[31:0])
0
0
0
DIN[31:0]
CIN[31:0] = DIN[31:0]
0
0
1
DIN[31:0]
CIN[31:0] = DIN[24:31], DIN[16:23], DIN[8:15], DIN[0:7]
0
1
0
DIN[31:0]
CIN[31:0] = DIN[23:16], DIN[31:24], DIN[7:0], DIN[15:8]
0
1
1
DIN[31:0]
CIN[31:0] = DIN[16:23], DIN[24:31], DIN[0:7], DIN[8:15]
1
0
0
DIN[31:0]
CIN[31:0] = DIN[15:0], DIN[31:16]
1
0
1
DIN[31:0]
CIN[31:0] = DIN[8:15], DIN[0:7], DIN[24:31], DIN[16:23]
1
1
0
DIN[31:0]
CIN[31:0] = DIN[7:0], DIN[15:8], DIN[23:16], DIN[31:24]
1
1
1
DIN[31:0]
CIN[31:0] = DIN[0:7], DIN[8:15], DIN[16:23], DIN[24:31]
14–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRC Register Descriptions
ADuCM4050 CRC Register Descriptions
CRC Accelerator (CRC) contains the following registers.
Table 14-3: ADuCM4050 CRC Register List
Name
Description
CRC_CTL
CRC Control
CRC_IPBITS[n]
Input Data Bits
CRC_IPBYTE
Input Data Byte
CRC_IPDATA
Input Data Word
CRC_POLY
Programmable CRC Polynomial
CRC_RESULT
CRC Result
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–9
ADuCM4050 CRC Register Descriptions
CRC Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
W16SWP (R/W)
Word16 Swap
EN (R/W)
CRC Peripheral Enable
BYTMIRR (R/W)
Byte Mirroring
LSBFIRST (R/W)
LSB First Calculation Order
BITMIRR (R/W)
Bit Mirroring
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
RevID (R)
Revision ID
Figure 14-2: CRC_CTL Register Diagram
Table 14-4: CRC_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 REVID
Revision ID.
(R/NW)
4 W16SWP
(R/W)
Word16 Swap.
This bit will swap 16-bit half-words within a 32-bit word.
0 Word16 Swap disabled
1 Word16 Swap enabled
3 BYTMIRR
(R/W)
Byte Mirroring.
This bit will swap 8-bit bytes within each 16-bit half-word.
0 Byte Mirroring is disabled
1 Byte Mirroring is enabled
2 BITMIRR
(R/W)
Bit Mirroring.
This bit will swap bits within each byte.
0 Bit Mirroring is disabled
1 Bit Mirroring is enabled
1 LSBFIRST
(R/W)
LSB First Calculation Order.
0 MSB First CRC calculation is done
1 LSB First CRC calculation is done
14–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRC Register Descriptions
Table 14-4: CRC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 EN
(R/W)
CRC Peripheral Enable.
0 CRC peripheral is disabled
1 CRC peripheral is enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–11
ADuCM4050 CRC Register Descriptions
Input Data Bits
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DATA_BITS (W)
Input Data Bits
Figure 14-3: CRC_IPBITS[n] Register Diagram
Table 14-5: CRC_IPBITS[n] Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 DATA_BITS
(RX/W)
14–12
Input Data Bits.
These fields are used to calculate CRC on partial data byte from 1-7 bits of input data.
Computing CRC on n bits of input data can be achieved by writing byte to n bit of
CRC_IPBITS[n].DATA_BITS.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRC Register Descriptions
Input Data Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DATA_BYTE (W)
Input Data Byte
Figure 14-4: CRC_IPBYTE Register Diagram
Table 14-6: CRC_IPBYTE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 DATA_BYTE
(RX/W)
Input Data Byte.
Writing data to this field calculates CRC on a byte of data.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–13
ADuCM4050 CRC Register Descriptions
Input Data Word
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Data Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Data Input
Figure 14-5: CRC_IPDATA Register Diagram
Table 14-7: CRC_IPDATA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Data Input.
(RX/W)
14–14
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 CRC Register Descriptions
Programmable CRC Polynomial
15 14 13 12 11 10 9
0
0
0
1
1
1
0
8
7
6
5
4
3
2
1
0
1
1
0
1
1
0
1
1
1
VALUE[15:0] (R/W)
CRC Reduction Polynomial
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
VALUE[31:16] (R/W)
CRC Reduction Polynomial
Figure 14-6: CRC_POLY Register Diagram
Table 14-8: CRC_POLY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
CRC Reduction Polynomial.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
14–15
ADuCM4050 CRC Register Descriptions
CRC Result
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
CRC Residue
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
CRC Residue
Figure 14-7: CRC_RESULT Register Diagram
Table 14-9: CRC_RESULT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
CRC Residue.
(R/W)
14–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Serial Peripheral Interface (SPI)
15 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an industry-standard synchronous serial link that supports communication
with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of
two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other
SPI-compatible devices. Enhanced modes of operation such as flow control, fast mode, and read-command mode
(half-duplex operation) are also supported. In addition, a DMA mode allows for transferring several words with
minimal CPU interaction.
With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible
devices in master mode, slave mode, and multislave environments. The SPI peripheral includes programmable baud
rates, clock phase, and clock polarity. The peripheral can operate in a multislave environment by interfacing with
several other devices, acting as either a master device or a slave device. In a multislave environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to
interface with fast master devices by providing an SPI ready pin which flexibly controls the transfers.
SPI Features
The SPI module supports the following features:
• Serial clock phase mode and serial clock polarity mode
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation
• Flow control
• Multiple CS line
• CS software override
• Support for 3-pin SPI Master or Slave mode
• LSB-first transfer option
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–1
SPI Functional Description
• Interrupt mode: interrupt after 1, 2, 3, 4, 5, 6, 7, or 8 bytes
SPI Functional Description
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A
serial clock line synchronizes shifting and sampling of the information on the two serial data lines. During a data
transfer, one SPI system acts as the link master which controls the data flow, while the other system acts as the slave,
which has data shifted into and out of it by the master. Different devices can take turn being masters, and one master may simultaneously shift data into multiple slaves (broadcast mode).
However, only one slave may drive its output to write data back to the master at any given time. This must be enforced in the broadcast mode, where several slaves can be selected to receive data from the master, but only one slave
can be enabled to send data back to the master.
The SPI port can be configured for master or slave operation and consists of four pins: MISO, MOSI, SCLK, and
CS. Note that the GPIOs used for SPI communication must be configured in SPI mode before enabling the SPI
peripheral. The peripheral should be enabled by setting the SPI_CTL.SPIEN bit. If not used, the peripheral must
be turned off by clearing this bit.
SPI Block Diagram
The figure shows the SPI block diagram.
SPI
Flow Control
APB
Registers
16-bit
APB
State Machine
SPI
(3 or 4 pins)
External
SCLK
Generation
Interface
Tx/Rx FIFO
IRQ,
DMA - Req
IRQ/DMA
Generation
Figure 15-1: SPI Block Diagram
15–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Functional Description
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on
the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on
the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as
byte wide (8-bit) serial data.
SCLK (Serial Clock I/O) Pin
The master serial clock (SCLK) synchronizes the data being transmitted and received during the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
In the master mode, the polarity and phase of the clock are controlled by the SPI_CTL register, and the bit rate is
defined in the SPI_DIV register as follows:
f serial clock = CLK / ( 2 (1 + SPIx_DIV))
CLK is PCLK for SPI0 and SPI1, and HCLK for SPIH
The maximum data rate is 13 Mbps for a maximum clock frequency of 26 MHz.
In the slave mode, the SPI_CTL register must be configured with the phase and polarity of the expected input
clock. The slave accepts data from an external master up to 13 Mbps.
In both master and slave modes, data is transmitted on one edge of the SCLK signal and sampled on the other.
Therefore, the polarity and phase are configured the same for the master and slave devices.
Chip Select (CS I/O) Pin
In SPI slave mode, a transfer is initiated by the assertion of CS, which is an active low input signal. The SPI port
then transmits and receives 8-bit data until the transfer is concluded by deassertion of CS. In slave mode, CS is
always an input.
In SPI master mode, the CS is an active low output signal. It asserts itself automatically at the beginning of a transfer
and deasserts itself upon completion.
In a multi-slave environment, we would support up to 4 different slaves. The SPI master can be configured to drive
up to four CS lines (CS0, CS1, CS2, and CS3) using the SPI_CS_CTL register. Multiple CS lines can be driven
simultaneously for a broadcast access. There are also override fields to enable software driving of 0 or 1 on the active
CS line(s), which may be required for some special use cases. All other SPI pins are shared across by the slaves.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–3
SPI Operating Modes
SPI Operating Modes
The SPI supports the following features.
Wired-OR Mode (WOM)
To prevent contention when the SPI is used in multislave system, the data output pins, MOSI and MISO, can be
configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected.
The SPI_CTL.WOM bit in the control register controls the pad enable outputs for the data lines.
General Instructions
1. SPI module operates on PCLK. So, if PCLK is stopped, this block does not work.
2. Whenever SPI configuration needs to be changed, ensure that the CS is de-asserted. This avoids any abrupt
breaks in the SPI transfers. If the configuration changes while SPI transfer is actively going on, the behavior of
the peripheral is nondeterministic.
3. While changing configurations, program SPI_CNT register only after changing SPI_CTL and SPI_IEN
registers. Else, transfers may get started even before the configuration is changed.
Power-down Mode
In master mode, before entering power-down mode, the user should ensure that the transfers are completed by
checking the appropriate interrupts/status bits. The SPI block should then be disabled by clearing the
SPI_CTL.SPIEN bit. Only then, the power-down entry would be clean.
In slave mode, in either mode of operation (interrupt driven or DMA), the CS line level must be checked using the
SPI_STAT.CS bit to ensure that the SPI is not communicating. The SPI block must be disabled only when the
CS line is high.
While being powered down, the following fields are retained:
• All the bit fields of SPI_CTL register except SPI_CTL.SPIEN. During power-up, the SPI_CTL.SPIEN
bit is reset. This allows a fresh start of the peripheral at wake up.
• SPI_IEN.IRQMODE bit
• SPI_DIV.VALUE bit
• SPI_RD_CTL.THREEPIN bit
• SPI_FLOW_CTL.RDYPOL bit
All the other fields are not retained. They are reset on power-up. On exiting the power-down mode, the software
must reprogram all the non-retained registers as required. The SPI block must be re-enabled by setting the
SPI_CTL.SPIEN bit.
15–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Operating Modes
SPI2 vs SPI0/SPI1
From an SPI programming and users model perspective, SPI0, SPI1, and SPI2 are identical. The main difference
between SPI2 and SPI0/1 is the internal bus interface, which they are connected to. SPI2 is connected to a higher
performance Advanced Peripheral Bus (APB) which is always clocked at the higher system clock rate (HCLK) and
contains fewer modules requiring arbitration. Therefore, SPI2 is also know as SPIH (SPI High performance). SPI0
and SPI1 are connected to the main Advanced Peripheral Bus (APB) which selectively can be clocked at a lower rate
(PCLK) and whose latency is more uncertain due to a greater number of modules requiring arbitration. This means
that under higher data rates, SPI2 can move data more efficiently and with lower latency. SPI2 is recommended for
use with high data rate peripherals.
Interfacing with SPI Slaves
Though the SPI transfers are usually full-duplex, in many cases, the slave works on a protocol which consists of
Command, Address, and Data Read/Write. The write command is always unidirectional. However, the read command needs a transmit transfer followed by a receive transfer in a single CS frame. An example protocol is shown
below.
Figure 15-2: SPI Register Read
To support transfers like the above one, which resembles a half-duplex operation, SPI_RD_CTL.CMDEN bit must
be set. The number of bytes to be transmitted should be programmed in SPI_RD_CTL.TXBYTES field (which is
1 for the above example). The number of bytes to be received (after completing the transmit) would be specified by
the SPI_CNT.VALUE bits. In this case, SPI_CNT.VALUE must be 1.
The SPI_RD_CTL.OVERLAP bit specifices if the bytes received while transmitting the command and address
bytes must be stored or ignored. If this bit is set, the SPI_CNT.VALUE bit refers to the total number of bytes in
the entire frame. Some SPI read examples are given below.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–5
SPI Operating Modes
Read Command with TXBYTES = 1, CNT = 4, OVERLAP = 0
CSn
MOSI
X/Z
MISO
X
Tx0
Tx1
X
X/Z
X
Rx0
Rx1
Rx2
Rx3
X
SCLK
Read Command with TXBYTES = 1, CNT = 6, OVERLAP = 1
CSn
MOSI
X/Z
Tx0
Tx1
MISO
X
Rx0
Rx1
X/Z
X
Rx2
Rx3
Rx4
Rx5
X
SCLK
Figure 15-3: SPI Read Examples
Pseudo Code Example for Read Command Mode
SPI0_DIV = 0x0001
SPI0_CTL = 0x0883
//SPI serial clk frequency = ¼ of PCLK freq
//Enable SPI in master mode, ZEN=1,
//Continuous mode, TIM=0
SPI0_CNT = 0x0040
//64 bytes to be received
SPI0_DMA = 0x0005
//Enable DMA mode and Rx-DMA request
SPI0_RD_CTL = 0x000D //TXBYTES=3, CMDEN=1, Write 4 Tx bytes
//in two 16-bit writes (DMA mode)
SPI0_TX = 0xB6A5
SPI0_TX = 0xD8C7
read_data = SPI0_RX //Do a dummy read of the receive FIFO to
//initiate SPI transfers
In this case, only 4 bytes are transmitted as TXBYTES is 3. However, zeroes are sent on MOSI for the next 64 bytes
that are being received. In total, 4 bytes are transmitted and 64 bytes are received in a non-overlapping mode.
Flow Control
Several converters use a flow-control mechanism to match the required data/sample rate. The SPI master supports
the following types of flow-control:
• Using a 16-bit timer clocked at the serial clock rate to introduce wait-states while reading data. The master
waits until the timer ends and then reads SPI_FLOW_CTL.RDBURSTSZ+1 number of bytes. It goes back to
wait state and restarts the timer. This continues until SPI_CNT.VALUE number of bytes are received.
15–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Operating Modes
• Using a separate RDY pin which is connected through one of the GPIOs. The master waits until it sees an
active level in this pin. Once it detects the transition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number of
bytes and then goes back to wait state until another active level is detected. This continues until
SPI_CNT.VALUE number of bytes are received.
• Using the MISO pin. In this mode, the master waits for an active level on the MISO pin. Once it detects the
transition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number of bytes and then goes back to wait state until
another active level is detected. This continues until SPI_CNT.VALUE number of bytes are received.
In all the above cases, SPI_CNT.VALUE must be an integer multiple of SPI_FLOW_CTL.RDBURSTSZ+1.
Some example flow-controlled transfers are shown below.
Read Command with TXBYTES = 1, CNT = 3, RDBURSTSZ = 0, RDY_POL = 1 (using MISO pin)
CSn
MOSI
X/Z
MISO
x
Tx1
Tx0
X/Z
x
Rx1
Rx0
Rx3
X
SCLK
Read Command with CPHA = 1, CPOL = 0, TXBYTES = 0, CNT = 4, RDBURSTSZ = 1, WAIT_TMR = 10 (using Timer)
CSn
MOSI
X/Z
MISO
X
Tx0
X/Z
Rx0
X
Rx1
X
Rx2
Rx3
X
SCLK
<- 10 SCLK Cycles ->
<- 10 SCLK Cycles ->
Figure 15-4: Flow-controlled Transfer Examples
NOTE: While stalling the SCLK output for flow-control or FIFO data/space unavailability, the last SCLK edge is
always a sampling edge. This is to avoid a driving edge before the stall period. That way, the slave would have an
SCLK driving edge to proceed with, after the stall period.
Though the SCLK signal idles low for a SPI_CTL.CPOL =0 and idles high for a SPI_CTL.CPOL = 1, the
SPI_CTL.CPHA bit determines the sequence of sampling and driving edges. If SPI_CTL.CPHA = 1, the SCLK
signal is stalled at the same level as the idle level. If SPI_CTL.CPHA = 0, the SCLK is stalled at the opposite level
to the idle level. At the end of a transfer (when CS is deasserted), the SCLK is always idled as per SPI_CTL.CPOL.
The Flow Control table explains the same.
Table 15-1: Flow Control
CPHA
CPOL
SCLK Idle level
SCLK Stalled level
0
0
0
1
0
1
1
0
1
0
0
0
1
1
1
1
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–7
SPI Operating Modes
Read Command with CPHA = 0, CPOL = 0, TXBYTES = 0, CNT = 2, RDBURSTSZ = 0, WAIT_TMR = 10 (using Timer)
CSn
MOSI
X/Z
MISO
X
Tx0
X/Z
Rx0
X
Rx1
X
X
SCLK
(Inled LOW,
Stalled HIGH)
<- 10 SCLK Cycles ->
<- 10 SCLK Cycles ->
Figure 15-5: Sample Transfer
Three-Pin Mode
SPI can be used in a 3-pin mode where the data transmission/reception occurs over a single bi-directional line. The
SPI master supports this for read command mode, where the MOSI line is used for transmission of 'Command +
address' bytes and the same line is used for receiving the read data. To enable this, SPI_RD_CTL.THREEPIN and
SPI_RD_CTL.CMDEN fields of SPI_RD_CTL register should be set. Inherently, there is a half SCLK cycle between the last sampling edge of transmit phase and the first driving edge of receive phase. However, if the slave needs
a larger turn-around time, then it should enable timer based flow-control and program the
SPI_WAIT_TMR.VALUE as required. An example 3-pin SPI transfer is shown below.
Read Command with 3-pin SPI, TXBYTES = 0, CNT = 2. RDBURSTSZ = 0, WAIT_TMR = 1 (using Timer)
CSn
MOSI
X/Z
Rx1 (driven by Slave)
Rx0 (driven by Slave)
Tx0 (driven by Master)
X/Z
SCLK
1 SCLK
1 SCLK
Figure 15-6: 3-Pin SPI Transfer
SPI Data Transfer
In master mode, the transfer and interrupt mode bit (SPI_CTL.TIM) determines the manner in which an SPI
serial transfer is initiated. If the SPI_CTL.TIM bit is set, a serial transfer is initiated after a write to the transmit
FIFO occurs. If the SPI_CTL.TIM bit is cleared, a serial transfer is initiated after a read of the receive FIFO. The
read must be done while the SPI interface is idle. A read done during an active transfer will not initiate another
transfer.
For any setting of the master mode enable (SPI_CTL.MASEN) and SPI_CTL.TIM bits, the SPI simultaneously
receives and transmits data (if SPI_RD_CTL.CMDEN bit is 0). Therefore, during data transmission, the SPI is also
receiving data and filling up the receive FIFO. If the data is not read from the receive FIFO, the overflow interrupt
occurs once the FIFO starts to overflow. If the user does not want to read the receive data or receive overflow interrupts, the receive FIFO flush enable (SPI_CTL.RFLUSH) bit can be set, and the receive data will not be saved to
the receive FIFO. Else, if the user just wants to read the receive data (not concerned about the overflow condition),
this interrupt can be disabled by clearing the SPI_IEN.RXOVR bit. Similarly, when the user only wants to receive
15–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Data Transfer
data and does not want to write data to the transmit FIFO, the transmit FIFO flush enable (SPI_CTL.TFLUSH)
bit can be set to avoid getting underflow interrupts from the transmit FIFO. Alternatively, if the user wants to send
the FIFO data, but, does not want underflow interrupts, the SPI_IEN.TXUNDR bit must be cleared.
Transmit Initiated Transfer
For transfers initiated by a write to the transmit FIFO, the SPI transmits as soon as the first byte is written to the
FIFO. The SPI transfer of the first byte happens immediately.
If the continuous transfer enable bit (SPI_CTL.CON) is set, the transfer continues until it is complete. This completion is either the end of SPI_CNT.VALUE number of bytes (if SPI_CNT.VALUE > 0) or when no valid data
is available in the transmit FIFO (if SPI_CNT.VALUE = 0). Chip Select remains asserted for the duration of the
complete transfer. If SPI_CNT.FRAMECONT is cleared and SPI_CNT.VALUE > 0, the transfer stops when all
the SPI_CNT.VALUE bytes have been transferred. If the SPI_CNT.FRAMECONT is set, a new frame starts after
every SPI_CNT.VALUE number of bytes. Therefore, multiples of the SPI_CNT.VALUE bytes are transferred. If
there is no data/space in FIFO, the transfer stalls until it is available. Conversely, the transfer continues when there is
valid data in the FIFO.
If SPI_CTL.CON is cleared, each transfer consists of a single 8-bit serial transfer. If valid data exists in the transmit
FIFO, a new transfer is initiated after a stall period, where Chip Select is deasserted.
Receive Initiated Transfer
Transfers initiated by a read of the receive FIFO depend on the number of bytes to be received in the FIFO. If
SPI_IEN.IRQMODE is set to 7 and a read to the receive FIFO occurs, the SPI master initiates an 8-byte transfer.
If continuous mode is set (SPI_CTL.CON), the 8 bytes happen continuously with no deassertion of Chip Select
between bytes. If continuous mode is not set, the 8 bytes will happen with stall periods between transfers, where the
Chip Select is deasserted. However, in continuous mode, if SPI_CNT.VALUE > 0, CS is asserted for the entire
frame duration. SPI will introduce stall periods by not clocking SCL until FIFO space is available.
If SPI_IEN.IRQMODE is set to 6, then a read of the receive FIFO will initiate a 7-byte transfer similar to above. If
SPI_IEN.IRQMODE is set to 1, then a read of the receive FIFO will initiate a 2-byte transfer. Finally, a read of the
FIFO with SPI_IEN.IRQMODE set to 0 initiates a single byte transfer. A read of the receive FIFO while the SPI is
receiving data will not initiate another transfer after the present transfer is complete. In continuous mode, if
SPI_CNT.VALUE > 0 and SPI_CNT.FRAMECONT = 1, read of receive FIFO at the end of an SPI frame (to get
the last set of bytes received) will always initiate a new SPI frame. Therefore, to stop SPI transfers at any given frame,
SPI_CNT.FRAMECONT bit should be cleared before reading the final set of receive bytes.
Full-duplex transfer with CON = 0, CNT = 4
CSn
MOSI
X/Z
Tx0
X/Z
Tx1
X/Z
Tx2
X/Z
Tx3
X/Z
MISO
X
Rx0
X
Rx1
X
Rx2
X
Rx3
X
SCLK
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–9
SPI Data Transfer
Rx-only transfer with CON = 1, CNT = 6, FRAMECONT = 0
CSn
MOSI
X/Z
MISO
X
X
Rx0
Rx1
X/Z
Rx2
Rx3
Rx5
Rx4
X
SCLK
Tx-only transfer with CON = 1, CNT = 3, FRAMECONT = 1
CSn
MOSI
X/Z
MISO
X
Tx0
Tx1
Tx2
X/Z
Tx3
Tx4
Tx5
X
X/Z
X
SCLK
Figure 15-7: SPI Transfers
Transfers in Slave Mode
In slave mode, a transfer is initiated by the assertion of the Chip Select of the device.
Though the master can support upto four CS output lines, only one CS input, CS0, is used in slave mode.
The device as a slave transmits and receives 8-bit data until the transfer is concluded by the deassertion of Chip
Select.
The following SPI transfer protocol figures show the data transfer protocol for SPI and the effects of
SPI_CTL.CPHA and SPI_CTL.CPOL bits in the control register on that protocol, as indicated by T1, T2, and
T3 ( See Figures SPI Transfer Protocol CPHA = 0 and SPI Transfer Protocol CPHA = 1).
NOTE: Chip Select must not be tied to the ground.
15–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Data Transfer
Clock Cycle
Number
1
2
3
4
5
6
7
8
SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)
MISO
(From Slave)
XX
XX
msb
6
5
4
3
2
1
1sb
xx
msb
6
5
4
3
2
1
1sb
xx
CS
T1
T3
T2
Figure 15-8: SPI Transfer Protocol CPHA = 0
Clock Cycle
Number
1
2
3
4
5
6
7
8
SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)
MISO
(From Slave)
XX
XX
msb
6
5
4
3
2
1
1sb
xx
msb
6
5
4
3
2
1
1sb
xx
CS
T1
T2
T3
Figure 15-9: SPI Transfer Protocol CPHA = 1
SPI Data Underflow and Overflow
If the transmit zeroes underflow mode bit (SPI_CTL.ZEN) is cleared, the last stale byte is shifted out when a
transfer is initiated with no valid data in the FIFO. If SPI_CTL.ZEN is set, zeros are transmitted when a transfer is
initiated with no valid data in the FIFO.
If the receive overflow overwrite enable bit (SPI_CTL.RXOF) is set, the valid data in the receive FIFO is overwritten by the new serial byte received when there is no space left in the FIFO. If SPI_CTL.RXOF is cleared, the new
serial byte received is discarded when there is no space left in the FIFO.
When valid data is being overwritten in the receive FIFO, the oldest byte is overwritten first followed by the next
oldest byte and so on.
SPI Interrupts and Exceptions
There is one interrupt line per SPI and eleven sources of interrupts.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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SPI Interrupts and Exceptions
The SPI_STAT.IRQ bit reflects the state of the interrupt line.
The SPI_STAT[15:12] and SPI_STAT[7:1] bits reflect the state of the eleven sources.
The SPI generates either Transmit Interrupt Requests (TIRQ) or Receive Interrupt Request (RIRQ). Both interrupts
cannot be enabled at the same time. The appropriate interrupt is enabled using the SPI_CTL.TIM bit. If
SPI_CTL.TIM = 1, TIRQ is enabled. If SPI_CTL.TIM = 0, RIRQ is enabled.
All interrupts are sticky and are cleared only when the appropriate interrupt bits in SPI_STAT register are written
with a 1. The interrupt line from the device is cleared only after all the interrupt sources are cleared.
Transmit Interrupt
If the SPI_CTL.TIM bit is set, the transmit FIFO status causes the interrupt. The SPI_IEN.IRQMODE bit control when the interrupt occurs. When the SPI_IEN.IRQMODE bits are set to:
000: An interrupt is generated after each byte that is transmitted. The interrupt occurs when the byte is read from
the FIFO and written to the shift register.
001: An interrupt is generated after every two bytes that are transmitted.
...
110: An interrupt occurs after every seven bytes that are transmitted.
111: An interrupt occurs after every eight bytes that are transmitted.
The interrupts are generated depending on the number of bytes transmitted and not on the number of bytes in the
FIFO. This is different from the receive interrupt, which depends on the number of bytes in the receive FIFO and
not the number of bytes received.
The status of this interrupt can be read by reading the TXIRQ status bit. The interrupt is disabled if transmit FIFO
flush enable (TFLUSH) is high.
NOTE: Write to the SPI_CTL register resets the transmitted byte counter back to zero. For example, when the
SPI_IEN.IRQMODE bit is set to 0x3 and after three bytes have been transmitted, the SPI_CTL register is reinitialized, the transmit interrupt does not occur until another 4 bytes have been transmitted.
Receive Interrupt
If the SPI_CTL.TIM is cleared, the receive FIFO status causes the interrupt. Again, SPI_IEN.IRQMODE controls when the interrupt will occur. The status of this interrupt can be read by reading the SPI_STAT.RXIRQ
status bit.
Interrupts are only generated when data is written to the FIFO. For example, if SPI_IEN.IRQMODE is set to 0x0,
an interrupt is generated after the first byte is received. If the interrupt was cleared by writing 1 and the data byte
was not read from the receive FIFO, the interrupt will not be regenerated. Another interrupt will only be generated
when another byte is received into the FIFO.
15–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPI Interrupts and Exceptions
The interrupt depends on the number of valid bytes in FIFO when the SPI is receiving data. It does not depend on
the number of bytes received over the SPI.
The interrupt is disabled if SPI_CTL.RFLUSH is left high.
Underflow/Overflow Interrupts
When a transfer starts with no data in the transmit FIFO, the SPI_STAT.TXUNDR bit of the Status register gets
set to indicate an underflow condition. This will cause an interrupt if SPI_STAT.TXUNDR is set. This interrupt
will occur irrespective of what SPI_CTL.TIM bit is set to. This interrupt is disabled if SPI_CTL.TFLUSH bit is
set.
If data is received when the receive FIFO is already full, this will cause the SPI_STAT.RXOVR bit of the Status
register to go high indicating an overflow condition. This will cause an interrupt if SPI_IEN.RXOVR is set. This
interrupt occurs irrespective of the SPI_CTL.TIM bit setting. This interrupt is disabled if SPI_CTL.RFLUSH
bit is set.
The receive and transmit interrupts are cleared if the relevant flush bits are asserted or SPI is disabled. Else, the interrupts stay active even if the SPI is reconfigured.
SPI Programming Model
The following section provides the SPI DMA details.
SPI DMA
Two DMA channels are dedicated to SPI, transmit and receive. The two SPI DMA channels should be configured
in the DMA controller.
It is possible to enable DMA request on 1 or 2 channels at the same time, by setting the DMA request bits for
receive or transmit in the SPI_DMA register. If only the DMA transmit request (SPI_DMA.TXEN) is enabled, the
Rx FIFO overflows during the SPI transfer unless received data is read by user code, and an overflow interrupt is
generated. To avoid generating overflow interrupts, the Rx FIFO flush bit (SPI_CTL.RFLUSH) should be set, or
the SPI_IEN.RXOVR bit should be cleared, or the SPI interrupt be disabled in the NVIC of the core. If only the
DMA receive request (SPI_DMA.RXEN) is enabled, the Tx FIFO underflows. Again, to avoid underflow interrupt,
the SPI_IEN.TXUNDR bit must be cleared or the SPI interrupt must be disabled in the NVIC.
NOTE: Check the status of Tx FIFO. It should not be empty before issuing a dummy read so that unintended Tx
underflow interrupt is not observed.
The SPI Tx and Rx interrupts are not generated when DMA is used. SPI_IEN.IRQMODE is not used in transmit
mode and must be set to 3'b000 in receive mode.
The DMA bit (SPI_DMA.TXEN) controls the start of a DMA transfer. DMA requests are only generated when
SPI_DMA.EN = 1. At the end of a DMA transfer, that is, when receiving a DMA SPI transfer interrupt, this bit
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–13
SPI Programming Model
needs to be cleared to prevent extra DMA requests to the µDMA controller. The data still present in the Tx FIFO is
transmitted if in Tx mode.
All DMA data transfers are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16
bytes of data are to be transferred over the SPI, the DMA should be programmed to perform eight half-word (16bit) transfers. If 17 bytes are to be transferred, nine half-word transfers are required, the additional byte is discarded.
Data errors occur if the DMA transfers are programmed as byte-wide transfers.
In DMA mode, the Tx/Rx FIFOs are 2 bytes wide. Bits[7:0] are first accessed by the SPI followed by the bits[15:8].
This is irrespective of count or SPI_CTL.LSB settings. For example, if SPI_CNT.VALUE = 3, the order of
transmission/reception is as follows (Byte-3 is ignored).
Byte-1
Byte-0
Byte-3
Byte-2
NOTE: The SPI_CTL.LSB bit does not affect the FIFO access order in the DMA mode. It only affects how each
byte is transferred over SPI.
DMA Master Transmit Configuration
The DMA SPI Tx channel must be configured. The NVIC must be configured to enable DMA Tx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
SPI_CTL = 0x1043;
//enables SPI in master mode and transmit mode, Rx FIFO
//flush enabled.
SPI_CNT.VALUE = NUM_BYTES_TO transfer; //sets the number of bytes to transfer.
SPI_DMA = 0x1;
//(optional) enables FIFO to accept 16-bit
//core data writes.
SPI_TX = 0xXXXX;
//(optional) up to four 16-bit core writes can be performed
//to preload FIFO.
SPI_DMA = 0x3;
//enable DMA mode, enable Tx DMA request.
All DMA transfers are expected to be 16-bit transfers. When all data present in the DMA buffer are transmitted, the
DMA generates an interrupt. User code should disable DMA request. Data will still be in the Tx FIFO as the DMA
request is generated each time there is free space in the Tx FIFO, to keep the FIFO always full.
DMA Master Receive Configuration
The SPI_CNT register sets the number of receive bytes required by the SPI master. When the required number of
bytes has been received, no more transfers are initiated. To initiate a DMA master receive transfer, a dummy read
should be done by user code. This dummy read must not be added to the SPI_CNT number.
The counter counting the bytes as they are received is reset when SPI is disabled using the SPI_CTL.SPIEN bit in
SPI_CTL, or if the SPI_CNT register is modified by user code.
15–14
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
To perform SPI DMA master receive:
The DMA SPI Rx channel must be configured. The NVIC of the core must be configured to enable DMA Rx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
SPI_CTL = 0x2003;
//enable SPI in master mode and
//receive mode, 1 byte transfer.
SPI_DMA = 0x5;
//enable DMA mode, enable Rx DMA request.
SPI_CNT.VALUE = XXX;
//number of bytes to be received.
A = SPI_RX;
//dummy read.
The DMA transfer stops when the appropriate number of clock cycles has been generated. All DMA data transfers
are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be
received over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be received, nine 16-bit transfers are required. The additional byte is padded for the final DMA transfer. Data errors occur if the DMA transfers are programmed as byte wide transfers.
NOTE: DMA buffer must be of the same size as SPI_CNT.VALUE (or same size plus one if SPI_CNT.VALUE is
odd) to generate a DMA interrupt when the transfer is complete.
ADuCM4050 SPI Register Descriptions
Serial Peripheral Interface (SPI) contains the following registers.
Table 15-2: ADuCM4050 SPI Register List
Name
Description
SPI_CNT
Transfer Byte Count
SPI_CS_CTL
Chip Select Control for Multi-slave Connections
SPI_CS_OVERRIDE
Chip Select Override
SPI_CTL
SPI Configuration
SPI_DIV
SPI Baud Rate Selection
SPI_DMA
SPI DMA Enable
SPI_FIFO_STAT
FIFO Status
SPI_FLOW_CTL
Flow Control
SPI_IEN
SPI Interrupts Enable
SPI_RD_CTL
Read Control
SPI_RX
Receive
SPI_STAT
Status
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–15
ADuCM4050 SPI Register Descriptions
Table 15-2: ADuCM4050 SPI Register List (Continued)
Name
Description
SPI_TX
Transmit
SPI_WAIT_TMR
Wait Timer for Flow Control
15–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Transfer Byte Count
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FRAMECONT (R/W)
Continue Frame
VALUE (R/W)
Transfer Byte Count
Figure 15-10: SPI_CNT Register Diagram
Table 15-3: SPI_CNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 FRAMECONT
(R/W)
Continue Frame.
This bit should be used in conjunction with SPI_CTL.CON and SPI_CNT.VALUE
fields. It is used to control SPI data framing. If this bit is cleared, the SPI master transfers only one frame of SPI_CNT.VALUE bytes. If set, the SPI master will transfer
data in frames of SPI_CNT.VALUE bytes each.
Note: If SPI_CNT.VALUE = 0, this field has no effect as the SPI master will continue with transfers as long as Tx/Rx FIFO is ready. If SPI_CTL.CON = 0, this field has
no effect as all SPI frames are single byte wide irrespective of other control fields.
0 If SPI_CNT.VALUE > 0, stop SPI transfers after
SPI_CNT.VALUE number of bytes.
1 Continue SPI transfers as long as Tx/Rx FIFO is ready.
13:0 VALUE
(R/W)
Transfer Byte Count.
This field specifies the number of bytes to be transferred. It is used in both receive and
transmit transfer types. This value assures that a master mode transfer terminates at the
proper time and that 16-bit SPI_DMA transfers are byte padded or discarded as required to match odd transfer counts.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–17
ADuCM4050 SPI Register Descriptions
Chip Select Control for Multi-slave Connections
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
SEL (R/W)
Chip Select Control
Figure 15-11: SPI_CS_CTL Register Diagram
Table 15-4: SPI_CS_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 SEL
(R/W)
Chip Select Control.
This field specifies the CS line to be used for the current SPI transfer. It is useful in a
multi-slave setup where only the CS lines are unique across the various slaves. The SPI
master can support up to 4 different CS lines. By default, CS0 is used if none of the
bits are set.
Note: If multiple bits are set, the respective CS lines are active simultaneously.
15–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Chip Select Override
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CTL (R/W)
CS Override Control
Figure 15-12: SPI_CS_OVERRIDE Register Diagram
Table 15-5: SPI_CS_OVERRIDE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 CTL
(R/W)
CS Override Control.
This bit overrides the actual CS output from the master state machine. It may be needed for special SPI transfers. Note: Use it with precaution.
0 CS is not forced.
1 CS is forced to drive 1'b1.
2 CS is forced to drive 1'b0.
3 CS is not forced.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–19
ADuCM4050 SPI Register Descriptions
SPI Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CSRST (R/W)
Reset Mode for CS Error Bit
SPIEN (R/W)
SPI Enable
TFLUSH (R/W)
SPI Tx FIFO Flush Enable
MASEN (R/W)
Master Mode Enable
RFLUSH (R/W)
SPI Rx FIFO Flush Enable
CPHA (R/W)
Serial Clock Phase Mode
CON (R/W)
Continuous Transfer Enable
CPOL (R/W)
Serial Clock Polarity
LOOPBACK (R/W)
Loopback Enable
WOM (R/W)
SPI Wired-OR Mode
OEN (R/W)
Slave MISO Output Enable
LSB (R/W)
LSB First Transfer Enable
RXOF (R/W)
Rx Overflow Overwrite Enable
TIM (R/W)
SPI Transfer and Interrupt Mode
ZEN (R/W)
Transmit Zeros Enable
Figure 15-13: SPI_CTL Register Diagram
Table 15-6: SPI_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 CSRST
(R/W)
13 TFLUSH
(R/W)
Reset Mode for CS Error Bit.
If this bit is set, the bit counter will be reset after a CS error condition and the Cortex
is expected to clear the SPI_CTL.SPIEN. If this bit is clear, the bit counter will continue from where it stopped. SPI can receive the remaining bits when CS gets asserted
and Cortex has to ignore the SPI_STAT.CSERR interrupt. However, it is recommended to set this bit for recovery after a CS error.
SPI Tx FIFO Flush Enable.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is left high, then either the last transmitted value or
0x00 is transmitted depending on the SPI_CTL.ZEN bit. Any writes to the Tx
FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
15–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Table 15-6: SPI_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 RFLUSH
(R/W)
SPI Rx FIFO Flush Enable.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is set all incoming data is ignored and no interrupts
are generated. If set and SPI_CTL.TIM = 0, a read of the Rx FIFO will initiate a
transfer.
Clear this bit to disable Rx FIFO flushing.
11 CON
(R/W)
Continuous Transfer Enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until
no valid data is available in the SPI_TX register (SPI_CTL.TIM=1) or until the Rx
FIFO is full (SPI_CTL.TIM=0). CS is asserted and remains asserted for the duration
of each 8-bit serial transfer until Tx FIFO is empty or Rx FIFO is full.
Cleared by user to disable continuous transfer. Each SPI frame then consists of a single
8-bit serial transfer. If valid data exists in the SPI_TX register (SPI_CTL.TIM=1) or
Rx FIFO is not full (SPI_CTL.TIM=0), a new transfer is initiated after a stall period
of 1 serial clock cycle.
10 LOOPBACK
(R/W)
9 OEN
(R/W)
8 RXOF
(R/W)
7 ZEN
(R/W)
6 TIM
(R/W)
Loopback Enable.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave MISO Output Enable.
Set this bit for MISO to operate as normal. Clear this bit to disable the output driver
on the MISO pin. The MISO pin will be Open-Circuit when this bit is clear.
Rx Overflow Overwrite Enable.
Set by user, the valid data in the SPI_RX register is overwritten by the new serial byte
received. Cleared by user, the new serial byte received is discarded.
Transmit Zeros Enable.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit
to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI Transfer and Interrupt Mode.
Set by user to initiate transfer with a write to the SPI_TX register. Interrupt only occurs when SPI_IEN.IRQMODE+1 number of bytes have been transmitted.
Cleared by user to initiate transfer with a read of the SPI_RX register. Interrupt only
occurs when Rx-FIFO has SPI_IEN.IRQMODE+1 number of bytes or more.
5 LSB
(R/W)
LSB First Transfer Enable.
0 MSB transmitted first
1 LSB transmitted first
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–21
ADuCM4050 SPI Register Descriptions
Table 15-6: SPI_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 WOM
SPI Wired-OR Mode.
(R/W)
0 Normal output levels
1 Enables open circuit data output enable. External pullups required on data out pins
3 CPOL
Serial Clock Polarity.
(R/W)
0 Serial clock idles low
1 Serial clock idles high
2 CPHA
Serial Clock Phase Mode.
(R/W)
0 Serial clock pulses at the end of each serial bit transfer
1 Serial clock pulses at the beginning of each serial bit
transfer
1 MASEN
(R/W)
Master Mode Enable.
Note: Clearing this bit issues a synchronous reset to the design and most status bits,
while other MMRs are unaffected.
0 Enable slave mode
1 Enable master mode
0 SPIEN
(R/W)
SPI Enable.
0 Disable the SPI
1 Enable the SPI
15–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
SPI Baud Rate Selection
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
SPI Clock Divider
Figure 15-14: SPI_DIV Register Diagram
Table 15-7: SPI_DIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:0 VALUE
(R/W)
SPI Clock Divider.
SPI_DIV.VALUE is the factor used to divide PCLK to generate the serial clock.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–23
ADuCM4050 SPI Register Descriptions
SPI DMA Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RXEN (R/W)
Enable Receive DMA Request
EN (R/W)
Enable DMA for Data Transfer
TXEN (R/W)
Enable Transmit DMA Request
Figure 15-15: SPI_DMA Register Diagram
Table 15-8: SPI_DMA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RXEN
(R/W)
1 TXEN
(R/W)
Enable Receive DMA Request.
If this bit is set when DMA is enabled, then a Rx DMA request is raised as long there
is valid data in Rx FIFO.
Enable Transmit DMA Request.
If this bit is set and DMA is enabled, a Tx DMA request is raised as long there is space
in Tx FIFO.
Note: This bit needs to be cleared as soon as a Tx DMA DONE interrupt is received
to prevent extra Tx DMA requests to the DMA controller.
0 EN
(R/W)
15–24
Enable DMA for Data Transfer.
Set by user code to start a DMA transfer.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
FIFO Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RX (R)
SPI Rx FIFO Status
TX (R)
SPI Tx FIFO Status
Figure 15-16: SPI_FIFO_STAT Register Diagram
Table 15-9: SPI_FIFO_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 RX
(R/NW)
SPI Rx FIFO Status.
This field specifies the number of bytes in Rx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Rx FIFO.
0 Rx FIFO empty
1 1 valid byte/half-word in Rx FIFO
2 2 valid bytes/half-words in Rx FIFO
3 3 valid bytes/half-words in Rx FIFO
4 4 valid bytes/half-words in Rx FIFO
5 5 valid bytes/half-words in Rx FIFO
6 6 valid bytes/half-words in Rx FIFO
7 7 valid bytes/half-words in Rx FIFO
8 8 valid bytes/half-words in Rx FIFO (Rx FIFO full)
3:0 TX
(R/NW)
SPI Tx FIFO Status.
This field specifies the number of bytes in Tx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Tx FIFO.
0 Tx FIFO empty
1 1 valid byte/half-word in Tx FIFO
2 2 valid bytes/half-words in Tx FIFO
3 3 valid bytes/half-words in Tx FIFO
4 4 valid bytes/half-words in Tx FIFO
5 5 valid bytes/half-words in Tx FIFO
6 6 valid bytes/half-words in Tx FIFO
7 7 valid bytes/half-words in Tx FIFO
8 8 valid bytes/half-words in Tx FIFO (Tx FIFO full)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–25
ADuCM4050 SPI Register Descriptions
Flow Control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDBURSTSZ (R/W)
Read Data Burst Size - 1
MODE (R/W)
Flow Control Mode
RDYPOL (R/W)
Polarity of RDY/MISO Line
Figure 15-17: SPI_FLOW_CTL Register Diagram
Table 15-10: SPI_FLOW_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:6 RDBURSTSZ
(R/W)
Read Data Burst Size - 1.
Specifies number of bytes to be received - 1 in a single burst from a slave before waiting for flow-control.
This is not valid if SPI_FLOW_CTL.MODE is 2'b00. For all other values of
SPI_FLOW_CTL.MODE, this field is valid. It takes values from 0 to 1023 implying a
read burst of 1 to 1024 bytes respectively.
Note: This mode is useful for reading fixed-width conversion results periodically.
4 RDYPOL
(R/W)
Polarity of RDY/MISO Line.
Specifies the polarity of the RDY/MISO pin, which indicates that the slave's read data
is ready.
If SPI_FLOW_CTL.MODE= 2'b10, it refers to the polarity of RDY pin.
If SPI_FLOW_CTL.MODE=2'b11, it refers to the polarity of MISO (DOUT) line.
For all other values of SPI_FLOW_CTL.MODE, this bit is ignored.
0 Polarity is active high. SPI master waits until RDY/
MISO becomes high.
1 Polarity is active low. SPI master waits until RDY/
MISO becomes low.
15–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Table 15-10: SPI_FLOW_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 MODE
(R/W)
Flow Control Mode.
Flow control configuration for data reads.
Note: When RDY signal is used for flow-control, it could be any signal which is tied to
this RDY input of SPI module. For example, it can be an off-chip input, on-chip timer
output, or any other control signal.
0 Flow control is disabled.
1 Flow control is based on timer (WAIT_TMR).
2 Flow control is based on RDY signal.
3 Flow control is based on MISO pin.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–27
ADuCM4050 SPI Register Descriptions
SPI Interrupts Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TXEMPTY (R/W)
Tx FIFO Empty Interrupt Enable
IRQMODE (R/W)
SPI IRQ Mode Bits
XFRDONE (R/W)
SPI Transfer Completion Interrupt Enable
CS (R/W)
Enable Interrupt on Every CS Edge
in Slave CON Mode
TXDONE (R/W)
SPI Transmit Done Interrupt Enable
TXUNDR (R/W)
Tx Underflow Interrupt Enable
RDY (R/W)
Ready Signal Edge Interrupt Enable
RXOVR (R/W)
Rx Overflow Interrupt Enable
Figure 15-18: SPI_IEN Register Diagram
Table 15-11: SPI_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 TXEMPTY
(R/W)
Tx FIFO Empty Interrupt Enable.
This bit enables the SPI_STAT.TXEMPTY interrupt whenever Tx FIFO gets emptied.
0 TXEMPTY interrupt is disabled.
1 TXEMPTY interrupt is enabled.
13 XFRDONE
(R/W)
SPI Transfer Completion Interrupt Enable.
This bit enables the SPI_STAT.XFRDONE interrupt.
0 XFRDONE interrupt is disabled.
1 XFRDONE interrupt is enabled.
12 TXDONE
(R/W)
SPI Transmit Done Interrupt Enable.
This bit enables the SPI_STAT.TXDONE interrupt in read command mode.
Note: This can be used to signal the change of SPI transfer direction in read command
mode.
0 TXDONE interrupt is disabled.
1 TXDONE interrupt is enabled.
15–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Table 15-11: SPI_IEN Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 RDY
(R/W)
Ready Signal Edge Interrupt Enable.
Enables the SPI_STAT.RDY interrupt whenever an active edge occurs on RDY/
MISO signals.
If SPI_FLOW_CTL.MODE = 2'b10, edge detection happens on RDY signal.
If SPI_FLOW_CTL.MODE = 2'b11, MISO signal is used instead of RDY.
For all other values of SPI_FLOW_CTL.MODE, this bit has no effect.
The active edge (rising/falling) is determined by the SPI_FLOW_CTL.RDYPOL bit.
0 RDY signal edge interrupt is disabled.
1 RDY signal edge interrupt is enabled.
10 RXOVR
Rx Overflow Interrupt Enable.
(R/W)
0 Rx overflow interrupt is disabled.
1 Rx overflow interrupt is enabled.
9 TXUNDR
Tx Underflow Interrupt Enable.
(R/W)
0 Tx underflow interrupt is disabled.
1 Tx underflow interrupt is enabled.
8 CS
(R/W)
Enable Interrupt on Every CS Edge in Slave CON Mode.
If this bit is set and the SPI module is configured as a slave in continuous mode, any
edge on CS will generate an interrupt and the corresponding status bits
(SPI_STAT.CSRISE, SPI_STAT.CSFALL) will be asserted.
If this bit is not set, then no interrupt will be generated and the status bits will not be
asserted.
This bit has no effect if the SPI is not in continuous mode or if it is a master.
2:0 IRQMODE
(R/W)
SPI IRQ Mode Bits.
These bits configure when the Tx/Rx interrupts occur in a transfer. For DMA Rx
transfer, these bits must be 3'b000.
0 Tx interrupt occurs when 1 byte has been transferred.
Rx interrupt occurs when 1 or more bytes have been received into the FIFO.
1 Tx interrupt occurs when 2 bytes have been transferred.
Rx interrupt occurs when 2 or more bytes have been received into the FIFO.
2 Tx interrupt occurs when 3 bytes have been transferred.
Rx interrupt occurs when 3 or more bytes have been received into the FIFO.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–29
ADuCM4050 SPI Register Descriptions
Table 15-11: SPI_IEN Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 Tx interrupt occurs when 4 bytes have been transferred.
Rx interrupt occurs when 4 or more bytes have been received into the FIFO.
4 Tx interrupt occurs when 5 bytes have been transferred.
Rx interrupt occurs when 5 or more bytes have been received into the FIFO.
5 Tx interrupt occurs when 6 bytes have been transferred.
Rx interrupt occurs when 6 or more bytes have been received into the FIFO.
6 Tx interrupt occurs when 7 bytes have been transferred.
Rx interrupt occurs when 7 or more bytes have been received into the FIFO.
7 Tx interrupt occurs when 8 bytes have been transferred.
Rx interrupt occurs when the FIFO is full.
15–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Read Control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
THREEPIN (R/W)
Three Pin SPI Mode
CMDEN (R/W)
Read Command Enable
TXBYTES (R/W)
Transmit Byte Count - 1 (Read Command)
OVERLAP (R/W)
Tx/Rx Overlap Mode
Figure 15-19: SPI_RD_CTL Register Diagram
Table 15-12: SPI_RD_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 THREEPIN
(R/W)
Three Pin SPI Mode.
Specifies if the SPI interface has a bidirectional data pin (3-pin interface) or dedicated
unidirectional data pins for Tx and Rx (4-pin interface). This is only valid in Readcommand mode and when SPI_FLOW_CTL.MODE = 2'b01.
If 3-pin mode is selected, MOSI pin will be driven by master during transmit phase
and after a wait time of SPI_WAIT_TMR SCLK cycles, the slave is expected to drive
the same MOSI pin.
Note: SPI_FLOW_CTL.MODE should be programmed to 2'b01 to introduce wait
states for allowing turnaround time. Else, the slave only has a turn-around time of half
SCLK period (between sampling and driving edges of SCLK). If this mode is used, set
SPI_RD_CTL.OVERLAP = 0.
0 SPI is a 4-pin interface.
1 SPI is a 3-pin interface.
5:2 TXBYTES
(R/W)
Transmit Byte Count - 1 (Read Command).
Specifies the number of bytes to be transmitted - 1 before reading data from a slave.
This field can take values from 0 to 15 corresponding to 1 to 16 Tx bytes . This includes all the bytes that need to be sent out to the slave viz., command and address (if
required). The design does not differentiate between these two. It just transmits the
specified number of bytes from the Tx FIFO.
Note: If there is a latency between the command transmission and data reception, then
the number of Tx bytes (mostly 0's) to be padded for that delay should also be accounted for in this count.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–31
ADuCM4050 SPI Register Descriptions
Table 15-12: SPI_RD_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 OVERLAP
(R/W)
Tx/Rx Overlap Mode.
This bit specifies if the start of Tx and Rx overlap. In most of the slaves, the read data
starts only after the master completes the transmission of 'command+address'. This is a
non-overlapping transfer. In some slaves, there might be status bytes sent out while the
command is being received. So, user may need to start receiving the bytes from the
beginning of the CS frame. This is overlapping mode.
Note: In case of overlapping mode, SPI_CNT.VALUE refers to the total number of
bytes to be received. So, the extra status bytes (which are in addition to the actual read
bytes) should be accounted for while programming SPI_CNT.VALUE.
0 Tx/Rx overlap is disabled.
1 Tx/Rx overlap is enabled.
0 CMDEN
(R/W)
Read Command Enable.
SPI read command mode where a command + address is transmitted and read data is
expected in the same CS frame. If this bit is cleared, all other fields of SPI_RD_CTL,
SPI_FLOW_CTL and SPI_WAIT_TMR registers do not have any effect.
0 Read command mode is disabled.
1 Read command mode is enabled.
15–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Receive
This register allows access to the 8-deep receive FIFO.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BYTE2 (R)
8-bit Receive Buffer, Used Only in DMA
Modes
BYTE1 (R)
8-bit Receive Buffer
Figure 15-20: SPI_RX Register Diagram
Table 15-13: SPI_RX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 BYTE2
(R/NW)
7:0 BYTE1
8-bit Receive Buffer, Used Only in DMA Modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access. They return zeros if SPI_DMA is disabled.
8-bit Receive Buffer.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–33
ADuCM4050 SPI Register Descriptions
Status
15 14 13 12 11 10 9
0
RDY (R/W1C)
Detected an Edge on Ready Indicator
for Flow Control
CSFALL (R/W1C)
Detected a Falling Edge on CS, in Slave
CON Mode
CSRISE (R/W1C)
Detected a Rising Edge on CS, in Slave
CON Mode
CSERR (R/W1C)
Detected a CS Error Condition in Slave
Mode
CS (R)
CS Status
0
0
0
1
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IRQ (R)
SPI Interrupt Status
XFRDONE (R)
SPI Transfer Completion
TXEMPTY (R/W1C)
SPI Tx FIFO Empty Interrupt
TXDONE (R/W1C)
SPI Tx Done in Read Command Mode
TXUNDR (R/W1C)
SPI Tx FIFO Underflow
TXIRQ (R/W1C)
SPI Tx IRQ
RXOVR (R/W1C)
SPI Rx FIFO Overflow
RXIRQ (R/W1C)
SPI Rx IRQ
Figure 15-21: SPI_STAT Register Diagram
Table 15-14: SPI_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RDY
(R/W1C)
Detected an Edge on Ready Indicator for Flow Control.
This bit indicates that there was an active edge on the RDY/MISO line depending on
the flow control mode. If SPI_FLOW_CTL.MODE = 2'b10, this bit is set whenever
an active edge is detected on RDY signal.
If SPI_FLOW_CTL.MODE = 2'b11, this bit is set if an active edge is detected on MISO signal.
For all other values of MODE, this bit is always 0.
The active edge (rising/falling) is determined by the SPI_FLOW_CTL.RDYPOL.
When SPI_IEN.RDY is set, this bit will cause an interrupt, and it is cleared only
when 1 is written to this bit.
Note: This can be used for staggered flow-control on transmit side, along with a CS
override if required.
15–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Table 15-14: SPI_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
14 CSFALL
(R/W1C)
Detected a Falling Edge on CS, in Slave CON Mode.
This bit indicates that there was a falling edge in CS line, when the device was a slave
in continuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt.
It is cleared when 1 is written to this bit or when SPI_CTL.SPIEN is cleared.
This can be used to identify the start of an SPI data frame.
13 CSRISE
(R/W1C)
Detected a Rising Edge on CS, in Slave CON Mode.
This bit indicates that there was a rising edge in CS line, when the device was a slave in
continuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt. It
is cleared when 1 is written to this bit or when SPI_CTL.SPIEN is cleared.
This can be used to identify the end of an SPI data frame.
12 CSERR
(R/W1C)
Detected a CS Error Condition in Slave Mode.
This bit indicates that the CS line was de-asserted abruptly by an external master, even
before the full-byte of data was transmitted completely.
This bit will cause an interrupt. It is cleared when 1 is written to this bit or when
SPI_CTL.SPIEN is cleared.
11 CS
(R/NW)
CS Status.
This bit reflects the actual CS status as seen by the SPI module.
Note: This uses SCLK-PCLK synchronization. So, there would be a slight delay when
CS changes state.
0 CS line is low.
1 CS line is high.
7 RXOVR
(R/W1C)
SPI Rx FIFO Overflow.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This
bit generates an interrupt if SPI_IEN.RXOVR is set, except when
SPI_CTL.RFLUSH is set.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.
6 RXIRQ
(R/W1C)
SPI Rx IRQ.
Set when a receive interrupt occurs. Not available in DMA mode. This bit is set when
SPI_CTL.TIM is cleared and the required number of bytes have been received.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.
5 TXIRQ
(R/W1C)
SPI Tx IRQ.
SPI Tx IRQ Status Bit. Not available in DMA mode.
Set when a transmit interrupt occurs. This bit is set when SPI_CTL.TIM is set and
the required number of bytes have been transmitted.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–35
ADuCM4050 SPI Register Descriptions
Table 15-14: SPI_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 TXUNDR
(R/W1C)
SPI Tx FIFO Underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This
bit generates an interrupt if SPI_IEN.TXUNDR is set, except when
SPI_CTL.TFLUSH is set.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.
3 TXDONE
(R/W1C)
SPI Tx Done in Read Command Mode.
This bit is set when the entire transmit is completed in a read command. This bit generates an interrupt if SPI_IEN.TXDONE is set.
This bit is valid only if SPI_RD_CTL.CMDEN is set. It is cleared only when 1 is written to this bit.
2 TXEMPTY
(R/W1C)
SPI Tx FIFO Empty Interrupt.
This bit is set when the Tx-FIFO is empty and SPI_IEN.TXEMPTY is set, except
when SPI_CTL.TFLUSH is set. This bit generates an interrupt.
It is cleared when 1 is written to this bit or SPI_CTL.SPIEN is cleared.
1 XFRDONE
(R/NW)
SPI Transfer Completion.
This bit indicates the status of SPI transfer completion in master mode. It is set when
the transfer of SPI_CNT.VALUE number of bytes have been finished. In slave mode
or if SPI_CNT.VALUE = 0, this bit is invalid.
If SPI_IEN.XFRDONE is set, this bit generates an interrupt. It uses the state of the
master state machine to determine the completion of a SPI transfer. Therefore, a CS
override does not affect this bit. It is cleared only when 1 is written to this bit.
0 IRQ
(R/NW)
15–36
SPI Interrupt Status.
Set to 1 when an SPI based interrupt occurs. Cleared when all the interrupt sources are
cleared.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPI Register Descriptions
Transmit
This register allows access to the 8-deep transmit FIFO.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BYTE2 (W)
8-bit Transmit Buffer, Used Only in
DMA Modes
BYTE1 (W)
8-bit Transmit Buffer
Figure 15-22: SPI_TX Register Diagram
Table 15-15: SPI_TX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 BYTE2
(RX/W)
7:0 BYTE1
8-bit Transmit Buffer, Used Only in DMA Modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access.
8-bit Transmit Buffer.
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
15–37
ADuCM4050 SPI Register Descriptions
Wait Timer for Flow Control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Wait Timer
Figure 15-23: SPI_WAIT_TMR Register Diagram
Table 15-16: SPI_WAIT_TMR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Wait Timer.
This field specifies the number of SCLK cycles to wait before continuing the SPI read.
This field can take values of 0 to 65535.
This field is only valid if SPI_FLOW_CTL.MODE = 2'b01.
For all other values of SPI_FLOW_CTL.MODE, this field is ignored.
A value of 0 implies a wait time of 1 SCLK cycle.
15–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Serial Port (SPORT)
16 Serial Port (SPORT)
The ADuCM4050 MCU has a serial port (SPORT) that support a variety of serial data communication protocols.
In addition, the SPORT provides a glueless hardware interface to several industry-standard data converters, codecs
and other processors, including DSPs. The SPORT top module comprises of two half SPORTs (HSPORT) with
identical functionality SPORT_A and SPORT_B. Each half SPORT can be independently configured as either a
transmitter or receiver and can be coupled with the other HSPORT within the same SPORT. Each half SPORT has
the same capabilities and is programmed in the same way.
SPORT Features
Each HSPORT supports the following features:
• One bidirectional data line, configurable as either transmitter or receiver. Further, two half SPORT can be
combined to enable full-duplex operation.
• Operation mode:
• Standard DSP serial mode
• Timer-enabled mode
• Serial data words between 4 and 32 bits in length.
• Improved granularity for internal clock generation, allowing even PCLK to SPT_CLK ratios. The SPORTs can
also accept an input clock from an external source.
• Configurable rising or falling edge of the SPT_CLK for driving or sampling data and frame sync.
• Gated clock mode support for internal clock mode.
• Frame Sync options:
• Unframed mode
• Internal/external frame sync options
• Programmable polarity
• Early/Late Frame Sync
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–1
Signal Description
• External frame sync signal configured as level-sensitive signal.
• Status flagging and optional interrupt generation for prematurely received external frame syncs and transmit
underflow (or receive overflow).
• Optional 16-bit to 32-bit word or 8-bit to 32-bit packing when SPORT is configured as receiver and 32-bit to
16-bit or 32-bit to 8-bit word unpacking when configured as Transmitter.
• Interrupt driven transfer support.
• Interrupt control.
• Transfer Finish Interrupt (TFI): An interrupt is generated when the last bit of programmed number of transfers
is transmitted out.
• Programmable bit order - MSB/LSB first.
• Programmable transfer count of 1-4095 words.
• Dedicated DMA channel for each half SPORT.
• Ability to route and share the clocks and/or frame sync between the SPORT halves of the SPORT module.
• SPT_CNV signal generation in timer-enable mode.
• One DMA channel per half SPORT.
• Each half SPORT has its own set of control registers and data buffers.
• Core can also access the data buffers.
Signal Description
Each half SPORT module has four dedicated pins, as described in the following table.
Table 16-1: SPORT Pin Descriptions
Internal Node
Direction
Description
SPT_CLK
I/O
Transmit/Receive Serial Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated.
SPT_FS
I/O
Transmit/Receive Frame Sync. The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally.
SPT_D0
I/O
Transmit/receive Data channel. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data.
SPT_CNV
Output
This is an additional control signal used only in the case of Timer enable mode for
peripherals which require two signals for control information.
• The clock and frame sync signals can be interconnected between the half SPORT pair.
• The SPT_CNV signal is used only in the timer enable mode (see Timer-Enable Mode).
16–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Functional Description
SPORT Functional Description
The following section provides general information about functionality of the serial ports of MCU.
SPORT Block Diagram
The figure shows the top-level block diagram of the SPORT.
It shows the interfacing with the APB and DMA channel. It also shows the connection with the peripheral.
CORE IRQ
SPT_CNV A
SPT_FS A
HALF SPORT A
SPT_CLK A
DMA Signals
SPT_D0 A
APB Bus
SPT_CNV B
SPT_FS B
HALF SPORT B
SPT_CLK B
DMA Signals
SPT_D0 B
CORE IRQ
Figure 16-1: Top-level Block Diagram of SPORT
The following figure shows the block diagram of a half SPORT.
Core IRQ
SPT_FS
MMR
Regis
ters
32
SPORT
transmit block
SPORT
receive block
32
TX FIFO
Control
information
DMA signals
SPT_CLK
SPT_CNV
RX FIFO
APB signals
Control block
TX data
SPT_D0
RX
data
Figure 16-2: Half SPORT Block Diagram
Each SPORT module consists of two separate blocks, known as half SPORT (HSPORT) A and B, with identical
functionality. These blocks can be independently configured as transmitter or receiver, as shown in the top-level
block diagram.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–3
SPORT Functional Description
Each HSPORT has its own set of control registers and data buffers. The Two HSPORTs must be combined to achieve full-duplex operation.
SPORT Transfer
The SPORT is configured in transmit mode, if SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control
bit is set. If this bit is cleared, serial port is configured in receive mode. Once a path is activated, data is shifted in
response to a frame sync at the rate of serial clock. Receive data buffers are inactive when SPORT is operating in
transmit mode and transmit data buffers when in receive mode. Inactive data buffers are not used and should not be
accessed. An application program must use the appropriate data buffers.
Transmit Path
The SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control bit, when set, configures the SPORT in
transmit mode.
The SPORT_TX_A and SPORT_TX_B registers are used as the transmit data buffer (which is a three deep FIFO).
The data to be transmitted is written to the SPORT_TX_A and SPORT_TX_B registers to transmit data through
the APB bus. This data is then transferred to the transmit shift register. The shift register, clocked by SPT_CLK
signal, then serially shifts out this data on SPT_D0, synchronously. If framing signal is used, the SPT_FS signal
indicates the start of the serial word transmission.
When SPORT is configured as transmitter, the enabled SPORT data pins SPT_ D0 are always driven.
NOTE: If next frame sync is assigned after a time duration greater than serial word length, then during inactive
serial clock cycles (clock cycles after data transmission in the current frame), the SPORT drives the first bit of next
word to be transmitted on the data pin. This does not cause any problem at the receiver end, as it starts sampling the
data pin only after detecting a valid frame sync. Note that this is not the case in gated clock mode as no clock is
present during inactive frame sync.
The serial port provides status of transmit data buffers and error detection logic for transmit errors such as underrun. For more information, refer to Error Detection.
When a serial port is configured in transmit mode, the receive data path is deactivated and do not respond to serial
clock or frame sync signals. So, reading from an empty Receive Data Buffer is not recommended in Tx mode.
Receive Path
The SPORT_CTL_A.SPTRAN bit, when cleared, configures the SPORT in receive mode.
The SPORT_RX_A and SPORT_RX_B registers, which are the receive data buffers (three deep FIFO), are accessible over APB.
In Rx mode, the input shift register shifts in data bits on the SPT_D0, synchronous to the SPT_CLK. If framing
signal is used, the SPT_AFS signal indicates the beginning of the serial word being received. When an entire word is
shifted in on the channel, the data is available to be read from SPORT_RX_x.
The serial port provides the status of Receive Data buffers and error detection logic for receive errors such as overflow. For more information, refer to Error Detection.
16–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Functional Description
When a serial port is configured in receive mode, the transmit path is deactivated and does not respond to serial
clock or frame sync signals. Therefore, accessing the transmit data buffer is not recommended in Rx mode.
Multiplexer Logic
There is a multiplexing block, known as SPMUX that is integrated between the SPORT and the PinMux logic. It
allows flexibility to route and share the clock and frame sync signals between the two half SPORT pairs. This feature
can be used to reduce the total number of pins for the interface and is efficient when the half SPORT pair is used
for full-duplex operation.
SPORT_CTL_A.CKMUXSEL and SPORT_CTL_A.FSMUXSEL are used to configure this feature.
The figure below shows the operation of this multiplexer connected between half SPORTs clocks. Half SPORT A
can be programmed to obtain clock from the neighboring half SPORT B.
SPT_CLK A
HSCLK A_IN
0
HSPORT A
1
SPORT_CTL_A.CKMUXSEL
HSCLK B_OUT
SPT_CLK B
HSPORT B
Figure 16-3: Multiplexer Logic When HSPORT A Uses HSPORT B’s Internal Clock
If SPORT_CTL_A.CKMUXSEL is 1, it receives an internal clock of B when SPORT_CTL_B.ICLK value is 1.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–5
SPORT Functional Description
HSCLK A_IN
0
SPT_CLK A
1
SPT_CLK B
HSPORT A
SPORT_CTL_A.CKMUXSEL
HSCLK B_IN
HSPORT B
Figure 16-4: Multiplexer Logic When HSPORT A and HSPORT B Use Same External Clock
If SPORT_CTL_A.CKMUXSEL is 1 and SPORT_CTL_B.ICLK is 0, both half SPORTs get the same external
clock.
If SPORT_CTL_A.CKMUXSEL is 0, normal operation of clock is carried out for both the half SPORTs.
The figure below shows the operation of the multiplexer connected between half SPORTs frame sync. Half SPORT
A can be programmed to obtain frame sync from the neighboring half SPORT B
SPT_FSA
HSFS A_IN
0
HSPORT A
1
SPORT_CTL_A.FSMUXSEL
HSCLK B_OUT
SPT_FS B
HSPORT B
Figure 16-5: Multiplexer Logic When HSPORT A Uses HSPORT B’s Internal Frame Sync
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Functional Description
If SPORT_CTL_A.FSMUXSEL is 1, it gets internal frame sync of B when SPORT_CTL_B.IFS value is 1.
HSFS A_IN
0
SPT_FS A
1
SPT_FS B
HSPORT A
SPORT_CTL_A.FSMUXSEL
HSFS B_IN
HSPORT B
Figure 16-6: Multiplexer Logic When HSPORT A and HSPORT B Use Same External Frame Sync
If SPORT_CTL_A.FSMUXSEL is 1 and SPORT_CTL_B.IFS is 0, both half SPORTs get the same external
frame sync.
If SPORT_CTL_A.FSMUXSEL is 0, normal operation of frame sync is carried out for both the half SPORTs.
Polarity bits such as SPORT_CTL_A.CKRE,SPORT_CTL_B.CKRE, SPORT_CTL_A.LFS, and
SPORT_CTL_B.LFS must have identical settings when using muxing between two SPORT halves. The number
of transfers (NUMTRAN) value must also be programmed with the same number in both half SPORTs when same
internal clock/frame sync is used in both halves.
NOTE: HSPORT A can import serial clock signal from HSPORT B, only when it is configured in external clock
mode. Similarly, it can import frame sync signal, only when it is configured in external frame sync mode.
SPORT_CTL_A register programming (for SPORT_CTL_A.CKMUXSEL and SPORT_CTL_A.FSMUXSEL) is
required only for HSPORT A (not for HSPORT B) to enable this sharing. HSPORTB cannot import serial clock
sgnal and framne sync signal from HSPORT A
Serial Clock
The serial clock (SPT_CLK) signal controls how the data bits are driven or sampled. The frame sync signal is also
driven (in internal frame sync mode) or sampled (in external frame sync mode) with respect to serial clock the signal. The serial clock can be internally generated from the MCU's system clock or externally provided, based on the
SPORT_CTL_x.ICLK (SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) bit. If a SPORT is configured in
internal clock mode (SPORT_CTL_x.ICLK= 1), then the SPORT_DIV_x.CLKDIV
(SPORT_DIV_A.CLKDIV or SPORT_DIV_B.CLKDIV) field specifies the divider to generate serial port clock
signal from its fundamental clock, PCLK. This divisor is a 16-bit value, allowing a wide range of serial clock rates.
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SPORT Functional Description
The following equation is used to calculate the serial clock frequency:
f SPT_CLK =
PCLK
2x(1+SPORT_DIV_xCLKDIV)
The maximum serial data rate is 13 Mbps for a maximum PCLK frequency of 26 MHz.
In gated clock mode, the serial port can be configured to generate gated clock which is active only for the duration
of valid data.
If a SPORT is configured in external clock mode (SPORT_CTL_x.ICLK = 0), then serial clock is an input signal
and the SPORT operates in slave mode. The SPORT_DIV_x.CLKDIV is ignored.
The externally supplied serial clock is always considered as an asynchronous clock with respect to the MCU system
clock. For exact AC timing specifications, refer to the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with
Integrated Power Management Data Sheet.
Frame Sync
Frame sync is a control signal, used to determine the start of new word or frame. Upon detecting this signal, serial
port starts shifting in or out the data bits serially based on the direction selected. The frame sync signal can be internally generated from its serial clock (SPT_CLK x) or externally provided, based on the SPORT_CTL_x.IFS
(SPORT_CTL_A.IFS or SPORT_CTL_B.IFS) bit setting.
If SPORT is configured for internal frame sync mode (SPORT_CTL_x.IFS = 1), then the
SPORT_DIV_x.FSDIV (SPORT_DIV_A.FSDIV or SPORT_DIV_B.FSDIV) field specifies the divider to
generate SPT_FS x signal from the serial clock. This divisor is a 8-bit value, allowing a wide range of frame sync
rates to initiate periodic transfers.
Number of serial clocks between frame syncs = (SPORT_DIV_x.FSDIV + 1).
FSDIV is used for the internally generated SPT_CNV signal when it is operating in timer enable mode. Therefore,
for timer enable mode, this field refers to the number of serial clock cycles between SPT_CNV pulses.
The value of SPORT_DIV_x.FSDIV must not be less than the value of the SPORT_CTL_x.SLEN
(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) bit field (the serial word length minus one, as this may cause
an external device to abort the current operation or cause other unpredictable results.
NOTE: After enabling the SPORT, the first internal frame sync (or CNV in case of Timer enable mode) appears
after a delay of (SPORT_DIV_x. FSDIV + 1) serial clocks.
If a SPORT is configured in external frame sync mode (SPORT_CTL_x.IFS = 0), then SPT_FS x is an input
signal and the SPORT_DIV_x.FSDIV field of the SPORT_DIV_x (SPORT_DIV_A or SPORT_DIV_B) register is ignored. By default, this external signal is level-sensitive. The frame sync is expected to be synchronous with
the serial clock. If not, it must meet the timing requirements mentioned in the ADuCM4050 Ultra Low Power ARM
Cortex-M4F MCU with Integrated Power Management Data Sheet.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Frame Sync
NOTE: When the SPORT is enabled, frame sync must be deasserted.
Frame Sync Options
The framing signals may be active high or low. The SPORT_CTL_x.LFS bit (SPORT_CTL_A.LFS or
SPORT_CTL_B.LFS) selects the logic level of the frame sync signals.
• When SPORT_CTL_x.LFS = 0, the corresponding frame sync signal is active high. Default polarity of frame
sync signal
• When SPORT_CTL_x.LFS = 1, the corresponding frame sync signal is active low.
The following sections describe how frame sync signal is used by the serial port in an operating mode.
Data Dependent Frame Sync and Data Independent Frame Sync
When a SPORT is configured as a transmitter, that is, SPORT_CTL_x.SPTRAN bit (SPORT_CTL_A.SPTRAN
or SPORT_CTL_B.SPTRAN) is 1, and if data independent frame sync select, that is SPORT_CTL_x.DIFS bit
(SPORT_CTL_A.DIFS or SPORT_CTL_B.DIFS) is 0, then an internally-generated transmit frame sync is only
driven when a new data word has been loaded into the transmit buffer of the SPORT. In other words, frame sync
signal generation and therefore data transmission is data-dependent. This mode of operation allows for wait states
when data is not ready.
When SPORT is configured as receiver (SPORT_CTL_x.SPTRAN = 0) and if SPORT_CTL_x.DIFS= 0, then a
receive frame sync signal is generated only when receive data buffer status is not full.
The data-independent frame sync mode allows the continuous generation of the framing signal, regardless of the
buffer status. Setting SPORT_CTL_x.DIFS activates this mode. When SPORT_CTL_x.DIFS = 1, a transmit/
receive frame sync signal is generated regardless of the transmit/receive data buffer status respectively.
NOTE: The DMA typically keeps the transmit buffer full. The application is responsible for filling the transmit
buffers with data. Else, an underflow/overflow case would arise and it would be flagged.
Early Frame Sync and Late Frame Sync
The frame sync signals can be early or late. The SPORT_CTL_x.LAFS bit of the serial port control register configures this option.
By default, when SPORT_CTL_x.LAFS is cleared, the frame sync signal is configured as early framing signal. This
is the normal mode of operation. In this mode, the first bit of the transmit data word is available (and the first bit of
the receive data word is latched) in the next serial clock cycle after the frame sync is asserted. The frame sync is not
checked again until the entire word has been transmitted (or received).
If data transmission is continuous in early framing mode (in other words, the last bit of each word is immediately
followed by the first bit of the next word), then frame sync signal occurs during the last bit of each word. Internally
generated frame syncs are asserted for one clock cycle in early framing mode.
When SPORT_CTL_x.LAFS is set, late frame syncs are configured; this is the alternate mode of operation. In this
mode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in the
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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Frame Sync
same serial clock cycle that the frame sync is asserted. Receive data bits are latched by serial clock edges. Internallygenerated frame syncs remain asserted for the entire length of the data word in late framing mode.
NOTE: In the case of late frame sync, externally generated frame syncs are expected to be asserted for the entire
word length of the data transfer. Else, unpredictable results can occur.
The figure shows the two modes of frame signal timing.
Serial CLK
Early
Frame Sync
1 CLK
Late
Word Length
Frame Sync
Data
D3
D2
D1
D0
Figure 16-7: Normal Framing (Early Frame Sync) and Alternate Framing (Late Frame Sync)
Framed Sync and Unframed Frame Sync
The use of frame sync signal is optional in serial port communications. The SPORT_CTL_x.FSR bit
(SPORT_CTL_A.FSR or SPORT_CTL_B.FSR) determines if framing signal is required.
When SPORT_CTL_x.FSR bit is set, a frame sync signal is required for every data word.
When SPORT_CTL_x.FSR is cleared, the corresponding frame sync signal is not required. A single frame sync is
required to initiate communications but it is ignored after the first bit is transferred. Data words are then transferred
continuously in what is referred to as an unframed mode. Unframed mode is appropriate for continuous reception/
transmission.
The following figure shows the framed versus unframed mode of serial port operation.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Functional Description
Clk
Framed Mode - Frame Sync
Data
B
B
B
B
B
B
B
B
3
2
1
0
3
2
1
0
B
B
B
B
B
B
B
B
B
B
B
3
2
1
0
3
2
1
0
3
2
1
Unframed Mode - Frame Sync
Data
Figure 16-8: Framed Data Stream and Unframed Data Stream
NOTE: In unframed mode of operation, the SPORT_CTL_x.DIFS bit must always be set to 1.
SPORT_CTL_x.DIFS=0 is not supported for unframed mode. Also, the SPORT_CTL_x.LAFS bit must always
be set as zero. Late frame sync is not supported for unframed mode.
Sampling Edge
The serial port uses two control signals to sample or drive the serial data:
• Serial clock (SPT_CLK) applies the bit clock for each serial data.
• Frame sync (SPT_FS) divides the data stream into frames.
These control signals can be internally generated or externally provided, determined by the SPORT_CTL_x.ICLK
(SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) and SPORT_CTL_x.IFS (SPORT_CTL_A.IFS or
SPORT_CTL_B.IFS) bit settings.
Data and frame syncs can be sampled on the rising or falling edges of the serial port clock signals. The
SPORT_CTL_x.CKRE (SPORT_CTL_A.CKRE or SPORT_CTL_B.CKRE) bit controls the sampling edge. By
default, when SPORT_CTL_x.CKRE = 0, the MCU selects the falling edge of SPT_CLK signal for sampling receive data and external frame sync. The receive data and frame sync are sampled on the rising edge of SPT_CLK
when SPORT_CTL_x.CKRE = 1.
Transmit data and internal frame sync signals are driven (change their state) on the serial clock edge that is not selected. By default, (SPORT_CTL_x.CKRE = 0) the SPORTs drive data and frame sync signals on the rising edge
of the SPT_CLK signal and drives on falling edge when SPORT_CTL_x.CKRE= 1.
Therefore, transmit and receive functions of any two serial ports connected together should always select the same
value for SPORT_CTL_x.CKRE so that internally generated signals are driven on one edge, and received signals
are sampled on the opposite edge.
The following figure shows the typical SPORT signals on two sides of serial communication for
SPORT_CTL_x.CKRE = 0.
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SPORT Functional Description
DRIVE
SCLK
External
Frame Sync
SDRIVE
DATA
D6
D7
D5
D4
D3
D2
D1
D0
Internal
Frame Sync
SAMPLED
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16-9: Frame Sync and Data Driven on Rising Edge
When the slave samples the Frame Sync signal, the word counter is reloaded to the maximum setting. Each
SPT_CLK decrements this word counter until the full frame is received.
Therefore, if the transmitter drives the internal frame sync and data on the rising edge of serial clock, the falling edge
must be used by receiver to sample the external frame sync and data, and vice versa.
Premature Frame Sync Error Detection
A SPORT framing signal is used to synchronize transmit or receive data. In external FS mode, if a frame sync received when an active frame is in progress or the frame sync truncates during an on-going transfer when using late
frame sync, it is called premature frame sync and is invalid.
If premature frame sync is received, the SPORT_STAT_x.FSERR bit (SPORT_STAT_A.FSERR or
SPORT_STAT_B.FSERR) is flagged to indicate this framing error. An optional error interrupt can be generated
for this event by setting the SPORT_IEN_x.FSERRMSK bits (SPORT_IEN_A.FSERRMSK and
SPORT_IEN_B.FSERRMSK).
As shown in the figure, the frame sync error (which sets the error bit) is triggered when an early frame sync occurs
during data transfer (transmission or reception) or for late frame sync if the period of the frame sync is smaller than
the serial word length (SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN).
FSERR Interrupt
EARLY FS
DRIVE
SCLK
DRIVE
FS
SDRIVE
DATA
D6
D7
D5
D4
D3
D2
D1
D0
SAMPLED
FS
SLEN
COUNTER
SAMPLED
DATA
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 16-10: Frame Sync Error Detection
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Functional Description
When a frame sync error occurs, the SPORT_CTL_x_FSERMODE bit (SPORT_CTL_A.FSERRMODE or
SPORT_CTL_B.FSERRMODE) decides the way this error is handled only in case of receive operation. If this bit is
set, the receive data is discarded. When the next frame sync comes, fresh receive transfer is carried out.
If this bit is zero, then the frame sync error is flagged and the transfer is continued. No action is taken with respect
to the transfer.
Serial Word Length
The SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field of serial port control register determines the word
length of serial data to transmit and receive. Each half SPORT can independently handle word lengths up to 32 bits.
Words smaller than 32 bits are right-justified during transmit or receive buffers to least significant bit (LSB) position. However, data can be shifted-in or out in MSB first or LSB first format based on SPORT_CTL_A.LSBF or
SPORT_CTL_B.LSBF bit setting.
The value of the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field can be calculated as:
SLEN = Serial port word length - 1
The range of valid word length in Standard serial mode is 4-32.
Number of Transfers
The register SPORT_NUMTRAN_A or SPORT_NUMTRAN_B of the SPORT determines the number of word transfers. The word length is specified in the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field. Each half
SPORT has this field and can be used for receive or transmit depending on the SPORT_CTL_A.SPTRAN or
SPORT_CTL_B.SPTRAN bit. This field can be programmed to the required number of word transfers to be transmitted/received. Once the programmed number of transfers are done, the SPORT disables all the operations. That
is, clock is not generated if in internal clock mode and not latched if in external clock mode. The frame sync is not
generated and no operation is performed for received frame syncs.
For example, if 20 transfers are programmed and word length programmed is 20 bits, after 400 bits of transfer the
SPORT would disable all the operations.
This register has 12 programmable bits to decide the number of transfers.
To start the next set of transfers, the SPORT_NUMTRAN_CNT_A and SPORT_NUMTRAN_CNT_B registers must
be reprogrammed with the desired number of transfers. If the same number of transfers need to be programmed, the
same value must be reprogrammed.
Also, once the number of transfers are finished, in external clock mode, no extra frame syncs are expected to be sent
to the SPORT. For new transfers, the frame sync must be sent only once the NUMTRAN is reprogrammed.
NOTE: In unframed mode, the number of transfers cannot be reprogrammed to perform the next set of transfers.
SPORT must be disabled and re-enabled to perform the operation for the next set of transfers in case of unframed
mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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SPORT Functional Description
SPORT Power Management
When the chip goes into hibernate mode, the configuration values are retained. The following registers are retained:
• SPORT_CTL_A (except DMAEN and SPEN bit fields)
• SPORT_DIV_A
• SPORT_CNVT_A
• SPORT_CTL_B (except DMAEN and SPEN bit fields)
• SPORT_DIV_B
• SPORT_CNVT_B
NOTE: If any transfer is going on before the chip goes into hibernate, that transfer does not resume after returning
from hibernate. A fresh start must be made when SPORT comes back from hibernate for the new transfer. Program
the SPORT_NUMTRAN_A or SPORT_NUMTRAN_B register appropriately and then program the
SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN bit to enable the SPORT operation.
SPORT Operating Modes
The ADuCM4050 MCU has SPORT that supports the following operating modes:
• Standard serial mode
• Timer-enable mode
The SPORT halves within a SPORT can be independently configured if they are not coupled using SPMUX logic.
NOTE:
• These modes support either, cases where the clock and the frame sync are both internal or both are external.
Modes with external frame sync, internal clock and internal frame sync, external clock is not supported by the
SPORT. Only for the unframed mode, external clock (SPORT_CTL_x.ICLK = 0 (SPORT_CTL_A.ICLK
or SPORT_CTL_B.ICLK)) and internal frame sync pulse (SPORT_CTL_x.IFS = 1
(SPORT_CTL_A.IFS or SPORT_CTL_B.IFS)), generated for the start of transfer is supported.
• To change the SPORT configuration (for example, changing SPORT_CTL_x.SLEN
(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) or SPORT_CTL_x.LSBF (SPORT_CTL_A.LSBF
or SPORT_CTL_B.LSBF)), clear the SPORT_CTL_x.SPEN bit (SPORT_CTL_A.SPEN or
SPORT_CTL_B.SPEN) and re-enable again by setting this bit.
• When SPORT is operating in external clock mode, SPORT needs three serial clocks after the SPORT is enabled before the normal operation can begin.
Mode Selection
The operating mode is configured in the SPORT_CTL_x.OPMODE (SPORT_CTL_A.OPMODE or
SPORT_CTL_B.OPMODE).
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Operating Modes
Standard Serial Mode
The SPORT can be configured in standard DSP serial mode by clearing the SPORT_CTL_x.OPMODE. The standard serial mode lets programs configure serial ports to connect to a variety of serial devices such as serial data converters and audio codecs. In order to connect to these devices, a variety of clocking, framing, and data formatting
options are available. All these options are as discussed in the above section describing the signals and the various
features. All of these options can be used in the standard serial mode.
Timer-Enable Mode
Few ADCs/DACs require two control signals for their conversion process. To interface with such devices, an extra
signal (SPT_CNV) is required. The timer-enable mode must be enabled to use this signal by programming the
SPORT_CTL_x.OPMODE to 1. A PWM timer inside the module is used to generate the programmable CNV signal.
The width of the SPT_ONV signal is programmed in the SPORT_CNVT_x.WID (SPORT_CNVT_A.WID or
SPORT_CNVT_B.WID) field. The delay between SPT_CNV assertion and frame sync assertion is programmed in
the SPORT_CNVT_x.CNVT2FS (SPORT_CNVT_A.CNVT2FS or SPORT_CNVT_B.CNVT2FS). This programmability provides flexibility in the use of these signals. The following figure shows these values.
Serial CLK
CNV
CNV_WIDTH
CNV_WIDTH
CNV_FS_DURTN
Frame Sync
Data
Word Length
D3
D2
D1
D0
FSDIV
Figure 16-11: Signals Interfaced in Timer-Enable Mode
The polarity of the SPT_CNV signal can be programmed in the SPORT_CNVT_x.POL (SPORT_CNVT_A.POL
or SPORT_CNVT_B.POL) bit field.
The number of serial clock cycles between CNV pulse is given by FSDIV value. All the other programmable options
defined for frame sync in the DSP serial mode can be used in this mode except the following options:
• External frame sync and external clock cannot be used.
• Early frame sync cannot be used.
• Unframed mode cannot be used.
NOTE: SPT_CNV signal is not used when DSP serial mode is in use.
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SPORT Data Transfer
SPORT Data Transfer
The SPORT uses either a core driven or DMA driven data transfers. DMA transfers can be set up to transfer a configurable number of serial words between the serial port transmit or receive data buffers and internal memory automatically. Core-driven transfers use SPORT interrupts to signal the MCU core to perform single word transfers to/
from the serial port data buffers.
Single Word (Core) Transfers
Individual data words may also be transmitted or received by the serial ports, with interrupts occurring as each data
word is transmitted or received. When a serial port is enabled and corresponding DMA is disabled, the SPORT
interrupts are generated whenever a complete word has been received in the receive data buffer, or whenever the
transmit data buffer is not full.
When serial port data packing is enabled, transmit and receive interrupts are generated for 32-bit packed words, not
for each 16-bit or 8-bit word. When performing core driven transfers, write to the buffer designated by the
SPORT_CTL_A.SPTRAN (where A is the half SPORT) bit setting. To avoid undetermined behavior, check the
status of appropriate data buffers when the MCU core tries to read a word from a serial port's receive buffer or
writes a word to its transmit buffer. The full/empty status can be read using the SPORT_STAT_x.DXS
(SPORT_STAT_A.DXS or SPORT_STAT_B.DXS) bits.
DMA Transfers
Direct memory access (DMA) provides a mechanism for receiving or transmitting an entire block of serial data before an interrupt is generated. When SPORT DMA is not enabled, the SPORT generates an interrupt every time it
receives or starts to transmit a data word. The MCU's on-chip DMA controller handles the DMA transfer, allowing
the MCU core to either go to sleep or continue running other tasks until the entire block of data is transmitted or
received. Service routines can then operate on the block of data rather than on single words, significantly reducing
overhead.
Therefore, set the direction bit, DMA enable bit, and serial port enable bit before initiating any operations on the
SPORT data buffers. Do not try to access data buffers when the associated DMA channel of serial port is enabled.
Each half SPORT has a dedicated DMA channel for Tx and Rx data paths. In transmit mode, the DMA controller
writes to the transmit data buffer. Similarly, in receive mode, the DMA controller reads from the receive data buffer.
The DMA controller generates an interrupt at the end of the completion of a DMA transfer.
Though DMA transfers are performed with 32-bit words, the SPORTs can handle word sizes from 4 to 32 bits (as
defined by SPORT_CTL_x.SLEN (SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) field). If serial data
length is 16 bits or smaller, two data bytes can be packed into 32-bit words for each DMA transfer. If serial data
length is 8 bits or smaller, four data can be packed into 32-bit words for each DMA transfer. When serial port data
packing is enabled, transmit and receive DMA requests are generated for the 32-bit packed words, not for each 16bit or 8-bit word.
Depending on whether packing is enabled, appropriate DMA transfer width needs to be selected in the DMA controller. If packing is enabled or greater than 16-bit transfers are desired, use word transfers in DMA. If packing is not
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SPORT Data Buffers
enabled and transfer is less than 16 bits but greater than 8 bits, use half word transfers. If packing is not enabled and
transfer length is less than 8 bits, use byte transfers within the DMA controller.
NOTE: DMA requests may not be serviced frequently to guarantee continuous data flow in case of continuous
transmission/reception. Ensure that the DMA channel has the highest priority when performing such transfers.
SPORT Data Buffers
Data Buffer Status
The SPORT provides status information about data buffers. Depending on the SPORT_CTL_A.SPTRAN bit setting, these bits reflect the status of transmit data buffers or receive data buffers. The SPORT_STAT_x.DXS bits
indicate if the buffers are full, partially full, or empty.
To avoid undetermined conditions, always check the buffer status to determine if the access can be made. The status
bits in the SPORT_STAT_A.DXS field always reflect the FIFO status.
Three complete 32-bit words can be stored in the receive buffer while the fourth word is being shifted in. Therefore,
four complete words can be received without the receive buffer being read, before an overflow occurs. After receiving
the fourth word completely, the shift register contents overwrite the third word if the first word has not been read
out (by the MCU core or DMA controller). When this happens, the receive overflow status is flagged through the
error status bits of the SPORT_STAT_A.DERR register. The overflow status is generated after the last bit of the
fourth word is received.
Data Buffer Packing
When the SPORT is configured as a receiver with a serial data word length of 16 or less or even 8 or less, then
received data words may be packed into a 32-bit word. Similarly, if the SPORT is configured as transmitter with a
serial data word length of 16 or less, then 32-bit words being transmitted may be unpacked into two 16-bit words or
four 8-bit words. This feature is selected by the SPORT_CTL_x.PACK (SPORT_CTL_A.PACK or
SPORT_CTL_B.PACK) bit.
NOTE: If packing is not enabled for lower length transfers, bus bandwidth as well as FIFO buffers are not efficiently
used.
When SPORT_CTL_x.PACK= 01, four successive words received are packed into a single 32-bit word, or each 32bit word is unpacked and transmitted as four 8-bit words. The words with less than 16-bit are packed as [SLEN:
0], [(SLEN+8):8], [(SLEN+16):16], and [(SLEN+24):24]. This applies to both receive (packing)
and transmit (unpacking) operations.
The figure shows the 8-bit packing. The dark region corresponds to the packed bits.
32 SLEN+24
24
SLEN+16
16 SLEN+8
8
SLEN
0
Figure 16-12: Packed Data (8-bit Packing)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
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SPORT Interrupts and Exceptions
When SPORT_CTL_x.PACK is assigned 10, two successive words received are packed into a single 32-bit word,
or each 32-bit word is unpacked and transmitted as two 16-bit words. The words with less than 16-bit are packed as
[SLEN: 0] and [(SLEN+16):16].This applies to both receive (packing) and transmit (unpacking) operations.
The figure shows the 16-bit packing.
32
SLEN+16
16
SLEN
0
Figure 16-13: Packed Data (16-bit Packing)
In packing, transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word or 8
bit word. The packing feature enables efficient utilization of the system bandwidth.
NOTE: When packing is enabled, the word length must be programmed lesser than the programmed packing. For
example, if 8-bit packing is programmed, SLEN must be less than or equal to 7 and if 16-bit packing is programmed, SLEN must be less than or equal to 15.
SPORT Interrupts and Exceptions
Each half SPORT has an interrupt associated with it. To determine the source of an interrupt, applications should
check the interrupt status register. This section describes the various interrupt sources. In core mode, SPORT is able
to generate data interrupts for receive or transmit operations. Moreover, the SPORT modules generate error conditions which have a separate status bit for each interrupt source.
NOTE: To clear the interrupt signal, the corresponding status bit is written by 1. This clears the value of the status
bit, that is, the corresponding status bit becomes zero.
Error Detection
When the SPORT is configured as a transmitter, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit
provides transmit data buffer underflow status for the data path (it indicates that frame sync signal occurred when
the transmit data buffer was empty). The SPORT transmits data whenever it detects a framing signal.
Similarly, if the SPORT configured as a receiver, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit
provides receive overflow status of receive data buffer. In other words, the SPORT indicates that a channel has received new data when the receive buffer is full, so new data overwrites existing data. The SPORT receives data when
it detects a framing signal.
These error conditions occur in case of external frame sync or when the DIFS (Data independent frame sync) is set.
The SPORT_IEN_x.DERRMSK (SPORT_IEN_A.DERRMSK or SPORT_IEN_B.DERRMSK)(data error interrupt enable) bit can be used to unmask the status interrupt for data errors.
In addition to data underflow and data overflow errors, the status interrupt is also triggered optionally when frame
sync error is detected. The SPORT_IEN_x.FSERRMSK (SPORT_IEN_A.FSERRMSK or
16–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
SPORT Interrupts and Exceptions
SPORT_IEN_B.FSERRMSK)(frame sync error interrupt enable) bit unmasks the status interrupt for this frame
sync error. This frame sync error is generated due to premature frame sync. For more information about this, refer to
Premature Frame Sync Error Detection.
NOTE: A frame sync error is not detected when there is no active data transmit/receive and the frame sync pulse
occurs due to noise in the input signal.
System Transfer Interrupts
When the SPORT is configured to transmit, an interrupt is generated when an attempt is made by the core to write
into a Transmit FIFO which is full. The SPORT_STAT_A.SYSDATERR or SPORT_STAT_B.SYSDATERR
status indicates this Transmit FIFO overflow error.
Similarly, when the SPORT is configured to receive, an interrupt is generated when an attempt is made by the core
to read from an empty Receive FIFO. The field SPORT_STAT_A.SYSDATERR or
SPORT_STAT_B.SYSDATERR status now indicates Receive FIFO underflow error.
NOTE: In DMA mode, SPORT does not produce a DMA request when Transmit FIFO is full or Receive FIFO is
empty. Interrupt is not generated for DMA transfers.
Transfer Finish Interrupt (TFI)
The Transmit Finish Interrupt feature is used to signal the end of the transmission/reception. This feature can be
enabled by setting SPORT_IEN_A or SPORT_IEN_B bit. When the number of transfers programmed in
SPORT_NUMTRAN_A or SPORT_NUMTRAN_B field are finished, SPORT waits until all the data in the FIFO is
transmitted out (including the transmit shift register) or received completely in the receive registers and then generates the Transfer Finish Interrupt. This feature allows the user to determine that all data corresponding to understand that data corresponding to the programmed number of transfers have been transmitted out or received completely by the SPORT.
NOTE: Once the Transfer Finish Interrupt is obtained, the user can either reprogram the number of transfers or
disable the SPORT and re-enabled (if needed). To reprogram the number of transfers, see Number of Transfers.
To re-enable the SPORT, see SPORT Programming Model.
SPORT Programming Model
The following are the SPORT programming guidelines:
• Write all the registers of SPORT with the desired values of configuration except the control register.
• After configuration, write the control register (SPORT_CTL_A or SPORT_CTL_B) with desired configuration for the transfer. SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN field must be programmed as 1.
• When the SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN fields are written to 1, normal operation of the
SPORT can start based on the programmed configuration values.
The SPORT registers that need to be written with configuration values are:
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–19
ADuCM4050 SPORT Register Descriptions
• Write SPORT_DIV_A or SPORT_DIV_B to program the desired CLKDIV and FSDIV values.
• The SPORT_CNVT_A or SPORT_CNVT_B register must only be written in timer-enable mode.
• EN register is written based on the interrupts. For example, if an interrupt is desired for an underflow/overflow
error, SPORT_IEN_A or SPORT_IEN_B must be set.
• Write SPORT_NUMTRAN_A or SPORT_NUMTRAN_B with the desired number of transfers. This must not
be programmed to zero.
ADuCM4050 SPORT Register Descriptions
Serial Port (SPORT) contains the following registers.
Table 16-2: ADuCM4050 SPORT Register List
Name
Description
SPORT_CTL_A
Half SPORT 'A' Control Register
SPORT_CTL_B
Half SPORT 'B' Control Register
SPORT_DIV_A
Half SPORT 'A' Divisor Register
SPORT_DIV_B
Half SPORT 'B' Divisor Register
SPORT_IEN_A
Half SPORT A's Interrupt Enable register
SPORT_IEN_B
Half SPORT B's Interrupt Enable register
SPORT_NUMTRAN_A
Half SPORT A Number of transfers register
SPORT_NUMTRAN_B
Half SPORT B Number of transfers register
SPORT_RX_A
Half SPORT 'A' Rx Buffer Register
SPORT_RX_B
Half SPORT 'B' Rx Buffer Register
SPORT_STAT_A
Half SPORT 'A' Status register
SPORT_STAT_B
Half SPORT 'B' Status register
SPORT_CNVT_A
Half SPORT 'A' CNV width
SPORT_CNVT_B
Half SPORT 'B' CNV width register
SPORT_TX_A
Half SPORT 'A' Tx Buffer Register
SPORT_TX_B
Half SPORT 'B' Tx Buffer Register
16–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' Control Register
The SPORT_CTL_A contains transmit and receive control bits for SPORT half 'A', including serial port mode selection
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIFS (R/W)
Data-Independent Frame Sync
SPEN (R/W)
Serial Port Enable
IFS (R/W)
Internal Frame Sync
FSMUXSEL (R/W)
Frame Sync Multiplexer Select
FSR (R/W)
Frame Sync Required
CKMUXSEL (R/W)
Clock Multiplexer Select
CKRE (R/W)
Clock Rising Edge
LSBF (R/W)
Least-Significant Bit First
OPMODE (R/W)
Operation mode
SLEN (R/W)
Serial Word Length
ICLK (R/W)
Internal Clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAEN (R/W)
DMA Enable
LFS (R/W)
Active-Low Frame Sync
SPTRAN (R/W)
Serial Port Transfer Direction
LAFS (R/W)
Late Frame Sync
DATMUXSEL (R/W)
Data Multiplexer select
PACK (R/W)
Packing Enable
GCLKEN (R/W)
Gated Clock Enable
FSERRMODE (R/W)
Frame Sync Error Operation
Figure 16-14: SPORT_CTL_A Register Diagram
Table 16-3: SPORT_CTL_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26 DMAEN
(R/W)
DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when the
Transmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–21
ADuCM4050 SPORT Register Descriptions
Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
25 SPTRAN
(R/W)
Serial Port Transfer Direction.
The SPORT_CTL_A.SPTRAN bit selects the transfer direction (receive or transmit)
for the half SPORT's channels.
0 Receive
1 Transmit
22 DATMUXSEL
(R/W)
Data Multiplexer select.
This bit is set to use the Data multiplexer to route the data from Half SPORT B to
Half SPORT A.
0 Reserved
1 Reserved
21 GCLKEN
(R/W)
Gated Clock Enable.
The SPORT_CTL_A.GCLKEN bit enables gated clock operation for the half
SPORT.
When SPORT_CTL_A.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable
20 FSERRMODE
(R/W)
Frame Sync Error Operation.
The SPORT_CTL_A.FSERRMODE bit decides the way the SPORT responds when a
frame sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data
19:18 PACK
(R/W)
Packing Enable.
The SPORT_CTL_A.PACK bit enables the half SPORT to perform 16- to 32-bit or
8- to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit
unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved
16–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
17 LAFS
(R/W)
Late Frame Sync.
The SPORT_CTL_A.LAFS bit selects whether the half SPORT generates a late
frame sync (SPORT_AFS during first data bit) or generates an early frame sync signal
(SPORT_AFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync
16 LFS
(R/W)
Active-Low Frame Sync.
The SPORT_CTL_A.LFS bit selects whether the half SPORT uses active low or active high frame sync.
0 Active high frame sync
1 Active low frame sync
15 DIFS
(R/W)
Data-Independent Frame Sync.
The SPORT_CTL_A.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync,
the half SPORT generates the sync at the interval selected by
SPORT_DIV_A.FSDIV. When using a data-dependent frame sync, the half SPORT
generates the sync on the selected interval when the transmit buffer is not empty or
when the receive buffer is not full.
0 Data-dependent frame sync
1 Data-independent frame sync
14 IFS
(R/W)
Internal Frame Sync.
The SPORT_CTL_A.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous with
the processor's system clock.
0 External frame sync
1 Internal frame sync
13 FSR
(R/W)
Frame Sync Required.
The SPORT_CTL_A.FSR selects whether or not the half SPORT requires frame
sync for data transfer.
0 No frame sync required
1 Frame sync required
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–23
ADuCM4050 SPORT Register Descriptions
Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 CKRE
(R/W)
Clock Rising Edge.
The SPORT_CTL_A.CKRE selects the rising or falling edge of the SPORT_ACLK
clock for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge
11 OPMODE
(R/W)
Operation mode.
The SPORT_CTL_A.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or in Timer enable mode
0 DSP standard
1 Timer_enable mode
10 ICLK
(R/W)
Internal Clock.
The SPORT_CTL_A.ICLK bit selects whether the half SPORT uses an internal or
external clock.
0 External clock
1 Internal clock
8:4 SLEN
(R/W)
Serial Word Length.
The SPORT_CTL_A.SLEN bits selects word length in bits for the half SPORT's data
transfers. Word may be from 4- to 32-bits in length. The formula for selecting the
word length in bits is:
SPORT_CTL_A.SLEN = (serial word length in bits) - 1
3 LSBF
(R/W)
Least-Significant Bit First.
The SPORT_CTL_A.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received
2 CKMUXSEL
(R/W)
Clock Multiplexer Select.
The SPORT_CTL_A.CKMUXSEL bit enables multiplexing of the half SPORT' serial
clock. In this mode, the serial clock of the related half SPORT is used instead of the
half SPORT's own serial clock. For example, if SPORT_CTL_A.CKMUXSEL is enabled, half SPORT 'A' uses SPORT_BCLK instead of SPORT_ACLK.
0 Disable serial clock multiplexing
1 Enable serial clock multiplexing
16–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-3: SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 FSMUXSEL
(R/W)
Frame Sync Multiplexer Select.
The SPORT_CTL_A.FSMUXSEL bit enables multiplexing of the half SPORT' frame
sync. In this mode, the frame sync of the related half SPORT is used instead of the half
SPORT's own frame sync. For example, if SPORT_CTL_A.FSMUXSEL is enabled,
half SPORT 'A' uses SPORT_BFS instead of SPORT_AFS.
0 Disable frame sync multiplexing
1 Enable frame sync multiplexing
0 SPEN
(R/W)
Serial Port Enable.
The SPORT_CTL_A.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes the
channel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–25
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' Control Register
The SPORT_CTL_B contains transmit and receive control bits for SPORT half 'B', including serial port mode selection for the channels. The function of some bits in SPORT_CTL_B vary, depending on the SPORT's operating
mode. For more information, see the SPORT operating modes description. If reading reserved bits, the read value is
the last written value to these bits or is the reset value of these bits.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIFS (R/W)
Data-Independent Frame Sync
SPEN (R/W)
Serial Port Enable
IFS (R/W)
Internal Frame Sync
LSBF (R/W)
Least-Significant Bit First
FSR (R/W)
Frame Sync Required
SLEN (R/W)
Serial Word Length
CKRE (R/W)
Clock Rising Edge
ICLK (R/W)
Internal Clock
OPMODE (R/W)
Operation mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAEN (R/W)
DMA Enable
LFS (R/W)
Active-Low Frame Sync
SPTRAN (R/W)
Serial Port Transfer Direction
LAFS (R/W)
Late Frame Sync
GCLKEN (R/W)
Gated Clock Enable
PACK (R/W)
Packing Enable
FSERRMODE (R/W)
Frame Sync Error Operation
Figure 16-15: SPORT_CTL_B Register Diagram
Table 16-4: SPORT_CTL_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26 DMAEN
(R/W)
DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when the
Transmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled
16–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
25 SPTRAN
(R/W)
Serial Port Transfer Direction.
The SPORT_CTL_B.SPTRAN bit selects the transfer direction (receive or transmit)
for the half SPORT's channels.
0 Receive
1 Transmit
21 GCLKEN
(R/W)
Gated Clock Enable.
The SPORT_CTL_B.GCLKEN bit enables gated clock operation for the half SPORT
when in DSP serial mode.
When SPORT_CTL_B.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable
20 FSERRMODE
(R/W)
Frame Sync Error Operation.
The SPORT_CTL_B.FSERRMODE bit decides the way the SPORT responds when a
frame sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data
19:18 PACK
(R/W)
Packing Enable.
The SPORT_CTL_B.PACK bit enables the half SPORT to perform 16- to 32-bit or
8- to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit
unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved
17 LAFS
(R/W)
Late Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0) ,
the SPORT_CTL_B.LAFS bit selects whether the half SPORT generates a late frame
sync (SPORT_BFS during first data bit) or generates an early frame sync signal
(SPORT_BFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–27
ADuCM4050 SPORT Register Descriptions
Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
16 LFS
(R/W)
Active-Low Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.LFS bit selects whether the half SPORT uses active low or active
high frame sync.
0 Active high frame sync
1 Active low frame sync
15 DIFS
(R/W)
Data-Independent Frame Sync.
The SPORT_CTL_B.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync,
the half SPORT generates the sync at the interval selected by
SPORT_DIV_B.FSDIV. When using a data-dependent frame sync, the half SPORT
generates the sync on the selected interval when the transmit buffer is not empty or
when the receive buffer is not full.
0 Data-dependent frame sync
1 Data-independent frame sync
14 IFS
(R/W)
Internal Frame Sync.
The SPORT_CTL_B.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous with
the processor's system clock.
0 External frame sync
1 Internal frame sync
13 FSR
(R/W)
Frame Sync Required.
The SPORT_CTL_B.FSR selects whether or not the half SPORT requires frame
sync for data transfer.
0 No frame sync required
1 Frame sync required
12 CKRE
(R/W)
Clock Rising Edge.
The SPORT_CTL_B.CKRE selects the rising or falling edge of the SPORT_BCLK
clock for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge
16–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-4: SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 OPMODE
(R/W)
Operation mode.
The SPORT_CTL_B.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or timer enable mode
0 DSP standard mode
1 Timer Enable mode
10 ICLK
(R/W)
Internal Clock.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.ICLK bit selects whether the half SPORT uses an internal or external clock. For internal clock enabled, the half SPORT generates the SPORT_BCLK
clock signal, and the SPORT_BCLK is an output. The SPORT_DIV_B.CLKDIV
serial clock divisor value determines the clock frequency. For internal clock disabled,
the SPORT_BCLK clock signal is an input, and the serial clock divisor is ignored.
Note that the externally-generated serial clock does not need to be synchronous with
the processor's system clock.
0 External clock
1 Internal clock
8:4 SLEN
(R/W)
Serial Word Length.
The SPORT_CTL_B.SLEN bits selects word length in bits for the half SPORT's data
transfers. Word may be from 4- to 32-bits in length. The formula for selecting the
word length in bits is:
SPORT_CTL_B.SLEN = (serial word length in bits) - 1
3 LSBF
(R/W)
Least-Significant Bit First.
The SPORT_CTL_B.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received
0 SPEN
(R/W)
Serial Port Enable.
The SPORT_CTL_B.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes the
channel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–29
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' Divisor Register
The SPORT_DIV_A contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for half SPORT 'A'.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSDIV (R/W)
Frame Sync Divisor
Figure 16-16: SPORT_DIV_A Register Diagram
Table 16-5: SPORT_DIV_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 FSDIV
(R/W)
15:0 CLKDIV
(R/W)
16–30
Frame Sync Divisor.
The SPORT_DIV_A.FSDIV bits select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse. The half
SPORT counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles
before generating CNV signal in timer enable mode.
Clock Divisor.
The SPORT_DIV_A.CLKDIV bits select the divisor that the half SPORT uses to
calculate the serial clock (SPORT_ACLK) from the processor system clock (PCLK).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' Divisor Register
The SPORT_DIV_B contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for SPORT half 'B'.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSDIV (R/W)
Frame Sync Divisor
Figure 16-17: SPORT_DIV_B Register Diagram
Table 16-6: SPORT_DIV_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 FSDIV
(R/W)
15:0 CLKDIV
(R/W)
Frame Sync Divisor.
The SPORT_DIV_B.FSDIV bits select the number of transmit or receive clock cycles that the half SPORT counts before generating a frame sync pulse. The half
SPORT counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles
before generating CNV signal in timer enable mode.
Clock Divisor.
The SPORT_DIV_B.CLKDIV bits select the divisor that the half SPORT uses to
calculate the serial clock (SPORT_BCLK) from the processor system clock (PCLK).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–31
ADuCM4050 SPORT Register Descriptions
Half SPORT A's Interrupt Enable register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT A.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SYSDATERR (R/W)
Data error for system writes or reads
TF (R/W)
Transfer Finish Interrupt Enable
DATA (R/W)
Data request interrupt to the core
DERRMSK (R/W)
Data Error (Interrupt) Mask
FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-18: SPORT_IEN_A Register Diagram
Table 16-7: SPORT_IEN_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 SYSDATERR
(R/W)
Data error for system writes or reads.
This field enables the half SPORT to generate the data error interrupt for the system
write resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt
3 DATA
(R/W)
Data request interrupt to the core.
This bit enables interrupt given to the core for a data write into transmit FIFO for
transmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable
2 FSERRMSK
(R/W)
Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_A.FSERRMSK unmasks (enables) the half SPORT to generate the
frame sync error interrupt.
0 Mask (disable)
1 Unmask (enable)
16–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-7: SPORT_IEN_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 DERRMSK
(R/W)
Data Error (Interrupt) Mask.
The SPORT_IEN_A.DERRMSK unmasks (enables) the half SPORT to generate the
data error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)
0 TF
(R/W)
Transfer Finish Interrupt Enable.
The SPORT_IEN_A.TF bit selects when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When enabled (SPORT_IEN_A.TF =1), when the last bit of last word of the programmed
number of transfers is shifted out or received completely, an interrupt is generated.
When disabled (SPORT_IEN_A.TF =0), no interrupt is generated by SPORT.
0 Transfer finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–33
ADuCM4050 SPORT Register Descriptions
Half SPORT B's Interrupt Enable register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT B.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SYSDATERR (R/W)
Data error for system writes or reads
TF (R/W)
Transmit Finish Interrupt Enable
DATA (R/W)
Data request interrupt to the core
DERRMSK (R/W)
Data Error (Interrupt) Mask
FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-19: SPORT_IEN_B Register Diagram
Table 16-8: SPORT_IEN_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 SYSDATERR
(R/W)
Data error for system writes or reads.
This field enables the half SPORT to generate the data error interrupt for the system
write resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt
3 DATA
(R/W)
Data request interrupt to the core.
This bit enables interrupt given to the core for a data write into transmit FIFO for
transmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable
2 FSERRMSK
(R/W)
Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_B.FSERRMSK unmasks (enables) the half SPORT to generate the
frame sync error interrupt.
0 Mask (disable)
1 Unmask (enable)
16–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-8: SPORT_IEN_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 DERRMSK
(R/W)
Data Error (Interrupt) Mask.
The SPORT_IEN_B.DERRMSK unmasks (enables) the half SPORT to generate the
data error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)
0 TF
(R/W)
Transmit Finish Interrupt Enable.
The SPORT_IEN_B.TF bit selects when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When enabled (SPORT_IEN_B.TF =1), when the last bit of last word of the programmed
number of transfers is shifted out or received completely, an interrupt is generated.
When disabled (SPORT_IEN_B.TF =0), no interrupt is generated by SPORT
0 Transfer Finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–35
ADuCM4050 SPORT Register Descriptions
Half SPORT A Number of transfers register
This register specifies the number of transfers of words to transfer or receive depending on
SPORT_CTL_A.SPTRAN.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Number of transfers (Half SPORT A)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-20: SPORT_NUMTRAN_A Register Diagram
Table 16-9: SPORT_NUMTRAN_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:0 VALUE
Number of transfers (Half SPORT A).
(R/W)
16–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT B Number of transfers register
This register specifies the number of transfers of the words to transfer or receive depending on
SPORT_CTL_B.SPTRAN.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Number of transfers (Half SPORT B)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-21: SPORT_NUMTRAN_B Register Diagram
Table 16-10: SPORT_NUMTRAN_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:0 VALUE
Number of transfers (Half SPORT B).
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–37
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' Rx Buffer Register
The SPORT_RX_A register buffers the half SPORT's receive data. This buffer becomes active when the half
SPORT is configured to receive data. After a complete word has been received in receive shifter, it is placed into the
SPORT_RX_A register. This data can be read in core mode (in interrupt-based or polling-based mechanism) or directly DMA'd into processor memory using DMA controller.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Receive Buffer
Figure 16-22: SPORT_RX_A Register Diagram
Table 16-11: SPORT_RX_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
16–38
Receive Buffer.
The SPORT_RX_A.VALUE bits hold the half SPORT's channel receive data.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' Rx Buffer Register
The SPORT_RX_B register buffers the half SPORT's channel receive data. This buffer becomes active when the
half SPORT is configured to receive data. After a complete word has been received in receive shifter, it is placed into
the SPORT_RX_B register. This data can be read in core mode or directly DMA'd into processor memory using
DMA controller.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Receive Buffer
Figure 16-23: SPORT_RX_B Register Diagram
Table 16-12: SPORT_RX_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
Receive Buffer.
The SPORT_RX_B.VALUE bits hold the half SPORT's receive data.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–39
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' Status register
This register contains all the status fields in the half SPORT A. Detected errors are frame sync violations or buffer
over/underflow conditions.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DXS (R)
Data Transfer Buffer Status
TFI (R/W1C)
Transmit Finish Interrupt Status
SYSDATERR (R/W1C)
System Data Error Status
DERR (R/W1C)
Data Error Status
DATA (R)
Data Buffer status
FSERR (R/W1C)
Frame Sync Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-24: SPORT_STAT_A Register Diagram
Table 16-13: SPORT_STAT_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 DXS
(R/NW)
Data Transfer Buffer Status.
The SPORT_STAT_A.DXS indicates the status of the half SPORT A's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full
4 SYSDATERR
(R/W1C)
System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during system
transfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_A.SYSDATERR indicates transmit overflow status. For receive
(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_A.SYSDATERR indicates receive
underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO
3 DATA
(R/NW)
Data Buffer status.
This field indicates only the status of the data buffers in Half SPORT A.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty
16–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-13: SPORT_STAT_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 FSERR
(R/W1C)
Frame Sync Error Status.
The SPORT_STAT_A.FSERR bit indicates that the half SPORT has detected a
frame sync when the bit count (bits remaining in the frame) is non-zero or it has seen
frame sync active for less than the word length in case of late frame sync.
0 No error
1 Frame Sync Error occurred
1 DERR
(R/W1C)
Data Error Status.
The SPORT_STAT_A.DERR bit indicates the error status for the half SPORT's data
buffers. During transmit (SPORT_CTL_A.SPTRAN =1), SPORT_STAT_A.DERR
indicates transmit underflow status. During receive (SPORT_CTL_A.SPTRAN =0),
SPORT_STAT_A.DERR indicates receive overflow status.
0 No error
1 Error (transmit underflow or receive overflow)
0 TFI
(R/W1C)
Transmit Finish Interrupt Status.
The SPORT_STAT_A.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is
1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–41
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' Status register
This register contains all the status fields present in the half SPORT B. Detected errors are frame sync violations or
buffer over/underflow conditions.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DXS (R)
Data Transfer Buffer Status
TFI (R/W1C)
Transmit Finish Interrupt Status
SYSDATERR (R/W1C)
System Data Error Status
DERR (R/W1C)
Data Error Status
DATA (R/W1C)
Data Buffer status
FSERR (R/W1C)
Frame Sync Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-25: SPORT_STAT_B Register Diagram
Table 16-14: SPORT_STAT_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 DXS
(R/NW)
Data Transfer Buffer Status.
The SPORT_STAT_B.DXS indicates the status of the half SPORT B's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full
4 SYSDATERR
(R/W1C)
System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during system
transfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_B.SYSDATERR indicates transmit overflow status. For receive
(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_B.SYSDATERR indicates receive
underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO
3 DATA
(R/W1C)
Data Buffer status.
This field indicates only the status of the data buffers in Half SPORT B.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty
16–42
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Table 16-14: SPORT_STAT_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 FSERR
(R/W1C)
Frame Sync Error Status.
The SPORT_STAT_B.FSERR bit indicates that the half SPORT has detected a
frame sync when the bit count (bits remaining in the frame) is non-zero or it has seen
frame sync active for less than the word length in case of late frame sync.
0 No error
1 Error (non-zero bit count at frame sync)
1 DERR
(R/W1C)
Data Error Status.
The SPORT_STAT_B.DERR bit indicates the error status for the half SPORT B's
data buffers. During transmit (SPORT_CTL_B.SPTRAN =1),
SPORT_STAT_B.DERR indicates transmit underflow status. During receive
(SPORT_CTL_B.SPTRAN =0), SPORT_STAT_B.DERR indicates receive overflow
status.
0 No error
1 Error (transmit underflow or receive overflow)
0 TFI
(R/W1C)
Transmit Finish Interrupt Status.
The SPORT_STAT_B.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is
1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–43
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' CNV width
This register contains the settings related to the CNV signal for Half SPORT A
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
POL (R/W)
Polarity of the CNV signal
WID (R/W)
CNV signal width: Half SPORT A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNVT2FS (R/W)
CNV to FS duration: Half SPORT A
Figure 16-26: SPORT_CNVT_A Register Diagram
Table 16-15: SPORT_CNVT_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 CNVT2FS
(R/W)
8 POL
(R/W)
CNV to FS duration: Half SPORT A.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CNV signal to Frame
sync signal for Half SPORT A
Polarity of the CNV signal.
This bit decides the polarity of the CNV signal
0 Active High Polarity
1 Active low Polarity
3:0 WID
(R/W)
16–44
CNV signal width: Half SPORT A.
This field contains the value of the number of serial clocks for which CNV signal
should be active for Half SPORT A
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' CNV width register
This register contains the settings related to the CNV signal for Half SPORT B
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
POL (R/W)
Polarity of the CNV signal
WID (R/W)
CNV signal width: Half SPORT B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNVT2FS (R/W)
CNV to FS duration: Half SPORT B
Figure 16-27: SPORT_CNVT_B Register Diagram
Table 16-16: SPORT_CNVT_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 CNVT2FS
(R/W)
8 POL
(R/W)
CNV to FS duration: Half SPORT B.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CNV signal to Frame
sync signal for Half SPORT B
Polarity of the CNV signal.
This bit decides the polarity of the CNV signal
0 Active High Polarity
1 Active low Polarity
3:0 WID
(R/W)
CNV signal width: Half SPORT B.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired width of the CNV signal for Half SPORT B
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–45
ADuCM4050 SPORT Register Descriptions
Half SPORT 'A' Tx Buffer Register
The SPORT_TX_A register buffers the half SPORT's transmit data. This register must be loaded with the data to
be transmitted if the half SPORT is configured to transmit. Either a program running on the processor core may
load the data into the buffer (word-by-word process) or the DMA controller may automatically load the data into
the buffer (DMA process).
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Transmit Buffer
Figure 16-28: SPORT_TX_A Register Diagram
Table 16-17: SPORT_TX_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
16–46
Transmit Buffer.
The SPORT_TX_A.VALUE bits hold the half SPORT's channel transmit data.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 SPORT Register Descriptions
Half SPORT 'B' Tx Buffer Register
The SPORT_TX_B register buffers the half SPORT's channel transmit data. This register must be loaded with the
data to be transmitted. Either a program running on the processor core may load the data into the buffer (word-byword process) or the DMA controller may automatically load the data into the buffer (DMA process).
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Transmit Buffer
Figure 16-29: SPORT_TX_B Register Diagram
Table 16-18: SPORT_TX_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
Transmit Buffer.
The SPORT_TX_B.VALUE bits hold the half SPORT's transmit data.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
16–47
Universal Asynchronous Receiver/Transmitter (UART)
17 Universal Asynchronous Receiver/Transmitter (UART)
The UART peripheral is a serial full duplex universal asynchronous receiver/ transmitter, compatible with the industry-standard 16450/16550. The serial communication follows an asynchronous protocol supporting various word
lengths, stop bits, and parity generation options. The ADuCM4050 MCU has two UART cores.
UART Features
This UART also contains interrupt handling hardware and provides a fractional divider that facilitates high accuracy
baud rate generation.
Interrupts may be generated from a number of unique events, such as data buffer full/empty, transfer error detection, and break detection.
The standard UART interface supports modem control signals. However, this UART implementation supports only
serial Tx and Rx functionalities.
The following modem inputs are tied high internally:
• UART_MSR.DCD
• UART_MSR.RI
• UART_MSR.DSR
• UART_MSR.CTS
The following modem outputs are not connected:
• UART_MCR.RTS
• UART_MCR.DTR
• UART_MCR.OUT1
• UART_MCR.OUT2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–1
UART Functional Description
UART Functional Description
The UART peripheral supports industry standard asynchronous serial communication and can transfer data through
the transmit and receive pins. It supports the word lengths from 7 to 12 bits. Transmit operation is initiated by
writing to the transmit holding register (UART_TX). Receive operation uses the same data format as the transmit
configuration, except for the number of stop bits, which is always one.
UART Block Diagram
The UART block diagram is shown below.
PCLK domain
16550 UART CORE
RXFULL
Clock
Gating
RX FIFO
PCLK
RX
PCLKg
RX LOGIC
RX FIFO
timeout
monitor
Fractional
Baud Rate
Generate
Fractional
Baud Rate
Generate
Modulation
TX
REG
I/F
APB Slave IF
TX LOGIC
TX FIFO
MODEM
CTL
Interrupt
Encoding
Figure 17-1: UART Block Diagram
UART Operations
Serial Communications
The asynchronous serial communication protocol supports the following options:
17–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
UART Operations
• 5 to 8 data bits
• 1, 2 or 1 and 1/2 stop bits
• None, or even or odd parity
• Programmable over sample rate by 4, 8, 16, 32
• Baud rate = PCLK / ((M + N/2048) × 2OSR+2 × DIV)
where,
OSR (UART_LCR2.OSR) = 0 to 3
DIV (UART_DIV) = 1 to 65535
M (UART_FBR.DIVM) = 1 to 3
N (UART_FBR.DIVN) = 0 to 2047
All data words require a start bit and at least one stop bit. This creates a range from 7 bits to 12 bits for each word.
Transmit operation is initiated by writing to the transmit holding register (UART_TX). After a synchronization delay, the data is moved to the transmit shift register where it will be shifted out at a baud (bit) rate equal to PCLK /
((M + N/2048) × 2OSR+2 × DIV) with start, stop, and parity bits appended as required. All data words begin with a
low going start bit. The transfer of the transmit holding register to the transmit shift register causes the transmit
register empty status bit (UART_LSR.THRE) to be set.
Receive operation uses the same data format as the transmit configuration, except for the number of stop bits, which
is always one. After detecting the start bit, the received word is shifted to the receive shift register. After the appropriate number of bits (including stop bits) are received, the receive shift register is transferred to the receive buffer register, after the appropriate synchronization delay, and the receive buffer register full status flag (UART_IIR.STAT) is
updated.
A sampling clock equal to 2OSR+2 times the baud rate is used to sample the data as close to the midpoint of the bit
as possible. A receive filter is also present that removes spurious pulses less than the sampling clock period.
NOTE: Data is transmitted and received least significant bit first, that is, transmit shift register, bit 0.
Baud Rate Generator
To bypass the fractional divider, set UART_FBR.FBEN = 0.
This results in a baud rate = PCLK / (2OSR+2 × DIV).
To estimate the UART_FBR.DIVN and UART_FBR.DIVM values, the fractional baud rate generator fine tunes
the baud rate if the integer UART_DIV gives an unreasonable error to the rate.
NOTE: Setting UART_DIV to 0 disables the UART logic.
The following tables show example baud rates assuming a 52 MHz, 26 MHz and 16 MHz input clock.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–3
UART Operations
Table 17-1: Baud Rate Examples Based on 52 MHz PCLK
Baud Rate
OSR
DIV
DIVM
DIVN
Actual
Error
1,000,000
3
1
1
1280
1000000
0.0%
1,500,000
3
1
1
171
1499774
-0.002%
3,000,000
2
1
1
171
2999549
-0.015%
3,500,000
1
1
1
1755
3500394
0.0011%
Table 17-2: Baud Rate Examples Based on 26 MHz PCLK
Baud Rate
OSR
DIV
DIVM
DIVN
Actual
Error
9600
3
28
3
46
9600.74
0.0077%
19200
3
14
3
46
19201.48
0.0077%
38400
3
7
3
46
38402.95
0.0077%
57600
3
14
1
15
57613.74
0.0024%
115,200
3
3
2
719
115195.6
-0.004%
230,400
3
3
1
359
230439
0.0017%
460,800
3
1
1
1563
460814
0.003%
921,600
2
1
1
1563
921628
0.003%
1,000,000
2
1
1
1280
1000000
0.0%
1,500,000
2
1
1
171
1499774
-0.002%
Table 17-3: Baud Rate Examples Based on a 16 MHz PCLK
Baud Rates
OSR
DIV
DIVM
DIVN
Actual
% Error
9600
3
17
3
131
9599.25
-0.0078%
19200
3
8
3
523
19199.04
-0.0050%
38400
3
4
3
523
38398.08
-0.0050%
57600
3
8
1
174
57605.76
0.0100%
115,200
3
2
2
348
115211.5
0.0100%
230,400
3
2
1
174
230423
0.0100%
460,800
3
1
1
174
460846.1
0.0100%
921,600
2
1
1
174
921692.2
0.0100%
1,000,000
2
1
1
0
1000000
0.0000%
1,500,000
1
1
1
683
1499816.9
-0.012%
17–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
UART Operating Modes
UART Operating Modes
The UART used by the ADuCM4050 MCU supports the following modes.
IO Mode
In this mode, the software moves the data to and from the UART. This is accomplished by interrupt service routines
that respond to the transmit and receive interrupts by either reading or writing data as appropriate. In this mode, the
software must respond within a certain time to prevent overrun errors in the receive channel.
The IO mode also requires polling the status flags to determine when it is ok to move data.
This mode is core intensive and used only if the system can tolerate the overhead. Interrupts can be disabled using
the UART interrupt enable register (UART_IEN).
Writing to the transmit holding register when it is not empty, or reading from the receive buffer register when it is
not full produces an incorrect result. In the former case, the transmit holding register is overwritten by the new word
and the previous word is never transmitted, and in the latter case, the previously received word is read again. These
errors must be avoided in software by correctly using either interrupts or status register polling. These errors are not
detected in the hardware.
DMA Mode
In this mode, user code does not move data to and from the UART. The DMA request signals to the DMA block
are generated indicating that the UART is ready to transmit or receive data. These DMA request signals can be disabled in the UART_IEN register.
UART Interrupts
The UART peripheral has one output signal to the core interrupt controller representing all Rx and Tx interrupts.
The UART interrupt identification register (UART_IIR) must be read by the software to determine the cause of
the interrupt.
In the IO mode, interrupts may be generated for the following cases:
• Receive buffer register full
• Receive overrun error
• Receive parity error
• Receive framing error
• Receive FIFO timeout if FIFO (16550) is enabled
• Break interrupt (SIN held low)
• Modem status interrupt (changes to UART_MSR.DCD, UART_MSR.RI, UART_MSR.DSR, or
UART_MSR.CTS)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–5
FIFO Mode (16550)
• Transmit holding register empty
FIFO Mode (16550)
The 16-byte deep TX FIFO and RX FIFOs are implemented so that the UART is compatible with the industrystandard 16550.
By default, the FIFOs are disabled. They are enabled by setting the UART_FCR.FIFOEN bit. When enabled, the
internal FIFOs are activated, allowing 16 bytes (and 3 bits of error data per byte in the RX FIFO) to be stored in
both receive and transmit modes. This minimizes the system overhead and maximizes the system efficiency.
The interrupt and/or DMA trigger level of the RX FIFO are programmed by the UART_FCR.RFTRIG bit. Two
DMA modes are available. The required DMA mode can be programmed using the UART_FCR.FDMAMD bit.
DMA Mode 1 only works (in burst mode) when FIFO is enabled.
Auto Baud Rate Detection (ABD)
The Auto baud detection block is used to match the baud rates of two UART devices automatically without pre
assumptions. The receiver must be enabled to detect the mode before a common baud rate is configured.
The UART_ACR.ABE bit enables the receiver to work in the Auto baud detection mode. A 20-bit counter logic
counts the number of cycles between the programmed start and end edges (rising or falling). This 20-bit counter is
stored in the UART_ASRH.CNT (8 higher bits) and UART_ASRL.CNT (12 lower bits).
Figure 17-2: Auto Baud Rate Example
An interrupt is generated once the expected edges are reached. If the counter overflows while the timeout interrupt
is enabled (the UART_ACR.TOIEN set), the block generates a timeout interrupt due to long break
(UART_ASRL.BRKTO), no valid start edge (UART_ASRL.NSETO), or no valid ending edge
(UART_ASRL.NEETO). Once the CNT is read back, the software must be aware of the effective number of bits
between active starting and ending edges (defined as CountedBits) to obtain the baud rate. CountedBits depends on
the character and the selected starting and ending edges used for Auto baud detection.
Auto baud must be disabled to clear the internal counter and re-enabled for another run (if required).
The following figures show how to configure the different parameters depending on the character and edges used.
17–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Auto Baud Rate Detection (ABD)
For example, there are three rising and falling edges, if the data byte being received is 0x0D (0b'00001101, carriage
return), in 8-bit mode without parity bit, LSB first. To count from first to last edge of the carriage return, the
UART_ACR.SEC field must be written to 1 (second edge from the start bit), and the UART_ACR.EEC field must
be written to 3 to count until the edge on the stop bit (fourth edge from the starting edge). In this case, the CountedBits between the starting edge and ending edge is 8 bits.
SEC = 1
Edge count
Data
1
2
EEC = 3
1
2
3
4
START
STOP
1
0
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
0 = 0x0D Carriage return
D7
CountedBits = 8
Figure 17-3: Auto Baud Configuration Example
It is possible to count from the start bit to the stop bit. In this case, the UART_ACR.SEC field must be written to 0
(first edge from the start bit), the UART_ACR.EEC field to 4 (fifth edge from the start edge), and CountedBits
must be 9.
SEC = 0
Edge count
Data
1
EEC = 4
1
2
3
4
5
START
STOP
1
0
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
0 = 0x0D Carriage return
D7
CountedBits = 9
Figure 17-4: Auto Baud Configuration Example
Any other character can be used for auto baud rate detection. For example, the backspace 0x08 (0b'00010000), to
measure between the first edge on the data and stop bit, the UART_ACR.SEC field is set to 1, the
UART_ACR.EEC field is set to 1, and CountedBits must be 5.
EEC = 1
SEC = 1
Edge count
Data
1
2
1
2
START
STOP
0
0
0
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
0 = 0x08 Backspace
D7
CountedBits = 5
Figure 17-5: Auto Baud Configuration Example
The 20-bit counter uses the following equation:
CNT[19:0] = CountedBits × 2OSR+2 × UART_DIV × (UART_FBR.DIVM + UART_FBR.DIVN ÷ 2048)
Based on the UART baud rate configuration, the Auto Baud Detection result can be calculated in the following way:
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–7
RS485 Half-Duplex Mode
NOTE: To reduce truncation error, the UART_FBR.DIVM field is set to 1.
if CNT < 8 × CountedBits, OSR = 0, UART_FBR.DIVN = 512 × CNT ÷ CountedBits - 2048,
else if CNT < 16 × CountedBits, OSR = 1, UART_DIV = 1, UART_FBR.DIVN = 256 ×CNT ÷ CountedBits 2048,
else if CNT < 32 × CountedBits, OSR = 2, UART_DIV = 1, UART_FBR.DIVN = 128 ×CNT ÷ CountedBits 2048,
else if CNT > = 32 × CountedBits, OSR = 3,
if CNT exactly divided by (32 × CountedBits), UART_DIV = CNT ÷ 32 ÷ CountedBits,
else UART_DIV = 2log2(CNT ÷ 32 ÷ CountedBits) //The UART_DIV field is set to nearest power of 2 to reduce truncation error.
UART_FBR.DIVN = 64 × CNT ÷ UART_DIV ÷ CountedBits - 2048
RS485 Half-Duplex Mode
To support RS485 half-duplexing, SOUT_EN is implemented. The transmit driver must be enabled when
SOUT_EN is asserted.
Figure 17-6: UART with RS485 Transceiver
Receive Line Inversion
For specific applications such as UART communication through optical link, the receive line may work at the opposite level (that is, idling at low level). The UART_CTL.RXINV register can invert the receive line for this purpose.
NOTE: Do not use Receive line inversion with RS485 applications.
17–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Clock Gating
Configure the UART_CTL.RXINV register before configuring the UART and enabling Auto Baud.
Clock Gating
The clock driving the UART logic is automatically gated off when idle, and not accessed. This automatic clock gating cannot be disabled by the UART_CTL.FORCECLKON field.
UART and Power-Down Modes
Complete the on-going UART transfers before powering down the chip into the Hibernate mode. Else, disable the
UART by clearing the UART_DIV register before going into hibernate.
NOTE: If hibernate mode is selected while a UART transfer is on, the transfer does not continue on returning from
hibernate. All the intermediate data, states, status logic in the UART are cleared. However, the TX pads (SOUT and
SOUT_EN, if pin mux is selected) may remain active in hibernate mode while transmitting.
After hibernate, the UART can be enabled by setting the UART_DIV register (if previously cleared). If DMA mode
is needed, UART_IEN [5:4] must be configured.
For a clean wake-up,
• Prior to hibernate: Disable the UART block by clearing the UART_DIV register.
Or
• After waking from hibernate: Before any UART transaction, apply a break which is at least one frame period
longer than the system wake-up time (typically, 10 μs). This ensures that the UART identifies the transaction
start condition.
The wake-up time depends on the clock sources and memory used for instruction code.
The following registers are retained through hibernate mode. Other registers and internal logic are cleared to hardware default value.
• UART_IEN.ELSI, UART_IEN.ERBFI
• UART_LCR.BRK, UART_LCR.SP, UART_LCR.EPS, UART_LCR.PEN, UART_LCR.STOP,
UART_LCR.WLS
• UART_FCR.RFTRIG, UART_FCR.FDMAMD, UART_FCR.FIFOEN
• UART_FBR.FBEN, UART_FBR.DIVM, UART_FBR.DIVN
• UART_DIV.DIV
• UART_LCR2.OSR
• UART_CTL.RXINV, UART_CTL.FORCECLK
• UART_RSC.DISTX, UART_RSC.DISRX, UART_RSC.OENSP, UART_RSC.OENP
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–9
ADuCM4050 UART Register Descriptions
ADuCM4050 UART Register Descriptions
Universal Asynchronous Receiver/Transmitter (UART) contains the following registers.
Table 17-4: ADuCM4050 UART Register List
Name
Description
UART_ACR
Auto Baud Control
UART_ASRH
Auto Baud Status (High)
UART_ASRL
Auto Baud Status (Low)
UART_CTL
UART Control Register
UART_DIV
Baud Rate Divider
UART_FBR
Fractional Baud Rate
UART_FCR
FIFO Control
UART_IEN
Interrupt Enable
UART_IIR
Interrupt ID
UART_LCR
Line Control
UART_LCR2
Second Line Control
UART_LSR
Line Status
UART_MCR
Modem Control
UART_MSR
Modem Status
UART_RFC
RX FIFO Byte Count
UART_RSC
RS485 Half-duplex Control
UART_RX
Receive Buffer Register
UART_SCR
Scratch Buffer
UART_TFC
TX FIFO Byte Count
UART_TX
Transmit Holding Register
17–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Auto Baud Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EEC (R/W)
Ending Edge Count
ABE (R/W)
Auto Baud Enable
SEC (R/W)
Starting Edge Count
DNIEN (R/W)
Enable Done Interrupt
TOIEN (R/W)
Enable Time-out Interrupt
Figure 17-7: UART_ACR Register Diagram
Table 17-5: UART_ACR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 EEC
(R/W)
Ending Edge Count.
Counted from the start edge count configured by the UART_ACR.SEC bitfield.
0 First edge Corresponds to the first edge after the starting
edge (configured in UART_ACR.SEC).
1 Second edge
2 Third edge
3 Fourth edge
4 Fifth edge
5 Sixth edge
6 Seventh edge
7 Eighth edge
8 Ninth edge
6:4 SEC
(R/W)
Starting Edge Count.
Counted from the falling edge of START bit.
0 First edge Corresponds to the falling edge of the START
bit.
1 Second edge
2 Third edge
3 Fourth edge
4 Fifth edge
5 Sixth edge
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–11
ADuCM4050 UART Register Descriptions
Table 17-5: UART_ACR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
6 Seventh edge
7 Eighth edge
2 TOIEN
Enable Time-out Interrupt.
(R/W)
0 Disable timeout interrupt
1 Enable timeout interrupt
1 DNIEN
Enable Done Interrupt.
(R/W)
0 Disable done interrupt
1 Enable done interrupt
0 ABE
(R/W)
Auto Baud Enable.
0 Disable auto baudrate
1 Enable auto baudrate
17–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Auto Baud Status (High)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNT[19:12] (R)
Auto Baud Counter Value
Figure 17-8: UART_ASRH Register Diagram
Table 17-6: UART_ASRH Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 CNT
Auto Baud Counter Value.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–13
ADuCM4050 UART Register Descriptions
Auto Baud Status (Low)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNT[11:0] (R)
Auto Baud Counter Value
DONE (RC)
Auto Baud Done Successfully
NEETO (RC)
Timed Out Due to No Valid Ending
Edge Found
BRKTO (RC)
Timed Out Due to Long Time Break
Condition
NSETO (RC)
Timed Out Due to No Valid Start Edge
Found
Figure 17-9: UART_ASRL Register Diagram
Table 17-7: UART_ASRL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:4 CNT
Auto Baud Counter Value.
(R/NW)
3 NEETO
Timed Out Due to No Valid Ending Edge Found.
(RC/NW)
2 NSETO
Timed Out Due to No Valid Start Edge Found.
(RC/NW)
1 BRKTO
Timed Out Due to Long Time Break Condition.
(RC/NW)
0 DONE
Auto Baud Done Successfully.
(RC/NW)
17–14
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
UART Control Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
REV (R)
UART Revision ID
FORCECLK (R/W)
Force UCLK on
RXINV (R/W)
Invert Receiver Line
Figure 17-10: UART_CTL Register Diagram
Table 17-8: UART_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 REV
UART Revision ID.
(R/NW)
4 RXINV
Invert Receiver Line.
(R/W)
0 Don't invert receiver line (idling high).
1 Invert receiver line (idling low).
1 FORCECLK
(R/W)
Force UCLK on.
0 UCLK automatically gated
1 UCLK always working
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–15
ADuCM4050 UART Register Descriptions
Baud Rate Divider
Internal UART baud generation counters are restarted whenever UART_DIV register accessed by writing, regardless
same or different value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIV (R/W)
Baud Rate Divider
Figure 17-11: UART_DIV Register Diagram
Table 17-9: UART_DIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 DIV
(R/W)
17–16
Baud Rate Divider.
The UART_DIV register should not be 0, which is not specified. Allowed range is 1 to
65535.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Fractional Baud Rate
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FBEN (R/W)
Fractional Baud Rate Generator Enable
DIVN (R/W)
Fractional Baud Rate N Divide Bits 0
to 2047
DIVM (R/W)
Fractional Baud Rate M Divide Bits
1 to 3
Figure 17-12: UART_FBR Register Diagram
Table 17-10: UART_FBR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 FBEN
(R/W)
12:11 DIVM
(R/W)
10:0 DIVN
Fractional Baud Rate Generator Enable.
The generating of fractional baud rate can be described by the following formula and
the final baud rate of UART operation is calculated as Baudrate = (UCLK / (2 *
(UART_FBR.DIVM + UART_FBR.DIVN/2048) * 16 * UART_DIV) )
Fractional Baud Rate M Divide Bits 1 to 3.
This bit should not be 0 when Fractional Baud Rate enabled.
Fractional Baud Rate N Divide Bits 0 to 2047.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–17
ADuCM4050 UART Register Descriptions
FIFO Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RFTRIG (R/W)
Rx FIFO Trigger Level
FIFOEN (R/W)
FIFO Enable as to Work in 16550 Mode
FDMAMD (R/W)
FIFO DMA Mode
RFCLR (W)
Clear Rx FIFO
TFCLR (W)
Clear Tx FIFO
Figure 17-13: UART_FCR Register Diagram
Table 17-11: UART_FCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 RFTRIG
(R/W)
Rx FIFO Trigger Level.
Writable only if FIFOEN=1.
0 1 byte to trig RX interrupt
1 4 byte to trig RX interrupt
2 8 byte to trig RX interrupt
3 14 byte to trig RX interrupt
3 FDMAMD
(R/W)
FIFO DMA Mode.
Writable only if FIFOEN=1.
0 In DMA mode 0, RX DMA request will be asserted
whenever there's data in RBR or RX FIFO and de-assert
whenever RBR or RX FIFO is empty; TX DMA request
will be asserted whenever THR or TX FIFO is empty
and de-assert whenever data written to.
1 in DMA mode 1, RX DMA request will be asserted
whenever RX FIFO trig level or time out reached and
de-assert thereafter when RX FIFO is empty; TX DMA
request will be asserted whenever TX FIFO is empty
and de-assert thereafter when TX FIFO is completely
filled up full.
2 TFCLR
Clear Tx FIFO.
(RX/W)
1 RFCLR
Clear Rx FIFO.
(RX/W)
17–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Table 17-11: UART_FCR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 FIFOEN
FIFO Enable as to Work in 16550 Mode.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–19
ADuCM4050 UART Register Descriptions
Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EDMAR (R/W)
DMA Requests in Receive Mode
ERBFI (R/W)
Receive Buffer Full Interrupt
EDMAT (R/W)
DMA Requests in Transmit Mode
ETBEI (R/W)
Transmit Buffer Empty Interrupt
EDSSI (R/W)
Modem Status Interrupt
ELSI (R/W)
Rx Status Interrupt
Figure 17-14: UART_IEN Register Diagram
Table 17-12: UART_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 EDMAR
DMA Requests in Receive Mode.
(R/W)
0 DMA requests disabled
1 DMA requests enabled
4 EDMAT
DMA Requests in Transmit Mode.
(R/W)
0 DMA requests are disabled
1 DMA requests are enabled
3 EDSSI
(R/W)
Modem Status Interrupt.
Interrupt is generated when any of UART_MSR.DDCD, UART_MSR.TERI,
UART_MSR.DDSR, or UART_MSR.DCTS are set.
0 Interrupt disabled
1 Interrupt enabled
2 ELSI
(R/W)
Rx Status Interrupt.
0 Interrupt disabled
1 Interrupt enabled
1 ETBEI
(R/W)
Transmit Buffer Empty Interrupt.
0 Interrupt disabled
1 Interrupt enabled
0 ERBFI
(R/W)
Receive Buffer Full Interrupt.
0 Interrupt disabled
1 Interrupt enabled
17–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Interrupt ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
FEND (R)
FIFO Enabled
NIRQ (RS)
Interrupt Flag
STAT (RC)
Interrupt Status
Figure 17-15: UART_IIR Register Diagram
Table 17-13: UART_IIR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 FEND
FIFO Enabled.
(R/NW)
0 FIFO not enabled, 16450 mode
3 FIFO enabled, 16550 mode
3:1 STAT
(RC/NW)
Interrupt Status.
When UART_IIR.NIRQ is low (active-low), this indicates an interrupt and the
UART_IIR.STAT bit decoding below is used.
0 Modem status interrupt (Read MSR register to clear)
1 Transmit buffer empty interrupt (Write to Tx register or
read IIR register to clear)
2 Receive buffer full interrupt (Read Rx register to clear)
3 Receive line status interrupt (Read LSR register to clear)
6 Receive FIFO time-out interrupt (Read Rx register to
clear)
0 NIRQ
Interrupt Flag.
(RS/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–21
ADuCM4050 UART Register Descriptions
Line Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BRK (R/W)
Set Break
WLS (R/W)
Word Length Select
SP (R/W)
Stick Parity
STOP (R/W)
Stop Bit
EPS (R/W)
Parity Select
PEN (R/W)
Parity Enable
Figure 17-16: UART_LCR Register Diagram
Table 17-14: UART_LCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
6 BRK
Set Break.
(R/W)
0 Normal TxD operation
1 Force TxD to 0
5 SP
(R/W)
Stick Parity.
Used to force parity to defined values. When set, the parity will be based on the following bit settings : UART_LCR.EPS = 1 and UART_LCR.PEN = 1, parity will be
forced to 0. UART_LCR.EPS = 0 and UART_LCR.PEN = 1, parity will be forced to
1. UART_LCR.EPS = X and UART_LCR.PEN = 0, no parity will be transmitted
0 Parity will not be forced based on Parity Select and Parity Enable bits.
1 Parity forced based on Parity Select and Parity Enable
bits.
4 EPS
(R/W)
Parity Select.
This bit only has meaning if parity is enabled (UART_LCR.PEN set).
0 Odd parity will be transmitted and checked.
1 Even parity will be transmitted and checked.
3 PEN
(R/W)
Parity Enable.
Used to control of the parity bit transmitted and checked. The value transmitted and
the value checked will be based on the settings of UART_LCR.EPS and
UART_LCR.SP.
0 Parity will not be transmitted or checked.
1 Parity will be transmitted and checked.
17–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Table 17-14: UART_LCR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 STOP
(R/W)
Stop Bit.
Used to control the number of stop bits transmitted. In all cases only the first stop bit
will be evaluated on data received.
0 Send 1 stop bit regardless of the Word Length Select bit
1 Send a number of stop bits based on the word length as
follows: WLS = 00, 1.5 stop bits transmitted (5-bit
word length) WLS = 01 or 10 or 11, 2 stop bits transmitted (6 or 7 or 8-bit word length)
1:0 WLS
(R/W)
Word Length Select.
Selects the number of bits per transmission.
0 5 bits
1 6 bits
2 7 bits
3 8 bits
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–23
ADuCM4050 UART Register Descriptions
Second Line Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
OSR (R/W)
Over Sample Rate
Figure 17-17: UART_LCR2 Register Diagram
Table 17-15: UART_LCR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 OSR
(R/W)
Over Sample Rate.
0 Over sample by 4.
1 Over sample by 8.
2 Over sample by 16.
3 Over sample by 32.
17–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Line Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
0
FIFOERR (RC)
Rx FIFO Parity Error/Frame Error/Break
Indication
DR (RC)
Data Ready
OE (RC)
Overrun Error
TEMT (R)
Transmit and Shift Register Empty
Status
PE (RC)
Parity Error
THRE (R)
Transmit Register Empty
FE (RC)
Framing Error
BI (RC)
Break Indicator
Figure 17-18: UART_LSR Register Diagram
Table 17-16: UART_LSR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 FIFOERR
(RC/NW)
6 TEMT
Rx FIFO Parity Error/Frame Error/Break Indication.
Data byte(s) in RX FIFO have either parity error, frame error or break indication. only
used in 16550 mode. Read-clear if no more error in RX FIFO.
Transmit and Shift Register Empty Status.
(R/NW)
0 Tx register has been written to and contains data to be
transmitted. Care should be taken not to overwrite its
value.
1 Tx register and the transmit shift register are empty and
it is safe to write new data to the Tx Register. Data has
been transmitted.
5 THRE
(R/NW)
Transmit Register Empty.
THRE is cleared when UART_RX is read.
0 Tx register has been written to and contains data to be
transmitted. Care should be taken not to overwrite its
value.
1 Tx register is empty and it is safe to write new data to
Tx register The previous data may not have been transmitted yet and can still be present in the shift register.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–25
ADuCM4050 UART Register Descriptions
Table 17-16: UART_LSR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 BI
(RC/NW)
Break Indicator.
If set, this bit will self clear after UART_LSR is read.
0 SIN was not detected to be longer than the maximum
word length.
1 SIN was held low for more than the maximum word
length.
3 FE
(RC/NW)
Framing Error.
If set, this bit will self clear after UART_LSR is read.
0 No invalid Stop bit was detected.
1 An invalid Stop bit was detected on a received word.
2 PE
(RC/NW)
Parity Error.
If set, this bit will self clear after UART_LSR is read.
0 No parity error was detected.
1 A parity error occurred on a received word.
1 OE
(RC/NW)
Overrun Error.
If set, this bit will self clear after UART_LSR is read.
0 Receive data has not been overwritten.
1 Receive data was overwritten by new data before Rx register was read.
0 DR
(RC/NW)
Data Ready.
This bit is cleared only by reading UART_RX. This bit will not self clear.
0 Rx register does not contain new receive data.
1 Rx register contains receive data that should be read.
17–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Modem Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
LOOPBACK (R/W)
Loopback Mode
DTR (R/W)
Data Terminal Ready
OUT2 (R/W)
Output 2
RTS (R/W)
Request to Send
OUT1 (R/W)
Output 1
Figure 17-19: UART_MCR Register Diagram
Table 17-17: UART_MCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 LOOPBACK
(R/W)
Loopback Mode.
In loop back mode, the SOUT is forced high. The modem signals are also directly
connected to the status inputs (UART_MCR.RTS to UART_MSR.CTS,
UART_MCR.DTR to UART_MSR.DSR, UART_MCR.OUT1 to UART_MSR.RI,
and UART_MCR.OUT2 to UART_MSR.DCD).
0 Normal operation - loopback disabled
1 Loopback enabled
3 OUT2
Output 2.
(R/W)
0 Force nOUT2 to a logic 1
1 Force nOUT2 to a logic 0
2 OUT1
Output 1.
(R/W)
0 Force nOUT1 to a logic 1
1 Force nOUT1 to a logic 0
1 RTS
Request to Send.
(R/W)
0 Force nRTS to a logic 1
1 Force nRTS to a logic 0
0 DTR
(R/W)
Data Terminal Ready.
0 Force nDTR to a logic 1
1 Force nDTR to a logic 0
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–27
ADuCM4050 UART Register Descriptions
Modem Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
X X X X X X X X
DCD (R)
Data Carrier Detect
DCTS (R)
Delta CTS
RI (R)
Ring Indicator
DDSR (R)
Delta DSR
DSR (R)
Data Set Ready
TERI (R)
Trailing Edge RI
CTS (R)
Clear to Send
DDCD (R)
Delta DCD
Figure 17-20: UART_MSR Register Diagram
Table 17-18: UART_MSR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 DCD
(R/NW)
Data Carrier Detect.
This bit reflects the direct status complement of the nDCD pin.
0 nDCD is currently logic high.
1 nDCD is currently logic low.
6 RI
(R/NW)
Ring Indicator.
This bit reflects the direct status complement of the nRI pin.
0 nRI is currently logic high.
1 nRI is currently logic low.
5 DSR
(R/NW)
Data Set Ready.
This bit reflects the direct status complement of the nDSR pin
0 nDSR is currently logic high
1 nDSR is currently logic low
4 CTS
(R/NW)
Clear to Send.
Reflects the direct status complement of the nCTS pin
0 nCTS is currently logic high
1 nCTS is currently logic low
17–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Table 17-18: UART_MSR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 DDCD
(R/NW)
Delta DCD.
If set, this bit will self clear after UART_MSR is read.
0 Data Carrier Detect bit has not changed state since
UART_MSR was last read
1 Data Carrier Detect bit changed state since UART_MSR
last read
2 TERI
(R/NW)
Trailing Edge RI.
If set, this bit will self clear after UART_MSR is read.
0 Ring Indicator bit has not changed from 0 to 1 since
UART_MSR last read
1 Ring Indicator bit changed from 0 to 1 since
UART_MSR last read
1 DDSR
(R/NW)
Delta DSR.
If set, this bit will self clear after UART_MSR is read.
0 Data Set Ready bit has not changed state since
UART_MSR was last read
1 Data Set Ready bit changed state since UART_MSR last
read
0 DCTS
(R/NW)
Delta CTS.
If set, this bit will self clear after UART_MSR is read.
0 Clear to send bit has not changed state since
UART_MSR was last read
1 Clear to send bit changed state since UART_MSR last
read
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–29
ADuCM4050 UART Register Descriptions
RX FIFO Byte Count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RFC (R)
Current Rx FIFO Data Bytes
Figure 17-21: UART_RFC Register Diagram
Table 17-19: UART_RFC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4:0 RFC
Current Rx FIFO Data Bytes.
(R/NW)
17–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
RS485 Half-duplex Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DISTX (R/W)
Hold off Tx When Receiving
OENP (R/W)
SOUT_EN Polarity
DISRX (R/W)
Disable Rx When Transmitting
OENSP (R/W)
SOUT_EN De-assert Before Full Stop
Bit(s)
Figure 17-22: UART_RSC Register Diagram
Table 17-20: UART_RSC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 DISTX
Hold off Tx When Receiving.
(R/W)
2 DISRX
Disable Rx When Transmitting.
(R/W)
1 OENSP
SOUT_EN De-assert Before Full Stop Bit(s).
(R/W)
0 SOUT_EN de-assert same time as full stop bit(s)
1 SOUT_EN de-assert half-bit earlier than full stop bit(s)
0 OENP
(R/W)
SOUT_EN Polarity.
0 High active.
1 Low active.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–31
ADuCM4050 UART Register Descriptions
Receive Buffer Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RBR (R)
Receive Buffer Register
Figure 17-23: UART_RX Register Diagram
Table 17-21: UART_RX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 RBR
Receive Buffer Register.
(R/NW)
17–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Scratch Buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SCR (R/W)
Scratch
Figure 17-24: UART_SCR Register Diagram
Table 17-22: UART_SCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 SCR
(R/W)
Scratch.
An 8-bit register used to store intermediate results. The value contained in
UART_SCR does not affect the UART functionality or performance. Only 8 bits of
this register are implemented. Bits [15:8] are read only and always return 0x00 when
read. Writable with any value from 0 to 255. A read will return the last value written.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–33
ADuCM4050 UART Register Descriptions
TX FIFO Byte Count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TFC (R)
Current Tx FIFO Data Bytes
Figure 17-25: UART_TFC Register Diagram
Table 17-23: UART_TFC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4:0 TFC
Current Tx FIFO Data Bytes.
(R/NW)
17–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 UART Register Descriptions
Transmit Holding Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
THR (W)
Transmit Holding Register
Figure 17-26: UART_TX Register Diagram
Table 17-24: UART_TX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 THR
Transmit Holding Register.
(RX/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
17–35
Inter-Integrated Circuit (I2C) Interface
18 Inter-Integrated Circuit (I2C) Interface
The ADuCM4050 MCU provides an Inter-Integrated Circuit (I2C) interface with both master and slave functionalities. The peripheral complies with the I2C Bus Specification, Version 2.1.
I2C Features
The I2C interface in the ADuCM4050 MCU supports the following features:
• 2-byte transmit and receive FIFOs for the master and slave.
• Support for repeated starts.
• Support for 10-bit addressing.
• Master arbitration is supported.
• Continuous read mode for the master or up to 512 bytes fixed read.
• Clock stretching supported for the slave and the master.
• Slave address setting: support for four 7-bit addresses or one 10-bit address and two 7-bit adddresses.
• Support for internal and external loopback.
• Support for DMA.
• Support for bus clear.
I2C Functional Description
This section provides information on the function of the I2C used by the ADuCM4050 MCU.
I2C Block Diagram
The I2C block diagram is shown below.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–1
I2C Operating Modes
Master
Status
Machine
SCL
APB IF
APB
Interface
Datapath
Control
Status
Block
Slave
Status
Machine
MIRPT
SIRPT
DMA IF
Datapath
External
Interface
SDA
Figure 18-1: I2C Block Diagram
The I2C bus peripheral has two pins used for data transfer. SCL is a serial clock, and SDA is a serial data pin. The
pins are configured in a wired-AND format that allows arbitration in a multimaster system.
A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial
clock divisor register. The master channel can be set to operate in fast mode (400 kHz) or standard mode (100
kHz).
The I2C bus peripherals address in the I2C bus system is programmed by the user. This ID may be changed at any
time while a transfer is not in progress. The user can set up to four slave addresses that are recognized by the peripheral. The peripheral is implemented with a 2-byte FIFO for each transmit and receive shift register. IRQ pins and
status bits in the control registers are available to signal to the MCU core when the FIFO's need to be serviced.
I2C Operating Modes
The GPIOs used for I2C communication must be configured in I2C mode before enabling the I2C peripheral.
Master Transfer Initiation
If the master enable bit (I2C_MCTL.MASEN) is set, a master transfer sequence is initiated by writing a valid value
to the I2C_ADDR1 and I2C_ADDR2 registers. If there is valid data in the I2C_MTX register, it will be the first
byte transferred in the sequence after the address byte during a write sequence.
Slave Transfer Initiation
If the slave enable bit (I2C_SCTL.SLVEN) is set, a slave transfer sequence is monitored for the device address in
the I2C_ID0, I2C_ID1, I2C_ID2, or I2C_ID3 registers. If the device address is recognized, the part participates in the slave transfer sequence.
A slave operation always starts with the assertion of one of three interrupt sources (I2C_MSTAT.MRXREQ/
I2C_SSTAT.SRXREQ, I2C_MSTAT.MTXREQ/I2C_SSTAT.STXREQ, or I2C_SSTAT.GCINT). The
18–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
I2C Operating Modes
software looks for a stop interrupt to ensure that the transaction has completed correctly and to deassert the stop
interrupt status bit.
Rx/Tx Data FIFOs
The transmit datapath for both master and slave consists of Tx FIFOs 2 bytes deep, MTX and STX, and a transmit
shifter. The transmit status bits, I2C_MSTAT.MTXF and I2C_SSTAT.STXFSEREQ indicate if there is valid data in the Tx FIFO. Data from the Tx FIFO is loaded into the Tx shifter when a serial byte begins transmission. If
the Tx FIFO is not full during an active transfer sequence, the transmit request bit (I2C_MSTAT.MTXREQ or
I2C_SSTAT.STXREQ) will assert.
In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit
(I2C_SSTAT.STXUNDR) will assert.
The master generates a stop condition if there is no data in the transmit FIFO and the master is writing data.
The receive datapath consists of a master and slave Rx FIFO, each two bytes deep, I2C_MRX and I2C_SRX. The
receive request interrupt bits (I2C_MSTAT.MRXREQ or I2C_SSTAT.SRXREQ) indicate if there is valid data in
the Rx FIFO. Data is loaded into the Rx FIFO after each byte is received.
If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit (I2C_MSTAT.MRXOVR
or I2C_SSTAT.SRXOVR) will assert.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–3
I2C Operating Modes
Prior to this, I2C_SCTL.SLVEN, I2C_SCTL.IENRX, I2C_SCTL.IENTX,
and I2C_SCTL.IENSTOP must be set. If necessary,
set I2C_SCTL.ADR10EN and I2C_SCTL.EARLYTXR
Write Read
to from Slave
Start
Wait for
IRQ
Read I2C_SSTAT
I2C_SSTAT.SRXREQ asserted?
N
Y
Read byte of the
indirect address
from I2C_SRX
All of indirect address
received?
N
Y
I2C_SSTAT.STOP asserted?
Wait for
IRQ
I2C_SSTAT.SRXREQ asserted?
N
Read I2C_SSTAT
Y
I2C_SSTAT.SRXREQ asserted?
N
Verify which source
asserted IRQ and
take appropriate
action
N
Read a byte of data
from I2C_SRX
Y
Go to Read
Y
Using indirect address already received, read a
byte from memory and write it to I2C_STX
Slave Write
Finish
Wait for
IRQ
Read I2C_SSTAT
I2C_SSTAT.STXREQ asserted?
N
Y
I2C_SSTAT.STOP asserted?
Write the next byte of
data to I2C_STX
N
Y
Flush salve Tx FIFO
(Redundant data may be left)
Verify which source
caused the IRQ and
take action (for example,
2nd repeated start
during a read)
Slave Read
Complete
Figure 18-2: Slave Read/Write Flow
No Acknowledge from Master
When receiving data, the master responds with a NACK if its FIFO is full and an attempt is made to write another
byte to the FIFO. This last byte received is not written to the FIFO and is lost.
18–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
I2C Operating Modes
No Acknowledge from Slave
If the slave does not want to acknowledge a read access, simply not writing data into the slave transmit FIFO results
in a NACK.
If the slave does not want to acknowledge a master write, assert the I2C_SCTL.NACK bit in the slave control register.
Normally, the slave will ACK all bytes written into the receive FIFO. If the receive FIFO fills up, the slave cannot
write further bytes to it, and it will not acknowledge the byte that it was not written to the FIFO. Then, the master
must stop the transaction.
The slave does not acknowledge a matching device address if the direction bit is 1 (read) and the transmit FIFO is
empty. Therefore, the microcontroller has less time to respond to a slave transmit request and the assertion of ACK.
It is recommended to assert the I2C_SCTL.EARLYTXR bit.
General Call
If the general call enable bit (I2C_SCTL.GCEN) and slave enable bit (I2C_SCTL.SLVEN) are set, the device
responds to a general call. If the second byte of the general call is 0x06, the I2C interface (master and slave) is reset.
The general call interrupt status bit (I2C_SSTAT.GCINT) is asserted and general call ID bits
(I2C_SSTAT.GCID) are set to 0x1. User code must reset the entire system or re-enable the I2C interface.
If the second byte is 0x04(write programmable part of slave address by hardware), the general call interrupt status bit
(I2C_SSTAT.GCINT) is asserted and general call ID (I2C_SSTAT.GCID) is set to 0x2.
The general call interrupt status bit (I2C_SSTAT.GCINT) gets set on any general call after the second byte is
received. User code must ensure correct actions such as reprogramming the device address and so on.
If I2C_SCTL.GCEN is asserted, the slave always acknowledges the first byte of a general call. It acknowledges the
second byte of a general call if the second byte is 0x04 or 0x06, or if the second byte is a hardware general call, and
I2C_SCTL.HGCEN is asserted.
The I2C_ALT register contains an alternate device ID for the hardware general call sequence. If the
I2C_SCTL.HGCEN, I2C_SCTL.GCEN, and I2C_SCTL.SLVEN bits are set, the device recognizes a hardware
general call. When a general call sequence is issued, and the second byte of the sequence is identical to ALT, the
hardware call sequence is recognized for the device.
Generation of Repeated Starts by Master
The master generates a repeated start if the first master address byte register is written while the master is still busy
with a transaction. Once the state machine has started to transmit the device address, it is then safe to write to the
first master address byte register.
For instance, if a write-repeated start-read/write transaction is required, write to the first master address byte register
after the state machine starts to transmit the device address, or after the first TXREQ interrupt is received. When
the transmit FIFO empties, a repeated start is generated.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–5
I2C Operating Modes
Similarly, if a read-repeated start-read/write transaction is required, write to the first master address byte register after
the state machine starts to transmit the device address, or after the first RXREQ interrupt is received. When the
requested receive count is reached, a repeated start is generated.
DMA Requests
Four DMA channels (two for the master - MAS_DMA_RX_REQ and MAS_DMA_TX_REQ, and two for the
slave - SLV_DMA_RX_REQ and SLV_DMA_TX_REQ) are available. The DMA enable bits are provided in the
I2C_SCTL.STXDMA, I2C_SCTL.SRXDMA, I2C_MCTL.MTXDMA, and I2C_MCTL.MRXDMA registers.
I2C Reset Mode
The slave state machine is reset when I2C_SCTL.SLVEN is written to 0, and the master state machine is reset
when I2C_MCTL.MASEN is written to 0.
I2C Test Modes
The device can be placed in an internal loopback mode by setting the I2C_MCTL.LOOPBACK bit. There are four
FIFOs (master Tx and Rx and slave Tx and Rx); therefore in effect, the I2C peripheral can be setup to talk to itself.
External loopback can be performed if the master is setup to address the address of the slave.
I2C Low-Power Mode
If the master and slave are both disabled (I2C_MCTL.MASEN = I2C_SCTL.SLVEN = 0), the device is in its
lowest power mode.
Auto Clock Stretching
Automatic clock stretching pauses a transaction by holding the SCL line low. The transaction cannot continue until
the line is high.
An I2C slave may receive data at a faster rate, but might need more time to store the received byte or prepare another byte for transmission. Slaves can then hold the SCL line low after reception and acknowledgment of a byte. This
forces the master into a wait state until the slave is ready for the next byte transfer.
In the case where the MCU runs at a low frequency or the I2C interrupt has low priority, the automatic clock
stretching feature can be used to hold the I2C bus until the I2C interrupt has been processed.
I2C Bus Clear Operation
In the scenario where the external slave holds SDA low to transmit a 0 (or ACK), it does not release SDA until it
gets another falling edge on SCL. As a result, the bus hangs. If the I2C master initiates a new transfer, it hits an
arbitration lost condition as SDA does not match the address sent.
If the master lost arbitration when the I2C_MCTL.BUSCLR bit is set, the master sends out extra nine SCL cycles
so that the slave holding the SDA line can release it anywhere before those nine SCL cycles. If the
I2C_MCTL.STOPBUSCLR bit is asserted, the master stops sending the SCL clocks once SDA is released.
18–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
I2C Operating Modes
Power-down Considerations
Consider the following when the part is being powered down to hibernate mode. If the master/slave is IDLE (which
can be known from the respective status registers), it can be immediately disabled by clearing I2C_MCTL.MASEN/
I2C_SCTL.SLVEN bits in the master/slave control registers respectively.
If they are active, there are four cases:
• I2C is a master and it does Rx:
In this case, the device receives data based on the count programmed in the I2C_MRXCNT register. It would
be in continuous read-mode if the I2C_MRXCNT.EXTEND bit is set. To stop the read transfer, clear the
I2C_MRXCNT.EXTEND bit and assign the I2C_MRXCNT register with I2C_MCRXCNT.VALUE + 1,
where I2C_MCRXCNT.VALUE gives the current read count.
"+1" signifies that there must be some room for the completion. If the newly programmed value is less than the
current count, it receives until the current count overflows and reaches the programmed count. This ends the
transfer after receiving the next byte. Once the transaction complete interrupt is received, the core must disable
the master by clearing the I2C_MCTL.MASEN bit.
• I2C is a master and it does Tx:
The software must flush the Tx-FIFO by setting the I2C_STAT.MFLUSH bit, and disable Tx-request by
clearing the I2C_MCTL.IENMTX bit. This ends the current transfer after transmitting the byte in progress.
When the transaction complete interrupt is received, it must clear I2C_MCTL.MASEN bit.
NOTE: Disabling the master before completion can cause the bus to hang indefinitely.
• I2C is a slave and it does Rx:
The software must set the I2C_SCTL.NACK bit. This gives a NACK for the next communication, after
which, the external master has to STOP. On receiving the STOP interrupt, the core must disable the slave by
clearing I2C_SCTL.SLVEN bit.
• I2C is a slave and it does Tx:
Once the Slave transmit starts, it cannot NACK any further transaction (ACK is driven only by the master).
So, it has to wait until the external master issues a STOP condition. After receiving the STOP interrupt, the
slave can be disabled. This is a clean way to exit. However, if the slave has to be disabled immediately, then it
can be done only at the cost of wrong data getting transmitted (all FFs). This is because the SDA line is not
driven anymore and pulled up during the data phase. In this case, the bus does not hang.
I2C Data Transfer
The I2C peripheral can be programmed for data transfer through both core and DMA modes. There are dedicated
DMA channels for master and slave functionalities. Refer to the Direct Memory Access (DMA) for the DMA channel numbers.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–7
I2C Interrupts and Exceptions
I2C Interrupts and Exceptions
The I2C block can generate interrupts under various conditions in master and slave modes.
ADuCM4050 I2C Register Descriptions
I2C Master/Slave (I2C) contains the following registers.
Table 18-1: ADuCM4050 I2C Register List
Name
Description
I2C_ADDR1
Master Address Byte 1
I2C_ADDR2
Master Address Byte 2
I2C_ALT
Hardware General Call ID
I2C_ASTRETCH_SCL
Automatic Stretch SCL
I2C_BYT
Start Byte
I2C_DIV
Serial Clock Period Divisor
I2C_ID0
First Slave Address Device ID
I2C_ID1
Second Slave Address Device ID
I2C_ID2
Third Slave Address Device ID
I2C_ID3
Fourth Slave Address Device ID
I2C_MCTL
Master Control
I2C_MCRXCNT
Master Current Receive Data Count
I2C_MRX
Master Receive Data
I2C_MRXCNT
Master Receive Data Count
I2C_MSTAT
Master Status
I2C_MTX
Master Transmit Data
I2C_SCTL
Slave Control
I2C_SHCTL
Shared Control
I2C_SRX
Slave Receive
I2C_SSTAT
Slave I2C Status/Error/IRQ
I2C_STAT
Master and Slave FIFO Status
I2C_STX
Slave Transmit
I2C_TCTL
Timing Control Register
18–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Master Address Byte 1
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Address Byte 1
Figure 18-3: I2C_ADDR1 Register Diagram
Table 18-2: I2C_ADDR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Address Byte 1.
If a 7-bit address is required, Bit 7 to Bit 1 of I2C_ADDR1.VALUE are programmed
with the address, and Bit 0 of I2C_ADDR1.VALUE is programmed with the direction (read or write).
If a 10-bit address is required, Bit 7 to Bit 3 of I2C_ADDR1.VALUE are programmed with 11110, Bit 2 to Bit 1 of I2C_ADDR1.VALUE are programmed with the 2
MSBs of the address, and Bit 0 of I2C_ADDR1.VALUE is programmed to 0.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–9
ADuCM4050 I2C Register Descriptions
Master Address Byte 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Address Byte 2
Figure 18-4: I2C_ADDR2 Register Diagram
Table 18-3: I2C_ADDR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
18–10
Address Byte 2.
This register is only required when addressing a slave with a 10-bit address. Bit 7 to Bit
0 of I2C_ADDR2.VALUE are programmed with the lower 8 bits of the address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Hardware General Call ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ID (R/W)
Slave Alt
Figure 18-5: I2C_ALT Register Diagram
Table 18-4: I2C_ALT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 ID
(R/W)
Slave Alt.
This register is used in conjunction with I2C_SCTL.HGCEN to match a master generating a hardware general call. It is used when a master device cannot be programmed
with a slave address and the slave has to recognize the master address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–11
ADuCM4050 I2C Register Descriptions
Automatic Stretch SCL
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLVTMO (R)
Slave Automatic Stretch Timeout
MST (R/W)
Master Automatic Stretch Mode
MSTTMO (R)
Master Automatic Stretch Timeout
SLV (R/W)
Slave Automatic Stretch Mode
Figure 18-6: I2C_ASTRETCH_SCL Register Diagram
Table 18-5: I2C_ASTRETCH_SCL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 SLVTMO
(R/NW)
8 MSTTMO
(R/NW)
7:4 SLV
(R/W)
Slave Automatic Stretch Timeout.
Asserts when slave automatic stretch timeout occurs and gets cleared when the bit is
read.
Master Automatic Stretch Timeout.
Asserts when master automatic stretch timeout occurs and gets cleared when the bit is
read."
Slave Automatic Stretch Mode.
It defines the automatic stretch mode for slave. As a slave transmitter, SCL clock is automatically stretched start from the negative edge of SCL, when slave Tx FIFO is empty, before send ACK/NACK for address byte, or before send data for data byte.
Stretching stops when slave Tx FIFO is no longer empty or timeout occurs. As a slave
receiver, SCL clock is automatically stretched start from the negative edge of SCL,
when slave Rx FIFO is overflow, before send ACK/NACK. Stretching stops when slave
Rx FIFO is no longer overflow or timeout occurs.
Slave clock stretch mode is automatically disabled when slv_txint_clr is asserted.
Stretch mode will restore the old value after the master transmit interrupt is cleared.
Note: When this bit is 4b0000, I2C_SCTL.EARLYTXR must be set to 1. Otherwise, CPU has no time to service slave transmit interrupt when receive address and
read request.
18–12
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Table 18-5: I2C_ASTRETCH_SCL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 MST
(R/W)
Master Automatic Stretch Mode.
It defines the automatic stretch mode for master. Stretching means hold SCL line low,
then theres more time to service the interrupt. And use a timeout to avoid bus lockup.
0000: no SCL clock stretching
0001: stretch SCL up to 2^1 = 2 bit-times
0010: stretch SCL up to 2^2 = 4 bit-times
1110: stretch SCL up to 2^14 bit-times
1111: stretch SCL up to infinity (no timeout)
Bit time is decided by I2C_DIV.HIGH + I2C_DIV.LOW, and count by PCLK.
Maximum timeout = 2^14/400 kHz = 40 ms. Compatible with SMBus, which has a
timeout of 35 ms.
As a master transmitter, SCL clock is automatically stretched start from the negative
edge of SCL, when master Tx FIFO is empty, before send data. And stretching will
stop when master Tx FIFO is no longer empty or timeout occurs.
As a master receiver, SCL clock is automatically stretched start from the negative edge
of SCL, when master Rx FIFO is overflow, before ACK/NACK. And stretching will
stop when master Rx FIFO is no longer overflow or timeout occurs.
Master clock stretch mode will be automatically disabled when mas_txint_clr is asserted or a new address is written. Stretch mode restores the old value after mas_txint_clr
is cleared or the address is loaded (RESTART is sent).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–13
ADuCM4050 I2C Register Descriptions
Start Byte
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SBYTE (R/W)
Start Byte
Figure 18-7: I2C_BYT Register Diagram
Table 18-6: I2C_BYT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 SBYTE
(R/W)
18–14
Start Byte.
Used to generate a start byte at the start of a transaction. To generate a start byte followed by a normal address, first write to I2C_BYT.SBYTE then write to the address
register (I2C_ADDR1). This will drive the byte written in I2C_BYT.SBYTE on to
the bus followed by a repeated start. This register can be used to drive any byte on to
the I2C bus followed by a repeated start (not just a start byte 00000001).
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Serial Clock Period Divisor
15 14 13 12 11 10 9
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
1
1
1
HIGH (R/W)
Serial Clock High Time
LOW (R/W)
Serial Clock Low Time
Figure 18-8: I2C_DIV Register Diagram
Table 18-7: I2C_DIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 HIGH
(R/W)
Serial Clock High Time.
This register controls the clock high time. The timer is driven by the core clock
(UCLK). Use the following equation to derive the required high time.
I2C_DIV.HIGH = ( REQD_HIGH_TIME/PCLK_PERIOD ) - 2
For example, to generate a 400 kHz SCL with a low time of 1300ns and a high time of
1200ns, with a core clock frequency 50 MHz:
LOTIME = 1300 ns/20 ns - 1 = 0x40 (64 decimal)
I2C_DIV.HIGH = 1200 ns/20 ns - 2 = 0x3A (58 decimal).
This register is reset to 0x1F which gives an SCL high time of 33 PCLK ticks. tHD:
STA is also determined by the I2C_DIV.HIGH. tHD: STA = (HIGH-1) x pclk_period.
As tHD:STA must be 600 ns, with UCLK = 50 MHz the minimum value for
I2C_DIV.HIGH is 31. This gives an SCL high time of 660 ns.
7:0 LOW
(R/W)
Serial Clock Low Time.
This register controls the clock low time. The timer is driven by the core clock
(UCLK). Use the following equation to derive the required low time.
I2C_DIV.LOW = ( REQD_LOW_TIME/PCLK_PERIOD ) - 1
This register is reset to 0x1F, which gives an SCL low time of 32 PCLK ticks.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–15
ADuCM4050 I2C Register Descriptions
First Slave Address Device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave Device ID 0
Figure 18-9: I2C_ID0 Register Diagram
Table 18-8: I2C_ID0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
18–16
Slave Device ID 0.
I2C_ID0.VALUE[7:1] is programmed with the device ID. I2C_ID0.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10-bit address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Second Slave Address Device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave Device ID 1
Figure 18-10: I2C_ID1 Register Diagram
Table 18-9: I2C_ID1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Slave Device ID 1.
I2C_ID1.VALUE[7:1] is programmed with the device ID. I2C_ID1.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10-bit address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–17
ADuCM4050 I2C Register Descriptions
Third Slave Address Device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave Device ID 2
Figure 18-11: I2C_ID2 Register Diagram
Table 18-10: I2C_ID2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
18–18
Slave Device ID 2.
I2C_ID2.VALUE[7:1] is programmed with the device ID. I2C_ID2.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10-bit address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Fourth Slave Address Device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave Device ID 3
Figure 18-12: I2C_ID3 Register Diagram
Table 18-11: I2C_ID3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Slave Device ID 3.
I2C_ID3.VALUE[7:1] is programmed with the device ID. I2C_ID3.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10-bit address.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–19
ADuCM4050 I2C Register Descriptions
Master Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STOPBUSCLR (R/W)
Prestop Bus Clear
MASEN (R/W)
Master Enable
BUSCLR (R/W)
Bus-Clear Enable
COMPLETE (R/W)
Start Back-off Disable
MTXDMA (W)
Enable Master Tx DMA Request
LOOPBACK (R/W)
Internal Loopback Enable
MRXDMA (W)
Enable Master Rx DMA Request
STRETCHSCL (R/W)
Stretch SCL Enable
MXMITDEC (R/W)
Decrement Master Tx FIFO Status When
a Byte Txed
IENMRX (R/W)
Receive Request Interrupt Enable
IENMTX (R/W)
Transmit Request Interrupt Enable
IENCMP (R/W)
Transaction Completed (or Stop Detected)
Interrupt Enable
IENALOST (R/W)
Arbitration Lost Interrupt Enable
IENACK (R/W)
ACK Not Received Interrupt Enable
Figure 18-13: I2C_MCTL Register Diagram
Table 18-12: I2C_MCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 STOPBUSCLR
(R/W)
12 BUSCLR
(R/W)
11 MTXDMA
(RX/W)
10 MRXDMA
(RX/W)
18–20
Prestop Bus Clear.
This bit should be used in conjunction with I2C_MCTL.BUSCLR. If this bit is set,
the master will stop sending any more SCL clocks if SDA is released before 9 SCL cycles.
Bus-Clear Enable.
If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra
SCL cycles if the arbitration was lost. This bit is added to come out of a SDA-stuck
situation due to a misbehaving slave and hence it should be used with caution. It
should be set only when there is no other active I2C master.
Enable Master Tx DMA Request.
Set to 1 by user code to enable I2C master DMA Tx requests. Cleared by user code to
disable DMA mode.
Enable Master Rx DMA Request.
Set to 1 by user code to enable I2C master DMA Rx requests. Cleared by user code to
disable DMA mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Table 18-12: I2C_MCTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
9 MXMITDEC
(R/W)
8 IENCMP
(R/W)
7 IENACK
Decrement Master Tx FIFO Status When a Byte Txed.
Decrement master TX FIFO status when a byte has been transmitted. If set to 1, the
master transmit FIFO status is decremented when a byte has been transmitted. If set to
0, the master transmit FIFO status is decremented when the byte is unloaded from the
FIFO into a shadow register at the start of byte transmission.
Transaction Completed (or Stop Detected) Interrupt Enable.
Transaction completed interrupt enable. When asserted an interrupt is generated when
a STOP is detected.
ACK Not Received Interrupt Enable.
(R/W)
6 IENALOST
Arbitration Lost Interrupt Enable.
(R/W)
5 IENMTX
Transmit Request Interrupt Enable.
(R/W)
4 IENMRX
Receive Request Interrupt Enable.
(R/W)
3 STRETCHSCL
(R/W)
2 LOOPBACK
(R/W)
1 COMPLETE
(R/W)
0 MASEN
(R/W)
Stretch SCL Enable.
Setting this bit tells the device if SCL is 0 hold it at 0; or if SCL is 1 then when it next
goes to 0 hold it at 0.
Internal Loopback Enable.
When this bit is set, SCL and SDA lines are muxed onto their corresponding inputs.
Note that is also possible for the master to loop back a transfer to the slave as long as
the device address corresponds, i.e. external loopback.
Start Back-off Disable.
Setting this bit enables the device to compete for ownership even when another device
is driving a start condition.
Master Enable.
When the bit is 1 the master is enabled. When the bit is 0 all master state machine
flops are held in reset and the master is disabled. The master should be disabled when
not in use as this will gate the clock to the master and save power. This bit should not
be cleared until a transaction has completed, see the I2C_MSTAT.TCOMP. APB
writable register bits are not reset by this bit. Cleared by default.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–21
ADuCM4050 I2C Register Descriptions
Master Current Receive Data Count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Current Receive Count
Figure 18-14: I2C_MCRXCNT Register Diagram
Table 18-13: I2C_MCRXCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/NW)
18–22
Current Receive Count.
This register gives the total number of bytes received. If 256 bytes are requested, this
register will read 0 when the transaction is completed.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Master Receive Data
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Master Receive Register
Figure 18-15: I2C_MRX Register Diagram
Table 18-14: I2C_MRX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/NW)
Master Receive Register.
This register allows access to the receive data FIFO. The FIFO can hold 2 bytes.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–23
ADuCM4050 I2C Register Descriptions
Master Receive Data Count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EXTEND (R/W)
Extended Read
VALUE (R/W)
Receive Count
Figure 18-16: I2C_MRXCNT Register Diagram
Table 18-15: I2C_MRXCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 EXTEND
(R/W)
7:0 VALUE
(R/W)
18–24
Extended Read.
Use this bit if greater than 256 bytes are required for a read. For example, to receive
412 bytes write 1 to I2C_MRXCNT.EXTEND. Wait for the first byte to be received,
then check the I2C_MCRXCNT register for every byte received. When
I2C_MRXCNT.VALUE returns to 0, 256 bytes have been received. Then write
0x09C to the I2C_MRXCNT register.
Receive Count.
Program the number of bytes required minus one to this register. If just 1 byte is required write 0 to this register. If greater than 256 bytes are required then use
I2C_MRXCNT.EXTEND.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Master Status
15 14 13 12 11 10 9
0
1
1
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SCLFILT (R)
State of SCL Line
MTXF (R)
Master Transmit FIFO Status
SDAFILT (R)
State of SDA Line
MTXREQ (R/W)
Master Transmit Request/Clear Master
Transmit Interrupt
MTXUNDR (RC)
Master Transmit Underflow
MRXREQ (R)
Master Receive Request
MSTOP (RC)
STOP Driven by This I2C Master
NACKADDR (RC)
ACK Not Received in Response to an
Address
LINEBUSY (R)
Line is Busy
ALOST (RC)
Arbitration Lost
MRXOVR (RC)
Master Receive FIFO Overflow
MBUSY (R)
Master Busy
TCOMP (RC)
Transaction Complete or Stop Detected
NACKDATA (RC)
ACK Not Received in Response to Data
Write
Figure 18-17: I2C_MSTAT Register Diagram
Table 18-16: I2C_MSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 SCLFILT
(R/NW)
13 SDAFILT
(R/NW)
12 MTXUNDR
(RC/NW)
11 MSTOP
(RC/NW)
State of SCL Line.
This bit is the output of the glitch-filter on SCL. SCL is always pulled high when undriven.
State of SDA Line.
This bit is the output of the glitch-filter on SDA. SDA is always pulled high when undriven.
Master Transmit Underflow.
Asserts when the I2C master ends the transaction due to Tx FIFO empty condition.
This bit is asserted only when the I2C_MCTL.IENMTX bit is set.
STOP Driven by This I2C Master.
Asserts when this I2C master drives a STOP condition on the I2C bus. This bit, when
asserted, can indicate a Transaction completion, Tx-underflow, Rx-overflow or a
NACK by the slave. This is different from the I2C_MSTAT.TCOMP as this bit is not
asserted when the STOP condition occurs due to any other I2C master. No interrupt
is generated for the assertion of this bit. However, if I2C_MCTL.IENCMP = 1, every
STOP condition will generate an interrupt and this bit can be read. When this bit is
read, it will clear status.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–25
ADuCM4050 I2C Register Descriptions
Table 18-16: I2C_MSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 LINEBUSY
(R/NW)
9 MRXOVR
(RC/NW)
8 TCOMP
(RC/NW)
7 NACKDATA
(RC/NW)
6 MBUSY
(R/NW)
5 ALOST
(RC/NW)
4 NACKADDR
(RC/NW)
3 MRXREQ
(R/NW)
2 MTXREQ
(R/W)
18–26
Line is Busy.
Asserts when a START is detected on the I2C bus. De-asserts when a STOP is detected on the I2C bus.
Master Receive FIFO Overflow.
Asserts when a byte is written to the receive FIFO when the FIFO is already full.
When the bit is read it will clear status.
Transaction Complete or Stop Detected.
Transaction complete. This bit will assert when a STOP condition is detected on the
I2C bus. If I2C_MCTL.IENCMP = 1, an interrupt will be generated when this bit
asserts. This bit will only assert if the master is enabled (I2C_MCTL.MASEN = 1).
This bit should be used to determine when it is safe to disable the master. It can also be
used to wait for another master transaction to complete on the I2C bus when this master looses arbitration. When this bit is read it will clear status. This bit can drive an
interrupt.
ACK Not Received in Response to Data Write.
This bit will assert when an ACK is not received in response to a data write transfer. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. This
bit can drive an interrupt. This bit is cleared on a read of the I2C_MSTAT register.
Master Busy.
This bit indicates that the master state machine is servicing a transaction. It will be
clear if the state machine is idle or another device has control of the I2C bus.
Arbitration Lost.
This bit will assert if the master loses arbitration. If I2C_MCTL.IENALOST = 1, an
interrupt will be generated when this bit asserts. This bit is cleared on a read of the
I2C_MSTAT register. This bit can drive an interrupt.
ACK Not Received in Response to an Address.
This bit will assert if an ACK is not received in response to an address. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. This
bit is cleared on a read of the I2C_MSTAT register. This bit can drive an interrupt.
Master Receive Request.
This bit will assert when there is data in the receive FIFO. If I2C_MCTL.IENMRX =
1, an interrupt will be generated when this bit asserts. This bit can drive an interrupt.
Master Transmit Request/Clear Master Transmit Interrupt.
When read is master transmit request; when write is clear master transmit interrupt
(mas_txirq_clr) bit. This bit will assert when the direction bit is 0 and transmit FIFO
is not full. If I2C_MCTL.IENMTX = 1, an interrupt will be generated when this bit
asserts. When this bit is written to 1, master transmit interrupt and clock stretching
will be cleared.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Table 18-16: I2C_MSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 MTXF
(R/NW)
Master Transmit FIFO Status.
These 2 bits show the master transmit FIFO status.
0 FIFO Empty.
2 1 byte in FIFO.
3 FIFO Full.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–27
ADuCM4050 I2C Register Descriptions
Master Transmit Data
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Master Transmit Register
Figure 18-18: I2C_MTX Register Diagram
Table 18-17: I2C_MTX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
18–28
Master Transmit Register.
For test and debug purposes, when read, this register returns the byte that is currently
being transmitted by the master. That is a byte written to the transmit register can be
read back some time later when that byte is being transmitted on the line. This register
allows access to the transmit data FIFO. The FIFO can hold 2 bytes.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Slave Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STXDMA (R/W)
Enable Slave Tx DMA Request
SLVEN (R/W)
Slave Enable
SRXDMA (R/W)
Enable Slave Rx DMA Request
ADR10EN (R/W)
Enabled 10-bit Addressing
IENREPST (R/W)
Repeated Start Interrupt Enable
GCEN (R/W)
General Call Enable
STXDEC (R/W)
Decrement Slave Tx FIFO Status When
a Byte is Txed
HGCEN (R/W)
Hardware General Call Enable
GCSBCLR (W)
General Call Status Bit Clear
IENSTX (R/W)
Slave Transmit Request Interrupt Enable
EARLYTXR (R/W)
Early Transmit Request Mode
IENSRX (R/W)
Slave Receive Request Interrupt Enable
NACK (R/W)
NACK Next Communication
IENSTOP (R/W)
Stop Condition Detected Interrupt Enable
Figure 18-19: I2C_SCTL Register Diagram
Table 18-18: I2C_SCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 STXDMA
(R/W)
13 SRXDMA
(R/W)
12 IENREPST
(R/W)
11 STXDEC
(R/W)
10 IENSTX
Enable Slave Tx DMA Request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to
disable DMA mode.
Enable Slave Rx DMA Request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to
disable DMA mode.
Repeated Start Interrupt Enable.
If 1 an interrupt will be generated when the I2C_SSTAT.REPSTART status bit asserts. If 0 an interrupt will not be generated when the I2C_SSTAT.REPSTART status bit asserts.
Decrement Slave Tx FIFO Status When a Byte is Txed.
Decrement Slave Tx FIFO status when a byte has been transmitted. If set to 1, the
transmit FIFO status is decremented when a byte has been transmitted. If set to 0, the
transmit FIFO status is decremented when the byte is unloaded from the FIFO into a
shadow register at the start of byte transmission.
Slave Transmit Request Interrupt Enable.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–29
ADuCM4050 I2C Register Descriptions
Table 18-18: I2C_SCTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
9 IENSRX
Slave Receive Request Interrupt Enable.
(R/W)
8 IENSTOP
Stop Condition Detected Interrupt Enable.
(R/W)
7 NACK
(R/W)
5 EARLYTXR
(R/W)
4 GCSBCLR
(RX/W)
3 HGCEN
(R/W)
2 GCEN
(R/W)
1 ADR10EN
(R/W)
0 SLVEN
(R/W)
18–30
NACK Next Communication.
If this bit is set the next communication will be NACK 'ed. This could be used for
example if during a 24xx style access, an attempt was made to write to a 'read only' or
nonexisting location in system memory. That is the indirect address in a 24xx style
write pointed to an unwritable memory location.
Early Transmit Request Mode.
Setting this bit enables a transmit request just after the positive edge of the direction
bit SCL clock pulse.
General Call Status Bit Clear.
The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are cleared when a '1' is
written to this bit. The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are not
reset by anything other than a write to this bit or a full reset.
Hardware General Call Enable.
When this bit and the I2C_SCTL.GCEN bit are set the device after receiving a general call, address 00h and a data byte checks the contents of the I2C_ALT against the
receive shift register. If they match the device has received a 'hardware general call'.
This is used if a device needs urgent attention from a master device without knowing
which master it needs to turn to. This is a call "to whom it may concern". The device
that requires attention embeds its own address into the message. The LSB of the
I2C_ALT register should always be written to a 1, as per I2C January 2000 specification.
General Call Enable.
This bit enables the I2C slave to ACK an I2C general call, address 0x00 (Write).
Enabled 10-bit Addressing.
If this bit is clear, the slave can support four slave addresses, programmed in I2C_ID0
to I2C_ID0. When this bit is set, 10 bit addressing is enabled. One 10 bit address is
supported by the slave and is stored in I2C_ID0 and I2C_ID1, where I2C_ID0
contains the first byte of the address and the upper 5 bits must be programmed to
11110. I2C_ID2 and I2C_ID3 can be programmed with 7 bit addresses at the
same time.
Slave Enable.
When '1' the slave is enabled. When '0' all slave state machine flops are held in reset
and the slave is disabled. Note that APB writable register bits are not reset.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Shared Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RST (W)
Reset START STOP Detect Circuit
Figure 18-20: I2C_SHCTL Register Diagram
Table 18-19: I2C_SHCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 RST
(RX/W)
Reset START STOP Detect Circuit.
Writing a 1 to this bit will reset the SCL and SDA synchronisers, the START and
STOP detect circuit and the LINEBUSY detect circuit. These circuits are not reset
when both the master and slave are disabled as LINEBUSY needs to assert even when
the master is not enabled. It should only be necessary to reset these circuits after a
power on reset in case SCL/SDA do not power up cleanly. Reading this bit will always
read back '0'.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–31
ADuCM4050 I2C Register Descriptions
Slave Receive
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Slave Receive Register
Figure 18-21: I2C_SRX Register Diagram
Table 18-20: I2C_SRX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
Slave Receive Register.
(R/NW)
18–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Slave I2C Status/Error/IRQ
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
START (R)
Start and Matching Address
STXFSEREQ (R/W)
Slave Tx FIFO Status or Early Request
REPSTART (RC)
Repeated Start and Matching Address
STXUNDR (RC)
Slave Transmit FIFO Underflow
IDMAT (R)
Device ID Matched
STXREQ (RC)
Slave Transmit Request/Slave Transmit
Interrupt
STOP (RC)
Stop After Start and Matching Address
SRXREQ (RC)
Slave Receive Request
GCID (R)
General ID
SRXOVR (RC)
Slave Receive FIFO Overflow
GCINT (R)
General Call Interrupt
NOACK (RC)
ACK Not Generated by the Slave
SBUSY (R)
Slave Busy
Figure 18-22: I2C_SSTAT Register Diagram
Table 18-21: I2C_SSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 START
(R/NW)
13 REPSTART
(RC/NW)
12:11 IDMAT
(R/NW)
Start and Matching Address.
This bit is asserted if a start is detected on SCL/SDA and the device address matched,
or a general call(GC - 0000_0000) code is received and GC is enabled, or a High
Speed (HS - 0000_1XXX) code is received, or a start byte (0000_0001) is received. It
is cleared on receipt of either a stop or start condition.
Repeated Start and Matching Address.
This bit is asserted if I2C_SSTAT.START is already asserted and then a repeated
start is detected. It is cleared when read or on receipt of a STOP condition. This bit
can drive an interrupt.
Device ID Matched.
0 Received address matched ID register 0
1 Received address matched ID register 1
2 Received address matched ID register 2
3 Received address matched ID register 3
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–33
ADuCM4050 I2C Register Descriptions
Table 18-21: I2C_SSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 STOP
(RC/NW)
9:8 GCID
(R/NW)
Stop After Start and Matching Address.
Gets set by hardware if the slave device received a STOP condition after a previous
START condition and a matching address. Cleared by a read of the I2C_SSTAT register. If I2C_SCTL.IENSTOP in the slave control register is asserted, then the slave
interrupt request will assert when this bit is set. This bit can drive an interrupt.
General ID.
I2C_SSTAT.GCID is cleared when the I2C_SCTL.GCSBCLR is written to 1.
These status bits will not be cleared by a General call reset.
0 No general call
1 General call reset and program address
2 General call program address
3 General call matching alternative ID
7 GCINT
(R/NW)
6 SBUSY
(R/NW)
5 NOACK
(RC/NW)
4 SRXOVR
(RC/NW)
3 SRXREQ
(RC/NW)
18–34
General Call Interrupt.
This bit always drives an interrupt. The bit is asserted if the slave device receives a general call of any type. To clear, write 1 to the I2C_SCTL.GCSBCLR in the slave control register. If it was a general call reset, all registers will be at their default values. If it
was a hardware general call, the Rx FIFO holds the second byte of the general call, and
this can be compared with the I2C_ALT register.
Slave Busy.
Set by hardware if the slave device receives a I2C START condition. Cleared by hardware when the address does not match an ID register, the slave device receives a I2C
STOP condition, or if a repeated start address does not match.
ACK Not Generated by the Slave.
When asserted, it indicates that the slave responded to its device address with a
NOACK. It is asserted if there was no data to transmit and sequence was a slave read
or if the I2C_SCTL.NACK bit was set and the device was addressed. This bit is
cleared on a read of the I2C_SSTAT register.
Slave Receive FIFO Overflow.
Asserts when a byte is written to the slave receive FIFO when the FIFO is already full.
Slave Receive Request.
I2C_SSTAT.SRXREQ asserts whenever the slave receive FIFO is not empty. Read or
flush the slave receive FIFO to clear this bit. This bit will assert on the falling edge of
the SCL clock pulse that clocks in the last data bit of a byte. This bit can drive an
interrupt.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Table 18-21: I2C_SSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 STXREQ
(RC/NW)
Slave Transmit Request/Slave Transmit Interrupt.
When read is slave transmit request; when write is clear slave transmit interrupt
(slv_txint_clr) bit. This bit is read only.
If I2C_SCTL.EARLYTXR = 0, this bit is set when the direction bit for a transfer is
received high. There after, as long as the transmit FIFO is not full this bit will remain
asserted. Initially it is asserted on the negative edge of the SCL pulse that clocks in the
direction bit (if the device address matched also).
If I2C_SCTL.EARLYTXR = 1, this bit is set when the direction bit for a transfer is
received high. There after, as long as the transmit FIFO is not full this bit will remain
asserted. Initially it is asserted after the positive edge of the SCL pulse that clocks in
the direction bit (if the device address matched also).
This bit is cleared on a read of the I2C_SSTAT register. slv_txint_clr, write only.
When this bit is 1, slave transmit interrupt and clock stretching will be cleared. And
this bit will be cleared, when STOP or (RE)START is received (transfer is done); TX
FIFO is written (software decided it now has more data to send); TX FIFO is empty
and an ACK is received instead of a NACK.
1 STXUNDR
(RC/NW)
0 STXFSEREQ
(R/W)
Slave Transmit FIFO Underflow.
Is set if a master requests data from the device, and the Tx FIFO is empty for the rising
edge of SCL.
Slave Tx FIFO Status or Early Request.
If I2C_SCTL.EARLYTXR = 0, this bit is asserted whenever the slave Tx FIFO is
empty.
If I2C_SCTL.EARLYTXR = 1, this bit is set when the direction bit for a transfer is
received high. It asserts on the positive edge of the SCL clock pulse that clocks in the
direction bit (if the device address matched also). It only asserts once for a transfer. It is
cleared when read if I2C_SCTL.EARLYTXR is asserted.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–35
ADuCM4050 I2C Register Descriptions
Master and Slave FIFO Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MFLUSH (W)
Flush the Master Transmit FIFO
STXF (R)
Slave Transmit FIFO Status
SFLUSH (W)
Flush the Slave Transmit FIFO
SRXF (R)
Slave Receive FIFO Status
MRXF (R)
Master Receive FIFO Status
MTXF (R)
Master Transmit FIFO Status
Figure 18-23: I2C_STAT Register Diagram
Table 18-22: I2C_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 MFLUSH
(RX/W)
8 SFLUSH
(RX/W)
7:6 MRXF
(R/NW)
Flush the Master Transmit FIFO.
Writing a '1' to this bit flushes the master transmit FIFO. The master transmit FIFO
will have to flushed if arbitration is lost or a slave responds with a NACK.
Flush the Slave Transmit FIFO.
Writing a '1' to this bit flushes the slave transmit FIFO.
Master Receive FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
5:4 MTXF
(R/NW)
Master Transmit FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
18–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Table 18-22: I2C_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3:2 SRXF
(R/NW)
Slave Receive FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
1:0 STXF
(R/NW)
Slave Transmit FIFO Status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–37
ADuCM4050 I2C Register Descriptions
Slave Transmit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave Transmit Register
Figure 18-24: I2C_STX Register Diagram
Table 18-23: I2C_STX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
Slave Transmit Register.
(R/W)
18–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 I2C Register Descriptions
Timing Control Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
FILTEROFF (R/W)
Input Filter Control
THDATIN (R/W)
Data in Hold Start
Figure 18-25: I2C_TCTL Register Diagram
Table 18-24: I2C_TCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 FILTEROFF
(R/W)
Input Filter Control.
Input Filter Control. It may be desirable to disable the digital filter if PCLK rate becomes < 16MHz.
0 Digital filter is enabled and is equal to 1 PCLK
1 Digital filter is disabled. Filtering in the pad is unaffected
4:0 THDATIN
(R/W)
Data in Hold Start.
I2C_TCTL.THDATIN determines the hold time requirement that must be met before a start or stop condition is recognized. The hold time observed between SDA and
SCL fall must exceed the programmed value to be recognized as a valid Start.
I2C_TCTL.THDATIN = ( tHD;STA) / (Clock Period). For example, at 16MHz
PCLK (62.5ns) and setting a minimum tHD;STA limit of 300ns. (300ns)/(62.5ns) =
5.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
18–39
Beeper Driver (BEEP)
19 Beeper Driver (BEEP)
The beeper driver module generates a differential square wave of programmable frequency. It is used to drive an
external piezoelectric sound component whose two terminals connect to the differential square wave output. A
standard APB interface connects this module to the system bus.
Beeper Features
The beeper driver present in the MCU includes the following features:
• A module that can deliver frequencies from 8 kHz to ~0.25 kHz.
• It operates on a fixed, independent 32 kHz clock source that is unaffected by changes in system clocks.
• It allows a programmable tone duration from 4 ms to 1.02 s in 4 ms increments.
• Single-tone (pulse) and multitone (sequence) modes provide versatile playback options.
• In sequence mode, the beeper may be programmed to play any number of tone pairs from 1 to 254 (2 to 508
tones) or be programmed to play forever (until stopped by the user).
• Interrupts are available to indicate the start or end of any beep, the end of a sequence, or that the sequence is
nearing completion.
Beeper Functional Description
This section provides information on the function of the beeper driver used by the ADuCM4050 MCU.
Beeper Block Diagram
The figure shows the block diagram of the beeper driver used by the ADuCM4050 MCU.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–1
Beeper Operating Modes
Beeper
Beeper Controller
IRQ
Sequence
Control
APB
MMR
Pulse Control
32 kHz clock
Clock Divider
Tone
Generator
+
-
Figure 19-1: Beeper Driver
The clock divider divides the 32 kHz input clock down to frequencies between 8 kHz and ~0.25 kHz for driving
the off-chip piezoelectric component. The beeper controller block controls the tone generator, enabling and disabling its operation, and selecting the appropriate frequency output from the clock divider.
The beeper controller also tracks the durations and repeating sequences of tones. The beeper module can interrupt
the micro with one interrupt line. Its off-chip output lines are held low when the module is disabled (no voltage
across the piezoelectric component), and drive a differential square wave while tones are being played.
Beeper Operating Modes
The basic operation of the beeper driver consists of writing tone data into one or both tone registers, followed by
enabling the beeper by setting the BEEP_CFG.EN bit. Once enabled, the module plays one or more tones depending on the operating mode. During playback, the module outputs a differential square wave (VSS to VCC) with
frequency and duration based on the BEEP_TONEA or BEEP_TONEB register settings.
Beeper has two modes of operation. If the BEEP_CFG.SEQREPEAT bit fields have a non-zero value when the
beeper is enabled, the beeper operates in sequence mode. If the beeper is enabled with BEEP_CFG.SEQREPEAT
set to 0x0, the beeper operates in pulse mode.
Pulse mode operation completes after playing exactly one tone. Sequence mode operation plays a configurable number of tones before completion. While operating in pulse or sequence mode, the BEEP_STAT.BUSY bit is asserted. This bit is cleared on completion of the operation.
A currently playing tone may be prematurely terminated by writing 0x0 to the BEEP_TONEA.DUR and
BEEP_TONEB.DUR bits. When terminated, the BEEP_STAT.AENDED and BEEP_STAT.BENDED bits are
set, and generates an interrupt if configured using the BEEP_CFG.AENDIRQ and BEEP_CFG.BENDIRQ bits.
Alternatively, all playback may be immediately terminated by disabling the beeper (clearing the BEEP_CFG.EN
bit). Disabling the beeper prevents any events from occurring and, therefore, prevents an interrupt from being generated.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Beeper Operating Modes
An interrupt is generated when an event is requested. The BEEP_STAT register provides feedback on the six
tracked events that has occurred since the register was last cleared. Any of these six events may be used for generating
interrupts by selecting them in the BEEP_CFG register.
The operating mode of the beeper is set when the beeper is enabled and cannot be changed until the beeper is again
disabled. The beeper may be disabled by writing 0x0 to the BEEP_CFG.EN bit or by waiting for the beeper to
disable itself after the current pulse or sequence completes.
Pulse Mode
In pulse mode, the beeper plays back exactly one tone. Pulse mode operation begins by enabling the beeper with a
zero value in the BEEP_CFG.SEQREPEAT bit. Once enabled, the beeper plays back a single tone as described in
the BEEP_TONEA register. Once the playback of this tone has been completed, the BEEP_STAT.BUSY bit is
cleared.
Interrupts are generated as requested in the BEEP_CFG register. Note that the only events that may occur in this
mode (and used to generate meaningful interrupts) are for the start (BEEP_CFG.ASTARTIRQ) and end
(BEEP_CFG.AENDIRQ) of BEEP_TONEA play back.
Sequence Mode
In sequence mode, the beeper plays back a programmable number of tones. Sequence mode operation begins by
enabling the beeper with a non-zero value in the BEEP_CFG.SEQREPEAT field. Once enabled, the beeper plays
back a series of two-tone sequences as described in the BEEP_TONEA and BEEP_TONEB registers. Each two-tone
iteration starts by playing BEEP_TONEA and ends by playing BEEP_TONEB.
The sequence is repeated as configured in the BEEP_CFG.SEQREPEAT field. 0xFF is a special case used to run
the sequencer until terminated by the user code. Once all iterations have been completed, the BEEP_STAT.BUSY
bit is cleared.
The number of remaining sequence iterations may be read from the BEEP_STAT.SEQREMAIN bit. When running an infinite sequence, the BEEP_STAT.SEQREMAIN bit always returns 0xFF. Writing to
BEEP_CFG.SEQREPEAT while the beeper is running in sequence mode, restarts the iteration counter to that value and immediately updates the value of the BEEP_STAT.SEQREMAIN bit.
Sequence mode may be prematurely terminated by writing 0x0 to the BEEP_CFG.SEQREPEAT bit. Setting the
BEEP_CFG.SEQREPEAT bit to 0x0 causes the beeper to terminate playback and disable itself after the completion of the current two-tone sequence. When terminated, the BEEP_STAT.SEQENDED bit is set, and generates an
interrupt if configured using the BEEP_CFG.SEQATENDIRQ bit. Alternatively, all playback may be immediately
terminated by disabling the beeper (clearing the BEEP_CFG.EN bit); disabling the beeper prevents any events from
occurring and, therefore, prevents an interrupt from being generated.
Interrupts are generated in sequence mode as requested in the BEEP_CFG register. All beeper events are valid for
interrupt generation in this mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–3
Beeper Operating Modes
Tones
The frequency and duration of tones played by the beeper depend on the values stored in the BEEP_TONEA and
BEEP_TONEB registers. Each of these registers describes a single independent tone. Pulse mode plays tones only
from register BEEP_TONEA, while sequence mode plays tones from both tone registers.
The tone registers are broken into three fields: a duration field (BEEP_TONEA.DUR, BEEP_TONEB.DUR), a frequency field (BEEP_TONEA.FREQ, BEEP_TONEB.FREQ), and a disable field (BEEP_TONEA.DIS,
BEEP_TONEB.DIS).
Tone registers may be written at any time. Writing 0x0 to the duration field (BEEP_TONEA.DUR,
BEEP_TONEB.DUR) or setting/clearing the disable bit (BEEP_TONEA.DIS, BEEP_TONEB.DIS) for a currently playing tone will take effect immediately. All other modifications to the BEEP_TONEA and BEEP_TONEB
registers take effect only the next time the tone is played; for most use cases, this allows the next tone data to be
written to while the current tone is being played.
The duration field is used to program how long a tone will play when selected for playback. Durations are measured
in units of 4 ms. Any value from 0 through 255 may be stored in the tone register. A duration of 0x0 will cause the
tone playback to end immediately. A value of 255 (0xFF) is a special case value used to program a tone for infinite
duration; once started, the tone will play continuously until user code terminates the tone (writes 0x0 to
BEEP_TONEA.DUR, BEEP_TONEB.DUR) or disables the beeper (clears the BEEP_CFG.EN bit).
The frequency field is used to program the relative frequency of the tone with respect to the source clock (32.768
kHz). Writing values 0, 1, 2, or 3 into the frequency field all have the same effect: the output will not oscillate during playback (also known as rest tone). Any value from 4 through 127 (0x7F) may be used to divide the source clock
down to the desired tone frequency. This provides a playback range from 8 kHz down to ~0.25 kHz.
The disable field is used to provide further control over the output pins of the beeper during playback. When playing a tone with the BEEP_TONEA.DIS, BEEP_TONEB.DIS bit set, the output pins behave as though the beeper were disabled; both pins rest at logic 0 with no DC potential between them and no oscillations. This feature is
intended for use when long periods of silence exist in a programmed sequence. It may be used to prevent damage to
the piezo electric component during these periods of silence.
Clocking and Power
The frequency and duration timers of the beeper driver are based on a 32.768 kHz input clock. The clock source is
configured system wide, selecting between an external crystal or an internal oscillator by writing to the appropriate
clock control module register (CLKG_OSC_CTL.LFCLKMUX). The selected clock only provides a stable reference
for the timers; the internal logic of the beeper is clocked by the peripheral clock (PCLK) of the system. For this
reason, the beeper cannot run while the system is in a low power mode that gates the peripheral clock (PCLK).
Timer start events are synchronized with the 32 kHz clock. When enabling the beeper, its output may therefore be
delayed by as much as one 32 kHz clock period (30,520 ns). For a 4 MHz PCLK, this results in up to 122 PCLK
periods between starting the beeper and actually producing audio output. Any changes to the BEEP_TONEA and
19–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Beeper Operating Modes
BEEP_TONEB registers during this time will affect the pending audio. User code must ensure that the tone is playing before modifying the tone registers, either by polling the BEEP_STAT.ASTARTED and
BEEP_STAT.BSTARTED bits or by setting an interrupt for the same.
User code must disable the beeper prior to entering a low power state where the peripheral clock would be gated.
Damage to the piezo electric component may occur if the system enters a low power mode while the beeper is playing a tone due to constant, long term DC potential across the terminals of the piezo electric component.
Power-down Considerations
There is the possibility of irreversible damage to the external piezo beeper device if the beeper is enabled and driving
the Tone outputs under the following conditions:
• Entering the Hibernate power mode
• Entering the Shutdown power mode
• Turning off PCLK
The pins do not disengage automatically from the beeper module in these modes.
Beeper Interrupts and Events
There are six tracked events that may occur while the beeper is running: Tone A may start or end, Tone B may start
or end, and the sequencer may end or be one step away from ending. These six events are always monitored, and
when they occur, a sticky bit is set in the BEEP_STAT register to be read by the user at some future time. These
bits remain set until cleared by user code.
Any of these six events may also be used to generate an interrupt. Selecting which events will generate interrupts is
done by setting the respective bits in the BEEP_CFG register. When an event triggers an interrupt, user code must
clear the event bit or disable the interrupt selection bit when servicing the interrupt.
When servicing a beeper interrupt, user code should check and eventually clear all event bits in the BEEP_STAT
register; multiple events may have triggered the interrupt (if enabled). Writing 0xFF to BEEP_STAT clears all
events.
All tracked events are independently selectable for interrupt generation.
Beeper Programming Model
The following sections provide general programming guidelines and procedures.
Timing Diagram
The figure shows the behavior of the beeper when programmed to generate a tone.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–5
Beeper Programming Model
PCLK
32 kHz CLK
TONE_A
BEEP_CFG
A
CON
Tdel
TONE_P
TONE_N
Tfreq
Figure 19-2: Timing Diagram
In this example, the tone is first written to the BEEP_TONEA register, followed by enabling the beeper by writing to
the BEEP_CFG register. Tdel illustrates the maximum one 32 kHz clock period delay between enabling the beeper
and the actual start of playback. Tfreq illustrates the output period of the two differential pins; for a 1 kHz (1024
Hz) tone, Tfreq = 0.9766 ms.
Programming Guidelines
Programming Examples
The beeper driver is programmed for a single 1 kHz beep of 1 second length with an interrupt when the tone is
done playing.
1. Set Tone A duration to 1 s. BEEP_TONEA.DUR = 0xFA. // (250 × 4 ms).
2. Set Tone A frequency to 1 kHz. BEEP_TONEA.FREQ = 0x20 // (32 kHz/32).
3. Set interrupt at the end of Tone A. BEEP_CFG.AENDIRQ = 0x1.
4. Set the sequence repeat to zero. BEEP_CFG.SEQREPEAT = 0x0.
5. Enable the beeper. BEEP_CFG.EN = 0x1.
The register access sequence is BEEP_TONEA = 0x20FA and BEEP_CFG = 0x0900.
The beeper driver is programmed for a melody of 32 two-tone sequences of the note G# for 500 ms and F# for
1000 ms with an interrupt at the end of the melody.
1. Set Tone A duration to 500 ms. BEEP_TONEA.DUR = 0x7D. // (125 × 4 ms).
2. Set Tone A frequency to G#. BEEP_TONEA.FREQ = 0x27. // (32 kHz/39 = 840 Hz).
3. Set Tone B duration to 1000 ms. BEEP_TONEB.DUR = 0xFA // (250 × 4 ms).
4. Set Tone B frequency to F#. BEEP_TONEB.FREQ = 0x2C. //(32 kHz/44 = 745 Hz).
19–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 BEEP Register Descriptions
5. Set interrupt at end of sequence. BEEP_CFG.SEQATENDIRQ = 0x1.
6. Set sequence repeat to 32. BEEP_CFG.SEQREPEAT = 0x20.
7. Enable the beeper. BEEP_CFG.EN = 0x1.
The register access sequence is BEEP_TONEA = 0x277D, BEEP_TONEB = 0x2CFA, and BEEP_CFG = 0x8120.
ADuCM4050 BEEP Register Descriptions
Beeper Driver (BEEP) contains the following registers.
Table 19-1: ADuCM4050 BEEP Register List
Name
Description
BEEP_CFG
Beeper Configuration
BEEP_STAT
Beeper Status
BEEP_TONEA
Tone A Data
BEEP_TONEB
Tone B Data
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–7
ADuCM4050 BEEP Register Descriptions
Beeper Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SEQATENDIRQ (R/W)
Sequence End IRQ
SEQREPEAT (R/W)
Beeper Sequence Repeat Value
SEQNEARENDIRQ (R/W)
Sequence 1 Cycle from End IRQ
EN (W)
Beeper Enable
BENDIRQ (R/W)
Tone B End IRQ
ASTARTIRQ (R/W)
Tone A Start IRQ
BSTARTIRQ (R/W)
Tone B Start IRQ
AENDIRQ (R/W)
Tone A End IRQ
Figure 19-3: BEEP_CFG Register Diagram
Table 19-2: BEEP_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 SEQATENDIRQ
(R/W)
Sequence End IRQ.
Set this bit to request an interrupt on the event the sequencer has stopped playing.
0 IRQ not generated at end of Sequence
1 IRQ generated at end of Sequence
14 SEQNEARENDIRQ
(R/W)
Sequence 1 Cycle from End IRQ.
Set this bit to request an interrupt on the event the sequencer is currently running and
has just one repetition remaining before completion.
0 IRQ not generated 1 tone pair before Sequence ends
1 IRQ generated 1 tone pair before sequence ends
13 BENDIRQ
(R/W)
Tone B End IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB stops playing
0 IRQ not generated at end of Tone B
1 IRQ generated at end of Tone B
12 BSTARTIRQ
(R/W)
Tone B Start IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB starts playing
0 IRQ not generated at start of Tone B
1 IRQ generated at start of Tone B
19–8
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 BEEP Register Descriptions
Table 19-2: BEEP_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 AENDIRQ
(R/W)
Tone A End IRQ.
Set this bit to request an interrupt on the event Tone A stops playing.
0 IRQ not generated at end of Tone A
1 IRQ generated at end of Tone A
10 ASTARTIRQ
(R/W)
Tone A Start IRQ.
Set this bit to request an interrupt on the event Tone A starts playing.
0 IRQ not generated at start of Tone A
1 IRQ generated at start of Tone A
8 EN
(RX/W)
Beeper Enable.
Write 0x1 to this bit to start playing Tone A. Plays a single tone if
BEEP_CFG.SEQREPEAT = 0, else plays a series of two-tone sequences. Write 0x0 to
this bit at any time to end audio playback. Reading this bit always returns 0x0, read
BEEP_STAT.BUSY to determine if the beeper is currently enabled.
0 Disable module
1 Enable module
7:0 SEQREPEAT
(R/W)
Beeper Sequence Repeat Value.
When the beeper transitions to an enabled state, the value of this field selects whether
the beeper runs in Pulse mode or Sequence mode. If 0x0, the beeper runs in Pulse
mode and plays back only one tone (Tone A) before being disabled. If a non-zero value
is written to this field, the beeper runs in Sequence mode and plays the two-tone sequence (Tone A and Tone B) the requested number of times before being disabled.
Updates to this field have no affect while running in Pulse mode. Updates to this field
take immediate affect when running in Sequence mode.
0 Enabling will start in Pulse mode.
1-254 Enabling will start in Sequence mode and play a finite
number of notes.
255 Enabling will start in Sequence mode and play forever
until stopped by user code.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–9
ADuCM4050 BEEP Register Descriptions
Beeper Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SEQENDED (R/W1C)
Sequencer Has Ended
SEQREMAIN (R)
Remaining Tone-pair Iterations to Play
in Sequence Mode
SEQNEAREND (R/W1C)
Sequencer Last Tone-pair Has Started
BUSY (R)
Beeper is Busy
BENDED (R/W1C)
Tone B Has Ended
ASTARTED (R/W1C)
Tone A Has Started
BSTARTED (R/W1C)
Tone B Has Started
AENDED (R/W1C)
Tone A Has Ended
Figure 19-4: BEEP_STAT Register Diagram
Table 19-3: BEEP_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 SEQENDED
(R/W1C)
14 SEQNEAREND
(R/W1C)
13 BENDED
(R/W1C)
12 BSTARTED
(R/W1C)
11 AENDED
(R/W1C)
10 ASTARTED
(R/W1C)
19–10
Sequencer Has Ended.
This bit is asserted whenever the beeper stops running in Sequence mode. It is cleared
only by user code writing 0x1 to this location.
Sequencer Last Tone-pair Has Started.
This bit is asserted whenever the beeper is running in Sequence mode and has only one
iteration of sequences left to play. It is cleared only by user code writing 0x1 to this
location.
Tone B Has Ended.
This bit is asserted whenever the beeper stops playing Tone B. It is cleared only by user
code writing 0x1 to this location.
Tone B Has Started.
This bit is asserted whenever the beeper begins playing Tone B. It is cleared only by
user code writing 0x1 to this location.
Tone A Has Ended.
This bit is asserted whenever the beeper stops playing Tone A. It is cleared only by user
code writing 0x1 to this location.
Tone A Has Started.
This bit is asserted whenever the beeper begins playing Tone A. It is cleared only by
user code writing 0x1 to this location.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 BEEP Register Descriptions
Table 19-3: BEEP_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 BUSY
(R/NW)
Beeper is Busy.
This bit is asserted after enabling the beeper module by writing 0x1 to
BEEP_CFG.EN. The bit is cleared when the module completes its operation or when
user code writes 0x0 to BEEP_CFG.EN.
0 Beeper is currently disabled
1 Beeper is currently enabled
7:0 SEQREMAIN
(R/NW)
Remaining Tone-pair Iterations to Play in Sequence Mode.
After a sequence has ended, this field resets to BEEP_CFG.SEQREPEAT. This field
is updated as the beeper plays back audio in Sequence mode. Each two-tone iteration
starts by playing Tone A and ends by playing Tone B. This field is updated at the conclusion of Tone B playback and therefore during the last iteration will return 0x1 during Tone A and Tone B playback. When playing an infinite sequence this field always
returns 0xFF.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–11
ADuCM4050 BEEP Register Descriptions
Tone A Data
Tone A is the first tone to play in Sequence Mode, and the only tone to play in Pulse Mode. Writing 0x0 to the
BEEP_TONEA.DUR field while Tone A is playing will immediately terminate the tone. All other writes to
BEEP_TONEA affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
DIS (R/W)
Output Disable
DUR (R/W)
Tone Duration
FREQ (R/W)
Tone Frequency
Figure 19-5: BEEP_TONEA Register Diagram
Table 19-4: BEEP_TONEA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 DIS
(R/W)
Output Disable.
This bit is set to disable the beeper output while Tone A is playing. The beeper holds
both of its two output pins at logic 0 when disabled. Writes to this bit take effect immediately if Tone A is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins
14:8 FREQ
(R/W)
Tone Frequency.
This field defines the frequency for Tone A as integer divisions of the 32.768kHz
clock. The values 0 through 3 are interpreted as 'rest-tone' and will result in no oscillations of the beeper output pins. All other values are directly used to divide the 32kHz
input clock. Writes to this field immediately affect the output of Tone A if currently
playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)
7:0 DUR
(R/W)
Tone Duration.
This field defines the duration for Tone A in 4ms increments. Writing a value of 0x0
will immediately terminate Tone A if currently playing. Writing a value of 0xFF will
cause Tone A to play forever once started, or until user code terminates the tone. Only
a write of 0x0 will affect a currently playing tone, all other values written will be used
only the next time Tone A is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 BEEP Register Descriptions
Tone B Data
Tone B is the second tone to play in Sequence Mode, and is not played Pulse Mode. Writing 0x0 to the
BEEP_TONEB.DUR field while Tone B is playing will immediately terminate the tone. All other writes to
BEEP_TONEB affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
DIS (R/W)
Output Disable
DUR (R/W)
Tone Duration
FREQ (R/W)
Tone Frequency
Figure 19-6: BEEP_TONEB Register Diagram
Table 19-5: BEEP_TONEB Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 DIS
(R/W)
Output Disable.
This bit is set to disable the beeper output while Tone B is playing. The beeper holds
both of its two output pins at logic 0 when disabled. Writes to this bit take effect immediately if Tone B is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins
14:8 FREQ
(R/W)
Tone Frequency.
This field defines the frequency for Tone B as integer divisions of the 32.768kHz
clock. The values 0 through 3 are interpreted as 'rest-tone' and will result in no oscillations of the beeper output pins. All other values are directly used to divide the 32kHz
input clock. Writes to this field immediately affect the output of Tone B if currently
playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)
7:0 DUR
(R/W)
Tone Duration.
This field defines the duration for Tone B in 4ms increments. Writing a value of 0x0
will immediately terminate Tone B if currently playing. Writing a value of 0xFF will
cause Tone B to play forever once started, or until user code terminates the tone. Only
a write of 0x0 will affect a currently playing tone, all other values written will be used
only the next time Tone B is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
19–13
ADC Subsystem
20 ADC Subsystem
The ADuCM4050 MCU incorporates a fast, multichannel, 12-bit analog-to-digital converter (ADC) capable of operating up to a maximum of 1.8 MSPS. The ADC controller can be setup to perform a series of conversions and
transfer data to the system using a dedicated DMA channel. This allows the MCU to be in the Flexi mode (minimizing the overall device power consumption) or perform other tasks.
ADC Features
The ADC has the following features:
• 12-bit resolution.
• Programmable ADC update rate up to 1.8 MSPS.
• Integrated input mux that supports up to eight channels.
• Supports temperature sensing.
• Supports battery monitoring.
• Software selectable on-chip reference voltage generation: 1.25 V, 2.5 V, and VBAT.
• Software selectable internal or external reference.
• Auto cycle mode: Ability to automatically select a sequence of input channels for conversion.
• Averaging function: Converted data on single or multiple channels can be averaged over up to 256 samples.
• Alert function: Internal digital comparator for ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3
channels. An interrupt can be generated if the digital comparator detects an ADC result above or below the
user-defined threshold.
• Supports dedicated DMA channel.
• Each channel, including temperature sensor and battery monitoring, has a dedicated data register for conversion result.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–1
ADC Functional Description
ADC Functional Description
This section provides information on the function of the ADC Subsystem used by the ADuCM4050 MCU.
ADC Subsystem Block Diagram
The figure shows the ADC subsystem.
Ref Buffer
Vref
ACLK
VREFVBAT/VREFP_ADC
VBAT_ADC
APB
ADC
ADC Controller
DMA
ADC0_VIN7 - ADC0_VIN0
CORE IRQ
TMP_OUT
Temperature
Sensor
Figure 20-1: ADC Subsystem
ADC Subsystem Components
The ADC subsystem consists of the following components:
• ADC core
• ADC digital controller
• Reference buffer
• Temperature sensor
ADC Voltage Reference Selection
The ADC can use an internal voltage reference, battery voltage, or external voltage reference for its operation.
Internal Sources
The ADuCM4050 MCU integrates a reference buffer that can generate either 1.25 V or 2.5 V as reference using the
integrated bandgap reference. This internal reference buffer is enabled by setting the ADC_CFG.REFBUFEN bit.
Battery voltage (VBAT) can also be selected as reference by setting the ADC_CFG.VREFVBAT and
ADC_CFG.VREFVBAT_DEL bits.
20–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADC Subsystem Components
NOTE: After the ADC_CFG.VREFVBAT bit is set to 1, wait for 700 μs before setting the
ADC_CFG.VREFVBAT_DEL bit. Ensure that these settings are mutually exclusive. If the ADC_CFG.REFBUFEN,
ADC_CFG.VREFVBAT, and ADC_CFG.VREFVBAT_DEL bits are set, internal reference buffer is disabled and
battery voltage (VBAT) is chosen as reference voltage.
Depending on the battery voltage range indicated by the power supply monitor, use either 2.5 V or 1.25 V as reference. The ADC_CFG.VREFSEL bit selects the reference. If the battery voltage is above 2.75 V, select 2.5 V as reference. If the battery voltage is less than 2.75 V, select 1.25 V as reference.
Low Power Mode
For conversion rate less than 100 KSPS, the reference buffer offers a capability where it consumes less current when
compared with the regular operation. This mode of operation can be enabled by setting the ADC_CFG1.RBUFLP
bit.
Sink Enable
If an external bias voltage is generated that requires an inverting configuration, the reference buffer can sink current,
as shown in ADC Subsystem Reference Buffer with Current Sink figure. A 50 μA sink current capability at 1.25 V
reference, and 100 μA sink current capability at 2.5 V reference is provided in the ADC subsystem. This can be
enabled by setting the ADC_CFG.SINKEN bit.
The figure shows the reference buffer with a current sink.
10K
10K
Vref (1.25 V)
ISINK
VBIAS
2V
Figure 20-2: ADC Subsystem Reference Buffer with Current Sink
Fast Discharge of Internal Reference Buffer
For fast switching from a higher to lower reference voltage, write ADC_CFG.FAST_DISCH to 1.
For example, while using internal reference buffer at 2.5 V, if the battery discharges to 2.75 V, VREF must be
switched to 1.25 V. For this, write ADC_CFG.FAST_DISCH and ADC_CFG.VREFSEL to 1.
External Voltage Reference
To select an external reference voltage source as ADC reference, clear the ADC_CFG.REFBUFEN and
ADC_CFG.VREFVBAT bits, and connect the external voltage reference across VREFP_ADC and GND_VREFADC pins. VBAT_ADC can be connected externally to VREFP_ADC, to be used as a reference voltage. Ensure
that the external voltage reference is not greater than VBAT.
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ADC Subsystem Components
The Reference Voltage Selection table shows the programming of the various bit fields in the ADC_CFG register to
perform reference voltage selection.
Table 20-1: Reference Voltage Selection
Voltage
REFBUFEN
VREFSEL
VREFVBAT
1.25 V
1
1
0
2.5 V
1
0
0
External Voltage Reference
0
X
0
VBAT
0
X
1
NOTE: External Voltage Reference is connected to the ADC using VREFP_ADC pin. This pin must not be
grounded or connected to any voltage supply. It must be floating when internal reference and VBAT are used.
If the ADC and Reference buffers are not used, VREFP_ADC pin can be left floating (without connecting it to an
external capacitor). If reference buffer is powered up without an external capacitor, VREFP_ADC pin oscillates.
Digital Offset Calibration
An offset correction block is used to measure and correct the offset error of the reference voltage of the ADC. For
accuracy, calibration is required.
After the ADC is powered up, to start a new calibration cycle, the ADC_CFG.STARTCAL bit must be set after
ADC is ready. The ADC_STAT.CALDONE bit is set when calibration is done. Interrupt can be enabled by setting
the ADC_IRQ_EN.CALDONE bit. The ADC_CAL_WORD register is loaded with a new calibration word at the end
of calibration. This register is retained in the Hibernate mode. The ADC_CAL_WORD register can also be programmed by the user.
NOTE: If the ADC_CAL_WORD register is programmed during conversion, the new calibration word is considered
from the next conversion cycle.
Powering the ADC
The ADC, reference buffer, and temperature sensor are powered down at reset. The user has to explicitly power up
each of these blocks. The power-up sequence depends on the internal or external reference used.
Using External Reference or VBAT as Reference
To use the external reference as the ADC reference, the following sequence must be employed at power-up:
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set ADC_PWRUP.WAIT bits to generate 20 μs wait time with respect to the PCLK frequency set in the
CLKG_CLK_CTL1 register.
3. Set the ADC_CFG.VREFVBAT bit to use VBAT as reference voltage.
4. Assert the ADC_CFG.EN bit and enable the ADC.
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5. Wait for interrupt and write 1 to clear the ADC_STAT.RDY bit. Interrupt must be enabled by setting the
ADC_IRQ_EN.RDY bit.
6. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
The ADC subsystem is ready for operation.
Using Internal Reference Buffer
To use the internal reference buffer, the following sequence must be employed at power-up:
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set the ADC_PWRUP.WAIT field to generate 20 μs wait time with respect to the PCLK frequency set in the
CLKG_CLK_CTL1 register.
3. Select 1.25 V or 2.5 V as reference voltage using the ADC_CFG.VREFSEL bit.
4. Assert the ADC_CFG.REFBUFEN bit.
5. Assert the ADC_CFG.EN bit.
6. Wait for 3.5 ms.
One of the general-purpose timers can be used to wait for 3.5 ms. During this wait period, the device can be
put in Flexi mode to save system power, and woken up by genetal purpose timer interrupt.
7. Write 1 to clear the ADC_STAT.RDY bit.
8. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
The ADC is ready for conversion.
Hibernate
All components of the ADC subsystem are automatically powered down when the part goes to hibernate. This is
done to keep the power consumption minimum. After waking up from hibernate, all components must be explicitly
powered up and ready before a conversion can take place, as explained in Powering the ADC section.
However, while the ADC is in the Hibernate mode, the calibration coefficients are retained in the internal registers
of the ADC. In this way, the ADC can wake up from hibernate, and a calibrated conversion cycle can be started
immediately after the wake-up time has elapsed. A new calibration cycle, if required, can be run by asserting the
ADC_CFG.STARTCAL bit.
A new calibration cycle is recommended at wake-up if the system is in hibernate mode for an extended period, and
the operating conditions of the ADC, temperature, and reference voltage may have changed since the last calibration
cycle.
The following register fields are retained when the chip goes into hibernate mode:
• ADC_CFG.VREFSEL
• ADC_CFG.SINKEN
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• ADC_PWRUP.WAIT
• ADC_CAL_WORD.VALUE
• ADC_CNV_TIME.SAMPTIME
• ADC_AVG_CFG.FACTOR
• ADC_AVG_CFG.OS
• ADC_LIMx_LO.VALUE
• ADC_LIMx_HI.VALUE
• ADC_HYSx.VALUE
• ADC_HYSx.MONCYC
• ADC_CFG1.RBUFLP
NOTE: If a conversion is ongoing prior to the part going to hibernate mode, that conversion does not resume after
the part wakes up.
The ADC must be disabled before going to the Hibernate or Shutdown mode by clearing the ADC_CFG.EN bit.
Sampling and Conversion Time
The ADC can be in one of the following phases:
• Acquisition Phase: During the acquisition phase, the capacitor arrays are connected directly to the inputs to get
fully charged. The minimum required acquisition time depends on the output impedance. The timing for this
phase is programmed in the ADC_CNV_TIME.SAMPTIME bit in terms of number of clock cycles.
Acquisition phase is (SAMPTIME + 1) ACLK cycles.
The time depends on the SAMPTIME value and selected clock frequency (ACLK).
ACLK frequency = System clock frequency / ACLKDIV
ACLKDIV can be programmed in the CLKG_CLK_CTL1.ACLKDIVCNT register (9 bits).
• Conversion Phase: At the end of the acquisition phase, the conversion phase is initiated. The conversion is
completed by successive approximation.
NOTE: The time between two conversions must not exceed 100 μs.
In case, the ADC is idle for more than 100 μs, a dummy conversion must be performed.
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ADC Subsystem Components
Acquisition
Conversion
SAMPTIME+1
Acquisition
13
Sample period = SAMPTIME + 14
Where:
SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
Time units in ACLK cycles
Figure 20-3: Oversampling Disabled and Zero Delay
Acquisition 1
Conversion 1
SAMPTIME+1
13
Acquisition 2
Acquisition N
Conversion N
Acquisition 1
Sample period = N * (SAMPTIME + 14)
Where:
SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
N is the oversampling rate (ADC_AVG_CFG.FACTOR)
Time units in ACLK cycles
Figure 20-4: Oversampling Enabled and Zero Delay
Acquisition
SAMPTIME+1
Delay
Conversion
13
Acquisition
DLY+2
Sample period = SAMPTIME + DLY +16
Where:
SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
DLY is the delay - 2 * (ADC_CNV_TIME.DLY)
Time units in ACLK cycles
Figure 20-5: Oversampling Disabled and Delay > 0
Acquisition 1
Conversion 1
SAMPTIME+1
13
Acquisition 2
Acquisition N
Conversion N
Delay
Acquisition 1
DLY+2
Sample period = (N * (SAMPTIME + 14)) + (DLY +2)
Where:
SAMPTIME is the sampling time (ADC_CNV_TIME.SAMPTIME)
N is the oversampling rate (ADC_AVG_CFG.FACTOR)
DLY is the delay - 2 * (ADC_CNV_TIME.DLY)
Time units in ACLK cycles
Figure 20-6: Oversampling Enabled and Delay > 0
For a single channel:
• If ADC_CNV_TIME.DLY = 0,
ADC Sampling Rate = (Root_clock / ACLK_DIV) / [(14 + Sampling Time) (Oversampling Rate)]
• If ADC_CNV_TIME.DLY > 0,
ADC Sampling Rate = (Root_clock / ACLK_DIV) / [((14 + Sampling Time) (Oversampling Rate)) + (DLY +
2)]
For mutiple channels:
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ADC Subsystem Components
• If ADC_CNV_TIME.DLY = 0,
ADC Sampling Rate = (Root_clock / ACLK_DIV) / [(14 + Sampling Time) (Oversampling Rate) (Number of
Channels)]
• If ADC_CNV_TIME.DLY > 0,
ADC Sampling Rate = (Root_clock / ACLK_DIV) / [((14 + Sampling Time) (Oversampling Rate) (Number of
Channels)) + (DLY + 3)]
Operation
The ADC controller supports several use cases.
Single Channel Mode
The ADC can be configured to convert on a particular channel by selecting one of the channels using the
ADC_CNV_CFG.SEL bits. The ADC converts analog input, provides the CNV_DONE interrupt, and stores the
result in the corresponding CHx_OUT register. A channel can be enabled by writing to the specific bit in the
ADC_CNV_CFG.SEL bits. For example, to enable channel 2, set the ADC_CNV_CFG.SEL[2] bit. Ensure that
only one bit (out of SEL[7:0], BAT, TMP, TMP2) is set for conversion on single channel
(ADC_CNV_CFG.AUTOMODE = 0).
To perform multiple conversions on a selected channel, set the ADC_CNV_CFG.MULTI bit. An interrupt is generated if enabled, and the corresponding bit in the ADC_STAT register is set after each conversion. The conversion
output is stored in the CHx_OUT register.
If the result is not read from the output register and the status bit is not cleared before the next conversion ends, the
conversion output overflows and new result is stored in the CHx_OUT register, resulting in data loss.
It is recommended to use DMA for multiple conversions. Delay can also be introduced between successive conversions.
NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared to
stop the ADC subsystem from converting.
Auto Cycle Mode
Auto cycle mode reduces the MCU overhead of sampling and reading individual channel registers. It allows the user
to select a sequence of ADC input channels and provides a single interrupt when conversions on all channels end.
Temperature sensing and battery monitoring cannot be included in the auto cycle mode. Auto cycle mode is enabled
by setting the ADC_CNV_CFG.AUTOMODE bit.
Conversions are performed starting from the lowest numbered channel to the highest numbered channel of the
channels enabled. Output for each channel is stored in the respective CHx_OUT register, and the orresponding bits
in the ADC_STAT register are set after conversion on all channels (one sequence) is completed.
To initiate multiple conversions on selected channels, enable the ADC_CNV_CFG.MULTI bit. An interrupt is generated after each sequence completes. Delay can be introduced between successive sequences. It is recommended to
use DMA for multiple conversions due to the amount of data that can be generated.
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NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared to
stop the ADC subsystem from converting. ADC_CNV_CFG.MULTI must be low for a minimum of one ACLK
cycle. Status bits for conversion done, alert, and overflow must be cleared before starting a next conversion.
Delay Between Conversions
The ADC_CNV_TIME.DLY bits can be programmed to set the delay between completing one sequence of channels and starting another sequence, or multiple conversions on a single channel. This delay is in terms of number of
ACLK cycles.
MULTI
CNV
CNV1
Delay
CNV2
Delay
CNV3
Delay
Figure 20-7: Delay Between Conversions on Single Channel in Multiple Conversions Mode
MULTI
AUTO MODE
CNV
CNV on CH0
CNV on CH3
Delay
CNV on CH0
CNV on CH3
Figure 20-8: Delay Between Sequences in Auto Cycle Mode
DMA
A DMA channel can be used to reduce the MCU overhead by moving the ADC results directly into SRAM with a
single interrupt asserted after the required number of ADC conversions are completed. DMA can be enabled using
the ADC_CNV_CFG.DMAEN bit. The conversion result must be read from the ADC_DMA_OUT.RESULT bits.
The DMA channel can be programmed for a given number of conversions. The MCU can be in Flexi mode during
this period, until the programmed number of conversions is completed and the DMA done interrupt is received. For
more information, refer to the Programming Flow section.
Interrupts
The ADC controller has an interrupt associated with it. The interrupt status register indicates the source of an interrupt. When DMA is not used, the ADC controller generates data interrupts after a conversion.
NOTE: All interrupts are Write One to Clear.
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ADC Subsystem Components
Conversion
An interrupt can be generated after each conversion is complete by setting the ADC_IRQ_EN.CNVDONE bit. Corresponding DONE bit is set in the ADC_STAT register after the completion of a conversion.
Overflow
If output data is not read from the output register by the user or DMA before the next conversion is performed on
the channel, it is overwritten. The overflow bit is set for the respective channel in the ADC_OVF register and interrupt is generated. It remains set until it is cleared by the user. This interrupt must be enabled by the user by setting
the ADC_IRQ_EN.OVF bit.
NOTE: The ADC_CNV_CFG.SEL bits must remain unchanged when a conversion is being done.
Programming Flow
After powering up and calibrating (if required), the ADC is ready for conversion.
Single Conversion on Single Channel
This mode is used to perform a single conversion on a selected channel. The ADC_CNV_CFG.SINGLE bit must
set to 1 to perform the conversion. This bit works as a write one to action bit and reads as zero. DMA is not recommended for this mode, as only a single data needs to be read. The conversion result can be read from the RESULT
bits in the corresponding Channel Output register.
The following steps describe how to program the ADC for a single conversion on a single channel (say AIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
4. Interrupt is generated and STAT[2] is set when conversion is done.
5. Set cnv_result = ADC_CH0_OUT.RESULT to read the conversion result.
6. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.
CLK
SINGLE
DONE2
CH2_OUT[11:0]
Figure 20-9: Single Conversion on Single Channel
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ADC Subsystem Components
Multiple Conversion on Single Channel
The ADC_CNV_CFG.MULTI bit is used to perform multiple conversions on the selected channel. The conversions
continue until this bit is deasserted. Use DMA for this mode. This mode is similar to performing multiple back-toback single conversions on the channel with the added overhead of reading the data (else, it is overwritten) and restarting the conversion. When using DMA, the number of conversions to be done must be programmed in the
count descriptor of the DMA.
The following steps describe how to program the ADC for a multiple conversion on a single channel (say
ADC0_VIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set the following DMA configurations:
a. DMA count = 2 for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result.
e. Program the required increment (half-word) in the DMA channel control data structure.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA.
4. Set ADC_CNV_TIME.DLY = 0x14 and set the delay between two conversions.
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done interrupt is generated after three conversions (count = 2).
6. Set ADC_CNV_CFG.MULTI = 0 to clear MULTI and disable further conversions in ISR.
The conversion results can be read from the SRAM.
MULTI
CNV
CNV1
Delay
CNV2
Delay
CNV3
Delay
CNV4
dma_done
Figure 20-10: Multiple Conversion on Single Channel
Single Conversion in Auto Cycle Mode
Set the appropriate ADC_CNV_CFG.SEL channel bits to enable the channels included in the sequence.
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The following steps describe how to program the ADC for a single conversion on a series of channels in auto cycle
mode (say ADC0_VIN2, ADC0_VIN4, and ADC0_VIN7):
1. Set ADC_CNV_CFG.SEL = 0x94.
2. Set the following DMA configurations:
a. DMA count = 2, for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment (half-word) in the DMA channel control data structure.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1.
5. Set ADC_CNV_TIME.DLY = 0x0.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion results can be read from the SRAM or respective Channel Out registers.
SINGLE
AUTO MODE
CNV
CNV on CH2
CNV on CH4
CNV on CH7
dma_done
Figure 20-11: Single Conversion in Auto Cycle Mode
Multiple Conversions in Auto Cycle Mode
Program the number of sequences multiplied by number of channels selected to be run in the count descriptor of
the DMA.
The following steps describe how to program the ADC for a multiple conversion on a series of channels in auto
cycle mode (say ADC0_VIN0, ADC0_VIN2, and ADC0_VIN3):
1. Set ADC_CNV_CFG.SEL = 0x0D.
2. Set ADC_CNV_TIME.DLY = 0x7E.
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3. Set the following DMA configurations:
a. Source Address = Address of ADC_DMA_OUT register
b. Source Size = Halfword
c. Destination address of DMA as SRAM memory location address to store the conversion result
d. Program the required increment (half-word) in the DMA channel control data structure.
e. count = 5, for two sequences
4. Set ADC_CNV_CFG.DMAEN = 0x1.
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done is generated after conversion.
6. Set ADC_CNV_CFG.MULTI = 0 to disable further conversions in ISR.
The conversion results can be read from the SRAM.
MULTI
AUTO MODE
CNV
CNV on CH0 CNV on CH3 Delay CNV on CH0 CNV on CH3
dma_done
Figure 20-12: Multiple Conversions in Auto Cycle Mode
Temperature Sensor
The ADC subsystem provides a temperature sensor that measures die temperature. To enable the temperature sensing, set the ADC_CFG.TMPEN bit. Wait for 300 μs before starting the conversion. The temperature sensor can be
enabled along with the ADC or the reference buffer to save time.
This temperature sensor is not designed for use as an absolute ambient temperature calculator. It is used as an approximate indicator of temperature of the ADuCM4050 MCU die.
Program the ADC_CNV_TIME.SAMPTIME bit to provide an acquisition time of 65 μs.
The following steps describe how to measure temperature:
1. Set the ADC_CNV_CFG.TMP bit to 1.
2. Set the ADC_CNV_CFG.SINGLE bit.
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ADC Subsystem Components
3. The ADC_STAT.TMPDONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
4. Read the result from the ADC_TMP_OUT register.
5. Set the ADC_CNV_CFG.TMP2 bit to 1.
6. Set the ADC_CNV_CFG.SINGLE bit to 1.
7. The ADC_STAT.TMP2DONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
8. Read the result from ADC_TMP2_OUT register after conversion.
Auto mode can also be used.
Set the ADC_CNV_CFG.TMP and ADC_CNV_CFG.TMP2 bits.
Start the conversion by setting the ADC_CNV_CFG.SINGLE bit or ADC_CNV_CFG.MULTI bit (for multiple
conversions).
Temperature can be calculated as:
T (⁰C) = [[[ADC_TMP_OUT - (Offsetcode * 1.25 / Vref )] / (ADC_TMP2_OUT + (RG * ADC_TMP_OUT)] * [Rvirtualreference / idealsensitivity]] - 273.15
where,
• RG = 1.1829
• Rvirtualreference = 1.2256
• idealsensitivity = 0.0012411
• Offsetcode = 161
For example, if ADC_TMP_OUT is 1620 and ADC_TMP2_OUT is 2102, the temperature is 85⁰C.
Battery Monitoring
To enable battery monitoring, the ADC_CNV_CFG.BAT bit must be set. The ADC_CNV_TIME.SAMPTIME bit
must be set to obtain an acquisition time of 500 ns. Set the ADC_CNV_CFG.SINGLE bit to start conversion. The
ADC converted output can be read from the ADC_BAT_OUT register or SRAM, depending on the conversion
mode.
Conversion done interrupt can be enabled for getting an interrupt after conversion is done. Clear the
ADC_CNV_CFG.BAT bit after conversion is done to reduce power consumption.
To convert ADC result to battery voltage:
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ADC Subsystem Components
VBAT = 4 * ADC_BAT_OUT * Vref / (212 – 1)
where,
• VBAT is battery voltage
• Vref is reference voltage selected (preferred, 1.25 V)
• ADC_BAT_OUT is ADC converted output
Oversampling
Resolution greater than 12-bit can be achieved by oversampling. Oversampling can be enabled by writing the
ADC_AVG_CFG.OS and ADC_AVG_CFG.EN bits to 1. When oversampling is enabled, the ADC samples multiple times and averages the result to provide the required output in the CHx_OUT register. The value to be programmed in the ADC_AVG_CFG.FACTOR field for a required resolution is given in the Factor for Enhanced Resolution
table.
Table 20-2: Factor for Enhanced Resolution
Resolution Required
AVG_CFG_FACTOR to be programmed
Number of Samples Used
13-bit
h02
4
14-bit
h08
16
15-bit
h20
64
16-bit
h80
256
Averaging Function
When performing multiple conversions, averaging can be enabled on all selected channels. Averaging can be performed over a maximum of 256 samples, in the steps of power of 2 (that is, 2, 4, 8, 16…256). Averaging can be
enabled by writing the ADC_AVG_CFG.OS bit to 0 and the ADC_AVG_CFG.EN bit to 1.
Averaging factor is to be programmed as factor/2 in the ADC_AVG_CFG.FACTOR bits.
For example, to average 64 samples, program ADC_AVG_CFG.FACTOR as 32 (0x20). An interrupt is generated
after averaging is complete.
In case of auto cycle mode, DMA can be enabled.
For example, to average over 16 samples, 16 values are converted, added, and then divided by 16.
If averaging is enabled in auto mode (for multiple channels), programmed number of conversions are done on one
channel (and averaged) before moving to the next channel.
Averaging for Multiple Conversions on Single Channel
The following steps describe how to perform averaging over multiple conversions on a single channel (say
ADC0_VIN2):
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ADC Subsystem Components
1. Set ADC_CNV_CFG.SEL = 0x2 and select Channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_AVG_CFG.OS = 0.
4. Set ADC_AVG_CFG.EN = 0x1 to enable averaging.
5. Set ADC_AVG_CFG.FACTOR = 0x20 to average 64 samples.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
7. Interrupt is generated and ADC_STAT.DONE2 is set when conversion is done.
8. Set cnv_result = ADC_CH2_OUT.RESULT to read the conversion output.
9. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.
Averaging for Multiple Conversions in Auto Cycle Mode
The following steps describe how to perform averaging over multiple conversion on a series of channels in auto cycle
mode:
1. Set ADC_CNV_CFG.SEL = 0x30 and select Channel 5 and Channel 4 for conversion.
2. Set the following DMA configurations:
a. DMA count = 1, for averaging ones over two channels (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment in the destination address.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1 to start the conversion.
5. Set ADC_AVG_CFG.OS = 0.
6. Set ADC_AVG_CFG.EN = 0x1.
7. Set ADC_AVG_CFG.FACTOR = 0x08 to average 16 samples.
8. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion result can be read from the SRAM or respective Channel Out registers.
NOTE: Averaging/Over sampling and monitoring cannot be enabled together. They are mutually exclusive.
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ADC Digital Comparator
A digital comparator is provided to allow an interrupt to be triggered if the ADC input is above or below a programmable threshold. Input channels ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 can be used with
the digital comparator. This can be used to continuously monitor if any (or a set) of these channels stay within normal range of values. Comparators can be enabled only in multiple conversion mode, either on single channel or in
auto cycle mode. Overflow indication is disabled, as the user is not expected to read the results during monitoring.
To set up the ADC digital comparator:
• Lower threshold value must be written to 12-bit ADC_LIMx_LO.VALUE field. To enable comparison with
lower limit, the EN bit of the corresponding register must be set.
• Higher threshold value must be written to 12-bit ADC_LIMx_HI.VALUE field. To enable comparison, the
EN bit of the corresponding register must be set.
• Hysteresis value can also be given for each of these channels in the ADC_HYSx.VALUE bit . It must be enabled by setting the ADC_HYSx.EN bit.
• An alert is indicated if the ADC result crosses the threshold (ADC_LIMx_LO.VALUE or
ADC_LIMx_HI.VALUE) and does not return to its normal value within number of clock cycles programmed
in the ADC_HYSx.MONCYC bit.
The Normal value is defined as:
• For lower threshold: Above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE
• For higher threshold: Below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE
If the converted result is above ADC_LIMx_HI.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain above ADC_LIMx_HI.VALUE - ADC_HYSx.VALUE, an alert
is indicated.
If the converted result during monitoring is below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE, alert is not
indicated and monitoring stops.
Similarly, if the converted result is below ADC_LIMx_LO.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain below ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, an alert
is indicated.
If the converted result during monitoring is above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, alert is not
indicated and monitoring stops.
The ADC_ALERT register can be read to determine the source of alert. An interrupt is generated if the
ADC_IRQ_EN.ALERT bit is set.
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ADC_LIMx_HI.VALUE
ADC_LIMx_HI.VALUE
ADC_LIMx_LO.VALUE
HYS
- ADC_HYSx.VALUE
+ ADC_HYSx.VALUE
HYS
ADC_LIMx_LO.VALUE
Figure 20-13: Low-High Limits and Hysteresis
ADC_LIM0_HI
12’h2FF
ADC_HYS0.VALUE
9’h010
ADC_HYS0.MONCYC
3’h4
CNV
ADC_CH0_OUT
CNV1
12’h301
CNV2
12’h315
CNV3
CNV4
CNV5
12’h2F0
12’h2FD
12’h300
Monitor
ADC_ALERT.HI0
Figure 20-14: Alert Functionality
ADC_LIM2_L0
12’h01E
ADC_HYS2.VALUE
9’h00E
ADC_HYS2.MONCYC
3’h6
CNV
ADC_CH2_OUT
CNV1
CNV2
CNV3
CNV4
CNV5
12’h010
12’h00D
12’h012
12’h022
12’h02F
Monitor
ADC_ALERT.Hi1
Figure 20-15: Alert Not Indicated when Conversion Result Returns to Normal Value within MONCYC Cycles
In auto cycle mode, channels are converted sequentially. If any channel crosses the threshold, it is monitored before
moving to the next channel in sequence. Monitoring stops if the channel input returns to a normal value within
MONCYC cycles or an alert is raised after MONCYC cycles.
NOTE: Hysteresis is not supported with DMA enabled.
The flowchart explains the flow of conversion when comparison is enabled on three channels in auto cycle mode.
20–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
CNV on
First Channel
Yes
Crossed
Threshold?
Monitor
First Channel
No
Monitoring Stops
CNV on
Second Channel
Yes
Crossed
Threshold?
Monitor
Second Channel
No
Monitoring Stops
CNV on
Third Channel
No
Crossed
Threshold?
Yes
Monitor
Third Channel
Monitoring Stops
Figure 20-16: Conversion Flow for Comparison Enabled on Three Channels in Auto Cycle Mode
ADuCM4050 ADC Register Descriptions
Digital Controller for ADC (ADC) contains the following registers.
Table 20-3: ADuCM4050 ADC Register List
Name
Description
ADC_ALERT
Alert Indication
ADC_AVG_CFG
Averaging Configuration
ADC_BAT_OUT
Battery Monitoring Result
ADC_CAL_WORD
Calibration Word
ADC_CFG
ADC Configuration
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–19
ADuCM4050 ADC Register Descriptions
Table 20-3: ADuCM4050 ADC Register List (Continued)
Name
Description
ADC_CFG1
Reference Buffer Low Power Mode
ADC_CH0_OUT
Conversion Result Channel 0
ADC_CH1_OUT
Conversion Result Channel 1
ADC_CH2_OUT
Conversion Result Channel 2
ADC_CH3_OUT
Conversion Result Channel 3
ADC_CH4_OUT
Conversion Result Channel 4
ADC_CH5_OUT
Conversion Result Channel 5
ADC_CH6_OUT
Conversion Result Channel 6
ADC_CH7_OUT
Conversion Result Channel 7
ADC_CNV_CFG
ADC Conversion Configuration
ADC_CNV_TIME
ADC Conversion Time
ADC_DMA_OUT
DMA Output Register
ADC_HYS0
Channel 0 Hysteresis
ADC_HYS1
Channel 1 Hysteresis
ADC_HYS2
Channel 2 Hysteresis
ADC_HYS3
Channel 3 Hysteresis
ADC_IRQ_EN
Interrupt Enable
ADC_LIM0_HI
Channel 0 High Limit
ADC_LIM0_LO
Channel 0 Low Limit
ADC_LIM1_HI
Channel 1 High Limit
ADC_LIM1_LO
Channel 1 Low Limit
ADC_LIM2_HI
Channel 2 High Limit
ADC_LIM2_LO
Channel 2 Low Limit
ADC_LIM3_HI
Channel 3 High Limit
ADC_LIM3_LO
Channel 3 Low Limit
ADC_OVF
Overflow of Output Registers
ADC_PWRUP
ADC Power-up Time
ADC_STAT
ADC Status
ADC_TMP2_OUT
Temperature Result 2
ADC_TMP_OUT
Temperature Result
20–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Alert Indication
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
LO3 (R/W1C)
Channel 3 Low alert status
HI0 (R/W1C)
Channel 0 High alert status
HI3 (R/W1C)
Channel 3 High alert status
LO0 (R/W1C)
Channel 0 Low alert status
LO2 (R/W1C)
Channel 2 Low alert status
HI1 (R/W1C)
Channel 1 High alert status
HI2 (R/W1C)
Channel 2 High alert status
LO1 (R/W1C)
Channel 1 Low alert status
Figure 20-17: ADC_ALERT Register Diagram
Table 20-4: ADC_ALERT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 LO3
Channel 3 Low alert status.
(R/W1C)
6 HI3
Channel 3 High alert status.
(R/W1C)
5 LO2
Channel 2 Low alert status.
(R/W1C)
4 HI2
Channel 2 High alert status.
(R/W1C)
3 LO1
Channel 1 Low alert status.
(R/W1C)
2 HI1
Channel 1 High alert status.
(R/W1C)
1 LO0
Channel 0 Low alert status.
(R/W1C)
0 HI0
Channel 0 High alert status.
(R/W1C)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–21
ADuCM4050 ADC Register Descriptions
Averaging Configuration
15 14 13 12 11 10 9
0
1
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
EN (R/W)
To enable averaging on Channels enabled
in enable register
FACTOR (R/W)
Program averaging factor for averaging
enabled channels (1-256)
OS (R/W)
Enable oversampling
Figure 20-18: ADC_AVG_CFG Register Diagram
Table 20-5: ADC_AVG_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable averaging on Channels enabled in enable register.
(R/W)
14 OS
Enable oversampling.
(R/W)
7:0 FACTOR
Program averaging factor for averaging enabled channels (1-256).
(R/W)
20–22
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Battery Monitoring Result
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of battery monitoring
is stored here
Figure 20-19: ADC_BAT_OUT Register Diagram
Table 20-6: ADC_BAT_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of battery monitoring is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–23
ADuCM4050 ADC Register Descriptions
Calibration Word
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
VALUE (R/W)
Offset calibration word
Figure 20-20: ADC_CAL_WORD Register Diagram
Table 20-7: ADC_CAL_WORD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
6:0 VALUE
Offset calibration word.
(R/W)
20–24
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
ADC Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VREFVBAT_DEL (R/W)
VRef VBAT delayed
PWRUP (R/W)
Powering up ADC
FAST_DISCH (R/W)
For fast switchover of Vref from 2.5
V to 1.25 V
VREFSEL (R/W)
To select Vref as 1.25 V or 2.5 V
REFBUFEN (R/W)
To enable internal reference buffer
TMPEN (R/W)
To power up temperature sensor
VREFVBAT (R/W)
VRef VBAT
SINKEN (R/W)
To enable additional 50 uA sink current
capability @1.25 V, 100 uA current
capability @2.5 V
EN (R/W)
To enable ADC subsystem
RST (R/W)
Resets internal buffers and registers
when high
STARTCAL (R/W)
To start a new offset calibration cycle
Figure 20-21: ADC_CFG Register Diagram
Table 20-8: ADC_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10 VREFVBAT_DEL
(R/W)
9 FAST_DISCH
VRef VBAT delayed.
Set to 1 after minimum delay of 700 us from ADC_CFG.VREFVBAT field being set
to 1. NOTE: ADC_CFG.VREFVBAT_DEL and ADC_CFG.VREFVBAT must be reset to 0 together.
For fast switchover of Vref from 2.5 V to 1.25 V.
(R/W)
8 TMPEN
To power up temperature sensor.
(R/W)
7 SINKEN
(R/W)
6 RST
To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability
@2.5 V.
Resets internal buffers and registers when high.
(R/W)
5 STARTCAL
To start a new offset calibration cycle.
(R/W)
4 EN
To enable ADC subsystem.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–25
ADuCM4050 ADC Register Descriptions
Table 20-8: ADC_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 VREFVBAT
(R/W)
VRef VBAT.
Set to 1 to select VBAT as Vref. After a minimum delay of 700 us from setting this
field, ADC_CFG.VREFVBAT_DEL field must be set to 1.
Note: ADC_CFG.VREFVBAT_DEL and ADC_CFG.VREFVBAT must be reset to 0
together.
2 REFBUFEN
To enable internal reference buffer.
(R/W)
0 External reference is used
1 Reference buffer is enabled
1 VREFSEL
To select Vref as 1.25 V or 2.5 V.
(R/W)
0 Vref = 2.5 V
1 Vref = 1.25 V
0 PWRUP
Powering up ADC.
(R/W)
20–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Reference Buffer Low Power Mode
15 14 13 12 11 10 9
0
0
0
0
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RBUFLP (R/W)
Enable low power mode for reference
buffer
Figure 20-22: ADC_CFG1 Register Diagram
Table 20-9: ADC_CFG1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 RBUFLP
Enable low power mode for reference buffer.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–27
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 0
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 0 is stored
here
Figure 20-23: ADC_CH0_OUT Register Diagram
Table 20-10: ADC_CH0_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 0 is stored here.
(R/NW)
20–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 1
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 1 is stored
here
Figure 20-24: ADC_CH1_OUT Register Diagram
Table 20-11: ADC_CH1_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 1 is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–29
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 2 is stored
here
Figure 20-25: ADC_CH2_OUT Register Diagram
Table 20-12: ADC_CH2_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 2 is stored here.
(R/NW)
20–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 3
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 3 is stored
here
Figure 20-26: ADC_CH3_OUT Register Diagram
Table 20-13: ADC_CH3_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 3 is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–31
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 4
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 4 is stored
here
Figure 20-27: ADC_CH4_OUT Register Diagram
Table 20-14: ADC_CH4_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 4 is stored here.
(R/NW)
20–32
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 5
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 5 is stored
here
Figure 20-28: ADC_CH5_OUT Register Diagram
Table 20-15: ADC_CH5_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 5 is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–33
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 6
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 6 is stored
here
Figure 20-29: ADC_CH6_OUT Register Diagram
Table 20-16: ADC_CH6_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 6 is stored here.
(R/NW)
20–34
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Conversion Result Channel 7
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of channel 7 is stored
here
Figure 20-30: ADC_CH7_OUT Register Diagram
Table 20-17: ADC_CH7_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of channel 7 is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–35
ADuCM4050 ADC Register Descriptions
ADC Conversion Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MULTI (R/W)
Set to start multiple conversions
SEL (R/W)
To select channel(s) to convert
SINGLE (R/W)
Set to start single conversion
BAT (R/W)
Enable Battery Monitoring
DMAEN (R/W)
Enable DMA Channel
TMP (R/W)
To select temperature measurement 1
AUTOMODE (R/W)
Enable Auto Mode
TMP2 (R/W)
To select temperature measurement 2
Figure 20-31: ADC_CNV_CFG Register Diagram
Table 20-18: ADC_CNV_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 MULTI
Set to start multiple conversions.
(R/W)
14 SINGLE
Set to start single conversion.
(R/W)
13 DMAEN
Enable DMA Channel.
(R/W)
12 AUTOMODE
Enable Auto Mode.
(R/W)
10 TMP2
To select temperature measurement 2.
(R/W)
9 TMP
To select temperature measurement 1.
(R/W)
8 BAT
Enable Battery Monitoring.
(R/W)
7:0 SEL
To select channel(s) to convert.
(R/W)
20–36
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
ADC Conversion Time
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DLY (R/W)
Delay between two consecutive conversions
in terms of number of ACLK cycles
SAMPTIME (R/W)
Number of clock cycles (ACLK) required
for sampling
Figure 20-32: ADC_CNV_TIME Register Diagram
Table 20-19: ADC_CNV_TIME Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 DLY
Delay between two consecutive conversions in terms of number of ACLK cycles.
(R/W)
7:0 SAMPTIME
Number of clock cycles (ACLK) required for sampling.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–37
ADuCM4050 ADC Register Descriptions
DMA Output Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Register to store conversion result
for DMA
Figure 20-33: ADC_DMA_OUT Register Diagram
Table 20-20: ADC_DMA_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Register to store conversion result for DMA.
(R/NW)
20–38
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 0 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 0
VALUE (R/W)
Hysteresis value for Channel 0
MONCYC (R/W)
Program number of conversion cycles
to monitor channel 0 before raising
alert
Figure 20-34: ADC_HYS0 Register Diagram
Table 20-21: ADC_HYS0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 0.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor channel 0 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 0.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–39
ADuCM4050 ADC Register Descriptions
Channel 1 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 1
VALUE (R/W)
Hysteresis value for Channel 1
MONCYC (R/W)
Program number of conversion cycles
to monitor channel 1 before raising
alert
Figure 20-35: ADC_HYS1 Register Diagram
Table 20-22: ADC_HYS1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 1.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor channel 1 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 1.
(R/W)
20–40
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 2 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 2
VALUE (R/W)
Hysteresis value for Channel 2
MONCYC (R/W)
Program number of conversion cycles
to monitor channel 2 before raising
alert
Figure 20-36: ADC_HYS2 Register Diagram
Table 20-23: ADC_HYS2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 2.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor channel 2 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 2.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–41
ADuCM4050 ADC Register Descriptions
Channel 3 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 3
VALUE (R/W)
Hysteresis value for Channel 3
MONCYC (R/W)
Program number of conversion cycles
to monitor channel 3 before raising
alert
Figure 20-37: ADC_HYS3 Register Diagram
Table 20-24: ADC_HYS3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 3.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor channel 3 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 3.
(R/W)
20–42
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDY (R/W)
Set to enable interrupt when ADC is
ready to convert
CNVDONE (R/W)
Set it to enable interrupt after conversion
is done
ALERT (R/W)
Enable Interrupt on Crossing Lower
or Higher Limit
CALDONE (R/W)
Set it to enable interrupt for calibration
done
OVF (R/W)
Set to enable interrupt in case of overflow
Figure 20-38: ADC_IRQ_EN Register Diagram
Table 20-25: ADC_IRQ_EN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 RDY
Set to enable interrupt when ADC is ready to convert.
(R/W)
12 ALERT
Enable Interrupt on Crossing Lower or Higher Limit.
(R/W)
11 OVF
Set to enable interrupt in case of overflow.
(R/W)
10 CALDONE
Set it to enable interrupt for calibration done.
(R/W)
0 CNVDONE
Set it to enable interrupt after conversion is done.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–43
ADuCM4050 ADC Register Descriptions
Channel 0 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 0
VALUE (R/W)
High limit value for channel 0
Figure 20-39: ADC_LIM0_HI Register Diagram
Table 20-26: ADC_LIM0_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 0.
(R/W)
11:0 VALUE
High limit value for channel 0.
(R/W)
20–44
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 0 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on
Channel 0
VALUE (R/W)
Low limit value for channel 0
Figure 20-40: ADC_LIM0_LO Register Diagram
Table 20-27: ADC_LIM0_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 0.
(R/W)
11:0 VALUE
Low limit value for channel 0.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–45
ADuCM4050 ADC Register Descriptions
Channel 1 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 1
VALUE (R/W)
High limit value for channel 1
Figure 20-41: ADC_LIM1_HI Register Diagram
Table 20-28: ADC_LIM1_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 1.
(R/W)
11:0 VALUE
High limit value for channel 1.
(R/W)
20–46
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 1 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on
Channel 1
VALUE (R/W)
Low limit value for channel 1
Figure 20-42: ADC_LIM1_LO Register Diagram
Table 20-29: ADC_LIM1_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 1.
(R/W)
11:0 VALUE
Low limit value for channel 1.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–47
ADuCM4050 ADC Register Descriptions
Channel 2 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 2
VALUE (R/W)
High limit value for channel 2
Figure 20-43: ADC_LIM2_HI Register Diagram
Table 20-30: ADC_LIM2_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 2.
(R/W)
11:0 VALUE
High limit value for channel 2.
(R/W)
20–48
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 2 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on
Channel 2
VALUE (R/W)
Low limit value for channel 2
Figure 20-44: ADC_LIM2_LO Register Diagram
Table 20-31: ADC_LIM2_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 2.
(R/W)
11:0 VALUE
Low limit value for channel 2.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–49
ADuCM4050 ADC Register Descriptions
Channel 3 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 3
VALUE (R/W)
High limit value for channel 3
Figure 20-45: ADC_LIM3_HI Register Diagram
Table 20-32: ADC_LIM3_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 3.
(R/W)
11:0 VALUE
High limit value for channel 3.
(R/W)
20–50
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Channel 3 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on
Channel 3
VALUE (R/W)
Low limit value for channel 3
Figure 20-46: ADC_LIM3_LO Register Diagram
Table 20-33: ADC_LIM3_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 3.
(R/W)
11:0 VALUE
Low limit value for channel 3.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–51
ADuCM4050 ADC Register Descriptions
Overflow of Output Registers
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TMP2 (R/W1C)
Indicates overflow in temperature 2
output register
CH0 (R/W1C)
Indicates overflow in channel 0 output
register
TMP (R/W1C)
Indicates overflow in temperature output
register
CH1 (R/W1C)
Indicates overflow in channel 1 output
register
BAT (R/W1C)
Indicates overflow in battery monitoring
output register
CH2 (R/W1C)
Indicates overflow in channel 2 output
register
CH7 (R/W1C)
Indicates overflow in channel 7 output
register
CH3 (R/W1C)
Indicates overflow in channel 3 output
register
CH6 (R/W1C)
Indicates overflow in channel 6 output
register
CH4 (R/W1C)
Indicates overflow in channel 4 output
register
CH5 (R/W1C)
Indicates overflow in channel 5 output
register
Figure 20-47: ADC_OVF Register Diagram
Table 20-34: ADC_OVF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10 TMP2
Indicates overflow in temperature 2 output register.
(R/W1C)
9 TMP
Indicates overflow in temperature output register.
(R/W1C)
8 BAT
Indicates overflow in battery monitoring output register.
(R/W1C)
7 CH7
Indicates overflow in channel 7 output register.
(R/W1C)
6 CH6
Indicates overflow in channel 6 output register.
(R/W1C)
5 CH5
Indicates overflow in channel 5 output register.
(R/W1C)
4 CH4
Indicates overflow in channel 4 output register.
(R/W1C)
20–52
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Table 20-34: ADC_OVF Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 CH3
Indicates overflow in channel 3 output register.
(R/W1C)
2 CH2
Indicates overflow in channel 2 output register.
(R/W1C)
1 CH1
Indicates overflow in channel 1 output register.
(R/W1C)
0 CH0
Indicates overflow in channel 0 output register.
(R/W1C)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–53
ADuCM4050 ADC Register Descriptions
ADC Power-up Time
15 14 13 12 11 10 9
0
0
0
0
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
0
0
WAIT (R/W)
Program this count to generate 20us
wait time with respect to the PCLK
frequency
Figure 20-48: ADC_PWRUP Register Diagram
Table 20-35: ADC_PWRUP Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10:0 WAIT
Program this count to generate 20us wait time with respect to the PCLK frequency.
(R/W)
20–54
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
ADC Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDY (R/W1C)
Indicates ADC is ready to start converting,
when using external reference buffer
DONE0 (R/W1C)
Indicates conversion done on Channel 0
DONE1 (R/W1C)
Indicates conversion done on Channel 1
CALDONE (R/W1C)
Indicates calibration is done
DONE2 (R/W1C)
Indicates conversion done on Channel 2
TMP2DONE (R/W1C)
Indicates conversion is done for temperature
sensing 2
DONE3 (R/W1C)
Indicates conversion done on Channel 3
TMPDONE (R/W1C)
Indicates conversion is done for temperature
sensing
DONE4 (R/W1C)
Indicates conversion done on Channel 4
DONE5 (R/W1C)
Indicates conversion done on Channel 5
BATDONE (R/W1C)
Indicates conversion done for battery
monitoring
DONE7 (R/W1C)
Indicates conversion done on Channel 7
DONE6 (R/W1C)
Indicates conversion done on Channel 6
Figure 20-49: ADC_STAT Register Diagram
Table 20-36: ADC_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RDY
Indicates ADC is ready to start converting, when using external reference buffer.
(R/W1C)
14 CALDONE
Indicates calibration is done.
(R/W1C)
10 TMP2DONE
Indicates conversion is done for temperature sensing 2.
(R/W1C)
9 TMPDONE
Indicates conversion is done for temperature sensing.
(R/W1C)
8 BATDONE
Indicates conversion done for battery monitoring.
(R/W1C)
7 DONE7
Indicates conversion done on Channel 7.
(R/W1C)
6 DONE6
Indicates conversion done on Channel 6.
(R/W1C)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–55
ADuCM4050 ADC Register Descriptions
Table 20-36: ADC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 DONE5
Indicates conversion done on Channel 5.
(R/W1C)
4 DONE4
Indicates conversion done on Channel 4.
(R/W1C)
3 DONE3
Indicates conversion done on Channel 3.
(R/W1C)
2 DONE2
Indicates conversion done on Channel 2.
(R/W1C)
1 DONE1
Indicates conversion done on Channel 1.
(R/W1C)
0 DONE0
Indicates conversion done on Channel 0.
(R/W1C)
20–56
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 ADC Register Descriptions
Temperature Result 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Temperature measurement
2 is stored here
Figure 20-50: ADC_TMP2_OUT Register Diagram
Table 20-37: ADC_TMP2_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Temperature measurement 2 is stored here.
(R/NW)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
20–57
ADuCM4050 ADC Register Descriptions
Temperature Result
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Temperature measurement
1 is stored here
Figure 20-51: ADC_TMP_OUT Register Diagram
Table 20-38: ADC_TMP_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Temperature measurement 1 is stored here.
(R/NW)
20–58
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
Real-Time Clock (RTC)
21 Real-Time Clock (RTC)
The ADuCM4050 MCU uses the real-time clock (RTC) that keeps track of elapsed time, in configurable time
units, using an externally attached 32,768 Hz crystal to generate a time base. When enabled, the RTC maintains a
cumulative count of elapsed time from the counts most recent redefinition (re-initialization) by the CPU or powerup value as applicable. The RTC can count from any configured initial value and roll-overs of the RTC count are
supported. The RTC is a 16-bit peripheral, but contains triple registers for any 47-bit quantities such as the elapsed
time count and alarm values.
The ADuCM4050 MCU has two real-time clock blocks, RTC0 and RTC1 (also called FLEX_RTC).
Each RTC has two configurable alarm features which permit the generation of absolute (exact time match) or periodic (every 60 increments of the RTC count) alarms.
Software is responsible for enabling and configuring the RTC and for interpreting its count value to turn this into
the time of day. The RTC logic also has a digital trim capability that is calibrated to achieve higher PPM accuracy in
tracking time.
RTC Features
The ADuCM4050 MCU supports the following features:
• An RTC count register with 32 integer bits and 15 fractional bits of elapsed time in configurable time units
from a programmable reference point (initial value). This register is programmed under software control.
• The RTC can count time in units of a divided-down period of the RTC base clock (nominally 32,768
Hz), where the division can be any power of two from zero to fifteen. The range of RTC time units is thus
30.52 μs to 1s.
When programming (initializing) or re-enabling the RTC count, or when changing the prescale division
ratio, the prescaler is automatically zeroed. This is so that the RTC count value is positioned on exact,
coincident boundaries of both the start of the prescale sequence and the modulo-60 count roll-over.
In practical terms, a CPU redefinition of the RTC count (elapsed time) can be deposited on coincident 1second and 1-minute boundaries, when using a time base of 1 second. The same capability is supported
by the RTC for any prescaled time base.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–1
RTC Functional Description
• Two optionally enabled, independent alarm features (one at absolute time and the other at modulo-60, periodic time) that cause a processor interrupt when the RTC count equals the alarm values. Note that such an interrupt wakes up the processor if the latter is in a sleep state.
• A digital trim capability whereby a positive or negative adjustment (in units of configured RTC time units) can
be added to the RTC count at a fixed interval to keep the RTC PPM time accuracy within target. The values
for both the adjustment and interval are calculated by running a calibration algorithm on the CPU.
• The RTC can take and preserve a snapshot of its elapsed real-time count when prompted to do so by the CPU.
This allows the CPU to associate a time stamp with an event such as incoming data packet. The RTC preserves
the snapshot for read-back by the CPU. The snapshot is persistent and is only overwritten when the CPU issues a request to capture a new value.
• RTC has four independent SensorStrobe channels with an alarm function. Each channel sends an output pulse
to an external device via GPIO, and instructs the device to measure or perform some action at a specific time.
The SensorStrobe events are scheduled by the CPU on the ADuCM4050 MCU by instructing the RTC to
activate the SensorStrobe events at a specific target time relative to the RTC real-time count. Duty-cycle and
frequency (0.5 Hz to 16384 Hz) of the output pulse can be configured.
• Each SensorStrobe channel can have up to three GPIO inputs from the external device, which can be sampled
based on the output pulse sent to the external device. Each SensorStrobe channel can be configured to interrupt the ADuCM4050 MCU when a specific activity is detected on these GPIO inputs from the external device. These inputs can broadcast sensor states like FIFO full, switch open, threshold crossed. This feature allows
the MCU to remain in a low power state and wake up to process the data only on specific activity.
• Input sampling is an optional feature of the RTC where dedicated GPIOs can be configured to be sampled on
the rising/falling edges of the SensorStrobe events.
• RTC has an input capture feature. Input capture is the process of taking a snapshot of the RTC real-time count
when an external device signals an event via a transition on one of the GPIO inputs to the ADuCM4050
MCU.
RTC Functional Description
This section provides information on the RTC functionalities of the ADuCM4050 MCU.
RTC Block Diagram
A high-level block diagram of the RTC is shown below. All functionality for counting, alarm, trim, snapshot and
wake-up interrupts is located in a dedicated 32 kHz timed, always ON RTC power domain. The APB interface with
the CPU, which comprises queuing and dispatch logic for posted register writes, along with interrupts to the Cortex
NVIC are all located in a PCLK/FCLK-timed (synchronous clocks) section of the main power-gated core domain.
21–2
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC Operating Modes
RTC
Clock Domain,
32 kHz
Crystal
Oscillator
Circuit
(Analog)
GPIOs
GPIOs
Processor
Clock Domain,
FCLK and PCLK
Digital
Trim
Prescaler
32 kHz
Base Clock
Prescaled, gated
32 kHz RTC time base
Snapshots /
Input
Capture
RTC
Count
Interrupt
Control
& Status
Clock
Domain
Crossing
Control
Alarms /
SensorStrobe
32 kHz FCLK
Posted
Write
Transaction
Engine
PCLK
GPIOs
FCLK-timed
IRQ to NVIC
FCLK
APB
Slave
Port
APB
PCLK
Interrupt
Control
32 kHz timed
wake-up IRQ to PMU
Figure 21-1: RTC High-level Block Diagram
The key use of the RTC is to provide time keeping functionality and maintain the time and date in an accurate and
reliable manner with minimal power consumption. In addition to time keeping, it also provides stopwatch and
alarm features. The RTC uses internal counters to keep the time of the day in terms of seconds, minutes, hours, and
days. This data is enough for the user application to extract the date and time information from RTC. Interrupts
can be issued periodically.
RTC Operating Modes
The RTC used by the ADuCM4050 MCU supports the following operations.
Initial RTC Power-Up
The RTC operates in a dedicated voltage domain which, under normal (configurable) conditions, is always powered.
However, when a battery is attached for the first time or replaced, a power-on reset occurs which resets all RTC
registers.
Upon detecting an RTC failure, the CPU will typically reprogram the RTCs count and digital trim registers and
clear the fail flag in the RTC control register. The CPU can optionally program the alarm registers of the RTC to
generate an interrupt when the alarm and count values match.
Persistent, Sticky RTC Wake-Up Events
There is no loss of any RTC alarm event that happens when the part is in a power down mode. The resulting interrupt due to the alarm, assuming it is enabled, is maintained in an asserted state by the RTC so that the NVIC will
subsequently see it (FCLK timed version of the interrupt) when power is restored to the processor. To facilitate this,
the RTC sends a 32 kHz-timed version of the same interrupt to the wake-up controller in the PMU which causes
the digital core to be repowered. Once the CPU is woken up, it can inspect both the PMU and RTC to understand
the cause of the interrupt event for the wake-up.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–3
RTC Operating Modes
RTC Capacity to Accommodate Posted Writes by CPU
If a posted write by the CPU to a 32 kHz-sourced MMR in the RTC is pending dispatch (in the RTC) due to a
queue of other, similar register writes to the 32 kHz domain, a second or subsequent write by the CPU to the same
RTC register cannot be stacked up or overwrite the pending transaction. Any such attempts will be rejected by the
RTC. These result in RTC_SR0.WPNDERRINT interrupt events in the RTC (see the MMR details of RTC_SR0).
Realignment of RTC Count to Packet Defined Time Reference
The CPU can instruct the RTC to take a snapshot of its elapsed time count by writing a software key of 0x7627 to
the RTC_GWY MMR. This causes the combined three snap registers (RTC_SNAP2, RTC_SNAP1, and
RTC_SNAP0) to update to the current value of the three count registers (RTC_CNT2, RTC_CNT1, and
RTC_CNT0) and to maintain this snapshot until subsequently told by the CPU to overwrite it.
RTC Recommendations: Clocks and Power
The following recommendations apply for using the RTC.
PCLK and FCLK Frequency
When RTC writes are in progress, PCLK and FCLK frequency must not drop below 1 MHz. RTC clock must be at
least 30 times slower than PCLK and FCLK.
Stopping PCLK
Before entering any mode which causes PCLK to stop, the CPU must first wait until there is confirmation from the
RTC that no previously posted writes are yet to complete. The CPU can check this by reading both the RTC_SR0
and RTC_SR2 registers.
Ensuring No Communication across RTC Power Boundary when Powering Down
When the CPU has advance knowledge about a power down, it must take the following action to ensure the integrity of always-on part of the RTC.
• Either :
The CPU must verify that there are no posted writes in the RTC awaiting execution.
• Or :
Cancel all queued and executing posted writes in the RTC. This is achieved by writing a cancellation key of
0xA2C5 to the RTC_GWY register which takes immediate effect.
• And :
Do not post any further register writes to the RTC until power is lost by the core.
These steps ensure that no communication between the CPU and the RTC is ongoing and thus liable to corruption
when the RTC power domains isolation barrier is subsequently activated.
21–4
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC Interrupts and Exceptions
RTC Interrupts and Exceptions
The RTC block can generate interrupts from multiple sources which can be unmasked by programming the control
register. The source of the interrupt is reflected in the Status register.
RTC Programming Model
The following section shows the programming sequence to configure RTC for an alarm event.
Programming Guidelines
The following are the programming guidelines:
1. Reset the RTC_CNT registers to 0.
2. Configure the prescaler to divide the RTC base clock in the RTC_CR1 register.
3. Poll for the RTC synchronization bit to be set in the RTC_SR1 register, as the MMR write happens in the
slower RTC domain.
4. Program the RTC_ALM0, RTC_ALM1, RTC_ALM2 registers with the intended alarm time.
5. Enable the interrupt for alarm by setting the RTC_CR0.ALMINTEN bit.
6. Set the RTC_CR0.ALMEN and RTC_CR0.CNTEN bits.
7. Wait for the RTC alarm interrupt which is triggered when the RTC_CNT matches with the RTC_ALM value.
RTC SensorStrobe
SensorStrobe is an alarm mechanism in the RTC. It sends an output pulse to an external device via GPIO, and instructs the device to measure or perform some action at a specific time. The SensorStrobe events are scheduled by
the CPU on the ADuCM4050 MCU by instructing the RTC to activate the SensorStrobe events at a specific target
time relative to the RTC real-time count.
The alarm time is programmed in the RTC by the CPU, typically before going into hibernate. When a SensorStrobe
event occurs, the RTC can optionally cause the CPU to be woken up and interrupted to examine the results of the
sensor obtained via the GPIO.
The input sampling feature is used to monitor the external device at specific time intervals. This period is controlled
by the SensorStrobe channel output. At a defined rate, inputs from the external device are sampled through dedicated GPIO inputs. When a specific programmed sequence from the external device is detected via these GPIO inputs,
the RTC can optionally cause the CPU to be woken up and interrupted to process the incoming data.
The RTC1 on the ADuCM4050 MCU has five SensorStrobe channels—SS0 (alarm only), SS1, SS2, SS3, and SS4.
These channels act as alarms scheduled in the RTC by the CPU. When a SensorStrobe event (alarm) occurs, the
channel toggles an output control line. This output is routed through a fixed GPIO pin for the channel concerned
and exported off chip.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–5
RTC SensorStrobe
Currently, the ADuCM4050 MCU has GPIO support for SS1, SS2, SS3, and SS4. SS0 is the 47-bit alarm feature
of the RTC without GPIO connectivity.
RTC0 has no SensorStrobe functionality.
The figure shows the SensorStrobe channels and how they align to the main RTC count.
15
RTC_CNT1
0
15
RTC_CNT0
0
15 14
RTC_CNT2
0
32-bit integer and 15-bit
fractional RTC count
Configurable
Compare
Unmasked for
Sensor
Strobe
Match
Masked
for Sensor
Strobe Match
RTC_ALM1
46
14
SS1
RTCSS1TGT
0
16 bit SensorStobe Alarm
SS1 (1 channel), when
prescaling by 215 to 1 Hz
M
14
SS1
RTC_SS1TGT
0
Bit 15 of SS1 target
time optionally masked out
M
M 13
0
Contiguous bits [15:14]
optionally masked out
M
M M 12 RTC_SS1TGT 0
Contiguous bits [15:13]
optionally masked out
M
SS1
M
M 0
RTC_SS1TGT
M
M
SS1
RTC_SS1TGT
SS1
...and so on, down to...
For all prescaled
alignments of the 16-bit
SS1 channel,
contiguous bit positions at
the MSB end of the
SensorStrobe Target
time can optionally be
masked out of a match
comparison against
corresponding bits in the
RTC Count Integer register
RTC_CNT0 and fractional
register RTC_CNT2
15
15
15
SS1
RTC_SS1TGT
2
15
SS1
RTC_SS1TGT
0
0
15
RTC_ALM0
0
31
30
SS0
SS1
RTC_SS1TGT
15
M
1
0
Alignment of 16-bit
SensorStrobe Channel, SS1
tracks prescaling of RTC time
base by any power of 2
15 14
14
RTC_ALM2
0
0
Contiguous bits [15:1]
optionally masked out
All bits
optionally masked out
16-bit SensorStrobe Alarm
SS1 (1 channel), when
prescaling by 22 to 8 kHz
16-bit SensorStrobe Alarm
SS1 (1 channel), when
prescaling by 20 to 32 kHz
SS0 is a 47 -bit SensorStorbe
Channel, which reuses
the RTC_ALM1/0/2 Alarm registers
Figure 21-2: RTC SensorStrobe Channels
The 47-bit SensorStrobe channel (SS0) is a synonym of the 47-bit alarm feature in the RTC defined by the
RTC_ALM1, RTC_ALM0, and RTC_ALM2 registers. This is an absolute-time alarm, unmaskable in any of its bit
positions and whose time span before the alarm repeats is equal to the length of the RTC count.
To use SS0 for frequent SensorStrobe activations, the CPU must reprogram the alarm time in the RTC_ALM1/
RTC_ALM0/RTC_ALM2 registers each time it is woken up and interrupted by the RTC upon an SS0 event. SS0
does not have GPIO activation associated with it.
The 16-bit SensorStrobe channels—SS1, SS2, SS3, and SS4 have a shorter time span, but more versatile than SS0.
They align the 16 usable bits for prescaling the RTC integer count time base.
The RTC_SSMSK register masks the contiguous MSB bits of its target time to reduce the periodicity of repeating
alarms (as shown in the RTC SensorStrobe Channels figure). The RTC_SSMSKOT register also masks the contiguous LSB bits of its target time to control high duration of the pulse. The 16-bit SensorStrobe channels—SS1, SS2,
SS3, and SS4 support optional auto-reloading for alarm periods which are not powers of 2 with respect to 32 kHz
clock period. Each SensorStrobe channel has a fixed GPIO associated with it to export a one-cycle activation of its
SensorStrobe line.
21–6
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC SensorStrobe
RTC SensorStrobe Channels figure shows three example degrees of prescaling (215, 22, and 20) of the RTC time
base. It shows how the 16 bits of the alarm time for SS1, SS2, SS3, and SS4 align with the degree of prescaling of
the 32 kHz clock.
All the fractional bits in the RTC_CNT2 register consistent with the configurable prescaling are compared with the
corresponding bit positions of the alarm time specified by SS1, SS2, SS3, and SS4 when checking for a SensorStrobe
match. The remaining bits are compared with the LSB end of the RTC_CNT0 register. This self-aligning of SS1,
SS2, SS3, and SS4 with the RTC_CNT2 and RTC_CNT0 registers based on prescaling is supported for all prescale
powers of 2 between 0 and 15.
SensorStrobe for two types of periodicity of alarms (SensorStrobe events):
• Periods which are a power of 2 with respect to the 32 kHz clock: Comparisons are made repeatedly between the
value in the SSx bits (x = 1, 2, 3, 4) in the RTC count, suitably aligned for prescaling.
Period = ((RTC_CR4SS.SSxMSKEN ?2RTC_SSMSK.SSxMSK: 216)) / 32768 seconds
On Time = 2SSMSKOT.SSxMSKOT / 32768 seconds
• Periods which are not a power of 2: Comparison is done by auto-reloading (cumulatively adding to the existing
content in the SSx) an offset value in the RTC_SSxHIGHDUR and RTC_SSxLOWDUR (x = 1, 2, 3) into
SSx (x = 1, 2, 3, 4) every time an SensorStrobe event occurs.
Period = (RTC_SSxLOWDUR + RTC_SSxHIGHDUR) / 32768 seconds
On Time = RTC_SSxHIGHDUR / 32768 seconds
The target time for an upcoming event on the SensorStrobe channel can be read by the CPU via the RTC_SSxTGT
register. For SensorStrobe that does not use auto reloading, the live value in the RTC_SSxTGT register is same as
the value of SSx (x = 1, 2, 3, 4) , as the step size between events is defined by the SSx. When auto-reloading is
used, the live value in the RTC_SSxTGT register reflects the repeated, cumulative, modulo-16 addition of the
RTC_SSxHIGHDUR and RTC_SSxLOWDUR to a starting value of the SSx. RTC_SSxTGT always allows the
CPU to know when a SensorStrobe event is due, in terms of a match between RTC_SSxTGT and RTC count.
All SensorStrobe channels can be partially masked on both MSB and LSB end of target. Masking allows shortening
of the period of recurrence of SensorStrobe events by considering the bit positions of the target time and RTC count
as Don’t Cares and contiguous matching in case of LSB masking. When a 16-bit SensorStrobe match check is carried out for SSx against the RTC count, contiguous bits at the MSB end of SSx and RTC_SSxTGT can optionally be masked, thereby becoming Don’t Cares (shown as M-bit positions in the figure). The number of contiguous
bits masked out in the SSx and RTC_SS1TGT are specified by RTC_SSMSK and RTC_SSMSKOT.
Each SensorStrobe channel has a dedicated GPIO output via which output pulses are exported outside the chip.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–7
RTC SensorStrobe
RTC Input Sampling
It is an optional feature associated with the SensorStrobe channel. Each SensorStrobe channel (SSx, where x = 1, 2,
3) has up to 3 GPIO inputs (SSxGPINy, y = 0, 1, 2). These inputs are sampled based on the output capture
events.
The falling edge, rising edge, or both SensorStrobe events can be used to sample the inputs. Sampled input for each
channel is available as a non-sticky read back status in the RTC_SR7.SSxSMP field (updated when next sample is
used). This allows periodic and controlled sampling of external activity generated by the sensor. Six sampling edges
are available for each output pulse.
RTC_SSx
Falling Edge
Rising Edge
32.768 kHz
RTC Clock
Before Falling Edge
Falling Edge
After Falling Edge
Before Rising Edge
Rising Edge
After Rising Edge
Figure 21-3: Sampling Edges
Sensor activity monitoring is achieved by generating an optional interrupt when the current sample matches with
certain behavior. One of the following sequence can be selected for this:
• Current sample (SMPnt) is different from a previously sampled value(SMPnt-1) or
• Current sample (SMPnt) is same as the previously sampled value(SMPnt-1) or
• Current sample (SMPnt) matches the expected sample value (EXP_SMPn) or
• Current sample (SMPnt) does not match the expected sample value (EXP_SMPn)
RTC_SSx
32.768 kHz
RTC Clock
SMPnt-1
SMPnt
SSxGPINy
Figure 21-4: RTC Input Sampling
The sticky status bit is available in the RTC_SR7 register denotes that the programmed sequence has occurred in
the sensor interface. This status bit can be optionally exported as interrupt to CPU. It allows the CPU to stay in low
power mode and wake up only when the programmed sequence occurs the sensor interface.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC SensorStrobe
Each SensorStrobe channel (SS1, SS2, SS3, and SS4) can select up to 3 GPIO inputs from available 8 dedicated
GPIOs by configuring the RTC_GPMUX0 and RTC_GPMUX1 registers. Selected GPIOs must be configured as an
input to monitor external activity.
GPMUX0/1.SSxGPINySEL
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
SSxGPINy
P0_12
P2_00
P0_09
P0_08
P1_13
P1_02
P2_07
P2_09
The following are the SensorStrobe capabilities of hibernate real time clock (RTC1) on the ADuCM4050 MCU:
• Supports four SensorStrobe channels (SS1, SS2, SS3, and SS4) with GPIO activation:
• 16-bit channels. The target time for the 16-bit channel is specified as:
{least_significant_integer_bits_to_bring_total_to_16,
fractional_bits_due_to_prescaling}
The total number of bits in this concatenated capture time is 16.
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHz
base clock. The number of fractional bits used in the input capture function tracks with the prescaling.
The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of
the RTC. The number of integer bits combined with the fractional bits (due to prescaling) must be 16.
• There is a 47-bit alarm feature in the RTC. However, there is no GPIO associated with it to act as a SensorStrobe channel. The target time for this 47-bit alarm is specified as:
{32_integer_bits, 15_fractional_bits}
• For SensorStrobe channel, the target time is always specified down to an individual 32 kHz clock cycle as all
relevant fractional bits are included in the target time.
• For the 16-bit SensorStrobe channels—SS1, SS2, SS3, and SS4, contiguous bits in the 16-bit target time can
be thermometer-code masked out, on a per-channel basis, from the MSB end of the target.
As a result of this optional masking, the contiguous bits at the MSB end of the target time are treated as Don’t
Cares, which results in dividing the periodicity of the repeating SensorStrobe event by 2 for every bit masked
out.
In other words, if more bits are masked out from the MSB end of the target time, the modular sequence of
repeating SensorStrobe events is shortened by a factor of 2 for that channel.
• For a 16-bit sensorstrobe channel, contiguous bits in the 16-bit target time can be thermometer code masked
out, on a per channel basis, from the LSB end of the target. As a result of this optional masking, the contiguous
bits at the LSB end of the target time are treated as Don’t Cares, which results in continuous match and hence
controlling the high duration of the output pulse. High duration of SensorStrobe channel scales by 2 for every
bit masked out in LSB.
In other words, if more bits are masked out from the LSB end of the target time, the high duration of senstrobe
events is increased by a factor of 2 for that channel.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–9
RTC SensorStrobe
• Auto Reload: Each time an event triggers, a configurable 16-bit delta (reload value) is added to its target time
to calculate the revised target for the next event. The reloaded value is derived from the low and high duration
registers. When the output pulse goes low due to a falling/rising edge event, the low/high duration value is used
as reload value and the next target is set for rising/falling edge event. This allows the periodicity and high duration of repeating events to be created on this channel which is not a power of two with respect to the 32 kHz
clock.
The reloaded target time can be read by the CPU to confirm the accumulation due to reloading with each
event on that SensorStrobe channel. The reloaded target can also be contiguously masked from the MSB end.
• The SensorStrobe channel has a readable, sticky interrupt source bit, which activates (sticks high) whenever a
SensorStrobe event occurs. Separate bits are available for falling edge and rising edge events. This interrupt
source bit can optionally be enabled to fan into the interrupt and wake-up lines from the RTC.
• The SS1, SS2, SS3, and SS4 output pulses are exported by the RTC via the GPIOs, to an external device,
prompting the device to act.
The exported pulses are on a dedicated-channel basis from the RTC to external device connected to the channel. A pulse on one SensorStrobe channel has no effect on other SensorStrobe channels. A non-inverted or an
inverted version of output pulse can be exported on a per-channel basis. Optionally, inverted version of SSx (x
= 1, 3) can be exported via GPIO of SSy (y = 2, 4) respectively. These channel pairs can be used for differential pairing. There is no broadcast function, where a SensorStrobe event on one channel can be routed to all
SensorStrobe channels and external devices.
• Each SensorStrobe channel can select up to 3 GPIO inputs from the available 8 GPIOs. These inputs are sampled with respect to the output pulse event as configured. The latest sampled value is available as a non-sticky
readback status. Optionally, an interrupt can be sent to the CPU when a specified sequence occurs on the sampled value.
• The SensorStrobe channel can be reconfigured and enabled/disabled on the fly, with no interruption to channels that are not part of the reconfiguration.
• A SensorStrobe channel is independent of input capture channels in the RTC.
RTC SensorStrobe Channel Waveforms show how the SensorStrobe for the SS1 channel works in the RTC.
21–10
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC SensorStrobe
32 kHz
Clock
RTC_CNT2[1:0]
Fractional
RTC count
01
00
RTC_CNT1,
RTC_CNT0
10
11
11
01
00
32'h0000_0000
10
11
00
32'h0000_0001
01
10
11
32'h0000_0002
PRESCALE2EXP = 4'b0010 : Prescale the RTC base 32 kHz clock by 2 2 = 4 for integer RTC count time base : Defines roll-over and significant bits of RTC_CNT2
RTC_SSMSK [3:0] = 4'b0010 : Mask out contiguous bits of SS1 and RTC_SS1TGT from the MSB end down to and including bit 2 when comparing against the RTC count
RTC_SS1 = 16'bxxxx_xxxx_xxxx_xx11 : Starting compare time, where “x” indicates a “don’t-care” bit value because of the RTC_SSMSK setting
RTC_SS1TGT = 16'bxxxx_xxxx_xxxx_xx11 : Target compare time (no auto-reloading), where “x” indicates a “don’t-care” bit value because of the RTC_SSMSK setting
GPIO (no auto-reloading)
SS1IRQ (no auto-reloading)
IRQ reasserted
IRQ reasserted
SS1ARLEN = 1'b1 : Enable auto-reloading (cumulative, additive target time) for SS1
RTCSS1_HIGHDUR = 16’d1, RTC_SS1LOWDUR = 16’d6 : Auto Reload Values
(3 + 1) Mod 4
RTC_SS1TGT
(with auto-reloading)
3
0
(0 + 6) Mod 4
2
(2 + 1) Mod 4 (3 + 6) Mod 4
3
1
(1 + 1) Mod 4
(2 + 6) Mod 4
2
0
GPIO (with auto-reloading)
SS1IRQ (with auto-reloading)
IRQ reasserted
IRQ reasserted
Figure 21-5: RTC SensorStrobe Channel Waveforms
The figure shows the occurrence of the SensorStrobe events when the RTC prescales the base 32 kHz clock by 22
(giving two meaningful, fractional bits in the RTC_CNT2 register). SensorStrobe is supported for all prescaling powers of 2 between 0 and 15, selected via RTC_CR1.PRESCALE2EXP.
The settings in red show a SensorStrobe event occurring on the SS1 channel for every four cycles of the 32 kHz
clock. The event has a period which is a power of two cycles due to the absence of auto-reloading, disabled via
RTC_CR4SS.SS1ARLEN. The value in the SS1 register defines the target time. Only two least significant bits of
SS1 are compared with the RTC count due to the mask setting in the RTC_SSMSK register. The number of unmasked bits (2) defines the periodicity of the compare events, as the unmasked target time 2'b11 at the LSB end of
SS1 is matched with every four increments of the RTC_CNT2 register.
The settings in blue show an equivalent sequence of SensorStrobe events with auto-reloading enabled. The effects of
the cumulative addition on the target time can be seen in the RTC_SS1TGT register. When auto-reloading is enabled, the initial target time is the value of SS1, but on activation of each event, the value of the
RTC_SS1HIGHDUR and RTC_SS1LOWDUR are added to the content existing in the RTC_SS1TGT register, allowing roll-overs in the addition. As the SensorStrobe match considers the masking specified in the RTC_SSMSK
register, cumulative addition when auto-reloading undergoes modulo operation (modular addition). Modulo operation is 2 Number of unmasked bits in the comparison.
The figure shows two unmasked LSBs of the auto-reload value (2'b11) being added cumulatively to the unmasked
bits of the RTC_SS1TGT. The result is subjected to a modulo-4 operation. The period of the compare events is
specified by the unmasked bits of the auto-reload value.
Masking and auto-reloading are optional features of the RTC.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–11
RTC SensorStrobe
There is an automatic alignment to the LSB end of the RTC count by the 16 bits (considering prescaling) in the
following:
• Initial target time in RTC_SS1
• Cumulative target time in the RTC_SS1TGT
• Any possible mask decoded from the RTC_SSMSK
When a SensorStrobe event occurs, a GPIO output is activated for one 32 kHz cycle along with the assertion of a
sticky interrupt source (RTC_CR3SS.SS1IRQEN), to record the occurrence of a new compare event since the
CPU last cleared this interrupt source bit. The CPU can optionally enable RTC_CR3SS.SS1IRQEN to contribute
to the activation of the RTC interrupt lines to the wake-up controller and NVIC. This is used to wake up the CPU
from hibernate and examine the results from an external sensor device prompted by an RTC SensorStrobe event to
perform an action.
32 Hz
Clock
RTC_SS1HIGHDUR = 4, RTC_SS1LOWDUR = 6
GPIO
SS1 output pulse
RTC_CR6SSS.SS1SMPONFE = 2'b10 : Sample input on falling edge of SS1.
RTC_CR6SSS.SS1SMPONRE = 2'b00 : No sample taken on rising edge of SS1.
GPIO
Input to be sampled
x
RTC_SR7.SS1SMP
read back value
RTC_SR7.SS1SMPMTCHIRQ
5
x
RTC_CR7SSS.SS1SMPPTRN = 2'b00 : Interrupt if sampled value changed from previous.
RTC_CR5SSS.SS1SMPEN = 3'b011 : Only lower two inputs are valid on sampled data, Any change in MSB is ignored as it is not enabled
x
7
x
5
3
7
IRQ Asserted (5 to 7 transition
has lower two bits changing)
x
3
No new IRQ Asserted (7 to 3 transition
has lower two bits constant)
Figure 21-6: RTC Input Capture
The figure shows the SensorStrobe sampling mechanism. The RTC_CR6SSS.SSxSMPONFE and
RTC_CR6SSS.SSxSMPONRE fields enable the sampling of input GPIOs around the falling and rising edge of
output pulse sent. In this example, inputs are sampled/recorded only on the falling edge of output pulse as per the
configuration. The sampling point and sampled value are marked in blue. At the first sampling point, the inputs
have value 5. At the next sampling points, it has values 7 and 3. These values are available as readback to user in the
RTC_SR7.SS1SMP field.
The core is configured to be interrupted only when inputs change (RTC_CR7SSS.SS1SMPPTRN is 2'b00). Only
two out of available 3 inputs are enabled. The RTC_CR5SSS.SS1SMPEN has a value of 3'b011. It denotes that
only 2 LSBs are considered and MSB is a Don’t Care.
For the first sample 5 (3'b101), interrupt is not generated as there is no reference to the previous sample. Also, interrupts are not generated.
For the next sample 7 (3'b111), lower two change and interrupt is sent to the core.
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC Input Capture
For the third sample 3 (3'b011), both LSBs are same as the previous and new interrupt is not generated.
The following table shows the summary of the Sensorstrobe channels.
Table 21-1: SensorStrobe Mechanism
SensorStrobe
Channel
Polarity Control
SS1
On/Off Time
On/Off Time
Mask Control
Interrupt Edge
Selection
Input Sampling
Differential Output Pairs
Yes
Yes
Yes
Yes
Yes
Yes
SS2
Yes
Yes
Yes
Yes
Yes
Yes
SS3
Yes
Yes
Yes
Yes
Yes
Yes
SS4
Yes
Yes
Yes
No
No
Yes
Fine control
Table 21-2: SensorStrobe Lookup Table
RTC_SSx
SensorStrobe Parameters
On Time (RTC Clocks)
RTC_CR4SS.
SSxMSKEN = 0
RTC_CR4SS.
SSxMSKEN = 1
RTC_CR4SS.
SSxMSKEN = 0
RTC_CR4SS.
SSxMSKEN = 1
RTC_CR4SS.
SSxARLEN = 0
RTC_CR4SS.
SSxARLEN = 0
RTC_CR4SS.
SSxARLEN = 1
RTC_CR4SS.
SSxARLEN = 1
(x = 1, 2, 3, 4)
(x = 1, 2, 3, 4)
(x = 1, 2, 3)
(x = 1, 2, 3)
RTC_SSxHIGHDUR.
SSxHIGHDUR
(RTC_SSxHIGHDUR.
SSxHIGHDUR)
2RTC_SSMSKOT.SSxMSKOT
% 2 SSxMSK
Period (RTC Clocks)
RTC_CR4SS.RTC_SSxMSKEN?
(2RTC_SSMSK.SSxMSK) : 216
RTC_SSxHIGHDUR.
SSxHIGHDUR +
RTC_SSxLOWDUR.
SSxLOWDUR
(RTC_SSxHIGHDUR.
SSxHIGHDUR +
RTC_SSxLOWDUR.
SSxLOWDUR)
% 2 SSxMSK
Illegal Case
NA
RTC_SSMSK.SSxMSK
≤
RTC_SSMSKOT.
SSxMSKOT
On Time = 0 Or Period = RTC_SSMSKOT.
SSxMSKOT != 0 Or On
0
Time = 0 Or Period = 0
RTC Input Capture
Input capture is the process of taking a snapshot of the RTC real-time count when an external device signals an
event via a transition on one of the GPIO inputs to the ADuCM4050 MCU. An input capture event is triggered by
an autonomous measurement or action on a device, which then signals to the ADuCM4050 MCU that the RTC
must take a snapshot of time corresponding to the event. Taking a snapshot can wake up the ADuCM4050 MCU
and interrupt the CPU. The CPU can subsequently obtain information from the RTC on the exact 32 kHz cycle
and exact time of the input capture event.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–13
RTC Input Capture
The RTC1 on the ADuCM4050 MCU has four input capture channels—RTCIC0, RTCIC2, RTCIC3, and
RTCIC4. RTCIC2, RTCIC3 and RTCIC4 are 16-bit input capture channels. RTCIC0 is a 47-bit wide channel.
Each of these independent channels can take a snapshot of the RTC count when a rising edge or falling edge event
(one of these edge types is selected per channel) occurs on a GPIO associated with that channel. The snapshots are
used to time stamp the inputs from external sensors devices for subsequent examination and processing by the CPU
(once woken up).
Input capture snapshots are accurate down to a single 32 kHz clock period for all prescaling by the RTC of this
clock. Prescaling is the process of dividing the 32 kHz clock by any power of 2 (between 0 and 15), to create a
slower time base and count the integer time in the RTC_CNT1 and RTC_CNT0 registers. Fractional time for this
time base is simultaneously counted in the RTC_CNT2 register in the units of 32 kHz clock periods. Each input
capture channel has a fixed GPIO pin to prompt the snapshot of RTC time to be taken when an edge (rising or
falling) occurs on the GPIO.
The RTCIC0 channel, unlike its counterparts, can also take a software-initiated snapshot when the CPU writes a
special key to the RTC.
The 16-bit input capture channels takes snapshots based on the degree of prescaling in the RTC for the integer
count time base, and align themselves accordingly. The 16-bit snapshots contain fractional bits in RTC_CNT2 register that are relevant for prescaling, and additional bits from the LSB end of the RTC_CNT0 register.
RTCIC0 snapshots all the bits from the RTC_CNT1, RTC_CNT0, and RTC_CNT2 registers. This gives a full, absolute-time snapshot for an event on the RTCIC0 channel. Other 16-bit input capture channels only have a time
span (uniqueness of the snapshot) equivalent to 216 periods of the 32 kHz clock.
The alignment of snapshots with the main RTC count is shown in the Input Capture Channels: 16-bit and 47-bit
Snapshots of RTC Count figure. It contains three example degrees of prescaling (215, 22, and 20) of the RTC time
base. All powers of 2 between 0 and 15 used in prescaling are supported for the 16-bit input capture channels.
15
RTC_CNT1
0
15
RTC_CNT 0
0
15 14
15
14
RTC_CNT2
0
32-bit integer and 15-bit
fractional RTC count
0
16-bit Input Capture
snapshots (3 channels) when
prescaling by 215 to 1 Hz
0
16-bit Input Capture
snapshots (3 channels) when
prescaling by 22 to 8 kHZ
Capture
15
46
RTC_SNAP1
15 RTC_IC2/3/4
2
15
RTC_IC2/3/4
0
0
15
RTC_SNAP 0
0
31
30
RTC_IC0
15
RTC_IC2/3/4
1
15 14
14
Alignment of 16-bit
16-bit Input Capture
Input Capture Channels
snapshots (3 channels) when
RTC_IC2/3/4, tracks
prescaling by 20 to 32 kHZ
prescaling of RTC time
base by any power of 2
RTC_IC0 is a 47-bit Input
0
RTC_SNAP2
Capture Channel, which reuses
RTC_SNAP 1/0/2 registers.
0
Figure 21-7: RTC Input Capture Channels: 16-bit and 47-bit Snapshots of RTC Count
Each input capture channel has an independent control of the following features and can be changed on-the-fly
without affecting the other channels:
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ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC Input Capture
• Enable/disable channel
• Polarity of the active-going edge, rising or falling, of the GPIO to prompt snapshots
• Enable to interrupt upon a capture event
• Sticky interrupt source for a capture event
• Read/unread status of a capture snapshot by the CPU
A common configurable setting RTC_CR2IC.RTCICOWUSEN is applied to all input capture channels. It is used
to select between allowing new snapshots overwrite unread previous ones on a per-channel basis, and having the
input capture snapshots stick until read by the CPU. While the same policy on overwriting snapshots applies to all
channels, each channel enforces it independently.
The following are the input capture capabilities of the hibernate real-time clock (RTC1) on the ADuCM4050
MCU:
• Supports four independent input capture channels (three 16-bit channels and one 47-bit channel):
• The three 16-bit channels snapshot the RTC elapsed count using 16 bits as follows:
{least_significant_integer_bits_to_bring_total_to_16,
fractional_bits_due_to_prescaling}
The total number of bits in this concatenated capture time is 16.
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHz
base clock. The number of fractional bits used in the input capture function tracks with the prescaling.
The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of
the RTC. The number of integer bits combined with the fractional bits (due to prescaling) must be 16.
• The 47-bit channel captures the absolute time for that input capture channel, where the capture time is
given as {32_integer_bits, 15_fractional_bits}.
• For each of the four input capture channels, the snapshot always has a resolution down to an individual 32 kHz
clock cycle as all relevant fractional bits are included in the capture time.
• When an input capture event is detected by the RTC, the accuracy of the snapshot time for the event is as
follows:
• For the three 16-bit input capture channels, each channel captures a snapshot which is exact in time down
to the 32 kHz cycle in which the event occurred.
• For the one 47-bit input capture channel, there is a fixed latency (delay) of one 32 kHz cycle of fractional
time in the snapshot value captured for that event.
This latency of one LSB of the fractional count can be subtracted later by the software.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–15
RTC Input Capture
• An input capture event can be configured as a low-to-high or high-to-low transition on the GPIO input for
that channel. The polarity of this transition can be configured on a per-channel basis. The input capture
channels can individually specify the type of transition that must cause an event for it.
• Each of the four input capture channels has a readable, sticky interrupt source bit, which activates (sticks high)
whenever an input capture event occurs. This interrupt source bit can optionally be enabled to fan into (be a
contributory term to) the interrupt and wake-up lines from the RTC.
• User can configure one of the following global overwrite policy for all the input capture channels in the RTC:
• When a new input capture event occurs on a given channel, the new snapshot value overwrites the previously captured value for that individual channel.
• For a given channel, snapshot can be overwritten by a new event only if the CPU has already read the
existing snapshot value for that channel.
NOTE: In addition to the readable interrupt sources, which stick active upon reception of new input capture events, the RTC also provides flags to the CPU confirming the read/unread status of the input capture snapshots. This aids the CPU if it is uses a policy of not allowing the unread snapshots to be overwritten by new events on the input capture channels.
• The input capture channels can be reconfigured and enabled/disabled on-the-fly, with no interruption to the
channels not part of the reconfiguration.
• The input capture channels operate independently of each other and independently of SensorStrobe channel in
the RTC.
RTC Input Capture Channels Waveforms show the input capture operation in the RTC. It shows the occurrence of
the capture events while the RTC prescales the 32 kHz base clock by 22 (giving two meaningful, fractional bits in
RTC_CNT2), but the input capture is supported for all prescaling powers of two between 0 and 15 (selected via
RTC_CR1.PRESCALE2EXP).
21–16
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
RTC Power Modes Behavior
32 kHz
Clock
GPIO
PRESCALE2EXP = 4'b0010 : Prescale the RTC base 32 kHz clock by 22 = 4 for integer RTC count time base : Defines roll-over and significant bits of RTC_CNT2
RTC_CNT2[1:0]
Fractional
RTC count
RTC_CNT1,
RTC_CNT0
Integer RTC count
00
01
10
11
00
32'h0000_0000
01
10
11
00
32'h0000_0001
01
10
11
32'h0000_0002
RTCIC0/2/3/4LH = 1'b1 : Take input -capture snapshots of the RTC count at the rising edge of the GPIO
RTCIC0/2/3/4 : Snapshots of RTC count
RTCIC2/3/4 = 16'b0000_0000_0000_0001
RTCIC0
= {32'h0000_0000, 15'b000_0000_0000_0001}
RTCIC0/2/3/4IRQ :
Interrupt due to input capture on rising edge of GPIO
RTCIC0/2/3/4LH = 1'b0 : Take input -capture snapshots of the RTC count at the falling edge of the GPIO
RTCIC0/2/3/4 : Snapshots of RTC count
RTCIC2/3/4 = 16'b0000_0000_0000_0110
RTCIC0
= {32'h0000_0001, 15'b000_0000_0000_0010}
RTCIC0/2/3/4IRQ :
Interrupt due to input capture on falling edge of GPIO
Figure 21-8: RTC Input Capture Channels Waveforms
For a given input capture channel, the RTC_CR2IC.RTCIC2LH/RTC_CR2IC.RTCIC3LH/
RTC_CR2IC.RTCIC4LH fields allow the user to take the snapshot of the RTC time on the rising edge or falling
edge of the GPIO (not both edges). When an input capture event occurs, a 16-bit input capture channel stores the
current value of the 16 meaningful LSBs (accounting for prescaling) from the RTC_CNT2 and RTC_CNT0 registers
necessary to identify the individual 32 kHz cycle in which the GPIO edge has occurred. The 47-bit input capture
channel (RTCIC0) stores all the bits from the RTC_CNT1, RTC_CNT0, and RTC_CNT2 registers, giving its snapshot a longer span of uniquely identifying a 32 kHz cycle.
If RTC_CR2IC.RTCICOWUSEN does not allows overwriting of unread snapshots due to new GPIO edges, the
snapshots of the RTC time are sticky (not overwritten) until read by the CPU. When a snapshot is taken, a sticky
interrupt source (RTC_SR3.RTCIC0IRQ/RTC_SR3.RTCIC2IRQ/RTC_SR3.RTCOC3IRQ/
RTC_SR3.RTCIC4IRQ) goes high to record the occurrence of a new input capture event since the CPU last
cleared the interrupt source bit. Optionally, the CPU can enable such sources to contribute to the interrupt lines
from the RTC to the wake-up controller and NVIC.
Any number of channels, ranging from 0 to 8, of the four input capture channels and four SensorStrobe channel can
operate simultaneously.
RTC Power Modes Behavior
The table shows the MMR retention in hibernate and shutdown mode.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–17
RTC Power Modes Behavior
Table 21-3: RTC Registers Summary
Register
RTC0 Retention Status
RTC1 Retention Status
Hibernate Mode
Shutdown Mode
Hibernate Mode
Shutdown Mode
RTC_CR0
Yes
Yes
Yes
No
RTC_SR0
Yes
Yes
Yes
No
RTC_SR1
Yes
Yes
Yes
No
RTC_CNT0
Yes
Yes
Yes
No
RTC_CNT1
Yes
Yes
Yes
No
RTC_ALM0
Yes
Yes
Yes
No
RTC_ALM1
Yes
Yes
Yes
No
RTC_TRM
Yes
Yes
Yes
No
RTC_GWY
No
No
No
No
RTC_CR1
Yes
Yes
Yes
No
RTC_SR2
Yes
Yes
Yes
No
RTC_SNAP0
Yes
Yes
Yes
No
RTC_SNAP1
Yes
Yes
Yes
No
RTC_SNAP2
Yes
Yes
Yes
No
RTC_MOD
Yes
Yes
Yes
No
RTC_CNT2
Yes
Yes
Yes
No
RTC_ALM2
Yes
Yes
Yes
No
RTC_SR3
NA
NA
Yes
No
RTC_CR2IC
NA
NA
Yes
No
RTC_CR3SS
NA
NA
Yes
No
RTC_CR4SS
NA
NA
Yes
No
RTC_SSMSK
NA
NA
Yes
No
RTC_IC2
NA
NA
Yes
No
RTC_IC3
NA
NA
Yes
No
RTC_IC4
NA
NA
Yes
No
RTC_SS1
NA
NA
Yes
No
RTC_SS2
NA
NA
Yes
No
RTC_SS3
NA
NA
Yes
No
RTC_SS4
NA
NA
Yes
No
RTC_SR4
NA
NA
Yes
No
21–18
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
Table 21-3: RTC Registers Summary (Continued)
Register
RTC0 Retention Status
RTC1 Retention Status
Hibernate Mode
Shutdown Mode
Hibernate Mode
Shutdown Mode
RTC_SR5
NA
NA
Yes
No
RTC_SR6
NA
NA
Yes
No
RTC_SS1TGT
NA
NA
Yes
No
RTC_FRZCNT
NA
NA
No
No
RTC_SS2TGT
NA
NA
Yes
No
RTC_SS3TGT
NA
NA
Yes
No
RTC_SS1LOWDUR
NA
NA
Yes
No
RTC_SS2LOWDUR
NA
NA
Yes
No
RTC_SS3LOWDUR
NA
NA
Yes
No
RTC_SS1HIGHDUR
NA
NA
Yes
No
RTC_SS2HIGHDUR
NA
NA
Yes
No
RTC_SS3HIGHDUR
NA
NA
Yes
No
RTC_SSMSKOT
NA
NA
Yes
No
RTC_CR5SSS
NA
NA
Yes
No
RTC_CR6SSS
NA
NA
Yes
No
RTC_CR7SSS
NA
NA
Yes
No
RTC_SR7
NA
NA
Yes
No
RTC_SR8
NA
NA
Yes
No
RTC_SR9
NA
NA
Yes
No
RTC_GPMUX0
NA
NA
Yes
No
RTC_GPMUX1
NA
NA
Yes
No
ADuCM4050 RTC Register Descriptions
Real-Time Clock (RTC) contains the following registers.
Table 21-4: ADuCM4050 RTC Register List
Name
Description
RTC_ALM0
RTC Alarm 0
RTC_ALM1
RTC Alarm 1
RTC_ALM2
RTC Alarm 2
RTC_CNT0
RTC Count 0
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–19
ADuCM4050 RTC Register Descriptions
Table 21-4: ADuCM4050 RTC Register List (Continued)
Name
Description
RTC_CNT1
RTC Count 1
RTC_CNT2
RTC Count 2
RTC_CR0
RTC Control 0
RTC_CR1
RTC Control 1
RTC_CR2IC
RTC Control 2 for Configuring Input Capture Channels
RTC_CR3SS
RTC Control 3 for Configuring SensorStrobe Channel
RTC_CR4SS
RTC Control 4 for Configuring SensorStrobe Channel
RTC_CR5SSS
RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling
RTC_CR6SSS
RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge
RTC_CR7SSS
RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity
RTC_FRZCNT
RTC Freeze Count
RTC_GPMUX0
RTC GPIO Pin Mux Control Register 0
RTC_GPMUX1
RTC GPIO Pin Mux Control Register 1
RTC_GWY
RTC Gateway
RTC_IC2
RTC Input Capture Channel 2
RTC_IC3
RTC Input Capture Channel 3
RTC_IC4
RTC Input Capture Channel 4
RTC_MOD
RTC Modulo
RTC_SS1
RTC SensorStrobe Channel 1
RTC_SS1HIGHDUR
RTC Auto-Reload High Duration for SensorStrobe Channel 1
RTC_SS1LOWDUR
RTC Auto-Reload Low Duration for SensorStrobe Channel 1
RTC_SS1TGT
RTC SensorStrobe Channel 1 Target
RTC_SS2
RTC SensorStrobe Channel 2
RTC_SS2HIGHDUR
RTC Auto-Reload High Duration for SensorStrobe Channel 2
RTC_SS2LOWDUR
RTC Auto-Reload Low Duration for SensorStrobe Channel 2
RTC_SS2TGT
RTC SensorStrobe Channel 2 Target
RTC_SS3
RTC SensorStrobe Channel 3
RTC_SS3HIGHDUR
RTC Auto-Reload High Duration for SensorStrobe Channel 3
RTC_SS3LOWDUR
RTC Auto-Reload Low Duration for SensorStrobe Channel 3
RTC_SS3TGT
RTC SensorStrobe Channel 3 Target
RTC_SS4
RTC SensorStrobe Channel 4
21–20
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
Table 21-4: ADuCM4050 RTC Register List (Continued)
Name
Description
RTC_SSMSK
RTC Mask for SensorStrobe Channel
RTC_SSMSKOT
RTC Masks for SensorStrobe Channels on Time Control
RTC_SNAP0
RTC Snapshot 0
RTC_SNAP1
RTC Snapshot 1
RTC_SNAP2
RTC Snapshot 2
RTC_SR0
RTC Status 0
RTC_SR1
RTC Status 1
RTC_SR2
RTC Status 2
RTC_SR3
RTC Status 3
RTC_SR4
RTC Status 4
RTC_SR5
RTC Status 5
RTC_SR6
RTC Status 6
RTC_SR7
RTC Status 7
RTC_SR8
RTC Status 8
RTC_SR9
RTC Status 9
RTC_TRM
RTC Trim
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–21
ADuCM4050 RTC Register Descriptions
RTC Alarm 0
RTC_ALM0 contains the lower 16 bits of the non-fractional (prescaled) RTC alarm target time value .
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE (R/W)
Lower 16 Prescaled (i.e. Non-Fractional)
Bits of the RTC Alarm Target Time
Figure 21-9: RTC_ALM0 Register Diagram
Table 21-5: RTC_ALM0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
21–22
Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
RTC Alarm 1
RTC_ALM1 contains the upper 16 bits of the non-fractional (prescaled) RTC alarm target time value.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE (R/W)
Upper 16 Prescaled (Non-Fractional)
Bits of the RTC Alarm Target Time
Figure 21-10: RTC_ALM1 Register Diagram
Table 21-6: RTC_ALM1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–23
ADuCM4050 RTC Register Descriptions
RTC Alarm 2
RTC_ALM2 specifies the fractional (non-prescaled) bits of the RTC alarm target time value, down to an individual
32 kHz clock cycle.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Fractional Bits of the Alarm Target Time
Figure 21-11: RTC_ALM2 Register Diagram
Table 21-7: RTC_ALM2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14:0 VALUE
(R/W)
21–24
Fractional Bits of the Alarm Target Time.
Fractional (non-prescaled) bits of the RTC alarm target time.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
RTC Count 0
RTC_CNT0 contains the lower 16 bits of the RTC counter which maintains a real-time count in elapsed prescaled
RTC time units.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Lower 16 Prescaled (Non-Fractional)
Bits of the RTC Real-Time Count
Figure 21-12: RTC_CNT0 Register Diagram
Table 21-8: RTC_CNT0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count.
(R/W)
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–25
ADuCM4050 RTC Register Descriptions
RTC Count 1
RTC_CNT1 contains the upper 16 bits of the RTC counter, which maintains a real-time count in elapsed prescaled
RTC time units.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Upper 16 Prescaled (Non-Fractional)
Bits of the RTC Real-Time Count
Figure 21-13: RTC_CNT1 Register Diagram
Table 21-9: RTC_CNT1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count.
(R/W)
21–26
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
RTC Count 2
RTC_CNT2 contains the fractional part of the RTC count. The overall resolution of the real-time count, including
the fractional bits in RTC_CNT2, is one 32 kHz clock period.
Note that the RTC_CNT2 register only exists in RTC1. In RTC0, the fractional part of the RTC count cannot be
read by the CPU.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Fractional Bits of the RTC Real-Time
Count
Figure 21-14: RTC_CNT2 Register Diagram
Table 21-10: RTC_CNT2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14:0 VALUE
(R/NW)
Fractional Bits of the RTC Real-Time Count.
RTC_CNT2 is zeroed when one of the following events occurs:
(i) The CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0 registers
to redefine the elapsed time units count while the RTC is enabled and the posted twin
write is executed.
(ii) The CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN
field.
(iii) When the RTC is enabled, the degree of prescaling in the RTC is changed via the
RTC_CR1.PRESCALE2EXP field.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–27
ADuCM4050 RTC Register Descriptions
RTC Control 0
RTC_CR0 is the primary of two control registers for the RTC, the other being RTC_CR1.
15 14 13 12 11 10 9
0
0
WPNDINTEN (R/W)
Enable Write Pending Sourced Interrupts
to the CPU
WSYNCINTEN (R/W)
Enable Write Synchronization Sourced
Interrupts to the CPU
0
0
0
0
1
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
1
0
0
CNTEN (R/W)
Global Enable for the RTC
ALMEN (R/W)
Enable the RTC Alarm (Absolute) Operation
ALMINTEN (R/W)
Enable ALMINT Sourced Alarm Interrupts
to the CPU
WPNDERRINTEN (R/W)
Enable Write Pending Error Sourced
Interrupts to the CPU When an RTC
Register-write Pending Error Occurs
TRMEN (R/W)
Enable RTC Digital Trimming
ISOINTEN (R/W)
Enable ISOINT Sourced Interrupts to
the CPU When Isolation of the RTC
Power Domain is Activated and Subsequently
De-activated
MOD60ALMEN (R/W)
Enable RTC Modulo-60 Counting of
Time Past a Modulo-60 Boundary
MOD60ALMINTEN (R/W)
Enable Periodic Modulo-60 RTC Alarm
Sourced Interrupts to the CPU
MOD60ALM (R/W)
Periodic, Modulo-60 Alarm Time in Prescaled
RTC Time Units Beyond a Modulo-60
Boundary
Figure 21-15: RTC_CR0 Register Diagram
Table 21-11: RTC_CR0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 WPNDINTEN
(R/W)
Enable Write Pending Sourced Interrupts to the CPU.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WPNDINT sticky interrupt source field.
0 Disable RTC_SR0.WPNDINT-sourced interrupts to
the CPU.
1 Enable RTC_SR0.WPNDINT-sourced interrupts to the
CPU.
21–28
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
Table 21-11: RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
14 WSYNCINTEN
(R/W)
Enable Write Synchronization Sourced Interrupts to the CPU.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WSYNCINT sticky interrupt source field.
0 Disable RTC_SR0.WSYNCINT-sourced interrupts to
the CPU.
1 Enable RTC_SR0.WSYNCINT-sourced interrupts to
the CPU.
13 WPNDERRINTEN
(R/W)
Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Registerwrite Pending Error Occurs.
This field is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WPNDINT sticky interrupt source field.
0 Don't enable interrupts if write pending errors occur in
the RTC.
1 Enable interrupts for write pending errors in the RTC.
12 ISOINTEN
(R/W)
Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power
Domain is Activated and Subsequently De-activated.
This field enables interrupts to the CPU based on the RTC_SR0.ISOINT sticky interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR0.ISOINT-sourced interrupts to the
CPU.
1 Enable RTC_SR0.ISOINT-sourced interrupts to the
CPU.
11 MOD60ALMINTEN
(R/W)
Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU.
This field enables interrupts to the CPU based on the RTC_SR0.MOD60ALMINT
sticky interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable periodic interrupts due to modulo-60 RTC
elapsed time.
1 Enable periodic interrupts due to modulo-60 RTC
elapsed time.
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
21–29
ADuCM4050 RTC Register Descriptions
Table 21-11: RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10:5 MOD60ALM
(R/W)
Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60
Boundary.
This field allows the CPU to position a periodic (repeating) alarm interrupt from the
RTC at any integer number of prescaled RTC time units from a modulo-60 boundary
(roll-over event) of the RTC integer count in RTC_CNT1 and RTC_CNT0.
Values of 0 to 59 are allowed. If a greater value is configured, it is treated as zero prescaled RTC time units.
Boundaries are defined whenever any of the following events occurs :
(i) the CPU writes a new pair of values to the RTC_CNT1and RTC_CNT0 registers.
(ii) the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN
field.
(iii) when the RTC is enabled by RTC_CR0.CNTEN, the degree of prescaling in the
RTC is changed via the RTC_CR1.PRESCALE2EXP field.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as all
zeros.
4 MOD60ALMEN
(R/W)
Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary.
RTC_CR0.MOD60ALMEN enables the RTC to detect and record until cleared by the
CPU the periodic interrupt condition of RTC_CNT1 and RTC_CNT0 having reached
RTC_CR0.MOD60ALM number of prescaled RTC time units past a modulo-60
boundary.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable determination of modul0-60 RTC elapsed time.
1 Enable determination of modulo-60 RTC elapsed time.
3 TRMEN
(R/W)
Enable RTC Digital Trimming.
Trimming of the RTC allows the real-time count in prescaled RTC time units to be
adjusted on a periodic basis to track time with better accuracy. RTC_CR0.TRMEN
enables this adjustment, provided the RTC is enabled via RTC_CR0.CNTEN.
Note that if RTC_CR0.TRMEN is activated from a disabled state while
RTC_CR0.CNTEN is also active, this will cause a trim interval boundary to occur and
a new trim interval will begin. No trim adjustment of the RTC count occurs on such
RTC_CR0.TRMEN activation. A whole, enabled trim interval must have elapsed before any adjustment is made.
0 Digital trimming of the RTC count value is disabled.
1 Trim is enabled.
21–30
ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference
ADuCM4050 RTC Register Descriptions
Table 21-11: RTC_