Micro SD / MicroSDHC - Super Talent Technology

Secure Digital Card
Secure Digital Card
Data Sheet
Rev. 1.1
1
MAR 2012
Secure Digital Card
Table of Contents
1 Introduction to the SD Card ...................................................................................................... 4
2 SD Card Feature ......................................................................................................................... 4
3 Product Specification ................................................................................................................ 5
4 SD Card Interface Description .................................................................................................. 10
5 Physical Outline ......................................................................................................................... 12
Rev. 1.1
2
MAR 2012
Secure Digital Card
Revision History
Date
Revision
FEB 2009
1.0
New Creation
MAR 2011
1.1
Modify SD Card Feature
Rev. 1.1
History
3
MAR 2012
Secure Digital Card
1. Introduction to the SD Card
The SD Card is a memory card that is small and thin with SDMI. SD Card is a Flash–Based memory card that is
designed to meet the security, capacity, performance and environment requirements inherent to used in emerging
audio and video electronic device.
The SD Card includes a copyright protection mechanism that complies with the security of the SDMI standard (SDMI:
Secure Digital Music Initiative). The SD Card communication is based on an advance 9-pin interface (clock, command,
4x Data and 3x power lines) and the SD Card host interface supports regular Multi Media Card operation as well.
2. SD Card Feature
※ Flash memory card capacity support list below:
Standard Capacity SD Memory Card:
◆ 128MB
◆ 256MB
◆ 512MB
◆ 1GB
◆ 2GB
High Capacity SD Memory Card:
◆ 4GB
◆ 8GB
◆ 16GB
◆ 32GB
※ Compliant SDA Specification Ver 2.0
※ Variable clock rate:
◆
Default mode: 0-25 MHz, up to 12.5MB/sec interface speed.
◆
High-speed mode:0-50 MHz, up to 25MB/sec interface speed.
※ High Capacity SD Memory Cards shall support Speed Class Specification and have performance more
Than or equal to Class 2, it includes:
◆ Class 2
◆ Class 4
◆ Class 6
※ Support CPRM
※ No external programming voltage required
※ SD Card protocol compatible
※ Targeted for portable and stationary applications for secured (copyrights protected) and non-secured data storage
※ Correction of memory field errors
※ Copyrights Protection Mechanism: Complies with highest security of SDMI standard.
※ Password Protection of cards (CMD42-LOCK_UNLOCK).
※ Card detection command (Insertion / Removal)
※ CE and FCC certificates
※ Easy handling for the end user
Notes: The performance depends on different test platform with different result.
‧The communication channel is described in the table
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Secure Digital Card
SD Bus/SPI Bus comparison
SD Card Using SD Bus
SD Card Using SPI Bus
Six-wire communication channel (clock, command, 4 data
Three-wire serial data bus (Clock, dataIn, data Out )+card
lines)
specific CS signal(hardwired card selection)
Error-protected data transfer
Optional non protected data transfer mode available
Single or multiple block oriented data transfer
Single or multiple block oriented data transfer
3.Product Specification
3.1 System Environment Specifications
Temperature
Operating: Non-Operating:
-25℃ to 85℃ -40℃ (168h) to 85℃(500h)
Operating: Non-Operating:
25°C / 95% rel. humidity 40°C / 93% rel.
hum./500h salt water spray: 3%
NaCl/35C; 24h acc. MIL STD Method
1009
15 G peak to peak max. 15 G peak to
peak max.
Moisture and corrosion
Vibration
Operating: Non-Operating:
Shock
Operating: Non-Operating:
1,000 G max. 1,000 G max.
Altitude (relative to sea level)
Operating: Non-Operating:
80,000 feet max. 80,000 feet max.
3.2 Reliability and Duraility Specifications
Durability
10,000 mating cycles
Bending
10N
Torque
0.10N.m or ±2.5 deg.
Drop Test
1.5m free fall
UV: 254nm, 15Ws/cm2 according to IOS 7816-1
UV Light Exposure
Visual Inspection/Shape and Form
No warp age; no mold slim; complete form; no cavities; surface smoothness≦-0.1
mm/ cm2 within contour; no cracks; no pollution (oil, dust, etc.)
3.3 Typical Card Pow Requirement
VDD (fipple:max,60mV peak to peak
2.7V~3.6V
3.4 System performance
Block Read Access Time
CMD1 to Ready (after power up)
Sleep to Read
typical
Maximum
1.5 m sec
50 m sec
1 m sec
15 m sec
500 m sec
2 m sec
3.5 System Reliability and Maintenance
MTBF
Preventive Maintenance
Data Reliability
>1,000,000 hours
None
< 1 non-recoverable error in 1014 bits read
100,000 write/erase cycles (SLC NAND flash)
10,000 write/erase cycles (MLC NAND flash)
Endurance
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MAR 2012
Secure Digital Card
3.6 SD Bus Topology
The SD bus has six communication lines and two supply lines:
‧ CMD: Command is bi-directional signal. (Host and card drivers are operating in push pull mode.)
‧ DAT0-3: Data lines are bi-directional signals. (Host and card drivers are operating in push pull mode.)
‧ CLK: Clock is a host to cards signal. (CLK operates in push pull mode.)
‧ VDD: VDD is the power supply line for all cards.
‧ VSS: VSS are two ground lines.
The following figure shows the bus topology of several cards with one host in SD Bus mode.
SD Card System Bus Topology
During the initialization process, commands are sent to each card individually, allowing the application to detect the
cards and assign logical addresses to the physical slots. Data is always sent to each card individually. However, to
simplify the handling of the card stack, after initialization, all commands may be sent concurrently to all cards.
Addressing information is provided in the command packet.
The SD Bus allows dynamic configuration of the number of data lines. After power-up, by default, the SD Card will
use only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines). This
feature allows and easy trade off between hardware cost and system performance.
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Secure Digital Card
Bus Circuitry Diagram
3.7 SPI Bus Topology
The SD Card SPI interface is compatible with SPI hosts available on the market. As any other SPI device the SD
Card SPI channel consists of the following 4 signals:
1) CS: Host to card Chip Select signal.
2) SCLK: Host to card clock signal.
3) Data In: Host to card data signal.
4) Data Out: Card to host data signal.
Another SPI common characteristic, which is implemented in the SD Card as well, is byte transfers. All data tokens are multiples of
8 bit bytes and always byte aligned to the CS signal.
The SPI standard defines the physical link only and not the complete data transfer protocol. In SPI Bus mode, the SD Card uses a
subset of the SD Card protocol and command set.
The SD Card identification and addressing algorithms are replaced by a hardware Chip Select (CS) signal. A card (slave) is
selected, for every command, by asserting (active low) the CS signal.
The CS signal must be continuously active for the duration of the SPI transaction (command, response and data).
The only exception is card programming time. At this time the host can de-assert the CS signal without affecting the
programming process.
The bi-directional CMD and DAT lines are replaced by uni-directional data In and data Out signals. This eliminates
the
ability of executing commands while data is being read or written. An exception is the multi read/write operations.
The Stop Transmission command can be sent during data read. In the multi block write operation a Stop Transmission
sent as the first byte of the data block.
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token is
Secure Digital Card
3.8 Electrical Interface
The power up of the SD Card bus is handled locally in each SD Card and in the bus master.
SPI Mode bus operating conditions are identical to SD Card mode bus operating conditions. The CS (chip select) signal
timing is identical to the input signal timing.
Power Supply Voltage
General
Parameter
Symbol
Peak voltage on all lines
Min.
Max.
Unit
-0.3
VDD+ 0.3
V
-10
10
uA
-10
10
uA
Min.
Max.
Unit
2.0
3.6
V
Remark
All Inputs
Input Leakage Current
SD Card Bus System
All Outputs
Output Leakage Current
Power supply Voltage
Parameter
Symbol
Supply Voltage for voltage range
VDD
CMD0, 15, 55, ACMD41
Commands
Except CMD0, 15, 55,
Supply voltage specified in OCR register
ACMD41 Commands
Supply voltage differentials
-0.3
Power up time
Rev. 1.1
Remark
8
0.3
V
250
ms
from 0V to VDD Min.
MAR 2012
Secure Digital Card
3.9 Bus Timing
Timing Diagram Data In put. Output Referenced to Clock
Bus Timing
Parameter
Symbol
Min.
Max.
Unit
Remark
Clock CLK (All values are referred to min.(VIH) and max.(VIL))
Clock Frequency Data Transfer Mode
fPP
0
25
MHz
CL≦100pF (7 Cards)
Clock Frequency (Identification Mode)
fOD
0/100
400
KHz
CL≦250pF (21 Cards)
Clock Low Time
tWL
10
ns
CL≦100pF (7 Cards)
Clock High Time
tWH
10
ns
CL≦100pF (7 Cards)
Clock Rise Time
tTLH
10
ns
CL≦100pF (7 Cards)
Clock Fall Time
tTHL
10
ns
CL≦100pF (7 Cards)
Clock Low Time
tWL
50
ns
CL≦250pF (21 Cards)
Clock High Time
tWH
50
ns
CL≦250pF (21 Cards)
Clock Rise Time
tTLH
50
ns
CL≦250pF (21 Cards)
Clock Fall Time
tTHL
50
ns
CL≦250pF (21 Cards)
Inputs CMD,DAT(referenced to CLK)
Input set-up time
tISU
5
ns
CL≦25pF (1 Cards)
tIH
5
ns
CL≦25pF (1 Cards)
Output Delay time during data transfer mode
tDLY
0
14
ns
CL≦25pF (1 Cards)
Output Delay time during identification mode
tDLY
0
50
ns
CL≦25pF (1 Cards)
Input hold time
Outputs CMD,DAT(referenced to CLK)
3.10 Operating Conditions Register (OCR)
The 32-bit operation conditions register stores the VDD voltage profile of the card. The SD Card is capable of executing
the voltage recognition procedure (CMD1) with any standard SD Card host using operating voltages form 2 to 3.6 Volts.
Accessing the data in the memory array, however, requires 2.7 to 3.6 Volts. The OCR shows the voltage range in which
the card data can be accessed. The structure of the OCR register is described in under table.
Rev. 1.1
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MAR 2012
Secure Digital Card
Rev. 1.1
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Rev. 1.1
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Secure Digital Card
5. Physical Outline
Rev. 1.1
12
MAR 2012
Secure Digital Card
Rev. 1.1
13
MAR 2012