Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures
Optimization Reference Manual
Order Number: 248966-039
December 2017
Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer.
No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages
resulting from such losses.
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel
products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which
includes subject matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
This document contains information on products, services and/or processes in development. All information provided here is subject
to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps.
Results have been estimated or simulated using internal Intel analysis or architecture simulation or modeling, and provided to you for
informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained
by calling 1-800-548-4725, or by visiting http://www.intel.com/design/literature.htm.
Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation
in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 1997-2017, Intel Corporation. All Rights Reserved.
CONTENTS
PAGE
CHAPTER 1
INTRODUCTION
1.1
1.2
1.3
TUNING YOUR APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ABOUT THIS MANUAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
RELATED INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
CHAPTER 2
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.1
2.1.1
2.1.1.1
2.1.1.2
2.1.1.3
2.1.2
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.4.1
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.2.4
2.4.3
2.4.3.1
2.4.3.2
2.4.4
2.4.5
2.4.5.1
2.4.5.2
2.4.5.3
2.4.5.4
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.5.2.4
2.5.2.5
2.5.2.6
2.5.3
2.5.3.1
THE SKYLAKE SERVER MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Skylake Server Microarchitecture Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Larger Mid-Level Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Non-Inclusive Last Level Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Skylake Server Microarchitecture Cache Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
Non-Temporal Stores on Skylake Server Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
THE SKYLAKE MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
The Out-of-Order Execution Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
Cache and Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Pause Latency in Skylake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
HASWELL MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
The Out-of-Order Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Execution Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Cache and Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Load and Store Operation Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
The Haswell-E Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
The Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Intel® Microarchitecture Code Name Sandy Bridge Pipeline Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Legacy Decode Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Decoded ICache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Micro-op Queue and the Loop Stream Detector (LSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
The Out-of-Order Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Renamer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
The Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Cache Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Load and Store Operation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
L1 DCache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Ring Interconnect and Last Level Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Data Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
System Agent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Intel® Microarchitecture Code Name Ivy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
INTEL® CORE™ MICROARCHITECTURE AND ENHANCED INTEL® CORE™ MICROARCHITECTURE . . . . . . . . . . . . . . . . 2-38
Intel® Core™ Microarchitecture Pipeline Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Branch Prediction Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Instruction Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Instruction Queue (IQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Instruction Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Stack Pointer Tracker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Micro-fusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
Issue Ports and Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
iii
CONTENTS
PAGE
2.5.4
2.5.4.1
2.5.4.2
2.5.4.3
2.5.4.4
2.5.4.5
2.5.5
2.5.5.1
2.5.5.2
2.6
2.6.1
2.6.2
2.6.3
2.6.3.1
2.6.4
2.6.5
2.6.5.1
2.6.5.2
2.6.6
2.6.7
2.6.8
2.6.9
2.7
2.7.1
2.7.1.1
2.7.1.2
2.7.1.3
2.7.2
2.7.3
2.7.4
2.7.5
2.8
2.9
2.10
2.10.1
2.10.2
2.10.3
2.10.4
2.10.5
2.10.6
2.10.7
2.10.8
2.10.9
2.10.10
2.10.11
2.10.12
2.10.13
2.10.14
2.10.15
2.10.16
2.10.17
Intel® Advanced Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Prefetch to L1 caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Prefetch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Disambiguation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Advanced Smart Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® MICROARCHITECTURE CODE NAME NEHALEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front End Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Issue Ports and Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache and Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Load and Store Operation Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Efficient Handling of Alignment Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Store Forwarding Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REP String Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhancements for System Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Efficiency Enhancements for Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hyper-Threading Technology Support in Intel® Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . .
INTEL® HYPER-THREADING TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Resources and HT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replicated Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partitioned Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shared Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture Pipeline and HT Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front End Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® 64 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIMD TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SUMMARY OF SIMD TECHNOLOGIES AND APPLICATION LEVEL EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MMX™ Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Streaming SIMD Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Streaming SIMD Extensions 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Streaming SIMD Extensions 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supplemental Streaming SIMD Extensions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSE4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AESNI and PCLMULQDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Advanced Vector Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half-Precision Floating-Point Conversion (F16C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDRAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fused-Multiply-ADD (FMA) Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Bit-Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Transactional Synchronization Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDSEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADCX and ADOX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 3
GENERAL OPTIMIZATION GUIDELINES
3.1
3.1.1
3.1.2
3.1.3
3.2
3.2.1
3.2.2
3.2.3
3.3
3.4
iv
2-45
2-46
2-47
2-47
2-48
2-49
2-49
2-51
2-51
2-52
2-52
2-54
2-55
2-56
2-57
2-58
2-58
2-58
2-60
2-61
2-61
2-61
2-61
2-63
2-63
2-63
2-64
2-64
2-64
2-64
2-65
2-65
2-65
2-67
2-68
2-68
2-68
2-68
2-68
2-69
2-69
2-69
2-70
2-70
2-70
2-70
2-71
2-71
2-71
2-71
2-71
PERFORMANCE TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Intel® C++ and Fortran Compilers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
General Compiler Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
VTune™ Performance Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
PROCESSOR PERSPECTIVES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
CPUID Dispatch Strategy and Compatible Code Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Transparent Cache-Parameter Strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
Threading Strategy and Hardware Multithreading Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
CODING RULES, SUGGESTIONS AND TUNING HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
OPTIMIZING THE FRONT END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
CONTENTS
PAGE
3.4.1
Branch Prediction Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4
3.4.1.1
Eliminating Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.4.1.2
Spin-Wait and Idle Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
3.4.1.3
Static Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6
3.4.1.4
Inlining, Calls and Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.1.5
Code Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.4.1.6
Branch Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.4.1.7
Loop Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.1.8
Compiler Support for Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.4.2
Fetch and Decode Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2.1
Optimizing for Micro-fusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2.2
Optimizing for Macro-fusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2.3
Length-Changing Prefixes (LCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.2.4
Optimizing the Loop Stream Detector (LSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.4.2.5
Exploit LSD Micro-op Emission Bandwidth in Intel® Microarchitecture Code Name Sandy Bridge. . . . . . . . 3-18
3.4.2.6
Optimization for Decoded ICache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.2.7
Other Decoding Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.5
OPTIMIZING THE EXECUTION CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.5.1
Instruction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.5.1.1
Integer Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.5.1.2
Using LEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.5.1.3
ADC and SBB in Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.5.1.4
Bitwise Rotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.5.1.5
Variable Bit Count Rotation and Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.5.1.6
Address Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.5.1.7
Clearing Registers and Dependency Breaking Idioms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.5.1.8
Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.5.1.9
Using NOPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.5.1.10
Mixing SIMD Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.5.1.11
Spill Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.5.1.12
Zero-Latency MOV Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.5.2
Avoiding Stalls in Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.5.2.1
ROB Read Port Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.5.2.2
Writeback Bus Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.2.3
Bypass between Execution Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.2.4
Partial Register Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.5.2.5
Partial XMM Register Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.5.2.6
Partial Flag Register Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
3.5.2.7
Floating-Point/SIMD Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.5.3
Vectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
3.5.4
Optimization of Partially Vectorizable Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
3.5.4.1
Alternate Packing Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
3.5.4.2
Simplifying Result Passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
3.5.4.3
Stack Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.5.4.4
Tuning Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.6
OPTIMIZING MEMORY ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.6.1
Load and Store Execution Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42
3.6.1.1
Make Use of Load Bandwidth in Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . 3-42
3.6.1.2
L1D Cache Latency in Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
3.6.1.3
Handling L1D Cache Bank Conflict . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
3.6.2
Minimize Register Spills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
3.6.3
Enhance Speculative Execution and Memory Disambiguation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
3.6.4
Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.6.5
Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
3.6.5.1
Store-to-Load-Forwarding Restriction on Size and Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
3.6.5.2
Store-forwarding Restriction on Data Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.6.6
Data Layout Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.6.7
Stack Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
3.6.8
Capacity Limits and Aliasing in Caches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
3.6.8.1
Capacity Limits in Set-Associative Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
3.6.8.2
Aliasing Cases in the Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo and Intel® Core™ 2 Duo Processors3-58
3.6.9
Mixing Code and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
3.6.9.1
Self-modifying Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
3.6.9.2
Position Independent Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
3.6.10
Write Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
v
CONTENTS
PAGE
3.6.11
3.6.12
3.6.13
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.6.1
3.7.6.2
3.7.6.3
3.8
3.8.1
3.8.2
3.8.2.1
3.8.2.2
3.8.3
3.8.3.1
3.8.3.2
3.8.3.3
3.8.4
3.8.4.1
3.8.4.2
3.8.5
3.8.5.1
3.8.5.2
3.9
3.9.1
Locality Enhancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimizing Bus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Temporal Store Bus Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PREFETCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Instruction Fetching and Software Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Prefetching for First-Level Data Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Prefetching for Second-Level Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cacheability Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REP Prefix and Data Movement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enhanced REP MOVSB and STOSB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memcpy Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memmove Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memset Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FLOATING-POINT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guidelines for Optimizing Floating-point Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microarchitecture Specific Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Long-Latency FP Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-point Modes and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dealing with floating-point exceptions in x87 FPU code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-point Exceptions in SSE/SSE2/SSE3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-point Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rounding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x87 vs. Scalar SIMD Floating-point Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Scalar SSE/SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transcendental Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAXIMIZING PCIE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimizing PCIe Performance for Accesses Toward Coherent Memory and Toward MMIO Regions (P2P) . .
CHAPTER 4
CODING FOR SIMD ARCHITECTURES
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.3
4.4.4
4.4.4.1
vi
3-61
3-62
3-62
3-63
3-63
3-64
3-66
3-66
3-66
3-69
3-69
3-70
3-71
3-71
3-71
3-72
3-72
3-72
3-72
3-72
3-73
3-73
3-73
3-74
3-76
3-76
3-76
3-77
3-77
3-78
CHECKING FOR PROCESSOR SUPPORT OF SIMD TECHNOLOGIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Checking for MMX Technology Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Checking for Streaming SIMD Extensions Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Checking for Streaming SIMD Extensions 2 Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Checking for Streaming SIMD Extensions 3 Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Checking for Supplemental Streaming SIMD Extensions 3 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Checking for SSE4.1 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Checking for SSE4.2 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
DetectiON of PCLMULQDQ and AESNI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Detection of AVX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Detection of VEX-Encoded AES and VPCLMULQDQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Detection of F16C Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Detection of FMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
Detection of AVX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
CONSIDERATIONS FOR CODE CONVERSION TO SIMD PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Identifying Hot Spots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Determine If Code Benefits by Conversion to SIMD Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
CODING TECHNIQUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Coding Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Automatic Vectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
STACK AND DATA ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Alignment and Contiguity of Data Access Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Using Padding to Align Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Using Arrays to Make Data Contiguous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Stack Alignment For 128-bit SIMD Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Data Alignment for MMX Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Data Alignment for 128-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Compiler-Supported Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
CONTENTS
PAGE
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.7
IMPROVING MEMORY UTILIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Structure Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strip-Mining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INSTRUCTION SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIMD Optimizations and Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TUNING THE FINAL APPLICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-20
4-20
4-23
4-24
4-26
4-27
4-28
CHAPTER 5
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.1
5.2
5.2.1
5.2.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
5.4.13
5.4.14
5.4.15
5.4.16
5.5
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.6.1
5.6.6.2
5.6.7
5.6.8
5.6.9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.7
5.7.1
5.7.1.1
5.7.2
5.7.2.1
5.7.2.2
5.7.2.3
5.7.3
5.8
5.8.1
5.8.1.1
GENERAL RULES ON SIMD INTEGER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
USING SIMD INTEGER WITH X87 FLOATING-POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Using the EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
Guidelines for Using EMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
DATA ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
DATA MOVEMENT CODING TECHNIQUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Unsigned Unpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
Signed Unpack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5
Interleaved Pack with Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
Interleaved Pack without Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7
Non-Interleaved Unpack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
Extract Data Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-9
Insert Data Element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Non-Unit Stride Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Move Byte Mask to Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Packed Shuffle Word for 64-bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Packed Shuffle Word for 128-bit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Shuffle Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Conditional Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Unpacking/interleaving 64-bit Data in 128-bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
GENERATING CONSTANTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
BUILDING BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Absolute Difference of Unsigned Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Absolute Difference of Signed Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Pixel Format Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Endian Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Clipping to an Arbitrary Range [High, Low] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Highly Efficient Clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Clipping to an Arbitrary Unsigned Range [High, Low] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Packed Max/Min of Byte, Word and Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Packed Multiply Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Packed Sum of Absolute Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
MPSADBW and PHMINPOSUW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Packed Average (Byte/Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Complex Multiply by a Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Packed 64-bit Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
128-bit Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
PTEST and Conditional Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Vectorization of Heterogeneous Computations across Loop Iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Vectorization of Control Flows in Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
MEMORY OPTIMIZATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Partial Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Supplemental Techniques for Avoiding Cache Line Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Increasing Bandwidth of Memory Fills and Video Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Increasing Memory Bandwidth Using the MOVDQ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Increasing Memory Bandwidth by Loading and Storing to and from the Same DRAM Page . . . . . . . . . . . . 5-30
Increasing UC and WC Store Bandwidth by Using Aligned Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Reverse Memory Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
CONVERTING FROM 64-BIT TO 128-BIT SIMD INTEGERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
SIMD Optimizations and Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Packed SSE2 Integer versus MMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
vii
CONTENTS
PAGE
5.8.1.2
Work-around for False Dependency Issue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
TUNING PARTIALLY VECTORIZABLE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
PARALLEL MODE AES ENCRYPTION AND DECRYPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10.1
AES Counter Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10.2
AES Key Expansion Alternative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10.3
Enhancement in Intel Microarchitecture Code Name Haswell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10.3.1
AES and Multi-Buffer Cryptographic Throughput. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10.3.2
PCLMULQDQ Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11
LIGHT-WEIGHT DECOMPRESSION AND DATABASE PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.1
Reduced Dynamic Range Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11.2
Compression and Decompression Using SIMD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-35
5-35
5-38
5-38
5-46
5-48
5-48
5-48
5-48
5-49
5-49
CHAPTER 6
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.1.1
6.5.1.2
6.5.1.3
6.5.1.4
6.5.2
6.5.3
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.2
6.6.3
6.6.4
6.6.4.1
GENERAL RULES FOR SIMD FLOATING-POINT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
PLANNING CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
USING SIMD FLOATING-POINT WITH X87 FLOATING-POINT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
SCALAR FLOATING-POINT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
DATA ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Data Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Vertical versus Horizontal Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Data Swizzling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-5
Data Deswizzling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
Horizontal ADD Using SSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
Use of CVTTPS2PI/CVTTSS2SI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Flush-to-Zero and Denormals-are-Zero Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
SIMD OPTIMIZATIONS AND MICROARCHITECTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
SIMD Floating-point Programming Using SSE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
SSE3 and Complex Arithmetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Packed Floating-Point Performance in Intel Core Duo Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Dot Product and Horizontal SIMD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Vector Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Using Horizontal SIMD Instruction Sets and Data Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
SOA and Vector Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
CHAPTER 7
OPTIMIZING CACHE USAGE
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.1.4
7.4.2
7.4.2.1
7.4.2.2
7.4.3
7.4.4
7.4.5
7.4.5.1
7.4.5.2
7.4.5.3
7.4.6
7.4.7
7.5
7.5.1
viii
GENERAL PREFETCH CODING GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
PREFETCH AND CACHEABILITY INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
PREFETCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
Software Data Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Prefetch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3
Prefetch and Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
CACHEABILITY CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
The Non-temporal Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
Fencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Streaming Non-temporal Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Memory Type and Non-temporal Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Write-Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6
Streaming Store Usage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
Coherent Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
Non-coherent requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
Streaming Store Instruction Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
The Streaming Load Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
FENCE Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
SFENCE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
LFENCE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
MFENCE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
CLFLUSH Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
CLFLUSHOPT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
MEMORY OPTIMIZATION USING PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Software-Controlled Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
CONTENTS
PAGE
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.6
7.6.1
7.6.2
7.6.2.1
7.6.2.2
7.6.2.3
7.6.2.4
7.6.2.5
7.6.2.6
7.6.2.7
7.6.2.8
7.6.3
7.6.3.1
7.6.3.2
7.6.3.3
Hardware Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of Effective Latency Reduction with Hardware Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example of Latency Hiding with S/W Prefetch Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Prefetching Usage Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Prefetch Scheduling Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Prefetch Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Minimize Number of Software Prefetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mix Software Prefetch with Computation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Prefetch and Cache Blocking Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Prefetching and Cache Blocking Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pass versus Multi-pass Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY OPTIMIZATION USING NON-TEMPORAL STORES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-temporal Stores and Software Write-Combining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conclusions from Video Encoder and Decoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimizing Memory Copy Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLB Priming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the 8-byte Streaming Stores and Software Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using 16-byte Streaming Stores and Hardware Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Comparisons of Memory Copy Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Deterministic Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Sharing Using Deterministic Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache Sharing in Single-Core or Multicore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Determine Prefetch Stride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-12
7-13
7-14
7-15
7-16
7-16
7-17
7-19
7-19
7-23
7-24
7-25
7-25
7-26
7-26
7-26
7-27
7-27
7-28
7-29
7-29
7-30
7-31
7-32
7-32
7-32
CHAPTER 8
INTRODUCING SUB-NUMA CLUSTERING
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
SUB-NUMA CLUSTERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
COMPARISON WITH CLUSTER-ON-DIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
SNC USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
How to Check NUMA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
MPI Optimizations for SNC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
SNC Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-8
CHAPTER 9
MULTICORE AND HYPER-THREADING TECHNOLOGY
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.1.1
9.2.2
9.2.3
9.2.3.1
9.2.4
9.2.4.1
9.2.4.2
9.2.4.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.4
9.4.1
9.4.2
9.4.3
9.4.4
PERFORMANCE AND USAGE MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
Multitasking Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
PROGRAMMING MODELS AND MULTITHREADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Parallel Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
Domain Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
Functional Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
Specialized Programming Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
Producer-Consumer Threading Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
Tools for Creating Multithreaded Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
Programming with OpenMP Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Automatic Parallelization of Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Supporting Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
OPTIMIZATION GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
Key Practices of Thread Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Key Practices of System Bus Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
Key Practices of Memory Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
Key Practices of Execution Resource Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
Generality and Performance Impact. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
THREAD SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Choice of Synchronization Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Synchronization for Short Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
Optimization with Spin-Locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Synchronization for Longer Periods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ix
CONTENTS
PAGE
9.4.4.1
9.4.5
9.4.6
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.6
9.6.1
9.6.2
9.6.2.1
9.6.2.2
9.6.3
9.7
9.7.1
9.8
9.8.1
9.8.2
9.9
9.9.1
Avoid Coding Pitfalls in Thread Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Prevent Sharing of Modified Data and False-Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Placement of Shared Synchronization Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
SYSTEM BUS OPTIMIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Conserve Bus Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Understand the Bus and Cache Interactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Avoid Excessive Software Prefetches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17
Improve Effective Latency of Cache Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
Use Full Write Transactions to Achieve Higher Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18
MEMORY OPTIMIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Cache Blocking Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Shared-Memory Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Minimize Sharing of Data between Physical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19
Batched Producer-Consumer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Eliminate 64-KByte Aliased Data Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
FRONT END OPTIMIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Avoid Excessive Loop Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
AFFINITIES AND MANAGING SHARED PLATFORM RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-22
Topology Enumeration of Shared Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
Non-Uniform Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23
OPTIMIZATION OF OTHER SHARED RESOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
Expanded Opportunity for HT Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25
CHAPTER 10
64-BIT MODE CODING GUIDELINES
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.3
10.3.1
10.3.2
10.3.3
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CODING RULES AFFECTING 64-BIT MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Legacy 32-Bit Instructions When Data Size Is 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Extra Registers to Reduce Register Pressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effective Use of 64-Bit by 64-Bit Multiplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Replace 128-bit Integer Division with 128-bit Multiplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sign Extension to Full 64-Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ALTERNATE CODING RULES FOR 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use 64-Bit Registers Instead of Two 32-Bit Registers for 64-Bit Arithmetic Result. . . . . . . . . . . . . . . . . . . . . .
CVTSI2SS and CVTSI2SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using Software Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-1
10-1
10-1
10-1
10-2
10-2
10-4
10-5
10-5
10-6
10-6
CHAPTER 11 SSE4.2 AND SIMD PROGRAMMING FOR TEXTPROCESSING/LEXING/PARSING
11.1
11.1.1
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.4
11.5
11.5.1
11.5.1.1
SSE4.2 STRING AND TEXT INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
CRC32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
USING SSE4.2 STRING AND TEXT INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Unaligned Memory Access and Buffer Size Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Unaligned Memory Access and String Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
SSE4.2 APPLICATION CODING GUIDELINE AND EXAMPLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Null Character Identification (Strlen equivalent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
White-Space-Like Character Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Substring Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
String Token Extraction and Case Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Unicode Processing and PCMPxSTRy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Replacement String Library Function Using SSE4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26
SSE4.2 ENABLED NUMERICAL AND LEXICAL COMPUTATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28
NUMERICAL DATA CONVERSION TO ASCII FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
Large Integer Numeric Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
MULX Instruction and Large Integer Numeric Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
CHAPTER 12
OPTIMIZATIONS FOR INTEL® AVX, FMA AND AVX2
12.1
12.1.1
12.2
x
INTEL® AVX INTRINSICS CODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Intel® AVX Assembly Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
NON-DESTRUCTIVE SOURCE (NDS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5
CONTENTS
PAGE
12.3
MIXING AVX CODE WITH SSE CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
12.3.1
Mixing Intel® AVX and Intel SSE in Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.4
128-BIT LANE OPERATION AND AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.4.1
Programming With the Lane Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.4.2
Strided Load Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11
12.4.3
The Register Overlap Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.5
DATA GATHER AND SCATTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.5.1
Data Gather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
12.5.2
Data Scatter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.6
DATA ALIGNMENT FOR INTEL® AVX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.6.1
Align Data to 32 Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
12.6.2
Consider 16-Byte Memory Access when Memory is Unaligned. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.6.3
Prefer Aligned Stores Over Aligned Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.7
L1D CACHE LINE REPLACEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.8
4K ALIASING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22
12.9
CONDITIONAL SIMD PACKED LOADS AND STORES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23
12.9.1
Conditional Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.10 MIXING INTEGER AND FLOATING-POINT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12.11 HANDLING PORT 5 PRESSURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.11.1
Replace Shuffles with Blends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
12.11.2
Design Algorithm With Fewer Shuffles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30
12.11.3
Perform Basic Shuffles on Load Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
12.12 DIVIDE AND SQUARE ROOT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34
12.12.1
Single-Precision Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
12.12.2
Single-Precision Reciprocal Square Root. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
12.12.3
Single-Precision Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
12.13 OPTIMIZATION OF ARRAY SUB SUM EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
12.14 HALF-PRECISION FLOATING-POINT CONVERSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
12.14.1
Packed Single-Precision to Half-Precision Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
12.14.2
Packed Half-Precision to Single-Precision Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
12.14.3
Locality Consideration for using Half-Precision FP to Conserve Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45
12.15 FUSED MULTIPLY-ADD (FMA) INSTRUCTIONS GUIDELINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46
12.15.1
Optimizing Throughput with FMA and Floating-Point Add/MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47
12.15.2
Optimizing Throughput with Vector Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48
12.16 AVX2 OPTIMIZATION GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49
12.16.1
Multi-Buffering and AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12.16.2
Modular Multiplication and AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12.16.3
Data Movement Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54
12.16.3.1
SIMD Heuristics to implement Memcpy(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55
12.16.3.2
Memcpy() Implementation Using Enhanced REP MOVSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55
12.16.3.3
Memset() Implementation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56
12.16.3.4
Hoisting Memcpy/Memset Ahead of Consuming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
12.16.3.5
256-bit Fetch versus Two 128-bit Fetches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
12.16.3.6
Mixing MULX and AVX2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
12.16.4
Considerations for Gather Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64
12.16.4.1
Strided Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-67
12.16.4.2
Adjacent Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-68
12.16.5
AVX2 Conversion Remedy to MMX Instruction Throughput Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69
CHAPTER 13
INTEL® TSX RECOMMENDATIONS
13.1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1.1
Optimization Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2
APPLICATION-LEVEL TUNING AND OPTIMIZATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.1
Existing TSX-enabled Locking Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.1.1
Libraries allowing lock elision for unmodified programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.1.2
Libraries requiring program modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.2
Initial Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.3
Run and Profile the Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.4
Minimize Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.4.1
Transactional Aborts due to Data Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.4.2
Transactional Aborts due to Limited Transactional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.4.3
Lock Elision Specific Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2.4.4
HLE Specific Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13-1
13-2
13-2
13-3
13-3
13-3
13-3
13-3
13-4
13-5
13-6
13-7
13-7
xi
CONTENTS
PAGE
13.2.4.5
13.2.5
13.2.6
13.2.6.1
13.2.6.2
13.2.6.3
13.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.6.1
13.3.6.2
13.3.6.3
13.3.6.4
13.3.7
13.3.8
13.3.9
13.3.10
13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.4.8
13.4.9
13.4.10
13.5
13.6
13.7
13.7.1
13.7.1.1
13.7.2
13.7.2.1
13.7.2.2
13.7.2.3
13.7.3
Miscellaneous Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Using Transactional-Only Code Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Dealing with Transactional Regions or Paths that Abort at a High Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Transitioning to Non-Elided Execution without Aborting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Forcing an Early Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Not Eliding Selected Locks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
DEVELOPING AN INTEL TSX ENABLED SYNCHRONIZATION LIBRARY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Adding HLE Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Elision Friendly Critical Section Locks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Using HLE or RTM for Lock Elision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
An example wrapper for lock elision using RTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Guidelines for the RTM fallback handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Implementing Elision-Friendly Locks using Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Implementing a Simple Spinlock using HLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Implementing Reader-Writer Locks using Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Implementing Ticket Locks using Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Implementing Queue-Based Locks using Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Eliding Application-Specific Meta-Locks using Intel TSX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Avoiding Persistent Non-Elided Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Reading the Value of an Elided Lock in RTM-based libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
Intermixing HLE and RTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
USING THE PERFORMANCE MONITORING SUPPORT FOR INTEL TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
Measuring Transactional Success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
Finding locks to elide and verifying all locks are elided. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
Sampling Transactional Aborts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
Classifying Aborts using a Profiling Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
XABORT Arguments for RTM fallback handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
Call Graphs for Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
Last Branch Records and Transactional Aborts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
Profiling and Testing Intel TSX Software using the Intel® SDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
HLE Specific Performance Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24
Computing Useful Metrics for Intel TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
PERFORMANCE GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
DEBUGGING GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
COMMON INTRINSICS FOR INTEL TSX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
RTM C intrinsics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
Emulated RTM intrinsics on older gcc compatible compilers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
HLE intrinsics on gcc and other Linux compatible compilers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
Generating HLE intrinsics with gcc4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
C++11 atomic support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
Emulating HLE intrinsics with older gcc-compatible compilers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
HLE intrinsics on Windows C/C++ compilers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
CHAPTER 14
POWER OPTIMIZATION FOR MOBILE USAGES
14.1
14.2
14.2.1
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.4.7.1
14.4.7.2
14.4.7.3
xii
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
MOBILE USAGE SCENARIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
Intelligent Energy Efficient Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
ACPI C-STATES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Processor-Specific C4 and Deep C4 States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Processor-Specific Deep C-States and Intel® Turbo Boost Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Processor-Specific Deep C-States for Intel® Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . 14-5
Intel® Turbo Boost Technology 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
GUIDELINES FOR EXTENDING BATTERY LIFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Adjust Performance to Meet Quality of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Reducing Amount of Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Platform-Level Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
Handling Sleep State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Using Enhanced Intel SpeedStep® Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Enabling Intel® Enhanced Deeper Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Multicore Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Enhanced Intel SpeedStep® Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Thread Migration Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
Multicore Considerations for C-States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
CONTENTS
PAGE
14.5
TUNING SOFTWARE FOR INTELLIGENT POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.1
Reduction of Active Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.1.1
Multi-threading to reduce Active Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
14.5.1.2
Vectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
14.5.2
PAUSE and Sleep(0) Loop Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
14.5.3
Spin-Wait Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.4
Using Event Driven Service Instead of Polling in Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.5
Reducing Interrupt Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.6
Reducing Privileged Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
14.5.7
Setting Context Awareness in the Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
14.5.8
Saving Energy by Optimizing for Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.6
PROCESSOR SPECIFIC POWER MANAGEMENT OPTIMIZATION FOR SYSTEM SOFTWARE . . . . . . . . . . . . . . . . . . . 14-17
14.6.1
Power Management Recommendation of Processor-Specific Inactive State Configurations . . . . . . . . . . . . . 14-17
14.6.1.1
Balancing Power Management and Responsiveness of Inactive To Active State Transitions. . . . . . . . . . 14-19
CHAPTER 15
SKYLAKE SERVER MICROARCHITECTURE AND SOFTWARE OPTIMIZATION FOR INTEL®
AVX-512
15.1
BASIC INTEL® AVX-512 VS. INTEL® AVX2 CODING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.1
Intrinsic Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.2
Assembly Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2
MASKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.2.1
Masking Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.2.2
Masking Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
15.2.3
Masking vs. Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.2.4
Nested Conditions / Mask Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
15.2.5
Memory Masking Microarchitecture Improvements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
15.2.6
Peeling and Remainder Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.3
FORWARDING AND UNMASKED OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
15.4
FORWARDING AND MEMORY MASKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.5
DATA COMPRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.5.1
Data Compress Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
15.6
DATA EXPAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.6.1
Data Expand Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.7
TERNARY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.7.1
Ternary Logic Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
15.7.2
Ternary Logic Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
15.8
NEW SHUFFLE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
15.8.1
Two Source Permute Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
15.9
BROADCAST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.9.1
Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.9.2
Broadcast Executed on Load Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
15.10 EMBEDDED ROUNDING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29
15.10.1
Static Rounding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29
15.11 SCATTER INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
15.11.1
Data Scatter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31
15.12 STATIC ROUNDING MODES, SUPPRESS-ALL-EXCEPTIONS (SAE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33
15.13 QWORD INSTRUCTION SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-33
15.13.1
QUADWORD Support in Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
15.13.2
QUADWORD Support in Convert Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37
15.13.3
QUADWORD Support for Convert with Truncation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.14 VECTOR LENGTH ORTHOGONALITY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.15 NEW INTEL® AVX-512 INSTRUCTIONS FOR TRANSCENDENTAL SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.15.1
VRCP14, VRSQRT14 - Software Sequences for 1/x, x/y, sqrt(x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.15.1.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
15.15.2
VGETMANT VGETEXP - Vector Get Mantissa and Vector Get Exponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.15.2.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.15.3
VRNDSCALE - Vector Round Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.15.3.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39
15.15.4
VREDUCE - Vector Reduce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
15.15.4.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
15.15.5
VSCALEF - Vector Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
15.15.5.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40
xiii
CONTENTS
PAGE
15.15.6
VFPCLASS - Vector Floating Point Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
15.15.6.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
15.15.7
VPERM, VPERMI2, VPERMT2 - Small Table Lookup Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
15.15.7.1
Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
15.16 CONFLICT DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-41
15.16.1
Vectorization with Conflict Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-42
15.16.2
Sparse Dot Product with VPCONFLICT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-46
15.17 FMA LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48
15.18 MIXING INTEL® AVX EXTENSIONS OR INTEL® AVX-512 EXTENSIONS WITH INTEL® STREAMING SIMD EXTENSIONS
(INTEL® SSE) CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49
15.19 MIXING ZMM VECTOR CODE WITH XMM/YMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50
15.20 SERVERS WITH A SINGLE FMA UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51
15.21 GATHER/SCATTER TO SHUFFLE (G2S/STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54
15.21.1
Gather to Shuffle in Strided Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54
15.21.2
Scatter to Shuffle in Strided Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-56
15.21.3
Gather to Shuffle in Adjacent Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-57
15.22 DATA ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-58
15.22.1
Align Data to 64 Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-58
15.23 DYNAMIC MEMORY ALLOCATION AND MEMORY ALIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-59
15.24 DIVISION AND SQUARE ROOT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-60
15.24.1
Divide and Square Root Approximation Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-61
15.24.2
Divide and Square Root Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-62
15.24.3
Approximation Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-62
15.24.4
Code Snippets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64
15.24.4.1
Single Precision, Divide, 24 Bits (IEEE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64
15.24.4.2
Single Precision, Divide, 23 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-64
15.24.4.3
Single Precision, Divide, 14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65
15.24.4.4
Single Precision, Reciprocal Square Root, 22 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65
15.24.4.5
Single Precision, Reciprocal Square Root, 23 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-65
15.24.4.6
Single Precision, Reciprocal Square Root, 14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-66
15.24.4.7
Single Precision, Square Root, 24 Bits (IEEE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-66
15.24.4.8
Single Precision, Square Root, 23 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-66
15.24.4.9
Single Precision, Square Root, 14 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67
15.24.4.10
Double Precision, Divide, 53 Bits (IEEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67
15.24.4.11
Double Precision, Divide, 52 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67
15.24.4.12
Double Precision, Divide, 26 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-68
15.24.4.13
Double Precision, Divide, 14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-68
15.24.4.14
Double Precision, Reciprocal Square Root, 51 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-69
15.24.4.15
Double Precision, Reciprocal Square Root, 52 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-69
15.24.4.16
Double Precision, Reciprocal Square Root, 50 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-70
15.24.4.17
Double Precision, Reciprocal Square Root, 26 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-70
15.24.4.18
Double Precision, Reciprocal Square Root, 14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-71
15.24.4.19
Double Precision, Square Root, 53 Bits (IEEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-71
15.24.4.20
Double Precision, Square Root, 52 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-71
15.24.4.21
Double Precision, Square Root, 26 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-72
15.24.4.22
Double Precision, Square Root, 14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-72
15.25 TIPS ON COMPILER USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-72
15.26 SKYLAKE SERVER POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-76
CHAPTER 16
SOFTWARE OPTIMIZATION FOR GOLDMONT PLUS, GOLDMONT, AND SILVERMONT
MICROARCHITECTURES
16.1
MICROARCHITECTURES OF RECENT INTEL ATOM PROCESSOR GENERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.1
Goldmont Plus Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1.2
Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4
16.1.3
Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
16.1.3.1
Integer Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.1.3.2
Floating-Point Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.2
CODING RECOMMENDATIONS FOR GOLDMONT PLUS, GOLDMONT AND SILVERMONT
MICROARCHITECTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.2.1
Optimizing The Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.2.1.1
Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10
16.2.1.2
Front End High IPC Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
xiv
CONTENTS
PAGE
16.2.1.3
Branching Across 4GB Boundary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.2.1.4
Loop Unrolling and Loop Stream Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.2.1.5
Mixing Code and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.2.2
Optimizing The Execution Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.2.2.1
Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.2.2.2
Address Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.2.2.3
FP Multiply-Accumulate-Store Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
16.2.2.4
Integer Multiply Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
16.2.2.5
Zeroing Idioms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.2.2.6
NOP Idioms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.2.2.7
Move Elimination and ESP Folding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.2.2.8
Stack Manipulation Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.2.2.9
Flags usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.2.2.10
SIMD Floating-Point and X87 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.2.2.11
SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.2.2.12
Vectorization Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17
16.2.2.13
Other SIMD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.2.2.14
Instruction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
16.2.2.15
Integer Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
16.2.2.16
Integer Shift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
16.2.2.17
Pause Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.2.3
Optimizing Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.2.3.1
Reduce Unaligned Memory Access with PALIGNR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.2.3.2
Minimize Memory Execution Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.2.3.3
Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21
16.2.3.4
PrefetchW Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
16.2.3.5
Cache Line Splits and Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16.2.3.6
Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16.2.3.7
Copy and String Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
16.3
INSTRUCTION LATENCY AND THROUGHPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23
CHAPTER 17
KNIGHTS LANDING MICROARCHITECTURE AND SOFTWARE OPTIMIZATION
17.1
KNIGHTS LANDING MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.1.1
Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.2
Out-of-Order Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
17.1.3
UnTile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.2
INTEL® AVX-512 CODING RECOMMENDATIONS FOR KNIGHTS LANDING MICROARCHITECTURE . . . . . . . . . . . . . . 17-7
17.2.1
Using Gather and Scatter Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2.2
Using Enhanced Reciprocal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
17.2.3
Using AVX-512CD Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
17.2.4
Using Intel® Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
17.2.5
Front End Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.2.5.1
Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.2.5.2
Branching Indirectly Across a 4GB Boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.2.6
Integer Execution Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.2.6.1
Flags usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.2.6.2
Integer Division. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.2.7
Optimizing FP and Vector Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.2.7.1
Instruction Selection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
17.2.7.2
Porting Intrinsic From Prior Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.2.7.3
Vectorization Trade-Off Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
17.2.8
Memory Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.2.8.1
Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
17.2.8.2
Hardware Prefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.2.8.3
Software Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.2.8.4
Memory Execution Cluster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
17.2.8.5
Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.2.8.6
Way, Set Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
17.2.8.7
Streaming Store Versus Regular Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.2.8.8
Compiler Switches and Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
17.2.8.9
Direct Mapped MCDRAM Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20
xv
CONTENTS
PAGE
APPENDIX A
APPLICATION PERFORMANCE TOOLS
A.1
A.1.1
A.1.2
A.1.2.1
A.1.2.2
A.1.3
A.1.4
A.1.4.1
A.1.4.2
A.1.5
A.2
A.2.1
A.2.2
A.2.3
A.2.4
A.3
A.3.1
A.3.1.1
A.3.1.2
A.3.1.3
A.4
A.4.1
A.5
A.5.1
A.6
A.6.1
A.6.1.1
A.6.2
A.6.3
A.7
COMPILERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Optimization Settings for Intel® 64 and IA-32 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vectorization and Loop Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multithreading with OpenMP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inline Expansion of Library Functions (/Oi, /Oi-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interprocedural and Profile-Guided Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interprocedural Optimization (IPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Profile-Guided Optimization (PGO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Cilk™ Plus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PERFORMANCE LIBRARIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Integrated Performance Primitives (Intel® IPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Math Kernel Library (Intel® MKL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Threading Building Blocks (Intel® TBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Benefits Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PERFORMANCE PROFILERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® VTune™ Amplifier XE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Event-Based Sampling Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Algorithm Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Platform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THREAD AND MEMORY CHECKERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Inspector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VECTORIZATION ASSISTANT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Advisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLUSTER TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® Trace Analyzer and Collector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPI Performance Snapshot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® MPI Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel® MPI Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTEL® ACADEMIC COMMUNITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX B
USING PERFORMANCE MONITORING EVENTS
B.1
B.1.1
B.1.2
B.1.3
B.1.4
B.1.5
B.1.6
B.1.7
B.1.8
B.1.8.1
B.2
B.3
B.4
B.4.1
B.4.1.1
B.4.1.2
B.4.2
B.4.2.1
B.4.3
B.4.3.1
B.4.3.2
B.4.3.3
B.4.3.4
B.4.3.5
B.4.3.6
B.4.3.7
B.4.3.8
B.4.3.9
xvi
A-2
A-2
A-3
A-3
A-3
A-3
A-3
A-3
A-4
A-4
A-4
A-5
A-5
A-5
A-5
A-5
A-6
A-6
A-6
A-6
A-6
A-7
A-7
A-7
A-7
A-7
A-7
A-7
A-8
A-8
TOP-DOWN ANALYSIS METHOD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Top-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Front End Bound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3
Back End Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Memory Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Core Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Bad Speculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Retiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
TMAM and Skylake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
TMAM Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
PERFORMANCE MONITORING AND MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
INTEL® XEON® PROCESSOR 5500 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-13
PERFORMANCE ANALYSIS TECHNIQUES FOR INTEL® XEON® PROCESSOR 5500 SERIES . . . . . . . . . . . . . . . . . . . . . B-14
Cycle Accounting and Uop Flow Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
Cycle Drill Down and Branch Mispredictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16
Basic Block Drill Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19
Stall Cycle Decomposition and Core Memory Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20
Measuring Costs of Microarchitectural Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-20
Core PMU Precise Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21
Precise Memory Access Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-22
Load Latency Event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-23
Precise Execution Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-25
Last Branch Record (LBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-26
Measuring Core Memory Access Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
Measuring Per-Core Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30
Miscellaneous L1 and L2 Events for Cache Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31
TLB Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-31
L1 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-32
CONTENTS
PAGE
B.4.4
B.4.4.1
B.4.4.2
B.4.5
B.4.5.1
B.4.5.2
B.4.5.3
B.4.5.4
B.4.6
B.4.7
B.5
B.5.1
B.5.2
B.5.2.1
B.5.2.2
B.5.2.3
B.5.3
B.5.4
B.5.4.1
B.5.4.2
B.5.4.3
B.5.4.4
B.5.5
B.5.5.1
B.5.5.2
B.5.6
B.5.6.1
B.5.7
B.5.7.1
B.5.7.2
B.5.7.3
B.5.7.4
B.5.7.5
B.6
B.6.1
B.6.2
B.6.3
B.7
B.7.1
B.7.2
B.7.3
B.8
B.8.1
B.8.2
B.8.2.1
B.8.2.2
B.8.2.3
B.8.2.4
B.8.2.5
B.8.2.6
B.8.3
B.8.3.1
B.8.3.2
B.8.3.3
B.8.4
B.8.4.1
B.8.4.2
B.8.4.3
B.8.4.4
B.8.4.5
B.8.4.6
B.8.5
B.8.5.1
B.8.5.2
Front End Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Mispredictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front End Code Generation Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Uncore Performance Monitoring Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Queue Occupancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Queue Port Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Queue Snoop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
L3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intel QuickPath Interconnect Home Logic (QHL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measuring Bandwidth From the Uncore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PERFORMANCE TUNING TECHNIQUES FOR INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE . . . . . . .
Correlating Performance Bottleneck to Source Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hierarchical Top-Down Performance Characterization Methodology and Locating Performance
Bottlenecks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Back End Bound Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Bound Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bound Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Back End Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Sub-System Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accounting for Load Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache-line Replacement Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lock Contention Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Memory Access Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Longer Instruction Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bad Speculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Mispredicts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front End Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding the Micro-op Delivery Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Understanding the Sources of the Micro-op Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Decoded ICache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Issues in the Legacy Decode Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USING PERFORMANCE EVENTS OF INTEL® CORE™ SOLO AND INTEL® CORE™ DUO PROCESSORS. . . . . . . . . . . . . .
Understanding the Results in a Performance Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ratio Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes on Selected Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRILL-DOWN TECHNIQUES FOR PERFORMANCE ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Composition at Issue Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cycle Composition of OOO Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drill-Down on Performance Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVENT RATIOS FOR INTEL CORE MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks Per Instructions Retired Ratio (CPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front End Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Code Locality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branching and Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer Tracker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Macro-fusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Length Changing Prefix (LCP) Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Self Modifying Code Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Prediction Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Branch Mispredictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Tables and Indirect Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mispredicted Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resource Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ROB Read Port Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Register Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Partial Flag Stalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass Between Execution Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating-Point Performance Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Sub-System - Access Conflicts Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loads Blocked by the L1 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4K Aliasing and Store Forwarding Block Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-32
B-32
B-32
B-33
B-33
B-35
B-35
B-36
B-36
B-41
B-42
B-42
B-43
B-44
B-44
B-44
B-45
B-46
B-47
B-48
B-49
B-49
B-52
B-52
B-52
B-53
B-53
B-53
B-53
B-55
B-56
B-57
B-57
B-58
B-58
B-58
B-59
B-59
B-61
B-61
B-62
B-63
B-63
B-64
B-64
B-64
B-64
B-64
B-65
B-65
B-65
B-65
B-65
B-66
B-66
B-66
B-66
B-66
B-66
B-66
B-66
B-67
B-67
B-67
xvii
CONTENTS
PAGE
B.8.5.3
B.8.5.4
B.8.5.5
B.8.6
B.8.6.1
B.8.6.2
B.8.6.3
B.8.7
B.8.7.1
B.8.7.2
B.8.7.3
B.8.8
B.8.9
B.8.9.1
B.8.9.2
B.8.9.3
B.8.10
B.8.10.1
B.8.10.2
Load Block by Preceding Stores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-67
Memory Disambiguation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
Load Operation Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
Memory Sub-System - Cache Misses Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
Locating Cache Misses in the Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
L1 Data Cache Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
L2 Cache Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-68
Memory Sub-system - Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
L1 Data Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
L2 Hardware Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
Software Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
Memory Sub-system - TLB Miss Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-69
Memory Sub-system - Core Interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Modified Data Sharing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Fast Synchronization Penalty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Simultaneous Extensive Stores and Load Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Memory Sub-system - Bus Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Bus Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70
Modified Cache Lines Eviction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-71
APPENDIX C
INSTRUCTION LATENCY AND THROUGHPUT
C.1
C.2
C.3
C.3.1
C.3.2
C.3.3
C.3.3.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
DEFINITIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
LATENCY AND THROUGHPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Latency and Throughput with Register Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3
Table Footnotes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18
Instructions with Memory Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-19
Software Observable Latency of Memory References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-20
APPENDIX D
INTEL® ATOM™ MICROARCHITECTURE AND SOFTWARE OPTIMIZATION
D.1
D.2
D.2.1
D.3
D.3.1
D.3.2
D.3.2.1
D.3.2.2
D.3.2.3
D.3.2.4
D.3.2.5
D.3.2.6
D.3.3
D.3.3.1
D.3.3.2
D.3.3.3
D.3.3.4
D.3.3.5
D.3.3.6
D.3.3.7
D.3.3.8
D.4
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
INTEL® ATOM™ MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Hyper-Threading Technology Support in Intel® Atom™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
CODING RECOMMENDATIONS FOR INTEL® ATOM™ MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Optimization for Front End of Intel® Atom™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Optimizing the Execution Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
Integer Instruction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5
Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
Integer Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6
Integer Shift Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
Partial Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
FP/SIMD Instruction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-7
Optimizing Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
First-level Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-9
Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
String Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
Parameter Passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
Function Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
Optimization of Multiply/Add Dependent Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
Position Independent Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
INSTRUCTION LATENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
EXAMPLES
Example 2-1.
Example 2-2.
Example 3-1.
Example 3-2.
xviii
Dynamic Pause Loop Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Contended Locks with Increasing Back-off Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Assembly Code with an Unpredictable Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Code Optimization to Eliminate Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
CONTENTS
PAGE
Example 3-3.
Example 3-4.
Example 3-5.
Example 3-6.
Example 3-7.
Example 3-8.
Example 3-9.
Example 3-10.
Example 3-11.
Example 3-12.
Example 3-13.
Example 3-14.
Example 3-15.
Example 3-16.
Example 3-17.
Example 3-18.
Example 3-19.
Example 3-20.
Example 3-21.
Example 3-22.
Example 3-23.
Example 3-24.
Example 3-25.
Example 3-26.
Example 3-27.
Example 3-28.
Example 3-29.
Example 3-30.
Example 3-31.
Example 3-32.
Example 3-33.
Example 3-34.
Example 3-35.
Example 3-36.
Example 3-37.
Example 3-38.
Example 3-39.
Example 3-40.
Example 3-41.
Example 3-42.
Example 3-43.
Example 3-44.
Example 3-45.
Example 3-46.
Example 3-47.
Example 3-48.
Example 3-49.
Example 3-50.
Example 3-51.
Example 3-52.
Example 3-53.
Example 3-54.
Example 3-55.
Example 3-56.
Example 3-57.
Example 3-58.
Example 4-1.
Example 4-2.
Example 4-3.
Eliminating Branch with CMOV Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Use of PAUSE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Static Branch Prediction Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Static Taken Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Static Not-Taken Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Indirect Branch With Two Favored Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
A Peeling Technique to Reduce Indirect Branch Misprediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Loop Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Macro-fusion, Unsigned Iteration Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Macro-fusion, If Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Macro-fusion, Signed Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Macro-fusion, Signed Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Additional Macro-fusion Benefit in Intel Microarchitecture Code Name Sandy Bridge. . . . . . . . . . . . . . 3-16
Avoiding False LCP Delays with 0xF7 Group Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
Unrolling Loops in LSD to Optimize Emission Bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Independent Two-Operand LEA Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Alternative to Three-Operand LEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Examples of 512-bit Additions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Clearing Register to Break Dependency While Negating Array Elements . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Spill Scheduling Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
Zero-Latency MOV Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Byte-Granular Data Computation Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
Re-ordering Sequence to Improve Effectiveness of Zero-Latency MOV Instructions . . . . . . . . . . . . . . 3-31
Avoiding Partial Register Stalls in Integer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
Avoiding Partial Register Stalls in SIMD Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
Avoiding Partial Flag Register Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
Partial Flag Register Accesses in Intel Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . 3-35
Reference Code Template for Partially Vectorizable Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
Three Alternate Packing Methods for Avoiding Store Forwarding Difficulty . . . . . . . . . . . . . . . . . . . . . . 3-39
Using Four Registers to Reduce Memory Spills and Simplify Result Passing . . . . . . . . . . . . . . . . . . . . . . 3-39
Stack Optimization Technique to Simplify Parameter Passing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
Base Line Code Sequence to Estimate Loop Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
Optimize for Load Port Bandwidth in Intel Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . 3-43
Index versus Pointers in Pointer-Chasing Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
Example of Bank Conflicts in L1D Cache and Remedy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
Using XMM Register in Lieu of Memory for Register Spills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Loads Blocked by Stores of Unknown Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
Code That Causes Cache Line Split . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
Situations Showing Small Loads After Large Store. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
Non-forwarding Example of Large Load After Small Store. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
A Non-forwarding Situation in Compiler Generated Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51
Two Ways to Avoid Non-forwarding Situation in Example 3-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
Large and Small Load Stalls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
Loop-carried Dependence Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
Rearranging a Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
Decomposing an Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55
Examples of Dynamical Stack Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57
Aliasing Between Loads and Stores Across Loop Iterations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
Instruction Pointer Query Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60
Using Non-temporal Stores and 64-byte Bus Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
On-temporal Stores and Partial Bus Write Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
Using DCU Hardware Prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
Avoid Causing DCU Hardware Prefetch to Fetch Un-needed Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65
Technique For Using L1 Hardware Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
REP STOSD with Arbitrary Count Size and 4-Byte-Aligned Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68
Algorithm to Avoid Changing Rounding Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Identification of MMX Technology with CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Identification of SSE with CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Identification of SSE2 with cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
xix
CONTENTS
PAGE
Example 4-4.
Example 4-5.
Example 4-6.
Example 4-7.
Example 4-8.
Example 4-9.
Example 4-10.
Example 4-11.
Example 4-12.
Example 4-13.
Example 4-14.
Example 4-15.
Example 4-16.
Example 4-17.
Example 4-18.
Example 4-19.
Example 4-20.
Example 4-21.
Example 4-22.
Example 4-23.
Example 4-24.
Example 4-25.
Example 4-26.
Example 5-1.
Example 5-2.
Example 5-3.
Example 5-4.
Example 5-5.
Example 5-6.
Example 5-7.
Example 5-8.
Example 5-9.
Example 5-10.
Example 5-11.
Example 5-12.
Example 5-13.
Example 5-14.
Example 5-15.
Example 5-16.
Example 5-17.
Example 5-18.
Example 5-19.
Example 5-20.
Example 5-21.
Example 5-22.
Example 5-23.
Example 5-24.
Example 5-25.
Example 5-26.
Example 5-27.
Example 5-28.
Example 5-29.
Example 5-30.
Example 5-31.
Example 5-32.
Example 5-33.
Example 5-34.
Example 5-35.
Example 5-36.
xx
Identification of SSE3 with CPUID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Identification of SSSE3 with cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Identification of SSE4.1 with cpuid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Identification of SSE4.2 with cpuid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Detection of AESNI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Detection of PCLMULQDQ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Detection of AVX Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Detection of VEX-Encoded AESNI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Detection of VEX-Encoded AESNI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Simple Four-Iteration Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Streaming SIMD Extensions Using Inlined Assembly Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Simple Four-Iteration Loop Coded with Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
C++ Code Using the Vector Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
Automatic Vectorization for a Simple Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16
C Algorithm for 64-bit Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
AoS Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
SoA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
AoS and SoA Code Samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
Hybrid SoA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Pseudo-code Before Strip Mining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Strip Mined Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Loop Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Emulation of Conditional Moves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Resetting Register Between __m64 and FP Data Types Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
FIR Processing Example in C language Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
SSE2 and SSSE3 Implementation of FIR Processing Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Zero Extend 16-bit Values into 32 Bits Using Unsigned Unpack Instructions Code . . . . . . . . . . . . . . . . . . 5-5
Signed Unpack Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Interleaved Pack with Saturation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Interleaved Pack without Saturation Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Unpacking Two Packed-word Sources in Non-interleaved Way Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
PEXTRW Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
PINSRW Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Repeated PINSRW Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Non-Unit Stride Load/Store Using SSE4.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Scatter and Gather Operations Using SSE4.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
PMOVMSKB Instruction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Broadcast a Word Across XMM, Using 2 SSE2 Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Swap/Reverse words in an XMM, Using 3 SSE2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
Generating Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Absolute Difference of Two Unsigned Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Absolute Difference of Signed Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Computing Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Basic C Implementation of RGBA to BGRA Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Color Pixel Format Conversion Using SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Color Pixel Format Conversion Using SSSE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Big-Endian to Little-Endian Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Clipping to a Signed Range of Words [High, Low]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Clipping to an Arbitrary Signed Range [High, Low] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Simplified Clipping to an Arbitrary Signed Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Clipping to an Arbitrary Unsigned Range [High, Low] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Complex Multiply by a Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Using PTEST to Separate Vectorizable and non-Vectorizable Loop Iterations. . . . . . . . . . . . . . . . . . . . . 5-24
Using Variable BLEND to Vectorize Heterogeneous Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Baseline C Code for Mandelbrot Set Map Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Vectorized Mandelbrot Set Map Evaluation Using SSE4.1 Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
A Large Load after a Series of Small Stores (Penalty) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Accessing Data Without Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
A Series of Small Loads After a Large Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
CONTENTS
PAGE
Example 5-37.
Example 5-38.
Example 5-39.
Example 5-40.
Example 5-41.
Example 5-42.
Example 5-43.
Example 5-44.
Example 5-45.
Example 5-46.
Example 5-47.
Example 5-48.
Example 5-49.
Example 5-50.
Example 6-1.
Example 6-2.
Example 6-3.
Example 6-4.
Example 6-5.
Example 6-6.
Example 6-7.
Example 6-8.
Example 6-9.
Example 6-10.
Example 6-11.
Example 6-12.
Example 6-13.
Example 6-14.
Example 6-15.
Example 6-16.
Example 6-17.
Example 6-18.
Example 6-19.
Example 6-20.
Example 6-21.
Example 6-22.
Example 6-23.
Example 6-24.
Example 7-1.
Example 7-2.
Example 7-3.
Example 7-4.
Example 7-5.
Example 7-6.
Example 7-7.
Example 7-8.
Example 7-9.
Example 7-10.
Example 7-11.
Example 7-12.
Example 9-1.
Example 9-2.
Example 9-3.
Example 9-4.
Example 9-5.
Example 9-6.
Example 9-7.
Example 9-8.
Example 9-9.
Eliminating Delay for a Series of Small Loads after a Large Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
An Example of Video Processing with Cache Line Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
Video Processing Using LDDQU to Avoid Cache Line Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Un-optimized Reverse Memory Copy in C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Using PSHUFB to Reverse Byte Ordering 16 Bytes at a Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
PMOVSX/PMOVZX Work-around to Avoid False Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Table Look-up Operations in C Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
Shift Techniques on Non-Vectorizable Table Look-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
PEXTRD Techniques on Non-Vectorizable Table Look-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
Pseudo-Code Flow of AES Counter Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
AES128-CTR Implementation with Eight Block in Parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
AES128 Key Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-46
Compress 32-bit Integers into 5-bit Buckets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-49
Decompression of a Stream of 5-bit Integers into 32-bit Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51
Pseudocode for Horizontal (xyz, AoS) Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Pseudocode for Vertical (xxxx, yyyy, zzzz, SoA) Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Swizzling Data Using SHUFPS, MOVLHPS, MOVHLPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Swizzling Data Using UNPCKxxx Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Deswizzling Single-Precision SIMD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Deswizzling Data Using SIMD Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Horizontal Add Using MOVHLPS/MOVLHPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Horizontal Add Using Intrinsics with MOVHLPS/MOVLHPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Multiplication of Two Pair of Single-precision Complex Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Division of Two Pair of Single-precision Complex Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Double-Precision Complex Multiplication of Two Pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Double-Precision Complex Multiplication Using Scalar SSE2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Dot Product of Vector Length 4 Using SSE/SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Dot Product of Vector Length 4 Using SSE3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Dot Product of Vector Length 4 Using SSE4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Unrolled Implementation of Four Dot Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Normalization of an Array of Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Normalize (x, y, z) Components of an Array of Vectors Using SSE2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Normalize (x, y, z) Components of an Array of Vectors Using SSE4.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Data Organization in Memory for AOS Vector-Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
AOS Vector-Matrix Multiplication with HADDPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
AOS Vector-Matrix Multiplication with DPPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Data Organization in Memory for SOA Vector-Matrix Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Vector-Matrix Multiplication with Native SOA Data Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Pseudo-code Using CLFLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
Flushing Cache Lines Using CLFLUSH or CLFLUSHOPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Populating an Array for Circular Pointer Chasing with Constant Stride . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
Prefetch Scheduling Distance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Using Prefetch Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Concatenation and Unrolling the Last Iteration of Inner Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Data Access of a 3D Geometry Engine without Strip-mining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
Data Access of a 3D Geometry Engine with Strip-mining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
Using HW Prefetch to Improve Read-Once Memory Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Basic Algorithm of a Simple Memory Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
A Memory Copy Routine Using Software Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Memory Copy Using Hardware Prefetch and Bus Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29
Serial Execution of Producer and Consumer Work Items. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Basic Structure of Implementing Producer Consumer Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Thread Function for an Interlaced Producer Consumer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
Spin-wait Loop and PAUSE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Coding Pitfall using Spin Wait Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Placement of Synchronization and Regular Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Declaring Synchronization Variables without Sharing a Cache Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Batched Implementation of the Producer Consumer Threads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
Parallel Memory Initialization Technique Using OpenMP and NUMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24
xxi
CONTENTS
PAGE
Example 10-1. Compute 64-bit Quotient and Remainder with 64-bit Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Example 10-2. Quotient and Remainder of 128-bit Dividend with 64-bit Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Example 11-1. A Hash Function Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Example 11-2. Hash Function Using CRC32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Example 11-3. Strlen() Using General-Purpose Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Example 11-4. Sub-optimal PCMPISTRI Implementation of EOS handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Example 11-5. Strlen() Using PCMPISTRI without Loop-Carry Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Example 11-6. WordCnt() Using C and Byte-Scanning Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Example 11-7. WordCnt() Using PCMPISTRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
Example 11-8. KMP Substring Search in C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Example 11-9. Brute-Force Substring Search Using PCMPISTRI Intrinsic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Example 11-10.Substring Search Using PCMPISTRI and KMP Overlap Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Example 11-11.I Equivalent Strtok_s() Using PCMPISTRI Intrinsic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Example 11-12.I Equivalent Strupr() Using PCMPISTRM Intrinsic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Example 11-13.UTF16 VerStrlen() Using C and Table Lookup Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
Example 11-14.Assembly Listings of UTF16 VerStrlen() Using PCMPISTRI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Example 11-15.Intrinsic Listings of UTF16 VerStrlen() Using PCMPISTRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25
Example 11-16.Replacement String Library Strcmp Using SSE4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
Example 11-17.High-level flow of Character Subset Validation for String Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Example 11-18.Intrinsic Listings of atol() Replacement Using PCMPISTRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29
Example 11-19.Auxiliary Routines and Data Constants Used in sse4i_atol() listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31
Example 11-20.Conversion of 64-bit Integer to ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34
Example 11-21.Conversion of 64-bit Integer to ASCII without Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35
Example 11-22.Conversion of 64-bit Integer to ASCII Using SSE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
Example 11-23.Conversion of 64-bit Integer to Wide Character String Using SSE4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43
Example 11-24. MULX and Carry Chain in Large Integer Numeric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48
Example 11-25. Building-block Macro Used in Binary Decimal Floating-point Operations . . . . . . . . . . . . . . . . . . . . . . . . . 11-49
Example 12-1. Cartesian Coordinate Transformation with Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
Example 12-2. Cartesian Coordinate Transformation with Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Example 12-3. Direct Polynomial Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Example 12-4. Function Calls and AVX/SSE transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Example 12-5. AoS to SoA Conversion of Complex Numbers in C Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Example 12-6. Aos to SoA Conversion of Complex Numbers Using AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Example 12-7. Register Overlap Method for Median of 3 Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
Example 12-8. Data Gather - AVX versus Scalar Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
Example 12-9. Scatter Operation Using AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
Example 12-10.SAXPY using Intel AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19
Example 12-11.Using 16-Byte Memory Operations for Unaligned 32-Byte Memory Operation. . . . . . . . . . . . . . . . . . . 12-21
Example 12-12.SAXPY Implementations for Unaligned Data Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
Example 12-13.Loop with Conditional Expression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
Example 12-14.Handling Loop Conditional with VMASKMOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
Example 12-15.Three-Tap Filter in C Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
Example 12-16.Three-Tap Filter with 128-bit Mixed Integer and FP SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
Example 12-17.256-bit AVX Three-Tap Filter Code with VSHUFPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
Example 12-18.Three-Tap Filter Code with Mixed 256-bit AVX and 128-bit AVX Code. . . . . . . . . . . . . . . . . . . . . . . . . . 12-27
Example 12-19.8x8 Matrix Transpose - Replace Shuffles with Blends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-29
Example 12-20.8x8 Matrix Transpose Using VINSRTPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
Example 12-21.Port 5 versus Load Port Shuffles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
Example 12-22.Divide Using DIVPS for 24-bit Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Example 12-23.Divide Using RCPPS 11-bit Approximation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Example 12-24.Divide Using RCPPS and Newton-Raphson Iteration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Example 12-25.Reciprocal Square Root Using DIVPS+SQRTPS for 24-bit Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
Example 12-26.Reciprocal Square Root Using RCPPS 11-bit Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
Example 12-27.Reciprocal Square Root Using RCPPS and Newton-Raphson Iteration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38
Example 12-28.Square Root Using SQRTPS for 24-bit Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
Example 12-29. Square Root Using RCPPS 11-bit Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
Example 12-30. Square Root Using RCPPS and One Taylor Series Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40
Example 12-31. Array Sub Sums Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42
Example 12-32. Single-Precision to Half-Precision Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
xxii
CONTENTS
PAGE
Example 12-33. Half-Precision to Single-Precision Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
Example 12-34. Performance Comparison of Median3 using Half-Precision vs. Single-Precision . . . . . . . . . . . . . . . . . . 12-45
Example 12-35. FP Mul/FP Add Versus FMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47
Example 12-36. Unrolling to Hide Dependent FP Add Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47
Example 12-37. FP Mul/FP Add Versus FMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49
Example 12-38. Macros for Separable KLT Intra-block Transformation Using AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50
Example 12-39. Separable KLT Intra-block Transformation Using AVX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51
Example 12-40. Macros for Parallel Moduli/Remainder Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57
Example 12-41. Signed 64-bit Integer Conversion Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-58
Example 12-42. Unsigned 63-bit Integer Conversion Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60
Example 12-43. Access Patterns Favoring Non-VGATHER Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64
Example 12-44. Access Patterns Likely to Favor VGATHER Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65
Example 12-45. Software AVX Sequence Equivalent to Full-Mask VPGATHERD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66
Example 12-46.AOS to SOA Transformation Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-67
Example 12-47. Non-Strided AOS to SOA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-68
Example 12-48. Conversion to Throughput-Reduced MMX sequence to AVX2 Alternative . . . . . . . . . . . . . . . . . . . . . . 12-70
Example 13-1. Reduce Data Conflict with Conditional Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Example 13-2. Transition from Non-Elided Execution without Aborting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
Example 13-3. Exemplary Wrapper Using RTM for Lock/Unlock Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Example 13-4. Spin Lock Example Using HLE in GCC 4.8 and Later . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Example 13-5. Spin Lock Example Using HLE in Intel and Microsoft Compiler Intrinsic . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Example 13-6. A Meta Lock Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Example 13-7. A Meta Lock Example Using RTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Example 13-8. HLE-enabled Lock-Acquire/ Lock-Release Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
Example 13-9. A Spin Wait Example Using HLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
Example 13-10. A Conceptual Example of Intermixed HLE and RTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
Example 13-11. Emulated RTM intrinsic for Older GCC compilers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-27
Example 13-12. C++ Example of HLE Intrinsic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
Example 13-13. Emulated HLE Intrinsic with Older GCC compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
Example 13-14. HLE Intrinsic Supported by Intel and Microsoft Compilers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
Example 14-1. Unoptimized Sleep Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Example 14-2. Power Consumption Friendly Sleep Loop Using PAUSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Example 15-1. Cartesian Coordinate System Rotation with Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Example 15-2. Cartesian Coordinate System Rotation with Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
Example 15-3. Masking with Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Example 15-4. Masking with Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Example 15-5. Masking vs. Blending Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
Example 15-6. Masking vs. Blending Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Example 15-7. Multiple Condition Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Example 15-8. Peeling and Remainder Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
Example 15-9. Comparing Intel® AVX-512 Data Compress with Other Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
Example 15-10.Comparing Intel® AVX-512 Data Expand Operation with Other Alternatives . . . . . . . . . . . . . . . . . . . . . 15-22
Example 15-11.Comparing Ternary Logic to Other Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23
Example 15-12.Comparing Ternary Logic to Other Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
Example 15-13.Broadcast Executed on Load Ports Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-28
Example 15-14.16-bit Broadcast Executed on Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29
Example 15-15.Embedded vs Non-embedded Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30
Example 15-16.Embedded vs Non-embedded Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32
Example 15-17.QWORD Example, Intel® AVX2 vs. Intel® AVX-512. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
Example 15-18.Scatter Implementation Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
Example 15-19.Scalar vs. Vector Update Using AVX-512CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-47
Example 15-20.256-bit Code vs. 256-bit Code Mixed with 512-bit Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50
Example 15-21.Identifying One or Two FMA Units in a Processor Based on Skylake Microarchitecture . . . . . . . . . . . 15-51
Example 15-22.Gather to Shuffle in Strided Loads Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55
Example 15-23.Gather to Shuffle in Strided Stores Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-56
Example 15-24.Gather to Shuffle in Adjacent Loads Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-57
Example 16-1. Unrolled Loop Executes In-Order Due to Multiply-Store Port Conflict. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
Example 16-2. Grouping Store Instructions Eliminates Bubbles and Improves IPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
Example 17-1. Gather Comparison Between AVX-512F and AVX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
xxiii
CONTENTS
PAGE
Example 17-2.
Example 17-3.
Example 17-4.
Example 17-5.
Example 17-6.
Example 17-7.
Example 17-8.
Example D-1.
Example D-2.
Example D-3.
Example D-4.
Example D-5.
Example D-6.
xxiv
Gather Comparison Between AVX-512F and KNC Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8
Using VRCP28SS for 32-bit Floating-Point Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Vectorized Histogram Update Using AVX-512CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Replace VCOMIS* with VCMPSS/KORTEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
Using Software Sequence for Horizontal Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
Optimized Inner Loop of DGEMM for Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . 17-14
Ordering of Memory Instruction for MEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19
Instruction Pairing and Alignment to Optimize Decode Throughput on Intel® Atom™ MicroarchitectureD-4
Alternative to Prevent AGU and Execution Unit Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-6
Pipeling Instruction Execution in Integer Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .D-7
Memory Copy of 64-byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11
Examples of Dependent Multiply and Add Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
Instruction Pointer Query Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13
CONTENTS
PAGE
FIGURES
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 6-4.
Figure 6-5.
Figure 6-6.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 7-7.
Figure 7-8.
Figure 7-9.
Figure 7-10.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Processor Core Pipeline Functionality of the Skylake Server Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Broadwell Microarchitecture and Skylake Server Microarchitecture Cache Structures . . . . . . . . . . . . . . . . . . . 2-5
CPU Core Pipeline Functionality of the Skylake Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CPU Core Pipeline Functionality of the Haswell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Four Core System Integration of the Haswell Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
An Example of the Haswell-E Microarchitecture Supporting 12 Processor Cores . . . . . . . . . . . . . . . . . . . . . 2-19
Intel Microarchitecture Code Name Sandy Bridge Pipeline Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Intel Core Microarchitecture Pipeline Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Execution Core of Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
Store-Forwarding Enhancements in Enhanced Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Intel Advanced Smart Cache Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Intel Microarchitecture Code Name Nehalem Pipeline Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Front End of Intel Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
Store-Forwarding Scenarios of 16-Byte Store Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Store-Forwarding Enhancement in Intel Microarchitecture Code Name Nehalem. . . . . . . . . . . . . . . . . . . . . . 2-60
Hyper-Threading Technology on an SMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Typical SIMD Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
SIMD Instruction Register Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Generic Program Flow of Partially Vectorized Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
Cache Line Split in Accessing Elements in a Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
Size and Alignment Restrictions in Store Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
Memcpy Performance Comparison for Lengths up to 2KB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-69
General Procedural Flow of Application Detection of AVX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
General Procedural Flow of Application Detection of Float-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
Converting to Streaming SIMD Extensions Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Hand-Coded Assembly and High-Level Compiler Performance Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Loop Blocking Access Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
PACKSSDW mm, mm/mm64 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Interleaved Pack with Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Result of Non-Interleaved Unpack Low in MM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Result of Non-Interleaved Unpack High in MM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
PEXTRW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
PINSRW Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
PMOVSMKB Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Data Alignment of Loads and Stores in Reverse Memory Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
A Technique to Avoid Cacheline Split Loads in Reverse Memory Copy Using Two Aligned Loads . . . . . . . 5-33
Homogeneous Operation on Parallel Data Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Horizontal Computation Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Dot Product Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Horizontal Add Using MOVHLPS/MOVLHPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Asymmetric Arithmetic Operation of the SSE3 Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
Horizontal Arithmetic Operation of the SSE3 Instruction HADDPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-11
CLFLUSHOPT versus CLFLUSH In SkyLake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11
Effective Latency Reduction as a Function of Access Stride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
Memory Access Latency and Execution Without Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
Memory Access Latency and Execution With Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15
Prefetch and Loop Unrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Memory Access Latency and Execution With Prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Spread Prefetch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
Cache Blocking – Temporally Adjacent and Non-adjacent Passes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Examples of Prefetch and Strip-mining for Temporally Adjacent and Non-Adjacent Passes Loops . . . . . .7-21
Single-Pass Vs. Multi-Pass 3D Geometry Engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25
Example of SNC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
NUMA Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
SNC Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
SNC On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Domain Example with One MPI Process Per Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
xxv
CONTENTS
PAGE
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 11-4.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
Figure 14-8.
Figure 14-9.
Figure 14-10.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
Figure 15-6.
Figure 15-7.
Figure 15-8.
Figure 15-9.
Figure 15-10.
Figure 15-11.
Figure 15-12.
Figure 15-13.
Figure 15-14.
Figure 15-15.
Figure 15-16.
Figure 15-17.
Figure 15-18.
Figure 16-1.
Figure 16-2.
Figure 16-3.
Figure 17-1.
Figure 17-2.
Figure B-1.
Figure B-2.
Figure B-3.
Figure B-4.
Figure B-5.
Figure B-6.
Figure B-7.
Figure B-8.
Figure B-9.
Figure B-11.
Figure B-10.
xxvi
Amdahl’s Law and MP Speed-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Single-threaded Execution of Producer-consumer Threading Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Execution of Producer-consumer Threading Model on a Multicore Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Interlaced Variation of the Producer Consumer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Batched Approach of Producer Consumer Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20
SSE4.2 String/Text Instruction Immediate Operand Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Retrace Inefficiency of Byte-Granular, Brute-Force Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
SSE4.2 Speedup of SubString Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Compute Four Remainders of Unsigned Short Integer in Parallel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37
AVX-SSE Transitions in the Broadwell, and Prior Generation Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . 12-8
AVX-SSE Transitions in the Skylake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
4x4 Image Block Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50
Throughput Comparison of Gather Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65
Comparison of HW GATHER Versus Software Sequence in Skylake Microarchitecture. . . . . . . . . . . . . . . . 12-66
Performance History and State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Active Time Versus Halted Time of a Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Application of C-states to Idle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Profiles of Coarse Task Scheduling and Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Thread Migration in a Multicore Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Progression to Deeper Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Energy Saving due to Performance Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Energy Saving due to Vectorization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Energy Saving Comparison of Synchronization Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
Power Saving Comparison of Power-Source-Aware Frame Rate Configurations . . . . . . . . . . . . . . . . . . . . . 14-17
Intel® AVX-512 Extensions Supported by Skylake Server Microarchitecture and Knights Landing
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
Cartesian Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
Data Forwarding Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Data Compress Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
Data Expand Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
Ternary Logic Example 1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22
Ternary Logic Example 2 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
vpermi2ps Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25
vscatterdpd Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31
VPCONFLICTD Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-43
VPCONFLICTD Merging Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-44
VPCONFLICTD Permute Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-44
VPCONFLICTD ZMM2 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-45
Sparse Vector Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-46
Fast Bypass When All Sources Come from FMA Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48
Mixing Intel AVX Instructions or Intel AVX-512 Instructions with Intel SSE Instructions . . . . . . . . . . . . . . 15-49
Mixed Workloads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-76
LINPACK Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-77
CPU Core Pipeline Functionality of the Goldmont Plus Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
CPU Core Pipeline Functionality of the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Silvermont Microarchitecture Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
Tile-Mesh Topology of the Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
Processor Core Pipeline Functionality of the Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . 17-2
General TMAM Hierarchy for Out-of-Order Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
TMAM’s Top Level Drill Down Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
TMAM Hierarchy Supported by Skylake Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
System Topology Supported by Intel® Xeon® Processor 5500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-14
PMU Specific Event Logic Within the Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16
LBR Records and Basic Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27
Using LBR Records to Rectify Skewed Sample Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27
RdData Request after LLC Miss to Local Home (Clean Rsp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
RdData Request after LLC Miss to Remote Home (Clean Rsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
RdData Request after LLC Miss to Local Home (Hitm Response) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-39
RdData Request after LLC Miss to Remote Home (Hitm Response) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-39
CONTENTS
PAGE
Figure B-12.
Figure B-13.
Figure B-15.
Figure B-14.
Figure B-16.
Figure D-1.
RdData Request after LLC Miss to Local Home (Hit Response) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-40
RdInvOwn Request after LLC Miss to Remote Home (Clean Res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-40
RdInvOwn Request after LLC Miss to Local Home (Hit Res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
RdInvOwn Request after LLC Miss to Remote Home (Hitm Res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Performance Events Drill-Down and Software Tuning Feedback Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Intel Atom Microarchitecture Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
xxvii
CONTENTS
PAGE
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 2-14.
Table 2-15.
Table 2-16.
Table 2-17.
Table 2-18.
Table 2-19.
Table 2-20.
Table 2-21.
Table 2-22.
Table 2-23.
Table 2-24.
Table 2-25.
Table 2-26.
Table 2-27.
Table 2-28.
Table 2-29.
Table 2-30.
Table 2-31.
Table 2-32.
Table 2-33.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 5-1.
Table 6-1.
Table 7-1.
Table 7-2.
Table 7-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 11-1.
Table 11-2.
Table 11-3.
Table 11-4.
Table 11-5.
Table 12-1.
Table 12-2.
Table 12-3.
Table 12-4.
Table 12-5.
xxviii
Cache Comparison Between Skylake Microarchitecture and Broadwell Microarchitecture . . . . . . . . . . . . . . . 2-4
Dispatch Port and Execution Stacks of the Skylake Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Skylake Microarchitecture Execution Units and Representative Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Bypass Delay Between Producer and Consumer Micro-ops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Cache Parameters of the Skylake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
TLB Parameters of the Skylake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Dispatch Port and Execution Stacks of the Haswell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-15
Haswell Microarchitecture Execution Units and Representative Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .2-16
Bypass Delay Between Producer and Consumer Micro-ops (cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
Cache Parameters of the Haswell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-17
TLB Parameters of the Haswell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18
TLB Parameters of the Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19
Components of the Front End of Intel Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . .2-22
ICache and ITLB of Intel Microarchitecture Code Name Sandy Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-22
Dispatch Port and Execution Stacks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
Execution Core Writeback Latency (cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29
Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29
Lookup Order and Load Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30
L1 Data Cache Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-31
Effect of Addressing Modes on Load Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32
DTLB and STLB Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32
Store Forwarding Conditions (1 and 2 byte stores) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-33
Store Forwarding Conditions (4-16 byte stores) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-33
32-byte Store Forwarding Conditions (0-15 byte alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-34
32-byte Store Forwarding Conditions (16-31 byte alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-34
Components of the Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-40
Issue Ports of Intel Core Microarchitecture and Enhanced Intel Core Microarchitecture. . . . . . . . . . . . . . . . .2-44
Cache Parameters of Processors based on Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-50
Characteristics of Load and Store Operations in Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . .2-51
Bypass Delay Between Producer and Consumer Micro-ops (cycles) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56
Issue Ports of Intel Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56
Cache Parameters of Intel Core i7 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57
Performance Impact of Address Alignments of MOVDQU from L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58
Macro-Fusible Instructions in Intel Microarchitecture Code Name Sandy Bridge . . . . . . . . . . . . . . . . . . . . . . . .3-13
Small Loop Criteria Detected by Sandy Bridge and Haswell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . .3-18
Store Forwarding Restrictions of Processors Based on Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . .3-53
Relative Performance of Memcpy() Using Enhanced REP MOVSB and STOSB Vs. 128-bit AVX . . . . . . . . . .3-70
Effect of Address Misalignment on Memcpy() Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70
Intel Processor CPU RP Device IDs for Processors Optimizing PCIe Performance . . . . . . . . . . . . . . . . . . . . . . .3-78
PSHUF Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
SoA Form of Representing Vertices Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Software Prefetching Considerations into Strip-mining Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23
Relative Performance of Memory Copy Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30
Deterministic Cache Parameters Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
Properties of Synchronization Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
Design-Time Resource Management Choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-22
Microarchitectural Resources Comparisons of HT Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-25
SSE4.2 String/Text Instructions Compare Operation on N-elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
SSE4.2 String/Text Instructions Unary Transformation on IntRes1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3
SSE4.2 String/Text Instructions Output Selection Imm[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3
SSE4.2 String/Text Instructions Element-Pair Comparison Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3
SSE4.2 String/Text Instructions Eflags Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3
Features between 256-bit AVX, 128-bit AVX and Legacy SSE Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-2
State Transitions of Mixing AVX and SSE Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-9
Approximate Magnitude of AVX-SSE Transition Penalties in Different Microarchitectures. . . . . . . . . . . . . .12-9
Effect of VZEROUPPER with Inter-Function Calls Between AVX and SSE Code . . . . . . . . . . . . . . . . . . . . . . 12-10
Comparison of Numeric Alternatives of Selected Linear Algebra in Skylake Microarchitecture . . . . . . . . 12-34
CONTENTS
PAGE
Table 12-6.
Table 12-7.
Table 12-8.
Table 12-9.
Table 12-10.
Table 12-11.
Table 13-1.
Table 14-1.
Table 14-2.
Table 14-3.
Table 14-4.
Table 14-5.
Table 14-6.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 15-5.
Table 15-6.
Table 15-7.
Table 15-8.
Table 15-9.
Table 15-10.
Table 15-11.
Table 15-12.
Table 15-13.
Table 15-15.
Table 15-14.
Table 15-16.
Table 16-1.
Table 16-2.
Table 16-3.
Table 16-5.
Table 16-6.
Table 16-4.
Table 16-7.
Table 16-8.
Table 16-9.
Table 16-10.
Table 16-11.
Table 16-12.
Table 16-13.
Table 16-14.
Table 16-15.
Table 16-16.
Table 16-17.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 17-5.
Table A-1.
Table B-1.
Table B-2.
Single-Precision Divide and Square Root Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
Comparison of Single-Precision Divide Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
Comparison of Single-Precision Reciprocal Square Root Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-39
Comparison of Single-Precision Square Root Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41
Comparison of AOS to SOA with Strided Access Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-68
Comparison of Indexed AOS to SOA Transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69
RTM Abort Status Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
ACPI C-State Type Mappings to Processor Specific C-State for Mobile Processors Based on Intel
Microarchitecture Code Name Nehalem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
ACPI C-State Type Mappings to Processor Specific C-State of Intel Microarchitecture Code Name Sandy
Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
C-State Total Processor Exit Latency for Client Systems (Core+ Package Exit Latency) with Slow VR. 14-18
C-State Total Processor Exit Latency for Client Systems (Core+ Package Exit Latency) with Fast VR . 14-18
C-State Core-Only Exit Latency for Client Systems with Slow VR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
POWER_CTL MSR in Next Generation Intel Processor (Intel® Microarchitecture Code Name Sandy
Bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Masking Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Cache Comparison Between Skylake Server Microarchitecture and Broadwell Microarchitecture . . . . . 15-15
Static Rounding Mode Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-29
Vector Quadword Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37
Scalar Quadword Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37
Vector Quadword Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
Scalar Quadword Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38
FMA Unit Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49
Data Alignment Effects on SAXPY Performance vs. Speedup Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-59
Skylake Microarchitecture Recommendations for DIV/SQRT Based Operations (Single Precision) . . . . . 15-61
Skylake Microarchitecture Recommendations for DIV/SQRT Based Operations (Double Precision) . . . . 15-61
256-bit Intel AVX2 Divide and Square Root Instruction Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-62
512-bit Intel AVX-512 Divide and Square Root Instruction Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-62
Latency/Throughput of Different Methods of Computing Divide and Square Root on Skylake
Microarchitecture for Different Vector Widths, on Double Precision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-63
Latency/Throughput of Different Methods of Computing Divide and Square Root on Skylake
Microarchitecture for Different Vector Widths, on Single Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-63
Maximum Intel® Turbo Boost Technology Core Frequency Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-76
Comparison of Front End Cluster Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Comparison of Distributed Reservation Stations on Scheduling Uops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Function Unit Mapping of the Goldmont Plus Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Comparison of Distributed Reservation Stations on Scheduling Uops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Function Unit Mapping of the Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Comparison of Front End Cluster Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Comparison of MEC Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
Function Unit Mapping of the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
Alternatives to MSROM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
Comparison of Decoder Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Integer Multiply Operation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
Floating-Point and SIMD Integer Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18
Unsigned Integer Division Operation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
Signed Integer Division Operation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20
Store Forwarding Conditions (1 and 2 Byte Stores) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
Store Forwarding Conditions (4-16 Byte Stores). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22
Instructions Latency and Throughput Recent Microarchitectures for Intel Atom Processors . . . . . . . . . 16-24
Integer Pipeline Characteristics of the Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Vector Pipeline Characteristics of the Knights Landing Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5
Characteristics of Caching Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Alternatives to MSROM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
Cycle Cost Building Blocks for Vectorization Estimate for Knights Landing Microarchitecture . . . . . . . . . 17-15
Recommended Processor Optimization Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
Performance Monitoring Taxonomy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
Cycle Accounting and Micro-ops Flow Recipe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
xxix
CONTENTS
PAGE
Table B-3.
Table B-4.
Table B-5.
Table B-6.
Table B-7.
Table B-8.
Table B-9.
Table B-10.
Table B-11.
Table B-12.
Table B-13.
Table B-14.
Table B-15.
Table B-16.
Table C-1.
Table C-2.
Table C-3.
Table C-4.
Table C-5.
Table C-6.
Table C-7.
Table C-8.
Table C-9.
Table C-10.
Table C-11.
Table C-12.
Table C-13.
Table C-14.
Table C-15.
Table C-16.
Table C-17.
Table C-18.
Table D-1.
Table D-2.
xxx
CMask/Inv/Edge/Thread Granularity of Events for Micro-op Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-16
Cycle Accounting of Wasted Work Due to Misprediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17
Cycle Accounting of Instruction Starvation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
CMask/Inv/Edge/Thread Granularity of Events for Micro-op Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-19
Approximate Latency of L2 Misses of Intel Xeon Processor 5500. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-21
Load Latency Event Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24
Data Source Encoding for Load Latency PEBS Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-24
Core PMU Events to Drill Down L2 Misses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-28
Core PMU Events for Super Queue Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
Core PMU Event to Drill Down OFFCore Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
OFFCORE_RSP_0 MSR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29
Common Request and Response Types for OFFCORE_RSP_0 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30
Uncore PMU Events for Occupancy Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-35
Common QHL Opcode Matching Facility Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
CPUID Signature Values of Of Recent Intel Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
Instruction Extensions Introduction by Microarchitectures (CPUID Signature). . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
BMI1, BMI2 and General Purpose Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
256-bit AVX2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5
Gather Timing Data from L1D* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-6
BMI1, BMI2 and General Purpose Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-7
F16C,RDRAND InstructionsC-7
256-bit AVX InstructionsC-7
AESNI and PCLMULQDQ InstructionsC-9
SSE4.2 InstructionsC-10
SSE4.1 InstructionsC-10
Supplemental Streaming SIMD Extension 3 InstructionsC-11
Streaming SIMD Extension 3 SIMD Floating-point InstructionsC-12
Streaming SIMD Extension 2 128-bit Integer InstructionsC-12
Streaming SIMD Extension 2 Double-precision Floating-point InstructionsC-14
Streaming SIMD Extension Single-precision Floating-point InstructionsC-15
General Purpose InstructionsC-17
Pointer-Chasing Variability of Software Measurable Latency of L1 Data Cache LatencyC-20
Instruction Latency/Throughput Summary of Intel® Atom™ MicroarchitectureD-7
Intel® Atom™ Microarchitecture Instructions Latency DataD-14
CHAPTER 1
INTRODUCTION
The Intel® 64 and IA-32 Architectures Optimization Reference Manual describes how to optimize software to take advantage of the performance characteristics of IA-32 and Intel 64 architecture processors.
Optimizations described in this manual apply to processors based on the Intel® Core™ microarchitecture, Enhanced Intel® Core™ microarchitecture, Intel® microarchitecture code name Nehalem, Intel®
microarchitecture code name Westmere, Intel® microarchitecture code name Sandy Bridge, Intel®
microarchitecture code name Ivy Bridge, Intel® microarchitecture code name Haswell, Intel NetBurst®
microarchitecture, the Intel® Core™ Duo, Intel® Core™ Solo, Pentium® M processor families.
The target audience for this manual includes software programmers and compiler writers. This manual
assumes that the reader is familiar with the basics of the IA-32 architecture and has access to the Intel®
64 and IA-32 Architectures Software Developer’s Manual (five volumes). A detailed understanding of Intel
64 and IA-32 processors is often required. In many cases, knowledge of the underlying microarchitectures is required.
The design guidelines that are discussed in this manual for developing highperformance software generally apply to current as well as to future IA-32 and Intel 64 processors. The
coding rules and code optimization techniques listed target the Intel Core microarchitecture, the Intel
NetBurst microarchitecture and the Pentium M processor microarchitecture. In most cases, coding rules
apply to software running in 64-bit mode of Intel 64 architecture, compatibility mode of Intel 64 architecture, and IA-32 modes (IA-32 modes are supported in IA-32 and Intel 64 architectures). Coding rules
specific to 64-bit modes are noted separately.
1.1
TUNING YOUR APPLICATION
Tuning an application for high performance on any Intel 64 or IA-32 processor requires understanding
and basic skills in:
•
•
•
•
•
Intel 64 and IA-32 architecture.
C and Assembly language.
Hot-spot regions in the application that have impact on performance.
Optimization capabilities of the compiler.
Techniques used to evaluate application performance.
The Intel® VTune™ Performance Analyzer can help you analyze and locate hot-spot regions in your applications. On the Intel® Core™ i7, Intel® Core™2 Duo, Intel® Core™ Duo, Intel® Core™ Solo, Pentium®
4, Intel® Xeon® and Pentium® M processors, this tool can monitor an application through a selection of
performance monitoring events and analyze the performance event data that is gathered during code
execution.
This manual also describes information that can be gathered using the performance counters through
Pentium 4 processor’s performance monitoring events.
1.2
ABOUT THIS MANUAL
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200 and 7300 series, Intel® Pentium® dual-core,
Intel® Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel®
Core™ microarchitecture. In this document, references to the Core 2 Duo processor refer to processors
based on the Intel® Core™ microarchitecture.
The Intel® Xeon® processor 3100, 3300, 5200, 5400, 7400 series, Intel® Core™2 Quad processor
Q8000 series, and Intel® Core™2 Extreme processors QX9000 series are based on 45 nm Enhanced
Intel® Core™microarchitecture.
INTRODUCTION
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm
Intel® microarchitecture code name Nehalem. Intel® microarchitecture code name Westmere is a 32 nm
version of Intel® microarchitecture code name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon
processor E7 and various Intel Core i7, i5, i3 processors are based on Intel® microarchitecture code
name Westmere.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor
E7-8800/4800/2800 product families, Intel® CoreTM i7-3930K processor, and 2nd generation Intel®
CoreTM i7-2xxx, Intel® CoreTM i5-2xxx, Intel® CoreTM i3-2xxx processor series are based on the Intel®
microarchitecture code name Sandy Bridge.
The 3rd generation Intel® Core™ processors and the Intel Xeon processor E3-1200 v2 product family are
based on Intel® microarchitecture code name Ivy Bridge. The Intel® Xeon® processor E5 v2 and E7 v2
families are based on the Ivy Bridge-E microarchitecture, support Intel 64 architecture and multiple
physical processor packages in a platform.
The 4th generation Intel® Core™ processors and the Intel® Xeon® processor E3-1200 v3 product family
are based on Intel® microarchitecture code name Haswell. The Intel® Xeon® processor E5 26xx v3
family is based on the Haswell-E microarchitecture, supports Intel 64 architecture and multiple physical
processor packages in a platform.
The Intel® Core™ M processor family and 5th generation Intel® Core™ processors are based on the
Intel® microarchitecture code name Broadwell and support Intel 64 architecture.
The 6th generation Intel® Core™ processors are based on the Intel® microarchitecture code name
Skylake and support Intel 64 architecture.
In this document, references to the Pentium 4 processor refer to processors based on the Intel NetBurst®
microarchitecture. This includes the Intel Pentium 4 processor and many Intel Xeon processors based on
Intel NetBurst microarchitecture. Where appropriate, differences are noted (for example, some Intel
Xeon processors have third level cache).
The Dual-core Intel® Xeon® processor LV is based on the same architecture as Intel® Core™ Duo and
Intel® Core™ Solo processors.
Intel® Atom™ processor is based on Intel® Atom™ microarchitecture.
The following bullets summarize chapters in this manual.
•
•
Chapter 1: Introduction — Defines the purpose and outlines the contents of this manual.
Chapter 2: Intel® 64 and IA-32 Processor Architectures — Describes the microarchitecture of
recent IA-32 and Intel 64 processor families, and other features relevant to software optimization.
•
Chapter 3: General Optimization Guidelines — Describes general code development and optimization techniques that apply to all applications designed to take advantage of the common features
of the Intel Core microarchitecture, Enhanced Intel Core microarchitecture, Intel NetBurst microarchitecture and Pentium M processor microarchitecture.
•
Chapter 4: Coding for SIMD Architectures — Describes techniques and concepts for using the
SIMD integer and SIMD floating-point instructions provided by the MMX™ technology, Streaming
SIMD Extensions, Streaming SIMD Extensions 2, Streaming SIMD Extensions 3, SSSE3, and SSE4.1.
•
Chapter 5: Optimizing for SIMD Integer Applications — Provides optimization suggestions and
common building blocks for applications that use the 128-bit SIMD integer instructions.
•
Chapter 6: Optimizing for SIMD Floating-point Applications — Provides optimization
suggestions and common building blocks for applications that use the single-precision and doubleprecision SIMD floating-point instructions.
•
Chapter 7: Optimizing Cache Usage — Describes how to use the PREFETCH instruction, cache
control management instructions to optimize cache usage, and the deterministic cache parameters.
•
Chapter 8: Introducing sub-numa clustering — Describes Sub-NUMA Clustering (SNC), a mode
for improving average latency from last level cache (LLC) to local memory.
•
Chapter 9: Multicore and Hyper-Threading Technology — Describes guidelines and techniques
for optimizing multithreaded applications to achieve optimal performance scaling. Use these when
1-2
INTRODUCTION
targeting multicore processor, processors supporting Hyper-Threading Technology, or multiprocessor
(MP) systems.
•
Chapter 10: 64-Bit Mode Coding Guidelines — This chapter describes a set of additional coding
guidelines for application software written to run in 64-bit mode.
•
Chapter 11: SSE4.2 and SIMD Programming for Text-Processing/Lexing/Parsing—
Describes SIMD techniques of using SSE4.2 along with other instruction extensions to improve
text/string processing and lexing/parsing applications.
•
Chapter 12: Optimizations for Intel® AVX, FMA and AVX2— Provides optimization suggestions
and common building blocks for applications that use Intel® Advanced Vector Extensions, FMA, and
AVX2.
•
Chapter 13: Optimizations for Intel® AVX-512— Provides optimization suggestions and
common building blocks for applications that use Intel® Advanced Vector Extensions 512.
•
Chapter 14: Intel Transactional Synchronization Extensions — Tuning recommendations to
use lock elision techniques with Intel Transactional Synchronization Extensions to optimize multithreaded software with contended locks.
•
Chapter 15: Power Optimization for Mobile Usages — This chapter provides background on
power saving techniques in mobile processors and makes recommendations that developers can
leverage to provide longer battery life.
•
Chapter 16: Silvermont Microarchitecture and Software Optimization — Describes the microarchitecture of processor families based on the Silvermont microarchitecture, and software optimization techniques targeting Intel processors based on the Silvermont microarchitecture.
•
Chapter 17: Knights Landing Microarchitecture and Software Optimization — Describes the
microarchitecture of processor families based on the Silvermont Knights Landing microarchitecture,
and software optimization techniques targeting Intel processors based on the Knights Landing microarchitecture.
•
Appendix A: Application Performance Tools — Introduces tools for analyzing and enhancing
application performance without having to write assembly code.
•
Appendix B: Using Performance Monitoring Events — Provides information on the Top-Down
Analysis Method and information on how to use performance events specific to the Intel Xeon
processor 5500 series, processors based on Intel microarchitecture code name Sandy Bridge, and
Intel Core Solo and Intel Core Duo processors.
•
Appendix C: IA-32 Instruction Latency and Throughput — Provides latency and throughput
data for the IA-32 instructions. Instruction timing data specific to recent processor families are
provided.
•
Appendix D: Intel® Atom™ Microarchitecture and Software Optimization — Describes the
microarchitecture of processor families based on Intel Atom microarchitecture, and software optimization techniques targeting Intel Atom microarchitecture.
1.3
RELATED INFORMATION
For more information on the Intel® architecture, techniques, and the processor architecture terminology,
the following are of particular interest:
•
•
•
•
•
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual
Developing Multi-threaded Applications: A Platform Consistent Approach
Intel® C++ Compiler documentation and online help
Intel® Fortran Compiler documentation and online help
Intel® VTune™ Amplifier documentation and online help
Using Spin-Loops on Intel Pentium 4 Processor and Intel Xeon Processor MP
1-3
INTRODUCTION
More relevant links are:
•
Developer Zone:
https://software.intel.com/en-us/all-dev-areas
•
Processor support general link:
https://www.intel.com/content/www/us/en/products/processors.html
•
Intel Multi-Core Technology:
https://software.intel.com/en-us/articles/multi-core-introduction
•
Hyper-Threading Technology (HT Technology):
http://www.intel.com/content/www/us/en/architecture-and-technology/hyper-threading/hyperthreading-technology.html
•
SSE4.1 Application Note: Motion Estimation with Intel® Streaming SIMD Extensions 4:
https://software.intel.com/en-us/articles/motion-estimation-with-intel-streaming-simd-extensions4-intel-sse4
•
Intel® SSE4 Programming Reference:
https://software.intel.com/sites/default/files/m/8/b/8/D9156103.pdf
•
Intel® 64 Architecture Processor Topology Enumeration:
https://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration
•
Multi-buffering techniques using SIMD extensions:
http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/communicationsia-multi-buffer-paper.pdf
•
Parallel hashing using Multi-buffering techniques:
http://www.scirp.org/journal/PaperInformation.aspx?paperID=23995
http://eprint.iacr.org/2012/476.pdf
•
PCMMULQDQ resources:
https://software.intel.com/en-us/articles/intel-carry-less-multiplication-instruction-and-its-usagefor-computing-the-gcm-mode
•
Modular exponentiation using redundant representation and AVX2:
http://rd.springer.com/chapter/10.1007%2F978-3-642-31662-3_9?LI=true
1-4
CHAPTER 2
INTEL 64 AND IA-32 PROCESSOR ARCHITECTURES
®
This chapter gives an overview of features relevant to software optimization for current generations of
Intel 64 and IA-32 processors (processors based on Intel® microarchitecture code name Skylake Server,
Intel® microarchitecture code name Skylake, Intel® microarchitecture code name Broadwell, Intel®
microarchitecture code name Haswell, Intel microarchitecture code name Ivy Bridge, Intel microarchitecture code name Sandy Bridge, processors based on the Intel Core microarchitecture, Enhanced Intel
Core microarchitecture, Intel microarchitecture code name Nehalem). These features are:
•
Microarchitectures that enable executing instructions with high throughput at high clock rates, a high
speed cache hierarchy and high speed system bus.
•
•
•
•
Multicore architecture available across Intel Core processor and Intel Xeon processor families.
•
•
•
•
•
•
Intel® Advanced Vector Extensions (Intel® AVX).
Hyper-Threading Technology1 (HT Technology) support.
Intel 64 architecture on Intel 64 processors.
SIMD instruction extensions: MMX technology, Streaming SIMD Extensions (SSE), Streaming SIMD
Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), Supplemental Streaming SIMD
Extensions 3 (SSSE3), SSE4.1, and SSE4.2.
Half-precision floating-point conversion and RDRAND.
Fused Multiply Add Extensions.
Intel® Advanced Vector Extensions 2 (Intel® AVX2).
ADX and RDSEED.
Intel® Advanced Vector Extensions 512 (Intel® AVX-512).
The Intel Core 2, Intel Core 2 Extreme, Intel Core 2 Quad processor family, Intel Xeon processor 3000,
3200, 5100, 5300, 7300 series are based on the high-performance and power-efficient Intel Core
microarchitecture. Intel Xeon processor 3100, 3300, 5200, 5400, 7400 series, Intel Core 2 Extreme
processor QX9600, QX9700 series, Intel Core 2 Quad Q9000 series, Q8000 series are based on the
enhanced Intel Core microarchitecture. Intel Core i7 processor is based on Intel microarchitecture code
name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and Intel Core i7, i5, i3
processors are based on Intel microarchitecture code name Westmere.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor
E7-8800/4800/2800 product families, Intel® CoreTM i7-3930K processor, and 2nd generation Intel®
Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Intel®
microarchitecture code name Sandy Bridge.
The Intel® Xeon® processor E3-1200 v2 product family and the 3rd generation Intel® Core™ processors
are based on the Ivy Bridge microarchitecture and support Intel 64 architecture. The Intel® Xeon®
processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture, support Intel 64
architecture and multiple physical processor packages in a platform.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are
based on the Haswell microarchitecture and support Intel 64 architecture. The Intel® Xeon® processor
E5 26xx v3 family is based on the Haswell-E microarchitecture, supports Intel 64 architecture and
multiple physical processor packages in a platform.
Intel® Core™ M processors, 5th generation Intel Core processors and Intel Xeon processor E3-1200 v4
series are based on the Broadwell microarchitecture and support Intel 64 architecture.
1. Hyper-Threading Technology requires a computer system with an Intel processor supporting HT Technology and an HT
Technology enabled chipset, BIOS and operating system. Performance varies depending on the hardware and software
used.
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The 6th generation Intel Core processors, Intel Xeon processor E3-1500m v5 are based on the Skylake
microarchitecture and support Intel 64 architecture.
The Intel® Xeon® Processor Scalable Family is based on the Skylake Server microarchitecture and
supports Intel 64 architecture.
2.1
THE SKYLAKE SERVER MICROARCHITECTURE
®
The Intel Xeon® Processor Scalable Family is based on the Skylake Server microarchitecture. Processors based on the Skylake microarchitecture can be identified using CPUID’s DisplayFamily_DisplayModel
signature, which can be found in Table 2-1 of CHAPTER 2 of Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 4.
The Skylake Server microarchitecture introduces the following new features2 that allow you to optimize
your application for performance and power consumption.
•
A new core based on the Skylake Server microarchitecture with process improvements based on the
Kaby Lake microarchitecture.
•
•
•
•
•
•
•
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) support.
More cores per socket (max 28 vs. max 22).
6 memory channels per socket in Skylake microarchitecture vs. 4 in the Broadwell microarchitecture.
Bigger L2 cache, smaller non inclusive L3 cache.
Intel® Optane™ support.
Intel® Omni-Path Architecture (Intel® OPA).
Sub-NUMA Clustering (SNC) support.
The green stars in Figure 2-1 represent new features in Skylake Server microarchitecture compared to
Skylake microarchitecture for client; a 1MB L2 cache and an additional Intel AVX-512 FMA unit on port 5
which is available on some parts.
Since port 0 and port 1 are 256-bits wide, Intel AVX-512 operations that will be dispatched to port 0 will
execute on both port 0 and port 1; however, other operations such as lea can still execute on port 1 in
parallel. See the red block in Figure 2-3 for the fusion of ports 0 and 1.
Notice that, unlike Skylake microarchitecture for client, the Skylake Server microarchitecture has its
front end loop stream detector (LSD) disabled.
2. Some features may not be available on all products.
2-2
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Figure 2-1. Processor Core Pipeline Functionality of the Skylake Server Microarchitecture
2.1.1
Skylake Server Microarchitecture Cache
The Intel Xeon Processor Scalable Family based on Skylake Server microarchitecture has significant
changes in core and uncore architecture to improve performance and scalability of several components
compared with the previous generation of the Intel Xeon processor family based on Broadwell microarchitecture.
2.1.1.1
Larger Mid-Level Cache
Skylake Server microarchitecture implements a mid-level (L2) cache of 1 MB capacity with a minimum
load-to-use latency of 14 cycles. The mid-level cache capacity is four times larger than the capacity in
previous Intel Xeon processor family implementations. The line size of the mid-level cache is 64B and it
is 16-way associative. The mid-level cache is private to each core.
Software that has been optimized to place data in mid-level cache may have to be revised to take advantage of the larger mid-level cache available in Skylake Server microarchitecture.
2.1.1.2
Non-Inclusive Last Level Cache
The last level cache (LLC) in Skylake is a non-inclusive, distributed, shared cache. The size of each of the
banks of last level cache has shrunk to 1.375 MB per bank. Because of the non-inclusive nature of the last
level cache, blocks that are present in the mid-level cache of one of the cores may not have a copy resi2-3
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
dent in a bank of last level cache. Based on the access pattern, size of the code and data accessed, and
sharing behavior between cores for a cache block, the last level cache may appear as a victim cache of
the mid-level cache and the aggregate cache capacity per core may appear to be a combination of the
private mid-level cache per core and a portion of the last level cache.
2.1.1.3
Skylake Server Microarchitecture Cache Recommendations
A high-level comparison between Skylake Server microarchitecture cache and the previous generation
Broadwell microarchitecture cache is available in the table below.
Table 2-1. Cache Comparison Between Skylake Microarchitecture and Broadwell Microarchitecture
Cache level
Category
Broadwell
Microarchitecture
Skylake Server
Microarchitecture
L1 Data Cache
Unit (DCU)
Size [KB]
32
32
Latency [cycles]
4-6
4-6
Max bandwidth [bytes/cycles]
96
192
Sustained bandwidth [bytes/cycles]
93
133
Associativity [ways]
8
8
256
1024 (1MB)
12
14
Max bandwidth [bytes/cycles]
32
64
Sustained bandwidth [bytes/cycles]
25
52
Associativity [ways]
8
16
Size [MB]
Up to 2.5 per core
up to 1.3751 per core
Latency [cycles]
50-60
50-70
Max bandwidth [bytes/cycles]
16
16
Sustained bandwidth [bytes/cycles]
14
15
L2 Mid-level Cache Size [KB]
(MLC)
Latency [cycles]
L3 Last-level
Cache (LLC)
NOTES:
1. Some Skylake Server parts have some cores disabled and hence have more than 1.375 MB per core of L3 cache.
The figure below shows how Skylake Server microarchitecture shifts the memory balance from shareddistributed with high latency, to private-local with low latency.
2-4
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Figure 2-2. Broadwell Microarchitecture and Skylake Server Microarchitecture Cache Structures
The potential performance benefit from the cache changes is high, but software will need to adapt its
memory tiling strategy to be optimal for the new cache sizes.
Recommendation: Rebalance application shared and private data sizes to match the smaller, noninclusive L3 cache, and larger L2 cache.
Choice of cache blocking should be based on application bandwidth requirements and changes from one
application to another. Having four times the L2 cache size and twice the L2 cache bandwidth compared
to the previous generation Broadwell microarchitecture enables some applications to block to L2 instead
of L1 and thereby improves performance.
Recommendation: Consider blocking to L2 on Skylake Server microarchitecture if L2 can sustain the
application’s bandwidth requirements.
The change from inclusive last level cache to non-inclusive means that the capacity of mid-level and last
level cache can now be added together. Programs that determine cache capacity per core at run time
should now use a combination of mid-level cache size and last level cache size per core to estimate the
effective cache size per core. Using just the last level cache size per core may result in non-optimal use
of available on-chip cache; see Section 2.1.2 for details.
Recommendation: In case of no data sharing, applications should consider cache capacity per core as
L2 and L3 cache sizes and not only L3 cache size.
2.1.2
Non-Temporal Stores on Skylake Server Microarchitecture
Because of the change in the size of each bank of last level cache on Skylake Server microarchitecture, if
an application, library, or driver only considers the last level cache to determine the size of on-chip cacheper-core, it may see a reduction with Skylake Server microarchitecture and may use non-temporal store
with smaller blocks of memory writes. Since non-temporal stores evict cache lines back to memory, this
may result in an increase in the number of subsequent cache misses and memory bandwidth demands
on Skylake Server microarchitecture, compared to the previous Intel Xeon processor family.
Also, because of a change in the handling of accesses resulting from non-temporal stores by Skylake
Server microarchitecture, the resources within each core remain busy for a longer duration compared to
similar accesses on the previous Intel Xeon processor family. As a result, if a series of such instructions
are executed, there is a potential that the processor may run out of resources and stall, thus limiting the
memory write bandwidth from each core.
2-5
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The increase in cache misses due to overuse of non-temporal stores and the limit on the memory write
bandwidth per core for non-temporal stores may result in reduced performance for some applications.
To avoid the performance condition described above with Skylake Server microarchitecture, include midlevel cache capacity per core in addition to the last level cache per core for applications, libraries, or
drivers that determine the on-chip cache available with each core. Doing so optimizes the available onchip cache capacity on Skylake Server microarchitecture as intended, with its non-inclusive last level
cache implementation.
2.2
THE SKYLAKE MICROARCHITECTURE
The Skylake microarchitecture builds on the successes of the Haswell and Broadwell microarchitectures.
The basic pipeline functionality of the Skylake microarchitecture is depicted in Figure 2-3.
32K L1 Instruction
Cache
BPU
Decoded Icache
(DSB)
MSROM
4 uops/cycle
Legacy Decode
Pipeline
5 uops/cycle
6 uops/cycle
Instruction Decode Queue (IDQ,, or micro-op queue)
Allocate/Rename/Retire/MoveElimination/ZeroIdiom
Scheduler
Port 0
Int ALU,
Vec FMA,
Vec MUL,
Vec Add,
Vec ALU,
Vec Shft,
Divide,
Branch2
Port 1
Int ALU,
Fast LEA,
Vec FMA,
Vec MUL,
Vec Add,
Vec ALU,
Vec Shft,
Int MUL,
Slow LEA
Port 5
Int ALU,
Fast LEA,
Vec SHUF,
Vec ALU,
CVT
Port 6
Int ALU,
Int Shft,
Branch1,
Port 2
LD/STA
256K L2 Cache
(Unified)
Port 3
LD/STA
Port 4
STD
32K L1 Data Cache
Port 7
STA
Figure 2-3. CPU Core Pipeline Functionality of the Skylake Microarchitecture
The Skylake microarchitecture offers the following enhancements:
•
•
•
•
•
•
2-6
Larger internal buffers to enable deeper OOO execution and higher cache bandwidth.
Improved front end throughput.
Improved branch predictor.
Improved divider throughput and latency.
Lower power consumption.
Improved SMT performance with Hyper-Threading Technology.
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
Balanced floating-point ADD, MUL, FMA throughput and latency.
The microarchitecture supports flexible integration of multiple processor cores with a shared uncore subsystem consisting of a number of components including a ring interconnect to multiple slices of L3 (an
off-die L4 is optional), processor graphics, integrated memory controller, interconnect fabrics, etc. A
four-core configuration can be supported similar to the arrangement shown in Figure 2-5.
2.2.1
The Front End
The front end in the Skylake microarchitecture provides the following improvements over previous
generation microarchitectures:
•
Legacy Decode Pipeline delivery of 5 uops per cycle to the IDQ compared to 4 uops in previous generations.
•
•
The DSB delivers 6 uops per cycle to the IDQ compared to 4 uops in previous generations.
•
The LSD in the IDQ can detect loops up to 64 uops per logical processor irrespective ST or SMT
operation.
•
Improved Branch Predictor.
The IDQ can hold 64 uops per logical processor vs. 28 uops per logical processor in previous
generations when two sibling logical processors in the same core are active (2x64 vs. 2x28 per core).
If only one logical processor is active in the core, the IDQ can hold 64 uops (64 vs. 56 uops in ST
operation).
2.2.2
The Out-of-Order Execution Engine
The Out of Order and execution engine changes in Skylake microarchitecture include:
•
•
•
•
Larger buffers enable deeper OOO execution compared to previous generations.
Improved throughput and latency for divide/sqrt and approximate reciprocals.
Identical latency and throughput for all operations running on FMA units.
Longer pause latency enables better power efficiency and better SMT performance resource utilization.
Table 2-2 summarizes the OOO engine’s capability to dispatch different types of operations to various
ports.
Table 2-2. Dispatch Port and Execution Stacks of the Skylake Microarchitecture
Port 0
Port 1
Port 2, 3
ALU,
ALU,
LD
Vec ALU
Fast LEA,
STA
Port 4
STD
Port 5
Port 6
ALU,
ALU,
Fast LEA,
Shft,
Vec ALU
Vec ALU,
Vec Shft,
Vec Shft,
Vec Shuffle,
Vec Add,
Vec Add,
Vec Mul,
Vec Mul,
FMA,
FMA
DIV,
Slow Int
Branch2
Slow LEA
Port 7
STA
Branch1
2-7
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-3 lists execution units and common representative instructions that rely on these units.
Throughput improvements across the SSE, AVX and general-purpose instruction sets are related to the
number of units for the respective operations, and the varieties of instructions that execute using a
particular unit.
Table 2-3. Skylake Microarchitecture Execution Units and Representative Instructions1
Execution
Unit
# of
Unit
Instructions
ALU
4
add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa, (v)movap*, (v)movup*
SHFT
2
sal, shl, rol, adc, sarx, adcx, adox, etc.
Slow Int
1
mul, imul, bsr, rcl, shld, mulx, pdep, etc.
BM
2
andn, bextr, blsi, blsmsk, bzhi, etc
Vec ALU
3
(v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)movap*, (v)movup*,
(v)andp*, (v)orp*, (v)paddb/w/d/q, (v)blendv*, (v)blendp*, (v)pblendd
Vec_Shft
2
(v)psllv*, (v)psrlv*, vector shift count in imm8
Vec Add
2
(v)addp*, (v)cmpp*, (v)max*, (v)min*, (v)padds*, (v)paddus*, (v)psign, (v)pabs, (v)pavgb,
(v)pcmpeq*, (v)pmax, (v)cvtps2dq, (v)cvtdq2ps, (v)cvtsd2si, (v)cvtss2si
Shuffle
1
(v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*,
vbroadcast*, (v)pslldq, (v)psrldq, (v)pblendw
Vec Mul
2
(v)mul*, (v)pmul*, (v)pmadd*,
SIMD Misc
1
STTNI, (v)pclmulqdq, (v)psadw, vector shift count in xmm,
FP Mov
1
(v)movsd/ss, (v)movd gpr,
DIVIDE
1
divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
NOTES:
1. Execution unit mapping to MMX instructions are not covered in this table. See Section 12.16.5 on MMX instruction
throughput remedy.
A significant portion of the SSE, AVX and general-purpose instructions also have latency improvements.
Appendix C lists the specific details. Software-visible latency exposure of an instruction sometimes may
include additional contributions that depend on the relationship between micro-ops flows of the producer
instruction and the micro-op flows of the ensuing consumer instruction. For example, a two-uop instruction like VPMULLD may experience two cumulative bypass delays of 1 cycle each from each of the two
micro-ops of VPMULLD.
Table 2-4 describes the bypass delay in cycles between a producer uop and the consumer uop. The leftmost column lists a variety of situations characteristic of the producer micro-op. The top row lists a
variety of situations characteristic of the consumer micro-op.
2-8
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-4. Bypass Delay Between Producer and Consumer Micro-ops
SIMD/0,1/
1
FMA/0,1/
4
VIMUL/0,1/
4
SIMD/5/1,3
SHUF/5/1,
3
V2I/0/3
I2V/5/1
SIMD/0,1/1
0
1
1
0
0
0
NA
FMA/0,1/4
1
0
1
0
0
0
NA
VIMUL/0,1/4
1
0
1
0
0
0
NA
SIMD/5/1,3
0
1
1
0
0
0
NA
SHUF/5/1,3
0
0
1
0
0
0
NA
V2I/0/3
NA
NA
NA
NA
NA
NA
NA
I2V/5/1
0
0
1
0
0
0
NA
The attributes that are relevant to the producer/consumer micro-ops for bypass are a triplet of abbreviation/one or more port number/latency cycle of the uop. For example:
•
•
•
“SIMD/0,1/1” applies to 1-cycle vector SIMD uop dispatched to either port 0 or port 1.
“VIMUL/0,1/4” applies to 4-cycle vector integer multiply uop dispatched to either port 0 or port 1.
“SIMD/5/1,3” applies to either 1-cycle or 3-cycle non-shuffle uop dispatched to port 5.
2.2.3
Cache and Memory Subsystem
The cache hierarchy of the Skylake microarchitecture has the following enhancements:
•
•
•
Higher Cache bandwidth compared to previous generations.
•
•
•
Page split load penalty down from 100 cycles in previous generation to 5 cycles.
•
•
Reduced performance penalty for a software prefetch that specifies a NULL pointer.
Simultaneous handling of more loads and stores enabled by enlarged buffers.
Processor can do two page walks in parallel compared to one in Haswell microarchitecture and earlier
generations.
L3 write bandwidth increased from 4 cycles per line in previous generation to 2 per line.
Support for the CLFLUSHOPT instruction to flush cache lines and manage memory ordering of flushed
data using SFENCE.
L2 associativity changed from 8 ways to 4 ways.
2-9
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-5. Cache Parameters of the Skylake Microarchitecture
Level
Capacity /
Associativity
Line Size
(bytes)
Fastest
Latency1
Peak Bandwidth
(bytes/cyc)
Sustained Bandwidth
(bytes/cyc)
Update
Policy
First Level Data
32 KB/ 8
64
4 cycle
96 (2x32B Load +
1*32B Store)
~81
Writeback
Instruction
32 KB/8
64
N/A
N/A
N/A
N/A
Second Level
256KB/4
64
12 cycle
64
~29
Writeback
64
44
32
~18
Writeback
Third Level
(Shared L3)
Up to 2MB
per core/Up
to 16 ways
NOTES:
1. Software-visible latency will vary depending on access patterns and other factors.
The TLB hierarchy consists of dedicated level one TLB for instruction cache, TLB for L1D, plus unified TLB
for L2. The partition column of Table 2-6 indicates the resource sharing policy when Hyper-Threading
Technology is active.
Table 2-6. TLB Parameters of the Skylake Microarchitecture
Level
Page Size
Entries
Associativity
Partition
Instruction
4KB
128
8 ways
dynamic
Instruction
2MB/4MB
8 per thread
First Level Data
4KB
64
4
fixed
First Level Data
2MB/4MB
32
4
fixed
First Level Data
1GB
4
4
fixed
Second Level
Shared by 4KB and 2/4MB pages
1536
12
fixed
Second Level
1GB
16
4
fixed
2.2.4
fixed
Pause Latency in Skylake Microarchitecture
The PAUSE instruction is typically used with software threads executing on two logical processors located
in the same processor core, waiting for a lock to be released. Such short wait loops tend to last between
tens and a few hundreds of cycles, so performance-wise it is better to wait while occupying the CPU than
yielding to the OS. When the wait loop is expected to last for thousands of cycles or more, it is preferable
to yield to the operating system by calling an OS synchronization API function, such as WaitForSingleObject on Windows* OS or futex on Linux.
The PAUSE instruction is intended to:
•
Temporarily provide the sibling logical processor (ready to make forward progress exiting the spin
loop) with competitively shared hardware resources. The competitively-shared microarchitectural
resources that the sibling logical processor can utilize in the Skylake microarchitecture are listed
below.
— Front end slots in the Decode ICache, LSD and IDQ.
— Execution slots in the RS.
•
Save power consumed by the processor core compared with executing equivalent spin loop
instruction sequence in the following configurations.
— One logical processor is inactive (e.g., entering a C-state).
— Both logical processors in the same core execute the PAUSE instruction.
2-10
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
— HT is disabled (e.g. using BIOS options).
The latency of the PAUSE instruction in prior generation microarchitectures is about 10 cycles, whereas
in Skylake microarchitecture it has been extended to as many as 140 cycles.
The increased latency (allowing more effective utilization of competitively-shared microarchitectural
resources to the logical processor ready to make forward progress) has a small positive performance
impact of 1-2% on highly threaded applications. It is expected to have negligible impact on less threaded
applications if forward progress is not blocked executing a fixed number of looped PAUSE instructions.
There's also a small power benefit in 2-core and 4-core systems.
As the PAUSE latency has been increased significantly, workloads that are sensitive to PAUSE latency will
suffer some performance loss.
The following is an example of how to use the PAUSE instruction with a dynamic loop iteration count.
Notice that in the Skylake microarchitecture the RDTSC instruction counts at the machine's guaranteed
P1 frequency independently of the current processor clock (see the INVARIANT TSC property), and
therefore, when running in Intel® Turbo-Boost-enabled mode, the delay will remain constant, but the
number of instructions that could have been executed will change.
Use PollDelay function in your lock to wait a given amount of guaranteed P1 frequency cycles, specified
in the “clocks” variable.
Example 2-1. Dynamic Pause Loop Example
#include <x86intrin.h>
#include <stdint.h>
/* A useful predicate for dealing with timestamps that may wrap.
Is a before b? Since the timestamps may wrap, this is asking whether it's
shorter to go clockwise from a to b around the clock-face, or anti-clockwise.
Times where going clockwise is less distance than going anti-clockwise
are in the future, others are in the past. e.g. a = MAX-1, b = MAX+1 (=0),
then a > b (true) does not mean a reached b; whereas signed(a) = -2,
signed(b) = 0 captures the actual difference */
static inline bool before(uint64_t a, uint64_t b)
{
return ((int64_t)b - (int64_t)a) > 0;
}
void pollDelay(uint32_t clocks)
{
uint64_t endTime = _rdtsc()+ clocks;
for (; before(_rdtsc(), endTime); )
_mm_pause();
}
For contended spinlocks of the form shown in the baseline example below, we recommend an exponential back off when the lock is found to be busy, as shown in the improved example, to avoid significant
performance degradation that can be caused by conflicts between threads in the machine. This is more
important as we increase the number of threads in the machine and make changes to the architecture
that might aggravate these conflict conditions. In multi-socket Intel server processors with shared
memory, conflicts across threads take much longer to resolve as the number of threads contending for
the same lock increases. The exponential back off is designed to avoid these conflicts between the
threads thus avoiding the potential performance degradation. Note that in the example below, the
2-11
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
number of PAUSE instructions are increased by a factor of 2 until some MAX_BACKOFF is reached which
is subject to tuning.
Example 2-2. Contended Locks with Increasing Back-off Example
/*******************/
/*Baseline Version */
/*******************/
// atomic {if (lock == free) then change lock state to busy}
while (cmpxchg(lock, free, busy) == fail)
{
while (lock == busy)
{
__asm__ ("pause");
}
}
/*******************/
/*Improved Version */
/*******************/
int mask = 1;
int const max = 64; //MAX_BACKOFF
while (cmpxchg(lock, free, busy) == fail)
{
while (lock == busy)
{
for (int i=mask; i; --i){
__asm__ ("pause");
}
mask = mask < max ? mask<<1 : max;
}
}
2.3
HASWELL MICROARCHITECTURE
The Haswell microarchitecture builds on the successes of the Sandy Bridge and Ivy Bridge microarchitectures. The basic pipeline functionality of the Haswell microarchitecture is depicted in Figure 2-4. In
general, most of the features described in Section 2.3.1 - Section 2.3.4 also apply to the Broadwell
microarchitecture. Enhancements of the Broadwell microarchitecture are summarized in Section 2.3.6.
2-12
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
32K L1 Instruction Cache
Pre-Decode
MSROM
Instruction Queue
Decoder
IDQ
BPU
Uop Cache (DSB)
Load Buffers, Store
Buffers, Reorder Buffers
Allocate/Rename/Retire/
MoveElimination/ZeroIdiom
Scheduler
Port 0
ALU,
SHFT,
VEC LOG,
VEC SHFT,
FP mul,
FMA,
DIV,
STTNI,
Branch2
Port 1
Port 5
ALU,
Fast LEA,
VEC ALU,
VEC LOG,
FP mul,
FMA,
FP add,
Slow Int
ALU,
Fast LEA,
VEC ALU,
VEC LOG,
VEC SHUF,
Port 6
Port 4
Port 2
Port 3
Port 7
ALU, Shft
STD
LD/STA
LD/STA
STA
Primary
Branch
Memory Control
32K L1 Data Cache
Line Fill Buffers
256K L2 Cache (Unified)
Figure 2-4. CPU Core Pipeline Functionality of the Haswell Microarchitecture
The Haswell microarchitecture offers the following innovative features:
•
•
•
•
•
•
•
•
•
•
•
•
Support for Intel Advanced Vector Extensions 2 (Intel AVX2), FMA.
Support for general-purpose, new instructions to accelerate integer numeric encryption.
Support for Intel® Transactional Synchronization Extensions (Intel® TSX).
Each core can dispatch up to 8 micro-ops per cycle.
256-bit data path for memory operation, FMA, AVX floating-point and AVX2 integer execution units.
Improved L1D and L2 cache bandwidth.
Two FMA execution pipelines.
Four arithmetic logical units (ALUs).
Three store address ports.
Two branch execution units.
Advanced power management features for IA processor core and uncore sub-systems.
Support for optional fourth level cache.
The microarchitecture supports flexible integration of multiple processor cores with a shared uncore subsystem consisting of a number of components including a ring interconnect to multiple slices of L3 (an
off-die L4 is optional), processor graphics, integrated memory controller, interconnect fabrics, etc. An
example of the system integration view of four CPU cores with uncore components is illustrated in
Figure 2-5.
2-13
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
PCIe
Disp
Eng
DMI
PEG
DMI
DRAM
PCIe
Brdg
IMc
System Agent
CPU Core
L3 Slice
CPU Core
L3 Slice
CPU Core
L3 Slice
CPU Core
L3 Slice
Legend:
Uncore
CPU Core
Processor Graphics/
Media Engine
Figure 2-5. Four Core System Integration of the Haswell Microarchitecture
2.3.1
The Front End
The front end of Intel microarchitecture code name Haswell builds on that of Intel microarchitecture code
name Sandy Bridge and Intel microarchitecture code name Ivy Bridge, see Section 2.4.2 and Section
2.4.7. Additional enhancements in the front end include:
•
•
The uop cache (or decoded ICache) is partitioned equally between two logical processors.
•
The LSD in the micro-op queue (or IDQ) can detect small loops up to 56 micro-ops. The 56-entry
micro-op queue is shared by two logical processors if Hyper-Threading Technology is active (Intel
microarchitecture Sandy Bridge provides duplicated 28-entry micro-op queue in each core).
The instruction decoders will alternate between each active logical processor. If one sibling logical
processor is idle, the active logical processor will use the decoders continuously.
2.3.2
The Out-of-Order Engine
The key components and significant improvements to the out-of-order engine are summarized below:
Renamer: The Renamer moves micro-ops from the micro-op queue to bind to the dispatch ports in the
Scheduler with execution resources. Zero-idiom, one-idiom and zero-latency register move operations
are performed by the Renamer to free up the Scheduler and execution core for improved performance.
Scheduler: The Scheduler controls the dispatch of micro-ops onto the dispatch ports. There are eight
dispatch ports to support the out-of-order execution core. Four of the eight ports provided execution
resources for computational operations. The other 4 ports support memory operations of up to two 256bit load and one 256-bit store operation in a cycle.
2-14
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Execution Core: The scheduler can dispatch up to eight micro-ops every cycle, one on each port. Of the
four ports providing computational resources, each provides an ALU, two of these execution pipes
provided dedicated FMA units. With the exception of division/square-root, STTNI/AESNI units, most
floating-point and integer SIMD execution units are 256-bit wide. The four dispatch ports servicing
memory operations consist with two dual-use ports for load and store-address operation. Plus a dedicated 3rd store-address port and one dedicated store-data port. All memory ports can handle 256-bit
memory micro-ops. Peak floating-point throughput, at 32 single-precision operations per cycle and 16
double-precision operations per cycle using FMA, is twice that of Intel microarchitecture code name
Sandy Bridge.
The out-of-order engine can handle 192 uops in flight compared to 168 in Intel microarchitecture code
name Sandy Bridge.
2.3.3
Execution Engine
Table 2-7 summarizes which operations can be dispatched on which port.
Table 2-7. Dispatch Port and Execution Stacks of the Haswell Microarchitecture
Port 0
Port 1
Port 2, 3
ALU,
ALU,
Load_Addr,
Shift
Fast LEA,
Store_addr
Port 4
Store_data
Port 5
Port 6
ALU,
ALU,
Fast LEA,
Shift,
BM
BM
JEU
SIMD_Log,
SIMD misc,
SIMD_Shifts
SIMD_ALU,
SIMD_Log
SIMD_ALU,
SIMD_Log,
FMA/FP_mul,
Divide
FMA/FP_mul,
FP_add
Shuffle
2nd_Jeu
slow_int,
Port 7
Store_addr,
Simple_AGU
FP mov,
AES
Table 2-8 lists execution units and common representative instructions that rely on these units. Table 2-8
also includes some instructions that are available only on processors based on the Broadwell microarchitecture.
2-15
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-8. Haswell Microarchitecture Execution Units and Representative Instructions
Execution
Unit
# of
Ports
Instructions
ALU
4
add, and, cmp, or, test, xor, movzx, movsx, mov, (v)movdqu, (v)movdqa
SHFT
2
sal, shl, rol, adc, sarx, (adcx, adox)1 etc.
Slow Int
1
mul, imul, bsr, rcl, shld, mulx, pdep, etc.
BM
2
andn, bextr, blsi, blsmsk, bzhi, etc
SIMD Log
3
(v)pand, (v)por, (v)pxor, (v)movq, (v)movq, (v)blendp*, vpblendd
SIMD_Shft
1
(v)psl*, (v)psr*
SIMD ALU
2
(v)padd*, (v)psign, (v)pabs, (v)pavgb, (v)pcmpeq*, (v)pmax, (v)pcmpgt*
Shuffle
1
(v)shufp*, vperm*, (v)pack*, (v)unpck*, (v)punpck*, (v)pshuf*, (v)pslldq, (v)alignr, (v)pmovzx*,
vbroadcast*, (v)pslldq, (v)pblendw
SIMD Misc
1
(v)pmul*, (v)pmadd*, STTNI, (v)pclmulqdq, (v)psadw, (v)pcmpgtq, vpsllvd, (v)bendv*, (v)plendw,
FP Add
1
(v)addp*, (v)cmpp*, (v)max*, (v)min*,
FP Mov
1
(v)movap*, (v)movup*, (v)movsd/ss, (v)movd gpr, (v)andp*, (v)orp*
DIVIDE
1
divp*, divs*, vdiv*, sqrt*, vsqrt*, rcp*, vrcp*, rsqrt*, idiv
NOTES:
1. Only available in processors based on the Broadwell microarchitecture and support CPUID ADX feature flag.
The reservation station (RS) is expanded to 60 entries deep (compared to 54 entries in Intel microarchitecture code name Sandy Bridge). It can dispatch up to eight micro-ops in one cycle if the micro-ops are
ready to execute. The RS dispatch a micro-op through an issue port to a specific execution cluster,
arranged in several stacks to handle specific data types or granularity of data.
When a source of a micro-op executed in one stack comes from a micro-op executed in another stack, a
delay can occur. The delay occurs also for transitions between Intel SSE integer and Intel SSE floatingpoint operations. In some of the cases the data transition is done using a micro-op that is added to the
instruction flow. Table 2-30 describes how data, written back after execution, can bypass to micro-op
execution in the following cycles.
2-16
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-9. Bypass Delay Between Producer and Consumer Micro-ops (cycles)
From/To
INT
SSE-INT/
AVX-INT
•
•
INT
SSE-INT/
AVX-INT
micro-op (port 1)
SSE-FP/
AVX-FP_LOW
micro-op (port 1)
X87/
AVX-FP_High
micro-op (port 1) + 3
cycle delay
micro-op (port 5)
micro-op (port 6) +
1 cycle
•
•
micro-op (port 5)
micro-op (port 6) + 1
cycle
X87/
AVX-FP_High
micro-op (port 5) + 3
cycle delay
1 cycle delay
1 cycle delay
Load
2.3.4
SSE-FP/
AVX-FP_LOW
micro-op (port 5) +
1cycle delay
micro-op (port 5) +
1cycle delay
1 cycle delay
1 cycle delay
2 cycle delay
Cache and Memory Subsystem
The cache hierarchy is similar to prior generations, including an instruction cache, a first-level data cache
and a second-level unified cache in each core, and a 3rd-level unified cache with size dependent on
specific product configuration. The 3rd-level cache is organized as multiple cache slices, the size of each
slice may depend on product configurations, connected by a ring interconnect. The exact details of the
cache topology is reported by CPUID leaf 4. The 3rd level cache resides in the “uncore” sub-system that
is shared by all the processor cores. In some product configurations, a fourth level cache is also
supported. Table 2-28 provides more details of the cache hierarchy.
Table 2-10. Cache Parameters of the Haswell Microarchitecture
Level
Capacity/Ass
ociativity
Line Size
(bytes)
Fastest
Latency1
Throughput Peak Bandwidth
(clocks)
(bytes/cyc)
Update
Policy
First Level Data
32 KB/ 8
64
4 cycle
0.52
64 (Load) + 32 (Store)
Writeback
Instruction
32 KB/8
64
N/A
N/A
N/A
N/A
Second Level
256KB/8
64
11 cycle
Varies
64
Writeback
64
~34
Varies
Third Level
(Shared L3)
Varies
Writeback
NOTES:
1. Software-visible latency will vary depending on access patterns and other factors. L3 latency can vary due to clock
ratios between the processor core and uncore.
2. First level data cache supports two load micro-ops each cycle; each micro-op can fetch up to 32-bytes of data.
2-17
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The TLB hierarchy consists of dedicated level one TLB for instruction cache, TLB for L1D, plus unified TLB
for L2.
Table 2-11. TLB Parameters of the Haswell Microarchitecture
Level
Page Size
Entries
Associativity
Partition
Instruction
4KB
128
4 ways
dynamic
Instruction
2MB/4MB
8 per thread
First Level Data
4KB
64
4
fixed
First Level Data
2MB/4MB
32
4
fixed
First Level Data
1GB
4
4
fixed
Second Level
Shared by 4KB and 2/4MB pages
1024
8
fixed
2.3.4.1
fixed
Load and Store Operation Enhancements
The L1 data cache can handle two 256-bit load and one 256-bit store operations each cycle. The unified
L2 can service one cache line (64 bytes) each cycle. Additionally, there are 72 load buffers and 42 store
buffers available to support micro-ops execution in-flight.
2.3.5
The Haswell-E Microarchitecture
Intel processors based on the Haswell-E microarchitecture comprises the same processor cores as
described in the Haswell microarchitecture, but provides more advanced uncore and integrated I/O capabilities. Processors based on the Haswell-E microarchitecture support platforms with multiple sockets.
The Haswell-E microarchitecture supports versatile processor architectures and platform configurations
for scalability and high performance. Some of capabilities provided by the uncore and integrated I/O subsystem of the Haswell-E microarchitecture include:
•
•
•
•
Support for multiple Intel QPI interconnects in multi-socket configurations.
Up to two integrated memory controllers per physical processor.
Up to 40 lanes of PCI Express* 3.0 links per physical processor.
Up to 18 processor cores connected by two ring interconnects to the L3 in each physical processor.
An example of a possible 12-core processor implementation using the Haswell-E microarchitecture is
illustrated in Figure 2-6. The capabilities of the uncore and integrated I/O sub-system vary across the
processor family implementing the Haswell-E microarchitecture. For details, please consult the data
sheets of respective Intel Xeon E5 v3 processors.
2-18
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Legend:
PCIe
Uncore
QPI
CPU Core
Integrated I/O
QPII Links
Sbox
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Core
L3 Slice
Sbox
DRAM
Home Agent
Memory Controller
DRAM
DRAM
Home Agent
Memory Controller
DRAM
Figure 2-6. An Example of the Haswell-E Microarchitecture Supporting 12 Processor Cores
2.3.6
The Broadwell Microarchitecture
Intel Core M processors are based on the Broadwell microarchitecture. The Broadwell microarchitecture
builds from the Haswell microarchitecture and provides several enhancements. This section covers
enhanced features of the Broadwell microarchitecture.
•
Floating-point multiply instruction latency is improved from 5 cycles in prior generation to 3 cycle in
the Broadwell microarchitecture. This applies to AVX, SSE and FP instruction sets.
•
•
The throughput of gather instructions has been improved significantly, see Table C-5.
The PCLMULQDQ instruction implementation is a single uop in the Broadwell microarchitecture with
improved latency and throughput.
The TLB hierarchy consists of dedicated level one TLB for instruction cache, TLB for L1D, plus unified TLB
for L2.
Table 2-12. TLB Parameters of the Broadwell Microarchitecture
Level
Page Size
Entries
Associativity
Partition
Instruction
4KB
128
4 ways
dynamic
Instruction
2MB/4MB
8 per thread
First Level Data
4KB
64
4
fixed
First Level Data
2MB/4MB
32
4
fixed
First Level Data
1GB
4
4
fixed
Second Level
Shared by 4KB and 2MB pages
1536
6
fixed
Second Level
1GB pages
16
4
fixed
fixed
2-19
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.4
INTEL® MICROARCHITECTURE CODE NAME SANDY BRIDGE
Intel® microarchitecture code name Sandy Bridge builds on the successes of Intel® Core™ microarchitecture and Intel microarchitecture code name Nehalem. It offers the following innovative features:
•
Intel Advanced Vector Extensions (Intel AVX)
— 256-bit floating-point instruction set extensions to the 128-bit Intel Streaming SIMD Extensions,
providing up to 2X performance benefits relative to 128-bit code.
— Non-destructive destination encoding offers more flexible coding techniques.
— Supports flexible migration and co-existence between 256-bit AVX code, 128-bit AVX code and
legacy 128-bit SSE code.
•
Enhanced front end and execution engine
— New decoded ICache component that improves front end bandwidth and reduces branch misprediction penalty.
— Advanced branch prediction.
— Additional macro-fusion support.
— Larger dynamic execution window.
— Multi-precision integer arithmetic enhancements (ADC/SBB, MUL/IMUL).
— LEA bandwidth improvement.
— Reduction of general execution stalls (read ports, writeback conflicts, bypass latency, partial
stalls).
— Fast floating-point exception handling.
— XSAVE/XRSTORE performance improvements and XSAVEOPT new instruction.
•
Cache hierarchy improvements for wider data path
— Doubling of bandwidth enabled by two symmetric ports for memory operation.
— Simultaneous handling of more in-flight loads and stores enabled by increased buffers.
— Internal bandwidth of two loads and one store each cycle.
— Improved prefetching.
— High bandwidth low latency LLC architecture.
— High bandwidth ring architecture of on-die interconnect.
•
System-on-a-chip support
— Integrated graphics and media engine in second generation Intel Core processors.
— Integrated PCIE controller.
— Integrated memory controller.
•
Next generation Intel Turbo Boost Technology
— Leverage TDP headroom to boost performance of CPU cores and integrated graphic unit.
2.4.1
Intel® Microarchitecture Code Name Sandy Bridge Pipeline Overview
Figure 2-7 depicts the pipeline and major components of a processor core that’s based on Intel microarchitecture code name Sandy Bridge. The pipeline consists of
•
An in-order issue front end that fetches instructions and decodes them into micro-ops (micro-operations). The front end feeds the next pipeline stages with a continuous stream of micro-ops from the
most likely path that the program will execute.
2-20
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
An out-of-order, superscalar execution engine that dispatches up to six micro-ops to execution, per
cycle. The allocate/rename block reorders micro-ops to "dataflow" order so they can execute as soon
as their sources are ready and execution resources are available.
•
An in-order retirement unit that ensures that the results of execution of the micro-ops, including any
exceptions they may have encountered, are visible according to the original program order.
The flow of an instruction in the pipeline can be summarized in the following progression:
1. The Branch Prediction Unit chooses the next block of code to execute from the program. The
processor searches for the code in the following resources, in this order:
a. Decoded ICache.
b. Instruction Cache, via activating the legacy decode pipeline.
c.
L2 cache, last level cache (LLC) and memory, as necessary.
32K L1 Instruction Cache
Pre-decode
Instr Queue
Branch Predictor
Load
Buffers
Store
Buffers
Decoders
1.5K uOP Cache
Reorder
Buffers
Allocate/Rename/Retire
In-order
out-of-order
Port 0
ALU
V-Mul
V-Shuffle
Fdiv
256- FP MUL
256- FP Blend
Scheduler
Port 1
Port 5
ALU
ALU
JMP
V-Add
V-Shuffle
256- FP Add
Port 2
Load
StAddr
Port 3
Port 4
Load
StAddr
STD
256- FP Shuf
256- FP Bool
256- FP Blend
Memory Control
48 bytes/cycle
256K L2 Cache (Unified)
Line Fill
Buffers
32K L1 Data Cache
Figure 2-7. Intel Microarchitecture Code Name Sandy Bridge Pipeline Functionality
2. The micro-ops corresponding to this code are sent to the Rename/retirement block. They enter into
the scheduler in program order, but execute and are de-allocated from the scheduler according to
data-flow order. For simultaneously ready micro-ops, FIFO ordering is nearly always maintained.
Micro-op execution is executed using execution resources arranged in three stacks. The execution
units in each stack are associated with the data type of the instruction.
Branch mispredictions are signaled at branch execution. It re-steers the front end which delivers
micro-ops from the correct path. The processor can overlap work preceding the branch misprediction with work from the following corrected path.
2-21
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
3. Memory operations are managed and reordered to achieve parallelism and maximum performance.
Misses to the L1 data cache go to the L2 cache. The data cache is non-blocking and can handle
multiple simultaneous misses.
4. Exceptions (Faults, Traps) are signaled at retirement (or attempted retirement) of the faulting
instruction.
Each processor core based on Intel microarchitecture code name Sandy Bridge can support two logical
processor if Intel Hyper-Threading Technology is enabled.
2.4.2
The Front End
This section describes the key characteristics of the front end. Table 2-13 lists the components of the
front end, their functions, and the problems they address.
Table 2-13. Components of the Front End of Intel Microarchitecture Code Name Sandy Bridge
Component
Functions
Performance Challenges
Instruction Cache
32-Kbyte backing store of instruction bytes
Fast access to hot code instruction bytes
Legacy Decode Pipeline
Decode instructions to micro-ops, delivered to
the micro-op queue and the Decoded ICache.
Provides the same decode latency and
bandwidth as prior Intel processors.
Decoded ICache warm-up
Decoded ICache
Provide stream of micro-ops to the micro-op
queue.
MSROM
Complex instruction micro-op flow store,
accessible from both Legacy Decode Pipeline
and Decoded ICache
Branch Prediction Unit
(BPU)
Determine next block of code to be executed
and drive lookup of Decoded ICache and legacy
decode pipelines.
Improves performance and energy
efficiency through reduced branch
mispredictions.
Micro-op queue
Queues micro-ops from the Decoded ICache
and the legacy decode pipeline.
Hide front end bubbles; provide execution
micro-ops at a constant rate.
2.4.2.1
Provides higher micro-op bandwidth at
lower latency and lower power than the
legacy decode pipeline
Legacy Decode Pipeline
The Legacy Decode Pipeline comprises the instruction translation lookaside buffer (ITLB), the instruction
cache (ICache), instruction predecode, and instruction decode units.
Instruction Cache and ITLB
An instruction fetch is a 16-byte aligned lookup through the ITLB and into the instruction cache. The
instruction cache can deliver every cycle 16 bytes to the instruction pre-decoder. Table 2-13 compares
the ICache and ITLB with prior generation.
Table 2-14. ICache and ITLB of Intel Microarchitecture Code Name Sandy Bridge
Component
Intel microarchitecture code name Sandy
Bridge
Intel microarchitecture code name
Nehalem
ICache Size
32-Kbyte
32-Kbyte
ICache Ways
8
4
ITLB 4K page entries
128
128
ITLB large page (2M or
4M) entries
8
7
2-22
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Upon ITLB miss there is a lookup to the Second level TLB (STLB) that is common to the DTLB and the
ITLB. The penalty of an ITLB miss and a STLB hit is seven cycles.
Instruction PreDecode
The predecode unit accepts the 16 bytes from the instruction cache and determines the length of the
instructions.
The following length changing prefixes (LCPs) imply instruction length that is different from the default
length of instructions. Therefore they cause an additional penalty of three cycles per LCP during length
decoding. Previous processors incur a six-cycle penalty for each 16-byte chunk that has one or more
LCPs in it. Since usually there is no more than one LCP in a 16-byte chunk, in most cases, Intel microarchitecture code name Sandy Bridge introduces an improvement over previous processors.
•
Operand Size Override (66H) preceding an instruction with a word/double immediate data. This
prefix might appear when the code uses 16 bit data types, unicode processing, and image
processing.
•
Address Size Override (67H) preceding an instruction with a modr/m in real, big real, 16-bit
protected or 32-bit protected modes. This prefix may appear in boot code sequences.
•
The REX prefix (4xh) in the Intel® 64 instruction set can change the size of two classes of instructions: MOV offset and MOV immediate. Despite this capability, it does not cause an LCP penalty and
hence is not considered an LCP.
Instruction Decode
There are four decoding units that decode instruction into micro-ops. The first can decode all IA-32 and
Intel 64 instructions up to four micro-ops in size. The remaining three decoding units handle singlemicro-op instructions. All four decoding units support the common cases of single micro-op flows
including micro-fusion and macro-fusion.
Micro-ops emitted by the decoders are directed to the micro-op queue and to the Decoded ICache.
Instructions longer than four micro-ops generate their micro-ops from the MSROM. The MSROM bandwidth is four micro-ops per cycle. Instructions whose micro-ops come from the MSROM can start from
either the legacy decode pipeline or from the Decoded ICache.
MicroFusion
Micro-fusion fuses multiple micro-ops from the same instruction into a single complex micro-op. The
complex micro-op is dispatched in the out-of-order execution core as many times as it would if it were
not micro-fused.
Micro-fusion enables you to use memory-to-register operations, also known as the complex instruction
set computer (CISC) instruction set, to express the actual program operation without worrying about a
loss of decode bandwidth. Micro-fusion improves instruction bandwidth delivered from decode to retirement and saves power.
Coding an instruction sequence by using single-uop instructions will increases the code size, which can
decrease fetch bandwidth from the legacy pipeline.
The following are examples of micro-fused micro-ops that can be handled by all decoders.
•
All stores to memory, including store immediate. Stores execute internally as two separate functions,
store-address and store-data.
•
All instructions that combine load and computation operations (load+op), for example:
•
•
•
•
•
ADDPS XMM9, OWORD PTR [RSP+40]
FADD DOUBLE PTR [RDI+RSI*8]
XOR RAX, QWORD PTR [RBP+32]
All instructions of the form "load and jump," for example:
•
•
JMP [RDI+200]
RET
CMP and TEST with immediate operand and memory
2-23
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
An instruction with RIP relative addressing is not micro-fused in the following cases:
•
•
An additional immediate is needed, for example:
•
•
CMP [RIP+400], 27
MOV [RIP+3000], 142
The instruction is a control flow instruction with an indirect target specified using RIP-relative
addressing, for example:
•
JMP [RIP+5000000]
In these cases, an instruction that can not be micro-fused will require decoder 0 to issue two micro-ops,
resulting in a slight loss of decode bandwidth.
In 64-bit code, the usage of RIP Relative addressing is common for global data. Since there is no microfusion in these cases, performance may be reduced when porting 32-bit code to 64-bit code.
Macro-Fusion
Macro-fusion merges two instructions into a single micro-op. In Intel Core microarchitecture, this hardware optimization is limited to specific conditions specific to the first and second of the macro-fusable
instruction pair.
•
The first instruction of the macro-fused pair modifies the flags. The following instructions can be
macro-fused:
— In Intel microarchitecture code name Nehalem: CMP, TEST.
— In Intel microarchitecture code name Sandy Bridge: CMP, TEST, ADD, SUB, AND, INC, DEC
— These instructions can fuse if
•
•
•
The first source / destination operand is a register.
The second source operand (if exists) is one of: immediate, register, or non RIP-relative
memory.
The second instruction of the macro-fusable pair is a conditional branch. Table 3-1 describes, for each
instruction, what branches it can fuse with.
Macro fusion does not happen if the first instruction ends on byte 63 of a cache line, and the second
instruction is a conditional branch that starts at byte 0 of the next cache line.
Since these pairs are common in many types of applications, macro-fusion improves performance even
on non-recompiled binaries.
Each macro-fused instruction executes with a single dispatch. This reduces latency and frees execution
resources. You also gain increased rename and retire bandwidth, increased virtual storage, and power
savings from representing more work in fewer bits.
2.4.2.2
Decoded ICache
The Decoded ICache is essentially an accelerator of the legacy decode pipeline. By storing decoded
instructions, the Decoded ICache enables the following features:
•
•
•
Reduced latency on branch mispredictions.
Increased micro-op delivery bandwidth to the out-of-order engine.
Reduced front end power consumption.
The Decoded ICache caches the output of the instruction decoder. The next time the micro-ops are
consumed for execution the decoded micro-ops are taken from the Decoded ICache. This enables skipping the fetch and decode stages for these micro-ops and reduces power and latency of the Front End.
The Decoded ICache provides average hit rates of above 80% of the micro-ops; furthermore, "hot spots"
typically have hit rates close to 100%.
Typical integer programs average less than four bytes per instruction, and the front end is able to race
ahead of the back end, filling in a large window for the scheduler to find instruction level parallelism.
However, for high performance code with a basic block consisting of many instructions, for example, Intel
2-24
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
SSE media algorithms or excessively unrolled loops, the 16 instruction bytes per cycle is occasionally a
limitation. The 32-byte orientation of the Decoded ICache helps such code to avoid this limitation.
The Decoded ICache automatically improves performance of programs with temporal and spatial locality.
However, to fully utilize the Decoded ICache potential, you might need to understand its internal organization.
The Decoded ICache consists of 32 sets. Each set contains eight Ways. Each Way can hold up to six
micro-ops. The Decoded ICache can ideally hold up to 1536 micro-ops.
The following are some of the rules how the Decoded ICache is filled with micro-ops:
•
All micro-ops in a Way represent instructions which are statically contiguous in the code and have
their EIPs within the same aligned 32-byte region.
•
Up to three Ways may be dedicated to the same 32-byte aligned chunk, allowing a total of 18 microops to be cached per 32-byte region of the original IA program.
•
•
•
•
•
•
•
A multi micro-op instruction cannot be split across Ways.
Up to two branches are allowed per Way.
An instruction which turns on the MSROM consumes an entire Way.
A non-conditional branch is the last micro-op in a Way.
Micro-fused micro-ops (load+op and stores) are kept as one micro-op.
A pair of macro-fused instructions is kept as one micro-op.
Instructions with 64-bit immediate require two slots to hold the immediate.
When micro-ops cannot be stored in the Decoded ICache due to these restrictions, they are delivered
from the legacy decode pipeline. Once micro-ops are delivered from the legacy pipeline, fetching microops from the Decoded ICache can resume only after the next branch micro-op. Frequent switches can
incur a penalty.
The Decoded ICache is virtually included in the Instruction cache and ITLB. That is, any instruction with
micro-ops in the Decoded ICache has its original instruction bytes present in the instruction cache.
Instruction cache evictions must also be evicted from the Decoded ICache, which evicts only the necessary lines.
There are cases where the entire Decoded ICache is flushed. One reason for this can be an ITLB entry
eviction. Other reasons are not usually visible to the application programmer, as they occur when important controls are changed, for example, mapping in CR3, or feature and mode enabling in CR0 and CR4.
There are also cases where the Decoded ICache is disabled, for instance, when the CS base address is
NOT set to zero.
2.4.2.3
Branch Prediction
Branch prediction predicts the branch target and enables the processor to begin executing instructions
long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU)
for prediction. This unit predicts the target address not only based on the EIP of the branch but also
based on the execution path through which execution reached this EIP. The BPU can efficiently predict the
following branch types:
•
•
•
•
Conditional branches.
Direct calls and jumps.
Indirect calls and jumps.
Returns.
2.4.2.4
Micro-op Queue and the Loop Stream Detector (LSD)
The micro-op queue decouples the front end and the out-of order engine. It stays between the micro-op
generation and the renamer as shown in Figure 2-7. This queue helps to hide bubbles which are introduced between the various sources of micro-ops in the front end and ensures that four micro-ops are
delivered for execution, each cycle.
2-25
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The micro-op queue provides post-decode functionality for certain instructions types. In particular, loads
combined with computational operations and all stores, when used with indexed addressing, are represented as a single micro-op in the decoder or Decoded ICache. In the micro-op queue they are fragmented into two micro-ops through a process called un-lamination, one does the load and the other does
the operation. A typical example is the following "load plus operation" instruction:
ADD
RAX, [RBP+RSI]; rax := rax + LD( RBP+RSI )
Similarly, the following store instruction has three register sources and is broken into "generate store
address" and "generate store data" sub-components.
MOV
[ESP+ECX*4+12345678], AL
The additional micro-ops generated by unlamination use the rename and retirement bandwidth.
However, it has an overall power benefit. For code that is dominated by indexed addressing (as often
happens with array processing), recoding algorithms to use base (or base+displacement) addressing can
sometimes improve performance by keeping the load plus operation and store instructions fused.
The Loop Stream Detector (LSD)
The Loop Stream Detector was introduced in Intel® Core microarchitectures. The LSD detects small loops
that fit in the micro-op queue and locks them down. The loop streams from the micro-op queue, with no
more fetching, decoding, or reading micro-ops from any of the caches, until a branch mis-prediction
inevitably ends it.
The loops with the following attributes qualify for LSD/micro-op queue replay:
•
•
•
•
•
Up to eight chunk fetches of 32-instruction-bytes.
Up to 28 micro-ops (~28 instructions).
All micro-ops are also resident in the Decoded ICache.
Can contain no more than eight taken branches and none of them can be a CALL or RET.
Cannot have mismatched stack operations. For example, more PUSH than POP instructions.
Many calculation-intensive loops, searches and software string moves match these characteristics.
Use the loop cache functionality opportunistically. For high performance code, loop unrolling is generally
preferable for performance even when it overflows the LSD capability.
2.4.3
The Out-of-Order Engine
The Out-of-Order engine provides improved performance over prior generations with excellent power
characteristics. It detects dependency chains and sends them to execution out-of-order while maintaining the correct data flow. When a dependency chain is waiting for a resource, such as a second-level
data cache line, it sends micro-ops from another chain to the execution core. This increases the overall
rate of instructions executed per cycle (IPC).
The out-of-order engine consists of two blocks, shown in Figure 2-7: Core Functional Diagram, the
Rename/retirement block, and the Scheduler.
The Out-of-Order engine contains the following major components:
Renamer. The Renamer component moves micro-ops from the front end to the execution core. It eliminates false dependencies among micro-ops, thereby enabling out-of-order execution of micro-ops.
Scheduler. The Scheduler component queues micro-ops until all source operands are ready. Schedules
and dispatches ready micro-ops to the available execution units in as close to a first in first out (FIFO)
order as possible.
Retirement. The Retirement component retires instructions and micro-ops in order and handles faults
and exceptions.
2-26
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.4.3.1
Renamer
The Renamer is the bridge between the in-order part in Figure 2-7, and the dataflow world of the Scheduler. It moves up to four micro-ops every cycle from the micro-op queue to the out-of-order engine.
Although the renamer can send up to 4 micro-ops (unfused, micro-fused, or macro-fused) per cycle, this
is equivalent to the issue port can dispatch six micro-ops per cycle. In this process, the out-of-order core
carries out the following steps:
•
Renames architectural sources and destinations of the micro-ops to micro-architectural sources and
destinations.
•
•
Allocates resources to the micro-ops. For example, load or store buffers.
Binds the micro-op to an appropriate dispatch port.
Some micro-ops can execute to completion during rename and are removed from the pipeline at that
point, effectively costing no execution bandwidth. These include:
•
•
•
•
Zero idioms (dependency breaking idioms).
NOP.
VZEROUPPER.
FXCHG.
The renamer can allocate two branches each cycle, compared to one branch each cycle in the previous
microarchitecture. This can eliminate some bubbles in execution.
Micro-fused load and store operations that use an index register are decomposed to two micro-ops,
hence consume two out of the four slots the Renamer can use every cycle.
Dependency Breaking Idioms
Instruction parallelism can be improved by using common instructions to clear register contents to zero.
The renamer can detect them on the zero evaluation of the destination register.
Use one of these dependency breaking idioms to clear a register when possible.
•
•
•
•
•
•
•
XOR REG,REG
SUB REG,REG
PXOR/VPXOR XMMREG,XMMREG
PSUBB/W/D/Q XMMREG,XMMREG
VPSUBB/W/D/Q XMMREG,XMMREG
XORPS/PD XMMREG,XMMREG
VXORPS/PD YMMREG, YMMREG
Since zero idioms are detected and removed by the renamer, they have no execution latency.
There is another dependency breaking idiom - the "ones idiom".
•
CMPEQ
XMM1, XMM1; "ones idiom" set all elements to all "ones"
In this case, the micro-op must execute, however, since it is known that regardless of the input data the
output data is always "all ones" the micro-op dependency upon its sources does not exist as with the zero
idiom and it can execute as soon as it finds a free execution port.
2.4.3.2
Scheduler
The scheduler controls the dispatch of micro-ops onto their execution ports. In order to do this, it must
identify which micro-ops are ready and where its sources come from: a register file entry, or a bypass
directly from an execution unit. Depending on the availability of dispatch ports and writeback buses, and
the priority of ready micro-ops, the scheduler selects which micro-ops are dispatched every cycle.
2-27
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.4.4
The Execution Core
The execution core is superscalar and can process instructions out of order. The execution core optimizes
overall performance by handling the most common operations efficiently, while minimizing potential
delays.
The out-of-order execution core improves execution unit organization over prior generation in the
following ways:
•
•
•
•
Reduction in read port stalls.
Reduction in writeback conflicts and delays.
Reduction in power.
Reduction of SIMD FP assists dealing with denormal inputs and underflow outputs.
Some high precision FP algorithms need to operate with FTZ=0 and DAZ=0, i.e. permitting underflowed
intermediate results and denormal inputs to achieve higher numerical precision at the expense of
reduced performance on prior generation microarchitectures due to SIMD FP assists. The reduction of
SIMD FP assists in Intel microarchitecture code name Sandy Bridge applies to the following SSE instructions (and AVX variants): ADDPD/ADDPS, MULPD/MULPS, DIVPD/DIVPS, and CVTPD2PS.
The out-of-order core consist of three execution stacks, where each stack encapsulates a certain type of
data. The execution core contains the following execution stacks:
•
•
•
General purpose integer.
SIMD integer and floating-point.
X87.
The execution core also contains connections to and from the cache hierarchy. The loaded data is fetched
from the caches and written back into one of the stacks.
The scheduler can dispatch up to six micro-ops every cycle, one on each port. The following table
summarizes which operations can be dispatched on which port.
Table 2-15. Dispatch Port and Execution Stacks
Port 0
Integer
SSE-Int,
AVX-Int,
ALU, Shift
Mul, Shift,
STTNI, Int-Div,
Port 1
Port 2
Port 3
Port 4
ALU,
Load_Addr,
Load_Addr
Store_data
Fast LEA,
Store_addr
Store_addr
Port 5
ALU,
Shift,
Slow LEA,
Branch,
MUL
Fast LEA
ALU, Shuf,
Blend, 128bMov
Store_data
ALU, Shuf,
Shift, Blend,
128b-Mov
MMX
128b-Mov
SSE-FP,
Mul, Div, Blend,
256b-Mov
Add, CVT
Store_data
Shuf, Blend,
256b-Mov
Mul, Div, Blend,
256b-Mov
Add, CVT
Store_data
Shuf, Blend,
256b-Mov
AVX-FP_low
X87,
AVX-FP_High
After execution, the data is written back on a writeback bus corresponding to the dispatch port and the
data type of the result. Micro-ops that are dispatched on the same port but have different latencies may
need the write back bus at the same cycle. In these cases the execution of one of the micro-ops is
delayed until the writeback bus is available. For example, MULPS (five cycles) and BLENDPS (one cycle)
may collide if both are ready for execution on port 0: first the MULPS and four cycles later the BLENDPS.
Intel microarchitecture code name Sandy Bridge eliminates such collisions as long as the micro-ops write
2-28
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
the results to different stacks. For example, integer ADD (one cycle) can be dispatched four cycles after
MULPS (five cycles) since the integer ADD uses the integer stack while the MULPS uses the FP stack.
When a source of a micro-op executed in one stack comes from a micro-op executed in another stack, a
one- or two-cycle delay can occur. The delay occurs also for transitions between Intel SSE integer and
Intel SSE floating-point operations. In some of the cases the data transition is done using a micro-op that
is added to the instruction flow. The following table describes how data, written back after execution, can
bypass to micro-op execution in the following cycles.
Table 2-16. Execution Core Writeback Latency (cycles)
Integer
SSE-Int, AVX-Int,
SSE-FP,
X87,
MMX
AVX-FP_low
AVX-FP_High
Integer
0
micro-op (port 0)
micro-op (port 0)
micro-op (port 0) +
1 cycle
SSE-Int, AVX-Int,
MMX
micro-op (port 5) or
micro-op (port 5) +1
cycle
0
1 cycle delay
0
SSE-FP,
micro-op (port 5) or
micro-op (port 5) +1
cycle
1 cycle delay
0
micro-op (port 5) +1
cycle
0
micro-op (port 5)
+1 cycle
0
AVX-FP_High
micro-op (port 5) +1
cycle
Load
0
1 cycle delay
1 cycle delay
2 cycle delay
2.4.5
Cache Hierarchy
AVX-FP_low
X87,
The cache hierarchy contains a first level instruction cache, a first level data cache (L1 DCache) and a
second level (L2) cache, in each core. The L1D cache may be shared by two logical processors if the
processor support Intel HyperThreading Technology. The L2 cache is shared by instructions and data. All
cores in a physical processor package connect to a shared last level cache (LLC) via a ring connection.
The caches use the services of the Instruction Translation Lookaside Buffer (ITLB), Data Translation
Lookaside Buffer (DTLB) and Shared Translation Lookaside Buffer (STLB) to translate linear addresses to
physical address. Data coherency in all cache levels is maintained using the MESI protocol. For more
information, see the Intel® 64 IA-32 Architectures Software Developer's Manual, Volume 3. Cache hierarchy details can be obtained at run-time using the CPUID instruction. see the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A.
Table 2-17. Cache Parameters
Level
Capacity
Associativity
(ways)
Line Size
(bytes)
Write Update
Policy
Inclusive
L1 Data
32 KB
8
64
Writeback
-
Instruction
32 KB
8
N/A
N/A
-
L2 (Unified)
256 KB
8
64
Writeback
No
Third Level (LLC)
Varies, query
CPUID leaf 4
Varies with cache
size
64
Writeback
Yes
2-29
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.4.5.1
Load and Store Operation Overview
This section provides an overview of the load and store operations.
Loads
When an instruction reads data from a memory location that has write-back (WB) type, the processor
looks for it in the caches and memory. Table 2-18 shows the access lookup order and best case latency.
The actual latency can vary depending on the cache queue occupancy, LLC ring occupancy, memory
components, and their parameters.
Table 2-18. Lookup Order and Load Latency
Level
Latency (cycles)
Bandwidth (per core per cycle)
L1 Data
41
2 x16 bytes
L2 (Unified)
12
1 x 32 bytes
Third Level (LLC)
26-312
1 x 32 bytes
L2 and L1 DCache in other cores
if applicable
43- clean hit;
60 - dirty hit
NOTES:
1. Subject to execution core bypass restriction shown in Table 2-16.
2. Latency of L3 varies with product segment and sku. The values apply to second generation Intel Core processor families.
The LLC is inclusive of all cache levels above it - data contained in the core caches must also reside in the
LLC. Each cache line in the LLC holds an indication of the cores that may have this line in their L2 and L1
caches. If there is an indication in the LLC that other cores may hold the line of interest and its state
might have to modify, there is a lookup into the L1 DCache and L2 of these cores too. The lookup is called
“clean” if it does not require fetching data from the other core caches. The lookup is called “dirty” if modified data has to be fetched from the other core caches and transferred to the loading core.
The latencies shown above are the best-case scenarios. Sometimes a modified cache line has to be
evicted to make space for a new cache line. The modified cache line is evicted in parallel to bringing the
new data and does not require additional latency. However, when data is written back to memory, the
eviction uses cache bandwidth and possibly memory bandwidth as well. Therefore, when multiple cache
misses require the eviction of modified lines within a short time, there is an overall degradation in cache
response time. Memory access latencies vary based on occupancy of the memory controller queues,
DRAM configuration, DDR parameters, and DDR paging behavior (if the requested page is a page-hit,
page-miss or page-empty).
Stores
When an instruction writes data to a memory location that has a write back memory type, the processor
first ensures that it has the line containing this memory location in its L1 DCache, in Exclusive or Modified
MESI state. If the cache line is not there, in the right state, the processor fetches it from the next levels
of the memory hierarchy using a Read for Ownership request. The processor looks for the cache line in
the following locations, in the specified order:
1. L1 DCache
2. L2
3. Last Level Cache
4. L2 and L1 DCache in other cores, if applicable
5. Memory
Once the cache line is in the L1 DCache, the new data is written to it, and the line is marked as Modified.
Reading for ownership and storing the data happens after instruction retirement and follows the order of
store instruction retirement. Therefore, the store latency usually does not affect the store instruction
itself. However, several sequential stores that miss the L1 DCache may have cumulative latency that can
2-30
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
affect performance. As long as the store does not complete, its entry remains occupied in the store
buffer. When the store buffer becomes full, new micro-ops cannot enter the execution pipe and execution
might stall.
2.4.5.2
L1 DCache
The L1 DCache is the first level data cache. It manages all load and store requests from all types through
its internal data structures. The L1 DCache:
•
•
•
Enables loads and stores to issue speculatively and out of order.
Ensures that retired loads and stores have the correct data upon retirement.
Ensures that loads and stores follow the memory ordering rules of the IA-32 and Intel 64 instruction
set architecture.
Table 2-19. L1 Data Cache Components
Component
Intel microarchitecture code name
Sandy Bridge
Intel microarchitecture code name
Nehalem
Data Cache Unit (DCU)
32KB, 8 ways
32KB, 8 ways
Load buffers
64 entries
48 entries
Store buffers
36 entries
32 entries
Line fill buffers (LFB)
10 entries
10 entries
The DCU is organized as 32 KBytes, eight-way set associative. Cache line size is 64-bytes arranged in
eight banks.
Internally, accesses are up to 16 bytes, with 256-bit Intel AVX instructions utilizing two 16-byte
accesses. Two load operations and one store operation can be handled each cycle.
The L1 DCache maintains requests which cannot be serviced immediately to completion. Some reasons
for requests that are delayed: cache misses, unaligned access that splits across cache lines, data not
ready to be forwarded from a preceding store, loads experiencing bank collisions, and load block due to
cache line replacement.
The L1 DCache can maintain up to 64 load micro-ops from allocation until retirement. It can maintain up
to 36 store operations from allocation until the store value is committed to the cache, or written to the
line fill buffers (LFB) in the case of non-temporal stores.
The L1 DCache can handle multiple outstanding cache misses and continue to service incoming stores
and loads. Up to 10 requests of missing cache lines can be managed simultaneously using the LFB.
The L1 DCache is a write-back write-allocate cache. Stores that hit in the DCU do not update the lower
levels of the memory hierarchy. Stores that miss the DCU allocate a cache line.
Loads
The L1 DCache architecture can service two loads per cycle, each of which can be up to 16 bytes. Up to
32 loads can be maintained at different stages of progress, from their allocation in the out of order engine
until the loaded value is returned to the execution core.
Loads can:
•
Read data before preceding stores when the load address and store address ranges are known not to
conflict.
•
•
Be carried out speculatively, before preceding branches are resolved.
Take cache misses out of order and in an overlapped manner.
Loads cannot:
•
•
Speculatively take any sort of fault or trap.
Speculatively access uncacheable memory.
2-31
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The common load latency is five cycles. When using a simple addressing mode, base plus offset that is
smaller than 2048, the load latency can be four cycles. This technique is especially useful for pointerchasing code. However, overall latency varies depending on the target register data type due to stack
bypass. See Section 2.4.4 for more information.
The following table lists overall load latencies. These latencies assume the common case of flat segment,
that is, segment base address is zero. If segment base is not zero, load latency increases.
Table 2-20. Effect of Addressing Modes on Load Latency
Data Type/Addressing Mode
Base + Offset > 2048;
Base + Index [+ Offset]
Base + Offset < 2048
Integer
5
4
MMX, SSE, 128-bit AVX
6
5
X87
7
6
256-bit AVX
7
7
Stores
Stores to memory are executed in two phases:
•
Execution phase. Fills the store buffers with linear and physical address and data. Once store address
and data are known, the store data can be forwarded to the following load operations that need it.
•
Completion phase. After the store retires, the L1 DCache moves its data from the store buffers to the
DCU, up to 16 bytes per cycle.
Address Translation
The DTLB can perform three linear to physical address translations every cycle, two for load addresses
and one for a store address. If the address is missing in the DTLB, the processor looks for it in the STLB,
which holds data and instruction address translations. The penalty of a DTLB miss that hits the STLB is
seven cycles. Large page support include 1G byte pages, in addition to 4K and 2M/4M pages.
The DTLB and STLB are four way set associative. The following table specifies the number of entries in
the DTLB and STLB.
Table 2-21. DTLB and STLB Parameters
TLB
DTLB
STLB
Page Size
Entries
4KB
64
2MB/4MB
32
1GB
4
4KB
512
Store Forwarding
If a load follows a store and reloads the data that the store writes to memory, the data can forward
directly from the store operation to the load. This process, called store to load forwarding, saves cycles
by enabling the load to obtain the data directly from the store operation instead of through memory. You
can take advantage of store forwarding to quickly move complex structures without losing the ability to
forward the subfields. The memory control unit can handle store forwarding situations with less restrictions compared to previous micro-architectures.
The following rules must be met to enable store to load forwarding:
•
•
•
The store must be the last store to that address, prior to the load.
The store must contain all data being loaded.
The load is from a write-back memory type and neither the load nor the store are non-temporal
accesses.
2-32
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Stores cannot forward to loads in the following cases:
•
Four byte and eight byte loads that cross eight byte boundary, relative to the preceding 16- or 32byte store.
•
Any load that crosses a 16-byte boundary of a 32-byte store.
Table 2-22 to Table 2-25 detail the store to load forwarding behavior. For a given store size, all the loads
that may overlap are shown and specified by ‘F’. Forwarding from 32 byte store is similar to forwarding
from each of the 16 byte halves of the store. Cases that cannot forward are shown as ‘N’.
Table 2-22. Store Forwarding Conditions (1 and 2 byte stores)
Load Alignment
Store
Size
Load
Size
0
1
1
1
F
2
1
F
F
2
F
N
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 2-23. Store Forwarding Conditions (4-16 byte stores)
Load Alignment
Store
Size
Load
Size
0
1
2
3
4
1
F
F
F
F
2
F
F
F
N
4
F
N
N
N
1
F
F
F
2
F
F
4
F
8
8
16
4
5
6
7
8
9
10
11
12
13
14
15
F
F
F
F
F
F
F
F
F
F
N
F
F
F
F
N
N
N
F
N
N
N
N
N
N
N
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
2
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
N
4
F
F
F
F
F
N
N
N
F
F
F
F
F
N
N
N
8
F
N
N
N
N
N
N
N
F
N
N
N
N
N
N
N
16
F
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
2-33
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-24. 32-byte Store Forwarding Conditions (0-15 byte alignment)
Load Alignment
Store
Size
Load
Size
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
2
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
N
4
F
F
F
F
F
N
N
N
F
F
F
F
F
N
N
N
8
F
N
N
N
N
N
N
N
F
N
N
N
N
N
N
N
16
F
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
32
F
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Table 2-25. 32-byte Store Forwarding Conditions (16-31 byte alignment)
Load Alignment
Store
Size
Load
Size
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
2
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
N
4
F
F
F
F
F
N
N
N
F
F
F
F
F
N
N
N
8
F
N
N
N
N
N
N
N
F
N
N
N
N
N
N
N
16
F
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
32
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Memory Disambiguation
A load operation may depend on a preceding store. Many microarchitectures block loads until all
preceding store addresses are known. The memory disambiguator predicts which loads will not depend
on any previous stores. When the disambiguator predicts that a load does not have such a dependency,
the load takes its data from the L1 data cache even when the store address is unknown. This hides the
load latency. Eventually, the prediction is verified. If an actual conflict is detected, the load and all
succeeding instructions are re-executed.
The following loads are not disambiguated. The execution of these loads is stalled until addresses of all
previous stores are known.
•
•
Loads that cross the 16-byte boundary
32-byte Intel AVX loads that are not 32-byte aligned.
The memory disambiguator always assumes dependency between loads and earlier stores that have the
same address bits 0:11.
Bank Conflict
Since 16-byte loads can cover up to three banks, and two loads can happen every cycle, it is possible that
six of the eight banks may be accessed per cycle, for loads. A bank conflict happens when two load
accesses need the same bank (their address has the same 2-4 bit value) in different sets, at the same
time. When a bank conflict occurs, one of the load accesses is recycled internally.
In many cases two loads access exactly the same bank in the same cache line, as may happen when
popping operands off the stack, or any sequential accesses. In these cases, conflict does not occur and
the loads are serviced simultaneously.
2-34
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.4.5.3
Ring Interconnect and Last Level Cache
The system-on-a-chip design provides a high bandwidth bi-directional ring bus to connect between the
IA cores and various sub-systems in the uncore. In the second generation Intel Core processor 2xxx
series, the uncore subsystem include a system agent, the graphics unit (GT) and the last level cache
(LLC).
The LLC consists of multiple cache slices. The number of slices is equal to the number of IA cores. Each
slice has logic portion and data array portion. The logic portion handles data coherency, memory
ordering, access to the data array portion, LLC misses and writeback to memory, and more. The data
array portion stores cache lines. Each slice contains a full cache port that can supply 32 bytes/cycle.
The physical addresses of data kept in the LLC data arrays are distributed among the cache slices by a
hash function, such that addresses are uniformly distributed. The data array in a cache block may have
4/8/12/16 ways corresponding to 0.5M/1M/1.5M/2M block size. However, due to the address distribution
among the cache blocks from the software point of view, this does not appear as a normal N-way cache.
From the processor cores and the GT view, the LLC act as one shared cache with multiple ports and bandwidth that scales with the number of cores. The LLC hit latency, ranging between 26-31 cycles, depends
on the core location relative to the LLC block, and how far the request needs to travel on the ring.
The number of cache-slices increases with the number of cores, therefore the ring and LLC are not likely
to be a bandwidth limiter to core operation.
The GT sits on the same ring interconnect, and uses the LLC for its data operations as well. In this respect
it is very similar to an IA core. Therefore, high bandwidth graphic applications using cache bandwidth and
significant cache footprint, can interfere, to some extent, with core operations.
All the traffic that cannot be satisfied by the LLC, such as LLC misses, dirty line writeback, non-cacheable
operations, and MMIO/IO operations, still travels through the cache-slice logic portion and the ring, to
the system agent.
In the Intel Xeon Processor E5 Family, the uncore subsystem does not include the graphics unit (GT).
Instead, the uncore subsystem contains many more components, including an LLC with larger capacity
and snooping capabilities to support multiple processors, Intel® QuickPath Interconnect interfaces that
can support multi-socket platforms, power management control hardware, and a system agent capable
of supporting high-bandwidth traffic from memory and I/O devices.
In the Intel Xeon processor E5 2xxx or 4xxx families, the LLC capacity generally scales with the number
of processor cores with 2.5 MBytes per core.
2.4.5.4
Data Prefetching
Data can be speculatively loaded to the L1 DCache using software prefetching, hardware prefetching, or
any combination of the two.
You can use the four Streaming SIMD Extensions (SSE) prefetch instructions to enable softwarecontrolled prefetching. These instructions are hints to bring a cache line of data into the desired levels of
the cache hierarchy. The software-controlled prefetch is intended for prefetching data, but not for
prefetching code.
The rest of this section describes the various hardware prefetching mechanisms provided by Intel microarchitecture code name Sandy Bridge and their improvement over previous processors. The goal of the
prefetchers is to automatically predict which data the program is about to consume. If this data is not
close-by to the execution core or inner cache, the prefetchers bring it from the next levels of cache hierarchy and memory. Prefetching has the following effects:
•
•
Improves performance if data is arranged sequentially in the order used in the program.
•
On rare occasions, if the algorithm's working set is tuned to occupy most of the cache and unneeded
prefetches evict lines required by the program, hardware prefetcher may cause severe performance
degradation due to cache capacity of L1.
May cause slight performance degradation due to bandwidth issues, if access patterns are sparse
instead of local.
2-35
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Data Prefetch to L1 Data Cache
Data prefetching is triggered by load operations when the following conditions are met:
•
•
•
•
•
Load is from writeback memory type.
The prefetched data is within the same 4K byte page as the load instruction that triggered it.
No fence is in progress in the pipeline.
Not many other load misses are in progress.
There is not a continuous stream of stores.
Two hardware prefetchers load data to the L1 DCache:
•
Data cache unit (DCU) prefetcher. This prefetcher, also known as the streaming prefetcher, is
triggered by an ascending access to very recently loaded data. The processor assumes that this
access is part of a streaming algorithm and automatically fetches the next line.
•
Instruction pointer (IP)-based stride prefetcher. This prefetcher keeps track of individual load
instructions. If a load instruction is detected to have a regular stride, then a prefetch is sent to the
next address which is the sum of the current address and the stride. This prefetcher can prefetch
forward or backward and can detect strides of up to 2K bytes.
Data Prefetch to the L2 and Last Level Cache
The following two hardware prefetchers fetched data from memory to the L2 cache and last level cache:
Spatial Prefetcher: This prefetcher strives to complete every cache line fetched to the L2 cache with
the pair line that completes it to a 128-byte aligned chunk.
Streamer: This prefetcher monitors read requests from the L1 cache for ascending and descending
sequences of addresses. Monitored read requests include L1 DCache requests initiated by load and store
operations and by the hardware prefetchers, and L1 ICache requests for code fetch. When a forward or
backward stream of requests is detected, the anticipated cache lines are prefetched. Prefetched cache
lines must be in the same 4K page.
The streamer and spatial prefetcher prefetch the data to the last level cache. Typically data is brought
also to the L2 unless the L2 cache is heavily loaded with missing demand requests.
Enhancement to the streamer includes the following features:
•
The streamer may issue two prefetch requests on every L2 lookup. The streamer can run up to 20
lines ahead of the load request.
•
Adjusts dynamically to the number of outstanding requests per core. If there are not many
outstanding requests, the streamer prefetches further ahead. If there are many outstanding
requests it prefetches to the LLC only and less far ahead.
•
When cache lines are far ahead, it prefetches to the last level cache only and not to the L2. This
method avoids replacement of useful cache lines in the L2 cache.
•
Detects and maintains up to 32 streams of data accesses. For each 4K byte page, you can maintain
one forward and one backward stream can be maintained.
2.4.6
System Agent
The system agent implemented in the second generation Intel Core processor family contains the
following components:
•
An arbiter that handles all accesses from the ring domain and from I/O (PCIe* and DMI) and routes
the accesses to the right place.
•
PCIe controllers connect to external PCIe devices. The PCIe controllers have different configuration
possibilities the varies with product segment specifics: x16+x4, x8+x8+x4, x8+x4+x4+x4.
•
•
DMI controller connects to the PCH chipset.
Integrated display engine, Flexible Display Interconnect, and Display Port, for the internal graphic
operations.
2-36
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
Memory controller.
All main memory traffic is routed from the arbiter to the memory controller. The memory controller in the
second generation Intel Core processor 2xxx series support two channels of DDR, with data rates of
1066MHz, 1333MHz and 1600MHz, and 8 bytes per cycle, depending on the unit type, system configuration and DRAMs. Addresses are distributed between memory channels based on a local hash function
that attempts to balance the load between the channels in order to achieve maximum bandwidth and
minimum hotspot collisions.
For best performance, populate both channels with equal amounts of memory, preferably the exact same
types of DIMMs. In addition, using more ranks for the same amount of memory, results in somewhat
better memory bandwidth, since more DRAM pages can be open simultaneously. For best performance,
populate the system with the highest supported speed DRAM (1333MHz or 1600MHz data rates,
depending on the max supported frequency) with the best DRAM timings.
The two channels have separate resources and handle memory requests independently. The memory
controller contains a high-performance out-of-order scheduler that attempts to maximize memory bandwidth while minimizing latency. Each memory channel contains a 32 cache-line write-data-buffer. Writes
to the memory controller are considered completed when they are written to the write-data-buffer. The
write-data-buffer is flushed out to main memory at a later time, not impacting write latency.
Partial writes are not handled efficiently on the memory controller and may result in read-modify-write
operations on the DDR channel if the partial-writes do not complete a full cache-line in time. Software
should avoid creating partial write transactions whenever possible and consider alternative, such as buffering the partial writes into full cache line writes.
The memory controller also supports high-priority isochronous requests (such as USB isochronous, and
Display isochronous requests). High bandwidth of memory requests from the integrated display engine
takes up some of the memory bandwidth and impacts core access latency to some degree.
2.4.7
Intel® Microarchitecture Code Name Ivy Bridge
Third generation Intel Core processors are based on Intel microarchitecture code name Ivy Bridge. Most
of the features described in Section 2.4.1 - Section 2.4.6 also apply to Intel microarchitecture code name
Ivy Bridge. This section covers feature differences in microarchitecture that can affect coding and performance.
Support for new instructions enabling include:
•
•
•
Numeric conversion to and from half-precision floating-point values.
Hardware-based random number generator compliant to NIST SP 800-90A.
Reading and writing to FS/GS base registers in any ring to improve user-mode threading support.
For details about using the hardware based random number generator instruction RDRAND, please refer
to the article available from Intel Software Network at https://software.intel.com/en-us/articles/inteldigital-random-number-generator-drng-software-implementation-guide/.
A small number of microarchitectural enhancements that can be beneficial to software:
•
Hardware prefetch enhancement: A next-page prefetcher (NPP) is added in Intel microarchitecture
code name Ivy Bridge. The NPP is triggered by sequential accesses to cache lines approaching the
page boundary, either upwards or downwards.
•
Zero-latency register move operation: A subset of register-to-register MOV instructions are executed
at the front end, conserving scheduling and execution resource in the out-of-order engine.
•
Front end enhancement: In Intel microarchitecture code name Sandy Bridge, the micro-op queue is
statically partitioned to provide 28 entries for each logical processor, irrespective of software
executing in single thread or multiple threads. If one logical processor is not active in Intel microarchitecture code name Ivy Bridge, then a single thread executing on that processor core can use the
56 entries in the micro-op queue. In this case, the LSD can handle larger loop structure that would
require more than 28 entries.
2-37
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
The latency and throughput of some instructions have been improved over those of Intel microarchitecture code name Sandy Bridge. For example, 256-bit packed floating-point divide and square root
operations are faster; ROL and ROR instructions are also improved.
2.5
INTEL® CORE™ MICROARCHITECTURE AND ENHANCED INTEL®
CORE™ MICROARCHITECTURE
Intel Core microarchitecture introduces the following features that enable high performance and powerefficient performance for single-threaded as well as multi-threaded workloads:
•
Intel® Wide Dynamic Execution enables each processor core to fetch, dispatch, execute with high
bandwidths and retire up to four instructions per cycle. Features include:
— Fourteen-stage efficient pipeline.
— Three arithmetic logical units.
— Four decoders to decode up to five instruction per cycle.
— Macro-fusion and micro-fusion to improve front end throughput.
— Peak issue rate of dispatching up to six micro-ops per cycle.
— Peak retirement bandwidth of up to four micro-ops per cycle.
— Advanced branch prediction.
— Stack pointer tracker to improve efficiency of executing function/procedure entries and exits.
•
Intel® Advanced Smart Cache delivers higher bandwidth from the second level cache to the core,
optimal performance and flexibility for single-threaded and multi-threaded applications. Features
include:
— Optimized for multicore and single-threaded execution environments.
— 256 bit internal data path to improve bandwidth from L2 to first-level data cache.
— Unified, shared second-level cache of 4 Mbyte, 16 way (or 2 MByte, 8 way).
•
Intel® Smart Memory Access prefetches data from memory in response to data access patterns
and reduces cache-miss exposure of out-of-order execution. Features include:
— Hardware prefetchers to reduce effective latency of second-level cache misses.
— Hardware prefetchers to reduce effective latency of first-level data cache misses.
— Memory disambiguation to improve efficiency of speculative execution engine.
•
Intel® Advanced Digital Media Boost improves most 128-bit SIMD instructions with single-cycle
throughput and floating-point operations. Features include:
— Single-cycle throughput of most 128-bit SIMD instructions (except 128-bit shuffle, pack, unpack
operations)
— Up to eight floating-point operations per cycle
— Three issue ports available to dispatching SIMD instructions for execution.
The Enhanced Intel Core microarchitecture supports all of the features of Intel Core microarchitecture
and provides a comprehensive set of enhancements.
•
Intel® Wide Dynamic Execution includes several enhancements:
— A radix-16 divider replacing previous radix-4 based divider to speedup long-latency operations
such as divisions and square roots.
— Improved system primitives to speedup long-latency operations such as RDTSC, STI, CLI, and VM
exit transitions.
•
Intel® Advanced Smart Cache provides up to 6 MBytes of second-level cache shared between two
processor cores (quad-core processors have up to 12 MBytes of L2); up to 24 way/set associativity.
2-38
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
Intel® Smart Memory Access supports high-speed system bus up 1600 MHz and provides more
efficient handling of memory operations such as split cache line load and store-to-load forwarding
situations.
•
Intel® Advanced Digital Media Boost provides 128-bit shuffler unit to speedup shuffle, pack,
unpack operations; adds support for 47 SSE4.1 instructions.
In the sub-sections of 2.1.x, most of the descriptions on Intel Core microarchitecture also applies to
Enhanced Intel Core microarchitecture. Differences between them are note explicitly.
2.5.1
Intel® Core™ Microarchitecture Pipeline Overview
The pipeline of the Intel Core microarchitecture contains:
•
An in-order issue front end that fetches instruction streams from memory, with four instruction
decoders to supply decoded instruction (micro-ops) to the out-of-order execution core.
•
An out-of-order superscalar execution core that can issue up to six micro-ops per cycle (see
Table 2-27) and reorder micro-ops to execute as soon as sources are ready and execution resources
are available.
•
An in-order retirement unit that ensures the results of execution of micro-ops are processed and
architectural states are updated according to the original program order.
Intel Core 2 Extreme processor X6800, Intel Core 2 Duo processors and Intel Xeon processor 3000, 5100
series implement two processor cores based on the Intel Core microarchitecture. Intel Core 2 Extreme
quad-core processor, Intel Core 2 Quad processors and Intel Xeon processor 3200 series, 5300 series
implement four processor cores. Each physical package of these quad-core processors contains two
processor dies, each die containing two processor cores. The functionality of the subsystems in each core
are depicted in Figure 2-8.
Instruction Fetch and P reD ecode
Instruction Q ueue
M icrocode
ROM
D ecode
Shared L2 C ache
U p to 10.7 G B/s
FS B
R enam e/Alloc
R etirem ent U nit
(R e-O rder B uffer)
Scheduler
ALU
B ranch
M M X/SS E/FP
M ove
ALU
FAdd
M M X /SSE
ALU
FM ul
M M X/S SE
Load
Store
L1D C ache and D TLB
O M 198 08
Figure 2-8. Intel Core Microarchitecture Pipeline Functionality
2-39
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.5.2
Front End
The front ends needs to supply decoded instructions (micro-ops) and sustain the stream to a six-issue
wide out-of-order engine. The components of the front end, their functions, and the performance challenges to microarchitectural design are described in Table 2-26.
Table 2-26. Components of the Front End
Component
Functions
Performance Challenges
Branch Prediction Unit
(BPU)
•
Helps the instruction fetch unit fetch the
most likely instruction to be executed by
predicting the various branch types:
conditional, indirect, direct, call, and
return. Uses dedicated hardware for each
type.
•
•
Enables speculative execution.
Improves speculative execution
efficiency by reducing the amount of
code in the “non-architected path”1
to be fetched into the pipeline.
Instruction Fetch Unit
•
Prefetches instructions that are likely to
be executed
Caches frequently-used instructions
Predecodes and buffers instructions,
maintaining a constant bandwidth despite
irregularities in the instruction stream
•
Variable length instruction format
causes unevenness (bubbles) in
decode bandwidth.
Taken branches and misaligned
targets causes disruptions in the
overall bandwidth delivered by the
fetch unit.
Decodes up to four instructions, or up to
five with macro-fusion
Stack pointer tracker algorithm for
efficient procedure entry and exit
Implements the Macro-Fusion feature,
providing higher performance and
efficiency
The Instruction Queue is also used as a
loop cache, enabling some loops to be
executed with both higher bandwidth
and lower power
•
•
•
Instruction Queue and
Decode Unit
•
•
•
•
•
•
•
Varying amounts of work per
instruction requires expansion into
variable numbers of micro-ops.
Prefix adds a dimension of decoding
complexity.
Length Changing Prefix (LCP) can
cause front end bubbles.
NOTES:
1. Code paths that the processor thought it should execute but then found out it should go in another path and therefore
reverted from its initial intention.
2.5.2.1
Branch Prediction Unit
Branch prediction enables the processor to begin executing instructions long before the branch outcome
is decided. All branches utilize the BPU for prediction. The BPU contains the following features:
•
•
16-entry Return Stack Buffer (RSB). It enables the BPU to accurately predict RET instructions.
Front end queuing of BPU lookups. The BPU makes branch predictions for 32 bytes at a time, twice
the width of the fetch engine. This enables taken branches to be predicted with no penalty.
Even though this BPU mechanism generally eliminates the penalty for taken branches, software
should still regard taken branches as consuming more resources than do not-taken branches.
The BPU makes the following types of predictions:
•
Direct Calls and Jumps. Targets are read as a target array, without regarding the taken or not-taken
prediction.
•
Indirect Calls and Jumps. These may either be predicted as having a monotonic target or as having
targets that vary in accordance with recent program behavior.
•
Conditional branches. Predicts the branch target and whether or not the branch will be taken.
For information about optimizing software for the BPU, see Section 3.4, “Optimizing the Front End.”
2-40
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.5.2.2
Instruction Fetch Unit
The instruction fetch unit comprises the instruction translation lookaside buffer (ITLB), an instruction
prefetcher, the instruction cache and the predecode logic of the instruction queue (IQ).
Instruction Cache and ITLB
An instruction fetch is a 16-byte aligned lookup through the ITLB into the instruction cache and instruction prefetch buffers. A hit in the instruction cache causes 16 bytes to be delivered to the instruction
predecoder. Typical programs average slightly less than 4 bytes per instruction, depending on the code
being executed. Since most instructions can be decoded by all decoders, an entire fetch can often be
consumed by the decoders in one cycle.
A misaligned target reduces the number of instruction bytes by the amount of offset into the 16 byte
fetch quantity. A taken branch reduces the number of instruction bytes delivered to the decoders since
the bytes after the taken branch are not decoded. Branches are taken approximately every 10 instructions in typical integer code, which translates into a “partial” instruction fetch every 3 or 4 cycles.
Due to stalls in the rest of the machine, front end starvation does not usually cause performance degradation. For extremely fast code with larger instructions (such as SSE2 integer media kernels), it may be
beneficial to use targeted alignment to prevent instruction starvation.
Instruction PreDecode
The predecode unit accepts the sixteen bytes from the instruction cache or prefetch buffers and carries
out the following tasks:
•
•
•
Determine the length of the instructions.
Decode all prefixes associated with instructions.
Mark various properties of instructions for the decoders (for example, “is branch.”).
The predecode unit can write up to six instructions per cycle into the instruction queue. If a fetch contains
more than six instructions, the predecoder continues to decode up to six instructions per cycle until all
instructions in the fetch are written to the instruction queue. Subsequent fetches can only enter predecoding after the current fetch completes.
For a fetch of seven instructions, the predecoder decodes the first six in one cycle, and then only one in
the next cycle. This process would support decoding 3.5 instructions per cycle. Even if the instruction per
cycle (IPC) rate is not fully optimized, it is higher than the performance seen in most applications. In
general, software usually does not have to take any extra measures to prevent instruction starvation.
The following instruction prefixes cause problems during length decoding. These prefixes can dynamically change the length of instructions and are known as length changing prefixes (LCPs):
•
•
Operand Size Override (66H) preceding an instruction with a word immediate data.
Address Size Override (67H) preceding an instruction with a mod R/M in real, 16-bit protected or 32bit protected modes.
When the predecoder encounters an LCP in the fetch line, it must use a slower length decoding algorithm.
With the slower length decoding algorithm, the predecoder decodes the fetch in 6 cycles, instead of the
usual 1 cycle.
Normal queuing within the processor pipeline usually cannot hide LCP penalties.
The REX prefix (4xh) in the Intel 64 architecture instruction set can change the size of two classes of
instruction: MOV offset and MOV immediate. Nevertheless, it does not cause an LCP penalty and hence is
not considered an LCP.
2.5.2.3
Instruction Queue (IQ)
The instruction queue is 18 instructions deep. It sits between the instruction predecode unit and the
instruction decoders. It sends up to five instructions per cycle, and supports one macro-fusion per cycle.
It also serves as a loop cache for loops smaller than 18 instructions. The loop cache operates as described
below.
2-41
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
A Loop Stream Detector (LSD) resides in the BPU. The LSD attempts to detect loops which are candidates
for streaming from the instruction queue (IQ). When such a loop is detected, the instruction bytes are
locked down and the loop is allowed to stream from the IQ until a misprediction ends it. When the loop
plays back from the IQ, it provides higher bandwidth at reduced power (since much of the rest of the
front end pipeline is shut off).
The LSD provides the following benefits:
•
•
•
•
No loss of bandwidth due to taken branches.
No loss of bandwidth due to misaligned instructions.
No LCP penalties, as the pre-decode stage has already been passed.
Reduced front end power consumption, because the instruction cache, BPU and predecode unit can
be idle.
Software should use the loop cache functionality opportunistically. Loop unrolling and other code optimizations may make the loop too big to fit into the LSD. For high performance code, loop unrolling is generally preferable for performance even when it overflows the loop cache capability.
2.5.2.4
Instruction Decode
The Intel Core microarchitecture contains four instruction decoders. The first, Decoder 0, can decode
Intel 64 and IA-32 instructions up to 4 micro-ops in size. Three other decoders handle single micro-op
instructions. The microsequencer can provide up to 3 micro-ops per cycle, and helps decode instructions
larger than 4 micro-ops.
All decoders support the common cases of single micro-op flows, including: micro-fusion, stack pointer
tracking and macro-fusion. Thus, the three simple decoders are not limited to decoding single micro-op
instructions. Packing instructions into a 4-1-1-1 template is not necessary and not recommended.
Macro-fusion merges two instructions into a single micro-op. Intel Core microarchitecture is capable of
one macro-fusion per cycle in 32-bit operation (including compatibility sub-mode of the Intel 64 architecture), but not in 64-bit mode because code that uses longer instructions (length in bytes) more often is
less likely to take advantage of hardware support for macro-fusion.
2.5.2.5
Stack Pointer Tracker
The Intel 64 and IA-32 architectures have several commonly used instructions for parameter passing and
procedure entry and exit: PUSH, POP, CALL, LEAVE and RET. These instructions implicitly update the
stack pointer register (RSP), maintaining a combined control and parameter stack without software
intervention. These instructions are typically implemented by several micro-ops in previous microarchitectures.
The Stack Pointer Tracker moves all these implicit RSP updates to logic contained in the decoders themselves. The feature provides the following benefits:
•
Improves decode bandwidth, as PUSH, POP and RET are single micro-op instructions in Intel Core
microarchitecture.
•
•
Conserves execution bandwidth as the RSP updates do not compete for execution resources.
•
Improves power efficiency as the RSP updates are carried out on small, dedicated hardware.
Improves parallelism in the out of order execution engine as the implicit serial dependencies between
micro-ops are removed.
2.5.2.6
Micro-fusion
Micro-fusion fuses multiple micro-ops from the same instruction into a single complex micro-op. The
complex micro-op is dispatched in the out-of-order execution core. Micro-fusion provides the following
performance advantages:
•
Improves instruction bandwidth delivered from decode to retirement.
2-42
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
Reduces power consumption as the complex micro-op represents more work in a smaller format (in
terms of bit density), reducing overall “bit-toggling” in the machine for a given amount of work and
virtually increasing the amount of storage in the out-of-order execution engine.
Many instructions provide register flavors and memory flavors. The flavor involving a memory operand
will decodes into a longer flow of micro-ops than the register version. Micro-fusion enables software to
use memory to register operations to express the actual program behavior without worrying about a loss
of decode bandwidth.
2.5.3
Execution Core
The execution core of the Intel Core microarchitecture is superscalar and can process instructions out of
order. When a dependency chain causes the machine to wait for a resource (such as a second-level data
cache line), the execution core executes other instructions. This increases the overall rate of instructions
executed per cycle (IPC).
The execution core contains the following three major components:
•
Renamer — Moves micro-ops from the front end to the execution core. Architectural registers are
renamed to a larger set of microarchitectural registers. Renaming eliminates false dependencies
known as read-after-read and write-after-read hazards.
•
Reorder buffer (ROB) — Holds micro-ops in various stages of completion, buffers completed microops, updates the architectural state in order, and manages ordering of exceptions. The ROB has 96
entries to handle instructions in flight.
•
Reservation station (RS) — Queues micro-ops until all source operands are ready, schedules and
dispatches ready micro-ops to the available execution units. The RS has 32 entries.
The initial stages of the out of order core move the micro-ops from the front end to the ROB and RS. In
this process, the out of order core carries out the following steps:
•
•
•
•
Allocates resources to micro-ops (for example: these resources could be load or store buffers).
Binds the micro-op to an appropriate issue port.
Renames sources and destinations of micro-ops, enabling out of order execution.
Provides data to the micro-op when the data is either an immediate value or a register value that has
already been calculated.
The following list describes various types of common operations and how the core executes them efficiently:
•
Micro-ops with single-cycle latency — Most micro-ops with single-cycle latency can be executed
by multiple execution units, enabling multiple streams of dependent operations to be executed
quickly.
•
Frequently-used μops with longer latency — These micro-ops have pipelined execution units so
that multiple micro-ops of these types may be executing in different parts of the pipeline simultaneously.
•
Operations with data-dependent latencies — Some operations, such as division, have data
dependent latencies. Integer division parses the operands to perform the calculation only on
significant portions of the operands, thereby speeding up common cases of dividing by small
numbers.
•
Floating-point operations with fixed latency for operands that meet certain restrictions —
Operands that do not fit these restrictions are considered exceptional cases and are executed with
higher latency and reduced throughput. The lower-throughput cases do not affect latency and
throughput for more common cases.
•
Memory operands with variable latency, even in the case of an L1 cache hit — Loads that are
not known to be safe from forwarding may wait until a store-address is resolved before executing.
The memory order buffer (MOB) accepts and processes all memory operations. See Section 2.5.4 for
more information about the MOB.
2-43
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.5.3.1
Issue Ports and Execution Units
The scheduler can dispatch up to six micro-ops per cycle through the issue ports. The issue ports of Intel
Core microarchitecture and Enhanced Intel Core microarchitecture are depicted in Table 2-27, the former
is denoted by its CPUID signature of DisplayFamily_DisplayModel value of 06_0FH, the latter denoted by
the corresponding signature value of 06_17H. The table provides latency and throughput data of
common integer and floating-point (FP) operations for each issue port in cycles.
Table 2-27. Issue Ports of Intel Core Microarchitecture and Enhanced Intel Core Microarchitecture
Executable operations
Latency, Throughput
Comment1
Signature =
06_0FH
Signature =
06_17H
Integer ALU
1, 1
1, 1
Includes 64-bit mode integer MUL;
Integer SIMD ALU
1, 1
1, 1
Issue port 0; Writeback port 0;
FP/SIMD/SSE2 Move and Logic
1, 1
1, 1
Single-precision (SP) FP MUL
4, 1
4, 1
Issue port 0; Writeback port 0
Double-precision FP MUL
5, 1
5, 1
FP MUL (X87)
5, 2
5, 2
Issue port 0; Writeback port 0
FP Shuffle
1, 1
1, 1
FP shuffle does not handle QW shuffle.
Integer ALU
1, 1
1, 1
Excludes 64-bit mode integer MUL;
Integer SIMD ALU
1, 1
1, 1
Issue port 1; Writeback port 1;
FP/SIMD/SSE2 Move and Logic
1, 1
1, 1
FP ADD
3, 1
3, 1
QW Shuffle
1, 12
1, 13
Integer loads
3, 1
3, 1
FP loads
4, 1
4, 1
Store address4
3, 1
3, 1
DIV/SQRT
Store data
5.
Issue port 2; Writeback port 2;
Issue port 3;
Issue Port 4;
Integer ALU
1, 1
1, 1
Integer SIMD ALU
1, 1
1, 1
FP/SIMD/SSE2 Move and Logic
1, 1
1, 1
QW shuffles
1, 12
128-bit Shuffle/Pack/Unpack
Issue port 1; Writeback port 1;
2-4,
2-46
1, 13
Issue port 5; Writeback port 5;
Issue port 5; Writeback port 5;
1-3, 17
NOTES:
1. Mixing operations of different latencies that use the same port can result in writeback bus conflicts; this can reduce overall throughput.
2. 128-bit instructions executes with longer latency and reduced throughput.
3. Uses 128-bit shuffle unit in port 5.
4. Prepares the store forwarding and store retirement logic with the address of the data being stored.
5. Prepares the store forwarding and store retirement logic with the data being stored.
6. Varies with instructions; 128-bit instructions are executed using QW shuffle units.
7. Varies with instructions, 128-bit shuffle unit replaces QW shuffle units in Intel Core microarchitecture.
In each cycle, the RS can dispatch up to six micro-ops. Each cycle, up to 4 results may be written back to
the RS and ROB, to be used as early as the next cycle by the RS. This high execution bandwidth enables
execution bursts to keep up with the functional expansion of the micro-fused micro-ops that are decoded
and retired.
2-44
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The execution core contains the following three execution stacks:
•
•
•
SIMD integer.
Regular integer.
x87/SIMD floating-point.
The execution core also contains connections to and from the memory cluster. See Figure 2-9.
EXE
Data Cache
Unit
0,1,5
SIMD
Integer
Integer/
SIMD
MUL
0,1,5
0,1,5
Integer
Floating
Point
dtlb
Memory ordering
store forwarding
Load
2
Store (address)
3
Store (data)
4
Figure 2-9. Execution Core of Intel Core Microarchitecture
Notice that the two dark squares inside the execution block (in grey color) and appear in the path
connecting the integer and SIMD integer stacks to the floating-point stack. This delay shows up as an
extra cycle called a bypass delay. Data from the L1 cache has one extra cycle of latency to the floatingpoint unit. The dark-colored squares in Figure 2-9 represent the extra cycle of latency.
2.5.4
Intel® Advanced Memory Access
The Intel Core microarchitecture contains an instruction cache and a first-level data cache in each core.
The two cores share a 2 or 4-MByte L2 cache. All caches are writeback and non-inclusive. Each core
contains:
•
L1 data cache, known as the data cache unit (DCU) — The DCU can handle multiple outstanding
cache misses and continue to service incoming stores and loads. It supports maintaining cache
coherency. The DCU has the following specifications:
— 32-KBytes size.
— 8-way set associative.
— 64-bytes line size.
•
Data translation lookaside buffer (DTLB) — The DTLB in Intel Core microarchitecture
implements two levels of hierarchy. Each level of the DTLB have multiple entries and can support
either 4-KByte pages or large pages. The entries of the inner level (DTLB0) is used for loads. The
entries in the outer level (DTLB1) support store operations and loads that missed DTLB0. All entries
are 4-way associative. Here is a list of entries in each DTLB:
2-45
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
— DTLB1 for large pages: 32 entries.
— DTLB1 for 4-KByte pages: 256 entries.
— DTLB0 for large pages: 16 entries.
— DTLB0 for 4-KByte pages: 16 entries.
An DTLB0 miss and DTLB1 hit causes a penalty of 2 cycles. Software only pays this penalty if the
DTLB0 is used in some dispatch cases. The delays associated with a miss to the DTLB1 and PMH are
largely non-blocking due to the design of Intel Smart Memory Access.
•
•
Page miss handler (PMH)
A memory ordering buffer (MOB) — Which:
— Enables loads and stores to issue speculatively and out of order.
— Ensures retired loads and stores have the correct data upon retirement.
— Ensures loads and stores follow memory ordering rules of the Intel 64 and IA-32 architectures.
The memory cluster of the Intel Core microarchitecture uses the following to speed up memory operations:
•
•
•
•
•
•
•
•
•
128-bit load and store operations.
Data prefetching to L1 caches.
Data prefetch logic for prefetching to the L2 cache.
Store forwarding.
Memory disambiguation.
8 fill buffer entries.
20 store buffer entries.
Out of order execution of memory operations.
Pipelined read-for-ownership operation (RFO).
For information on optimizing software for the memory cluster, see Section 3.6, “Optimizing Memory
Accesses.”
2.5.4.1
Loads and Stores
The Intel Core microarchitecture can execute up to one 128-bit load and up to one 128-bit store per
cycle, each to different memory locations. The microarchitecture enables execution of memory operations out of order with respect to other instructions and with respect to other memory operations.
Loads can:
•
•
•
•
Issue before preceding stores when the load address and store address are known not to conflict.
Be carried out speculatively, before preceding branches are resolved.
Take cache misses out of order and in an overlapped manner.
Issue before preceding stores, speculating that the store is not going to be to a conflicting address.
Loads cannot:
•
•
Speculatively take any sort of fault or trap.
Speculatively access the uncacheable memory type.
Faulting or uncacheable loads are detected and wait until retirement, when they update the programmer
visible state. x87 and floating-point SIMD loads add 1 additional clock latency.
Stores to memory are executed in two phases:
•
Execution phase — Prepares the store buffers with address and data for store forwarding.
Consumes dispatch ports, which are ports 3 and 4.
2-46
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
Completion phase — The store is retired to programmer-visible memory. It may compete for cache
banks with executing loads. Store retirement is maintained as a background task by the memory
order buffer, moving the data from the store buffers to the L1 cache.
2.5.4.2
Data Prefetch to L1 caches
Intel Core microarchitecture provides two hardware prefetchers to speed up data accessed by a program
by prefetching to the L1 data cache:
•
Data cache unit (DCU) prefetcher — This prefetcher, also known as the streaming prefetcher, is
triggered by an ascending access to very recently loaded data. The processor assumes that this
access is part of a streaming algorithm and automatically fetches the next line.
•
Instruction pointer (IP)- based strided prefetcher — This prefetcher keeps track of individual
load instructions. If a load instruction is detected to have a regular stride, then a prefetch is sent to
the next address which is the sum of the current address and the stride. This prefetcher can prefetch
forward or backward and can detect strides of up to half of a 4KB-page, or 2 KBytes.
Data prefetching works on loads only when the following conditions are met:
•
•
•
•
•
•
Load is from writeback memory type.
Prefetch request is within the page boundary of 4 Kbytes.
No fence or lock is in progress in the pipeline.
Not many other load misses are in progress.
The bus is not very busy.
There is not a continuous stream of stores.
DCU Prefetching has the following effects:
•
Improves performance if data in large structures is arranged sequentially in the order used in the
program.
•
May cause slight performance degradation due to bandwidth issues if access patterns are sparse
instead of local.
•
On rare occasions, if the algorithm's working set is tuned to occupy most of the cache and unneeded
prefetches evict lines required by the program, hardware prefetcher may cause severe performance
degradation due to cache capacity of L1.
In contrast to hardware prefetchers relying on hardware to anticipate data traffic, software prefetch
instructions relies on the programmer to anticipate cache miss traffic, software prefetch act as hints to
bring a cache line of data into the desired levels of the cache hierarchy. The software-controlled prefetch
is intended for prefetching data, but not for prefetching code.
2.5.4.3
Data Prefetch Logic
Data prefetch logic (DPL) prefetches data to the second-level (L2) cache based on past request patterns
of the DCU from the L2. The DPL maintains two independent arrays to store addresses from the DCU: one
for upstreams (12 entries) and one for down streams (4 entries). The DPL tracks accesses to one 4K byte
page in each entry. If an accessed page is not in any of these arrays, then an array entry is allocated.
The DPL monitors DCU reads for incremental sequences of requests, known as streams. Once the DPL
detects the second access of a stream, it prefetches the next cache line. For example, when the DCU
requests the cache lines A and A+1, the DPL assumes the DCU will need cache line A+2 in the near
future. If the DCU then reads A+2, the DPL prefetches cache line A+3. The DPL works similarly for
“downward” loops.
The Intel Pentium M processor introduced DPL. The Intel Core microarchitecture added the following
features to DPL:
•
The DPL can detect more complicated streams, such as when the stream skips cache lines. DPL may
issue 2 prefetch requests on every L2 lookup. The DPL in the Intel Core microarchitecture can run up
to 8 lines ahead from the load request.
2-47
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
DPL in the Intel Core microarchitecture adjusts dynamically to bus bandwidth and the number of
requests. DPL prefetches far ahead if the bus is not busy, and less far ahead if the bus is busy.
•
DPL adjusts to various applications and system configurations.
Entries for the two cores are handled separately.
2.5.4.4
Store Forwarding
If a load follows a store and reloads the data that the store writes to memory, the Intel Core microarchitecture can forward the data directly from the store to the load. This process, called store to load
forwarding, saves cycles by enabling the load to obtain the data directly from the store operation instead
of through memory.
The following rules must be met for store to load forwarding to occur:
•
•
•
•
•
The store must be the last store to that address prior to the load.
The store must be equal or greater in size than the size of data being loaded.
The load cannot cross a cache line boundary.
The load cannot cross an 8-Byte boundary. 16-Byte loads are an exception to this rule.
The load must be aligned to the start of the store address, except for the following exceptions:
— An aligned 64-bit store may forward either of its 32-bit halves.
— An aligned 128-bit store may forward any of its 32-bit quarters.
— An aligned 128-bit store may forward either of its 64-bit halves.
Software can use the exceptions to the last rule to move complex structures without losing the ability to
forward the subfields.
In Enhanced Intel Core microarchitecture, the alignment restrictions to permit store forwarding to
proceed have been relaxed. Enhanced Intel Core microarchitecture permits store-forwarding to proceed
in several situations that the succeeding load is not aligned to the preceding store. Figure 2-10 shows six
situations (in gradient-filled background) of store-forwarding that are permitted in Enhanced Intel Core
microarchitecture but not in Intel Core microarchitecture. The cases with backward slash background
depicts store-forwarding that can proceed in both Intel Core microarchitecture and Enhanced Intel Core
microarchitecture.
2-48
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
8 byte boundary
Byte 6
Byte 7
8 byte boundary
Store 32 bit
Load 32 bit
Load 16 bit
Example: 7 byte misalignment
Load 8
Load 16 bit
Load 8
Load 8
Load 8
Store 64 bit
Load 64 bit
Example: 1 byte misalignment
Load 32 bit
Load 16 bit
Load 8
Load 8
Load 32 bit
Load 16 bit
Load 8
Load 8
Load 16 bit
Load 8
Load 8
Load 16 bit
Load 8
Load 8
Store 64 bit
Load 64 bit
Store
Load 32 bit
Load 16 bit
Load 8
Load 8
Load 32 bit
Load 16 bit
Load 8
Load 8
Load 16 bit
Load 8
Load 8
Store-forwarding (SF) can not proceed
Load 16 bit
Load 8
Load 8
SF proceed in Enhanced Intel Core microarchitectu
SF proceed
Figure 2-10. Store-Forwarding Enhancements in Enhanced Intel Core Microarchitecture
2.5.4.5
Memory Disambiguation
A load instruction micro-op may depend on a preceding store. Many microarchitectures block loads until
all preceding store address are known.
The memory disambiguator predicts which loads will not depend on any previous stores. When the
disambiguator predicts that a load does not have such a dependency, the load takes its data from the L1
data cache.
Eventually, the prediction is verified. If an actual conflict is detected, the load and all succeeding instructions are re-executed.
2.5.5
Intel® Advanced Smart Cache
The Intel Core microarchitecture optimized a number of features for two processor cores on a single die.
The two cores share a second-level cache and a bus interface unit, collectively known as Intel Advanced
Smart Cache. This section describes the components of Intel Advanced Smart Cache. Figure 2-11 illustrates the architecture of the Intel Advanced Smart Cache.
2-49
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Core 1
Core 0
Branch
Prediction
Retirement
Fetch/
Decode
Execution
L1 Data
Cache
Branch
Prediction
Retirement
Fetch/
Decode
Execution
L1 Data
Cache
L1 Instr.
Cache
L1 Instr.
Cache
L2 Cache
Bus Interface Unit
System Bus
Figure 2-11. Intel Advanced Smart Cache Architecture
Table 2-28 details the parameters of caches in the Intel Core microarchitecture. For information on
enumerating the cache hierarchy identification using the deterministic cache parameter leaf of CPUID
instruction, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Table 2-28. Cache Parameters of Processors based on Intel Core Microarchitecture
Line Size
(bytes)
Access
Latency
(clocks)
Access
Throughput
(clocks)
Write Update
Policy
1
Writeback
Level
Capacity
Associativity
(ways)
First Level
32 KB
8
64
3
Instruction
32 KB
8
N/A
N/A
N/A
N/A
2
Second Level
(Shared L2)1
2, 4 MB
8 or 16
64
14
2
Writeback
Second Level
(Shared L2)3
3, 6MB
12 or 24
64
152
2
Writeback
Third Level4
8, 12, 16 MB 16
64
~110
12
Writeback
NOTES:
1. Intel Core microarchitecture (CPUID signature DisplayFamily = 06H, DisplayModel = 0FH).
2. Software-visible latency will vary depending on access patterns and other factors.
3. Enhanced Intel Core microarchitecture (CPUID signature DisaplyFamily = 06H, DisplayModel = 17H or 1DH).
4. Enhanced Intel Core microarchitecture (CPUID signature DisaplyFamily = 06H, DisplayModel = 1DH).
2-50
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.5.5.1
Loads
When an instruction reads data from a memory location that has write-back (WB) type, the processor
looks for the cache line that contains this data in the caches and memory in the following order:
1. DCU of the initiating core.
2. DCU of the other core and second-level cache.
3. System memory.
The cache line is taken from the DCU of the other core only if it is modified, ignoring the cache line availability or state in the L2 cache.
Table 2-29 shows the characteristics of fetching the first four bytes of different localities from the
memory cluster. The latency column provides an estimate of access latency. However, the actual latency
can vary depending on the load of cache, memory components, and their parameters.
Table 2-29. Characteristics of Load and Store Operations in Intel Core Microarchitecture
Data Locality
Load
Store
Latency
Throughput
Latency
Throughput
DCU
3
1
2
1
DCU of the other core in
modified state
14 + 5.5 bus cycles
14 + 5.5 bus cycles
14 + 5.5 bus cycles
2nd-level cache
14
3
14
3
Memory
14 + 5.5 bus cycles +
memory
Depends on bus read
protocol
14 + 5.5 bus cycles +
memory
Depends on bus
write protocol
Sometimes a modified cache line has to be evicted to make space for a new cache line. The modified
cache line is evicted in parallel to bringing the new data and does not require additional latency. However,
when data is written back to memory, the eviction uses cache bandwidth and possibly bus bandwidth as
well. Therefore, when multiple cache misses require the eviction of modified lines within a short time,
there is an overall degradation in cache response time.
2.5.5.2
Stores
When an instruction writes data to a memory location that has WB memory type, the processor first
ensures that the line is in Exclusive or Modified state in its own DCU. The processor looks for the cache
line in the following locations, in the specified order:
1. DCU of initiating core.
2. DCU of the other core and L2 cache.
3. System memory.
The cache line is taken from the DCU of the other core only if it is modified, ignoring the cache line availability or state in the L2 cache. After reading for ownership is completed, the data is written to the firstlevel data cache and the line is marked as modified.
Reading for ownership and storing the data happens after instruction retirement and follows the order of
retirement. Therefore, the store latency does not effect the store instruction itself. However, several
sequential stores may have cumulative latency that can affect performance. Table 2-29 presents store
latencies depending on the initial cache line location.
2-51
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.6
INTEL® MICROARCHITECTURE CODE NAME NEHALEM
Intel microarchitecture code name Nehalem provides the foundation for many innovative features of
Intel Core i7 processors and Intel Xeon processor 3400, 5500, and 7500 series. It builds on the success
of 45 nm enhanced Intel Core microarchitecture and provides the following feature enhancements:
•
Enhanced processor core
— Improved branch prediction and recovery from misprediction.
— Enhanced loop streaming to improve front end performance and reduce power consumption.
— Deeper buffering in out-of-order engine to extract parallelism.
— Enhanced execution units to provide acceleration in CRC, string/text processing and data
shuffling.
•
Hyper-Threading Technology
— Provides two hardware threads (logical processors) per core.
— Takes advantage of 4-wide execution engine, large L3, and massive memory bandwidth.
•
Smart Memory Access
— Integrated memory controller provides low-latency access to system memory and scalable
memory bandwidth.
— New cache hierarchy organization with shared, inclusive L3 to reduce snoop traffic.
— Two level TLBs and increased TLB size.
— Fast unaligned memory access.
•
Dedicated Power management Innovations
— Integrated microcontroller with optimized embedded firmware to manage power consumption.
— Embedded real-time sensors for temperature, current, and power.
— Integrated power gate to turn off/on per-core power consumption.
— Versatility to reduce power consumption of memory, link subsystems.
Intel microarchitecture code name Westmere is a 32 nm version of Intel microarchitecture code name
Nehalem. All of the features of latter also apply to the former.
2.6.1
Microarchitecture Pipeline
Intel microarchitecture code name Nehalem continues the four-wide microarchitecture pipeline
pioneered by the 65nm Intel Core microarchitecture. Figure 2-12 illustrates the basic components of the
pipeline of Intel microarchitecture code name Nehalem as implemented in Intel Core i7 processor, only
two of the four cores are sketched in the Figure 2-12 pipeline diagram.
2-52
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Instruction Fetch and
PreDecode
Instruction Fetch and
PreDecode
Instruction Queue
Instruction Queue
Microcode
ROM
Microcode
ROM
Decode
Decode
Rename/Alloc
Rename/Alloc
Retirement Unit
(Re-Order Buffer)
Retirement Unit
(Re-Order Buffer)
Scheduler
Scheduler
EXE
Unit
Cluster
0
EXE
Unit
Cluster
1
EXE
Unit
Cluster
5
Load
Stor
e
L1D Cache and DTLB
L2 Cache
EXE
Unit
Cluster
0
EXE
Unit
Cluster
1
EXE
Unit
Cluster
5
Stor
e
Load
L1D Cache and DTLB
L2 Cache
Other L2
Inclusive L3 Cache by all cores
OM19808p
Intel QPI Link Logic
Figure 2-12. Intel Microarchitecture Code Name Nehalem Pipeline Functionality
The length of the pipeline in Intel microarchitecture code name Nehalem is two cycles longer than its
predecessor in 45 nm Intel Core 2 processor family, as measured by branch misprediction delay. The
front end can decode up to 4 instructions in one cycle and supports two hardware threads by decoding
the instruction streams between two logical processors in alternate cycles. The front end includes
enhancement in branch handling, loop detection, MSROM throughput, etc. These are discussed in subsequent sections.
The scheduler (or reservation station) can dispatch up to six micro-ops in one cycle through six issue
ports (five issue ports are shown in Figure 2-12; store operation involves separate ports for store
address and store data but is depicted as one in the diagram).
The out-of-order engine has many execution units that are arranged in three execution clusters shown in
Figure 2-12. It can retire four micro-ops in one cycle, same as its predecessor.
2-53
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.6.2
Front End Overview
Figure 2-13 depicts the key components of the front end of the microarchitecture. The instruction fetch
unit (IFU) can fetch up to 16 bytes of aligned instruction bytes each cycle from the instruction cache to
the instruction length decoder (ILD). The instruction queue (IQ) buffers the ILD-processed instructions
and can deliver up to four instructions in one cycle to the instruction decoder.
MSROM
4 micro-ops per cycle
ICache
4
ILD
IDQ
4 micro-ops
per cycle
max
IQ
1
I Fetch U
1
Instr.
Length
Decoder
1
Instr. Queue
Instr. Decoder
Br. Predict U
LSD
Instr. Decoder
Queue
Figure 2-13. Front End of Intel Microarchitecture Code Name Nehalem
The instruction decoder has three decoder units that can decode one simple instruction per cycle per
unit. The other decoder unit can decode one instruction every cycle, either simple instruction or complex
instruction made up of several micro-ops. Instructions made up of more than four micro-ops are delivered from the MSROM. Up to four micro-ops can be delivered each cycle to the instruction decoder queue
(IDQ).
The loop stream detector is located inside the IDQ to improve power consumption and front end efficiency for loops with a short sequence of instructions.
The instruction decoder supports micro-fusion to improve front end throughput, increase the effective
size of queues in the scheduler and re-order buffer (ROB). The rules for micro-fusion are similar to those
of Intel Core microarchitecture.
The instruction queue also supports macro-fusion to combine adjacent instructions into one micro-ops
where possible. In previous generations of Intel Core microarchitecture, macro-fusion support for
CMP/Jcc sequence is limited to the CF and ZF flag, and macrofusion is not supported in 64-bit mode.
In Intel microarchitecture code name Nehalem , macro-fusion is supported in 64-bit mode, and the
following instruction sequences are supported:
•
CMP or TEST can be fused when comparing (unchanged):
REG-REG. For example: CMP EAX,ECX; JZ label
REG-IMM. For example: CMP EAX,0x80; JZ label
REG-MEM. For example: CMP EAX,[ECX]; JZ label
MEM-REG. For example: CMP [EAX],ECX; JZ label
•
TEST can fused with all conditional jumps (unchanged).
2-54
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
CMP can be fused with the following conditional jumps. These conditional jumps check carry flag (CF)
or zero flag (ZF). The list of macro-fusion-capable conditional jumps are (unchanged):
JA or JNBE
JAE or JNB or JNC
JE or JZ
JNA or JBE
JNAE or JC or JB
JNE or JNZ
•
CMP can be fused with the following conditional jumps in Intel microarchitecture code name
Nehalem, (this is an enhancement):
JL or JNGE
JGE or JNL
JLE or JNG
JG or JNLE
The hardware improves branch handling in several ways. Branch target buffer has increased to increase
the accuracy of branch predictions. Renaming is supported with return stack buffer to reduce mispredictions of return instructions in the code. Furthermore, hardware enhancement improves the handling of
branch misprediction by expediting resource reclamation so that the front end would not be waiting to
decode instructions in an architected code path (the code path in which instructions will reach retirement) while resources were allocated to executing mispredicted code path. Instead, new micro-ops
stream can start forward progress as soon as the front end decodes the instructions in the architected
code path.
2.6.3
Execution Engine
The IDQ (Figure 2-13) delivers micro-op stream to the allocation/renaming stage (Figure 2-12) of the
pipeline. The out-of-order engine supports up to 128 micro-ops in flight. Each micro-ops must be allocated with the following resources: an entry in the re-order buffer (ROB), an entry in the reservation
station (RS), and a load/store buffer if a memory access is required.
The allocator also renames the register file entry of each micro-op in flight. The input data associated
with a micro-op are generally either read from the ROB or from the retired register file.
The RS is expanded to 36 entry deep (compared to 32 entries in previous generation). It can dispatch up
to six micro-ops in one cycle if the micro-ops are ready to execute. The RS dispatch a micro-op through
an issue port to a specific execution cluster, each cluster may contain a collection of integer/FP/SIMD
execution units.
The result from the execution unit executing a micro-op is written back to the register file, or forwarded
through a bypass network to a micro-op in-flight that needs the result. Intel microarchitecture code
name Nehalem can support write back throughput of one register file write per cycle per port. The bypass
network consists of three domains of integer/FP/SIMD. Forwarding the result within the same bypass
domain from a producer micro-op to a consumer micro is done efficiently in hardware without delay.
Forwarding the result across different bypass domains may be subject to additional bypass delays. The
bypass delays may be visible to software in addition to the latency and throughput characteristics of individual execution units. The bypass delays between a producer micro-op and a consumer micro-op across
different bypass domains are shown in Table 2-30.
2-55
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-30. Bypass Delay Between Producer and Consumer Micro-ops (cycles)
FP
Integer
SIMD
FP
0
2
2
Integer
2
0
1
SIMD
2
1
0
2.6.3.1
Issue Ports and Execution Units
Table 2-31 summarizes the key characteristics of the issue ports and the execution unit latency/throughputs for common operations in the microarchitecture.
Table 2-31. Issue Ports of Intel Microarchitecture Code Name Nehalem
Port
Executable
operations
Latency
Throughpu
t
Domain
Port 0
Integer ALU
1
1
Integer
Integer Shift
1
1
Port 0
Port 0
Integer SIMD ALU
1
1
Integer SIMD Shuffle
1
1
Single-precision (SP)
FP MUL
4
1
Double-precision FP MUL
5
1
5
1
1
1
DIV/SQRT
1
1
FP MUL (X87)
FP/SIMD/SSE2 Move and
Logic
FP Shuffle
Port 1
Port 1
Integer ALU
1
1
Integer LEA
1
1
Integer Mul
3
1
Integer SIMD MUL
1
1
Integer SIMD Shift
1
1
PSAD
3
1
SIMD
FP
Integer
SIMD
StringCompare
Port 1
FP ADD
3
1
FP
Port 2
Integer loads
4
1
Integer
Port 3
Store address
5
1
Integer
Port 4
Store data
Port 5
Port 5
2-56
Integer
Integer ALU
1
1
Integer Shift
1
1
Jmp
1
1
Integer SIMD ALU
1
1
Integer SIMD Shuffle
1
1
Integer
SIMD
Comment
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Table 2-31. Issue Ports of Intel Microarchitecture Code Name Nehalem (Contd.)
Port
Executable
operations
Latency
Throughpu
t
Domain
Port 5
FP/SIMD/SSE2 Move and
Logic
1
1
FP
2.6.4
Comment
Cache and Memory Subsystem
Intel microarchitecture code name Nehalem contains an instruction cache, a first-level data cache and a
second-level unified cache in each core (see Figure 2-12). Each physical processor may contain several
processor cores and a shared collection of sub-systems that are referred to as “uncore“. Specifically in
Intel Core i7 processor, the uncore provides a unified third-level cache shared by all cores in the physical
processor, Intel QuickPath Interconnect links and associated logic. The L1 and L2 caches are writeback
and non-inclusive.
The shared L3 cache is writeback and inclusive, such that a cache line that exists in either L1 data cache,
L1 instruction cache, unified L2 cache also exists in L3. The L3 is designed to use the inclusive nature to
minimize snoop traffic between processor cores. Table 2-32 lists characteristics of the cache hierarchy.
The latency of L3 access may vary as a function of the frequency ratio between the processor and the
uncore sub-system.
Table 2-32. Cache Parameters of Intel Core i7 Processors
Line Size
(bytes)
Access
Latency
(clocks)
Access
Throughput
(clocks)
Write Update
Policy
Level
Capacity
Associativity
(ways)
First Level Data
32 KB
8
64
4
1
Writeback
Instruction
32 KB
4
N/A
N/A
N/A
N/A
64
101
Varies
Writeback
64
35-40+2
Varies
Writeback
Second Level
Third Level
(Shared L3)2
256KB
8MB
8
16
NOTES:
1. Software-visible latency will vary depending on access patterns and other factors.
2. Minimal L3 latency is 35 cycles if the frequency ratio between core and uncore is unity.
The Intel microarchitecture code name Nehalem implements two levels of translation lookaside buffer
(TLB). The first level consists of separate TLBs for data and code. DTLB0 handles address translation for
data accesses, it provides 64 entries to support 4KB pages and 32 entries for large pages. The ITLB
provides 64 entries (per thread) for 4KB pages and 7 entries (per thread) for large pages.
The second level TLB (STLB) handles both code and data accesses for 4KB pages. It support 4KB page
translation operation that missed DTLB0 or ITLB. All entries are 4-way associative. Here is a list of entries
in each DTLB:
•
•
•
STLB for 4-KByte pages: 512 entries (services both data and instruction look-ups).
DTLB0 for large pages: 32 entries.
DTLB0 for 4-KByte pages: 64 entries.
An DTLB0 miss and STLB hit causes a penalty of 7cycles. Software only pays this penalty if the DTLB0 is
used in some dispatch cases. The delays associated with a miss to the STLB and PMH are largely nonblocking.
2-57
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.6.5
Load and Store Operation Enhancements
The memory cluster of Intel microarchitecture code name Nehalem provides the following enhancements
to speed up memory operations:
•
•
•
•
•
Peak issue rate of one 128-bit load and one 128-bit store operation per cycle.
Deeper buffers for load and store operations: 48 load buffers, 32 store buffers and 10 fill buffers.
Fast unaligned memory access and robust handling of memory alignment hazards.
Improved store-forwarding for aligned and non-aligned scenarios.
Store forwarding for most address alignments.
2.6.5.1
Efficient Handling of Alignment Hazards
The cache and memory subsystems handles a significant percentage of instructions in every workload.
Different address alignment scenarios will produce varying performance impact for memory and cache
operations. For example, 1-cycle throughput of L1 (see Table 2-33) generally applies to naturally-aligned
loads from L1 cache. But using unaligned load instructions (e.g. MOVUPS, MOVUPD, MOVDQU, etc.) to
access data from L1 will experience varying amount of delays depending on specific microarchitectures
and alignment scenarios.
Table 2-33. Performance Impact of Address Alignments of MOVDQU from L1
Throughput (cycle)
Intel Core i7
Processor
45 nm Intel Core
Microarchitecture
65 nm Intel Core
Microarchitecture
Alignment Scenario
06_1AH
06_17H
06_0FH
16B aligned
1
2
2
Not-16B aligned, not cache split
1
~2
~2
Split cache line boundary
~4.5
~20
~20
Table 2-33 lists approximate throughput of issuing MOVDQU instructions with different address alignment scenarios to load data from the L1 cache. If a 16-byte load spans across cache line boundary,
previous microarchitecture generations will experience significant software-visible delays.
Intel microarchitecture code name Nehalem provides hardware enhancements to reduce the delays of
handling different address alignment scenarios including cache line splits.
2.6.5.2
Store Forwarding Enhancement
When a load follows a store and reloads the data that the store writes to memory, the microarchitecture
can forward the data directly from the store to the load in many cases. This situation, called store to load
forwarding, saves several cycles by enabling the load to obtain the data directly from the store operation
instead of through the memory system.
Several general rules must be met for store to load forwarding to proceed without delay:
•
•
•
The store must be the last store to that address prior to the load.
The store must be equal or greater in size than the size of data being loaded.
The load data must be completely contained in the preceding store.
Specific address alignment and data sizes between the store and load operations will determine whether
a store-forward situation may proceed with data forwarding or experience a delay via the cache/memory
sub-system. The 45 nm Enhanced Intel Core microarchitecture offers more flexible address alignment
and data sizes requirement than previous microarchitectures. Intel microarchitecture code name
Nehalem offers additional enhancement with allowing more situations to forward data expeditiously.
2-58
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The store-forwarding situations for with respect to store operations of 16 bytes are illustrated in
Figure 2-14.
Figure 2-14. Store-Forwarding Scenarios of 16-Byte Store Operations
Intel microarchitecture code name Nehalem allows store-to-load forwarding to proceed regardless of
store address alignment (The white space in the diagram does not correspond to an applicable store-toload scenario). Figure 2-15 illustrates situations for store operation of 8 bytes or less.
2-59
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Figure 2-15. Store-Forwarding Enhancement in Intel Microarchitecture Code Name Nehalem
2.6.6
REP String Enhancement
REP prefix in conjunction with MOVS/STOS instruction and a count value in ECX are frequently used to
implement library functions such as memcpy()/memset(). These are referred to as "REP string" instructions. Each iteration of these instruction can copy/write constant a value in byte/word/dword/qword
granularity The performance characteristics of using REP string can be attributed to two components:
startup overhead and data transfer throughput.
The two components of performance characteristics of REP String varies further depending on granularity, alignment, and/or count values. Generally, MOVSB is used to handle very small chunks of data.
Therefore, processor implementation of REP MOVSB is optimized to handle ECX < 4. Using REP MOVSB
with ECX > 3 will achieve low data throughput due to not only byte-granular data transfer but also additional startup overhead. The latency for MOVSB, is 9 cycles if ECX < 4; otherwise REP MOVSB with ECX
>9 have a 50-cycle startup cost.
For REP string of larger granularity data transfer, as ECX value increases, the startup overhead of REP
String exhibit step-wise increase:
•
•
Short string (ECX <= 12): the latency of REP MOVSW/MOVSD/MOVSQ is about 20 cycles.
Fast string (ECX >= 76: excluding REP MOVSB): the processor implementation provides hardware
optimization by moving as many pieces of data in 16 bytes as possible. The latency of REP string
latency will vary if one of the 16-byte data transfer spans across cache line boundary:
— Split-free: the latency consists of a startup cost of about 40 cycles and each 64 bytes of data adds
4 cycles.
— Cache splits: the latency consists of a startup cost of about 35 cycles and each 64 bytes of data
adds 6cycles.
•
Intermediate string lengths: the latency of REP MOVSW/MOVSD/MOVSQ has a startup cost of about
15 cycles plus one cycle for each iteration of the data movement in word/dword/qword.
Intel microarchitecture code name Nehalem improves the performance of REP strings significantly over
previous microarchitectures in several ways:
•
•
Startup overhead have been reduced in most cases relative to previous microarchitecture.
Data transfer throughput are improved over previous generation.
2-60
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
In order for REP string to operate in “fast string” mode, previous microarchitectures requires address
alignment. In Intel microarchitecture code name Nehalem, REP string can operate in “fast string”
mode even if address is not aligned to 16 bytes.
2.6.7
Enhancements for System Software
In addition to microarchitectural enhancements that can benefit both application-level and system-level
software, Intel microarchitecture code name Nehalem enhances several operations that primarily benefit
system software.
Lock primitives: Synchronization primitives using the Lock prefix (e.g. XCHG, CMPXCHG8B) executes
with significantly reduced latency than previous microarchitectures.
VMM overhead improvements: VMX transitions between a Virtual Machine (VM) and its supervisor (the
VMM) can take thousands of cycle each time on previous microarchitectures. The latency of VMX transitions has been reduced in processors based on Intel microarchitecture code name Nehalem.
2.6.8
Efficiency Enhancements for Power Consumption
Intel microarchitecture code name Nehalem is not only designed for high performance and power-efficient performance under wide range of loading situations, it also features enhancement for low power
consumption while the system idles. Intel microarchitecture code name Nehalem supports processorspecific C6 states, which have the lowest leakage power consumption that OS can manage through ACPI
and OS power management mechanisms.
2.6.9
Hyper-Threading Technology Support in Intel® Microarchitecture Code Name
Nehalem
Intel microarchitecture code name Nehalem supports Hyper-Threading Technology (HT). Its implementation of HT provides two logical processors sharing most execution/cache resources in each core. The HT
implementation in Intel microarchitecture code name Nehalem differs from previous generations of HT
implementations using Intel NetBurst microarchitecture in several areas:
•
Intel microarchitecture code name Nehalem provides four-wide execution engine, more functional
execution units coupled to three issue ports capable of issuing computational operations.
•
Intel microarchitecture code name Nehalem supports integrated memory controller that can provide
peak memory bandwidth of up to 25.6 GB/sec in Intel Core i7 processor.
•
Deeper buffering and enhanced resource sharing/partition policies:
— Replicated resource for HT operation: register state, renamed return stack buffer, large-page
ITLB.
— Partitioned resources for HT operation: load buffers, store buffers, re-order buffers, small-page
ITLB are statically allocated between two logical processors.
— Competitively-shared resource during HT operation: the reservation station, cache hierarchy, fill
buffers, both DTLB0 and STLB.
— Alternating during HT operation: front end operation generally alternates between two logical
processors to ensure fairness.
— HT unaware resources: execution units.
2.7
INTEL® HYPER-THREADING TECHNOLOGY
Intel® Hyper-Threading Technology (HT Technology) enables software to take advantage of task-level, or
thread-level parallelism by providing multiple logical processors within a physical processor package, or
within each processor core in a physical processor package. In its first implementation in the Intel Xeon
2-61
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
processor, Hyper-Threading Technology makes a single physical processor (or a processor core) appear
as two or more logical processors. Intel Xeon Phi processors based on the Knights Landing microarchitecture support 4 logical processors in each processor core; see Chapter 17 for detailed information of
Hyper-Threading Technology that is implemented in the Knights Landing microarchitecture.
Most Intel Architecture processor families support Hyper-Threading Technology with two logical processors in each processor core, or in a physical processor in early implementations. The rest of this section
describes features of the early implementation of Hyper-Threading Technology. Most of the descriptions
also apply to later Hyper-Threading Technology implementations supporting two logical processors. The
microarchitecture sections in this chapter provide additional details to individual microarchitecture and
enhancements to Hyper-Threading Technology.
The two logical processors each have a complete set of architectural registers while sharing one single
physical processor's resources. By maintaining the architecture state of two processors, an HT Technology capable processor looks like two processors to software, including operating system and application code.
By sharing resources needed for peak demands between two logical processors, HT Technology is well
suited for multiprocessor systems to provide an additional performance boost in throughput when
compared to traditional MP systems.
Figure 2-16 shows a typical bus-based symmetric multiprocessor (SMP) based on processors supporting
HT Technology. Each logical processor can execute a software thread, allowing a maximum of two software threads to execute simultaneously on one physical processor. The two software threads execute
simultaneously, meaning that in the same clock cycle an “add” operation from logical processor 0 and
another “add” operation and load from logical processor 1 can be executed simultaneously by the execution engine.
In the first implementation of HT Technology, the physical execution resources are shared and the architecture state is duplicated for each logical processor. This minimizes the die area cost of implementing HT
Technology while still achieving performance gains for multithreaded applications or multitasking workloads.
Architectural
State
Architectural
State
Architectural
State
Execution Engine
Execution Engine
Local APIC
Architectural
State
Local APIC
Local APIC
Bus Interface
Local APIC
Bus Interface
System Bus
OM15152
Figure 2-16. Hyper-Threading Technology on an SMP
2-62
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
The performance potential due to HT Technology is due to:
•
The fact that operating systems and user programs can schedule processes or threads to execute
simultaneously on the logical processors in each physical processor.
•
The ability to use on-chip execution resources at a higher level than when only a single thread is
consuming the execution resources; higher level of resource utilization can lead to higher system
throughput.
2.7.1
Processor Resources and HT Technology
The majority of microarchitecture resources in a physical processor are shared between the logical
processors. Only a few small data structures were replicated for each logical processor. This section
describes how resources are shared, partitioned or replicated.
2.7.1.1
Replicated Resources
The architectural state is replicated for each logical processor. The architecture state consists of registers
that are used by the operating system and application code to control program behavior and store data
for computations. This state includes the eight general-purpose registers, the control registers, machine
state registers, debug registers, and others. There are a few exceptions, most notably the memory type
range registers (MTRRs) and the performance monitoring resources. For a complete list of the architecture state and exceptions, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volumes 3A, 3B, 3C & 3D.
Other resources such as instruction pointers and register renaming tables were replicated to simultaneously track execution and state changes of the two logical processors. The return stack predictor is replicated to improve branch prediction of return instructions.
In addition, a few buffers (for example, the 2-entry instruction streaming buffers) were replicated to
reduce complexity.
2.7.1.2
Partitioned Resources
Several buffers are shared by limiting the use of each logical processor to half the entries. These are
referred to as partitioned resources. Reasons for this partitioning include:
•
•
Operational fairness.
Permitting the ability to allow operations from one logical processor to bypass operations of the other
logical processor that may have stalled.
For example: a cache miss, a branch misprediction, or instruction dependencies may prevent a logical
processor from making forward progress for some number of cycles. The partitioning prevents the stalled
logical processor from blocking forward progress.
In general, the buffers for staging instructions between major pipe stages are partitioned. These buffers
include µop queues after the execution trace cache, the queues after the register rename stage, the
reorder buffer which stages instructions for retirement, and the load and store buffers.
In the case of load and store buffers, partitioning also provided an easier implementation to maintain
memory ordering for each logical processor and detect memory ordering violations.
2-63
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.7.1.3
Shared Resources
Most resources in a physical processor are fully shared to improve the dynamic utilization of the resource,
including caches and all the execution units. Some shared resources which are linearly addressed, like
the DTLB, include a logical processor ID bit to distinguish whether the entry belongs to one logical
processor or the other.
The first level cache can operate in two modes depending on a context-ID bit:
•
•
Shared mode: The L1 data cache is fully shared by two logical processors.
Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically
across logical processors sharing the L1 data cache.
The other resources are fully shared.
2.7.2
Microarchitecture Pipeline and HT Technology
This section describes the HT Technology microarchitecture and how instructions from the two logical
processors are handled between the front end and the back end of the pipeline.
Although instructions originating from two programs or two threads execute simultaneously and not
necessarily in program order in the execution core and memory hierarchy, the front end and back end
contain several selection points to select between instructions from the two logical processors. All selection points alternate between the two logical processors unless one logical processor cannot make use of
a pipeline stage. In this case, the other logical processor has full use of every cycle of the pipeline stage.
Reasons why a logical processor may not use a pipeline stage include cache misses, branch mispredictions, and instruction dependencies.
2.7.3
Front End Pipeline
The execution trace cache is shared between two logical processors. Execution trace cache access is arbitrated by the two logical processors every clock. If a cache line is fetched for one logical processor in one
clock cycle, the next clock cycle a line would be fetched for the other logical processor provided that both
logical processors are requesting access to the trace cache.
If one logical processor is stalled or is unable to use the execution trace cache, the other logical processor
can use the full bandwidth of the trace cache until the initial logical processor’s instruction fetches return
from the L2 cache.
After fetching the instructions and building traces of µops, the µops are placed in a queue. This queue
decouples the execution trace cache from the register rename pipeline stage. As described earlier, if both
logical processors are active, the queue is partitioned so that both logical processors can make independent forward progress.
2.7.4
Execution Core
The core can dispatch up to six µops per cycle, provided the µops are ready to execute. Once the µops
are placed in the queues waiting for execution, there is no distinction between instructions from the two
logical processors. The execution core and memory hierarchy is also oblivious to which instructions
belong to which logical processor.
After execution, instructions are placed in the re-order buffer. The re-order buffer decouples the execution stage from the retirement stage. The re-order buffer is partitioned such that each uses half the
entries.
2-64
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.7.5
Retirement
The retirement logic tracks when instructions from the two logical processors are ready to be retired. It
retires the instruction in program order for each logical processor by alternating between the two logical
processors. If one logical processor is not ready to retire any instructions, then all retirement bandwidth
is dedicated to the other logical processor.
Once stores have retired, the processor needs to write the store data into the level-one data cache.
Selection logic alternates between the two logical processors to commit store data to the cache.
2.8
INTEL® 64 ARCHITECTURE
Intel 64 architecture supports almost all features in the IA-32 Intel architecture and extends support to
run 64-bit OS and 64-bit applications in 64-bit linear address space. Intel 64 architecture provides a new
operating mode, referred to as IA-32e mode, and increases the linear address space for software to 64
bits and supports physical address space up to 40 bits.
IA-32e mode consists of two sub-modes: (1) compatibility mode enables a 64-bit operating system to
run most legacy 32-bit software unmodified, (2) 64-bit mode enables a 64-bit operating system to run
applications written to access 64-bit linear address space.
In the 64-bit mode of Intel 64 architecture, software may access:
•
•
•
64-bit flat linear addressing.
8 additional general-purpose registers (GPRs).
8 additional registers (XMM) for streaming SIMD extensions (SSE, SSE2, SSE3, SSSE3, SSE4.1,
SSE4.2, AESNI, PCLMULQDQ).
— Sixteen 256-bit YMM registers (whose lower 128 bits are overlaid to the respective XMM
registers) if AVX, F16C, AVX2 or FMA are supported.
•
•
•
•
64-bit-wide GPRs and instruction pointers.
Uniform byte-register addressing.
Fast interrupt-prioritization mechanism.
A new instruction-pointer relative-addressing mode.
2.9
SIMD TECHNOLOGY
SIMD computations (see Figure 2-17) were introduced to the architecture with MMX technology. MMX
technology allows SIMD computations to be performed on packed byte, word, and doubleword integers.
The integers are contained in a set of eight 64-bit registers called MMX registers (see Figure 2-18).
The Pentium III processor extended the SIMD computation model with the introduction of the Streaming
SIMD Extensions (SSE). SSE allows SIMD computations to be performed on operands that contain four
packed single-precision floating-point data elements. The operands can be in memory or in a set of eight
128-bit XMM registers (see Figure 2-18). SSE also extended SIMD computational capability by adding
additional 64-bit MMX instructions.
Figure 2-17 shows a typical SIMD computation. Two sets of four packed data elements (X1, X2, X3, and
X4, and Y1, Y2, Y3, and Y4) are operated on in parallel, with the same operation being performed on each
corresponding pair of data elements (X1 and Y1, X2 and Y2, X3 and Y3, and X4 and Y4). The results of
the four parallel computations are sorted as a set of four packed data elements.
2-65
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
X4
Y4
X3
Y3
OP
X4 op Y4
X2
Y2
OP
X3 op Y3
X1
Y1
OP
X2 op Y2
OP
X1 op Y1
OM15148
Figure 2-17. Typical SIMD Operations
The Pentium 4 processor further extended the SIMD computation model with the introduction of
Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3), and Intel Xeon processor
5100 series introduced Supplemental Streaming SIMD Extensions 3 (SSSE3).
SSE2 works with operands in either memory or in the XMM registers. The technology extends SIMD
computations to process packed double-precision floating-point data elements and 128-bit packed integers. There are 144 instructions in SSE2 that operate on two packed double-precision floating-point data
elements or on 16 packed byte, 8 packed word, 4 doubleword, and 2 quadword integers.
SSE3 enhances x87, SSE and SSE2 by providing 13 instructions that can accelerate application performance in specific areas. These include video processing, complex arithmetics, and thread synchronization. SSE3 complements SSE and SSE2 with instructions that process SIMD data asymmetrically,
facilitate horizontal computation, and help avoid loading cache line splits. See Figure 2-18.
SSSE3 provides additional enhancement for SIMD computation with 32 instructions on digital video and
signal processing.
SSE4.1, SSE4.2 and AESNI are additional SIMD extensions that provide acceleration for applications in
media processing, text/lexical processing, and block encryption/decryption.
The SIMD extensions operates the same way in Intel 64 architecture as in IA-32 architecture, with the
following enhancements:
•
•
128-bit SIMD instructions referencing XMM register can access 16 XMM registers in 64-bit mode.
Instructions that reference 32-bit general purpose registers can access 16 general purpose registers
in 64-bit mode.
2-66
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
64-bit M MX Registers
128-bit XMM Registers
MM7
XMM7
MM7
MM6
XMM6
MM5
XMM5
MM4
XMM4
MM3
XMM3
MM2
XMM2
MM1
XMM1
MM0
XMM0
OM15149
Figure 2-18. SIMD Instruction Register Usage
SIMD improves the performance of 3D graphics, speech recognition, image processing, scientific applications and applications that have the following characteristics:
•
•
•
•
Inherently parallel.
Recurring memory access patterns.
Localized recurring operations performed on the data.
Data-independent control flow.
2.10
SUMMARY OF SIMD TECHNOLOGIES AND APPLICATION LEVEL
EXTENSIONS
SIMD floating-point instructions fully support the IEEE Standard 754 for Binary Floating-Point Arithmetic.
They are accessible from all IA-32 execution modes: protected mode, real address mode, and Virtual
8086 mode.
SSE, SSE2, and MMX technologies are architectural extensions. Existing software will continue to run
correctly, without modification on Intel microprocessors that incorporate these technologies. Existing
software will also run correctly in the presence of applications that incorporate SIMD technologies.
SSE and SSE2 instructions also introduced cacheability and memory ordering instructions that can
improve cache usage and application performance.
For more on SSE, SSE2, SSE3 and MMX technologies, see the following chapters in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1:
•
•
•
•
•
•
•
Chapter 9, “Programming with Intel® MMX™ Technology”.
Chapter 10, “Programming with Streaming SIMD Extensions (SSE)”.
Chapter 11, “Programming with Streaming SIMD Extensions 2 (SSE2)”.
Chapter 12, “Programming with SSE3, SSSE3 and SSE4”.
Chapter 14, “Programming with AVX, FMA and AVX2”.
Chapter 15, “Programming with Intel® AVX-512”.
Chapter 16, “Programming with Intel® Transactional Synchronization Extensions”.
2-67
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.10.1
MMX™ Technology
MMX Technology introduced:
•
•
64-bit MMX registers.
Support for SIMD operations on packed byte, word, and doubleword integers.
MMX instructions are useful for multimedia and communications software.
2.10.2
Streaming SIMD Extensions
Streaming SIMD extensions introduced:
•
•
•
•
•
128-bit XMM registers.
128-bit data type with four packed single-precision floating-point operands.
Data prefetch instructions.
Non-temporal store instructions and other cacheability and memory ordering instructions.
Extra 64-bit SIMD integer support.
SSE instructions are useful for 3D geometry, 3D rendering, speech recognition, and video encoding and
decoding.
2.10.3
Streaming SIMD Extensions 2
Streaming SIMD extensions 2 add the following:
•
•
128-bit data type with two packed double-precision floating-point operands.
•
•
•
•
Support for SIMD arithmetic on 64-bit integer operands.
128-bit data types for SIMD integer operation on 16-byte, 8-word, 4-doubleword, or 2-quadword
integers.
Instructions for converting between new and existing data types.
Extended support for data shuffling.
Extended support for cacheability and memory ordering operations.
SSE2 instructions are useful for 3D graphics, video decoding/encoding, and encryption.
2.10.4
Streaming SIMD Extensions 3
Streaming SIMD extensions 3 add the following:
•
•
•
•
SIMD floating-point instructions for asymmetric and horizontal computation.
A special-purpose 128-bit load instruction to avoid cache line splits.
An x87 FPU instruction to convert to integer independent of the floating-point control word (FCW).
Instructions to support thread synchronization.
SSE3 instructions are useful for scientific, video and multi-threaded applications.
2.10.5
Supplemental Streaming SIMD Extensions 3
The Supplemental Streaming SIMD Extensions 3 introduces 32 new instructions to accelerate eight
types of computations on packed integers. These include:
•
•
•
12 instructions that perform horizontal addition or subtraction operations.
6 instructions that evaluate the absolute values.
2 instructions that perform multiply and add operations and speed up the evaluation of dot products.
2-68
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
•
2 instructions that accelerate packed-integer multiply operations and produce integer values with
scaling.
•
2 instructions that perform a byte-wise, in-place shuffle according to the second shuffle control
operand.
•
6 instructions that negate packed integers in the destination operand if the signs of the corresponding element in the source operand is less than zero.
•
2 instructions that align data from the composite of two operands.
2.10.6
SSE4.1
SSE4.1 introduces 47 new instructions to accelerate video, imaging and 3D applications. SSE4.1 also
improves compiler vectorization and significantly increase support for packed dword computation. These
include:
•
•
•
•
•
•
Two instructions perform packed dword multiplies.
•
•
•
•
•
•
•
Seven instructions improve data insertion and extractions from XMM registers
Two instructions perform floating-point dot products with input/output selects.
One instruction provides a streaming hint for WC loads.
Six instructions simplify packed blending.
Eight instructions expand support for packed integer MIN/MAX.
Four instructions support floating-point round with selectable rounding mode and precision exception
override.
Twelve instructions improve packed integer format conversions (sign and zero extensions).
One instruction improves SAD (sum absolute difference) generation for small block sizes.
One instruction aids horizontal searching operations of word integers.
One instruction improves masked comparisons.
One instruction adds qword packed equality comparisons.
One instruction adds dword packing with unsigned saturation.
2.10.7
SSE4.2
SSE4.2 introduces 7 new instructions. These include:
•
•
A 128-bit SIMD integer instruction for comparing 64-bit integer data elements.
Four string/text processing instructions providing a rich set of primitives, these primitives can
accelerate:
— Basic and advanced string library functions from strlen, strcmp, to strcspn.
— Delimiter processing, token extraction for lexing of text streams.
— Parser, schema validation including XML processing.
•
•
A general-purpose instruction for accelerating cyclic redundancy checksum signature calculations.
A general-purpose instruction for calculating bit count population of integer numbers.
2.10.8
AESNI and PCLMULQDQ
AESNI introduces 7 new instructions, six of them are primitives for accelerating algorithms based on AES
encryption/decryption standard, referred to as AESNI.
The PCLMULQDQ instruction accelerates general-purpose block encryption, which can perform carry-less
multiplication for two binary numbers up to 64-bit wide.
2-69
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
Typically, algorithm based on AES standard involve transformation of block data over multiple iterations
via several primitives. The AES standard supports cipher key of sizes 128, 192, and 256 bits. The respective cipher key sizes correspond to 10, 12, and 14 rounds of iteration.
AES encryption involves processing 128-bit input data (plaintext) through a finite number of iterative
operation, referred to as “AES round”, into a 128-bit encrypted block (ciphertext). Decryption follows the
reverse direction of iterative operation using the “equivalent inverse cipher” instead of the “inverse
cipher”.
The cryptographic processing at each round involves two input data, one is the “state”, the other is the
“round key”. Each round uses a different “round key”. The round keys are derived from the cipher key
using a “key schedule” algorithm. The “key schedule” algorithm is independent of the data processing of
encryption/decryption, and can be carried out independently from the encryption/decryption phase.
The AES extensions provide two primitives to accelerate AES rounds on encryption, two primitives for
AES rounds on decryption using the equivalent inverse cipher, and two instructions to support the AES
key expansion procedure.
2.10.9
Intel® Advanced Vector Extensions
Intel® Advanced Vector Extensions offers comprehensive architectural enhancements over previous
generations of Streaming SIMD Extensions. Intel AVX introduces the following architectural enhancements:
•
•
Support for 256-bit wide vectors and SIMD register set.
•
Instruction syntax support for generalized three-operand syntax to improve instruction programming
flexibility and efficient encoding of new instruction extensions.
•
Enhancement of legacy 128-bit SIMD instruction extensions to support three-operand syntax and to
simplify compiler vectorization of high-level language expressions.
•
Support flexible deployment of 256-bit AVX code, 128-bit AVX code, legacy 128-bit code and scalar
code.
256-bit floating-point instruction set enhancement with up to 2X performance gain relative to 128-bit
Streaming SIMD extensions.
Intel AVX instruction set and 256-bit register state management detail are described in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D. Optimization techniques for
Intel AVX is discussed in Chapter 11, “Optimization for Intel® AVX, FMA, and AVX2”.
2.10.10 Half-Precision Floating-Point Conversion (F16C)
VCVTPH2PS and VCVTPS2PH are two instructions supporting half-precision floating-point data type
conversion to and from single-precision floating-point data types. These two instruction extends on the
same programming model as Intel AVX.
2.10.11 RDRAND
The RDRAND instruction retrieves a random number supplied by a cryptographically secure, deterministic random bit generator (DBRG). The DBRG is designed to meet NIST SP 800-90A standard.
2.10.12 Fused-Multiply-ADD (FMA) Extensions
FMA extensions enhances Intel AVX with high-throughput, arithmetic capabilities covering fused
multiply-add, fused multiply-subtract, fused multiply add/subtract interleave, signed-reversed multiply
on fused multiply-add and multiply-subtract operations. FMA extensions provide 36 256-bit floatingpoint instructions to perform computation on 256-bit vectors and additional 128-bit and scalar FMA
instructions.
2-70
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2.10.13 Intel AVX2
Intel AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions with 256-bit
numeric processing capabilities. AVX2 instructions follow the same programming model as AVX instructions.
In addition, AVX2 provide enhanced functionalities for broadcast/permute operations on data elements,
vector shift instructions with variable-shift count per data element, and instructions to fetch non-contiguous data elements from memory.
2.10.14 General-Purpose Bit-Processing Instructions
The fourth generation Intel Core processor family introduces a collection of bit processing instructions
that operate on the general purpose registers. The majority of these instructions uses the VEX-prefix
encoding scheme to provide non-destructive source operand syntax.
There instructions are enumerated by three separate feature flags reported by CPUID. For details, see
Section 5.1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 and chapters
3, 4 and 5 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C
& 2D.
2.10.15 Intel® Transactional Synchronization Extensions
The fourth generation Intel Core processor family introduces Intel® Transactional Synchronization
Extensions (Intel TSX), which aim to improve the performance of lock-protected critical sections of multithreaded applications while maintaining the lock-based programming model.
For background and details, see Chapter 16, “Programming with Intel® Transactional Synchronization
Extensions” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Software tuning recommendations for using Intel TSX on lock-protected critical sections of multithreaded
applications are described in Chapter 12, “Intel® TSX Recommendations”.
2.10.16 RDSEED
The Intel Core M processor family introduces the RDSEED, ADCX and ADOX instructions.
The RDSEED instruction retrieves a random number supplied by a cryptographically secure, enhanced
deterministic random bit generator Enhanced NRBG). The NRBG is designed to meet the NIST SP 80090B and NIST SP 800-90C standards.
2.10.17 ADCX and ADOX Instructions
The ADCX and ADOX instructions, in conjunction with MULX instruction, enable software to speed up
calculations that require large integer numerics. Details can be found at
http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/large-integersquaring-ia-paper.pdf.
2-71
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES
2-72
CHAPTER 3
GENERAL OPTIMIZATION GUIDELINES
This chapter discusses general optimization techniques that can improve the performance of applications
running on processors based on Intel microarchitecture code name Haswell, Ivy Bridge, Sandy Bridge,
Westmere, Nehalem, Enhanced Intel Core microarchitecture and Intel Core microarchitectures. These
techniques take advantage of microarchitectural described in Chapter 2, “Intel® 64 and IA-32 Processor
Architectures.” Optimization guidelines focusing on Intel multi-core processors, Hyper-Threading Technology and 64-bit mode applications are discussed in Chapter 9, “Multicore and Hyper-Threading Technology,” and Chapter 10, “64-bit Mode Coding Guidelines.”
Practices that optimize performance focus on three areas:
•
•
Tools and techniques for code generation.
•
Tuning code to the target microarchitecture (or families of microarchitecture) to improve performance.
Analysis of the performance characteristics of the workload and its interaction with microarchitectural sub-systems.
Some hints on using tools are summarized first to simplify the first two tasks. the rest of the chapter will
focus on recommendations of code generation or code tuning to the target microarchitectures.
This chapter explains optimization techniques for the Intel C++ Compiler, the Intel Fortran Compiler, and
other compilers.
3.1
PERFORMANCE TOOLS
Intel offers several tools to help optimize application performance, including compilers, performance
analyzer and multithreading tools.
3.1.1
Intel® C++ and Fortran Compilers
Intel compilers support multiple operating systems (Windows*, Linux*, Mac OS* and embedded). The
Intel compilers optimize performance and give application developers access to advanced features:
•
•
•
•
•
Flexibility to target 32-bit or 64-bit Intel processors for optimization
Compatibility with many integrated development environments or third-party compilers.
Automatic optimization features to take advantage of the target processor’s architecture.
Automatic compiler optimization reduces the need to write different code for different processors.
Common compiler features that are supported across Windows, Linux and Mac OS include:
— General optimization settings.
— Cache-management features.
— Interprocedural optimization (IPO) methods.
— Profile-guided optimization (PGO) methods.
— Multithreading support.
— Floating-point arithmetic precision and consistency support.
— Compiler optimization and vectorization reports.
GENERAL OPTIMIZATION GUIDELINES
3.1.2
General Compiler Recommendations
Generally speaking, a compiler that has been tuned for the target microarchitecture can be expected to
match or outperform hand-coding. However, if performance problems are noted with the compiled code,
some compilers (like Intel C++ and Fortran Compilers) allow the coder to insert intrinsics or inline
assembly in order to exert control over what code is generated. If inline assembly is used, the user must
verify that the code generated is of good quality and yields good performance.
Default compiler switches are targeted for common cases. An optimization may be made to the compiler
default if it is beneficial for most programs. If the root cause of a performance problem is a poor choice
on the part of the compiler, using different switches or compiling the targeted module with a different
compiler may be the solution.
3.1.3
VTune™ Performance Analyzer
VTune uses performance monitoring hardware to collect statistics and coding information of your application and its interaction with the microarchitecture. This allows software engineers to measure performance characteristics of the workload for a given microarchitecture. VTune supports all current and past
Intel processor families.
The VTune Performance Analyzer provides two kinds of feedback:
•
Indication of a performance improvement gained by using a specific coding recommendation or
microarchitectural feature.
•
Information on whether a change in the program has improved or degraded performance with
respect to a particular metric.
The VTune Performance Analyzer also provides measures for a number of workload characteristics,
including:
•
Retirement throughput of instruction execution as an indication of the degree of extractable
instruction-level parallelism in the workload.
•
•
Data traffic locality as an indication of the stress point of the cache and memory hierarchy.
Data traffic parallelism as an indication of the degree of effectiveness of amortization of data access
latency.
NOTE
Improving performance in one part of the machine does not necessarily bring significant
gains to overall performance. It is possible to degrade overall performance by improving
performance for some particular metric.
Where appropriate, coding recommendations in this chapter include descriptions of the VTune Performance Analyzer events that provide measurable data on the performance gain achieved by following the
recommendations. For more on using the VTune analyzer, refer to the application’s online help.
3.2
PROCESSOR PERSPECTIVES
Many coding recommendations for work well across modern microarchitectures from Intel Core microarchitecture to the Haswell microarchitecture. However, there are situations where a recommendation may
benefit one microarchitecture more than another. Some of these are:
•
Instruction decode throughput is important. Additionally, taking advantage of decoded ICache, Loop
Stream Detector and macrofusion can further improve front end performance.
•
Generating code to take advantage 4 decoders and employ micro-fusion and macro-fusion so that
each of three simple decoders are not restricted to handling simple instructions consisting of one
micro-op.
3-2
GENERAL OPTIMIZATION GUIDELINES
•
On processors based on Sandy Bridge, Ivy Bridge and Haswell microarchitectures, the code size for
optimal front end performance is associated with the decode ICache.
•
Dependencies for partial register writes can incur varying degree of penalties To avoid false
dependences from partial register updates, use full register updates and extended moves.
•
•
Use appropriate instructions that support dependence-breaking (e.g. PXOR, SUB, XOR, XORPS).
Hardware prefetching can reduce the effective memory latency for data and instruction accesses in
general. But different microarchitectures may require some custom modifications to adapt to the
specific hardware prefetch implementation of each microarchitecture.
3.2.1
CPUID Dispatch Strategy and Compatible Code Strategy
When optimum performance on all processor generations is desired, applications can take advantage of
the CPUID instruction to identify the processor generation and integrate processor-specific instructions
into the source code. The Intel C++ Compiler supports the integration of different versions of the code
for different target processors. The selection of which code to execute at runtime is made based on the
CPU identifiers. Binary code targeted for different processor generations can be generated under the
control of the programmer or by the compiler.
For applications that target multiple generations of microarchitectures, and where minimum binary code
size and single code path is important, a compatible code strategy is the best. Optimizing applications
using techniques developed for the Intel Core microarchitecture and combined with Intel microarchitecture code name Nehalem are likely to improve code efficiency and scalability when running on processors
based on current and future generations of Intel 64 and IA-32 processors.
3.2.2
Transparent Cache-Parameter Strategy
If the CPUID instruction supports function leaf 4, also known as deterministic cache parameter leaf, the
leaf reports cache parameters for each level of the cache hierarchy in a deterministic and forwardcompatible manner across Intel 64 and IA-32 processor families.
For coding techniques that rely on specific parameters of a cache level, using the deterministic cache
parameter allows software to implement techniques in a way that is forward-compatible with future
generations of Intel 64 and IA-32 processors, and cross-compatible with processors equipped with
different cache sizes.
3.2.3
Threading Strategy and Hardware Multithreading Support
Intel 64 and IA-32 processor families offer hardware multithreading support in two forms: dual-core
technology and HT Technology.
To fully harness the performance potential of hardware multithreading in current and future generations
of Intel 64 and IA-32 processors, software must embrace a threaded approach in application design. At
the same time, to address the widest range of installed machines, multi-threaded software should be
able to run without failure on a single processor without hardware multithreading support and should
achieve performance on a single logical processor that is comparable to an unthreaded implementation
(if such comparison can be made). This generally requires architecting a multi-threaded application to
minimize the overhead of thread synchronization. Additional guidelines on multithreading are discussed
in Chapter 9, “Multicore and Hyper-Threading Technology.”
3.3
CODING RULES, SUGGESTIONS AND TUNING HINTS
This section includes rules, suggestions and hints. They are targeted for engineers who are:
•
•
Modifying source code to enhance performance (user/source rules).
Writing assemblers or compilers (assembly/compiler rules).
3-3
GENERAL OPTIMIZATION GUIDELINES
•
Doing detailed performance tuning (tuning suggestions).
Coding recommendations are ranked in importance using two measures:
•
Local impact (high, medium, or low) refers to a recommendation’s affect on the performance of a
given instance of code.
•
Generality (high, medium, or low) measures how often such instances occur across all application
domains. Generality may also be thought of as “frequency”.
These recommendations are approximate. They can vary depending on coding style, application domain,
and other factors.
The purpose of the high, medium, and low (H, M, and L) priorities is to suggest the relative level of
performance gain one can expect if a recommendation is implemented.
Because it is not possible to predict the frequency of a particular code instance in applications, priority
hints cannot be directly correlated to application-level performance gain. In cases in which applicationlevel performance gain has been observed, we have provided a quantitative characterization of the gain
(for information only). In cases in which the impact has been deemed inapplicable, no priority is
assigned.
3.4
OPTIMIZING THE FRONT END
Optimizing the front end covers two aspects:
•
Maintaining steady supply of micro-ops to the execution engine — Mispredicted branches can disrupt
streams of micro-ops, or cause the execution engine to waste execution resources on executing
streams of micro-ops in the non-architected code path. Much of the tuning in this respect focuses on
working with the Branch Prediction Unit. Common techniques are covered in Section 3.4.1, “Branch
Prediction Optimization.”
•
Supplying streams of micro-ops to utilize the execution bandwidth and retirement bandwidth as
much as possible — For Intel Core microarchitecture and Intel Core Duo processor family, this aspect
focuses maintaining high decode throughput. In Intel microarchitecture code name Sandy Bridge,
this aspect focuses on keeping the hod code running from Decoded ICache. Techniques to maximize
decode throughput for Intel Core microarchitecture are covered in Section 3.4.2, “Fetch and Decode
Optimization.”
3.4.1
Branch Prediction Optimization
Branch optimizations have a significant impact on performance. By understanding the flow of branches
and improving their predictability, you can increase the speed of code significantly.
Optimizations that help branch prediction are:
•
Keep code and data on separate pages. This is very important; see Section 3.6, “Optimizing Memory
Accesses,” for more information.
•
•
•
•
•
Eliminate branches whenever possible.
•
Avoid putting two conditional branch instructions in a loop so that both have the same branch target
address and, at the same time, belong to (i.e. have their last bytes' addresses within) the same 16byte aligned code block.
3-4
Arrange code to be consistent with the static branch prediction algorithm.
Use the PAUSE instruction in spin-wait loops.
Inline functions and pair up calls and returns.
Unroll as necessary so that repeatedly-executed loops have sixteen or fewer iterations (unless this
causes an excessive code size increase).
GENERAL OPTIMIZATION GUIDELINES
3.4.1.1
Eliminating Branches
Eliminating branches improves performance because:
•
•
It reduces the possibility of mispredictions.
It reduces the number of required branch target buffer (BTB) entries. Conditional branches, which
are never taken, do not consume BTB resources.
There are four principal ways of eliminating branches:
•
•
•
•
Arrange code to make basic blocks contiguous.
Unroll loops, as discussed in Section 3.4.1.7, “Loop Unrolling.”
Use the CMOV instruction.
Use the SETCC instruction.
The following rules apply to branch elimination:
Assembly/Compiler Coding Rule 1. (MH impact, M generality) Arrange code to make basic blocks
contiguous and eliminate unnecessary branches.
Assembly/Compiler Coding Rule 2. (M impact, ML generality) Use the SETCC and CMOV
instructions to eliminate unpredictable conditional branches where possible. Do not do this for
predictable branches. Do not use these instructions to eliminate all unpredictable conditional branches
(because using these instructions will incur execution overhead due to the requirement for executing
both paths of a conditional branch). In addition, converting a conditional branch to SETCC or CMOV
trades off control flow dependence for data dependence and restricts the capability of the out-of-order
engine. When tuning, note that all Intel 64 and IA-32 processors usually have very high branch
prediction rates. Consistently mispredicted branches are generally rare. Use these instructions only if
the increase in computation time is less than the expected cost of a mispredicted branch.
Consider a line of C code that has a condition dependent upon one of the constants:
X = (A < B) ? CONST1 : CONST2;
This code conditionally compares two values, A and B. If the condition is true, X is set to CONST1; otherwise it is set to CONST2. An assembly code sequence equivalent to the above C code can contain
branches that are not predictable if there are no correlation in the two values.
Example 3-1 shows the assembly code with unpredictable branches. The unpredictable branches can be
removed with the use of the SETCC instruction. Example 3-2 shows optimized code that has no
branches.
Example 3-1. Assembly Code with an Unpredictable Branch
cmp a, b
jbe L30
mov ebx const1
jmp L31
L30:
mov ebx, const2
L31:
; Condition
; Conditional branch
; ebx holds X
; Unconditional branch
Example 3-2. Code Optimization to Eliminate Branches
xor ebx, ebx
cmp A, B
setge bl
; Clear ebx (X in the C code)
; When ebx = 0 or 1
; OR the complement condition
sub ebx, 1
; ebx=11...11 or 00...00
and ebx, CONST3; CONST3 = CONST1-CONST2
add ebx, CONST2; ebx=CONST1 or CONST2
3-5
GENERAL OPTIMIZATION GUIDELINES
The optimized code in Example 3-2 sets EBX to zero, then compares A and B. If A is greater than or equal
to B, EBX is set to one. Then EBX is decreased and AND’d with the difference of the constant values. This
sets EBX to either zero or the difference of the values. By adding CONST2 back to EBX, the correct value
is written to EBX. When CONST2 is equal to zero, the last instruction can be deleted.
Another way to remove branches is to use the CMOV and FCMOV instructions. Example 3-3 shows how to
change a TEST and branch instruction sequence using CMOV to eliminate a branch. If the TEST sets the
equal flag, the value in EBX will be moved to EAX. This branch is data-dependent, and is representative
of an unpredictable branch.
Example 3-3. Eliminating Branch with CMOV Instruction
test ecx, ecx
jne 1H
mov eax, ebx
1H:
; To optimize code, combine jne and mov into one cmovcc instruction that checks the equal flag
test ecx, ecx
; Test the flags
cmoveq eax, ebx
; If the equal flag is set, move
; ebx to eax- the 1H: tag no longer needed
3.4.1.2
Spin-Wait and Idle Loops
The Pentium 4 processor introduces a new PAUSE instruction; the instruction is architecturally a NOP on
Intel 64 and IA-32 processor implementations.
To the Pentium 4 and later processors, this instruction acts as a hint that the code sequence is a spin-wait
loop. Without a PAUSE instruction in such loops, the Pentium 4 processor may suffer a severe penalty
when exiting the loop because the processor may detect a possible memory order violation. Inserting the
PAUSE instruction significantly reduces the likelihood of a memory order violation and as a result
improves performance.
In Example 3-4, the code spins until memory location A matches the value stored in the register EAX.
Such code sequences are common when protecting a critical section, in producer-consumer sequences,
for barriers, or other synchronization.
Example 3-4. Use of PAUSE Instruction
lock:
loop:
cmp eax, a
jne loop
; Code in critical section:
pause
cmp eax, a
jne loop
jmp lock
3.4.1.3
Static Prediction
Branches that do not have a history in the BTB (see Section 3.4.1, “Branch Prediction Optimization”) are
predicted using a static prediction algorithm:
•
•
Predict unconditional branches to be taken.
Predict indirect branches to be NOT taken.
The following rule applies to static elimination:
3-6
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 3. (M impact, H generality) Arrange code to be consistent with
the static branch prediction algorithm: make the fall-through code following a conditional branch be the
likely target for a branch with a forward target, and make the fall-through code following a conditional
branch be the unlikely target for a branch with a backward target.
Example 3-5 illustrates the static branch prediction algorithm. The body of an IF-THEN conditional is
predicted.
Example 3-5. Static Branch Prediction Algorithm
//Forward condition branches not taken (fall through)
IF<condition> {....
↓
}
IF<condition> {...
↓
}
//Backward conditional branches are taken
LOOP {...
↑ −− }<condition>
//Unconditional branches taken
JMP
------→
Example 3-6 and Example 3-7 provide basic rules for a static prediction algorithm. In Example 3-6, the
backward branch (JC BEGIN) is not in the BTB the first time through; therefore, the BTB does not issue
a prediction. The static predictor, however, will predict the branch to be taken, so a misprediction will not
occur.
Example 3-6. Static Taken Prediction
Begin: mov
and
imul
shld
jc
eax, mem32
eax, ebx
eax, edx
eax, 7
Begin
The first branch instruction (JC BEGIN) in Example 3-7 is a conditional forward branch. It is not in the
BTB the first time through, but the static predictor will predict the branch to fall through. The static
prediction algorithm correctly predicts that the CALL CONVERT instruction will be taken, even before the
branch has any branch history in the BTB.
Example 3-7. Static Not-Taken Prediction
mov
and
imul
shld
jc
mov
Begin: call
eax, mem32
eax, ebx
eax, edx
eax, 7
Begin
eax, 0
Convert
3-7
GENERAL OPTIMIZATION GUIDELINES
The Intel Core microarchitecture does not use the static prediction heuristic. However, to maintain
consistency across Intel 64 and IA-32 processors, software should maintain the static prediction heuristic
as the default.
3.4.1.4
Inlining, Calls and Returns
The return address stack mechanism augments the static and dynamic predictors to optimize specifically
for calls and returns. It holds 16 entries, which is large enough to cover the call depth of most programs.
If there is a chain of more than 16 nested calls and more than 16 returns in rapid succession, performance may degrade.
The trace cache in Intel NetBurst microarchitecture maintains branch prediction information for calls and
returns. As long as the trace with the call or return remains in the trace cache and the call and return
targets remain unchanged, the depth limit of the return address stack described above will not impede
performance.
To enable the use of the return stack mechanism, calls and returns must be matched in pairs. If this is
done, the likelihood of exceeding the stack depth in a manner that will impact performance is very low.
The following rules apply to inlining, calls, and returns:
Assembly/Compiler Coding Rule 4. (MH impact, MH generality) Near calls must be matched with
near returns, and far calls must be matched with far returns. Pushing the return address on the stack
and jumping to the routine to be called is not recommended since it creates a mismatch in calls and
returns.
Calls and returns are expensive; use inlining for the following reasons:
•
•
•
Parameter passing overhead can be eliminated.
•
A mispredicted branch can lead to performance penalties inside a small function that are larger than
those that would occur if that function is inlined.
In a compiler, inlining a function exposes more opportunity for optimization.
If the inlined routine contains branches, the additional context of the caller may improve branch
prediction within the routine.
Assembly/Compiler Coding Rule 5. (MH impact, MH generality) Selectively inline a function if
doing so decreases code size or if the function is small and the call site is frequently executed.
Assembly/Compiler Coding Rule 6. (H impact, H generality) Do not inline a function if doing so
increases the working set size beyond what will fit in the trace cache.
Assembly/Compiler Coding Rule 7. (ML impact, ML generality) If there are more than 16 nested
calls and returns in rapid succession; consider transforming the program with inline to reduce the call
depth.
Assembly/Compiler Coding Rule 8. (ML impact, ML generality) Favor inlining small functions that
contain branches with poor prediction rates. If a branch misprediction results in a RETURN being
prematurely predicted as taken, a performance penalty may be incurred.
Assembly/Compiler Coding Rule 9. (L impact, L generality) If the last statement in a function is
a call to another function, consider converting the call to a jump. This will save the call/return overhead
as well as an entry in the return stack buffer.
Assembly/Compiler Coding Rule 10. (M impact, L generality) Do not put more than four
branches in a 16-byte chunk.
Assembly/Compiler Coding Rule 11. (M impact, L generality) Do not put more than two end loop
branches in a 16-byte chunk.
3.4.1.5
Code Alignment
Careful arrangement of code can enhance cache and memory locality. Likely sequences of basic blocks
should be laid out contiguously in memory. This may involve removing unlikely code, such as code to
handle error conditions, from the sequence. See Section 3.7, “Prefetching,” on optimizing the instruction
prefetcher.
3-8
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 12. (M impact, H generality) When executing code from the
DSB, direct branches that are mostly taken should have all their instruction bytes in a 64B cache line
and nearer the end of that cache line. Their targets should be at or near the beginning of a 64B cache
line.
When executing code from the legacy decode pipeline, direct branches that are mostly taken should have
all their instruction bytes in a 16B aligned chunk of memory and nearer the end of that 16B aligned
chunk. Their targets should be at or near the beginning of a 16B aligned chunk of memory.
Assembly/Compiler Coding Rule 13. (M impact, H generality) If the body of a conditional is not
likely to be executed, it should be placed in another part of the program. If it is highly unlikely to be
executed and code locality is an issue, it should be placed on a different code page.
3.4.1.6
Branch Type Selection
The default predicted target for indirect branches and calls is the fall-through path. Fall-through prediction is overridden if and when a hardware prediction is available for that branch. The predicted branch
target from branch prediction hardware for an indirect branch is the previously executed branch target.
The default prediction to the fall-through path is only a significant issue if no branch prediction is available, due to poor code locality or pathological branch conflict problems. For indirect calls, predicting the
fall-through path is usually not an issue, since execution will likely return to the instruction after the
associated return.
Placing data immediately following an indirect branch can cause a performance problem. If the data
consists of all zeros, it looks like a long stream of ADDs to memory destinations and this can cause
resource conflicts and slow down branch recovery. Also, data immediately following indirect branches
may appear as branches to the branch predication hardware, which can branch off to execute other data
pages. This can lead to subsequent self-modifying code problems.
Assembly/Compiler Coding Rule 14. (M impact, L generality) When indirect branches are
present, try to put the most likely target of an indirect branch immediately following the indirect
branch. Alternatively, if indirect branches are common but they cannot be predicted by branch
prediction hardware, then follow the indirect branch with a UD2 instruction, which will stop the
processor from decoding down the fall-through path.
Indirect branches resulting from code constructs (such as switch statements, computed GOTOs or calls
through pointers) can jump to an arbitrary number of locations. If the code sequence is such that the
target destination of a branch goes to the same address most of the time, then the BTB will predict accurately most of the time. Since only one taken (non-fall-through) target can be stored in the BTB, indirect
branches with multiple taken targets may have lower prediction rates.
The effective number of targets stored may be increased by introducing additional conditional branches.
Adding a conditional branch to a target is fruitful if:
•
The branch direction is correlated with the branch history leading up to that branch; that is, not just
the last target, but how it got to this branch.
•
The source/target pair is common enough to warrant using the extra branch prediction capacity. This
may increase the number of overall branch mispredictions, while improving the misprediction of
indirect branches. The profitability is lower if the number of mispredicting branches is very large.
User/Source Coding Rule 1. (M impact, L generality) If an indirect branch has two or more
common taken targets and at least one of those targets is correlated with branch history leading up to
the branch, then convert the indirect branch to a tree where one or more indirect branches are
preceded by conditional branches to those targets. Apply this “peeling” procedure to the common
target of an indirect branch that correlates to branch history.
The purpose of this rule is to reduce the total number of mispredictions by enhancing the predictability of
branches (even at the expense of adding more branches). The added branches must be predictable for
this to be worthwhile. One reason for such predictability is a strong correlation with preceding branch
history. That is, the directions taken on preceding branches are a good indicator of the direction of the
branch under consideration.
3-9
GENERAL OPTIMIZATION GUIDELINES
Example 3-8 shows a simple example of the correlation between a target of a preceding conditional
branch and a target of an indirect branch.
Example 3-8. Indirect Branch With Two Favored Targets
function ()
{
int n = rand();
// random integer 0 to RAND_MAX
if ( ! (n & 0x01) ) { // n will be 0 half the times
n = 0;
// updates branch history to predict taken
}
// indirect branches with multiple taken targets
// may have lower prediction rates
switch (n) {
case 0: handle_0(); break;
case 1: handle_1(); break;
case 3: handle_3(); break;
default: handle_other();
}
// common target, correlated with
// branch history that is forward taken
// uncommon
// uncommon
// common target
}
Correlation can be difficult to determine analytically, for a compiler and for an assembly language
programmer. It may be fruitful to evaluate performance with and without peeling to get the best performance from a coding effort.
An example of peeling out the most favored target of an indirect branch with correlated branch history is
shown in Example 3-9.
Example 3-9. A Peeling Technique to Reduce Indirect Branch Misprediction
function ()
{
int n = rand();
if( ! (n & 0x01) ) THEN
n = 0;
if (!n) THEN
handle_0();
// Random integer 0 to RAND_MAX
// n will be 0 half the times
// Peel out the most common target
// with correlated branch history
{
switch (n) {
case 1: handle_1(); break;
case 3: handle_3(); break;
default: handle_other();
}
}
}
3-10
// Uncommon
// Uncommon
// Make the favored target in
// the fall-through path
GENERAL OPTIMIZATION GUIDELINES
3.4.1.7
Loop Unrolling
Benefits of unrolling loops are:
•
Unrolling amortizes the branch overhead, since it eliminates branches and some of the code to
manage induction variables.
•
Unrolling allows one to aggressively schedule (or pipeline) the loop to hide latencies. This is useful if
you have enough free registers to keep variables live as you stretch out the dependence chain to
expose the critical path.
•
Unrolling exposes the code to various other optimizations, such as removal of redundant loads,
common subexpression elimination, and so on.
The potential costs of unrolling loops are:
•
Excessive unrolling or unrolling of very large loops can lead to increased code size. This can be
harmful if the unrolled loop no longer fits in the trace cache (TC).
•
Unrolling loops whose bodies contain branches increases demand on BTB capacity. If the number of
iterations of the unrolled loop is 16 or fewer, the branch predictor should be able to correctly predict
branches in the loop body that alternate direction.
Assembly/Compiler Coding Rule 15. (H impact, M generality) Unroll small loops until the
overhead of the branch and induction variable accounts (generally) for less than 10% of the execution
time of the loop.
Assembly/Compiler Coding Rule 16. (H impact, M generality) Avoid unrolling loops excessively;
this may thrash the trace cache or instruction cache.
Assembly/Compiler Coding Rule 17. (M impact, M generality) Unroll loops that are frequently
executed and have a predictable number of iterations to reduce the number of iterations to 16 or fewer.
Do this unless it increases code size so that the working set no longer fits in the trace or instruction
cache. If the loop body contains more than one conditional branch, then unroll so that the number of
iterations is 16/(# conditional branches).
Example 3-10 shows how unrolling enables other optimizations.
Example 3-10. Loop Unrolling
Before unrolling:
do i = 1, 100
if ( i mod 2 == 0 ) then a( i ) = x
else a( i ) = y
enddo
After unrolling
do i = 1, 100, 2
a( i ) = y
a( i+1 ) = x
enddo
In this example, the loop that executes 100 times assigns X to every even-numbered element and Y to
every odd-numbered element. By unrolling the loop you can make assignments more efficiently,
removing one branch in the loop body.
3.4.1.8
Compiler Support for Branch Prediction
Compilers generate code that improves the efficiency of branch prediction in Intel processors. The Intel
C++ Compiler accomplishes this by:
•
•
•
•
Keeping code and data on separate pages.
Using conditional move instructions to eliminate branches.
Generating code consistent with the static branch prediction algorithm.
Inlining where appropriate.
3-11
GENERAL OPTIMIZATION GUIDELINES
•
Unrolling if the number of iterations is predictable.
With profile-guided optimization, the compiler can lay out basic blocks to eliminate branches for the most
frequently executed paths of a function or at least improve their predictability. Branch prediction need
not be a concern at the source level. For more information, see Intel C++ Compiler documentation.
3.4.2
Fetch and Decode Optimization
Intel Core microarchitecture provides several mechanisms to increase front end throughput. Techniques
to take advantage of some of these features are discussed below.
3.4.2.1
Optimizing for Micro-fusion
An Instruction that operates on a register and a memory operand decodes into more micro-ops than its
corresponding register-register version. Replacing the equivalent work of the former instruction using
the register-register version usually require a sequence of two instructions. The latter sequence is likely
to result in reduced fetch bandwidth.
Assembly/Compiler Coding Rule 18. (ML impact, M generality) For improving fetch/decode
throughput, Give preference to memory flavor of an instruction over the register-only flavor of the
same instruction, if such instruction can benefit from micro-fusion.
The following examples are some of the types of micro-fusions that can be handled by all decoders:
•
All stores to memory, including store immediate. Stores execute internally as two separate microops: store-address and store-data.
•
All “read-modify” (load+op) instructions between register and memory, for example:
ADDPS XMM9, OWORD PTR [RSP+40]
FADD
DOUBLE PTR [RDI+RSI*8]
XOR
RAX, QWORD PTR [RBP+32]
•
All instructions of the form “load and jump,” for example:
JMP
[RDI+200]
RET
•
CMP and TEST with immediate operand and memory.
An Intel 64 instruction with RIP relative addressing is not micro-fused in the following cases:
•
When an additional immediate is needed, for example:
CMP
[RIP+400], 27
MOV
[RIP+3000], 142
•
When an RIP is needed for control flow purposes, for example:
JMP
[RIP+5000000]
In these cases, Intel Core microarchitecture and Intel microarchitecture code name Sandy Bridge
provides a 2 micro-op flow from decoder 0, resulting in a slight loss of decode bandwidth since 2 microop flow must be steered to decoder 0 from the decoder with which it was aligned.
RIP addressing may be common in accessing global data. Since it will not benefit from micro-fusion,
compiler may consider accessing global data with other means of memory addressing.
3.4.2.2
Optimizing for Macro-fusion
Macro-fusion merges two instructions to a single micro-op. Intel Core microarchitecture performs this
hardware optimization under limited circumstances.
The first instruction of the macro-fused pair must be a CMP or TEST instruction. This instruction can be
REG-REG, REG-IMM, or a micro-fused REG-MEM comparison. The second instruction (adjacent in the
instruction stream) should be a conditional branch.
Since these pairs are common ingredient in basic iterative programming sequences, macro-fusion
improves performance even on un-recompiled binaries. All of the decoders can decode one macro-fused
3-12
GENERAL OPTIMIZATION GUIDELINES
pair per cycle, with up to three other instructions, resulting in a peak decode bandwidth of 5 instructions
per cycle.
Each macro-fused instruction executes with a single dispatch. This process reduces latency, which in this
case shows up as a cycle removed from branch mispredict penalty. Software also gain all other fusion
benefits: increased rename and retire bandwidth, more storage for instructions in-flight, and power
savings from representing more work in fewer bits.
The following list details when you can use macro-fusion:
•
CMP or TEST can be fused when comparing:
REG-REG. For example: CMP EAX,ECX; JZ label
REG-IMM. For example: CMP EAX,0x80; JZ label
REG-MEM. For example: CMP EAX,[ECX]; JZ label
MEM-REG. For example: CMP [EAX],ECX; JZ label
•
•
TEST can fused with all conditional jumps.
CMP can be fused with only the following conditional jumps in Intel Core microarchitecture. These
conditional jumps check carry flag (CF) or zero flag (ZF). jump. The list of macro-fusion-capable
conditional jumps are:
JA or JNBE
JAE or JNB or JNC
JE or JZ
JNA or JBE
JNAE or JC or JB
JNE or JNZ
CMP and TEST can not be fused when comparing MEM-IMM (e.g. CMP [EAX],0x80; JZ label). Macrofusion is not supported in 64-bit mode for Intel Core microarchitecture.
•
Intel microarchitecture code name Nehalem supports the following enhancements in macrofusion:
— CMP can be fused with the following conditional jumps (that was not supported in Intel Core
microarchitecture):
•
•
•
•
JL or JNGE
JGE or JNL
JLE or JNG
JG or JNLE
— Macro-fusion is support in 64-bit mode.
•
Enhanced macrofusion support in Intel microarchitecture code name Sandy Bridge is summarized in
Table 3-1 with additional information in Section 2.4.2.1 and Example 3-15:
Table 3-1. Macro-Fusible Instructions in Intel Microarchitecture Code Name Sandy Bridge
Instructions
TEST
AND
CMP
ADD
SUB
INC
DEC
JO/JNO
Y
Y
N
N
N
N
N
JC/JB/JAE/JNB
Y
Y
Y
Y
Y
N
N
JE/JZ/JNE/JNZ
Y
Y
Y
Y
Y
Y
Y
JNA/JBE/JA/JNBE
Y
Y
Y
Y
Y
N
N
JS/JNS/JP/JPE/JNP/JPO
Y
Y
N
N
N
N
N
JL/JNGE/JGE/JNL/JLE/JNG/JG/JNLE
Y
Y
Y
Y
Y
Y
Y
3-13
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 19. (M impact, ML generality) Employ macro-fusion where
possible using instruction pairs that support macro-fusion. Prefer TEST over CMP if possible. Use
unsigned variables and unsigned jumps when possible. Try to logically verify that a variable is nonnegative at the time of comparison. Avoid CMP or TEST of MEM-IMM flavor when possible. However, do
not add other instructions to avoid using the MEM-IMM flavor.
Example 3-11. Macro-fusion, Unsigned Iteration Count
Without Macro-fusion
1
With Macro-fusion
C code
for (int i = 0; i < 1000; i++)
a++;
for ( unsigned int2 i = 0; i < 1000; i++)
a++;
Disassembly
for (int i = 0; i < 1000; i++)
mov
dword ptr [ i ], 0
jmp
First
Loop:
mov
eax, dword ptr [ i ]
add
eax, 1
mov
dword ptr [ i ], eax
for ( unsigned int i = 0; i < 1000; i++)
xor
eax, eax
mov
dword ptr [ i ], eax
jmp
First
Loop:
mov
eax, dword ptr [ i ]
add
eax, 1
mov
dword ptr [ i ], eax
First:
cmp
jge
First:
cmp
jae
dword ptr [ i ], 3E8H3
End
a++;
mov
eax, dword ptr [ a ]
addqq eax,1
mov
dword ptr [ a ], eax
jmp
Loop
End:
mov
add
mov
jmp
End:
eax, 3E8H 4
End
a++;
eax, dword ptr [ a ]
eax, 1
dword ptr [ a ], eax
Loop
NOTES:
1. Signed iteration count inhibits macro-fusion.
2. Unsigned iteration count is compatible with macro-fusion.
3. CMP MEM-IMM, JGE inhibit macro-fusion.
4. CMP REG-IMM, JAE permits macro-fusion.
Example 3-12. Macro-fusion, If Statement
Without Macro-fusion
With Macro-fusion
C code
int1
a = 7;
if ( a < 77 )
a++;
else
a--;
unsigned int2 a = 7;
if ( a < 77 )
a++;
else
a--;
Disassembly
int a = 7;
mov
dword ptr [ a ], 7
if (a < 77)
cmp
dword ptr [ a ], 4DH 3
jge
Dec
unsigned int a = 7;
mov
dword ptr [ a ], 7
if ( a < 77 )
mov
eax, dword ptr [ a ]
cmp
eax, 4DH
jae
Dec
3-14
GENERAL OPTIMIZATION GUIDELINES
Example 3-12. Macro-fusion, If Statement (Contd.)
Without Macro-fusion
With Macro-fusion
a++;
mov
eax, dword ptr [ a ]
add
eax, 1
mov
dword ptr [a], eax
else
jmp
End
a--;
Dec:
mov
eax, dword ptr [ a ]
sub
eax, 1
mov
dword ptr [ a ], eax
End::
add
mov
else
jmp
Dec:
sub
mov
End::
a++;
eax,1
dword ptr [ a ], eax
End
a--;
eax, 1
dword ptr [ a ], eax
NOTES:
1. Signed iteration count inhibits macro-fusion.
2. Unsigned iteration count is compatible with macro-fusion.
3. CMP MEM-IMM, JGE inhibit macro-fusion.
Assembly/Compiler Coding Rule 20. (M impact, ML generality) Software can enable macro
fusion when it can be logically determined that a variable is non-negative at the time of comparison;
use TEST appropriately to enable macro-fusion when comparing a variable with 0.
Example 3-13. Macro-fusion, Signed Variable
Without Macro-fusion
test
ecx, ecx
jle
OutSideTheIF
cmp
ecx, 64H
jge
OutSideTheIF
<IF BLOCK CODE>
OutSideTheIF:
With Macro-fusion
test
ecx, ecx
jle
OutSideTheIF
cmp
ecx, 64H
jae
OutSideTheIF
<IF BLOCK CODE>
OutSideTheIF:
For either signed or unsigned variable ‘a’; “CMP a,0” and “TEST a,a” produce the same result as far as the
flags are concerned. Since TEST can be macro-fused more often, software can use “TEST a,a” to replace
“CMP a,0” for the purpose of enabling macro-fusion.
Example 3-14. Macro-fusion, Signed Comparison
C Code
Without Macro-fusion
With Macro-fusion
if (a == 0)
cmp a, 0
jne lbl
...
lbl:
test a, a
jne lbl
...
lbl:
if ( a >= 0)
cmp a, 0
jl lbl;
...
lbl:
test a, a
jl lbl
...
lbl:
Intel microarchitecture code name Sandy Bridge enables more arithmetic and logic instructions to
macro-fuse with conditional branches. In loops where the ALU ports are already congested, performing
one of these macro-fusions can relieve the pressure, as the macro-fused instruction consumes only port
5, instead of an ALU port plus port 5.
In Example 3-15, the “add/cmp/jnz” loop contains two ALU instructions that can be dispatched via either
port 0, 1, 5. So there is higher probability of port 5 might bind to either ALU instruction causing JNZ to
3-15
GENERAL OPTIMIZATION GUIDELINES
wait a cycle. The “sub/jnz” loop, the likelihood of ADD/SUB/JNZ can be dispatched in the same cycle is
increased because only SUB is free to bind with either port 0, 1, 5.
Example 3-15. Additional Macro-fusion Benefit in Intel Microarchitecture Code Name Sandy Bridge
Add + cmp + jnz alternative
Loop control with sub + jnz
lea
xor
xor
loop:
add
add
cmp
jnz
3.4.2.3
rdx, buff
rcx, rcx
eax, eax
eax, [rdx + 4 * rcx]
rcx, 1
rcx, LEN
loop
lea
xor
xor
loop:
add
sub
jnz
rdx, buff - 4
rcx, LEN
eax, eax
eax, [rdx + 4 * rcx]
rcx, 1
loop
Length-Changing Prefixes (LCP)
The length of an instruction can be up to 15 bytes in length. Some prefixes can dynamically change the
length of an instruction that the decoder must recognize. Typically, the pre-decode unit will estimate the
length of an instruction in the byte stream assuming the absence of LCP. When the predecoder encounters an LCP in the fetch line, it must use a slower length decoding algorithm. With the slower length
decoding algorithm, the predecoder decodes the fetch in 6 cycles, instead of the usual 1 cycle. Normal
queuing throughout of the machine pipeline generally cannot hide LCP penalties.
The prefixes that can dynamically change the length of a instruction include:
•
•
Operand size prefix (0x66).
Address size prefix (0x67).
The instruction MOV DX, 01234h is subject to LCP stalls in processors based on Intel Core microarchitecture, and in Intel Core Duo and Intel Core Solo processors. Instructions that contain imm16 as part of
their fixed encoding but do not require LCP to change the immediate size are not subject to LCP stalls.
The REX prefix (4xh) in 64-bit mode can change the size of two classes of instruction, but does not cause
an LCP penalty.
If the LCP stall happens in a tight loop, it can cause significant performance degradation. When decoding
is not a bottleneck, as in floating-point heavy code, isolated LCP stalls usually do not cause performance
degradation.
Assembly/Compiler Coding Rule 21. (MH impact, MH generality) Favor generating code using
imm8 or imm32 values instead of imm16 values.
If imm16 is needed, load equivalent imm32 into a register and use the word value in the register instead.
Double LCP Stalls
Instructions that are subject to LCP stalls and cross a 16-byte fetch line boundary can cause the LCP stall
to trigger twice. The following alignment situations can cause LCP stalls to trigger twice:
•
An instruction is encoded with a MODR/M and SIB byte, and the fetch line boundary crossing is
between the MODR/M and the SIB bytes.
•
An instruction starts at offset 13 of a fetch line references a memory location using register and
immediate byte offset addressing mode.
The first stall is for the 1st fetch line, and the 2nd stall is for the 2nd fetch line. A double LCP stall causes
a decode penalty of 11 cycles.
3-16
GENERAL OPTIMIZATION GUIDELINES
The following examples cause LCP stall once, regardless of their fetch-line location of the first byte of the
instruction:
ADD DX, 01234H
ADD word ptr [EDX], 01234H
ADD word ptr 012345678H[EDX], 01234H
ADD word ptr [012345678H], 01234H
The following instructions cause a double LCP stall when starting at offset 13 of a fetch line:
ADD word ptr [EDX+ESI], 01234H
ADD word ptr 012H[EDX], 01234H
ADD word ptr 012345678H[EDX+ESI], 01234H
To avoid double LCP stalls, do not use instructions subject to LCP stalls that use SIB byte encoding or
addressing mode with byte displacement.
False LCP Stalls
False LCP stalls have the same characteristics as LCP stalls, but occur on instructions that do not have
any imm16 value.
False LCP stalls occur when (a) instructions with LCP that are encoded using the F7 opcodes, and (b) are
located at offset 14 of a fetch line. These instructions are: not, neg, div, idiv, mul, and imul. False LCP
experiences delay because the instruction length decoder can not determine the length of the instruction
before the next fetch line, which holds the exact opcode of the instruction in its MODR/M byte.
The following techniques can help avoid false LCP stalls:
•
•
Upcast all short operations from the F7 group of instructions to long, using the full 32 bit version.
Ensure that the F7 opcode never starts at offset 14 of a fetch line.
Assembly/Compiler Coding Rule 22. (M impact, ML generality) Ensure instructions using 0xF7
opcode byte does not start at offset 14 of a fetch line; and avoid using these instruction to operate on
16-bit data, upcast short data to 32 bits.
Example 3-16. Avoiding False LCP Delays with 0xF7 Group Instructions
A Sequence Causing Delay in the Decoder
Alternate Sequence to Avoid Delay
neg word ptr a
3.4.2.4
movsx eax, word ptr a
neg
eax
mov
word ptr a, AX
Optimizing the Loop Stream Detector (LSD)
Loops that fit the following criteria are detected by the LSD and replayed from the instruction queue to
feed the decoder in Intel Core microarchitecture:
•
•
•
•
Must be less than or equal to four 16-byte fetches.
Must be less than or equal to 18 instructions.
Can contain no more than four taken branches and none of them can be a RET.
Should usually have more than 64 iterations.
Loop Stream Detector in Intel microarchitecture code name Nehalem is improved by:
•
Caching decoded micro-operations in the instruction decoder queue (IDQ, see Section 2.6.2) to feed
the rename/alloc stage.
•
The size of the LSD is increased to 28 micro-ops.
3-17
GENERAL OPTIMIZATION GUIDELINES
The LSD and micro-op queue implementation continue to improve in Sandy Bridge and Haswell microarchitectures. They have the following characteristics:
Table 3-2. Small Loop Criteria Detected by Sandy Bridge and Haswell Microarchitectures
Sandy Bridge and Ivy Bridge microarchitectures
Haswell microarchitecture
Up to 8 chunk fetches of 32 instruction bytes
8 chunk fetches if HTT active, 11 chunk fetched if HTT
off
Up to 28 micro ops
28 micro-ops if HTT active, 56 micro-ops if HTT off
All micro-ops resident in Decoded Icache ( i.e. DSB), but not
from MSROM
All micro-ops resident in DSB, including micro-ops from
MSRROM
No more than 8 taken branches
Relaxed
Exclude CALL and RET
Exclude CALL and RET
Mismatched stack operation disqualify
Same
Many calculation-intensive loops, searches and software string moves match these characteristics. These
loops exceed the BPU prediction capacity and always terminate in a branch misprediction.
Assembly/Compiler Coding Rule 23. (MH impact, MH generality) Break up a loop long sequence
of instructions into loops of shorter instruction blocks of no more than the size of LSD.
Assembly/Compiler Coding Rule 24. (MH impact, M generality) Avoid unrolling loops containing
LCP stalls, if the unrolled block exceeds the size of LSD.
3.4.2.5
Exploit LSD Micro-op Emission Bandwidth in Intel® Microarchitecture Code Name
Sandy Bridge
The LSD holds micro-ops that construct small “infinite” loops. Micro-ops from the LSD are allocated in the
out-of-order engine. The loop in the LSD ends with a taken branch to the beginning of the loop. The taken
branch at the end of the loop is always the last micro-op allocated in the cycle. The instruction at the
beginning of the loop is always allocated at the next cycle. If the code performance is bound by front end
bandwidth, unused allocation slots result in a bubble in allocation, and can cause performance degradation.
Allocation bandwidth in Intel microarchitecture code name Sandy Bridge is four micro-ops per cycle.
Performance is best, when the number of micro-ops in the LSD result in the least number of unused allocation slots. You can use loop unrolling to control the number of micro-ops that are in the LSD.
In the Example 3-17, the code sums all array elements. The original code adds one element per iteration.
It has three micro-ops per iteration, all allocated in one cycle. Code throughput is one load per cycle.
When unrolling the loop once there are five micro-ops per iteration, which are allocated in two cycles.
Code throughput is still one load per cycle. Therefore there is no performance gain.
When unrolling the loop twice there are seven micro-ops per iteration, still allocated in two cycles. Since
two loads can be executed in each cycle this code has a potential throughput of three load operations in
two cycles.
.
Example 3-17. Unrolling Loops in LSD to Optimize Emission Bandwidth
No Unrolling
Unroll once
lp: add eax, [rsi + 4* rcx]
dec rcx
jnz lp
3-18
lp: add eax, [rsi + 4* rcx]
add eax, [rsi + 4* rcx +4]
add rcx, -2
jnz lp
Unroll Twice
lp: add eax, [rsi + 4* rcx]
add eax, [rsi + 4* rcx +4]
add eax, [rsi + 4* rcx + 8]
add rcx, -3
jnz lp
GENERAL OPTIMIZATION GUIDELINES
3.4.2.6
Optimization for Decoded ICache
The decoded ICache is a new feature in Intel microarchitecture code name Sandy Bridge. Running the
code from the Decoded ICache has two advantages:
•
•
Higher bandwidth of micro-ops feeding the out-of-order engine.
The front end does not need to decode the code that is in the Decoded ICache. This saves power.
There is overhead in switching between the Decoded ICache and the legacy decode pipeline. If your code
switches frequently between the front end and the Decoded ICache, the penalty may be higher than
running only from the legacy pipeline.
To ensure “hot” code is feeding from the decoded ICache:
•
Make sure each hot code block is less than about 500 instructions. Specifically, do not unroll to more
than 500 instructions in a loop. This should enable Decoded ICache residency even when hyperthreading is enabled.
•
For applications with very large blocks of calculations inside a loop, consider loop-fission: split the
loop into multiple loops that fit in the Decoded ICache, rather than a single loop that overflows.
•
If an application can be sure to run with only one thread per core, it can increase hot code block size
to about 1000 instructions.
Dense Read-Modify-Write Code
The Decoded ICache can hold only up to 18 micro-ops per each 32 byte aligned memory chunk. Therefore, code with a high concentration of instructions that are encoded in a small number of bytes, yet have
many micro-ops, may overflow the 18 micro-op limitation and not enter the Decoded ICache. Readmodify-write (RMW) instructions are a good example of such instructions.
RMW instructions accept one memory source operand, one register source operand, and use the source
memory operand as the destination. The same functionality can be achieved by two or three instructions:
the first reads the memory source operand, the second performs the operation with the second register
source operand, and the last writes the result back to memory. These instructions usually result in the
same number of micro-ops but use more bytes to encode the same functionality.
One case where RMW instructions may be used extensively is when the compiler optimizes aggressively
for code size.
Here are some possible solutions to fit the hot code in the Decoded ICache:
•
Replace RMW instructions with two or three instructions that have the same functionality. For
example, “adc [rdi], rcx“ is only three bytes long; the equivalent sequence “adc rax, [rdi]“ + “mov
[rdi], rax“ has a footprint of six bytes.
•
Align the code so that the dense part is broken down among two different 32-byte chunks. This
solution is useful when using a tool that aligns code automatically, and is indifferent to code changes.
•
Spread the code by adding multiple byte NOPs in the loop. Note that this solution adds micro-ops for
execution.
Align Unconditional Branches for Decoded ICache
For code entering the Decoded ICache, each unconditional branch is the last micro-op occupying a
Decoded ICache Way. Therefore, only three unconditional branches per a 32 byte aligned chunk can
enter the Decoded ICache.
Unconditional branches are frequent in jump tables and switch declarations. Below are examples for
these constructs, and methods for writing them so that they fit in the Decoded ICache.
Compilers create jump tables for C++ virtual class methods or DLL dispatch tables. Each unconditional
branch consumes five bytes; therefore up to seven of them can be associated with a 32-byte chunk. Thus
jump tables may not fit in the Decoded ICache if the unconditional branches are too dense in each
32Byte-aligned chunk. This can cause performance degradation for code executing before and after the
branch table.
The solution is to add multi-byte NOP instructions among the branches in the branch table. This may
increases code size and should be used cautiously. However, these NOPs are not executed and therefore
have no penalty in later pipe stages.
3-19
GENERAL OPTIMIZATION GUIDELINES
Switch-Case constructs represents a similar situation. Each evaluation of a case condition results in an
unconditional branch. The same solution of using multi-byte NOP can apply for every three consecutive
unconditional branches that fits inside an aligned 32-byte chunk.
Two Branches in a Decoded ICache Way
The Decoded ICache can hold up to two branches in a way. Dense branches in a 32 byte aligned chunk,
or their ordering with other instructions may prohibit all the micro-ops of the instructions in the chunk
from entering the Decoded ICache. This does not happen often. When it does happen, you can space the
code with NOP instructions where appropriate. Make sure that these NOP instructions are not part of hot
code.
Assembly/Compiler Coding Rule 25. (M impact, M generality) Avoid putting explicit references to
ESP in a sequence of stack operations (POP, PUSH, CALL, RET).
3.4.2.7
Other Decoding Guidelines
Assembly/Compiler Coding Rule 26. (ML impact, L generality) Use simple instructions that are
less than eight bytes in length.
Assembly/Compiler Coding Rule 27. (M impact, MH generality) Avoid using prefixes to change
the size of immediate and displacement.
Long instructions (more than seven bytes) may limit the number of decoded instructions per cycle. Each
prefix adds one byte to the length of instruction, possibly limiting the decoder’s throughput. In addition,
multiple prefixes can only be decoded by the first decoder. These prefixes also incur a delay when
decoded. If multiple prefixes or a prefix that changes the size of an immediate or displacement cannot be
avoided, schedule them behind instructions that stall the pipe for some other reason.
3.5
OPTIMIZING THE EXECUTION CORE
The superscalar, out-of-order execution core(s) in recent generations of microarchitectures contain
multiple execution hardware resources that can execute multiple micro-ops in parallel. These resources
generally ensure that micro-ops execute efficiently and proceed with fixed latencies. General guidelines
to make use of the available parallelism are:
•
Follow the rules (see Section 3.4) to maximize useful decode bandwidth and front end throughput.
These rules include favouring single micro-op instructions and taking advantage of micro-fusion,
Stack pointer tracker and macro-fusion.
•
Maximize rename bandwidth. Guidelines are discussed in this section and include properly dealing
with partial registers, ROB read ports and instructions which causes side-effects on flags.
•
Scheduling recommendations on sequences of instructions so that multiple dependency chains are
alive in the reservation station (RS) simultaneously, thus ensuring that your code utilizes maximum
parallelism.
•
Avoid hazards, minimize delays that may occur in the execution core, allowing the dispatched microops to make progress and be ready for retirement quickly.
3.5.1
Instruction Selection
Some execution units are not pipelined, this means that micro-ops cannot be dispatched in consecutive
cycles and the throughput is less than one per cycle.
It is generally a good starting point to select instructions by considering the number of micro-ops associated with each instruction, favoring in the order of: single micro-op instructions, simple instruction with
less then 4 micro-ops, and last instruction requiring microsequencer ROM (micro-ops which are executed
out of the microsequencer involve extra overhead).
3-20
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 28. (M impact, H generality) Favor single-micro-operation
instructions. Also favor instruction with shorter latencies.
A compiler may be already doing a good job on instruction selection. If so, user intervention usually is not
necessary.
Assembly/Compiler Coding Rule 29. (M impact, L generality) Avoid prefixes, especially multiple
non-0F-prefixed opcodes.
Assembly/Compiler Coding Rule 30. (M impact, L generality) Do not use many segment
registers.
Assembly/Compiler Coding Rule 31. (M impact, M generality) Avoid using complex instructions
(for example, enter, leave, or loop) that have more than four µops and require multiple cycles to
decode. Use sequences of simple instructions instead.
Assembly/Compiler Coding Rule 32. (MH impact, M generality) Use push/pop to manage stack
space and address adjustments between function calls/returns instead of enter/leave. Using enter
instruction with non-zero immediates can experience significant delays in the pipeline in addition to
misprediction.
Theoretically, arranging instructions sequence to match the 4-1-1-1 template applies to processors
based on Intel Core microarchitecture. However, with macro-fusion and micro-fusion capabilities in the
front end, attempts to schedule instruction sequences using the 4-1-1-1 template will likely provide
diminishing returns.
Instead, software should follow these additional decoder guidelines:
•
If you need to use multiple micro-op, non-microsequenced instructions, try to separate by a few
single micro-op instructions. The following instructions are examples of multiple micro-op instruction
not requiring micro-sequencer:
ADC/SBB
CMOVcc
Read-modify-write instructions
•
If a series of multiple micro-op instructions cannot be separated, try breaking the series into a
different equivalent instruction sequence. For example, a series of read-modify-write instructions
may go faster if sequenced as a series of read-modify + store instructions. This strategy could
improve performance even if the new code sequence is larger than the original one.
3.5.1.1
Integer Divide
Typically, an integer divide is preceded by a CWD or CDQ instruction. Depending on the operand size,
divide instructions use DX:AX or EDX:EAX for the dividend. The CWD or CDQ instructions sign-extend AX
or EAX into DX or EDX, respectively. These instructions have denser encoding than a shift and move
would be, but they generate the same number of micro-ops. If AX or EAX is known to be positive, replace
these instructions with:
xor dx, dx
or
xor edx, edx
Modern compilers typically can transform high-level language expression involving integer division where
the divisor is a known integer constant at compile time into a faster sequence using IMUL instruction
instead. Thus programmers should minimize integer division expression with divisor whose value can not
be known at compile time.
Alternately, if certain known divisor value are favored over other unknown ranges, software may consider
isolating the few favored, known divisor value into constant-divisor expressions.
Section 10.2.4 describes more detail of using MUL/IMUL to replace integer divisions.
3-21
GENERAL OPTIMIZATION GUIDELINES
3.5.1.2
Using LEA
In Intel microarchitecture code name Sandy Bridge, there are two significant changes to the performance characteristics of LEA instruction:
•
LEA can be dispatched via port 1 and 5 in most cases, doubling the throughput over prior generations. However this apply only to LEA instructions with one or two source operands.
Example 3-18. Independent Two-Operand LEA Example
mov
mov
mov
loop:
lea
lea
and
and
dec
jg
•
edx, N
eax, X
ecx, Y
ecx, [ecx + ecx]
eax, [eax + eax *4]
ecx, 0xff
eax, 0xff
edx
loop
// ecx = ecx*2
// eax = eax*5
For LEA instructions with three source operands and some specific situations, instruction latency has
increased to 3 cycles, and must dispatch via port 1:
— LEA that has all three source operands: base, index, and offset.
— LEA that uses base and index registers where the base is EBP, RBP, or R13.
— LEA that uses RIP relative addressing mode.
— LEA that uses 16-bit addressing mode.
3-22
GENERAL OPTIMIZATION GUIDELINES
.
Example 3-19. Alternative to Three-Operand LEA
3 operand LEA is slower
Two-operand LEA alternative
Alternative 2
#define K 1
uint32 an = 0;
uint32 N= mi_N;
mov ecx, N
xor esi, esi;
xor edx, edx;
cmp ecx, 2;
jb finished;
dec ecx;
#define K 1
uint32 an = 0;
uint32 N= mi_N;
mov ecx, N
xor esi, esi;
xor edx, edx;
cmp ecx, 2;
jb finished;
dec ecx;
#define K 1
uint32 an = 0;
uint32 N= mi_N;
mov ecx, N
xor esi, esi;
mov edx, K;
cmp ecx, 2;
jb finished;
mov eax, 2
dec ecx;
loop1:
mov edi, esi;
lea esi, [K+esi+edx];
and esi, 0xFF;
mov edx, edi;
dec ecx;
jnz loop1;
finished:
mov [an] ,esi;
loop1:
mov edi, esi;
lea esi, [K+edx];
lea esi, [esi+edx];
and esi, 0xFF;
mov edx, edi;
dec ecx;
jnz loop1;
finished:
mov [an] ,esi;
loop1:
mov edi, esi;
lea esi, [esi+edx];
and esi, 0xFF;
lea edx, [edi +K];
dec ecx;
jnz loop1;
finished:
mov [an] ,esi;
In some cases with processor based on Intel NetBurst microarchitecture, the LEA instruction or a
sequence of LEA, ADD, SUB and SHIFT instructions can replace constant multiply instructions. The LEA
instruction can also be used as a multiple operand addition instruction, for example:
LEA ECX, [EAX + EBX + 4 + A]
Using LEA in this way may avoid register usage by not tying up registers for operands of arithmetic
instructions. This use may also save code space.
If the LEA instruction uses a shift by a constant amount then the latency of the sequence of µops is
shorter if adds are used instead of a shift, and the LEA instruction may be replaced with an appropriate
sequence of µops. This, however, increases the total number of µops, leading to a trade-off.
Assembly/Compiler Coding Rule 33. (ML impact, L generality) If an LEA instruction using the
scaled index is on the critical path, a sequence with ADDs may be better. If code density and bandwidth
out of the trace cache are the critical factor, then use the LEA instruction.
3.5.1.3
ADC and SBB in Intel® Microarchitecture Code Name Sandy Bridge
The throughput of ADC and SBB in Intel microarchitecture code name Sandy Bridge is 1 cycle, compared
to 1.5-2 cycles in prior generation. These two instructions are useful in numeric handling of integer data
types that are wider than the maximum width of native hardware.
3-23
GENERAL OPTIMIZATION GUIDELINES
Example 3-20. Examples of 512-bit Additions
//Add 64-bit to 512 Number
lea
rsi, gLongCounter
lea
rdi, gStepValue
mov
rax, [rdi]
xor
rcx, rcx
oop_start:
mov
r10, [rsi+rcx]
add
r10, rax
mov
[rsi+rcx], r10
l
mov
adc
mov
r10, [rsi+rcx+8]
r10, 0
[rsi+rcx+8], r10
mov
adc
mov
mov
adc
mov
r10, [rsi+rcx+16]
r10, 0
[rsi+rcx+16], r10
r10, [rsi+rcx+24]
r10, 0
[rsi+rcx+24], r10
mov
adc
mov
r10, [rsi+rcx+32]
r10, 0
[rsi+rcx+32], r10
mov r10, [rsi+rcx+40]
adc r10, 0
mov [rsi+rcx+40], r10
mov r10, [rsi+rcx+48]
adc r10, 0
mov [rsi+rcx+48], r10
mov r10, [rsi+rcx+56]
adc r10, 0
mov [rsi+rcx+56], r10
add rcx, 64
cmp rcx, SIZE
jnz loop_start
3.5.1.4
// 512-bit Addition
loop1:
mov
rax, [StepValue]
add
rax, [LongCounter]
mov
LongCounter, rax
mov
rax, [StepValue+8]
adc
rax, [LongCounter+8]
mov
LongCounter+8, rax
mov
rax, [StepValue+16]
adc
rax, [LongCounter+16]
mov
mov
adc
LongCounter+16, rax
rax, [StepValue+24]
rax, [LongCounter+24]
mov
mov
adc
LongCounter+24, rax
rax, [StepValue+32]
rax, [LongCounter+32]
mov
mov
adc
LongCounter+32, rax
rax, [StepValue+40]
rax, [LongCounter+40]
mov
mov
adc
LongCounter+40, rax
rax, [StepValue+48]
rax, [LongCounter+48]
mov
mov
adc
LongCounter+48, rax
rax, [StepValue+56]
rax, [LongCounter+56]
mov
dec
jnz
LongCounter+56, rax
rcx
loop1
Bitwise Rotation
Bitwise rotation can choose between rotate with count specified in the CL register, an immediate constant
and by 1 bit. Generally, The rotate by immediate and rotate by register instructions are slower than
rotate by 1 bit. The rotate by 1 instruction has the same latency as a shift.
3-24
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 34. (ML impact, L generality) Avoid ROTATE by register or
ROTATE by immediate instructions. If possible, replace with a ROTATE by 1 instruction.
In Intel microarchitecture code name Sandy Bridge, ROL/ROR by immediate has 1-cycle throughput,
SHLD/SHRD using the same register as source and destination by an immediate constant has 1-cycle
latency with 0.5 cycle throughput. The “ROL/ROR reg, imm8” instruction has two micro-ops with the
latency of 1-cycle for the rotate register result and 2-cycles for the flags, if used.
In Intel microarchitecture code name Ivy Bridge, The “ROL/ROR reg, imm8” instruction with immediate
greater than 1, is one micro-op with one-cycle latency when the overflow flag result is used. When the
immediate is one, dependency on the overflow flag result of ROL/ROR by a subsequent instruction will
see the ROL/ROR instruction with two-cycle latency.
3.5.1.5
Variable Bit Count Rotation and Shift
In Intel microarchitecture code name Sandy Bridge, The “ROL/ROR/SHL/SHR reg, cl” instruction has
three micro-ops. When the flag result is not needed, one of these micro-ops may be discarded, providing
better performance in many common usages. When these instructions update partial flag results that are
subsequently used, the full three micro-ops flow must go through the execution and retirement pipeline,
experiencing slower performance. In Intel microarchitecture code name Ivy Bridge, executing the full
three micro-ops flow to use the updated partial flag result has additional delay. Consider the looped
sequence below:
loop:
shl eax, cl
add ebx, eax
dec edx ; DEC does not update carry, causing SHL to execute slower three micro-ops flow
jnz loop
The DEC instruction does not modify the carry flag. Consequently, the SHL EAX, CL instruction needs to
execute the three micro-ops flow in subsequent iterations. The SUB instruction will update all flags. So
replacing DEC with SUB will allow SHL EAX, CL to execute the two micro-ops flow.
3.5.1.6
Address Calculations
For computing addresses, use the addressing modes rather than general-purpose computations. Internally, memory reference instructions can have four operands:
•
•
•
•
Relocatable load-time constant.
Immediate constant.
Base register.
Scaled index register.
Note that the latency and throughput of LEA with more than two operands are slower (see Section
3.5.1.2) in Intel microarchitecture code name Sandy Bridge. Addressing modes that uses both base and
index registers will consume more read port resource in the execution engine and may experience more
stalls due to availability of read port resources. Software should take care by selecting the speedy version
of address calculation.
In the segmented model, a segment register may constitute an additional operand in the linear address
calculation. In many cases, several integer instructions can be eliminated by fully using the operands of
memory references.
3-25
GENERAL OPTIMIZATION GUIDELINES
3.5.1.7
Clearing Registers and Dependency Breaking Idioms
Code sequences that modifies partial register can experience some delay in its dependency chain, but
can be avoided by using dependency breaking idioms.
In processors based on Intel Core microarchitecture, a number of instructions can help clear execution
dependency when software uses these instruction to clear register content to zero. The instructions
include:
XOR REG, REG
SUB REG, REG
XORPS/PD XMMREG, XMMREG
PXOR XMMREG, XMMREG
SUBPS/PD XMMREG, XMMREG
PSUBB/W/D/Q XMMREG, XMMREG
In processors based on Intel microarchitecture code name Sandy Bridge, the instruction listed above plus
equivalent AVX counter parts are also zero idioms that can be used to break dependency chains. Furthermore, they do not consume an issue port or an execution unit. So using zero idioms are preferable than
moving 0’s into the register. The AVX equivalent zero idioms are:
VXORPS/PD XMMREG, XMMREG
VXORPS/PD YMMREG, YMMREG
VPXOR XMMREG, XMMREG
VSUBPS/PD XMMREG, XMMREG
VSUBPS/PD YMMREG, YMMREG
VPSUBB/W/D/Q XMMREG, XMMREG
In Intel Core Solo and Intel Core Duo processors, the XOR, SUB, XORPS, or PXOR instructions can be
used to clear execution dependencies on the zero evaluation of the destination register.
The Pentium 4 processor provides special support for XOR, SUB, and PXOR operations when executed
within the same register. This recognizes that clearing a register does not depend on the old value of the
register. The XORPS and XORPD instructions do not have this special support. They cannot be used to
break dependence chains.
Assembly/Compiler Coding Rule 35. (M impact, ML generality) Use dependency-breaking-idiom
instructions to set a register to 0, or to break a false dependence chain resulting from re-use of
registers. In contexts where the condition codes must be preserved, move 0 into the register instead.
This requires more code space than using XOR and SUB, but avoids setting the condition codes.
Example 3-21 of using pxor to break dependency idiom on a XMM register when performing negation on
the elements of an array.
int a[4096], b[4096], c[4096];
For ( int i = 0; i < 4096; i++ )
C[i] = - ( a[i] + b[i] );
3-26
GENERAL OPTIMIZATION GUIDELINES
Example 3-21. Clearing Register to Break Dependency While Negating Array Elements
Negation (-x = (x XOR (-1)) - (-1) without breaking
Negation (-x = 0 -x) using PXOR reg, reg breaks
dependency
dependency
Lea eax, a
lea ecx, b
lea edi, c
xor edx, edx
movdqa xmm7, allone
lp:
lea eax, a
lea ecx, b
lea edi, c
xor edx, edx
lp:
movdqa xmm0, [eax + edx]
paddd xmm0, [ecx + edx]
pxor xmm0, xmm7
psubd xmm0, xmm7
movdqa [edi + edx], xmm0
add edx, 16
cmp edx, 4096
jl lp
movdqa xmm0, [eax + edx]
paddd xmm0, [ecx + edx]
pxor xmm7, xmm7
psubd xmm7, xmm0
movdqa [edi + edx], xmm7
add edx,16
cmp edx, 4096
jl lp
Assembly/Compiler Coding Rule 36. (M impact, MH generality) Break dependences on portions
of registers between instructions by operating on 32-bit registers instead of partial registers. For
moves, this can be accomplished with 32-bit moves or by using MOVZX.
Sometimes sign-extended semantics can be maintained by zero-extending operands. For example, the C
code in the following statements does not need sign extension, nor does it need prefixes for operand size
overrides:
static short INT a, b;
IF (a == b) {
...
}
Code for comparing these 16-bit operands might be:
MOVZW EAX, [a]
MOVZW EBX, [b]
CMP
EAX, EBX
These circumstances tend to be common. However, the technique will not work if the compare is for
greater than, less than, greater than or equal, and so on, or if the values in eax or ebx are to be used in
another operation where sign extension is required.
Assembly/Compiler Coding Rule 37. (M impact, M generality) Try to use zero extension or
operate on 32-bit operands instead of using moves with sign extension.
The trace cache can be packed more tightly when instructions with operands that can only be represented as 32 bits are not adjacent.
Assembly/Compiler Coding Rule 38. (ML impact, L generality) Avoid placing instructions that
use 32-bit immediates which cannot be encoded as sign-extended 16-bit immediates near each other.
Try to schedule µops that have no immediate immediately before or after µops with 32-bit immediates.
3.5.1.8
Compares
Use TEST when comparing a value in a register with zero. TEST essentially ANDs operands together
without writing to a destination register. TEST is preferred over AND because AND produces an extra
result register. TEST is better than CMP ..., 0 because the instruction size is smaller.
3-27
GENERAL OPTIMIZATION GUIDELINES
Use TEST when comparing the result of a logical AND with an immediate constant for equality or
inequality if the register is EAX for cases such as:
IF (AVAR & 8) { }
The TEST instruction can also be used to detect rollover of modulo of a power of 2. For example, the C
code:
IF ( (AVAR % 16) == 0 ) { }
can be implemented using:
TEST
JNZ
EAX, 0x0F
AfterIf
Using the TEST instruction between the instruction that may modify part of the flag register and the
instruction that uses the flag register can also help prevent partial flag register stall.
Assembly/Compiler Coding Rule 39. (ML impact, M generality) Use the TEST instruction instead
of AND when the result of the logical AND is not used. This saves µops in execution. Use a TEST of a
register with itself instead of a CMP of the register to zero, this saves the need to encode the zero and
saves encoding space. Avoid comparing a constant to a memory operand. It is preferable to load the
memory operand and compare the constant to a register.
Often a produced value must be compared with zero, and then used in a branch. Because most Intel
architecture instructions set the condition codes as part of their execution, the compare instruction may
be eliminated. Thus the operation can be tested directly by a JCC instruction. The notable exceptions are
MOV and LEA. In these cases, use TEST.
Assembly/Compiler Coding Rule 40. (ML impact, M generality) Eliminate unnecessary compare
with zero instructions by using the appropriate conditional jump instruction when the flags are already
set by a preceding arithmetic instruction. If necessary, use a TEST instruction instead of a compare. Be
certain that any code transformations made do not introduce problems with overflow.
3.5.1.9
Using NOPs
Code generators generate a no-operation (NOP) to align instructions. Examples of NOPs of different
lengths in 32-bit mode are shown below:
1-byte: XCHG EAX, EAX
2-byte: 66 NOP
3-byte: LEA REG, 0 (REG) (8-bit displacement)
4-byte: NOP DWORD PTR [EAX + 0] (8-bit displacement)
5-byte: NOP DWORD PTR [EAX + EAX*1 + 0] (8-bit displacement)
6-byte: LEA REG, 0 (REG) (32-bit displacement)
7-byte: NOP DWORD PTR [EAX + 0] (32-bit displacement)
8-byte: NOP DWORD PTR [EAX + EAX*1 + 0] (32-bit displacement)
9-byte: NOP WORD PTR [EAX + EAX*1 + 0] (32-bit displacement)
These are all true NOPs, having no effect on the state of the machine except to advance the EIP. Because
NOPs require hardware resources to decode and execute, use the fewest number to achieve the desired
padding.
The one byte NOP:[XCHG EAX,EAX] has special hardware support. Although it still consumes a µop and
its accompanying resources, the dependence upon the old value of EAX is removed. This µop can be
executed at the earliest possible opportunity, reducing the number of outstanding instructions and is the
lowest cost NOP.
The other NOPs have no special hardware support. Their input and output registers are interpreted by the
hardware. Therefore, a code generator should arrange to use the register containing the oldest value as
input, so that the NOP will dispatch and release RS resources at the earliest possible opportunity.
3-28
GENERAL OPTIMIZATION GUIDELINES
Try to observe the following NOP generation priority:
•
•
•
Select the smallest number of NOPs and pseudo-NOPs to provide the desired padding.
Select NOPs that are least likely to execute on slower execution unit clusters.
Select the register arguments of NOPs to reduce dependencies.
3.5.1.10
Mixing SIMD Data Types
Previous microarchitectures (before Intel Core microarchitecture) do not have explicit restrictions on
mixing integer and floating-point (FP) operations on XMM registers. For Intel Core microarchitecture,
mixing integer and floating-point operations on the content of an XMM register can degrade performance. Software should avoid mixed-use of integer/FP operation on XMM registers. Specifically:
•
•
•
Use SIMD integer operations to feed SIMD integer operations. Use PXOR for idiom.
Use SIMD floating-point operations to feed SIMD floating-point operations. Use XORPS for idiom.
When floating-point operations are bitwise equivalent, use PS data type instead of PD data type.
MOVAPS and MOVAPD do the same thing, but MOVAPS takes one less byte to encode the instruction.
3.5.1.11
Spill Scheduling
The spill scheduling algorithm used by a code generator will be impacted by the memory subsystem. A
spill scheduling algorithm is an algorithm that selects what values to spill to memory when there are too
many live values to fit in registers. Consider the code in Example 3-22, where it is necessary to spill
either A, B, or C.
Example 3-22. Spill Scheduling Code
LOOP
C := ...
B := ...
A := A + ...
For modern microarchitectures, using dependence depth information in spill scheduling is even more
important than in previous processors. The loop-carried dependence in A makes it especially important
that A not be spilled. Not only would a store/load be placed in the dependence chain, but there would also
be a data-not-ready stall of the load, costing further cycles.
Assembly/Compiler Coding Rule 41. (H impact, MH generality) For small loops, placing loop
invariants in memory is better than spilling loop-carried dependencies.
A possibly counter-intuitive result is that in such a situation it is better to put loop invariants in memory
than in registers, since loop invariants never have a load blocked by store data that is not ready.
3.5.1.12
Zero-Latency MOV Instructions
In processors based on Intel microarchitecture code name Ivy Bridge, a subset of register-to-register
move operations are executed in the front end (similar to zero-idioms, see Section 3.5.1.7). This
conserves scheduling/execution resources in the out-of-order engine. Most forms of register-to-register
3-29
GENERAL OPTIMIZATION GUIDELINES
MOV instructions can benefit from zero-latency MOV. Example 3-23 list the details of those forms that
qualify and a small set that do not.
Example 3-23. Zero-Latency MOV Instructions
MOV instructions latency that can be eliminated
MOV reg32, reg32
MOV reg64, reg64
MOVUPD/MOVAPD xmm, xmm
MOVUPD/MOVAPD ymm, ymm
MOVUPS?MOVAPS xmm, xmm
MOVUPS/MOVAPS ymm, ymm
MOVDQA/MOVDQU xmm, xmm
MOVDQA/MOVDQU ymm, ymm
MOVZX reg32, reg8 (if not AH/BH/CH/DH)
MOVZX reg64, reg8 (if not AH/BH/CH/DH)
MOV instructions latency that cannot be eliminated
MOV reg8, reg8
MOV reg16, reg16
MOVZX reg32, reg8 (if AH/BH/CH/DH)
MOVZX reg64, reg8 (if AH/BH/CH/DH)
MOVSX
Example 3-24 shows how to process 8-bit integers using MOVZX to take advantage of zero-latency MOV
enhancement. Consider
X = (X * 3^N ) MOD 256;
Y = (Y * 3^N ) MOD 256;
When “MOD 256” is implemented using the “AND 0xff” technique, its latency is exposed in the resultdependency chain. Using a form of MOVZX on a truncated byte input, it can take advantage of zerolatency MOV enhancement and gain about 45% in speed.
Example 3-24. Byte-Granular Data Computation Technique
Use AND Reg32, 0xff
Use MOVZX
mov rsi, N
mov rax, X
mov rcx, Y
loop:
lea rcx, [rcx+rcx*2]
lea rax, [rax+rax*4]
and rcx, 0xff
and rax, 0xff
mov rsi, N
mov rax, X
mov rcx, Y
loop:
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
lea rcx, [rcx+rcx*2]
lea rax, [rax+rax*4]
and rcx, 0xff
and rax, 0xff
sub rsi, 2
jg loop
lea rdx, [rax+rax*4]
movzx, rax, dl
llea rdx, [rax+rax*4]
movzx, rax, dl
sub rsi, 2
jg loop
The effectiveness of coding a dense sequence of instructions to rely on a zero-latency MOV instruction
must also consider internal resource constraints in the microarchitecture.
3-30
GENERAL OPTIMIZATION GUIDELINES
Example 3-25. Re-ordering Sequence to Improve Effectiveness of Zero-Latency MOV Instructions
Needing more internal resource for zero-latency
MOVs
Needing less internal resource for zero-latency MOVs
mov rsi, N
mov rax, X
mov rcx, Y
mov rsi, N
mov rax, X
mov rcx, Y
loop:
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
lea rdx, [rax+rax*4]
movzx, rax, dl
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
llea rdx, [rax+rax*4]
movzx, rax, dl
sub rsi, 2
jg loop
loop:
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
lea rbx, [rcx+rcx*2]
movzx, rcx, bl
lea rdx, [rax+rax*4]
movzx, rax, dl
llea rdx, [rax+rax*4]
movzx, rax, dl
sub rsi, 2
jg loop
In Example 3-25, RBX/RCX and RDX/RAX are pairs of registers that are shared and continuously overwritten. In the right-hand sequence, registers are overwritten with new results immediately, consuming
less internal resources provided by the underlying microarchitecture. As a result, it is about 8% faster
than the left-hand sequence where internal resources could only support 50% of the attempt to take
advantage of zero-latency MOV instructions.
3.5.2
Avoiding Stalls in Execution Core
Although the design of the execution core is optimized to make common cases executes quickly. A microop may encounter various hazards, delays, or stalls while making forward progress from the front end to
the ROB and RS. The significant cases are:
•
•
•
•
ROB Read Port Stalls.
Partial Register Reference Stalls.
Partial Updates to XMM Register Stalls.
Partial Flag Register Reference Stalls.
3.5.2.1
ROB Read Port Stalls
As a micro-op is renamed, it determines whether its source operands have executed and been written to
the reorder buffer (ROB), or whether they will be captured “in flight” in the RS or in the bypass network.
Typically, the great majority of source operands are found to be “in flight” during renaming. Those that
have been written back to the ROB are read through a set of read ports.
Since the Intel Core microarchitecture is optimized for the common case where the operands are “in
flight”, it does not provide a full set of read ports to enable all renamed micro-ops to read all sources from
the ROB in the same cycle.
When not all sources can be read, a micro-op can stall in the rename stage until it can get access to
enough ROB read ports to complete renaming the micro-op. This stall is usually short-lived. Typically, a
micro-op will complete renaming in the next cycle, but it appears to the application as a loss of rename
bandwidth.
3-31
GENERAL OPTIMIZATION GUIDELINES
Some of the software-visible situations that can cause ROB read port stalls include:
•
Registers that have become cold and require a ROB read port because execution units are doing other
independent calculations.
•
•
Constants inside registers.
Pointer and index registers.
In rare cases, ROB read port stalls may lead to more significant performance degradations. There are a
couple of heuristics that can help prevent over-subscribing the ROB read ports:
•
Keep common register usage clustered together. Multiple references to the same written-back
register can be “folded” inside the out of order execution core.
•
Keep short dependency chains intact. This practice ensures that the registers will not have been
written back when the new micro-ops are written to the RS.
These two scheduling heuristics may conflict with other more common scheduling heuristics. To reduce
demand on the ROB read port, use these two heuristics only if both the following situations are met:
•
•
Short latency operations.
Indications of actual ROB read port stalls can be confirmed by measurements of the performance
event (the relevant event is RAT_STALLS.ROB_READ_PORT, see Chapter 19 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B).
If the code has a long dependency chain, these two heuristics should not be used because they can cause
the RS to fill, causing damage that outweighs the positive effects of reducing demands on the ROB read
port.
Starting with Intel microarchitecture code name Sandy Bridge, ROB port stall no longer applies because
data is read from the physical register file.
3.5.2.2
Writeback Bus Conflicts
The writeback bus inside the execution engine is a common resource needed to facilitate out-of-order
execution of micro-ops in flight. When the writeback bus is needed at the same time by two micro-ops
executing in the same stack of execution units (see Table 2-16), the younger micro-op will have to wait
for the writeback bus to be available. This situation typically will be more likely for short-latency instructions experience a delay when it might have been otherwise ready for dispatching into the execution
engine.
Consider a repeating sequence of independent floating-point ADDs with a single-cycle MOV bound to the
same dispatch port. When the MOV finds the dispatch port available, the writeback bus can be occupied
by the ADD. This delays the MOV operation.
If this problem is detected, you can sometimes change the instruction selection to use a different
dispatch port and reduce the writeback contention.
3.5.2.3
Bypass between Execution Domains
Floating-point (FP) loads have an extra cycle of latency. Moves between FP and SIMD stacks have
another additional cycle of latency.
Example:
ADDPS XMM0, XMM1
PAND XMM0, XMM3
ADDPS XMM2, XMM0
The overall latency for the above calculation is 9 cycles:
•
•
•
•
3 cycles for each ADDPS instruction.
1 cycle for the PAND instruction.
1 cycle to bypass between the ADDPS floating-point domain to the PAND integer domain.
1 cycle to move the data from the PAND integer to the second floating-point ADDPS domain.
3-32
GENERAL OPTIMIZATION GUIDELINES
To avoid this penalty, you should organize code to minimize domain changes. Sometimes you cannot
avoid bypasses.
Account for bypass cycles when counting the overall latency of your code. If your calculation is latencybound, you can execute more instructions in parallel or break dependency chains to reduce total latency.
Code that has many bypass domains and is completely latency-bound may run slower on the Intel Core
microarchitecture than it did on previous microarchitectures.
3.5.2.4
Partial Register Stalls
General purpose registers can be accessed in granularities of bytes, words, doublewords; 64-bit mode
also supports quadword granularity. Referencing a portion of a register is referred to as a partial register
reference.
A partial register stall happens when an instruction refers to a register, portions of which were previously
modified by other instructions. For example, partial register stalls occurs with a read to AX while previous
instructions stored AL and AH, or a read to EAX while previous instruction modified AX.
The delay of a partial register stall is small in processors based on Intel Core and NetBurst microarchitectures, and in Pentium M processor (with CPUID signature family 6, model 13), Intel Core Solo, and Intel
Core Duo processors. Pentium M processors (CPUID signature with family 6, model 9) and the P6 family
incur a large penalty.
Note that in Intel 64 architecture, an update to the lower 32 bits of a 64 bit integer register is architecturally defined to zero extend the upper 32 bits. While this action may be logically viewed as a 32 bit
update, it is really a 64 bit update (and therefore does not cause a partial stall).
Referencing partial registers frequently produces code sequences with either false or real dependencies.
Example 3-18 demonstrates a series of false and real dependencies caused by referencing partial registers.
If instructions 4 and 6 (in Example 3-18) are changed to use a movzx instruction instead of a mov, then
the dependences of instruction 4 on 2 (and transitively 1 before it), and instruction 6 on 5 are broken.
This creates two independent chains of computation instead of one serial one.
Example 3-26 illustrates the use of MOVZX to avoid a partial register stall when packing three byte
values into a register.
Example 3-26. Avoiding Partial Register Stalls in Integer Code
A Sequence Causing Partial Register Stall
Alternate Sequence Using MOVZX to Avoid Delay
mov al, byte ptr a[2]
shl eax,16
mov ax, word ptr a
movd mm0, eax
ret
movzx eax, byte ptr a[2]
shl eax, 16
movzx ecx, word ptr a
or eax,ecx
movd mm0, eax
ret
Starting with Intel microarchitecture code name Sandy Bridge and all subsequent generations of Intel
Core microarchitecture, partial register access is handled in hardware by inserting a micro-op that
merges the partial register with the full register in the following cases:
•
After a write to one of the registers AH, BH, CH or DH and before a following read of the 2-, 4- or 8byte form of the same register. In these cases a merge micro-op is inserted. The insertion consumes
a full allocation cycle in which other micro-ops cannot be allocated.
•
After a micro-op with a destination register of 1 or 2 bytes, which is not a source of the instruction (or
the register's bigger form), and before a following read of a 2-,4- or 8-byte form of the same register.
In these cases the merge micro-op is part of the flow. For example:
•
MOV AX, [BX]
When you want to load from memory to a partial register, consider using MOVZX or MOVSX to
avoid the additional merge micro-op penalty.
3-33
GENERAL OPTIMIZATION GUIDELINES
•
LEA
AX, [BX+CX]
For optimal performance, use of zero idioms, before the use of the register, eliminates the need for
partial register merge micro-ops.
3.5.2.5
Partial XMM Register Stalls
Partial register stalls can also apply to XMM registers. The following SSE and SSE2 instructions update
only part of the destination register:
MOVL/HPD XMM, MEM64
MOVL/HPS XMM, MEM32
MOVSS/SD between registers
Using these instructions creates a dependency chain between the unmodified part of the register and the
modified part of the register. This dependency chain can cause performance loss.
Example 3-27 illustrates the use of MOVZX to avoid a partial register stall when packing three byte
values into a register.
Follow these recommendations to avoid stalls from partial updates to XMM registers:
•
•
•
Avoid using instructions which update only part of the XMM register.
•
When copying the XMM register, use the following instructions for full register copy, even if you only
want to copy some of the source register data:
If a 64-bit load is needed, use the MOVSD or MOVQ instruction.
If 2 64-bit loads are required to the same register from non continuous locations, use
MOVSD/MOVHPD instead of MOVLPD/MOVHPD.
MOVAPS
MOVAPD
MOVDQA
Example 3-27. Avoiding Partial Register Stalls in SIMD Code
Using movlpd for memory transactions and movsd
Using movsd for memory and movapd between
between register copies Causing Partial Register Stall
register copies Avoid Delay
mov edx, x
mov ecx, count
movsd xmm3,_1_
movsd xmm2, _1pt5_
align 16
mov edx, x
mov ecx, count
movlpd xmm3,_1_
movlpd xmm2,_1pt5_
align 16
lp:
lp:
movlpd xmm0, [edx]
addsd xmm0, xmm3
movsd xmm1, xmm2
subsd xmm1, [edx]
mulsd xmm0, xmm1
movsd [edx], xmm0
add edx, 8
dec ecx
jnz lp
3.5.2.6
movsd xmm0, [edx]
addsd xmm0, xmm3
movapd xmm1, xmm2
subsd xmm1, [edx]
mulsd xmm0, xmm1
movsd [edx], xmm0
add edx, 8
dec ecx
jnz lp
Partial Flag Register Stalls
A “partial flag register stall” occurs when an instruction modifies a part of the flag register and the
following instruction is dependent on the outcome of the flags. This happens most often with shift
3-34
GENERAL OPTIMIZATION GUIDELINES
instructions (SAR, SAL, SHR, SHL). The flags are not modified in the case of a zero shift count, but the
shift count is usually known only at execution time. The front end stalls until the instruction is retired.
Other instructions that can modify some part of the flag register include CMPXCHG8B, various rotate
instructions, STC, and STD. An example of assembly with a partial flag register stall and alternative code
without the stall is shown in Example 3-28.
In processors based on Intel Core microarchitecture, shift immediate by 1 is handled by special hardware
such that it does not experience partial flag stall.
Example 3-28. Avoiding Partial Flag Register Stalls
Partial Flag Register Stall
xor eax, eax
mov ecx, a
sar ecx, 2
setz al ;SAR can update carry causing a stall
Avoiding Partial Flag Register Stall
or eax, eax
mov ecx, a
sar ecx, 2
test ecx, ecx ; test always updates all flags
setz al ;No partial reg or flag stall,
In Intel microarchitecture code name Sandy Bridge, the cost of partial flag access is replaced by the
insertion of a micro-op instead of a stall. However, it is still recommended to use less of instructions that
write only to some of the flags (such as INC, DEC, SET CL) before instructions that can write flags conditionally (such as SHIFT CL).
Example 3-29 compares two techniques to implement the addition of very large integers (e.g. 1024
bits). The alternative sequence on the right side of Example 3-29 will be faster than the left side on Intel
microarchitecture code name Sandy Bridge, but it will experience partial flag stalls on prior microarchitectures.
Example 3-29. Partial Flag Register Accesses in Intel Microarchitecture Code Name Sandy Bridge
Save partial flag register to avoid stall
Simplified code sequence
lea rsi, [A]
lea rdi, [B]
xor rax, rax
mov rcx, 16 ; 16*64 =1024 bit
lp_64bit:
add rax, [rsi]
adc rax, [rdi]
mov [rdi], rax
setc al ;save carry for next iteration
movzx rax, al
add rsi, 8
add rdi, 8
dec rcx
jnz lp_64bit
3.5.2.7
lea rsi, [A]
lea rdi, [B]
xor rax, rax
mov rcx, 16
lp_64bit:
add rax, [rsi]
adc rax, [rdi]
mov [rdi], rax
lea rsi, [rsi+8]
lea rdi, [rdi+8]
dec rcx
jnz lp_64bit
Floating-Point/SIMD Operands
Moves that write a portion of a register can introduce unwanted dependences. The MOVSD REG, REG
instruction writes only the bottom 64 bits of a register, not all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those bits are not longer wanted). The
dependence inhibits register renaming, and thereby reduces parallelism.
Use MOVAPD as an alternative; it writes all 128 bits. Even though this instruction has a longer latency,
the μops for MOVAPD use a different execution port and this port is more likely to be free. The change can
3-35
GENERAL OPTIMIZATION GUIDELINES
impact performance. There may be exceptional cases where the latency matters more than the dependence or the execution port.
Assembly/Compiler Coding Rule 42. (M impact, ML generality) Avoid introducing dependences
with partial floating-point register writes, e.g. from the MOVSD XMMREG1, XMMREG2 instruction. Use
the MOVAPD XMMREG1, XMMREG2 instruction instead.
The MOVSD XMMREG, MEM instruction writes all 128 bits and breaks a dependence.
The MOVUPD from memory instruction performs two 64-bit loads, but requires additional µops to adjust
the address and combine the loads into a single register. This same functionality can be obtained using
MOVSD XMMREG1, MEM; MOVSD XMMREG2, MEM+8; UNPCKLPD XMMREG1, XMMREG2, which uses
fewer µops and can be packed into the trace cache more effectively. The latter alternative has been found
to provide a several percent performance improvement in some cases. Its encoding requires more
instruction bytes, but this is seldom an issue for the Pentium 4 processor. The store version of MOVUPD
is complex and slow, so much so that the sequence with two MOVSD and a UNPCKHPD should always be
used.
Assembly/Compiler Coding Rule 43. (ML impact, L generality) Instead of using MOVUPD
XMMREG1, MEM for a unaligned 128-bit load, use MOVSD XMMREG1, MEM; MOVSD XMMREG2,
MEM+8; UNPCKLPD XMMREG1, XMMREG2. If the additional register is not available, then use MOVSD
XMMREG1, MEM; MOVHPD XMMREG1, MEM+8.
Assembly/Compiler Coding Rule 44. (M impact, ML generality) Instead of using MOVUPD MEM,
XMMREG1 for a store, use MOVSD MEM, XMMREG1; UNPCKHPD XMMREG1, XMMREG1; MOVSD
MEM+8, XMMREG1 instead.
3.5.3
Vectorization
This section provides a brief summary of optimization issues related to vectorization. There is more detail
in the chapters that follow.
Vectorization is a program transformation that allows special hardware to perform the same operation on
multiple data elements at the same time. Successive processor generations have provided vector
support through the MMX technology, Streaming SIMD Extensions (SSE), Streaming SIMD Extensions 2
(SSE2), Streaming SIMD Extensions 3 (SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3).
Vectorization is a special case of SIMD, a term defined in Flynn’s architecture taxonomy to denote a
single instruction stream capable of operating on multiple data elements in parallel. The number of
elements which can be operated on in parallel range from four single-precision floating-point data
elements in Streaming SIMD Extensions and two double-precision floating-point data elements in
Streaming SIMD Extensions 2 to sixteen byte operations in a 128-bit register in Streaming SIMD Extensions 2. Thus, vector length ranges from 2 to 16, depending on the instruction extensions used and on
the data type.
The Intel C++ Compiler supports vectorization in three ways:
•
•
•
The compiler may be able to generate SIMD code without intervention from the user.
The can user insert pragmas to help the compiler realize that it can vectorize the code.
The user can write SIMD code explicitly using intrinsics and C++ classes.
To help enable the compiler to generate SIMD code, avoid global pointers and global variables. These
issues may be less troublesome if all modules are compiled simultaneously, and whole-program optimization is used.
User/Source Coding Rule 2. (H impact, M generality) Use the smallest possible floating-point or
SIMD data type, to enable more parallelism with the use of a (longer) SIMD vector. For example, use
single precision instead of double precision where possible.
User/Source Coding Rule 3. (M impact, ML generality) Arrange the nesting of loops so that the
innermost nesting level is free of inter-iteration dependencies. Especially avoid the case where the
store of data in an earlier iteration happens lexically after the load of that data in a future iteration,
something which is called a lexically backward dependence.
3-36
GENERAL OPTIMIZATION GUIDELINES
The integer part of the SIMD instruction set extensions cover 8-bit,16-bit and 32-bit operands. Not all
SIMD operations are supported for 32 bits, meaning that some source code will not be able to be vectorized at all unless smaller operands are used.
User/Source Coding Rule 4. (M impact, ML generality) Avoid the use of conditional branches
inside loops and consider using SSE instructions to eliminate branches.
User/Source Coding Rule 5. (M impact, ML generality) Keep induction (loop) variable expressions
simple.
3.5.4
Optimization of Partially Vectorizable Code
Frequently, a program contains a mixture of vectorizable code and some routines that are non-vectorizable. A common situation of partially vectorizable code involves a loop structure which include mixtures
of vectorized code and unvectorizable code. This situation is depicted in Figure 3-1.
Packed SIMD Instruction
Unpacking
Unvectorizable Code
Serial Routine
Packing
Packed SIMD Instruction
Figure 3-1. Generic Program Flow of Partially Vectorized Code
It generally consists of five stages within the loop:
•
•
•
•
•
Prolog.
Unpacking vectorized data structure into individual elements.
Calling a non-vectorizable routine to process each element serially.
Packing individual result into vectorized data structure.
Epilog.
This section discusses techniques that can reduce the cost and bottleneck associated with the
packing/unpacking stages in these partially vectorize code.
Example 3-30 shows a reference code template that is representative of partially vectorizable coding
situations that also experience performance issues. The unvectorizable portion of code is represented
generically by a sequence of calling a serial function named “foo” multiple times. This generic example is
referred to as “shuffle with store forwarding”, because the problem generally involves an unpacking
stage that shuffles data elements between register and memory, followed by a packing stage that can
experience store forwarding issue.
3-37
GENERAL OPTIMIZATION GUIDELINES
There are more than one useful techniques that can reduce the store-forwarding bottleneck between the
serialized portion and the packing stage. The following sub-sections presents alternate techniques to
deal with the packing, unpacking, and parameter passing to serialized function calls.
Example 3-30. Reference Code Template for Partially Vectorizable Program
// Prolog ///////////////////////////////
push ebp
mov ebp, esp
// Unpacking ////////////////////////////
sub ebp, 32
and ebp, 0xfffffff0
movaps [ebp], xmm0
// Serial operations on components ///////
sub ebp, 4
mov eax, [ebp+4]
mov [ebp], eax
call foo
mov [ebp+16+4], eax
mov eax, [ebp+8]
mov [ebp], eax
call foo
mov [ebp+16+4+4], eax
mov eax, [ebp+12]
mov [ebp], eax
call foo
mov [ebp+16+8+4], eax
mov eax, [ebp+12+4]
mov [ebp], eax
call foo
mov [ebp+16+12+4], eax
// Packing ///////////////////////////////
movaps xmm0, [ebp+16+4]
// Epilog ////////////////////////////////
pop ebp
ret
3.5.4.1
Alternate Packing Techniques
The packing method implemented in the reference code of Example 3-30 will experience delay as it
assembles 4 doubleword result from memory into an XMM register due to store-forwarding restrictions.
3-38
GENERAL OPTIMIZATION GUIDELINES
Three alternate techniques for packing, using different SIMD instruction to assemble contents in XMM
registers are shown in Example 3-31. All three techniques avoid store-forwarding delay by satisfying the
restrictions on data sizes between a preceding store and subsequent load operations.
Example 3-31. Three Alternate Packing Methods for Avoiding Store Forwarding Difficulty
Packing Method 1
Packing Method 2
Packing Method 3
movd xmm0, [ebp+16+4]
movd xmm1, [ebp+16+8]
movd xmm2, [ebp+16+12]
movd xmm3, [ebp+12+16+4]
punpckldq xmm0, xmm1
punpckldq xmm2, xmm3
punpckldq xmm0, xmm2
3.5.4.2
movd xmm0, [ebp+16+4]
movd xmm1, [ebp+16+8]
movd xmm2, [ebp+16+12]
movd xmm3, [ebp+12+16+4]
psllq xmm3, 32
orps xmm2, xmm3
psllq xmm1, 32
orps xmm0, xmm1movlhps xmm0, xmm2
movd xmm0, [ebp+16+4]
movd xmm1, [ebp+16+8]
movd xmm2, [ebp+16+12]
movd xmm3, [ebp+12+16+4]
movlhps xmm1,xmm3
psllq xmm1, 32
movlhps xmm0, xmm2
orps xmm0, xmm1
Simplifying Result Passing
In Example 3-30, individual results were passed to the packing stage by storing to contiguous memory
locations. Instead of using memory spills to pass four results, result passing may be accomplished by
using either one or more registers. Using registers to simplify result passing and reduce memory spills
can improve performance by varying degrees depending on the register pressure at runtime.
Example 3-32 shows the coding sequence that uses four extra XMM registers to reduce all memory spills
of passing results back to the parent routine. However, software must observe the following conditions
when using this technique:
•
•
There is no register shortage.
If the loop does not have many stores or loads but has many computations, this technique does not
help performance. This technique adds work to the computational units, while the store and loads
ports are idle.
Example 3-32. Using Four Registers to Reduce Memory Spills and Simplify Result Passing
mov eax, [ebp+4]
mov [ebp], eax
call foo
movd xmm0, eax
mov eax, [ebp+8]
mov [ebp], eax
call foo
movd xmm1, eax
mov eax, [ebp+12]
mov [ebp], eax
call foo
movd xmm2, eax
mov eax, [ebp+12+4]
mov [ebp], eax
call foo
movd xmm3, eax
3-39
GENERAL OPTIMIZATION GUIDELINES
3.5.4.3
Stack Optimization
In Example 3-30, an input parameter was copied in turn onto the stack and passed to the non-vectorizable routine for processing. The parameter passing from consecutive memory locations can be simplified
by a technique shown in Example 3-33.
Example 3-33. Stack Optimization Technique to Simplify Parameter Passing
call foo
mov [ebp+16], eax
add ebp, 4
call foo
mov [ebp+16], eax
add ebp, 4
call foo
mov [ebp+16], eax
add ebp, 4
call foo
Stack Optimization can only be used when:
•
The serial operations are function calls. The function “foo” is declared as: INT FOO(INT A). The
parameter is passed on the stack.
•
The order of operation on the components is from last to first.
Note the call to FOO and the advance of EDP when passing the vector elements to FOO one by one from
last to first.
3.5.4.4
Tuning Considerations
Tuning considerations for situations represented by looping of Example 3-30 include:
•
Applying one of more of the following combinations:
— Choose an alternate packing technique.
— Consider a technique to simply result-passing.
— Consider the stack optimization technique to simplify parameter passing.
•
•
Minimizing the average number of cycles to execute one iteration of the loop.
Minimizing the per-iteration cost of the unpacking and packing operations.
The speed improvement by using the techniques discussed in this section will vary, depending on the
choice of combinations implemented and characteristics of the non-vectorizable routine. For example, if
the routine “foo” is short (representative of tight, short loops), the per-iteration cost of
unpacking/packing tend to be smaller than situations where the non-vectorizable code contain longer
operation or many dependencies. This is because many iterations of short, tight loop can be in flight in
the execution core, so the per-iteration cost of packing and unpacking is only partially exposed and
appear to cause very little performance degradation.
Evaluation of the per-iteration cost of packing/unpacking should be carried out in a methodical manner
over a selected number of test cases, where each case may implement some combination of the techniques discussed in this section. The per-iteration cost can be estimated by:
•
•
Evaluating the average cycles to execute one iteration of the test case.
Evaluating the average cycles to execute one iteration of a base line loop sequence of non-vectorizable code.
3-40
GENERAL OPTIMIZATION GUIDELINES
Example 3-34 shows the base line code sequence that can be used to estimate the average cost of a loop
that executes non-vectorizable routines.
Example 3-34. Base Line Code Sequence to Estimate Loop Overhead
push ebp
mov ebp, esp
sub ebp, 4
mov [ebp], edi
call foo
mov [ebp], edi
call foo
mov [ebp], edi
call foo
mov [ebp], edi
call foo
add ebp, 4
pop ebp
ret
The average per-iteration cost of packing/unpacking can be derived from measuring the execution times
of a large number of iterations by:
((Cycles to run TestCase) - (Cycles to run equivalent baseline sequence) ) / (Iteration count).
For example, using a simple function that returns an input parameter (representative of tight, short
loops), the per-iteration cost of packing/unpacking may range from slightly more than 7 cycles (the
shuffle with store forwarding case, Example 3-30) to ~0.9 cycles (accomplished by several test cases).
Across 27 test cases (consisting of one of the alternate packing methods, no result-simplification/simplification of either 1 or 4 results, no stack optimization or with stack optimization), the average per-iteration cost of packing/unpacking is about 1.7 cycles.
Generally speaking, packing method 2 and 3 (see Example 3-31) tend to be more robust than packing
method 1; the optimal choice of simplifying 1 or 4 results will be affected by register pressure of the
runtime and other relevant microarchitectural conditions.
Note that the numeric discussion of per-iteration cost of packing/packing is illustrative only. It will vary
with test cases using a different base line code sequence and will generally increase if the non-vectorizable routine requires longer time to execute because the number of loop iterations that can reside in
flight in the execution core decreases.
3-41
GENERAL OPTIMIZATION GUIDELINES
3.6
OPTIMIZING MEMORY ACCESSES
This section discusses guidelines for optimizing code and data memory accesses. The most important
recommendations are:
•
•
•
•
•
•
•
•
•
Execute load and store operations within available execution bandwidth.
Enable forward progress of speculative execution.
Enable store forwarding to proceed.
Align data, paying attention to data layout and stack alignment.
Place code and data on separate pages.
Enhance data locality.
Use prefetching and cacheability control instructions.
Enhance code locality and align branch targets.
Take advantage of write combining.
Alignment and forwarding problems are among the most common sources of large delays on processors
based on Intel NetBurst microarchitecture.
3.6.1
Load and Store Execution Bandwidth
Typically, loads and stores are the most frequent operations in a workload, up to 40% of the instructions
in a workload carrying load or store intent are not uncommon. Each generation of microarchitecture
provides multiple buffers to support executing load and store operations while there are instructions in
flight.
Software can maximize memory performance by not exceeding the issue or buffering limitations of the
machine. In the Intel Core microarchitecture, only 20 stores and 32 loads may be in flight at once. In
Intel microarchitecture code name Nehalem, there are 32 store buffers and 48 load buffers. Since only
one load can issue per cycle, algorithms which operate on two arrays are constrained to one operation
every other cycle unless you use programming tricks to reduce the amount of memory usage.
Intel Core Duo and Intel Core Solo processors have less buffers. Nevertheless the general heuristic
applies to all of them.
3.6.1.1
Make Use of Load Bandwidth in Intel® Microarchitecture Code Name Sandy Bridge
While prior microarchitecture has one load port (port 2), Intel microarchitecture code name Sandy Bridge
can load from port 2 and port 3. Thus two load operations can be performed every cycle and doubling the
load throughput of the code. This improves code that reads a lot of data and does not need to write out
results to memory very often (Port 3 also handles store-address operation). To exploit this bandwidth,
the data has to stay in the L1 data cache or it should be accessed sequentially, enabling the hardware
prefetchers to bring the data to the L1 data cache in time.
Consider the following C code example of adding all the elements of an array:
int buff[BUFF_SIZE];
int sum = 0;
for (i=0;i<BUFF_SIZE;i++){
sum+=buff[i];
}
Alternative 1 is the assembly code generated by the Intel compiler for this C code, using the optimization
flag for Intel microarchitecture code name Nehalem. The compiler vectorizes execution using Intel SSE
instructions. In this code, each ADD operation uses the result of the previous ADD operation. This limits
the throughput to one load and ADD operation per cycle. Alternative 2 is optimized for Intel microarchi-
3-42
GENERAL OPTIMIZATION GUIDELINES
tecture code name Sandy Bridge by enabling it to use the additional load bandwidth. The code removes
the dependency among ADD operations, by using two registers to sum the array values. Two load and
two ADD operations can be executed every cycle.
Example 3-35. Optimize for Load Port Bandwidth in Intel Microarchitecture Code Name Sandy Bridge
Register dependency inhibits PADD execution
Reduce register dependency allow two load port to supply
PADD execution
xor
pxor
lea
eax, eax
xmm0, xmm0
rsi, buff
loop_start:
paddd xmm0, [rsi+4*rax]
paddd xmm0, [rsi+4*rax+16]
paddd xmm0, [rsi+4*rax+32]
paddd xmm0, [rsi+4*rax+48]
paddd xmm0, [rsi+4*rax+64]
paddd xmm0, [rsi+4*rax+80]
paddd xmm0, [rsi+4*rax+96]
paddd xmm0, [rsi+4*rax+112]
add
eax, 32
cmp
eax, BUFF_SIZE
jl loop_start
sum_partials:
movdqa xmm1, xmm0
psrldq xmm1, 8
paddd xmm0, xmm1
movdqa xmm2, xmm0
psrldq xmm2, 4
paddd xmm0, xmm2
movd
[sum], xmm0
3.6.1.2
xor
pxor
pxor
lea
eax, eax
xmm0, xmm0
xmm1, xmm1
rsi, buff
loop_start:
paddd xmm0, [rsi+4*rax]
paddd xmm1, [rsi+4*rax+16]
paddd xmm0, [rsi+4*rax+32]
paddd xmm1, [rsi+4*rax+48]
paddd xmm0, [rsi+4*rax+64]
paddd xmm1, [rsi+4*rax+80]
paddd xmm0, [rsi+4*rax+96]
paddd xmm1, [rsi+4*rax+112]
add
eax, 32
cmp
eax, BUFF_SIZE
jl loop_start
sum_partials:
paddd xmm0, xmm1
movdqa xmm1, xmm0
psrldq xmm1, 8
paddd xmm0, xmm1
movdqa xmm2, xmm0
psrldq xmm2, 4
paddd xmm0, xmm2
movd
[sum], xmm0
L1D Cache Latency in Intel® Microarchitecture Code Name Sandy Bridge
Load latency from L1D cache may vary (see Table 2-20). The best case if 4 cycles, which apply to load
operations to general purpose registers using one of the following:
•
•
One register.
A base register plus an offset that is smaller than 2048.
Consider the pointer-chasing code example in Example 3-36.
3-43
GENERAL OPTIMIZATION GUIDELINES
Example 3-36. Index versus Pointers in Pointer-Chasing Code
Traversing through indexes
Traversing through pointers
// C code example
index = buffer.m_buff[index].next_index;
// ASM example
loop:
shl rbx, 6
mov rbx, 0x20(rbx+rcx)
dec rax
cmp rax, -1
jne loop
// C code example
node = node->pNext;
// ASM example
loop:
mov rdx, [rdx]
dec rax
cmp rax, -1
jne loop
The left side implements pointer chasing via traversing an index. Compiler then generates the code
shown below addressing memory using base+index with an offset. The right side shows compiler generated code from pointer de-referencing code and uses only a base register.
The code on the right side is faster than the left side across Intel microarchitecture code name Sandy
Bridge and prior microarchitecture. However the code that traverses index will be slower on Intel microarchitecture code name Sandy Bridge relative to prior microarchitecture.
3.6.1.3
Handling L1D Cache Bank Conflict
In Intel microarchitecture code name Sandy Bridge, the internal organization of the L1D cache may
manifest a situation when two load micro-ops whose addresses have a bank conflict. When a bank
conflict is present between two load operations, the more recent one will be delayed until the conflict is
resolved. A bank conflict happens when two simultaneous load operations have the same bit 2-5 of their
linear address but they are not from the same set in the cache (bits 6 - 12).
Bank conflicts should be handled only if the code is bound by load bandwidth. Some bank conflicts do not
cause any performance degradation since they are hidden by other performance limiters. Eliminating
such bank conflicts does not improve performance.
The following example demonstrates bank conflict and how to modify the code and avoid them. It uses
two source arrays with a size that is a multiple of cache line size. When loading an element from A and
the counterpart element from B the elements have the same offset in their cache lines and therefore a
bank conflict may happen.
With the Haswell microarchitecture, the L1 DCache bank conflict issue does not apply.
3-44
GENERAL OPTIMIZATION GUIDELINES
.
Example 3-37. Example of Bank Conflicts in L1D Cache and Remedy
int A[128];
int B[128];
int C[128];
for (i=0;i<128;i+=4){
C[i]=A[i]+B[i];
the loads from A[i] and B[i] collide
C[i+1]=A[i+1]+B[i+1];
C[i+2]=A[i+2]+B[i+2];
C[i+3]=A[i+3]+B[i+3];
}
// Code with Bank Conflicts
xor rcx, rcx
lea r11, A
lea r12, B
lea r13, C
loop:
lea esi, [rcx*4]
movsxd rsi, esi
mov edi, [r11+rsi*4]
add edi, [r12+rsi*4]
mov r8d, [r11+rsi*4+4]
add r8d, [r12+rsi*4+4]
mov r9d, [r11+rsi*4+8]
add r9d, [r12+rsi*4+8]
mov r10d, [r11+rsi*4+12]
add r10d, [r12+rsi*4+12]
// Code without Bank Conflicts
xor rcx, rcx
lea r11, A
lea r12, B
lea r13, C
loop:
lea esi, [rcx*4]
movsxd rsi, esi
mov edi, [r11+rsi*4]
mov r8d, [r11+rsi*4+4]
add edi, [r12+rsi*4]
add r8d, [r12+rsi*4+4]
mov r9d, [r11+rsi*4+8]
mov r10d, [r11+rsi*4+12]
add r9d, [r12+rsi*4+8]
add r10d, [r12+rsi*4+12]
mov [r13+rsi*4], edi
inc ecx
mov [r13+rsi*4+4], r8d
mov [r13+rsi*4+8], r9d
mov [r13+rsi*4+12], r10d
cmp ecx, LEN
jb loop
inc ecx
mov [r13+rsi*4], edi
mov [r13+rsi*4+4], r8d
mov [r13+rsi*4+8], r9d
mov [r13+rsi*4+12], r10d
cmp ecx, LEN
jb loop
3.6.2
Minimize Register Spills
When a piece of code has more live variables than the processor can keep in general purpose registers,
a common method is to hold some of the variables in memory. This method is called register spill. The
effect of L1D cache latency can negatively affect the performance of this code. The effect can be more
pronounced if the address of register spills uses the slower addressing modes.
One option is to spill general purpose registers to XMM registers. This method is likely to improve performance also on previous processor generations. The following example shows how to spill a register to an
XMM register rather than to memory.
3-45
GENERAL OPTIMIZATION GUIDELINES
Example 3-38. Using XMM Register in Lieu of Memory for Register Spills
Register spills into memory
Register spills into XMM
loop:
mov rdx, [rsp+0x18]
movdqa xmm0, [rdx]
movdqa xmm1, [rsp+0x20]
pcmpeqd xmm1, xmm0
pmovmskb eax, xmm1
test eax, eax
jne end_loop
movzx rcx, [rbx+0x60]
add qword ptr[rsp+0x18], 0x10
add rdi, 0x4
movzx rdx, di
sub rcx, 0x4
add rsi, 0x1d0
cmp rdx, rcx
jle loop
3.6.3
movq xmm4, [rsp+0x18]
mov rcx, 0x10
movq xmm5, rcx
loop:
movq rdx, xmm4
movdqa xmm0, [rdx]
movdqa xmm1, [rsp+0x20]
pcmpeqd xmm1, xmm0
pmovmskb eax, xmm1
test eax, eax
jne end_loop
movzx rcx, [rbx+0x60]
padd xmm4, xmm5
add rdi, 0x4
movzx rdx, di
sub rcx, 0x4
add rsi, 0x1d0
cmp rdx, rcx
jle loop
Enhance Speculative Execution and Memory Disambiguation
Prior to Intel Core microarchitecture, when code contains both stores and loads, the loads cannot be
issued before the address of the store is resolved. This rule ensures correct handling of load dependencies on preceding stores.
The Intel Core microarchitecture contains a mechanism that allows some loads to be issued early speculatively. The processor later checks if the load address overlaps with a store. If the addresses do overlap,
then the processor re-executes the instructions.
Example 3-39 illustrates a situation that the compiler cannot be sure that “Ptr->Array” does not change
during the loop. Therefore, the compiler cannot keep “Ptr->Array” in a register as an invariant and must
read it again in every iteration. Although this situation can be fixed in software by a rewriting the code to
require the address of the pointer is invariant, memory disambiguation provides performance gain
without rewriting the code.
3-46
GENERAL OPTIMIZATION GUIDELINES
Example 3-39. Loads Blocked by Stores of Unknown Address
C code
Assembly sequence
struct AA {
AA ** array;
};
void nullify_array ( AA *Ptr, DWORD Index, AA *ThisPtr
)
{
while ( Ptr->Array[--Index] != ThisPtr )
{
Ptr->Array[Index] = NULL ;
};
};
3.6.4
nullify_loop:
mov dword ptr [eax], 0
mov edx, dword ptr [edi]
sub ecx, 4
cmp dword ptr [ecx+edx], esi
lea eax, [ecx+edx]
jne nullify_loop
Alignment
Alignment of data concerns all kinds of variables:
•
•
•
•
Dynamically allocated variables.
Members of a data structure.
Global or local variables.
Parameters passed on the stack.
Misaligned data access can incur significant performance penalties. This is particularly true for cache line
splits. The size of a cache line is 64 bytes in the Pentium 4 and other recent Intel processors, including
processors based on Intel Core microarchitecture.
An access to data unaligned on 64-byte boundary leads to two memory accesses and requires several
µops to be executed (instead of one). Accesses that span 64-byte boundaries are likely to incur a large
performance penalty, the cost of each stall generally are greater on machines with longer pipelines.
Double-precision floating-point operands that are eight-byte aligned have better performance than operands that are not eight-byte aligned, since they are less likely to incur penalties for cache and MOB splits.
Floating-point operation on a memory operands require that the operand be loaded from memory. This
incurs an additional µop, which can have a minor negative impact on front end bandwidth. Additionally,
memory operands may cause a data cache miss, causing a penalty.
Assembly/Compiler Coding Rule 45. (H impact, H generality) Align data on natural operand size
address boundaries. If the data will be accessed with vector instruction loads and stores, align the data
on 16-byte boundaries.
For best performance, align data as follows:
•
•
•
•
•
•
Align 8-bit data at any address.
Align 16-bit data to be contained within an aligned 4-byte word.
Align 32-bit data so that its base address is a multiple of four.
Align 64-bit data so that its base address is a multiple of eight.
Align 80-bit data so that its base address is a multiple of sixteen.
Align 128-bit data so that its base address is a multiple of sixteen.
A 64-byte or greater data structure or array should be aligned so that its base address is a multiple of 64.
Sorting data in decreasing size order is one heuristic for assisting with natural alignment. As long as 16byte boundaries (and cache lines) are never crossed, natural alignment is not strictly necessary (though
it is an easy way to enforce this).
3-47
GENERAL OPTIMIZATION GUIDELINES
Example 3-40 shows the type of code that can cause a cache line split. The code loads the addresses of
two DWORD arrays. 029E70FEH is not a 4-byte-aligned address, so a 4-byte access at this address will
get 2 bytes from the cache line this address is contained in, and 2 bytes from the cache line that starts at
029E700H. On processors with 64-byte cache lines, a similar cache line split will occur every 8 iterations.
Example 3-40. Code That Causes Cache Line Split
mov
mov
Blockmove:
mov
mov
mov
mov
add
add
sub
jnz
esi, 029e70feh
edi, 05be5260h
eax, DWORD PTR [esi]
ebx, DWORD PTR [esi+4]
DWORD PTR [edi], eax
DWORD PTR [edi+4], ebx
esi, 8
edi, 8
edx, 1
Blockmove
Figure 3-2 illustrates the situation of accessing a data element that span across cache line boundaries.
Address 029e70c1h
Address 029e70feh
Cache Line 029e70c0h
Index 0
Cache Line 029e7100h
Index 0 cont'd
Index 1
Index 15
Index 16
Cache Line 029e7140h
Index 16 cont'd
Index 17
Index 31
Index 32
Figure 3-2. Cache Line Split in Accessing Elements in a Array
Alignment of code is less important for processors based on Intel NetBurst microarchitecture. Alignment
of branch targets to maximize bandwidth of fetching cached instructions is an issue only when not
executing out of the trace cache.
Alignment of code can be an issue for the Pentium M, Intel Core Duo and Intel Core 2 Duo processors.
Alignment of branch targets will improve decoder throughput.
3.6.5
Store Forwarding
The processor’s memory system only sends stores to memory (including cache) after store retirement.
However, store data can be forwarded from a store to a subsequent load from the same address to give
a much shorter store-load latency.
There are two kinds of requirements for store forwarding. If these requirements are violated, store
forwarding cannot occur and the load must get its data from the cache (so the store must write its data
back to the cache first). This incurs a penalty that is largely related to pipeline depth of the underlying
micro-architecture.
3-48
GENERAL OPTIMIZATION GUIDELINES
The first requirement pertains to the size and alignment of the store-forwarding data. This restriction is
likely to have high impact on overall application performance. Typically, a performance penalty due to
violating this restriction can be prevented. The store-to-load forwarding restrictions vary from one microarchitecture to another. Several examples of coding pitfalls that cause store-forwarding stalls and solutions to these pitfalls are discussed in detail in Section 3.6.5.1, “Store-to-Load-Forwarding Restriction on
Size and Alignment.” The second requirement is the availability of data, discussed in Section 3.6.5.2,
“Store-forwarding Restriction on Data Availability.” A good practice is to eliminate redundant load operations.
It may be possible to keep a temporary scalar variable in a register and never write it to memory. Generally, such a variable must not be accessible using indirect pointers. Moving a variable to a register eliminates all loads and stores of that variable and eliminates potential problems associated with store
forwarding. However, it also increases register pressure.
Load instructions tend to start chains of computation. Since the out-of-order engine is based on data
dependence, load instructions play a significant role in the engine’s ability to execute at a high rate. Eliminating loads should be given a high priority.
If a variable does not change between the time when it is stored and the time when it is used again, the
register that was stored can be copied or used directly. If register pressure is too high, or an unseen function is called before the store and the second load, it may not be possible to eliminate the second load.
Assembly/Compiler Coding Rule 46. (H impact, M generality) Pass parameters in registers
instead of on the stack where possible. Passing arguments on the stack requires a store followed by a
reload. While this sequence is optimized in hardware by providing the value to the load directly from
the memory order buffer without the need to access the data cache if permitted by store-forwarding
restrictions, floating-point values incur a significant latency in forwarding. Passing floating-point
arguments in (preferably XMM) registers should save this long latency operation.
Parameter passing conventions may limit the choice of which parameters are passed in registers which
are passed on the stack. However, these limitations may be overcome if the compiler has control of the
compilation of the whole binary (using whole-program optimization).
3.6.5.1
Store-to-Load-Forwarding Restriction on Size and Alignment
Data size and alignment restrictions for store-forwarding apply to processors based on Intel NetBurst
microarchitecture, Intel Core microarchitecture, Intel Core 2 Duo, Intel Core Solo and Pentium M processors. The performance penalty for violating store-forwarding restrictions is less for shorter-pipelined
machines than for Intel NetBurst microarchitecture.
Store-forwarding restrictions vary with each microarchitecture. Intel NetBurst microarchitecture places
more constraints than Intel Core microarchitecture on code generation to enable store-forwarding to
make progress instead of experiencing stalls. Fixing store-forwarding problems for Intel NetBurst microarchitecture generally also avoids problems on Pentium M, Intel Core Duo and Intel Core 2 Duo processors. The size and alignment restrictions for store-forwarding in processors based on Intel NetBurst
microarchitecture are illustrated in Figure 3-3.
3-49
GENERAL OPTIMIZATION GUIDELINES
Load Aligned with
Store W ill Forward
(a) Sm all load after
Large Store
(b) Size of Load >=
Store
(c) Size of Load >=
Store(s)
(d) 128-bit Forward
Must Be 16-Byte
Aligned
Non-Forwarding
Store
Penalty
Load
Store
Penalty
Load
Store
Penalty
Load
Store
Penalty
Load
16-Byte
Boundary
OM15155
Figure 3-3. Size and Alignment Restrictions in Store Forwarding
The following rules help satisfy size and alignment restrictions for store forwarding:
Assembly/Compiler Coding Rule 47. (H impact, M generality) A load that forwards from a store
must have the same address start point and therefore the same alignment as the store data.
Assembly/Compiler Coding Rule 48. (H impact, M generality) The data of a load which is
forwarded from a store must be completely contained within the store data.
A load that forwards from a store must wait for the store’s data to be written to the store buffer before
proceeding, but other, unrelated loads need not wait.
3-50
GENERAL OPTIMIZATION GUIDELINES
Assembly/Compiler Coding Rule 49. (H impact, ML generality) If it is necessary to extract a nonaligned portion of stored data, read out the smallest aligned portion that completely contains the data
and shift/mask the data as necessary. This is better than incurring the penalties of a failed storeforward.
Assembly/Compiler Coding Rule 50. (MH impact, ML generality) Avoid several small loads after
large stores to the same area of memory by using a single large read and register copies as needed.
Example 3-41 depicts several store-forwarding situations in which small loads follow large stores. The
first three load operations illustrate the situations described in Rule 50. However, the last load operation
gets data from store-forwarding without problem.
Example 3-41. Situations Showing Small Loads After Large Store
mov [EBP],‘abcd’
mov AL, [EBP]
mov BL, [EBP + 1]
mov CL, [EBP + 2]
mov DL, [EBP + 3]
mov AL, [EBP]
; Not blocked - same alignment
; Blocked
; Blocked
; Blocked
; Not blocked - same alignment
; n.b. passes older blocked loads
Example 3-42 illustrates a store-forwarding situation in which a large load follows several small stores.
The data needed by the load operation cannot be forwarded because all of the data that needs to be
forwarded is not contained in the store buffer. Avoid large loads after small stores to the same area of
memory.
Example 3-42. Non-forwarding Example of Large Load After Small Store
mov [EBP], ‘a’
mov [EBP + 1], ‘b’
mov [EBP + 2], ‘c’
mov [EBP + 3], ‘d’
mov EAX, [EBP] ; Blocked
; The first 4 small store can be consolidated into
; a single DWORD store to prevent this non-forwarding
; situation.
Example 3-43 illustrates a stalled store-forwarding situation that may appear in compiler generated
code. Sometimes a compiler generates code similar to that shown in Example 3-43 to handle a spilled
byte to the stack and convert the byte to an integer value.
Example 3-43. A Non-forwarding Situation in Compiler Generated Code
mov DWORD PTR [esp+10h], 00000000h
mov BYTE PTR [esp+10h], bl
mov eax, DWORD PTR [esp+10h] ; Stall
and eax, 0xff
; Converting back to byte value
3-51
GENERAL OPTIMIZATION GUIDELINES
Example 3-44 offers two alternatives to avoid the non-forwarding situation shown in Example 3-43.
Example 3-44. Two Ways to Avoid Non-forwarding Situation in Example 3-43
; A. Use MOVZ instruction to avoid large load after small
; store, when spills are ignored.
movz eax, bl
; Replaces the last three instructions
; B. Use MOVZ instruction and handle spills to the stack
mov DWORD PTR [esp+10h], 00000000h
mov BYTE PTR [esp+10h], bl
movz eax, BYTE PTR [esp+10h]
; Not blocked
When moving data that is smaller than 64 bits between memory locations, 64-bit or 128-bit SIMD
register moves are more efficient (if aligned) and can be used to avoid unaligned loads. Although
floating-point registers allow the movement of 64 bits at a time, floating-point instructions should not be
used for this purpose, as data may be inadvertently modified.
As an additional example, consider the cases in Example 3-45.
Example 3-45. Large and Small Load Stalls
; A. Large load stall
mov
mov
fld
mem, eax
mem + 4, ebx
mem
; Store dword to address “MEM"
; Store dword to address “MEM + 4"
; Load qword at address “MEM", stalls
; B. Small Load stall
fstp
mov
mov
mem
bx, mem+2
cx, mem+4
; Store qword to address “MEM"
; Load word at address “MEM + 2", stalls
; Load word at address “MEM + 4", stalls
In the first case (A), there is a large load after a series of small stores to the same area of memory
(beginning at memory address MEM). The large load will stall.
The FLD must wait for the stores to write to memory before it can access all the data it requires. This stall
can also occur with other data types (for example, when bytes or words are stored and then words or
doublewords are read from the same area of memory).
In the second case (B), there is a series of small loads after a large store to the same area of memory
(beginning at memory address MEM). The small loads will stall.
The word loads must wait for the quadword store to write to memory before they can access the data
they require. This stall can also occur with other data types (for example, when doublewords or words
are stored and then words or bytes are read from the same area of memory). This can be avoided by
moving the store as far from the loads as possible.
3-52
GENERAL OPTIMIZATION GUIDELINES
Store forwarding restrictions for processors based on Intel Core microarchitecture is listed in Table 3-3.
Table 3-3. Store Forwarding Restrictions of Processors Based on Intel Core Microarchitecture
Store Forwarding
Store Alignment Width of Store (bits) Load Alignment (byte)
Width of Load (bits)
Restriction
To Natural size
16
word aligned
8, 16
not stalled
To Natural size
16
not word aligned
8
stalled
To Natural size
32
dword aligned
8, 32
not stalled
To Natural size
32
not dword aligned
8
stalled
To Natural size
32
word aligned
16
not stalled
To Natural size
32
not word aligned
16
stalled
To Natural size
64
qword aligned
8, 16, 64
not stalled
To Natural size
64
not qword aligned
8, 16
stalled
To Natural size
64
dword aligned
32
not stalled
To Natural size
64
not dword aligned
32
stalled
To Natural size
128
dqword aligned
8, 16, 128
not stalled
To Natural size
128
not dqword aligned
8, 16
stalled
To Natural size
128
dword aligned
32
not stalled
To Natural size
128
not dword aligned
32
stalled
To Natural size
128
qword aligned
64
not stalled
To Natural size
128
not qword aligned
64
stalled
Unaligned, start
byte 1
32
byte 0 of store
8, 16, 32
not stalled
Unaligned, start
byte 1
32
not byte 0 of store
8, 16
stalled
Unaligned, start
byte 1
64
byte 0 of store
8, 16, 32
not stalled
Unaligned, start
byte 1
64
not byte 0 of store
8, 16, 32
stalled
Unaligned, start
byte 1
64
byte 0 of store
64
stalled
Unaligned, start
byte 7
32
byte 0 of store
8
not stalled
Unaligned, start
byte 7
32
not byte 0 of store
8
not stalled
Unaligned, start
byte 7
32
don’t care
16, 32
stalled
Unaligned, start
byte 7
64
don’t care
16, 32, 64
stalled
3.6.5.2
Store-forwarding Restriction on Data Availability
The value to be stored must be available before the load operation can be completed. If this restriction is
violated, the execution of the load will be delayed until the data is available. This delay causes some
execution resources to be used unnecessarily, and that can lead to sizable but non-deterministic delays.
However, the overall impact of this problem is much smaller than that from violating size and alignment
requirements.
3-53
GENERAL OPTIMIZATION GUIDELINES
In modern microarchitectures, hardware predicts when loads are dependent on and get their data
forwarded from preceding stores. These predictions can significantly improve performance. However, if a
load is scheduled too soon after the store it depends on or if the generation of the data to be stored is
delayed, there can be a significant penalty.
There are several cases in which data is passed through memory, and the store may need to be separated from the load:
•
•
•
•
•
Spills, save and restore registers in a stack frame.
Parameter passing.
Global and volatile variables.
Type conversion between integer and floating-point.
When compilers do not analyze code that is inlined, forcing variables that are involved in the interface
with inlined code to be in memory, creating more memory variables and preventing the elimination of
redundant loads.
Assembly/Compiler Coding Rule 51. (H impact, MH generality) Where it is possible to do so
without incurring other penalties, prioritize the allocation of variables to registers, as in register
allocation and for parameter passing, to minimize the likelihood and impact of store-forwarding
problems. Try not to store-forward data generated from a long latency instruction - for example, MUL
or DIV. Avoid store-forwarding data for variables with the shortest store-load distance. Avoid storeforwarding data for variables with many and/or long dependence chains, and especially avoid including
a store forward on a loop-carried dependence chain.
Example 3-46 shows an example of a loop-carried dependence chain.
Example 3-46. Loop-carried Dependence Chain
for ( i = 0; i < MAX; i++ ) {
a[i] = b[i] * foo;
foo = a[i] / 3;
}
// foo is a loop-carried dependence.
Assembly/Compiler Coding Rule 52. (M impact, MH generality) Calculate store addresses as
early as possible to avoid having stores block loads.
3.6.6
Data Layout Optimizations
User/Source Coding Rule 6. (H impact, M generality) Pad data structures defined in the source
code so that every data element is aligned to a natural operand size address boundary.
If the operands are packed in a SIMD instruction, align to the packed element size (64-bit or 128-bit).
Align data by providing padding inside structures and arrays. Programmers can reorganize structures and
arrays to minimize the amount of memory wasted by padding. However, compilers might not have this
freedom. The C programming language, for example, specifies the order in which structure elements are
allocated in memory. For more information, see Section 4.4, “Stack and Data Alignment”.
3-54
GENERAL OPTIMIZATION GUIDELINES
Example 3-47 shows how a data structure could be rearranged to reduce its size.
Example 3-47. Rearranging a Data Structure
struct unpacked { /* Fits in 20 bytes due to padding */
int
a;
char
b;
int
c;
char
d;
int
e;
};
struct packed { /* Fits in 16 bytes */
int
a;
int
c;
int
e;
char
b;
char
d;
}
Cache line size of 64 bytes can impact streaming applications (for example, multimedia). These reference and use data only once before discarding it. Data accesses which sparsely utilize the data within a
cache line can result in less efficient utilization of system memory bandwidth. For example, arrays of
structures can be decomposed into several arrays to achieve better packing, as shown in Example 3-48.
Example 3-48. Decomposing an Array
struct {
/* 1600 bytes */
int a, c, e;
char b, d;
} array_of_struct [100];
struct {
/* 1400 bytes */
int a[100], c[100], e[100];
char b[100], d[100];
} struct_of_array;
struct {
/* 1200 bytes */
int a, c, e;
} hybrid_struct_of_array_ace[100];
struct {
/* 200 bytes */
char b, d;
} hybrid_struct_of_array_bd[100];
The efficiency of such optimizations depends on usage patterns. If the elements of the structure are all
accessed together but the access pattern of the array is random, then ARRAY_OF_STRUCT avoids unnecessary prefetch even though it wastes memory.
However, if the access pattern of the array exhibits locality (for example, if the array index is being swept
through) then processors with hardware prefetchers will prefetch data from STRUCT_OF_ARRAY, even if
the elements of the structure are accessed together.
3-55
GENERAL OPTIMIZATION GUIDELINES
When the elements of the structure are not accessed with equal frequency, such as when element A is
accessed ten times more often than the other entries, then STRUCT_OF_ARRAY not only saves memory,
but it also prevents fetching unnecessary data items B, C, D, and E.
Using STRUCT_OF_ARRAY also enables the use of the SIMD data types by the programmer and the
compiler.
Note that STRUCT_OF_ARRAY can have the disadvantage of requiring more independent memory stream
references. This can require the use of more prefetches and additional address generation calculations.
It can also have an impact on DRAM page access efficiency. An alternative, HYBRID_STRUCT_OF_ARRAY
blends the two approaches. In this case, only 2 separate address streams are generated and referenced:
1 for HYBRID_STRUCT_OF_ARRAY_ACE and 1 for HYBRID_STRUCT_OF_ARRAY_BD. The second alterative also prevents fetching unnecessary data — assuming that (1) the variables A, C and E are always
used together, and (2) the variables B and D are always used together, but not at the same time as A, C
and E.
The hybrid approach ensures:
•
•
•
•
Simpler/fewer address generations than STRUCT_OF_ARRAY.
Fewer streams, which reduces DRAM page misses.
Fewer prefetches due to fewer streams.
Efficient cache line packing of data elements that are used concurrently.
Assembly/Compiler Coding Rule 53. (H impact, M generality) Try to arrange data structures
such that they permit sequential access.
If the data is arranged into a set of streams, the automatic hardware prefetcher can prefetch data that
will be needed by the application, reducing the effective memory latency. If the data is accessed in a nonsequential manner, the automatic hardware prefetcher cannot prefetch the data. The prefetcher can
recognize up to eight concurrent streams. See Chapter 7, “Optimizing Cache Usage,” for more information on the hardware prefetcher.
User/Source Coding Rule 7. (M impact, L generality) Beware of false sharing within a cache line
(64 bytes).
3.6.7
Stack Alignment
Performance penalty of unaligned access to the stack happens when a memory reference splits a cache
line. This means that one out of eight spatially consecutive unaligned quadword accesses is always
penalized, similarly for one out of 4 consecutive, non-aligned double-quadword accesses, etc.
Aligning the stack may be beneficial any time there are data objects that exceed the default stack alignment of the system. For example, on 32/64bit Linux, and 64bit Windows, the default stack alignment is
16 bytes, while 32bit Windows is 4 bytes.
Assembly/Compiler Coding Rule 54. (H impact, M generality) Make sure that the stack is aligned
at the largest multi-byte granular data type boundary matching the register width.
Aligning the stack typically requires the use of an additional register to track across a padded area of
unknown amount. There is a trade-off between causing unaligned memory references that spanned
across a cache line and causing extra general purpose register spills.
The assembly level technique to implement dynamic stack alignment may depend on compilers, and
specific OS environment. The reader may wish to study the assembly output from a compiler of interest.
3-56
GENERAL OPTIMIZATION GUIDELINES
Example 3-49. Examples of Dynamical Stack Alignment
// 32-bit environment
push
ebp ; save ebp
mov
ebp, esp ; ebp now points to incoming parameters
andl
esp, $-<N> ;align esp to N byte boundary
sub
esp, $<stack_size>; reserve space for new stack frame
.
; parameters must be referenced off of ebp
mov
esp, ebp ; restore esp
pop
ebp ; restore ebp
// 64-bit environment
sub
esp, $<stack_size +N>
mov
r13, $<offset_of_aligned_section_in_stack>
andl
r13, $-<N> ; r13 point to aligned section in stack
.
;use r13 as base for aligned data
If for some reason it is not possible to align the stack for 64-bits, the routine should access the parameter
and save it into a register or known aligned storage, thus incurring the penalty only once.
3.6.8
Capacity Limits and Aliasing in Caches
There are cases in which addresses with a given stride will compete for some resource in the memory
hierarchy.
Typically, caches are implemented to have multiple ways of set associativity, with each way consisting of
multiple sets of cache lines (or sectors in some cases). Multiple memory references that compete for the
same set of each way in a cache can cause a capacity issue. There are aliasing conditions that apply to
specific microarchitectures. Note that first-level cache lines are 64 bytes. Thus, the least significant 6 bits
are not considered in alias comparisons. For processors based on Intel NetBurst microarchitecture, data
is loaded into the second level cache in a sector of 128 bytes, so the least significant 7 bits are not
considered in alias comparisons.
3.6.8.1
Capacity Limits in Set-Associative Caches
Capacity limits may be reached if the number of outstanding memory references that are mapped to the
same set in each way of a given cache exceeds the number of ways of that cache. The conditions that
apply to the first-level data cache and second level cache are listed below:
•
L1 Set Conflicts — Multiple references map to the same first-level cache set. The conflicting
condition is a stride determined by the size of the cache in bytes, divided by the number of ways.
These competing memory references can cause excessive cache misses only if the number of
outstanding memory references exceeds the number of ways in the working set:
— On Pentium 4 and Intel Xeon processors with a CPUID signature of family encoding 15, model
encoding of 0, 1, or 2; there will be an excess of first-level cache misses for more than 4 simultaneous competing memory references to addresses with 2-KByte modulus.
— On Pentium 4 and Intel Xeon processors with a CPUID signature of family encoding 15, model
encoding 3; there will be an excess of first-level cache misses for more than 8 simultaneous
competing references to addresses that are apart by 2-KByte modulus.
3-57
GENERAL OPTIMIZATION GUIDELINES
— On Intel Core 2 Duo, Intel Core Duo, Intel Core Solo, and Pentium M processors, there will be an
excess of first-level cache misses for more than 8 simultaneous references to addresses that are
apart by 4-KByte modulus.
•
L2 Set Conflicts — Multiple references map to the same second-level cache set. The conflicting
condition is also determined by the size of the cache or the number of ways:
— On Pentium 4 and Intel Xeon processors, there will be an excess of second-level cache misses for
more than 8 simultaneous competing references. The stride sizes that can cause capacity issues
are 32 KBytes, 64 KBytes, or 128 KBytes, depending of the size of the second level cache.
— On Pentium M processors, the stride sizes that can cause capacity issues are 128 KBytes or 256
KBytes, depending of the size of the second level cache. On Intel Core 2 Duo, Intel Core Duo,
Intel Core Solo processors, stride size of 256 KBytes can cause capacity issue if the number of
simultaneous accesses exceeded the way associativity of the L2 cache.
3.6.8.2
Aliasing Cases in the Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo and Intel® Core™
2 Duo Processors
Pentium M, Intel Core Solo, Intel Core Duo and Intel Core 2 Duo processors have the following aliasing
case:
•
Store forwarding — If a store to an address is followed by a load from the same address, the load
will not proceed until the store data is available. If a store is followed by a load and their addresses
differ by a multiple of 4 KBytes, the load stalls until the store operation completes.
Assembly/Compiler Coding Rule 55. (H impact, M generality) Avoid having a store followed by a
non-dependent load with addresses that differ by a multiple of 4 KBytes. Also, lay out data or order
computation to avoid having cache lines that have linear addresses that are a multiple of 64 KBytes
apart in the same working set. Avoid having more than 4 cache lines that are some multiple of 2 KBytes
apart in the same first-level cache working set, and avoid having more than 8 cache lines that are some
multiple of 4 KBytes apart in the same first-level cache working set.
When declaring multiple arrays that are referenced with the same index and are each a multiple of 64
KBytes (as can happen with STRUCT_OF_ARRAY data layouts), pad them to avoid declaring them contiguously. Padding can be accomplished by either intervening declarations of other variables or by artificially
increasing the dimension.
User/Source Coding Rule 8. (H impact, ML generality) Consider using a special memory allocation
library with address offset capability to avoid aliasing. One way to implement a memory allocator to
avoid aliasing is to allocate more than enough space and pad. For example, allocate structures that are
68 KB instead of 64 KBytes to avoid the 64-KByte aliasing, or have the allocator pad and return random
offsets that are a multiple of 128 Bytes (the size of a cache line).
User/Source Coding Rule 9. (M impact, M generality) When padding variable declarations to
avoid aliasing, the greatest benefit comes from avoiding aliasing on second-level cache lines,
suggesting an offset of 128 bytes or more.
4-KByte memory aliasing occurs when the code accesses two different memory locations with a 4-KByte
offset between them. The 4-KByte aliasing situation can manifest in a memory copy routine where the
addresses of the source buffer and destination buffer maintain a constant offset and the constant offset
happens to be a multiple of the byte increment from one iteration to the next.
Example 3-50 shows a routine that copies 16 bytes of memory in each iteration of a loop. If the offsets
(modular 4096) between source buffer (EAX) and destination buffer (EDX) differ by 16, 32, 48, 64, 80;
loads have to wait until stores have been retired before they can continue. For example at offset 16, the
load of the next iteration is 4-KByte aliased current iteration store, therefore the loop must wait until the
store operation completes, making the entire loop serialized. The amount of time needed to wait
decreases with larger offset until offset of 96 resolves the issue (as there is no pending stores by the time
of the load with same address).
3-58
GENERAL OPTIMIZATION GUIDELINES
The Intel Core microarchitecture provides a performance monitoring event (see
LOAD_BLOCK.OVERLAP_STORE in Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B) that allows software tuning effort to detect the occurrence of aliasing conditions.
Example 3-50. Aliasing Between Loads and Stores Across Loop Iterations
LP:
movaps xmm0, [eax+ecx]
movaps [edx+ecx], xmm0
add ecx, 16
jnz lp
3.6.9
Mixing Code and Data
The aggressive prefetching and pre-decoding of instructions by Intel processors have two related effects:
•
Self-modifying code works correctly, according to the Intel architecture processor requirements, but
incurs a significant performance penalty. Avoid self-modifying code if possible.
•
Placing writable data in the code segment might be impossible to distinguish from self-modifying
code. Writable data in the code segment might suffer the same performance penalty as selfmodifying code.
Assembly/Compiler Coding Rule 56. (M impact, L generality) If (hopefully read-only) data must
occur on the same page as code, avoid placing it immediately after an indirect jump. For example,
follow an indirect jump with its mostly likely target, and place the data after an unconditional branch.
Tuning Suggestion 1. In rare cases, a performance problem may be caused by executing data on a
code page as instructions. This is very likely to happen when execution is following an indirect branch
that is not resident in the trace cache. If this is clearly causing a performance problem, try moving the
data elsewhere, or inserting an illegal opcode or a PAUSE instruction immediately after the indirect
branch. Note that the latter two alternatives may degrade performance in some circumstances.
Assembly/Compiler Coding Rule 57. (H impact, L generality) Always put code and data on
separate pages. Avoid self-modifying code wherever possible. If code is to be modified, try to do it all at
once and make sure the code that performs the modifications and the code being modified are on
separate 4-KByte pages or on separate aligned 1-KByte subpages.
3.6.9.1
Self-modifying Code
Self-modifying code (SMC) that ran correctly on Pentium III processors and prior implementations will run
correctly on subsequent implementations. SMC and cross-modifying code (when multiple processors in a
multiprocessor system are writing to a code page) should be avoided when high performance is desired.
Software should avoid writing to a code page in the same 1-KByte subpage that is being executed or
fetching code in the same 2-KByte subpage of that is being written. In addition, sharing a page
containing directly or speculatively executed code with another processor as a data page can trigger an
SMC condition that causes the entire pipeline of the machine and the trace cache to be cleared. This is
due to the self-modifying code condition.
Dynamic code need not cause the SMC condition if the code written fills up a data page before that page
is accessed as code. Dynamically-modified code (for example, from target fix-ups) is likely to suffer from
the SMC condition and should be avoided where possible. Avoid the condition by introducing indirect
branches and using data tables on data pages (not code pages) using register-indirect calls.
3-59
GENERAL OPTIMIZATION GUIDELINES
3.6.9.2
Position Independent Code
Position independent code often needs to obtain the value of the instruction pointer. Example 3-51a
shows one technique to put the value of IP into the ECX register by issuing a CALL without a matching
RET. Example 3-51b shows an alternative technique to put the value of IP into the ECX register using a
matched pair of CALL/RET.
Example 3-51. Instruction Pointer Query Techniques
a) Using call without return to obtain IP does not corrupt the RSB
call _label; return address pushed is the IP of next instruction
_label:
pop ECX; IP of this instruction is now put into ECX
b) Using matched call/ret pair
call _lblcx;
... ; ECX now contains IP of this instruction
...
_lblcx
mov ecx, [esp];
ret
3.6.10
Write Combining
Write combining (WC) improves performance in two ways:
•
On a write miss to the first-level cache, it allows multiple stores to the same cache line to occur
before that cache line is read for ownership (RFO) from further out in the cache/memory hierarchy.
Then the rest of line is read, and the bytes that have not been written are combined with the
unmodified bytes in the returned line.
•
Write combining allows multiple writes to be assembled and written further out in the cache hierarchy
as a unit. This saves port and bus traffic. Saving traffic is particularly important for avoiding partial
writes to uncached memory.
There are six write-combining buffers (on Pentium 4 and Intel Xeon processors with a CPUID signature of
family encoding 15, model encoding 3; there are 8 write-combining buffers). Two of these buffers may
be written out to higher cache levels and freed up for use on other write misses. Only four writecombining buffers are guaranteed to be available for simultaneous use. Write combining applies to
memory type WC; it does not apply to memory type UC.
There are six write-combining buffers in each processor core in Intel Core Duo and Intel Core Solo
processors. Processors based on Intel Core microarchitecture have eight write-combining buffers in each
core. Starting with Intel microarchitecture code name Nehalem, there are 10 buffers available for writecombining.
Assembly/Compiler Coding Rule 58. (H impact, L generality) If an inner loop writes to more than
four arrays (four distinct cache lines), apply loop fission to break up the body of the loop such that only
four arrays are being written to in each iteration of each of the resulting loops.
Write combining buffers are used for stores of all memory types. They are particularly important for
writes to uncached memory: writes to different parts of the same cache line can be grouped into a single,
full-cache-line bus transaction instead of going across the bus (since they are not cached) as several
partial writes. Avoiding partial writes can have a significant impact on bus bandwidth-bound graphics
applications, where graphics buffers are in uncached memory. Separating writes to uncached memory
and writes to writeback memory into separate phases can assure that the write combining buffers can fill
before getting evicted by other write traffic. Eliminating partial write transactions has been found to have
3-60
GENERAL OPTIMIZATION GUIDELINES
performance impact on the order of 20% for some applications. Because the cache lines are 64 bytes, a
write to the bus for 63 bytes will result in 8 partial bus transactions.
When coding functions that execute simultaneously on two threads, reducing the number of writes that
are allowed in an inner loop will help take full advantage of write-combining store buffers. For writecombining buffer recommendations for Hyper-Threading Technology, see Chapter 9, “Multicore and
Hyper-Threading Technology.”
Store ordering and visibility are also important issues for write combining. When a write to a writecombining buffer for a previously-unwritten cache line occurs, there will be a read-for-ownership (RFO).
If a subsequent write happens to another write-combining buffer, a separate RFO may be caused for that
cache line. Subsequent writes to the first cache line and write-combining buffer will be delayed until the
second RFO has been serviced to guarantee properly ordered visibility of the writes. If the memory type
for the writes is write-combining, there will be no RFO since the line is not cached, and there is no such
delay. For details on write-combining, see Chapter 7, “Optimizing Cache Usage.”
3.6.11
Locality Enhancement
Locality enhancement can reduce data traffic originating from an outer-level sub-system in the
cache/memory hierarchy. This is to address the fact that the access-cost in terms of cycle-count from an
outer level will be more expensive than from an inner level. Typically, the cycle-cost of accessing a given
cache level (or memory system) varies across different microarchitectures, processor implementations,
and platform components. It may be sufficient to recognize the relative data access cost trend by locality
rather than to follow a large table of numeric values of cycle-costs, listed per locality, per processor/platform implementations, etc. The general trend is typically that access cost from an outer sub-system may
be approximately 3-10X more expensive than accessing data from the immediate inner level in the
cache/memory hierarchy, assuming similar degrees of data access parallelism.
Thus locality enhancement should start with characterizing the dominant data traffic locality. Section A,
“Application Performance Tools,” describes some techniques that can be used to determine the dominant
data traffic locality for any workload.
Even if cache miss rates of the last level cache may be low relative to the number of cache references,
processors typically spend a sizable portion of their execution time waiting for cache misses to be
serviced. Reducing cache misses by enhancing a program’s locality is a key optimization. This can take
several forms:
•
Blocking to iterate over a portion of an array that will fit in the cache (with the purpose that
subsequent references to the data-block [or tile] will be cache hit references).
•
•
Loop interchange to avoid crossing cache lines or page boundaries.
Loop skewing to make accesses contiguous.
Locality enhancement to the last level cache can be accomplished with sequencing the data access
pattern to take advantage of hardware prefetching. This can also take several forms:
•
Transformation of a sparsely populated multi-dimensional array into a one-dimension array such that
memory references occur in a sequential, small-stride pattern that is friendly to the hardware
prefetch (see Section 2.4.5.4, “Data Prefetching”).
•
Optimal tile size and shape selection can further improve temporal data locality by increasing hit
rates into the last level cache and reduce memory traffic resulting from the actions of hardware
prefetching (see Section 7.5.11, “Hardware Prefetching and Cache Blocking Techniques”).
It is important to avoid operations that work against locality-enhancing techniques. Using the lock prefix
heavily can incur large delays when accessing memory, regardless of whether the data is in the cache or
in system memory.
User/Source Coding Rule 10. (H impact, H generality) Optimization techniques such as blocking,
loop interchange, loop skewing, and packing are best done by the compiler. Optimize data structures
either to fit in one-half of the first-level cache or in the second-level cache; turn on loop optimizations
in the compiler to enhance locality for nested loops.
3-61
GENERAL OPTIMIZATION GUIDELINES
Optimizing for one-half of the first-level cache will bring the greatest performance benefit in terms of
cycle-cost per data access. If one-half of the first-level cache is too small to be practical, optimize for the
second-level cache. Optimizing for a point in between (for example, for the entire first-level cache) will
likely not bring a substantial improvement over optimizing for the second-level cache.
3.6.12
Minimizing Bus Latency
Each bus transaction includes the overhead of making requests and arbitrations. The average latency of
bus read and bus write transactions will be longer if reads and writes alternate. Segmenting reads and
writes into phases can reduce the average latency of bus transactions. This is because the number of
incidences of successive transactions involving a read following a write, or a write following a read, are
reduced.
User/Source Coding Rule 11. (M impact, ML generality) If there is a blend of reads and writes on
the bus, changing the code to separate these bus transactions into read phases and write phases can
help performance.
Note, however, that the order of read and write operations on the bus is not the same as it appears in the
program.
Bus latency for fetching a cache line of data can vary as a function of the access stride of data references.
In general, bus latency will increase in response to increasing values of the stride of successive cache
misses. Independently, bus latency will also increase as a function of increasing bus queue depths (the
number of outstanding bus requests of a given transaction type). The combination of these two trends
can be highly non-linear, in that bus latency of large-stride, bandwidth-sensitive situations are such that
effective throughput of the bus system for data-parallel accesses can be significantly less than the effective throughput of small-stride, bandwidth-sensitive situations.
To minimize the per-access cost of memory traffic or amortize raw memory latency effectively, software
should control its cache miss pattern to favor higher concentration of smaller-stride cache misses.
User/Source Coding Rule 12. (H impact, H generality) To achieve effective amortization of bus
latency, software should favor data access patterns that result in higher concentrations of cache miss
patterns, with cache miss strides that are significantly smaller than half the hardware prefetch trigger
threshold.
3.6.13
Non-Temporal Store Bus Traffic
Peak system bus bandwidth is shared by several types of bus activities, including reads (from memory),
reads for ownership (of a cache line), and writes. The data transfer rate for bus write transactions is
higher if 64 bytes are written out to the bus at a time.
Typically, bus writes to Writeback (WB) memory must share the system bus bandwidth with read-forownership (RFO) traffic. Non-temporal stores do not require RFO traffic; they do require care in
managing the access patterns in order to ensure 64 bytes are evicted at once (rather than evicting
several 8-byte chunks).
3-62
GENERAL OPTIMIZATION GUIDELINES
Although the data bandwidth of full 64-byte bus writes due to non-temporal stores is twice that of bus
writes to WB memory, transferring 8-byte chunks wastes bus request bandwidth and delivers significantly lower data bandwidth. This difference is depicted in Examples 3-52 and 3-53.
Example 3-52. Using Non-temporal Stores and 64-byte Bus Write Transactions
#define STRIDESIZE 256
lea ecx, p64byte_Aligned
mov edx, ARRAY_LEN
xor eax, eax
slloop:
movntps XMMWORD ptr [ecx + eax], xmm0
movntps XMMWORD ptr [ecx + eax+16], xmm0
movntps XMMWORD ptr [ecx + eax+32], xmm0
movntps XMMWORD ptr [ecx + eax+48], xmm0
; 64 bytes is written in one bus transaction
add eax, STRIDESIZE
cmp eax, edx
jl slloop
Example 3-53. On-temporal Stores and Partial Bus Write Transactions
#define STRIDESIZE 256
Lea ecx, p64byte_Aligned
Mov edx, ARRAY_LEN
Xor eax, eax
slloop:
movntps XMMWORD ptr [ecx + eax], xmm0
movntps XMMWORD ptr [ecx + eax+16], xmm0
movntps XMMWORD ptr [ecx + eax+32], xmm0
; Storing 48 bytes results in 6 bus partial transactions
add eax, STRIDESIZE
cmp eax, edx
jl slloop
3.7
PREFETCHING
Recent Intel processor families employ several prefetching mechanisms to accelerate the movement of
data or code and improve performance:
•
•
•
Hardware instruction prefetcher.
Software prefetch for data.
Hardware prefetch for cache lines of data or instructions.
3.7.1
Hardware Instruction Fetching and Software Prefetching
Software prefetching requires a programmer to use PREFETCH hint instructions and anticipate some suitable timing and location of cache misses.
3-63
GENERAL OPTIMIZATION GUIDELINES
Software PREFETCH operations work the same way as do load from memory operations, with the
following exceptions:
•
•
Software PREFETCH instructions retire after virtual to physical address translation is completed.
•
Avoid specifying a NULL address for software prefetches.
If an exception, such as page fault, is required to prefetch the data, then the software prefetch
instruction retires without prefetching data.
3.7.2
Hardware Prefetching for First-Level Data Cache
The hardware prefetching mechanism for L1 in Intel Core microarchitecture is discussed in Section
2.5.4.2.
Example 3-54 depicts a technique to trigger hardware prefetch. The code demonstrates traversing a
linked list and performing some computational work on 2 members of each element that reside in 2
different cache lines. Each element is of size 192 bytes. The total size of all elements is larger than can
be fitted in the L2 cache.
Example 3-54. Using DCU Hardware Prefetch
Original code
Modified sequence benefit from prefetch
mov ebx, DWORD PTR [First]
xor eax, eax
scan_list:
mov eax, [ebx+4]
mov ecx, 60
mov ebx, DWORD PTR [First]
xor eax, eax
scan_list:
mov eax, [ebx+4]
mov eax, [ebx+4]
mov eax, [ebx+4]
mov ecx, 60
do_some_work_1:
add eax, eax
and eax, 6
sub ecx, 1
jnz do_some_work_1
mov eax, [ebx+64]
mov ecx, 30
do_some_work_2:
add eax, eax
and eax, 6
sub ecx, 1
jnz do_some_work_2
do_some_work_1:
add eax, eax
and eax, 6
sub ecx, 1
jnz do_some_work_1
mov eax, [ebx+64]
mov ecx, 30
do_some_work_2:
add eax, eax
and eax, 6
sub ecx, 1
jnz do_some_work_2
mov ebx, [ebx]
test ebx, ebx
jnz scan_list
mov ebx, [ebx]
test ebx, ebx
jnz scan_list
The additional instructions to load data from one member in the modified sequence can trigger the DCU
hardware prefetch mechanisms to prefetch data in the next cache line, enabling the work on the second
member to complete sooner.
Software can gain from the first-level data cache prefetchers in two cases:
•
If data is not in the second-level cache, the first-level data cache prefetcher enables early trigger of
the second-level cache prefetcher.
•
If data is in the second-level cache and not in the first-level data cache, then the first-level data cache
prefetcher triggers earlier data bring-up of sequential cache line to the first-level data cache.
3-64
GENERAL OPTIMIZATION GUIDELINES
There are situations that software should pay attention to a potential side effect of triggering unnecessary DCU hardware prefetches. If a large data structure with many members spanning many cache lines
is accessed in ways that only a few of its members are actually referenced, but there are multiple pair
accesses to the same cache line. The DCU hardware prefetcher can trigger fetching of cache lines that
are not needed. In Example , references to the “Pts” array and “AltPts” will trigger DCU prefetch to fetch
additional cache lines that won’t be needed. If significant negative performance impact is detected due
to DCU hardware prefetch on a portion of the code, software can try to reduce the size of that contemporaneous working set to be less than half of the L2 cache.
Example 3-55. Avoid Causing DCU Hardware Prefetch to Fetch Un-needed Lines
while ( CurrBond != NULL )
{
MyATOM *a1 = CurrBond->At1 ;
MyATOM *a2 = CurrBond->At2 ;
if ( a1->CurrStep <= a1->LastStep &&
a2->CurrStep <= a2->LastStep
)
{
a1->CurrStep++ ;
a2->CurrStep++ ;
double ux = a1->Pts[0].x - a2->Pts[0].x ;
double uy = a1->Pts[0].y - a2->Pts[0].y ;
double uz = a1->Pts[0].z - a2->Pts[0].z ;
a1->AuxPts[0].x += ux ;
a1->AuxPts[0].y += uy ;
a1->AuxPts[0].z += uz ;
a2->AuxPts[0].x += ux ;
a2->AuxPts[0].y += uy ;
a2->AuxPts[0].z += uz ;
};
CurrBond = CurrBond->Next ;
};
To fully benefit from these prefetchers, organize and access the data using one of the following methods:
Method 1:
•
•
Organize the data so consecutive accesses can usually be found in the same 4-KByte page.
Access the data in constant strides forward or backward IP Prefetcher.
Method 2:
•
•
Organize the data in consecutive lines.
Access the data in increasing addresses, in sequential cache lines.
Example demonstrates accesses to sequential cache lines that can benefit from the first-level cache
prefetcher.
3-65
GENERAL OPTIMIZATION GUIDELINES
Example 3-56. Technique For Using L1 Hardware Prefetch
unsigned int *p1, j, a, b;
for (j = 0; j < num; j += 16)
{
a = p1[j];
b = p1[j+1];
// Use these two values
}
By elevating the load operations from memory to the beginning of each iteration, it is likely that a significant part of the latency of the pair cache line transfer from memory to the second-level cache will be in
parallel with the transfer of the first cache line.
The IP prefetcher uses only the lower 8 bits of the address to distinguish a specific address. If the code
size of a loop is bigger than 256 bytes, two loads may appear similar in the lowest 8 bits and the IP
prefetcher will be restricted. Therefore, if you have a loop bigger than 256 bytes, make sure that no two
loads have the same lowest 8 bits in order to use the IP prefetcher.
3.7.3
Hardware Prefetching for Second-Level Cache
The Intel Core microarchitecture contains two second-level cache prefetchers:
•
Streamer — Loads data or instructions from memory to the second-level cache. To use the streamer,
organize the data or instructions in blocks of 128 bytes, aligned on 128 bytes. The first access to one
of the two cache lines in this block while it is in memory triggers the streamer to prefetch the pair
line. To software, the L2 streamer’s functionality is similar to the adjacent cache line prefetch
mechanism found in processors based on Intel NetBurst microarchitecture.
•
Data prefetch logic (DPL) — DPL and L2 Streamer are triggered only by writeback memory type.
They prefetch only inside page boundary (4 KBytes). Both L2 prefetchers can be triggered by
software prefetch instructions and by prefetch request from DCU prefetchers. DPL can also be
triggered by read for ownership (RFO) operations. The L2 Streamer can also be triggered by DPL
requests for L2 cache misses.
Software can gain from organizing data both according to the instruction pointer and according to line
strides. For example, for matrix calculations, columns can be prefetched by IP-based prefetches, and
rows can be prefetched by DPL and the L2 streamer.
3.7.4
Cacheability Instructions
SSE2 provides additional cacheability instructions that extend those provided in SSE. The new cacheability instructions include:
•
•
•
New streaming store instructions.
New cache line flush instruction.
New memory fencing instructions.
For more information, see Chapter 7, “Optimizing Cache Usage.”
3.7.5
REP Prefix and Data Movement
The REP prefix is commonly used with string move instructions for memory related library functions such
as MEMCPY (using REP MOVSD) or MEMSET (using REP STOS). These STRING/MOV instructions with the
REP prefixes are implemented in MS-ROM and have several implementation variants with different
performance levels.
3-66
GENERAL OPTIMIZATION GUIDELINES
The specific variant of the implementation is chosen at execution time based on data layout, alignment
and the counter (ECX) value. For example, MOVSB/STOSB with the REP prefix should be used with
counter value less than or equal to three for best performance.
String MOVE/STORE instructions have multiple data granularities. For efficient data movement, larger data
granularities are preferable. This means better efficiency can be achieved by decomposing an arbitrary
counter value into a number of doublewords plus single byte moves with a count value less than or equal
to 3.
Because software can use SIMD data movement instructions to move 16 bytes at a time, the following
paragraphs discuss general guidelines for designing and implementing high-performance library functions such as MEMCPY(), MEMSET(), and MEMMOVE(). Four factors are to be considered:
•
Throughput per iteration — If two pieces of code have approximately identical path lengths,
efficiency favors choosing the instruction that moves larger pieces of data per iteration. Also, smaller
code size per iteration will in general reduce overhead and improve throughput. Sometimes, this may
involve a comparison of the relative overhead of an iterative loop structure versus using REP prefix
for iteration.
•
Address alignment — Data movement instructions with highest throughput usually have alignment
restrictions, or they operate more efficiently if the destination address is aligned to its natural data
size. Specifically, 16-byte moves need to ensure the destination address is aligned to 16-byte
boundaries, and 8-bytes moves perform better if the destination address is aligned to 8-byte
boundaries. Frequently, moving at doubleword granularity performs better with addresses that are 8byte aligned.
•
REP string move vs. SIMD move — Implementing general-purpose memory functions using SIMD
extensions usually requires adding some prolog code to ensure the availability of SIMD instructions,
preamble code to facilitate aligned data movement requirements at runtime. Throughput comparison
must also take into consideration the overhead of the prolog when considering a REP string implementation versus a SIMD approach.
•
Cache eviction — If the amount of data to be processed by a memory routine approaches half the
size of the last level on-die cache, temporal locality of the cache may suffer. Using streaming store
instructions (for example: MOVNTQ, MOVNTDQ) can minimize the effect of flushing the cache. The
threshold to start using a streaming store depends on the size of the last level cache. Determine the
size using the deterministic cache parameter leaf of CPUID.
Techniques for using streaming stores for implementing a MEMSET()-type library must also consider
that the application can benefit from this technique only if it has no immediate need to reference
the target addresses. This assumption is easily upheld when testing a streaming-store implementation on a micro-benchmark configuration, but violated in a full-scale application situation.
When applying general heuristics to the design of general-purpose, high-performance library routines,
the following guidelines can are useful when optimizing an arbitrary counter value N and address alignment. Different techniques may be necessary for optimal performance, depending on the magnitude of
N:
•
When N is less than some small count (where the small count threshold will vary between microarchitectures -- empirically, 8 may be a good value when optimizing for Intel NetBurst microarchitecture),
each case can be coded directly without the overhead of a looping structure. For example, 11 bytes
can be processed using two MOVSD instructions explicitly and a MOVSB with REP counter equaling 3.
•
When N is not small but still less than some threshold value (which may vary for different microarchitectures, but can be determined empirically), an SIMD implementation using run-time CPUID
and alignment prolog will likely deliver less throughput due to the overhead of the prolog. A REP
string implementation should favor using a REP string of doublewords. To improve address
alignment, a small piece of prolog code using MOVSB/STOSB with a count less than 4 can be used to
peel off the non-aligned data moves before starting to use MOVSD/STOSD.
•
When N is less than half the size of last level cache, throughput consideration may favor either:
— An approach using a REP string with the largest data granularity because a REP string has little
overhead for loop iteration, and the branch misprediction overhead in the prolog/epilogue code to
handle address alignment is amortized over many iterations.
3-67
GENERAL OPTIMIZATION GUIDELINES
— An iterative approach using the instruction with largest data granularity, where the overhead for
SIMD feature detection, iteration overhead, and prolog/epilogue for alignment control can be
minimized. The trade-off between these approaches may depend on the microarchitecture.
An example of MEMSET() implemented using stosd for arbitrary counter value with the destination
address aligned to doubleword boundary in 32-bit mode is shown in Example 3-57.
•
When N is larger than half the size of the last level cache, using 16-byte granularity streaming stores
with prolog/epilog for address alignment will likely be more efficient, if the destination addresses will
not be referenced immediately afterwards.
Example 3-57. REP STOSD with Arbitrary Count Size and 4-Byte-Aligned Destination
A ‘C’ example of Memset()
Equivalent Implementation Using REP STOSD
void memset(void *dst,int c,size_t size)
{
char *d = (char *)dst;
size_t i;
for (i=0;i<size;i++)
*d++ = (char)c;
}
push edi
movzx eax, byte ptr [esp+12]
mov ecx, eax
shl ecx, 8
or ecx, eax
mov ecx, eax
shl ecx, 16
or eax, ecx
mov edi, [esp+8]
mov ecx, [esp+16]
shr ecx, 2
cmp ecx, 127
jle _main
test edi, 4
jz _main
stosd
dec ecx
_main:
rep stosd
mov ecx, [esp + 16]
and ecx, 3
rep stosb
pop edi
ret
; 4-byte aligned
; byte count
; do dword
;peel off one dword
; 8-byte aligned
; do count <= 3
; optimal with <= 3
Memory routines in the runtime library generated by Intel compilers are optimized across a wide range
of address alignments, counter values, and microarchitectures. In most cases, applications should take
advantage of the default memory routines provided by Intel compilers.
In some situations, the byte count of the data is known by the context (as opposed to being known by a
parameter passed from a call), and one can take a simpler approach than those required for a generalpurpose library routine. For example, if the byte count is also small, using REP MOVSB/STOSB with a
count less than four can ensure good address alignment and loop-unrolling to finish the remaining data;
using MOVSD/STOSD can reduce the overhead associated with iteration.
Using a REP prefix with string move instructions can provide high performance in the situations described
above. However, using a REP prefix with string scan instructions (SCASB, SCASW, SCASD, SCASQ) or
compare instructions (CMPSB, CMPSW, SMPSD, SMPSQ) is not recommended for high performance.
Consider using SIMD instructions instead.
3-68
GENERAL OPTIMIZATION GUIDELINES
3.7.6
Enhanced REP MOVSB and STOSB Operation
Beginning with processors based on Intel microarchitecture code name Ivy Bridge, REP string operation
using MOVSB and STOSB can provide both flexible and high-performance REP string operations for software in common situations like memory copy and set operations. Processors that provide enhanced
MOVSB/STOSB operations are enumerated by the CPUID feature flag: CPUID:(EAX=7H,
ECX=0H):EBX.[bit 9] = 1.
3.7.6.1
Memcpy Considerations
The interface for the standard library function memcpy introduces several factors (e.g. length, alignment
of the source buffer and destination) that interact with microarchitecture to determine the performance
characteristics of the implementation of the library function. Two of the common approaches to implement memcpy are driven from small code size vs. maximum throughput. The former generally uses REP
MOVSD+B (see Section 3.7.5), while the latter uses SIMD instruction sets and has to deal with additional
data alignment restrictions.
For processors supporting enhanced REP MOVSB/STOSB, implementing memcpy with REP MOVSB will
provide even more compact benefits in code size and better throughput than using the combination of
REP MOVSD+B. For processors based on Intel microarchitecture code name Ivy Bridge, implementing
memcpy using Enhanced REP MOVSB and STOSB might not reach the same level of throughput as using
256-bit or 128-bit AVX alternatives, depending on length and alignment factors.
160
REP MOVSB
REP MOVSD+B
140
120
100
se80
lc
yc60
40
20
0
0 2
0 2
4 6
8 0
2 4
6 8
0 2
4 6
8 0
2 4
6 8
0 2
4 6
8 0
2 4
3 4
6 6
9 8
2
1 6
1 9
1 2
2 5
2 8
2 2
3 5
3 8
3 1
4 4
4 8
4 1
5 4
5 7
5 0
6 4
6 7
6 0
7 3
7 6
7 0
8 3
8 6
8 9
8 2
9 6
9 9
9 2
0
1
length in bytes
Figure 3-4. Memcpy Performance Comparison for Lengths up to 2KB
Figure 3-4 depicts the relative performance of memcpy implementation on a third-generation Intel Core
processor using Enhanced REP MOVSB and STOSB versus REP MOVSD+B, for alignment conditions when
both the source and destination addresses are aligned to a 16-Byte boundary and the source region does
not overlap with the destination region. Using Enhanced REP MOVSB and STOSB always delivers better
performance than using REP MOVSD+B. If the length is a multiple of 64, it can produce even higher
3-69
GENERAL OPTIMIZATION GUIDELINES
performance. For example, copying 65-128 bytes takes 40 cycles, while copying 128 bytes needs only 35
cycles.
If an application wishes to bypass standard memcpy library implementation with its own custom implementation and have freedom to manage the buffer length allocation for both source and destination, it
may be worthwhile to manipulate the lengths of its memory copy operation to be multiples of 64 to take
advantage the code size and performance benefit of Enhanced REP MOVSB and STOSB.
The performance characteristic of implementing a general-purpose memcpy library function using a
SIMD register is significantly more colorful than an equivalent implementation using a general-purpose
register, depending on length, instruction set selection between SSE2, 128-bit AVX, 256-bit AVX, relative
alignment of source/destination, and memory address alignment granularities/boundaries, etc.
Hence comparing performance characteristics between a memcpy using Enhanced REP MOVSB and
STOSB versus a SIMD implementation is highly dependent on the particular SIMD implementation. The
remainder of this section discusses the relative performance of memcpy using Enhanced REP MOVSB and
STOSB versus unpublished, optimized 128-bit AVX implementation of memcpy to illustrate the hardware
capability of Intel microarchitecture code name Ivy Bridge.
Table 3-4. Relative Performance of Memcpy() Using Enhanced REP MOVSB and STOSB Vs. 128-bit AVX
Range of Lengths (bytes)
<128
128 to 2048
2048 to 4096
Memcpy_ERMSB/Memcpy_AVX128
0x7X
1X
1.02X
Table 3-4 shows the relative performance of the Memcpy function implemented using enhanced REP
MOVSB versus 128-bit AVX for several ranges of memcpy lengths, when both the source and destination
addresses are 16-byte aligned and the source region and destination region do not overlap. For memcpy
length less than 128 bytes, using Enhanced REP MOVSB and STOSB is slower than what’s possible using
128-bit AVX, due to internal start-up overhead in the REP string.
For situations with address misalignment, memcpy performance will generally be reduced relative to the
16-byte alignment scenario (see Table 3-5).
.
Table 3-5. Effect of Address Misalignment on Memcpy() Performance
Address Misalignment
Performance Impact
Source Buffer
The impact on Enhanced REP MOVSB and STOSB implementation versus 128bit AVX is similar.
Destination Buffer
The impact on Enhanced REP MOVSB and STOSB implementation can be 25%
degradation, while 128-bit AVX implementation of memcpy may degrade only
5%, relative to 16-byte aligned scenario.
Memcpy() implemented with Enhanced REP MOVSB and STOSB can benefit further from the 256-bit
SIMD integer data-path on the Haswell microarchitecture. see Section 12.16.3.
3.7.6.2
Memmove Considerations
When there is an overlap between the source and destination regions, software may need to use
memmove instead of memcpy to ensure correctness. It is possible to use REP MOVSB in conjunction with
the direction flag (DF) in a memmove() implementation to handle situations where the latter part of the
source region overlaps with the beginning of the destination region. However, setting the DF to force REP
MOVSB to copy bytes from high towards low addresses will experience significant performance degradation.
When using Enhanced REP MOVSB and STOSB to implement memmove function, one can detect the
above situation and handle first the rear chunks in the source region that will be written to as part of the
destination region, using REP MOVSB with the DF=0, to the non-overlapping region of the destination.
After the overlapping chunks in the rear section are copied, the rest of the source region can be
processed normally, also with DF=0.
3-70
GENERAL OPTIMIZATION GUIDELINES
3.7.6.3
Memset Considerations
The consideration of code size and throughput also applies for memset() implementations. For processors supporting Enhanced REP MOVSB and STOSB, using REP STOSB will again deliver more compact
code size and significantly better performance than the combination of STOSD+B technique described in
Section 3.7.5.
When the destination buffer is 16-byte aligned, memset() using Enhanced REP MOVSB and STOSB can
perform better than SIMD approaches. When the destination buffer is misaligned, memset() performance using Enhanced REP MOVSB and STOSB can degrade about 20% relative to aligned case, for
processors based on Intel microarchitecture code name Ivy Bridge. In contrast, SIMD implementation of
memset() will experience smaller degradation when the destination is misaligned.
Memset() implemented with Enhanced REP MOVSB and STOSB can benefit further from the 256-bit data
path on the Haswell microarchitecture. see Section 12.16.3.3.
3.8
FLOATING-POINT CONSIDERATIONS
When programming floating-point applications, it is best to start with a high-level programming
language such as C, C++, or Fortran. Many compilers perform floating-point scheduling and optimization
when it is possible. However in order to produce optimal code, the compiler may need some assistance.
3.8.1
Guidelines for Optimizing Floating-point Code
User/Source Coding Rule 13. (M impact, M generality) Enable the compiler’s use of SSE, SSE2
and more advanced SIMD instruction sets (e.g. AVX) with appropriate switches. Favor scalar SIMD code
generation to replace x87 code generation.
Follow this procedure to investigate the performance of your floating-point application:
•
•
•
•
•
•
Understand how the compiler handles floating-point code.
Look at the assembly dump and see what transforms are already performed on the program.
Study the loop nests in the application that dominate the execution time.
Determine why the compiler is not creating the fastest code.
See if there is a dependence that can be resolved.
Determine the problem area: bus bandwidth, cache locality, trace cache bandwidth, or instruction
latency. Focus on optimizing the problem area. For example, adding PREFETCH instructions will not
help if the bus is already saturated. If trace cache bandwidth is the problem, added prefetch µops
may degrade performance.
Also, in general, follow the general coding recommendations discussed in this chapter, including:
•
•
•
•
Blocking the cache.
Using prefetch.
Enabling vectorization.
Unrolling loops.
User/Source Coding Rule 14. (H impact, ML generality) Make sure your application stays in range
to avoid denormal values, underflows.
Out-of-range numbers cause very high overhead.
When converting floating-point values to 16-bit, 32-bit, or 64-bit integers using truncation, the instructions CVTTSS2SI and CVTTSD2SI are recommended over instructions that access x87 FPU stack. This
avoids changing the rounding mode.
3-71
GENERAL OPTIMIZATION GUIDELINES
User/Source Coding Rule 15. (M impact, ML generality) Usually, math libraries take advantage of
the transcendental instructions (for example, FSIN) when evaluating elementary functions. If there is
no critical need to evaluate the transcendental functions using the extended precision of 80 bits,
applications should consider an alternate, software-based approach, such as a look-up-table-based
algorithm using interpolation techniques. It is possible to improve transcendental performance with
these techniques by choosing the desired numeric precision and the size of the look-up table, and by
taking advantage of the parallelism of the SSE and the SSE2 instructions.
3.8.2
Microarchitecture Specific Considerations
3.8.2.1
Long-Latency FP Instructions
In the Haswell microarchitecture, long-latency floating-point instructions for division, square root operations have continued the improvements from the Ivy Bridge microarchitecture with pipe-lined hardware
implementation. These improvement will benefit existing code transparently.
3.8.2.2
Miscellaneous Instructions
In the Haswell microarchitecture, SIMD floating-point compare and set flag instructions (COMISD/SS,
UCOMISD/SS) is a one micro-op implementation for the register/register flavor of these instructions. The
latency is increased slightly to 3 cycles.
The ROUNDPD/SD instructions (both AVX and SSE4.1) are implemented as two micro-ops with latency
increased to 6 cycles. This can have a measurable impact to math library functions using these instructions to polynomial evaluation of exponentiation.
3.8.3
Floating-point Modes and Exceptions
When working with floating-point numbers, high-speed microprocessors frequently must deal with situations that need special handling in hardware or code.
3.8.3.1
Floating-point Exceptions
The most frequent cause of performance degradation is the use of masked floating-point exception
conditions such as:
•
•
•
Arithmetic overflow.
Arithmetic underflow.
Denormalized operand.
Refer to Chapter 4 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1 for definitions of overflow, underflow and denormal exceptions.
Denormalized floating-point numbers impact performance in two ways:
•
•
Directly when are used as operands.
Indirectly when are produced as a result of an underflow situation.
If a floating-point application never underflows, the denormals can only come from floating-point
constants.
User/Source Coding Rule 16. (H impact, ML generality) Denormalized floating-point constants
should be avoided as much as possible.
Denormal and arithmetic underflow exceptions can occur during the execution of x87 instructions or
SSE/SSE2/SSE3 instructions. Processors based on Intel NetBurst microarchitecture handle these exceptions more efficiently when executing SSE/SSE2/SSE3 instructions and when speed is more important
than complying with the IEEE standard. The following paragraphs give recommendations on how to optimize your code to reduce performance degradations related to floating-point exceptions.
3-72
GENERAL OPTIMIZATION GUIDELINES
3.8.3.2
Dealing with floating-point exceptions in x87 FPU code
Every special situation listed in Section 3.8.3.1, “Floating-point Exceptions,” is costly in terms of performance. For that reason, x87 FPU code should be written to avoid these situations.
There are basically three ways to reduce the impact of overflow/underflow situations with x87 FPU code:
•
Choose floating-point data types that are large enough to accommodate results without generating
arithmetic overflow and underflow exceptions.
•
Scale the range of operands/results to reduce as much as possible the number of arithmetic
overflow/underflow situations.
•
Keep intermediate results on the x87 FPU register stack until the final results have been computed
and stored in memory. Overflow or underflow is less likely to happen when intermediate results are
kept in the x87 FPU stack (this is because data on the stack is stored in double extended-precision
format and overflow/underflow conditions are detected accordingly).
•
Denormalized floating-point constants (which are read-only, and hence never change) should be
avoided and replaced, if possible, with zeros of the same sign.
3.8.3.3
Floating-point Exceptions in SSE/SSE2/SSE3 Code
Most special situations that involve masked floating-point exceptions are handled efficiently in hardware.
When a masked overflow exception occurs while executing SSE/SSE2/SSE3 code, processor hardware
can handles it without performance penalty.
Underflow exceptions and denormalized source operands are usually treated according to the IEEE 754
specification, but this can incur significant performance delay. If a programmer is willing to trade pure
IEEE 754 compliance for speed, two non-IEEE 754 compliant modes are provided to speed situations
where underflows and input are frequent: FTZ mode and DAZ mode.
When the FTZ mode is enabled, an underflow result is automatically converted to a zero with the correct
sign. Although this behavior is not compliant with IEEE 754, it is provided for use in applications where
performance is more important than IEEE 754 compliance. Since denormal results are not produced
when the FTZ mode is enabled, the only denormal floating-point numbers that can be encountered in FTZ
mode are the ones specified as constants (read only).
The DAZ mode is provided to handle denormal source operands efficiently when running a SIMD floatingpoint application. When the DAZ mode is enabled, input denormals are treated as zeros with the same
sign. Enabling the DAZ mode is the way to deal with denormal floating-point constants when performance is the objective.
If departing from the IEEE 754 specification is acceptable and performance is critical, run
SSE/SSE2/SSE3 applications with FTZ and DAZ modes enabled.
NOTE
The DAZ mode is available with both the SSE and SSE2 extensions, although the speed
improvement expected from this mode is fully realized only in SSE code.
3.8.4
Floating-point Modes
For x87 code, using the FLDCW instruction to change floating modes can be an expensive operation in
many cases.
Recent processor generations provide hardware optimization for FLDCW that allows programmers to
alternate between two constant values efficiently. For the FLDCW optimization to be effective, the two
constant FCW values are only allowed to differ on the following 5 bits in the FCW:
FCW[8-9]
; Precision control
FCW[10-11] ; Rounding control
FCW[12]
; Infinity control
3-73
GENERAL OPTIMIZATION GUIDELINES
If programmers need to modify other bits (for example: mask bits) in the FCW, the FLDCW instruction is
still an expensive operation.
In situations where an application cycles between three (or more) constant values, FLDCW optimization
does not apply, and the performance degradation occurs for each FLDCW instruction.
One solution to this problem is to choose two constant FCW values, take advantage of the optimization of
the FLDCW instruction to alternate between only these two constant FCW values, and devise some
means to accomplish the task that requires the 3rd FCW value without actually changing the FCW to a
third constant value. An alternative solution is to structure the code so that, for periods of time, the application alternates between only two constant FCW values. When the application later alternates between
a pair of different FCW values, the performance degradation occurs only during the transition.
It is expected that SIMD applications are unlikely to alternate between FTZ and DAZ mode values.
Consequently, the SIMD control word does not have the short latencies that the floating-point control
register does. A read of the MXCSR register has a fairly long latency, and a write to the register is a serializing instruction.
There is no separate control word for single and double precision; both use the same modes. Notably,
this applies to both FTZ and DAZ modes.
Assembly/Compiler Coding Rule 59. (H impact, M generality) Minimize changes to bits 8-12 of
the floating-point control word. Changes for more than two values (each value being a combination of
the following bits: precision, rounding and infinity control, and the rest of bits in FCW) leads to delays
that are on the order of the pipeline depth.
3.8.4.1
Rounding Mode
Many libraries provide float-to-integer library routines that convert floating-point values to integer. Many
of these libraries conform to ANSI C coding standards which state that the rounding mode should be
truncation. With the Pentium 4 processor, one can use the CVTTSD2SI and CVTTSS2SI instructions to
convert operands with truncation without ever needing to change rounding modes. The cost savings of
using these instructions over the methods below is enough to justify using SSE and SSE2 wherever
possible when truncation is involved.
For x87 floating-point, the FIST instruction uses the rounding mode represented in the floating-point
control word (FCW). The rounding mode is generally “round to nearest”, so many compiler writers implement a change in the rounding mode in the processor in order to conform to the C and FORTRAN standards. This implementation requires changing the control word on the processor using the FLDCW
instruction. For a change in the rounding, precision, and infinity bits, use the FSTCW instruction to store
the floating-point control word. Then use the FLDCW instruction to change the rounding mode to truncation.
In a typical code sequence that changes the rounding mode in the FCW, a FSTCW instruction is usually
followed by a load operation. The load operation from memory should be a 16-bit operand to prevent
store-forwarding problem. If the load operation on the previously-stored FCW word involves either an 8bit or a 32-bit operand, this will cause a store-forwarding problem due to mismatch of the size of the data
between the store operation and the load operation.
To avoid store-forwarding problems, make sure that the write and read to the FCW are both 16-bit operations.
If there is more than one change to the rounding, precision, and infinity bits, and the rounding mode is
not important to the result, use the algorithm in Example 3-58 to avoid synchronization issues, the overhead of the FLDCW instruction, and having to change the rounding mode. Note that the example suffers
3-74
GENERAL OPTIMIZATION GUIDELINES
from a store-forwarding problem which will lead to a performance penalty. However, its performance is
still better than changing the rounding, precision, and infinity bits among more than two values.
Example 3-58. Algorithm to Avoid Changing Rounding Mode
_fto132proc
lea
ecx, [esp-8]
sub
esp, 16
and
ecx, -8
fld
st(0)
fistp
fild
mov
mov
test
je
; Allocate frame
; Align pointer on boundary of 8
; Duplicate FPU stack top
qword ptr[ecx]
qword ptr[ecx]
edx, [ecx+4]
; High DWORD of integer
eax, [ecx]
; Low DWIRD of integer
eax, eax
integer_QnaN_or_zero
arg_is_not_integer_QnaN:
fsubp
st(1), st
test
edx, edx
jns
positive
fstp
dword ptr[ecx]
mov
ecx, [ecx]
add
esp, 16
xor
ecx, 80000000h
add
ecx,7fffffffh
adc
eax,0
ret
positive:
; TOS=d-round(d), { st(1) = st(1)-st & pop ST}
; What’s sign of integer
; Number is negative
; Result of subtraction
; DWORD of diff(single-precision)
; If diff<0 then decrement integer
; INC EAX (add CARRY flag)
positive:
fstp
dword ptr[ecx]
; 17-18 result of subtraction
mov
ecx, [ecx]
; DWORD of diff(single precision)
add
esp, 16
add
ecx, 7fffffffh
; If diff<0 then decrement integer
sbb
eax, 0
; DEC EAX (subtract CARRY flag)
ret
integer_QnaN_or_zero:
test
edx, 7fffffffh
jnz
arg_is_not_integer_QnaN
add esp, 16
ret
Assembly/Compiler Coding Rule 60. (H impact, L generality) Minimize the number of changes to
the rounding mode. Do not use changes in the rounding mode to implement the floor and ceiling
functions if this involves a total of more than two values of the set of rounding, precision, and infinity
bits.
3-75
GENERAL OPTIMIZATION GUIDELINES
3.8.4.2
Precision
If single precision is adequate, use it instead of double precision. This is true because:
•
Single precision operations allow the use of longer SIMD vectors, since more single precision data
elements can fit in a register.
•
If the precision control (PC) field in the x87 FPU control word is set to single precision, the floatingpoint divider can complete a single-precision computation much faster than either a double-precision
computation or an extended double-precision computation. If the PC field is set to double precision,
this will enable those x87 FPU operations on double-precision data to complete faster than extended
double-precision computation. These characteristics affect computations including floating-point
divide and square root.
Assembly/Compiler Coding Rule 61. (H impact, L generality) Minimize the number of changes to
the precision mode.
3.8.5
x87 vs. Scalar SIMD Floating-point Trade-offs
There are a number of differences between x87 floating-point code and scalar floating-point code (using
SSE and SSE2). The following differences should drive decisions about which registers and instructions to
use:
•
When an input operand for a SIMD floating-point instruction contains values that are less than the
representable range of the data type, a denormal exception occurs. This causes a significant
performance penalty. An SIMD floating-point operation has a flush-to-zero mode in which the results
will not underflow. Therefore subsequent computation will not face the performance penalty of
handling denormal input operands. For example, in the case of 3D applications with low lighting
levels, using flush-to-zero mode can improve performance by as much as 50% for applications with
large numbers of underflows.
•
Scalar floating-point SIMD instructions have lower latencies than equivalent x87 instructions. Scalar
SIMD floating-point multiply instruction may be pipelined, while x87 multiply instruction is not.
•
Although x87 supports transcendental instructions, software library implementation of transcendental function can be faster in many cases.
•
x87 supports 80-bit precision, double extended floating-point. SSE support a maximum of 32-bit
precision. SSE2 supports a maximum of 64-bit precision.
•
•
Scalar floating-point registers may be accessed directly, avoiding FXCH and top-of-stack restrictions.
The cost of converting from floating-point to integer with truncation is significantly lower with
Streaming SIMD Extensions 2 and Streaming SIMD Extensions in the processors based on Intel
NetBurst microarchitecture than with either changes to the rounding mode or the sequence
prescribed in the Example 3-58.
Assembly/Compiler Coding Rule 62. (M impact, M generality) Use Streaming SIMD Extensions 2
or Streaming SIMD Extensions unless you need an x87 feature. Most SSE2 arithmetic operations have
shorter latency then their X87 counterpart and they eliminate the overhead associated with the
management of the X87 register stack.
3.8.5.1
Scalar SSE/SSE2
In code sequences that have conversions from floating-point to integer, divide single-precision instructions, or any precision change, x87 code generation from a compiler typically writes data to memory in
single-precision and reads it again in order to reduce precision. Using SSE/SSE2 scalar code instead of
x87 code can generate a large performance benefit using Intel NetBurst microarchitecture and a modest
benefit on Intel Core Solo and Intel Core Duo processors.
3-76
GENERAL OPTIMIZATION GUIDELINES
Recommendation: Use the compiler switch to generate scalar floating-point code using XMM rather
than x87 code.
When working with scalar SSE/SSE2 code, pay attention to the need for clearing the content of unused
slots in an XMM register and the associated performance impact. For example, loading data from
memory with MOVSS or MOVSD causes an extra micro-op for zeroing the upper part of the XMM register.
3.8.5.2
Transcendental Functions
If an application needs to emulate math functions in software for performance or other reasons (see
Section 3.8.1, “Guidelines for Optimizing Floating-point Code”), it may be worthwhile to inline math
library calls because the CALL and the prologue/epilogue involved with such calls can significantly affect
the latency of operations.
3.9
MAXIMIZING PCIE PERFORMANCE
PCIe performance can be dramatically impacted by the size and alignment of upstream reads and writes
(read and write transactions issued from a PCIe agent to the host’s memory). As a general rule, the best
performance, in terms of both bandwidth and latency, is obtained by aligning the start addresses of
upstream reads and writes on 64-byte boundaries and ensuring that the request size is a multiple of 64bytes, with modest further increases in bandwidth when larger multiples (128, 192, 256 bytes) are
employed. In particular, a partial write will cause a delay for the following request (read or write).
A second rule is to avoid multiple concurrently outstanding accesses to a single cache line. This can result
in a conflict which in turn can cause serialization of accesses that would otherwise be pipelined, resulting
in higher latency and/or lower bandwidth. Patterns that violate this rule include sequential accesses
(reads or writes) that are not a multiple of 64-bytes, as well as explicit accesses to the same cache line
address. Overlapping requests—those with different start addresses but with request lengths that result
in overlap of the requests—can have the same effect. For example, a 96-byte read of address
0x00000200 followed by a 64-byte read of address 0x00000240 will cause a conflict—and a likely delay—
for the second read.
Upstream writes that are a multiple of 64-byte but are non-aligned will have the performance of a series
of partial and full sequential writes. For example, a write of length 128-byte to address 0x00000070 will
perform similarly to 3 sequential writes of lengths 16, 64, and 48 to addresses 0x00000070,
0x00000080, and 0x00000100, respectively.
For PCIe cards implementing multi-function devices, such as dual or quad port network interface cards
(NICs) or dual-GPU graphics cards, it is important to note that non-optimal behavior by one of those
devices can impact the bandwidth and/or latency observed by the other devices on that card. With
respect to the behavior described in this section, all traffic on a given PCIe port is treated as if it originated from a single device and function.
For the best PCIe bandwidth:
1.
Align start addresses of upstream reads and writes on 64-byte boundaries.
2.
Use read and write requests that are a multiple of 64-bytes.
3.
Eliminate or avoid sequential and random partial line upstream writes.
4.
Eliminate or avoid conflicting upstream reads, including sequential partial line reads.
Techniques for avoiding performance pitfalls include cache line aligning all descriptors and data buffers,
padding descriptors that are written upstream to 64-byte alignment, buffering incoming data to achieve
larger upstream write payloads, allocating data structures intended for sequential reading by the PCIe
device in such a way as to enable use of (multiple of) 64-byte reads. The negative impact of unoptimized
reads and writes depends on the specific workload and the microarchitecture on which the product is
based.
3-77
GENERAL OPTIMIZATION GUIDELINES
3.9.1
Optimizing PCIe Performance for Accesses Toward Coherent Memory and
Toward MMIO Regions (P2P)
In order to maximize performance for PCIe devices in the processors listed in Table 3-6 below, the software should determine whether the accesses are toward coherent memory (system memory) or toward
MMIO regions (P2P access to other devices). If the access is toward MMIO region, then software can
command HW to set the RO bit in the TLP header, as this would allow hardware to achieve maximum
throughput for these types of accesses. For accesses toward coherent memory, software can command
HW to clear the RO bit in the TLP header (no RO), as this would allow hardware to achieve maximum
throughput for these types of accesses.
.
Processor
Table 3-6. Intel Processor CPU RP Device IDs for Processors Optimizing PCIe Performance
CPU RP Device IDs
Intel Xeon processors based on Broadwell microarchitecture
6F01H-6F0EH
Intel Xeon processors based on Haswell microarchitecture
2F01H-2F0EH
3-78
CHAPTER 4
CODING FOR SIMD ARCHITECTURES
Processors based on Intel Core microarchitecture supports MMX, SSE, SSE2, SSE3, and SSSE3. Processors based on Enhanced Intel Core microarchitecture supports MMX, SSE, SSE2, SSE3, SSSE3 and
SSE4.1. Processors based on Intel microarchitecture code name Nehalem supports MMX, SSE, SSE2,
SSE3, SSSE3, SSE4.1 and SSE4.2. Processors based on Intel microarchitecture code name Westmere
supports MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AESNI. Processors based on Intel
microarchitecture code name Sandy Bridge supports MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
AESNI, PCLMULQDQ and Intel AVX.
Intel Pentium 4, Intel Xeon and Pentium M processors include support for SSE2, SSE, and MMX technology. SSE3 were introduced with the Pentium 4 processor supporting Hyper-Threading Technology at
90 nm technology. Intel Core Solo and Intel Core Duo processors support SSE3/SSE2/SSE, and MMX.
Single-instruction, multiple-data (SIMD) technologies enable the development of advanced multimedia,
signal processing, and modeling applications.
Single-instruction, multiple-data techniques can be applied to text/string processing, lexing and parser
applications. This is covered in Chapter 11, “SSE4.2 and SIMD Programming For TextProcessing/Lexing/Parsing”. Techniques for optimizing AESNI are discussed in Section 5.10.
To take advantage of the performance opportunities presented by these capabilities, do the following:
•
•
Ensure that the processor supports MMX technology, SSE, SSE2, SSE3, SSSE3 and SSE4.1.
•
•
•
Employ the optimization and scheduling strategies described in this book.
Ensure that the operating system supports MMX technology and SSE (OS support for SSE2, SSE3
and SSSE3 is the same as OS support for SSE).
Use stack and data alignment techniques to keep data properly aligned for efficient memory use.
Utilize the cacheability instructions offered by SSE and SSE2, where appropriate.
4.1
CHECKING FOR PROCESSOR SUPPORT OF SIMD TECHNOLOGIES
This section shows how to check whether a processor supports MMX technology, SSE, SSE2, SSE3,
SSSE3, and SSE4.1.
SIMD technology can be included in your application in three ways:
1. Check for the SIMD technology during installation. If the desired SIMD technology is available, the
appropriate DLLs can be installed.
2. Check for the SIMD technology during program execution and install the proper DLLs at runtime. This
is effective for programs that may be executed on different machines.
3. Create a “fat” binary that includes multiple versions of routines; versions that use SIMD technology
and versions that do not. Check for SIMD technology during program execution and run the
appropriate versions of the routines. This is especially effective for programs that may be executed
on different machines.
CODING FOR SIMD ARCHITECTURES
4.1.1
Checking for MMX Technology Support
If MMX technology is available, then CPUID.01H:EDX[BIT 23] = 1. Use the code segment in Example 4-1
to test for MMX technology.
Example 4-1. Identification of MMX Technology with CPUID
…identify existence of cpuid instruction
…
;
…
; Identify signature is genuine Intel
…
;
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test edx, 00800000h
; Is MMX technology bit (bit 23) in feature flags equal to 1
jnz
Found
For more information on CPUID see, Intel® Processor Identification with CPUID Instruction, order
number 241618.
4.1.2
Checking for Streaming SIMD Extensions Support
Checking for processor support of Streaming SIMD Extensions (SSE) on your processor is similar to
checking for MMX technology. However, operating system (OS) must provide support for SSE states save
and restore on context switches to ensure consistent application behavior when using SSE instructions.
To check whether your system supports SSE, follow these steps:
1. Check that your processor supports the CPUID instruction.
2. Check the feature bits of CPUID for SSE existence.
Example 4-2 shows how to find the SSE feature bit (bit 25) in CPUID feature flags.
Example 4-2. Identification of SSE with CPUID
…Identify existence of cpuid instruction
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H cpuid instruction
test EDX, 002000000h
; Bit 25 in feature flags equal to 1
jnz
Found
4.1.3
Checking for Streaming SIMD Extensions 2 Support
Checking for support of SSE2 is like checking for SSE support. The OS requirements for SSE2 Support are
the same as the OS requirements for SSE.
To check whether your system supports SSE2, follow these steps:
1. Check that your processor has the CPUID instruction.
2. Check the feature bits of CPUID for SSE2 technology existence.
4-2
CODING FOR SIMD ARCHITECTURES
Example 4-3 shows how to find the SSE2 feature bit (bit 26) in the CPUID feature flags.
Example 4-3. Identification of SSE2 with cpuid
…identify existence of cpuid instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test EDX, 004000000h
; Bit 26 in feature flags equal to 1
jnz
Found
4.1.4
Checking for Streaming SIMD Extensions 3 Support
SSE3 includes 13 instructions, 11 of those are suited for SIMD or x87 style programming. Checking for
support of SSE3 instructions is similar to checking for SSE support. The OS requirements for SSE3
Support are the same as the requirements for SSE.
To check whether your system supports the x87 and SIMD instructions of SSE3, follow these steps:
1. Check that your processor has the CPUID instruction.
2. Check the ECX feature bit 0 of CPUID for SSE3 technology existence.
Example 4-4 shows how to find the SSE3 feature bit (bit 0 of ECX) in the CPUID feature flags.
Example 4-4. Identification of SSE3 with CPUID
…identify existence of cpuid instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 000000001h
; Bit 0 in feature flags equal to 1
jnz
Found
Software must check for support of MONITOR and MWAIT before attempting to use MONITOR and
MWAIT.Detecting the availability of MONITOR and MWAIT can be done using a code sequence similar to
Example 4-4. The availability of MONITOR and MWAIT is indicated by bit 3 of the returned value in ECX.
4.1.5
Checking for Supplemental Streaming SIMD Extensions 3 Support
Checking for support of SSSE3 is similar to checking for SSE support. The OS requirements for SSSE3
support are the same as the requirements for SSE.
To check whether your system supports SSSE3, follow these steps:
1. Check that your processor has the CPUID instruction.
2. Check the feature bits of CPUID for SSSE3 technology existence.
Example 4-5 shows how to find the SSSE3 feature bit in the CPUID feature flags.
Example 4-5. Identification of SSSE3 with cpuid
…Identify existence of CPUID instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 000000200h
; ECX bit 9
jnz
Found
4-3
CODING FOR SIMD ARCHITECTURES
4.1.6
Checking for SSE4.1 Support
Checking for support of SSE4.1 is similar to checking for SSE support. The OS requirements for SSE4.1
support are the same as the requirements for SSE.
To check whether your system supports SSE4.1, follow these steps:
1. Check that your processor has the CPUID instruction.
2. Check the feature bit of CPUID for SSE4.1.
Example 4-6 shows how to find the SSE4.1 feature bit in the CPUID feature flags.
Example 4-6. Identification of SSE4.1 with cpuid
…Identify existence of CPUID instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 000080000h
; ECX bit 19
jnz
Found
4.1.7
Checking for SSE4.2 Support
Checking for support of SSE4.2 is similar to checking for SSE support. The OS requirements for SSE4.2
support are the same as the requirements for SSE.
To check whether your system supports SSE4.2, follow these steps:
1. Check that your processor has the CPUID instruction.
2. Check the feature bit of CPUID for SSE4.2.
Example 4-7 shows how to find the SSE4.2 feature bit in the CPUID feature flags.
Example 4-7. Identification of SSE4.2 with cpuid
…Identify existence of CPUID instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 000100000h
; ECX bit 20
jnz
Found
4.1.8
DetectiON of PCLMULQDQ and AESNI Instructions
Before an application attempts to use the following AESNI instructions: AESDEC/AESDECLAST/AESENC/AESENCLAST/AESIMC/AESKEYGENASSIST, it must check that the processor supports
the AESNI extensions. AESNI extensions is supported if CPUID.01H:ECX.AESNI[bit 25] = 1.
Prior to using PCLMULQDQ instruction, application must check if CPUID.01H:ECX.PCLMULQDQ[bit 1] =
1.
4-4
CODING FOR SIMD ARCHITECTURES
Operating systems that support handling SSE state will also support applications that use AESNI extensions and PCLMULQDQ instruction. This is the same requirement for SSE2, SSE3, SSSE3, and SSE4.
Example 4-8. Detection of AESNI Instructions
…Identify existence of CPUID instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 002000000h
; ECX bit 25
jnz
Found
Example 4-9. Detection of PCLMULQDQ Instruction
…Identify existence of CPUID instruction
…
; Identify signature is genuine intel
mov eax, 1
; Request for feature flags
cpuid
; 0FH, 0A2H CPUID instruction
test ECX, 000000002h
; ECX bit 1
jnz
Found
4.1.9
Detection of AVX Instructions
Intel AVX operates on the 256-bit YMM register state. Application detection of new instruction extensions
operating on the YMM state follows the general procedural flow in Figure 4-1.
Prior to using AVX, the application must identify that the operating system supports the XGETBV instruction, the YMM register state, in addition to processor’s support for YMM state management using
XSAVE/XRSTOR and AVX instructions. The following simplified sequence accomplishes both and is
strongly recommended.
1) Detect CPUID.1:ECX.OSXSAVE[bit 27] = 1 (XGETBV enabled for application use1)
2) Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = ‘11b’ (XMM state and YMM state are
enabled by OS).
3) Detect CPUID.1:ECX.AVX[bit 28] = 1 (AVX instructions supported).
Note: Step 3 can be done in any order relative to 1 and 2.
1. If CPUID.01H:ECX.OSXSAVE reports 1, it also indirectly implies the processor supports XSAVE, XRSTOR, XGETBV, processor extended state bit vector XFEATURE_ENALBED_MASK register. Thus an application may streamline the checking
of CPUID feature flags for XSAVE and OSXSAVE. XSETBV is a privileged instruction.
4-5
CODING FOR SIMD ARCHITECTURES
Check feature flag
CPUID.1H:ECX.OXSAVE = 1?
Yes
OS provides processor
extended state management
Implied HW support for
XSAVE, XRSTOR, XGETBV, XFEATURE_ENABLED_MASK
Check enabled state in
XCR0 via XGETBV
State
enabled
Check feature flag
for Instruction set
ok to use
Instructions
Figure 4-1. General Procedural Flow of Application Detection of AVX
The following pseudocode illustrates this recommended application AVX detection process:
Example 4-10. Detection of AVX Instruction
INT supports_AVX()
{ mov
eax, 1
cpuid
and
ecx, 018000000H
cmp
ecx, 018000000H; check both OSXSAVE and AVX feature flags
jne
not_supported
; processor supports AVX instructions and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
Note: It is unwise for an application to rely exclusively on CPUID.1:ECX.AVX[bit 28] or at all on
CPUID.1:ECX.XSAVE[bit 26]: These indicate hardware support but not operating system support. If YMM
state management is not enabled by an operating systems, AVX instructions will #UD regardless of
CPUID.1:ECX.AVX[bit 28]. “CPUID.1:ECX.XSAVE[bit 26] = 1” does not guarantee the OS actually uses
the XSAVE process for state management.
4-6
CODING FOR SIMD ARCHITECTURES
4.1.10
Detection of VEX-Encoded AES and VPCLMULQDQ
VAESDEC/VAESDECLAST/VAESENC/VAESENCLAST/VAESIMC/VAESKEYGENASSIST instructions operate
on YMM states. The detection sequence must combine checking for CPUID.1:ECX.AES[bit 25] = 1 and
the sequence for detection application support for AVX.
Example 4-11. Detection of VEX-Encoded AESNI Instructions
INT supports_VAESNI()
{ mov
eax, 1
cpuid
and
ecx, 01A000000H
cmp
ecx, 01A000000H; check OSXSAVE AVX and AESNI feature flags
jne
not_supported
; processor supports AVX and VEX-encoded AESNI and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
Similarly, the detection sequence for VPCLMULQDQ must combine checking for
CPUID.1:ECX.PCLMULQDQ[bit 1] = 1 and the sequence for detection application support for AVX.
This is shown in the pseudocode:
Example 4-12. Detection of VEX-Encoded AESNI Instructions
INT supports_VPCLMULQDQ)
{ mov
eax, 1
cpuid
and
ecx, 018000002H
cmp
ecx, 018000002H; check OSXSAVE AVX and PCLMULQDQ feature flags
jne
not_supported
; processor supports AVX and VEX-encoded PCLMULQDQ and XGETBV is enabled by OS
mov
ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV
; result in EDX:EAX
and
eax, 06H
cmp
eax, 06H; check OS has enabled both XMM and YMM state support
jne
not_supported
mov
eax, 1
jmp
done
NOT_SUPPORTED:
mov
eax, 0
done:
4.1.11
Detection of F16C Instructions
Application using float 16 instruction must follow a detection sequence similar to AVX to ensure:
•
The OS has enabled YMM state management support.
4-7
CODING FOR SIMD ARCHITECTURES
•
The processor support AVX as indicated by the CPUID feature flag, i.e. CPUID.01H:ECX.AVX[bit 28]
= 1.
•
The processor support 16-bit floating-point conversion instructions via a CPUID feature flag
(CPUID.01H:ECX.F16C[bit 29] = 1).
Application detection of Float-16 conversion instructions follow the general procedural flow in Figure 4-2.
Check feature flag
CPUID.1H:ECX.OXSAVE = 1?
Yes
OS provides processor
extended state management
Implied HW support for
XSAVE, XRSTOR, XGETBV, XFEATURE_ENABLED_MASK
Check enabled YMM state in
XCR0 via XGETBV
Check feature flags
State
enabled
for AVX and F16C
ok to use
Instructions
Figure 4-2. General Procedural Flow of Application Detection of Float-16
---------------------------------------------------------------------------------------INT supports_f16c()
{
; result in eax
mov eax, 1
cpuid
and ecx, 038000000H
cmp ecx, 038000000H; check OSXSAVE, AVX, F16C feature flags
jne not_supported
; processor supports AVX,F16C instructions and XGETBV is enabled by OS
mov ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
done:
}
-------------------------------------------------------------------------------
4.1.12
Detection of FMA
Hardware support for FMA is indicated by CPUID.1:ECX.FMA[bit 12]=1.
4-8
CODING FOR SIMD ARCHITECTURES
Application Software must identify that hardware supports AVX, after that it must also detect support for
FMA by CPUID.1:ECX.FMA[bit 12]. The recommended pseudocode sequence for detection of FMA is:
---------------------------------------------------------------------------------------INT supports_fma()
{
; result in eax
mov eax, 1
cpuid
and ecx, 018001000H
cmp ecx, 018001000H; check OSXSAVE, AVX, FMA feature flags
jne not_supported
; processor supports AVX,FMA instructions and XGETBV is enabled by OS
mov ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
done:
}
-------------------------------------------------------------------------------
4.1.13
Detection of AVX2
Hardware support for AVX2 is indicated by CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]=1.
Application Software must identify that hardware supports AVX, after that it must also detect support for
AVX2 by checking CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]. The recommended pseudocode
sequence for detection of AVX2 is:
---------------------------------------------------------------------------------------INT supports_avx2()
{
; result in eax
mov eax, 1
cpuid
and ecx, 018000000H
cmp ecx, 018000000H; check both OSXSAVE and AVX feature flags
jne not_supported
; processor supports AVX instructions and XGETBV is enabled by OS
mov eax, 7
mov ecx, 0
cpuid
and ebx, 20H
cmp ebx, 20H; check AVX2 feature flags
jne not_supported
4-9
CODING FOR SIMD ARCHITECTURES
mov ecx, 0; specify 0 for XFEATURE_ENABLED_MASK register
XGETBV; result in EDX:EAX
and eax, 06H
cmp eax, 06H; check OS has enabled both XMM and YMM state support
jne not_supported
mov eax, 1
jmp done
NOT_SUPPORTED:
mov eax, 0
done:
}
-------------------------------------------------------------------------------
4.2
CONSIDERATIONS FOR CODE CONVERSION TO SIMD
PROGRAMMING
The VTune Performance Enhancement Environment CD provides tools to aid in the evaluation and tuning.
Before implementing them, you need answers to the following questions:
1. Will the current code benefit by using MMX technology, Streaming SIMD Extensions, Streaming
SIMD Extensions 2, Streaming SIMD Extensions 3, or Supplemental Streaming SIMD Extensions 3?
2. Is this code integer or floating-point?
3. What integer word size or floating-point precision is needed?
4. What coding techniques should I use?
5. What guidelines do I need to follow?
6. How should I arrange and align the datatypes?
Figure 4-3 provides a flowchart for the process of converting code to MMX technology, SSE, SSE2, SSE3,
or SSSE3.
4-10
CODING FOR SIMD ARCHITECTURES
Identify Hot Spots in Code
No
Code benefits
from SIMD
Yes
Floating Point
W hy FP?
Integer or
floating-point?
Integer
Perform ance
If possible, re-arrange data
for SIMD efficiency
Range or
Precision
Align data structures
Can convert
to Integer?
Yes
Convert to code to use
SIMD Technologies
Change to use
SIMD Integer
Follow general coding
guidelines and SIMD
coding guidelines
No
Can convert to
Single-precision?
Yes
Change to use
Single Precision
Use m em ory optim izations
and prefetch if appropriate
Schedule instructions to
optim ize perform ance
No
STOP
OM15156
Figure 4-3. Converting to Streaming SIMD Extensions Chart
To use any of the SIMD technologies optimally, you must evaluate the following situations in your code:
•
•
•
•
•
•
•
Fragments that are computationally intensive.
Fragments that are executed often enough to have an impact on performance.
Fragments that with little data-dependent control flow.
Fragments that require floating-point computations.
Fragments that can benefit from moving data 16 bytes at a time.
Fragments of computation that can coded using fewer instructions.
Fragments that require help in using the cache hierarchy efficiently.
4-11
CODING FOR SIMD ARCHITECTURES
4.2.1
Identifying Hot Spots
To optimize performance, use the VTune Performance Analyzer to find sections of code that occupy most
of the computation time. Such sections are called the hotspots. See Appendix A, “Application Performance Tools.”
The VTune analyzer provides a hotspots view of a specific module to help you identify sections in your
code that take the most CPU time and that have potential performance problems. The hotspots view
helps you identify sections in your code that take the most CPU time and that have potential performance
problems.
The VTune analyzer enables you to change the view to show hotspots by memory location, functions,
classes, or source files. You can double-click on a hotspot and open the source or assembly view for the
hotspot and see more detailed information about the performance of each instruction in the hotspot.
The VTune analyzer offers focused analysis and performance data at all levels of your source code and
can also provide advice at the assembly language level. The code coach analyzes and identifies opportunities for better performance of C/C++, Fortran and Java* programs, and suggests specific optimizations. Where appropriate, the coach displays pseudo-code to suggest the use of highly optimized
intrinsics and functions in the Intel® Performance Library Suite. Because VTune analyzer is designed
specifically for Intel architecture (IA)-based processors, including the Pentium 4 processor, it can offer
detailed approaches to working with IA. See Appendix A.1.1, “Recommended Optimization Settings for
Intel® 64 and IA-32 Processors,” for details.
4.2.2
Determine If Code Benefits by Conversion to SIMD Execution
Identifying code that benefits by using SIMD technologies can be time-consuming and difficult. Likely
candidates for conversion are applications that are highly computation intensive, such as the following:
•
•
•
•
•
•
•
•
•
•
•
Speech compression algorithms and filters.
Speech recognition algorithms.
Video display and capture routines.
Rendering routines.
3D graphics (geometry).
Image and video processing algorithms.
Spatial (3D) audio.
Physical modeling (graphics, CAD).
Workstation applications.
Encryption algorithms.
Complex arithmetics.
Generally, good candidate code is code that contains small-sized repetitive loops that operate on sequential arrays of integers of 8, 16 or 32 bits, single-precision 32-bit floating-point data, double precision 64bit floating-point data (integer and floating-point data items should be sequential in memory). The repetitiveness of these loops incurs costly application processing time. However, these routines have potential
for increased performance when you convert them to use one of the SIMD technologies.
Once you identify your opportunities for using a SIMD technology, you must evaluate what should be
done to determine whether the current algorithm or a modified one will ensure the best performance.
4.3
CODING TECHNIQUES
The SIMD features of SSE3, SSE2, SSE, and MMX technology require new methods of coding algorithms.
One of them is vectorization. Vectorization is the process of transforming sequentially-executing, or
scalar, code into code that can execute in parallel, taking advantage of the SIMD architecture parallelism.
4-12
CODING FOR SIMD ARCHITECTURES
This section discusses the coding techniques available for an application to make use of the SIMD architecture.
To vectorize your code and thus take advantage of the SIMD architecture, do the following:
•
•
Determine if the memory accesses have dependencies that would prevent parallel execution.
•
Re-code the loop with the SIMD instructions.
“Strip-mine” the inner loop to reduce the iteration count by the length of the SIMD operations (for
example, four for single-precision floating-point SIMD, eight for 16-bit integer SIMD on the XMM
registers).
Each of these actions is discussed in detail in the subsequent sections of this chapter. These sections also
discuss enabling automatic vectorization using the Intel C++ Compiler.
4.3.1
Coding Methodologies
Software developers need to compare the performance improvement that can be obtained from
assembly code versus the cost of those improvements. Programming directly in assembly language for a
target platform may produce the required performance gain, however, assembly code is not portable
between processor architectures and is expensive to write and maintain.
Performance objectives can be met by taking advantage of the different SIMD technologies using highlevel languages as well as assembly. The new C/C++ language extensions designed specifically for
SSSE3, SSE3, SSE2, SSE, and MMX technology help make this possible.
Figure 4-4 illustrates the trade-offs involved in the performance of hand-coded assembly versus the ease
of programming and portability.
Performance
Assembly
Instrinsics
Automatic
Vectorization
C/C++/Fortran
Ease of Programming/Portability
Figure 4-4. Hand-Coded Assembly and High-Level Compiler Performance Trade-offs
The examples that follow illustrate the use of coding adjustments to enable the algorithm to benefit from
the SSE. The same techniques may be used for single-precision floating-point, double-precision floatingpoint, and integer data under SSSE3, SSE3, SSE2, SSE, and MMX technology.
4-13
CODING FOR SIMD ARCHITECTURES
As a basis for the usage model discussed in this section, consider a simple loop shown in Example 4-13.
Example 4-13. Simple Four-Iteration Loop
void add(float *a, float *b, float *c)
{
int i;
for (i = 0; i < 4; i++) {
c[i] = a[i] + b[i];
}
}
Note that the loop runs for only four iterations. This allows a simple replacement of the code with
Streaming SIMD Extensions.
For the optimal use of the Streaming SIMD Extensions that need data alignment on the 16-byte
boundary, all examples in this chapter assume that the arrays passed to the routine, A, B, C, are aligned
to 16-byte boundaries by a calling routine. For the methods to ensure this alignment, please refer to the
application notes for the Pentium 4 processor.
The sections that follow provide details on the coding methodologies: inlined assembly, intrinsics, C++
vector classes, and automatic vectorization.
4.3.1.1
Assembly
Key loops can be coded directly in assembly language using an assembler or by using inlined assembly
(C-asm) in C/C++ code. The Intel compiler or assembler recognize the new instructions and registers,
then directly generate the corresponding code. This model offers the opportunity for attaining greatest
performance, but this performance is not portable across the different processor architectures.
Example 4-14 shows the Streaming SIMD Extensions inlined assembly encoding.
Example 4-14. Streaming SIMD Extensions Using Inlined Assembly Encoding
void add(float *a, float *b, float *c)
{
__asm {
mov eax, a
mov edx, b
mov ecx, c
movaps xmm0, XMMWORD PTR [eax]
addps xmm0, XMMWORD PTR [edx]
movaps XMMWORD PTR [ecx], xmm0
}
}
4.3.1.2
Intrinsics
Intrinsics provide the access to the ISA functionality using C/C++ style coding instead of assembly
language. Intel has defined three sets of intrinsic functions that are implemented in the Intel C++
Compiler to support the MMX technology, Streaming SIMD Extensions and Streaming SIMD Extensions 2.
Four new C data types, representing 64-bit and 128-bit objects are used as the operands of these
intrinsic functions. __M64 is used for MMX integer SIMD, __M128 is used for single-precision floatingpoint SIMD, __M128I is used for Streaming SIMD Extensions 2 integer SIMD, and __M128D is used for
double precision floating-point SIMD. These types enable the programmer to choose the implementation
of an algorithm directly, while allowing the compiler to perform register allocation and instruction sched-
4-14
CODING FOR SIMD ARCHITECTURES
uling where possible. The intrinsics are portable among all Intel architecture-based processors supported
by a compiler.
The use of intrinsics allows you to obtain performance close to the levels achievable with assembly. The
cost of writing and maintaining programs with intrinsics is considerably less. For a detailed description of
the intrinsics and their use, refer to the Intel C++ Compiler documentation.
Example 4-15 shows the loop from Example 4-13 using intrinsics.
Example 4-15. Simple Four-Iteration Loop Coded with Intrinsics
#include <xmmintrin.h>
void add(float *a, float *b, float *c)
{
__m128 t0, t1;
t0 = _mm_load_ps(a);
t1 = _mm_load_ps(b);
t0 = _mm_add_ps(t0, t1);
_mm_store_ps(c, t0);
}
The intrinsics map one-to-one with actual Streaming SIMD Extensions assembly code. The
XMMINTRIN.H header file in which the prototypes for the intrinsics are defined is part of the Intel C++
Compiler included with the VTune Performance Enhancement Environment CD.
Intrinsics are also defined for the MMX technology ISA. These are based on the __m64 data type to
represent the contents of an mm register. You can specify values in bytes, short integers, 32-bit values,
or as a 64-bit object.
The intrinsic data types, however, are not a basic ANSI C data type, and therefore you must observe the
following usage restrictions:
•
Use intrinsic data types only on the left-hand side of an assignment as a return value or as a
parameter. You cannot use it with other arithmetic expressions (for example, “+”, “>>”).
•
Use intrinsic data type objects in aggregates, such as unions to access the byte elements and
structures; the address of an __M64 object may be also used.
•
Use intrinsic data type data only with the MMX technology intrinsics described in this guide.
For complete details of the hardware instructions, see the Intel Architecture MMX Technology
Programmer’s Reference Manual. For a description of data types, see the Intel® 64 and IA-32 Architectures Software Developer’s Manual.
4.3.1.3
Classes
A set of C++ classes has been defined and available in Intel C++ Compiler to provide both a higher-level
abstraction and more flexibility for programming with MMX technology, Streaming SIMD Extensions and
Streaming SIMD Extensions 2. These classes provide an easy-to-use and flexible interface to the intrinsic
functions, allowing developers to write more natural C++ code without worrying about which intrinsic or
assembly language instruction to use for a given operation. Since the intrinsic functions underlie the
implementation of these C++ classes, the performance of applications using this methodology can
approach that of one using the intrinsics. Further details on the use of these classes can be found in the
Intel C++ Class Libraries for SIMD Operations User’s Guide, order number 693500.
4-15
CODING FOR SIMD ARCHITECTURES
Example 4-16 shows the C++ code using a vector class library. The example assumes the arrays passed
to the routine are already aligned to 16-byte boundaries.
Example 4-16. C++ Code Using the Vector Classes
#include <fvec.h>
void add(float *a, float *b, float *c)
{
F32vec4 *av=(F32vec4 *) a;
F32vec4 *bv=(F32vec4 *) b;
F32vec4 *cv=(F32vec4 *) c;
*cv=*av + *bv;
}
Here, fvec.h is the class definition file and F32vec4 is the class representing an array of four floats. The
“+” and “=” operators are overloaded so that the actual Streaming SIMD Extensions implementation in
the previous example is abstracted out, or hidden, from the developer. Note how much more this resembles the original code, allowing for simpler and faster programming.
Again, the example is assuming the arrays, passed to the routine, are already aligned to 16-byte
boundary.
4.3.1.4
Automatic Vectorization
The Intel C++ Compiler provides an optimization mechanism by which loops, such as in Example 4-13
can be automatically vectorized, or converted into Streaming SIMD Extensions code. The compiler uses
similar techniques to those used by a programmer to identify whether a loop is suitable for conversion to
SIMD. This involves determining whether the following might prevent vectorization:
•
•
The layout of the loop and the data structures used.
Dependencies amongst the data accesses in each iteration and across iterations.
Once the compiler has made such a determination, it can generate vectorized code for the loop, allowing
the application to use the SIMD instructions.
The caveat to this is that only certain types of loops can be automatically vectorized, and in most cases
user interaction with the compiler is needed to fully enable this.
Example 4-17 shows the code for automatic vectorization for the simple four-iteration loop (from
Example 4-13).
Example 4-17. Automatic Vectorization for a Simple Loop
void add (float *restrict a,
float *restrict b,
float *restrict c)
{
int i;
for (i = 0; i < 4; i++) {
c[i] = a[i] + b[i];
}
}
Compile this code using the -QAX and -QRESTRICT switches of the Intel C++ Compiler, version 4.0 or
later.
The RESTRICT qualifier in the argument list is necessary to let the compiler know that there are no other
aliases to the memory to which the pointers point. In other words, the pointer for which it is used,
4-16
CODING FOR SIMD ARCHITECTURES
provides the only means of accessing the memory in question in the scope in which the pointers live.
Without the restrict qualifier, the compiler will still vectorize this loop using runtime data dependence
testing, where the generated code dynamically selects between sequential or vector execution of the
loop, based on overlap of the parameters (See documentation for the Intel C++ Compiler). The restrict
keyword avoids the associated overhead altogether.
See Intel C++ Compiler documentation for details.
4.4
STACK AND DATA ALIGNMENT
To get the most performance out of code written for SIMD technologies data should be formatted in
memory according to the guidelines described in this section. Assembly code with an unaligned accesses
is a lot slower than an aligned access.
4.4.1
Alignment and Contiguity of Data Access Patterns
The 64-bit packed data types defined by MMX technology, and the 128-bit packed data types for
Streaming SIMD Extensions and Streaming SIMD Extensions 2 create more potential for misaligned data
accesses. The data access patterns of many algorithms are inherently misaligned when using MMX technology and Streaming SIMD Extensions. Several techniques for improving data access, such as padding,
organizing data elements into arrays, etc. are described below. SSE3 provides a special-purpose instruction LDDQU that can avoid cache line splits is discussed in Section 5.7.1.1, “Supplemental Techniques for
Avoiding Cache Line Splits.”
4.4.1.1
Using Padding to Align Data
However, when accessing SIMD data using SIMD operations, access to data can be improved simply by a
change in the declaration. For example, consider a declaration of a structure, which represents a point in
space plus an attribute.
typedef struct {short x,y,z; char a} Point;
Point pt[N];
Assume we will be performing a number of computations on X, Y, Z in three of the four elements of a
SIMD word; see Section 4.5.1, “Data Structure Layout,” for an example. Even if the first element in array
PT is aligned, the second element will start 7 bytes later and not be aligned (3 shorts at two bytes each
plus a single byte = 7 bytes).
By adding the padding variable PAD, the structure is now 8 bytes, and if the first element is aligned to 8
bytes (64 bits), all following elements will also be aligned. The sample declaration follows:
typedef struct {short x,y,z; char a; char pad;} Point;
Point pt[N];
4.4.1.2
Using Arrays to Make Data Contiguous
In the following code,
for (i=0; i<N; i++) pt[i].y *= scale;
the second dimension Y needs to be multiplied by a scaling value. Here, the FOR loop accesses each Y
dimension in the array PT thus disallowing the access to contiguous data. This can degrade the performance of the application by increasing cache misses, by poor utilization of each cache line that is fetched,
and by increasing the chance for accesses which span multiple cache lines.
The following declaration allows you to vectorize the scaling operation and further improve the alignment
of the data access patterns:
short ptx[N], pty[N], ptz[N];
for (i=0; i<N; i++) pty[i] *= scale;
4-17
CODING FOR SIMD ARCHITECTURES
With the SIMD technology, choice of data organization becomes more important and should be made
carefully based on the operations that will be performed on the data. In some applications, traditional
data arrangements may not lead to the maximum performance.
A simple example of this is an FIR filter. An FIR filter is effectively a vector dot product in the length of the
number of coefficient taps.
Consider the following code:
(data [ j ] *coeff [0] + data [j+1]*coeff [1]+...+data [j+num of taps-1]*coeff [num of taps-1]),
If in the code above the filter operation of data element I is the vector dot product that begins at data
element J, then the filter operation of data element I+1 begins at data element J+1.
Assuming you have a 64-bit aligned data vector and a 64-bit aligned coefficients vector, the filter operation on the first data element will be fully aligned. For the second data element, however, access to the
data vector will be misaligned. For an example of how to avoid the misalignment problem in the FIR filter,
refer to Intel application notes on Streaming SIMD Extensions and filters.
Duplication and padding of data structures can be used to avoid the problem of data accesses in algorithms which are inherently misaligned. Section 4.5.1, “Data Structure Layout,” discusses trade-offs for
organizing data structures.
NOTE
The duplication and padding technique overcomes the misalignment problem, thus
avoiding the expensive penalty for misaligned data access, at the cost of increasing the
data size. When developing your code, you should consider this tradeoff and use the
option which gives the best performance.
4.4.2
Stack Alignment For 128-bit SIMD Technologies
For best performance, the Streaming SIMD Extensions and Streaming SIMD Extensions 2 require their
memory operands to be aligned to 16-byte boundaries. Unaligned data can cause significant performance penalties compared to aligned data. However, the existing software conventions for IA-32
(STDCALL, CDECL, FASTCALL) as implemented in most compilers, do not provide any mechanism for
ensuring that certain local data and certain parameters are 16-byte aligned. Therefore, Intel has defined
a new set of IA-32 software conventions for alignment to support the new __M128* datatypes (__M128,
__M128D, and __M218I). These meet the following conditions:
•
Functions that use Streaming SIMD Extensions or Streaming SIMD Extensions 2 data need to provide
a 16-byte aligned stack frame.
•
__M128* parameters need to be aligned to 16-byte boundaries, possibly creating “holes” (due to
padding) in the argument block.
The new conventions presented in this section as implemented by the Intel C++ Compiler can be used as
a guideline for an assembly language code as well. In many cases, this section assumes the use of the
__M128* data types, as defined by the Intel C++ Compiler, which represents an array of four 32-bit floats.
4.4.3
Data Alignment for MMX Technology
Many compilers enable alignment of variables using controls. This aligns variable bit lengths to the
appropriate boundaries. If some of the variables are not appropriately aligned as specified, you can align
them using the C algorithm in Example 4-18.
Example 4-18. C Algorithm for 64-bit Data Alignment
/* Make newp a pointer to a 64-bit aligned array of NUM_ELEMENTS 64-bit elements. */
double *p, *newp;
p = (double*)malloc (sizeof(double)*(NUM_ELEMENTS+1));
newp = (p+7) & (~0x7);
4-18
CODING FOR SIMD ARCHITECTURES
The algorithm in Example 4-18 aligns an array of 64-bit elements on a 64-bit boundary. The constant of
7 is derived from one less than the number of bytes in a 64-bit element, or 8-1. Aligning data in this
manner avoids the significant performance penalties that can occur when an access crosses a cache line
boundary.
Another way to improve data alignment is to copy the data into locations that are aligned on 64-bit
boundaries. When the data is accessed frequently, this can provide a significant performance improvement.
4.4.4
Data Alignment for 128-bit data
Data must be 16-byte aligned when loading to and storing from the 128-bit XMM registers used by
SSE/SSE2/SSE3/SSSE3. This must be done to avoid severe performance penalties and, at worst, execution faults.
There are MOVE instructions (and intrinsics) that allow unaligned data to be copied to and out of XMM
registers when not using aligned data, but such operations are much slower than aligned accesses. If
data is not 16-byte-aligned and the programmer or the compiler does not detect this and uses the
aligned instructions, a fault occurs. So keep data 16-byte-aligned. Such alignment also works for MMX
technology code, even though MMX technology only requires 8-byte alignment.
The following describes alignment techniques for Pentium 4 processor as implemented with the Intel
C++ Compiler.
4.4.4.1
Compiler-Supported Alignment
The Intel C++ Compiler provides the following methods to ensure that the data is aligned.
Alignment by F32vec4 or __m128 Data Types
When the compiler detects F32VEC4 or __M128 data declarations or parameters, it forces alignment of
the object to a 16-byte boundary for both global and local data, as well as parameters. If the declaration
is within a function, the compiler also aligns the function's stack frame to ensure that local data and
parameters are 16-byte-aligned. For details on the stack frame layout that the compiler generates for
both debug and optimized (“release”-mode) compilations, refer to Intel’s compiler documentation.
__declspec(align(16)) specifications
These can be placed before data declarations to force 16-byte alignment. This is useful for local or global
data declarations that are assigned to 128-bit data types. The syntax for it is
__declspec(align(integer-constant))
where the INTEGER-CONSTANT is an integral power of two but no greater than 32. For example, the
following increases the alignment to 16-bytes:
__declspec(align(16)) float buffer[400];
The variable BUFFER could then be used as if it contained 100 objects of type __M128 or F32VEC4. In the
code below, the construction of the F32VEC4 object, X, will occur with aligned data.
void foo() {
F32vec4 x = *(__m128 *) buffer;
...
}
Without the declaration of __DECLSPEC(ALIGN(16)), a fault may occur.
Alignment by Using a UNION Structure
When feasible, a UNION can be used with 128-bit data types to allow the compiler to align the data structure by default. This is preferred to forcing alignment with __DECLSPEC(ALIGN(16)) because it exposes
the true program intent to the compiler in that __M128 data is being used. For example:
4-19
CODING FOR SIMD ARCHITECTURES
union {
float f[400];
__m128 m[100];
} buffer;
Now, 16-byte alignment is used by default due to the __M128 type in the UNION; it is not necessary to
use __DECLSPEC(ALIGN(16)) to force the result.
In C++ (but not in C) it is also possible to force the alignment of a CLASS/STRUCT/UNION type, as in the
code that follows:
struct __declspec(align(16)) my_m128
{
float f[4];
};
If the data in such a CLASS is going to be used with the Streaming SIMD Extensions or Streaming SIMD
Extensions 2, it is preferable to use a UNION to make this explicit. In C++, an anonymous UNION can be
used to make this more convenient:
class my_m128 {
union {
__m128 m;
float f[4];
};
};
Because the UNION is anonymous, the names, M and F, can be used as immediate member names of
MY__M128. Note that __DECLSPEC(ALIGN) has no effect when applied to a CLASS, STRUCT, or UNION
member in either C or C++.
Alignment by Using __m64 or DOUBLE Data
In some cases, the compiler aligns routines with __M64 or DOUBLE data to 16-bytes by default. The
command-line switch, -QSFALIGN16, limits the compiler so that it only performs this alignment on
routines that contain 128-bit data. The default behavior is to use -QSFALIGN8. This switch instructs the
complier to align routines with 8- or 16-byte data types to 16 bytes.
For more, see the Intel C++ Compiler documentation.
4.5
IMPROVING MEMORY UTILIZATION
Memory performance can be improved by rearranging data and algorithms for SSE, SSE2, and MMX
technology intrinsics. Methods for improving memory performance involve working with the following:
•
•
•
Data structure layout.
Strip-mining for vectorization and memory utilization.
Loop-blocking.
Using the cacheability instructions, prefetch and streaming store, also greatly enhance memory utilization. See also: Chapter 7, “Optimizing Cache Usage.”
4.5.1
Data Structure Layout
For certain algorithms, like 3D transformations and lighting, there are two basic ways to arrange vertex
data. The traditional method is the array of structures (AoS) arrangement, with a structure for each
4-20
CODING FOR SIMD ARCHITECTURES
vertex (Example 4-19). However this method does not take full advantage of SIMD technology capabilities.
Example 4-19. AoS Data Structure
typedef struct{
float x,y,z;
int a,b,c;
...
} Vertex;
Vertex Vertices[NumOfVertices];
The best processing method for code using SIMD technology is to arrange the data in an array for each
coordinate (Example 4-20). This data arrangement is called structure of arrays (SoA).
Example 4-20. SoA Data Structure
typedef struct{
float x[NumOfVertices];
float y[NumOfVertices];
float z[NumOfVertices];
int a[NumOfVertices];
int b[NumOfVertices];
int c[NumOfVertices];
...
} VerticesList;
VerticesList Vertices;
There are two options for computing data in AoS format: perform operation on the data as it stands in
AoS format, or re-arrange it (swizzle it) into SoA format dynamically. See Example 4-21 for code samples
of each option based on a dot-product computation.
Example 4-21. AoS and SoA Code Samples
; The dot product of an array of vectors (Array) and a fixed vector (Fixed) is a
; common operation in 3D lighting operations, where Array = (x0,y0,z0),(x1,y1,z1),...
; and Fixed = (xF,yF,zF)
; A dot product is defined as the scalar quantity d0 = x0*xF + y0*yF + z0*zF.
;
; AoS code
; All values marked DC are “don’t-care.”
; In the AOS model, the vertices are stored in the xyz format
movaps xmm0, Array
; xmm0 = DC, x0, y0, z0
movaps xmm1, Fixed
; xmm1 = DC, xF, yF, zF
mulps xmm0, xmm1
; xmm0 = DC, x0*xF, y0*yF, z0*zF
movhlps xmm, xmm0
; xmm = DC, DC, DC, x0*xF
addps xmm1, xmm0
; xmm0 = DC, DC, DC,
; x0*xF+z0*zFmovaps xmm2, xmm1
shufps xmm2, xmm2,55h ; xmm2 = DC, DC, DC, y0*yF
addps xmm2, xmm1
; xmm1 = DC, DC, DC,
; x0*xF+y0*yF+z0*zF
4-21
CODING FOR SIMD ARCHITECTURES
Example 4-21. AoS and SoA Code Samples (Contd.)
; SoA code
; X = x0,x1,x2,x3
; Y = y0,y1,y2,y3
; Z = z0,z1,z2,z3
; A = xF,xF,xF,xF
; B = yF,yF,yF,yF
; C = zF,zF,zF,zF
movaps xmm0, X
movaps xmm1, Y
movaps xmm2, Z
mulps xmm0, A
mulps xmm1, B
mulps xmm2, C
addps xmm0, xmm1
addps xmm0, xmm2
; xmm0 = x0,x1,x2,x3
; xmm0 = y0,y1,y2,y3
; xmm0 = z0,z1,z2,z3
; xmm0 = x0*xF, x1*xF, x2*xF, x3*xF
; xmm1 = y0*yF, y1*yF, y2*yF, y3*xF
; xmm2 = z0*zF, z1*zF, z2*zF, z3*zF
; xmm0 = (x0*xF+y0*yF+z0*zF), ...
Performing SIMD operations on the original AoS format can require more calculations and some operations do not take advantage of all SIMD elements available. Therefore, this option is generally less efficient.
The recommended way for computing data in AoS format is to swizzle each set of elements to SoA format
before processing it using SIMD technologies. Swizzling can either be done dynamically during program
execution or statically when the data structures are generated. See Chapter 5 and Chapter 6 for examples. Performing the swizzle dynamically is usually better than using AoS, but can be somewhat inefficient because there are extra instructions during computation. Performing the swizzle statically, when
data structures are being laid out, is best as there is no runtime overhead.
As mentioned earlier, the SoA arrangement allows more efficient use of the parallelism of SIMD technologies because the data is ready for computation in a more optimal vertical manner: multiplying components X0,X1,X2,X3 by XF,XF,XF,XF using 4 SIMD execution slots to produce 4 unique results. In contrast,
computing directly on AoS data can lead to horizontal operations that consume SIMD execution slots but
produce only a single scalar result (as shown by the many “don’t-care” (DC) slots in Example 4-21).
Use of the SoA format for data structures can lead to more efficient use of caches and bandwidth. When
the elements of the structure are not accessed with equal frequency, such as when element x, y, z are
accessed ten times more often than the other entries, then SoA saves memory and prevents fetching
unnecessary data items a, b, and c.
Example 4-22. Hybrid SoA
Data Structure
NumOfGroups = NumOfVertices/SIMDwidth
typedef struct{
float x[SIMDwidth];
float y[SIMDwidth];
float z[SIMDwidth];
} VerticesCoordList;
typedef struct{
int a[SIMDwidth];
int b[SIMDwidth];
int c[SIMDwidth];
...
} VerticesColorList;
VerticesCoordList VerticesCoord[NumOfGroups];
VerticesColorList VerticesColor[NumOfGroups];
4-22
CODING FOR SIMD ARCHITECTURES
Note that SoA can have the disadvantage of requiring more independent memory stream references. A
computation that uses arrays X, Y, and Z (see Example 4-20) would require three separate data streams.
This can require the use of more prefetches, additional address generation calculations, as well as having
a greater impact on DRAM page access efficiency.
There is an alternative: a hybrid SoA approach blends the two alternatives (see Example 4-22). In this
case, only 2 separate address streams are generated and referenced: one contains XXXX, YYYY,ZZZZ,
ZZZZ,... and the other AAAA, BBBB, CCCC, AAAA, DDDD,... . The approach prevents fetching unnecessary data, assuming the variables X, Y, Z are always used together; whereas the variables A, B, C would
also be used together, but not at the same time as X, Y, Z.
The hybrid SoA approach ensures:
•
•
•
•
•
Data is organized to enable more efficient vertical SIMD computation.
Simpler/less address generation than AoS.
Fewer streams, which reduces DRAM page misses.
Use of fewer prefetches, due to fewer streams.
Efficient cache line packing of data elements that are used concurrently.
With the advent of the SIMD technologies, the choice of data organization becomes more important and
should be carefully based on the operations to be performed on the data. This will become increasingly
important in the Pentium 4 processor and future processors. In some applications, traditional data
arrangements may not lead to the maximum performance. Application developers are encouraged to
explore different data arrangements and data segmentation policies for efficient computation. This may
mean using a combination of AoS, SoA, and Hybrid SoA in a given application.
4.5.2
Strip-Mining
Strip-mining, also known as loop sectioning, is a loop transformation technique for enabling SIMDencodings of loops, as well as providing a means of improving memory performance. First introduced for
vectorizers, this technique consists of the generation of code when each vector operation is done for a
size less than or equal to the maximum vector length on a given vector machine. By fragmenting a large
loop into smaller segments or strips, this technique transforms the loop structure by:
•
Increasing the temporal and spatial locality in the data cache if the data are reusable in different
passes of an algorithm.
•
Reducing the number of iterations of the loop by a factor of the length of each “vector,” or number of
operations being performed per SIMD operation. In the case of Streaming SIMD Extensions, this
vector or strip-length is reduced by 4 times: four floating-point data items per single Streaming SIMD
Extensions single-precision floating-point SIMD operation are processed. Consider Example 4-23.
Example 4-23. Pseudo-code Before Strip Mining
typedef struct _VERTEX {
float x, y, z, nx, ny, nz, u, v;
} Vertex_rec;
main()
{
Vertex_rec v[Num];
....
for (i=0; i<Num; i++) {
Transform(v[i]);
}
4-23
CODING FOR SIMD ARCHITECTURES
Example 4-23. Pseudo-code Before Strip Mining (Contd.)
for (i=0; i<Num; i++) {
Lighting(v[i]);
}
....
}
The main loop consists of two functions: transformation and lighting. For each object, the main loop calls
a transformation routine to update some data, then calls the lighting routine to further work on the data.
If the size of array V[NUM] is larger than the cache, then the coordinates for V[I] that were cached during
TRANSFORM(V[I]) will be evicted from the cache by the time we do LIGHTING(V[I]). This means that
V[I] will have to be fetched from main memory a second time, reducing performance.
In Example 4-24, the computation has been strip-mined to a size STRIP_SIZE. The value STRIP_SIZE is
chosen such that STRIP_SIZE elements of array V[NUM] fit into the cache hierarchy. By doing this, a
given element V[I] brought into the cache by TRANSFORM(V[I]) will still be in the cache when we
perform LIGHTING(V[I]), and thus improve performance over the non-strip-mined code.
Example 4-24. Strip Mined Code
MAIN()
{
Vertex_rec v[Num];
....
for (i=0; i < Num; i+=strip_size) {
FOR (J=I; J < MIN(NUM, I+STRIP_SIZE); J++) {
TRANSFORM(V[J]);
}
FOR (J=I; J < MIN(NUM, I+STRIP_SIZE); J++) {
LIGHTING(V[J]);
}
}
}
4.5.3
Loop Blocking
Loop blocking is another useful technique for memory performance optimization. The main purpose of
loop blocking is also to eliminate as many cache misses as possible. This technique transforms the
memory domain of a given problem into smaller chunks rather than sequentially traversing through the
entire memory domain. Each chunk should be small enough to fit all the data for a given computation
into the cache, thereby maximizing data reuse. In fact, one can treat loop blocking as strip mining in two
or more dimensions. Consider the code in Example 4-23 and access pattern in Figure 4-5. The twodimensional array A is referenced in the J (column) direction and then referenced in the I (row) direction
(column-major order); whereas array B is referenced in the opposite manner (row-major order). Assume
the memory layout is in column-major order; therefore, the access strides of array A and B for the code
in Example 4-25 would be 1 and MAX, respectively.
Example 4-25. Loop Blocking
A. Original Loop
float A[MAX, MAX], B[MAX, MAX]
for (i=0; i< MAX; i++) {
for (j=0; j< MAX; j++) {
A[i,j] = A[i,j] + B[j, i];
}
}
4-24
CODING FOR SIMD ARCHITECTURES
Example 4-25. Loop Blocking (Contd.)
B. Transformed Loop after Blocking
float A[MAX, MAX], B[MAX, MAX];
for (i=0; i< MAX; i+=block_size) {
for (j=0; j< MAX; j+=block_size) {
for (ii=i; ii<i+block_size; ii++) {
for (jj=j; jj<j+block_size; jj++) {
A[ii,jj] = A[ii,jj] + B[jj, ii];
}
}
}
}
For the first iteration of the inner loop, each access to array B will generate a cache miss. If the size of
one row of array A, that is, A[2, 0:MAX-1], is large enough, by the time the second iteration starts, each
access to array B will always generate a cache miss. For instance, on the first iteration, the cache line
containing B[0, 0:7] will be brought in when B[0,0] is referenced because the float type variable is four
bytes and each cache line is 32 bytes. Due to the limitation of cache capacity, this line will be evicted due
to conflict misses before the inner loop reaches the end. For the next iteration of the outer loop, another
cache miss will be generated while referencing B[0, 1]. In this manner, a cache miss occurs when each
element of array B is referenced, that is, there is no data reuse in the cache at all for array B.
This situation can be avoided if the loop is blocked with respect to the cache size. In Figure 4-5, a
BLOCK_SIZE is selected as the loop blocking factor. Suppose that BLOCK_SIZE is 8, then the blocked
chunk of each array will be eight cache lines (32 bytes each). In the first iteration of the inner loop, A[0,
0:7] and B[0, 0:7] will be brought into the cache. B[0, 0:7] will be completely consumed by the first iteration of the outer loop. Consequently, B[0, 0:7] will only experience one cache miss after applying loop
blocking optimization in lieu of eight misses for the original algorithm. As illustrated in Figure 4-5, arrays
A and B are blocked into smaller rectangular chunks so that the total size of two blocked A and B chunks
is smaller than the cache size. This allows maximum data reuse.
4-25
CODING FOR SIMD ARCHITECTURES
A (i, j) access pattern
A(i, j) access pattern
after blocking
j
Blocking
i
+
< cache size
B(i, j) access pattern
after blocking
OM15158
Figure 4-5. Loop Blocking Access Pattern
As one can see, all the redundant cache misses can be eliminated by applying this loop blocking technique. If MAX is huge, loop blocking can also help reduce the penalty from DTLB (data translation lookaside buffer) misses. In addition to improving the cache/memory performance, this optimization technique also saves external bus bandwidth.
4.6
INSTRUCTION SELECTION
The following section gives some guidelines for choosing instructions to complete a task.
One barrier to SIMD computation can be the existence of data-dependent branches. Conditional moves
can be used to eliminate data-dependent branches. Conditional moves can be emulated in SIMD computation by using masked compares and logicals, as shown in Example 4-26. SSE4.1 provides packed blend
instruction that can vectorize data-dependent branches in a loop.
Example 4-26. Emulation of Conditional Moves
High-level code:
__declspec(align(16)) short A[MAX_ELEMENT], B[MAX_ELEMENT], C[MAX_ELEMENT], D[MAX_ELEMENT],
E[MAX_ELEMENT];
for (i=0; i<MAX_ELEMENT; i++) {
if (A[i] > B[i]) {
C[i] = D[i];
} else {
C[i] = E[i];
}
4-26
CODING FOR SIMD ARCHITECTURES
Example 4-26. Emulation of Conditional Moves (Contd.)
}
MMX assembly code processes 4 short values per iteration:
xor
eax, eax
top_of_loop:
movq
mm0, [A + eax]
pcmpgtwxmm0, [B + eax]; Create compare mask
movq
mm1, [D + eax]
pand
mm1, mm0; Drop elements where A<B
pandn mm0, [E + eax] ; Drop elements where A>B
por
movq
add
cmp
jle
mm0, mm1; Crete single word
[C + eax], mm0
eax, 8
eax, MAX_ELEMENT*2
top_of_loop
SSE4.1 assembly processes 8 short values per iteration:
xor
eax, eax
top_of_loop:
movdqq xmm0, [A + eax]
pcmpgtwxmm0, [B + eax]; Create compare mask
movdqa xmm1, [E + eax]
pblendv xmm1, [D + eax], xmm0;
movdqa [C + eax], xmm1;
add
eax, 16
cmp
eax, MAX_ELEMENT*2
jle
top_of_loop
If there are multiple consumers of an instance of a register, group the consumers together as closely as
possible. However, the consumers should not be scheduled near the producer.
4.6.1
SIMD Optimizations and Microarchitectures
Pentium M, Intel Core Solo and Intel Core Duo processors have a different microarchitecture than Intel
NetBurst microarchitecture. The following sub-section discusses optimizing SIMD code targeting Intel
Core Solo and Intel Core Duo processors.
The register-register variant of the following instructions has improved performance on Intel Core Solo
and Intel Core Duo processor relative to Pentium M processors. This is because the instructions consist of
two micro-ops instead of three. Relevant instructions are: unpcklps, unpckhps, packsswb, packuswb,
packssdw, pshufd, shuffps and shuffpd.
Recommendation: When targeting code generation for Intel Core Solo and Intel Core Duo processors,
favor instructions consisting of two micro-ops over those with more than two micro-ops.
Intel Core microarchitecture generally executes SIMD instructions more efficiently than previous
microarchitectures in terms of latency and throughput, most 128-bit SIMD operations have 1 cycle
throughput (except shuffle, pack, unpack operations). Many of the restrictions specific to Intel Core Duo,
Intel Core Solo processors (such as 128-bit SIMD operations having 2 cycle throughput at a minimum)
do not apply to Intel Core microarchitecture. The same is true of Intel Core microarchitecture relative to
Intel NetBurst microarchitectures.
Enhanced Intel Core microarchitecture provides dedicated 128-bit shuffler and radix-16 divider hardware. These capabilities and SSE4.1 instructions will make vectorization using 128-bit SIMD instructions
even more efficient and effective.
4-27
CODING FOR SIMD ARCHITECTURES
Recommendation: With the proliferation of 128-bit SIMD hardware in Intel Core microarchitecture and
Enhanced Intel Core microarchitecture, integer SIMD code written using MMX instructions should
consider more efficient implementations using 128-bit SIMD instructions.
4.7
TUNING THE FINAL APPLICATION
The best way to tune your application once it is functioning correctly is to use a profiler that measures the
application while it is running on a system. Intel VTune Amplifier XE can help you determine where to
make changes in your application to improve performance. Using Intel VTune Amplifier XE can help you
with various phases required for optimized performance. See Appendix A.3.1, “Intel® VTune™ Amplifier
XE,” for details. After every effort to optimize, you should check the performance gains to see where you
are making your major optimization gains.
4-28
CHAPTER 5
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
SIMD integer instructions provide performance improvements in applications that are integer-intensive
and can take advantage of SIMD architecture.
Guidelines in this chapter for using SIMD integer instructions (in addition to those described in Chapter
3) may be used to develop fast and efficient code that scales across processor generations.
The collection of 64-bit and 128-bit SIMD integer instructions supported by MMX technology, SSE, SSE2,
SSE3, SSSE3, SSE4.1, and PCMPEQQ in SSE4.2 are referred to as SIMD integer instructions.
Code sequences in this chapter demonstrates the use of basic 64-bit SIMD integer instructions and more
efficient 128-bit SIMD integer instructions.
Processors based on Intel Core microarchitecture support MMX, SSE, SSE2, SSE3, and SSSE3. Processors based on Enhanced Intel Core microarchitecture support SSE4.1 and all previous generations of
SIMD integer instructions. Processors based on Intel microarchitecture code name Nehalem supports
MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2.
Single-instruction, multiple-data techniques can be applied to text/string processing, lexing and parser
applications. SIMD programming in string/text processing and lexing applications often require sophisticated techniques beyond those commonly used in SIMD integer programming. This is covered in Chapter
11, “SSE4.2 and SIMD Programming For Text-Processing/Lexing/Parsing”.
Execution of 128-bit SIMD integer instructions in Intel Core microarchitecture and Enhanced Intel Core
microarchitecture are substantially more efficient than on previous microarchitectures. Thus newer
SIMD capabilities introduced in SSE4.1 operate on 128-bit operands and do not introduce equivalent 64bit SIMD capabilities. Conversion from 64-bit SIMD integer code to 128-bit SIMD integer code is highly
recommended.
This chapter contains examples that will help you to get started with coding your application. The goal is
to provide simple, low-level operations that are frequently used. The examples use a minimum number
of instructions necessary to achieve best performance on the current generation of Intel 64 and IA-32
processors.
Each example includes a short description, sample code, and notes if necessary. These examples do not
address scheduling as it is assumed the examples will be incorporated in longer code sequences.
For planning considerations of using the SIMD integer instructions, refer to Section 4.1.3.
5.1
GENERAL RULES ON SIMD INTEGER CODE
General rules and suggestions are:
•
Do not intermix 64-bit SIMD integer instructions with x87 floating-point instructions. See Section
5.2, “Using SIMD Integer with x87 Floating-point.” Note that all SIMD integer instructions can be
intermixed without penalty.
•
Favor 128-bit SIMD integer code over 64-bit SIMD integer code. On microarchitectures prior to Intel
Core microarchitecture, most 128-bit SIMD instructions have two-cycle throughput restrictions due
to the underlying 64-bit data path in the execution engine. Intel Core microarchitecture executes
most SIMD instructions (except shuffle, pack, unpack operations) with one-cycle throughput and
provides three ports to execute multiple SIMD instructions in parallel. Enhanced Intel Core microarchitecture speeds up 128-bit shuffle, pack, unpack operations with 1 cycle throughput.
•
When writing SIMD code that works for both integer and floating-point data, use the subset of SIMD
convert instructions or load/store instructions to ensure that the input operands in XMM registers
contain data types that are properly defined to match the instruction.
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Code sequences containing cross-typed usage produce the same result across different implementations but incur a significant performance penalty. Using SSE/SSE2/SSE3/SSSE3/SSE44.1 instructions to operate on type-mismatched SIMD data in the XMM register is strongly discouraged.
•
Use the optimization rules and guidelines described in Chapter 3 and Chapter 4.
•
Take advantage of hardware prefetcher where possible. Use the PREFETCH instruction only when
data access patterns are irregular and prefetch distance can be pre-determined. See Chapter 7,
“Optimizing Cache Usage.”
•
Emulate conditional moves by using blend, masked compares and logicals instead of using
conditional branches.
5.2
USING SIMD INTEGER WITH X87 FLOATING-POINT
All 64-bit SIMD integer instructions use MMX registers, which share register state with the x87 floatingpoint stack. Because of this sharing, certain rules and considerations apply. Instructions using MMX
registers cannot be freely intermixed with x87 floating-point registers. Take care when switching
between 64-bit SIMD integer instructions and x87 floating-point instructions to ensure functional
correctness. See Section 5.2.1.
Both Section 5.2.1 and Section 5.2.2 apply only to software that employs MMX instructions. As noted
before, 128-bit SIMD integer instructions should be favored to replace MMX code and achieve higher
performance. That also obviates the need to use EMMS, and the performance penalty of using EMMS
when intermixing MMX and X87 instructions.
For performance considerations, there is no penalty of intermixing SIMD floating-point operations and
128-bit SIMD integer operations and x87 floating-point operations.
5.2.1
Using the EMMS Instruction
When generating 64-bit SIMD integer code, keep in mind that the eight MMX registers are aliased to x87
floating-point registers. Switching from MMX instructions to x87 floating-point instructions incurs a finite
delay, so it is the best to minimize switching between these instruction types. But when switching, the
EMMS instruction provides an efficient means to clear the x87 stack so that subsequent x87 code can
operate properly.
As soon as an instruction makes reference to an MMX register, all valid bits in the x87 floating-point tag
word are set, which implies that all x87 registers contain valid values. In order for software to operate
correctly, the x87 floating-point stack should be emptied when starting a series of x87 floating-point
calculations after operating on the MMX registers.
Using EMMS clears all valid bits, effectively emptying the x87 floating-point stack and making it ready for
new x87 floating-point operations. The EMMS instruction ensures a clean transition between using operations on the MMX registers and using operations on the x87 floating-point stack. On the Pentium 4
processor, there is a finite overhead for using the EMMS instruction.
Failure to use the EMMS instruction (or the _MM_EMPTY() intrinsic) between operations on the MMX
registers and x87 floating-point registers may lead to unexpected results.
NOTE
Failure to reset the tag word for FP instructions after using an MMX instruction can result
in faulty execution or poor performance.
5.2.2
Guidelines for Using EMMS Instruction
When developing code with both x87 floating-point and 64-bit SIMD integer instructions, follow these
steps:
5-2
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
1. Always call the EMMS instruction at the end of 64-bit SIMD integer code when the code transitions to
x87 floating-point code.
2. Insert the EMMS instruction at the end of all 64-bit SIMD integer code segments to avoid an x87
floating-point stack overflow exception when an x87 floating-point instruction is executed.
When writing an application that uses both floating-point and 64-bit SIMD integer instructions, use the
following guidelines to help you determine when to use EMMS:
•
If next instruction is x87 FP — Use _MM_EMPTY() after a 64-bit SIMD integer instruction if the
next instruction is an X87 FP instruction; for example, before doing calculations on floats, doubles or
long doubles.
•
Don’t empty when already empty — If the next instruction uses an MMX register, _MM_EMPTY()
incurs a cost with no benefit.
•
Group Instructions — Try to partition regions that use X87 FP instructions from those that use 64bit SIMD integer instructions. This eliminates the need for an EMMS instruction within the body of a
critical loop.
•
Runtime initialization — Use _MM_EMPTY() during runtime initialization of __M64 and X87 FP data
types. This ensures resetting the register between data type transitions. See Example 5-1 for coding
usage.
Example 5-1. Resetting Register Between __m64 and FP Data Types Code
Incorrect Usage
Correct Usage
__m64 x = _m_paddd(y, z);
float f = init();
__m64 x = _m_paddd(y, z);
float f = (_mm_empty(), init());
You must be aware that your code generates an MMX instruction, which uses MMX registers with the Intel
C++ Compiler, in the following situations:
•
when using a 64-bit SIMD integer intrinsic from MMX technology, SSE/SSE2/SSSE3
•
when using a 64-bit SIMD integer instruction from MMX technology, SSE/SSE2/SSSE3 through inline
assembly
•
when referencing the __M64 data type variable
Additional information on the x87 floating-point programming model can be found in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1. For more on EMMS, visit http://developer.intel.com.
5.3
DATA ALIGNMENT
Make sure that 64-bit SIMD integer data is 8-byte aligned and that 128-bit SIMD integer data is 16-byte
aligned. Referencing unaligned 64-bit SIMD integer data can incur a performance penalty due to
accesses that span 2 cache lines. Referencing unaligned 128-bit SIMD integer data results in an exception unless the MOVDQU (move double-quadword unaligned) instruction is used. Using the MOVDQU
instruction on unaligned data can result in lower performance than using 16-byte aligned references.
Refer to Section 4.4, “Stack and Data Alignment,” for more information.
Loading 16 bytes of SIMD data efficiently requires data alignment on 16-byte boundaries. SSSE3
provides the PALIGNR instruction. It reduces overhead in situations that requires software to processing
data elements from non-aligned address. The PALIGNR instruction is most valuable when loading or
storing unaligned data with the address shifts by a few bytes. You can replace a set of unaligned loads
with aligned loads followed by using PALIGNR instructions and simple register to register copies.
5-3
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Using PALIGNRs to replace unaligned loads improves performance by eliminating cache line splits and
other penalties. In routines like MEMCPY( ), PALIGNR can boost the performance of misaligned cases.
Example 5-2 shows a situation that benefits by using PALIGNR.
Example 5-2. FIR Processing Example in C language Code
void FIR(float *in, float *out, float *coeff, int count)
{int i,j;
for ( i=0; i<count - TAP; i++ )
{
float sum = 0;
for ( j=0; j<TAP; j++ )
{
sum += in[j]*coeff[j]; }
*out++ = sum;
in++;
}
}
Example 5-3 compares an optimal SSE2 sequence of the FIR loop and an equivalent SSSE3 implementation. Both implementations unroll 4 iteration of the FIR inner loop to enable SIMD coding techniques. The
SSE2 code can not avoid experiencing cache line split once every four iterations. PALGNR allows the
SSSE3 code to avoid the delays associated with cache line splits.
Example 5-3. SSE2 and SSSE3 Implementation of FIR Processing Code
Optimized for SSE2
Optimized for SSSE3
pxor
xor
mov
mov
pxor xmm0, xmm0
xor
ecx, ecx
mov
eax, dword ptr[input]
mov
ebx, dword ptr[coeff4]
xmm0, xmm0
ecx, ecx
eax, dword ptr[input]
ebx, dword ptr[coeff4]
inner_loop:
movaps xmm1, xmmword ptr[eax+ecx]
mulps xmm1, xmmword ptr[ebx+4*ecx]
addps xmm0, xmm1
inner_loop:
movaps xmm1, xmmword ptr[eax+ecx]
movaps xmm3, xmm1
mulps xmm1, xmmword ptr[ebx+4*ecx]
addps xmm0, xmm1
movups xmm1, xmmword ptr[eax+ecx+4]
mulps xmm1, xmmword ptr[ebx+4*ecx+16]
addps xmm0, xmm1
movaps xmm2, xmmword ptr[eax+ecx+16]
movaps xmm1, xmm2
palignr xmm2, xmm3, 4
mulps xmm2, xmmword ptr[ebx+4*ecx+16]
addps xmm0, xmm2
movups xmm1, xmmword ptr[eax+ecx+8]
mulps xmm1, xmmword ptr[ebx+4*ecx+32]
addps xmm0, xmm1
movaps xmm2, xmm1
palignr xmm2, xmm3, 8
mulps xmm2, xmmword ptr[ebx+4*ecx+32]
addps xmm0, xmm2
movups xmm1, xmmword ptr[eax+ecx+12]
mulps xmm1, xmmword ptr[ebx+4*ecx+48]
addps xmm0, xmm1
movaps xmm2, xmm1
palignr xmm2, xmm3, 12
mulps xmm2, xmmword ptr[ebx+4*ecx+48]
addps xmm0, xmm2
add
cmp
jl
ecx, 16
ecx, 4*TAP
inner_loop
mov
eax, dword ptr[output]
movaps xmmword ptr[eax], xmm0
5-4
add
cmp
jl
ecx, 16
ecx, 4*TAP
inner_loop
mov
eax, dword ptr[output]
movaps xmmword ptr[eax], xmm0
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.4
DATA MOVEMENT CODING TECHNIQUES
In general, better performance can be achieved if data is pre-arranged for SIMD computation (see
Section 4.5, “Improving Memory Utilization”). This may not always be possible.
This section covers techniques for gathering and arranging data for more efficient SIMD computation.
5.4.1
Unsigned Unpack
MMX technology provides several instructions that are used to pack and unpack data in the MMX registers. SSE2 extends these instructions so that they operate on 128-bit source and destinations.
The unpack instructions can be used to zero-extend an unsigned number. Example 5-4 assumes the
source is a packed-word (16-bit) data type.
Example 5-4. Zero Extend 16-bit Values into 32 Bits Using Unsigned Unpack Instructions Code
; Input:
;
;
;
;
; Output:
;
;
;
;
;
;
XMM0
XMM7 0
8 16-bit values in source
a local variable can be used
instead of the register XMM7 if
desired.
XMM0
four zero-extended 32-bit
doublewords from four low-end
words
four zero-extended 32-bit
doublewords from four high-end
words
XMM1
movdqa
xmm1, xmm0 ; copy source
punpcklwd xmm0, xmm7 ; unpack the 4 low-end words
; into 4 32-bit doubleword
punpckhwd xmm1, xmm7 ; unpack the 4 high-end words
; into 4 32-bit doublewords
5.4.2
Signed Unpack
Signed numbers should be sign-extended when unpacking values. This is similar to the zero-extend
shown above, except that the PSRAD instruction (packed shift right arithmetic) is used to sign extend the
values.
Example 5-5 assumes the source is a packed-word (16-bit) data type.
Example 5-5. Signed Unpack Code
Input:
;
; Output:
;
;
;
;
;
XMM0
source value
XMM0
four sign-extended 32-bit doublewords
from four low-end words
four sign-extended 32-bit doublewords
from four high-end words
XMM1
5-5
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-5. Signed Unpack Code (Contd.)
movdqa
punpcklwd
xmm1, xmm0 ; copy source
xmm0, xmm0 ; unpack four low end words of the source
; into the upper 16 bits of each doubleword
; in the destination
punpckhwd xmm1, xmm1 ; unpack 4 high-end words of the source
; into the upper 16 bits of each doubleword
; in the destination
psrad
xmm0, 16
psrad
xmm1, 16
5.4.3
; sign-extend the 4 low-end words of the source
; into four 32-bit signed doublewords
; sign-extend the 4 high-end words of the
; source into four 32-bit signed doublewords
Interleaved Pack with Saturation
Pack instructions pack two values into a destination register in a predetermined order. PACKSSDW saturates two signed doublewords from a source operand and two signed doublewords from a destination
operand into four signed words; and it packs the four signed words into a destination register. See
Figure 5-1.
SSE2 extends PACKSSDW so that it saturates four signed doublewords from a source operand and four
signed doublewords from a destination operand into eight signed words; the eight signed words are
packed into the destination.
m m /m 64
mm
D
C
D1
B
C1
B1
A
A1
mm
OM15159
Figure 5-1. PACKSSDW mm, mm/mm64 Instruction
Figure 5-2 illustrates where two pairs of values are interleaved in a destination register; Example 5-6
shows MMX code that accomplishes the operation.
Two signed doublewords are used as source operands and the result is interleaved signed words. The
sequence in Example 5-6 can be extended in SSE2 to interleave eight signed words using XMM registers.
5-6
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
M M /M 6 4
mm
D
C
D1
B
B1
C1
A
A1
mm
O M 15160
Figure 5-2. Interleaved Pack with Saturation
Example 5-6. Interleaved Pack with Saturation Code
; Input:
;
; Output:
;
;
;
MM0
MM1
signed source1 value
signed source2 value
MM0
the first and third words contain the
signed-saturated doublewords from MM0,
the second and fourth words contain
signed-saturated doublewords from MM1
;
packssdw mm0, mm0
packssdw mm1, mm1
punpcklwd mm0, mm1
; pack and sign saturate
; pack and sign saturate
; interleave the low-end 16-bit
; values of the operands
Pack instructions always assume that source operands are signed numbers. The result in the destination
register is always defined by the pack instruction that performs the operation. For example, PACKSSDW
packs each of two signed 32-bit values of two sources into four saturated 16-bit signed values in a destination register. PACKUSWB, on the other hand, packs the four signed 16-bit values of two sources into
eight saturated eight-bit unsigned values in the destination.
5.4.4
Interleaved Pack without Saturation
Example 5-7 is similar to Example 5-6 except that the resulting words are not saturated. In addition, in
order to protect against overflow, only the low order 16 bits of each doubleword are used. Again,
Example 5-7 can be extended in SSE2 to accomplish interleaving eight words without saturation.
Example 5-7. Interleaved Pack without Saturation Code
; Input:
;
MM0
;
MM1
signed source value
signed source value
; Output:
;
MM0
;
;
;
the first and third words contain the
low 16-bits of the doublewords in MM0,
the second and fourth words contain the
low 16-bits of the doublewords in MM1
5-7
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-7. Interleaved Pack without Saturation Code (Contd.)
pslld
pand
por
5.4.5
mm1, 16
; shift the 16 LSB from each of the
; doubleword values to the 16 MSB
; position
mm0, {0,ffff,0,ffff}
; mask to zero the 16 MSB
; of each doubleword value
mm0, mm1 ; merge the two operands
Non-Interleaved Unpack
Unpack instructions perform an interleave merge of the data elements of the destination and source
operands into the destination register.
The following example merges the two operands into destination registers without interleaving. For
example, take two adjacent elements of a packed-word data type in SOURCE1 and place this value in the
low 32 bits of the results. Then take two adjacent elements of a packed-word data type in SOURCE2 and
place this value in the high 32 bits of the results. One of the destination registers will have the combination illustrated in Figure 5-3.
m m /m 64
23
22
mm
21
20
21
13
20
11
12
11
10
10
mm
Figure 5-3. Result of Non-Interleaved Unpack Low in MM0
The other destination register will contain the opposite combination illustrated in Figure 5-4.
m m /m 6 4
23
22
mm
21
20
23
13
22
13
12
11
12
mm
Figure 5-4. Result of Non-Interleaved Unpack High in MM1
5-8
10
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Code in the Example 5-8 unpacks two packed-word sources in a non-interleaved way. The goal is to use
the instruction which unpacks doublewords to a quadword, instead of using the instruction which
unpacks words to doublewords.
Example 5-8. Unpacking Two Packed-word Sources in Non-interleaved Way Code
; Input:
;
;
; Output:
;
;
;
;
movq
punpckldq
MM0
MM1
packed-word source value
packed-word source value
MM0
contains the two low-end words of the
original sources, non-interleaved
contains the two high end words of the
original sources, non-interleaved.
MM2
mm2, mm0
mm0, mm1
punpckhdq mm2, mm1
5.4.6
; copy source1
; replace the two high-end words of MMO with
; two low-end words of MM1;
; leave the two low-end words of MM0 in place
; move two high-end words of MM2 to the two low-end
; words of MM2; place the two high-end words of
; MM1 in two high-end words of MM2
Extract Data Element
The PEXTRW instruction in SSE takes the word in the designated MMX register selected by the two least
significant bits of the immediate value and moves it to the lower half of a 32-bit integer register. See
Figure 5-5 and Example 5-9.
With SSE2, PEXTRW can extract a word from an XMM register to the lower 16 bits of an integer register.
SSE4.1 provides extraction of a byte, word, dword and qword from an XMM register into either a memory
location or integer register.
MM
63
31
X4
X3
0
X2
X1
R32
31
0 ..0
0
X1
OM15163
Figure 5-5. PEXTRW Instruction
5-9
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-9. PEXTRW Instruction Code
; Input:
;
eax
source value
;
immediate value: “0”
; Output:
;
edx
32-bit integer register containing the extracted word in the
;
low-order bits & the high-order bits zero-extended
movq mm0, [eax]
pextrw edx, mm0, 0
5.4.7
Insert Data Element
The PINSRW instruction in SSE loads a word from the lower half of a 32-bit integer register or from
memory and inserts it in an MMX technology destination register at a position defined by the two least
significant bits of the immediate constant. Insertion is done in such a way that three other words from
the destination register are left untouched. See Figure 5-6 and Example 5-10.
With SSE2, PINSRW can insert a word from the lower 16 bits of an integer register or memory into an
XMM register. SSE4.1 provides insertion of a byte, dword and qword from either a memory location or
integer register into an XMM register.
MM
63
31
X4
X3
0
Y1
X1
R32
31
Y2
0
Y1
OM15164
Figure 5-6. PINSRW Instruction
Example 5-10. PINSRW Instruction Code
; Input:
;
edx
pointer to source value
; Output:
;
mm0
register with new 16-bit value inserted
;
mov
eax, [edx]
pinsrw mm0, eax, 1
5-10
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
If all of the operands in a register are being replaced by a series of PINSRW instructions, it can be useful
to clear the content and break the dependence chain by either using the PXOR instruction or loading the
register. See Example 5-11 and Section 3.5.1.7, “Clearing Registers and Dependency Breaking Idioms.”
Example 5-11. Repeated PINSRW Instruction Code
; Input:
;
;
;
; Output:
;
;
pxor
mov
pinsrw
mov
pinsrw
mov
pinsrw
mov
pinsrw
5.4.8
edx
pointer to structure containing source
values at offsets: of +0, +10, +13, and +24
immediate value: “1”
MMX
register with new 16-bit value inserted
mm0, mm0 ; Breaks dependency on previous value of mm0
eax, [edx]
mm0, eax, 0
eax, [edx+10]
mm0, eax, 1
eax, [edx+13]
mm0, eax, 2
eax, [edx+24]
mm0, eax, 3
Non-Unit Stride Data Movement
SSE4.1 provides instructions to insert a data element from memory into an XMM register, and to extract
a data element from an XMM register into memory directly. Separate instructions are provided to handle
floating-point data and integer byte, word, or dword. These instructions are suited for vectorizing code
that loads/stores non-unit stride data from memory, see Example 5-12.
Example 5-12. Non-Unit Stride Load/Store Using SSE4.1 Instructions
/* Goal: Non-Unit Stride Load Dwords*/
/* Goal: Non-Unit Stride Store Dwords*/
movd xmm0, [addr]
pinsrd xmm0, [addr + stride], 1
pinsrd xmm0, [addr + 2*stride], 2
pinsrd xmm0, [addr + 3*stride], 3
movd [addr], xmm0
pextrd [addr + stride], xmm0, 1
pextrd [addr + 2*stride], xmm0, 2
pextrd [addr + 3*stride], xmm0, 3
Example 5-13 provides two examples: using INSERTPS and PEXTRD to perform gather operations on
floating-point data; using EXTRACTPS and PEXTRD to perform scatter operations on floating-point data.
Example 5-13. Scatter and Gather Operations Using SSE4.1 Instructions
/* Goal: Gather Operation*/
/* Goal: Scatter Operation*/
movd eax, xmm0
movss xmm1, [addr + 4*eax]
pextrd eax, xmm0, 1
insertps xmm1, [addr + 4*eax], 1
pextrd eax, xmm0, 2
insertps xmm1, [addr + 4*eax], 2
pextrd eax, xmm0, 3
insertps xmm1, [addr + 4*eax], 3
movd eax, xmm0
movss [addr + 4*eax], xmm1
pextrd eax, xmm0, 1
extractps [addr + 4*eax], xmm1, 1
pextrd eax, xmm0, 2
extractps [addr + 4*eax], xmm1, 2
pextrd eax, xmm0, 3
extractps [addr + 4*eax], xmm1, 3
5-11
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.4.9
Move Byte Mask to Integer
The PMOVMSKB instruction returns a bit mask formed from the most significant bits of each byte of its
source operand. When used with 64-bit MMX registers, this produces an 8-bit mask, zeroing out the
upper 24 bits in the destination register. When used with 128-bit XMM registers, it produces a 16-bit
mask, zeroing out the upper 16 bits in the destination register.
The 64-bit version of this instruction is shown in Figure 5-7 and Example 5-14.
MM
63
55
47
39
31
23
15
7
0
31
0..0
0..0
7
0
R32
OM15165
Figure 5-7. PMOVSMKB Instruction
Example 5-14. PMOVMSKB Instruction Code
; Input:
;
source value
; Output:
;
32-bit register containing the byte mask in the lower eight bits
;
movq mm0, [edi]
pmovmskb eax, mm0
5.4.10
Packed Shuffle Word for 64-bit Registers
The PSHUFW instruction uses the immediate (IMM8) operand to select between the four words in either
two MMX registers or one MMX register and a 64-bit memory location. SSE2 provides PSHUFLW to shuffle
the lower four words into an XMM register. In addition to the equivalent to the PSHUFW, SSE2 also
provides PSHUFHW to shuffle the higher four words. Furthermore, SSE2 offers PSHUFD to shuffle four
dwords into an XMM register. All of these four PSHUF instructions use an immediate byte to encode the
data path of individual words within the corresponding 8 bytes from source to destination, shown in Table
5-1.
5-12
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Table 5-1. PSHUF Encoding
Bits
Words
1-0
0
3-2
1
5-4
2
7-6
3
5.4.11
Packed Shuffle Word for 128-bit Registers
The PSHUFLW/PSHUFHW instruction performs a full shuffle of any source word field within the low/high
64 bits to any result word field in the low/high 64 bits, using an 8-bit immediate operand; other high/low
64 bits are passed through from the source operand.
PSHUFD performs a full shuffle of any double-word field within the 128-bit source to any double-word
field in the 128-bit result, using an 8-bit immediate operand.
No more than 3 instructions, using PSHUFLW/PSHUFHW/PSHUFD, are required to implement many
common data shuffling operations. Broadcast, Swap, and Reverse are illustrated in Example 5-15 and
Example 5-16.
Example 5-15. Broadcast a Word Across XMM, Using 2 SSE2 Instructions
/* Goal: Broadcast the value from word 5 to all words */
/* Instruction
Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFHW (3,2,1,1)| 7| 6| 5| 5| 3| 2| 1| 0|
PSHUFD (2,2,2,2) | 5| 5| 5| 5| 5| 5| 5| 5|
Example 5-16. Swap/Reverse words in an XMM, Using 3 SSE2 Instructions
/* Goal: Swap the values in word 6 and word 1 */
/* Instruction
Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
/* Goal: Reverse the order of the words */
/* Instruction
Result */
| 7| 6| 5| 4| 3| 2| 1| 0|
PSHUFD (3,0,1,2) | 7| 6| 1| 0| 3| 2| 5| 4|
PSHUFLW (0,1,2,3)| 7| 6| 5| 4| 0| 1| 2| 3|
PSHUFHW (3,1,2,0)| 7| 1| 6| 0| 3| 2| 5| 4|
PSHUFHW (0,1,2,3)| 4| 5| 6| 7| 0| 1| 2| 3|
PSHUFD (3,0,1,2) | 7| 1| 5| 4| 3| 2| 6| 0|
PSHUFD (1,0,3,2) | 0| 1| 2| 3| 4| 5| 6| 7|
5.4.12
Shuffle Bytes
SSSE3 provides PSHUFB; this instruction carries out byte manipulation within a 16 byte range. PSHUFB
can replace up to 12 other instructions: including SHIFT, OR, AND and MOV.
Use PSHUFB if the alternative uses 5 or more instructions.
5-13
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.4.13
Conditional Data Movement
SSE4.1 provides two packed blend instructions on byte and word data elements in 128-bit operands.
Packed blend instructions conditionally copies data elements from selected positions in the source to the
corresponding data element using a mask specified by an immediate control byte or an implied XMM
register (XMM0). The mask can be generated by a packed compare instruction for example. Thus packed
blend instructions are most useful for vectorizing conditional flows within a loop and can be more efficient
than inserting single element one at a time for some situations.
5.4.14
Unpacking/interleaving 64-bit Data in 128-bit Registers
The PUNPCKLQDQ/PUNPCHQDQ instructions interleave the low/high-order 64-bits of the source operand
and the low/high-order 64-bits of the destination operand. It then writes the results to the destination
register.
The high/low-order 64-bits of the source operands are ignored.
5.4.15
Data Movement
There are two additional instructions to enable data movement from 64-bit SIMD integer registers to
128-bit SIMD registers.
The MOVQ2DQ instruction moves the 64-bit integer data from an MMX register (source) to a 128-bit
destination register. The high-order 64 bits of the destination register are zeroed-out.
The MOVDQ2Q instruction moves the low-order 64-bits of integer data from a 128-bit source register to
an MMX register (destination).
5.4.16
Conversion Instructions
SSE provides Instructions to support 4-wide conversion of single-precision data to/from double-word
integer data. Conversions between double-precision data to double-word integer data have been added
in SSE2.
SSE4.1 provides 4 rounding instructions to convert floating-point values to integer values with rounding
control specified in a more flexible manner and independent of the rounding control in MXCSR. The
integer values produced by ROUNDxx instructions are maintained as floating-point data.
SSE4.1 also provides instructions to convert integer data from:
•
Packed bytes to packed word/dword/qword format using either sign extension or zero extension.
•
Packed words to packed dword/qword format using either sign extension or zero extension.
•
Packed dword to packed qword format using either sign extension or zero extension.
5.5
GENERATING CONSTANTS
SIMD integer instruction sets do not have instructions that will load immediate constants to the SIMD
registers.
The following code segments generate frequently used constants in the SIMD register. These examples
can also be extended in SSE2 by substituting MMX with XMM registers. See Example 5-17.
5-14
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-17. Generating Constants
pxor
mm0, mm0
pcmpeq mm1, mm1
; generate a zero register in MM0
; Generate all 1's in register MM1,
; which is -1 in each of the packed
; data type fields
pxor
mm0, mm0
pcmpeq mm1, mm1
psubb mm0, mm1 [psubw mm0, mm1] (psubd mm0, mm1)
; three instructions above generate
; the constant 1 in every
; packed-byte [or packed-word]
; (or packed-dword) field
pcmpeq mm1, mm1
psrlw mm1, 16-n(psrld mm1, 32-n)
; two instructions above generate
; the signed constant 2n–1 in every
; packed-word (or packed-dword) field
pcmpeq mm1, mm1
psllw mm1, n (pslld mm1, n)
; two instructions above generate
; the signed constant -2n in every
; packed-word (or packed-dword) field
NOTE
Because SIMD integer instruction sets do not support shift instructions for bytes, 2n–1
and -2n are relevant only for packed words and packed doublewords.
5.6
BUILDING BLOCKS
This section describes instructions and algorithms which implement common code building blocks.
5.6.1
Absolute Difference of Unsigned Numbers
Example 5-18 computes the absolute difference of two unsigned numbers. It assumes an unsigned
packed-byte data type.
Here, we make use of the subtract instruction with unsigned saturation. This instruction receives
UNSIGNED operands and subtracts them with UNSIGNED saturation. This support exists only for packed
bytes and packed words, not for packed doublewords.
Example 5-18. Absolute Difference of Two Unsigned Numbers
; Input:
;
MM0 source operand
;
MM1 source operand
; Output:
;
MM0 absolute difference of the unsigned operands
5-15
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-18. Absolute Difference of Two Unsigned Numbers (Contd.)
movq mm2, mm0
psubusbmm0, mm1
psubusbmm1, mm2
por
mm0, mm1
; make a copy of mm0
; compute difference one way
; compute difference the other way
; OR them together
This example will not work if the operands are signed. Note that PSADBW may also be used in some situations. See Section 5.6.9 for details.
5.6.2
Absolute Difference of Signed Numbers
Example 5-19 computes the absolute difference of two signed numbers using SSSE3 instruction PABSW.
This sequence is more efficient than using previous generation of SIMD instruction extensions.
Example 5-19. Absolute Difference of Signed Numbers
;Input:
;
XMM0 signed source operand
;
XMM1 signed source operand
;Output:
;
XMM1absolute difference of the unsigned operands
psubw xmm0, xmm1 ; subtract words
pabsw xmm1, xmm0 ; results in XMM1
5.6.3
Absolute Value
Example 5-20 show an MMX code sequence to compute
signed words to be the operands.
|X|, where X is signed. This example assumes
With SSSE3, this sequence of three instructions can be replaced by the PABSW instruction. Additionally,
SSSE3 provides a 128-bit version using XMM registers and supports byte, word and doubleword granularity.
Example 5-20. Computing Absolute Value
; Input:
;
MM0
; Output:
;
MM1
pxor
mm1, mm1
psubw mm1, mm0
pmaxswmm1, mm0
signed source operand
ABS(MMO)
; set mm1 to all zeros
; make each mm1 word contain the
; negative of each mm0 word
; mm1 will contain only the positive
; (larger) values - the absolute value
NOTE
The absolute value of the most negative number (that is, 8000H for 16-bit) cannot be
represented using positive numbers. This algorithm will return the original value for the
absolute value (8000H).
5-16
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.6.4
Pixel Format Conversion
SSSE3 provides the PSHUFB instruction to carry out byte manipulation within a 16-byte range. PSHUFB
can replace a set of up to 12 other instruction, including SHIFT, OR, AND and MOV.
Use PSHUFB if the alternative code uses 5 or more instructions. Example 5-21 shows the basic form of
conversion of color pixel formats.
Example 5-21. Basic C Implementation of RGBA to BGRA Conversion
Standard C Code:
struct RGBA{BYTE r,g,b,a;};
struct BGRA{BYTE b,g,r,a;};
void BGRA_RGBA_Convert(BGRA *source, RGBA *dest, int num_pixels)
{
for(int i = 0; i < num_pixels; i++){
dest[i].r = source[i].r;
dest[i].g = source[i].g;
dest[i].b = source[i].b;
dest[i].a = source[i].a;
}
}
Example 5-22 and Example 5-23 show SSE2 code and SSSE3 code for pixel format conversion. In the
SSSE3 example, PSHUFB replaces six SSE2 instructions.
Example 5-22. Color Pixel Format Conversion Using SSE2
; Optimized for SSE2
mov esi, src
mov edi, dest
mov ecx, iterations
movdqa xmm0, ag_mask //{0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff}
movdqa xmm5, rb_mask //{ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0,ff,0}
mov eax, remainder
convert16Pixs: // 16 pixels, 64 byte per iteration
movdqa xmm1, [esi] // xmm1 = [r3g3b3a3,r2g2b2a2,r1g1b1a1,r0g0b0a0]
movdqa xmm2, xmm1
movdqa xmm7, xmm1
//xmm7 abgr
psrld xmm2, 16
//xmm2 00ab
pslld xmm1, 16
//xmm1 gr00
por xmm1, xmm2
pand xmm7, xmm0
pand xmm1, xmm5
por xmm1, xmm7
movdqa [edi], xmm1
//xmm1 grab
//xmm7 a0g0
//xmm1 0r0b
//xmm1 argb
5-17
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-22. Color Pixel Format Conversion Using SSE2 (Contd.)
//repeats for another 3*16 bytes
…
add
add
sub
jnz
esi, 64
edi, 64
ecx, 1
convert16Pixs
Example 5-23. Color Pixel Format Conversion Using SSSE3
; Optimized for SSSE3
mov esi, src
mov edi, dest
mov ecx, iterations
movdqa xmm0, _shufb
// xmm0 = [15,12,13,14,11,8,9,10,7,4,5,6,3,0,1,2]
mov
eax, remainder
convert16Pixs: // 16 pixels, 64 byte per iteration
movdqa xmm1, [esi]
// xmm1 = [r3g3b3a3,r2g2b2a2,r1g1b1a1,r0g0b0a0]
movdqa xmm2, [esi+16]
pshufb xmm1, xmm0
// xmm1 = [b3g3r3a3,b2g2r2a2,b1g1r1a1,b0g0r0a0]
movdqa [edi], xmm1
//repeats for another 3*16 bytes
…
add
add
sub
jnz
5.6.5
esi, 64
edi, 64
ecx, 1
convert16Pixs
Endian Conversion
The PSHUFB instruction can also be used to reverse byte ordering within a doubleword. It is more efficient than traditional techniques, such as BSWAP.
Example 5-24 (a) shows the traditional technique using four BSWAP instructions to reverse the bytes
within a DWORD. Each BSWAP requires executing two micro-ops. In addition, the code requires 4 loads
and 4 stores for processing 4 DWORDs of data.
Example 5-24 (b) shows an SSSE3 implementation of endian conversion using PSHUFB. The reversing of
four DWORDs requires one load, one store, and PSHUFB.
On Intel Core microarchitecture, reversing 4 DWORDs using PSHUFB can be approximately twice as fast
as using BSWAP.
5-18
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-24. Big-Endian to Little-Endian Conversion
;;(a) Using BSWAP
lea eax, src
lea ecx, dst
mov edx, elCount
start:
mov edi, [eax]
mov esi, [eax+4]
bswap edi
mov ebx, [eax+8]
;; (b) Using PSHUFB
__declspec(align(16)) BYTE bswapMASK[16] =
{3,2,1,0, 7,6,5,4, 11,10,9,8, 15,14,13,12};
lea eax, src
lea ecx, dst
mov edx, elCount
movaps xmm7, bswapMASK
start:
movdqa xmm0, [eax]
bswap esi
mov ebp, [eax+12]
mov [ecx], edi
mov [ecx+4], esi
bswap ebx
mov [ecx+8], ebx
bswap ebp
mov [ecx+12], ebp
pshufb xmm0, xmm7
movdqa [ecx], xmm0
add eax, 16
add ecx, 16
sub edx, 4
jnz start
add eax, 16
add ecx, 16
sub edx, 4
jnz start
5.6.6
Clipping to an Arbitrary Range [High, Low]
This section explains how to clip a values to a range [HIGH, LOW]. Specifically, if the value is less than
LOW or greater than HIGH, then clip to LOW or HIGH, respectively. This technique uses the packed-add
and packed-subtract instructions with saturation (signed or unsigned), which means that this technique
can only be used on packed-byte and packed-word data types.
The examples in this section use the constants PACKED_MAX and PACKED_MIN and show operations on
word values. For simplicity, we use the following constants (corresponding constants are used in case the
operation is done on byte values):
PACKED_MAX equals 0X7FFF7FFF7FFF7FFF
PACKED_MIN equals 0X8000800080008000
PACKED_LOW contains the value LOW in all four words of the packed-words data type
PACKED_HIGH contains the value HIGH in all four words of the packed-words data type
PACKED_USMAX all values equal 1
HIGH_US adds the HIGH value to all data elements (4 words) of PACKED_MIN
LOW_US adds the LOW value to all data elements (4 words) of PACKED_MIN
5.6.6.1
Highly Efficient Clipping
For clipping signed words to an arbitrary range, the PMAXSW and PMINSW instructions may be used. For
clipping unsigned bytes to an arbitrary range, the PMAXUB and PMINUB instructions may be used.
5-19
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-25 shows how to clip signed words to an arbitrary range; the code for clipping unsigned bytes
is similar.
Example 5-25. Clipping to a Signed Range of Words [High, Low]
; Input:
;
MM0
signed source operands
; Output:
;
MM0
signed words clipped to the signed
;
range [high, low]
pminsw mm0, packed_high
pmaxswmm0, packed_low
With SSE4.1, Example 5-25 can be easily extended to clip signed bytes, unsigned words, signed and
unsigned dwords.
Example 5-26. Clipping to an Arbitrary Signed Range [High, Low]
; Input:
;
MM0
; Output:
;
MM1
;
signed source operands
signed operands clipped to the unsigned
range [high, low]
paddw mm0, packed_min
; add with no saturation
; 0x8000 to convert to unsigned
padduswmm0, (packed_usmax - high_us)
; in effect this clips to high
psubuswmm0, (packed_usmax - high_us + low_us)
; in effect this clips to low
paddw mm0, packed_low
; undo the previous two offsets
The code above converts values to unsigned numbers first and then clips them to an unsigned range. The
last instruction converts the data back to signed data and places the data within the signed range.
Conversion to unsigned data is required for correct results when (High - Low) < 0X8000. If (High - Low)
>= 0X8000, simplify the algorithm as in Example 5-27.
Example 5-27. Simplified Clipping to an Arbitrary Signed Range
; Input:
; Output:
;
paddssw
MM0
MM1
signed source operands
signed operands clipped to the unsigned
range [high, low]
mm0, (packed_max - packed_high)
; in effect this clips to high
psubssw mm0, (packed_usmax - packed_high + packed_low)
; clips to low
paddw
mm0, low
; undo the previous two offsets
This algorithm saves a cycle when it is known that (High - Low) >= 0x8000. The three-instruction algorithm does not work when (High - Low) < 0x8000 because 0xffff minus any number < 0x8000 will yield
a number greater in magnitude than 0x8000 (which is a negative number).
When the second instruction, psubssw MM0, (0xffff - High + Low) in the three-step algorithm
(Example 5-27) is executed, a negative number is subtracted. The result of this subtraction causes the
values in MM0 to be increased instead of decreased, as should be the case, and an incorrect answer is
generated.
5-20
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.6.6.2
Clipping to an Arbitrary Unsigned Range [High, Low]
Example 5-28 clips an unsigned value to the unsigned range [High, Low]. If the value is less than low or
greater than high, then clip to low or high, respectively. This technique uses the packed-add and packedsubtract instructions with unsigned saturation, thus the technique can only be used on packed-bytes and
packed-words data types.
Figure 5-28 illustrates operation on word values.
Example 5-28. Clipping to an Arbitrary Unsigned Range [High, Low]
; Input:
;
; Output:
;
;
paddusw
psubusw
paddw
5.6.7
MM0
unsigned source operands
MM1
unsigned operands clipped to the unsigned
range [HIGH, LOW]
mm0, 0xffff - high
; in effect this clips to high
mm0, (0xffff - high + low)
; in effect this clips to low
mm0, low
; undo the previous two offsets
Packed Max/Min of Byte, Word and Dword
The PMAXSW instruction returns the maximum between four signed words in either of two SIMD registers, or one SIMD register and a memory location.
The PMINSW instruction returns the minimum between the four signed words in either of two SIMD
registers, or one SIMD register and a memory location.
The PMAXUB instruction returns the maximum between the eight unsigned bytes in either of two SIMD
registers, or one SIMD register and a memory location.
The PMINUB instruction returns the minimum between the eight unsigned bytes in either of two SIMD
registers, or one SIMD register and a memory location.
SSE2 extended PMAXSW/PMAXUB/PMINSW/PMINUB to 128-bit operations. SSE4.1 adds 128-bit operations for signed bytes, unsigned word, signed and unsigned dword.
5.6.8
Packed Multiply Integers
The PMULHUW/PMULHW instruction multiplies the unsigned/signed words in the destination operand
with the unsigned/signed words in the source operand. The high-order 16 bits of the 32-bit intermediate
results are written to the destination operand. The PMULLW instruction multiplies the signed words in the
destination operand with the signed words in the source operand. The low-order 16 bits of the 32-bit
intermediate results are written to the destination operand.
SSE2 extended PMULHUW/PMULHW/PMULLW to 128-bit operations and adds PMULUDQ.
The PMULUDQ instruction performs an unsigned multiply on the lower pair of double-word operands
within 64-bit chunks from the two sources; the full 64-bit result from each multiplication is returned to
the destination register.
This instruction is added in both a 64-bit and 128-bit version; the latter performs 2 independent operations, on the low and high halves of a 128-bit register.
SSE4.1 adds 128-bit operations of PMULDQ and PMULLD. The PMULLD instruction multiplies the signed
dwords in the destination operand with the signed dwords in the source operand. The low-order 32 bits
of the 64-bit intermediate results are written to the destination operand. The PMULDQ instruction multiplies the two low-order, signed dwords in the destination operand with the two low-order, signed dwords
in the source operand and stores two 64-bit results in the destination operand.
5-21
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.6.9
Packed Sum of Absolute Differences
The PSADBW instruction computes the absolute value of the difference of unsigned bytes for either two
SIMD registers, or one SIMD register and a memory location. The differences of 8 pairs of unsigned bytes
are then summed to produce a word result in the lower 16-bit field, and the upper three words are set to
zero. With SSE2, PSADBW is extended to compute two word results.
The subtraction operation presented above is an absolute difference. That is, T = ABS(X-Y). Byte values
are stored in temporary space, all values are summed together, and the result is written to the lower
word of the destination register.
Motion estimation involves searching reference frames for best matches. Sum absolute difference (SAD)
on two blocks of pixels is a common ingredient in video processing algorithms to locate matching blocks
of pixels. PSADBW can be used as building blocks for finding best matches by way of calculating SAD
results on 4x4, 8x4, 8x8 blocks of pixels.
5.6.10
MPSADBW and PHMINPOSUW
The MPSADBW instruction in SSE4.1 performs eight SAD operations. Each SAD operation produces a
word result from 4 pairs of unsigned bytes. With 8 SAD result in an XMM register, PHMINPOSUM can help
search for the best match between eight 4x4 pixel blocks.
For motion estimation algorithms, MPSADBW is likely to improve over PSADBW in several ways:
•
Simplified data movement to construct packed data format for SAD computation on pixel blocks.
•
Higher throughput in terms of SAD results per iteration (less iteration required per frame).
•
MPSADBW results are amenable to efficient search using PHMINPOSUW.
Examples of MPSADBW vs. PSADBW for 4x4 and 8x8 block search can be found in the white paper listed
in the reference section of Chapter 1.
5.6.11
Packed Average (Byte/Word)
The PAVGB and PAVGW instructions add the unsigned data elements of the source operand to the
unsigned data elements of the destination register, along with a carry-in. The results of the addition are
then independently shifted to the right by one bit position. The high order bits of each element are filled
with the carry bits of the corresponding sum.
The destination operand is an SIMD register. The source operand can either be an SIMD register or a
memory operand.
The PAVGB instruction operates on packed unsigned bytes and the PAVGW instruction operates on
packed unsigned words.
5.6.12
Complex Multiply by a Constant
Complex multiplication is an operation which requires four multiplications and two additions. This is
exactly how the PMADDWD instruction operates. In order to use this instruction, you need to format the
data into multiple 16-bit values. The real and imaginary components should be 16-bits each. Consider
Example 5-29, which assumes that the 64-bit MMX registers are being used:
•
Let the input data be DR and DI, where DR is real component of the data and DI is imaginary
component of the data.
•
Format the constant complex coefficients in memory as four 16-bit values [CR -CI CI CR]. Remember
to load the values into the MMX register using MOVQ.
•
The real component of the complex product is PR = DR*CR - DI*CI and the imaginary component of
the complex product is PI = DR*CI + DI*CR.
5-22
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
•
The output is a packed doubleword. If needed, a pack instruction can be used to convert the result to
16-bit (thereby matching the format of the input).
Example 5-29. Complex Multiply by a Constant
; Input:
;
;
;
; Output:
;
;
punpckldq
pmaddwd
5.6.13
MM0
MM1
complex value, Dr, Di
constant complex coefficient in the form
[Cr -Ci Ci Cr]
MM0
two 32-bit dwords containing [Pr Pi]
mm0, mm0
mm0, mm1
; makes [dr di dr di]
; done, the result is
; [(Dr*Cr-Di*Ci)(Dr*Ci+Di*Cr)]
Packed 64-bit Add/Subtract
The PADDQ/PSUBQ instructions add/subtract quad-word operands within each 64-bit chunk from the two
sources; the 64-bit result from each computation is written to the destination register. Like the integer
ADD/SUB instruction, PADDQ/PSUBQ can operate on either unsigned or signed (two’s complement notation) integer operands.
When an individual result is too large to be represented in 64-bits, the lower 64-bits of the result are
written to the destination operand and therefore the result wraps around. These instructions are added
in both a 64-bit and 128-bit version; the latter performs 2 independent operations, on the low and high
halves of a 128-bit register.
5.6.14
128-bit Shifts
The PSLLDQ/PSRLDQ instructions shift the first operand to the left/right by the number of bytes specified
by the immediate operand. The empty low/high-order bytes are cleared (set to zero).
If the value specified by the immediate operand is greater than 15, then the destination is set to all zeros.
5.6.15
PTEST and Conditional Branch
SSE4.1 offers PTEST instruction that can be used in vectorizing loops with conditional branches. PTEST is
an 128-bit version of the general-purpose instruction TEST. The ZF or CF field of the EFLAGS register are
modified as a result of PTEST.
Example 5-30(a) depicts a loop that requires a conditional branch to handle the special case of divide-byzero. In order to vectorize such loop, any iteration that may encounter divide-by-zero must be treated
outside the vectorizable iterations.
5-23
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-30. Using PTEST to Separate Vectorizable and non-Vectorizable Loop Iterations
(a) /* Loops requiring infrequent exception
handling*/
float a[CNT];
unsigned int i;
for (i=0;i<CNT;i++)
{
if (a[i] != 0.0)
{
a[i] = 1.0f/a[i];
}
else
{
call DivException();
}
}
(b) /* PTEST enables early out to handle infrequent, non-vectorizable
portion*/
xor
eax,eax
movaps xmm7, [all_ones]
xorps
xmm6, xmm6
lp:
movaps xmm0, a[eax]
cmpeqps xmm6, xmm0 ; convert each non-zero to ones
ptest
xmm6, xmm7
jnc zero_present; carry will be set if all 4 were non-zero
movaps xmm1,[_1_0f_]
divps
xmm1, xmm0
movaps a[eax], xmm1
add
eax, 16
cmp
eax, CNT
jnz
lp
jmp
end
zero_present:
// execute one by one, call
// exception when value is zero
Example 5-30(b) shows an assembly sequence that uses PTEST to cause an early-out branch whenever
any one of the four floating-point values in xmm0 is zero. The fall-through path enables the rest of the
floating-point calculations to be vectorized because none of the four values are zero.
5.6.16
Vectorization of Heterogeneous Computations across Loop Iterations
Vectorization techniques on unrolled loops generally rely on repetitive, homogeneous operations
between each loop iteration. Using variable blend instructions, vectorization of heterogeneous operations
across loop iterations may be possible.
Example 5-31(a) depicts a simple heterogeneous loop. The heterogeneous operation and conditional
branch makes simple loop-unrolling techniques infeasible for vectorization.
Example 5-31. Using Variable BLEND to Vectorize Heterogeneous Loops
(a) /* Loops with heterogeneous operation
across iterations*/
float a[CNT];
unsigned int i;
for (i=0;i<CNT;i++)
{
if (a[i] > b[i])
{ a[i] += b[i]; }
else
{ a[i] -= b[i]; }
}
5-24
(b) /* Vectorize Condition Flow with BLENDVPS*/
xor
eax,eax
lp:
movaps xmm0, a[eax]
movaps xmm1, b[eax]
movaps xmm2, xmm0
// compare a and b values
cmpgtps xmm0, xmm1
// xmm3 - will hold -b
movaps xmm3, [SIGN_BIT_MASK]
xorps
xmm3, xmm1
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-31. Using Variable BLEND to Vectorize Heterogeneous Loops (Contd.)
// select values for the add operation,
// true condition produce a+b, false will become a+(-b)
// blend mask is xmm0
blendvps xmm1,xmm3, xmm0
addps
xmm2, xmm1
movaps a[eax], xmm2
add
eax, 16
cmp
eax, CNT
jnz
lp
Example 5-31(b) depicts an assembly sequence that uses BLENDVPS to vectorize the handling of heterogeneous computations occurring across four consecutive loop iterations.
5.6.17
Vectorization of Control Flows in Nested Loops
The PTEST and BLENDVPx instructions can be used as building blocks to vectorize more complex controlflow statements, where each control flow statement is creating a “working” mask used as a predicate of
which the conditional code under the mask will operate.
The Mandelbrot-set map evaluation is useful to illustrate a situation with more complex control flows in
nested loops. The Mandelbrot-set is a set of height values mapped to a 2-D grid. The height value is the
number of Mandelbrot iterations (defined over the complex number space as In = In-12 + I0) needed to
get |In| > 2. It is common to limit the map generation by setting some maximum threshold value of the
height, all other points are assigned with a height equal to the threshold. Example 5-32 shows an
example of Mandelbrot map evaluation implemented in C.
Example 5-32. Baseline C Code for Mandelbrot Set Map Evaluation
#define DIMX (64)
#define DIMY (64)
#define X_STEP (0.5f/DIMX)
#define Y_STEP (0.4f/(DIMY/2))
int map[DIMX][DIMY];
void mandelbrot_C()
{ int i,j;
float x,y;
for (i=0,x=-1.8f;i<DIMX;i++,x+=X_STEP)
{
for (j=0,y=-0.2f;j<DIMY/2;j++,y+=Y_STEP)
{float sx,sy;
int iter = 0;
sx = x;
sy = y;
5-25
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-32. Baseline C Code for Mandelbrot Set Map Evaluation (Contd.)
while (iter < 256)
{
if (sx*sx + sy*sy >= 4.0f)
float old_sx = sx;
sx = x + sx*sx - sy*sy;
sy = y + 2*old_sx*sy;
iter++;
}
map[i][j] = iter;
break;
}
}
}
Example 5-33 shows a vectorized implementation of Mandelbrot map evaluation. Vectorization is not
done on the inner most loop, because the presence of the break statement implies the iteration count will
vary from one pixel to the next. The vectorized version take into account the parallel nature of 2-D,
vectorize over four iterations of Y values of 4 consecutive pixels, and conditionally handles three
scenarios:
•
In the inner most iteration, when all 4 pixels do not reach break condition, vectorize 4 pixels.
•
When one or more pixels reached break condition, use blend intrinsics to accumulate the complex
height vector for the remaining pixels not reaching the break condition and continue the inner
iteration of the complex height vector.
•
When all four pixels reached break condition, exit the inner loop.
Example 5-33. Vectorized Mandelbrot Set Map Evaluation Using SSE4.1 Intrinsics
__declspec(align(16)) float _INIT_Y_4[4] = {0,Y_STEP,2*Y_STEP,3*Y_STEP};
F32vec4 _F_STEP_Y(4*Y_STEP);
I32vec4 _I_ONE_ = _mm_set1_epi32(1);
F32vec4 _F_FOUR_(4.0f);
F32vec4 _F_TWO_(2.0f);;
void mandelbrot_C()
{ int i,j;
F32vec4 x,y;
for (i = 0, x = F32vec4(-1.8f); i < DIMX; i ++, x += F32vec4(X_STEP))
{
for (j = DIMY/2, y = F32vec4(-0.2f) +
*(F32vec4*)_INIT_Y_4; j < DIMY; j += 4, y += _F_STEP_Y)
{
F32vec4 sx,sy;
I32vec4 iter = _mm_setzero_si128();
int scalar_iter = 0;
sx = x;
sy = y;
5-26
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-33. Vectorized Mandelbrot Set Map Evaluation Using SSE4.1 Intrinsics (Contd.)
while (scalar_iter < 256)
{
int mask = 0;
F32vec4 old_sx = sx;
__m128 vmask = _mm_cmpnlt_ps(sx*sx + sy*sy,_F_FOUR_);
// if all data points in our vector are hitting the “exit” condition,
// the vectorized loop can exit
if (_mm_test_all_ones(_mm_castps_si128(vmask)))
break;
(continue)
// if non of the data points are out, we don’t need the extra code which blends the results
if (_mm_test_all_zeros(_mm_castps_si128(vmask),
_mm_castps_si128(vmask)))
{
sx = x + sx*sx - sy*sy;
sy = y + _F_TWO_*old_sx*sy;
iter += _I_ONE_;
}
else
{
// Blended flavour of the code, this code blends values from previous iteration with the values
// from current iteration. Only values which did not hit the “exit” condition are being stored;
// values which are already “out” are maintaining their value
sx = _mm_blendv_ps(x + sx*sx - sy*sy,sx,vmask);
sy = _mm_blendv_ps(y + _F_TWO_*old_sx*sy,sy,vmask);
iter = I32vec4(_mm_blendv_epi8(iter + _I_ONE_,
iter,_mm_castps_si128(vmask)));
}
scalar_iter++;
}
_mm_storeu_si128((__m128i*)&map[i][j],iter);
}
}
}
5.7
MEMORY OPTIMIZATIONS
You can improve memory access using the following techniques:
•
Avoiding partial memory accesses.
•
Increasing the bandwidth of memory fills and video fills.
•
Prefetching data with Streaming SIMD Extensions. See Chapter 7, “Optimizing Cache Usage.”
MMX registers and XMM registers allow you to move large quantities of data without stalling the
processor. Instead of loading single array values that are 8, 16, or 32 bits long, consider loading the
values in a single quadword or double quadword and then incrementing the structure or array pointer
accordingly.
Any data that will be manipulated by SIMD integer instructions should be loaded using either:
•
An SIMD integer instruction that loads a 64-bit or 128-bit operand (for example: MOVQ MM0, M64).
•
The register-memory form of any SIMD integer instruction that operates on a quadword or double
quadword memory operand (for example, PMADDW MM0, M64).
All SIMD data should be stored using an SIMD integer instruction that stores a 64-bit or 128-bit operand
(for example: MOVQ M64, MM0).
5-27
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
The goal of the above recommendations is twofold. First, the loading and storing of SIMD data is more
efficient using the larger block sizes. Second, following the above recommendations helps to avoid
mixing of 8-, 16-, or 32-bit load and store operations with SIMD integer technology load and store operations to the same SIMD data.
This prevents situations in which small loads follow large stores to the same area of memory, or large
loads follow small stores to the same area of memory. The Pentium II, Pentium III, and Pentium 4 processors may stall in such situations. See Chapter 3 for details.
5.7.1
Partial Memory Accesses
Consider a case with a large load after a series of small stores to the same area of memory (beginning at
memory address MEM). The large load stalls in the case shown in Example 5-34.
Example 5-34. A Large Load after a Series of Small Stores (Penalty)
mov
mem, eax
mov
mem + 4, ebx
:
:
movq mm0, mem
; store dword to address “mem"
; store dword to address “mem + 4"
; load qword at address “mem", stalls
MOVQ must wait for the stores to write memory before it can access all data it requires. This stall can also
occur with other data types (for example, when bytes or words are stored and then words or doublewords are read from the same area of memory). When you change the code sequence as shown in
Example 5-35, the processor can access the data without delay.
Example 5-35. Accessing Data Without Delay
movd
mm1, ebx
movd
psllq
mm2, eax
mm1, 32
por
movq
mm1, mm2
mem, mm1
:
:
movq
mm0, mem
; build data into a qword first
; before storing it to memory
; store SIMD variable to “mem" as
; a qword
; load qword SIMD “mem", no stall
Consider a case with a series of small loads after a large store to the same area of memory (beginning at
memory address MEM), as shown in Example 5-36. Most of the small loads stall because they are not
aligned with the store. See Section 3.6.5, “Store Forwarding,” for details.
Example 5-36. A Series of Small Loads After a Large Store
movq
:
:
mov
mov
mem, mm0
; store qword to address “mem"
bx, mem + 2
cx, mem + 4
; load word at “mem + 2" stalls
; load word at “mem + 4" stalls
The word loads must wait for the quadword store to write to memory before they can access the data
they require. This stall can also occur with other data types (for example: when doublewords or words
are stored and then words or bytes are read from the same area of memory).
5-28
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
When you change the code sequence as shown in Example 5-37, the processor can access the data
without delay.
Example 5-37. Eliminating Delay for a Series of Small Loads after a Large Store
movq
:
:
mem, mm0
; store qword to address “mem"
movq
movd
mm1, mem
eax, mm1
; load qword at address “mem"
; transfer “mem + 2" to eax from
; MMX register, not memory
psrlq
shr
movd
mm1, 32
eax, 16
ebx, mm1
and
ebx, 0ffffh
; transfer “mem + 4" to bx from
; MMX register, not memory
These transformations, in general, increase the number of instructions required to perform the desired
operation. For Pentium II, Pentium III, and Pentium 4 processors, the benefit of avoiding forwarding problems outweighs the performance penalty due to the increased number of instructions.
5.7.1.1
Supplemental Techniques for Avoiding Cache Line Splits
Video processing applications sometimes cannot avoid loading data from memory addresses that are not
aligned to 16-byte boundaries. An example of this situation is when each line in a video frame is averaged by shifting horizontally half a pixel.
Example shows a common operation in video processing that loads data from memory address not
aligned to a 16-byte boundary. As video processing traverses each line in the video frame, it experiences
a cache line split for each 64 byte chunk loaded from memory.
Example 5-38. An Example of Video Processing with Cache Line Splits
// Average half-pels horizontally (on // the “x” axis),
// from one reference frame only.
nextLinesLoop:
movdqu xmm0, XMMWORD PTR [edx] // may not be 16B aligned
movdqu xmm0, XMMWORD PTR [edx+1]
movdqu xmm1, XMMWORD PTR [edx+eax]
movdqu xmm1, XMMWORD PTR [edx+eax+1]
pavgbxmm0, xmm1
pavgbxmm2, xmm3
movdqaXMMWORD PTR [ecx], xmm0
movdqaXMMWORD PTR [ecx+eax], xmm2
// (repeat ...)
SSE3 provides an instruction LDDQU for loading from memory address that are not 16-byte aligned.
LDDQU is a special 128-bit unaligned load designed to avoid cache line splits. If the address of the load
is aligned on a 16-byte boundary, LDQQU loads the 16 bytes requested. If the address of the load is not
aligned on a 16-byte boundary, LDDQU loads a 32-byte block starting at the 16-byte aligned address
immediately below the address of the load request. It then provides the requested 16 bytes. If the
5-29
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
address is aligned on a 16-byte boundary, the effective number of memory requests is implementation
dependent (one, or more).
LDDQU is designed for programming usage of loading data from memory without storing modified data
back to the same address. Thus, the usage of LDDQU should be restricted to situations where no storeto-load forwarding is expected. For situations where store-to-load forwarding is expected, use regular
store/load pairs (either aligned or unaligned based on the alignment of the data accessed).
Example 5-39. Video Processing Using LDDQU to Avoid Cache Line Splits
// Average half-pels horizontally (on // the “x” axis),
// from one reference frame only.
nextLinesLoop:
lddqu xmm0, XMMWORD PTR [edx] // may not be 16B aligned
lddqu xmm0, XMMWORD PTR [edx+1]
lddqu xmm1, XMMWORD PTR [edx+eax]
lddqu xmm1, XMMWORD PTR [edx+eax+1]
pavgbxmm0, xmm1
pavgbxmm2, xmm3
movdqaXMMWORD PTR [ecx], xmm0 //results stored elsewhere
movdqaXMMWORD PTR [ecx+eax], xmm2
// (repeat ...)
5.7.2
Increasing Bandwidth of Memory Fills and Video Fills
It is beneficial to understand how memory is accessed and filled. A memory-to-memory fill (for example
a memory-to-video fill) is defined as a 64-byte (cache line) load from memory which is immediately
stored back to memory (such as a video frame buffer).
The following are guidelines for obtaining higher bandwidth and shorter latencies for sequential memory
fills (video fills). These recommendations are relevant for all Intel architecture processors with MMX
technology and refer to cases in which the loads and stores do not hit in the first- or second-level cache.
5.7.2.1
Increasing Memory Bandwidth Using the MOVDQ Instruction
Loading any size data operand will cause an entire cache line to be loaded into the cache hierarchy. Thus,
any size load looks more or less the same from a memory bandwidth perspective. However, using many
smaller loads consumes more microarchitectural resources than fewer larger stores. Consuming too
many resources can cause the processor to stall and reduce the bandwidth that the processor can
request of the memory subsystem.
Using MOVDQ to store the data back to UC memory (or WC memory in some cases) instead of using 32bit stores (for example, MOVD) will reduce by three-quarters the number of stores per memory fill cycle.
As a result, using the MOVDQ in memory fill cycles can achieve significantly higher effective bandwidth
than using MOVD.
5.7.2.2
Increasing Memory Bandwidth by Loading and Storing to and from the Same DRAM
Page
DRAM is divided into pages, which are not the same as operating system (OS) pages. The size of a DRAM
page is a function of the total size of the DRAM and the organization of the DRAM. Page sizes of several
Kilobytes are common. Like OS pages, DRAM pages are constructed of sequential addresses. Sequential
memory accesses to the same DRAM page have shorter latencies than sequential accesses to different
DRAM pages.
In many systems the latency for a page miss (that is, an access to a different page instead of the page
previously accessed) can be twice as large as the latency of a memory page hit (access to the same page
5-30
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
as the previous access). Therefore, if the loads and stores of the memory fill cycle are to the same DRAM
page, a significant increase in the bandwidth of the memory fill cycles can be achieved.
5.7.2.3
Increasing UC and WC Store Bandwidth by Using Aligned Stores
Using aligned stores to fill UC or WC memory will yield higher bandwidth than using unaligned stores. If
a UC store or some WC stores cross a cache line boundary, a single store will result in two transaction on
the bus, reducing the efficiency of the bus transactions. By aligning the stores to the size of the stores,
you eliminate the possibility of crossing a cache line boundary, and the stores will not be split into separate transactions.
5.7.3
Reverse Memory Copy
Copying blocks of memory from a source location to a destination location in reverse order presents a
challenge for software to make the most out of the machines capabilities while avoiding microarchitectural hazards. The basic, un-optimized C code is shown in Example 5-40.
The simple C code in Example 5-40 is sub-optimal, because it loads and stores one byte at a time (even
in situations that hardware prefetcher might have brought data in from system memory to cache).
Example 5-40. Un-optimized Reverse Memory Copy in C
unsigned char* src;
unsigned char* dst;
while (len > 0)
{
*dst-- = *src++;
--len;
}
5-31
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Using MOVDQA or MOVDQU, software can load and store up to 16 bytes at a time but must either ensure
16 byte alignment requirement (if using MOVDQA) or minimize the delays MOVDQU may encounter if
data span across cache line boundary.
(a)
N
0 1 2 3 4 5 6 ...
Source Bytes
16 Byte Aligned
Cache Line boundary
Destination Bytes
(b)
0 1 2 3 4 5 6 ...
N
Source
Destination
Figure 5-8. Data Alignment of Loads and Stores in Reverse Memory Copy
Given the general problem of arbitrary byte count to copy, arbitrary offsets of leading source byte and
destination bytes, address alignment relative to 16 byte and cache line boundaries, these alignment situations can be a bit complicated. Figure 5-8 (a) and (b) depict the alignment situations of reverse memory
copy of N bytes.
The general guidelines for dealing with unaligned loads and stores are (in order of importance):
•
Avoid stores that span cache line boundaries.
•
Minimize the number of loads that span cacheline boundaries.
•
Favor 16-byte aligned loads and stores over unaligned versions.
In Figure 5-8 (a), the guidelines above can be applied to the reverse memory copy problem as follows:
1. Peel off several leading destination bytes until it aligns on 16 Byte boundary, then the ensuing
destination bytes can be written to using MOVAPS until the remaining byte count falls below 16 bytes.
2. After the leading source bytes have been peeled (corresponding to step 1 above), the source
alignment in Figure 5-8 (a) allows loading 16 bytes at a time using MOVAPS until the remaining byte
count falls below 16 bytes.
Switching the byte ordering of each 16 bytes of data can be accomplished by a 16-byte mask with
PSHUFB. The pertinent code sequence is shown in Example 5-41.
5-32
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-41. Using PSHUFB to Reverse Byte Ordering 16 Bytes at a Time
__declspec(align(16)) static const unsigned char BswapMask[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
mov esi, src
mov edi, dst
mov ecx, len
movaps xmm7, BswapMask
start:
movdqa xmm0, [esi]
pshufb xmm0, xmm7
movdqa [edi-16], xmm0
sub edi, 16
add esi, 16
sub ecx, 16
cmp ecx, 32
jae start
//handle left-overs
In Figure 5-8 (b), we also start with peeling the destination bytes:
1. Peel off several leading destination bytes until it aligns on 16 Byte boundary, then the ensuing
destination bytes can be written to using MOVAPS until the remaining byte count falls below 16 bytes.
However, the remaining source bytes are not aligned on 16 byte boundaries, replacing MOVDQA with
MOVDQU for loads will inevitably run into cache line splits.
2. To achieve higher data throughput than loading unaligned bytes with MOVDQU, the 16 bytes of data
targeted to each of 16 bytes of aligned destination addresses can be assembled using two aligned
loads. This technique is illustrated in Figure 5-9.
0 1 2 3 4 5 6 ...
N
Step 1:Pell off
leading bytes
Step1: Pell off
leading bytes
Source Bytes
R
PO
PO
R
Step2 : Load 2
aligned 16-Byte
Blocks
Reverse byte ord
er In register, Sto
re
aligned 16 bytes
16 Byte Aligned
Cache Line boundary
Destination Bytes
Figure 5-9. A Technique to Avoid Cacheline Split Loads in Reverse Memory Copy Using Two Aligned
Loads
5-33
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.8
CONVERTING FROM 64-BIT TO 128-BIT SIMD INTEGERS
SSE2 defines a superset of 128-bit integer instructions currently available in MMX technology; the operation of the extended instructions remains. The superset simply operates on data that is twice as wide.
This simplifies porting of 64-bit integer applications. However, there are few considerations:
•
Computation instructions which use a memory operand that may not be aligned to a 16-byte
boundary must be replaced with an unaligned 128-bit load (MOVDQU) followed by the same
computation operation that uses instead register operands.
Use of 128-bit integer computation instructions with memory operands that are not 16-byte aligned
will result in a #GP. Unaligned 128-bit loads and stores are not as efficient as corresponding aligned
versions; this fact can reduce the performance gains when using the 128-bit SIMD integer
extensions.
•
General guidelines on the alignment of memory operands are:
— The greatest performance gains can be achieved when all memory streams are 16-byte aligned.
— Reasonable performance gains are possible if roughly half of all memory streams are 16-byte
aligned and the other half are not.
— Little or no performance gain may result if all memory streams are not aligned to 16-bytes. In
this case, use of the 64-bit SIMD integer instructions may be preferable.
•
Loop counters need to be updated because each 128-bit integer instruction operates on twice the
amount of data as its 64-bit integer counterpart.
•
Extension of the PSHUFW instruction (shuffle word across 64-bit integer operand) across a full 128bit operand is emulated by a combination of the following instructions: PSHUFHW, PSHUFLW, and
PSHUFD.
•
Use of the 64-bit shift by bit instructions (PSRLQ, PSLLQ) are extended to 128 bits by:
— Use of PSRLQ and PSLLQ, along with masking logic operations.
— A Code sequence rewritten to use the PSRLDQ and PSLLDQ instructions (shift double quad-word
operand by bytes).
5.8.1
SIMD Optimizations and Microarchitectures
Pentium M, Intel Core Solo and Intel Core Duo processors have a different microarchitecture than Intel
NetBurst microarchitecture. The following sections discuss optimizing SIMD code that targets Intel Core
Solo and Intel Core Duo processors.
On Intel Core Solo and Intel Core Duo processors, LDDQU behaves identically to movdqu by loading 16
bytes of data irrespective of address alignment.
5.8.1.1
Packed SSE2 Integer versus MMX Instructions
In general, 128-bit SIMD integer instructions should be favored over 64-bit MMX instructions on Intel
Core Solo and Intel Core Duo processors. This is because:
•
Improved decoder bandwidth and more efficient micro-op flows relative to the Pentium M processor.
•
Wider width of the XMM registers can benefit code that is limited by either decoder bandwidth or
execution latency. XMM registers can provide twice the space to store data for in-flight execution.
Wider XMM registers can facilitate loop-unrolling or in reducing loop overhead by halving the number
of loop iterations.
In microarchitectures prior to Intel Core microarchitecture, execution throughput of 128-bit SIMD integration operations is basically the same as 64-bit MMX operations. Some shuffle/unpack/shift operations
do not benefit from the front end improvements. The net impact of using 128-bit SIMD integer instruction on Intel Core Solo and Intel Core Duo processors is likely to be slightly positive overall, but there
may be a few situations where their use will generate an unfavorable performance impact.
5-34
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Intel Core microarchitecture generally executes 128-bit SIMD instructions more efficiently than previous
microarchitectures in terms of latency and throughput, many of the limitations specific to Intel Core Duo,
Intel Core Solo processors do not apply. The same is true of Intel Core microarchitecture relative to Intel
NetBurst microarchitectures.
Enhanced Intel Core microarchitecture provides even more powerful 128-bit SIMD execution capabilities
and more comprehensive sets of SIMD instruction extensions than Intel Core microarchitecture. The
integer SIMD instructions offered by SSE4.1 operates on 128-bit XMM register only. All of these highly
encourages software to favor 128-bit vectorizable code to take advantage of processors based on
Enhanced Intel Core microarchitecture and Intel Core microarchitecture.
5.8.1.2
Work-around for False Dependency Issue
In processor based on Intel microarchitecture code name Nehalem, using PMOVSX and PMOVZX instructions to combine data type conversion and data movement in the same instruction will create a falsedependency due to hardware causes. A simple work-around to avoid the false dependency issue is to use
PMOVSX, PMOVZX instruction solely for data type conversion and issue separate instruction to move data
to destination or from origin.
Example 5-42. PMOVSX/PMOVZX Work-around to Avoid False Dependency
#issuing the instruction below will create a false dependency on xmm0
pmovzxbd xmm0, dword ptr [eax]
// the above instruction may be blocked if xmm0 are updated by other instructions in flight
................................................................
#Alternate solution to avoid false dependency
movd xmm0, dword ptr [eax] ; OOO hardware can hoist loads to hide latency
pmovsxbd xmm0, xmm0
5.9
TUNING PARTIALLY VECTORIZABLE CODE
Some loop structured code are more difficult to vectorize than others. Example 5-43 depicts a loop
carrying out table look-up operation and some arithmetic computation.
Example 5-43. Table Look-up Operations in C Code
// pIn1
integer input arrays.
// pOut
integer output array.
// count
size of array.
// LookUpTable integer values.
TABLE_SIZE
size of the look-up table.
for (unsigned i=0; i < count; i++)
{ pOut[i] =
( ( LookUpTable[pIn1[i] % TABLE_SIZE] + pIn1[i] + 17 ) | 17
) % 256;
}
Although some of the arithmetic computations and input/output to data array in each iteration can be
easily vectorizable, but the table look-up via an index array is not. This creates different approaches to
5-35
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
tuning. A compiler can take a scalar approach to execute each iteration sequentially. Hand-tuning of such
loops may use a couple of different techniques to handle the non-vectorizable table look-up operation.
One vectorization technique is to load the input data for four iteration at once, then use SSE2 instruction
to shift out individual index out of an XMM register to carry out table look-up sequentially. The shift technique is depicted by Example 5-44. Another technique is to use PEXTRD in SSE4.1 to extract the index
from an XMM directly and then carry out table look-up sequentially. The PEXTRD technique is depicted by
Example 5-45.
Example 5-44. Shift Techniques on Non-Vectorizable Table Look-up
int modulo[4] = {256-1, 256-1, 256-1, 256-1};
int c[4] = {17, 17, 17, 17};
mov
esi, pIn1
mov
ebx, pOut
mov
ecx, count
mov
edx, pLookUpTablePTR
movaps xmm6, modulo
movaps xmm5, c
lloop:
// vectorizable multiple consecutive data accesses
movaps
xmm4, [esi]
// read 4 indices from pIn1
movaps
xmm7, xmm4
pand
xmm7, tableSize
//Table look-up is not vectorizable, shift out one data element to look up table one by one
movd
eax, xmm7
// get first index
movd
xmm0, word ptr[edx + eax*4]
psrldq
xmm7, 4
movd
eax, xmm7
// get 2nd index
movd
xmm1, word ptr[edx + eax*4]
psrldq
xmm7, 4
movd
eax, xmm7
// get 3rdindex
movd
xmm2, word ptr[edx + eax*4]
psrldq
xmm7, 4
movd
eax, xmm7
// get fourth index
movd
xmm3, word ptr[edx + eax*4]
//end of scalar part
//packing
movlhps
xmm1,xmm3
psllq
xmm1,32
movlhps
xmm0,xmm2
orps
xmm0,xmm1
//end of packing
(continue)
//Vectorizable computation operations
paddd
xmm0, xmm4 //+pIn1
paddd
xmm0, xmm5 // +17
por
xmm0, xmm5
andps
xmm0, xmm6 //mod
movaps
[ebx], xmm0
//end of vectorizable operation
5-36
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-44. Shift Techniques on Non-Vectorizable Table Look-up (Contd.)
add
add
add
sub
test
jne lloop
ebx, 16
esi, 16
edi, 16
ecx, 1
ecx, ecx
Example 5-45. PEXTRD Techniques on Non-Vectorizable Table Look-up
int modulo[4] = {256-1, 256-1, 256-1, 256-1};
int c[4] = {17, 17, 17, 17};
mov
esi, pIn1
mov
ebx, pOut
mov
ecx, count
mov
edx, pLookUpTablePTR
movaps xmm6, modulo
movaps xmm5, c
lloop:
// vectorizable multiple consecutive data accesses
movaps
xmm4, [esi]
// read 4 indices from pIn1
movaps
xmm7, xmm4
pand
xmm7, tableSize
//Table look-up is not vectorizable, extract one data element to look up table one by one
movd
eax, xmm7
// get first index
mov
eax, [edx + eax*4]
movd
xmm0, eax
(continue)
pextrd
eax, xmm7, 1
// extract 2nd index
mov
eax, [edx + eax*4]
pinsrd
xmm0, eax, 1
pextrd
eax, xmm7, 2
// extract 2nd index
mov
eax, [edx + eax*4]
pinsrd
xmm0, eax, 2
pextrd
eax, xmm7, 3
// extract 2nd index
mov
eax, [edx + eax*4]
pinsrd
xmm0, eax, 2
//end of scalar part
//packing not needed
//Vectorizable operations
paddd
xmm0, xmm4 //+pIn1
paddd
xmm0, xmm5 // +17
por
xmm0, xmm5
andps
xmm0, xmm6 //mod
movaps
[ebx], xmm0
5-37
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-45. PEXTRD Techniques on Non-Vectorizable Table Look-up (Contd.)
add
add
add
sub
test
jne lloop
ebx, 16
esi, 16
edi, 16
ecx, 1
ecx, ecx
The effectiveness of these two hand-tuning techniques on partially vectorizable code depends on the
relative cost of transforming data layout format using various forms of pack and unpack instructions.
The shift technique requires additional instructions to pack scalar table values into an XMM to transition
into vectorized arithmetic computations. The net performance gain or loss of this technique will vary with
the characteristics of different microarchitectures. The alternate PEXTRD technique uses less instruction
to extract each index, does not require extraneous packing of scalar data into packed SIMD data format
to begin vectorized arithmetic computation.
5.10
PARALLEL MODE AES ENCRYPTION AND DECRYPTION
To deliver optimal encryption and decryption throughput using AESNI, software can optimize by reordering the computations and working on multiple blocks in parallel. This can speed up encryption (and
decryption) in parallel modes of operation such as ECB, CTR, and CBC-Decrypt (comparing to CBCEncrypt which is serial mode of operation). See details in Recommendation for Block Cipher Modes of
Operation?. The Related Documentation section provides a pointer to this document.
In Intel microarchitecture code name Sandy Bridge, the AES round instructions (AESENC / AESECNLAST
/ AESDEC / AESDECLAST) have a throughput of one cycle and latency of eight cycles. This allows independent AES instructions for multiple blocks to be dispatched every cycle, if data can be provided sufficiently fast. Compared to the prior Intel microarchitecture code name Westmere, where these
instructions have throughput of two cycles and a latency of six cycles, the AES encryption/decryption
throughput can be significantly increased, for parallel modes of operation.
To achieve optimal parallel operation with multiple blocks, write the AES software sequences in a way
that it computes one AES round on multiple blocks, using one Round Key, and then it continues to
compute the subsequent round for multiple blocks, using another Round Key.
For such software optimization, you need to define the number of blocks that are processed in parallel.
In Intel microarchitecture code name Sandy Bridge, the optimal parallelization parameter is eight blocks,
compared to four blocks on prior microarchitecture.
5.10.1
AES Counter Mode of Operation
Example 5-46 is an example of a function that implements the Counter Mode (CTR mode) of operations
while operating on eight blocks in parallel. The following pseudo-code encrypts n data blocks of 16 byte
each (PT[i]):
5-38
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-46. Pseudo-Code Flow of AES Counter Mode Operation
CTRBLK := NONCE || IV || ONE
FOR i := 1 to n-1 DO
CT[i] := PT[i] XOR AES(CTRBLK)
CTRBLK := CTRBLK + 1) % 256;
END
CT[n] := PT[n] XOR TRUNC(AES(CTRBLK)) CTRBLK := NONCE || IV || ONE
FOR i := 1 to n-1 DO
CT[i] := PT[i] XOR AES(CTRBLK)// CT [i] is the i-th ciphetext block
CTRBLK := CTRBLK + 1
END
CT[n]:= PT[n] XOR TRUNC(AES(CTRBLK))
Example 5-47 in the following pages show the assembly implementation of the above code, optimized for
Intel microarchitecture code name Sandy Bridge.
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel
/*****************************************************************************/
/* This function encrypts an input buffer using AES in CTR mode
*/
/* The parameters:
*/
/* const unsigned char *in - pointer to the palintext for encryption or */
/* ciphertextfor decryption
*/
/* unsigned char *out - pointer to the buffer where the encrypted/decrypted*/
/*
data will be stored
*/
/* const unsigned char ivec[8] - 8 bytes of the initialization vector */
/* const unsigned char nonce[4] - 4 bytes of the nonce
*/
/* const unsigned long length - the length of the input in bytes
*/
/* int number_of_rounds - number of AES round. 10 = AES128, 12 = AES192, 14 = AES256 */
/* unsigned char *key_schedule - pointer to the AES key schedule
*/
/*****************************************************************************/
//void AES_128_CTR_encrypt_parallelize_8_blocks_unrolled (
//
const unsigned char *in,
//
unsigned char *out,
//
const unsigned char ivec[8],
//
const unsigned char nonce[4],
//
const unsigned long length,
//
unsigned char *key_schedule)
.align 16,0x90
.align 16
ONE:
.quad 0x00000000,0x00000001
.align 16
FOUR:
.quad 0x00000004,0x00000004
.align 16
EIGHT:
.quad 0x00000008,0x00000008
(continue)
5-39
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
.align 16
TWO_N_ONE:
.quad 0x00000002,0x00000001
.align 16
TWO_N_TWO:
.quad 0x00000002,0x00000002
.align 16
LOAD_HIGH_BROADCAST_AND_BSWAP:
.byte 15,14,13,12,11,10,9,8
.byte 15,14,13,12,11,10,9,8
align 16
BSWAP_EPI_64:
.byte 7,6,5,4,3,2,1,0
.byte 15,14,13,12,11,10,9,8
.globl AES_CTR_encrypt
AES_CTR_encrypt:
# parameter 1: %rdi
# parameter 2: %rsi
# parameter 3: %rdx
# parameter 4: %rcx
# parameter 5: %r8
# parameter 6: %r9
# parameter 7: 8 + %rsp
movq %r8, %r10
movl 8(%rsp), %r12d
shrq $4, %r8
shlq $60, %r10
je
NO_PARTS
addq $1, %r8
NO_PARTS:
movq %r8, %r10
shlq $61, %r10
shrq $61, %r10
pinsrq $1, (%rdx), %xmm0
pinsrd $1, (%rcx), %xmm0
psrldq $4, %xmm0
movdqa %xmm0, %xmm4
pshufb (LOAD_HIGH_BROADCAST_AND_BSWAP), %xmm4
paddq (TWO_N_ONE), %xmm4
movdqa %xmm4, %xmm1
paddq (TWO_N_TWO), %xmm4
movdqa %xmm4, %xmm2
paddq (TWO_N_TWO), %xmm4
movdqa %xmm4, %xmm3
paddq (TWO_N_TWO), %xmm4
pshufb (BSWAP_EPI_64), %xmm1
pshufb (BSWAP_EPI_64), %xmm2
pshufb (BSWAP_EPI_64), %xmm3
pshufb (BSWAP_EPI_64), %xmm4
shrq
$3, %r8
je
REMAINDER
subq $128, %rsi
subq $128, %rdi
(continue)
5-40
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
LOOP:
addq
addq
$128, %rsi
$128, %rdi
movdqa
movdqa
movdqa
movdqa
movdqa
movdqa
movdqa
movdqa
%xmm0, %xmm7
%xmm0, %xmm8
%xmm0, %xmm9
%xmm0, %xmm10
%xmm0, %xmm11
%xmm0, %xmm12
%xmm0, %xmm13
%xmm0, %xmm14
shufpd
shufpd
shufpd
shufpd
shufpd
shufpd
shufpd
shufpd
$2, %xmm1, %xmm7
$0, %xmm1, %xmm8
$2, %xmm2, %xmm9
$0, %xmm2, %xmm10
$2, %xmm3, %xmm11
$0, %xmm3, %xmm12
$2, %xmm4, %xmm13
$0, %xmm4, %xmm14
pshufb
pshufb
pshufb
pshufb
(BSWAP_EPI_64), %xmm1
(BSWAP_EPI_64), %xmm2
(BSWAP_EPI_64), %xmm3
(BSWAP_EPI_64), %xmm4
movdqa (%r9), %xmm5
movdqa 16(%r9), %xmm6
paddq
paddq
paddq
paddq
(EIGHT), %xmm1
(EIGHT), %xmm2
(EIGHT), %xmm3
(EIGHT), %xmm4
pxor
pxor
pxor
pxor
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
pxor
pxor
pxor
pxor
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
pshufb
pshufb
pshufb
pshufb
(BSWAP_EPI_64), %xmm1
(BSWAP_EPI_64), %xmm2
(BSWAP_EPI_64), %xmm3
(BSWAP_EPI_64), %xmm4
(continue)
5-41
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
movdqa 32(%r9), %xmm5
movdqa 48(%r9), %xmm6
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
movdqa 64(%r9), %xmm5
movdqa 80(%r9), %xmm6
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
(continue)
5-42
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
movdqa 96(%r9), %xmm5
movdqa 112(%r9), %xmm6
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
movdqa 128(%r9), %xmm5
movdqa 144(%r9), %xmm6
movdqa 160(%r9), %xmm15
cmp
$12, %r12d
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
jb
LAST
(continue)
5-43
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
movdqa 160(%r9), %xmm5
movdqa 176(%r9), %xmm6
movdqa 192(%r9), %xmm15
cmp
$14, %r12d
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
jb
LAST
movdqa 192(%r9), %xmm5
movdqa 208(%r9), %xmm6
movdqa 224(%r9), %xmm15
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
%xmm5, %xmm7
%xmm5, %xmm8
%xmm5, %xmm9
%xmm5, %xmm10
%xmm5, %xmm11
%xmm5, %xmm12
%xmm5, %xmm13
%xmm5, %xmm14
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
aesenc
LAST:
%xmm6, %xmm7
%xmm6, %xmm8
%xmm6, %xmm9
%xmm6, %xmm10
%xmm6, %xmm11
%xmm6, %xmm12
%xmm6, %xmm13
%xmm6, %xmm14
(continue)
5-44
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
aesenclast %xmm15, %xmm7
aesenclast %xmm15, %xmm8
aesenclast %xmm15, %xmm9
aesenclast %xmm15, %xmm10
aesenclast %xmm15, %xmm11
aesenclast %xmm15, %xmm12
aesenclast %xmm15, %xmm13
aesenclast %xmm15, %xmm14
pxor
pxor
pxor
pxor
pxor
pxor
pxor
pxor
(%rdi), %xmm7
16(%rdi), %xmm8
32(%rdi), %xmm9
48(%rdi), %xmm10
64(%rdi), %xmm11
80(%rdi), %xmm12
96(%rdi), %xmm13
112(%rdi), %xmm14
dec %r8
movdqu %xmm7, (%rsi)
movdqu %xmm8, 16(%rsi)
movdqu %xmm9, 32(%rsi)
movdqu %xmm10, 48(%rsi)
movdqu %xmm11, 64(%rsi)
movdqu %xmm12, 80(%rsi)
movdqu %xmm13, 96(%rsi)
movdqu %xmm14, 112(%rsi)
jne LOOP
addq $128,%rsi
addq $128,%rdi
REMAINDER:
cmp $0, %r10
je END
shufpd $2, %xmm1, %xmm0
IN_LOOP:
movdqa %xmm0, %xmm11
pshufb (BSWAP_EPI_64), %xmm0
pxor (%r9), %xmm11
paddq (ONE), %xmm0
aesenc 16(%r9), %xmm11
aesenc 32(%r9), %xmm11
pshufb (BSWAP_EPI_64), %xmm0
(continue)
5-45
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-47. AES128-CTR Implementation with Eight Block in Parallel (Contd.)
aesenc 48(%r9), %xmm11
aesenc 64(%r9), %xmm11
aesenc 80(%r9), %xmm11
aesenc 96(%r9), %xmm11
aesenc 112(%r9), %xmm11
aesenc 128(%r9), %xmm11
aesenc 144(%r9), %xmm11
movdqa 160(%r9), %xmm2
cmp $12, %r12d
jb IN_LAST
aesenc 160(%r9), %xmm11
aesenc 176(%r9), %xmm11
movdqa 192(%r9), %xmm2
cmp $14, %r12d
jb IN_LAST
aesenc 192(%r9), %xmm11
aesenc 208(%r9), %xmm11
movdqa 224(%r9), %xmm2
IN_LAST:
aesenclast %xmm2, %xmm11
pxor
(%rdi) ,%xmm11
movdqu %xmm11, (%rsi)
addq
$16,%rdi
addq
$16,%rsi
dec
%r10
jne
IN_LOOP
END:
ret
5.10.2
AES Key Expansion Alternative
In Intel microarchitecture code name Sandy Bridge, the throughput of AESKEYGENASSIST is two cycles
with higher latency than the AESENC/AESDEC instructions. Software may consider implementing the
AES key expansion by using the AESENCLAST instruction with the second operand (i.e., the round key)
being the RCON value, duplicated four times in the register. The AESENCLAST instruction performs the
SubBytes step and the xor-with-RCON step, while the ROTWORD step can be done using a PSHUFB
instruction. Following are code examples of AES128 key expansion using either method.
Example 5-48. AES128 Key Expansion
// Use AESKENYGENASSIST
.align 16,0x90
.globl AES_128_Key_Expansion
AES_128_Key_Expansion:
# parameter 1: %rdi
# parameter 2: %rsi
movl $10, 240(%rsi)
movdqu (%rdi), %xmm1
movdqa %xmm1, (%rsi)
(continue)
5-46
// Use AESENCLAST
mask:
.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d
con1:
.long 1,1,1,1
con2:
.long 0x1b,0x1b,0x1b,0x1b
.align 16,0x90
.globl AES_128_Key_Expansion
(continue)
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-48. AES128 Key Expansion (Contd.)
aeskeygenassist $1, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 16(%rsi)
aeskeygenassist $2, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 32(%rsi)
aeskeygenassist $4, %xmm1, %xmm2
ASSISTS:
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 48(%rsi)
aeskeygenassist $8, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 64(%rsi)
aeskeygenassist $16, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 80(%rsi)
aeskeygenassist $32, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 96(%rsi)
aeskeygenassist $64, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 112(%rsi)
aeskeygenassist $0x80, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 128(%rsi)
aeskeygenassist $0x1b, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 144(%rsi)
aeskeygenassist $0x36, %xmm1, %xmm2
call PREPARE_ROUNDKEY_128
movdqa %xmm1, 160(%rsi)
ret
PREPARE_ROUNDKEY_128:
pshufd $255, %xmm2, %xmm2
movdqa %xmm1, %xmm3
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pxor %xmm2, %xmm1
ret
AES_128_Key_Expansion:
# parameter 1: %rdi
# parameter 2: %rsi
movdqu (%rdi), %xmm1
movdqa %xmm1, (%rsi)
movdqa %xmm1, %xmm2
movdqa (con1), %xmm0
movdqa (mask), %xmm15
mov $8, %ax
LOOP1:
add $16, %rsi
dec %ax
pshufb %xmm15,%xmm2
aesenclast %xmm0, %xmm2
pslld $1, %xmm0
movdqa %xmm1, %xmm3
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pxor %xmm2, %xmm1
movdqa %xmm1, (%rsi)
movdqa %xmm1, %xmm2
jne LOOP1
movdqa (con2), %xmm0
pshufb %xmm15,%xmm2
aesenclast %xmm0, %xmm2
pslld $1, %xmm0
movdqa %xmm1, %xmm3
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pxor %xmm2, %xmm1
movdqa %xmm1, 16(%rsi)
movdqa %xmm1, %xmm2
pshufb %xmm15,%xmm2
aesenclast %xmm0, %xmm2
movdqa %xmm1, %xmm3
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pslldq $4, %xmm3
pxor %xmm3, %xmm1
(continue)
5-47
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-48. AES128 Key Expansion (Contd.)
pslldq $4, %xmm3
pxor %xmm3, %xmm1
pxor %xmm2, %xmm1
movdqa %xmm1, 32(%rsi)
movdqa %xmm1, %xmm2
ret
5.10.3
Enhancement in Intel Microarchitecture Code Name Haswell
5.10.3.1
AES and Multi-Buffer Cryptographic Throughput
The AESINC/AESINCLAST, AESDEC/AESDECLAST instructions in Intel microarchitecture code name
Haswell have slightly improvement latency and are one micro-op. These improvements are expected to
benefit AES algorithms operating in parallel modes (e.g. CBC decryption) and multiple-buffer implementations of AES algorithms. See the following link for additional details on AESNI:
•
http://software.intel.com/en-us/articles/intel-advanced-encryption-standard-aes-instructions-set.
5.10.3.2
PCLMULQDQ Improvement
The latency of PCLMULQDQ in Intel microarchitecture code name Haswell is reduced from 14 to 7 cycles,
and throughput improved from once every 8 cycle to every other cycle, when compared to prior generations. This will speed up CRC calculations for generic polynomials. Details and examples can be found at:
•
http://www.intel.com/Assets/PDF/manual/323640.pdf.
AES-GCM implemented using PCLMULQDQ can be found in OpenSSL project at:
•
http://www.intel.com/content/dam/www/public/us/en/documents/software-support/enabling-highperformance-gcm.pdf.
5.11
LIGHT-WEIGHT DECOMPRESSION AND DATABASE PROCESSING
Traditionally, database storage requires high-compression ratio means to preserve the finite disk I/O
bandwidth limitations. In row-optimized database architecture, the primary limitation on database
processing performance often correlates to the hardware constraints of the storage I/O bandwidth, the
locality issues of data records from rows in large tables that must be decompressed from its storage
format. Many recent database innovations are centered around columnar database architecture, where
storage format is optimized for query operations to fetch data in a sequential manner.
Some of the recent advances in columnar database (also known as in-memory database) are lightweight compression/decompression techniques and vectorized query operation primitives using SSE4.2
and other SIMD instructions. When a database engine combines those processing techniques with a
column-optimized storage system using solid state drives, query performance increase of several fold
has been reported1. This section discusses the usage of SIMD instructions for light-weight compression/decompression in columnar databases.
The optimal objective for light-weight compression/decompression is to deliver high throughput at
reasonably low CPU utilization, such that the finite total compute bandwidth can be divided more favorably between query processing and decompression to achieve maximal query throughput. SSE4.2 can
raise the compute bandwidth for some query operations to a significantly higher level (see Section
11.3.3), compared to query primitives implemented using general-purpose-register instructions. This
also places higher demand on the streaming data feed of decompressed columnar data.
1. See published TPC-H non-clustered performance results at www.tpc.org
5-48
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
5.11.1
Reduced Dynamic Range Datasets
One of the more successful approaches to compress/decompress columnar data in high-speed is based
on the idea that an ensemble of integral values in a sequential data stream of fixed-size storage width
can be represented more compactly if the dynamic range of that ensemble is reduced by way of partitioning, offset from a common reference value, and additional techniques2,3.
For example, a column that stores 5-digit ZIPCODE as 32-bit integers only requires a dynamic range of
17 bits. The unique primary keys in a 2 billion row table can be reduced through partitioning of sequential
blocks of 2^N entries to store the offset in the block header and reducing the storage size of each 32-bit
integer as N bits.
5.11.2
Compression and Decompression Using SIMD Instructions
To illustrate the usage of SIMD instructions for reduced-dynamic-range compression/decompression,
and compressed data elements are not byte-aligned, we consider an array of 32-bit integers whose
dynamic range only requires 5 bits per value.
To pack a stream of 32-bit integer values into consecutive 5-bit buckets, the SIMD technique illustrated
in Example 5-49 consists of the following phases:
•
Dword-to-byte packing and byte-array sequencing: The stream of dword elements is reduced to byte
streams with each iteration handling 32 elements. The two resulting 16-byte vectors are sequenced
to enable 4-way bit-stitching using PSLLD and PSRLD instructions.
Example 5-49. Compress 32-bit Integers into 5-bit Buckets
;
static __declspec(align(16)) short mask_dw_5b[16] = // 5-bit mask for 4 way bit-packing via dword
{0x1f, 0x0, 0x1f, 0x0, 0x1f, 0x0, 0x1f, 0x0}; // packed shift
static __declspec(align(16)) short sprdb_0_5_10_15[8] = // shuffle control to re-arrange
{ 0xff00, 0xffff, 0x04ff, 0xffff, 0xffff, 0xff08, 0xffff, 0x0cff}; // bytes 0, 4, 8, 12 to gap positions at 0, 5, 10, 15
void RDRpack32x4_sse(int *src, int cnt, char * out)
int i, j;
__m128i a0, a1, a2, a3, c0, c1, b0, b1, b2, b3, bb;
__m128i msk4 ;
__m128i sprd4 = _mm_loadu_si128( (__m128i*) &sprdb_0_5_10_15[0]);
switch( bucket_width) {
case 5:j= 0;
(continue)
2. “SIMD-scan: ultra fast in-memory table scan using on-chip vector processing units”, T. Willhalm, et. al., Proceedings of the
VLDB Endowment, Vol. 2, #1, August 2009.
3. "Super-Scalar RAM-CPU Cache Compression," M. Zukowski, et, al, Data Engineering, International Conference, vol. 0, no. 0,
pp. 59, 2006.
5-49
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-49. Compress 32-bit Integers into 5-bit Buckets (Contd.)
msk4 = _mm_loadu_si128( (__m128i*) &mask_dw_5b[0]);
// process 32 elements in each iteration
for (i = 0; i < cnt; i+= 32) {
b0 = _mm_packus_epi32(_mm_loadu_si128( (__m128i*) &src[i]), _mm_loadu_si128( (__m128i*) &src[i+4]));
b1 = _mm_packus_epi32(_mm_loadu_si128( (__m128i*) &src[i+8]), _mm_loadu_si128( (__m128i*) &src[i+12]));
b2 = _mm_packus_epi32(_mm_loadu_si128( (__m128i*) &src[i+16]), _mm_loadu_si128( (__m128i*)
&src[i+20]));
b3 = _mm_packus_epi32(_mm_loadu_si128( (__m128i*) &src[i+24]), _mm_loadu_si128( (__m128i*)
&src[i+28]));
c0 = _mm_packus_epi16( _mm_unpacklo_epi64(b0, b1), _mm_unpacklo_epi64(b2, b3));
// c0 contains bytes: 0-3, 8-11, 16-19, 24-27 elements
c1 = _mm_packus_epi16( _mm_unpackhi_epi64(b0, b1), _mm_unpackhi_epi64(b2, b3));
// c1 contains bytes: 4-7, 12-15, 20-23, 28-31
b0 = _mm_and_si128( c0, msk4);
// keep lowest 5 bits in each way/dword
b1 = _mm_and_si128( _mm_srli_epi32(c0, 3), _mm_slli_epi32(msk4, 5));
b0 = _mm_or_si128( b0, b1);
// add next 5 bits to each way/dword
b1 = _mm_and_si128( _mm_srli_epi32(c0, 6), _mm_slli_epi32(msk4, 10));
b0 = _mm_or_si128( b0, b1);
b1 = _mm_and_si128( _mm_srli_epi32(c0, 9), _mm_slli_epi32(msk4, 15));
b0 = _mm_or_si128( b0, b1);
b1 = _mm_and_si128( _mm_slli_epi32(c1, 20), _mm_slli_epi32(msk4, 20));
b0 = _mm_or_si128( b0, b1);
b1 = _mm_and_si128( _mm_slli_epi32(c1, 17), _mm_slli_epi32(msk4, 25));
b0 = _mm_or_si128( b0, b1);
b1 = _mm_and_si128( _mm_slli_epi32(c1, 14), _mm_slli_epi32(msk4, 30));
b0 = _mm_or_si128( b0, b1);
// add next 2 bits from each dword channel, xmm full
*(int*)&out[j] = _mm_cvtsi128_si32( b0);// the first dword is compressed and ready
// re-distribute the remaining 3 dword and add gap bytes to store remained bits
b0 = _mm_shuffle_epi8(b0, gap4x3);
b1 = _mm_and_si128( _mm_srli_epi32(c1, 18), _mm_srli_epi32(msk4, 2)); // do 4-way packing of the next 3 bits
b2 = _mm_and_si128( _mm_srli_epi32(c1, 21), _mm_slli_epi32(msk4, 3));
b1 = _mm_or_si128( b1, b2); //5th byte compressed at bytes 0, 4, 8, 12
// shuffle the fifth byte result to byte offsets of 0, 5, 10, 15
b0 = _mm_or_si128( b0, _mm_shuffle_epi8(b1, sprd4));
_mm_storeu_si128( (__m128i *) &out[j+4] , b0);
j += bucket_width*4;
}
// handle remainder if cnt is not multiples of 32
break;
}
}
•
Four-way bit stitching: In each way (dword) of the destination, 5 bits are packed consecutively from
the corresponding byte element that contains 5 non-zero bit patterns. Since each dword destination
will be completely filled up by the contents of 7 consecutive elements, the remaining three bits of the
7th element and the 8th element are done separately in a similar 4-way stitching operation but
require the assistance of shuffle operations.
Example 5-50 shows the reverse operation of decompressing consecutively packed 5-bit buckets into
32-bit data elements.
5-50
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-50. Decompression of a Stream of 5-bit Integers into 32-bit Elements
;
static __declspec(align(16)) short mask_dw_5b[16] = // 5-bit mask for 4 way bit-packing via dword
{0x1f, 0x0, 0x1f, 0x0, 0x1f, 0x0, 0x1f, 0x0}; // packed shift
static __declspec(align(16)) short pack_dw_4x3[8] = // pack 3 dwords 1-4, 6-9, 11-14
{ 0xffff, 0xffff, 0x0201, 0x0403, 0x0706, 0x0908, 0xc0b, 0x0e0d}; // to vacate bytes 0-3
static __declspec(align(16)) short packb_0_5_10_15[8] = // shuffle control to re-arrange bytes
{ 0xffff, 0x0ff, 0xffff, 0x5ff, 0xffff, 0xaff, 0xffff, 0x0fff}; // 0, 5, 10, 15 to gap positions at 3, 7, 11, 15
void RDRunpack32x4_sse(char *src, int cnt, int * out)
{int i, j;
__m128i a0, a1, a2, a3, c0, c1, b0, b1, b2, b3, bb, d0, d1, d2, d3;
__m128i msk4 ;
__m128i pck4 = _mm_loadu_si128( (__m128i*) &packb_0_5_10_15[0]);
__m128i pckdw3 = _mm_loadu_si128( (__m128i*) &pack_dw_4x3[0]);
switch( bucket_width) {
case 5:j= 0;
msk4 = _mm_loadu_si128( (__m128i*) &mask_dw_5b[0]);
for (i = 0; i < cnt; i+= 32) {
a1 = _mm_loadu_si128( (__m128i*) &src[j +4]);
// pick up bytes 4, 9, 14, 19 and shuffle into offset 3, 7, 11, 15
c0 = _mm_shuffle_epi8(a1, pck4);
b1 = _mm_and_si128( _mm_srli_epi32(c0, 3), _mm_slli_epi32(msk4, 24));
// put 3 unaligned dword 1-4, 6-9, 11-14 to vacate bytes 0-3
a1 = _mm_shuffle_epi8(a1, pckdw3);
b0 = _mm_and_si128( _mm_srli_epi32(c0, 6), _mm_slli_epi32(msk4, 16));
a0 = _mm_cvtsi32_si128( *(int *)&src[j ]);
b1 = _mm_or_si128( b0, b1); // finished decompress source bytes 4, 9, 14, 19
a0 = _mm_or_si128( a0, a1); // bytes 0-16 contain compressed bits
b0 = _mm_and_si128( _mm_srli_epi32(a0, 14), _mm_slli_epi32(msk4, 16));
b1 = _mm_or_si128( b0, b1);
b0 = _mm_and_si128( _mm_srli_epi32(a0, 17), _mm_slli_epi32(msk4, 8));
b1 = _mm_or_si128( b0, b1);
b0 = _mm_and_si128( _mm_srli_epi32(a0, 20), msk4);
b1 = _mm_or_si128( b0, b1);// b1 now full with decompressed 4-7,12-15,20-23,28-31
_mm_storeu_si128( (__m128i *) &out[i+4] , _mm_cvtepu8_epi32(b1));
b0 = _mm_and_si128( _mm_slli_epi32(a0, 9), _mm_slli_epi32(msk4, 24));
c0 = _mm_and_si128( _mm_slli_epi32(a0, 6), _mm_slli_epi32(msk4, 16));
b0 = _mm_or_si128( b0, c0);
_mm_storeu_si128( (__m128i *) &out[i+12] , _mm_cvtepu8_epi32(_mm_srli_si128(b1, 4)));
c0 = _mm_and_si128( _mm_slli_epi32(a0, 3), _mm_slli_epi32(msk4, 8));
_mm_storeu_si128( (__m128i *) &out[i+20] , _mm_cvtepu8_epi32(_mm_srli_si128(b1, 8)));
b0 = _mm_or_si128( b0, c0);
_mm_storeu_si128( (__m128i *) &out[i+28] , _mm_cvtepu8_epi32(_mm_srli_si128(b1, 12)));
c0 = _mm_and_si128( a0, msk4);
b0 = _mm_or_si128( b0, c0);// b0 now full with decompressed 0-3,8-11,16-19,24-27
5-51
OPTIMIZING FOR SIMD INTEGER APPLICATIONS
Example 5-50. Decompression of a Stream of 5-bit Integers into 32-bit Elements (Contd.)
_mm_storeu_si128( (__m128i *) &out[i] , _mm_cvtepu8_epi32(b0));
_mm_storeu_si128( (__m128i *) &out[i+8] , _mm_cvtepu8_epi32(_mm_srli_si128(b0, 4)));
_mm_storeu_si128( (__m128i *) &out[i+16] , _mm_cvtepu8_epi32(_mm_srli_si128(b0, 8)));
_mm_storeu_si128( (__m128i *) &out[i+24] , _mm_cvtepu8_epi32(_mm_srli_si128(b0, 12)));
j += g_bwidth*4;
}
break;
}
}
Compression/decompression of integers for dynamic range that are non-power-of-2 can generally use
similar mask/packed shift/stitch technique with additional adaptation of the horizontal rearrangement of
partially stitched vectors. The increase in throughput relative to using general-purpose scalar instructions will depend on implementation and bucket width.
When compiled with the “/O2” option on an Intel Compiler, the compression throughput can reach 6
Bytes/cycle on Intel microarchitecture code name Sandy Bridge, and the throughput varies little for
working set sizes due to the streaming data access pattern and the effectiveness of hardware
prefetchers. The decompression throughput of the above example is more than 5 Bytes/cycle at full utilization, allowing a database query engine to partition CPU utilization effectively to allocate a small fraction
for on-the-fly decompression to feed vectorized query computation.
The decompression throughput increase using a SIMD light-weight compression technique offers database architects new degrees of freedom to relocate critical performance bottlenecks from a lowerthroughput technology (disk I/O, DRAM) to a faster pipeline.
5-52
CHAPTER 6
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
This chapter discusses rules for optimizing for the single-instruction, multiple-data (SIMD) floating-point
instructions available in SSE, SSE2 SSE3, and SSE4.1. The chapter also provides examples that illustrate
the optimization techniques for single-precision and double-precision SIMD floating-point applications.
6.1
GENERAL RULES FOR SIMD FLOATING-POINT CODE
The rules and suggestions in this section help optimize floating-point code containing SIMD floatingpoint instructions. Generally, it is important to understand and balance port utilization to create efficient
SIMD floating-point code. Basic rules and suggestions include the following:
•
•
Follow all guidelines in Chapter 3 and Chapter 4.
•
Utilize the flush-to-zero and denormals-are-zero modes for higher performance to avoid the penalty
of dealing with denormals and underflows.
•
Use the reciprocal instructions followed by iteration for increased accuracy. These instructions yield
reduced accuracy but execute much faster. Note the following:
Mask exceptions to achieve higher performance. When exceptions are unmasked, software
performance is slower.
— If reduced accuracy is acceptable, use them with no iteration.
— If near full accuracy is needed, use a Newton-Raphson iteration.
— If full accuracy is needed, then use divide and square root which provide more accuracy, but slow
down performance.
6.2
PLANNING CONSIDERATIONS
Whether adapting an existing application or creating a new one, using SIMD floating-point instructions to
achieve optimum performance gain requires programmers to consider several issues. In general, when
choosing candidates for optimization, look for code segments that are computationally intensive and
floating-point intensive. Also consider efficient use of the cache architecture.
The sections that follow answer the questions that should be raised before implementation:
•
•
•
•
•
Can data layout be arranged to increase parallelism or cache utilization?
•
•
•
Does the result of computation affected by enabling flush-to-zero or denormals-to-zero modes?
Which part of the code benefits from SIMD floating-point instructions?
Is the current algorithm the most appropriate for SIMD floating-point instructions?
Is the code floating-point intensive?
Do either single-precision floating-point or double-precision floating-point computations provide
enough range and precision?
Is the data arranged for efficient utilization of the SIMD floating-point registers?
Is this application targeted for processors without SIMD floating-point instructions?
See also: Section 4.2, “Considerations for Code Conversion to SIMD Programming.”
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
6.3
USING SIMD FLOATING-POINT WITH X87 FLOATING-POINT
Because the XMM registers used for SIMD floating-point computations are separate registers and are not
mapped to the existing x87 floating-point stack, SIMD floating-point code can be mixed with x87
floating-point or 64-bit SIMD integer code.
With Intel Core microarchitecture, 128-bit SIMD integer instructions provides substantially higher efficiency than 64-bit SIMD integer instructions. Software should favor using SIMD floating-point and
integer SIMD instructions with XMM registers where possible.
6.4
SCALAR FLOATING-POINT CODE
There are SIMD floating-point instructions that operate only on the lowest order element in the SIMD
register. These instructions are known as scalar instructions. They allow the XMM registers to be used for
general-purpose floating-point computations.
In terms of performance, scalar floating-point code can be equivalent to or exceed x87 floating-point
code and has the following advantages:
•
SIMD floating-point code uses a flat register model, whereas x87 floating-point code uses a stack
model. Using scalar floating-point code eliminates the need to use FXCH instructions. These have
performance limits on the Intel Pentium 4 processor.
•
•
•
Mixing with MMX technology code without penalty.
Flush-to-zero mode.
Shorter latencies than x87 floating-point.
When using scalar floating-point instructions, it is not necessary to ensure that the data appears in
vector form. However, the optimizations regarding alignment, scheduling, instruction selection, and
other optimizations covered in Chapter 3 and Chapter 4 should be observed.
6.5
DATA ALIGNMENT
SIMD floating-point data is 16-byte aligned. Referencing unaligned 128-bit SIMD floating-point data will
result in an exception unless MOVUPS or MOVUPD (move unaligned packed single or unaligned packed
double) is used. The unaligned instructions used on aligned or unaligned data will also suffer a performance penalty relative to aligned accesses.
See also: Section 4.4, “Stack and Data Alignment.”
6.5.1
Data Arrangement
Because SSE and SSE2 incorporate SIMD architecture, arranging data to fully use the SIMD registers
produces optimum performance. This implies contiguous data for processing, which leads to fewer cache
misses. Correct data arrangement can potentially quadruple data throughput when using SSE or double
throughput when using SSE2. Performance gains can occur because four data elements can be loaded
with 128-bit load instructions into XMM registers using SSE (MOVAPS). Similarly, two data elements can
loaded with 128-bit load instructions into XMM registers using SSE2 (MOVAPD).
Refer to the Section 4.4, “Stack and Data Alignment,” for data arrangement recommendations. Duplicating and padding techniques overcome misalignment problems that occur in some data structures and
arrangements. This increases the data space but avoids penalties for misaligned data access.
For some applications (for example: 3D geometry), traditional data arrangement requires some changes
to fully utilize the SIMD registers and parallel techniques. Traditionally, the data layout has been an array
of structures (AoS). To fully utilize the SIMD registers in such applications, a new data layout has been
proposed — a structure of arrays (SoA) resulting in more optimized performance.
6-2
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
6.5.1.1
Vertical versus Horizontal Computation
The majority of the floating-point arithmetic instructions in SSE/SSE2 provide greater performance gain
on vertical data processing for parallel data elements. This means each element of the destination is the
result of an arithmetic operation performed from the source elements in the same vertical position
(Figure 6-1).
To supplement these homogeneous arithmetic operations on parallel data elements, SSE and SSE2
provides data movement instructions (e.g., SHUFPS, UNPCKLPS, UNPCKHPS, MOVLHPS, MOVHLPS, etc.)
that facilitate moving data elements
horizontally.
X3
X2
Y3
X1
Y2
X0
Y1
OP
OP
OP
X3 OP Y3
X2 OP Y2
X 1OP Y1
Y0
OP
X0 OP Y0
Figure 6-1. Homogeneous Operation on Parallel Data Elements
The organization of structured data have a significant impact on SIMD programming efficiency and
performance. This can be illustrated using two common type of data structure organizations:
•
Array of Structure: This refers to the arrangement of an array of data structures. Within the data
structure, each member is a scalar. This is shown in Figure 6-2. Typically, a repetitive sequence of
computation is applied to each element of an array, i.e., a data structure. Computational sequence
for the scalar members of the structure is likely to be non-homogeneous within each iteration. AoS is
generally associated with a horizontal computation model.
X
Y
Z
W
Figure 6-2. Horizontal Computation Model
•
Structure of Array: Here, each member of the data structure is an array. Each element of the array is
a scalar. This is shown Table 6-1. Repetitive computational sequence is applied to scalar elements
and homogeneous operation can be easily achieved across consecutive iterations within the same
structural member. Consequently, SoA is generally amenable to the vertical computation model.
6-3
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Table 6-1. SoA Form of Representing Vertices Data
Vx array
X1
X2
X3
X4
.....
Xn
Vy array
Y1
Y2
Y3
Y4
.....
Yn
Vz array
Z1
Z2
Z3
Y4
.....
Zn
Vw array
W1
W2
W3
W4
.....
Wn
Using SIMD instructions with vertical computation on SOA arrangement can achieve higher efficiency and
performance than AOS and horizontal computation. This can be seen with dot-product operation on
vectors. The dot product operation on SoA arrangement is shown in Figure 6-3.
X1
X2
X3
X4
X
Fx
Fx
Fx
Fx
+
Y1
Y2
Y3
Y4
X
Fy
Fy
Fy
Fy
+
Z1
Z2
Z3
Z4
X
Fz
Fz
Fz
Fz
+
W1
W2
W3
W4
X
Fw
Fw
Fw
Fw
=
R1
R2
R3
R4
OM15168
Figure 6-3. Dot Product Operation
Example 6-1 shows how one result would be computed for seven instructions if the data were organized
as AoS and using SSE alone: four results would require 28 instructions.
Example 6-1. Pseudocode for Horizontal (xyz, AoS) Computation
mulps
movaps
shufps
addps
movaps
shufps
addps
6-4
; x*x', y*y', z*z'
; reg->reg move, since next steps overwrite
; get b,a,d,c from a,b,c,d
; get a+b,a+b,c+d,c+d
; reg->reg move
; get c+d,c+d,a+b,a+b from prior addps
; get a+b+c+d,a+b+c+d,a+b+c+d,a+b+c+d
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Now consider the case when the data is organized as SoA. Example 6-2 demonstrates how four results
are computed for five instructions.
Example 6-2. Pseudocode for Vertical (xxxx, yyyy, zzzz, SoA) Computation
mulps
mulps
mulps
addps
addps
; x*x' for all 4 x-components of 4 vertices
; y*y' for all 4 y-components of 4 vertices
; z*z' for all 4 z-components of 4 vertices
; x*x' + y*y'
; x*x'+y*y'+z*z'
For the most efficient use of the four component-wide registers, reorganizing the data into the SoA
format yields increased throughput and hence much better performance for the instructions used.
As seen from this simple example, vertical computation can yield 100% use of the available SIMD registers to produce four results. (The results may vary for other situations.) If the data structures are represented in a format that is not “friendly” to vertical computation, it can be rearranged “on the fly” to
facilitate better utilization of the SIMD registers. This operation is referred to as “swizzling” operation and
the reverse operation is referred to as “deswizzling.”
6.5.1.2
Data Swizzling
Swizzling data from SoA to AoS format can apply to a number of application domains, including 3D
geometry, video and imaging. Two different swizzling techniques can be adapted to handle floating-point
and integer data. Example 6-3 illustrates a swizzle function that uses SHUFPS, MOVLHPS, MOVHLPS
instructions.
Example 6-3. Swizzling Data Using SHUFPS, MOVLHPS, MOVHLPS
typedef struct _VERTEX_AOS {
float x, y, z, color;
} Vertex_aos;
typedef struct _VERTEX_SOA {
float x[4], float y[4], float z[4];
float color[4];
// AoS structure declaration
} Vertex_soa;
// SoA structure declaration
void swizzle_asm (Vertex_aos *in, Vertex_soa *out)
{
// in mem: x1y1z1w1-x2y2z2w2-x3y3z3w3-x4y4z4w4// SWIZZLE XYZW --> XXXX
asm {
mov ebx, in
// get structure addresses
mov edx, out
movaps
movaps
movaps
movaps
movaps
movhlps
movaps
movlhps
movhlps
movlhps
xmm1, [ebx ]
// x4 x3 x2 x1
xmm2, [ebx + 16] // y4 y3 y2 y1
xmm3, [ebx + 32] // z4 z3 z2 z1
xmm4, [ebx + 48] // w4 w3 w2 w1
xmm7, xmm4 // xmm7= w4 z4 y4 x4
xmm7, xmm3 // xmm7= w4 z4 w3 z3
xmm6, xmm2 // xmm6= w2 z2 y2 x2
xmm3, xmm4 // xmm3= y4 x4 y3 x3
xmm2, xmm1 // xmm2= w2 z2 w1 z1
xmm1, xmm6 // xmm1= y2 x2 y1 x1
6-5
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-3. Swizzling Data (Contd.)Using SHUFPS, MOVLHPS, MOVHLPS (Contd.)
movaps
movaps
shufps
shufps
shufps
shufps
xmm6, xmm2// xmm6= w2 z2 w1 z1
xmm5, xmm1// xmm5= y2 x2 y1 x1
xmm2, xmm7, 0xDD // xmm2= w4 w3 w2 w1 => v4
xmm1, xmm3, 0x88 // xmm1= x4 x3 x2 x1 => v1
xmm5, xmm3, 0xDD // xmm5= y4 y3 y2 y1 => v2
xmm6, xmm7, 0x88 // xmm6= z4 z3 z2 z1 => v3
movaps
movaps
movaps
movaps
[edx], xmm1
[edx+16], xmm5
[edx+32], xmm6
[edx+48], xmm2
// store X
// store Y
// store Z
// store W
}
}
Example 6-4 shows a similar data-swizzling algorithm using SIMD instructions in the integer domain.
Example 6-4. Swizzling Data Using UNPCKxxx Instructions
void swizzle_asm (Vertex_aos *in, Vertex_soa *out)
{
// in mem: x1y1z1w1-x2y2z2w2-x3y3z3w3-x4y4z4w4// SWIZZLE XYZW --> XXXX
asm {
mov ebx, in
// get structure addresses
mov edx, out
movdqa
movdqa
movdqa
movdqa
movdqa
punpckldq
punpckhdq
movdqa
punpckldq
punpckldq
movdqa
punpcklqdq
punpckhqdq
movdqa
punpcklqdq
punpckhqdq
xmm1, [ebx + 0*16]
//w0 z0 y0 x0
xmm2, [ebx + 1*16]
//w1 z1 y1 x1
xmm3, [ebx + 2*16]
//w2 z2 y2 x2
xmm4, [ebx + 3*16]
//w3 z3 y3 x3
xmm5, xmm1
xmm1, xmm2
// y1 y0 x1 x0
xmm5, xmm2
// w1 w0 z1 z0
xmm2, xmm3
xmm3, xmm4
// y3 y2 x3 x2
xmm2, xmm4
// w3 w2 z3 z2
xmm4, xmm1
xmm1, xmm3
// x3 x2 x1 x0
xmm4, xmm3
// y3 y2 y1 y0
xmm3, xmm5
xmm5, xmm2
// z3 z2 z1 z0
xmm3, xmm2
// w3 w2 w1 w0
movdqa
movdqa
movdqa
movdqa
[edx+0*16], xmm1
[edx+1*16], xmm4
[edx+2*16], xmm5
[edx+3*16], xmm3
//x3 x2 x1 x0
//y3 y2 y1 y0
//z3 z2 z1 z0
//w3 w2 w1 w0
}
The technique in Example 6-3 (loading 16 bytes, using SHUFPS and copying halves of XMM registers) is
preferable over an alternate approach of loading halves of each vector using MOVLPS/MOVHPS on newer
microarchitectures. This is because loading 8 bytes using MOVLPS/MOVHPS can create code dependency
and reduce the throughput of the execution engine.
6-6
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
The performance considerations of Example 6-3 and Example 6-4 often depends on the characteristics of
each microarchitecture. For example, in Intel Core microarchitecture, executing a SHUFPS tend to be
slower than a PUNPCKxxx instruction. In Enhanced Intel Core microarchitecture, SHUFPS and
PUNPCKxxx instruction all executes with 1 cycle throughput due to the 128-bit shuffle execution unit.
Then the next important consideration is that there is only one port that can execute PUNPCKxxx vs.
MOVLHPS/MOVHLPS can execute on multiple ports. The performance of both techniques improves on
Intel Core microarchitecture over previous microarchitectures due to 3 ports for executing SIMD instructions. Both techniques improves further on Enhanced Intel Core microarchitecture due to the 128-bit
shuffle unit.
6.5.1.3
Data Deswizzling
In the deswizzle operation, we want to arrange the SoA format back into AoS format so the XXXX, YYYY,
ZZZZ are rearranged and stored in memory as XYZ. Example 6-5 illustrates one deswizzle function for
floating-point data.
Example 6-5. Deswizzling Single-Precision SIMD Data
void deswizzle_asm(Vertex_soa *in, Vertex_aos *out)
{
__asm {
mov
ecx, in
// load structure addresses
mov
edx, out
movaps
xmm0, [ecx ]
//x3 x2 x1 x0
movaps
xmm1, [ecx + 16]
//y3 y2 y1 y0
movaps
xmm2, [ecx + 32]
//z3 z2 z1 z0
movaps
xmm3, [ecx + 48]
//w3 w2 w1 w0
movaps
movaps
unpcklps
unpcklps
movdqa
movlhps
movhlps
xmm5, xmm0
xmm7, xmm2
xmm0, xmm1
xmm2, xmm3
xmm4, xmm0
xmm0, xmm2
xmm4, xmm2
unpckhps
unpckhps
movdqa
movlhps
movhlps
movaps
movaps
movaps
movaps
xmm5, xmm1
// y3 x3 y2 x2
xmm7, xmm3
// w3 z3 w2 z2
xmm6, xmm5
xmm5, xmm7
// w2 z2 y2 x2
xmm6, xmm7
// w3 z3 y3 x3
[edx+0*16], xmm0 //w0 z0 y0 x0
[edx+1*16], xmm4 //w1 z1 y1 x1
[edx+2*16], xmm5 //w2 z2 y2 x2
[edx+3*16], xmm6 //w3 z3 y3 x3
// y1 x1 y0 x0
// w1 z1 w0 z0
// w0 z0 y0 x0
// w1 z1 y1 x1
}
}
Example 6-6 shows a similar deswizzle function using SIMD integer instructions. Both of these techniques demonstrate loading 16 bytes and performing horizontal data movement in registers. This
approach is likely to be more efficient than alternative techniques of storing 8-byte halves of XMM registers using MOVLPS and MOVHPS.
6-7
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-6. Deswizzling Data Using SIMD Integer Instructions
void deswizzle_rgb(Vertex_soa *in, Vertex_aos *out)
{
//---deswizzle rgb--// assume: xmm1=rrrr, xmm2=gggg, xmm3=bbbb, xmm4=aaaa
__asm {
mov
ecx, in
// load structure addresses
mov
edx, out
movdqa
xmm0, [ecx]
// load r4 r3 r2 r1 => xmm1
movdqa
xmm1, [ecx+16]
// load g4 g3 g2 g1 => xmm2
movdqa
xmm2, [ecx+32]
movdqa
xmm3, [ecx+48]
// Start deswizzling here
movdqa
xmm5, xmm0
movdqa
xmm7, xmm2
punpckldq
xmm0, xmm1
punpckldq
xmm2, xmm3
movdqa
xmm4, xmm0
punpcklqdq xmm0, xmm2
punpckhqdq xmm4, xmm2
punpckhdq xmm5, xmm1
punpckhdq xmm7, xmm3
movdqa
xmm6, xmm5
punpcklqdq xmm5, xmm7
punpckhqdq xmm6, xmm7
movdqa
// load b4 b3 b2 b1 => xmm3
// load a4 a3 a2 a1 => xmm4
// g2 r2 g1 r1
// a2 b2 a1 b1
// a1 b1 g1 r1 => v1
// a2 b2 g2 r2 => v2
// g4 r4 g3 r3
// a4 b4 a3 b3
// a3 b3 g3 r3 => v3
// a4 b4 g4 r4 => v4
[edx], xmm0
movdqa
[edx+16], xmm4
movdqa
[edx+32], xmm5
movdqa
[edx+48], xmm6
// DESWIZZLING ENDS HERE
}
}
6.5.1.4
// v1
// v2
// v3
// v4
Horizontal ADD Using SSE
Although vertical computations generally make use of SIMD performance better than horizontal computations, in some cases, code must use a horizontal operation.
MOVLHPS/MOVHLPS and shuffle can be used to sum data horizontally. For example, starting with four
128-bit registers, to sum up each register horizontally while having the final results in one register, use
the MOVLHPS/MOVHLPS to align the upper and lower parts of each register. This allows you to use a
vertical add. With the resulting partial horizontal summation, full summation follows easily.
Figure 6-4 presents a horizontal add using MOVHLPS/MOVLHPS. Example 6-7 and Example 6-8 provide
the code for this operation.
6-8
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
xm m 0
A1
A2
A3
xm m 1
A4
B1
MO VLHPS
A1
A2
B1
B2
B3
xm m 2
B4
C1
MOVHLPS
B2
A3
A4
B3
C2
C3
A2+A4
B4
C1
C2
D1
B1+B3
D1
D2
D2
D3
D4
M OVHLPS
C3
C4
D3
D4
ADDPS
B1+B3
B2+B4
C1+C3
C2+C4
SHUFPS
A1+A3
C4
MOVLHPS
ADDPS
A1+A3
xm m 3
C1+C3
D1+D3
D2+D4
SHUFPS
D1+D3
A2+A4
B2+B4
C2+C4
D2+D4
ADDPS
A1+A2+A3+A4
B1+B2+B3+B4
C1+C2+C3+C4
D1+D2+D3+D4
OM15169
Figure 6-4. Horizontal Add Using MOVHLPS/MOVLHPS
Example 6-7. Horizontal Add Using MOVHLPS/MOVLHPS
void horiz_add(Vertex_soa *in, float *out) {
__asm {
mov ecx, in
// load structure addresses
mov edx, out
movaps xmm0, [ecx]
// load A1 A2 A3 A4 => xmm0
movaps xmm1, [ecx+16]
// load B1 B2 B3 B4 => xmm1
movaps xmm2, [ecx+32]
// load C1 C2 C3 C4 => xmm2
movaps xmm3, [ecx+48]
// load D1 D2 D3 D4 => xmm3
// START HORIZONTAL ADD
movaps xmm5, xmm0
movlhps xmm5, xmm1
movhlps xmm1, xmm0
addps xmm5, xmm1
movaps xmm4, xmm2
movlhps xmm2, xmm3
movhlps xmm3, xmm4
addps xmm3, xmm2
movaps xmm6, xmm3
shufps xmm3, xmm5, 0xDD
// xmm5= A1,A2,A3,A4
// xmm5= A1,A2,B1,B2
// xmm1= A3,A4,B3,B4
// xmm5= A1+A3,A2+A4,B1+B3,B2+B4
// xmm2= C1,C2,D1,D2
// xmm3= C3,C4,D3,D4
// xmm3= C1+C3,C2+C4,D1+D3,D2+D4
// xmm6= C1+C3,C2+C4,D1+D3,D2+D4
//xmm6=A1+A3,B1+B3,C1+C3,D1+D3
shufps xmm5, xmm6, 0x88
addps xmm6, xmm5
// xmm5= A2+A4,B2+B4,C2+C4,D2+D4
// xmm6= D,C,B,A
6-9
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-7. Horizontal Add Using MOVHLPS/MOVLHPS (Contd.)
// END HORIZONTAL ADD
movaps [edx], xmm6
}
}
Example 6-8. Horizontal Add Using Intrinsics with MOVHLPS/MOVLHPS
void horiz_add_intrin(Vertex_soa *in, float *out)
{
__m128 v, v2, v3, v4;
__m128 tmm0,tmm1,tmm2,tmm3,tmm4,tmm5,tmm6;
// Temporary variables
tmm0 = _mm_load_ps(in->x);
// tmm0 = A1 A2 A3 A4
tmm1 = _mm_load_ps(in->y);
tmm2 = _mm_load_ps(in->z);
tmm3 = _mm_load_ps(in->w);
tmm5 = tmm0;
tmm5 = _mm_movelh_ps(tmm5, tmm1);
tmm1 = _mm_movehl_ps(tmm1, tmm0);
tmm5 = _mm_add_ps(tmm5, tmm1);
tmm4 = tmm2;
// tmm1 = B1 B2 B3 B4
// tmm2 = C1 C2 C3 C4
// tmm3 = D1 D2 D3 D4
// tmm0 = A1 A2 A3 A4
// tmm5 = A1 A2 B1 B2
// tmm1 = A3 A4 B3 B4
// tmm5 = A1+A3 A2+A4 B1+B3 B2+B4
tmm2 = _mm_movelh_ps(tmm2, tmm3);
tmm3 = _mm_movehl_ps(tmm3, tmm4);
tmm3 = _mm_add_ps(tmm3, tmm2);
tmm6 = tmm3;
tmm6 = _mm_shuffle_ps(tmm3, tmm5, 0xDD);
// tmm2 = C1 C2 D1 D2
// tmm3 = C3 C4 D3 D4
// tmm3 = C1+C3 C2+C4 D1+D3 D2+D4
// tmm6 = C1+C3 C2+C4 D1+D3 D2+D4
// tmm6 = A1+A3 B1+B3 C1+C3 D1+D3
tmm5 = _mm_shuffle_ps(tmm5, tmm6, 0x88);
tmm6 = _mm_add_ps(tmm6, tmm5);
// tmm5 = A2+A4 B2+B4 C2+C4 D2+D4
// tmm6 = A1+A2+A3+A4 B1+B2+B3+B4
// C1+C2+C3+C4 D1+D2+D3+D4
_mm_store_ps(out, tmm6);
}
6.5.2
Use of CVTTPS2PI/CVTTSS2SI Instructions
The CVTTPS2PI and CVTTSS2SI instructions encode the truncate/chop rounding mode implicitly in the
instruction. They take precedence over the rounding mode specified in the MXCSR register. This behavior
can eliminate the need to change the rounding mode from round-nearest, to truncate/chop, and then
back to round-nearest to resume computation.
Avoid frequent changes to the MXCSR register since there is a penalty associated with writing this
register. Typically, when using CVTTPS2P/CVTTSS2SI, rounding control in MXCSR can always be set to
round-nearest.
6.5.3
Flush-to-Zero and Denormals-are-Zero Modes
The flush-to-zero (FTZ) and denormals-are-zero (DAZ) modes are not compatible with the IEEE Standard 754. They are provided to improve performance for applications where underflow is common and
where the generation of a denormalized result is not necessary.
6-10
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
See also: Section 3.8.3, “Floating-point Modes and Exceptions.”
6.6
SIMD OPTIMIZATIONS AND MICROARCHITECTURES
Pentium M, Intel Core Solo and Intel Core Duo processors have a different microarchitecture than Intel
NetBurst microarchitecture. Intel Core microarchitecture offers significantly more efficient SIMD floatingpoint capability than previous microarchitectures. In addition, instruction latency and throughput of
SSE3 instructions are significantly improved in Intel Core microarchitecture over previous microarchitectures.
6.6.1
SIMD Floating-point Programming Using SSE3
SSE3 enhances SSE and SSE2 with nine instructions targeted for SIMD floating-point programming. In
contrast to many SSE/SSE2 instructions offering homogeneous arithmetic operations on parallel data
elements and favoring the vertical computation model, SSE3 offers instructions that performs asymmetric arithmetic operation and arithmetic operation on horizontal data elements.
ADDSUBPS and ADDSUBPD are two instructions with asymmetric arithmetic processing capability (see
Figure 6-5). HADDPS, HADDPD, HSUBPS and HSUBPD offers horizontal arithmetic processing capability
(see Figure 6-6). In addition: MOVSLDUP, MOVSHDUP and MOVDDUP load data from memory (or XMM
register) and replicate data elements at once.
X1
X0
Y1
Y0
ADD
SUB
X1 + Y1
X0 -Y0
Figure 6-5. Asymmetric Arithmetic Operation of the SSE3 Instruction
X1
X0
Y1
Y0
ADD
ADD
Y0 + Y1
X0 + X1
Figure 6-6. Horizontal Arithmetic Operation of the SSE3 Instruction HADDPD
6-11
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
6.6.1.1
SSE3 and Complex Arithmetics
The flexibility of SSE3 in dealing with AOS-type of data structure can be demonstrated by the example of
multiplication and division of complex numbers. For example, a complex number can be stored in a structure consisting of its real and imaginary part. This naturally leads to the use of an array of structure.
Example 6-9 demonstrates using SSE3 instructions to perform multiplications of single-precision
complex numbers. Example 6-10 demonstrates using SSE3 instructions to perform division of complex
numbers.
Example 6-9. Multiplication of Two Pair of Single-precision Complex Number
// Multiplication of (ak + i bk ) * (ck + i dk )
// a + i b can be stored as a data structure
movsldup xmm0, Src1; load real parts into the destination,
; a1, a1, a0, a0
movaps xmm1, src2; load the 2nd pair of complex values,
; i.e. d1, c1, d0, c0
mulps xmm0, xmm1; temporary results, a1d1, a1c1, a0d0,
; a0c0
shufps xmm1, xmm1, b1; reorder the real and imaginary
; parts, c1, d1, c0, d0
movshdup xmm2, Src1; load the imaginary parts into the
; destination, b1, b1, b0, b0
mulps xmm2, xmm1; temporary results, b1c1, b1d1, b0c0,
; b0d0
addsubps xmm0, xmm2; b1c1+a1d1, a1c1 -b1d1, b0c0+a0d0,
; a0c0-b0d0
Example 6-10. Division of Two Pair of Single-precision Complex Numbers
// Division of (ak + i bk ) / (ck + i dk )
movshdup xmm0, Src1; load imaginary parts into the
; destination, b1, b1, b0, b0
movaps xmm1, src2; load the 2nd pair of complex values,
; i.e. d1, c1, d0, c0
mulps xmm0, xmm1; temporary results, b1d1, b1c1, b0d0,
; b0c0
shufps xmm1, xmm1, b1; reorder the real and imaginary
; parts, c1, d1, c0, d0
movsldup xmm2, Src1; load the real parts into the
; destination, a1, a1, a0, a0
mulps xmm2, xmm1; temp results, a1c1, a1d1, a0c0, a0d0
addsubps xmm0, xmm2; a1c1+b1d1, b1c1-a1d1, a0c0+b0d0,
; b0c0-a0d0
mulps
movps
shufps
addps
6-12
xmm1, xmm1 ; c1c1, d1d1, c0c0, d0d0
xmm2, xmm1; c1c1, d1d1, c0c0, d0d0
xmm2, xmm2, b1; d1d1, c1c1, d0d0, c0c0
xmm2, xmm1; c1c1+d1d1, c1c1+d1d1, c0c0+d0d0,
; c0c0+d0d0
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-10. Division of Two Pair of Single-precision Complex Numbers (Contd.)
divps xmm0, xmm2
shufps xmm0, xmm0, b1 ; (b1c1-a1d1)/(c1c1+d1d1),
; (a1c1+b1d1)/(c1c1+d1d1),
; (b0c0-a0d0)/( c0c0+d0d0),
; (a0c0+b0d0)/( c0c0+d0d0)
In both examples, the complex numbers are store in arrays of structures. MOVSLDUP, MOVSHDUP and
the asymmetric ADDSUBPS allow performing complex arithmetics on two pair of single-precision
complex number simultaneously and without any unnecessary swizzling between data elements.
Due to microarchitectural differences, software should implement multiplication of complex doubleprecision numbers using SSE3 instructions on processors based on Intel Core microarchitecture. In Intel
Core Duo and Intel Core Solo processors, software should use scalar SSE2 instructions to implement
double-precision complex multiplication. This is because the data path between SIMD execution units is
128 bits in Intel Core microarchitecture, and only 64 bits in previous microarchitectures. Processors
based on the Enhanced Intel Core microarchitecture generally executes SSE3 instruction more efficiently
than previous microarchitectures, they also have a 128-bit shuffle unit that will benefit complex arithmetic operations further than Intel Core microarchitecture did.
Example 6-11 shows two equivalent implementations of double-precision complex multiply of two pair of
complex numbers using vector SSE2 versus SSE3 instructions. Example 6-12 shows the equivalent
scalar SSE2 implementation.
Example 6-11. Double-Precision Complex Multiplication of Two Pairs
SSE2 Vector Implementation
SSE3 Vector Implementation
movapd xmm0, [eax] ;y x
movapd xmm1, [eax+16] ;w z
unpcklpd xmm1, xmm1 ;z z
movapd xmm2, [eax+16] ;w z
unpckhpd xmm2, xmm2 ;w w
mulpd xmm1, xmm0 ;z*y z*x
mulpd xmm2, xmm0 ;w*y w*x
xorpd xmm2, xmm7 ;-w*y +w*x
shufpd xmm2, xmm2,1 ;w*x -w*y
addpd xmm2, xmm1 ;z*y+w*x z*x-w*y
movapd [ecx], xmm2
movapd xmm0, [eax] ;y x
movapd xmm1, [eax+16] ;z z
movapd xmm2, xmm1
unpcklpd xmm1, xmm1
unpckhpd xmm2, xmm2
mulpd xmm1, xmm0 ;z*y z*x
mulpd xmm2, xmm0 ;w*y w*x
shufpd xmm2, xmm2, 1 ;w*x w*y
addsubpd xmm1, xmm2 ;w*x+z*y z*x-w*y
movapd [ecx], xmm1
Example 6-12. Double-Precision Complex Multiplication Using Scalar SSE2
movsd
movsd
movsd
movsd
xmm0, [eax]
;x
xmm5, [eax+8]
;y
xmm1, [eax+16] ;z
xmm2, [eax+24] ;w
movsd
movsd
mulsd
mulsd
mulsd
xmm3, xmm1 ;z
xmm4, xmm2 ;w
xmm1, xmm0 ;z*x
xmm2, xmm0 ;w*x
xmm3, xmm5 ;z*y
6-13
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-12. Double-Precision Complex Multiplication Using Scalar SSE2 (Contd.)
mulsd
subsd
addsd
movsd
movsd
xmm4, xmm5 ;w*y
xmm1, xmm4 ;z*x - w*y
xmm3, xmm2 ;z*y + w*x
[ecx], xmm1
[ecx+8], xmm3
6.6.1.2
Packed Floating-Point Performance in Intel Core Duo Processor
Most packed SIMD floating-point code will speed up on Intel Core Solo processors relative to Pentium M
processors. This is due to improvement in decoding packed SIMD instructions.
The improvement of packed floating-point performance on the Intel Core Solo processor over Pentium M
processor depends on several factors. Generally, code that is decoder-bound and/or has a mixture of
integer and packed floating-point instructions can expect significant gain. Code that is limited by execution latency and has a “cycles per instructions” ratio greater than one will not benefit from decoder
improvement.
When targeting complex arithmetics on Intel Core Solo and Intel Core Duo processors, using singleprecision SSE3 instructions can deliver higher performance than alternatives. On the other hand, tasks
requiring double-precision complex arithmetics may perform better using scalar SSE2 instructions on
Intel Core Solo and Intel Core Duo processors. This is because scalar SSE2 instructions can be dispatched
through two ports and executed using two separate floating-point units.
Packed horizontal SSE3 instructions (HADDPS and HSUBPS) can simplify the code sequence for some
tasks. However, these instruction consist of more than five micro-ops on Intel Core Solo and Intel Core
Duo processors. Care must be taken to ensure the latency and decoding penalty of the horizontal instruction does not offset any algorithmic benefits.
6.6.2
Dot Product and Horizontal SIMD Instructions
Sometimes the AOS type of data organization are more natural in many algebraic formula, one common
example is the dot product operation. Dot product operation can be implemented using SSE/SSE2
instruction sets. SSE3 added a few horizontal add/subtract instructions for applications that rely on the
horizontal computation model. SSE4.1 provides additional enhancement with instructions that are
capable of directly evaluating dot product operations of vectors of 2, 3 or 4 components.
Example 6-13. Dot Product of Vector Length 4 Using SSE/SSE2
Using SSE/SSE2 to compute one dot product
movaps xmm0, [eax] // a4, a3, a2, a1
mulps xmm0, [eax+16] // a4*b4, a3*b3, a2*b2, a1*b1
movhlps xmm1, xmm0 // X, X, a4*b4, a3*b3, upper half not needed
addps xmm0, xmm1 // X, X, a2*b2+a4*b4, a1*b1+a3*b3,
pshufd xmm1, xmm0, 1 // X, X, X, a2*b2+a4*b4
addss xmm0, xmm1 // a1*b1+a3*b3+a2*b2+a4*b4
movss [ecx], xmm0
6-14
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-14. Dot Product of Vector Length 4 Using SSE3
Using SSE3 to compute one dot product
movaps xmm0, [eax]
mulps xmm0, [eax+16] // a4*b4, a3*b3, a2*b2, a1*b1
haddps xmm0, xmm0 // a4*b4+a3*b3, a2*b2+a1*b1, a4*b4+a3*b3, a2*b2+a1*b1
movaps xmm1, xmm0 // a4*b4+a3*b3, a2*b2+a1*b1, a4*b4+a3*b3, a2*b2+a1*b1
psrlq xmm0, 32 // 0, a4*b4+a3*b3, 0, a4*b4+a3*b3
addss xmm0, xmm1 // -, -, -, a1*b1+a3*b3+a2*b2+a4*b4
movss [eax], xmm0
Example 6-15. Dot Product of Vector Length 4 Using SSE4.1
Using SSE4.1 to compute one dot product
movaps xmm0, [eax]
dpps xmm0, [eax+16], 0xf1 // 0, 0, 0, a1*b1+a3*b3+a2*b2+a4*b4
movss [eax], xmm0
Example 6-13, Example 6-14, and Example 6-15 compare the basic code sequence to compute one dotproduct result for a pair of vectors.
The selection of an optimal sequence in conjunction with an application’s memory access patterns may
favor different approaches. For example, if each dot product result is immediately consumed by additional computational sequences, it may be more optimal to compare the relative speed of these different
approaches. If dot products can be computed for an array of vectors and kept in the cache for subsequent
computations, then more optimal choice may depend on the relative throughput of the sequence of
instructions.
In Intel Core microarchitecture, Example 6-14 has higher throughput than Example 6-13. Due to the
relatively longer latency of HADDPS, the speed of Example 6-14 is slightly slower than Example 6-13.
In Enhanced Intel Core microarchitecture, Example 6-15 is faster in both speed and throughput than
Example 6-13 and Example 6-14. Although the latency of DPPS is also relatively long, it is compensated
by the reduction of number of instructions in Example 6-15 to do the same amount of work.
Unrolling can further improve the throughput of each of three dot product implementations.
Example 6-16 shows two unrolled versions using the basic SSE2 and SSE3 sequences. The SSE4.1
version can also be unrolled and using INSERTPS to pack 4 dot-product results.
Example 6-16. Unrolled Implementation of Four Dot Products
SSE2 Implementation
SSE3 Implementation
movaps xmm0, [eax]
mulps xmm0, [eax+16]
;w0*w1 z0*z1 y0*y1 x0*x1
movaps xmm2, [eax+32]
mulps xmm2, [eax+16+32]
;w2*w3 z2*z3 y2*y3 x2*x3
movaps xmm3, [eax+64]
mulps xmm3, [eax+16+64]
;w4*w5 z4*z5 y4*y5 x4*x5
movaps xmm4, [eax+96]
mulps xmm4, [eax+16+96]
;w6*w7 z6*z7 y6*y7 x6*x7
movaps xmm0, [eax]
mulps xmm0, [eax+16]
movaps xmm1, [eax+32]
mulps xmm1, [eax+16+32]
movaps xmm2, [eax+64]
mulps xmm2, [eax+16+64]
movaps xmm3, [eax+96]
mulps xmm3, [eax+16+96]
haddps xmm0, xmm1
haddps xmm2, xmm3
haddps xmm0, xmm2
movaps [ecx], xmm0
6-15
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-16. Unrolled Implementation of Four Dot Products (Contd.)
SSE2 Implementation
SSE3 Implementation
movaps xmm1, xmm0
unpcklps xmm0, xmm2
; y2*y3 y0*y1 x2*x3 x0*x1
unpckhps xmm1, xmm2
; w2*w3 w0*w1 z2*z3 z0*z1
movaps xmm5, xmm3
unpcklps xmm3, xmm4
; y6*y7 y4*y5 x6*x7 x4*x5
unpckhps xmm5, xmm4
; w6*w7 w4*w5 z6*z7 z4*z5
addps xmm0, xmm1
addps xmm5, xmm3
movaps xmm1, xmm5
movhlps xmm1, xmm0
movlhps xmm0, xmm5
addps xmm0, xmm1
movaps [ecx], xmm0
6.6.3
Vector Normalization
Normalizing vectors is a common operation in many floating-point applications. Example 6-17 shows an
example in C of normalizing an array of (x, y, z) vectors.
Example 6-17. Normalization of an Array of Vectors
for (i=0;i<CNT;i++)
{ float size = nodes[i].vec.dot();
if (size != 0.0)
{ size = 1.0f/sqrtf(size); }
else
{ size = 0.0; }
nodes[i].vec.x *= size;
nodes[i].vec.y *= size;
nodes[i].vec.z *= size;
}
Example 6-18 shows an assembly sequence that normalizes the x, y, z components of a vector.
6-16
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-18. Normalize (x, y, z) Components of an Array of Vectors Using SSE2
Vec3 *p = &nodes[i].vec;
__asm
{ mov
eax, p
xorps
xmm2, xmm2
movups xmm1, [eax] // loads the (x, y, z) of input vector plus x of next vector
movaps xmm7, xmm1 // save a copy of data from memory (to restore the unnormalized value)
movaps xmm5, _mask // mask to select (x, y, z) values from an xmm register to normalize
andps xmm1, xmm5 // mask 1st 3 elements
movaps xmm6, xmm1 // save a copy of (x, y, z) to compute normalized vector later
mulps
xmm1,xmm1 // 0, z*z, y*y, x*x
pshufd xmm3, xmm1, 0x1b // x*x, y*y, z*z, 0
addps
xmm1, xmm3 // x*x, z*z+y*y, z*z+y*y, x*x
pshufd xmm3, xmm1, 0x41 // z*z+y*y, x*x, x*x, z*z+y*y
addps
xmm1, xmm3 // x*x+y*y+z*z, x*x+y*y+z*z, x*x+y*y+z*z, x*x+y*y+z*z
comisd xmm1, xmm2 // compare size to 0
jz zero
movaps xmm3, xmm4// preloaded unitary vector (1.0, 1.0, 1.0, 1.0)
sqrtps xmm1, xmm1
divps
xmm3, xmm1
jmp
store
zero:
movaps xmm3, xmm2
store:
mulps
andnps
orps
movaps
xmm3, xmm6 //normalize the vector in the lower 3 elements
xmm5, xmm7 // mask off the lower 3 elements to keep the un-normalized value
xmm3, xmm5 // order the un-normalized component after the normalized vector
[eax ], xmm3 // writes normalized x, y, z; followed by unmodified value
Example 6-19 shows an assembly sequence using SSE4.1 to normalizes the x, y, z components of a
vector.
6-17
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-19. Normalize (x, y, z) Components of an Array of Vectors Using SSE4.1
Vec3 *p = &nodes[i].vec;
__asm
{ mov
eax, p
xorps
xmm2, xmm2
movups xmm1, [eax] // loads the (x, y, z) of input vector plus x of next vector
movaps xmm7, xmm1 // save a copy of data from memory
dpps
xmm1, xmm1, 0x7f // x*x+y*y+z*z, x*x+y*y+z*z, x*x+y*y+z*z, x*x+y*y+z*z
comisd xmm1, xmm2 // compare size to 0
jz zero
movaps xmm3, xmm4// preloaded unitary vector (1.0, 1.0, 1.0, 1.0)
sqrtps xmm1, xmm1
divps
xmm3, xmm1
jmp
store
zero:
movaps xmm3, xmm2
store:
mulps
xmm3, xmm6 //normalize the vector in the lower 3 elements
blendps xmm3, xmm7, 0x8 // copy the un-normalized component next to the normalized vector
movaps [eax ], xmm3
In Example 6-18 and Example 6-19, the throughput of these instruction sequences are basically limited
by the long-latency instructions of DIVPS and SQRTPS. In Example 6-19, the use of DPPS replaces eight
SSE2 instructions to evaluate and broadcast the dot-product result to four elements of an XMM register.
This could result in improvement of the relative speed of Example 6-19 over Example 6-18.
6.6.4
Using Horizontal SIMD Instruction Sets and Data Layout
SSE and SSE2 provide packed add/subtract, multiply/divide instructions that are ideal for situations that
can take advantage of vertical computation model, such as SOA data layout. SSE3 and SSE4.1 added
horizontal SIMD instructions including horizontal add/subtract, dot-product operations. These more
recent SIMD extensions provide tools to solve problems involving data layouts or operations that do not
conform to the vertical SIMD computation model.
In this section, we consider a vector-matrix multiplication problem and discuss the relevant factors for
choosing various horizontal SIMD instructions.
Example 6-20 shows the vector-matrix data layout in AOS, where the input and out vectors are stored as
an array of structure.
6-18
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-20. Data Organization in Memory for AOS Vector-Matrix Multiplication
Matrix M4x4 (pMat): M00 M01 M02 M03
M10 M11 M12 M13
M20 M21 M22 M23
M30 M31 M32 M33
4 input vertices V4x1 (pVert): V0x V0y V0z V0w
V1x V1y V1z V1w
V2x V2y V2z V2w
V3x V3y V3z V3w
Output vertices O4x1 (pOutVert): O0x O0y O0z O0w
O1x O1y O1z O1w
O2x O2y O2z O2w
O3x O3y O3z O3w
Example 6-21 shows an example using HADDPS and MULPS to perform vector-matrix multiplication with
data layout in AOS. After three HADDPS completing the summations of each output vector component,
the output components are arranged in AOS.
Example 6-21. AOS Vector-Matrix Multiplication with HADDPS
mov
mov
mov
xor
movaps
movaps
movaps
lloop:
movaps
movaps
mulps
movaps
mulps
movaps
mulps
movaps
mulps
haddps
haddps
haddps
movaps
add
cmp
jb lloop
eax, pMat
ebx, pVert
ecx, pOutVert
edx, edx
xmm5,[eax+16] // load row M1?
xmm6,[eax+2*16] // load row M2?
xmm7,[eax+3*16] // load row M3?
xmm4, [ebx + edx] // load input vector
xmm0, xmm4
xmm0, [eax] // m03*vw, m02*vz, m01*vy, m00*vx,
xmm1, xmm4
xmm1, xmm5 // m13*vw, m12*vz, m11*vy, m10*vx,
xmm2, xmm4
xmm2, xmm6// m23*vw, m22*vz, m21*vy, m20*vx
xmm3, xmm4
xmm3, xmm7 // m33*vw, m32*vz, m31*vy, m30*vx,
xmm0, xmm1
xmm2, xmm3
xmm0, xmm2
[ecx + edx], xmm0// store a vector of length 4
edx, 16
edx, top
Example 6-22 shows an example using DPPS to perform vector-matrix multiplication in AOS.
6-19
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-22. AOS Vector-Matrix Multiplication with DPPS
mov
mov
mov
xor
movaps
movaps
movaps
lloop:
movaps
movaps
dpps
movaps
dpps
movaps
dpps
movaps
dpps
movss
movss
movss
movss
add
cmp
jb
eax, pMat
ebx, pVert
ecx, pOutVert
edx, edx
xmm5,[eax+16] // load row M1?
xmm6,[eax+2*16] // load row M2?
xmm7,[eax+3*16] // load row M3?
xmm4, [ebx + edx] // load input vector
xmm0, xmm4
xmm0, [eax], 0xf1// calculate dot product of length 4, store to lowest dword
xmm1, xmm4
xmm1, xmm5, 0xf1
xmm2, xmm4
xmm2, xmm6, 0xf1
xmm3, xmm4
xmm3, xmm7, 0xf1
[ecx + edx + 0*4], xmm0// store one element of vector length 4
[ecx + edx + 1*4], xmm1
[ecx + edx + 2*4], xmm2
[ecx + edx + 3*4], xmm3
edx, 16
edx, top
lloop
Example 6-21 and Example 6-22 both work with AOS data layout using different horizontal processing
techniques provided by SSE3 and SSE4.1. The effectiveness of either techniques will vary, depending on
the degree of exposures of long-latency instruction in the inner loop, the overhead/efficiency of data
movement, and the latency of HADDPS vs. DPPS.
On processors that support both HADDPS and DPPS, the choice between either technique may depend on
application-specific considerations. If the output vectors are written back to memory directly in a batch
situation, Example 6-21 may be preferable over Example 6-22, because the latency of DPPS is long and
storing each output vector component individually is less than ideal for storing an array of vectors.
There may be partially-vectorizable situations that the individual output vector component is consumed
immediately by other non-vectorizable computations. Then, using DPPS producing individual component
may be more suitable than dispersing the packed output vector produced by three HADDPS as in
Example 6-21.
6.6.4.1
SOA and Vector Matrix Multiplication
If the native data layout of a problem conforms to SOA, then vector-matrix multiply can be coded using
MULPS, ADDPS without using the longer-latency horizontal arithmetic instructions, or packing scalar
components into packed format (Example 6-22). To achieve higher throughput with SOA data layout,
there are either pre-requisite data preparation or swizzling/deswizzling on-the-fly that must be comprehended. For example, an SOA data layout for vector-matrix multiplication is shown in Example 6-23.
6-20
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Each matrix element is replicated four times to minimize data movement overhead for producing packed
results.
Example 6-23. Data Organization in Memory for SOA Vector-Matrix Multiplication
Matrix M16x4 (pMat):
M00 M00 M00 M00 M01 M01 M01 M01 M02 M02 M02 M02 M03 M03 M03 M03
M10 M10 M10 M10 M11 M11 M11 M11 M12 M12 M12 M12 M13 M13 M13 M13
M20 M20 M20 M20 M21 M21 M21 M21 M22 M22 M22 M22 M23 M23 M23 M23
M30 M30 M30 M30 M31 M31 M31 M31 M32 M32 M32 M32 M33 M33 M33 M33
4 input vertices V4x1 (pVert): V0x V1x V2x V3x
V0y V1y V2y V3y
V0z V1z V2z V3z
V0w V1w V2w V3w
Ouput vertices O4x1 (pOutVert): O0x O1x O2x O3x
O0y O1y O2y O3y
O0z O1z O2z O3z
O0w O1w O2w O3w
The corresponding vector-matrix multiply example in SOA (unrolled for four iteration of vectors) is shown
in Example 6-24.
6-21
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS
Example 6-24. Vector-Matrix Multiplication with Native SOA Data Layout
mov
ebx, pVert
mov
ecx, pOutVert
xor
edx, edx
movaps xmm5,[eax+16] // load row M1?
movaps xmm6,[eax+2*16] // load row M2?
movaps xmm7,[eax+3*16] // load row M3?
lloop_vert:
mov
eax, pMat
xor
edi, edi
movaps xmm0, [ebx ] // load V3x, V2x, V1x, V0x
movaps xmm1, [ebx ] // load V3y, V2y, V1y, V0y
movaps xmm2, [ebx ] // load V3z, V2z, V1z, V0z
movaps xmm3, [ebx ] // load V3w, V2w, V1w, V0w
loop_mat:
movaps xmm4, [eax] // m00, m00, m00, m00,
mulps
xmm4, xmm0 // m00*V3x, m00*V2x, m00*V1x, m00*V0x,
movaps xmm4, [eax + 16] // m01, m01, m01, m01,
mulps
xmm5, xmm1 // m01*V3y, m01*V2y, m01*V1y, m01*V0y,
addps
xmm4, xmm5
movaps xmm5, [eax + 32] // m02, m02, m02, m02,
mulps
xmm5, xmm2 // m02*V3z, m02*V2z, m02*V1z, m02*V0z,
addps
xmm4, xmm5
movaps xmm5, [eax + 48] // m03, m03, m03, m03,
mulps
xmm5, xmm3 // m03*V3w, m03*V2w, m03*V1w, m03*V0w,
addps
xmm4, xmm5
movaps [ecx + edx], xmm4
add
eax, 64
add
edx, 16
add
edi, 1
cmp
edi, 4
jb lloop_mat
add
ebx, 64
cmp
edx, top
jb lloop_vert
6-22
CHAPTER 7
OPTIMIZING CACHE USAGE
Over the past decade, processor speed has increased. Memory access speed has increased at a slower
pace. The resulting disparity has made it important to tune applications in one of two ways: either (a) a
majority of data accesses are fulfilled from processor caches, or (b) effectively masking memory latency
to utilize peak memory bandwidth as much as possible.
Hardware prefetching mechanisms are enhancements in microarchitecture to facilitate the latter aspect,
and will be most effective when combined with software tuning. The performance of most applications
can be considerably improved if the data required can be fetched from the processor caches or if memory
traffic can take advantage of hardware prefetching effectively.
Standard techniques to bring data into the processor before it is needed involve additional programming
which can be difficult to implement and may require special steps to prevent performance degradation.
Streaming SIMD Extensions addressed this issue by providing various prefetch instructions.
Streaming SIMD Extensions introduced the various non-temporal store instructions. SSE2 extends this
support to new data types and also introduce non-temporal store support for the 32-bit integer registers.
This chapter focuses on:
•
Hardware Prefetch Mechanism, Software Prefetch and Cacheability Instructions — Discusses microarchitectural feature and instructions that allow you to affect data caching in an application.
•
Memory Optimization Using Hardware Prefetching, Software Prefetch and Cacheability Instructions
— Discusses techniques for implementing memory optimizations using the above instructions.
NOTE
In a number of cases presented, the prefetching and cache utilization described are
specific to current implementations of Intel NetBurst microarchitecture but are largely
applicable for the future processors.
•
Using deterministic cache parameters to manage cache hierarchy.
7.1
GENERAL PREFETCH CODING GUIDELINES
The following guidelines will help you to reduce memory traffic and utilize peak memory system bandwidth more effectively when large amounts of data movement must originate from the memory system:
•
Take advantage of the hardware prefetcher’s ability to prefetch data that are accessed in linear
patterns, in either a forward or backward direction.
•
Take advantage of the hardware prefetcher’s ability to prefetch data that are accessed in a regular
pattern with access strides that are substantially smaller than half of the trigger distance of the
hardware prefetch.
•
Facilitate compiler optimization by:
— Minimize use of global variables and pointers.
— Minimize use of complex control flow.
— Use the const modifier, avoid register modifier.
— Choose data types carefully (see below) and avoid type casting.
•
Use cache blocking techniques (for example, strip mining) as follows:
— Improve cache hit rate by using cache blocking techniques such as strip-mining (one dimensional
arrays) or loop blocking (two dimensional arrays).
OPTIMIZING CACHE USAGE
— Explore using hardware prefetching mechanism if your data access pattern has sufficient
regularity to allow alternate sequencing of data accesses (for example: tiling) for improved
spatial locality. Otherwise use PREFETCHNTA.
•
Balance single-pass versus multi-pass execution:
— Single-pass, or unlayered execution passes a single data element through an entire computation
pipeline.
— Multi-pass, or layered execution performs a single stage of the pipeline on a batch of data
elements before passing the entire batch on to the next stage.
— If your algorithm is single-pass use PREFETCHNTA. If your algorithm is multi-pass use
PREFETCHT0.
•
Resolve memory bank conflict issues. Minimize memory bank conflicts by applying array grouping to
group contiguously used data together or by allocating data within 4-KByte memory pages.
•
Resolve cache management issues. Minimize the disturbance of temporal data held within
processor’s caches by using streaming store instructions.
•
Optimize software prefetch scheduling distance:
— Far ahead enough to allow interim computations to overlap memory access time.
— Near enough that prefetched data is not replaced from the data cache.
•
Use software prefetch concatenation. Arrange prefetches to avoid unnecessary prefetches at the end
of an inner loop and to prefetch the first few iterations of the inner loop inside the next outer loop.
•
Minimize the number of software prefetches. Prefetch instructions are not completely free in terms of
bus cycles, machine cycles and resources; excessive usage of prefetches can adversely impact
application performance.
•
Interleave prefetches with computation instructions. For best performance, software prefetch
instructions must be interspersed with computational instructions in the instruction sequence (rather
than clustered together).
7.2
PREFETCH AND CACHEABILITY INSTRUCTIONS
The PREFETCH instruction, inserted by the programmers or compilers, accesses a minimum of two cache
lines of data on the Pentium 4 processor prior to the data actually being needed (one cache line of data
on the Pentium M processor). This hides the latency for data access in the time required to process data
already resident in the cache.
Many algorithms can provide information in advance about the data that is to be required. In cases where
memory accesses are in long, regular data patterns; the automatic hardware prefetcher should be
favored over software prefetches.
The cacheability control instructions allow you to control data caching strategy in order to increase cache
efficiency and minimize cache pollution.
Data reference patterns can be classified as follows:
•
•
•
Temporal — Data will be used again soon.
Spatial — Data will be used in adjacent locations (for example, on the same cache line).
Non-temporal — Data which is referenced once and not reused in the immediate future (for example,
for some multimedia data types, as the vertex buffer in a 3D graphics application).
These data characteristics are used in the discussions that follow.
7-2
OPTIMIZING CACHE USAGE
7.3
PREFETCH
This section discusses the mechanics of the software PREFETCH instructions. In general, software
prefetch instructions should be used to supplement the practice of tuning an access pattern to suit the
automatic hardware prefetch mechanism.
7.3.1
Software Data Prefetch
The PREFETCH instruction can hide the latency of data access in performance-critical sections of application code by allowing data to be fetched in advance of actual usage. PREFETCH instructions do not
change the user-visible semantics of a program, although they may impact program performance.
PREFETCH merely provides a hint to the hardware and generally does not generate exceptions or faults.
PREFETCH loads either non-temporal data or temporal data in the specified cache level. This data access
type and the cache level are specified as a hint. Depending on the implementation, the instruction
fetches 32 or more aligned bytes (including the specified address byte) into the instruction-specified
cache levels.
PREFETCH is implementation-specific; applications need to be tuned to each implementation to maximize performance.
NOTE
Using the PREFETCH instruction is recommended only if data does not fit in cache. Use of
software prefetch should be limited to memory addresses that are managed or owned
within the application context. Prefetching to addresses that are not mapped to physical
pages can experience non-deterministic performance penalty. For example specifying a
NULL pointer (0L) as address for a prefetch can cause long delays.
PREFETCH provides a hint to the hardware; it does not generate exceptions or faults except for a few
special cases (see Section 7.3.3, “Prefetch and Load Instructions”). However, excessive use of PREFETCH
instructions may waste memory bandwidth and result in a performance penalty due to resource
constraints.
Nevertheless, PREFETCH can lessen the overhead of memory transactions by preventing cache pollution
and by using caches and memory efficiently. This is particularly important for applications that share critical system resources, such as the memory bus. See an example in Section 7.6.2.1, “Video Encoder.”
PREFETCH is mainly designed to improve application performance by hiding memory latency in the background. If segments of an application access data in a predictable manner (for example, using arrays
with known strides), they are good candidates for using PREFETCH to improve performance.
Use the PREFETCH instructions in:
•
•
•
Predictable memory access patterns.
Time-consuming innermost loops.
Locations where the execution pipeline may stall if data is not available.
7.3.2
Prefetch Instructions
Streaming SIMD Extensions include four PREFETCH instruction variants; one non-temporal and three
temporal. They correspond to two types of operations, temporal and non-temporal.
Additionally, the PREFETCHW instruction is a hint to fetch data closer to the processor and invalidates any
other cached copy in anticipation of a write.
NOTE
At the time of PREFETCH, if data is already found in a cache level that is closer to the
processor than the cache level specified by the instruction, no data movement occurs.
7-3
OPTIMIZING CACHE USAGE
The implementation details of the prefetch hint instructions vary across different microarchitectures. A
summary is given below.
•
PREFETCHNTA — fetch data into non-temporal cache close to the processor, minimizing cache
pollution.
— Pentium III processor: 1st level cache.
— Processors based on Intel NetBurst microarchitecture: 2nd level cache.
— Intel Core duo, Core 2 processors, Intel Atom processors: 1st but not 2nd level cache.
— Intel Core Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 1st, but not 2nd level cache; may fetch into 3rd level cache with fast replacement.
— Intel Xeon Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: must fetch into 3rd level cache with fast replacement.
•
PREFETCHT0 — fetch data into all cache levels.
— Pentium III processor: 1st and 2nd level cache.
— Processors based on Intel NetBurst microarchitecture: 2nd level cache.
— Intel Core duo, Core 2 processors, Intel Atom processors: 1st and 2nd level cache.
— Intel Core Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 1st, 2nd and 3rd level cache.
— Intel Xeon Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 1st, 2nd and 3rd level cache.
•
PREFETCHT1 — fetch data into 2nd and 3rd level caches.
— Pentium III processor: 2nd level cache.
— Processors based on Intel NetBurst microarchitecture: 2nd level cache.
— Intel Core duo, Core 2 processors, Intel Atom processors: 2nd level cache.
— Intel Core Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 2nd and 3rd level cache.
— Intel Xeon Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 2nd and 3rd level cache.
•
PREFETCHT2 — this instruction is identical to PREFETCHT1.
— Pentium III processor: 2nd level cache.
— Processors based on Intel NetBurst microarchitecture: 2nd level cache.
— Intel Core duo, Core 2 processors, Intel Atom processors: 2nd level cache.
— Intel Core Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 2nd and 3rd level cache.
— Intel Xeon Processors based on Nehalem, Westmere, Sandy Bridge and newer microarchitectures: 2nd and 3rd level cache.
•
PREFETCHW — fetch data into cache in anticipation of write; invalidate cached copies.
— Intel Atom processors based on Silvermont and newer microarchitectures: 1st and 2nd level
cache.
— Intel Core Processors based on Broadwell and Skylake microarchitectures: 1st, 2nd and 3rd level
cache.
— Intel Xeon Processors based on Broadwell and Skylake microarchitectures: 1st, 2nd and 3rd level
cache.
7-4
OPTIMIZING CACHE USAGE
7.3.3
Prefetch and Load Instructions
Most of the recent generations of microarchitectures have decoupled execution and memory pipelines.
This allows instructions to be executed independently with memory accesses if there are no data and
resource dependencies. Programs or compilers can use dummy load instructions to imitate PREFETCH
functionality, but preloading is not completely equivalent to using PREFETCH instructions. PREFETCH
provides greater performance than preloading.
PREFETCH can provide greater performance than preloading because:
•
•
•
•
•
Has no destination register, it only updates cache lines.
•
Does not complete its own execution if that would cause a fault.
Does not stall the normal instruction retirement.
Does not affect the functional behavior of the program.
Has no cache line split accesses.
Does not cause exceptions except when the LOCK prefix is used. The LOCK prefix is not a valid prefix
for use with PREFETCH.
The advantages of PREFETCH over preloading instructions are processor specific. This may change in the
future.
There are cases where a PREFETCH will not perform the data prefetch. These include:
•
In older microarchitectures, PREFETCH causing a Data Translation Lookaside Buffer (DTLB) miss
would be dropped. In processors based on Nehalem, Westmere, Sandy Bridge, and newer microarchitectures, Intel Core 2 processors, and Intel Atom processors, PREFETCH causing a DTLB miss can
be fetched across a page boundary.
•
•
An access to the specified address that causes a fault/exception.
•
•
PREFETCH targets an uncacheable memory region (for example, USWC and UC).
If the memory subsystem runs out of request buffers between the first-level cache and the second-level
cache.
The LOCK prefix is used. This causes an invalid opcode exception.
7.4
CACHEABILITY CONTROL
This section covers the mechanics of cacheability control instructions.
7.4.1
The Non-temporal Store Instructions
This section describes the behavior of streaming stores and reiterates some of the information presented
in the previous section.
In Streaming SIMD Extensions, the MOVNTPS, MOVNTPD, MOVNTQ, MOVNTDQ, MOVNTI, MASKMOVQ
and MASKMOVDQU instructions are streaming, non-temporal stores. With regard to memory characteristics and ordering, they are similar to the Write-Combining (WC) memory type:
•
•
•
Write combining — Successive writes to the same cache line are combined.
•
Uncacheable and not write-allocating — Stored data is written around the cache and will not generate
a read-for-ownership bus request for the corresponding cache line.
Write collapsing — Successive writes to the same byte(s) result in only the last write being visible.
Weakly ordered — No ordering is preserved between WC stores or between WC stores and other
loads or stores.
7-5
OPTIMIZING CACHE USAGE
7.4.1.1
Fencing
Because streaming stores are weakly ordered, a fencing operation is required to ensure that the stored
data is flushed from the processor to memory. Failure to use an appropriate fence may result in data
being “trapped” within the processor and will prevent visibility of this data by other processors or system
agents.
WC stores require software to ensure coherence of data by performing the fencing operation. See Section
7.4.5, “FENCE Instructions.”
7.4.1.2
Streaming Non-temporal Stores
Streaming stores can improve performance by:
•
Increasing store bandwidth if the 64 bytes that fit within a cache line are written consecutively (since
they do not require read-for-ownership bus requests and 64 bytes are combined into a single bus
write transaction).
•
Reducing disturbance of frequently used cached (temporal) data (since they write around the
processor caches).
Streaming stores allow cross-aliasing of memory types for a given memory region. For instance, a region
may be mapped as write-back (WB) using page attribute tables (PAT) or memory type range registers
(MTRRs) and yet is written using a streaming store.
7.4.1.3
Memory Type and Non-temporal Stores
Memory type can take precedence over a non-temporal hint, leading to the following considerations:
•
If the programmer specifies a non-temporal store to strongly-ordered uncacheable memory (for
example, Uncacheable (UC) or Write-Protect (WP) memory types), then the store behaves like an
uncacheable store. The non-temporal hint is ignored and the memory type for the region is retained.
•
If the programmer specifies the weakly-ordered uncacheable memory type of Write-Combining
(WC), then the non-temporal store and the region have the same semantics and there is no conflict.
•
If the programmer specifies a non-temporal store to cacheable memory (for example, Write-Back
(WB) or Write-Through (WT) memory types), two cases may result:
— CASE 1 — If the data is present in the cache hierarchy, the instruction will ensure consistency. A
particular processor may choose different ways to implement this. The following approaches are
probable: (a) updating data in-place in the cache hierarchy while preserving the memory type
semantics assigned to that region or (b) evicting the data from the caches and writing the new
non-temporal data to memory (with WC semantics).
The approaches (separate or combined) can be different for future processors. Pentium 4, Intel
Core Solo and Intel Core Duo processors implement the latter policy (of evicting data from all
processor caches). The Pentium M processor implements a combination of both approaches.
If the streaming store hits a line that is present in the first-level cache, the store data is combined
in place within the first-level cache. If the streaming store hits a line present in the second-level,
the line and stored data is flushed from the second-level to system memory.
— CASE 2 — If the data is not present in the cache hierarchy and the destination region is mapped
as WB or WT; the transaction will be weakly ordered and is subject to all WC memory semantics.
This non-temporal store will not write-allocate. Different implementations may choose to collapse
and combine such stores.
7.4.1.4
Write-Combining
Generally, WC semantics require software to ensure coherence with respect to other processors and
other system agents (such as graphics cards). Appropriate use of synchronization and a fencing operation must be performed for producer-consumer usage models (see Section 7.4.5, “FENCE Instructions”).
7-6
OPTIMIZING CACHE USAGE
Fencing ensures that all system agents have global visibility of the stored data. For instance, failure to
fence may result in a written cache line staying within a processor, and the line would not be visible to
other agents.
For processors which implement non-temporal stores by updating data in-place that already resides in
the cache hierarchy, the destination region should also be mapped as WC. Otherwise, if mapped as WB
or WT, there is a potential for speculative processor reads to bring the data into the caches. In such a
case, non-temporal stores would then update in place and data would not be flushed from the processor
by a subsequent fencing operation.
The memory type visible on the bus in the presence of memory type aliasing is implementation-specific.
As one example, the memory type written to the bus may reflect the memory type for the first store to
the line, as seen in program order. Other alternatives are possible. This behavior should be considered
reserved and dependence on the behavior of any particular implementation risks future incompatibility.
7.4.2
Streaming Store Usage Models
The two primary usage domains for streaming store are coherent requests and non-coherent requests.
7.4.2.1
Coherent Requests
Coherent requests are normal loads and stores to system memory, which may also hit cache lines
present in another processor in a multiprocessor environment. With coherent requests, a streaming store
can be used in the same way as a regular store that has been mapped with a WC memory type (PAT or
MTRR). An SFENCE instruction must be used within a producer-consumer usage model in order to ensure
coherency and visibility of data between processors.
Within a single-processor system, the CPU can also re-read the same memory location and be assured of
coherence (that is, a single, consistent view of this memory location). The same is true for a multiprocessor (MP) system, assuming an accepted MP software producer-consumer synchronization policy is
employed.
7.4.2.2
Non-coherent requests
Non-coherent requests arise from an I/O device, such as an AGP graphics card, that reads or writes
system memory using non-coherent requests, which are not reflected on the processor bus and thus will
not query the processor’s caches. An SFENCE instruction must be used within a producer-consumer
usage model in order to ensure coherency and visibility of data between processors. In this case, if the
processor is writing data to the I/O device, a streaming store can be used with a processor with any
behavior of Case 1 (Section 7.4.1.3) only if the region has also been mapped with a WC memory type
(PAT, MTRR).
NOTE
Failure to map the region as WC may allow the line to be speculatively read into the
processor caches (via the wrong path of a mispredicted branch).
In case the region is not mapped as WC, the streaming might update in-place in the cache and a subsequent SFENCE would not result in the data being written to system memory. Explicitly mapping the
region as WC in this case ensures that any data read from this region will not be placed in the processor’s
caches. A read of this memory location by a non-coherent I/O device would return incorrect/out-of-date
results.
For a processor which solely implements Case 2 (Section 7.4.1.3), a streaming store can be used in this
non-coherent domain without requiring the memory region to also be mapped as WB, since any cached
data will be flushed to memory by the streaming store.
7-7
OPTIMIZING CACHE USAGE
7.4.3
Streaming Store Instruction Descriptions
MOVNTQ/MOVNTDQ (non-temporal store of packed integer in an MMX technology or Streaming SIMD
Extensions register) store data from a register to memory. They are implicitly weakly-ordered, do no
write-allocate, and so minimize cache pollution.
MOVNTPS (non-temporal store of packed single precision floating-point) is similar to MOVNTQ. It stores
data from a Streaming SIMD Extensions register to memory in 16-byte granularity. Unlike MOVNTQ, the
memory address must be aligned to a 16-byte boundary or a general protection exception will occur. The
instruction is implicitly weakly-ordered, does not write-allocate, and thus minimizes cache pollution.
MASKMOVQ/MASKMOVDQU (non-temporal byte mask store of packed integer in an MMX technology or
Streaming SIMD Extensions register) store data from a register to the location specified by the EDI
register. The most significant bit in each byte of the second mask register is used to selectively write the
data of the first register on a per-byte basis. The instructions are implicitly weakly-ordered (that is,
successive stores may not write memory in original program-order), do not write-allocate, and thus minimize cache pollution.
7.4.4
The Streaming Load Instruction
SSE4.1 introduces the MOVNTDQA instruction. MOVNTDQA loads 16 bytes from memory using a nontemporal hint if the memory source is WC type. For WC memory type, the non-temporal hint may be
implemented by loading into a temporary internal buffer with the equivalent of an aligned cache line
without filling this data to the cache. Subsequent MOVNTDQA reads to unread portions of the buffered
WC data will cause 16 bytes of data transferred from the temporary internal buffer to an XMM register if
data is available.
If used appropriately, MOVNTDQA can help software achieve significantly higher throughput when
loading data in WC memory region into the processor than other means.
Chapter 1 provides a reference to an application note on using MOVNTDQA. Additional information and
requirements to use MOVNTDQA appropriately can be found in Chapter 12, “Programming with SSE3,
SSSE3 and SSE4” of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, and the
instruction reference pages of MOVNTDQA in Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2A.
7.4.5
FENCE Instructions
The following fence instructions are available: SFENCE, lFENCE, and MFENCE.
7.4.5.1
SFENCE Instruction
The SFENCE (STORE FENCE) instruction makes it possible for every STORE instruction that precedes an
SFENCE in program order to be globally visible before any STORE that follows the SFENCE. SFENCE
provides an efficient way of ensuring ordering between routines that produce weakly-ordered results.
The use of weakly-ordered memory types can be important under certain data sharing relationships
(such as a producer-consumer relationship). Using weakly-ordered memory can make assembling the
data more efficient, but care must be taken to ensure that the consumer obtains the data that the
producer intended to see.
Some common usage models may be affected by weakly-ordered stores. Examples are:
•
•
•
Library functions, which use weakly-ordered memory to write results.
Compiler-generated code, which also benefits from writing weakly-ordered results.
Hand-crafted code.
The degree to which a consumer of data knows that the data is weakly-ordered can vary for different
cases. As a result, SFENCE should be used to ensure ordering between routines that produce weaklyordered data and routines that consume this data.
7-8
OPTIMIZING CACHE USAGE
7.4.5.2
LFENCE Instruction
The LFENCE (LOAD FENCE) instruction makes it possible for every LOAD instruction that precedes the
LFENCE instruction in program order to be globally visible before any LOAD instruction that follows the
LFENCE.
The LFENCE instruction provides a means of segregating LOAD instructions from other LOADs.
7.4.5.3
MFENCE Instruction
The MFENCE (MEMORY FENCE) instruction makes it possible for every LOAD/STORE instruction
preceding MFENCE in program order to be globally visible before any LOAD/STORE following MFENCE.
MFENCE provides a means of segregating certain memory instructions from other memory references.
The use of a LFENCE and SFENCE is not equivalent to the use of a MFENCE since the load and store fences
are not ordered with respect to each other. In other words, the load fence can be executed before prior
stores and the store fence can be executed before prior loads.
MFENCE should be used whenever the cache line flush instruction (CLFLUSH) is used to ensure that speculative memory references generated by the processor do not interfere with the flush. See Section 7.4.6,
“CLFLUSH Instruction.”
7.4.6
CLFLUSH Instruction
The CLFLUSH instruction invalidates the cache line associated with the linear address that contain the
byte address of the memory location, from all levels of the processor cache hierarchy (data and instruction). This invalidation is broadcast throughout the coherence domain. If, at any level of the cache hierarchy, a line is inconsistent with memory (dirty), it is written to memory before invalidation. Other
characteristics include:
•
The data size affected is the cache coherency size, which is enumerated by the CPUID instruction. It
is typically 64 bytes.
•
The memory attribute of the page containing the affected line has no effect on the behavior of this
instruction.
•
The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking
and faults associated with a byte load.
Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes,
locked read-modify-write instructions, fence instructions, and executions of CLFLUSHOPT to the same
cache line1. They are not ordered with respect to executions of CLFLUSHOPT to different cache lines. For
updated memory order details of CLFLUSH and other memory traffic, please refer to the CLFLUSH reference pages in Chapter 3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A,
and the “Memory Ordering” section in Chapter 8 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
As an example, consider a video usage model where a video capture device is using non-coherent
accesses to write a capture stream directly to system memory. Since these non-coherent writes are not
broadcast on the processor bus, they will not flush copies of the same locations that reside in the
processor caches. As a result, before the processor re-reads the capture buffer, it should use CLFLUSH to
ensure that stale, cached copies of the capture buffer are flushed from the processor caches.
1. Memory order recommendation of CLFLUSH in previous manuals had required software to add MFENCE after CLFLUSH.
MFENCE is not required following CLFLUSH as all processors implementing the CLFLUSH instruction also order it relative
to the other operations enumerated above.
7-9
OPTIMIZING CACHE USAGE
Example 7-1 provides pseudo-code for CLFLUSH usage.
Example 7-1. Pseudo-code Using CLFLUSH
while (!buffer_ready} {}
sfence
for(i=0;i<num_cachelines;i+=cacheline_size) {
clflush (char *)((unsigned int)buffer + i)
}
prefnta buffer[0];
VAR = buffer[0];
The throughput characteristics of using CLFLUSH to flush cache lines can vary significantly depending on
several factors. In general using CLFLUSH back-to-back to flush a large number of cache lines will experience larger cost per cache line than flushing a moderately-sized buffer (e.g. less than 4KB); the reduction of CLFLUSH throughput can be an order of magnitude. Flushing cache lines in modified state are
more costly than flushing cache lines in non-modified states.
7.4.7
CLFLUSHOPT Instruction
The CLFLUSHOPT instruction is first introduced in the 6th Generation Intel Core Processors. Similar to
CLFLUSH, CLFLUSHOPT invalidates the cache line associated with the linear address that contain the byte
address of the memory location, in all levels of the processor cache hierarchy (data and instruction).
Executions of the CLFLUSHOPT instruction are ordered with respect to locked read-modify-write instructions, fence instructions, and writes to the cache line being invalidated. (They are also ordered with
respect to executions of CLFLUSH and CLFLUSHOPT to the same cache line.) They are not ordered with
respect to writes to cache lines other than the one being invalidated. (They are also not ordered with
respect to executions of CLFLUSH and CLFLUSHOPT to different cache lines.) Software can insert an
SFENCE instruction between CFLUSHOPT and a store to another cache line with which the CLFLUSHOPT
should be ordered.
In general, CLFLUSHOPT throughput is higher than that of CLFLUSH, because CLFLUSHOPT orders itself
with respect to a smaller set of memory traffic as described above and in Section 7.4.6. The throughput
of CLFLUSHOPT will also vary. When using CLFLUSHOPT, flushing modified cache lines will experience a
higher cost than flushing cache lines in non-modified states. CLFLUSHOPT will provide a performance
benefit over CLFLUSH for cache lines in any coherence states. CLFLUSHOPT is more suitable to flush
large buffers (e.g. greater than many KBytes), compared to CLFLUSH. In single-threaded applications,
flushing buffers using CLFLUSHOPT may be up to 9X better than using CLFLUSH with Skylake microarchitecture.
Figure 7-1 shows the comparison of the performance characteristics of executing CLFLUSHOPT versus
CLFLUSH for buffers of various sizes.
7-10
OPTIMIZING CACHE USAGE
Figure 7-1. CLFLUSHOPT versus CLFLUSH In SkyLake Microarchitecture
User/Source Coding Rule 17. If CLFLUSHOPT is available, use CLFLUSHOPT over CLFLUSH and use
SFENCE to guard CLFLUSHOPT to ensure write order is globally observed. If CLUSHOPT is not available,
consider flushing large buffers with CLFLUSH in smaller chunks of less than 4KB.
Example 7-2 gives equivalent assembly sequences of flushing cache lines using CLFLUSH or
CLFLUSHOPT. The corresponding sequence in C are:
CLFLUSH:
For (i = 0; i < iSizeOfBufferToFlush; i += CACHE_LINE_SIZE) _mm_clflush( &pBufferToFlush[ i ] );
CLFLUSHOPT:
_mm_sfence();
For (i = 0; i < iSizeOfBufferToFlush; i += CACHE_LINE_SIZE) _mm_clflushopt( &pBufferToFlush[ i ] );
_mm_sfence();
7-11
OPTIMIZING CACHE USAGE
Example 7-2. Flushing Cache Lines Using CLFLUSH or CLFLUSHOPT
CLFLUSH no longer requires mfence
xor rcx, rcx
mov r9, pBufferToFlush
mov rsi, iSizeOfBufferToFlush
;; mfence - obsolete
loop:
clflush [r9+rcx]
add rcx, 0x40
cmp rcx, rsi
jl loop
;; mfence - obsolete
CLFLUSHOPT w/ SFENCE
xor rcx, rcx
mov r9, pBufferToFlush
mov rsi, iSizeOfBufferToFlush
sfence
loop:
clflushopt [r9+rcx]
add rcx, 0x40
cmp rcx, rsi
jl loop
sfence
* If imposing memory ordering rules is important for the application then executing CLFLUSHOPT instructions should be
guarded with SFENCE instructions to guarantee order of memory writes. As per the figure above, such solution still
performs better than using the CLFLUSH instruction, and its performance is identical to CLFLUSHOPT from 2048 byte
buffers and bigger.
7.5
MEMORY OPTIMIZATION USING PREFETCH
Recent generations of Intel processors have two mechanisms for data prefetch: software-controlled
prefetch and an automatic hardware prefetch.
7.5.1
Software-Controlled Prefetch
The software-controlled prefetch is enabled using the four PREFETCH instructions introduced with
Streaming SIMD Extensions instructions. These instructions are hints to bring a cache line of data in to
various levels and modes in the cache hierarchy. The software-controlled prefetch is not intended for
prefetching code. Using it can incur significant penalties on a multiprocessor system when code is
shared.
Software prefetching has the following characteristics:
•
•
•
Can handle irregular access patterns which do not trigger the hardware prefetcher.
Can use less bus bandwidth than hardware prefetching; see below.
Software prefetches must be added to new code, and do not benefit existing applications.
7.5.2
Hardware Prefetch
Automatic hardware prefetch can bring cache lines into the unified last-level cache based on prior data
misses. It will attempt to prefetch two cache lines ahead of the prefetch stream. Characteristics of the
hardware prefetcher are:
•
It requires some regularity in the data access patterns.
— If a data access pattern has constant stride, hardware prefetching is effective if the access stride
is less than half of the trigger distance of hardware prefetcher.
— If the access stride is not constant, the automatic hardware prefetcher can mask memory latency
if the strides of two successive cache misses are less than the trigger threshold distance (smallstride memory traffic).
— The automatic hardware prefetcher is most effective if the strides of two successive cache misses
remain less than the trigger threshold distance and close to 64 bytes.
7-12
OPTIMIZING CACHE USAGE
•
There is a start-up penalty before the prefetcher triggers and there may be fetches an array finishes.
For short arrays, overhead can reduce effectiveness.
— The hardware prefetcher requires a couple misses before it starts operating.
— Hardware prefetching generates a request for data beyond the end of an array, which is not be
utilized. This behavior wastes bus bandwidth. In addition this behavior results in a start-up
penalty when fetching the beginning of the next array. Software prefetching may recognize and
handle these cases.
•
It will not prefetch across a 4-KByte page boundary. A program has to initiate demand loads for the
new page before the hardware prefetcher starts prefetching from the new page.
•
The hardware prefetcher may consume extra system bandwidth if the application’s memory traffic
has significant portions with strides of cache misses greater than the trigger distance threshold of
hardware prefetch (large-stride memory traffic).
•
The effectiveness with existing applications depends on the proportions of small-stride versus largestride accesses in the application’s memory traffic. An application with a preponderance of smallstride memory traffic with good temporal locality will benefit greatly from the automatic hardware
prefetcher.
•
In some situations, memory traffic consisting of a preponderance of large-stride cache misses can be
transformed by re-arrangement of data access sequences to alter the concentration of small-stride
cache misses at the expense of large-stride cache misses to take advantage of the automatic
hardware prefetcher.
7.5.3
Example of Effective Latency Reduction with Hardware Prefetch
Consider the situation that an array is populated with data corresponding to a constant-access-stride,
circular pointer chasing sequence (see Example 7-3). The potential of employing the automatic hardware
prefetching mechanism to reduce the effective latency of fetching a cache line from memory can be illustrated by varying the access stride between 64 bytes and the trigger threshold distance of hardware
prefetch when populating the array for circular pointer chasing.
Example 7-3. Populating an Array for Circular Pointer Chasing with Constant Stride
register char ** p;
char *next;
// Populating pArray for circular pointer
// chasing with constant access stride
// p = (char **) *p; loads a value pointing to next load
p = (char **)&pArray;
for ( i = 0; i < aperture; i += stride) {
p = (char **)&pArray[i];
if (i + stride >= g_array_aperture) {
next = &pArray[0 ];
}
else {
next = &pArray[i + stride];
}
*p = next; // populate the address of the next node
}
The effective latency reduction for several microarchitecture implementations is shown in Figure 7-2. For
a constant-stride access pattern, the benefit of the automatic hardware prefetcher begins at half the
trigger threshold distance and reaches maximum benefit when the cache-miss stride is 64 bytes.
7-13
OPTIMIZING CACHE USAGE
U p p e r b o u n d o f P o in t e r - C h a s i n g L a t e n c y R e d u c t io n
120%
Effective Latency Reduction
100%
80%
F a m .1 5 ; M o d e l 3 , 4
F a m .1 5 ; M o d e l 0 ,1 ,2
60%
Fam . 6; M odel 13
Fam . 6; M odel 14
Fam . 15; M odel 6
40%
20%
4
8
2
0
24
22
20
0
4
8
6
19
17
16
14
2
12
96
11
80
64
0%
S tr i d e (B y te s)
Figure 7-2. Effective Latency Reduction as a Function of Access Stride
7.5.4
Example of Latency Hiding with S/W Prefetch Instruction
Achieving the highest level of memory optimization using PREFETCH instructions requires an understanding of the architecture of a given machine. This section translates the key architectural implications
into several simple guidelines for programmers to use.
Figure 7-3 and Figure 7-4 show two scenarios of a simplified 3D geometry pipeline as an example. A 3Dgeometry pipeline typically fetches one vertex record at a time and then performs transformation and
lighting functions on it. Both figures show two separate pipelines, an execution pipeline, and a memory
pipeline (front-side bus).
Since the Pentium 4 processor (similar to the Pentium II and Pentium III processors) completely decouples the functionality of execution and memory access, the two pipelines can function concurrently.
Figure 7-3 shows “bubbles” in both the execution and memory pipelines. When loads are issued for
accessing vertex data, the execution units sit idle and wait until data is returned. On the other hand, the
memory bus sits idle while the execution units are processing vertices. This scenario severely decreases
the advantage of having a decoupled architecture.
Tim e
Execution
pipeline
Execution units idle
Execution units idle
Issue loads
(vertex data)
Front-Side
Bus
M em latency
Vertex n
Issue loads
FSB idle
M em latency
Vertex n+1
OM15170
Figure 7-3. Memory Access Latency and Execution Without Prefetch
7-14
OPTIMIZING CACHE USAGE
Tim e
Execution
pipeline
Front-Side
Bus
Vertex n-2
Vertex n-1
Vertex n
issue prefetch
for vertex n
prefetch
V n+1
prefetch
V n+2
Vertex n+1
Mem latency for V n
Mem latency for V n+1
Mem latency for V n+2
OM15171
Figure 7-4. Memory Access Latency and Execution With Prefetch
The performance loss caused by poor utilization of resources can be completely eliminated by correctly
scheduling the PREFETCH instructions. As shown in Figure 7-4, prefetch instructions are issued two
vertex iterations ahead. This assumes that only one vertex gets processed in one iteration and a new
data cache line is needed for each iteration. As a result, when iteration n, vertex Vn, is being processed;
the requested data is already brought into cache. In the meantime, the front-side bus is transferring the
data needed for iteration n+1, vertex Vn+1. Because there is no dependence between Vn+1 data and the
execution of Vn, the latency for data access of Vn+1 can be entirely hidden behind the execution of Vn.
Under such circumstances, no “bubbles” are present in the pipelines and thus the best possible performance can be achieved.
Prefetching is useful for inner loops that have heavy computations, or are close to the boundary between
being compute-bound and memory-bandwidth-bound. It is probably not very useful for loops which are
predominately memory bandwidth-bound.
When data is already located in the first level cache, prefetching can be useless and could even slow
down the performance because the extra µops either back up waiting for outstanding memory accesses
or may be dropped altogether. This behavior is platform-specific and may change in the future.
7.5.5
Software Prefetching Usage Checklist
The following checklist covers issues that need to be addressed and/or resolved to use the software
PREFETCH instruction properly:
•
•
•
•
•
•
•
•
Determine software prefetch scheduling distance.
Use software prefetch concatenation.
Minimize the number of software prefetches.
Mix software prefetch with computation instructions.
Use cache blocking techniques (for example, strip mining).
Balance single-pass versus multi-pass execution.
Resolve memory bank conflict issues.
Resolve cache management issues.
Subsequent sections discuss the above items.
7-15
OPTIMIZING CACHE USAGE
7.5.6
Software Prefetch Scheduling Distance
Determining the ideal prefetch placement in the code depends on many architectural parameters,
including: the amount of memory to be prefetched, cache lookup latency, system memory latency, and
estimate of computation cycle. The ideal distance for prefetching data is processor- and platform-dependent. If the distance is too short, the prefetch will not hide the latency of the fetch behind computation.
If the prefetch is too far ahead, prefetched data may be flushed out of the cache by the time it is
required.
Since prefetch distance is not a well-defined metric, for this discussion, we define a new term, prefetch
scheduling distance (PSD), which is represented by the number of iterations. For large loops, prefetch
scheduling distance can be set to 1 (that is, schedule prefetch instructions one iteration ahead). For small
loop bodies (that is, loop iterations with little computation), the prefetch scheduling distance must be
more than one iteration.
A simplified equation to compute PSD is deduced from the mathematical model.
Example 7-4 illustrates the use of a prefetch within the loop body. The prefetch scheduling distance is set
to 3, ESI is effectively the pointer to a line, EDX is the address of the data being referenced and XMM1XMM4 are the data used in computation. Example 7-5 uses two independent cache lines of data per iteration. The PSD would need to be increased/decreased if more/less than two cache lines are used per iteration.
Example 7-4. Prefetch Scheduling Distance
top_loop:
prefetchnta [edx + esi + 128*3]
prefetchnta [edx*4 + esi + 128*3]
.....
movaps
movaps
movaps
movaps
.....
.....
xmm1, [edx + esi]
xmm2, [edx*4 + esi]
xmm3, [edx + esi + 16]
xmm4, [edx*4 + esi + 16]
add
cmp
jl
esi, 128
esi, ecx
top_loop
7.5.7
Software Prefetch Concatenation
Maximum performance can be achieved when the execution pipeline is at maximum throughput, without
incurring any memory latency penalties. This can be achieved by prefetching data to be used in successive iterations in a loop. De-pipelining memory generates bubbles in the execution pipeline.
To explain this performance issue, a 3D geometry pipeline that processes 3D vertices in strip format is
used as an example. A strip contains a list of vertices whose predefined vertex order forms contiguous
triangles. It can be easily observed that the memory pipe is de-pipelined on the strip boundary due to
ineffective prefetch arrangement. The execution pipeline is stalled for the first two iterations for each
strip. As a result, the average latency for completing an iteration will be 165 (FIX) clocks.
This memory de-pipelining creates inefficiency in both the memory pipeline and execution pipeline. This
de-pipelining effect can be removed by applying a technique called prefetch concatenation. With this
technique, the memory access and execution can be fully pipelined and fully utilized.
For nested loops, memory de-pipelining could occur during the interval between the last iteration of an
inner loop and the next iteration of its associated outer loop. Without paying special attention to prefetch
insertion, loads from the first iteration of an inner loop can miss the cache and stall the execution pipeline
waiting for data returned, thus degrading the performance.
7-16
OPTIMIZING CACHE USAGE
In Example 7-5, the cache line containing A[II][0] is not prefetched at all and always misses the cache.
This assumes that no array A[][] footprint resides in the cache. The penalty of memory de-pipelining
stalls can be amortized across the inner loop iterations. However, it may become very harmful when the
inner loop is short. In addition, the last prefetch in the last PSD iterations are wasted and consume
machine resources. Prefetch concatenation is introduced here in order to eliminate the performance
issue of memory de-pipelining.
Example 7-5. Using Prefetch Concatenation
for (ii = 0; ii < 100; ii++) {
for (jj = 0; jj < 32; jj+=8) {
prefetch a[ii][jj+8]
computation a[ii][jj]
}
}
Prefetch concatenation can bridge the execution pipeline bubbles between the boundary of an inner loop
and its associated outer loop. Simply by unrolling the last iteration out of the inner loop and specifying
the effective prefetch address for data used in the following iteration, the performance loss of memory
de-pipelining can be completely removed. Example 7-6 gives the rewritten code.
Example 7-6. Concatenation and Unrolling the Last Iteration of Inner Loop
for (ii = 0; ii < 100; ii++) {
for (jj = 0; jj < 24; jj+=8) { /* N-1 iterations */
prefetch a[ii][jj+8]
computation a[ii][jj]
}
prefetch a[ii+1][0]
computation a[ii][jj]/* Last iteration */
}
This code segment for data prefetching is improved and only the first iteration of the outer loop suffers
any memory access latency penalty, assuming the computation time is larger than the memory latency.
Inserting a prefetch of the first data element needed prior to entering the nested loop computation would
eliminate or reduce the start-up penalty for the very first iteration of the outer loop. This uncomplicated
high-level code optimization can improve memory performance significantly.
7.5.8
Minimize Number of Software Prefetches
Prefetch instructions are not completely free in terms of bus cycles, machine cycles and resources, even
though they require minimal clock and memory bandwidth.
Excessive prefetching may lead to performance penalties because of issue penalties in the front end of
the machine and/or resource contention in the memory sub-system. This effect may be severe in cases
where the target loops are small and/or cases where the target loop is issue-bound.
One approach to solve the excessive prefetching issue is to unroll and/or software-pipeline loops to
reduce the number of prefetches required. Figure 7-5 presents a code example which implements
prefetch and unrolls the loop to remove the redundant prefetch instructions whose prefetch addresses hit
the previously issued prefetch instructions. In this particular example, unrolling the original loop once
saves six prefetch instructions and nine instructions for conditional jumps in every other iteration.
7-17
OPTIMIZING CACHE USAGE
top_loop:
prefetchnta [edx+esi+32]
prefetchnta [edx*4+esi+32]
. . . . .
m ovaps xm m 1, [edx+esi]
m ovaps xm m 2, [edx*4+esi]
. . . . .
add esi, 16
unrolled
cm p esi, ecx
iteration
jl top_loop
top_loop:
prefetchnta [edx+esi+128]
prefetchnta [edx*4+esi+128]
. . . . .
m ovaps xm m 1, [edx+esi]
m ovaps xm m 2, [edx*4+esi]
. . . . .
m ovaps xm m 1, [edx+esi+16]
m ovaps xm m 2, [edx*4+esi+16]
. . . . .
m ovaps xm m 1, [edx+esi+96]
m ovaps xm m 2, [edx*4+esi+96]
. . . . .
. . . . .
add esi, 128
cm p esi, ecx
jl top_loop
OM15172
Figure 7-5. Prefetch and Loop Unrolling
Figure 7-6 demonstrates the effectiveness of software prefetches in latency hiding.
Tim e
Execution
pipeline
Front-Side
Bus
Vertex n-2
Vertex n-1
Vertex n
issue prefetch
for vertex n
prefetch
V n+1
prefetch
V n+2
Vertex n+1
Mem latency for V n
Mem latency for V n+1
Mem latency for V n+2
OM15171
Figure 7-6. Memory Access Latency and Execution With Prefetch
The X axis in Figure 7-6 indicates the number of computation clocks per loop (each iteration is independent). The Y axis indicates the execution time measured in clocks per loop. The secondary Y axis indicates the percentage of bus bandwidth utilization. The tests vary by the following parameters:
•
Number of load/store streams — Each load and store stream accesses one 128-byte cache line each
per iteration.
•
Amount of computation per loop — This is varied by increasing the number of dependent arithmetic
operations executed.
•
Number of the software prefetches per loop — For example, one every 16 bytes, 32 bytes, 64 bytes,
128 bytes.
7-18
OPTIMIZING CACHE USAGE
As expected, the leftmost portion of each of the graphs in Figure 7-6 shows that when there is not
enough computation to overlap the latency of memory access, prefetch does not help and that the
execution is essentially memory-bound. The graphs also illustrate that redundant prefetches do not
increase performance.
7.5.9
Mix Software Prefetch with Computation Instructions
It may seem convenient to cluster all of PREFETCH instructions at the beginning of a loop body or before
a loop, but this can lead to severe performance degradation. In order to achieve the best possible performance, PREFETCH instructions must be interspersed with other computational instructions in the instruction sequence rather than clustered together. If possible, they should also be placed apart from loads.
This improves the instruction level parallelism and reduces the potential instruction resource stalls. In
addition, this mixing reduces the pressure on the memory access resources and in turn reduces the
possibility of the prefetch retiring without fetching data.
Figure 7-7 illustrates distributing PREFETCH instructions. A simple and useful heuristic of prefetch
spreading for a Pentium 4 processor is to insert a PREFETCH instruction every 20 to 25 clocks. Rearranging PREFETCH instructions could yield a noticeable speedup for the code which stresses the cache
resource.
top_loop:
prefetchnta [ebx+128]
prefetchnta [ebx+1128]
prefetchnta [ebx+2128]
prefetchnta [ebx+3128]
. . . .
. . . .
prefetchnta [ebx+17128]
prefetchnta [ebx+18128]
prefetchnta [ebx+19128]
prefetchnta [ebx+20128]
movps xmm1, [ebx]
addps xmm2, [ebx+3000]
mulps xmm3, [ebx+4000]
addps xmm1, [ebx+1000]
addps xmm2, [ebx+3016]
mulps xmm1, [ebx+2000]
mulps xmm1, xmm2
. . . . . . . .
. . . . . .
. . . . .
add ebx, 128
cmp ebx, ecx
jl top_loop
sp
dp
re a
r
tch
efe
es
top_loop:
prefetchnta [ebx+128]
movps xmm1, [ebx]
addps xmm2, [ebx+3000]
mulps xmm3, [ebx+4000]
prefetchnta [ebx+1128]
addps xmm1, [ebx+1000]
addps xmm2, [ebx+3016]
prefetchnta [ebx+2128]
mulps xmm1, [ebx+2000]
mulps xmm1, xmm2
prefetchnta [ebx+3128]
. . . . . . .
. . .
prefetchnta [ebx+18128]
. . . . . .
prefetchnta [ebx+19128]
. . . . . .
. . . .
prefetchnta [ebx+20128]
add ebx, 128
cmp ebx, ecx
jl top_loop
Figure 7-7. Spread Prefetch Instructions
NOTE
To avoid instruction execution stalls due to the over-utilization of the resource, PREFETCH
instructions must be interspersed with computational instructions
7.5.10
Software Prefetch and Cache Blocking Techniques
Cache blocking techniques (such as strip-mining) are used to improve temporal locality and the cache hit
rate. Strip-mining is one-dimensional temporal locality optimization for memory. When two-dimensional
arrays are used in programs, loop blocking technique (similar to strip-mining but in two dimensions) can
be applied for a better memory performance.
7-19
OPTIMIZING CACHE USAGE
If an application uses a large data set that can be reused across multiple passes of a loop, it will benefit
from strip mining. Data sets larger than the cache will be processed in groups small enough to fit into
cache. This allows temporal data to reside in the cache longer, reducing bus traffic.
Data set size and temporal locality (data characteristics) fundamentally affect how PREFETCH instructions are applied to strip-mined code. Figure 7-8 shows two simplified scenarios for temporally-adjacent
data and temporally-non-adjacent data.
Dataset A
Dataset A
Pass 1
Dataset A
Dataset B
Pass 2
Dataset B
Dataset A
Pass 3
Dataset B
Dataset B
Pass 4
Temporally
adjacent passes
Temporally
non-adjacent
passes
Figure 7-8. Cache Blocking – Temporally Adjacent and Non-adjacent Passes
In the temporally-adjacent scenario, subsequent passes use the same data and find it already in secondlevel cache. Prefetch issues aside, this is the preferred situation. In the temporally non-adjacent
scenario, data used in pass m is displaced by pass (m+1), requiring data re-fetch into the first level cache
and perhaps the second level cache if a later pass reuses the data. If both data sets fit into the secondlevel cache, load operations in passes 3 and 4 become less expensive.
Figure 7-9 shows how prefetch instructions and strip-mining can be applied to increase performance in
both of these scenarios.
7-20
OPTIMIZING CACHE USAGE
Prefetchnta
Dataset A
Prefetcht0
Dataset A
SM1
Reuse
Dataset A
Prefetcht0
Dataset B
Prefetchnta
Dataset B
Reuse
Dataset A
SM2
SM1
Reuse
Dataset B
Reuse
Dataset B
Temporally
adjacent passes
Temporally
non-adjacent passes
Figure 7-9. Examples of Prefetch and Strip-mining for Temporally Adjacent and Non-Adjacent Passes
Loops
For Pentium 4 processors, the left scenario shows a graphical implementation of using PREFETCHNTA to
prefetch data into selected ways of the second-level cache only (SM1 denotes strip mine one way of
second-level), minimizing second-level cache pollution. Use PREFETCHNTA if the data is only touched
once during the entire execution pass in order to minimize cache pollution in the higher level caches. This
provides instant availability, assuming the prefetch was issued far ahead enough, when the read access
is issued.
In scenario to the right (see Figure 7-9), keeping the data in one way of the second-level cache does not
improve cache locality. Therefore, use PREFETCHT0 to prefetch the data. This amortizes the latency of
the memory references in passes 1 and 2, and keeps a copy of the data in second-level cache, which
reduces memory traffic and latencies for passes 3 and 4. To further reduce the latency, it might be worth
considering extra PREFETCHNTA instructions prior to the memory references in passes 3 and 4.
In Example 7-7, consider the data access patterns of a 3D geometry engine first without strip-mining
and then incorporating strip-mining. Note that 4-wide SIMD instructions of Pentium III processor can
process 4 vertices per every iteration.
Without strip-mining, all the x,y,z coordinates for the four vertices must be re-fetched from memory in
the second pass, that is, the lighting loop. This causes under-utilization of cache lines fetched during
transformation loop as well as bandwidth wasted in the lighting loop.
Example 7-7. Data Access of a 3D Geometry Engine without Strip-mining
while (nvtx < MAX_NUM_VTX) {
prefetchnta vertexi data
prefetchnta vertexi+1 data
prefetchnta vertexi+2 data
prefetchnta vertexi+3 data
TRANSFORMATION code
nvtx+=4
// v =[x,y,z,nx,ny,nz,tu,tv]
// use only x,y,z,tu,tv of a vertex
7-21
OPTIMIZING CACHE USAGE
Example 7-7. Data Access of a 3D Geometry Engine without Strip-mining (Contd.)
}
while (nvtx < MAX_NUM_VTX) {
prefetchnta vertexi data
prefetchnta vertexi+1 data
prefetchnta vertexi+2 data
prefetchnta vertexi+3 data
compute the light vectors
LOCAL LIGHTING code
nvtx+=4
// v =[x,y,z,nx,ny,nz,tu,tv]
// x,y,z fetched again
// use only x,y,z
// use only nx,ny,nz
}
Now consider the code in Example 7-8 where strip-mining has been incorporated into the loops.
Example 7-8. Data Access of a 3D Geometry Engine with Strip-mining
while (nstrip < NUM_STRIP) {
/* Strip-mine the loop to fit data into one way of the second-level
cache */
while (nvtx < MAX_NUM_VTX_PER_STRIP) {
prefetchnta vertexi data
// v=[x,y,z,nx,ny,nz,tu,tv]
prefetchnta vertexi+1 data
prefetchnta vertexi+2 data
prefetchnta vertexi+3 data
TRANSFORMATION code
nvtx+=4
}
while (nvtx < MAX_NUM_VTX_PER_STRIP) {
/* x y z coordinates are in the second-level cache, no prefetch is
required */
compute the light vectors
POINT LIGHTING code
nvtx+=4
}
}
With strip-mining, all vertex data can be kept in the cache (for example, one way of second-level cache)
during the strip-mined transformation loop and reused in the lighting loop. Keeping data in the cache
reduces both bus traffic and the number of prefetches used.
Table 7-1 summarizes the steps of the basic usage model that incorporates only software prefetch with
strip-mining. The steps are:
•
•
Do strip-mining: partition loops so that the dataset fits into second-level cache.
Use PREFETCHNTA if the data is only used once or the dataset fits into 32 KBytes (one way of secondlevel cache). Use PREFETCHT0 if the dataset exceeds 32 KBytes.
The above steps are platform-specific and provide an implementation example. The variables
NUM_STRIP and MAX_NUM_VX_PER_STRIP can be heuristically determined for peak performance for
specific application on a specific platform.
7-22
OPTIMIZING CACHE USAGE
Table 7-1. Software Prefetching Considerations into Strip-mining Code
Read-Multiple-Times Array References
Read-Once Array References
Adjacent Passes
Non-Adjacent Passes
Prefetchnta
Prefetch0, SM1
Prefetch0, SM1
(2nd Level Pollution)
Evict one way; Minimize pollution
Pay memory access cost for the first
pass of each array; Amortize the first
pass with subsequent passes
Pay memory access cost for the first
pass of every strip; Amortize the first
pass with subsequent passes
7.5.11
Hardware Prefetching and Cache Blocking Techniques
Tuning data access patterns for the automatic hardware prefetch mechanism can minimize the memory
access costs of the first-pass of the read-multiple-times and some of the read-once memory references.
An example of the situations of read-once memory references can be illustrated with a matrix or image
transpose, reading from a column-first orientation and writing to a row-first orientation, or vice versa.
Example 7-9 shows a nested loop of data movement that represents a typical matrix/image transpose
problem. If the dimension of the array are large, not only the footprint of the dataset will exceed the last
level cache but cache misses will occur at large strides. If the dimensions happen to be powers of 2,
aliasing condition due to finite number of way-associativity (see “Capacity Limits and Aliasing in Caches”
in Chapter ) will exacerbate the likelihood of cache evictions.
Example 7-9. Using HW Prefetch to Improve Read-Once Memory Traffic
a) Un-optimized image transpose
// dest and src represent two-dimensional arrays
for( i = 0;i < NUMCOLS; i ++) {
// inner loop reads single column
for( j = 0; j < NUMROWS ; j ++) {
// Each read reference causes large-stride cache miss
dest[i*NUMROWS +j] = src[j*NUMROWS + i];
}
}
b)
// tilewidth = L2SizeInBytes/2/TileHeight/Sizeof(element)
for( i = 0; i < NUMCOLS; i += tilewidth) {
for( j = 0; j < NUMROWS ; j ++) {
// access multiple elements in the same row in the inner loop
// access pattern friendly to hw prefetch and improves hit rate
for( k = 0; k < tilewidth; k ++)
dest[j+ (i+k)* NUMROWS] = src[i+k+ j* NUMROWS];
}
}
Example 7-9 (b) shows applying the techniques of tiling with optimal selection of tile size and tile width
to take advantage of hardware prefetch. With tiling, one can choose the size of two tiles to fit in the last
level cache. Maximizing the width of each tile for memory read references enables the hardware
prefetcher to initiate bus requests to read some cache lines before the code actually reference the linear
addresses.
7-23
OPTIMIZING CACHE USAGE
7.5.12
Single-pass versus Multi-pass Execution
An algorithm can use single- or multi-pass execution defined as follows:
•
Single-pass, or unlayered execution passes a single data element through an entire computation
pipeline.
•
Multi-pass, or layered execution performs a single stage of the pipeline on a batch of data elements,
before passing the batch on to the next stage.
A characteristic feature of both single-pass and multi-pass execution is that a specific trade-off exists
depending on an algorithm’s implementation and use of a single-pass or multiple-pass execution. See
Figure 7-10.
Multi-pass execution is often easier to use when implementing a general purpose API, where the choice
of code paths that can be taken depends on the specific combination of features selected by the application (for example, for 3D graphics, this might include the type of vertex primitives used and the number
and type of light sources).
With such a broad range of permutations possible, a single-pass approach would be complicated, in
terms of code size and validation. In such cases, each possible permutation would require a separate
code sequence. For example, an object with features A, B, C, D can have a subset of features enabled,
say, A, B, D. This stage would use one code path; another combination of enabled features would have a
different code path. It makes more sense to perform each pipeline stage as a separate pass, with conditional clauses to select different features that are implemented within each stage. By using strip-mining,
the number of vertices processed by each stage (for example, the batch size) can be selected to ensure
that the batch stays within the processor caches through all passes. An intermediate cached buffer is
used to pass the batch of vertices from one stage or pass to the next one.
Single-pass execution can be better suited to applications which limit the number of features that may be
used at a given time. A single-pass approach can reduce the amount of data copying that can occur with
a multi-pass engine. See Figure 7-10.
7-24
OPTIMIZING CACHE USAGE
strip list
80 vis
60 invis
40 vis
80 vis
40 vis
Culling
Culling
Transform
Vertex
processing
(inner loop)
Transform
Outer loop is
processing
strips
Lighting
Single-Pass
Lighting
Multi-Pass
Figure 7-10. Single-Pass Vs. Multi-Pass 3D Geometry Engines
The choice of single-pass or multi-pass can have a number of performance implications. For instance, in
a multi-pass pipeline, stages that are limited by bandwidth (either input or output) will reflect more of
this performance limitation in overall execution time. In contrast, for a single-pass approach, bandwidthlimitations can be distributed/amortized across other computation-intensive stages. Also, the choice of
which prefetch hints to use are also impacted by whether a single-pass or multi-pass approach is used.
7.6
MEMORY OPTIMIZATION USING NON-TEMPORAL STORES
Non-temporal stores can also be used to manage data retention in the cache. Uses for non-temporal
stores include:
•
•
To combine many writes without disturbing the cache hierarchy.
To manage which data structures remain in the cache and which are transient.
Detailed implementations of these usage models are covered in the following sections.
7.6.1
Non-temporal Stores and Software Write-Combining
Use non-temporal stores in the cases when the data to be stored is:
•
•
Write-once (non-temporal).
Too large and thus cause cache thrashing.
7-25
OPTIMIZING CACHE USAGE
Non-temporal stores do not invoke a cache line allocation, which means they are not write-allocate. As a
result, caches are not polluted and no dirty writeback is generated to compete with useful data bandwidth. Without using non-temporal stores, bus bandwidth will suffer when caches start to be thrashed
because of dirty writebacks.
In Streaming SIMD Extensions implementation, when non-temporal stores are written into writeback or
write-combining memory regions, these stores are weakly-ordered and will be combined internally inside
the processor’s write-combining buffer and be written out to memory as a line burst transaction. To
achieve the best possible performance, it is recommended to align data along the cache line boundary
and write them consecutively in a cache line size while using non-temporal stores. If the consecutive
writes are prohibitive due to programming constraints, then software write-combining (SWWC) buffers
can be used to enable line burst transaction.
You can declare small SWWC buffers (a cache line for each buffer) in your application to enable explicit
write-combining operations. Instead of writing to non-temporal memory space immediately, the program
writes data into SWWC buffers and combines them inside these buffers. The program only writes a
SWWC buffer out using non-temporal stores when the buffer is filled up, that is, a cache line (128 bytes
for the Pentium 4 processor). Although the SWWC method requires explicit instructions for performing
temporary writes and reads, this ensures that the transaction on the front-side bus causes line transaction rather than several partial transactions. Application performance gains considerably from implementing this technique. These SWWC buffers can be maintained in the second-level and re-used
throughout the program.
7.6.2
Cache Management
Streaming instructions (PREFETCH and STORE) can be used to manage data and minimize disturbance of
temporal data held within the processor’s caches.
In addition, the Pentium 4 processor takes advantage of Intel C ++ Compiler support for C ++ languagelevel features for the Streaming SIMD Extensions. Streaming SIMD Extensions and MMX technology
instructions provide intrinsics that allow you to optimize cache utilization. Examples of such Intel
compiler intrinsics are _MM_PREFETCH, _MM_STREAM, _MM_LOAD, _MM_SFENCE. For detail, refer to
the Intel C ++ Compiler User’s Guide documentation.
The following examples of using prefetching instructions in the operation of video encoder and decoder
as well as in simple 8-byte memory copy, illustrate performance gain from using the prefetching instructions for efficient cache management.
7.6.2.1
Video Encoder
In a video encoder, some of the data used during the encoding process is kept in the processor’s secondlevel cache. This is done to minimize the number of reference streams that must be re-read from system
memory. To ensure that other writes do not disturb the data in the second-level cache, streaming stores
(MOVNTQ) are used to write around all processor caches.
The prefetching cache management implemented for the video encoder reduces the memory traffic. The
second-level cache pollution reduction is ensured by preventing single-use video frame data from
entering the second-level cache. Using a non-temporal PREFETCH (PREFETCHNTA) instruction brings
data into only one way of the second-level cache, thus reducing pollution of the second-level cache.
If the data brought directly to second-level cache is not re-used, then there is a performance gain from
the non-temporal prefetch over a temporal prefetch. The encoder uses non-temporal prefetches to avoid
pollution of the second-level cache, increasing the number of second-level cache hits and decreasing the
number of polluting write-backs to memory. The performance gain results from the more efficient use of
the second-level cache, not only from the prefetch itself.
7.6.2.2
Video Decoder
In the video decoder example, completed frame data is written to local memory of the graphics card,
which is mapped to WC (Write-combining) memory type. A copy of reference data is stored to the WB
7-26
OPTIMIZING CACHE USAGE
memory at a later time by the processor in order to generate future data. The assumption is that the size
of the reference data is too large to fit in the processor’s caches. A streaming store is used to write the
data around the cache, to avoid displaying other temporal data held in the caches. Later, the processor
re-reads the data using PREFETCHNTA, which ensures maximum bandwidth, yet minimizes disturbance
of other cached temporal data by using the non-temporal (NTA) version of prefetch.
7.6.2.3
Conclusions from Video Encoder and Decoder Implementation
These two examples indicate that by using an appropriate combination of non-temporal prefetches and
non-temporal stores, an application can be designed to lessen the overhead of memory transactions by
preventing second-level cache pollution, keeping useful data in the second-level cache and reducing
costly write-back transactions. Even if an application does not gain performance significantly from having
data ready from prefetches, it can improve from more efficient use of the second-level cache and
memory. Such design reduces the encoder’s demand for such critical resource as the memory bus. This
makes the system more balanced, resulting in higher performance.
7.6.2.4
Optimizing Memory Copy Routines
Creating memory copy routines for large amounts of data is a common task in software optimization.
Example 7-10 presents a basic algorithm for a the simple memory copy.
Example 7-10. Basic Algorithm of a Simple Memory Copy
#define N 512000
double a[N], b[N];
for (i = 0; i < N; i++) {
b[i] = a[i];
}
This task can be optimized using various coding techniques. One technique uses software prefetch and
streaming store instructions. It is discussed in the following paragraph and a code example shown in
Example 7-11.
The memory copy algorithm can be optimized using the Streaming SIMD Extensions with these considerations:
•
•
•
•
•
Alignment of data.
Proper layout of pages in memory.
Cache size.
Interaction of the transaction lookaside buffer (TLB) with memory accesses.
Combining prefetch and streaming-store instructions.
The guidelines discussed in this chapter come into play in this simple example. TLB priming is required
for the Pentium 4 processor just as it is for the Pentium III processor, since software prefetch instructions
will not initiate page table walks on either processor.
7-27
OPTIMIZING CACHE USAGE
Example 7-11. A Memory Copy Routine Using Software Prefetch
#define PAGESIZE 4096;
#define NUMPERPAGE 512
double a[N], b[N], temp;
for (kk=0; kk<N; kk+=NUMPERPAGE) {
temp = a[kk+NUMPERPAGE];
// use block size = page size,
// # of elements to fit a page
// TLB priming
// prefetch entire block, one cache line per loop
for (j=kk+16; j<kk+NUMPERPAGE; j+=16) {
_mm_prefetch((char*)&a[j], _MM_HINT_NTA);
}
// copy 128 byte per loop
for (j=kk; j<kk+NUMPERPAGE; j+=16) {
_mm_stream_ps((float*)&b[j],
_mm_load_ps((float*)&a[j]));
_mm_stream_ps((float*)&b[j+2],
_mm_load_ps((float*)&a[j+2]));
_mm_stream_ps((float*)&b[j+4],
_mm_load_ps((float*)&a[j+4]));
_mm_stream_ps((float*)&b[j+6],
_mm_load_ps((float*)&a[j+6]));
_mm_stream_ps((float*)&b[j+8],
_mm_load_ps((float*)&a[j+8]));
_mm_stream_ps((float*)&b[j+10],
_mm_load_ps((float*)&a[j+10]));
_mm_stream_ps((float*)&b[j+12],
_mm_load_ps((float*)&a[j+12]));
_mm_stream_ps((float*)&b[j+14],
_mm_load_ps((float*)&a[j+14]));
} // finished copying one block
}
// finished copying N elements
_mm_sfence();
7.6.2.5
TLB Priming
The TLB is a fast memory buffer that is used to improve performance of the translation of a virtual
memory address to a physical memory address by providing fast access to page table entries. If memory
pages are accessed and the page table entry is not resident in the TLB, a TLB miss results and the page
table must be read from memory.
The TLB miss results in a performance degradation since another memory access must be performed
(assuming that the translation is not already present in the processor caches) to update the TLB. The TLB
can be preloaded with the page table entry for the next desired page by accessing (or touching) an
address in that page. This is similar to prefetch, but instead of a data cache line the page table entry is
being loaded in advance of its use. This helps to ensure that the page table entry is resident in the TLB
and that the prefetch happens as requested subsequently.
7-28
OPTIMIZING CACHE USAGE
7.6.2.6
Using the 8-byte Streaming Stores and Software Prefetch
Example 7-11 presents the copy algorithm that uses second level cache. The algorithm performs the
following steps:
1. Uses blocking technique to transfer 8-byte data from memory into second-level cache using the
_MM_PREFETCH intrinsic, 128 bytes at a time to fill a block. The size of a block should be less than
one half of the size of the second-level cache, but large enough to amortize the cost of the loop.
2. Loads the data into an XMM register using the _MM_LOAD_PS intrinsic.
3. Transfers the 8-byte data to a different memory location via the _MM_STREAM intrinsics, bypassing
the cache. For this operation, it is important to ensure that the page table entry prefetched for the
memory is preloaded in the TLB.
In Example 7-11, eight _MM_LOAD_PS and _MM_STREAM_PS intrinsics are used so that all of the data
prefetched (a 128-byte cache line) is written back. The prefetch and streaming-stores are executed in
separate loops to minimize the number of transitions between reading and writing data. This significantly
improves the bandwidth of the memory accesses.
The TEMP = A[KK+CACHESIZE] instruction is used to ensure the page table entry for array, and A is
entered in the TLB prior to prefetching. This is essentially a prefetch itself, as a cache line is filled from
that memory location with this instruction. Hence, the prefetching starts from KK+4 in this loop.
This example assumes that the destination of the copy is not temporally adjacent to the code. If the
copied data is destined to be reused in the near future, then the streaming store instructions should be
replaced with regular 128 bit stores (_MM_STORE_PS). This is required because the implementation of
streaming stores on Pentium 4 processor writes data directly to memory, maintaining cache coherency.
7.6.2.7
Using 16-byte Streaming Stores and Hardware Prefetch
An alternate technique for optimizing a large region memory copy is to take advantage of hardware
prefetcher, 16-byte streaming stores, and apply a segmented approach to separate bus read and write
transactions. See Section 3.6.12, “Minimizing Bus Latency.”
The technique employs two stages. In the first stage, a block of data is read from memory to the cache
sub-system. In the second stage, cached data are written to their destination using streaming stores.
Example 7-12. Memory Copy Using Hardware Prefetch and Bus Segmentation
void block_prefetch(void *dst,void *src)
{ _asm {
mov edi,dst
mov esi,src
mov edx,SIZE
align 16
main_loop:
xor ecx,ecx
align 16
}
prefetch_loop:
movaps xmm0, [esi+ecx]
movaps xmm0, [esi+ecx+64]
add ecx,128
cmp ecx,BLOCK_SIZE
jne prefetch_loop
xor ecx,ecx
align 16
cpy_loop:
7-29
OPTIMIZING CACHE USAGE
Example 7-12. Memory Copy Using Hardware Prefetch and Bus Segmentation (Contd.)
movdqa xmm0,[esi+ecx]
movdqa xmm1,[esi+ecx+16]
movdqa xmm2,[esi+ecx+32]
movdqa xmm3,[esi+ecx+48]
movdqa xmm4,[esi+ecx+64]
movdqa xmm5,[esi+ecx+16+64]
movdqa xmm6,[esi+ecx+32+64]
movdqa xmm7,[esi+ecx+48+64]
movntdq [edi+ecx],xmm0
movntdq [edi+ecx+16],xmm1
movntdq [edi+ecx+32],xmm2
movntdq [edi+ecx+48],xmm3
movntdq [edi+ecx+64],xmm4
movntdq [edi+ecx+80],xmm5
movntdq [edi+ecx+96],xmm6
movntdq [edi+ecx+112],xmm7
add ecx,128
cmp ecx,BLOCK_SIZE
jne cpy_loop
add esi,ecx
add edi,ecx
sub edx,ecx
jnz main_loop
sfence
}
}
7.6.2.8
Performance Comparisons of Memory Copy Routines
The throughput of a large-region, memory copy routine depends on several factors:
•
•
Coding techniques that implements the memory copy task.
•
Microarchitecture of the processor.
Characteristics of the system bus (speed, peak bandwidth, overhead in read/write transaction
protocols).
A comparison of the two coding techniques discussed above and two un-optimized techniques is shown
in Table 7-2.
Table 7-2. Relative Performance of Memory Copy Routines
Processor, CPUID
Signature and FSB
Speed
4KB-Block HW
prefetch + 16 byte
streaming stores
Byte Sequential
DWORD Sequential
SW prefetch + 8 byte
streaming store
Pentium M processor,
0x6Dn, 400
1.3X
1.2X
1.6X
2.5X
Intel Core Solo and
Intel Core Duo
processors, 0x6En,
667
3.3X
3.5X
2.1X
4.7X
Pentium D processor,
0xF4n, 800
3.4X
3.3X
4.9X
5.7X
7-30
OPTIMIZING CACHE USAGE
The baseline for performance comparison is the throughput (bytes/sec) of 8-MByte region memory copy
on a first-generation Pentium M processor (CPUID signature 0x69n) with a 400-MHz system bus using
byte-sequential technique similar to that shown in Example 7-10. The degree of improvement relative to
the performance baseline for some recent processors and platforms with higher system bus speed using
different coding techniques are compared.
The second coding technique moves data at 4-Byte granularity using REP string instruction. The third
column compares the performance of the coding technique listed in Example 7-11. The fourth column of
performance compares the throughput of fetching 4-KBytes of data at a time (using hardware prefetch
to aggregate bus read transactions) and writing to memory via 16-Byte streaming stores.
Increases in bus speed is the primary contributor to throughput improvements. The technique shown in
Example 7-12 will likely take advantage of the faster bus speed in the platform more efficiently. Additionally, increasing the block size to multiples of 4-KBytes while keeping the total working set within the
second-level cache can improve the throughput slightly.
The relative performance figure shown in Table 7-2 is representative of clean microarchitectural conditions within a processor (e.g. looping s simple sequence of code many times). The net benefit of integrating a specific memory copy routine into an application (full-featured applications tend to create many
complicated micro-architectural conditions) will vary for each application.
7.6.3
Deterministic Cache Parameters
If CPUID supports the deterministic parameter leaf, software can use the leaf to query each level of the
cache hierarchy. Enumeration of each cache level is by specifying an index value (starting form 0) in the
ECX register (see “CPUID-CPU Identification” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A).
The list of parameters is shown in Table 7-3.
Table 7-3. Deterministic Cache Parameters Leaf
Bit Location
Name
Meaning
EAX[4:0]
Cache Type
0 = Null - No more caches
1 = Data Cache
2 = Instruction Cache
3 = Unified Cache
4-31 = Reserved
EAX[7:5]
Cache Level
Starts at 1
EAX[8]
Self Initializing cache level
1: does not need SW initialization
EAX[9]
Fully Associative cache
1: Yes
EAX[13:10]
Reserved
EAX[25:14]
Maximum number of logical processors sharing this
cache
Plus encoding
EAX[31:26]
Maximum number of cores in a package
Plus 1 encoding
EBX[11:0]
System Coherency Line Size (L)
Plus 1 encoding (Bytes)
EBX[21:12]
Physical Line partitions (P)
Plus 1 encoding
EBX[31:22]
Ways of associativity (W)
Plus 1 encoding
ECX[31:0]
Number of Sets (S)
Plus 1 encoding
EDX
Reserved
CPUID leaves > 3 < 80000000 are only visible when IA32_CR_MISC_ENABLES.BOOT_NT4 (bit 22) is clear (Default).
7-31
OPTIMIZING CACHE USAGE
The deterministic cache parameter leaf provides a means to implement software with a degree of forward
compatibility with respect to enumerating cache parameters. Deterministic cache parameters can be
used in several situations, including:
•
•
Determine the size of a cache level.
•
Determine multithreading resource topology in an MP system (See Chapter 8, “Multiple-Processor
Management,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).
•
Determine cache hierarchy topology in a platform using multicore processors (See topology
enumeration white paper and reference code listed at the end of CHAPTER 1).
•
•
Manage threads and processor affinities.
Adapt cache blocking parameters to different sharing topology of a cache-level across HyperThreading Technology, multicore and single-core processors.
Determine prefetch stride.
The size of a given level of cache is given by:
(# of Ways) * (Partitions) * (Line_size) * (Sets) = (EBX[31:22] + 1) * (EBX[21:12] + 1) *
(EBX[11:0] + 1) * (ECX + 1)
7.6.3.1
Cache Sharing Using Deterministic Cache Parameters
Improving cache locality is an important part of software optimization. For example, a cache blocking
algorithm can be designed to optimize block size at runtime for single-processor implementations and a
variety of multiprocessor execution environments (including processors supporting HT Technology, or
multicore processors).
The basic technique is to place an upper limit of the blocksize to be less than the size of the target cache
level divided by the number of logical processors serviced by the target level of cache. This technique is
applicable to multithreaded application programming. The technique can also benefit single-threaded
applications that are part of a multi-tasking workloads.
7.6.3.2
Cache Sharing in Single-Core or Multicore
Deterministic cache parameters are useful for managing shared cache hierarchy in multithreaded applications for more sophisticated situations. A given cache level may be shared by logical processors in a
processor or it may be implemented to be shared by logical processors in a physical processor package.
Using the deterministic cache parameter leaf and initial APIC_ID associated with each logical processor
in the platform, software can extract information on the number and the topological relationship of
logical processors sharing a cache level.
7.6.3.3
Determine Prefetch Stride
The prefetch stride (see description of CPUID.01H.EBX) provides the length of the region that the
processor will prefetch with the PREFETCHh instructions (PREFETCHT0, PREFETCHT1, PREFETCHT2 and
PREFETCHNTA). Software will use the length as the stride when prefetching into a particular level of the
cache hierarchy as identified by the instruction used. The prefetch size is relevant for cache types of Data
Cache (1) and Unified Cache (3); it should be ignored for other cache types. Software should not assume
that the coherency line size is the prefetch stride.
If the prefetch stride field is zero, then software should assume a default size of 64 bytes is the prefetch
stride. Software should use the following algorithm to determine what prefetch size to use depending on
whether the deterministic cache parameter mechanism is supported or the legacy mechanism:
•
If a processor supports the deterministic cache parameters and provides a non-zero prefetch size,
then that prefetch size is used.
•
If a processor supports the deterministic cache parameters and does not provides a prefetch size
then default size for each level of the cache hierarchy is 64 bytes.
7-32
OPTIMIZING CACHE USAGE
•
If a processor does not support the deterministic cache parameters but provides a legacy prefetch
size descriptor (0xF0 - 64 byte, 0xF1 - 128 byte) will be the prefetch size for all levels of the cache
hierarchy.
•
If a processor does not support the deterministic cache parameters and does not provide a legacy
prefetch size descriptor, then 32-bytes is the default size for all levels of the cache hierarchy.
7-33
OPTIMIZING CACHE USAGE
7-34
CHAPTER 8
INTRODUCING SUB-NUMA CLUSTERING
Sub-NUMA Clustering (SNC) is a mode for improving average latency from last level cache (LLC) to local
memory. It replaces the Cluster-on-Die (COD) implementation which was used in the previous generation of the Intel® Xeon® processor E5 family.
8.1
SUB-NUMA CLUSTERING
SNC can improve the average LLC/memory latency by splitting the LLC into disjoint clusters based on
address range, with each cluster bound to a subset of memory controllers in the system.
Figure 8-1. Example of SNC Configuration
8.2
COMPARISON WITH CLUSTER-ON-DIE
SNC provides similar localization benefits to those of COD, but without some of COD’s disadvantages.
Unlike COD, SNC has the following properties.
INTRODUCING SUB-NUMA CLUSTERING
•
•
•
Only one Ultra Path Interconnect (UPI) caching agent is required.
Memory access latency in remote clusters is smaller, as no UPI flow is needed.
It uses LLC capacity more efficiently as there is no duplication of lines in the LLC.
A disadvantage of SNC is listed below.
•
8.3
Remote cluster addresses are never cached in local cluster LLC, resulting in larger latency
compared to Cluster-on-Die (COD) in some cases.
SNC USAGE
This section describes the following modes and their BIOS names in brackets (the exact BIOS parameter
names may vary depending on the BIOS vendor and version).
•
•
•
NUMA disabled (NUMA Optimized: Disabled)
SNC off (Integrated Memory Controller (IMC) Interleaving: auto, NUMA Optimized: Enabled,
Sub_NUMA Cluster: Disabled)
SNC on (IMC Interleaving: 1-way Interleave, NUMA Optimized: Enabled, Sub_NUMA Cluster:
Enabled)
The commands that follow were executed on a 2-socket Intel® Xeon® system, 28 cores per a socket,
Intel® Hyper-Threading Technology enabled.
8.3.1
How to Check NUMA Configuration
There are additional NUMA nodes in a system with SNC enabled; to get benefits from the SNC feature, a
developer should be aware of the NUMA configuration.
This chapter describes different ways to check NUMA system configuration.
libnuma
An application can check NUMA configuration with libnuma.
As an example this code uses the libnuma library to find the maximum number of NUMA nodes.
#include <stdio.h>
#include <stdlib.h>
#include <numa.h>
int main(int argc, char *argv[])
{
int max_node;
/* Check the system for NUMA support */
max_node = numa_max_node();
printf("%d\n", max_node);
return 0;
}
8-2
INTRODUCING SUB-NUMA CLUSTERING
numactl
In Linux* you can check the NUMA configuration with the numactl utility (the numactl-libs, and
numactl-devel packages might also be required).
$ numactl --hardware
NUMA disabled:
available: 1 nodes (0)
node 0 cpus: 0 1 2 3 4 5 6
23 24 25 26 27 28 29 30 31
47 48 49 50 51 52 53 54 55
71 72 73 74 75 76 77 78 79
95 96 97 98 99 100 101 102
node 0 size: 196045 MB
node 0 free: 190581 MB
node distances:
node
0
0: 10
7 8 9 10 11 12 13 14
32 33 34 35 36 37 38
56 57 58 59 60 61 62
80 81 82 83 84 85 86
103 104 105 106 107
15 16 17 18
39 40 41 42
63 64 65 66
87 88 89 90
108 109 110
19 20
43 44
67 68
91 92
111
21
45
69
93
22
46
70
94
SNC off:
available: 2 nodes (0-1)
node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
23 24 25 26 27 56 57 58 59 60 61 62 63 64 65 66 67
75 76 77 78 79 80 81 82 83
node 0 size: 96973 MB
node 0 free: 94089 MB
node 1 cpus: 28 29 30 31 32 33 34 35 36 37 38 39 40
48 49 50 51 52 53 54 55 84 85 86 87 88 89 90 91 92
100 101 102 103 104 105 106 107 108 109 110 111
node 1 size: 98304 MB
node 1 free: 95694 MB
node distances:
node
0
1
0: 10 21
1: 21 10
16 17 18 19 20 21 22
68 69 70 71 72 73 74
41 42 43 44 45 46 47
93 94 95 96 97 98 99
8-3
INTRODUCING SUB-NUMA CLUSTERING
SNC on:
available: 4 nodes (0-3)
node 0 cpus: 0 1 2 3 7 8 9 14 15 16 17 21 22 23
71 72 73 77 78 79
node 0 size: 47821 MB
node 0 free: 45759 MB
node 1 cpus: 4 5 6 10 11 12 13 18 19 20 24 25 26
74 75 76 80 81 82 83
node 1 size: 49152 MB
node 1 free: 47097 MB
node 2 cpus: 28 29 30 31 35 36 37 42 43 44 45 49
93 98 99 100 101 105 106 107
node 2 size: 49152 MB
node 2 free: 47617 MB
node 3 cpus: 32 33 34 38 39 40 41 46 47 48 52 53
97 102 103 104 108 109 110 111
node 3 size: 49152 MB
node 3 free: 47231 MB
node distances:
node
0
1
2
3
0: 10 11 21 21
1: 11 10 21 21
2: 21 21 10 11
3: 21 21 11 10
56 57 58 59 63 64 65 70
27 60 61 62 66 67 68 69
50 51 84 85 86 87 91 92
54 55 88 89 90 94 95 96
hwloc
In Linux* you can also check the NUMA configuration with the lstopo utility (the
required). For example:
hwloc package is
$ lstopo -p --of png --no-io --no-caches > numa_topology.png
8-4
INTRODUCING SUB-NUMA CLUSTERING
Figure 8-2. NUMA Disabled
8-5
INTRODUCING SUB-NUMA CLUSTERING
Figure 8-3. SNC Off
8-6
INTRODUCING SUB-NUMA CLUSTERING
Figure 8-4. SNC On
8.3.2
MPI Optimizations for SNC
Software needs to be NUMA optimized to benefit from SNC. Running one MPI rank per NUMA region
trivially ensures locality-of-access without requiring changes to the code to ensure that it behaves in a
NUMA friendly manner. This is a simple way to improve performance through the use of SNC.
The Intel® MPI Library includes some NUMA-related optimizations. The out-of-the-box behavior of the
Intel MPI Library should cover most cases, but there are some environment variables available to
control NUMA-related features that can improve performance in specific cases.
The relevant environment variables mainly relate to MPI process placement, that is, process
pinning/binding – such as the I_MPI_PIN_DOMAIN variable. For more information, see the Intel® MPI
Library Developer Reference. This environment variable defines a number of non-overlapping subsets
(domains) of logical processors on a node, and a set of rules for how MPI processes are bound to these
domains: one MPI process per domain, as illustrated below.
8-7
INTRODUCING SUB-NUMA CLUSTERING
Figure 8-5. Domain Example with One MPI Process Per Domain
Each MPI process can create a number of child threads to run within the corresponding domain. The
process’ threads can freely migrate from one logical processor to another within the particular domain.
For example, I_MPI_PIN_DOMAIN=numa may be a reasonable option for hybrid MPI/OpenMP* applications with SNC mode enabled. In this case, each domain consists of logical processors that share a
particular NUMA node. The number of domains on a machine is equal to the number of NUMA nodes on
the machine.
Refer to Intel MPI Library documentation for detailed information: https://software.intel.com/enus/intel-mpi-library/documentation.
8.3.3
SNC Performance Comparison
This section contains performance data collected with Intel® Memory Latency Checker (Intel® MLC) to
demonstrate the variations in performance (latency) between NUMA nodes in different modes.
An important factor in determining application performance is the time required for the application to
fetch data from the processor’s cache hierarchy and from the memory subsystem. Local memory and
cross-socket memory latencies vary significantly in a NUMA-enabled multi-socket system. Bandwidth
also plays an important role in determining performance. So measuring these latencies and bandwidths
is important when establishing a baseline for the system being tested, and performing performance analysis.
Intel MLC is a tool used to measure memory latencies and bandwidth, and how they change as the load
on the system increases. It also provides several options for more fine-grained investigation where bandwidth and latencies from a specific set of cores to caches or memory can be measured as well.
See https://software.intel.com/en-us/articles/intelr-memory-latency-checker for details about Intel®
MLC.
The following command was used to collect the performance data:
% mlc_avx512 --latency_matrix
This command measures idle memory latency from each socket in the system to every other socket and
reports the results in a matrix. The default invocation reports latencies to all of the NUMA nodes in the
system. NUMA-level reporting works only on Linux. On Windows, only socket level reporting is supported.
8-8
INTRODUCING SUB-NUMA CLUSTERING
NOTE
It is challenging to measure memory latencies on modern Intel processors accurately as
they have sophisticated HW prefetchers. Intel MLC automatically disables these
prefetchers while measuring the latencies and restores them to their previous state on
completion. The prefetcher control is exposed through an MSR (see
https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-someintel-processors for details) and MSR access requires root level permission. So, Intel MLC
needs to be run as ‘root’ on Linux.
The software configuration used for these measurements is Intel MLC v3.3-Beta2, Red Hat* Linux* 7.2.
NUMA disabled:
Using buffer size of 2000.000MB
Measuring idle latencies (in ns)...
Memory node
Socket
0
1
0 126.5 129.4
1 123.1 122.6
SNC off:
Using buffer size of 2000.000MB
Measuring idle latencies (in ns)...
Numa node
Numa node
0
1
0
1
81.9 153.1
153.7
82.0
SNC on:
Using buffer size of 2000.000MB
Measuring idle latencies (in ns)...
Numa node
Numa node
0
1
2
3
0
81.6
89.4 140.4 153.6
1
86.5
78.5 144.3 162.8
2
142.3 153.0
81.6
89.3
3
144.5 162.8
85.5
77.4
8-9
INTRODUCING SUB-NUMA CLUSTERING
8-10
CHAPTER 9
MULTICORE AND HYPER-THREADING TECHNOLOGY
This chapter describes software optimization techniques for multithreaded applications running in an
environment using either multiprocessor (MP) systems or processors with hardware-based multithreading support. Multiprocessor systems are systems with two or more sockets, each mated with a
physical processor package. Intel 64 and IA-32 processors that provide hardware multithreading support
include dual-core processors, quad-core processors and processors supporting HT Technology1.
Computational throughput in a multithreading environment can increase as more hardware resources
are added to take advantage of thread-level or task-level parallelism. Hardware resources can be added
in the form of more than one physical-processor, processor-core-per-package, and/or logical-processorper-core. Therefore, there are some aspects of multithreading optimization that apply across MP, multicore, and HT Technology. There are also some specific microarchitectural resources that may be implemented differently in different hardware multithreading configurations (for example: execution
resources are not shared across different cores but shared by two logical processors in the same core if
HT Technology is enabled). This chapter covers guidelines that apply to these situations.
This chapter covers:
•
•
•
Performance characteristics and usage models.
Programming models for multithreaded applications.
Software optimization techniques in five specific areas.
9.1
PERFORMANCE AND USAGE MODELS
The performance gains of using multiple processors, multicore processors or HT Technology are greatly
affected by the usage model and the amount of parallelism in the control flow of the workload. Two
common usage models are:
•
•
Multithreaded applications.
Multitasking using single-threaded applications.
9.1.1
Multithreading
When an application employs multithreading to exploit task-level parallelism in a workload, the control
flow of the multi-threaded software can be divided into two parts: parallel tasks and sequential tasks.
Amdahl’s law describes an application’s performance gain as it relates to the degree of parallelism in the
control flow. It is a useful guide for selecting the code modules, functions, or instruction sequences that
are most likely to realize the most gains from transforming sequential tasks and control flows into
parallel code to take advantage multithreading hardware support.
Figure 9-1 illustrates how performance gains can be realized for any workload according to Amdahl’s law.
The bar in Figure 9-1 represents an individual task unit or the collective workload of an entire application.
1. The presence of hardware multithreading support in Intel 64 and IA-32 processors can be detected by checking the feature flag CPUID .01H:EDX[28]. A return value of in bit 28 indicates that at least one form of hardware multithreading is
present in the physical processor package. The number of logical processors present in each package can also be
obtained from CPUID. The application must check how many logical processors are enabled and made available to application at runtime by making the appropriate operating system calls. See the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A for information.
MULTICORE AND HYPER-THREADING TECHNOLOGY
In general, the speed-up of running multiple threads on an MP systems with N physical processors, over
single-threaded execution, can be expressed as:
Tsequential
P
RelativeResponse = -------------------------------- =  1 – P + ---- + O


Tparallel
N
where P is the fraction of workload that can be parallelized, and O represents the overhead of multithreading and may vary between different operating systems. In this case, performance gain is the
inverse of the relative response.
Tsequential
Single Thread
1-P
P
Tparallel
1-P
P/2
P/2
Overhead
Multi-Thread on MP
Figure 9-1. Amdahl’s Law and MP Speed-up
When optimizing application performance in a multithreaded environment, control flow parallelism is
likely to have the largest impact on performance scaling with respect to the number of physical processors and to the number of logical processors per physical processor.
If the control flow of a multi-threaded application contains a workload in which only 50% can be executed
in parallel, the maximum performance gain using two physical processors is only 33%, compared to using
a single processor. Using four processors can deliver no more than a 60% speed-up over a single
processor. Thus, it is critical to maximize the portion of control flow that can take advantage of parallelism.
Improper implementation of thread synchronization can significantly increase the proportion of serial
control flow and further reduce the application’s performance scaling.
In addition to maximizing the parallelism of control flows, interaction between threads in the form of
thread synchronization and imbalance of task scheduling can also impact overall processor scaling significantly.
Excessive cache misses are one cause of poor performance scaling. In a multithreaded execution environment, they can occur from:
•
•
•
Aliased stack accesses by different threads in the same process.
Thread contentions resulting in cache line evictions.
False-sharing of cache lines between different processors.
Techniques that address each of these situations (and many other areas) are described in sections in this
chapter.
9.1.2
Multitasking Environment
Hardware multithreading capabilities in Intel 64 and IA-32 processors can exploit task-level parallelism
when a workload consists of several single-threaded applications and these applications are scheduled to
run concurrently under an MP-aware operating system. In this environment, hardware multithreading
capabilities can deliver higher throughput for the workload, although the relative performance of a single
9-2
MULTICORE AND HYPER-THREADING TECHNOLOGY
task (in terms of time of completion relative to the same task when in a single-threaded environment)
will vary, depending on how much shared execution resources and memory are utilized.
For development purposes, several popular operating systems (for example Microsoft Windows* XP
Professional and Home, Linux* distributions using kernel 2.4.19 or later2) include OS kernel code that
can manage the task scheduling and the balancing of shared execution resources within each physical
processor to maximize the throughput.
Because applications run independently under a multitasking environment, thread synchronization
issues are less likely to limit the scaling of throughput. This is because the control flow of the workload is
likely to be 100% parallel3 (if no inter-processor communication is taking place and if there are no
system bus constraints).
With a multitasking workload, however, bus activities and cache access patterns are likely to affect the
scaling of the throughput. Running two copies of the same application or same suite of applications in a
lock-step can expose an artifact in performance measuring methodology. This is because an access
pattern to the first level data cache can lead to excessive cache misses and produce skewed performance
results. Fix this problem by:
•
•
Including a per-instance offset at the start-up of an application.
•
Randomizing the sequence of start-up of applications when running multiple copies of the same suite.
Introducing heterogeneity in the workload by using different datasets with each instance of the application.
When two applications are employed as part of a multitasking workload, there is little synchronization
overhead between these two processes. It is also important to ensure each application has minimal
synchronization overhead within itself.
An application that uses lengthy spin loops for intra-process synchronization is less likely to benefit from
HT Technology in a multitasking workload. This is because critical resources will be consumed by the long
spin loops.
9.2
PROGRAMMING MODELS AND MULTITHREADING
Parallelism is the most important concept in designing a multithreaded application and realizing optimal
performance scaling with multiple processors. An optimized multithreaded application is characterized by
large degrees of parallelism or minimal dependencies in the following areas:
•
•
•
Workload.
Thread interaction.
Hardware utilization.
The key to maximizing workload parallelism is to identify multiple tasks that have minimal inter-dependencies within an application and to create separate threads for parallel execution of those tasks.
Concurrent execution of independent threads is the essence of deploying a multithreaded application on
a multiprocessing system. Managing the interaction between threads to minimize the cost of thread
synchronization is also critical to achieving optimal performance scaling with multiple processors.
Efficient use of hardware resources between concurrent threads requires optimization techniques in
specific areas to prevent contentions of hardware resources. Coding techniques for optimizing thread
synchronization and managing other hardware resources are discussed in subsequent sections.
Parallel programming models are discussed next.
2. This code is included in Red Hat* Linux Enterprise AS 2.1.
3. A software tool that attempts to measure the throughput of a multitasking workload is likely to introduce control flows
that are not parallel. Thread synchronization issues must be considered as an integral part of its performance measuring
methodology.
9-3
MULTICORE AND HYPER-THREADING TECHNOLOGY
9.2.1
Parallel Programming Models
Two common programming models for transforming independent task requirements into application
threads are:
•
•
Domain decomposition.
Functional decomposition.
9.2.1.1
Domain Decomposition
Usually large compute-intensive tasks use data sets that can be divided into a number of small subsets,
each having a large degree of computational independence. Examples include:
•
Computation of a discrete cosine transformation (DCT) on two-dimensional data by dividing the twodimensional data into several subsets and creating threads to compute the transform on each subset.
•
Matrix multiplication; here, threads can be created to handle the multiplication of half of matrix with
the multiplier matrix.
Domain Decomposition is a programming model based on creating identical or similar threads to process
smaller pieces of data independently. This model can take advantage of duplicated execution resources
present in a traditional multiprocessor system. It can also take advantage of shared execution resources
between two logical processors in HT Technology. This is because a data domain thread typically
consumes only a fraction of the available on-chip execution resources.
Section 9.3.4, “Key Practices of Execution Resource Optimization,” discusses additional guidelines that
can help data domain threads use shared execution resources cooperatively and avoid the pitfalls
creating contentions of hardware resources between two threads.
9.2.2
Functional Decomposition
Applications usually process a wide variety of tasks with diverse functions and many unrelated data sets.
For example, a video codec needs several different processing functions. These include DCT, motion estimation and color conversion. Using a functional threading model, applications can program separate
threads to do motion estimation, color conversion, and other functional tasks.
Functional decomposition will achieve more flexible thread-level parallelism if it is less dependent on the
duplication of hardware resources. For example, a thread executing a sorting algorithm and a thread
executing a matrix multiplication routine are not likely to require the same execution unit at the same
time. A design recognizing this could advantage of traditional multiprocessor systems as well as multiprocessor systems using processors supporting HT Technology.
9.2.3
Specialized Programming Models
Intel Core Duo processor and processors based on Intel Core microarchitecture offer a second-level
cache shared by two processor cores in the same physical package. This provides opportunities for two
application threads to access some application data while minimizing the overhead of bus traffic.
Multi-threaded applications may need to employ specialized programming models to take advantage of
this type of hardware feature. One such scenario is referred to as producer-consumer. In this scenario,
one thread writes data into some destination (hopefully in the second-level cache) and another thread
executing on the other core in the same physical package subsequently reads data produced by the first
thread.
The basic approach for implementing a producer-consumer model is to create two threads; one thread is
the producer and the other is the consumer. Typically, the producer and consumer take turns to work on
a buffer and inform each other when they are ready to exchange buffers. In a producer-consumer model,
there is some thread synchronization overhead when buffers are exchanged between the producer and
consumer. To achieve optimal scaling with the number of cores, the synchronization overhead must be
kept low. This can be done by ensuring the producer and consumer threads have comparable time
constants for completing each incremental task prior to exchanging buffers.
9-4
MULTICORE AND HYPER-THREADING TECHNOLOGY
Example 9-1 illustrates the coding structure of single-threaded execution of a sequence of task units,
where each task unit (either the producer or consumer) executes serially (shown in Figure 9-2). In the
equivalent scenario under multi-threaded execution, each producer-consumer pair is wrapped as a
thread function and two threads can be scheduled on available processor resources simultaneously.
Example 9-1. Serial Execution of Producer and Consumer Work Items
for (i = 0; i < number_of_iterations; i++) {
producer (i, buff); // pass buffer index and buffer address
consumer (i, buff);
}(
Main
Thread
P(1)
C(1)
P(1)
C(1)
P(1)
Figure 9-2. Single-threaded Execution of Producer-consumer Threading Model
9.2.3.1
Producer-Consumer Threading Models
Figure 9-3 illustrates the basic scheme of interaction between a pair of producer and consumer threads.
The horizontal direction represents time. Each block represents a task unit, processing the buffer
assigned to a thread.
The gap between each task represents synchronization overhead. The decimal number in the parenthesis
represents a buffer index. On an Intel Core Duo processor, the producer thread can store data in the
second-level cache to allow the consumer thread to continue work requiring minimal bus traffic.
Main
Thread
P: producer
C: consumer
P(1)
P(2)
P(1)
P(2)
P(1)
C(1)
C(2)
C(1)
C(2)
Figure 9-3. Execution of Producer-consumer Threading Model
on a Multicore Processor
The basic structure to implement the producer and consumer thread functions with synchronization to
communicate buffer index is shown in Example 9-2.
9-5
MULTICORE AND HYPER-THREADING TECHNOLOGY
Example 9-2. Basic Structure of Implementing Producer Consumer Threads
(a) Basic structure of a producer thread function
void producer_thread()
{
int iter_num = workamount - 1; // make local copy
int mode1 = 1; // track usage of two buffers via 0 and 1
produce(buffs[0],count); // placeholder function
while (iter_num--) {
Signal(&signal1,1); // tell the other thread to commence
produce(buffs[mode1],count); // placeholder function
WaitForSignal(&end1);
mode1 = 1 - mode1; // switch to the other buffer
}
}
b) Basic structure of a consumer thread
void consumer_thread()
{
int mode2 = 0; // first iteration start with buffer 0, than alternate
int iter_num = workamount - 1;
while (iter_num--) {
WaitForSignal(&signal1);
consume(buffs[mode2],count); // placeholder function
Signal(&end1,1);
mode2 = 1 - mode2;
}
consume(buffs[mode2],count);
}
It is possible to structure the producer-consumer model in an interlaced manner such that it can minimize bus traffic and be effective on multicore processors without shared second-level cache.
In this interlaced variation of the producer-consumer model, each scheduling quanta of an application
thread comprises of a producer task and a consumer task. Two identical threads are created to execute
in parallel. During each scheduling quanta of a thread, the producer task starts first and the consumer
task follows after the completion of the producer task; both tasks work on the same buffer. As each task
completes, one thread signals to the other thread notifying its corresponding task to use its designated
buffer. Thus, the producer and consumer tasks execute in parallel in two threads. As long as the data
generated by the producer reside in either the first or second level cache of the same core, the consumer
can access them without incurring bus traffic. The scheduling of the interlaced producer-consumer model
is shown in Figure 9-4.
Thread 0
Thread 1
P(1)
C(1)
P(1)
C(1)
P(1)
P(2)
C(2)
P(2)
C(2)
Figure 9-4. Interlaced Variation of the Producer Consumer Model
9-6
MULTICORE AND HYPER-THREADING TECHNOLOGY
Example 9-3 shows the basic structure of a thread function that can be used in this interlaced producerconsumer model.
Example 9-3. Thread Function for an Interlaced Producer Consumer Model
// master thread starts first iteration, other thread must wait
// one iteration
void producer_consumer_thread(int master)
{
int mode = 1 - master; // track which thread and its designated
// buffer index
unsigned int iter_num = workamount >> 1;
unsigned int i=0;
iter_num += master & workamount & 1;
if (master) // master thread starts the first iteration
{
produce(buffs[mode],count);
Signal(sigp[1-mode1],1); // notify producer task in follower
// thread that it can proceed
consume(buffs[mode],count);
Signal(sigc[1-mode],1);
i = 1;
}
for (; i < iter_num; i++)
{
WaitForSignal(sigp[mode]);
produce(buffs[mode],count); // notify the producer task in
// other thread
Signal(sigp[1-mode],1);
WaitForSignal(sigc[mode]);
consume(buffs[mode],count);
Signal(sigc[1-mode],1);
}
}
9.2.4
Tools for Creating Multithreaded Applications
Programming directly to a multithreading application programming interface (API) is not the only method
for creating multithreaded applications. New tools (such as the Intel compiler) have become available
with capabilities that make the challenge of creating multithreaded application easier.
Features available in the latest Intel compilers are:
•
•
Generating multithreaded code using OpenMP* directives4.
Generating multithreaded code automatically from unmodified high-level code5.
4. Intel Compiler 5.0 and later supports OpenMP directives. Visit http://software.intel.com for details.
5. Intel Compiler 6.0 supports auto-parallelization.
9-7
MULTICORE AND HYPER-THREADING TECHNOLOGY
9.2.4.1
Programming with OpenMP Directives
OpenMP provides a standardized, non-proprietary, portable set of Fortran and C++ compiler directives
supporting shared memory parallelism in applications. OpenMP supports directive-based processing.
This uses special preprocessors or modified compilers to interpret parallelism expressed in Fortran
comments or C/C++ pragmas. Benefits of directive-based processing include:
•
•
The original source can be compiled unmodified.
•
Incremental code changes help programmers maintain serial consistency. When the code is run on
one processor, it gives the same result as the unmodified source code.
•
•
Offering directives to fine tune thread scheduling imbalance.
It is possible to make incremental code changes. This preserves algorithms in the original code and
enables rapid debugging.
Intel’s implementation of OpenMP runtime can add minimal threading overhead relative to handcoded multithreading.
9.2.4.2
Automatic Parallelization of Code
While OpenMP directives allow programmers to quickly transform serial applications into parallel applications, programmers must identify specific portions of the application code that contain parallelism and
add compiler directives. Intel Compiler 6.0 supports a new (-QPARALLEL) option, which can identify loop
structures that contain parallelism. During program compilation, the compiler automatically attempts to
decompose the parallelism into threads for parallel processing. No other intervention or programmer is
needed.
9.2.4.3
Supporting Development Tools
See Appendix A, “Application Performance Tools” for information on the various tools that Intel provides
for software development.
9.3
OPTIMIZATION GUIDELINES
This section summarizes optimization guidelines for tuning multithreaded applications. Five areas are
listed (in order of importance):
•
•
•
•
•
Thread synchronization.
Bus utilization.
Memory optimization.
Front end optimization.
Execution resource optimization.
Practices associated with each area are listed in this section. Guidelines for each area are discussed in
greater depth in sections that follow.
Most of the coding recommendations improve performance scaling with processor cores; and scaling
due to HT Technology. Techniques that apply to only one environment are noted.
9.3.1
Key Practices of Thread Synchronization
Key practices for minimizing the cost of thread synchronization are summarized below:
•
Insert the PAUSE instruction in fast spin loops and keep the number of loop repetitions to a minimum
to improve overall system performance.
•
Replace a spin-lock that may be acquired by multiple threads with pipelined locks such that no more
than two threads have write accesses to one lock. If only one thread needs to write to a variable
shared by two threads, there is no need to acquire a lock.
9-8
MULTICORE AND HYPER-THREADING TECHNOLOGY
•
•
•
Use a thread-blocking API in a long idle loop to free up the processor.
Prevent “false-sharing” of per-thread-data between two threads.
Place each synchronization variable alone, separated by 128 bytes or in a separate cache line.
See Section 9.4, “Thread Synchronization,” for details.
9.3.2
Key Practices of System Bus Optimization
Managing bus traffic can significantly impact the overall performance of multithreaded software and MP
systems. Key practices of system bus optimization for achieving high data throughput and quick
response are:
•
•
Improve data and code locality to conserve bus command bandwidth.
•
Consider using overlapping multiple back-to-back memory reads to improve effective cache miss
latencies.
•
Use full write transactions to achieve higher data throughput.
Avoid excessive use of software prefetch instructions and allow the automatic hardware prefetcher to
work. Excessive use of software prefetches can significantly and unnecessarily increase bus
utilization if used inappropriately.
See Section 9.5, “System Bus Optimization,” for details.
9.3.3
Key Practices of Memory Optimization
Key practices for optimizing memory operations are summarized below:
•
Use cache blocking to improve locality of data access. Target one quarter to one half of cache size
when targeting processors supporting HT Technology.
•
Minimize the sharing of data between threads that execute on different physical processors sharing a
common bus.
•
•
Minimize data access patterns that are offset by multiples of 64-KBytes in each thread.
•
Add a per-instance stack offset when two instances of the same application are executing in lock
steps to avoid memory accesses that are offset by multiples of 64 KByte or 1 MByte when targeting
processors supporting HT Technology.
Adjust the private stack of each thread in an application so the spacing between these stacks is not
offset by multiples of 64 KBytes or 1 MByte (prevents unnecessary cache line evictions) when
targeting processors supporting HT Technology.
See Section 9.6, “Memory Optimization,” for details.
9.3.4
Key Practices of Execution Resource Optimization
Each physical processor has dedicated execution resources. Logical processors in physical processors
supporting HT Technology share specific on-chip execution resources. Key practices for execution
resource optimization include:
•
•
Optimize each thread to achieve optimal frequency scaling first.
•
Use on-chip execution resources cooperatively if two threads are sharing the execution resources in
the same physical processor package.
•
For each processor supporting HT Technology, consider adding functionally uncorrelated threads to
increase the hardware resource utilization of each physical processor package.
Optimize multithreaded applications to achieve optimal scaling with respect to the number of
physical processors.
See Section 9.8, “Affinities and Managing Shared Platform Resources,” for details.
9-9
MULTICORE AND HYPER-THREADING TECHNOLOGY
9.3.5
Generality and Performance Impact
The next five sections cover the optimization techniques in detail. Recommendations discussed in each
section are ranked by importance in terms of estimated local impact and generality.
Rankings are subjective and approximate. They can vary depending on coding style, application and
threading domain. The purpose of including high, medium and low impact ranking with each recommendation is to provide a relative indicator as to the degree of performance gain that can be expected when
a recommendation is implemented.
It is not possible to predict the likelihood of a code instance across many applications, so an impact
ranking cannot be directly correlated to application-level performance gain. The ranking on generality is
also subjective and approximate.
Coding recommendations that do not impact all three scaling factors are typically categorized as medium
or lower.
9.4
THREAD SYNCHRONIZATION
Applications with multiple threads use synchronization techniques in order to ensure correct operation.
However, thread synchronization that are improperly implemented can significantly reduce performance.
The best practice to reduce the overhead of thread synchronization is to start by reducing the application’s requirements for synchronization. Intel Thread Profiler can be used to profile the execution timel