DS87C550 EPROM High–Speed Micro with A/D and PWM

DS87C550
PRODUCT PREVIEW
DS87C550
EPROM High–Speed
Micro with A/D and PWM
FEATURES
• 87C52 Compatible
•
•
•
•
•
•
•
•
•
•
•
•
– 8051–pin and instruction set compatible
– Three 16–bit timer/counters
– 256 bytes scratchpad RAM
On–chip Memory
– 8K bytes EPROM (OTP & Windowed Packages)
– 1K byte extra on–chip SRAM for MOVX access
On–chip Analog to Digital Converter
– Eight channels of analog input, 10–bit resolution
– Fast conversion time
– Selectable internal or external reference voltage
Pulse Width Modulator Outputs
– Four channels of 8–bit PWM
– Channels cascadable to 16–bit PWM
4 capture + 3 compare registers
55 I/O Port pins
New Dual Data Pointer Operation
– Either data pointer can be incremented or
decremented
ROMSIZE Feature
– Selects effective on–chip ROM size from 0 to 8K
– Allows access to entire external memory map
– Dynamically adjustable by software
High–Speed Architecture
– 4 clocks/machine cycle (8051 = 12)
– Runs DC to 33 MHz clock rates
– Single–cycle instruction in 121 ns
– New Stretch Cycle feature allows access to
fast/slow memory or peripherals
Unique Power Savings Modes
EMI Reduction Mode disables ALE when not needed
High integration controller includes:
– Power–fail reset
– Early–warning power–fail interrupt
– Two full–duplex hardware serial ports
– Programmable Watchdog timer
16 total interrupt sources with 6 external
PIN ASSIGNMENT
9
1
61
10
60
DALLAS
DS87C550
26
44
27
68–PIN PLCC
68–PIN WINDOWED CLCC
80
43
65
1
64
DALLAS
DS87C550
24
41
25
40
80–PIN PQFP
Available in 68–pin PLCC, 80–pin PQFP, and
68–pin windowed CLCC
DESCRIPTION
The DS87C550 is a member of the fastest 100% 8051
compatible microcontroller family available. It features a
redesigned processor core that removes wasted clock
and memory cycles. As a result, it executes 8051
instructions up to 3 times faster than the original architecture for the same crystal speed. The DS87C550 also
091698 1/47
DS87C550
offers a maximum crystal speed of 33 MHz, resulting in
apparent execution speeds of up to 99 MHz.
The DS87C550 uses an industry standard 8051 pin–out
and includes standard resources such as 3 timer/counters, and 256 bytes of scratchpad RAM. This device also
features 8K bytes of EPROM with an extra 1K byte of
data RAM (in addition to the 256 bytes of scratchpad
RAM), and 55 I/O ports pins. Both One–Time–Programmable (OTP) and windowed packages are available.
Besides greater speed, the DS87C550 includes a
second full hardware serial port, seven additional interrupts, a programmable watchdog timer, brownout monitor, and power–fail reset.
The DS87C550 also provides dual data pointers
(DPTRs) to speed block data memory moves. The user
can also dynamically adjust the speed of external
accesses between two and twelve machine cycles for
flexibility in selecting memory and peripherals.
Power Management Mode (PMM) is useful for portable
or battery powered applications. This feature allows
software to select a lower speed clock as the main time
base. While normal operation has a machine cycle rate
of 4 clocks per cycle, the PMM allows the processor to
run at 1024 clocks per cycle. For example, at 12 MHz,
standard operation has a machine cycle rate of 3 MHz.
In Power Management Mode, software can select an
11.7 kHz (12MHz/1024) machine cycle rate. There is a
corresponding reduction in power consumption due to
the processor running slower.
The DS87C550 also offers two features that can significantly reduce electromagnetic interference (EMI). One
EMI reduction feature allows software to select a
reduced emission mode that disables the ALE signal
when it is unneeded. The other EMI reduction feature
controls the current to the address and data pins interfacing to external devices producing a controlled transition of these signals.
ORDERING INFORMATION
PART NUMBER
PACKAGE
MAX. CLOCK SPEED
TEMPERATURE RANGE
DS87C550–QCL
68–pin PLCC
33 MHz
0°C to 70°C
DS87C550–FCL
80–pin PQFP
33 MHz
0°C to 70°C
DS87C550–QNL
68–pin PLCC
33 MHz
–40°C to +85°C
DS87C550–FNL
80–pin PQFP
33 MHz
–40°C to +85°C
DS87C550–KCL
68–pin windowed CLCC
33 MHz
0°C to 70°C
091698 2/47
DS87C550
DS87C550 BLOCK DIAGRAM Figure 1
P6.0–P6.5
(PWM I/O)
P6.7
P5.0–P5.7
(ADC0:7)
AVCC
AVSS
Aref–
Aref+
P4.0–P4.7
(CAPTURE/COMPARE I/O)
STADC
PORT 4
PORT 6
PORT 5
PWM
x4
10–BIT
ADC
PORT LATCH
PORT LATCH
ALU
8K x 8
EPROM
STACK
POLMER
P0.0–P0.7
PSW
ALU REG. 2
PORT 0
ALU REG. 1
PORT LATCH
1K x 8
SRAM
B REGISTER
DATA BUS
TIMER 2
CAP/CMP
SERIAL PORT 1
PORT 1
P1.0–P1.7
PORT LATCH
ACCUMULATER
PORT LATCH
DPTR
1
INTERRUPT
LOGIC
PC ADDR. REG.
SFR RAM
ADDRESS
TIMER 1
256 BYTES
SFM SRMA
PC INCREMENT
POWER CONTROL REG.
CLOCKS AND
MEMORY CONTROL
OSCILLATOR
WATCHDOG TIMER
RESET
CONTROL
P2.0–P2.7
DPTR0
INSTRUCTION
DECODE
PORT 2
TIMER 0
INSTRUCTION REG.
PORT LATCH
PROG. COUNTER
PORT LATCH
PORT 3
P3.0–P3.7
SERIAL PORT 0
TIMED
ACCESS
ADDRESS BUS
BUFFER
WATCHDOG REG.
VCC POWER MONITOR
GND
VCC
RST
PSEN
ALE PROG
EA VCC
Xtal1
Xtal2
091698 3/47
DS87C550
PIN DESCRIPTION Table 1
PLCC/
CLCC
QFP
SIGNAL
NAME
2
72
VCC
VCC – Digital +5V power input.
36
37
34
35
GND
GND – Digital ground.
15
9
RST
RST – I/O. The RST input pin contains a Schmitt voltage input to recognize
external active high Reset inputs. The pin also employs an internal pull–down
resistor to allow for a combination of wired OR external Reset sources. An RC
is not required for power–up, as the DS87C550 provides this function internally.
This pin also acts as an output when the source of the reset is internal to the
device (i.e., watchdog timer, power fail, or crystal fail detect). In this case, the
RST pin will be held high while the processor is in a reset state, and will return
to low as the processor exits this state. When this output capability is used, the
RST pin should not be connected to an RC network or a logic output driver.
35
34
32
31
XTAL1
XTAL2
Input – The crystal oscillator pins XTAL1 and XTAL2 provide support for fundamental mode, parallel resonant, AT cut crystals. XTAL1 acts also as an input
if there is an external clock source in place of a crystal. XTAL2 serves as the
output of the crystal amplifier. Note that this output cannot be used to drive any
additional load when a crystal is attached as this can disturb the oscillator circuit.
47
48
PSEN
PSEN – Output. The Program Store Enable output. This signal is commonly
connected to optional external ROM memory as a chip enable. PSEN will provide an active low pulse during a program byte access, and is driven high when
not accessing external program memory.
48
49
ALE
ALE – Output. The Address Latch Enable output functions as a clock to latch
the external address LSB from the multiplexed address/data bus on Port 0. This
signal is commonly connected to the latch enable of an external 373 family
transparent latch. ALE is driven high when the DS87C550 is in a Reset condition. ALE can also be disabled and forced high using the EMI reduction mode
ALEOFF.
091698 4/47
DESCRIPTION
DS87C550
PIN DESCRIPTION Table 1 Cont’d
PLCC/
CLCC
QFP
SIGNAL
NAME
DESCRIPTION
49
50
EA
EA – Input. An active low input pin that when connected to ground will force
the DS87C550 to use an external program memory. The internal RAM is still
accessible as determined by register settings. EA should be connected to VCC
to use internal program memory. The input level on this pin is latched at reset.
16–23
10–17
P1.0–P1.7
Port 1 – I/O. Port 1 functions as both an 8–bit bi–directional I/O port and an
alternate functional interface for several internal resources. The reset condition
of Port 1 is all bits at logic 1. In this state, a weak pull–up holds the port high.
This condition allows the pins to serve as both an input and an output. Input is
possible since any external circuit whose output drives the port will overcome
the weak pull–up. When software writes a 0 to any Port 1 pin, the DS87C550
will activate a strong pull–down that remains on until either a 1 is written or a
reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pull–up. Once the
momentary strong driver turns off, the port again returns to a weakly held high
output (and input) state. The alternate functions of Port 1 pins are detailed
below. Note that when the Capture/Compare functions of timer 2 are used, the
interrupt input pins become capture trigger inputs.
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
50–57
56
55
54
53
52
51
50
51–58
57
56
55
54
53
52
51
39–46
39
40
41
42
43
44
45
46
38–42,
45–47
38
39
40
41
42
45
46
47
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
INT2/CT0 External Interrupt 2/Capture Trigger 0
INT3/CT1 External Interrupt 3/Capture Trigger 1
INT4/CT2 External Interrupt 4/Capture Trigger 2
INT5/CT3 External Interrupt 5/Capture Trigger 3
T2
External I/O for Timer/Counter 2
T2EX
Timer/Counter 2 Capture/Reload Trigger
RXD1
Serial Port 1 Input
TXD1
Serial Port 1 Output
P0.0 (AD0)
P.01 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
Port 0–I/O – AD0–7. Port 0 is an open–drain 8–bit bi–directional general–purpose I/O port. When used in this mode Pull–up resistors are required to provide
a logic 1 output. As an alternate function, Port 0 operates as a multiplexed
address/data bus to access off–chip memory or peripherals. In this mode, the
LSB of the memory address is output on the bus during the time that ALE is
high. When ALE falls to a logic 0, the port transitions to a bi–directional data bus.
In this mode, the port provides active high drivers for logic 1 output. The reset
condition of Port 0 is tri–state (i.e., the open drain devices are off).
P2.0 (A8)
P2.1 (A9)
P2.2 (A10)
P2.3 (A11)
P2.4 (A12)
P2.5 (A13)
P2.6 (A14)
P2.7 (A15)
Port 2–I/O Address A15:A8. Port 2 functions as an 8–bit bi–directional I/O
port or alternately as an external address bus (A15–A8). The reset condition
of Port 2 is logic high I/O state. In this state, weak pull–ups hold the port high
allowing the pins to be used as an input or output as described above for Port
1. As an alternate function Port 2 can function as MSB of the external address
bus. This bus can be used to read external memory or peripherals.
091698 5/47
DS87C550
PIN DESCRIPTION Table 1 cont’d
PLCC/
CLCC
QFP
SIGNAL
NAME
24–31
18–20,
23–27
P3.0–P3.7
24
25
26
27
28
29
30
31
18
19
20
23
24
25
26
27
7–14
80,
1–2,
4–8
7
8
9
10
11
12
13
14
80
1
2
4
5
6
7
8
1, 62–
68
64–71
1
68
67
66
65
64
63
62
71
70
69
68
67
66
65
64
091698 6/47
DESCRIPTION
Port 3 – I/O. Port 3 functions as an 8–bit bi–directional I/O port or alternately
as an interface for External Interrupts, Serial Port 0, Timer 0 & 1 Inputs, and RD
and WR strobes. When functioning as an I/O port, these pins operate as indicated above for Port 1. The alternate modes of Port 3 are detailed below.
Port
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0–P4.7
Port 4 – I/O. Port 4 functions as an 8–bit bi–directional I/O port or alternately
as an interface to Timer 2’s Capture Compare functions. When functioning as
an I/O port, these pins operate as indicated in the Port 1 description. The alternate modes of Port 4 are detailed below.
Port 4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0–P5.7
Alternate Mode
RXD0
Serial Port 0 Input
TXD0
Serial Port 0 Output
External Interrupt 0
INT0
External Interrupt 1
INT1
T0
Timer 0 External Input
T1
Timer 1 External Input
External Data Memory Write Strobe
WR
External Data Memory Read Strobe
RD
Alternate Mode
CMSR0
Timer 2 compare match set/reset output 0
CMSR1
Timer 2 compare match set/reset output 1
CMSR2
Timer 2 compare match set/reset output 2
CMSR3
Timer 2 compare match set/reset output 3
CMSR4
Timer 2 compare match set/reset output 4
CMSR5
Timer 2 compare match set/reset output 5
CMT0
Timer 2 compare match toggle output 0
CMT1
Timer 2 compare match toggle output 1
Port 5 – I/O. Port 5 functions as an open–drain 8–bit bi–directional I/O port or
alternately as an interface to the A/D converter. When used for general purpose
I/O, these pins operate in a quasi–bi–directional mode. Writing a logic 1 to these
pins (reset condition) will cause them to tri–state. This allows the pins to serve
as inputs since the tri–state condition can be driven by an external device. If a
logic 0 is written to a pin, it is pulled down internally and therefore serves as an
output pin containing a logic 0. Because these pins are open drain, external
pull–up resistors are required to create a logic 1 level when they are used as
outputs. As an alternate function Port 5 pins operate as the analog inputs for
the A/D converter as described below.
Port
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
Alternate Mode
ADC0
Analog to Digital Converter input channel 0
ADC1
Analog to Digital Converter input channel 1
ADC2
Analog to Digital Converter input channel 2
ADC3
Analog to Digital Converter input channel 3
ADC4
Analog to Digital Converter input channel 4
ADC5
Analog to Digital Converter input channel 5
ADC6
Analog to Digital Converter input channel 6
ADC7
Analog to Digital Converter input channel 7
DS87C550
PIN DESCRIPTION Table 1 cont’d
PLCC/
CLCC
QFP
SIGNAL
NAME
DESCRIPTION
3–6, 32
33, 38
28, 29
37, 74–
77
P6.0–P6.5,
P6.7
4
5
32
33
6
38
3
75
76
28
29
77
37
74
59
60
Avref+
A/D +Reference – Input. When selected, supplies the positive reference voltage for the A/D converter. This signal should be isolated from digital VCC to prevent noise from affecting A/D measurements.
58
59
Avref–
A/D –Reference – Input. When selected, supplies the negative reference voltage for the A/D converter. This signal should be isolated from digital Gnd to prevent noise from affecting A/D measurements.
61
63
AVCC
Analog Vcc
60
61
AVSS
Analog Ground
3, 21,
22, 30,
33, 36,
43, 44,
62, 73,
78,79
NC
Port 6 – I/O. Port 6 functions as an 7–bit bi–directional I/O port or alternately
as an interface to the PWM and A/D on–board peripherals. As an I/O port, these
pins operate as described in Port 1. The alternate modes of Port 4 are detailed
below.
Port
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.7
Alternate
PWMO0
PWMO1
PWMO2
PWMO3
PWMC0
PWMC1
STADC
Function
PWM channel 0 output
PWM channel 1 output
PWM channel 2 output
PWM channel 3 output
PWM0 clock input
PWM1 clock input
External A/D conversion start signal (active low)
NC–Reserved. These pins should not be connected. They are reserved for use
with future devices in this family.
COMPATIBILITY
The DS87C550 is a fully static CMOS 8051 compatible
microcontroller designed for high performance. While
remaining familiar to 8051 family users, it has many new
features. With very few exceptions, software written for
existing 8051 based systems works without modification on the DS87C550. The exception is critical timing
since the High Speed Micro performs its instructions
much faster than the original for any given crystal selection. The DS87C550 runs the standard 8051 family
instruction set and is pin compatible with existing
devices with similar features in PLCC or QFP packages.
The DS87C550 provides three 16–bit timer/counters,
two full–duplex serial ports, 256 bytes of direct RAM
plus 1K byte of extra MOVX RAM. I/O ports have the
same operation as a standard 8051 product. Timers will
default to a 12 clock per cycle operation to keep their
timing compatible with original 8051 family systems.
However, timers are individually programmable to run at
the new 4 clocks per cycle if desired.
The DS87C550 provides several new hardware features implemented by new Special Function Registers.
A summary of all SFRs is provided in Table 2.
PERFORMANCE OVERVIEW
The DS87C550 features a high speed 8051 compatible
core. Higher speed comes not just from increasing the
clock frequency, but from a newer, more efficient
design.
This updated core does not have the dummy memory
cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock
frequency divided by 12. In the DS87C550, the same
machine cycle takes 4 clocks. Thus the fastest instruc-
091698 7/47
DS87C550
tion, 1 machine cycle, executes 3 times faster for the
same crystal frequency. Note that these are identical
instructions. The majority of instructions on the
DS87C550 will see the full 3 to 1 speed improvement.
However, some instructions will achieve between 1.5
and 2.4 to 1 improvement. Regardless of specific performance improvements, all instructions are faster than
the original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual mix of
instructions used. Speed sensitive applications would
make the most use of instructions that are 3 times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any arbitrary combination of instructions. These architecture
improvements and the sub–micron CMOS design produce a peak instruction cycle in 121 ns (8.25 MIPs). The
Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of
memory.
ers optionally can run at 4 clocks per increment to take
advantage of faster processor operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For example, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
they required the same amount of time. In the
DS87C550, the MOVX instruction takes as little as two
machine cycles or 8 oscillator cycles but the “MOV
direct, direct” uses three machine cycles or 12 oscillator
cycles. While both are faster than their original counterparts, they now have different execution times. This is
because the DS87C550 usually uses one instruction
cycle for each instruction byte. Examine the timing of
each instruction for familiarity with the changes. Note
that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the original architecture, all were one or two cycles except for
MUL and DIV. Refer to the High Speed Micro User’s
Guide for details and individual instruction timing.
INSTRUCTION SET SUMMARY
All instructions in the DS87C550 perform exactly the
same functions as their 8051 counterparts. Their effect
on bits, flags, and other status functions is identical.
However, the timing of each instruction is different. This
applies both in absolute and relative number of clocks.
For absolute timing of real–time events, the timing of
software loops can be calculated using a table in the
High Speed Micro User’s Guide. However, counter/timers default to run at the old 12 clocks per increment. In
this way, timer–based events occur at the standard
intervals with software executing at higher speed. Tim-
091698 8/47
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special
features of the DS87C550. This allows the DS87C550
to have many new features but use the same instruction
set as the 8051. When writing software to use a new feature, an equate statement defines the SFR to an assembler or compiler. This is the only change needed to
access the new function. The DS87C550 duplicates the
SFRs contained in the standard 80C52. Table 2 shows
the register addresses and bit locations. Many are standard 80C52 registers. The High Speed Micro User’s
Guide describes all SFRs in full detail.
DS87C550
SPECIAL FUNCTION REGISTER LOCATION: Table 2
REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
AD–
DRESS
PORT0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
80h
SP
81h
DPL
82h
DPH
83h
DPL1
84h
DPH1
85h
DPS
ID1
ID0
TSL
–
–
–
–
SEL
86h
PCON
SMOD_0
SMOD0
OFDF
OFDE
GF1
GF0
STOP
IDLE
87h
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
88h
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
89h
TL0
8Ah
TL1
8Bh
TH0
8Ch
TH1
8Dh
CKCON
WD1
WD0
T2M
T1M
T0M
MD2
MD1
MD0
8Eh
PORT1
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
RCON
–
–
–
–
CKRDY
RGMD
P1.1
P1.0
90h
RGSL
BGS
91h
SCON0
SM0/FE_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
98h
SBUF0
99h
PMR
CD1
CD0
SWB
CTM
4X/2X
ALEOFF
DME1
DME0
9F0h
PORT2
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
A0h
SADDR0
A1h
SADDR1
A2h
IE
EA
EAD
ES1
ES0
ET1
EX1
ET0
EX0
A8h
CMPL0
A9h
CMPL1
AAh
CMPL2
ABh
CPTL0
ACh
CPTL1
ADh
CPTL2
AEh
CPTL3
AFh
PORT3
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
B0h
ADCON1
STRT/
BSY
EOC
CONT/
SS
ADEX
WCQ
WCM
ADON
WCIO
B2h
091698 9/47
DS87C550
SPECIAL FUNCTION REGISTER LOCATION: Table 2 cont’d
REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
AD–
DRESS
ADCON2
OUTCF
MUX2
MUX1
MUX0
APS3
APS2
APS1
APS0
B3h
ADMSB
B4h
ADLSB
B5h
WINHI
B6h
WINLO
IP
B7h
–
PAD
PS1
PS0
PT1
PX1
PT0
PX0
B8h
SADEN0
B9h
SADEN1
BAh
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
RL2
BEh
T2MOD
–
–
–
–
–
–
T2OE
DCEN
BFh
PORT4
CMT1
CMT0
CMSR5
CMSR4
CMSR3
CMSR2
CMSR1
CMSR0
C0h
ROMSIZE
–
–
–
–
–
RMS2
RMS1
RMS0
C2h
PORT5
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
C4h
STATUS
PIP
HIP
LIP
–
SPTA1
SPRA1
SPTA0
SPRA0
C5h
TA
T2IR
C7h
–
CM2F
CM1F
CM0F
IE5/CF3
IE4/CF2
IE3/CF1
IE2/CF0
C8h
CMPH0
C9h
CMPH1
CAh
CMPH2
CBh
CPTH0
CCh
CPTH1
CDh
CPTH2
CEh
CPTH3
CFh
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
D0h
PW0FG
D2h
PW1FG
D3h
PW2FG
D4h
PW3FG
D5h
PWMADR
ADRS
–
–
–
–
–
PWE1
PWE0
D6h
SCON1
SM0/FE_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
D8h
SBUF1
D9h
PWM0
DCh
PWM1
DDh
PWM2
DEh
PWM3
DFh
091698 10/47
DS87C550
SPECIAL FUNCTION REGISTER LOCATION: Table 2 cont’d
REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
AD–
DRESS
ACC
E0h
PW01CS
PW0S2
PW0S1
PW0S0
PW0EN
PW1S2
PW1S1
PW1S0
PW1EN
E1h
PW23CS
PW2S2
PW2S1
PW2S0
PW2EN
PW3S2
PW3S1
PW3S0
PW3EN
E2h
PW01CON
PW0F
PW0DC
PW0OE
PW0T/C
PW1F
PW1DC
PW1OE
PW1T/C
E3h
PW23CON
PW2F
PW2DC
PW2OE
PW2T/C
PW3F
PW3DC
PW3OE
PW3T/C
E4h
RLOADL
E6h
RLOADH
E7h
EIE
ET2
ECM2
ECM1
ECM0
T2SEL
TF2S
CTCON
CT3
TF2BS
–
TF2B
CT3
CT2
CT2
EX5/EC3
EX4/EC2
EX3/EC1
EX2/EC0
E8h
–
–
T2P1
T2P0
EAh
CT1
CT1
CT0
CT0
EBh
TL2
ECh
TH2
EDh
SETR
TGFF1
TGFF0
CMS5
CMS4
CMS3
CMS2
CMS1
CMS0
EEh
RSTR
CMT1
CMT0
CMR5
CMR4
CMR3
CMR2
CMR1
CMR0
EFh
B
F0h
PORT6
STADC
–
PWMC1
PWMC0
PWMO3
PWMO2
PWMO1
PWMO0
F1h
EIP
PT2
PCM2
PCM1
PCM0
PX5/PC3
PX4/PC2
PX3/PC1
PX2/PC0
F8h
WDCON
SMOD_1
POR
EPFI
PFI
WDIF
WTRF
EWT
RWT
FFh
MEMORY RESOURCES
PROGRAM MEMORY
As is convention within the 8051 architecture, the
DS87C550 uses three memory areas. The total
memory configuration of the DS87C550 is 8K bytes of
EPROM, 1K byte of data SRAM and 256 bytes of
scratchpad or direct RAM. The 1K byte of data space
SRAM is read/write accessible and is memory mapped.
This on–chip SRAM is reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register mapped RAM and is
identical to the RAM found on the 80C52. There is no
conflict or overlap among the 256 bytes and the 1K as
they use different addressing modes and separate
instructions.
On–chip ROM begins at address 0000h and is contiguous through 1FFFh (8K). Exceeding the maximum
address of on–chip ROM will cause the DS87C550 to
access off–chip memory. However, the maximum on–
chip decoded address is selectable by software using
the ROMSIZE feature. Software can cause the
DS87C550 to behave like a device with less on–chip
memory. This is beneficial when overlapping external
memory, such as Flash, is used.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CLCC package
should be covered without regard to the programmed/
unprogrammed state of the EPROM. Otherwise, the
device may not meet the AC and DC parameters listed
in the datasheet.
With the ROMSIZE feature the maximum on–chip
memory size is dynamically variable. Thus a portion of
on–chip memory can be removed from the memory map
to access off–chip memory, then restored to access on–
chip memory. In fact, all of the on–chip memory can be
removed from the memory map allowing the full 64K
memory space to be addressed as off–chip memory.
ROM addresses that are larger than the selected maximum are automatically fetched from outside the part via
Ports 0 & 2. A depiction of the ROM memory map is
shown in Figure 2.
091698 11/47
DS87C550
The ROMSIZE register is used to select the maximum
on–chip decoded address for ROM. Bits RMS2, RMS1,
RMS0 (ROMSIZE2:0) have the following effect.
RMS2
0
0
0
0
1
1
1
1
RMS1
0
0
1
1
0
0
1
1
RMS0
0
1
0
1
0
1
0
1
Maximum on–chip
ROM Address
0K
1K (0h – 03FFh)
2K (0h – 07FFh)
4K (0h – 0FFFh)
8K (0h – 1FFFh) default
invalid – reserved
Invalid – reserved
Invalid – reserved
The reset default condition is a maximum on–chip ROM
address of 8K bytes. Thus no action is required if this
feature is not used. Therefore when accessing external
program memory, the first 8K bytes would be inaccessible. To select a smaller effective ROM size, software
must alter bits RMS2–RMS0. Altering these bits
requires a Timed Access procedure as explained below.
The ROMSIZE register should be manipulated from a
safe area in the program memory map. This is a program memory address that will not be affected by the
change. For example, do not select a maximum ROM
size of 4K from an internal ROM address of 5K. This
would cause the current address to switch from internal
to external and potentially cause invalid operation. Similarly, do not instantly switch from external to internal
memory. For example, do not select a maximum ROM
address of 8K from an external ROM address of 7K (if
ROMSIZE is set for 4K or less).
Off–chip memory is accessed using the multiplexed
address/data bus on P0 and the MSB address on P2.
While serving as a memory bus, these pins are not available as I/O ports. This convention follows the standard
8051 method of expanding on–chip memory. Off–chip
ROM access also occurs if the EA pin is logic 0. EA overrides all bit settings. The PSEN signal will go active (low)
to serve as a chip enable or output enable when Ports 0
& 2 fetch from external ROM.
ROM MEMORY MAP Figure 2
ROM SIZE ADJUSTABLE
DEFAULT = 8K BYTES
ROM SIZE IGNORED
/EA = 1
64K
FFFFh
/EA = 0
FFFFh
64K
OFF CHIP
OFF CHIP
8k
1FFFh
USER
SELECTABLE
ON CHIP
0000h
0000h
DATA MEMORY
Unlike many 8051 derivatives, the DS87C550 contains
additional on–chip data memory. In addition to the standard 256 bytes of data RAM accessed by direct instructions, the DS87C550 contains another 1K byte of data
091698 12/47
memory that is accessed using the MOVX instruction.
Although physically on–chip, software treats this area
as though it was located off–chip. The 1K byte of SRAM
DS87C550
is permanently located from address 0000h to 03FFh
(when enabled).
Access to the on–chip data RAM is optional under software control. When enabled by software, the data
SRAM is between 0000h and 03FFh. Any MOVX
instruction that uses this area will go to the on–chip RAM
while enabled. MOVX addresses greater than 1K automatically go to external memory through Ports 0 & 2.
When disabled, the 1K memory area is transparent to
the system memory map. Any MOVX directed to the
space between 0000h and FFFFh goes to the expanded
bus on Ports 0 & 2. This also is the default condition.
This default allows the DS87C550 to drop into an existing system that uses these addresses for other hardware and still have full compatibility.
The on–chip data area is software selectable using two
bits in the Power Management Register (DME1,
DME0). This selection is dynamically programmable.
Thus access to the on–chip area becomes transparent
to reach off–chip devices at the same addresses. These
bits have the following operation:
DATA MEMORY ACCESS CONTROL Table 3
DME1
DME0
DATA MEMORY ADDRESS
0
0
0000h – FFFFh
External Data Memory
MEMORY FUNCTION
0
1
0000h – 03FFh
0400h – FFFFh
Internal SRAM Data Memory
External Data Memory
1
0
Reserved
1
1
0000h – 03FFh
0400h – FFFBh
FFFCh
FFFDh – FFFFh
* Default condition
Reserved
Internal SRAM Data Memory
Reserved – no external access
Read access to the status of lock bits
Reserved
Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2–0 reflect the programmed status of the security lock
bits LB2–LB0. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed.
These status bits allow software to verify that the part has been locked before running if desired. The bits are read only.
STRETCH MEMORY CYCLE
The DS87C550 allows software to adjust the speed of
off–chip data memory and/or peripheral access by
adjusting the number of machine cycles it takes to
execute a MOVX instruction. The micro is capable of
performing the MOVX in as little as two machine cycles.
The on–chip SRAM uses this speed and any MOVX
instruction directed internally always uses two cycles.
However, the time for the instruction execution can be
stretched for slower interface to external devices. This
allows access to both fast memory and slow memory or
peripherals with no glue logic. Even in high–speed systems, it may not be necessary or desirable to perform
off–chip data memory access at full speed. In addition,
there are a variety of memory mapped peripherals such
as LCDs or UART’s that are slow and require more time
to access.
The Stretch MOVX function is controlled by the
MD2–MD0 SFR bits in the Clock Control Register
(CKCON.2–0) as described below. They allow the user
to select a Stretch value between zero and seven. A
Stretch of zero will result in a two–machine cycle MOVX
instruction. A Stretch of seven will result in a MOVX of
twelve machine cycles. Software can dynamically
change the stretch value depending on the particular
memory or peripheral being accessed. The default
stretch of one allows the use of commonly available
SRAMs without dramatically lengthening the memory
access times.
Note that the STRETCH MOVX function is slightly different in the DS87C550 than in earlier members of the
high–speed microcontroller family. In all members of
this family (including the DS87C550), increasing the
stretch value from 0 to 1 causes setup and hold times to
be increased by 1 crystal clock each. In older members
of the family, there is no further change in setup and hold
times regardless of the number of stretch cycles
selected. In the DS87C550 however, when a stretch
value of 4 or above is selected, the timing of the interface
changes dramatically to allow for very slow peripherals.
First, the ALE signal is increased by 1 machine cycle.
This increases the address setup time into the peripheral by this amount. Next, the address is held on the bus
for one additional machine cycle, increasing the
address hold time by this amount. The Read or Write
signal is then increased by a machine cycle. Finally, the
091698 13/47
DS87C550
data is held on the bus (for a write cycle) one additional
machine cycle, thereby increasing the data hold time by
this amount. For every Stretch value greater than 4, the
setup and hold times remain constant, and only the
width of the read or write signal is increased.
On reset, the Stretch value will default to a one resulting
in a three cycle MOVX for any external access. Therefore, the default off–chip RAM access is not at full
speed. This is a convenience to existing designs that
may not have fast RAM in place. Internal SRAM access
is always at full speed regardless of the Stretch setting.
When maximum speed is desired, software should
select a Stretch value of zero. When using very slow
RAM or peripherals, the application software can select
a larger Stretch value. Note that this affects data
memory accesses only and that there is no way to slow
the accesses to program memory other than to use a
slower crystal (or external clock).
The specific timing of the variable speed Stretch MOVX
is provided in the Electrical Specifications section of this
data sheet. Table 4 shows the resulting MOVX instruction timing and the read or write strobe widths for each
Stretch value.
DATA MEMORY CYCLE STRETCH VALUES Table 4
CKCON.2–0
M2 M1 M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MOVX MACHINE
CYCLES
2 (forced internal)
3 (default external)
4
5
9
10
11
12
DUAL DATA POINTER WITH INC/DEC
The DS87C550 contains several new, unique features
that are associated with the Data Pointer register. In the
original 8051 architecture, the DPTR was a 16–bit value
that was used to address off–chip data RAM or peripherals. To improve the efficiency of data moves, the
DS87C550 contains two Data Pointer registers (DPTR0
and DPTR1). By loading one DPTR with the source
address and the other with the destination address ,
block data moves can be made much more efficient.
Since DPTR0 is located at the same address as the
single DPTR in the original 8051 architecture, code written for the original architecture will operate normally on
the DS87C550 with no modification necessary.
The second data pointer, DPTR1 is located at the next
two register locations (up from DPTR0), and is selected
using the data pointer select bit SEL (DPS.0). If SEL = 0,
then DPtR0 is the active data pointer. Conversely, if
SEL = 1, then DPTR1 is the active data pointer. Any
instruction that reference the DPTR (ex. MOVX A, @
DPTR) refers to the active data pointer as determined
by the Sel bit. Since the bit adjacent to SEL in the DPS
register is not used, the fastest means of changing the
SEL (and thereby changing the active data pointer) is
091698 14/47
RD OR WR STROBE WIDTH
IN MACHINE CYCLES
0.5
1
2
3
4
5
6
7
with an INC instruction. Each INC DPS Instruction will
toggle the active data pointer.
Unlike the standard 8051, the DS87C550 has the ability
to decrement as well as increment the data pointers
without additional instructions. When the INC DPTR
instruction is executed, the active DPTR is incremented
or decremented according to the ID1, ID0 (DPS.7–6),
and SEL (DPS.0) bits as shown. The inactive DPTR is
not affected.
ID1
ID0
SEL
X
0
0
INCREMENT DPTR0
X
1
0
DECREMENT DPTR0
0
X
1
INCREMENT DPTR1
1
X
1
DECREMENT DPTR1
RESULT OF INC DPTR
Another useful feature of the device is its ability to automatically switch the active data pointer after a DPTR–
based instruction is executed. This feature can greatly
reduce the software overhead associated with data
memory block moves, which toggle between the source
DS87C550
and destination registers. When the Toggle Select bit
(TSL;DPS.5) is set to 1, the SEL bit (DPS.0) is automatically toggled every time one of the following DPTR
related instructions are executed.
• INC DPTR
• MOV DPTR, #data16
• MOVC A, @A+DPTR
• MOVX A, @DPTR
• MOVX @DPTR, A
As a brief example, if TSL is set to 1, then both data
pointers can be updated with the two instruction series
shown. Assume that SEL to 1. The second instruction
increments DPTR1 and toggles SEL back to 0.
INC DPTR
INC DPTR
With TSL set, the first increment instruction increments
the active data pointer, and then causes the SEL bit to
toggle making the other DPTR active. The second increment instruction increments the newly active data
pointer and then toggles SEL to make the original data
pointer active again.
CLOCK CONTROL and POWER
MANAGEMENT
The DS87C550 includes a number of unique features
that allow flexibility in selecting system clock sources
and operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a
clock multiplier is included in the processors clock circuit. Also, along with the Idle and power down (Stop)
modes of the standard 80C52, the DS87C550 provides
a new Power Management Mode. This mode allows the
processor to continue instruction execution at a very low
speed to significantly reduce power consumption
(below even idle mode). The DS87C550 also features
several enhancements to Stop mode that make this
extremely low power mode more useful. Each of these
features is discussed in detail below.
SYSTEM CLOCK CONTROL
As mentioned previously, the DS87C550 contains special clock control circuitry that simultaneously provides
maximum timing flexibility and maximum availability
and economy in crystal selection. There are two basic
functions to this circuitry: a frequency multiplier and a
clock divider. By including a frequency multiplier circuit,
full speed operation of the processor may be achieved
with a lower frequency crystal. This allows the user the
ability to choose a more cost effective and easily obtainable crystal than would be possible otherwise.
The logical operation of the system clock divide control
function is shown in Figure 3. The clock signal from the
crystal oscillator (or external clock source) is provided to
the frequency multiplier module, to a divide by 256 module, and to a 3–to–1 multiplexer. The output of this multiplexer is considered the system clock. The system
clock provides the time base for timers and internal
peripherals, and feeds the CPU State Clock Generation
circuitry. This circuitry divides the system clock by four,
and it is the four phases of this clock that make up the
instruction execution clock. The four phases of a single
instruction execution clock are also called a single
machine cycle clock. Instructions in the DS87C550 all
use the machine cycle as the fundamental unit of measure and are executed in from one to five of these
machine cycles. It is important to note the distinction
between the system clock and the machine cycle clock
as they are often confused, creating errors in timing calculations. In performing timing calculations, it is important to remember that all timers and internal peripherals
operate off of some version of the system clock while the
instruction execution engine always operates off of the
machine cycle clock.
When CD1 and CD0 (PMR.7–6) are both cleared to a
logic 0, the multiplexer selects the frequency multiplier
output. The frequency multiplier can supply a clock that
is 2 times or 4 times the frequency of the incoming signal. If the four times multiplier is selected by setting the
4X/2X bit (PMR.3) to 1, for example, the incoming signal
is multiplied by four. This 4X clock is then passed
through the multiplexer, and then output to the CPU
State Clock Generation circuits. These CPU State
Clock Generation circuits always divide the incoming
clock by four to arrive at the four states (called a
machine cycle) necessary for correct processor operation. In this example, since the clock multiplier multiplies
by four and the CPU State Clock Generation circuit
divides by four, the apparent instruction execution
speed is one external (or crystal oscillator) clock per
instruction. If the 4X/2X bit is set to 0, then the apparent
instruction execution speed is 2 clocks per instruction.
It is important to note that the clock multiplier function
does not increase the maximum clock (system clock)
rate of the device. The DS87C550 operates at a maximum system clock rate of 33 MHz. Therefore, the maximum crystal frequency is 8.25 MHz when a clock multi-
091698 15/47
DS87C550
plier of 4 is used, and is 16.5 MHz when a clock multiplier
of 2 is used. The purpose of the clock multiplier is to simplify crystal selection when maximum processor operation is desired. Specifically, a 8.25 MHz fundamental
mode, AT cut, parallel resonant crystal is much easier to
obtain than the same crystal at 33 MHz. Most crystals in
that frequency range tend to be third overtone type.
As illustrated in Figure 3, the programmable Clock
Divide control bits CD1–CD0 (PMR.7–6) provide the
processor with the ability to adapt to different crystal
(and external clock) frequencies and also to allow
extreme division of the incoming clock providing lower
power operation when desired. The effect of these bits
is shown in Table 5.
CD1:CD0 OPERATION Table 5
CD1
CD0
Instruction Execution
0
0
Frequency multiplier (1 or 2 clocks
per machine cycle
0
1
Reserved
1
0
Clock divided by 4 (4 clocks per
machine cycle) Default
1
1
Clock divided by 1024 (1024 clocks
per machine cycle)
Besides the ability to use a multiplied clock signal, the
normal mode of operation, i.e. the reset default condition (CD1 = 1, CD0 = 0) passes the incoming crystal or
external oscillator clock signal straight through as the
system clock. Because of the CPU State Clock generation circuitry’s normal divide by 4 function, the default
execution speed of the DS87C550’s basic instruction is
one–fourth the clock frequency.
The selection of instruction cycle rate takes effect after a
delay of one instruction cycle. Note that the clock divider
choice applies to all functions including timers. Since
091698 16/47
baud rates are altered, it may be difficult to conduct
serial communication while in divide by 1024 mode.
This is simplified by the use of switchback mode
(described later) included on the DS87C550.
CLOCK SWITCHING RESTRICTIONS
To ensure clean “glitch–free” switching of the system
clock and to ensure that all clocks are running and
stable before they are used, there are minor restrictions
on accessing the clock selection bits CD1:0 and the
4X/2X bit.
One restriction is that any change in the CD1 and CD0
bits from a condition other than a 1 0 state (i.e., clock
divided by four mode) must pass through the divide by
four state before proceeding to the desired state. As a
specific example, if the clock divisor bits are set to use
the frequency multiplier in 4X mode, no other clock setting is possible until after the CD1:0 bits are set to divide
by 4 mode. After setting clock divided by 4 mode, then
clock divided by 1024 can be selected by setting CD1
and CD0 to “11b”. Any attempt to change these bits to
an disallowed state will be ignored by the hardware.
There are also some minor restrictions when changing
from one clock multiplier to another. Changing the clock
multiplier can only be performed when the Crystal Multiplier Enable bit CTM (PMR.4) is set to 0. This bit disables the clock multiplication function. However, the
CTM bit can only be changed when CD1 and CD0 are
set to divide by 4 mode (i.e., “10b”) and the ring mode
(RNGMD = RCON.2) bit is 0 (discussed later). Changing the clock multiplication factor also requires that the
new frequency be stable prior to effecting the change.
The SFR bit CKRDY (RCON.3) indicates the state of the
stabilization time–out. Setting the CTM bit to a 0 from a 1
disables the clock multiplier function, automatically
clears the CKRDY bit, and starts the stabilization time–
out.
DS87C550
SYSTEM CLOCK CONTROL Figure 3
SYSTEM
CLOCK
FROM
CRYSTAL
OSCILLATOR
OR
EXTERNAL
CLOCK SOURCE
DIVIDE
BY 256
MUX
FREQUENCY
MULTIPLIER
MACHINE CYCLE
CLOCK
CPU
STATE
GENERATION
(divide by 4)
CTM
(ENABLE
2X4X
During the stabilization period, CKRDY will remain low,
and software will be unable to set the CD1:0 bits to
select the frequency multiplier. After the stabilization
delay, CKRDY will be set to a 1 by hardware. Note that
this bit cannot be set to 1 by software. After hardware
sets CKRDY bit, then the CD1:0 bits can be set to use
the clock multiplier function. However before changing
CD1:0, the 4X/2X bit must be set to the desired state.
Following this, the CTM bit must be set to 1 to enable the
crystal multiplier. Finally the CD1:0 bits may be set to
select the crystal multiplier function. By following this
procedure, the processor is guaranteed to receive a
stable, glitch–free clock.
OSCILLATOR FAIL DETECT
The DS87C550 contains a unique safety mechanism
called an on–chip Oscillator Fail Detect circuit. When
enabled, this circuit causes the processor to be reset if
the oscillator frequency falls below TBD kHz. The processor is held in reset until the oscillator frequency rises
above TBD kHz. In operation, this circuit can provide a
backup for the Watchdog timer. Normally, the watchdog
timer is initialized so that it will time–out and will cause a
processor reset in the event that the processor loses
control. This works perfectly as long as there is a clock
from the crystal or external oscillator, but if this clock
fails, there is the potential for the processor to fail in an
uncontrolled and possibly undesirable state. With the
use of the oscillator fail detect circuit, the processor will
be forced to a known state (i.e., reset) even if the oscillator stops.
The oscillator fail detect circuitry is enabled by software
setting the enable bit OFDE (PCON.4) to a 1. Please
note that software must use a “Timed Access” procedure (described later) to write to this bit. There is an
CD1, CD0
oscillator fail detect flag, OFDF (PCON.5), that is set to a
1 by the hardware when it detects an oscillator failure.
The processor will be forced into a reset state when this
occurs if enabled by OFDE. The oscillator fail detect
flag can only be cleared to a 0 by a power–up reset or by
software. It should be noted that the oscillator fail detect
circuitry is not disabled by entering Stop mode. There
fore, the user must ensure that this feature is disabled
before entering Stop mode.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of
reduced internal clock speeds that allow the CPU to run
software but to use substantially less power. Normally,
during default operation, the DS87C550 uses 4 clocks
per machine cycle. Thus the instruction cycle (machine
cycle clock) rate is Clock/4. At 33 MHz crystal speed,
the instruction cycle speed is 8.25 MHz. In PMM, the
microcontroller operates, but from an internally divided
version of the clock source. This creates a lower power
state without external components. As shown in Figure
3, the system clock may be selected to use the crystal
(or external oscillator) frequency divided by 256. This
produces a machine cycle that consists of the crystal
frequency divided by 1024, which is considered Power
Management Mode (PMM). With the processor executing instructions at this much lower rate, a significant
amount of power is saved.
Software is the only mechanism to invoke the PMM.
Table 6 illustrates the instruction cycle rate in PMM for
several common crystal frequencies. Since power consumption is a direct function of operating speed, PMM
runs very slowly and provides the lowest power consumption without stopping the CPU. This is illustrated in
Table 7.
091698 17/47
DS87C550
MACHINE CYCLE RATE Table 6
Crystal
Speed
Full Operation
PMM
(4 clocks per
(1024 clocks per
machine cycle) machine cycle)
11.0592 MHz 2.765 MHz
10.8 kHz
16 MHz
4.0 MHz
15.6 kHz
25 MHz
6.25 MHz
24.4 kHz
33 MHz
8.25 MHz
32.2 kHz
OPERATING CURRENT ESTIMATES IN PMM
Table 7
Crystal
Speed
Full Operation
PMM
(4 clocks per
(1024 clocks per
machine cycle) machine cycle)
11.0592 MHz 13.1 mA
4.8 mA
16 MHz
17.2 mA
5.6 mA
25 MHz
25.7 mA
7.0 mA
33 MHz
32.8 mA
8.2 mA
Note that PMM provides a lower power condition than
Idle mode. This is because in Idle, all clocked functions
such as timers run at a rate of crystal divided by 4. Since
wake–up from PMM is as fast as or faster than from Idle
and PMM allows the CPU to continue to execute instructions (even if doing NOPs), there is little reason to use
Idle in new designs.
Switchback
One of the other unique features included on the
DS87C550 is Switchback. Simply, Switchback when
enabled will allow serial ports and interrupts to automatically switch back from divide by 1024 (PMM) to divide by
four (standard speed operation). This feature makes it
very convenient to use the Power Management Mode in
real time applications. Of course to return to a divide by
four clock rate from divide by 1024 PMM, software can
simply select the CD1 & CD0 clock control bits to the
four clocks per cycle state. However, the DS87C550
provides hardware alternatives for automatic Switchback to standard speed operation.
The Switchback feature is enabled by setting the SFR
bit SWB (PMR.5) to a 1. Once it is enabled, and when
PMM is selected, there are two possible events that can
cause an automatic switchback to divide by four mode.
First, if an interrupt occurs and is set so that it will be
acknowledged, this event will cause the system clock to
091698 18/47
revert from PMM to divide by four mode. For example, if
INT0 is enabled then Switchback will occur on INT0.
However, if INT0 is not enabled, then activity on INT0
will not cause switchback to occur.
A Switchback can also occur when an enabled UART
detects the start bit indicating the beginning of an incoming serial character or when the SBUF register is loaded
initiating a serial transmission. Note that a serial character’s start bit does not generate an interrupt. This occurs
only on reception of a complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial
reception or transmission. So with Switchback enabled
and a serial port enabled, the automatic switch to normal speed operation occurs automatically in time to
receive or transmit a complete serial character as if
nothing special had happened.
Once Switchback causes the processor to make the
transition back to divide by four mode, software must
modify SFR bits CD1 & CD0 to re–enter Power Management Mode. However, if a serial port is in the process of
transmitting or receiving a character, then this change
back to PMM will not be allowed as the hardware prevents a write to CD1 & CD0 during any serial port
activity.
Since the reception of a serial start bit or an interrupt
priority lockout is normally undetectable by software in
an 8051, the Status register features several new flags
that are useful. These are described below.
Status
Information in the Status register assists decisions
about switching into PMM. This register contains
information about the level of active interrupts and the
activity on the serial ports.
The DS87C550 supports three levels of interrupt priority. These levels are Power–fail, High, and Low. Status
bits STAT.7–5 indicate the service status of each level. If
PIP (Power–fail Interrupt Priority; STATUS.7) is a 1,
then the processor is servicing this level. If either HIP
(High Interrupt Priority; STATUS.6) or LIP (Low Interrupt
Priority; STATUS.5) is high, then the corresponding
level is in service.
Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a
higher level is in service. Check the current priority ser-
DS87C550
vice level before entering PMM. If the current service
level locks out a desired Switchback source, then it
would be advisable to wait until this condition clears
before entering PMM.
Alternately, software can prevent an undesired exit from
PMM by entering a low priority interrupt service level
before entering PMM. This will prevent other low priority
interrupts from causing a Switchback.
Status also contains information about the state of the
serial ports. Serial Port Zero Receive Activity (SPRA0;
STATUS.0) indicates a serial word is being received on
Serial Port 0 when this bit is set to a 1. Serial Port Zero
Transmit Activity (SPTA0; STATUS.1) indicates that the
serial port is still shifting out a serial transmission. STATUS.2 (SPRA1) and STATUS.3 (SPTA1) provide the
same information for Serial Port 1, respectively. While
one of these bits is set, hardware prohibits software
from entering PMM (CD1 & CD0 are write protected)
since this would corrupt the corresponding serial transmissions.
IDLE MODE
Setting the LSB of the Power Control register (PCON.0)
invokes the Idle mode. Idle will leave internal clocks,
serial ports and timers running. Power consumption
drops because memory is not being accessed and
instructions are not being executed. Since clocks are
running, the Idle power consumption is a function of
crystal frequency. It should be approximately 1/2 of the
operational power at a given frequency. The CPU can
exit the Idle state with any interrupt or a reset. Idle is
available for backward software compatibility. However,
due to improvements over the original architecture, the
processor’s power consumption can be reduced to
below Idle levels by invoking Power Management Mode
(PMM) and running NOPs.
STOP MODE
Setting bit 1 of the Power Control register (PCON.1)
invokes the Stop mode. Stop mode is the lowest power
state (besides power off) since it turns off all internal
clocking. The ICC of a standard Stop mode is approximately 1 uA (but is specified in the Electrical Specifications). All processor operation ceases at the end of the
instruction that sets PCON.1. The CPU can exit Stop
mode from an external interrupt or a reset condition.
Internally generated interrupts (timer, serial port, etc.)
are not useful since they require clocking activity.
BAND–GAP SELECT
The DS87C550 provides two enhancements to the Stop
mode. As described below, the DS87C550 provides a
band–gap reference to determine Power–fail Interrupt
and Reset thresholds. The default state is that the
band–gap reference is off while in Stop mode. This
mode allows the extremely low power state mentioned
above. A user can optionally choose to have the band–
gap enabled during Stop mode. With the band–gap reference enabled, PFI and Power–fail reset are functional
and are valid means for leaving Stop mode. This allows
software to detect and compensate for a brownout or
power supply sag, even when in Stop mode.
In Stop mode with the band–gap enabled, ICC will be
approximately 100 uA compared with 1 uA with the
band–gap off. If a user does not require a Power–fail
Reset or Interrupt while in Stop mode, the band–gap
can remain disabled. Only the most power sensitive
applications should turn off the band–gap, as this
results in an uncontrolled power down condition.
The control of the band–gap reference is located in the
Ring Oscillator Control Register (RCON). Setting BGS
(RCON.0) to a 1 will keep the band–gap reference
enabled during Stop mode. The default or reset condition is with the bit at a logic 0. This results in the band–
gap being off during Stop mode. Note that this bit has no
control of the reference during full power, PMM, or Idle
modes.
RING OSCILLATOR
The second enhancement to Stop mode on the
DS87C550 allows an additional power saving option
while also making Stop easier to use. This is the ability
to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this feature. This ring can
be a clock source when exiting Stop mode in response
to an interrupt. The benefit of the ring oscillator is as follows.
Entering Stop mode turns off the crystal oscillator and all
internal clocks to save power. When exiting Stop mode,
the external crystal may require up to 10 ms to begin
oscillating again. The DS87C550 can eliminate that
delay through the use of the internal ring oscillator,
resuming operation in less than 100 ns when exiting
Stop mode. If a user selects the ring to provide the
start–up clock and the processor remains running,
hardware will automatically switch to the crystal once a
091698 19/47
DS87C550
power–on reset interval (65536 crystal clocks) has
expired.
The ring oscillator runs at approximately 4 MHz but will
not be a precise value. Do not conduct real–time precision operations (including serial communication) during
this ring period. The default state is to exit Stop mode
without using the ring oscillator, so action to enable the
ring must be taken before entering stop mode.
The Ring Select (RGSL) bit in the RCON register
(RCON.1) controls this function. When RGSL = 1, the
CPU will use the ring oscillator to exit Stop mode quickly.
As mentioned above, the processor will automatically
switch from the ring to the crystal after a delay of 65,536
crystal clocks. For a 3.57 MHz crystal, this is approximately 18 ms. The processor sets a flag called Ring
Mode (RGMD = RCON.2) that tells software that the
ring is being used. The bit will be a logic 1 when the ring
is in use.
TIMED ACCESS PROTECTION
Selected SFR bits are critical to operation, making it
desirable to protect them against an accidental write
operation. The Timed Access procedure prevents an
errant processor from accidentally altering a bit that
would seriously affect processor operation. The Timed
Access procedure requires that the write of a protected
bit be preceded by the following instructions :
MOV
MOV
0C7h, #0AAh
0C7h, #55h
By writing an AAh followed by a 55h to the Timed Access
register (location C7h), the hardware opens a three
cycle window that allows software to modify one of the
protected bits. If the instruction that seeks to modify the
protected bit is not immediately preceded by these
instructions, the write will not take effect. The protected
bits are :
WDCON.6
POR
Power–On Reset Flag
WDCON.3
WDIF
Watchdog Interrupt Flag
WDCON.1
EWT
Watchdog Reset Enable
WDCON.0
RWT
Reset Watchdog Timer
RCON.0
BGS
Band–Gap Select
091698 20/47
ROMSIZE.2
RMS2
Program Memory Select
Bit 2
ROMSIZE.1
RMS1
Program Memory Select
Bit 1
ROMSIZE.0
RMS0
Program Memory Select
Bit 0
EMI REDUCTION
One of the major contributors to radiated noise in an
8051 based system is the toggling of ALE. The
DS87C550 allows software to disable ALE when not
used by setting the ALEOFF (PMR.2) bit to a 1. When
ALEOFF = 1, ALE will still toggle during an off–chip
MOVX. However, ALE will remain inactive when performing on–chip memory access. The default state is
ALEOFF = 0 so ALE normally toggles at a frequency of
XTAL/4.
PERIPHERAL OVERVIEW
The DS87C550 provides several of the most commonly
needed peripheral functions in microcomputer–based
systems. New functions include a second serial port,
power–fail reset, power–fail interrupt flag, and a programmable watchdog timer. In addition, the DS87C550
contains an analog–to–digital converter and four channels of pulse width modulation for industrial control and
measurement applications. Each of these peripherals is
described below. More details are available in the High
Speed Micro Data Book (or its most recent addendum).
SERIAL PORTS
The DS87C550 provides a serial port (UART) that is
identical to the 80C52. In addition it includes a second
hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1)
and P1.3 (TXD1). It has duplicate control functions
included in new SFR locations.
Both ports can operate simultaneously but can be at different baud rates or even in different modes. The
second serial port has similar control registers (SCON1,
SBUF1) to the original. The new serial port can only use
Timer 1 for timer generated baud rates.
Control for serial port 0 is provided by the SCON0 register while its I/O buffer is SBUF0. The registers SCON1
and SBUF1 provide the same functions for the second
DS87C550
serial port. A full description of the use and operation of
both serial ports may be found in the “High–Speed
Microcontroller Data Book”.
ANALOG TO DIGITAL CONVERTER
external pin STADC (P6.7). If continuous mode is
selected (CONT/SS = 1), then the first conversion is initiated as described above, but another conversion will
be automatically started at the completion of the previous conversion.
The DS87C550 contains a 10–bit successive approximation analog–to–digital converter. This converter provides eight multiplexed channels of analog input, and
allows the user to select either an external or internal
precision voltage reference to be used for the conversion process. The A/D converter provides true 9–bit
accuracy with a total error of less than ±2 LSBs.
Once initiated, the conversion process requires 16 A/D
clock periods (TACLK) to complete. Because of the
dynamic nature of the converter, the A/D clock period
can be no less that 1 us and no more than 6.25 us. This
requirement is expressed as follows:
The A/D Converter may be disabled to conserve power
by writing a 0 to the SFR ADON bit (ADCON1.1). At
reset, this is the default condition, and the user must
write a 1 to this bit prior to using the A/D Converter.
Therefore any single conversion time can range from 16
us minimum to 100 us maximum, depending on the
selected A/D clock frequency.
A/D CONVERTER INPUT
The A/D Converter of the DS87C550 provides eight
channels of analog input on device pins ADC7 through
ADC0 (P5.7–P5.0). The signals on these pins are input
into an analog multiplexer. The magnitude (and polarity)
of these signals is limited by the reference voltage used
by the converter (see DC Specifications section). This
reference voltage may be selected to be either an internal band–gap voltage (VBG) or an external reference
(Avref+, Avref–). This selection is made by writing a 0
(uses internal reference VBG) or writing a 1 (uses external reference AVref±) to the ADRS bit (PWMADR.7).
The default reset condition is for the internal reference
to be selected.
Selecting a single analog signal for conversion is
achieved by software writing the desired channel number (0 through 7) into SFR bits MUX2 through MUX0 bits
of the A/D Control register 2 (ADCON2.6–4). The single
output of the multiplexer is then provided to a sample
and hold circuit that maintains a steady signal during the
conversion process.
A/D CONVERSION PROCESS
The A/D conversion process can be configured for one–
shot or continuous mode operation. For one–shot
operation, the SFR bit CONT/SS (ADCON1.5) must be
a 0. The conversion process is then initiated by software
writing a 1 to the STRT/BSY SFR bit (ADCON1.7) if the
ADEX (ADCON1.4) bit is a 0. If the ADEX bit is a 1, then
the conversion is initiated by an active low signal on the
1.0 us <= TACLK <= 6.25 us
The A/D clock frequency is a function of the processor’s
machine cycle clock and the A/D clock’s prescaler setting as shown by the following equation.
TACLK = TMCLK * (N+1)
where N is the prescaler setting in APS3:0
The processor’s machine cycle clock period (TMCLK) is
normally the external crystal (or oscillator) frequency
multiplied by 4 (but can be affected by the CD1, CD0,
and 4X/2X bits). The A/D clock period must be set by the
user to ensure that it falls within the minimum and maximum values specified above. As an example, assume
the processor’s crystal frequency is 33 MHz and that the
processor is running in a standard divide by, 4 mode.
This means that the period of the processors machine
cycle clock, i.e., TMCLK ,will be (1/33 MHz)*4 or 121.2
ns. If it is assumed that the application requires the fastest possible conversion time then the desired TACLK is
1.0 us. The necessary prescale value can then be calculated as:
N = (TACLK/TMCLK)–1
Therefore for this example, N = 7.25. Since N must be
an integer, the value of N must be 8 (rounded up to the
next integer). This results in a conversion clock TACLK =
1.091 us.
The prescaler value must be stored in SFR bits APS3
through APS0 (ADCON2.3–0) to achieve the proper
A/D clock. These bits default to 0 on a processor reset,
091698 21/47
DS87C550
so they must be set as desired by the processor’s initialization software.
range. Otherwise WCM is cleared. The state of the
WCM bit is expressed by the following equation:
WCM = WCIO ⊕ (WINHI ≤ ADMSB) ⊕ (WINLO ≤ ADMSB)
A/D Output
There are two SFR locations that contain the result of
the A/D conversion process. They are ADMSB (most
significant byte) and ADLSB (least significant byte). The
ADLSB byte always contains the eight least significant
bits of the 10–bit result. The ADMSB can be configured
in two different ways through the use of the SFR bit
OUTCF (ADCON2.7). If OUTCF is a 0, then ADMSB
contains the eight most significant bits of the 10–bit conversion (i.e., bits 9–2). If OUTCF is a 0, then ADMSB
contains A/D output bits 9–8 (right justified). The upper 6
bits of the register are set to zero in this case.
The value stored in the output registers is given by the
following equation:
1024 x ((Vin–Avref–)/(Avref+ – Avref–))
This equation shows that the A/D conversion result is a
10–bit binary number that represents what fraction of
the available reference voltage the input signal is. As
you can see with a reference voltage of 2.5 volts, the
output has a resolution of 2.44 millivolts. This shows that
the reference voltage must be very well regulated to
ensure satisfactory performance. It should be noted that
the output of the A/D conversion process will be
“0000000000” for voltages from Avref– to (Avref– +1/2
LSB). In addition, “1111111111” will be output for voltages from (Avref+ – 3/2 LSB) to Avref+.
The DS87C550 offers a unique feature that allows the
result of an A/D conversion to be compared with two
user–defined values stored in the WINHI and WINLO
registers. The results of this comparison will set or clear
the WCM (ADCON 1.2) bit, and this bit can be used as a
qualifier to the A/D interrupt. This comparison is built
into hardware so that this feature is performed without
any burden on the software, and A/D results that are not
of particular interest to the application can be ignored.
Special function registers WINHI and WINLO are
loaded by application software with 8–bit numbers that
are compared with the eight MSBs of the A/D result.
These user–defined numbers form a range of values,
and the A/D result is evaluated to be inside or outside of
this range. When WCIO (ADCON.1) is 0, then WCM is
set if the A/D result is found to be inside the range.
Otherwise WCM is cleared. When WCIO is a 1, then
WCM is set if the A/D result is found to be outside the
091698 22/47
This equation precisely identifies the relationship
between the window registers (WINHI and WINLO), the
MSB of the A/D conversion (ADMSB), and the WCIO
and WCM bits. However by observation, it is not particularly intuitive as to how this interaction works in a practical sense. If the user makes the assumption that the
value stored in WINHI is greater that the value stored in
WINLO (this is normally but not necessarily the case),
then this equation can be simplified to the following two
cases:
For WCIO = 0: WCM = (WINHI > ADMSB) AND (ADMSB ≥
WINLO)
For WCIO = 1: WCM = (WINHI ≤ ADMSB) OR (ADMSB <
WINLO)
It is clear that these two equations now express the
cases where the A/D result is inside the comparison
window (WCIO = 0) and outside the comparison window
(WCIO = 1). It is important to note the ≤ and ≥ symbols
and account for the specific values that are included in
the comparison.
There is another SFR bit, WCQ, that further defines the
action taken when the WCM is set. If WCQ is 0, then an
A/D Interrupt will occur (if enabled) regardless of the
comparison results. When WCQ is set to a 1, then an
A/D Interrupt will only occur if WCM is set (i.e., the A/D
result comparison was true). This feature allows software to respond only to conditions that meet the programmed range.
PULSE WIDTH MODULATION
The DS87C550 contains four independent 8–bit pulse
width modulator (PWMs) functions each with independently selectable clock sources. For more precise modulation operations, two 8–bit PWM functions (PWM0 &
PWM1 and/or PWM2 & PWM3) can be cascaded
together to form a 16–bit PWM function.
The PWM function is divided into three major blocks: a
clock prescaler, a clock generator, and a pulse generator. A single prescaler provides selectable clocks of different frequencies to each of the four clock generator
blocks. Each clock generator is an 8–bit reloadable
DS87C550
counter that determines the repetition rate (frequency)
of its associated PWM. Each pulse generator PWM
block is an 8–bit timer clocked by the clock generator’s
output. When this timer reaches zero, the output of the
PWM is set to 1. When the timer reaches the user
selected PWM match value stored in SFR PWMx, the
PWM output is cleared to 0. In this way, the frequency
and duty cycle of the PWM is varied under software
control.
PWM PRESCALER
The prescaler block of the PWM function accepts as a
clock input the system clock provided to the CPU (and
other peripherals), and divides it by 1, 4, 16, and 64.
Each of these clocks is available at the output of the
prescaler, and is provided to all four of the PWM clock
generator blocks. The actual clock used by the clock
generator block is dependant on the setting of SFR bits
PWxS2:0 (where x is the PWM channel number 0–3)
located in the PW01CS or PW23CS registers. In addition to selecting one of the prescaler’s CPU clock
divided outputs, setting PWxS2 to a 1 allows an external
clock to be used as an input to the clock generators. The
external clocks are input on device pins PWMC0 (P6.4
for PWM0 or PWM1) or PWMC1 (P6.5 for PWM2 or
PWM3). Like all other inputs to the 8051, these inputs
are synchronized by sampling them using the internal
machine cycle clock. Therefore these inputs must be of
sufficient duration for the clock to sample them properly
(i.e., 2 machine cycles). The complete functionality of
the clock selection SFR bits is as follows:
091698 23/47
DS87C550
Prescaler Output
PWxS2:0
Machine Cycle_Clock/1
000
Machine Cycle_Clock/4
001
Machine Cycle_Clock/16
010
Machine Cycle_Clock/64
011
PWMCx (external)
1xx
In determining the exact frequency output of the prescaler, it is important to note that the machine cycle clock
provided to the prescaler is also software selectable.
The machine cycle clock can be the crystal (or oscillator
frequency) divided by 1, 2, 4, or 1024 as determined by
the CD1:0 and the 4X/2X SFR bits (see Clock Divide
Control section for details).
PWM CLOCK GENERATOR
The clock generator blocks of the PWM modules are
pre–loaded by software with an 8–bit value, and this
value determines the frequency or repetition rate of the
PWM function. A value of 0 causes the selected output
of the prescaler to be passed directly to the pulse generator function (i.e., divide by 1). A value of FFh passes a
clock to the pulse generator function that is the selected
prescaler output divided by 256. In general, the clock
generators provide a divide by N+1 selectable repetition
rate (i.e., frequency) for their PWM channel.
Each clock generator has an associated SFR that contains the 8–bit reload value. These registers are called
PW0FG, PW1FG, PW2FG, and PW3FG (see SFR map
for addresses). In addition, there is a frequency generator enable bit (PW0EN, PW1EN, PW2EN, & PW3EN)
for each of the clock generator blocks that must be set to
a 1 before these blocks will function. These bits are set
to 0 after all resets so software must set them to 1 to
enable the PWM clocks.
The output of the clock generator block is supplied to the
input of the pulse generator block.
PWM PULSE GENERATOR
The pulse generator block of the PWM function produces the PWM output signal on device pins PWMO0
(P6.0), PWMO1(P6.1), PWMO2 (P6.2), AND PWMO3
(P6.3). Each of these output bits has an enable bit:
PW0OE (PW01CON.5), PW1OE (PW01CON.1),
PW2OE (PW23CON.5), and PW3OE (PW23CON.1)
091698 24/47
that are cleared to 0 on all resets, and must be set to 1 by
software before the PWMs will output a signal.
As described earlier, the pulse generator block is basically a free running timer with a comparison register that
is loaded with an 8–bit value by software. The value of
this register establishes the duty cycle of the PWM function. The comparison values are stored in SFRs PWM0,
PWM1, PWM2, and PWM3 for the respective PWM
channels, and it is these values that determine the pulse
duration.
Actually, in accessing these specific SFRs, software
has access to both the compare registers and the timer
registers of the pulse generator blocks. When the PWM
Timer/Compare Value Select SFR bits PW0T/C
(PW01CON.4), PW1T/C (PW01CON.0), PW2T/C
(PW23CON.4), and PW3T/C (PW23CON.0) are
cleared to 0, a read or write to the respective PWMx register accesses the compare register. When these bits
are set to 1, a read or write accesses the timer value.
With the use of these bits, the timers in the pulse generator sections of the PWM functions can be used as general timer functions if desired.
When the free running timer of the pulse generator block
rolls over from FFh to 00h, the PWM’s output is set to a
1. As the timer continues to count up from zero, the output of the PWM is cleared to 0 when the timer value is
equal to the comparison register value. This cycle continues automatically without processor intervention until
software or a reset changes some condition.
The value of 0 in the comparison register is a special
case of each PWM function. Rather than allow a set and
a reset of the PWM output bit, special hardware ensures
that 0 will be output continuously if 0 is loaded into the
compare register.
There are other SFR bits that affect PWM operation for
special modes. Bits PW0DC (PW01CON.6), PW1DC
(PW01CON.2), PW2DC (PW23CON.6), and PW3DC
(PW23CON.2) cause the output of the respective PWM
function to be a constant 1. This feature may be useful
for driving a fixed DC voltage into any circuitry attached
to the PWM output. Bits PW0F (PW01CON.7), PW1F
(PW01CON.3), PW2F (PW23CON.7), and PW3F
(PW23CON.3) are flags that are set by the hardware
when the respective PWM pulse generator timer rolls
over from FFh to 0. These flags must be cleared by software to remove their set condition.
DS87C550
16–Bit Mode
For more precise PWM operations, two 8–bit PWMs
may be combined into a single 16–bit PWM function. By
setting SFR bit PWE0 (PWMADR.0) to a 1, a new 16–bit
PWM0 function is formed from the 8–bit PWM functions
PWM0 (LSB) and PWM1 (MSB). Similarly, by setting
PWE1 (PWMADR.1) to a 1, a new 16–bit PWM1 function is formed from PWM2 (LSB) and PWM3 (MSB).
Since each pair of PWMs can be independently configured into a 16–bit arrangement, the user has the option
of having four 8–bit PWM functions, two 8–bit PWM
functions and a 16–bit PWM function, or two 16–bit
PWM functions.
In 16–bit PWM mode, the prescaler operates exactly as
it did in 8–bit mode. Its outputs are available to all four
clock generator blocks. However in 16–bit mode, the
clock generators for 8–bit PWM1 and PWM3 are not
functional. The clock for 16–bit PWM0 function is provided by the clock generator for 8–bit PWM0 and the
clock for 16–bit PWM1 function is provided by the clock
generator for 8–bit PWM2. The SFR bits PW0EN (clock
generator enable) and PW0S2:0 (clock select bits) provide the programmable clock controls for 16–bit PWM
channel 0, and bits PW2EN and PW2S2:0 provide the
programmable clock controls for 16–bit PWM channel
1. The clock divisor values for the 16–bit PWM operating
frequency are contained in the PW0FG and PW2FG
registers for 16–bit PWM0 and PWM1 (respectively).
Note that these registers remain 8–bit values so the
clock division remains the same for 16–bit and 8–bit
operation.
When in 16–bit mode, the two 8–bit pulse generator timers are concatenated together forming a 16–bit timer.
Therefore the pulse generator section of a 16–bit PWM
channel has a repetition rate of the input clock divided
by 65,536. As in 8–bit mode when the counter reaches
zero, the output of the 16–bit PWM channel is set (i.e.,
logic 1), and when it reaches the pre–loaded match
value it is cleared (i.e., logic 0).
General Purpose Timers/Counters
The DS87C550 contains three general purpose timer/
counters. Timers 0 and 1 are standard 8051 16–bit timer/counters with three modes of operation. Each of
these devices can be used as a 13–bit timer/counter,
16–bit timer/counter or 8–bit timer/counter with auto–reload. Timer 0 can also operate as two 8–bit timer counters. Each timer can also be used as a counter of external pulses on the corresponding T0 or T1 pin. The mode
of operation is controlled by the Timer Mode (TMOD)
register. Each timer/counter consists of a 16–bit register
in two bytes, which can be found in the SFR map as TL0,
TH0, TL1, and TH1. These two timers are enabled by
the Timer Control (TCON) register. A complete description of use and operation of these timers may be found in
the “High–Speed Microcontroller Data Book”.
Timer 2 is a true 16–bit timer/counter with several additional features as compared to timers 1 and 0. With a
16–bit reload register (RLOADL, RLOADH), it provides
up/down auto–reload timer/counters and timer output
clock generation. Timer 2 also supports a capture/
compare function. This new feature provides additional
timing control capabilities for real–time applications with
less CPU intervention. A more detailed description of
this capture/compare feature is provided below.
TIMER 2
The selection of a timer or counter function is controlled
by the C/T2 (T2CON.1) bit When C/T2 is set to 1, Timer
2 acts as a counter where it counts 1 to 0 transitions on
the T2 pin. When C/T2 is cleared to a 0, Timer 2 functions as a timer where it counts the system clock as
determined by the T2M bit (CKCON.5) and the clock
divide control bits CD1, CD0 (PMR.7:6) and the 4X/2X
(PMR.3) bit. A prescaler is used to further divide the
input clock by a programmable ratio. The prescaler
value is programmable to divide by 1, 2, 4, and 8 as
defined by the T2P1 and T2P0 (T2SEL.1:0) bits. Timer 2
is enabled by setting bit TR2 (T2CON.2) to a 1, and disabled by clearing it to a 0.
When the LSB of timer/counter 2 (TL2) overflows, flag
TF2B (T2SEL.4) is set, and flag TF2 (T2CON.7) is set
when the high byte (TH2) overflows. Setting flag TF2
also sets flag TF2B. Even though only one interrupt is
available for Timer 2, either or both of these overflows
can be programmed to request an interrupt. To enable
the interrupt, the Timer 2 interrupt enable bit ET2 (EIE.7)
must be set to a 1. The 8–bit overflow interrupt or the
16–bit overflow interrupt is then individually enabled by
setting TF2BS (T2SEL.6) or TF2S (T2SEL.7). Since
there is only one interrupt vector for both possible Timer
2 interrupts, the interrupt service routine must determine which event caused the interrupt by polling the
available flags. For both interrupt flags, software must
clear them upon servicing the interrupt. There is no
automatic hardware clearing of these flags.
091698 25/47
DS87C550
TIMER 2 CAPTURE FEATURE
One of the new features added to Timer 2 is the capture
function. The output of Timer 2 is available to four independent 16–bit capture registers (CPTR3, CPTR2,
CPTR1, & CPTR0). These registers are loaded with the
16–bit value contained in Timer 2 when transitions
occur on the corresponding input pin CAPT0, CAPT1,
CAPT2, or CAPT3 (P1.0, P1.2, P1.3, or P1.4) respectively. When the capture function is not being used,
these input pins also serve as external interrupt inputs.
The Capture Trigger Control register (CTCON) can be
programmed to make the capture occur on a rising
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
CT3
CT3
CT2
CT2
CT1
CT1
CT0
CT0
CTCON REGISTER FUNCTIONALITY
Capture register 3 triggered by a falling edge on INT5/CT3
Capture register 3 triggered by a rising edge on INT5/CT3
Capture register 2 triggered by a falling edge on INT4/CT2
Capture register 2 triggered by a rising edge on INT4/CT2
Capture register 1 triggered by a falling edge on INT3/CT1
Capture register 1 triggered by a rising edge on INT3/CT1
Capture register 0 triggered by a falling edge on INT2/CT0
Capture register 0 triggered by a rising edge on INT2/CT0
TIMER 2 COMPARE FEATURE
Another new feature added to Timer 2 capabilities is the
compare function. Prior to enabling this function, the
associated compare register (CMPH0: CMPL0,
CMPH1: CMPL1, CMPH3: CMPL3) is loaded by software with a 16–bit number. Each time Timer 2 is incremented, the contents of these registers are compared
with the new value of the timer. When a match occurs,
the corresponding interrupt flag (T2IR.6:4) is set to a 1
on the next machine cycle and an interrupt will occur if
the corresponding enable bit is set in the Extended
Interrupt Enable (EIE.6:4) register. When a match with
CMPH0: CMPL0 occurs, port pins P4.0 through P4.5
are set to a 1 if the corresponding bits of the Set Enable
SETR.7
SETR.6
SETR.5
SETR.4
SETR.3
SETR.2
SETR.1
SETR.0
091698 26/47
TGFF1
TGFF0
CMS5
CMS4
CMS3
CMS2
CMS1
CMS0
edge, a falling edge, or on either a rising or a falling edge
on these input pins. The functionality of the CTCON register is illustrated below. Note that the edge sensitivity
established by the setting of CTCON bits applies to both
the capture function and the external interrupt function
of these input pins. This addition allows maximum flexibility in selecting interrupt polarity. Whether these input
pins are used as external interrupt inputs or as capture
commands, the input will set the appropriate flag in the
External Interrupt Flag register (T2IR.3:0) and will
create an interrupt if the associated enable in the
Extended Interrupt Enable (EIE.3:0) register is set.
register (SETR) are at logic 1. If the match is with
CMPH1: CMPL1, port pins P4.0 through P4.5 are reset
to 0 when the corresponding bits in the reset/toggle
enable register RSTR are at logic 1. A match with
CMPH2: CMPL2 toggles port pins P4.6 and 4.7 if the
corresponding bits in the RSTR register are at logic 1.
Note that for the toggle function, it is not the port pin latch
that is actually toggled. Instead, separate flip–flops output the SFR bits TGFF1and TGFF0 actually determine
the state of the respective port pin. A 0 in a bit position in
either the SETR or the RSTR register disables the corresponding port pin function. The functionality of the
SETR and RSTR registers is shown below.
SETR REGISTER FUNCTIONALITY
This bit toggles if CMR2 and Timer 2 match and CMT1 is 1
This bit toggles if CMR2 and Timer 2 match and CMT0 is 1
If 1 then P4.5 is set on a match between CMR0 and Timer 2
If 1 then P4.4 is set on a match between CMR0 and Timer 2
If 1 then P4.3 is set on a match between CMR0 and Timer 2
If 1 then P4.2 is set on a match between CMR0 and Timer 2
If 1 then P4.1 is set on a match between CMR0 and Timer 2
If 1 then P4.0 is set on a match between CMR0 and Timer 2
DS87C550
RSTR.7
RSTR.6
RSTR.5
RSTR.4
RSTR.3
RSTR.2
RSTR.1
RSTR.0
CMT1
CMT0
CMR5
CMR4
CMR3
CMR2
CMR1
CMR0
RSTR REGISTER FUNCTIONALITY
If 1 then P4.7 toggles on a match between CMR2 and Timer 2
If 1 then P4.6 toggles on a match between CMR2 and Timer 2
If 1 then P4.5 is reset on a match between CMR1 and Timer 2
If 1 then P4.4 is reset on a match between CMR1 and Timer 2
If 1 then P4.3 is reset on a match between CMR1 and Timer 2
If 1 then P4.2 is reset on a match between CMR1 and Timer 2
If 1 then P4.1 is reset on a match between CMR1 and Timer 2
If 1 then P4.0 is reset on a match between CMR1 and Timer 2
WATCHDOG TIMER
control bits. Then, it resets the timer and enables the
processor reset function. After enabling the processor
reset function, software must then reset the timer before
its time–out period or hardware will reset the CPU. Both
the EWT and the Watchdog Reset control (RWT =
WDCON.0) bits are protected by a Timed Access circuit. This prevents errant software from accidentally
clearing the Watchdog.
The free–running watchdog timer, if enabled, will set a
flag and cause a reset if not restarted by software within
the user selectable time–out period.
A typical application is to allow the flag to cause a reset.
When the Watchdog times out, it sets the Watchdog
Timer Reset Flag (WTRF=WDCON.2) which generates
a reset if enabled by the Enable Watchdog Timer Reset
(EWT=WDCON.1) bit. In this way if the code execution
goes awry and software does not reset the watchdog as
scheduled, the processor is put in a known good state:
reset.
The Watchdog timer is controlled by the Clock Control
(CKCON) and the Watchdog Control (WDCON) SFRs.
CKCON.7 and CKCON.6 are WD1 and WD0 respectively, and they select the Watchdog time–out period. Of
course, the 4X/2X (PMR.3) and CD1:0 (PMR.7:6) system clock control bits also affect the time–out period.
Selection of time–out is shown in Table 8.
In a typical initialization, software selects the desired
time–out period using the WD1:0 and the system clock
WATCHDOG TIME–OUT VALUES Table 8
INTERRUPT TIME–OUT (CLOCKS)
4X/2X
1
0
x
x
x
RESET TIME–CLOCKS)
CD1:0
WD1:0=00
WD1:0=01
WD1:0=10
WD1:0=11
WD1:0=00
WD1:0=01
WD1:0=10
WD1:0=11
00
00
01
10
11
215
216
217
217
225
218
219
220
220
228
221
222
223
223
231
224
225
226
226
234
215+512
216+512
217+512
217+512
225+512
218+512
219+512
220+512
220+512
228+512
221+512
222+512
223+512
223+512
231+512
224+512
225+512
226+512
226+512
234+512
The Watchdog Timer uses the internal system clock as
a time base so its time–out periods are very accurate.
From the table, it can be seen that for a 33 MHz crystal
frequency, the Watchdog timer is capable of producing
time–out periods from 3.97 ms (217 * 1/33 MHz) to over
two seconds (2.034 = 226 * 1/33 MHz) with the default
setting of CD1:0 (=10). This wide variation in time–out
periods allows very flexible system implementation.
been completed. Regardless of whether the software
makes use of this flag, there are then 512 clocks left until
the reset flag (WTRF=WDCON.2) is set. Software can
enable (1) or disable (0) the reset using the Enable
Watchdog Reset (EWT=WDCON.1) bit. Note that the
Watchdog is a free running timer and does not require
an enable.
In a typical initialization, the user selects one of the possible counter values to determine the time–out. Once
the counter chain has completed a full count, hardware
will set the interrupt flag (WDIF=WDCON.3). There is no
hardware support for a Watchdog interrupt, but this flag
may be polled to determine if the time–out period has
POWER FAIL RESET
The DS87C550 incorporates an internal precision
band–gap voltage reference which, when coupled with
a comparator circuit, provides a full power–on and power–fail reset function. This circuit monitors the processor’s incoming power supply voltage (Vcc), and holds
091698 27/47
DS87C550
the processor in reset while VCC is out of tolerance.
Once VCC has risen above VRST, the DS87C550 will
restart the oscillator for the external crystal and count
65,536 clock cycles before program execution begins at
location 0000h. This power supply monitor will also
invoke the reset state when VCC drops below the threshold condition. This reset condition will remain while
power is below the minimum voltage level. When power
exceeds the reset threshold, a full power–on reset will
be performed. In this way, this internal voltage monitoring circuitry handles both power–up and power down
conditions without the need for additional external components.
The processor exits the reset condition automatically
once VCC meets VRST. This helps the system maintain
reliable operation by only permitting processor operation when its supply voltage is in a known good state.
Software can determine that a Power–On Reset has
occurred by checking the Power–On Reset flag
(POR=WDCON.6). Software should clear the POR bit
after reading it.
The Reset pin of the DS87C550 is both an input and an
output. When the processor is being held in reset by the
power–fail detection circuitry, the reset pin will be
actively pulled high by the processor, and can therefore
be used as an input to other external devices.
POWER FAIL INTERRUPT
The band–gap voltage reference that sets a precise
reset threshold also generates an optional early warn-
091698 28/47
ing Power–fail Interrupt (PFI). When enabled by software, the processor will vector to ROM address 0033h if
VCC drops below VPFW. PFI has the highest priority. The
PFI enable is in the Watchdog Control SFR
(EPFI=WDCON.5). Setting this bit to a logic 1 will
enable the PFI. Application software can also read the
PFI flag at WDCON.4. A PFI condition sets this bit to a 1.
The flag is independent of the interrupt enable and software must manually clear it.
INTERRUPTS
The DS87C550 provides 16 interrupt sources with three
priority levels. The Power–fail Interrupt (PFI) has the
highest priority. All interrupts, with the exception of the
Power Fail interrupt, are controlled by a series combination of individual enable bits and a global interrupt
enable EA (IE.7). Setting EA to a 1 allows individual
interrupts to be enabled. Clearing EA disables all interrupts regardless of their individual enable settings.
The three available priority levels are low, high, and
highest. The highest priority level is reserved for the
Power Fail Interrupt only. All other interrupt priority levels have individual priority bits that when set to a 1
establish the particular interrupt as high priority. In addition to the user selectable priorities, each interrupt also
has an inherent natural priority. Given that all interrupt
sources maintain the default low priority, the natural
priority determines the priority of simultaneously occurring interrupts. The available interrupt sources, their
flags, their enables their natural priority, and their available priority selection bits are identified in Table 9.
DS87C550
INTERRUPT SOURCES AND PRIORITIES Table 9
NAME
DESCRIPTION
VECTOR
NATURAL
PRIORITY
FLAG
BIT
ENABLE
BIT
PRIORITY
CONTROL BIT
PFI
Power Fail
Interrupt
33h
0
PFI(WDCON.4)
EPFI(WDCON.5)
N/A
INT0
External
Interrupt 0
03h
1
IE0(TCON.1)
EX0(IE.0)
PX0(IP.0)
SCON1
TI1 or RI1 from
serial port 1
0Bh
2
RI_1(SCON1.0)
TI_1(SCON1.1)
ES1(IE.5)
PS1(IP.5)
A/D
A/D Converter
Interrupt
13h
3
EOC(ADCON1.6)
EAD(IE.6)
PAD(IP.6)
TF0
Timer 0
1Bh
4
TF0(TCON.5)
ET0(IE.1)
PT0(IP.1)
INT2/
CF0
External Interrupt 2 or
Capture 0
23h
5
IE2/CF0(T2IR.0)
EX2/EC0(EIE.0)
PX2/PC0(EIP.0)
CM0F
Compare
Match 0
2Bh
6
CM0F(T2IR.4)
ECM0(EIE.4)
PCM0(EIP.4)
INT1
External
Interrupt 1
3Bh
7
IE1(TCON.3)
EX1(IE.2)
PX1(IP.2)
INT3/
CF1
External
Interrupt 3 or
Capture 1
43h
8
IE3/CF1(T2IR.1)
EX3/EC1(EIE.1)
PX3/PC1(EIP.1)
CM1F
Compare
Match 1
4Bh
9
CM1F(T2IR.5)
ECM1(EIE.5)
PCM1(EIP.5)
TF1
Timer 1
53h
10
TF1(TCON.7)
ET1(IE.3)
PT1(IP.3)
INT4/
CF2
External
Interrupt 4 or
Captur 2
5Bh
11
IE4/CF2(T2IR.2)
EX4/EC2(EIE.2)
PX4/PC2(EIP.2)
CM2F
Compare
Match 2
63h
12
CM2F(T2IR.6)
ECM2(EIE.6)
PCM2(EIP.6)
SCON0
TI0 or RI0
from serial
port 0
6Bh
13
RI_0(SCON0.0)
TI_0(SCON0.1)
ES0(IE.4)
PS0(IP.4)
INT5/
CF3
External
Interrupt 5
or Capture 3
73h
14
IE5/CF3(T2IR.3)
EX5/EC3(EIE.3)
PX5/PC3(EIP.3)
TF2
Timer 2
7Bh
15
TF2(TCON.7)
TF2B(T2SEL.4)
ET2(EIE.7)
PT2(EIP.7)
EPROM PROGRAMMING
The DS87C550 follows 8K byte EPROM standards for
the 8051 family. It is available in a UV erasable, ceramic
windowed package and in plastic packages for one–
time user–programmable versions. The part has unique
signature information so programmers can support its
specific EPROM options.
ture should apply address information for each byte to
the address lines and the data value to the data lines.
The control signals must be manipulated as shown in
Table 10. The diagram in Figure 5 shows the expected
electrical connection for programming. Note that the
programmer must apply addresses in demultiplexed
fashion to Ports 1 and 2 with data on Port 0. Waveforms
and timing are provided in the Electrical Specifications.
PROGRAMMING PROCEDURE
Program the DS87C550 as follows :
The DS87C550 should run from a clock speed between
4 and 6 MHz when programmed. The programming fix-
1. Apply the address value
091698 29/47
DS87C550
2. Apply the data value
5. Pulse the PROG signal 5 times for EPROM array
and 25 times for encryption table, lock bits, and other
EPROM bits.
3. Select the programming option from Table 10 using
the control signals.
6. Repeat as many times as necessary.
4. Increase the voltage on VPP from 5V to 12.75V if
writing to the EPROM.
EPROM PROGRAMMING MODES Table 10
MODE
RST
PSEN
ALE/
PROG
EA/
VPP
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code Data
H
L
PL5*
12.75
V
L
H
H
H
H
Verify Code Data
H
L
H
H
L
L
L
H
H
Program Encryption Array
Address 0–3Fh
H
L
PL25*
12.75
V
L
H
H
L
H
LB1
H
L
PL25*
12.75
V
H
H
H
H
H
LB2
H
L
PL25*
12.75
V
H
H
H
L
L
LB3
H
L
PL25*
12.75
V
H
L
H
H
L
H
L
PL25*
12.75
V
L
H
H
L
L
H
L
H
H
L
L
L
L
L
Program Lock Bits
Program Option Register
Address FCh
Read Signature or Option
Register 30, 31, 60, FCh
*PLn indicates pulse to a logic low n times
EPROM LOCK BITS Table 11
Level
Lock Bits
Protection
LB1
LB2
LB3
1
U
U
U
No program lock. Encrypted verify if Encryption table was programmed.
2
P
U
U
Prevent MOVC instructions in external memory from reading program bytes in
internal memory. EA is sampled and latched on reset. Allow no further programming of EPROM.
3
P
P
U
Level 2 plus no verify operation. Also, prevents MOVX instructions in external
memory from reading SRAM (MOVX) in internal memory.
4
P
P
P
Level 3 plus no external execution.
SECURITY OPTIONS
The DS87C550 employs a standard three–level lock
that restricts viewing of the EPROM contents. A
64–byte Encryption Array allows the authorized user to
verify memory by presenting the data in encrypted form.
Lock Bits
The security lock consists of 3 lock bits. These bits
select a total of 4 levels. Higher levels provide increasing security but also limit application flexibility. Table 11
091698 30/47
shows the security settings. Note that the programmer
cannot directly read the state of the security lock.
Encryption Array
The Encryption Array allows an authorized user to verify
EPROM without allowing the true memory to be
dumped. During a verify operation, each byte is Exclusive NORed (XNOR) with a byte in the Encryption Array.
This results in a true representation of the EPROM while
the Encryption is unprogrammed (FFh). Once the
DS87C550
Encryption Array is programmed in a non–FFh state, the
verify value will be encrypted.
For encryption to be effective, the Encryption Array
must be unknown to the party that is trying to verify
memory. The entire EPROM also should be a non–FFh
state or the Encryption Array can be discovered.
The Encryption Array is programmed as shown in Table
10. Note that the programmer cannot read the array.
Also note that the verify operation always uses the
Encryption Array. The array has no impact while FFh.
Simply programming the array to a non–FFh state will
cause the encryption to function.
EPROM ERASURE CHARACTERISTICS
Erasure of the information stored in the DS87C550’s
EPROM occurs when the isolated gate structure of the
EPROM stage element is exposed to certain wavelengths of light. While the gate structure is to some
degree sensitive to a wide range of wavelengths, it is
mostly wavelengths shorter than approximately 4,000
angstroms that are most effective in erasing the
EPROM. Since fluorescent lighting and sunlight have
wavelengths in this range, they can cause erasure if the
device is exposed to them over an extended period of
time (weeks for sunlight, years in room level fluorescent
light). For this reason (and others mentioned previously), it is recommended that an opaque covering be
placed over the window of the –K (windowed PLCC)
package type.
For complete EPROM erasure, exposure to ultraviolet
light at approximately 2537 angstroms to a dose of
15W–sec/cm2 at minimum is recommended. In practice, exposing the EPROM to an ultraviolet lamp of
12,000uW/cm2 rating for 20 to 39 minutes, at a distance
of approximately one–inch will normally be sufficient.
OTHER EPROM OPTIONS
The DS87C550 has user selectable options that must
be set before beginning software execution. These
options use EPROM bits rather than SFRs.
The EPROM selectable options may be programmed
as shown in Table 10. The Option Register sets or reads
these selections. The bits in the Option Register have
the following function:
Bit 7 –4
Bit 3
Reserved. Program to a 1.
Watchdog POR default. Set to 1:
Watchdog reset function is disabled on
power–up. Set to 0: Watchdog reset
function is enabled automatically.
Reserved. Program to a 1.
Bit 2–0
SIGNATURE
The Signature bytes identify the product and programming revision to EPROM programmers. This information is located at programming addresses 30h, 31h, and
60h. This information is as follows:
Address
30h
31h
60h
Value
DAh
55
00
Meaning
Manufacturer
Model
Extension
EPROM PROGRAMMING CONFIGURATION Figure 5
CONTROL SIGNALS
RST
CONTROL SIGNALS
A14
A15
CONTROL SIGNALS
CONTROL SIGNALS
P3.3
P3.4
P3.5
PORT 0
A0 – A7
PORT 1
+5V
EA/VPP
ALE/PROG
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
PROG/VERIFY
DATA
PROGRAM SIGNALS
PROGRAM SIGNALS
CONTROL SIGNALS
CONTROL SIGNALS
CONTROL SIGNALS
A8 – A13
091698 31/47
DS87C550
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin** Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.3V to +6.0V
0°C to 70°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
**Except EA pin which will handle the programming supply voltage for EPROM.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
VCC
4.5
5.0
5.5
V
1
Power–fail Warning
VPFW
4.25
4.38
4.5
V
1
Minimum Operating Voltage
VRST
4.0
4.13
4.25
V
1
Supply Current Active Mode
ICC
30
mA
2
Supply Current Idle Mode
IIDLE
15
mA
3
Supply Current Stop Mode
ISTOP
1
µA
4
Supply Current Stop Mode
w Band–gap
ISPBG
100
µA
4
Input Low Level
VIL
–0.3
+0.8
V
1
Input High Level
VIH
2.0
VCC+0.3
V
1
Input High Level XTAL2 and RST
VIH2
3.5
VCC+0.3
V
1
Output Low Voltage Ports 1, 3,
4, 6, @ IOL=1.6 mA
VOL1
0.15
0.45
V
1
Output Low Voltage Ports 0, 2, 5,
ALE, PSEN @ IOL=3.2 mA
VOL2
0.15
0.45
V
1
Output High Voltage Ports 1, 2, 3,
4, 6, ALE, PSEN @ IOH=–50 µA
VOH1
2.4
V
1,6
Output High Voltage Ports 1, 2, 3,
4, 6, @ IOH= –1.5 mA
VOH2
2.4
V
1, 7
Output High Voltage Port 0, 2, 5,
ALE, PSEN in Bus Mode IOH=
–8 mA
VOH3
2.4
V
1, 5
Input Low Current Ports 1, 2, 3
@ 0.45V
IIL
–55
µA
11
Transition Current from 1 to 0
Ports 1, 2, 3 @ 2V
ITL
–650
µA
8
Input Leakage Port 0, and EA
IL
–10
+10
µA
10
Input Leakage Port 0, 5, Bus
Mode
IL
–300
+300
µA
9
RST Pull–down Resistance
RRST
50
170
kΩ
091698 32/47
DS87C550
NOTES FOR DS87C550 DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. Voltage referenced to digital ground (GND).
2. Active current measured with 33 MHz clock source on XTAL1, Vcc=RST=5.5V, other pins disconnected.
3. Idle mode current measured with 33 MHz clock source on XTAL1, Vcc=5.5V, RST at ground, other pins disconnected.
4. Stop mode current measured with XTAL1 and RST grounded, Vcc=5.5V, all other pins disconnected. This value
is not guaranteed. Users that are sensitive to this specification should contact Dallas Semiconductor for more
information.
5. When addressing external memory.
6. RST= Vcc. This condition mimics operation of pins in I/O mode. Port 0 is tristated in reset and when at a logic high
state during I/O mode.
7. During a 0 to 1 transition, a one–shot drives the ports hard for two oscillator clock cycles. This measurement
reflects port in transition mode.
8. Ports 1, 2, 3, 5, 6 source transition current when being pulled down externally. Current reaches its maximum at
approximately 2 V.
9. 0.45<Vin< Vcc. Not a high impedance input. This port is a weak address holding latch in Bus Mode. Peak current
occurs near the input transition point of the latch, approximately 2V.
10. 0.45<Vin<Vcc. RST= Vcc. This condition mimics operation of pins in I/O mode.
11. This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding
port latch is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin
will also have to overcome the transition current.
A/D CONVERTER ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
Analog Supply Voltage
AVCC
AVSS
Analog Supply Current
AIDD
Analog Idle Mode Current
TYP
MAX
UNITS
NOTES
VCC
VCC
GND
V
1
GND
1
mA
AIDDI
TBD
µA
Analog Power Down Mode
Current
AIDDPD
300
nA
Analog Input Voltage
Internal Reference
External Reference
ADC7–
ADC0
External Analog Reference
Voltage
AVREF–
AVREF+
AVSS–0.2
Internal Reference Voltage
Change with Temperature
Change with AVCC
VBG
VBGT
VBGV
2.4375
V
0
2.50
AVREF+
AVREF–
2.50
± 50
± 10
AVCC +
0.2
V
2.5625
V
PPM/°C
mV/V
091698 33/47
DS87C550
A/D CONVERTER ELECTRICAL CHARACTERISTICS cont’d
PARAMETER
SYMBOL
Analog Input Capacitance
MIN
CIN
TYP
MAX
UNITS
10
15
PF
6.25
us
A/D Clock
tACLK
1
Sampling Time
tADS
5 tACLK
tACLK
Conversion Time
tADC
16 tACLK
tACLK
Resolution
10
Bits
Differential non–linearity
EDL
±1.0
LSB
Integral non–linearity
EIL
±2.0
LSB
Offset Error
EOS
±2.0
LSB
Gain Error
EG
±1.0
%
Crosstalk between A/D inputs
ECT
–60
dB
NOTES FOR A/D CONVERTER ELECTRICAL CHARACTERISTICS
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. The following condition must not be exceeded: GND–0.2V < AVSS < VCC + 0.2V.
2. Due to the dynamic nature of the A/D converter, tACLK has both min and max specifications.
3. A complete conversion cycle requires 16 ACLK periods, including five input sampling periods.
TYPICAL ICC VERSUS FREQUENCY
ICC
mA
30
@ 5V
25
20
15
5
3
2
0
091698 34/47
2
4
6
8
10 12
16
20
24
30
33 MHz
XTAL
FREQUENCY
NOTES
2
3
DS87C550
AC ELECTRICAL CHARACTERISTICS
33 MHz
VARIABLE CLOCK
SYMBOL
MIN
MAX
MIN
MAX
UNITS
1/tCLCL
0
1
33
33
0
1
33
33
MHz
ALE Pulse Width
tLHLL
40
0.375 tMCS
–5
ns
Port 0 Address Valid to ALE Low
tAVLL
10
0.125 tMCS
–5
ns
Address Hold after ALE Low
tLLAX1
10
0.125 tMCS
–5
ns
PARAMETER
Oscillator Freq. (Ext. Osc.)
(Ext. Crystal)
ALE Low to Valid Instruction In
tLLIV
56
0.625tMCS
–20
ALE Low to PSEN Low
tLLPL
10
0.125tMCS
–5
ns
PSEN Pulse Width
tPLPH
55
0.5tMCS–5
ns
41
0.5tMCS–20
ns
PSEN Low to Valid Instr. In
tPLIV
Input Instruction Hold after PSEN
tPXIX
0
Input Instruction Float after PSEN
tPXIZ
26
0.25tMCS–5
ns
Port 0 Address to Valid Instr. In
tAVIV
71
0.75tMCS–20
ns
Port 2 Address to Valid Instr. In
tAVIV2
81
0.875tMCS
–25
ns
PSEN Low to Address Float
tPLAZ
0
0
ns
0
ns
ns
NOTES FOR AC ELECTRICAL CHARACTERISTICS
• The value for tMCS is a time period related to the machine cycle clock in terms of the processor’s input clock fre•
•
•
•
quency. Its value is highlighted in the table “STRETCH VALUE TIMING” for all possible settings of the 4X/2X and
CD1:0 bits. The default condition is CD1 = 1 and CD0 = 0, where 4X/2X is disregarded.
All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN, RD and WR with 100 pF.
Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not damage the parts, but will cause an increase in operating current.
Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle
variation.
091698 35/47
DS87C550
MOVX CHARACTERISTICS
VARIABLE CLOCK
MIN
PARAMETER
MAX
SYMBOL
UNITS
STRETCH
VALUES
CST
(MD2:0)
Data Access ALE Pulse Width
tLHLL2
0.375tMCS–5
0.5tMCS–5
1.5tMCS–10
ns
CST=0
1<=CST<=3
4<=CST<=7
Address Hold after ALE Low for
MOVX Write
tLLAX2
0.125tMCS–5
0.25tMCS–5
1.25tMCS–10
ns
CST=0
1<=CST<=3
4<=CST<=7
RD Pulse Width
tRLRH
ns
WR Pulse Width
tWLWH
0.5tMCS–5
CST*tMCS–10
0.5tMCS–5
CST*tMCS–10
RD Low to Valid Data In
tRLDV
CST=0
1<=CST<=7
CST=0
1<=CST<=7
CST=0
1<=CST<=7
Data Hold after Read
tRHDX
Data Float after Read
tRHDZ
0.25tMCS–5
0.5tMCS–5
1.5tMCS–15
ns
CST=0
1<=CST<=3
4<=CST<=7
ALE Low to Valid Data In
tLLDV
0.625tMCS–20
(CST+0.25)*tMCS–40
(CST+1.25)*tMCS–40
ns
CST=0
1<=CST<=3
4<=CST<=7
Port 0 Address to Valid Data In
tAVDV1
0.75tMCS–20
(CST+0.375)*tMCS–20
(CST+1.375)*tMCS–20
ns
CST=0
1<=CST<=3
4<=CST<=7
Port 2 Address to Valid Data In
tAVDV2
0.875tMCS–20
(CST+0.5)*tMCS–20
(CST+1.5)*tMCS–20
ns
CST=0
1<=CST<=3
4<=CST<=7
ALE Low to RD or WR Low
tLLWL
0.125tMCS–5
0.25tMCS–5
1.25tMCS–10
0.125tMCS+5
0.25tMCS+5
1.25tMCS+10
ns
CST=0
1<=CST<=3
4<=CST<=7
Port 0 Address to RD or WR
Low
tAVWL1
0.25tMCS–5
0.5tMCS–5
2.5tMCS–10
ns
CST=0
1<=CST<=3
4<=CST<=7
Port 2 Address to RD or WR
Low
tAVWL2
0.375tMCS–5
0.625tMCS–5
2.625tMCS–10
ns
CST=0
1<=CST<=3
4<=CST<=7
ns
0.5tMCS–20
CST*tMCS–20
0
ns
ns
Data Valid to WR Transition
tQVWX
–5
ns
Data Hold after Write
tWHQX
0.25tMCS–5
0.5tMCS–5
1.5tMCS–10
ns
RD Low to Address Float
tRLAZ
RD or WR High to ALE High
tWHLH
0
0.25tMCS–5
1.25tMCS–10
–((0.125 tMCS)–5)
ns
10
0.25tMCS+5
1.25tMCS+10
ns
CST=0
1<=CST<=3
4<=CST<=7
CST=0
1<=CST<=3
4<=CST<=7
NOTES FOR MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES
• tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS
for each Stretch selection.
• CST is the stretch cycle value as determined by the MD2, MD1, & MD0 bits of the CKCON register.
091698 36/47
DS87C550
tMCS TIME PERIODS
System Clock Selection
tMCS
4X/2X, CD1, CD0 = 100
0.5 tCLCL
4X/2X, CD1, CD0 = 000
1 tCLCL
4X/2X, CD1, CD0 = x10
4 tCLCL
4X/2X, CD1, CD0 = x11
1024 tCLCL
RD, WR PULSE WIDTH WITH STRETCH CYCLES
RD, WR Pulse Width (in oscillator clocks)
MD2
MD1
MD0
MOVX
Machine
Cycles
0
0
0
2
0.5 tCLCL
1 tCLCL
2 tCLCL
2048 tCLCL
0
0
1
3
tCLCL
2 tCLCL
4 tCLCL
4096 tCLCL
0
1
0
4
2 tCLCL
4 tCLCL
8 tCLCL
8192 tCLCL
0
1
1
5
3 tCLCL
6 tCLCL
12 tCLCL
12288 tCLCL
1
0
0
9
4 tCLCL
8 tCLCL
16 tCLCL
16384 tCLCL
1
0
1
10
5 tCLCL
10 tCLCL
20 tCLCL
20480 tCLCL
1
1
0
11
6 tCLCL
12 tCLCL
24 tCLCL
24576 tCLCL
1
1
1
12
7 tCLCL
14 tCLCL
28 tCLCL
28672 tCLCL
4X/2X=1
CD1:0=00
4X/2X=0
CD1:0=00
4X/2X=x
CD1:0=10
4X/2X=x
CD1:0=11
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER
SYMBOL
MIN
Clock High Time
tCHCX
10
TYP
MAX
UNITS
ns
Clock Low Time
tCLCX
10
ns
Clock Rise Time
tCLCL
5
ns
Clock Fall Time
tCHCL
5
ns
NOTES
091698 37/47
DS87C550
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER
Serial Port Clock Cycle Time
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
tXLXL
Output Data Setup to Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tQVXH
Output Data Hold from Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHQX
Input Data Hold after Clock Rising
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHDX
Clock Rising Edge to Input Data
Valid
SM2=0, 12 clocks per cycle
SM2=1, 4 clocks per cycle
tXHDV
12tCLCL
4tCLCL
ns
ns
12tCLCL
4tCLCL
ns
ns
12tCLCL
4tCLCL
ns
ns
12tCLCL
4tCLCL
ns
ns
12tCLCL
4tCLCL
ns
ns
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such
devices, using the same symbols. For completeness, the following is an explanation of the symbols.
t
A
C
D
H
L
I
Time
Address
Clock
Input data
Logic level high
Logic level low
Instruction
P
Q
R
V
W
X
Z
PSEN
Output data
RD signal
Valid
WR signal
No longer a valid logic level
Tristate
POWER CYCLE TIMING CHARACTERISTICS
PARAMETER
SYMBOL
Cycle Start–up Time
tCSU
Power–on Reset Delay
tPOR
MIN
TYP
MAX
1.8
65536
UNITS
NOTES
ms
1
tCLCL
2
NOTES FOR POWER CYCLE TIMING CHARACTERISTICS
1. Start–up time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crystal manufactured by Fox.
2. Reset delay is a synchronous counter of crystal oscillations after crystal start–up. At 33 MHz, this time is 1.99 ms.
091698 38/47
DS87C550
EPROM PROGRAMMING AND VERIFICATION
PARAMETER
SYMBOL
MIN
Programming Voltage
VPP
12.5
Programming Supply Current
IPP
(21°C to 27°C; VCC=4.5V to 5.5V)
TYP
MAX
UNITS
NOTES
13.0
V
1
75
mA
6
MHz
Oscillator Frequency
1/tCLCL
4
POR Delay
tDELAY
65536
Address Setup to PROG Low
tAVGL
48tCLCL
Address Hold after PROG
tGHAX
48tCLCL
Data Setup to PROG Low
tDVGL
48tCLCL
Data Hold after PROG
tGHDX
48tCLCL
Enable High to VPP
tEHSH
48tCLCL
VPP Setup to PROG Low
tSHGL
10
µs
VPP Hold after PROG
tGHSL
10
µs
PROG Width
tGLGH
90
Address to Data Valid
tAVQV
48tCLCL
Enable Low to Data Valid
tELQV
48tCLCL
Data Float after Enable
tEHQZ
0
PROG High to PROG Low
tGHGL
10
tCLCL
110
2
µs
48tCLCL
µs
NOTES FOR EPROM PROGRAMMING AND VERIFICATION
1. All voltage referenced to ground.
2. The microcontroller holds itself in reset for this duration when power is applied. No signals should be manipulated
during this interval since the microcontroller is ignoring inputs. At a 4 MHz oscillator frequency, this period is
16.4 ms.
091698 39/47
DS87C550
EXTERNAL PROGRAM MEMORY READ CYCLE
tLHLL
tLLIV
ALE
tAVLL
tPLPH
tPLIV
PSEN
tLLPL
tPXIZ
tPLAZ
tPXIX
tLLAX1
ADDRESS
A0–A7
PORT 0
INSTRUCTION
IN
ADDRESS
A0–A7
tAVIV1
tAVIV2
ADDRESS A8–A15 OUT
PORT 2
ADDRESS A8–A15 OUT
EXTERNAL DATA MEMORY READ CYCLE
tLHLL2
tLLDV
ALE
tWHLH
tLLWL
tLLAX1
PSEN
tRLRH
RD
tAVLL
tRLDV
tRLAZ
tRHDZ
tRHDX
tAVWL1
PORT 0
INSTRUCTION
IN
ADDRESS
A0–A7
DATA IN
tAVDV1
tAVDV2
PORT 2
ADDRESS A8–A15 OUT
tAVWL2
091698 40/47
ADDRESS
A0–A7
DS87C550
EXTERNAL DATA MEMORY WRITE CYCLE
tLHLL2
ALE
tWHLH
tLLWL
PSEN
tLLAX2
tWLWH
WR
tAVLL
tWHQX
INSTRUCTION
IN
PORT 0
ADDRESS
A0–A7
ADDRESS
A0–A7
DATA OUT
tQVWX
tAVWL1
ADDRESS A8–A15 OUT
PORT 2
tAVWL2
DATA MEMORY WRITE WITH STRETCH=1
Last Cycle of
Previous
Instruction
First
Machine
Cycle
Second
Machine
Cycle
Third
Machine
Cycle
Next
Instruction
Machine Cycle
MOVX Instruction
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
WR
PORT 0
A0–A7
MOVX
Instruction
Address
PORT 2
D0–D7
A0–A7
D0–D7
Next Instr.
Address
MOVX
Instruction
A8–A15
Next
Instruction
Read
A8–A15
A0–A7
D0–D7
MOVX
Data
Address
MOVX Data
A8–A15
A0–A7
D0–D7
A8–A15
091698 41/47
DS87C550
DATA MEMORY WRITE WITH STRETCH=2
Last Cycle
of Previous
Instruction
First
Machine
Cycle
Second
Machine
Cycle
Third
Machine
Cycle
Fourth
Machine
Cycle
Next
Instruction
Machine
Cycle
MOVX Instruction
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
C1
C2
C3
C4
CLK
ALE
PSEN
WR
PORT 0
D0–D7
A0–A7
D0–D7
A0–A7
MOVX
Next Instr.
Instruction MOVX Address
Instruction
Address
PORT 2
A8–A15
D0–D7
A0–A7
MOVX
Next
Data
Instruction Address
Read
D0–D7
A0–A7
MOVX Data
A8–A15
A8–A15
A8–A15
FOUR CYCLE DATA MEMORY WRITE
STRETCH VALUE=2
DATA MEMORY WRITE WITH STRETCH = 4
Last
Cycle
of Previous
instruction
C1 C2 C3 C4
A0–A7
MOVX
Instruction
Address
Second
Machine
Cycle
First
Machine
Cycle
Fourth
Machine
Cycle
C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
D0–D7
D0–D7
A0–A7
Next
Next
MOVX Instruction Instruction
Read
Instruction Address
A8–15
Third
Machine
Cycle
C1 C2 C3 C4 C1 C2 C3 C4
A0–A7
D0–D7
MOVX
Data
Address
A8–15
Fifth
Machine
Cycle
C1 C2 C3 C4
Ninth
Machine
Cycle
Next
Instruction
Machine
Cycle
C1 C2 C3 C4 C1 C2 C3 C4
A0–A7
D0–D7
MOVX Data
A8–A15
A8–A15
EXTERNAL CLOCK DRIVE
tCLCL
tCHCX
XTAL1
tCHCL
tCLCH
tCLCX
091698 42/47
Eighth
Machine
Cycle
DS87C550
SERIAL PORT MODE 0 TIMING
SERIAL PORT 0 (SYNCHRONOUS MODE)
HIGH SPEED OPERATION SM2=1=>TXD CLOCK=XTAL/4
ALE
PSEN
tQVXH
tXHQX
WRITE TO SBUF
RXD
DATA OUT
D0
D1
D2
D3
D4
D5
D7
D8
TRANSMIT
TXD
CLOCK
tXLXL
TI
WRITE TO SCON
TO CLEAR RI
RXD
DATA IN
D0
D1
D2
D3
D4
D5
D7
D8
TXD
CLOCK
RI
RECEIVE
tXHDV
tXHDX
SERIAL PORT 0 (SYNCHRONOUS MODE)
SM2=0=>TXD CLOCK=XTAL/12
ALE
PSEN
1/(XTAL FREQ/12)
WRITE TO SBUF
D0
D1
D6
TRANSMIT
RXD
DATA OUT
D7
TXD
CLOCK
TI
WRITE TO SCON TO CLEAR RI
TXD CLOCK
D0
D1
D6
D7
RECEIVE
RXD DATA IN
RI
091698 43/47
DS87C550
POWER CYCLE TIMING
VCC
VPFW
VRST
VSS
INTERRUPT
SERVICE ROUTINE
tCSU
XTAL1
tPOR
INTERNAL RESET
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
PROGRAMMING
VERIFICATION
A0–A15
ADDRESS
ADDRESS
D0–D7
DATA IN
tAVQV
DATA OUT
tDVGL
tGHDX
5 PULSES
tAVGL
tGHAX
ALE/PROG
tGHSL
tSHGL
tGHGL
tGLGH
EA/VPP
tEHSH
CONTROL
SIGNALS
091698 44/47
tELQV
tEHQZ
DS87C550
80–PIN QUAD FLAT PACK (14.0 MM X 20.0 MM)
091698 45/47
DS87C550
68–PIN WINDOWED CLCC
091698 46/47
DS87C550
68–PIN PLCC
091698 47/47