AD8061/AD8062/AD8063 (Rev. H) - AV-iQ

Low Cost, 300 MHz
Rail-to-Rail Amplifiers
AD8061/AD8062/AD8063
Data Sheet
CONNECTION DIAGRAMS
APPLICATIONS
Imaging
Photodiode preamps
Professional video and cameras
Handsets
DVDs/CDs
Base stations
Filters
ADC drivers
Clock buffers
8
DISABLE
–IN 2
7
+VS
+IN 3
6
VOUT
5
NC
(Not to Scale)
01065-001
–VS 4
(AD8063 ONLY)
NC = NO CONNECT
Figure 1. 8-Lead SOIC (R)
AD8063
–VS 2
4
8
+VS
–IN1
2
7
VOUT2
+IN1
3
6
–IN2
–VS
4
5
+IN2
(Not to Scale)
AD8061
6 +VS
VOUT 1
5 DISABLE
+IN 3
1
Figure 2. 8-Lead SOIC (R)/MSOP (RM)
–IN
(Not to Scale)
Figure 3. 6-Lead SOT-23 (RJ)
5
+VS
4
–IN
–VS 2
01065-002
VOUT 1
AD8062
VOUT1
01065-003
AD8061/
AD8063
NC 1
+IN 3
(Not to Scale)
Figure 4. 5-Lead SOT-23 (RJ)
3
RF = 50Ω
0
NORMALIZED GAIN (dB)
Low cost
Single (AD8061), dual (AD8062)
Single with disable (AD8063)
Rail-to-rail output swing
Low offset voltage: 6 mV
High speed
300 MHz, −3 dB bandwidth (G = 1)
650 V/µs slew rate
8.5 nV/√Hz at 5 V
35 ns settling time to 0.1% with 1 V step
Operates on 2.7 V to 8 V supplies
Input voltage range = −0.2 V to +3.2 V with VS = 5 V
Excellent video specifications (RL = 150 Ω, G = 2)
Gain flatness: 0.1 dB to 30 MHz
0.01% differential gain error
0.04° differential phase error
35 ns overload recovery
Low power
6.8 mA/amplifier typical supply current
AD8063 400 µA when disabled
01065-004
FEATURES
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
–3
RF = 0Ω
RF
–6
OUT
RL
IN
50Ω
–9
01065-005
VBIAS
–12
1
10
100
1k
FREQUENCY (MHz)
Figure 5. Small Signal Response, RF = 0 Ω, 50 Ω
GENERAL DESCRIPTION
The AD8061/AD8062/AD8063 are rail-to-rail output voltage
feedback amplifiers offering ease of use and low cost. They have
a bandwidth and slew rate typically found in current feedback
amplifiers. All have a wide input common-mode voltage range
and output voltage swing, making them easy to use on single
supplies as low as 2.7 V.
Despite being low cost, the AD8061/AD8062/AD8063 provide
excellent overall performance. For video applications, their
differential gain and phase errors are 0.01% and 0.04° into a
Rev. H
150 Ω load, along with 0.1 dB flatness out to 30 MHz. Additionally, they offer wide bandwidth to 300 MHz along with
650 V/µs slew rate.
The AD8061/AD8062/AD8063 offer a typical low power of
6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400 µA. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
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Technical Support
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AD8061/AD8062/AD8063
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Headroom Considerations ........................................................ 14
Applications ....................................................................................... 1
Overload Behavior and Recovery ............................................ 15
Connection Diagrams ...................................................................... 1
Capacitive Load Drive ............................................................... 16
General Description ......................................................................... 1
Disable Operation ...................................................................... 16
Revision History ............................................................................... 2
Board Layout Considerations ................................................... 16
Specifications..................................................................................... 3
Applications Information .............................................................. 17
Absolute Maximum Ratings ............................................................ 6
Single-Supply Sync Stripper ...................................................... 17
Maximum Power Dissipation ..................................................... 6
RGB Amplifier ............................................................................ 17
ESD Caution .................................................................................. 6
Multiplexer .................................................................................. 18
Typical Performance Characteristics ............................................. 7
Outline Dimensions ....................................................................... 19
Circuit Description ......................................................................... 14
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/13—Rev. G to Rev. H
Changes to Figure 12 ........................................................................ 7
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
2/10—Rev. F to Rev. G
Changes to Table 4 ............................................................................ 6
11/09—Rev. E to Rev. F
Changed Input Common-Mode Voltage Range Parameter........ 4
Updated Outline Dimensions ....................................................... 19
10/07—Rev. D to Rev. E
Changes to Applications .................................................................. 1
Updated Outline Dimensions ....................................................... 19
12/05—Rev. C to Rev. D
Updated Format .................................................................. Universal
Change to Features and General Description ............................... 1
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
5/01—Rev. B to Rev. C
Replaced TPC 9 with new graph .................................................... 7
11/00—Rev. A to Rev. B
2/00—Rev. 0 to Rev. A
11/99—Revision 0: Initial Version
Rev. H | Page 2 of 20
Data Sheet
AD8061/AD8062/AD8063
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
−3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p
G = 1, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step, RL = 2 kΩ
G = 2, VO = 2 V step
150
60
320
115
280
30
650
500
35
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
−77
−50
−90
8.5
1.2
0.01
0.04
28
62
dBc
dBc
dBc
nV/√Hz
pA/√Hz
%
Degrees
dBc
dB
500
300
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2, AD8062
f = 100 kHz
f = 100 kHz
G = 2, RL = 150 Ω
G = 2, RL = 150 Ω
f = 10 MHz
f = 5 MHz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Third-Order Intercept
SFDR
DC PERFORMANCE
Input Offset Voltage
68
74
1
2
3.5
3.5
4
±0.3
70
90
VCM = –0.2 V to +3.2 V
62
13
1
−0.2 to
+3.2
80
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 4.5 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
0.3
0.25
25
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
Input Offset Current
Open-Loop Gain
VO = 0.5 V to 4.5 V, RL = 150 Ω
VO = 0.5 V to 4.5 V, RL = 2 kΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing (Load Resistance Is Terminated at Midsupply)
Output Current
Capacitive Load Drive, VOUT = 0.8 V
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage (Off)
DISABLE Voltage (On)
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
0.1 to 4.5
0.1 to 4.9
50
25
300
Max
6
6
9
9
±4.5
∆VS = 2.7 V to 5 V
Rev. H | Page 3 of 20
72
5
6.8
0.4
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
MΩ
pF
V
dB
4.75
4.85
40
300
2.8
3.2
2.7
Unit
V
V
mA
pF
pF
ns
ns
V
V
8
9.5
V
mA
mA
dB
AD8061/AD8062/AD8063
Data Sheet
TA = 25°C, VS = 3 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
–3 dB Large Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p
G = 1, VO = 1 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
150
60
300
115
250
30
280
230
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
−60
−44
−90
8.5
1.2
dBc
dBc
dBc
nV/√Hz
pA/√Hz
190
180
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
Input Offset Current
Open-Loop Gain
VO = 0.5 V to 2.5 V, RL = 150 Ω
VO = 0.5 V to 2.5 V, RL = 2 kΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing (Load Resistance Is Terminated at Midsupply)
Output Current
Capacitive Load Drive, VOUT = 0.8 V
66
74
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage—Off
DISABLE Voltage—On
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6
6
8.5
8.5
±4.5
13
1
−0.2 to +1.2
80
VCM = –0.2 V to +1.2 V
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 2.5 V
30% overshoot, G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
1
2
3.5
3.5
4
±0.3
70
90
Max
0.3
0.3
0.1 to 2.87
0.1 to 2.9
25
25
300
72
Rev. H | Page 4 of 20
6.8
0.4
80
mV
mV
µV/°C
µA
µA
µA
dB
dB
MΩ
pF
V
dB
2.85
2.90
40
300
0.8
1.2
2.7
Unit
V
V
mA
pF
pF
ns
ns
V
V
3
9
V
mA
mA
dB
Data Sheet
AD8061/AD8062/AD8063
TA = 25°C, VS = 2.7 V, RL = 1 kΩ, VO = 1 V, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Conditions
Min
Typ
G = 1, VO = 0.2 V p-p
G = –1, +2, VO = 0.2 V p-p
G = 1, VO = 1 V p-p
G = 1, VO = 0.2 V p-p, VO dc = 1 V
G = 1, VO = 0.7 V step, RL = 2 kΩ
G = 2, VO = 1.5 V step, RL = 2 kΩ
G = 2, VO = 1 V step
150
60
300
115
230
30
150
130
40
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
–60
–44
–90
8.5
1.2
dBc
dBc
dBc
nV/√Hz
pA/√Hz
110
95
fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ
fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ
f = 5 MHz, G = 2
f = 100 kHz
f = 100 kHz
Crosstalk, Output to Output
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
TMIN to TMAX
Input Offset Current
Open-Loop Gain
VO = 0.5 V to 2.2 V, RL = 150 Ω
VO = 0.5 V to 2.2 V, RL = 2 kΩ
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing (Load Resistance Is Terminated at Midsupply)
Output Current
Capacitive Load Drive, VOUT = 0.8 V
63
74
0.3
0.25
0.1 to 2.55
0.1 to 2.6
25
25
Unit
mV
mV
µV/°C
µA
µA
µA
dB
dB
MΩ
pF
V
dB
2.55
2.6
V
V
mA
pF
pF
40
300
0.5
ns
ns
V
0.9
V
2.7
6.8
0.4
80
Rev. H | Page 5 of 20
8.5
±4.5
300
POWER-DOWN DISABLE
Turn-On Time
Turn-Off Time
DISABLE Voltage (Off)
DISABLE Voltage (On)
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Supply Current when Disabled (AD8063 Only)
Power Supply Rejection Ratio
6
6
13
1
–0.2 to +0.9
0.8
VCM = –0.2 V to +0.9 V
RL = 150 Ω
RL = 2 kΩ
VO = 0.5 V to 2.2 V
30% overshoot: G = 1, RS = 0 Ω
G = 2, RS = 4.7 Ω
1
2
3.5
3.5
4
±0.3
70
90
Max
8
8.5
V
mA
mA
dB
AD8061/AD8062/AD8063
Data Sheet
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 4.
0.8 W
0.5 W
0.5 W
0.6 W
(−VS − 0.2 V) to (+VS + 0.2 V)
±VS
Observe power derating curves
−65°C to +125°C
−40°C to +85°C
300°C
The maximum power that can be safely dissipated by the
AD8061/AD8062/AD8063 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure. While the
AD8061/AD8062/AD8063 is internally short-circuit protected,
this may not be sufficient to guarantee that the maximum
junction temperature (150°C) is not exceeded under all
conditions.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
Specification is for device in free air.
8-Lead SOIC_N: θJA = 160°C/W; θJC = 56°C/W.
5-Lead SOT-23: θJA = 240°C/W; θJC = 92°C/W.
6-Lead SOT-23: θJA = 230°C/W; θJC = 92°C/W.
8-Lead MSOP: θJA = 200°C/W; θJC = 44°C/W.
MAXIMUM POWER DISSIPATION (W)
1
Rating
8V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TJ = 150°C
8-LEAD SOIC
PACKAGE
1.5
1.0
0.5
MSOP
SOT-23-5, SOT-23-6
0
–50 –40 –30 –20 –10
0
10
20
30
40
01065-006
Parameter
Supply Voltage
Internal Power Dissipation1
8-lead SOIC (R)
5-lead SOT-23 (RJ)
6-lead SOT-23 (RJ)
8-lead MSOP (RM)
Input Voltage (Common-Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
R-8, RM-8, SOT-23-5, SOT-23-6
Operating Temperature Range
Lead Temperature (Soldering,
10 sec)
50
60
70
80
AMBIENT TEMPERATURE (°C)
Figure 6. Maximum Power Dissipation vs. Temperature for
AD8061/AD8062/AD8063
ESD CAUTION
Rev. H | Page 6 of 20
90
Data Sheet
AD8061/AD8062/AD8063
TYPICAL PERFORMANCE CHARACTERISTICS
3
G = +1
+VOUT @ +85°C
NORMALIZED GAIN (dB)
0
+VOUT @ +25°C
0.8
+VOUT @ –40°C
0.6
–VOUT @ –40°C
0.4
–VOUT @ +25°C
0
30
20
10
0
50
40
60
70
80
G = +2
–6
G = +5
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
–9
–VOUT @ +85°C
0.2
–3
–12
90
1
10
Figure 7. Output Saturation Voltage vs. Load Current
3
VO = 1.0V p-p
RL = 1kΩ
VBIAS = 1V
AD8062
G = +1
0
NORMALIZED GAIN (dB)
14
12
10
AD8061
8
6
4
G = +2
–3
G = +5
–6
2
5
4
3
2
6
7
01065-011
01065-008
–9
0
–12
8
1
SINGLE POWER SUPPLY (V)
10
100
1k
FREQUENCY (MHz)
Figure 8. ISUPPLY vs. VSUPPLY
Figure 11. Large Signal Frequency Response
3
3
RF = 50Ω
0
VS = 5V
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
–3
NORMALIZED GAIN (dB)
0
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
RF = 0Ω
RF
–6
OUT
IN
RL
50Ω
–9
G = –1
G = –5
–3
G = –2
–6
–12
1
10
100
01065-012
–9
VBIAS
01065-009
NORMALIZED GAIN (dB)
1k
Figure 10. Small Signal Frequency Response
18
POWER SUPPLY CURRENT (mA)
100
FREQUENCY (MHz)
LOAD CURRENT (mA)
16
01065-010
1.0
01065-007
VOLTAGE DIFFERENTIAL FROM VS (Unit)
1.2
–12
1k
1
FREQUENCY (MHz)
10
100
FREQUENCY (MHz)
Figure 9. Small Signal Response, RF = 0 Ω, 50 Ω
Figure 12. Small Signal Frequency Response
Rev. H | Page 7 of 20
1k
AD8061/AD8062/AD8063
Data Sheet
0
VS = 5V
VO = 1V p-p
RL = 1kΩ
VBIAS = 1V
HARMONIC DISTORTION (dBc)
NORMALIZED GAIN (dB)
0
G = –1
–3
G = –2
–6
G = –5
01065-013
–9
–12
1
–20
–30
2ND @ 1MHz
–40
3RD @ 10MHz
–50
–60
–70
–80
–90
–100
0.5
1k
100
10
VS = 5V
RL = 1kΩ
G = +1
–10
NORMALIZED GAIN (dB)
0
–40
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
G = +1
3.5
3.0
604Ω
10µF
+
5V
–50
0.1µF
1kΩ
DISTORTION (dB)
–0.1
VS = 5V
VS = 3V
–0.3
50Ω
1MΩ INPUT
52.3Ω
0.1µF
1.25Vdc
–70
+
1kΩ
(RLOAD)
–
–80
2ND H
–90
–0.4
10
100
3RD H
–110
0.01
1k
FREQUENCY (MHz)
Figure 17. Harmonic Distortion for a 1 V p-p Output Signal vs.
Input Signal DC Bias
SERIES 1
200
–30
150
–40
100
–50
40
SERIES 2
0
–50
20
–100
0
–150
PHASE (Degrees)
50
0.1
1
10
100
–300
1k
01065-015
–250
2ND
VS = 5V
RL = 1kΩ
G = +5
VO = 1V p-p
3RD
10MHz
–60
–70
–80
2ND
–90
3RD
5MHz
–100
–200
– 20
DISTORTION (dB)
80
– 40
0.01
50
10
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
Figure 14. 0.1 dB Flatness
60
1
0.1
1MHz
–110
3RD
2ND
–120
0
1
2
3
4
OUTPUT SIGNAL DC BIAS (V)
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Output Signal DC Bias
Figure 15. AD8062 Open-Loop Gain and Phase vs. Frequency,
VS = 5 V, RL = 1 kΩ
Rev. H | Page 8 of 20
01065-018
1
01065-017
–100
01065-014
–0.5
OPEN-LOOP GAIN (dB)
2.5
Figure 16. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
–60
–0.2
2.0
1.5
INPUT SIGNAL DC BIAS (V)
Figure 13. Large Signal Frequency Response
VS = 2.7V
3RD @ 1MHz
2ND @ 10MHz
1.0
FREQUENCY (MHz)
0.1
01065-016
3
5
Data Sheet
AD8061/AD8062/AD8063
–40
+ 10µF
0.1µF
50Ω
1kΩ
–70
DIFFERENTIAL GAIN
(%)
5V
1kΩ
50Ω
1kΩ
1MΩ
INPUT
TO
3589A
2ND @ 2MHz
–80
2ND @ 500kHz
–90
3RD @ 2MHz
01065-019
–100
3RD @ 500kHz
–110
1.0
1.5
2.0
2.5
4.0
3.5
3.0
0.01
4.5
RTO OUTPUT (V p-p)
0
–0.01
–0.02
–0.04
–0.06
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
DIFFERENTIAL PHASE
(Degrees)
DISTORTION (dB)
–60
2ND @ 10MHz
0.02
0
–0.02
–0.04
01065-022
VS = 5V
RF = RL = 1kΩ
G = +2
–50
–0.06
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
Figure 19. Harmonic Distortion vs. Output Signal Amplitude
Figure 22. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 1 kΩ, VS = 5 V
–30
S1 3RD HARMONIC/
DUAL ±2.5V SUPPLY
S1 2ND HARMONIC/
DUAL ±2.5V SUPPLY
–70
–100
01065-020
–90
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
–110
0.01
0.1
–0.010
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
–80
0
–0.005
1
10
0.04
0.03
0.02
0.01
0
–0.01
–0.02
01065-023
–60
0.010
0.005
DIFFERENTIAL PHASE
(Degrees)
DISTORTION (dB)
–50
DIFFERENTIAL GAIN
(%)
VS = 5V
RI = RL = 1kΩ
VO = 2V p-p
G=2
–40
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
FREQUENCY (MHz, START = 10kHz, STOP = 30MHz)
Figure 23. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, RL = 150 Ω, VS = 5 V
Figure 20. Harmonic Distortion vs. Frequency
1000
VS = 5V
RL = 1kΩ
G = +1
900
800
0.7
700
SLEW RATE (V/µs)
0.8
0.6
0.5
0.4
RISING EDGE
500
400
300
0.2
200
0.1
0
0
0.1
0.2
0.3
0.4
FALLING EDGE
VS = 5V
RL = 1kΩ
G = +1
600
0.3
01065-021
OUTPUT VOLTAGE (V)
0.9
01065-024
1.0
100
0
1.0
0.5
1.5
2.0
2.5
OUTPUT STEP AMPLITUDE (V)
TIME (µs)
Figure 24. Slew Rate vs. Output Step Amplitude
Figure 21. 400 mV Pulse Response
Rev. H | Page 9 of 20
3.0
AD8061/AD8062/AD8063
Data Sheet
1400
FALLING EDGE
VS = ±4V
1200
2.5V
FALLING EDGE
VS = +5V
VOUT
VOLTS
1000
800
600
RISING EDGE
VS = ±4V
400
0V
RISING EDGE
VS = +5V
01065-025
200
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
01065-028
SLEW RATE (V/µs)
VS = ±2.5V
G = +1
RL = 1kΩ
VIN
500mV/DIV
0
4.0
20
40
60
100
80
120
140
160
Figure 25. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 kΩ, VS = 5 V
200
Figure 28. Input Overload Recovery, Input Step = 0 V to 2 V
1k
VS = ±2.5V
G = +5
RL = 1kΩ
VS = 5V
RL = 1kΩ
VOUT
2.5V
100
VOLTS
VOLTAGE NOISE (nV/ Hz)
180
TIME (ns)
OUTPUT STEP (V)
VIN
1.0V
10
100
1k
10k
100k
1M
01065-029
1
10
01065-026
0V
500mV/DIV
0
10M
20
40
60
Figure 26. Voltage Noise vs. Frequency
100
120
140
160
180
200
Figure 29. Output Overload Recovery, Input Step = 0 V to 1 V
100
0
VS = 5V
RL = 1kΩ
–10
–20
VCM = 0.2V p-p
RL = 100Ω
VS = ±2.5V
SIDE 2
–30
10
–40
–50
–60
604Ω
1
604Ω
–70
VIN
200mV p-p
–80
0
10
100
1k
10k
100k
1M
57.6Ω
–90
–100
0.01
10M
FREQUENCY (Hz)
0.1
1
50Ω
154Ω
154Ω
10
FREQUENCY (MHz)
Figure 27. Current Noise vs. Frequency
Figure 30. CMRR vs. Frequency
Rev. H | Page 10 of 20
01065-030
CMRR (dB)
SIDE 1
01065-027
CURRENT NOISE (pA/ Hz)
80
TIME (ns)
FREQUENCY (Hz)
100
500
Data Sheet
0
AD8061/AD8062/AD8063
7
ΔVS = 0.2V p-p
RL = 1kΩ
VS = 5V
–10
VS = 5V
6
–20
–PSRR
5
ISUPPLY (mA)
PSRR (dB)
–30
–40
–50
+PSRR
–60
–70
4
3
2
–80
–100
0.01
0.1
10
1
100
0
1.0
500
01065-034
1
01065-031
–90
1.5
2.0
Figure 31. ±PSRR vs. Frequency Delta
3.5
4.0
4.5
5.0
6
1kΩ
–30
1kΩ
+2.5V
VS = 5V
G = +2
fIN = 10MHz
@ 1.3VBIAS
RL = 100Ω
VDISABLE
5
–40
50Ω
–60
1kΩ
–2.5V
–70
INPUT = SIDE 2
INPUT = SIDE 1
–80
–90
VS = 5V
VIN = 400mV rms
RL = 1kΩ
G = +2
–100
–110
–120
0.01
0.1
1
10
100
4
3
2
1
0
VOUT
–1
500
0
0.8
0.4
FREQUENCY (MHz)
1.6
2.0
Figure 35. AD8063 DISABLE Function, Voltage = 0 V to 5 V
0
1k
VS = 5V
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
–20
1.2
TIME (µs)
Figure 32. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 kΩ, G = 2, VS = 5 V
–10
01065-035
OUT
IN
OUTPUT VOLTAGE (V)
–50
01065-032
OUTPUT TO OUTPUT CROSSTALK (dB)
3.0
Figure 34. AD8063 DISABLE Voltage vs. Supply Current
–20
100
IMPEDANCE (Ω)
–30
–40
–50
–60
–70
VS = 5V
VO = 0.2V p-p
RL = 1kΩ
VBIAS = 1V
10
1
–80
–90
1
10
100
0.01
0.1
1k
FREQUENCY (MHz)
01065-036
0.1
01065-033
DISABLED ISOLATION (dB)
2.5
DISABLE VOLTAGE
FREQUENCY (MHz)
1
10
100
FREQUENCY (MHz)
Figure 33. AD8063 Disabled Output Isolation Frequency Response
Figure 36. Output Impedance vs. Frequency,
VOUT = 0.2 V p-p, RL = 1 kΩ, VS = 5 V
Rev. H | Page 11 of 20
1k
AD8061/AD8062/AD8063
Data Sheet
VS = 5V
G = +2
RL = 1kΩ
VIN = 1V p-p
3.5V
+0.1%
VOLTS
–0.1%
1kΩ
2.5V
1kΩ
1.5V
RL = 1kΩ
01065-037
50Ω
t=0
01065-040
SETTLING TIME TO 0.1%
VS = 5V
RL = 1kΩ
500mV/DIV
0
20ns/DIV
10
20
30
40
50
60
80
70
90
100
TIME (ns)
Figure 37. Output Settling Time to 0.1%
Figure 40. 1 V Step Response
50
45
2.6V
40
35
RISING EDGE
VOLTS
30
25
2.5V
20
VS = 5V
RL = 1kΩ
G = +1
10
5
0
0.5
1.0
1.5
20mV/DIV
2.5
2.0
0
10
20
OUTPUT VOLTAGE STEP
Figure 38. Settling Time vs. VOUT
30
40
50
60
TIME (ns)
70
80
90
100
Figure 41. 100 mV Step Response
VS = 5V
G = –1
RF = 1kΩ
RL = 1kΩ
VS = 5V
G = +2
RF = RL = 1kΩ
VIN = 4V p-p
VOLTS
4.86V
2.43V
0V
2µs
1V
2µs/DIV
Figure 42. Output Rail-to-Rail Swing
Figure 39. Output Swing
Rev. H | Page 12 of 20
1V/DIV
01065-042
0V
01065-039
VOLTS
01065-041
2.4V
15
01065-038
SETTLING TIME (ns)
VS = 5V
G = +2
RL = 1kΩ
VIN = 100mV
FALLING EDGE
Data Sheet
AD8061/AD8062/AD8063
VS = 5V
G = +2
RL = RF = 1kΩ
VIN = 2V p-p
VS = 5V
G = +1
RL = 1kΩ
VOLTS
4.5V
2.5V
2.4V
2.5V
50mV/DIV
0
5
10
15
20
25
30
35
40
45
01065-044
0.5V
01065-043
VOLTS
2.6V
1V/DIV
50
0
5
10
15
20
25
30
35
TIME (ns)
TIME (ns)
Figure 43. 200 mV Step Response
Figure 44. 2 V Step Response
Rev. H | Page 13 of 20
40
45
50
AD8061/AD8062/AD8063
Data Sheet
CIRCUIT DESCRIPTION
–0.4
–0.8
–1.2
–1.6
VOS (mV)
The AD8061/AD8062/AD8063 family is comprised of high
speed voltage feedback op amps. The high slew rate input stage
is a true, single-supply topology, capable of sensing signals at or
below the minus supply rail. The rail-to-rail output stage can
pull within 30 mV of either supply rail when driving light loads
and within 0.3 V when driving 150 Ω. High speed performance is maintained at supply voltages as low as 2.7 V.
HEADROOM CONSIDERATIONS
–2.0
–2.4
–2.8
These amplifiers are designed for use in low voltage systems.
To obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier’s headroom limits.
The input stage is the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 45 shows a typical offset voltage vs. input
common-mode voltage for the AD8061/AD8062/AD8063
amplifier on a 5 V supply. Accurate dc performance is maintained from approximately 200 mV below the minus supply
to within 1.8 V of the positive supply. For high speed signals,
however, there are other considerations. Figure 46 shows −3 dB
bandwidth vs. dc input voltage for a unity-gain follower. As
the common-mode voltage approaches the positive supply,
the amplifier holds together well, but the bandwidth begins to
drop at 1.9 V within +VS.
This manifests itself in increased distortion or settling time.
Figure 16 plots the distortion of a 1 V p-p signal with the
AD8061/AD8062/AD8063 amplifier used as a follower on
a 5 V supply vs. signal common-mode voltage. Distortion
performance is maintained until the input signal center voltage
gets beyond 2.5 V, as the peak of the input sine wave begins to
run into the upper common-mode voltage limit.
01065-045
–4.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VCM (V)
Figure 45. VOS vs. Common-Mode Voltage, VS = 5 V
2
0
VCM = 3.0
VCM = 3.1
VCM = 3.2
–2
VCM = 3.3
VCM = 3.4
–4
–6
–8
0.1
01065-046
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier’s positive input lies within the amplifier’s input
common-mode range.
–3.6
GAIN (dB)
The AD8061/AD8062/AD8063 input common-mode voltage
range extends from the negative supply voltage (actually 200 mV
below this), or ground for single-supply operation, to within
1.8 V of the positive supply voltage. Thus, at a gain of 2, the
AD8061/AD8062/AD8063 can provide full rail-to-rail output
swing for supply voltage as low as 3.6 V, assuming the input
signal swings from −VS (or ground) to +VS/2. At a gain of 3,
the AD8061/AD8062/AD8063 can provide a rail-to-rail output
range down to 2.7 V total supply voltage.
–3.2
1
10
100
1k
10k
FREQUENCY (MHz)
Figure 46. Unity-Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
Higher frequency signals require more headroom than lower
frequencies to maintain distortion performance. Figure 47
illustrates how the rising edge settling time for the amplifier
configured as a unity-gain follower stretches out as the top of
a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit is
the output stage. The AD8061/AD8062/AD8063 amplifiers use
a common emitter style output stage. This output stage
maximizes the available output range, limited by the saturation
voltage of the output transistors. The saturation voltage
increases with the drive current the output transistor is required
to supply, due to the output transistors’ collector resistance. The
saturation voltage is estimated using the equation
VSAT = 25 mV + IO × 8 Ω
where:
IO is the output current.
8 Ω is a typical value for the output transistors’ collector
resistance.
Rev. H | Page 14 of 20
Data Sheet
AD8061/AD8062/AD8063
3.6
3.7
3.4
3.5
3.0
2V TO 3V STEP
2.1V TO 3.1V STEP
2.2V TO 3.2V STEP
2.6
2.3V TO 3.3V STEP
2.4
4
8
12
16
20
24
28
2.9
VOLTAGE STEP
FROM 2.4V TO 3.6V
2.7
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
2.3
01065-047
0
VOLTAGE STEP
FROM 2.4V TO 3.4V
2.5
2.4V TO 3.4V STEP
2.2
2.0
3.1
2.1
0
32
100
200
300
400
500
600
TIME (ns)
TIME (ns)
Figure 48. Pulse Response for G = 1 Follower,
Input Step Overloading the Input Stage
Figure 47. Output Rising Edge for 1 V Step at
Input Headroom Limits, G = 1, VS = 5 V, 0 V
As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals. Figure 16, Figure 17, and Figure 18 illustrate this point,
plotting typical distortion vs. output amplitude and bias for
gains of 2 and 5.
Output
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49
shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
5.0
4.6
Input
The specified input common-mode voltage of the AD8061/
AD8062/AD8063 is −200 mV below the negative supply to
within 1.8 V of the positive supply. Exceeding the top limit
results in lower bandwidth and increased settling time as seen
in Figure 46 and Figure 47. Pushing the input voltage of a unitygain follower beyond 1.6 V within the positive supply leads to
the behavior shown in Figure 48—an increasing amount of
output error and much increased settling time. Recovery time
from input voltages 1.6 V or closer to the positive supply is
approximately 35 ns, which is limited by the settling artifacts
caused by transistors in the input stage coming out of saturation.
INPUT AND OUTPUT VOLTAGE (V)
OVERLOAD BEHAVIOR AND RECOVERY
The AD8061/AD8062/AD8063 family does not exhibit phase
reversal, even for input voltages beyond the voltage supply rails.
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.
Rev. H | Page 15 of 20
OUTPUT VOLTAGE
5V TO 2.5V
4.2
3.8
OUTPUT VOLTAGE
0V TO 2.5V
3.4
3.0
2.6
INPUT VOLTAGE
EDGES
2.2
R
1.8
1.4
R
1.0
VIN
–
0.6
5V
2.5V
VO
–
0.2
–0.2
0
10
20
30
40
50
60
TIME (ns)
Figure 49. Overload Recovery, G = −1, VS = 5 V
70
01065-049
2.8
3.3
01065-048
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.2
AD8061/AD8062/AD8063
Data Sheet
CAPACITIVE LOAD DRIVE
DISABLE OPERATION
The AD8061/AD8062/AD8063 family is optimized for
bandwidth and speed, not for driving capacitive loads. Output
capacitance creates a pole in the amplifier’s feedback path,
leading to excessive peaking and potential oscillation. If dealing
with load capacitance is a requirement of the application, the
two strategies to consider are as follows:
The internal circuit for the AD8063 disable function is shown
in Figure 52. When the DISABLE node is pulled below 2 V
from the positive supply, the supply current decreases from
typically 6.5 mA to under 400 µA, and the AD8063 output
enters a high impedance state. If the DISABLE node is not
connected and allowed to float, the AD8063 stays biased at
full power.
Figure 50 shows a unity-gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
VCC
2V
TO AMPLIFIER
BIAS
DISABLE
VEE
Figure 52. Disable Circuit of the AD8063
RSERIES
AD8061
CLOAD
01065-050
VO
VIN
Figure 50. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in the AD8061/AD8062/
AD8063 family are able to drive more capacitive load without
excessive peaking when used in higher gain configurations
because the increased noise gain reduces the bandwidth of the
overall feedback loop. Figure 51 plots the capacitance that
produces 30% overshoot vs. noise gain for a typical amplifier.
Figure 34 shows the AD8063 supply current vs. DISABLE
voltage. Figure 35 plots the output seen when the AD8063 input
is driven with a 10 MHz sine wave, and DISABLE is toggled
from 0 V to 5 V, illustrating the part’s turn-on and turn-off
time. Figure 33 shows the input/output isolation response with
the AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high speed performance of the AD8061/AD8062/
AD8063 family requires the use of high speed board layout
techniques and low parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. Remove the ground plane near the package to reduce
parasitic capacitance.
RS = 4.7
1k
RS = 0
100
01065-051
CAPACITIVE LOAD (pF)
10k
10
1
01065-052
Use a small resistor in series with the amplifier’s output and the
load capacitance.
Reduce the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
2
3
4
CLOSED-LOOP GAIN
Figure 51. Capacitive Load vs. Closed-Loop Gain
5
Proper bypassing is critical. Use a ceramic 0.1 µF chip capacitor
to bypass both supplies. Locate the chip capacitor within 3 mm
of each power pin. Additionally, connect in parallel a 4.7 µF to
10 µF tantalum electrolytic capacitor to provide charge for fast,
large signal changes at the output.
Minimizing parasitic capacitance at the amplifier’s inverting
input pin is very important. Locate the feedback resistor close to
the inverting input pin. The value of the feedback resistor may
come into play—for instance, 1 kΩ interacting with 1 pF of
parasitic capacitance creates a pole at 159 MHz. Use stripline
design techniques for signal traces longer than 25 mm. Design
them with either 50 Ω or 75 Ω characteristic impedance and
proper termination at each end.
Rev. H | Page 16 of 20
Data Sheet
AD8061/AD8062/AD8063
APPLICATIONS INFORMATION
SINGLE-SUPPLY SYNC STRIPPER
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of analog-to-digital conversion,
the sync pulses consume some of the dynamic range, so
removing them increases the converter’s available dynamic
range for the video information.
Figure 53 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the negative
supply is at ground potential, the lowest potential to which the
output can go is ground. This feature is exploited to create a
waveform whose lowest amplitude is the black level of the video
and does not include the sync level.
3V
4
RG
1kΩ
6
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
MONITOR
#1
10µF
75Ω
1kΩ
VIDEO OUT
3V
75Ω
RF
1kΩ
PIN NUMBERS ARE
FOR 8-LEAD PACKAGE
1kΩ
3
Figure 53. Single 3 V Sync Stripper Using AD8061
10µF
0.1µF
7
2
AD8061
75Ω
6
RED
75Ω
4
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Because the sync level is
below the black level, it does not show up at the output. However,
all of the active video portion of the waveform is amplified by a
gain of 2 and then normalized to unity gain by the backterminated transmission line. Figure 54 is an oscilloscope plot
of the input and output waveforms.
1kΩ
3V
MONITOR
#2
10µF
0.1µF
8
1kΩ
2
3
1
AD8062
7
AD8062
1kΩ
75Ω
1kΩ
BLUE
75Ω
6
INPUT
GREEN
75Ω
5
1
75Ω
4
Figure 55. RGB Cable Driver Using AD8061 and AD8062
2
RGB AMPLIFIER
500mV
10µs
01065-054
OUTPUT
Figure 54. Input and Output Waveforms for a Single-Supply
Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single-supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not
at ground but at a positive voltage.
Most RGB graphics signals are created by video DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and the voltage of the video
is also zero. Before the availability of high speed rail-to-rail op
amps, it was essential that an amplifier have a negative supply
to amplify such a signal. Such an amplifier is necessary if one
wants to drive a second monitor from the same DAC outputs.
However, high speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 accept ground-level input signals and
output ground-level signals. They are used as RGB signal
amplifiers. A combination of the AD8061 (single) and the
AD8062 (dual) amplifies the three video channels of an RGB
system. Figure 55 shows a circuit that performs this function.
Rev. H | Page 17 of 20
01065-055
AD8061
2
GREEN
DAC
01065-053
7
3
75Ω
RED
DAC
BLUE
DAC
0.1µF
VIDEO IN
The circuit can be modified to provide the sync stripping
function for such a waveform. Instead of connecting RG to
ground, connect it to a dc voltage that is two times the black
level of the input signal. The gain from the noninverting input
to the output is 2, which means the black level is amplified by 2
to the output. However, the gain through RG is −1 to the output.
It takes a dc level of twice the input black level to shift the black
level to ground at the output. When this occurs, the sync is
stripped, and the active video is passed as in the groundreferenced case.
AD8061/AD8062/AD8063
Data Sheet
MULTIPLEXER
The AD8063 has a disable pin used to power down the amplifier to save power or to create a mux circuit. If two (or more)
AD8063 outputs are connected together, and only one is enabled,
then only the signal of the enabled amplifier will appear at the
output. This configuration is used to select from various input
signal sources. Additionally, the same input signal is applied to
different gain stages, or differently tuned filters, to make a gainstep amplifier or a selectable frequency amplifier.
Figure 56 shows a schematic of two AD8063 devices used to
create a mux that selects between two inputs. One of these is a
1 V p-p, 3 MHz sine wave; the other is a 2 V p-p, 1 MHz sine wave.
The select signal and the output waveforms for this circuit are
shown in Figure 57. For synchronization clarity, two different
frequency synthesizers, whose time bases are locked to each
other, generate the signals.
2µs
OUTPUT
SELECT
0.1µF
10µF
1V
49.9Ω
AD8063
1
0.1µF
–4V
Figure 57. AD8063 Mux Output
10µF
1kΩ
49.9Ω
1kΩ
+4V
49.9Ω
0.1µF
49.9Ω
2V p-p
1MHz
AD8063
TIME
BASE
IN
10µF
1
0.1µF
–4V
VOUT
10µF
1kΩ
1kΩ
HCO4
SELECT
01065-056
1V p-p
3MHz
TIME
BASE
OUT
Figure 56. Two-to-One Multiplexer Using Two AD8063s
Rev. H | Page 18 of 20
2V
01065-057
+4V
Data Sheet
AD8061/AD8062/AD8063
OUTLINE DIMENSIONS
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
5.00 (0.1968)
4.80 (0.1890)
3.00
2.80
2.60
3
8
4.00 (0.1574)
3.80 (0.1497)
0.95 BSC
5
1
4
6.20 (0.2441)
5.80 (0.2284)
1.90
BSC
1.27 (0.0500)
BSC
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.25 (0.0098)
0.10 (0.0040)
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
5°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.55
0.45
0.35
1.75 (0.0688)
1.35 (0.0532)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
1.45 MAX
0.95 MIN
11-01-2010-A
1.30
1.15
0.90
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Figure 58. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
3.00
2.90
2.80
5
4
1
2
3
3.20
3.00
2.80
3.00
2.80
2.60
8
3.20
3.00
2.80
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
5.15
4.90
4.65
4
PIN 1
IDENTIFIER
1.30
1.15
0.90
0.65 BSC
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.95
0.85
0.75
0.55
0.45
0.35
0.60
BSC
12-16-2008-A
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
1
5
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 60. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
Rev. H | Page 19 of 20
15° MAX
1.10 MAX
0.15
0.05
COPLANARITY
0.10
0.40
0.25
6°
0°
0.23
0.09
0.80
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
10-07-2009-B
1.70
1.60
1.50
6
AD8061/AD8062/AD8063
Data Sheet
ORDERING GUIDE
Model 1
AD8061AR
AD8061ARZ
AD8061ARZ-REEL
AD8061ARZ-REEL7
AD8061ART-R2
AD8061ART-REEL7
AD8061ARTZ-R2
AD8061ARTZ-REEL
AD8061ARTZ-REEL7
AD8061AR-EBZ
AD8061ART-EBZ
AD8062AR
AD8062ARZ
AD8062ARZ-RL
AD8062ARZ-R7
AD8062ARMZ
AD8062ARMZ-RL
AD8062ARMZ-R7
AD8062AR-EBZ
AD8062ARM-EBZ
AD8063ARZ
AD8063ARZ-REEL
AD8063ARZ-REEL7
AD8063ART-R2
AD8063ART-REEL7
AD8063ARTZ-R2
AD8063ARTZ-REEL
AD8063ARTZ-REEL7
AD8063AR-EBZ
AD8063ART-EBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
–40°C to +85°C
40°C to +85°C
40°C to +85°C
40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
5-Lead SOT-23, 250 Piece Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
5-Lead SOT-23, 250 Piece Tape and Reel
5-Lead SOT-23, 13-Inch Tape and Reel
5-Lead SOT-23, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 5-Lead SOT-23
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13-Inch Tape and Reel
8-Lead MSOP, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N, 13-Inch Tape and Reel
8-Lead SOIC_N, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
6-Lead SOT-23, 250 Piece Tape and Reel
6-Lead SOT-23, 13-Inch Tape and Reel
6-Lead SOT-23, 7-Inch Tape and Reel
Evaluation Board for 8-Lead SOIC_N
Evaluation Board for 6-Lead SOT-23
Z = RoHS Compliant Part, # denotes RoHS product may be top or bottom marked.
New branding after data code 0542, previously branded HGA.
3
New branding after data code 0542, previously branded HHA.
1
2
©1999–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01065-0-1/13(H)
Rev. H | Page 20 of 20
Package Option
R-8
R-8
R-8
R-8
RJ-5
RJ-5
RJ-5
RJ-5
RJ-5
Branding
HGA
HGA
H0D 2
H0D2
H0D2
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
#HCA
#HCA
#HCA
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
RJ-6
RJ-6
HHA
HHA
H0E 3
H0E3
H0E3