Intel® 64 and IA-32 Architectures Software Developer'

Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 2 (2A, 2B, 2C & 2D):
Instruction Set Reference, A-Z
NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of three volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference A-Z, Order Number 325383;
System Programming Guide, Order Number 325384. Refer to all three volumes when evaluating your
design needs.
Order Number: 325383-060US
September 2016
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CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2
OVERVIEW OF VOLUME 2A, 2B, 2C AND 2D: INSTRUCTION SET REFERENCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.1
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
1.3.2
Reserved Bits and Software Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.3
Instruction Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.4
Hexadecimal and Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.5
Segmented Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.6
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.7
A New Syntax for CPUID, CR, and MSR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4
RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
CHAPTER 2
INSTRUCTION FORMAT
2.1
INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE . . . . . . . . . . . . . . . . . . . . 2-1
2.1.1
Instruction Prefixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.2
Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.3
ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.4
Displacement and Immediate Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.5
Addressing-Mode Encoding of ModR/M and SIB Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.2
IA-32E MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.2.1
REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.1
Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.2
More on REX Prefix Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.2.1.3
Displacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.4
Direct Memory-Offset MOVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.5
Immediates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.2.1.6
RIP-Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.1.7
Default 64-Bit Operand Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.2.2
Additional Encodings for Control and Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.1
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.2
VEX and the LOCK prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.3
VEX and the 66H, F2H, and F3H prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.4
VEX and the REX prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.5
The VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.5.1
VEX Byte 0, bits[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.2
VEX Byte 1, bit [7] - ‘R’. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.5.3
3-byte VEX byte 1, bit[6] - ‘X’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.4
3-byte VEX byte 1, bit[5] - ‘B’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.5
3-byte VEX byte 2, bit[7] - ‘W’ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.5.6
2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest Register Specifier. . . . . 2-16
2.3.6
Instruction Operand Encoding and VEX.vvvv, ModR/M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.6.1
3-byte VEX byte 1, bits[4:0] - “m-mmmm”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.2
2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.6.3
2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.7
The Opcode Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.8
The MODRM, SIB, and Displacement Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.9
The Third Source Operand (Immediate Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10
AVX Instructions and the Upper 128-bits of YMM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.10.1
Vector Length Transition and Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Vol. 2A iii
CONTENTS
PAGE
2.3.11
2.3.12
2.3.12.1
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
2.4.10
2.5
2.5.1
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.7
2.6.8
2.6.9
2.6.10
2.6.11
2.6.11.1
2.6.11.2
2.6.11.3
2.6.12
2.6.13
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.7.6
2.7.7
2.7.8
2.7.9
2.7.10
2.7.11
2.8
AVX Instruction Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Vector SIB (VSIB) Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
64-bit Mode VSIB Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
AVX AND SSE INSTRUCTION EXCEPTION SPECIFICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Exceptions Type 1 (Aligned memory reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Exceptions Type 3 (<16 Byte memory argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Exceptions Type 5 (<16 Byte mem arg and no FP exceptions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Exceptions Type 7 (No FP exceptions, no memory arg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Exceptions Type 8 (AVX and no memory argument) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Exception Type 11 (VEX-only, mem arg no AC, floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Exception Conditions for VEX-Encoded GPR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
INTEL® AVX-512 ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Instruction Format and EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Register Specifier Encoding and EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Opmask Register Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Masking Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Compressed Displacement (disp8*N) Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
EVEX Encoding of Broadcast/Rounding/SAE Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Embedded Broadcast Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Static Rounding Support in EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
SAE Support in EVEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Vector Length Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
#UD Equations for EVEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
State Dependent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Independent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Dependent #UD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Device Not Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Scalar Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
Exceptions Type E1 and E1NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
Exceptions Type E2 of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Exceptions Type E3 and E3NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Exceptions Type E4 and E4NF of EVEX-Encoded Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Exceptions Type E5 and E5NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Exceptions Type E6 and E6NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Exceptions Type E7NM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Exceptions Type E9 and E9NF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Exceptions Type E10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Exception Type E11 (EVEX-only, mem arg no AC, floating-point exceptions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Exception Type E12 and E12NP (VSIB mem arg, no AC, no floating-point exceptions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
EXCEPTION CLASSIFICATIONS OF OPMASK INSTRUCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
CHAPTER 3
INSTRUCTION SET REFERENCE, A-L
3.1
INTERPRETING THE INSTRUCTION REFERENCE PAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1.1
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1.1.1
Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2
3.1.1.2
Opcode Column in the Instruction Summary Table (Instructions with VEX prefix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3
3.1.1.3
Instruction Column in the Opcode Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5
3.1.1.4
Operand Encoding Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.1.1.5
64/32-bit Mode Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8
3.1.1.6
CPUID Support Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.1.7
Description Column in the Instruction Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
3.1.1.8
Description Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9
iv Vol. 2A
CONTENTS
PAGE
3.1.1.9
Operation Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.1.10
Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
3.1.1.11
Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.12
FPU Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.13
Protected Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
3.1.1.14
Real-Address Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
3.1.1.15
Virtual-8086 Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15
3.1.1.16
Floating-Point Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.17
SIMD Floating-Point Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.18
Compatibility Mode Exceptions Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.1.1.19
64-Bit Mode Exceptions Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.2
INSTRUCTIONS (A-L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
AAA—ASCII Adjust After Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
AAD—ASCII Adjust AX Before Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
AAM—ASCII Adjust AX After Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
AAS—ASCII Adjust AL After Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
ADC—Add with Carry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
ADD—Add. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
ADDPD—Add Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
ADDPS—Add Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36
ADDSD—Add Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39
ADDSS—Add Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41
ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43
ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48
AESDEC—Perform One Round of an AES Decryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
AESDECLAST—Perform Last Round of an AES Decryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
AESENC—Perform One Round of an AES Encryption Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
AESENCLAST—Perform Last Round of an AES Encryption Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
AESIMC—Perform the AES InvMixColumn Transformation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58
AESKEYGENASSIST—AES Round Key Generation Assist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
AND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61
ANDN — Logical AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-64
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-70
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73
ARPL—Adjust RPL Field of Segment Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76
BLENDPD — Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78
BEXTR — Bit Field Extract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80
BLENDPS — Blend Packed Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-81
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85
BLSI — Extract Lowest Set Isolated Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88
BLSMSK — Get Mask Up to Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89
BLSR — Reset Lowest Set Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-90
BNDCL—Check Lower Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-91
BNDCU/BNDCN—Check Upper Bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93
BNDLDX—Load Extended Bounds Using Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95
BNDMK—Make Bounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98
BNDMOV—Move Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
BNDSTX—Store Extended Bounds Using Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
BOUND—Check Array Index Against Bounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106
BSF—Bit Scan Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-108
BSR—Bit Scan Reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110
BSWAP—Byte Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112
BT—Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113
BTC—Bit Test and Complement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115
Vol. 2A v
CONTENTS
PAGE
BTR—Bit Test and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-117
BTS—Bit Test and Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-119
BZHI — Zero High Bits Starting with Specified Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-121
CALL—Call Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-122
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword . . . . . . .3-135
CLAC—Clear AC Flag in EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-136
CLC—Clear Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-137
CLD—Clear Direction Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-138
CLFLUSH—Flush Cache Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-139
CLFLUSHOPT—Flush Cache Line Optimized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-141
CLI — Clear Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-143
CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-145
CLWB—Cache Line Write Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-146
CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-148
CMOVcc—Conditional Move. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-149
CMP—Compare Two Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-153
CMPPD—Compare Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-155
CMPPS—Compare Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-162
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-169
CMPSD—Compare Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-173
CMPSS—Compare Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-177
CMPXCHG—Compare and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-181
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-183
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . .3-186
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . .3-188
CPUID—CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-190
CRC32 — Accumulate CRC32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-225
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values . . . . . . . . . . . . .3-228
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . .3-232
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . .3-235
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-239
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values .3240
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-244
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-245
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values .3-246
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values .3249
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-252
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . .3-253
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value. .3-255
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . .3-257
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . .3-259
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value. .3-261
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer . . . . . . . . . . . . . . . . . . . . . . . . . .3-263
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers3265
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . .3-269
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-270
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers . . . . . . . . . . . . . .3-273
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer . . . . . . . . . . . . .3-274
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer . . . . . . . . . . . . . . . . . . . . .3-276
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-278
DAA—Decimal Adjust AL after Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-279
DAS—Decimal Adjust AL after Subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-281
DEC—Decrement by 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-283
DIV—Unsigned Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-285
DIVPD—Divide Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-288
vi Vol. 2A
CONTENTS
PAGE
DIVPS—Divide Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-291
DIVSD—Divide Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-294
DIVSS—Divide Scalar Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-296
DPPD — Dot Product of Packed Double Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-298
DPPS — Dot Product of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-300
EMMS—Empty MMX Technology State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-303
ENTER—Make Stack Frame for Procedure Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-304
EXTRACTPS—Extract Packed Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-307
F2XM1—Compute 2x–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309
FABS—Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-311
FADD/FADDP/FIADD—Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-312
FBLD—Load Binary Coded Decimal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-315
FBSTP—Store BCD Integer and Pop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317
FCHS—Change Sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319
FCLEX/FNCLEX—Clear Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-321
FCMOVcc—Floating-Point Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-323
FCOM/FCOMP/FCOMPP—Compare Floating Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325
FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-328
FCOS— Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-331
FDECSTP—Decrement Stack-Top Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-333
FDIV/FDIVP/FIDIV—Divide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-334
FDIVR/FDIVRP/FIDIVR—Reverse Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-337
FFREE—Free Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-340
FICOM/FICOMP—Compare Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341
FILD—Load Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-343
FINCSTP—Increment Stack-Top Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-345
FINIT/FNINIT—Initialize Floating-Point Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-346
FIST/FISTP—Store Integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
FISTTP—Store Integer with Truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-351
FLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-353
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-355
FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-357
FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-359
FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-361
FNOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-364
FPATAN—Partial Arctangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365
FPREM—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
FPREM1—Partial Remainder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
FPTAN—Partial Tangent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-371
FRNDINT—Round to Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-373
FRSTOR—Restore x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-374
FSAVE/FNSAVE—Store x87 FPU State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-376
FSCALE—Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379
FSIN—Sine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
FSINCOS—Sine and Cosine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-383
FSQRT—Square Root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-385
FST/FSTP—Store Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-387
FSTCW/FNSTCW—Store x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-389
FSTENV/FNSTENV—Store x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-391
FSTSW/FNSTSW—Store x87 FPU Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-393
FSUB/FSUBP/FISUB—Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-395
FSUBR/FSUBRP/FISUBR—Reverse Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-398
FTST—TEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403
FXAM—Examine Floating-Point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406
FXCH—Exchange Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-408
FXRSTOR—Restore x87 FPU, MMX, XMM, and MXCSR State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-410
FXSAVE—Save x87 FPU, MMX Technology, and SSE State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-413
FXTRACT—Extract Exponent and Significand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-421
Vol. 2A vii
CONTENTS
PAGE
FYL2X—Compute y * log2x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-423
FYL2XP1—Compute y * log2(x +1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-425
HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-427
HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-430
HLT—Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-433
HSUBPD—Packed Double-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-434
HSUBPS—Packed Single-FP Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-437
IDIV—Signed Divide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-440
IMUL—Signed Multiply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-443
IN—Input from Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-447
INC—Increment by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-449
INS/INSB/INSW/INSD—Input from Port to String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-451
INSERTPS—Insert Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-454
INT n/INTO/INT 3—Call to Interrupt Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-457
INVD—Invalidate Internal Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-469
INVLPG—Invalidate TLB Entries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-471
INVPCID—Invalidate Process-Context Identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-473
IRET/IRETD—Interrupt Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-476
Jcc—Jump if Condition Is Met. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-483
JMP—Jump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-488
KADDW/KADDB/KADDQ/KADDD—ADD Two Masks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-496
KANDW/KANDB/KANDQ/KANDD—Bitwise Logical AND Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-497
KANDNW/KANDNB/KANDNQ/KANDND—Bitwise Logical AND NOT Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-498
KMOVW/KMOVB/KMOVQ/KMOVD—Move from and to Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-499
KNOTW/KNOTB/KNOTQ/KNOTD—NOT Mask Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-501
KORW/KORB/KORQ/KORD—Bitwise Logical OR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-502
KORTESTW/KORTESTB/KORTESTQ/KORTESTD—OR Masks And Set Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-503
KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD—Shift Left Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-505
KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD—Shift Right Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-507
KTESTW/KTESTB/KTESTQ/KTESTD—Packed Bit Test Masks and Set Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-509
KUNPCKBW/KUNPCKWD/KUNPCKDQ—Unpack for Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-511
KXNORW/KXNORB/KXNORQ/KXNORD—Bitwise Logical XNOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-512
KXORW/KXORB/KXORQ/KXORD—Bitwise Logical XOR Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-513
LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-514
LAR—Load Access Rights Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-515
LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-518
LDMXCSR—Load MXCSR Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-520
LDS/LES/LFS/LGS/LSS—Load Far Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-521
LEA—Load Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-525
LEAVE—High Level Procedure Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-527
LFENCE—Load Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-529
LGDT/LIDT—Load Global/Interrupt Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-530
LLDT—Load Local Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-533
LMSW—Load Machine Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-535
LOCK—Assert LOCK# Signal Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-537
LODS/LODSB/LODSW/LODSD/LODSQ—Load String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-539
LOOP/LOOPcc—Loop According to ECX Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-542
LSL—Load Segment Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-544
LTR—Load Task Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-547
LZCNT— Count the Number of Leading Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-549
CHAPTER 4
INSTRUCTION SET REFERENCE, M-U
4.1
IMM8 CONTROL BYTE OPERATION FOR PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.2
Source Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.3
Aggregation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4.1.4
Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4.1.5
Output Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
viii Vol. 2A
CONTENTS
PAGE
4.1.6
4.1.7
4.1.8
4.2
4.3
Valid/Invalid Override of Comparisons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Summary of Im8 Control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Diagram Comparison and Aggregation Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
COMMON TRANSFORMATION AND PRIMITIVE FUNCTIONS FOR SHA1XXX AND SHA256XXX . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
INSTRUCTIONS (M-U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
MASKMOVDQU—Store Selected Bytes of Double Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8
MASKMOVQ—Store Selected Bytes of Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
MAXPD—Maximum of Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
MAXPS—Maximum of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
MFENCE—Memory Fence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
MINPD—Minimum of Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
MINPS—Minimum of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
MINSD—Return Minimum Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29
MINSS—Return Minimum Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
MONITOR—Set Up Monitor Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33
MOV—Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35
MOV—Move to/from Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40
MOV—Move to/from Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43
MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45
MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49
MOVBE—Move Data After Swapping Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53
MOVD/MOVQ—Move Doubleword/Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55
MOVDDUP—Replicate Double FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-62
MOVDQU,VMOVDQU8/16/32/64—Move Unaligned Packed Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
MOVDQ2Q—Move Quadword from XMM to MMX Technology Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75
MOVHLPS—Move Packed Single-Precision Floating-Point Values High to Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-76
MOVHPD—Move High Packed Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
MOVHPS—Move High Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-80
MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
MOVLPD—Move Low Packed Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
MOVLPS—Move Low Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88
MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-90
MOVNTDQA—Load Double Quadword Non-Temporal Aligned Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-92
MOVNTDQ—Store Packed Integers Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94
MOVNTI—Store Doubleword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . 4-98
MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . 4-100
MOVNTQ—Store of Quadword Using Non-Temporal Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-102
MOVQ—Move Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103
MOVQ2DQ—Move Quadword from MMX Technology to XMM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-107
MOVSD—Move or Merge Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-111
MOVSHDUP—Replicate Single FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114
MOVSLDUP—Replicate Single FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
MOVSS—Move or Merge Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-120
MOVSX/MOVSXD—Move with Sign-Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-124
MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-126
MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-130
MOVZX—Move with Zero-Extend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134
MPSADBW — Compute Multiple Packed Sums of Absolute Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-136
MUL—Unsigned Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
MULPD—Multiply Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-146
MULPS—Multiply Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-149
MULSD—Multiply Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-152
MULSS—Multiply Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-154
Vol. 2A ix
CONTENTS
PAGE
MULX — Unsigned Multiply Without Affecting Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-156
MWAIT—Monitor Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-158
NEG—Two's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-161
NOP—No Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-163
NOT—One's Complement Negation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-164
OR—Logical Inclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-166
ORPD—Bitwise Logical OR of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-168
ORPS—Bitwise Logical OR of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-171
OUT—Output to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-174
OUTS/OUTSB/OUTSW/OUTSD—Output String to Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-176
PABSB/PABSW/PABSD/PABSQ — Packed Absolute Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-180
PACKSSWB/PACKSSDW—Pack with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-186
PACKUSDW—Pack with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-194
PACKUSWB—Pack with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-199
PADDB/PADDW/PADDD/PADDQ—Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-204
PADDSB/PADDSW—Add Packed Signed Integers with Signed Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-211
PADDUSB/PADDUSW—Add Packed Unsigned Integers with Unsigned Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-215
PALIGNR — Packed Align Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-219
PAND—Logical AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-223
PANDN—Logical AND NOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-226
PAUSE—Spin Loop Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-229
PAVGB/PAVGW—Average Packed Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-230
PBLENDVB — Variable Blend Packed Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-234
PBLENDW — Blend Packed Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-238
PCLMULQDQ - Carry-Less Multiplication Quadword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-241
PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-244
PCMPEQQ — Compare Packed Qword Data for Equal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-250
PCMPESTRI — Packed Compare Explicit Length Strings, Return Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-253
PCMPESTRM — Packed Compare Explicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-255
PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-257
PCMPGTQ — Compare Packed Data for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-263
PCMPISTRI — Packed Compare Implicit Length Strings, Return Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-266
PCMPISTRM — Packed Compare Implicit Length Strings, Return Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-268
PDEP — Parallel Bits Deposit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-270
PEXT — Parallel Bits Extract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-272
PEXTRB/PEXTRD/PEXTRQ — Extract Byte/Dword/Qword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-274
PEXTRW—Extract Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-277
PHADDW/PHADDD — Packed Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-280
PHADDSW — Packed Horizontal Add and Saturate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-284
PHMINPOSUW — Packed Horizontal Word Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-286
PHSUBW/PHSUBD — Packed Horizontal Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-288
PHSUBSW — Packed Horizontal Subtract and Saturate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-291
PINSRB/PINSRD/PINSRQ — Insert Byte/Dword/Qword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-293
PINSRW—Insert Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-296
PMADDUBSW — Multiply and Add Packed Signed and Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-298
PMADDWD—Multiply and Add Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-301
PMAXSB/PMAXSW/PMAXSD/PMAXSQ—Maximum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-304
PMAXUB/PMAXUW—Maximum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-311
PMAXUD/PMAXUQ—Maximum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-316
PMINSB/PMINSW—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-320
PMINSD/PMINSQ—Minimum of Packed Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-325
PMINUB/PMINUW—Minimum of Packed Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-329
PMINUD/PMINUQ—Minimum of Packed Unsigned Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-334
PMOVMSKB—Move Byte Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-338
PMOVSX—Packed Move with Sign Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-340
PMOVZX—Packed Move with Zero Extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-350
PMULDQ—Multiply Packed Doubleword Integers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-359
PMULHRSW — Packed Multiply High with Round and Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-362
PMULHUW—Multiply Packed Unsigned Integers and Store High Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-366
x Vol. 2A
CONTENTS
PAGE
PMULHW—Multiply Packed Signed Integers and Store High Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-370
PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-374
PMULLW—Multiply Packed Signed Integers and Store Low Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-378
PMULUDQ—Multiply Packed Unsigned Doubleword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-382
POP—Pop a Value from the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-385
POPA/POPAD—Pop All General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-390
POPCNT — Return the Count of Number of Bits Set to 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-392
POPF/POPFD/POPFQ—Pop Stack into EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-394
POR—Bitwise Logical OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-399
PREFETCHh—Prefetch Data Into Caches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-402
PREFETCHW—Prefetch Data into Caches in Anticipation of a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-404
PREFETCHWT1—Prefetch Vector Data Into Caches with Intent to Write and T1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-406
PSADBW—Compute Sum of Absolute Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-408
PSHUFB — Packed Shuffle Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-412
PSHUFD—Shuffle Packed Doublewords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-416
PSHUFHW—Shuffle Packed High Words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-420
PSHUFLW—Shuffle Packed Low Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-423
PSHUFW—Shuffle Packed Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-426
PSIGNB/PSIGNW/PSIGND — Packed SIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-427
PSLLDQ—Shift Double Quadword Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-431
PSLLW/PSLLD/PSLLQ—Shift Packed Data Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-433
PSRAW/PSRAD/PSRAQ—Shift Packed Data Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-445
PSRLDQ—Shift Double Quadword Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-455
PSRLW/PSRLD/PSRLQ—Shift Packed Data Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-457
PSUBB/PSUBW/PSUBD—Subtract Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-469
PSUBQ—Subtract Packed Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-476
PSUBSB/PSUBSW—Subtract Packed Signed Integers with Signed Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-479
PSUBUSB/PSUBUSW—Subtract Packed Unsigned Integers with Unsigned Saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-483
PTEST- Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-487
PTWRITE - Write Data to a Processor Trace Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-489
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ— Unpack High Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-491
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ—Unpack Low Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-501
PUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-511
PUSHA/PUSHAD—Push All General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-514
PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-516
PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-518
RCL/RCR/ROL/ROR—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-521
RCPPS—Compute Reciprocals of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-526
RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-528
RDFSBASE/RDGSBASE—Read FS/GS Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-530
RDMSR—Read from Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-532
RDPID—Read Processor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-534
RDPKRU—Read Protection Key Rights for User Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-535
RDPMC—Read Performance-Monitoring Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-537
RDRAND—Read Random Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-541
RDSEED—Read Random SEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-543
RDTSC—Read Time-Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-545
RDTSCP—Read Time-Stamp Counter and Processor ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-547
REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-549
RET—Return from Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-553
RORX — Rotate Right Logical Without Affecting Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-563
ROUNDPD — Round Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-564
ROUNDPS — Round Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-567
ROUNDSD — Round Scalar Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-570
ROUNDSS — Round Scalar Single Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-572
RSM—Resume from System Management Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-574
RSQRTPS—Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . 4-576
RSQRTSS—Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . 4-578
SAHF—Store AH into Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-580
Vol. 2A xi
CONTENTS
PAGE
SAL/SAR/SHL/SHR—Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-582
SARX/SHLX/SHRX — Shift Without Affecting Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-587
SBB—Integer Subtraction with Borrow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-589
SCAS/SCASB/SCASW/SCASD—Scan String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-592
SETcc—Set Byte on Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-596
SFENCE—Store Fence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-599
SGDT—Store Global Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-600
SHA1RNDS4—Perform Four Rounds of SHA1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-602
SHA1NEXTE—Calculate SHA1 State Variable E after Four Rounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-604
SHA1MSG1—Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords . . . . . . . . . . . . . . . . . . . . .4-605
SHA1MSG2—Perform a Final Calculation for the Next Four SHA1 Message Dwords. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-606
SHA256RNDS2—Perform Two Rounds of SHA256 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-607
SHA256MSG1—Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . .4-609
SHA256MSG2—Perform a Final Calculation for the Next Four SHA256 Message Dwords . . . . . . . . . . . . . . . . . . . . . . . . .4-610
SHLD—Double Precision Shift Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-611
SHRD—Double Precision Shift Right. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-614
SHUFPD—Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . .4-617
SHUFPS—Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . .4-622
SIDT—Store Interrupt Descriptor Table Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-626
SLDT—Store Local Descriptor Table Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-628
SMSW—Store Machine Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-630
SQRTPD—Square Root of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-632
SQRTPS—Square Root of Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-635
SQRTSD—Compute Square Root of Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-638
SQRTSS—Compute Square Root of Scalar Single-Precision Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-640
STAC—Set AC Flag in EFLAGS Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-642
STC—Set Carry Flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-643
STD—Set Direction Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-644
STI—Set Interrupt Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-645
STMXCSR—Store MXCSR Register State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-647
STOS/STOSB/STOSW/STOSD/STOSQ—Store String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-648
STR—Store Task Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-652
SUB—Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-654
SUBPD—Subtract Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-656
SUBPS—Subtract Packed Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-659
SUBSD—Subtract Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-662
SUBSS—Subtract Scalar Single-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-664
SWAPGS—Swap GS Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-666
SYSCALL—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-668
SYSENTER—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-670
SYSEXIT—Fast Return from Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-673
SYSRET—Return From Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-676
TEST—Logical Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-679
TZCNT — Count the Number of Trailing Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-681
UCOMISD—Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . .4-683
UCOMISS—Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS . . . . . . . . . . . . . . . . . . . .4-685
UD2—Undefined Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-687
UNPCKHPD—Unpack and Interleave High Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . .4-688
UNPCKHPS—Unpack and Interleave High Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . .4-692
UNPCKLPD—Unpack and Interleave Low Packed Double-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . .4-696
UNPCKLPS—Unpack and Interleave Low Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . .4-700
CHAPTER 5
INSTRUCTION SET REFERENCE, V-Z
5.1
TERNARY BIT VECTOR LOGIC TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.2
INSTRUCTIONS (V-Z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
VALIGND/VALIGNQ—Align Doubleword/Quadword Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
VBLENDMPD/VBLENDMPS—Blend Float64/Float32 Vectors Using an OpMask Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
VBROADCAST—Load with Broadcast Floating-Point Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
xii Vol. 2A
CONTENTS
PAGE
VPBROADCASTM—Broadcast Mask to Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
VCOMPRESSPD—Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory. . . . . . . . . . . . . . . . . 5-21
VCOMPRESSPS—Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory . . . . . . . . . . . . . . . . . . 5-23
VCVTPD2QQ—Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers . . . . . . . . . . . . . . 5-25
VCVTPD2UDQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers . 5-28
VCVTPD2UQQ—Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers . . . 5-31
VCVTPH2PS—Convert 16-bit FP values to Single-Precision FP values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
VCVTPS2PH—Convert Single-Precision FP value to 16-bit FP value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
VCVTPS2UDQ—Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values541
VCVTPS2QQ—Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values . . 5-44
VCVTPS2UQQ—Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values5-47
VCVTQQ2PD—Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . 5-50
VCVTQQ2PS—Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . 5-52
VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer . . . . . . . . . . . . . 5-54
VCVTSS2USI—Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer . . . . . . . . . . . . . . 5-55
VCVTTPD2QQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers557
VCVTTPD2UDQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword
Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
VCVTTPD2UQQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62
VCVTTPS2UDQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword
Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-64
VCVTTPS2QQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-66
VCVTTPS2UQQ—Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68
VCVTTSD2USI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer . . . . . . . . 5-70
VCVTTSS2USI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer . . . . . . . . . 5-71
VCVTUDQ2PD—Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values . 5-73
VCVTUDQ2PS—Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values . . 5-75
VCVTUQQ2PD—Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values . . . 5-77
VCVTUQQ2PS—Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values . . . . 5-79
VCVTUSI2SD—Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
VCVTUSI2SS—Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-83
VDBPSADBW—Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes . . . . . . . . . . . . . . . . . . . . . . . . . 5-85
VEXPANDPD—Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory . . . . . . . . . . . . . . . . . . . 5-89
VEXPANDPS—Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory . . . . . . . . . . . . . . . . . . . . 5-91
VERR/VERW—Verify a Segment for Reading or Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-93
VEXP2PD—Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23
Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
VEXP2PS—Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23
Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-97
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4—Extract Packed Floating-Point
Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4—Extract packed Integer Values5106
VFIXUPIMMPD—Fix Up Special Packed Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-112
VFIXUPIMMPS—Fix Up Special Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-116
VFIXUPIMMSD—Fix Up Special Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-120
VFIXUPIMMSS—Fix Up Special Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-123
VFMADD132PD/VFMADD213PD/VFMADD231PD—Fused Multiply-Add of Packed Double-Precision Floating-Point Values5126
VFMADD132PS/VFMADD213PS/VFMADD231PS—Fused Multiply-Add of Packed Single-Precision Floating-Point Values5133
VFMADD132SD/VFMADD213SD/VFMADD231SD—Fused Multiply-Add of Scalar Double-Precision Floating-Point Values5140
VFMADD132SS/VFMADD213SS/VFMADD231SS—Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. 5Vol. 2A xiii
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143
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD—Fused Multiply-Alternating Add/Subtract of Packed DoublePrecision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-146
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS—Fused Multiply-Alternating Add/Subtract of Packed SinglePrecision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-156
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD—Fused Multiply-Alternating Subtract/Add of Packed DoublePrecision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-165
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS—Fused Multiply-Alternating Subtract/Add of Packed SinglePrecision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-175
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD—Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-185
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS—Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values
5-192
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD—Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values
5-199
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS—Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values
5-202
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD—Fused Negative Multiply-Add of Packed Double-Precision FloatingPoint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-205
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS—Fused Negative Multiply-Add of Packed Single-Precision FloatingPoint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-212
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD—Fused Negative Multiply-Add of Scalar Double-Precision FloatingPoint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-218
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS—Fused Negative Multiply-Add of Scalar Single-Precision FloatingPoint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-221
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD—Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-224
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS—Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-230
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD—Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-236
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS—Fused Negative Multiply-Subtract of Scalar Single-Precision FloatingPoint Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-239
VFPCLASSPD—Tests Types Of a Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-242
VFPCLASSPS—Tests Types Of a Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-245
VFPCLASSSD—Tests Types Of a Scalar Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-247
VFPCLASSSS—Tests Types Of a Scalar Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-249
VGATHERDPD/VGATHERQPD — Gather Packed DP FP Values Using Signed Dword/Qword Indices. . . . . . . . . . . . . . . . .5-251
VGATHERDPS/VGATHERQPS — Gather Packed SP FP values Using Signed Dword/Qword Indices. . . . . . . . . . . . . . . . . .5-256
VGATHERDPS/VGATHERDPD—Gather Packed Single, Packed Double with Signed Dword . . . . . . . . . . . . . . . . . . . . . . . . .5-261
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD—Sparse Prefetch Packed SP/DP Data Values
with Signed Dword, Signed Qword Indices Using T0 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-264
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD—Sparse Prefetch Packed SP/DP Data Values
with Signed Dword, Signed Qword Indices Using T1 Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-267
VGATHERQPS/VGATHERQPD—Gather Packed Single, Packed Double with Signed Qword Indices . . . . . . . . . . . . . . . . . .5-270
VPGATHERDD/VPGATHERQD — Gather Packed Dword Values Using Signed Dword/Qword Indices . . . . . . . . . . . . . . . .5-273
VPGATHERDD/VPGATHERDQ—Gather Packed Dword, Packed Qword with Signed Dword Indices. . . . . . . . . . . . . . . . . .5-277
VPGATHERDQ/VPGATHERQQ — Gather Packed Qword Values Using Signed Dword/Qword Indices . . . . . . . . . . . . . . . .5-280
VPGATHERQD/VPGATHERQQ—Gather Packed Dword, Packed Qword with Signed Qword Indices . . . . . . . . . . . . . . . . .5-285
VGETEXPPD—Convert Exponents of Packed DP FP Values to DP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-288
VGETEXPPS—Convert Exponents of Packed SP FP Values to SP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-291
VGETEXPSD—Convert Exponents of Scalar DP FP Values to DP FP Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-295
VGETEXPSS—Convert Exponents of Scalar SP FP Values to SP FP Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-297
VGETMANTPD—Extract Float64 Vector of Normalized Mantissas from Float64 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . .5-299
VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . .5-303
VGETMANTSD—Extract Float64 of Normalized Mantissas from Float64 Scalar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-306
VGETMANTSS—Extract Float32 Vector of Normalized Mantissa from Float32 Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-308
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4—Insert Packed Floating-Point Values.5310
xiv Vol. 2A
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VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4—Insert Packed Integer Values . . . . . . 5-314
VMASKMOV—Conditional SIMD Packed Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-318
VPBLENDD — Blend Packed Dwords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-321
VPBLENDMB/VPBLENDMW—Blend Byte/Word Vectors Using an Opmask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-323
VPBLENDMD/VPBLENDMQ—Blend Int32/Int64 Vectors Using an OpMask Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-325
VPBROADCASTB/W/D/Q—Load with Broadcast Integer Data from General Purpose Register . . . . . . . . . . . . . . . . . . . . . 5-328
VPBROADCAST—Load Integer and Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-331
VPCMPB/VPCMPUB—Compare Packed Byte Values Into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-339
VPCMPD/VPCMPUD—Compare Packed Integer Values into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-342
VPCMPQ/VPCMPUQ—Compare Packed Integer Values into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-345
VPCMPW/VPCMPUW—Compare Packed Word Values Into Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-348
VPCOMPRESSD—Store Sparse Packed Doubleword Integer Values into Dense Memory/Register . . . . . . . . . . . . . . . . . . 5-351
VPCOMPRESSQ—Store Sparse Packed Quadword Integer Values into Dense Memory/Register . . . . . . . . . . . . . . . . . . . 5-353
VPCONFLICTD/Q—Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register. 5-355
VPERM2F128 — Permute Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-358
VPERM2I128 — Permute Integer Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-360
VPERMD/VPERMW—Permute Packed Doublewords/Words Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-362
VPERMI2W/D/Q/PS/PD—Full Permute From Two Tables Overwriting the Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-365
VPERMILPD—Permute In-Lane of Pairs of Double-Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-371
VPERMILPS—Permute In-Lane of Quadruples of Single-Precision Floating-Point Values. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-376
VPERMPD—Permute Double-Precision Floating-Point Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-381
VPERMPS—Permute Single-Precision Floating-Point Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-384
VPERMQ—Qwords Element Permutation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-387
VPEXPANDD—Load Sparse Packed Doubleword Integer Values from Dense Memory / Register . . . . . . . . . . . . . . . . . . . 5-390
VPEXPANDQ—Load Sparse Packed Quadword Integer Values from Dense Memory / Register . . . . . . . . . . . . . . . . . . . . 5-392
VPLZCNTD/Q—Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values. . . . . . . . 5-394
VPMASKMOV — Conditional SIMD Integer Packed Loads and Stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-397
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q—Convert a Mask Register to a Vector Register . . . . . . . . . . . . . . 5-400
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M—Convert a Vector Register to a Mask . . . . . . . . . . . . . . . . . . . . . . 5-403
VPMOVQB/VPMOVSQB/VPMOVUSQB—Down Convert QWord to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-406
VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-410
VPMOVQD/VPMOVSQD/VPMOVUSQD—Down Convert QWord to DWord . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-414
VPMOVDB/VPMOVSDB/VPMOVUSDB—Down Convert DWord to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-418
VPMOVDW/VPMOVSDW/VPMOVUSDW—Down Convert DWord to Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-422
VPMOVWB/VPMOVSWB/VPMOVUSWB—Down Convert Word to Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-426
PROLD/PROLVD/PROLQ/PROLVQ—Bit Rotate Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-430
PRORD/PRORVD/PRORQ/PRORVQ—Bit Rotate Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-435
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ—Scatter Packed Dword, Packed Qword with Signed Dword,
Signed Qword Indices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-440
VPSLLVW/VPSLLVD/VPSLLVQ—Variable Bit Shift Left Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-445
VPSRAVW/VPSRAVD/VPSRAVQ—Variable Bit Shift Right Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-450
VPSRLVW/VPSRLVD/VPSRLVQ—Variable Bit Shift Right Logical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-455
VPTERNLOGD/VPTERNLOGQ—Bitwise Ternary Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-460
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ—Logical AND and Set Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-463
VPTESTNMB/W/D/Q—Logical NAND and Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-466
VRANGEPD—Range Restriction Calculation For Packed Pairs of Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-470
VRANGEPS—Range Restriction Calculation For Packed Pairs of Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-475
VRANGESD—Range Restriction Calculation From a pair of Scalar Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-479
VRANGESS—Range Restriction Calculation From a Pair of Scalar Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-482
VRCP14PD—Compute Approximate Reciprocals of Packed Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
VRCP14SD—Compute Approximate Reciprocal of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-487
VRCP14PS—Compute Approximate Reciprocals of Packed Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-489
VRCP14SS—Compute Approximate Reciprocal of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-491
VRCP28PD—Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-493
VRCP28SD—Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative
Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-495
VRCP28PS—Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-497
Vol. 2A xv
CONTENTS
PAGE
VRCP28SS—Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative
Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-499
VREDUCEPD—Perform Reduction Transformation on Packed Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-501
VREDUCESD—Perform a Reduction Transformation on a Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-504
VREDUCEPS—Perform Reduction Transformation on Packed Float32 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-506
VREDUCESS—Perform a Reduction Transformation on a Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-508
VRNDSCALEPD—Round Packed Float64 Values To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . .5-510
VRNDSCALESD—Round Scalar Float64 Value To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . . . .5-514
VRNDSCALEPS—Round Packed Float32 Values To Include A Given Number Of Fraction Bits . . . . . . . . . . . . . . . . . . . . . .5-516
VRNDSCALESS—Round Scalar Float32 Value To Include A Given Number Of Fraction Bits. . . . . . . . . . . . . . . . . . . . . . . . .5-519
VRSQRT14PD—Compute Approximate Reciprocals of Square Roots of Packed Float64 Values. . . . . . . . . . . . . . . . . . . .5-521
VRSQRT14SD—Compute Approximate Reciprocal of Square Root of Scalar Float64 Value . . . . . . . . . . . . . . . . . . . . . . . .5-523
VRSQRT14PS—Compute Approximate Reciprocals of Square Roots of Packed Float32 Values . . . . . . . . . . . . . . . . . . . .5-525
VRSQRT14SS—Compute Approximate Reciprocal of Square Root of Scalar Float32 Value . . . . . . . . . . . . . . . . . . . . . . . .5-527
VRSQRT28PD—Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less
Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-529
VRSQRT28SD—Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less
Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-531
VRSQRT28PS—Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less
Than 2^-28 Relative Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-533
VRSQRT28SS—Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than
2^-28 Relative Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-535
VSCALEFPD—Scale Packed Float64 Values With Float64 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-537
VSCALEFSD—Scale Scalar Float64 Values With Float64 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-540
VSCALEFPS—Scale Packed Float32 Values With Float32 Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-542
VSCALEFSS—Scale Scalar Float32 Value With Float32 Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-544
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD—Scatter Packed Single, Packed Double with Signed Dword
and Qword Indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-546
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . .5-551
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD—Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write . . . . . . . . . . . . . . . . . . . . . . . . . .5-553
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2—Shuffle Packed Values at 128-bit Granularity . . . . . . . . . . .5-555
VTESTPD/VTESTPS—Packed Bit Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-560
VZEROALL—Zero All YMM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-563
VZEROUPPER—Zero Upper Bits of YMM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-565
WAIT/FWAIT—Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-567
WBINVD—Write Back and Invalidate Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-568
WRFSBASE/WRGSBASE—Write FS/GS Segment Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-570
WRMSR—Write to Model Specific Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-572
WRPKRU—Write Data to User Page Key Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-574
XACQUIRE/XRELEASE — Hardware Lock Elision Prefix Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-575
XABORT — Transactional Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-579
XADD—Exchange and Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-581
XBEGIN — Transactional Begin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-583
XCHG—Exchange Register/Memory with Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-586
XEND — Transactional End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-588
XGETBV—Get Value of Extended Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-590
XLAT/XLATB—Table Look-up Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-592
XOR—Logical Exclusive OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-594
XORPD—Bitwise Logical XOR of Packed Double Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-596
XORPS—Bitwise Logical XOR of Packed Single Precision Floating-Point Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-599
XRSTOR—Restore Processor Extended States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-602
XRSTORS—Restore Processor Extended States Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-606
XSAVE—Save Processor Extended States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-610
XSAVEC—Save Processor Extended States with Compaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-613
XSAVEOPT—Save Processor Extended States Optimized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-616
XSAVES—Save Processor Extended States Supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-619
XSETBV—Set Extended Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-622
xvi Vol. 2A
CONTENTS
PAGE
XTEST — Test If In Transactional Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-624
CHAPTER 6
SAFER MODE EXTENSIONS REFERENCE
6.1
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2
SMX FUNCTIONALITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.1
Detecting and Enabling SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2.2
SMX Instruction Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2.1
GETSEC[CAPABILITIES] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2.2.2
GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.3
GETSEC[EXITAC]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.4
GETSEC[SENTER] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
6.2.2.5
GETSEC[SEXIT] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.6
GETSEC[PARAMETERS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.7
GETSEC[SMCTRL]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.2.8
GETSEC[WAKEUP] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.2.3
Measured Environment and SMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3
GETSEC LEAF FUNCTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
GETSEC[CAPABILITIES] - Report the SMX Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
GETSEC[ENTERACCS] - Execute Authenticated Chipset Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
GETSEC[EXITAC]—Exit Authenticated Code Execution Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
GETSEC[SENTER]—Enter a Measured Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
GETSEC[SEXIT]—Exit Measured Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
GETSEC[PARAMETERS]—Report the SMX Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
GETSEC[SMCTRL]—SMX Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
GETSEC[WAKEUP]—Wake up sleeping processors in measured environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
APPENDIX A
OPCODE MAP
A.1
USING OPCODE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2
KEY TO ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.2.1
Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
A.2.2
Codes for Operand Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-2
A.2.3
Register Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
A.2.4
Opcode Look-up Examples for One, Two, and Three-Byte Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-3
A.2.4.1
One-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.2.4.2
Two-Byte Opcode Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.2.4.3
Three-Byte Opcode Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.4.4
VEX Prefix Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.2.5
Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-6
A.3
ONE, TWO, AND THREE-BYTE OPCODE MAPS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.4
OPCODE EXTENSIONS FOR ONE-BYTE AND TWO-BYTE OPCODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.4.1
Opcode Look-up Examples Using Opcode Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.4.2
Opcode Extension Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
A.5
ESCAPE OPCODE INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.1
Opcode Look-up Examples for Escape Instruction Opcodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2
Escape Opcode Instruction Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.1
Escape Opcodes with D8 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
A.5.2.2
Escape Opcodes with D9 as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
A.5.2.3
Escape Opcodes with DA as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
A.5.2.4
Escape Opcodes with DB as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
A.5.2.5
Escape Opcodes with DC as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
A.5.2.6
Escape Opcodes with DD as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
A.5.2.7
Escape Opcodes with DE as First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
A.5.2.8
Escape Opcodes with DF As First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
APPENDIX B
INSTRUCTION FORMATS AND ENCODINGS
B.1
MACHINE INSTRUCTION FORMAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Vol. 2A xvii
CONTENTS
PAGE
B.1.1
B.1.2
B.1.3
B.1.4
B.1.4.1
B.1.4.2
B.1.4.3
B.1.4.4
B.1.4.5
B.1.4.6
B.1.4.7
B.1.4.8
B.1.5
B.2
B.2.1
B.3
B.4
B.5
B.5.1
B.5.2
B.5.3
B.6
B.7
B.8
B.9
B.9.1
B.10
B.11
B.12
B.13
B.14
B.15
B.16
B.17
B.18
B.19
Legacy Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
REX Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Opcode Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Special Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-2
Reg Field (reg) for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-3
Reg Field (reg) for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-4
Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-5
Condition Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
Other Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-6
GENERAL-PURPOSE INSTRUCTION FORMATS AND ENCODINGS FOR NON-64-BIT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
MMX INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Granularity Field (gg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
MMX Technology and General-Purpose Register Fields (mmxreg and reg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
MMX Instruction Formats and Encodings Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
PROCESSOR EXTENDED STATE INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
P6 FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
SSE INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42
SSE2 INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Granularity Field (gg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
SSE3 FORMATS AND ENCODINGS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
SSSE3 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
AESNI AND PCLMULQDQ INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-63
SPECIAL ENCODINGS FOR 64-BIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
SSE4.1 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66
SSE4.2 FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-71
AVX FORMATS AND ENCODING TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
VMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117
SMX INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-118
APPENDIX C
INTEL® C/C++ COMPILER INTRINSICS AND FUNCTIONAL EQUIVALENTS
C.1
SIMPLE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2
COMPOSITE INTRINSICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14
xviii Vol. 2A
CONTENTS
PAGE
FIGURES
Figure 1-1.
Figure 1-2.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Figure 3-14.
Figure 3-15.
Figure 3-16.
Figure 3-17.
Figure 3-18.
Figure 3-19.
Figure 3-20.
Figure 3-21.
Figure 3-22.
Figure 3-23.
Figure 3-24.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 4-14.
Figure 4-15.
Figure 4-16.
Figure 4-17.
Figure 4-18.
Figure 4-19.
Figure 4-20.
Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Syntax for CPUID, CR, and MSR Data Presentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Intel 64 and IA-32 Architectures Instruction Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table Interpretation of ModR/M Byte (C8H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Prefix Ordering in 64-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Memory Addressing Without an SIB Byte; REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Register-Register Addressing (No Memory Operand); REX.X Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Memory Addressing With a SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Instruction Encoding Format with VEX Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
VEX bit fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AVX-512 Instruction Format and the EVEX Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Bit Field Layout of the EVEX Prefix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
Bit Offset for BIT[RAX, 21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Memory Bit Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
ADDSUBPD—Packed Double-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44
ADDSUBPS—Packed Single-FP Add/Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46
Memory Layout of BNDMOV to/from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100
Version Information Returned by CPUID in EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-204
Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-206
Feature Information Returned in the EDX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-208
Determination of Support for the Processor Brand String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-217
Algorithm for Extracting Processor Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218
CVTDQ2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-229
VCVTPD2DQ (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-236
VCVTPD2PS (VEX.256 encoded version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-241
CVTPS2PD (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-250
VCVTTPD2DQ (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-266
HADDPD—Packed Double-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-427
VHADDPD operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-428
HADDPS—Packed Single-FP Horizontal Add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
VHADDPS operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-431
HSUBPD—Packed Double-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-434
VHSUBPD operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-435
HSUBPS—Packed Single-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-438
VHSUBPS operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-438
INVPCID Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-473
Operation of PCMPSTRx and PCMPESTRx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
VMOVDDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-60
MOVSHDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114
MOVSLDUP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-117
256-bit VMPSADBW Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-137
Operation of the PACKSSDW Instruction Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187
256-bit VPALIGN Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-220
PDEP Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-270
PEXT Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-272
256-bit VPHADDD Instruction Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-281
PMADDWD Execution Model Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-302
PMULHUW and PMULHW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-367
PMULLU Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-379
PSADBW Instruction Operation Using 64-bit Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-409
PSHUFB with 64-Bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-414
256-bit VPSHUFD Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-417
PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-435
PSRAW and PSRAD Instruction Operation Using a 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-447
PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-459
PUNPCKHBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-493
Vol. 2A xix
CONTENTS
PAGE
Figure 4-21.
Figure 4-22.
Figure 4-23.
Figure 4-24.
Figure 4-25.
Figure 4-26.
Figure 4-27.
Figure 4-28.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
Figure 5-15.
Figure 5-16.
Figure 5-17.
Figure 5-18.
Figure 5-19.
Figure 5-20.
Figure 5-21.
Figure 5-22.
Figure 5-23.
Figure 5-24.
Figure 5-25.
Figure 5-26.
Figure 5-27.
Figure 5-28.
Figure 5-29.
Figure A-1.
Figure B-1.
Figure B-2.
xx Vol. 2A
256-bit VPUNPCKHDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-493
PUNPCKLBW Instruction Operation Using 64-bit Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-503
256-bit VPUNPCKLDQ Instruction Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-503
Bit Control Fields of Immediate Byte for ROUNDxx Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-565
256-bit VSHUFPD Operation of Four Pairs of DP FP Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-618
256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result . . . . . . . . . . . . . 4-623
VUNPCKHPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-693
VUNPCKLPS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-701
VBROADCASTSS Operation (VEX.256 encoded version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
VBROADCASTSS Operation (VEX.128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
VBROADCASTSD Operation (VEX.256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VBROADCASTF128 Operation (VEX.256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VBROADCASTF64X4 Operation (512-bit version with writemask all 1s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
VCVTPH2PS (128-bit Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
VCVTPS2PH (128-bit Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
64-bit Super Block of SAD Operation in VDBPSADBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-86
VFIXUPIMMPD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-115
VFIXUPIMMPS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-119
VFIXUPIMMSD Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-122
VFIXUPIMMSS Immediate Control Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-125
Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-242
VGETEXPPS Functionality On Normal Input values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-292
Imm8 Controls for VGETMANTPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-299
VPBROADCASTD Operation (VEX.256 encoded version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VPBROADCASTD Operation (128-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VPBROADCASTQ Operation (256-bit version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VBROADCASTI128 Operation (256-bit version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-333
VBROADCASTI256 Operation (512-bit version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-334
VPERM2F128 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-358
VPERM2I128 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-360
VPERMILPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
VPERMILPD Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-372
VPERMILPS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-377
VPERMILPS Shuffle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-377
Imm8 Controls for VRANGEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-470
Imm8 Controls for VREDUCEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-501
Imm8 Controls for VRNDSCALEPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-511
ModR/M Byte nnn Field (Bits 5, 4, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
General Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
Hybrid Notation of VEX-Encoded Key Instruction Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
CONTENTS
PAGE
TABLES
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-6.
Table 2-5.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 2-14.
Table 2-15.
Table 2-16.
Table 2-17.
Table 2-18.
Table 2-19.
Table 2-20.
Table 2-21.
Table 2-22.
Table 2-23.
Table 2-24.
Table 2-25.
Table 2-26.
Table 2-27.
Table 2-28.
Table 2-29.
Table 2-30.
Table 2-31.
Table 2-32.
Table 2-33.
Table 2-34.
Table 2-35.
Table 2-36.
Table 2-37.
Table 2-38.
Table 2-39.
Table 2-40.
Table 2-41.
Table 2-42.
Table 2-43.
Table 2-44.
Table 2-45.
Table 2-46.
Table 2-47.
Table 2-48.
Table 2-49.
Table 2-50.
Table 2-51.
Table 2-52.
Table 2-53.
Table 2-54.
Table 2-55.
Table 2-56.
Table 2-57.
16-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
32-Bit Addressing Forms with the ModR/M Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
32-Bit Addressing Forms with the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7
REX Prefix Fields [BITS: 0100WRXB] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Direct Memory Offset Form of MOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Special Cases of REX Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
RIP-Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VEX.vvvv to register name mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Instructions with a VEX.vvvv destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
VEX.m-mmmm interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VEX.L interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
VEX.pp interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
32-Bit VSIB Addressing Forms of the SIB Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Exception class description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Instructions in each Exception Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
#UD Exception and VEX.W=1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
#UD Exception and VEX.L Field Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Type 1 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Type 2 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Type 3 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Type 4 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Type 5 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
Type 6 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
Type 7 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Type 8 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32
Type 11 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Type 12 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
VEX-Encoded GPR Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Exception Definition (VEX-Encoded GPR Instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
EVEX Prefix Bit Field Functional Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
EVEX Encoding Register Specifiers in 32-bit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Opmask Register Specifier Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Compressed Displacement (DISP8*N) Affected by Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
EVEX DISP8*N for Instructions Not Affected by Embedded Broadcast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
OS XSAVE Enabling Requirements of Instruction Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Opcode Independent, State Dependent EVEX Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
#UD Conditions of Operand-Encoding EVEX Prefix Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
#UD Conditions of Opmask Related Encoding Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
#UD Conditions Dependent on EVEX.b Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
EVEX-Encoded Instruction Exception Class Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
EVEX Instructions in each Exception Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45
Type E1 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
Type E1NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Type E2 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Type E3 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
Type E3NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
Type E4 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Type E4NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
Type E5 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55
Type E5NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56
Type E6 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Type E6NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Type E7NM Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Type E9 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-60
Type E9NF Class Exception Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Vol. 2A xxi
CONTENTS
PAGE
Table 2-58.
Table 2-59.
Table 2-60.
Table 2-61.
Table 2-62.
Table 2-63.
Table 2-64.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-8.
Table 3-9.
Table 3-10.
Table 3-11.
Table 3-12.
Table 3-13.
Table 3-14.
Table 3-15.
Table 3-16.
Table 3-17.
Table 3-18.
Table 3-19.
Table 3-20.
Table 3-21.
Table 3-22.
Table 3-23.
Table 3-24.
Table 3-25.
Table 3-26.
Table 3-27.
Table 3-28.
Table 3-29.
Table 3-30.
Table 3-31.
Table 3-32.
Table 3-33.
Table 3-34.
Table 3-35.
Table 3-36.
Table 3-37.
Table 3-38.
Table 3-39.
Table 3-40.
Table 3-41.
Table 3-42.
Table 3-43.
xxii Vol. 2A
Type E10 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
Type E10NF Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63
Type E11 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64
Type E12 Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
Type E12NP Class Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg) . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory) . . . . . . . . . . . . . . . . . . . . . . . 2-68
Register Codes Associated With +rb, +rw, +rd, +ro. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Range of Bit Positions Specified by Bit Offset Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Standard and Non-standard Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Intel 64 and IA-32 General Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
x87 FPU Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
SIMD Floating-Point Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Decision Table for CLI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143
Comparison Predicate for CMPPD and CMPPS Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156
Pseudo-Op and CMPPD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157
Pseudo-Op and VCMPPD Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158
Pseudo-Op and CMPPS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-163
Pseudo-Op and VCMPPS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164
Pseudo-Op and CMPSD Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174
Pseudo-Op and VCMPSD Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-174
Pseudo-Op and CMPSS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Pseudo-Op and VCMPSS Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-178
Information Returned by CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-191
Processor Type Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-205
Feature Information Returned in the ECX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-206
More on Feature Information Returned in the EDX Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-209
Encoding of CPUID Leaf 2 Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-211
Processor Brand String Returned with Pentium 4 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-218
Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-219
DIV Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-285
Results Obtained from F2XM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-309
Results Obtained from FABS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-311
FADD/FADDP/FIADD Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-313
FBSTP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-317
FCHS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-319
FCOM/FCOMP/FCOMPP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-325
FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-328
FCOS Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-331
FDIV/FDIVP/FIDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-335
FDIVR/FDIVRP/FIDIVR Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-338
FICOM/FICOMP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-341
FIST/FISTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348
FISTTP Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-351
FMUL/FMULP/FIMUL Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-362
FPATAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-365
FPREM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-367
FPREM1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-369
FPTAN Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-371
FSCALE Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-379
FSIN Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-381
FSINCOS Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-383
FSQRT Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-385
FSUB/FSUBP/FISUB Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-396
FSUBR/FSUBRP/FISUBR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-399
FTST Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-401
FUCOM/FUCOMP/FUCOMPP Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-403
FXAM Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406
Non-64-bit-Mode Layout of FXSAVE and FXRSTOR
CONTENTS
PAGE
Table 3-44.
Table 3-45.
Table 3-46.
Table 3-47.
Table 3-48.
Table 3-49.
Table 3-50.
Table 3-51.
Table 3-52.
Table 3-53.
Table 3-54.
Table 3-55.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 4-5.
Table 4-6.
Table 4-7.
Table 4-8.
Table 4-9.
Table 4-10.
Table 4-11.
Table 4-12.
Table 4-13.
Table 4-14.
Table 4-15.
Table 4-16.
Table 4-17.
Table 4-18.
Table 4-19.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 5-10.
Table 5-11.
Table 5-12.
Table 5-13.
Table 5-14.
Table 5-15.
Table 5-16.
Table 5-17.
Table 5-18.
Table 5-19.
Table 5-20.
Table 5-21.
Table 5-22.
Table 5-23.
Table 5-24.
Table 5-25.
Table 5-26.
Memory Region3-413
Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-414
Recreating FSAVE Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-416
Layout of the 64-bit-mode FXSAVE64 Map
(requires REX.W = 1)3-417
Layout of the 64-bit-mode FXSAVE Map (REX.W = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-418
FYL2X Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-423
FYL2XP1 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-425
IDIV Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-440
Decision Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-458
Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-516
Non-64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-525
64-bit Mode LEA Operation with Address and Operand Size Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-525
Segment and Gate Descriptor Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-545
Source Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Aggregation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Aggregation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Comparison Result for Each Element Pair BoolRes[i.j] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Summary of Imm8 Control Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
MUL Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144
MWAIT Extension Register (ECX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-159
MWAIT Hints Register (EAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-159
Recommended Multi-Byte Sequence of NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-163
PCLMULQDQ Quadword Selection of Immediate Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Pseudo-Op and PCLMULQDQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-241
Effect of POPF/POPFD on the EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-395
Valid General and Special Purpose Performance Counter Index Range for RDPMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-537
Repeat Prefixes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-550
Rounding Modes and Encoding of Rounding Control (RC) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-565
Decision Table for STI Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-645
Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
Low 8 columns of the 16x16 Map of VPTERNLOG Boolean Logic Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38
Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-96
Special Values Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-98
Classifier Operations for VFPCLASSPD/SD/PS/SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-242
VGETEXPPD/SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-288
VGETEXPPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-291
GetMant() Special Float Values Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-300
Pseudo-Op and VPCMP* Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-340
Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-461
Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2] . . . . . . . . . . . . . . . . . 5-471
Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS . . . . . . . . . . . . . . . . . . . . 5-471
Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0). . . . . . . . . . . . 5-471
VRCP14PD/VRCP14SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-485
VRCP14PS/VRCP14SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-489
VRCP28PD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-494
VRCP28SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-496
VRCP28PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-498
VRCP28SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-500
VREDUCEPD/SD/PS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-502
VRNDSCALEPD/SD/PS/SS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-511
VRSQRT14PD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-522
VRSQRT14SD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-524
VRSQRT14PS Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-526
VRSQRT14SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-528
Vol. 2A xxiii
CONTENTS
PAGE
Table 5-27.
Table 5-28.
Table 5-29.
Table 5-30.
Table 5-31.
Table 5-32.
Table 5-33.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 6-5.
Table 6-6.
Table 6-7.
Table 6-8.
Table 6-9.
Table 6-10.
Table 6-11.
Table 6-12.
Table A-1.
Table A-2.
Table A-3.
Table A-4.
Table A-5.
Table A-6.
Table A-7.
Table A-8.
Table A-9.
Table A-10.
Table A-11.
Table A-12.
Table A-13.
Table A-14.
Table A-15.
Table A-16.
Table A-17.
Table A-18.
Table A-19.
Table A-20.
Table A-21.
Table A-22.
Table B-1.
Table B-2.
Table B-3.
Table B-4.
Table B-5.
Table B-6.
Table B-7.
Table B-8.
Table B-9.
Table B-10.
Table B-11.
Table B-13.
Table B-12.
Table B-14.
Table B-15.
Table B-16.
Table B-17.
Table B-18.
xxiv Vol. 2A
VRSQRT28PD Special Cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-530
VRSQRT28SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-532
VRSQRT28PS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-534
VRSQRT28SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-536
\VSCALEFPD/SD/PS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-537
Additional VSCALEFPD/SD Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-538
Additional VSCALEFPS/SS Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-542
Layout of IA32_FEATURE_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
GETSEC Leaf Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Getsec Capability Result Encoding (EBX = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Register State Initialization after GETSEC[ENTERACCS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
IA32_MISC_ENABLE MSR Initialization by ENTERACCS and SENTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
Register State Initialization after GETSEC[SENTER] and GETSEC[WAKEUP]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
SMX Reporting Parameters Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
TXT Feature Extensions Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
External Memory Types Using Parameter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Default Parameter Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Supported Actions for GETSEC[SMCTRL(0)] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
RLP MVMM JOIN Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Superscripts Utilized in Opcode Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6
One-byte Opcode Map: (00H — F7H) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7
Two-byte Opcode Map: 00H — 77H (First Byte is 0FH) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
Three-byte Opcode Map: 00H — F7H (First Two Bytes are 0F 38H) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-13
Three-byte Opcode Map: 00H — F7H (First two bytes are 0F 3AH) * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-15
Opcode Extensions for One- and Two-byte Opcodes by Group Number * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-18
D8 Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
D8 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
D9 Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
D9 Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
DA Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-22
DA Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
DB Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-23
DB Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
DC Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
DC Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
DD Opcode Map When ModR/M Byte is Within 00H to BFH *. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
DD Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
DE Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-26
DE Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
DF Opcode Map When ModR/M Byte is Within 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-27
DF Opcode Map When ModR/M Byte is Outside 00H to BFH * . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-28
Special Fields Within Instruction Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Encoding of reg Field When w Field is Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Encoding of reg Field When w Field is Not Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of reg Field When w Field is Present in Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of Operand Size (w) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
Encoding of Sign-Extend (s) Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of the Segment Register (sreg) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of Special-Purpose Register (eee) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5
Encoding of Conditional Test (tttn) Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
Encoding of Operation Direction (d) Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6
General Purpose Instruction Formats and Encodings for Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Notes on Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-7
Special Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-18
Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Pentium Processor Family Instruction Formats and Encodings, 64-Bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-37
Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
CONTENTS
PAGE
Table B-19.
Table B-20.
Table B-21.
Table B-22.
Table B-23.
Table B-25.
Table B-24.
Table B-26.
Table B-27.
Table B-28.
Table B-29.
Table B-30.
Table B-31.
Table B-32.
Table B-33.
Table B-34.
Table B-35.
Table B-36.
Table B-37.
Table B-38.
Table B-39.
Table B-40.
Table B-41.
Table C-1.
Table C-2.
MMX Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-38
Formats and Encodings of XSAVE/XRSTOR/XGETBV/XSETBV Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Formats and Encodings of P6 Family Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-41
Formats and Encodings of SSE Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42
Formats and Encodings of SSE Integer Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-47
Encoding of Granularity of Data Field (gg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Format and Encoding of SSE Cacheability & Memory Ordering Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48
Formats and Encodings of SSE2 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-49
Formats and Encodings of SSE2 Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54
Format and Encoding of SSE2 Cacheability Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-58
Formats and Encodings of SSE3 Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Formats and Encodings for SSE3 Event Management Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-59
Formats and Encodings for SSE3 Integer and Move Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Formats and Encodings for SSSE3 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-60
Formats and Encodings of AESNI and PCLMULQDQ Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-63
Special Case Instructions Promoted Using REX.W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-64
Encodings of SSE4.1 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66
Encodings of SSE4.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-72
Encodings of AVX instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-73
General Floating-Point Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113
Encodings for VMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-117
Encodings for SMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-118
Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
Composite Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-14
Vol. 2A xxv
CONTENTS
PAGE
xxvi Vol. 2A
CHAPTER 1
ABOUT THIS MANUAL
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018 and 334569) are part of a set that describes the architecture
and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set are:
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (Order
Number 253665).
•
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D: System
Programming Guide (order numbers 253668, 253669, 326019 and 332831).
The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C & 2D, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers who write operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers. In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B, addresses the programming environment for classes of software that host operating systems.
1.1
INTEL® 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
This manual set includes information pertaining primarily to the most recent Intel 64 and IA-32 processors, which
include:
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Pentium® processors
P6 family processors
Pentium® 4 processors
Pentium® M processors
Intel® Xeon® processors
Pentium® D processors
Pentium® processor Extreme Editions
64-bit Intel® Xeon® processors
Intel® Core™ Duo processor
Intel® Core™ Solo processor
Dual-Core Intel® Xeon® processor LV
Intel® Core™2 Duo processor
Intel® Core™2 Quad processor Q6000 series
Intel® Xeon® processor 3000, 3200 series
Intel® Xeon® processor 5000 series
Intel® Xeon® processor 5100, 5300 series
Intel® Core™2 Extreme processor X7000 and X6800 series
Intel® Core™2 Extreme processor QX6000 series
Intel® Xeon® processor 7100 series
Intel® Pentium® Dual-Core processor
Intel® Xeon® processor 7200, 7300 series
Intel® Xeon® processor 5200, 5400, 7400 series
Vol. 2A 1-1
ABOUT THIS MANUAL
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•
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Intel® Core™2 Extreme processor QX9000 and X9000 series
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Intel® Core™ i7 processor
Intel® Core™2 Quad processor Q9000 series
Intel® Core™2 Duo processor E8000, T9000 series
Intel® Atom™ processor family
Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are built from 45 nm and 32 nm processes
Intel® Core™ i5 processor
Intel® Xeon® processor E7-8800/4800/2800 product families
Intel® Core™ i7-3930K processor
2nd generation Intel® Core™ i7-2xxx, Intel® Core™ i5-2xxx, Intel® Core™ i3-2xxx processor series
Intel® Xeon® processor E3-1200 product family
Intel® Xeon® processor E5-2400/1400 product family
Intel® Xeon® processor E5-4600/2600/1600 product family
3rd generation Intel® Core™ processors
Intel® Xeon® processor E3-1200 v2 product family
Intel® Xeon® processor E5-2400/1400 v2 product families
Intel® Xeon® processor E5-4600/2600/1600 v2 product families
Intel® Xeon® processor E7-8800/4800/2800 v2 product families
4th generation Intel® Core™ processors
The Intel® Core™ M processor family
Intel® Core™ i7-59xx Processor Extreme Edition
Intel® Core™ i7-49xx Processor Extreme Edition
Intel® Xeon® processor E3-1200 v3 product family
Intel® Xeon® processor E5-2600/1600 v3 product families
5th generation Intel® Core™ processors
Intel® Xeon® processor D-1500 product family
Intel® Xeon® processor E5 v4 family
Intel® Atom™ processor X7-Z8000 and X5-Z8000 series
Intel® Atom™ processor Z3400 series
Intel® Atom™ processor Z3500 series
6th generation Intel® Core™ processors
Intel® Xeon® processor E3-1500m v5 product family
P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium®
Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors.
The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture. Intel Xeon
processor 5000, 7100 series are based on the Intel NetBurst® microarchitecture.
The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LV are based on an improved
Pentium® M processor microarchitecture.
The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel® Pentium® dual-core, Intel®
Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2 Extreme processors are based on Intel® Core™ microarchitecture.
1-2 Vol. 2A
ABOUT THIS MANUAL
The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® Core™2 Quad processor Q9000 series, and Intel®
Core™2 Extreme processors QX9000, X9000 series, Intel® Core™2 processor E8000 series are based on Enhanced
Intel® Core™ microarchitecture.
The Intel® Atom™ processors 200, 300, D400, D500, D2000, N200, N400, N2000, E2000, Z500, Z600, Z2000,
C1000 series are based on the Intel® Atom™ microarchitecture and supports Intel 64 architecture.
The Intel® Core™ i7 processor and Intel® Xeon® processor 3400, 5500, 7500 series are based on 45 nm Intel®
microarchitecture code name Nehalem. Intel® microarchitecture code name Westmere is a 32 nm version of Intel®
microarchitecture code name Nehalem. Intel® Xeon® processor 5600 series, Intel Xeon processor E7 and various
Intel Core i7, i5, i3 processors are based on Intel® microarchitecture code name Westmere. These processors
support Intel 64 architecture.
The Intel® Xeon® processor E5 family, Intel® Xeon® processor E3-1200 family, Intel® Xeon® processor E78800/4800/2800 product families, Intel® Core™ i7-3930K processor, and 2nd generation Intel® Core™ i7-2xxx,
Intel® CoreTM i5-2xxx, Intel® Core™ i3-2xxx processor series are based on the Intel® microarchitecture code name
Sandy Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E7-8800/4800/2800 v2 product families, Intel® Xeon® processor E3-1200 v2 product
family and 3rd generation Intel® Core™ processors are based on the Intel® microarchitecture code name Ivy
Bridge and support Intel 64 architecture.
The Intel® Xeon® processor E5-4600/2600/1600 v2 product families, Intel® Xeon® processor E5-2400/1400 v2
product families and Intel® Core™ i7-49xx Processor Extreme Edition are based on the Intel® microarchitecture
code name Ivy Bridge-E and support Intel 64 architecture.
The Intel® Xeon® processor E3-1200 v3 product family and 4th Generation Intel® Core™ processors are based on
the Intel® microarchitecture code name Haswell and support Intel 64 architecture.
The Intel® Core™ M processor family, 5th generation Intel® Core™ processors, Intel® Xeon® processor D-1500
product family and the Intel® Xeon® processor E5 v4 family are based on the Intel® microarchitecture code name
Broadwell and support Intel 64 architecture.
The Intel® Xeon® processor E3-1500m v5 product family and 6th generation Intel® Core™ processors are based
on the Intel® microarchitecture code name Skylake and support Intel 64 architecture.
The Intel® Xeon® processor E5-2600/1600 v3 product families and the Intel® Core™ i7-59xx Processor Extreme
Edition are based on the Intel® microarchitecture code name Haswell-E and support Intel 64 architecture.
The Intel® Atom™ processor Z8000 series is based on the Intel microarchitecture code name Airmont.
The Intel® Atom™ processor Z3400 series and the Intel® Atom™ processor Z3500 series are based on the Intel
microarchitecture code name Silvermont.
P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-core Intel® Xeon® processor LV,
and early generations of Pentium 4 and Intel Xeon processors support IA-32 architecture. The Intel® AtomTM
processor Z5xx series support IA-32 architecture.
The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100, 7200, 7300, 7400 series, Intel®
Core™2 Duo, Intel® Core™2 Extreme, Intel® Core™2 Quad processors, Pentium® D processors, Pentium® DualCore processor, newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64 architecture.
IA-32 architecture is the instruction set architecture and programming environment for Intel's 32-bit microprocessors. Intel® 64 architecture is the instruction set architecture and programming environment which is the superset
of Intel’s 32-bit and 64-bit architectures. It is compatible with the IA-32 architecture.
1.2
OVERVIEW OF VOLUME 2A, 2B, 2C AND 2D: INSTRUCTION SET REFERENCE
A description of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C & 2D content
follows:
Chapter 1 — About This Manual. Gives an overview of all seven volumes of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. It also describes the notational conventions in these manuals and lists related
Intel® manuals and documentation of interest to programmers and hardware designers.
Vol. 2A 1-3
ABOUT THIS MANUAL
Chapter 2 — Instruction Format. Describes the machine-level instruction format used for all IA-32 instructions
and gives the allowable encodings of prefixes, the operand-identifier byte (ModR/M byte), the addressing-mode
specifier byte (SIB byte), and the displacement and immediate bytes.
Chapter 3 — Instruction Set Reference, A-L. Describes Intel 64 and IA-32 instructions in detail, including an
algorithmic description of operations, the effect on flags, the effect of operand- and address-size attributes, and
the exceptions that may be generated. The instructions are arranged in alphabetical order. General-purpose, x87
FPU, Intel MMX™ technology, SSE/SSE2/SSE3/SSSE3/SSE4 extensions, and system instructions are included.
Chapter 4 — Instruction Set Reference, M-U. Continues the description of Intel 64 and IA-32 instructions
started in Chapter 3. It starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
Chapter 5 — Instruction Set Reference, V-Z. Continues the description of Intel 64 and IA-32 instructions
started in chapters 3 and 4. It provides the balance of the alphabetized list of instructions and starts Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2C.
Chapter 6— Safer Mode Extensions Reference. Describes the safer mode extensions (SMX). SMX is intended
for a system executive to support launching a measured environment in a platform where the identity of the software controlling the platform hardware can be measured for the purpose of making trust decisions. This chapter
starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2D.
Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.
Appendix B — Instruction Formats and Encodings. Gives the binary encoding of each form of each IA-32
instruction.
Appendix C — Intel® C/C++ Compiler Intrinsics and Functional Equivalents. Lists the Intel® C/C++ compiler
intrinsics and their assembly code equivalents for each of the IA-32 MMX and SSE/SSE2/SSE3 instructions.
1.3
NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for
hexadecimal and binary numbers. A review of this notation makes the manual easier to read.
1.3.1
Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the bottom of the figure; addresses
increase toward the top. Bit positions are numbered from right to left. The numerical value of a set bit is equal to
two raised to the power of the bit position. IA-32 processors are “little endian” machines; this means the bytes of
a word are numbered starting from the least significant byte. Figure 1-1 illustrates these conventions.
Highest
Address 31
24 23
Byte 3
Data Structure
8 7
16 15
Byte 2
Byte 1
0
Byte 0
Bit offset
28
24
20
16
12
8
4
0
Byte Offset
Figure 1-1. Bit and Byte Order
1-4 Vol. 2A
Lowest
Address
ABOUT THIS MANUAL
1.3.2
Reserved Bits and Software Compatibility
In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as
reserved, it is essential for compatibility with future processors that software treat these bits as having a future,
though unknown, effect. The behavior of reserved bits should be regarded as not only undefined, but unpredictable. Software should follow these guidelines in dealing with reserved bits:
•
Do not depend on the states of any reserved bits when testing the values of registers which contain such bits.
Mask out the reserved bits before testing.
•
•
•
Do not depend on the states of any reserved bits when storing to memory or to a register.
Do not depend on the ability to retain information written into any reserved bits.
When loading a register, always load the reserved bits with the values indicated in the documentation, if any,
or reload them with values previously read from the same register.
NOTE
Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon
the values of reserved register bits will make software dependent upon the unspecified manner in
which the processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.
1.3.3
Instruction Operands
When instructions are represented symbolically, a subset of the IA-32 assembly language is used. In this subset,
an instruction has the following format:
label: mnemonic argument1, argument2, argument3
where:
•
•
•
A label is an identifier which is followed by a colon.
A mnemonic is a reserved name for a class of instruction opcodes which have the same function.
The operands argument1, argument2, and argument3 are optional. There may be from zero to three operands,
depending on the opcode. When present, they take the form of either literals or identifiers for data items.
Operand identifiers are either reserved names of registers or are assumed to be assigned to data items
declared in another part of the program (which may not be shown in the example).
When two operands are present in an arithmetic or logical instruction, the right operand is the source and the left
operand is the destination.
For example:
LOADREG: MOV EAX, SUBTOTAL
In this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode, EAX is the destination operand,
and SUBTOTAL is the source operand. Some assembly languages put the source and destination in reverse order.
1.3.4
Hexadecimal and Binary Numbers
Base 16 (hexadecimal) numbers are represented by a string of hexadecimal digits followed by the character H (for
example, F82EH). A hexadecimal digit is a character from the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D,
E, and F.
Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for
example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might
arise.
Vol. 2A 1-5
ABOUT THIS MANUAL
1.3.5
Segmented Addressing
The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes.
Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes in memory. The
range of memory that can be addressed is called an address space.
The processor also supports segmented addressing. This is a form of addressing where a program may have many
independent address spaces, called segments. For example, a program can keep its code (instructions) and stack
in separate segments. Code addresses would always refer to the code space, and stack addresses would always
refer to the stack space. The following notation is used to specify a byte address within a segment:
Segment-register:Byte-address
For example, the following segment address identifies the byte at address FF79H in the segment pointed by the DS
register:
DS:FF79H
The following segment address identifies an instruction address in the code segment. The CS register points to the
code segment and the EIP register contains the address of the instruction.
CS:EIP
1.3.6
Exceptions
An exception is an event that typically occurs when an instruction causes an error. For example, an attempt to
divide by zero generates an exception. However, some exceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about the
error. An example of the notation used to show an exception and error code is shown below:
#PF(fault code)
This example refers to a page-fault exception under conditions where an error code naming a type of fault is
reported. Under some conditions, exceptions which produce error codes may not be able to report an accurate
code. In this case, the error code is zero, as shown below for a general-protection exception:
#GP(0)
1.3.7
A New Syntax for CPUID, CR, and MSR Values
Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register
bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information.
See Figure 1-2.
1-6 Vol. 2A
ABOUT THIS MANUAL
CPUID Input and Output
CPUID.01H:ECX.SSE[bit 25] = 1
Input value for EAX register
Output register and feature flag or field
name with bit position(s)
Value (or range) of output
Control Register Values
CR4.OSFXSR[bit 9] = 1
Example CR name
Feature flag or field name
with bit position(s)
Value (or range) of output
Model-Specific Register Values
IA32_MISC_ENABLE.ENABLEFOPCODE[bit 2] = 1
Example MSR name
Feature flag or field name with bit position(s)
Value (or range) of output
SDM20002
Figure 1-2. Syntax for CPUID, CR, and MSR Data Presentation
1.4
RELATED LITERATURE
Literature related to Intel 64 and IA-32 processors is listed and viewable on-line at:
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
See also:
•
•
•
The data sheet for a particular Intel 64 or IA-32 processor
•
Intel® Fortran Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
The specification update for a particular Intel 64 or IA-32 processor
Intel® C++ Compiler documentation and online help:
http://software.intel.com/en-us/articles/intel-compilers/
Vol. 2A 1-7
ABOUT THIS MANUAL
•
Intel® Software Development Tools:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® 64 and IA-32 Architectures Software Developer’s Manual (in three or seven volumes):
http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
•
Intel® 64 and IA-32 Architectures Optimization Reference Manual:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimizationmanual.html
•
Intel 64 Architecture x2APIC Specification:
http://www.intel.com/content/www/us/en/architecture-and-technology/64-architecture-x2apic-specification.html
•
Intel® Trusted Execution Technology Measured Launched Environment Programming Guide:
http://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
•
Developing Multi-threaded Applications: A Platform Consistent Approach:
https://software.intel.com/sites/default/files/article/147714/51534-developing-multithreaded-applications.pdf
•
Using Spin-Loops on Intel® Pentium® 4 Processor and Intel® Xeon® Processor:
http://software.intel.com/en-us/articles/ap949-using-spin-loops-on-intel-pentiumr-4-processor-and-intelxeonr-processor/
•
Performance Monitoring Unit Sharing Guide
http://software.intel.com/file/30388
Literature related to selected features in future Intel processors are available at:
•
Intel® Architecture Instruction Set Extensions Programming Reference
https://software.intel.com/en-us/isa-extensions
•
Intel® Software Guard Extensions (Intel® SGX) Programming Reference
https://software.intel.com/en-us/isa-extensions/intel-sgx
More relevant links are:
•
Intel® Developer Zone:
•
Developer centers:
https://software.intel.com/en-us
http://www.intel.com/content/www/us/en/hardware-developers/developer-centers.html
•
Processor support general link:
http://www.intel.com/support/processors/
•
Software products and packages:
http://www.intel.com/cd/software/products/asmo-na/eng/index.htm
•
Intel® Hyper-Threading Technology (Intel® HT Technology):
http://www.intel.com/technology/platform-technology/hyper-threading/index.htm
1-8 Vol. 2A
CHAPTER 2
INSTRUCTION FORMAT
This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for
protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for
IA-32e mode and its sub-modes are described in Section 2.2.
2.1
INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE,
AND VIRTUAL-8086 MODE
The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an
addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base)
byte, a displacement (if required), and an immediate data field (if required).
Instruction
Prefixes
Opcode
ModR/M
SIB
Prefixes of
1-, 2-, or 3-byte 1 byte
1 byte each opcode
(if required)
(optional)1, 2
7
6 5
Mod
3 2
Reg/
Opcode
0
R/M
1 byte
(if required)
7
Immediate
Address
displacement
of 1, 2, or 4
bytes or none3
Immediate
data of
1, 2, or 4
bytes or none3
3 2
6 5
Scale
Displacement
Index
0
Base
1. The REX prefix is optional, but if used must be immediately before the opcode; see Section
2.2.1, “REX Prefixes” for additional information.
2. For VEX encoding information, see Section 2.3, “Intel® Advanced Vector Extensions (Intel®
AVX)”.
3. Some rare instructions can take an 8B immediate or 8B displacement.
Figure 2-1. Intel 64 and IA-32 Architectures Instruction Format
2.1.1
Instruction Prefixes
Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, it
is only useful to include up to one prefix code from each of the four groups (Groups 1, 2, 3, 4). Groups 1 through 4
may be placed in any order relative to each other.
•
Group 1
— Lock and repeat prefixes:
•
•
•
LOCK prefix is encoded using F0H.
REPNE/REPNZ prefix is encoded using F2H. Repeat-Not-Zero prefix applies only to string and
input/output instructions. (F2H is also used as a mandatory prefix for some instructions.)
REP or REPE/REPZ is encoded using F3H. The repeat prefix applies only to string and input/output
instructions. F3H is also used as a mandatory prefix for POPCNT, LZCNT and ADOX instructions.
— Bound prefix is encoded using F2H if the following conditions are true:
•
CPUID.(EAX=07H, ECX=0):EBX.MPX[bit 14] is set.
Vol. 2A 2-1
INSTRUCTION FORMAT
•
•
•
BNDCFGU.EN and/or IA32_BNDCFGS.EN is set.
When the F2 prefix precedes a near CALL, a near RET, a near JMP, or a near Jcc instruction (see Chapter
17, “Intel® MPX,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1).
Group 2
— Segment override prefixes:
•
•
•
•
•
•
2EH—CS segment override (use with any branch instruction is reserved).
36H—SS segment override prefix (use with any branch instruction is reserved).
3EH—DS segment override prefix (use with any branch instruction is reserved).
26H—ES segment override prefix (use with any branch instruction is reserved).
64H—FS segment override prefix (use with any branch instruction is reserved).
65H—GS segment override prefix (use with any branch instruction is reserved).
— Branch hints1:
•
•
•
3EH—Branch taken (used only with Jcc instructions).
Group 3
•
•
2EH—Branch not taken (used only with Jcc instructions).
Operand-size override prefix is encoded using 66H (66H is also used as a mandatory prefix for some
instructions).
Group 4
•
67H—Address-size override prefix.
The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor environment. See “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction Set Reference, A-L,” for a description
of this prefix.
Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of a string. Use these prefixes
only with string and I/O instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS). Use of repeat prefixes
and/or undefined opcodes with other Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable
behavior.
Some instructions may use F2H,F3H as a mandatory prefix to express distinct functionality.
Branch hint prefixes (2EH, 3EH) allow a program to give a hint to the processor about the most likely code path for
a branch. Use these prefixes only with conditional branch instructions (Jcc). Other use of branch hint prefixes
and/or other undefined opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable
behavior.
The operand-size override prefix allows a program to switch between 16- and 32-bit operand sizes. Either size can
be the default; use of the prefix selects the non-default size.
Some SSE2/SSE3/SSSE3/SSE4 instructions and instructions using a three-byte sequence of primary opcode bytes
may use 66H as a mandatory prefix to express distinct functionality.
Other use of the 66H prefix is reserved; such use may cause unpredictable behavior.
The address-size override prefix (67H) allows programs to switch between 16- and 32-bit addressing. Either size
can be the default; the prefix selects the non-default size. Using this prefix and/or other undefined opcodes when
operands for the instruction do not reside in memory is reserved; such use may cause unpredictable behavior.
1. Some earlier microarchitectures used these as branch hints, but recent generations have not and they are reserved for future hint
usage.
2-2 Vol. 2A
INSTRUCTION FORMAT
2.1.2
Opcodes
A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is sometimes encoded in the
ModR/M byte. Smaller fields can be defined within the primary opcode. Such fields define the direction of operation, size of displacements, register encoding, condition codes, or sign extension. Encoding fields used by an
opcode vary depending on the class of operation.
Two-byte opcode formats for general-purpose and SIMD instructions consist of one of the following:
•
•
An escape opcode byte 0FH as the primary opcode and a second opcode byte.
A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a second opcode byte (same as previous
bullet).
For example, CVTDQ2PD consists of the following sequence: F3 0F E6. The first byte is a mandatory prefix (it is not
considered as a repeat prefix).
Three-byte opcode formats for general-purpose and SIMD instructions consist of one of the following:
•
•
An escape opcode byte 0FH as the primary opcode, plus two additional opcode bytes.
A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, plus two additional opcode bytes (same as
previous bullet).
For example, PHADDW for XMM registers consists of the following sequence: 66 0F 38 01. The first byte is the
mandatory prefix.
Valid opcode expressions are defined in Appendix A and Appendix B.
2.1.3
ModR/M and SIB Bytes
Many instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M
byte) following the primary opcode. The ModR/M byte contains three fields of information:
•
•
The mod field combines with the r/m field to form 32 possible values: eight registers and 24 addressing modes.
•
The r/m field can specify a register as an operand or it can be combined with the mod field to encode an
addressing mode. Sometimes, certain combinations of the mod field and the r/m field are used to express
opcode information for some instructions.
The reg/opcode field specifies either a register number or three more bits of opcode information. The purpose
of the reg/opcode field is specified in the primary opcode.
Certain encodings of the ModR/M byte require a second addressing byte (the SIB byte). The base-plus-index and
scale-plus-index forms of 32-bit addressing require the SIB byte. The SIB byte includes the following fields:
•
•
•
The scale field specifies the scale factor.
The index field specifies the register number of the index register.
The base field specifies the register number of the base register.
See Section 2.1.5 for the encodings of the ModR/M and SIB bytes.
2.1.4
Displacement and Immediate Bytes
Some addressing forms include a displacement immediately following the ModR/M byte (or the SIB byte if one is
present). If a displacement is required, it can be 1, 2, or 4 bytes.
If an instruction specifies an immediate operand, the operand always follows any displacement bytes. An immediate operand can be 1, 2 or 4 bytes.
Vol. 2A 2-3
INSTRUCTION FORMAT
2.1.5
Addressing-Mode Encoding of ModR/M and SIB Bytes
The values and corresponding addressing forms of the ModR/M and SIB bytes are shown in Table 2-1 through Table
2-3: 16-bit addressing forms specified by the ModR/M byte are in Table 2-1 and 32-bit addressing forms are in
Table 2-2. Table 2-3 shows 32-bit addressing forms specified by the SIB byte. In cases where the reg/opcode field
in the ModR/M byte represents an extended opcode, valid encodings are shown in Appendix B.
In Table 2-1 and Table 2-2, the Effective Address column lists 32 effective addresses that can be assigned to the
first operand of an instruction by using the Mod and R/M fields of the ModR/M byte. The first 24 options provide
ways of specifying a memory location; the last eight (Mod = 11B) provide ways of specifying general-purpose, MMX
technology and XMM registers.
The Mod and R/M columns in Table 2-1 and Table 2-2 give the binary encodings of the Mod and R/M fields required
to obtain the effective address listed in the first column. For example: see the row indicated by Mod = 11B, R/M =
000B. The row identifies the general-purpose registers EAX, AX or AL; MMX technology register MM0; or XMM
register XMM0. The register used is determined by the opcode byte and the operand-size attribute.
Now look at the seventh row in either table (labeled “REG =”). This row specifies the use of the 3-bit Reg/Opcode
field when the field is used to give the location of a second operand. The second operand must be a generalpurpose, MMX technology, or XMM register. Rows one through five list the registers that may correspond to the
value in the table. Again, the register used is determined by the opcode byte along with the operand-size attribute.
If the instruction does not require a second operand, then the Reg/Opcode field may be used as an opcode extension. This use is represented by the sixth row in the tables (labeled “/digit (Opcode)”). Note that values in row six
are represented in decimal form.
The body of Table 2-1 and Table 2-2 (under the label “Value of ModR/M Byte (in Hexadecimal)”) contains a 32 by
8 array that presents all of 256 values of the ModR/M byte (in hexadecimal). Bits 3, 4 and 5 are specified by the
column of the table in which a byte resides. The row specifies bits 0, 1 and 2; and bits 6 and 7. The figure below
demonstrates interpretation of one table value.
Mod 11
RM
000
/digit (Opcode); REG =
001
C8H 11001000
Figure 2-2. Table Interpretation of ModR/M Byte (C8H)
2-4 Vol. 2A
INSTRUCTION FORMAT
Table 2-1. 16-Bit Addressing Forms with the ModR/M Byte
r8(/r)
r16(/r)
r32(/r)
mm(/r)
xmm(/r)
(In decimal) /digit (Opcode)
(In binary) REG =
Effective Address
AL
AX
EAX
MM0
XMM0
0
000
Mod
CL
CX
ECX
MM1
XMM1
1
001
R/M
DL
DX
EDX
MM2
XMM2
2
010
BL
BX
EBX
MM3
XMM3
3
011
AH
SP
ESP
MM4
XMM4
4
100
CH
BP1
EBP
MM5
XMM5
5
101
DH
SI
ESI
MM6
XMM6
6
110
BH
DI
EDI
MM7
XMM7
7
111
Value of ModR/M Byte (in Hexadecimal)
[BX+SI]
[BX+DI]
[BP+SI]
[BP+DI]
[SI]
[DI]
disp162
[BX]
00
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
[BX+SI]+disp83
[BX+DI]+disp8
[BP+SI]+disp8
[BP+DI]+disp8
[SI]+disp8
[DI]+disp8
[BP]+disp8
[BX]+disp8
01
000
001
010
011
100
101
110
111
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
[BX+SI]+disp16
[BX+DI]+disp16
[BP+SI]+disp16
[BP+DI]+disp16
[SI]+disp16
[DI]+disp16
[BP]+disp16
[BX]+disp16
10
000
001
010
011
100
101
110
111
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EAX/AX/AL/MM0/XMM0
ECX/CX/CL/MM1/XMM1
EDX/DX/DL/MM2/XMM2
EBX/BX/BL/MM3/XMM3
ESP/SP/AHMM4/XMM4
EBP/BP/CH/MM5/XMM5
ESI/SI/DH/MM6/XMM6
EDI/DI/BH/MM7/XMM7
11
000
001
010
011
100
101
110
111
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
EQ
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
NOTES:
1. The default segment register is SS for the effective addresses containing a BP index, DS for other effective addresses.
2. The disp16 nomenclature denotes a 16-bit displacement that follows the ModR/M byte and that is added to the index.
3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and that is sign-extended and added to the
index.
Vol. 2A 2-5
INSTRUCTION FORMAT
Table 2-2. 32-Bit Addressing Forms with the ModR/M Byte
r8(/r)
r16(/r)
r32(/r)
mm(/r)
xmm(/r)
(In decimal) /digit (Opcode)
(In binary) REG =
Effective Address
AL
AX
EAX
MM0
XMM0
0
000
Mod
CL
CX
ECX
MM1
XMM1
1
001
R/M
DL
DX
EDX
MM2
XMM2
2
010
BL
BX
EBX
MM3
XMM3
3
011
AH
SP
ESP
MM4
XMM4
4
100
CH
BP
EBP
MM5
XMM5
5
101
DH
SI
ESI
MM6
XMM6
6
110
BH
DI
EDI
MM7
XMM7
7
111
Value of ModR/M Byte (in Hexadecimal)
[EAX]
[ECX]
[EDX]
[EBX]
[--][--]1
disp322
[ESI]
[EDI]
00
000
001
010
011
100
101
110
111
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
[EAX]+disp83
[ECX]+disp8
[EDX]+disp8
[EBX]+disp8
[--][--]+disp8
[EBP]+disp8
[ESI]+disp8
[EDI]+disp8
01
000
001
010
011
100
101
110
111
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
[EAX]+disp32
[ECX]+disp32
[EDX]+disp32
[EBX]+disp32
[--][--]+disp32
[EBP]+disp32
[ESI]+disp32
[EDI]+disp32
10
000
001
010
011
100
101
110
111
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
EAX/AX/AL/MM0/XMM0
ECX/CX/CL/MM/XMM1
EDX/DX/DL/MM2/XMM2
EBX/BX/BL/MM3/XMM3
ESP/SP/AH/MM4/XMM4
EBP/BP/CH/MM5/XMM5
ESI/SI/DH/MM6/XMM6
EDI/DI/BH/MM7/XMM7
11
000
001
010
011
100
101
110
111
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
NOTES:
1. The [--][--] nomenclature means a SIB follows the ModR/M byte.
2. The disp32 nomenclature denotes a 32-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is
added to the index.
3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte (or the SIB byte if one is present) and that is
sign-extended and added to the index.
Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal). General purpose registers used
as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field.
Table rows in the body of the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling
factor (determined by SIB byte bits 6 and 7).
2-6 Vol. 2A
INSTRUCTION FORMAT
Table 2-3. 32-Bit Addressing Forms with the SIB Byte
r32
(In decimal) Base =
(In binary) Base =
EAX
0
000
Scaled Index
SS
ECX
1
001
Index
EDX
2
010
EBX
3
011
ESP
4
100
[*]
5
101
ESI
6
110
EDI
7
111
Value of SIB Byte (in Hexadecimal)
[EAX]
[ECX]
[EDX]
[EBX]
none
[EBP]
[ESI]
[EDI]
00
000
001
010
011
100
101
110
111
00
08
10
18
20
28
30
38
01
09
11
19
21
29
31
39
02
0A
12
1A
22
2A
32
3A
03
0B
13
1B
23
2B
33
3B
04
0C
14
1C
24
2C
34
3C
05
0D
15
1D
25
2D
35
3D
06
0E
16
1E
26
2E
36
3E
07
0F
17
1F
27
2F
37
3F
[EAX*2]
[ECX*2]
[EDX*2]
[EBX*2]
none
[EBP*2]
[ESI*2]
[EDI*2]
01
000
001
010
011
100
101
110
111
40
48
50
58
60
68
70
78
41
49
51
59
61
69
71
79
42
4A
52
5A
62
6A
72
7A
43
4B
53
5B
63
6B
73
7B
44
4C
54
5C
64
6C
74
7C
45
4D
55
5D
65
6D
75
7D
46
4E
56
5E
66
6E
76
7E
47
4F
57
5F
67
6F
77
7F
[EAX*4]
[ECX*4]
[EDX*4]
[EBX*4]
none
[EBP*4]
[ESI*4]
[EDI*4]
10
000
001
010
011
100
101
110
111
80
88
90
98
A0
A8
B0
B8
81
89
91
99
A1
A9
B1
B9
82
8A
92
9A
A2
AA
B2
BA
83
8B
93
9B
A3
AB
B3
BB
84
8C
94
9C
A4
AC
B4
BC
85
8D
95
9D
A5
AD
B5
BD
86
8E
96
9E
A6
AE
B6
BE
87
8F
97
9F
A7
AF
B7
BF
[EAX*8]
[ECX*8]
[EDX*8]
[EBX*8]
none
[EBP*8]
[ESI*8]
[EDI*8]
11
000
001
010
011
100
101
110
111
C0
C8
D0
D8
E0
E8
F0
F8
C1
C9
D1
D9
E1
E9
F1
F9
C2
CA
D2
DA
E2
EA
F2
FA
C3
CB
D3
DB
E3
EB
F3
FB
C4
CC
D4
DC
E4
EC
F4
FC
C5
CD
D5
DD
E5
ED
F5
FD
C6
CE
D6
DE
E6
EE
F6
FE
C7
CF
D7
DF
E7
EF
F7
FF
NOTES:
1. The [*] nomenclature means a disp32 with no base if the MOD is 00B. Otherwise, [*] means disp8 or disp32 + [EBP]. This provides the
following address modes:
MOD bits Effective Address
00
[scaled index] + disp32
01
[scaled index] + disp8 + [EBP]
10
[scaled index] + disp32 + [EBP]
2.2
IA-32E MODE
IA-32e mode has two sub-modes. These are:
•
Compatibility Mode. Enables a 64-bit operating system to run most legacy protected mode software
unmodified.
•
64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space.
Vol. 2A 2-7
INSTRUCTION FORMAT
2.2.1
REX Prefixes
REX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following:
•
•
•
Specify GPRs and SSE registers.
Specify 64-bit operand size.
Specify extended control registers.
Not all instructions require a REX prefix in 64-bit mode. A prefix is necessary only if an instruction references one
of the extended registers or uses a 64-bit operand. If a REX prefix is used when it has no meaning, it is ignored.
Only one REX prefix is allowed per instruction. If used, the REX prefix byte must immediately precede the opcode
byte or the escape opcode byte (0FH). When a REX prefix is used in conjunction with an instruction containing a
mandatory prefix, the mandatory prefix must come before the REX so the REX prefix can be immediately preceding
the opcode or the escape byte. For example, CVTDQ2PD with a REX prefix should have REX placed between F3 and
0F E6. Other placements are ignored. The instruction-size limit of 15 bytes still applies to instructions with a REX
prefix. See Figure 2-3.
Legacy
Prefixes
REX
Prefix
Grp 1, Grp
2, Grp 3,
Grp 4
(optional)
(optional)
Opcode
ModR/M
1-, 2-, or
3-byte
opcode
1 byte
(if required)
SIB
1 byte
(if required)
Displacement
Address
displacement of
1, 2, or 4 bytes
Immediate
Immediate data
of 1, 2, or 4
bytes or none
Figure 2-3. Prefix Ordering in 64-bit Mode
2.2.1.1
Encoding
Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encoding, depending
on the format:
•
•
ModR/M: the reg and r/m fields of the ModR/M byte.
•
Instructions without ModR/M: the reg field of the opcode.
ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of the SIB (scale, index, base)
byte.
In 64-bit mode, these formats do not change. Bits needed to define fields in the 64-bit context are provided by the
addition of REX prefixes.
2.2.1.2
More on REX Prefix Fields
REX prefixes are a set of 16 opcodes that span one row of the opcode map and occupy entries 40H to 4FH. These
opcodes represent valid instructions (INC or DEC) in IA-32 operating modes and in compatibility mode. In 64-bit
mode, the same opcodes represent the instruction prefix REX and are not treated as individual instructions.
The single-byte-opcode forms of the INC/DEC instructions are not available in 64-bit mode. INC/DEC functionality
is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1).
See Table 2-4 for a summary of the REX prefix format. Figure 2-4 though Figure 2-7 show examples of REX prefix
fields in use. Some combinations of REX prefix fields are invalid. In such cases, the prefix is ignored. Some additional information follows:
•
Setting REX.W can be used to determine the operand size but does not solely determine operand width. Like
the 66H size prefix, 64-bit operand size override has no effect on byte-specific operations.
•
•
For non-byte operations: if a 66H prefix is used with prefix (REX.W = 1), 66H is ignored.
If a 66H override is used with REX and REX.W = 0, the operand size is 16 bits.
2-8 Vol. 2A
INSTRUCTION FORMAT
•
REX.R modifies the ModR/M reg field when that field encodes a GPR, SSE, control or debug register. REX.R is
ignored when ModR/M specifies other registers or defines an extended opcode.
•
•
REX.X bit modifies the SIB index field.
REX.B either modifies the base in the ModR/M r/m field or SIB base field; or it modifies the opcode reg field
used for accessing GPRs.
Table 2-4. REX Prefix Fields [BITS: 0100WRXB]
Field Name
Bit Position
Definition
-
7:4
0100
W
3
0 = Operand size determined by CS.D
1 = 64 Bit Operand Size
R
2
Extension of the ModR/M reg field
X
1
Extension of the SIB index field
B
0
Extension of the ModR/M r/m field, SIB base field, or Opcode reg field
ModRM Byte
REX PREFIX
Opcode
mod
≠11
0100WR0B
reg
rrr
r/m
bbb
Rrrr
Bbbb
OM17Xfig1-3
Figure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used
ModRM Byte
REX PREFIX
0100WR0B
Opcode
mod
11
reg
rrr
Rrrr
r/m
bbb
Bbbb
OM17Xfig1-4
Figure 2-5. Register-Register Addressing (No Memory Operand); REX.X Not Used
Vol. 2A 2-9
INSTRUCTION FORMAT
ModRM Byte
REX PREFIX
Opcode
mod
≠ 11
0100WRXB
reg
rrr
SIB Byte
r/m
100
index
xxx
scale
ss
Rrrr
Xxxx
base
bbb
Bbbb
OM17Xfig1-5
Figure 2-6. Memory Addressing With a SIB Byte
REX PREFIX
0100W00B
Opcode
reg
bbb
Bbbb
OM17Xfig1-6
Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not Used
In the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) are encoded in the ModR/M byte’s
reg field, the r/m field or the opcode reg field as registers 0 through 7. REX prefixes provide an additional
addressing capability for byte-registers that makes the least-significant byte of GPRs available for byte operations.
Certain combinations of the fields of the ModR/M byte and the SIB byte have special meaning for register encodings. For some combinations, fields expanded by the REX prefix are not decoded. Table 2-5 describes how each
case behaves.
2-10 Vol. 2A
INSTRUCTION FORMAT
Table 2-5. Special Cases of REX Encodings
ModR/M or
SIB
Sub-field
Encodings
ModR/M Byte mod ≠ 11
Compatibility Mode
Operation
Compatibility Mode
Implications
SIB byte present.
SIB byte required for REX prefix adds a fourth bit (b) which is not decoded
ESP-based addressing. (don't care).
r/m =
b*100(ESP)
ModR/M Byte mod = 0
r/m =
b*101(EBP)
Additional Implications
SIB byte also required for R12-based addressing.
Base register not
used.
EBP without a
REX prefix adds a fourth bit (b) which is not decoded
displacement must be (don't care).
done using
Using RBP or R13 without displacement must be done
mod = 01 with
using mod = 01 with a displacement of 0.
displacement of 0.
SIB Byte
index =
0100(ESP)
Index register not
used.
ESP cannot be used as REX prefix adds a fourth bit (b) which is decoded.
an index register.
There are no additional implications. The expanded
index field allows distinguishing RSP from R12,
therefore R12 can be used as an index.
SIB Byte
base =
0101(EBP)
Base register is
unused if mod = 0.
Base register depends REX prefix adds a fourth bit (b) which is not decoded.
on mod encoding.
This requires explicit displacement to be used with
EBP/RBP or R13.
NOTES:
* Don’t care about value of REX.B
2.2.1.3
Displacement
Addressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings. The ModR/M and SIB displacement
sizes do not change. They remain 8 bits or 32 bits and are sign-extended to 64 bits.
2.2.1.4
Direct Memory-Offset MOVs
In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate
absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For
these MOV instructions, the size of the memory offset follows the address-size default (64 bits in 64-bit mode). See
Table 2-6.
Table 2-6. Direct Memory Offset Form of MOV
Opcode
Instruction
A0
MOV AL, moffset
A1
MOV EAX, moffset
A2
MOV moffset, AL
A3
MOV moffset, EAX
2.2.1.5
Immediates
In 64-bit mode, the typical size of immediate operands remains 32 bits. When the operand size is 64 bits, the
processor sign-extends all immediates to 64 bits prior to their use.
Support for 64-bit immediate operands is accomplished by expanding the semantics of the existing move (MOV
reg, imm16/32) instructions. These instructions (opcodes B8H – BFH) move 16-bits or 32-bits of immediate data
(depending on the effective operand size) into a GPR. When the effective operand size is 64 bits, these instructions
can be used to load an immediate into a GPR. A REX prefix is needed to override the 32-bit default operand size to
a 64-bit operand size.
For example:
48 B8 8877665544332211 MOV RAX,1122334455667788H
Vol. 2A 2-11
INSTRUCTION FORMAT
2.2.1.6
RIP-Relative Addressing
A new addressing form, RIP-relative (relative instruction-pointer) addressing, is implemented in 64-bit mode. An
effective address is formed by adding displacement to the 64-bit RIP of the next instruction.
In IA-32 architecture and compatibility mode, addressing relative to the instruction pointer is available only with
control-transfer instructions. In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative
addressing. Without RIP-relative addressing, all ModR/M modes address memory relative to zero.
RIP-relative addressing allows specific ModR/M modes to address memory relative to the 64-bit RIP using a signed
32-bit displacement. This provides an offset range of ±2GB from the RIP. Table 2-7 shows the ModR/M and SIB
encodings for RIP-relative addressing. Redundant forms of 32-bit displacement-addressing exist in the current
ModR/M and SIB encodings. There is one ModR/M encoding and there are several SIB encodings. RIP-relative
addressing is encoded using a redundant form.
In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than
displacement-only. See Table 2-7.
Table 2-7. RIP-Relative Addressing
ModR/M and SIB Sub-field Encodings Compatibility Mode
Operation
64-bit Mode
Operation
Additional Implications in 64-bit mode
ModR/M Byte
Disp32
RIP + Disp32
Must use SIB form with normal (zero-based)
displacement addressing
if mod = 00, Disp32
Same as legacy
None
mod = 00
r/m = 101 (none)
SIB Byte
base = 101 (none)
index = 100 (none)
scale = 0, 1, 2, 4
The ModR/M encoding for RIP-relative addressing does not depend on using a prefix. Specifically, the r/m bit field
encoding of 101B (used to select RIP-relative addressing) is not affected by the REX prefix. For example, selecting
R13 (REX.B = 1, r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/m field of REX.B
combined with ModR/M is not fully decoded. In order to address R13 with no displacement, software must encode
R13 + 0 using a 1-byte displacement of zero.
RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. The use of the address-size prefix
does not disable RIP-relative addressing. The effect of the address-size prefix is to truncate and zero-extend the
computed effective address to 32 bits.
2.2.1.7
Default 64-Bit Operand Size
In 64-bit mode, two groups of instructions have a default operand size of 64 bits (do not need a REX prefix for this
operand size). These are:
•
•
Near branches.
All instructions, except far branches, that implicitly reference the RSP.
2.2.2
Additional Encodings for Control and Debug Registers
In 64-bit mode, more encodings for control and debug registers are available. The REX.R bit is used to modify the
ModR/M reg field when that field encodes a control or debug register (see Table 2-4). These encodings enable the
processor to address CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit mode. CR8
becomes the Task Priority Register (TPR).
In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented. Any attempt to access
unimplemented registers results in an invalid-opcode exception (#UD).
2-12 Vol. 2A
INSTRUCTION FORMAT
2.3
INTEL® ADVANCED VECTOR EXTENSIONS (INTEL® AVX)
Intel AVX instructions are encoded using an encoding scheme that combines prefix bytes, opcode extension field,
operand encoding fields, and vector length encoding capability into a new prefix, referred to as VEX. In the VEX
encoding scheme, the VEX prefix may be two or three bytes long, depending on the instruction semantics. Despite
the two-byte or three-byte length of the VEX prefix, the VEX encoding format provides a more compact representation/packing of the components of encoding an instruction in Intel 64 architecture. The VEX encoding scheme
also allows more headroom for future growth of Intel 64 architecture.
2.3.1
Instruction Format
Instruction encoding using VEX prefix provides several advantages:
•
Instruction syntax support for three operands and up-to four operands when necessary. For example, the third
source register used by VBLENDVPD is encoded using bits 7:4 of the immediate byte.
•
•
•
Encoding support for vector length of 128 bits (using XMM registers) and 256 bits (using YMM registers).
Encoding support for instruction syntax of non-destructive source operands.
Elimination of escape opcode byte (0FH), SIMD prefix byte (66H, F2H, F3H) via a compact bit field representation within the VEX prefix.
•
Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8R15) for direct register access, memory addressing, or accessing XMM8-XMM15 (including YMM8-YMM15).
•
Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only because only a
subset of SIMD instructions need them.
•
Extensibility for future instruction extensions without significant instruction length increase.
Figure 2-8 shows the Intel 64 instruction encoding format with VEX prefix support. Legacy instruction without a
VEX prefix is fully supported and unchanged. The use of VEX prefix in an Intel 64 instruction is optional, but a VEX
prefix is required for Intel 64 instructions that operate on YMM registers or support three and four operand syntax.
VEX prefix is not a constant-valued, “single-purpose” byte like 0FH, 66H, F2H, F3H in legacy SSE instructions. VEX
prefix provides substantially richer capability than the REX prefix.
# Bytes
[Prefixes]
2,3
[VEX]
1
OPCODE
1
0,1
ModR/M
[SIB]
0,1,2,4
[DISP]
0,1
[IMM]
Figure 2-8. Instruction Encoding Format with VEX Prefix
2.3.2
VEX and the LOCK prefix
Any VEX-encoded instruction with a LOCK prefix preceding VEX will #UD.
2.3.3
VEX and the 66H, F2H, and F3H prefixes
Any VEX-encoded instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.
2.3.4
VEX and the REX prefix
Any VEX-encoded instruction with a REX prefix proceeding VEX will #UD.
Vol. 2A 2-13
INSTRUCTION FORMAT
2.3.5
The VEX Prefix
The VEX prefix is encoded in either the two-byte form (the first byte must be C5H) or in the three-byte form (the
first byte must be C4H). The two-byte VEX is used mainly for 128-bit, scalar, and the most common 256-bit AVX
instructions; while the three-byte VEX provides a compact replacement of REX and 3-byte opcode instructions
(including AVX and FMA instructions). Beyond the first byte of the VEX prefix, it consists of a number of bit fields
providing specific capability, they are shown in Figure 2-9.
The bit fields of the VEX prefix can be summarized by its functional purposes:
•
Non-destructive source register encoding (applicable to three and four operand syntax): This is the first source
operand in the instruction syntax. It is represented by the notation, VEX.vvvv. This field is encoded using 1’s
complement form (inverted form), i.e. XMM0/YMM0/R0 is encoded as 1111B, XMM15/YMM15/R15 is encoded
as 0000B.
•
Vector length encoding: This 1-bit field represented by the notation VEX.L. L= 0 means vector length is 128 bits
wide, L=1 means 256 bit vector. The value of this field is written as VEX.128 or VEX.256 in this document to
distinguish encoded values of other VEX bit fields.
•
REX prefix functionality: Full REX prefix functionality is provided in the three-byte form of VEX prefix. However
the VEX bit fields providing REX functionality are encoded using 1’s complement form, i.e. XMM0/YMM0/R0 is
encoded as 1111B, XMM15/YMM15/R15 is encoded as 0000B.
— Two-byte form of the VEX prefix only provides the equivalent functionality of REX.R, using 1’s complement
encoding. This is represented as VEX.R.
— Three-byte form of the VEX prefix provides REX.R, REX.X, REX.B functionality using 1’s complement
encoding and three dedicated bit fields represented as VEX.R, VEX.X, VEX.B.
— Three-byte form of the VEX prefix provides the functionality of REX.W only to specific instructions that need
to override default 32-bit operand size for a general purpose register to 64-bit size in 64-bit mode. For
those applicable instructions, VEX.W field provides the same functionality as REX.W. VEX.W field can
provide completely different functionality for other instructions.
Consequently, the use of REX prefix with VEX encoded instructions is not allowed. However, the intent of the
REX prefix for expanding register set is reserved for future instruction set extensions using VEX prefix
encoding format.
•
Compaction of SIMD prefix: Legacy SSE instructions effectively use SIMD prefixes (66H, F2H, F3H) as an
opcode extension field. VEX prefix encoding allows the functional capability of such legacy SSE instructions
(operating on XMM registers, bits 255:128 of corresponding YMM unmodified) to be encoded using the VEX.pp
field without the presence of any SIMD prefix. The VEX-encoded 128-bit instruction will zero-out bits 255:128
of the destination register. VEX-encoded instruction may have 128 bit vector length or 256 bits length.
•
Compaction of two-byte and three-byte opcode: More recently introduced legacy SSE instructions employ two
and three-byte opcode. The one or two leading bytes are: 0FH, and 0FH 3AH/0FH 38H. The one-byte escape
(0FH) and two-byte escape (0FH 3AH, 0FH 38H) can also be interpreted as an opcode extension field. The
VEX.mmmmm field provides compaction to allow many legacy instruction to be encoded without the constant
byte sequence, 0FH, 0FH 3AH, 0FH 38H. These VEX-encoded instruction may have 128 bit vector length or 256
bits length.
The VEX prefix is required to be the last prefix and immediately precedes the opcode bytes. It must follow any
other prefixes. If VEX prefix is present a REX prefix is not supported.
The 3-byte VEX leaves room for future expansion with 3 reserved bits. REX and the 66h/F2h/F3h prefixes are
reclaimed for future use.
VEX prefix has a two-byte form and a three byte form. If an instruction syntax can be encoded using the two-byte
form, it can also be encoded using the three byte form of VEX. The latter increases the length of the instruction by
one byte. This may be helpful in some situations for code alignment.
The VEX prefix supports 256-bit versions of floating-point SSE, SSE2, SSE3, and SSE4 instructions. Note, certain
new instruction functionality can only be encoded with the VEX prefix.
The VEX prefix will #UD on any instruction containing MMX register sources or destinations.
2-14 Vol. 2A
INSTRUCTION FORMAT
3-byte VEX
0 7 6 5 4
11000100
7
2-byte VEX
Byte 2
Byte 1
Byte 0
(Bit Position) 7
0
11000101
0
RXB
m-mmmm
7
3
R
6
vvvv
1
7
W
6
3
vvvv
1
2 1 0
L pp
2 1 0
L
pp
R: REX.R in 1’s complement (inverted) form
1: Same as REX.R=0 (must be 1 in 32-bit mode)
0: Same as REX.R=1 (64-bit mode only)
X: REX.X in 1’s complement (inverted) form
1: Same as REX.X=0 (must be 1 in 32-bit mode)
0: Same as REX.X=1 (64-bit mode only)
B: REX.B in 1’s complement (inverted) form
1: Same as REX.B=0 (Ignored in 32-bit mode).
0: Same as REX.B=1 (64-bit mode only)
W: opcode specific (use like REX.W, or used for opcode
extension, or ignored, depending on the opcode byte)
m-mmmm:
00000: Reserved for future use (will #UD)
00001: implied 0F leading opcode byte
00010: implied 0F 38 leading opcode bytes
00011: implied 0F 3A leading opcode bytes
00100-11111: Reserved for future use (will #UD)
vvvv: a register specifier (in 1’s complement form) or 1111 if unused.
L: Vector Length
0: scalar or 128-bit vector
1: 256-bit vector
pp: opcode extension providing equivalent functionality of a SIMD prefix
00: None
01: 66
10: F3
11: F2
Figure 2-9. VEX bit fields
The following subsections describe the various fields in two or three-byte VEX prefix.
2.3.5.1
VEX Byte 0, bits[7:0]
VEX Byte 0, bits [7:0] must contain the value 11000101b (C5h) or 11000100b (C4h). The 3-byte VEX uses the C4h
first byte, while the 2-byte VEX uses the C5h first byte.
2.3.5.2
VEX Byte 1, bit [7] - ‘R’
VEX Byte 1, bit [7] contains a bit analogous to a bit inverted REX.R. In protected and compatibility modes the bit
must be set to ‘1’ otherwise the instruction is LES or LDS.
Vol. 2A 2-15
INSTRUCTION FORMAT
This bit is present in both 2- and 3-byte VEX prefixes.
The usage of WRXB bits for legacy instructions is explained in detail section 2.2.1.2 of Intel 64 and IA-32 Architectures Software developer’s manual, Volume 2A.
This bit is stored in bit inverted format.
2.3.5.3
3-byte VEX byte 1, bit[6] - ‘X’
Bit[6] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.X. It is an extension of the SIB Index
field in 64-bit modes. In 32-bit modes, this bit must be set to ‘1’ otherwise the instruction is LES or LDS.
This bit is available only in the 3-byte VEX prefix.
This bit is stored in bit inverted format.
2.3.5.4
3-byte VEX byte 1, bit[5] - ‘B’
Bit[5] of the 3-byte VEX byte 1 encodes a bit analogous to a bit inverted REX.B. In 64-bit modes, it is an extension
of the ModR/M r/m field, or the SIB base field. In 32-bit modes, this bit is ignored.
This bit is available only in the 3-byte VEX prefix.
This bit is stored in bit inverted format.
2.3.5.5
3-byte VEX byte 2, bit[7] - ‘W’
Bit[7] of the 3-byte VEX byte 2 is represented by the notation VEX.W. It can provide following functions, depending
on the specific opcode.
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have a
general-purpose register operand with its operand size attribute promotable by REX.W), if REX.W promotes
the operand size attribute of the general-purpose register operand in legacy SSE instruction, VEX.W has same
meaning in the corresponding AVX equivalent form. In 32-bit modes, VEX.W is silently ignored.
• For AVX instructions that have equivalent legacy SSE instructions (typically these SSE instructions have operands with their operand size attribute fixed and not promotable by REX.W), if REX.W is don’t care in legacy
SSE instruction, VEX.W is ignored in the corresponding AVX equivalent form irrespective of mode.
• For new AVX instructions where VEX.W has no defined function (typically these meant the combination of the
opcode byte and VEX.mmmmm did not have any equivalent SSE functions), VEX.W is reserved as zero and
setting to other than zero will cause instruction to #UD.
2.3.5.6
2-byte VEX Byte 1, bits[6:3] and 3-byte VEX Byte 2, bits [6:3]- ‘vvvv’ the Source or Dest
Register Specifier
In 32-bit mode the VEX first byte C4 and C5 alias onto the LES and LDS instructions. To maintain compatibility with
existing programs the VEX 2nd byte, bits [7:6] must be 11b. To achieve this, the VEX payload bits are selected to
place only inverted, 64-bit valid fields (extended register selectors) in these upper bits.
The 2-byte VEX Byte 1, bits [6:3] and the 3-byte VEX, Byte 2, bits [6:3] encode a field (shorthand VEX.vvvv) that
for instructions with 2 or more source registers and an XMM or YMM or memory destination encodes the first source
register specifier stored in inverted (1’s complement) form.
VEX.vvvv is not used by the instructions with one source (except certain shifts, see below) or on instructions with
no XMM or YMM or memory destination. If an instruction does not use VEX.vvvv then it should be set to 1111b
otherwise instruction will #UD.
In 64-bit mode all 4 bits may be used. See Table 2-8 for the encoding of the XMM or YMM registers. In 32-bit and
16-bit modes bit 6 must be 1 (if bit 6 is not 1, the 2-byte VEX version will generate LDS instruction and the 3-byte
VEX version will ignore this bit).
2-16 Vol. 2A
INSTRUCTION FORMAT
Table 2-8. VEX.vvvv to register name mapping
VEX.vvvv
Dest Register
Valid in Legacy/Compatibility 32-bit modes?
1111B
XMM0/YMM0
Valid
1110B
XMM1/YMM1
Valid
1101B
XMM2/YMM2
Valid
1100B
XMM3/YMM3
Valid
1011B
XMM4/YMM4
Valid
1010B
XMM5/YMM5
Valid
1001B
XMM6/YMM6
Valid
1000B
XMM7/YMM7
Valid
0111B
XMM8/YMM8
Invalid
0110B
XMM9/YMM9
Invalid
0101B
XMM10/YMM10
Invalid
0100B
XMM11/YMM11
Invalid
0011B
XMM12/YMM12
Invalid
0010B
XMM13/YMM13
Invalid
0001B
XMM14/YMM14
Invalid
0000B
XMM15/YMM15
Invalid
The VEX.vvvv field is encoded in bit inverted format for accessing a register operand.
2.3.6
Instruction Operand Encoding and VEX.vvvv, ModR/M
VEX-encoded instructions support three-operand and four-operand instruction syntax. Some VEX-encoded
instructions have syntax with less than three operands, e.g. VEX-encoded pack shift instructions support one
source operand and one destination operand).
The roles of VEX.vvvv, reg field of ModR/M byte (ModR/M.reg), r/m field of ModR/M byte (ModR/M.r/m) with
respect to encoding destination and source operands vary with different type of instruction syntax.
The role of VEX.vvvv can be summarized to three situations:
•
VEX.vvvv encodes the first source register operand, specified in inverted (1’s complement) form and is valid for
instructions with 2 or more source operands.
•
VEX.vvvv encodes the destination register operand, specified in 1’s complement form for certain vector shifts.
The instructions where VEX.vvvv is used as a destination are listed in Table 2-9. The notation in the “Opcode”
column in Table 2-9 is described in detail in section 3.1.1.
•
VEX.vvvv does not encode any operand, the field is reserved and should contain 1111b.
Table 2-9. Instructions with a VEX.vvvv destination
Opcode
Instruction mnemonic
VEX.NDD.128.66.0F 73 /7 ib
VPSLLDQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /3 ib
VPSRLDQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /2 ib
VPSRLW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /2 ib
VPSRLD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /2 ib
VPSRLQ xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /4 ib
VPSRAW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /4 ib
VPSRAD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 71 /6 ib
VPSLLW xmm1, xmm2, imm8
VEX.NDD.128.66.0F 72 /6 ib
VPSLLD xmm1, xmm2, imm8
VEX.NDD.128.66.0F 73 /6 ib
VPSLLQ xmm1, xmm2, imm8
Vol. 2A 2-17
INSTRUCTION FORMAT
The role of ModR/M.r/m field can be summarized to two situations:
•
•
ModR/M.r/m encodes the instruction operand that references a memory address.
For some instructions that do not support memory addressing semantics, ModR/M.r/m encodes either the
destination register operand or a source register operand.
The role of ModR/M.reg field can be summarized to two situations:
•
•
ModR/M.reg encodes either the destination register operand or a source register operand.
For some instructions, ModR/M.reg is treated as an opcode extension and not used to encode any instruction
operand.
For instruction syntax that support four operands, VEX.vvvv, ModR/M.r/m, ModR/M.reg encodes three of the four
operands. The role of bits 7:4 of the immediate byte serves the following situation:
•
Imm8[7:4] encodes the third source register operand.
2.3.6.1
3-byte VEX byte 1, bits[4:0] - “m-mmmm”
Bits[4:0] of the 3-byte VEX byte 1 encode an implied leading opcode byte (0F, 0F 38, or 0F 3A). Several bits are
reserved for future use and will #UD unless 0.
Table 2-10. VEX.m-mmmm interpretation
VEX.m-mmmm
Implied Leading Opcode Bytes
00000B
Reserved
00001B
0F
00010B
0F 38
00011B
0F 3A
00100-11111B
Reserved
(2-byte VEX)
0F
VEX.m-mmmm is only available on the 3-byte VEX. The 2-byte VEX implies a leading 0Fh opcode byte.
2.3.6.2
2-byte VEX byte 1, bit[2], and 3-byte VEX byte 2, bit [2]- “L”
The vector length field, VEX.L, is encoded in bit[2] of either the second byte of 2-byte VEX, or the third byte of 3byte VEX. If “VEX.L = 1”, it indicates 256-bit vector operation. “VEX.L = 0” indicates scalar and 128-bit vector
operations.
The instruction VZEROUPPER is a special case that is encoded with VEX.L = 0, although its operation zero’s bits
255:128 of all YMM registers accessible in the current operating mode.
See the following table.
Table 2-11. VEX.L interpretation
2.3.6.3
VEX.L
Vector Length
0
128-bit (or 32/64-bit scalar)
1
256-bit
2-byte VEX byte 1, bits[1:0], and 3-byte VEX byte 2, bits [1:0]- “pp”
Up to one implied prefix is encoded by bits[1:0] of either the 2-byte VEX byte 1 or the 3-byte VEX byte 2. The prefix
behaves as if it was encoded prior to VEX, but after all other encoded prefixes.
See the following table.
2-18 Vol. 2A
INSTRUCTION FORMAT
Table 2-12. VEX.pp interpretation
2.3.7
pp
Implies this prefix after other prefixes but before VEX
00B
None
01B
66
10B
F3
11B
F2
The Opcode Byte
One (and only one) opcode byte follows the 2 or 3 byte VEX. Legal opcodes are specified in Appendix B, in color.
Any instruction that uses illegal opcode will #UD.
2.3.8
The MODRM, SIB, and Displacement Bytes
The encodings are unchanged but the interpretation of reg_field or rm_field differs (see above).
2.3.9
The Third Source Operand (Immediate Byte)
VEX-encoded instructions can support instruction with a four operand syntax. VBLENDVPD, VBLENDVPS, and
PBLENDVB use imm8[7:4] to encode one of the source registers.
2.3.10
AVX Instructions and the Upper 128-bits of YMM registers
If an instruction with a destination XMM register is encoded with a VEX prefix, the processor zeroes the upper bits
(above bit 128) of the equivalent YMM register. Legacy SSE instructions without VEX preserve the upper bits.
2.3.10.1
Vector Length Transition and Programming Considerations
An instruction encoded with a VEX.128 prefix that loads a YMM register operand operates as follows:
•
•
Data is loaded into bits 127:0 of the register
Bits above bit 127 in the register are cleared.
Thus, such an instruction clears bits 255:128 of a destination YMM register on processors with a maximum vectorregister width of 256 bits. In the event that future processors extend the vector registers to greater widths, an
instruction encoded with a VEX.128 or VEX.256 prefix will also clear any bits beyond bit 255. (This is in contrast
with legacy SSE instructions, which have no VEX prefix; these modify only bits 127:0 of any destination register
operand.)
Programmers should bear in mind that instructions encoded with VEX.128 and VEX.256 prefixes will clear any
future extensions to the vector registers. A calling function that uses such extensions should save their state before
calling legacy functions. This is not possible for involuntary calls (e.g., into an interrupt-service routine). It is
recommended that software handling involuntary calls accommodate this by not executing instructions encoded
with VEX.128 and VEX.256 prefixes. In the event that it is not possible or desirable to restrict these instructions,
then software must take special care to avoid actions that would, on future processors, zero the upper bits of
vector registers.
Processors that support further vector-register extensions (defining bits beyond bit 255) will also extend the
XSAVE and XRSTOR instructions to save and restore these extensions. To ensure forward compatibility, software
that handles involuntary calls and that uses instructions encoded with VEX.128 and VEX.256 prefixes should first
save and then restore the vector registers (with any extensions) using the XSAVE and XRSTOR instructions with
save/restore masks that set bits that correspond to all vector-register extensions. Ideally, software should rely on
a mechanism that is cognizant of which bits to set. (E.g., an OS mechanism that sets the save/restore mask bits
for all vector-register extensions that are enabled in XCR0.) Saving and restoring state with instructions other than
XSAVE and XRSTOR will, on future processors with wider vector registers, corrupt the extended state of the vector
registers - even if doing so functions correctly on processors supporting 256-bit vector registers. (The same is true
Vol. 2A 2-19
INSTRUCTION FORMAT
if XSAVE and XRSTOR are used with a save/restore mask that does not set bits corresponding to all supported
extensions to the vector registers.)
2.3.11
AVX Instruction Length
The AVX instructions described in this document (including VEX and ignoring other prefixes) do not exceed 11
bytes in length, but may increase in the future. The maximum length of an Intel 64 and IA-32 instruction remains
15 bytes.
2.3.12
Vector SIB (VSIB) Memory Addressing
®
In Intel Advanced Vector Extensions 2 (Intel® AVX2), an SIB byte that follows the ModR/M byte can support VSIB
memory addressing to an array of linear addresses. VSIB addressing is only supported in a subset of Intel AVX2
instructions. VSIB memory addressing requires 32-bit or 64-bit effective address. In 32-bit mode, VSIB addressing
is not supported when address size attribute is overridden to 16 bits. In 16-bit protected mode, VSIB memory
addressing is permitted if address size attribute is overridden to 32 bits. Additionally, VSIB memory addressing is
supported only with VEX prefix.
In VSIB memory addressing, the SIB byte consists of:
•
•
The scale field (bit 7:6) specifies the scale factor.
•
The base field (bits 2:0) specifies the register number of the base register.
The index field (bits 5:3) specifies the register number of the vector index register, each element in the vector
register specifies an index.
Table 2-3 shows the 32-bit VSIB addressing form. It is organized to give 256 possible values of the SIB byte (in
hexadecimal). General purpose registers used as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field. The register names also include R8L-R15L applicable only in 64-bit
mode (when address size override prefix is used, but the value of VEX.B is not shown in Table 2-3). In 32-bit mode,
R8L-R15L does not apply.
Table rows in the body of the table indicate the vector index register used as the index field and each supported
scaling factor shown separately. Vector registers used in the index field can be XMM or YMM registers. The leftmost column includes vector registers VR8-VR15 (i.e. XMM8/YMM8-XMM15/YMM15), which are only available in
64-bit mode and does not apply if encoding in 32-bit mode.
Table 2-13. 32-Bit VSIB Addressing Forms of the SIB Byte
r32
(In decimal) Base =
(In binary) Base =
Scaled Index
SS
EAX/
R8L
0
000
ECX/
R9L
1
001
EDX/
R10L
2
010
Index
EBX/
R11L
3
011
ESP/
R12L
4
100
EBP/
R13L1
5
101
ESI/
R14L
6
110
EDI/
R15L
7
111
Value of SIB Byte (in Hexadecimal)
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*1
00
000
001
010
011
100
101
110
111
00
08
10
18
20
28
30
38
01
09
11
19
21
29
31
39
02
0A
12
1A
22
2A
32
3A
03
0B
13
1B
23
2B
33
3B
04
0C
14
1C
24
2C
34
3C
05
0D
15
1D
25
2D
35
3D
06
0E
16
1E
26
2E
36
3E
07
0F
17
1F
27
2F
37
3F
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*2
01
000
001
010
011
100
101
110
111
40
48
50
58
60
68
70
78
41
49
51
59
61
69
71
79
42
4A
52
5A
62
6A
72
7A
43
4B
53
5B
63
6B
73
7B
44
4C
54
5C
64
6C
74
7C
45
4D
55
5D
65
6D
75
7D
46
4E
56
5E
66
6E
76
7E
47
4F
57
5F
67
6F
77
7F
2-20 Vol. 2A
INSTRUCTION FORMAT
Table 2-13. 32-Bit VSIB Addressing Forms of the SIB Byte (Contd.)
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*4
10
000
001
010
011
100
101
110
111
80
88
90
98
A0
A8
B0
B8
81
89
91
89
A1
A9
B1
B9
82
8A
92
9A
A2
AA
B2
BA
83
8B
93
9B
A3
AB
B3
BB
84
8C
94
9C
A4
AC
B4
BC
85
8D
95
9D
A5
AD
B5
BD
86
8E
96
9E
A6
AE
B6
BE
87
8F
97
9F
A7
AF
B7
BF
VR0/VR8
VR1/VR9
VR2/VR10
VR3/VR11
VR4/VR12
VR5/VR13
VR6/VR14
VR7/VR15
*8
11
000
001
010
011
100
101
110
111
C0
C8
D0
D8
E0
E8
F0
F8
C1
C9
D1
D9
E1
E9
F1
F9
C2
CA
D2
DA
E2
EA
F2
FA
C3
CB
D3
DB
E3
EB
F3
FB
C4
CC
D4
DC
E4
EC
F4
FC
C5
CD
D5
DD
E5
ED
F5
FD
C6
CE
D6
DE
E6
EE
F6
FE
C7
CF
D7
DF
E7
EF
F7
FF
NOTES:
1. If ModR/M.mod = 00b, the base address is zero, then effective address is computed as [scaled vector index] + disp32. Otherwise the
base address is computed as [EBP/R13]+ disp, the displacement is either 8 bit or 32 bit depending on the value of ModR/M.mod:
MOD
Effective Address
00b
[Scaled Vector Register] + Disp32
01b
[Scaled Vector Register] + Disp8 + [EBP/R13]
10b
[Scaled Vector Register] + Disp32 + [EBP/R13]
2.3.12.1
64-bit Mode VSIB Memory Addressing
In 64-bit mode VSIB memory addressing uses the VEX.B field and the base field of the SIB byte to encode one of
the 16 general-purpose register as the base register. The VEX.X field and the index field of the SIB byte encode one
of the 16 vector registers as the vector index register.
In 64-bit mode the top row of Table 2-13 base register should be interpreted as the full 64-bit of each register.
2.4
AVX AND SSE INSTRUCTION EXCEPTION SPECIFICATION
To look up the exceptions of legacy 128-bit SIMD instruction, 128-bit VEX-encoded instructions, and 256-bit VEXencoded instruction, Table 2-14 summarizes the exception behavior into separate classes, with detailed exception
conditions defined in sub-sections 2.4.1 through 2.5.1. For example, ADDPS contains the entry:
“See Exceptions Type 2”
In this entry, “Type2” can be looked up in Table 2-14.
The instruction’s corresponding CPUID feature flag can be identified in the fourth column of the Instruction
summary table.
Note: #UD on CPUID feature flags=0 is not guaranteed in a virtualized environment if the hardware supports the
feature flag.
NOTE
Instructions that operate only with MMX, X87, or general-purpose registers are not covered by the
exception classes defined in this section. For instructions that operate on MMX registers, see
Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers”
in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
Vol. 2A 2-21
INSTRUCTION FORMAT
Table 2-14. Exception class description
Exception Class
Instruction set
Mem arg
Floating-Point
Exceptions (#XM)
Type 1
AVX,
Legacy SSE
16/32 byte explicitly
aligned
None
Type 2
AVX,
Legacy SSE
16/32 byte not explicitly
aligned
Yes
Type 3
AVX,
Legacy SSE
< 16 byte
Yes
Type 4
AVX,
Legacy SSE
16/32 byte not explicitly
aligned
No
Type 5
AVX,
Legacy SSE
< 16 byte
No
Type 6
AVX (no Legacy SSE)
Varies
(At present, none do)
Type 7
AVX,
Legacy SSE
None
None
Type 8
AVX
None
None
F16C
8 or 16 byte, Not explicitly
aligned, no AC#
Yes
AVX2
Not explicitly aligned, no
AC#
No
Type 11
Type 12
See Table 2-15 for lists of instructions in each exception class.
2-22 Vol. 2A
INSTRUCTION FORMAT
Table 2-15. Instructions in each Exception Class
Exception Class
Instruction
Type 1
(V)MOVAPD, (V)MOVAPS, (V)MOVDQA, (V)MOVNTDQ, (V)MOVNTDQA, (V)MOVNTPD, (V)MOVNTPS
Type 2
(V)ADDPD, (V)ADDPS, (V)ADDSUBPD, (V)ADDSUBPS, (V)CMPPD, (V)CMPPS, (V)CVTDQ2PS, (V)CVTPD2DQ,
(V)CVTPD2PS, (V)CVTPS2DQ, (V)CVTTPD2DQ, (V)CVTTPS2DQ, (V)DIVPD, (V)DIVPS, (V)DPPD*, (V)DPPS*,
VFMADD132PD, VFMADD213PD, VFMADD231PD, VFMADD132PS, VFMADD213PS, VFMADD231PS,
VFMADDSUB132PD, VFMADDSUB213PD, VFMADDSUB231PD, VFMADDSUB132PS, VFMADDSUB213PS,
VFMADDSUB231PS, VFMSUBADD132PD, VFMSUBADD213PD, VFMSUBADD231PD, VFMSUBADD132PS,
VFMSUBADD213PS, VFMSUBADD231PS, VFMSUB132PD, VFMSUB213PD, VFMSUB231PD, VFMSUB132PS,
VFMSUB213PS, VFMSUB231PS, VFNMADD132PD, VFNMADD213PD, VFNMADD231PD, VFNMADD132PS,
VFNMADD213PS, VFNMADD231PS, VFNMSUB132PD, VFNMSUB213PD, VFNMSUB231PD, VFNMSUB132PS,
VFNMSUB213PS, VFNMSUB231PS, (V)HADDPD, (V)HADDPS, (V)HSUBPD, (V)HSUBPS, (V)MAXPD, (V)MAXPS,
(V)MINPD, (V)MINPS, (V)MULPD, (V)MULPS, (V)ROUNDPS, (V)SQRTPD, (V)SQRTPS, (V)SUBPD, (V)SUBPS
Type 3
(V)ADDSD, (V)ADDSS, (V)CMPSD, (V)CMPSS, (V)COMISD, (V)COMISS, (V)CVTPS2PD, (V)CVTSD2SI, (V)CVTSD2SS,
(V)CVTSI2SD, (V)CVTSI2SS, (V)CVTSS2SD, (V)CVTSS2SI, (V)CVTTSD2SI, (V)CVTTSS2SI, (V)DIVSD, (V)DIVSS,
VFMADD132SD, VFMADD213SD, VFMADD231SD, VFMADD132SS, VFMADD213SS, VFMADD231SS,
VFMSUB132SD, VFMSUB213SD, VFMSUB231SD, VFMSUB132SS, VFMSUB213SS, VFMSUB231SS,
VFNMADD132SD, VFNMADD213SD, VFNMADD231SD, VFNMADD132SS, VFNMADD213SS, VFNMADD231SS,
VFNMSUB132SD, VFNMSUB213SD, VFNMSUB231SD, VFNMSUB132SS, VFNMSUB213SS, VFNMSUB231SS,
(V)MAXSD, (V)MAXSS, (V)MINSD, (V)MINSS, (V)MULSD, (V)MULSS, (V)ROUNDSD, (V)ROUNDSS, (V)SQRTSD,
(V)SQRTSS, (V)SUBSD, (V)SUBSS, (V)UCOMISD, (V)UCOMISS
Type 4
(V)AESDEC, (V)AESDECLAST, (V)AESENC, (V)AESENCLAST, (V)AESIMC, (V)AESKEYGENASSIST, (V)ANDPD,
(V)ANDPS, (V)ANDNPD, (V)ANDNPS, (V)BLENDPD, (V)BLENDPS, VBLENDVPD, VBLENDVPS, (V)LDDQU***,
(V)MASKMOVDQU, (V)PTEST, VTESTPS, VTESTPD, (V)MOVDQU*, (V)MOVSHDUP, (V)MOVSLDUP, (V)MOVUPD*,
(V)MOVUPS*, (V)MPSADBW, (V)ORPD, (V)ORPS, (V)PABSB, (V)PABSW, (V)PABSD, (V)PACKSSWB, (V)PACKSSDW,
(V)PACKUSWB, (V)PACKUSDW, (V)PADDB, (V)PADDW, (V)PADDD, (V)PADDQ, (V)PADDSB, (V)PADDSW,
(V)PADDUSB, (V)PADDUSW, (V)PALIGNR, (V)PAND, (V)PANDN, (V)PAVGB, (V)PAVGW, (V)PBLENDVB,
(V)PBLENDW, (V)PCMP(E/I)STRI/M***, (V)PCMPEQB, (V)PCMPEQW, (V)PCMPEQD, (V)PCMPEQQ, (V)PCMPGTB,
(V)PCMPGTW, (V)PCMPGTD, (V)PCMPGTQ, (V)PCLMULQDQ, (V)PHADDW, (V)PHADDD, (V)PHADDSW,
(V)PHMINPOSUW, (V)PHSUBD, (V)PHSUBW, (V)PHSUBSW, (V)PMADDWD, (V)PMADDUBSW, (V)PMAXSB,
(V)PMAXSW, (V)PMAXSD, (V)PMAXUB, (V)PMAXUW, (V)PMAXUD, (V)PMINSB, (V)PMINSW, (V)PMINSD,
(V)PMINUB, (V)PMINUW, (V)PMINUD, (V)PMULHUW, (V)PMULHRSW, (V)PMULHW, (V)PMULLW, (V)PMULLD,
(V)PMULUDQ, (V)PMULDQ, (V)POR, (V)PSADBW, (V)PSHUFB, (V)PSHUFD, (V)PSHUFHW, (V)PSHUFLW, (V)PSIGNB,
(V)PSIGNW, (V)PSIGND, (V)PSLLW, (V)PSLLD, (V)PSLLQ, (V)PSRAW, (V)PSRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ,
(V)PSUBB, (V)PSUBW, (V)PSUBD, (V)PSUBQ, (V)PSUBSB, (V)PSUBSW, (V)PUNPCKHBW, (V)PUNPCKHWD,
(V)PUNPCKHDQ, (V)PUNPCKHQDQ, (V)PUNPCKLBW, (V)PUNPCKLWD, (V)PUNPCKLDQ, (V)PUNPCKLQDQ,
(V)PXOR, (V)RCPPS, (V)RSQRTPS, (V)SHUFPD, (V)SHUFPS, (V)UNPCKHPD, (V)UNPCKHPS, (V)UNPCKLPD,
(V)UNPCKLPS, (V)XORPD, (V)XORPS, VPBLENDD, VPERMD, VPERMPS, VPERMPD, VPERMQ, VPSLLVD, VPSLLVQ,
VPSRAVD, VPSRLVD, VPSRLVQ, VPERMILPD, VPERMILPS, VPERM2F128
Type 5
(V)CVTDQ2PD, (V)EXTRACTPS, (V)INSERTPS, (V)MOVD, (V)MOVQ, (V)MOVDDUP, (V)MOVLPD, (V)MOVLPS,
(V)MOVHPD, (V)MOVHPS, (V)MOVSD, (V)MOVSS, (V)PEXTRB, (V)PEXTRD, (V)PEXTRW, (V)PEXTRQ, (V)PINSRB,
(V)PINSRD, (V)PINSRW, (V)PINSRQ, (V)RCPSS, (V)RSQRTSS, (V)PMOVSX/ZX, VLDMXCSR*, VSTMXCSR
Type 6
VEXTRACTF128, VBROADCASTSS, VBROADCASTSD, VBROADCASTF128, VINSERTF128, VMASKMOVPS**,
VMASKMOVPD**, VPMASKMOVD, VPMASKMOVQ, VBROADCASTI128, VPBROADCASTB, VPBROADCASTD,
VPBROADCASTW, VPBROADCASTQ, VEXTRACTI128, VINSERTI128, VPERM2I128
Type 7
(V)MOVLHPS, (V)MOVHLPS, (V)MOVMSKPD, (V)MOVMSKPS, (V)PMOVMSKB, (V)PSLLDQ, (V)PSRLDQ, (V)PSLLW,
(V)PSLLD, (V)PSLLQ, (V)PSRAW, (V)PSRAD, (V)PSRLW, (V)PSRLD, (V)PSRLQ
Type 8
VZEROALL, VZEROUPPER
Type 11
VCVTPH2PS, VCVTPS2PH
Type 12
VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD,
VPGATHERQQ
(*) - Additional exception restrictions are present - see the Instruction description for details
(**) - Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits of all 1s, i.e. no
alignment checks are performed.
Vol. 2A 2-23
INSTRUCTION FORMAT
(***) - PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM and LDDQU instructions do not cause #GP if the memory operand is not
aligned to 16-Byte boundary.
Table 2-15 classifies exception behaviors for AVX instructions. Within each class of exception conditions that are
listed in Table 2-18 through Table 2-27, certain subsets of AVX instructions may be subject to #UD exception
depending on the encoded value of the VEX.L field. Table 2-17 provides supplemental information of AVX instructions that may be subject to #UD exception if encoded with incorrect values in the VEX.W or VEX.L field.
Table 2-16. #UD Exception and VEX.W=1 Encoding
Exception Class
#UD If VEX.W = 1 in all modes
#UD If VEX.W = 1 in
non-64-bit modes
Type 1
Type 2
Type 3
Type 4
VBLENDVPD, VBLENDVPS, VPBLENDVB, VTESTPD, VTESTPS, VPBLENDD, VPERMD,
VPERMPS, VPERM2I128, VPSRAVD, VPERMILPD, VPERMILPS, VPERM2F128
Type 5
Type 6
VPEXTRQ, VPINSRQ,
VEXTRACTF128, VBROADCASTSS, VBROADCASTSD, VBROADCASTF128,
VINSERTF128, VMASKMOVPS, VMASKMOVPD, VBROADCASTI128,
VPBROADCASTB/W/D, VEXTRACTI128, VINSERTI128
Type 7
Type 8
Type 11
Type 12
2-24 Vol. 2A
VCVTPH2PS, VCVTPS2PH
INSTRUCTION FORMAT
Table 2-17. #UD Exception and VEX.L Field Encoding
Exception
Class
#UD If VEX.L = 0
Type 1
#UD If (VEX.L = 1 && AVX2 not present && AVX
present)
#UD If (VEX.L = 1 && AVX2
present)
VMOVNTDQA
VDPPD
VDPPD
VPCMP(E/I)STRI/M,
PHMINPOSUW
Type 4
VMASKMOVDQU, VMPSADBW, VPABSB/W/D,
VPACKSSWB/DW, VPACKUSWB/DW, VPADDB/W/D,
VPADDQ, VPADDSB/W, VPADDUSB/W, VPALIGNR, VPAND,
VPANDN, VPAVGB/W, VPBLENDVB, VPBLENDW,
VPCMP(E/I)STRI/M, VPCMPEQB/W/D/Q, VPCMPGTB/W/D/Q,
VPHADDW/D, VPHADDSW, VPHMINPOSUW, VPHSUBD/W,
VPHSUBSW, VPMADDWD, VPMADDUBSW, VPMAXSB/W/D,
VPMAXUB/W/D, VPMINSB/W/D, VPMINUB/W/D,
VPMULHUW, VPMULHRSW, VPMULHW/LW, VPMULLD,
VPMULUDQ, VPMULDQ, VPOR, VPSADBW, VPSHUFB/D,
VPSHUFHW/LW, VPSIGNB/W/D, VPSLLW/D/Q, VPSRAW/D,
VPSRLW/D/Q, VPSUBB/W/D/Q, VPSUBSB/W,
VPUNPCKHBW/WD/DQ, VPUNPCKHQDQ,
VPUNPCKLBW/WD/DQ, VPUNPCKLQDQ, VPXOR
Same as column 3
Type 5
VEXTRACTPS, VINSERTPS, VMOVD, VMOVQ, VMOVLPD,
VMOVLPS, VMOVHPD, VMOVHPS, VPEXTRB, VPEXTRD,
VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW,
VPINSRQ, VPMOVSX/ZX, VLDMXCSR, VSTMXCSR
VMOVLHPS, VMOVHLPS, VPMOVMSKB, VPSLLDQ,
VPSRLDQ, VPSLLW, VPSLLD, VPSLLQ, VPSRAW, VPSRAD,
VPSRLW, VPSRLD, VPSRLQ
VMOVLHPS, VMOVHLPS
Type 2
Type 3
Type 6
Type 7
VEXTRACTF128,
VPERM2F128,
VBROADCASTSD,
VBROADCASTF128,
VINSERTF128,
Type 8
Type 11
Type 12
Vol. 2A 2-25
INSTRUCTION FORMAT
2.4.1
Exceptions Type 1 (Aligned memory reference)
Invalid Opcode,
#UD
Device Not Available, #NM
X
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
X
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
X
VEX.256: Memory operand is not 32-byte aligned.
VEX.128: Memory operand is not 16-byte aligned.
X
X
Legacy SSE: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
2-26 Vol. 2A
Cause of Exception
X
Stack, SS(0)
General Protection, #GP(0)
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-18. Type 1 Class Exception Conditions
X
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
For a page fault.
INSTRUCTION FORMAT
2.4.2
Exceptions Type 2 (>=16 Byte Memory Reference, Unaligned)
Invalid Opcode,
#UD
Device Not Available, #NM
X
X
X
X
X
X
X
Cause of Exception
VEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
X
X
X
X
X
General Protection, #GP(0)
Page Fault
#PF(fault-code)
X
If a memory address referencing the SS segment is in a non-canonical form.
Legacy SSE: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
SIMD Floatingpoint Exception,
#XM
64-bit
X
Protected and
Compatibility
Virtual 8086
Exception
Real
Table 2-19. Type 2 Class Exception Conditions
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
X
For a page fault.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
Vol. 2A 2-27
INSTRUCTION FORMAT
2.4.3
Exceptions Type 3 (<16 Byte memory argument)
X
X
X
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-20. Type 3 Class Exception Conditions
VEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
Invalid Opcode, #UD
Device Not Available,
#NM
X
X
X
X
Cause of Exception
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault
#PF(fault-code)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 Bytes or
less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
2-28 Vol. 2A
X
INSTRUCTION FORMAT
2.4.4
Exceptions Type 4 (>=16 Byte mem arg no alignment, no floating-point exceptions)
Invalid Opcode, #UD
Device Not Available,
#NM
X
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
X
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
Legacy SSE: Memory operand is not 16-byte aligned.1
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
Page Fault
#PF(fault-code)
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-21. Type 4 Class Exception Conditions
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
If the memory address is in a non-canonical form.
X
X
For a page fault.
NOTES:
1. PCMPESTRI, PCMPESTRM, PCMPISTRI, PCMPISTRM and LDDQU instructions do not cause #GP if the memory operand is not aligned to
16-Byte boundary.
Vol. 2A 2-29
INSTRUCTION FORMAT
2.4.5
Exceptions Type 5 (<16 Byte mem arg and no FP exceptions)
Invalid Opcode, #UD
Device Not Available,
#NM
X
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-22. Type 5 Class Exception Conditions
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault
#PF(fault-code)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made
while the current privilege level is 3.
2-30 Vol. 2A
INSTRUCTION FORMAT
2.4.6
Exceptions Type 6 (VEX-Encoded Instructions Without Legacy SSE Analogues)
Note: At present, the AVX instructions in this category do not generate floating-point exceptions.
X
Device Not Available,
#NM
Stack, SS(0)
General Protection,
#GP(0)
Page Fault
#PF(fault-code)
Alignment Check
#AC(0)
Cause of Exception
VEX prefix.
X
Invalid Opcode, #UD
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-23. Type 6 Class Exception Conditions
X
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If the memory address is in a non-canonical form.
X
X
For a page fault.
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference is made while the current privilege level is 3.
Vol. 2A 2-31
INSTRUCTION FORMAT
2.4.7
Exceptions Type 7 (No FP exceptions, no memory arg)
Invalid Opcode, #UD
X
Cause of Exception
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
X
X
Legacy SSE instruction:
If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
X
X
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Device Not Available,
#NM
2.4.8
64-bit
X
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-24. Type 7 Class Exception Conditions
Exceptions Type 8 (AVX and no memory argument)
X
X
X
2-32 Vol. 2A
X
Cause of Exception
Always in Real or Virtual-8086 mode.
X
Device Not Available,
#NM
64-bit
Virtual-8086
Invalid Opcode, #UD
Protected and
Compatibility
Exception
Real
Table 2-25. Type 8 Class Exception Conditions
X
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
If CPUID.01H.ECX.AVX[bit 28]=0.
If VEX.vvvv ≠ 1111B.
X
X
If proceeded by a LOCK prefix (F0H).
X
X
If CR0.TS[bit 3]=1.
INSTRUCTION FORMAT
2.4.9
Exception Type 11 (VEX-only, mem arg no AC, floating-point exceptions)
X
X
Device Not Available, #NM
64-bit
Virtual-8086
Invalid Opcode, #UD
Protected and
Compatibility
Exception
Real
Table 2-26. Type 11 Class Exception Conditions
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
General Protection,
#GP(0)
X
For an illegal address in the SS segment.
X
X
Page Fault #PF
(fault-code)
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
SIMD Floating-Point
Exception, #XM
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
X
For a page fault.
X
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
Vol. 2A 2-33
INSTRUCTION FORMAT
2.4.10
Exception Type 12 (VEX-only, VSIB mem arg, no AC, no floating-point exceptions)
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual-8086
Exception
Real
Table 2-27. Type 12 Class Exception Conditions
X
X
VEX prefix.
X
X
VEX prefix:
If XCR0[2:1] ≠ ‘11b’.
If CR4.OSXSAVE[bit 18]=0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm ≠ ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If any vector register is used more than once between the destination register,
mask register and the index register in VSIB addressing.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
2.5
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
Page Fault #PF (faultcode)
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
For a page fault.
VEX ENCODING SUPPORT FOR GPR INSTRUCTIONS
VEX prefix may be used to encode instructions that operate on neither YMM nor XMM registers. VEX-encoded
general-purpose-register instructions have the following properties:
•
•
Instruction syntax support for three encodable operands.
•
Elimination of escape opcode byte (0FH), two-byte escape via a compact bit field representation within the VEX
prefix.
•
Elimination of the need to use REX prefix to encode the extended half of general-purpose register sets (R8-R15)
for direct register access or memory addressing.
•
Flexible and more compact bit fields are provided in the VEX prefix to retain the full functionality provided by
REX prefix. REX.W, REX.X, REX.B functionalities are provided in the three-byte VEX prefix only.
•
VEX-encoded GPR instructions are encoded with VEX.L=0.
Encoding support for instruction syntax of non-destructive source operand, destination operand encoded via
VEX.vvvv, and destructive three-operand syntax.
2-34 Vol. 2A
INSTRUCTION FORMAT
Any VEX-encoded GPR instruction with a 66H, F2H, or F3H prefix preceding VEX will #UD.
Any VEX-encoded GPR instruction with a REX prefix proceeding VEX will #UD.
VEX-encoded GPR instructions are not supported in real and virtual 8086 modes.
2.5.1
Exception Conditions for VEX-Encoded GPR Instructions
The exception conditions applicable to VEX-encoded GPR instruction differs from those of legacy GPR instructions.
Table 2-28 lists VEX-encoded GPR instructions. The exception conditions for VEX-encoded GRP instructions are
found in Table 2-29 for those instructions which have a default operand size of 32 bits and 16-bit operand size is
not encodable.
Table 2-28. VEX-Encoded GPR Instructions
Exception Class
Instruction
See Table 2-29
ANDN, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX
(*) - Additional exception restrictions are present - see the Instruction description for details.
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual-8086
Exception
Real
Table 2-29. Exception Definition (VEX-Encoded GPR Instructions)
X
X
X
X
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null
segment selector.
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
If BMI1/BMI2 CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
Stack, SS(0)
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made
while the current privilege level is 3.
2.6
INTEL® AVX-512 ENCODING
The majority of the Intel AVX-512 family of instructions (operating on 512/256/128-bit vector register operands)
are encoded using a new prefix (called EVEX). Opmask instructions (operating on opmask register operands) are
encoded using the VEX prefix. The EVEX prefix has some parts resembling the instruction encoding scheme using
the VEX prefix, and many other capabilities not available with the VEX prefix.
The significant feature differences between EVEX and VEX are summarized below.
Vol. 2A 2-35
INSTRUCTION FORMAT
•
EVEX is a 4-Byte prefix (the first byte must be 62H); VEX is either a 2-Byte (C5H is the first byte) or 3-Byte
(C4H is the first byte) prefix.
•
•
EVEX prefix can encode 32 vector registers (XMM/YMM/ZMM) in 64-bit mode.
•
EVEX memory addressing with disp8 form uses a compressed disp8 encoding scheme to improve the encoding
density of the instruction byte stream.
•
EVEX prefix can encode functionality that are specific to instruction classes (e.g., packed instruction with
“load+op” semantic can support embedded broadcast functionality, floating-point instruction with rounding
semantic can support static rounding functionality, floating-point instruction with non-rounding arithmetic
semantic can support “suppress all exceptions” functionality).
EVEX prefix can encode an opmask register for conditional processing or selection control in EVEX-encoded
vector instructions. Opmask instructions, whose source/destination operands are opmask registers and treat
the content of an opmask register as a single value, are encoded using the VEX prefix.
2.6.1
Instruction Format and EVEX
The placement of the EVEX prefix in an IA instruction is represented in Figure 2-10.
# of bytes:
[Prefixes]
1
4
EVEX
1
Opcode
1
ModR/M
[SIB]
4
[Disp32]
1
[Immediate]
1
[Disp8*N]
Figure 2-10. AVX-512 Instruction Format and the EVEX Prefix
The EVEX prefix is a 4-byte prefix, with the first two bytes derived from unused encoding form of the 32-bit-modeonly BOUND instruction. The layout of the EVEX prefix is shown in Figure 2-11. The first byte must be 62H, followed
by three payload bytes, denoted as P0, P1, and P2 individually or collectively as P[23:0] (see Figure 2-11).
EVEX
62H
P0
P1
7
P0
R
7
P1
W
7
P2
z
6
X
6
v
6
L’
P2
5
B
5
v
5
L
4
R’
4
v
4
b
3
0
3
v
3
V’
2
0
2
1
2
a
1
0
m
1
m
0
p
1
p
P[15:8]
0
a
Figure 2-11. Bit Field Layout of the EVEX Prefix
2-36 Vol. 2A
P[7:0]
a
P[23:16]
INSTRUCTION FORMAT
Table 2-30. EVEX Prefix Bit Field Functional Grouping
Notation
Bit field Group
Position
Comment
--
Reserved
P[3 : 2]
Must be 0.
--
Fixed Value
P[10]
Must be 1.
EVEX.mm
Compressed legacy escape
P[1: 0]
Identical to low two bits of VEX.mmmmm.
EVEX.pp
Compressed legacy prefix
P[9 : 8]
Identical to VEX.pp.
EVEX.RXB
Next-8 register specifier modifier
P[7 : 5]
Combine with ModR/M.reg, ModR/M.rm (base, index/vidx).
EVEXR’
High-16 register specifier modifier
P[4]
Combine with EVEX.R and ModR/M.reg.
EVEXX
High-16 register specifier modifier
P[6]
Combine with EVEX.B and ModR/M.rm, when SIB/VSIB absent.
EVEX.vvvv
NDS register specifier
P[14 : 11]
Same as VEX.vvvv.
EVEXV’
High-16 NDS/VIDX register specifier
P[19]
Combine with EVEX.vvvv or when VSIB present.
EVEX.aaa
Embedded opmask register specifier
P[18 : 16]
EVEX.W
Osize promotion/Opcode extension
P[15]
EVEX.z
Zeroing/Merging
P[23]
EVEX.b
Broadcast/RC/SAE Context
P[20]
EVEX.L’L
Vector length/RC
P[22 : 21]
The bit fields in P[23:0] are divided into the following functional groups (Table 2-30 provides a tabular summary):
•
•
•
Reserved bits: P[3:2] must be 0, otherwise #UD.
•
Operand specifier modifier bits for vector register, general purpose register, memory addressing: P[7:5] allows
access to the next set of 8 registers beyond the low 8 registers when combined with ModR/M register specifiers.
•
Operand specifier modifier bit for vector register: P[4] (or EVEX.R’) allows access to the high 16 vector register
set when combined with P[7] and ModR/M.reg specifier; P[6] can also provide access to a high 16 vector
register when SIB or VSIB addressing are not needed.
•
Non-destructive source /vector index operand specifier: P[19] and P[14:11] encode the second source vector
register operand in a non-destructive source syntax, vector index register operand can access an upper 16
vector register using P[19].
•
Op-mask register specifiers: P[18:16] encodes op-mask register set k0-k7 in instructions operating on vector
registers.
•
EVEX.W: P[15] is similar to VEX.W which serves either as opcode extension bit or operand size promotion to
64-bit in 64-bit mode.
•
Vector destination merging/zeroing: P[23] encodes the destination result behavior which either zeroes the
masked elements or leave masked element unchanged.
•
Broadcast/Static-rounding/SAE context bit: P[20] encodes multiple functionality, which differs across different
classes of instructions and can affect the meaning of the remaining field (EVEX.L’L). The functionality for the
following instruction classes are:
Fixed-value bit: P[10] must be 1, otherwise #UD.
Compressed legacy prefix/escape bytes: P[1:0] is identical to the lowest 2 bits of VEX.mmmmm; P[9:8] is
identical to VEX.pp.
— Broadcasting a single element across the destination vector register: this applies to the instruction class
with Load+Op semantic where one of the source operand is from memory.
— Redirect L’L field (P[22:21]) as static rounding control for floating-point instructions with rounding
semantic. Static rounding control overrides MXCSR.RC field and implies “Suppress all exceptions” (SAE).
— Enable SAE for floating -point instructions with arithmetic semantic that is not rounding.
— For instruction classes outside of the afore-mentioned three classes, setting EVEX.b will cause #UD.
Vol. 2A 2-37
INSTRUCTION FORMAT
•
Vector length/rounding control specifier: P[22:21] can serve one of three options.
— Vector length information for packed vector instructions.
— Ignored for instructions operating on vector register content as a single data element.
— Rounding control for floating-point instructions that have a rounding semantic and whose source and
destination operands are all vector registers.
2.6.2
Register Specifier Encoding and EVEX
EVEX-encoded instruction can access 8 opmask registers, 16 general-purpose registers and 32 vector registers in
64-bit mode (8 general-purpose registers and 8 vector registers in non-64-bit modes). EVEX-encoding can support
instruction syntax that access up to 4 instruction operands. Normal memory addressing modes and VSIB memory
addressing are supported with EVEX prefix encoding. The mapping of register operands used by various instruction
syntax and memory addressing in 64-bit mode are shown in Table 2-31. Opmask register encoding is described in
Section 2.6.3.
Table 2-31. 32-Register Support in 64-bit Mode Using EVEX with Embedded REX Bits
41
3
[2:0]
Reg. Type
Common Usages
REG
EVEX.R’
REX.R
modrm.reg
GPR, Vector
Destination or Source
NDS/NDD
EVEX.V’
GPR, Vector
2ndSource or Destination
RM
EVEX.X
EVEX.B
modrm.r/m
GPR, Vector
1st Source or Destination
BASE
0
EVEX.B
modrm.r/m
GPR
memory addressing
INDEX
0
EVEX.X
sib.index
GPR
memory addressing
EVEX.V’
EVEX.X
sib.index
Vector
VSIB memory addressing
VIDX
EVEX.vvvv
NOTES:
1. Not applicable for accessing general purpose registers.
The mapping of register operands used by various instruction syntax and memory addressing in 32-bit modes are
shown in Table 2-32.
Table 2-32. EVEX Encoding Register Specifiers in 32-bit Mode
[2:0]
Reg. Type
Common Usages
REG
modrm.reg
GPR, Vector
Destination or Source
NDS/NDD
EVEX.vvv
GPR, Vector
2nd Source or Destination
RM
modrm.r/m
GPR, Vector
1st Source or Destination
BASE
modrm.r/m
GPR
Memory Addressing
INDEX
sib.index
GPR
Memory Addressing
VIDX
sib.index
Vector
VSIB Memory Addressing
2.6.3
Opmask Register Encoding
There are eight opmask registers, k0-k7. Opmask register encoding falls into two categories:
•
Opmask registers that are the source or destination operands of an instruction treating the content of opmask
register as a scalar value, are encoded using the VEX prefix scheme. It can support up to three operands using
standard modR/M byte’s reg field and rm field and VEX.vvvv. Such a scalar opmask instruction does not support
conditional update of the destination operand.
•
An opmask register providing conditional processing and/or conditional update of the destination register of a
vector instruction is encoded using EVEX.aaa field (see Section 2.6.4).
2-38 Vol. 2A
INSTRUCTION FORMAT
•
An opmask register serving as the destination or source operand of a vector instruction is encoded using
standard modR/M byte’s reg field and rm fields.
Table 2-33. Opmask Register Specifier Encoding
[2:0]
Register Access
Common Usages
REG
modrm.reg
k0-k7
Source
NDS
VEX.vvvv
k0-k7
2nd Source
RM
modrm.r/m
k0-7
1st Source
{k1}
EVEX.aaa
1
k0 -k7
Opmask
NOTES:
1. Instructions that overwrite the conditional mask in opmask do not permit using k0 as the embedded mask.
2.6.4
Masking Support in EVEX
EVEX can encode an opmask register to conditionally control per-element computational operation and updating of
result of an instruction to the destination operand. The predicate operand is known as the opmask register. The
EVEX.aaa field, P[18:16] of the EVEX prefix, is used to encode one out of a set of eight 64-bit architectural registers. Note that from this set of 8 architectural registers, only k1 through k7 can be addressed as predicate operands. k0 can be used as a regular source or destination but cannot be encoded as a predicate operand.
AVX-512 instructions support two types of masking with EVEX.z bit (P[23]) controlling the type of masking:
•
Merging-masking, which is the default type of masking for EVEX-encoded vector instructions, preserves the old
value of each element of the destination where the corresponding mask bit has a 0. It corresponds to the case
of EVEX.z = 0.
•
Zeroing-masking, is enabled by having the EVEX.z bit set to 1. In this case, an element of the destination is set
to 0 when the corresponding mask bit has a 0 value.
AVX-512 Foundation instructions can be divided into the following groups:
•
Instructions which support “zeroing-masking”.
— Also allow merging-masking.
•
Instructions which require aaa = 000.
— Do not allow any form of masking.
•
Instructions which allow merging-masking but do not allow zeroing-masking.
— Require EVEX.z to be set to 0.
— This group is mostly composed of instructions that write to memory.
•
Instructions which require aaa <> 000 do not allow EVEX.z to be set to 1.
— Allow merging-masking and do not allow zeroing-masking, e.g., gather instructions.
2.6.5
Compressed Displacement (disp8*N) Support in EVEX
For memory addressing using disp8 form, EVEX-encoded instructions always use a compressed displacement
scheme by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length,
the value of EVEX.b bit (embedded broadcast) and the input element size of the instruction. In general, the factor
N corresponds to the number of bytes characterizing the internal memory operation of the input operand (e.g., 64
when the accessing a full 512-bit memory vector). The scale factor N is listed in Table 2-34 and Table 2-35 below,
where EVEX encoded instructions are classified using the tupletype attribute. The scale factor N of each tupletype
is listed based on the vector length (VL) and other factors affecting it.
Table 2-34 covers EVEX-encoded instructions which has a load semantic in conjunction with additional computational or data element movement operation, operating either on the full vector or half vector (due to conversion of
Vol. 2A 2-39
INSTRUCTION FORMAT
numerical precision from a wider format to narrower format). EVEX.b is supported for such instructions for data
element sizes which are either dword or qword (see Section 2.6.11).
EVEX-encoded instruction that are pure load/store, and “Load+op” instruction semantic that operate on data
element size less then dword do not support broadcasting using EVEX.b. These are listed in Table 2-35. Table 2-35
also includes many broadcast instructions which perform broadcast using a subset of data elements without using
EVEX.b. These instructions and a few data element size conversion instruction are covered in Table 2-35. Instruction classified in Table 2-35 do not use EVEX.b and EVEX.b must be 0, otherwise #UD will occur.
The tupletype abbreviation will be referenced in the instruction operand encoding table in the reference page of
each instruction, providing the cross reference for the scaling factor N to encoding memory addressing operand.
Note that the disp8*N rules still apply when using 16b addressing.
Table 2-34. Compressed Displacement (DISP8*N) Affected by Embedded Broadcast
TupleType
EVEX.b
InputSize
EVEX.W
0
32bit
0
none
16
32
64
1
32bit
0
{1tox}
4
4
4
0
64bit
1
none
16
32
64
1
64bit
1
{1tox}
8
8
8
0
32bit
0
none
8
16
32
1
32bit
0
{1tox}
4
4
4
Full Vector
(FV)
Half Vector
(HV)
Broadcast N (VL=128) N (VL=256)
N (VL= 512)
Comment
Load+Op (Full Vector
Dword/Qword)
Load+Op (Half Vector)
Table 2-35. EVEX DISP8*N for Instructions Not Affected by Embedded Broadcast
TupleType
InputSize
Full Vector Mem (FVM)
N/A
N/A
16
32
64
8bit
N/A
1
1
1
16bit
N/A
2
2
2
32bit
0
4
4
4
64bit
1
8
8
8
32bit
N/A
4
4
4
64bit
N/A
8
8
8
32bit
0
8
8
8
64bit
1
NA
16
16
32bit
0
NA
16
16
64bit
1
NA
NA
32
Tuple8 (T8)
32bit
0
NA
NA
32
Broadcast (8 elements)
Half Mem (HVM)
N/A
N/A
8
16
32
SubQword Conversion
QuarterMem (QVM)
N/A
N/A
4
8
16
SubDword Conversion
OctMem (OVM)
N/A
N/A
2
4
8
SubWord Conversion
Mem128 (M128)
N/A
N/A
16
16
16
Shift count from memory
MOVDDUP (DUP)
N/A
N/A
8
32
64
VMOVDDUP
Tuple1 Scalar (T1S)
Tuple1 Fixed (T1F)
Tuple2 (T2)
Tuple4 (T4)
2.6.6
EVEX.W N (VL= 128) N (VL= 256) N (VL= 512)
Comment
Load/store or subDword full vector
1Tuple less than Full Vector
1 Tuple memsize not affected by
EVEX.W
Broadcast (2 elements)
Broadcast (4 elements)
EVEX Encoding of Broadcast/Rounding/SAE Support
EVEX.b can provide three types of encoding context, depending on the instruction classes:
2-40 Vol. 2A
INSTRUCTION FORMAT
•
Embedded broadcasting of one data element from a source memory operand to the destination for vector
instructions with “load+op” semantic.
•
•
Static rounding control overriding MXCSR.RC for floating-point instructions with rounding semantic.
“Suppress All exceptions” (SAE) overriding MXCSR mask control for floating-point arithmetic instructions that
do not have rounding semantic.
2.6.7
Embedded Broadcast Support in EVEX
EVEX encodes an embedded broadcast functionality that is supported on many vector instructions with 32-bit
(double word or single-precision floating-point) and 64-bit data elements, and when the source operand is from
memory. EVEX.b (P[20]) bit is used to enable broadcast on load-op instructions. When enabled, only one element
is loaded from memory and broadcasted to all other elements instead of loading the full memory size.
The following instruction classes do not support embedded broadcasting:
•
•
•
Instructions with only one scalar result is written to the vector destination.
Instructions with explicit broadcast functionality provided by its opcode.
Instruction semantic is a pure load or a pure store operation.
2.6.8
Static Rounding Support in EVEX
Static rounding control embedded in the EVEX encoding system applies only to register-to-register flavor of
floating-point instructions with rounding semantic at two distinct vector lengths: (i) scalar, (ii) 512-bit. In both
cases, the field EVEX.L’L expresses rounding mode control overriding MXCSR.RC if EVEX.b is set. When EVEX.b is
set, “suppress all exceptions” is implied. The processor behave as if all MXCSR masking controls are set.
2.6.9
SAE Support in EVEX
The EVEX encoding system allows arithmetic floating-point instructions without rounding semantic to be encoded
with the SAE attribute. This capability applies to scalar and 512-bit vector lengths, register-to-register only, by
setting EVEX.b. When EVEX.b is set, “suppress all exceptions” is implied. The processor behaves as if all MXCSR
masking controls are set.
2.6.10
Vector Length Orthogonality
The architecture of EVEX encoding scheme can support SIMD instructions operating at multiple vector lengths.
Many AVX-512 Foundation instructions operate at 512-bit vector length. The vector length of EVEX encoded vector
instructions are generally determined using the L’L field in EVEX prefix, except for 512-bit floating-point, reg-reg
instructions with rounding semantic. The table below shows the vector length corresponding to various values of
the L’L bits. When EVEX is used to encode scalar instructions, L’L is generally ignored.
When EVEX.b bit is set for a register-register instructions with floating-point rounding semantic, the same two bits
P2[6:5] specifies rounding mode for the instruction, with implied SAE behavior. The mapping of different instruction classes relative to the embedded broadcast/rounding/SAE control and the EVEX.L’L fields are summarized in
Table 2-36.
Table 2-36. EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions
Position
P2[4]
P2[6:5]
P2[6:5]
Broadcast/Rounding/SAE Context
EVEX.b
EVEX.L’L
EVEX.RC
Reg-reg, FP Instructions w/ rounding semantic
Enable static rounding
control (SAE implied)
Vector length Implied
(512 bit or scalar)
00b: SAE + RNE
01b: SAE + RD
10b: SAE + RU
11b: SAE + RZ
Vol. 2A 2-41
INSTRUCTION FORMAT
Table 2-36. EVEX Embedded Broadcast/Rounding/SAE and Vector Length on Vector Instructions
Position
P2[4]
P2[6:5]
P2[6:5]
Broadcast/Rounding/SAE Context
EVEX.b
EVEX.L’L
EVEX.RC
FP Instructions w/o rounding semantic, can cause #XF
SAE control
Load+op Instructions w/ memory source
Broadcast Control
Other Instructions (
Explicit Load/Store/Broadcast/Gather/Scatter)
Must be 0 (otherwise
#UD)
2.6.11
00b: 128-bit
01b: 256-bit
10b: 512-bit
11b: Reserved (#UD)
NA
NA
NA
#UD Equations for EVEX
Instructions encoded using EVEX can face three types of UD conditions: state dependent, opcode independent and
opcode dependent.
2.6.11.1
State Dependent #UD
In general, attempts of execute an instruction, which required OS support for incremental extended state component, will #UD if required state components were not enabled by OS. Table 2-37 lists instruction categories with
respect to required processor state components. Attempts to execute a given category of instructions while
enabled states were less than the required bit vector in XCR0 shown in Table 2-37 will cause #UD.
Table 2-37. OS XSAVE Enabling Requirements of Instruction Categories
Vector Register State Access
Required XCR0 Bit Vector [7:0]
Legacy SIMD prefix encoded Instructions (e.g SSE)
XMM
xxxxxx11b
VEX-encoded instructions operating on YMM
YMM
xxxxx111b
EVEX-encoded 128-bit instructions
ZMM
111xx111b
EVEX-encoded 256-bit instructions
ZMM
111xx111b
EVEX-encoded 512-bit instructions
ZMM
111xx111b
VEX-encoded instructions operating on opmask
k-reg
xx1xxx11b
Instruction Categories
2.6.11.2
Opcode Independent #UD
A number of bit fields in EVEX encoded instruction must obey mode-specific but opcode-independent patterns
listed in Table 2-38.
Table 2-38. Opcode Independent, State Dependent EVEX Bit Fields
Position
Notation
64-bit #UD
Non-64-bit #UD
P[3 : 2]
--
if > 0
if > 0
P[10]
--
if 0
if 0
P[1: 0]
EVEX.mm
if 00b
if 00b
P[7 : 6]
EVEX.RX
None (valid)
None (BOUND if EVEX.RX != 11b)
2.6.11.3
Opcode Dependent #UD
This section describes legal values for the rest of the EVEX bit fields. Table 2-39 lists the #UD conditions of EVEX
prefix bit fields which encodes or modifies register operands.
Table 2-39. #UD Conditions of Operand-Encoding EVEX Prefix Bit Fields
Notation
2-42 Vol. 2A
Position
Operand Encoding
64-bit #UD
Non-64-bit #UD
INSTRUCTION FORMAT
Table 2-39. #UD Conditions of Operand-Encoding EVEX Prefix Bit Fields (Contd.)
EVEX.R
EVEX.X
EVEX.B
EVEXR’
EVEX.vvvv
EVEXV’
P[7]
P[6]
P[5]
P[4]
P[14 : 11]
P[19]
ModRM.reg encodes k-reg
if EVEX.R = 0
ModRM.reg is opcode extension
None (ignored)
ModRM.reg encodes all other registers
None (valid)
ModRM.r/m encodes ZMM/YMM/XMM
None (valid)
ModRM.r/m encodes k-reg or GPR
None (ignored)
ModRM.r/m without SIB/VSIB
None (ignored)
ModRM.r/m with SIB/VSIB
None (valid)
ModRM.r/m encodes k-reg
None (ignored)
ModRM.r/m encodes other registers
None (valid)
ModRM.r/m base present
None (valid)
ModRM.r/m base not present
None (ignored)
ModRM.reg encodes k-reg or GPR
if 0
None (BOUND if
EVEX.RX != 11b)
None (ignored)
None (ignored)
ModRM.reg is opcode extension
None (ignored)
ModRM.reg encodes ZMM/YMM/XMM
None (valid)
vvvv encodes ZMM/YMM/XMM
None (valid)
None (valid)
P[14] ignored
Otherwise
if != 1111b
if != 1111b
Encodes ZMM/YMM/XMM
None (valid)
if 0
Otherwise
if 0
if 0
Table 2-40 lists the #UD conditions of instruction encoding of opmask register using EVEX.aaa and EVEX.z
Table 2-40. #UD Conditions of Opmask Related Encoding Field
Notation
EVEX.aaa
EVEX.z
Position
P[18 : 16]
P[23]
Operand Encoding
Instructions do not use opmask for conditional
64-bit #UD
processing1.
Non-64-bit #UD
if aaa != 000b
if aaa != 000b
Opmask used as conditional processing mask and updated
at completion2.
if aaa = 000b
if aaa = 000b;
Opmask used as conditional processing.
None (valid3)
None (valid1)
Vector instruction using opmask as source or destination4.
if EVEX.z != 0
if EVEX.z != 0
Store instructions or gather/scatter instructions.
if EVEX.z != 0
if EVEX.z != 0
Instruction supporting conditional processing mask with
EVEX.aaa = 000b.
if EVEX.z != 0
if EVEX.z != 0
NOTES:
1. E.g., VBROADCASTMxxx, VPMOVM2x, VPMOVx2M.
2. E.g., Gather/Scatter family.
3. aaa can take any value. A value of 000 indicates that there is no masking on the instruction; in this case, all elements will be processed as if there was a mask of ‘all ones’ regardless of the actual value in K0.
4. E.g., VFPCLASSPD/PS, VCMPB/D/Q/W family, VPMOVM2x, VPMOVx2M.
Table 2-41 lists the #UD conditions of EVEX bit fields that depends on the context of EVEX.b.
Table 2-41. #UD Conditions Dependent on EVEX.b Context
Notation
Position
Operand Encoding
64-bit #UD
Non-64-bit #UD
Vol. 2A 2-43
INSTRUCTION FORMAT
Table 2-41. #UD Conditions Dependent on EVEX.b Context (Contd.)
EVEX.L’Lb
P[22 : 20]
Reg-reg, FP instructions with rounding semantic.
None (valid1)
None (valid1)
Other reg-reg, FP instructions that can cause #XF.
None (valid2)
None (valid2)
Other reg-mem instructions in Table 2-34.
None (valid3)
None (valid3)
Other instruction classes4 in Table 2-35.
If EVEX.b > 0
If EVEX.b > 0
NOTES:
1. L’L specifies rounding control, see Table 2-36, supports {er} syntax.
2. L’L specifies vector length, see Table 2-36, supports {sae} syntax.
3. L’L specifies vector length, see Table 2-36, supports embedded broadcast syntax
4. L’L specifies either vector length or ignored.
2.6.12
Device Not Available
EVEX-encoded instructions follow the same rules when it comes to generating #NM (Device Not Available) exception. In particular, it is generated when CR0.TS[bit 3]= 1.
2.6.13
Scalar Instructions
EVEX-encoded scalar SIMD instructions can access up to 32 registers in 64-bit mode. Scalar instructions support
masking (using the least significant bit of the opmask register), but broadcasting is not supported.
2.7
EXCEPTION CLASSIFICATIONS OF EVEX-ENCODED INSTRUCTIONS
The exception behavior of EVEX-encoded instructions can be classified into the classes shown in the rest of this
section. The classification of EVEX-encoded instructions follow a similar framework as those of AVX and AVX2
instructions using the VEX prefix. Exception types for EVEX-encoded instructions are named in the style of
“E##” or with a suffix “E##XX”. The “##” designation generally follows that of AVX/AVX2 instructions. The
majority of EVEX encoded instruction with “Load+op” semantic supports memory fault suppression, which is represented by E##. The instructions with “Load+op” semantic but do not support fault suppression are named
“E##NF”. A summary table of exception classes by class names are shown below.
Table 2-42. EVEX-Encoded Instruction Exception Class Summary
Exception Class
Instruction set
Mem arg
(#XM)
Type E1
Vector Moves/Load/Stores
Explicitly aligned, w/ fault suppression
None
Type E1NF
Vector Non-temporal Stores
Explicitly aligned, no fault suppression
None
Type E2
FP Vector Load+op
Support fault suppression
Yes
Type E2NF
FP Vector Load+op
No fault suppression
Yes
Type E3
FP Scalar/Partial Vector, Load+Op
Support fault suppression
Yes
Type E3NF
FP Scalar/Partial Vector, Load+Op
No fault suppression
Yes
Type E4
Integer Vector Load+op
Support fault suppression
No
Type E4NF
Integer Vector Load+op
No fault suppression
No
Type E5
Legacy-like Promotion
Varies, Support fault suppression
No
Type E5NF
Legacy-like Promotion
Varies, No fault suppression
No
Type E6
Post AVX Promotion
Varies, w/ fault suppression
No
Type E6NF
Post AVX Promotion
Varies, no fault suppression
No
2-44 Vol. 2A
INSTRUCTION FORMAT
Table 2-42. EVEX-Encoded Instruction Exception Class Summary
Exception Class
Instruction set
Mem arg
(#XM)
Type E7NM
Register-to-register op
None
None
Type E9NF
Miscellaneous 128-bit
Vector-length Specific, no fault suppression
None
Type E10
Non-XF Scalar
Vector Length ignored, w/ fault suppression
None
Type E10NF
Non-XF Scalar
Vector Length ignored, no fault suppression
None
Type E11
VCVTPH2PS
Half Vector Length, w/ fault suppression
Yes
Type E11NF
VCVTPS2PH
Half Vector Length, no fault suppression
Yes
Type E12
Gather and Scatter Family
VSIB addressing, w/ fault suppression
None
Type E12NP
Gather and Scatter Prefetch Family
VSIB addressing, w/o page fault
None
Table 2-43 lists EVEX-encoded instruction mnemonic by exception classes.
Table 2-43. EVEX Instructions in each Exception Class
Exception Class
Type E1
Type E1NF
Instruction
VMOVAPD, VMOVAPS, VMOVDQA32, VMOVDQA64
VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS
VADDPD, VADDPS, VCMPPD, VCMPPS, VCVTDQ2PS, VCVTPD2DQ, VCVTPD2PS, VCVTPS2DQ, VCVTTPD2DQ,
VCVTTPS2DQ, VDIVPD, VDIVPS, VFMADDxxxPD, VFMADDxxxPS, VFMSUBADDxxxPD, VFMSUBADDxxxPS,
VFMSUBxxxPD, VFMSUBxxxPS, VFNMADDxxxPD, VFNMADDxxxPS, VFNMSUBxxxPD, VFNMSUBxxxPS, VMAXPD,
VMAXPS, VMINPD, VMINPS, VMULPD, VMULPS, VSQRTPD, VSQRTPS, VSUBPD, VSUBPS
Type E2
VCVTPD2QQ, VCVTPD2UQQ, VCVTPD2UDQ, VCVTPS2UDQS, VCVTQQ2PD, VCVTQQ2PS, VCVTTPD2DQ,
VCVTTPD2QQ, VCVTTPD2UDQ, VCVTTPD2UQQ, VCVTTPS2DQ, VCVTTPS2UDQ, VCVTUDQ2PS, VCVTUQQ2PD,
VCVTUQQ2PS, VFIXUPIMMPD, VFIXUPIMMPS, VGETEXPPD, VGETEXPPS, VGETMANTPD, VGETMANTPS, VRANGEPD,
VRANGEPS, VREDUCEPD, VREDUCEPS, VRNDSCALEPD, VRNDSCALEPS, VSCALEFPD, VSCALEFPS, VRCP28PD,
VRCP28PS, VRSQRT28PD, VRSQRT28PS
VADDSD, VADDSS, VCMPSD, VCMPSS, VCVTPS2PD, VCVTSD2SS, VCVTSS2SD, VDIVSD, VDIVSS, VMAXSD, VMAXSS,
VMINSD, VMINSS, VMULSD, VMULSS, VSQRTSD, VSQRTSS, VSUBSD, VSUBSS
Type E3
Type E3NF
VCVTPS2QQ, VCVTPS2UQQ, VCVTTPS2QQ, VCVTTPS2UQQ, VFMADDxxxSD, VFMADDxxxSS, VFMSUBxxxSD,
VFMSUBxxxSS, VFNMADDxxxSD, VFNMADDxxxSS, VFNMSUBxxxSD, VFNMSUBxxxSS, VFIXUPIMMSD,
VFIXUPIMMSS, VGETEXPSD, VGETEXPSS, VGETMANTSD, VGETMANTSS, VRANGESD, VRANGESS, VREDUCESD,
VREDUCESS, VRNDSCALESD, VRNDSCALESS, VSCALEFSD, VSCALEFSS, VRCP28SD, VRCP28SS, VRSQRT28SD,
VRSQRT28SS
VCOMISD, VCOMISS, VCVTSD2SI, VCVTSI2SD, VCVTSI2SS, VCVTSS2SI, VCVTTSD2SI, VCVTTSS2SI, VUCOMISD,
VUCOMISS
VCVTSD2USI, VCVTTSD2USI, VCVTSS2USI, VCVTTSS2USI, VCVTUSI2SD, VCVTUSI2SS
Vol. 2A 2-45
INSTRUCTION FORMAT
Table 2-43. EVEX Instructions in each Exception Class (Contd.)
Exception Class
Instruction
VANDPD, VANDPS, VANDNPD, VANDNPS, VORPD, VORPS, VPABSD, VPABSQ, VPADDD, VPADDQ, VPANDD, VPANDQ,
VPANDND, VPANDNQ, VPCMPEQD, VPCMPEQQ, VPCMPGTD, VPCMPGTQ, VPMAXSD, VPMAXSQ, VPMAXUD,
VPMAXUQ, VPMINSD, VPMINSQ, VPMINUD, VPMINUQ, VPMULLD, VPMULLQ, VPMULUDQ, VPMULDQ, VPORD,
VPORQ, VPSUBD, VPSUBQ, VPXORD, VPXORQ, VXORPD, VXORPS, VPSLLVD, VPSLLVQ,
Type E4
VBLENDMPD, VBLENDMPS, VPBLENDMD, VPBLENDMQ, VFPCLASSPD, VFPCLASSPS, VPCMPD, VPCMPQ, VPCMPUD,
VPCMPUQ, VPLZCNTD, VPLZCNTQ, VPROLD, VPROLQ, (VPSLLD, VPSLLQ, VPSRAD, VPSRAQ, VPSRLD, VPSRLQ)1,
VPTERNLOGD, VPTERNLOGQ, VPTESTMD, VPTESTMQ, VPTESTNMD, VPTESTNMQ, VRCP14PD, VRCP14PS,
VRSQRT14PD, VRSQRT14PS, VPCONFLICTD, VPCONFLICTQ, VPSRAVW, VPSRAVD, VPSRAVW, VPSRAVQ,
VPMADD52LUQ, VPMADD52HUQ
VMOVUPD, VMOVUPS, VMOVDQU8, VMOVDQU16, VMOVDQU32, VMOVDQU64, VPCMPB, VPCMPW, VPCMPUB,
VPCMPUW, VEXPANDPD, VEXPANDPS, VPCOMPRESSD, VPCOMPRESSQ, VPEXPANDD, VPEXPANDQ,
VCOMPRESSPD, VCOMPRESSPS, VPABSB, VPABSW, VPADDB, VPADDW, VPADDSB, VPADDSW, VPADDUSB,
VPADDUSW, VPAVGB, VPAVGW, VPCMPEQB, VPCMPEQW, VPCMPGTB, VPCMPGTW, VPMAXSB, VPMAXSW,
VPMAXUB, VPMAXUW, VPMINSB, VPMINSW, VPMINUB, VPMINUW, VPMULHRSW, VPMULHUW, VPMULHW,
VPMULLW, VPSUBB, VPSUBW, VPSUBSB, VPSUBSW, VPTESTMB, VPTESTMW, VPTESTNMB, VPTESTNMW, VPSLLW,
VPSRAW, VPSRLW, VPSLLVW, VPSRLVW
E4.nb2
VPACKSSDW, VPACKUSDW VPSHUFD, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKLDQ, VPUNPCKLQDQ, VSHUFPD,
VSHUFPS, VUNPCKHPD, VUNPCKHPS, VUNPCKLPD, VUNPCKLPS, VPERMD, VPERMPS, VPERMPD, VPERMQ,
Type E4NF
E4NF.nb
2
Type E5
VALIGND, VALIGNQ, VPERMI2D, VPERMI2PS, VPERMI2PD, VPERMI2Q, VPERMT2D, VPERMT2PS, VPERMT2Q,
VPERMT2PD, VPERMILPD, VPERMILPS, VSHUFI32X4, VSHUFI64X2, VSHUFF32X4, VSHUFF64X2,
VPMULTISHIFTQB
VDBPSADBW, VPACKSSWB, VPACKUSWB, VPALIGNR, VPMADDWD, VPMADDUBSW, VMOVSHDUP, VMOVSLDUP,
VPSADBW, VPSHUFB, VPSHUFHW, VPSHUFLW, VPSLLDQ, VPSRLDQ, VPSLLW, VPSRAW, VPSRLW, (VPSLLD,
VPSLLQ, VPSRAD, VPSRAQ, VPSRLD, VPSRLQ)3, VPUNPCKHBW, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLWD,
VPERMW, VPERMI2W, VPERMT2W, VPERMB, VPERMI2B, VPERMT2B
VCVTDQ2PD, PMOVSXBW, PMOVSXBW, PMOVSXBD, PMOVSXBQ, PMOVSXWD, PMOVSXWQ, PMOVSXDQ,
PMOVZXBW, PMOVZXBD, PMOVZXBQ, PMOVZXWD, PMOVZXWQ, PMOVZXDQ
VCVTUDQ2PD
Type E5NF
VMOVDDUP
VBROADCASTSS, VBROADCASTSD, VBROADCASTF32X4, VBROADCASTI32X4, VPBROADCASTB, VPBROADCASTD,
VPBROADCASTW, VPBROADCASTQ,
Type E6
Type E6NF
Type
E7NM.1284
Type E7NM.
2-46 Vol. 2A
VBROADCASTF32X2, VBROADCASTF32X4, VBROADCASTF64X2, VBROADCASTF32X8, VBROADCASTF64X4,
VBROADCASTI32X2, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X8, VBROADCASTI64X4,
VFPCLASSSD, VFPCLASSSS, VPMOVQB, VPMOVSQB, VPMOVUSQB, VPMOVQW, VPMOVSQW, VPMOVUSQW,
VPMOVQD, VPMOVSQD, VPMOVUSQD, VPMOVDB, VPMOVSDB, VPMOVUSDB, VPMOVDW, VPMOVSDW,
VPMOVUSDW
VEXTRACTF32X4, VEXTRACTF64X2, VEXTRACTF32X8, VINSERTF32X4, VINSERTF64X2, VINSERTF64X4,
VINSERTF32X8, VINSERTI32X4, VINSERTI64X2, VINSERTI64X4, VINSERTI32X8, VEXTRACTI32X4,
VEXTRACTI64X2, VEXTRACTI32X8, VEXTRACTI64X4, VPBROADCASTMB2Q, VPBROADCASTMW2D, VPMOVWB,
VPMOVSWB, VPMOVUSWB
VMOVLHPS, VMOVHLPS
(VPBROADCASTD, VPBROADCASTQ, VPBROADCASTB, VPBROADCASTW)5, VPMOVM2B, VPMOVM2D, VPMOVM2Q,
VPMOVM2W, VPMOVB2M, VPMOVD2M, VPMOVQ2M, VPMOVW2M
INSTRUCTION FORMAT
Table 2-43. EVEX Instructions in each Exception Class (Contd.)
Exception Class
Instruction
Type E9NF
VEXTRACTPS, VINSERTPS, VMOVHPD, VMOVHPS, VMOVLPD, VMOVLPS, VMOVD, VMOVQ, VPEXTRB, VPEXTRD,
VPEXTRW, VPEXTRQ, VPINSRB, VPINSRD, VPINSRW, VPINSRQ
Type E10
VMOVSD, VMOVSS, VRCP14SD, VRCP14SS, VRSQRT14SD, VRSQRT14SS,
Type E10NF
(VCVTSI2SD, VCVTUSI2SD)6
Type E11
VCVTPH2PS, VCVTPS2PH
Type E12
VGATHERDPS, VGATHERDPD, VGATHERQPS, VGATHERQPD, VPGATHERDD, VPGATHERDQ, VPGATHERQD,
VPGATHERQQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, VSCATTERDPD, VSCATTERDPS,
VSCATTERQPD, VSCATTERQPS
Type E12NP
VGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS,
VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD,
VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTERPF1DPS, VSCATTERPF1QPD, VSCATTERPF1QPS
NOTES:
1. Operand encoding FVI tupletype with immediate.
2. Embedded broadcast is not supported with the “.nb” suffix.
3. Operand encoding M128 tupletype.
4. #UD raised if EVEX.L’L !=00b (VL=128).
5. The source operand is a general purpose register.
6. W0 encoding only.
Vol. 2A 2-47
INSTRUCTION FORMAT
2.7.1
Exceptions Type E1 and E1NF of EVEX-Encoded Instructions
EVEX-encoded instructions with memory alignment restrictions, and supporting memory fault suppression follow
exception class E1.
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-44. Type E1 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
General Protection,
#GP(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and a memory address referencing the SS segment is in
a non-canonical form.
X
EVEX.512: Memory operand is not 64-byte aligned.
EVEX.256: Memory operand is not 32-byte aligned.
EVEX.128: Memory operand is not 16-byte aligned.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
2-48 Vol. 2A
Cause of Exception
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
X
X
If fault suppression not set, and a page fault.
INSTRUCTION FORMAT
EVEX-encoded instructions with memory alignment restrictions, but do not support memory fault suppression
follow exception class E1NF.
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-45. Type E1NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
General Protection,
#GP(0)
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
X
EVEX.512: Memory operand is not 64-byte aligned.
EVEX.256: Memory operand is not 32-byte aligned.
EVEX.128: Memory operand is not 16-byte aligned.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
X
Page Fault
#PF(fault-code)
Cause of Exception
X
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to FFFFH.
X
X
For a page fault.
Vol. 2A 2-49
INSTRUCTION FORMAT
2.7.2
Exceptions Type E2 of EVEX-Encoded Instructions
EVEX-encoded vector instructions with arithmetic semantic follow exception class E2.
X
X
X
Invalid Opcode,
#UD
X
Device Not Available, #NM
X
64-bit
X
Protected and
Compatibility
Virtual 8086
Exception
Real
Table 2-46. Type E2 Class Exception Conditions
If EVEX prefix present.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
General Protection, #GP(0)
X
X
Page Fault
#PF(fault-code)
2-50 Vol. 2A
X
If fault suppression not set, and a memory address referencing the SS segment is in a
non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the CS,
DS, ES, FS or GS segments.
X
SIMD Floatingpoint Exception,
#XM
Cause of Exception
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
X
X
If fault suppression not set, and a page fault.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION FORMAT
2.7.3
Exceptions Type E3 and E3NF of EVEX-Encoded Instructions
EVEX-encoded scalar instructions with arithmetic semantic that support memory fault suppression follow exception class E3.
X
X
X
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-47. Type E3 Class Exception Conditions
Cause of Exception
If EVEX prefix present.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in
the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes
or less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
X
Vol. 2A 2-51
INSTRUCTION FORMAT
EVEX-encoded scalar instructions with arithmetic semantic that do not support memory fault suppression follow
exception class E3NF.
X
X
X
Invalid Opcode, #UD
Device Not Available,
#NM
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-48. Type E3NF Class Exception Conditions
Cause of Exception
EVEX prefix.
X
X
If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
For an illegal address in the SS segment.
X
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes
or less is made while the current privilege level is 3.
X
X
X
If an unmasked SIMD floating-point exception, {sae} or {er} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
SIMD Floating-point
Exception, #XM
2-52 Vol. 2A
X
INSTRUCTION FORMAT
2.7.4
Exceptions Type E4 and E4NF of EVEX-Encoded Instructions
EVEX-encoded vector instructions that cause no SIMD FP exception and support memory fault suppression follow
exception class E4.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-49. Type E4 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0 and in E4.nb subclass (see E4.nb entries in Table 2-43).
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in
the CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
Page Fault #PF(faultcode)
Cause of Exception
X
X
If fault suppression not set, and a page fault.
Vol. 2A 2-53
INSTRUCTION FORMAT
EVEX-encoded vector instructions that do not cause SIMD FP exception nor support memory fault suppression
follow exception class E4NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-50. Type E4NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0 and in E4NF.nb subclass (see E4NF.nb entries in Table 2-43).
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
2-54 Vol. 2A
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
Page Fault #PF(faultcode)
Cause of Exception
X
X
For a page fault.
INSTRUCTION FORMAT
2.7.5
Exceptions Type E5 and E5NF
EVEX-encoded scalar/partial-vector instructions that cause no SIMD FP exception and support memory fault
suppression follow exception class E5.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-51. Type E5 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
EVEX-encoded scalar/partial vector instructions that do not cause SIMD FP exception nor support memory fault
suppression follow exception class E5NF.
Vol. 2A 2-55
INSTRUCTION FORMAT
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-52. Type E5NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
Cause of Exception
If an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-56 Vol. 2A
INSTRUCTION FORMAT
2.7.6
Exceptions Type E6 and E6NF
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-53. Type E6 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Invalid Opcode, #UD
Device Not Available,
#NM
X
Stack, SS(0)
General Protection,
#GP(0)
Cause of Exception
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
X
If fault suppression not set, and the memory address is in a non-canonical form.
Page Fault #PF(faultcode)
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference of 8 bytes or less is made while the current privilege
level is 3.
Vol. 2A 2-57
INSTRUCTION FORMAT
EVEX-encoded instructions that do not cause SIMD FP exception nor support memory fault suppression follow
exception class E6NF.
Invalid Opcode, #UD
Device Not Available,
#NM
Stack, SS(0)
General Protection,
#GP(0)
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-54. Type E6NF Class Exception Conditions
Cause of Exception
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
X
For an illegal address in the SS segment.
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If the memory address is in a non-canonical form.
Page Fault #PF(faultcode)
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
For 4 or 8 byte memory references if alignment checking is enabled and an
unaligned memory reference of 8 bytes or less is made while the current privilege
level is 3.
2-58 Vol. 2A
INSTRUCTION FORMAT
2.7.7
Exceptions Type E7NM
EVEX-encoded instructions that cause no SIMD FP exception and do not reference memory follow exception class
E7NM.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-55. Type E7NM Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• Instruction specific EVEX.L’L restriction not met.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
If CR0.TS[bit 3]=1.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
X
X
Cause of Exception
Vol. 2A 2-59
INSTRUCTION FORMAT
2.7.8
Exceptions Type E9 and E9NF
EVEX-encoded vector or partial-vector instructions that do not cause no SIMD FP exception and support memory
fault suppression follow exception class E9.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-56. Type E9 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 00b (VL=128).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-60 Vol. 2A
INSTRUCTION FORMAT
EVEX-encoded vector or partial-vector instructions that must be encoded with VEX.L’L = 0, do not cause SIMD FP
exception nor support memory fault suppression follow exception class E9NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-57. Type E9NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 00b (VL=128).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If an illegal address in the SS segment.
X
X
General Protection,
#GP(0)
Cause of Exception
If an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
X
If a memory address referencing the SS segment is in a non-canonical form.
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference is made while
the current privilege level is 3.
Vol. 2A 2-61
INSTRUCTION FORMAT
2.7.9
Exceptions Type E10
EVEX-encoded scalar instructions that ignore EVEX.L’L vector length encoding and do not cause no SIMD FP exception, support memory fault suppression follow exception class E10.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-58. Type E10 Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-62 Vol. 2A
INSTRUCTION FORMAT
EVEX-encoded scalar instructions that must be encoded with VEX.L’L = 0, do not cause SIMD FP exception nor
support memory fault suppression follow exception class E10NF.
X
64-bit
X
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-59. Type E10NF Class Exception Conditions
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
Invalid Opcode, #UD
X
Device Not Available,
#NM
X
Cause of Exception
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
X
Stack, SS(0)
If fault suppression not set, and an illegal address in the SS segment.
X
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
General Protection,
#GP(0)
X
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
Page Fault #PF(faultcode)
X
X
X
If fault suppression not set, and a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
Vol. 2A 2-63
INSTRUCTION FORMAT
2.7.10
Exception Type E11 (EVEX-only, mem arg no AC, floating-point exceptions)
EVEX-encoded instructions that can cause SIMD FP exception, memory operand support fault suppression but do
not cause #AC follow exception class E11.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-60. Type E11 Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a EVEX prefix.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
If fault suppression not set, and an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
Page Fault #PF (faultcode)
2-64 Vol. 2A
X
If fault suppression not set, and a memory address referencing the SS segment is
in a non-canonical form.
If fault suppression not set, and an illegal memory operand effective address in the
CS, DS, ES, FS or GS segments.
X
SIMD Floating-Point
Exception, #XM
Cause of Exception
X
If fault suppression not set, and the memory address is in a non-canonical form.
If fault suppression not set, and any part of the operand lies outside the effective
address space from 0 to FFFFH.
X
X
X
If fault suppression not set, and a page fault.
X
X
X
If an unmasked SIMD floating-point exception, {sae} not set, and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION FORMAT
2.7.11
Exception Type E12 and E12NP (VSIB mem arg, no AC, no floating-point exceptions)
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-61. Type E12 Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
• If vvvv != 1111b.
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm != ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If k0 is used (gather or scatter operation).
X
X
X
X
If index = destination register (gather operation).
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
Page Fault #PF (faultcode)
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
X
X
For a page fault.
Vol. 2A 2-65
INSTRUCTION FORMAT
EVEX-encoded prefetch instructions that do not cause #PF follow exception class E12NP.
Invalid Opcode, #UD
X
X
Device Not Available,
#NM
64-bit
Protected and
Compatibility
Virtual 80x86
Exception
Real
Table 2-62. Type E12NP Class Exception Conditions
X
X
If EVEX prefix present.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
• Opmask encoding #UD condition of Table 2-40.
• If EVEX.b != 0.
• If EVEX.L’L != 10b (VL=512).
X
X
If preceded by a LOCK prefix (F0H).
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
X
NA
If address size attribute is 16 bit.
X
X
X
X
If ModR/M.mod = ‘11b’.
X
X
X
X
If ModR/M.rm != ‘100b’.
X
X
X
X
If any corresponding CPUID feature flag is ‘0’.
X
X
X
X
If k0 is used (gather or scatter operation).
X
X
X
X
If CR0.TS[bit 3]=1.
Stack, SS(0)
X
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
X
X
X
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
X
2-66 Vol. 2A
Cause of Exception
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
INSTRUCTION FORMAT
2.8
EXCEPTION CLASSIFICATIONS OF OPMASK INSTRUCTIONS
The exception behavior of VEX-encoded opmask instructions are listed below.
Exception conditions of Opmask instructions that do not address memory are listed as Type K20.
Device Not Available,
#NM
X
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual 80x86
Exception
Real
Table 2-63. TYPE K20 Exception Definition (VEX-Encoded OpMask Instructions w/o Memory Arg)
X
X
Cause of Exception
If relevant CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
X
X
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
X
X
If ModRM:[7:6] != 11b.
X
X
If CR0.TS[bit 3]=1.
Vol. 2A 2-67
INSTRUCTION FORMAT
Exception conditions of Opmask instructions that address memory are listed as Type K21.
X
X
X
64-bit
X
Protected and
Compatibility
Invalid Opcode, #UD
Virtual 80x86
Exception
Real
Table 2-64. TYPE K21 Exception Definition (VEX-Encoded OpMask Instructions Addressing Memory)
X
X
X
X
X
X
X
X
X
Stack, SS(0)
X
X
X
X
If CR0.TS[bit 3]=1.
If any REX, F2, F3, or 66 prefixes precede a VEX prefix.
If a memory address referencing the SS segment is in a non-canonical form.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null
segment selector.
X
X
If CR4.OSXSAVE[bit 18]=0.
If any one of following conditions applies:
• State requirement, Table 2-37 not met.
• Opcode independent #UD condition in Table 2-38.
• Operand encoding #UD conditions in Table 2-39.
For an illegal address in the SS segment.
X
General Protection,
#GP(0)
If relevant CPUID feature flag is ‘0’.
If a VEX prefix is present.
X
Device Not Available,
#NM
Cause of Exception
X
If the memory address is in a non-canonical form.
If any part of the operand lies outside the effective address space from 0 to
FFFFH.
Page Fault #PF(faultcode)
X
X
X
For a page fault.
Alignment Check
#AC(0)
X
X
X
If alignment checking is enabled and an unaligned memory reference of 8 bytes or
less is made while the current privilege level is 3.
2-68 Vol. 2A
CHAPTER 3
INSTRUCTION SET REFERENCE, A-L
This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-L) in IA-32e, protected,
virtual-8086, and real-address modes of operation. The set includes general-purpose, x87 FPU, MMX,
SSE/SSE2/SSE3/SSSE3/SSE4, AESNI/PCLMULQDQ, AVX and system instructions. See also Chapter 4, “Instruction
Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, and
Chapter 5, “Instruction Set Reference, V-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2C.
For each instruction, each operand combination is described. A description of the instruction and its operand, an
operational description, a description of the effect of the instructions on flags in the EFLAGS register, and a
summary of exceptions that can be generated are also provided.
3.1
INTERPRETING THE INSTRUCTION REFERENCE PAGES
This section describes the format of information contained in the instruction reference pages in this chapter. It
explains notational conventions and abbreviations used in these sections.
3.1.1
Instruction Format
The following is an example of the format used for each instruction description in this chapter. The heading below
introduces the example. The table below provides an example summary table.
CMC—Complement Carry Flag [this is an example]
Opcode
Instruction
Op/En
64/32-bit CPUID
Description
Mode
Feature Flag
F5
CMC
A
V/V
NP
Complement carry flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Vol. 2A 3-1
INSTRUCTION SET REFERENCE, A-L
3.1.1.1
Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix)
The “Opcode” column in the table above shows the object code produced for each form of the instruction. When
possible, codes are given as hexadecimal bytes in the same order in which they appear in memory. Definitions of
entries other than hexadecimal bytes are as follows:
•
REX.W — Indicates the use of a REX prefix that affects operand size or instruction semantics. The ordering of
the REX prefix and other optional/mandatory instruction prefixes are discussed Chapter 2. Note that REX
prefixes that promote legacy instructions to 64-bit behavior are not listed explicitly in the opcode column.
•
/digit — A digit between 0 and 7 indicates that the ModR/M byte of the instruction uses only the r/m (register
or memory) operand. The reg field contains the digit that provides an extension to the instruction's opcode.
•
•
/r — Indicates that the ModR/M byte of the instruction contains a register operand and an r/m operand.
cb, cw, cd, cp, co, ct — A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp), 8-byte (co) or 10-byte (ct) value
following the opcode. This value is used to specify a code offset and possibly a new value for the code segment
register.
•
ib, iw, id, io — A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte (io) immediate operand to the instruction that
follows the opcode, ModR/M bytes or scale-indexing bytes. The opcode determines if the operand is a signed
value. All words, doublewords and quadwords are given with the low-order byte first.
•
+rb, +rw, +rd, +ro — Indicated the lower 3 bits of the opcode byte is used to encode the register operand
without a modR/M byte. The instruction lists the corresponding hexadecimal value of the opcode byte with low
3 bits as 000b. In non-64-bit mode, a register code, from 0 through 7, is added to the hexadecimal value of the
opcode byte. In 64-bit mode, indicates the four bit field of REX.b and opcode[2:0] field encodes the register
operand of the instruction. “+ro” is applicable only in 64-bit mode. See Table 3-1 for the codes.
•
+i — A number used in floating-point instructions when one of the operands is ST(i) from the FPU register stack.
The number i (which can range from 0 to 7) is added to the hexadecimal byte given at the left of the plus sign
to form a single opcode byte.
Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro
0
RAX
None
Reg Field
REX.B
Register
quadword register
(64-Bit Mode only)
Reg Field
REX.B
Register
dword register
Reg Field
REX.B
Register
word register
Reg Field
REX.B
Register
byte register
AL
None
0
AX
None
0
EAX
None
0
CL
None
1
CX
None
1
ECX
None
1
RCX
None
1
DL
None
2
DX
None
2
EDX
None
2
RDX
None
2
BL
None
3
BX
None
3
EBX
None
3
RBX
None
3
AH
Not
encodab
le (N.E.)
4
SP
None
4
ESP
None
4
N/A
N/A
N/A
CH
N.E.
5
BP
None
5
EBP
None
5
N/A
N/A
N/A
DH
N.E.
6
SI
None
6
ESI
None
6
N/A
N/A
N/A
BH
N.E.
7
DI
None
7
EDI
None
7
N/A
N/A
N/A
SPL
Yes
4
SP
None
4
ESP
None
4
RSP
None
4
BPL
Yes
5
BP
None
5
EBP
None
5
RBP
None
5
SIL
Yes
6
SI
None
6
ESI
None
6
RSI
None
6
DIL
Yes
7
DI
None
7
EDI
None
7
RDI
None
7
Registers R8 - R15 (see below): Available in 64-Bit Mode Only
R8L
Yes
0
R8W
Yes
0
R8D
Yes
0
R8
Yes
0
R9L
Yes
1
R9W
Yes
1
R9D
Yes
1
R9
Yes
1
R10L
Yes
2
R10W
Yes
2
R10D
Yes
2
R10
Yes
2
3-2 Vol. 2A
INSTRUCTION SET REFERENCE, A-L
Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.)
Reg Field
REX.B
Register
quadword register
(64-Bit Mode only)
Reg Field
REX.B
Register
dword register
Reg Field
REX.B
Register
word register
Reg Field
REX.B
Register
byte register
R11L
Yes
3
R11W
Yes
3
R11D
Yes
3
R11
Yes
3
R12L
Yes
4
R12W
Yes
4
R12D
Yes
4
R12
Yes
4
R13L
Yes
5
R13W
Yes
5
R13D
Yes
5
R13
Yes
5
R14L
Yes
6
R14W
Yes
6
R14D
Yes
6
R14
Yes
6
R15L
Yes
7
R15W
Yes
7
R15D
Yes
7
R15
Yes
7
3.1.1.2
Opcode Column in the Instruction Summary Table (Instructions with VEX prefix)
In the Instruction Summary Table, the Opcode column presents each instruction encoded using the VEX prefix in
following form (including the modR/M byte if applicable, the immediate byte if applicable):
VEX.[NDS].[128,256].[66,F2,F3].0F/0F3A/0F38.[W0,W1] opcode [/r] [/ib,/is4]
•
VEX — Indicates the presence of the VEX prefix is required. The VEX prefix can be encoded using the threebyte form (the first byte is C4H), or using the two-byte form (the first byte is C5H). The two-byte form of VEX
only applies to those instructions that do not require the following fields to be encoded: VEX.mmmmm, VEX.W,
VEX.X, VEX.B. Refer to Section 2.3 for more detail on the VEX prefix.
The encoding of various sub-fields of the VEX prefix is described using the following notations:
— NDS, NDD, DDS: Specifies that VEX.vvvv field is valid for the encoding of a register operand:
•
VEX.NDS: VEX.vvvv encodes the first source register in an instruction syntax where the content of
source registers will be preserved.
•
•
VEX.NDD: VEX.vvvv encodes the destination register that cannot be encoded by ModR/M:reg field.
•
VEX.DDS: VEX.vvvv encodes the second source register in a three-operand instruction syntax where
the content of first source register will be overwritten by the result.
If none of NDS, NDD, and DDS is present, VEX.vvvv must be 1111b (i.e. VEX.vvvv does not encode an
operand). The VEX.vvvv field can be encoded using either the 2-byte or 3-byte form of the VEX prefix.
— 128,256: VEX.L field can be 0 (denoted by VEX.128 or VEX.LZ) or 1 (denoted by VEX.256). The VEX.L field
can be encoded using either the 2-byte or 3-byte form of the VEX prefix. The presence of the notation
VEX.256 or VEX.128 in the opcode column should be interpreted as follows:
•
If VEX.256 is present in the opcode column: The semantics of the instruction must be encoded with
VEX.L = 1. An attempt to encode this instruction with VEX.L= 0 can result in one of two situations: (a)
if VEX.128 version is defined, the processor will behave according to the defined VEX.128 behavior; (b)
an #UD occurs if there is no VEX.128 version defined.
•
If VEX.128 is present in the opcode column but there is no VEX.256 version defined for the same
opcode byte: Two situations apply: (a) For VEX-encoded, 128-bit SIMD integer instructions, software
must encode the instruction with VEX.L = 0. The processor will treat the opcode byte encoded with
VEX.L= 1 by causing an #UD exception; (b) For VEX-encoded, 128-bit packed floating-point instructions, software must encode the instruction with VEX.L = 0. The processor will treat the opcode byte
encoded with VEX.L= 1 by causing an #UD exception (e.g. VMOVLPS).
•
If VEX.LIG is present in the opcode column: The VEX.L value is ignored. This generally applies to VEXencoded scalar SIMD floating-point instructions. Scalar SIMD floating-point instruction can be distinguished from the mnemonic of the instruction. Generally, the last two letters of the instruction
mnemonic would be either “SS“, “SD“, or “SI“ for SIMD floating-point conversion instructions.
•
If VEX.LZ is present in the opcode column: The VEX.L must be encoded to be 0B, an #UD occurs if
VEX.L is not zero.
Vol. 2A 3-3
INSTRUCTION SET REFERENCE, A-L
— 66,F2,F3: The presence or absence of these values map to the VEX.pp field encodings. If absent, this
corresponds to VEX.pp=00B. If present, the corresponding VEX.pp value affects the “opcode” byte in the
same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing opcode byte. Thus a non-zero encoding
of VEX.pp may be considered as an implied 66H/F2H/F3H prefix. The VEX.pp field may be encoded using
either the 2-byte or 3-byte form of the VEX prefix.
— 0F,0F3A,0F38: The presence maps to a valid encoding of the VEX.mmmmm field. Only three encoded
values of VEX.mmmmm are defined as valid, corresponding to the escape byte sequence of 0FH, 0F3AH
and 0F38H. The effect of a valid VEX.mmmmm encoding on the ensuing opcode byte is same as if the corresponding escape byte sequence on the ensuing opcode byte for non-VEX encoded instructions. Thus a valid
encoding of VEX.mmmmm may be consider as an implies escape byte sequence of either 0FH, 0F3AH or
0F38H. The VEX.mmmmm field must be encoded using the 3-byte form of VEX prefix.
— 0F,0F3A,0F38 and 2-byte/3-byte VEX: The presence of 0F3A and 0F38 in the opcode column implies
that opcode can only be encoded by the three-byte form of VEX. The presence of 0F in the opcode column
does not preclude the opcode to be encoded by the two-byte of VEX if the semantics of the opcode does not
require any subfield of VEX not present in the two-byte form of the VEX prefix.
— W0: VEX.W=0.
— W1: VEX.W=1.
— The presence of W0/W1 in the opcode column applies to two situations: (a) it is treated as an extended
opcode bit, (b) the instruction semantics support an operand size promotion to 64-bit of a general-purpose
register operand or a 32-bit memory operand. The presence of W1 in the opcode column implies the opcode
must be encoded using the 3-byte form of the VEX prefix. The presence of W0 in the opcode column does
not preclude the opcode to be encoded using the C5H form of the VEX prefix, if the semantics of the opcode
does not require other VEX subfields not present in the two-byte form of the VEX prefix. Please see Section
2.3 on the subfield definitions within VEX.
— WIG: can use C5H form (if not requiring VEX.mmmmm) or VEX.W value is ignored in the C4H form of VEX
prefix.
— If WIG is present, the instruction may be encoded using either the two-byte form or the three-byte form of
VEX. When encoding the instruction using the three-byte form of VEX, the value of VEX.W is ignored.
•
•
opcode — Instruction opcode.
•
In general, the encoding o f VEX.R, VEX.X, VEX.B field are not shown explicitly in the opcode column. The
encoding scheme of VEX.R, VEX.X, VEX.B fields must follow the rules defined in Section 2.3.
/is4 — An 8-bit immediate byte is present containing a source register specifier in either imm8[7:4] (for 64bit mode) or imm8[6:4] (for 32-bit mode), and instruction-specific payload in imm8[3:0].
EVEX.[NDS/NDD/DDS].[128,256,512,LIG].[66,F2,F3].0F/0F3A/0F38.[W0,W1,WIG] opcode [/r] [ib]
•
EVEX — The EVEX prefix is encoded using the four-byte form (the first byte is 62H). Refer to Section 2.6.1 for
more detail on the EVEX prefix.
The encoding of various sub-fields of the EVEX prefix is described using the following notations:
— NDS, NDD, DDS: implies that EVEX.vvvv (and EVEX.v’) field is valid for the encoding of an operand. It may
specify either the source register (NDS) or the destination register (NDD). DDS expresses a syntax where
vvvv encodes the second source register in a three-operand instruction syntax where the content of first
source register will be overwritten by the result. If both NDS and NDD absent (i.e. EVEX.vvvv does not
encode an operand), EVEX.vvvv must be 1111b (and EVEX.v’ must be 1b).
— 128, 256, 512, LIG: This corresponds to the vector length; three values are allowed by EVEX: 512-bit,
256-bit and 128-bit. Alternatively, vector length is ignored (LIG) for certain instructions; this typically
applies to scalar instructions operating on one data element of a vector register.
— 66,F2,F3: The presence of these value maps to the EVEX.pp field encodings. The corresponding VEX.pp
value affects the “opcode” byte in the same way as if a SIMD prefix (66H, F2H or F3H) does to the ensuing
opcode byte. Thus a non-zero encoding of VEX.pp may be considered as an implied 66H/F2H/F3H prefix.
— 0F,0F3A,0F38: The presence maps to a valid encoding of the EVEX.mmm field. Only three encoded values
of EVEX.mmm are defined as valid, corresponding to the escape byte sequence of 0FH, 0F3AH and 0F38H.
3-4 Vol. 2A
INSTRUCTION SET REFERENCE, A-L
The effect of a valid EVEX.mmm encoding on the ensuing opcode byte is the same as if the corresponding
escape byte sequence on the ensuing opcode byte for non-EVEX encoded instructions. Thus a valid
encoding of EVEX.mmm may be considered as an implied escape byte sequence of either 0FH, 0F3AH or
0F38H.
— W0: EVEX.W=0.
— W1: EVEX.W=1.
— WIG: EVEX.W bit ignored
•
•
opcode — Instruction opcode.
In general, the encoding of EVEX.R and R’, EVEX.X and X’, and EVEX.B and B’ fields are not shown explicitly in
the opcode column.
3.1.1.3
Instruction Column in the Opcode Summary Table
The “Instruction” column gives the syntax of the instruction statement as it would appear in an ASM386 program.
The following is a list of the symbols used to represent operands in the instruction statements:
•
rel8 — A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the
end of the instruction.
•
rel16, rel32 — A relative address within the same code segment as the instruction assembled. The rel16
symbol applies to instructions with an operand-size attribute of 16 bits; the rel32 symbol applies to instructions
with an operand-size attribute of 32 bits.
•
ptr16:16, ptr16:32 — A far pointer, typically to a code segment different from that of the instruction. The
notation 16:16 indicates that the value of the pointer has two parts. The value to the left of the colon is a 16bit selector or value destined for the code segment register. The value to the right corresponds to the offset
within the destination segment. The ptr16:16 symbol is used when the instruction's operand-size attribute is
16 bits; the ptr16:32 symbol is used when the operand-size attribute is 32 bits.
•
r8 — One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL; or one
of the byte registers (R8L - R15L) available when using REX.R and 64-bit mode.
•
r16 — One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI; or one of the word registers
(R8-R15) available when using REX.R and 64-bit mode.
•
r32 — One of the doubleword general-purpose registers: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI; or one of
the doubleword registers (R8D - R15D) available when using REX.R in 64-bit mode.
•
r64 — One of the quadword general-purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8–R15.
These are available when using REX.R and 64-bit mode.
•
imm8 — An immediate byte value. The imm8 symbol is a signed number between –128 and +127 inclusive.
For instructions in which imm8 is combined with a word or doubleword operand, the immediate value is signextended to form a word or doubleword. The upper byte of the word is filled with the topmost bit of the
immediate value.
•
imm16 — An immediate word value used for instructions whose operand-size attribute is 16 bits. This is a
number between –32,768 and +32,767 inclusive.
•
imm32 — An immediate doubleword value used for instructions whose operand-size attribute is 32
bits. It allows the use of a number between +2,147,483,647 and –2,147,483,648 inclusive.
•
imm64 — An immediate quadword value used for instructions whose operand-size attribute is 64 bits.
The value allows the use of a number between +9,223,372,036,854,775,807 and –
9,223,372,036,854,775,808 inclusive.
•
r/m8 — A byte operand that is either the contents of a byte general-purpose register (AL, CL, DL, BL, AH, CH,
DH, BH, BPL, SPL, DIL and SIL) or a byte from memory. Byte registers R8L - R15L are available using REX.R in
64-bit mode.
•
r/m16 — A word general-purpose register or memory operand used for instructions whose operand-size
attribute is 16 bits. The word general-purpose registers are: AX, CX, DX, BX, SP, BP, SI, DI. The contents of
memory are found at the address provided by the effective address computation. Word registers R8W - R15W
are available using REX.R in 64-bit mode.
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•
r/m32 — A doubleword general-purpose register or memory operand used for instructions whose operandsize attribute is 32 bits. The doubleword general-purpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI,
EDI. The contents of memory are found at the address provided by the effective address computation.
Doubleword registers R8D - R15D are available when using REX.R in 64-bit mode.
•
r/m64 — A quadword general-purpose register or memory operand used for instructions whose operand-size
attribute is 64 bits when using REX.W. Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI,
RSI, RBP, RSP, R8–R15; these are available only in 64-bit mode. The contents of memory are found at the
address provided by the effective address computation.
•
•
m — A 16-, 32- or 64-bit operand in memory.
•
m16 — A word operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.
•
m32 — A doubleword operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. This nomenclature is used only with the string instructions.
•
•
•
m64 — A memory quadword operand in memory.
m8 — A byte operand in memory, usually expressed as a variable or array name, but pointed to by the
DS:(E)SI or ES:(E)DI registers. In 64-bit mode, it is pointed to by the RSI or RDI registers.
m128 — A memory double quadword operand in memory.
m16:16, m16:32 & m16:64 — A memory operand containing a far pointer composed of two numbers. The
number to the left of the colon corresponds to the pointer's segment selector. The number to the right
corresponds to its offset.
•
m16&32, m16&16, m32&32, m16&64 — A memory operand consisting of data item pairs whose sizes are
indicated on the left and the right side of the ampersand. All memory addressing modes are allowed. The
m16&16 and m32&32 operands are used by the BOUND instruction to provide an operand containing an upper
and lower bounds for array indices. The m16&32 operand is used by LIDT and LGDT to provide a word with
which to load the limit field, and a doubleword with which to load the base field of the corresponding GDTR and
IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to provide a word with which to
load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR
registers.
•
moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memory offset) of type byte, word, or
doubleword used by some variants of the MOV instruction. The actual address is given by a simple offset
relative to the segment base. No ModR/M byte is used in the instruction. The number shown with moffs
indicates its size, which is determined by the address-size attribute of the instruction.
•
Sreg — A segment register. The segment register bit assignments are ES = 0, CS = 1, SS = 2, DS = 3, FS = 4,
and GS = 5.
•
m32fp, m64fp, m80fp — A single-precision, double-precision, and double extended-precision (respectively)
floating-point operand in memory. These symbols designate floating-point values that are used as operands for
x87 FPU floating-point instructions.
•
m16int, m32int, m64int — A word, doubleword, and quadword integer (respectively) operand in memory.
These symbols designate integers that are used as operands for x87 FPU integer instructions.
•
•
•
•
ST or ST(0) — The top element of the FPU register stack.
•
mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMX registers are: MM0 through MM7.
The contents of memory are found at the address provided by the effective address computation.
•
xmm — An XMM register. The 128-bit XMM registers are: XMM0 through XMM7; XMM8 through XMM15 are
available using REX.R in 64-bit mode.
•
xmm/m32— An XMM register or a 32-bit memory operand. The 128-bit XMM registers are XMM0 through
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at
the address provided by the effective address computation.
ST(i) — The ith element from the top of the FPU register stack (i ← 0 through 7).
mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.
mm/m32 — The low order 32 bits of an MMX register or a 32-bit memory operand. The 64-bit MMX registers
are: MM0 through MM7. The contents of memory are found at the address provided by the effective address
computation.
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•
xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMD floating-point registers are
XMM0 through XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of
memory are found at the address provided by the effective address computation.
•
xmm/m128 — An XMM register or a 128-bit memory operand. The 128-bit XMM registers are XMM0 through
XMM7; XMM8 through XMM15 are available using REX.R in 64-bit mode. The contents of memory are found at
the address provided by the effective address computation.
•
<XMM0>— Indicates implied use of the XMM0 register.
When there is ambiguity, xmm1 indicates the first source operand using an XMM register and xmm2 the second
source operand using an XMM register.
Some instructions use the XMM0 register as the third source operand, indicated by <XMM0>. The use of the
third XMM register operand is implicit in the instruction encoding and does not affect the ModR/M encoding.
•
ymm — A YMM register. The 256-bit YMM registers are: YMM0 through YMM7; YMM8 through YMM15 are
available in 64-bit mode.
•
•
•
•
•
m256 — A 32-byte operand in memory. This nomenclature is used only with AVX instructions.
•
•
•
m512 — A 64-byte operand in memory.
•
{k1} — Without {z}: a mask register used as instruction writemask for instructions that do not allow zeroingmasking but support merging-masking. This corresponds to instructions that require the value of the aaa field
to be different than 0 (e.g., gather) and store-type instructions which allow only merging-masking.
•
k1 — A mask register used as a regular operand (either destination or source). The 64-bit k registers are: k0
through k7.
•
•
mV — A vector memory operand; the operand size is dependent on the instruction.
ymm/m256 — A YMM register or 256-bit memory operand.
<YMM0>— Indicates use of the YMM0 register as an implicit argument.
bnd — A 128-bit bounds register. BND0 through BND3.
mib — A memory operand using SIB addressing form, where the index register is not used in address calculation, Scale is ignored. Only the base and displacement are used in effective address calculation.
zmm/m512 — A ZMM register or 512-bit memory operand.
{k1}{z} — A mask register used as instruction writemask. The 64-bit k registers are: k1 through k7.
Writemask specification is available exclusively via EVEX prefix. The masking can either be done as a mergingmasking, where the old values are preserved for masked out elements or as a zeroing masking. The type of
masking is determined by using the EVEX.z bit.
vm32{x,y, z} — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
register with individual elements of 32-bit index value in an XMM register (vm32x), a YMM register (vm32y) or
a ZMM register (vm32z).
•
vm64{x,y, z} — A vector array of memory operands specified using VSIB memory addressing. The array of
memory addresses are specified using a common base register, a constant scale factor, and a vector index
register with individual elements of 64-bit index value in an XMM register (vm64x), a YMM register (vm64y) or
a ZMM register (vm64z).
•
zmm/m512/m32bcst — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit
vector loaded from a 32-bit memory location.
•
zmm/m512/m64bcst — An operand that can be a ZMM register, a 512-bit memory location or a 512-bit
vector loaded from a 64-bit memory location.
•
•
<ZMM0> — Indicates use of the ZMM0 register as an implicit argument.
•
{sae} — Indicates support for SAE (Suppress All Exceptions). This is used for instructions that support SAE,
but do not support embedded rounding control.
•
SRC1 — Denotes the first source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having two or more source operands.
{er} — Indicates support for embedded rounding control, which is only applicable to the register-register form
of the instruction. This also implies support for SAE (Suppress All Exceptions).
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•
SRC2 — Denotes the second source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having two or more source operands.
•
SRC3 — Denotes the third source operand in the instruction syntax of an instruction encoded with the
VEX/EVEX prefix and having three source operands.
•
•
SRC — The source in a single-source instruction.
DST — the destination in an instruction. This field is encoded by reg_field.
3.1.1.4
Operand Encoding Column in the Instruction Summary Table
The “operand encoding” column is abbreviated as Op/En in the Instruction Summary table heading. Instruction
operand encoding information is provided for each assembly instruction syntax using a letter to cross reference to
a row entry in the operand encoding definition table that follows the instruction summary table. The operand
encoding table in each instruction reference page lists each instruction operand (according to each instruction
syntax and operand ordering shown in the instruction column) relative to the ModRM byte, VEX.vvvv field or additional operand encoding placement.
EVEX encoded instructions employ compressed disp8*N encoding of the displacement bytes, where N is defined in
Table 2-34 and Table 2-35, according to tupletypes. The Op/En column of an EVEX encoded instruction uses an
abbreviation that corresponds to the tupletype abbreviation (and may include an additional abbreviation related to
ModR/M and vvvv encoding). Most EVEX encoded instructions with VEX encoded equivalent have the ModR/M and
vvvv encoding order. In such cases, the Tuple abbreviation is shown and the ModR/M, vvvv encoding abbreviation
may be omitted.
NOTES
•
•
3.1.1.5
The letters in the Op/En column of an instruction apply ONLY to the encoding definition table
immediately following the instruction summary table.
In the encoding definition table, the letter ‘r’ within a pair of parenthesis denotes the content of
the operand will be read by the processor. The letter ‘w’ within a pair of parenthesis denotes the
content of the operand will be updated by the processor.
64/32-bit Mode Column in the Instruction Summary Table
The “64/32-bit Mode” column indicates whether the opcode sequence is supported in (a) 64-bit mode or (b) the
Compatibility mode and other IA-32 modes that apply in conjunction with the CPUID feature flag associated
specific instruction extensions.
The 64-bit mode support is to the left of the ‘slash’ and has the following notation:
•
•
•
V — Supported.
•
•
•
N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode.
I — Not supported.
N.E. — Indicates an instruction syntax is not encodable in 64-bit mode (it may represent part of a sequence of
valid instructions in other modes).
N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode.
N.S. — Indicates an instruction syntax that requires an address override prefix in 64-bit mode and is not
supported. Using an address override prefix in 64-bit mode may result in model-specific execution behavior.
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The Compatibility/Legacy Mode support is to the right of the ‘slash’ and has the following notation:
• V — Supported.
• I — Not supported.
• N.E. — Indicates an Intel 64 instruction mnemonics/syntax that is not encodable; the opcode sequence is not
applicable as an individual instruction in compatibility mode or IA-32 mode. The opcode may represent a valid
sequence of legacy IA-32 instructions.
3.1.1.6
CPUID Support Column in the Instruction Summary Table
The fourth column holds abbreviated CPUID feature flags (e.g., appropriate bit in CPUID.1.ECX, CPUID.1.EDX
for SSE/SSE2/SSE3/SSSE3/SSE4.1/SSE4.2/AESNI/PCLMULQDQ/AVX/RDRAND support) that indicate processor
support for the instruction. If the corresponding flag is ‘0’, the instruction will #UD.
3.1.1.7
Description Column in the Instruction Summary Table
The “Description” column briefly explains forms of the instruction.
3.1.1.8
Description Section
Each instruction is then described by number of information sections. The “Description” section describes the
purpose of the instructions and required operands in more detail.
Summary of terms that may be used in the description section:
•
Legacy SSE — Refers to SSE, SSE2, SSE3, SSSE3, SSE4, AESNI, PCLMULQDQ and any future instruction sets
referencing XMM registers and encoded without a VEX prefix.
•
•
•
VEX.vvvv — The VEX bit field specifying a source or destination register (in 1’s complement form).
rm_field — shorthand for the ModR/M r/m field and any REX.B
reg_field — shorthand for the ModR/M reg field and any REX.R
3.1.1.9
Operation Section
The “Operation” section contains an algorithm description (frequently written in pseudo-code) for the instruction.
Algorithms are composed of the following elements:
•
•
Comments are enclosed within the symbol pairs “(*” and “*)”.
•
A register name implies the contents of the register. A register name enclosed in brackets implies the contents
of the location whose address is contained in that register. For example, ES:[DI] indicates the contents of the
location whose ES segment relative address is in register DI. [SI] indicates the contents of the address
contained in register SI relative to the SI register’s default segment (DS) or the overridden segment.
•
Parentheses around the “E” in a general-purpose register name, such as (E)SI, indicates that the offset is read
from the SI register if the address-size attribute is 16, from the ESI register if the address-size attribute is 32.
Parentheses around the “R” in a general-purpose register name, (R)SI, in the presence of a 64-bit register
definition such as (R)SI, indicates that the offset is read from the 64-bit RSI register if the address-size
attribute is 64.
•
Brackets are used for memory operands where they mean that the contents of the memory location is a
segment-relative offset. For example, [SRC] indicates that the content of the source operand is a segmentrelative offset.
•
•
A ← B indicates that the value of B is assigned to A.
Compound statements are enclosed in keywords, such as: IF, THEN, ELSE and FI for an if statement; DO and
OD for a do statement; or CASE... OF for a case statement.
The symbols =, ≠, >, <, ≥, and ≤ are relational operators used to compare two values: meaning equal, not
equal, greater or equal, less or equal, respectively. A relational expression such as A = B is TRUE if the value of
A is equal to B; otherwise it is FALSE.
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•
The expression “« COUNT” and “» COUNT” indicates that the destination operand should be shifted left or right
by the number of bits indicated by the count operand.
The following identifiers are used in the algorithmic descriptions:
•
OperandSize and AddressSize — The OperandSize identifier represents the operand-size attribute of the
instruction, which is 16, 32 or 64-bits. The AddressSize identifier represents the address-size attribute, which
is 16, 32 or 64-bits. For example, the following pseudo-code indicates that the operand-size attribute depends
on the form of the MOV instruction used.
IF Instruction = MOVW
THEN OperandSize ← 16;
ELSE
IF Instruction = MOVD
THEN OperandSize ← 32;
ELSE
IF Instruction = MOVQ
THEN OperandSize ← 64;
FI;
FI;
FI;
See “Operand-Size and Address-Size Attributes” in Chapter 3 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 1, for guidelines on how these attributes are determined.
•
StackAddrSize — Represents the stack address-size attribute associated with the instruction, which has a
value of 16, 32 or 64-bits. See “Address-Size Attribute for Stack” in Chapter 6, “Procedure Calls, Interrupts, and
Exceptions,” of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
•
•
•
SRC — Represents the source operand.
DEST — Represents the destination operand.
VLMAX — The maximum vector register width pertaining to the instruction. This is not the vector-length
encoding in the instruction's prefix but is instead determined by the current value of XCR0. For existing
processors, VLMAX is 256 whenever XCR0.YMM[bit 2] is 1. Future processors may defined new bits in XCR0
whose setting may imply other values for VLMAX.
VLMAX Definition
XCR0 Component
VLMAX
XCR0.YMM
256
The following functions are used in the algorithmic descriptions:
•
ZeroExtend(value) — Returns a value zero-extended to the operand-size attribute of the instruction. For
example, if the operand-size attribute is 32, zero extending a byte value of –10 converts the byte from F6H to
a doubleword value of 000000F6H. If the value passed to the ZeroExtend function and the operand-size
attribute are the same size, ZeroExtend returns the value unaltered.
•
SignExtend(value) — Returns a value sign-extended to the operand-size attribute of the instruction. For
example, if the operand-size attribute is 32, sign extending a byte containing the value –10 converts the byte
from F6H to a doubleword value of FFFFFFF6H. If the value passed to the SignExtend function and the operandsize attribute are the same size, SignExtend returns the value unaltered.
•
SaturateSignedWordToSignedByte — Converts a signed 16-bit value to a signed 8-bit value. If the signed
16-bit value is less than –128, it is represented by the saturated value -128 (80H); if it is greater than 127, it
is represented by the saturated value 127 (7FH).
•
SaturateSignedDwordToSignedWord — Converts a signed 32-bit value to a signed 16-bit value. If the
signed 32-bit value is less than –32768, it is represented by the saturated value –32768 (8000H); if it is greater
than 32767, it is represented by the saturated value 32767 (7FFFH).
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•
SaturateSignedWordToUnsignedByte — Converts a signed 16-bit value to an unsigned 8-bit value. If the
signed 16-bit value is less than zero, it is represented by the saturated value zero (00H); if it is greater than
255, it is represented by the saturated value 255 (FFH).
•
SaturateToSignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less
than –128, it is represented by the saturated value –128 (80H); if it is greater than 127, it is represented by
the saturated value 127 (7FH).
•
SaturateToSignedWord — Represents the result of an operation as a signed 16-bit value. If the result is less
than –32768, it is represented by the saturated value –32768 (8000H); if it is greater than 32767, it is
represented by the saturated value 32767 (7FFFH).
•
SaturateToUnsignedByte — Represents the result of an operation as a signed 8-bit value. If the result is less
than zero it is represented by the saturated value zero (00H); if it is greater than 255, it is represented by the
saturated value 255 (FFH).
•
SaturateToUnsignedWord — Represents the result of an operation as a signed 16-bit value. If the result is
less than zero it is represented by the saturated value zero (00H); if it is greater than 65535, it is represented
by the saturated value 65535 (FFFFH).
•
LowOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the least significant
word of the doubleword result in the destination operand.
•
HighOrderWord(DEST * SRC) — Multiplies a word operand by a word operand and stores the most
significant word of the doubleword result in the destination operand.
•
Push(value) — Pushes a value onto the stack. The number of bytes pushed is determined by the operand-size
attribute of the instruction. See the “Operation” subsection of the “PUSH—Push Word, Doubleword or
Quadword Onto the Stack” section in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B.
•
Pop() — removes the value from the top of the stack and returns it. The statement EAX ← Pop(); assigns to
EAX the 32-bit value from the top of the stack. Pop will return either a word, a doubleword or a quadword
depending on the operand-size attribute. See the “Operation” subsection in the “POP—Pop a Value from the
Stack” section of Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
•
PopRegisterStack — Marks the FPU ST(0) register as empty and increments the FPU register stack pointer
(TOP) by 1.
•
•
Switch-Tasks — Performs a task switch.
Bit(BitBase, BitOffset) — Returns the value of a bit within a bit string. The bit string is a sequence of bits in
memory or a register. Bits are numbered from low-order to high-order within registers and within memory
bytes. If the BitBase is a register, the BitOffset can be in the range 0 to [15, 31, 63] depending on the mode
and register size. See Figure 3-1: the function Bit[RAX, 21] is illustrated.
63
31
21
0
Bit Offset ← 21
Figure 3-1. Bit Offset for BIT[RAX, 21]
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INSTRUCTION SET REFERENCE, A-L
If BitBase is a memory address, the BitOffset can range has different ranges depending on the operand size
(see Table 3-2).
Table 3-2. Range of Bit Positions Specified by Bit Offset Operands
Operand Size
Immediate BitOffset
Register BitOffset
16
0 to 15
− 215 to 215 − 1
32
0 to 31
− 231 to 231 − 1
64
0 to 63
− 263 to 263 − 1
The addressed bit is numbered (Offset MOD 8) within the byte at address (BitBase + (BitOffset DIV 8)) where
DIV is signed division with rounding towards negative infinity and MOD returns a positive number (see
Figure 3-2).
7
5
0 7
BitBase +
0 7
BitBase
0
BitBase −
BitOffset ← +13
7
0 7
BitBase
0 7
BitBase −
5
0
BitBase −
BitOffset ← −
Figure 3-2. Memory Bit Indexing
3.1.1.10
Intel® C/C++ Compiler Intrinsics Equivalents Section
The Intel C/C++ compiler intrinsic functions give access to the full power of the Intel Architecture Instruction Set,
while allowing the compiler to optimize register allocation and instruction scheduling for faster execution. Most of
these functions are associated with a single IA instruction, although some may generate multiple instructions or
different instructions depending upon how they are used. In particular, these functions are used to invoke instructions that perform operations on vector registers that can hold multiple data elements. These SIMD instructions
use the following data types.
•
__m128, __m256 and __m512 can represent 4, 8 or 16 packed single-precision floating-point values, and are
used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128 data
type is also used with various single-precision floating-point scalar instructions that perform calculations using
only the lowest 32 bits of a vector register; the remaining bits of the result come from one of the sources or are
set to zero depending upon the instruction.
•
__m128d, __m256d and __m512d can represent 2, 4 or 8 packed double-precision floating-point values, and
are used with the vector registers and SSE, AVX, or AVX-512 instruction set extension families. The __m128d
data type is also used with various double-precision floating-point scalar instructions that perform calculations
using only the lowest 64 bits of a vector register; the remaining bits of the result come from one of the sources
or are set to zero depending upon the instruction.
•
__m128i, __m256i and __m512i can represent integer data in bytes, words, doublewords, quadwords, and
occasionally larger data types.
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Each of these data types incorporates in its name the number of bits it can hold. For example, the __m128 type
holds 128 bits, and because each single-precision floating-point value is 32 bits long the __m128 type holds
(128/32) or four values. Normally the compiler will allocate memory for these data types on an even multiple of the
size of the type. Such aligned memory locations may be faster to read and write than locations at other addresses.
These SIMD data types are not basic Standard C data types or C++ objects, so they may be used only with the
assignment operator, passed as function arguments, and returned from a function call. If you access the internal
members of these types directly, or indirectly by using them in a union, there may be side effects affecting optimization, so it is recommended to use them only with the SIMD instruction intrinsic functions described in this manual
or the Intel C/C++ compiler documentation.
Many intrinsic functions names are prefixed with an indicator of the vector length and suffixed by an indicator of
the vector element data type, although some functions do not follow the rules below. The prefixes are:
•
•
•
_mm_ indicates that the function operates on 128-bit (or sometimes 64-bit) vectors.
_mm256_ indicates the function operates on 256-bit vectors.
_mm512_ indicates that the function operates on 512-bit vectors.
The suffixes include:
•
_ps, which indicates a function that operates on packed single-precision floating-point data. Packed singleprecision floating-point data corresponds to arrays of the C/C++ type float with either 4, 8 or 16 elements.
Values of this type can be loaded from an array using the _mm_loadu_ps, _mm256_loadu_ps, or
_mm512_loadu_ps functions, or created from individual values using _mm_set_ps, _mm256_set_ps, or
_mm512_set_ps functions, and they can be stored in an array using _mm_storeu_ps, _mm256_storeu_ps, or
_mm512_storeu_ps.
•
_ss, which indicates a function that operates on scalar single-precision floating-point data. Single-precision
floating-point data corresponds to the C/C++ type float, and values of type float can be converted to type
__m128 for use with these functions using the _mm_set_ss function, and converted back using the
_mm_cvtss_f32 function. When used with functions that operate on packed single-precision floating-point data
the scalar element corresponds with the first packed value.
•
_pd, which indicates a function that operates on packed double-precision floating-point data. Packed doubleprecision floating-point data corresponds to arrays of the C/C++ type double with either 2, 4, or 8 elements.
Values of this type can be loaded from an array using the _mm_loadu_pd, _mm256_loadu_pd, or
_mm512_loadu_pd functions, or created from individual values using _mm_set_pd, _mm2566_set_pd, or
_mm512_set_pd functions, and they can be stored in an array using _mm_storeu_pd, _mm256_storeu_pd, or
_mm512_storeu_pd.
•
_sd, which indicates a function that operates on scalar double-precision floating-point data. Double-precision
floating-point data corresponds to the C/C++ type double, and values of type double can be converted to type
__m128d for use with these functions using the _mm_set_sd function, and converted back using the
_mm_cvtsd_f64 function. When used with functions that operate on packed double-precision floating-point
data the scalar element corresponds with the first packed value.
•
_epi8, which indicates a function that operates on packed 8-bit signed integer values. Packed 8-bit signed
integers correspond to an array of signed char with 16, 32 or 64 elements. Values of this type can be created
from individual elements using _mm_set_epi8, _mm256_set_epi8, or _mm512_set_epi8 functions.
•
_epi16, which indicates a function that operates on packed 16-bit signed integer values. Packed 16-bit signed
integers correspond to an array of short with 8, 16 or 32 elements. Values of this type can be created from
individual elements using _mm_set_epi16, _mm256_set_epi16, or _mm512_set_epi16 functions.
•
_epi32, which indicates a function that operates on packed 32-bit signed integer values. Packed 32-bit signed
integers correspond to an array of int with 4, 8 or 16 elements. Values of this type can be created from
individual elements using _mm_set_epi32, _mm256_set_epi32, or _mm512_set_epi32 functions.
•
_epi64, which indicates a function that operates on packed 64-bit signed integer values. Packed 64-bit signed
integers correspond to an array of long long (or long if it is a 64-bit data type) with 2, 4 or 8 elements. Values
of this type can be created from individual elements using _mm_set_epi32, _mm256_set_epi32, or
_mm512_set_epi32 functions.
•
_epu8, which indicates a function that operates on packed 8-bit unsigned integer values. Packed 8-bit unsigned
integers correspond to an array of unsigned char with 16, 32 or 64 elements.
Vol. 2A 3-13
INSTRUCTION SET REFERENCE, A-L
•
_epu16, which indicates a function that operates on packed 16-bit unsigned integer values. Packed 16-bit
unsigned integers correspond to an array of unsigned short with 8, 16 or 32 elements.
•
_epu32, which indicates a function that operates on packed 32-bit unsigned integer values. Packed 32-bit
unsigned integers correspond to an array of unsigned with 4, 8 or 16 elements.
•
_epu64, which indicates a function that operates on packed 64-bit unsigned integer values. Packed 64-bit
unsigned integers correspond to an array of unsigned long long (or unsigned long if it is a 64-bit data type) with
2, 4 or 8 elements.
•
•
•
_si128, which indicates a function that operates on a single 128-bit value of type __m128i.
_si256, which indicates a function that operates on a single a 256-bit value of type __m256i.
_si512, which indicates a function that operates on a single a 512-bit value of type __m512i.
Values of any packed integer type can be loaded from an array using the _mm_loadu_si128,
_mm256_loadu_si256, or _mm512_loadu_si512 functions, and they can be stored in an array using
_mm_storeu_si128, _mm256_storeu_si256, or _mm512_storeu_si512.
These functions and data types are used with the SSE, AVX, and AVX-512 instruction set extension families. In
addition there are similar functions that correspond to MMX instructions. These are less frequently used because
they require additional state management, and only operate on 64-bit packed integer values.
The declarations of Intel C/C++ compiler intrinsic functions may reference some non-standard data types, such as
__int64. The C Standard header stdint.h defines similar platform-independent types, and the documentation for
that header gives characteristics that apply to corresponding non-standard types according to the following table.
Table 3-3. Standard and Non-standard Data Types
Non-standard Type
Standard Type (from stdint.h)
__int64
int64_t
unsigned __int64
uint64_t
__int32
int32_t
unsigned __int32
uint32_t
__int16
int16_t
unsigned __int16
uint16_t
For a more detailed description of each intrinsic function and additional information related to its usage, refer to the
online Intel Intrinsics Guide, https://software.intel.com/sites/landingpage/IntrinsicsGuide.
3.1.1.11
Flags Affected Section
The “Flags Affected” section lists the flags in the EFLAGS register that are affected by the instruction. When a flag
is cleared, it is equal to 0; when it is set, it is equal to 1. The arithmetic and logical instructions usually assign
values to the status flags in a uniform manner (see Appendix A, “EFLAGS Cross-Reference,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 1). Non-conventional assignments are described in the
“Operation” section. The values of flags listed as undefined may be changed by the instruction in an indeterminate
manner. Flags that are not listed are unchanged by the instruction.
3.1.1.12
FPU Flags Affected Section
The floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affect
the four condition code flags of the FPU status word.
3.1.1.13
Protected Mode Exceptions Section
The “Protected Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
protected mode and the reasons for the exceptions. Each exception is given a mnemonic that consists of a pound
3-14 Vol. 2A
INSTRUCTION SET REFERENCE, A-L
sign (#) followed by two letters and an optional error code in parentheses. For example, #GP(0) denotes a general
protection exception with an error code of 0. Table 3-4 associates each two-letter mnemonic with the corresponding exception vector and name. See Chapter 6, “Procedure Calls, Interrupts, and Exceptions,” in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed description of the exceptions.
Application programmers should consult the documentation provided with their operating systems to determine
the actions taken when exceptions occur.
Table 3-4. Intel 64 and IA-32 General Exceptions
Vector
Name
Source
Protected
Mode1
Real
Address
Mode
Virtual
8086
Mode
0
#DE—Divide Error
DIV and IDIV instructions.
Yes
Yes
Yes
1
#DB—Debug
Any code or data reference.
Yes
Yes
Yes
3
#BP—Breakpoint
INT 3 instruction.
Yes
Yes
Yes
4
#OF—Overflow
INTO instruction.
Yes
Yes
Yes
5
#BR—BOUND Range Exceeded
BOUND instruction.
Yes
Yes
Yes
6
#UD—Invalid Opcode (Undefined
Opcode)
UD2 instruction or reserved opcode.
Yes
Yes
Yes
7
#NM—Device Not Available (No
Math Coprocessor)
Floating-point or WAIT/FWAIT instruction.
Yes
Yes
Yes
8
#DF—Double Fault
Any instruction that can generate an
exception, an NMI, or an INTR.
Yes
Yes
Yes
10
#TS—Invalid TSS
Task switch or TSS access.
Yes
Reserved
Yes
11
#NP—Segment Not Present
Loading segment registers or accessing system
segments.
Yes
Reserved
Yes
12
#SS—Stack Segment Fault
Stack operations and SS register loads.
Yes
Yes
Yes
13
#GP—General Protection2
Any memory reference and other protection
checks.
Yes
Yes
Yes
14
#PF—Page Fault
Any memory reference.
Yes
Reserved
Yes
16
#MF—Floating-Point Error (Math
Fault)
Floating-point or WAIT/FWAIT instruction.
Yes
Yes
Yes
17
#AC—Alignment Check
Any data reference in memory.
Yes
Reserved
Yes
18
#MC—Machine Check
Model dependent machine check errors.
Yes
Yes
Yes
19
#XM—SIMD Floating-Point
Numeric Error
SSE/SSE2/SSE3 floating-point instructions.
Yes
Yes
Yes
NOTES:
1. Apply to protected mode, compatibility mode, and 64-bit mode.
2. In the real-address mode, vector 13 is the segment overrun exception.
3.1.1.14
Real-Address Mode Exceptions Section
The “Real-Address Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
real-address mode (see Table 3-4).
3.1.1.15
Virtual-8086 Mode Exceptions Section
The “Virtual-8086 Mode Exceptions” section lists the exceptions that can occur when the instruction is executed in
virtual-8086 mode (see Table 3-4).
Vol. 2A 3-15
INSTRUCTION SET REFERENCE, A-L
3.1.1.16
Floating-Point Exceptions Section
The “Floating-Point Exceptions” section lists exceptions that can occur when an x87 FPU floating-point instruction
is executed. All of these exception conditions result in a floating-point error exception (#MF, exception 16) being
generated. Table 3-5 associates a one- or two-letter mnemonic with the corresponding exception name. See
“Floating-Point Exception Conditions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, for a detailed description of these exceptions.
Table 3-5. x87 FPU Floating-Point Exceptions
Mnemonic
Name
Source
Floating-point invalid operation:
#IS
#IA
- Stack overflow or underflow
- x87 FPU stack overflow or underflow
- Invalid arithmetic operation
- Invalid FPU arithmetic operation
#Z
Floating-point divide-by-zero
Divide-by-zero
#D
Floating-point denormal operand
Source operand that is a denormal number
#O
Floating-point numeric overflow
Overflow in result
#U
Floating-point numeric underflow
Underflow in result
#P
Floating-point inexact result (precision)
Inexact result (precision)
3.1.1.17
SIMD Floating-Point Exceptions Section
The “SIMD Floating-Point Exceptions” section lists exceptions that can occur when an SSE/SSE2/SSE3 floatingpoint instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XM,
exception 19) being generated. Table 3-6 associates a one-letter mnemonic with the corresponding exception
name. For a detailed description of these exceptions, refer to ”SSE and SSE2 Exceptions”, in Chapter 11 of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
Table 3-6. SIMD Floating-Point Exceptions
Mnemonic
Name
Source
#I
Floating-point invalid operation
Invalid arithmetic operation or source operand
#Z
Floating-point divide-by-zero
Divide-by-zero
#D
Floating-point denormal operand
Source operand that is a denormal number
#O
Floating-point numeric overflow
Overflow in result
#U
Floating-point numeric underflow
Underflow in result
#P
Floating-point inexact result
Inexact result (precision)
3.1.1.18
Compatibility Mode Exceptions Section
This section lists exceptions that occur within compatibility mode.
3.1.1.19
64-Bit Mode Exceptions Section
This section lists exceptions that occur within 64-bit mode.
3-16 Vol. 2A
INSTRUCTION SET REFERENCE, A-L
3.2
INSTRUCTIONS (A-L)
The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-L). See also: Chapter 4,
“Instruction Set Reference, M-U,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B, and Chapter 5, “Instruction Set Reference, V-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2C.
Vol. 2A 3-17
INSTRUCTION SET REFERENCE, A-L
AAA—ASCII Adjust After Addition
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
37
AAA
NP
Invalid
Valid
ASCII adjust AL after addition.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied
source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD
instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The
AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.
If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there
was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4
through 7 of the AL register are set to 0.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
IF ((AL AND 0FH) > 9) or (AF = 1)
THEN
AX ← AX + 106H;
AF ← 1;
CF ← 1;
ELSE
AF ← 0;
CF ← 0;
FI;
AL ← AL AND 0FH;
FI;
Flags Affected
The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF,
SF, ZF, and PF flags are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
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AAA—ASCII Adjust After Addition
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAA—ASCII Adjust After Addition
Vol. 2A 3-19
INSTRUCTION SET REFERENCE, A-L
AAD—ASCII Adjust AX Before Division
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
D5 0A
AAD
NP
Invalid
Valid
ASCII adjust AX before division.
D5 ib
AAD imm8
NP
Invalid
Valid
Adjust AX before division to number base
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the
AH register) so that a division operation performed on the result will yield a correct unpacked BCD value. The AAD
instruction is only useful when it precedes a DIV instruction that divides (binary division) the adjusted value in the
AX register by an unpacked BCD value.
The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and then clears the AH register to 00H.
The value in the AX register is then equal to the binary equivalent of the original unpacked two-digit (base 10)
number in registers AH and AL.
The generalized version of this instruction allows adjustment of two unpacked digits of any number base (see the
“Operation” section below), by setting the imm8 byte to the selected number base (for example, 08H for octal, 0AH
for decimal, or 0CH for base 12 numbers). The AAD mnemonic is interpreted by all assemblers to mean adjust
ASCII (base 10) values. To adjust values in another number base, the instruction must be hand coded in machine
code (D5 imm8).
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
tempAL ← AL;
tempAH ← AH;
AL ← (tempAL + (tempAH ∗ imm8)) AND FFH;
(* imm8 is set to 0AH for the AAD mnemonic.*)
AH ← 0;
FI;
The immediate value (imm8) is taken from the second byte of the instruction.
Flags Affected
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags
are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
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AAD—ASCII Adjust AX Before Division
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAD—ASCII Adjust AX Before Division
Vol. 2A 3-21
INSTRUCTION SET REFERENCE, A-L
AAM—ASCII Adjust AX After Multiply
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
D4 0A
AAM
NP
Invalid
Valid
ASCII adjust AX after multiply.
D4 ib
AAM imm8
NP
Invalid
Valid
Adjust AX after multiply to number base
imm8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD
values. The AX register is the implied source and destination operand for this instruction. The AAM instruction is
only useful when it follows an MUL instruction that multiplies (binary multiplication) two unpacked BCD values and
stores a word result in the AX register. The AAM instruction then adjusts the contents of the AX register to contain
the correct 2-digit unpacked (base 10) BCD result.
The generalized version of this instruction allows adjustment of the contents of the AX to create two unpacked
digits of any number base (see the “Operation” section below). Here, the imm8 byte is set to the selected number
base (for example, 08H for octal, 0AH for decimal, or 0CH for base 12 numbers). The AAM mnemonic is interpreted
by all assemblers to mean adjust to ASCII (base 10) values. To adjust to values in another number base, the
instruction must be hand coded in machine code (D4 imm8).
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
tempAL ← AL;
AH ← tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)
AL ← tempAL MOD imm8;
FI;
The immediate value (imm8) is taken from the second byte of the instruction.
Flags Affected
The SF, ZF, and PF flags are set according to the resulting binary value in the AL register. The OF, AF, and CF flags
are undefined.
Protected Mode Exceptions
#DE
If an immediate value of 0 is used.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
3-22 Vol. 2A
AAM—ASCII Adjust AX After Multiply
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAM—ASCII Adjust AX After Multiply
Vol. 2A 3-23
INSTRUCTION SET REFERENCE, A-L
AAS—ASCII Adjust AL After Subtraction
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
3F
AAS
NP
Invalid
Valid
ASCII adjust AL after subtraction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register
is the implied source and destination operand for this instruction. The AAS instruction is only useful when it follows
a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another and stores a byte
result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1digit unpacked BCD result.
If the subtraction produced a decimal carry, the AH register decrements by 1, and the CF and AF flags are set. If no
decimal carry occurred, the CF and AF flags are cleared, and the AH register is unchanged. In either case, the AL
register is left with its top four bits set to 0.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-bit mode
THEN
#UD;
ELSE
IF ((AL AND 0FH) > 9) or (AF = 1)
THEN
AX ← AX – 6;
AH ← AH – 1;
AF ← 1;
CF ← 1;
AL ← AL AND 0FH;
ELSE
CF ← 0;
AF ← 0;
AL ← AL AND 0FH;
FI;
FI;
Flags Affected
The AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and
PF flags are undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
Same exceptions as protected mode.
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AAS—ASCII Adjust AL After Subtraction
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
Same exceptions as protected mode.
Compatibility Mode Exceptions
Same exceptions as protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
AAS—ASCII Adjust AL After Subtraction
Vol. 2A 3-25
INSTRUCTION SET REFERENCE, A-L
ADC—Add with Carry
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
14 ib
ADC AL, imm8
I
Valid
Valid
Add with carry imm8 to AL.
15 iw
ADC AX, imm16
I
Valid
Valid
Add with carry imm16 to AX.
15 id
ADC EAX, imm32
I
Valid
Valid
Add with carry imm32 to EAX.
REX.W + 15 id
ADC RAX, imm32
I
Valid
N.E.
Add with carry imm32 sign extended to 64bits to RAX.
80 /2 ib
ADC r/m8, imm8
MI
Valid
Valid
Add with carry imm8 to r/m8.
REX + 80 /2 ib
*
ADC r/m8 , imm8
MI
Valid
N.E.
Add with carry imm8 to r/m8.
81 /2 iw
ADC r/m16, imm16
MI
Valid
Valid
Add with carry imm16 to r/m16.
81 /2 id
ADC r/m32, imm32
MI
Valid
Valid
Add with CF imm32 to r/m32.
REX.W + 81 /2 id
ADC r/m64, imm32
MI
Valid
N.E.
Add with CF imm32 sign extended to 64-bits
to r/m64.
83 /2 ib
ADC r/m16, imm8
MI
Valid
Valid
Add with CF sign-extended imm8 to r/m16.
83 /2 ib
ADC r/m32, imm8
MI
Valid
Valid
Add with CF sign-extended imm8 into r/m32.
REX.W + 83 /2 ib
ADC r/m64, imm8
MI
Valid
N.E.
Add with CF sign-extended imm8 into r/m64.
10 /r
ADC r/m8, r8
MR
Valid
Valid
Add with carry byte register to r/m8.
REX + 10 /r
ADC r/m8*, r8*
MR
Valid
N.E.
Add with carry byte register to r/m64.
11 /r
ADC r/m16, r16
MR
Valid
Valid
Add with carry r16 to r/m16.
11 /r
ADC r/m32, r32
MR
Valid
Valid
Add with CF r32 to r/m32.
REX.W + 11 /r
ADC r/m64, r64
MR
Valid
N.E.
Add with CF r64 to r/m64.
12 /r
ADC r8, r/m8
RM
Valid
Valid
Add with carry r/m8 to byte register.
REX + 12 /r
ADC r8*, r/m8*
RM
Valid
N.E.
Add with carry r/m64 to byte register.
13 /r
ADC r16, r/m16
RM
Valid
Valid
Add with carry r/m16 to r16.
13 /r
ADC r32, r/m32
RM
Valid
Valid
Add with CF r/m32 to r32.
REX.W + 13 /r
ADC r64, r/m64
RM
Valid
N.E.
Add with CF r/m64 to r64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and
stores the result in the destination operand. The destination operand can be a register or a memory location; the
source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be
used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate
value is used as an operand, it is sign-extended to the length of the destination operand format.
3-26 Vol. 2A
ADC—Add with Carry
INSTRUCTION SET REFERENCE, A-L
The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates
the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result,
respectively. The SF flag indicates the sign of the signed result.
The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is
followed by an ADC instruction.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST + SRC + CF;
Intel C/C++ Compiler Intrinsic Equivalent
ADC:
extern unsigned char _addcarry_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *sum_out);
ADC:
extern unsigned char _addcarry_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short
*sum_out);
ADC:
extern unsigned char _addcarry_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *sum_out);
ADC:
extern unsigned char _addcarry_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64
*sum_out);
Flags Affected
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
ADC—Add with Carry
Vol. 2A 3-27
INSTRUCTION SET REFERENCE, A-L
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-28 Vol. 2A
ADC—Add with Carry
INSTRUCTION SET REFERENCE, A-L
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
ADX
Description
RM
64/32bit
Mode
Support
V/V
66 0F 38 F6 /r
ADCX r32, r/m32
66 REX.w 0F 38 F6 /r
ADCX r64, r/m64
RM
V/NE
ADX
Unsigned addition of r64 with CF, r/m64 to r64, writes CF.
Unsigned addition of r32 with CF, r/m32 to r32, writes CF.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand)
and the carry-flag (CF) and stores the result in the destination operand. The destination operand is a generalpurpose register, whereas the source operand can be a general-purpose register or memory location. The state of
CF can represent a carry from a previous addition. The instruction sets the CF flag with the carry generated by the
unsigned addition of the operands.
The ADCX instruction is executed in the context of multi-precision addition, where we add a series of operands with
a carry-chain. At the beginning of a chain of additions, we need to make sure the CF is in a desired initial state.
Often, this initial state needs to be 0, which can be achieved with an instruction to zero the CF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64bit mode.
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64 bits.
ADCX executes normally either inside or outside a transaction region.
Note: ADCX defines the OF flag differently than the ADD/ADC instructions as defined in Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN CF:DEST[63:0] ← DEST[63:0] + SRC[63:0] + CF;
ELSE CF:DEST[31:0] ← DEST[31:0] + SRC[31:0] + CF;
FI;
Flags Affected
CF is updated based on result. OF, SF, ZF, AF and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
Vol. 2A 3-29
INSTRUCTION SET REFERENCE, A-L
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-30 Vol. 2A
ADCX — Unsigned Integer Addition of Two Operands with Carry Flag
INSTRUCTION SET REFERENCE, A-L
ADD—Add
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
04 ib
ADD AL, imm8
I
Valid
Valid
Add imm8 to AL.
05 iw
ADD AX, imm16
I
Valid
Valid
Add imm16 to AX.
05 id
ADD EAX, imm32
I
Valid
Valid
Add imm32 to EAX.
REX.W + 05 id
ADD RAX, imm32
I
Valid
N.E.
Add imm32 sign-extended to 64-bits to RAX.
80 /0 ib
ADD r/m8, imm8
MI
Valid
Valid
Add imm8 to r/m8.
REX + 80 /0 ib
ADD r/m8*, imm8
MI
Valid
N.E.
Add sign-extended imm8 to r/m64.
81 /0 iw
ADD r/m16, imm16
MI
Valid
Valid
Add imm16 to r/m16.
81 /0 id
ADD r/m32, imm32
MI
Valid
Valid
Add imm32 to r/m32.
REX.W + 81 /0 id
ADD r/m64, imm32
MI
Valid
N.E.
Add imm32 sign-extended to 64-bits to
r/m64.
83 /0 ib
ADD r/m16, imm8
MI
Valid
Valid
Add sign-extended imm8 to r/m16.
83 /0 ib
ADD r/m32, imm8
MI
Valid
Valid
Add sign-extended imm8 to r/m32.
REX.W + 83 /0 ib
ADD r/m64, imm8
MI
Valid
N.E.
Add sign-extended imm8 to r/m64.
00 /r
ADD r/m8, r8
MR
Valid
Valid
Add r8 to r/m8.
MR
Valid
N.E.
Add r8 to r/m8.
MR
Valid
Valid
Add r16 to r/m16.
*
*
REX + 00 /r
ADD r/m8 , r8
01 /r
ADD r/m16, r16
01 /r
ADD r/m32, r32
MR
Valid
Valid
Add r32 to r/m32.
REX.W + 01 /r
ADD r/m64, r64
MR
Valid
N.E.
Add r64 to r/m64.
02 /r
ADD r8, r/m8
RM
Valid
Valid
Add r/m8 to r8.
RM
Valid
N.E.
Add r/m8 to r8.
REX + 02 /r
*
ADD r8 , r/m8
*
03 /r
ADD r16, r/m16
RM
Valid
Valid
Add r/m16 to r16.
03 /r
ADD r32, r/m32
RM
Valid
Valid
Add r/m32 to r32.
REX.W + 03 /r
ADD r64, r/m64
RM
Valid
N.E.
Add r/m64 to r64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Adds the destination operand (first operand) and the source operand (second operand) and then stores the result
in the destination operand. The destination operand can be a register or a memory location; the source operand
can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one
instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination
operand format.
The ADD instruction performs integer addition. It evaluates the result for both signed and unsigned integer operands and sets the CF and OF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The
SF flag indicates the sign of the signed result.
ADD—Add
Vol. 2A 3-31
INSTRUCTION SET REFERENCE, A-L
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST + SRC;
Flags Affected
The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-32 Vol. 2A
ADD—Add
INSTRUCTION SET REFERENCE, A-L
ADDPD—Add Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 58 /r
ADDPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 58 /r
VADDPD xmm1,xmm2,
xmm3/m128
VEX.NDS.256.66.0F.WIG 58 /r
VADDPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 58 /r
VADDPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 58 /r
VADDPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 58 /r
VADDPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
RVM
V/V
AVX
RVM
V/V
AVX
Add packed double-precision floating-point values from
ymm3/mem to ymm2 and store result in ymm1.
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Add packed double-precision floating-point values from
xmm3/m128/m64bcst to xmm2 and store result in xmm1
with writemask k1.
Add packed double-precision floating-point values from
ymm3/m256/m64bcst to ymm2 and store result in ymm1
with writemask k1.
Add packed double-precision floating-point values from
zmm3/m512/m64bcst to zmm2 and store result in zmm1
with writemask k1.
Description
Add packed double-precision floating-point values from
xmm2/mem to xmm1 and store result in xmm1.
Add packed double-precision floating-point values from
xmm3/mem to xmm2 and store result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Add two, four or eight packed double-precision floating-point values from the first source operand to the second
source operand, and stores the packed double-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
Operation
VADDPD (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
ADDPD—Add Packed Double-Precision Floating-Point Values
Vol. 2A 3-33
INSTRUCTION SET REFERENCE, A-L
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+63:i]  SRC1[i+63:i] + SRC2[i+63:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VADDPD (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i]  SRC1[i+63:i] + SRC2[63:0]
ELSE
DEST[i+63:i]  SRC1[i+63:i] + SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VADDPD (VEX.256 encoded version)
DEST[63:0]  SRC1[63:0] + SRC2[63:0]
DEST[127:64]  SRC1[127:64] + SRC2[127:64]
DEST[191:128]  SRC1[191:128] + SRC2[191:128]
DEST[255:192]  SRC1[255:192] + SRC2[255:192]
DEST[MAX_VL-1:256]  0
.
3-34 Vol. 2A
ADDPD—Add Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VADDPD (VEX.128 encoded version)
DEST[63:0]  SRC1[63:0] + SRC2[63:0]
DEST[127:64]  SRC1[127:64] + SRC2[127:64]
DEST[MAX_VL-1:128]  0
ADDPD (128-bit Legacy SSE version)
DEST[63:0]  DEST[63:0] + SRC[63:0]
DEST[127:64]  DEST[127:64] + SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDPD __m512d _mm512_add_pd (__m512d a, __m512d b);
VADDPD __m512d _mm512_mask_add_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VADDPD __m512d _mm512_maskz_add_pd (__mmask8 k, __m512d a, __m512d b);
VADDPD __m256d _mm256_mask_add_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VADDPD __m256d _mm256_maskz_add_pd (__mmask8 k, __m256d a, __m256d b);
VADDPD __m128d _mm_mask_add_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VADDPD __m128d _mm_maskz_add_pd (__mmask8 k, __m128d a, __m128d b);
VADDPD __m512d _mm512_add_round_pd (__m512d a, __m512d b, int);
VADDPD __m512d _mm512_mask_add_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VADDPD __m512d _mm512_maskz_add_round_pd (__mmask8 k, __m512d a, __m512d b, int);
ADDPD __m256d _mm256_add_pd (__m256d a, __m256d b);
ADDPD __m128d _mm_add_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
ADDPD—Add Packed Double-Precision Floating-Point Values
Vol. 2A 3-35
INSTRUCTION SET REFERENCE, A-L
ADDPS—Add Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 58 /r
ADDPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 58 /r
VADDPS xmm1,xmm2, xmm3/m128
VEX.NDS.256.0F.WIG 58 /r
VADDPS ymm1, ymm2, ymm3/m256
EVEX.NDS.128.0F.W0 58 /r
VADDPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 58 /r
VADDPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 58 /r
VADDPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst {er}
RVM
V/V
AVX
RVM
V/V
AVX
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Add packed single-precision floating-point values from
xmm2/m128 to xmm1 and store result in xmm1.
Add packed single-precision floating-point values from
xmm3/m128 to xmm2 and store result in xmm1.
Add packed single-precision floating-point values from
ymm3/m256 to ymm2 and store result in ymm1.
Add packed single-precision floating-point values from
xmm3/m128/m32bcst to xmm2 and store result in
xmm1 with writemask k1.
Add packed single-precision floating-point values from
ymm3/m256/m32bcst to ymm2 and store result in
ymm1 with writemask k1.
Add packed single-precision floating-point values from
zmm3/m512/m32bcst to zmm2 and store result in
zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Add four, eight or sixteen packed single-precision floating-point values from the first source operand with the
second source operand, and stores the packed single-precision floating-point results in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: the first source operand is a XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
Operation
VADDPS (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
3-36 Vol. 2A
ADDPS—Add Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
FI;
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i]  SRC1[i+31:i] + SRC2[i+31:i]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL]  0
VADDPS (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i]  SRC1[i+31:i] + SRC2[31:0]
ELSE
DEST[i+31:i]  SRC1[i+31:i] + SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR;
DEST[MAX_VL-1:VL]  0
ADDPS—Add Packed Single-Precision Floating-Point Values
Vol. 2A 3-37
INSTRUCTION SET REFERENCE, A-L
VADDPS (VEX.256 encoded version)
DEST[31:0]  SRC1[31:0] + SRC2[31:0]
DEST[63:32]  SRC1[63:32] + SRC2[63:32]
DEST[95:64]  SRC1[95:64] + SRC2[95:64]
DEST[127:96]  SRC1[127:96] + SRC2[127:96]
DEST[159:128]  SRC1[159:128] + SRC2[159:128]
DEST[191:160] SRC1[191:160] + SRC2[191:160]
DEST[223:192]  SRC1[223:192] + SRC2[223:192]
DEST[255:224]  SRC1[255:224] + SRC2[255:224].
DEST[MAX_VL-1:256]  0
VADDPS (VEX.128 encoded version)
DEST[31:0]  SRC1[31:0] + SRC2[31:0]
DEST[63:32]  SRC1[63:32] + SRC2[63:32]
DEST[95:64]  SRC1[95:64] + SRC2[95:64]
DEST[127:96]  SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128]  0
ADDPS (128-bit Legacy SSE version)
DEST[31:0]  SRC1[31:0] + SRC2[31:0]
DEST[63:32]  SRC1[63:32] + SRC2[63:32]
DEST[95:64]  SRC1[95:64] + SRC2[95:64]
DEST[127:96]  SRC1[127:96] + SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDPS __m512 _mm512_add_ps (__m512 a, __m512 b);
VADDPS __m512 _mm512_mask_add_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VADDPS __m512 _mm512_maskz_add_ps (__mmask16 k, __m512 a, __m512 b);
VADDPS __m256 _mm256_mask_add_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VADDPS __m256 _mm256_maskz_add_ps (__mmask8 k, __m256 a, __m256 b);
VADDPS __m128 _mm_mask_add_ps (__m128d s, __mmask8 k, __m128 a, __m128 b);
VADDPS __m128 _mm_maskz_add_ps (__mmask8 k, __m128 a, __m128 b);
VADDPS __m512 _mm512_add_round_ps (__m512 a, __m512 b, int);
VADDPS __m512 _mm512_mask_add_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VADDPS __m512 _mm512_maskz_add_round_ps (__mmask16 k, __m512 a, __m512 b, int);
ADDPS __m256 _mm256_add_ps (__m256 a, __m256 b);
ADDPS __m128 _mm_add_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.
3-38 Vol. 2A
ADDPS—Add Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSD—Add Scalar Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 58 /r
ADDSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 58 /r
VADDSD xmm1, xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 58 /r
VADDSD xmm1 {k1}{z},
xmm2, xmm3/m64{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Add the low double-precision floating-point value from
xmm2/mem to xmm1 and store the result in xmm1.
Add the low double-precision floating-point value from
xmm3/mem to xmm2 and store the result in xmm1.
Add the low double-precision floating-point value from
xmm3/m64 to xmm2 and store the result in xmm1 with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S-RVM
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Adds the low double-precision floating-point values from the second source operand and the first source operand
and stores the double-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:64) of
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low quadword element of the destination is updated according to the writemask.
Software should ensure VADDSD is encoded with VEX.L=0. Encoding VADDSD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
VADDSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0]  SRC1[63:0] + SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0]  0
FI;
FI;
DEST[127:64]  SRC1[127:64]
ADDSD—Add Scalar Double-Precision Floating-Point Values
Vol. 2A 3-39
INSTRUCTION SET REFERENCE, A-L
DEST[MAX_VL-1:128]  0
VADDSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] + SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
ADDSD (128-bit Legacy SSE version)
DEST[63:0] DEST[63:0] + SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSD __m128d _mm_mask_add_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_maskz_add_sd (__mmask8 k, __m128d a, __m128d b);
VADDSD __m128d _mm_add_round_sd (__m128d a, __m128d b, int);
VADDSD __m128d _mm_mask_add_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VADDSD __m128d _mm_maskz_add_round_sd (__mmask8 k, __m128d a, __m128d b, int);
ADDSD __m128d _mm_add_sd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
3-40 Vol. 2A
ADDSD—Add Scalar Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSS—Add Scalar Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 58 /r
ADDSS xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 58 /r
VADDSS xmm1,xmm2,
xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 58 /r
VADDSS xmm1{k1}{z}, xmm2,
xmm3/m32{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Add the low single-precision floating-point value from
xmm2/mem to xmm1 and store the result in xmm1.
Add the low single-precision floating-point value from
xmm3/mem to xmm2 and store the result in xmm1.
Add the low single-precision floating-point value from
xmm3/m32 to xmm2 and store the result in xmm1with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Adds the low single-precision floating-point values from the second source operand and the first source operand,
and stores the double-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The first source and destination operands are the same. Bits (MAX_VL-1:32) of the
corresponding the destination register remain unchanged.
EVEX and VEX.128 encoded version: The first source operand is encoded by EVEX.vvvv/VEX.vvvv. Bits (127:32) of
the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VADDSS is encoded with VEX.L=0. Encoding VADDSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
Operation
VADDSS (EVEX encoded versions)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0]  SRC1[31:0] + SRC2[31:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0]  0
FI;
FI;
DEST[127:32]  SRC1[127:32]
ADDSS—Add Scalar Single-Precision Floating-Point Values
Vol. 2A 3-41
INSTRUCTION SET REFERENCE, A-L
DEST[MAX_VL-1:128]  0
VADDSS DEST, SRC1, SRC2 (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] + SRC2[31:0]
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
ADDSS DEST, SRC (128-bit Legacy SSE version)
DEST[31:0] DEST[31:0] + SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VADDSS __m128 _mm_mask_add_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_maskz_add_ss (__mmask8 k, __m128 a, __m128 b);
VADDSS __m128 _mm_add_round_ss (__m128 a, __m128 b, int);
VADDSS __m128 _mm_mask_add_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VADDSS __m128 _mm_maskz_add_round_ss (__mmask8 k, __m128 a, __m128 b, int);
ADDSS __m128 _mm_add_ss (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.
3-42 Vol. 2A
ADDSS—Add Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD—Packed Double-FP Add/Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F D0 /r
RM
V/V
SSE3
Add/subtract double-precision floating-point
values from xmm2/m128 to xmm1.
RVM V/V
AVX
Add/subtract packed double-precision
floating-point values from xmm3/mem to
xmm2 and stores result in xmm1.
RVM V/V
AVX
Add / subtract packed double-precision
floating-point values from ymm3/mem to
ymm2 and stores result in ymm1.
ADDSUBPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG D0 /r
VADDSUBPD xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG D0 /r
VADDSUBPD ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds odd-numbered double-precision floating-point values of the first source operand (second operand) with the
corresponding double-precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered
double-precision floating-point values from the second source operand from the corresponding double-precision
floating values in the first source operand; stores the result into the even-numbered values of the destination
operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-3.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
ADDSUBPD—Packed Double-FP Add/Subtract
Vol. 2A 3-43
INSTRUCTION SET REFERENCE, A-L
ADDSUBPD xmm1, xmm2/m128
xmm2/m128
[127:64]
[63:0]
xmm1[127:64] + xmm2/m128[127:64]
xmm1[63:0] - xmm2/m128[63:0]
[127:64]
[63:0]
RESULT:
xmm1
Figure 3-3. ADDSUBPD—Packed Double-FP Add/Subtract
Operation
ADDSUBPD (128-bit Legacy SSE version)
DEST[63:0]  DEST[63:0] - SRC[63:0]
DEST[127:64]  DEST[127:64] + SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VADDSUBPD (VEX.128 encoded version)
DEST[63:0]  SRC1[63:0] - SRC2[63:0]
DEST[127:64]  SRC1[127:64] + SRC2[127:64]
DEST[VLMAX-1:128]  0
VADDSUBPD (VEX.256 encoded version)
DEST[63:0]  SRC1[63:0] - SRC2[63:0]
DEST[127:64]  SRC1[127:64] + SRC2[127:64]
DEST[191:128]  SRC1[191:128] - SRC2[191:128]
DEST[255:192]  SRC1[255:192] + SRC2[255:192]
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPD:
__m128d _mm_addsub_pd(__m128d a, __m128d b)
VADDSUBPD:
__m256d _mm256_addsub_pd (__m256d a, __m256d b)
Exceptions
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Exceptions Type 2.
3-44 Vol. 2A
ADDSUBPD—Packed Double-FP Add/Subtract
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS—Packed Single-FP Add/Subtract
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
F2 0F D0 /r
RM
V/V
SSE3
Add/subtract single-precision floating-point
values from xmm2/m128 to xmm1.
RVM V/V
AVX
Add/subtract single-precision floating-point
values from xmm3/mem to xmm2 and stores
result in xmm1.
RVM V/V
AVX
Add / subtract single-precision floating-point
values from ymm3/mem to ymm2 and stores
result in ymm1.
ADDSUBPS xmm1, xmm2/m128
VEX.NDS.128.F2.0F.WIG D0 /r
VADDSUBPS xmm1, xmm2, xmm3/m128
VEX.NDS.256.F2.0F.WIG D0 /r
VADDSUBPS ymm1, ymm2, ymm3/m256
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Adds odd-numbered single-precision floating-point values of the first source operand (second operand) with the
corresponding single-precision floating-point values from the second source operand (third operand); stores the
result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered
single-precision floating-point values from the second source operand from the corresponding single-precision
floating values in the first source operand; stores the result into the even-numbered values of the destination
operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. See Figure 3-4.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
ADDSUBPS—Packed Single-FP Add/Subtract
Vol. 2A 3-45
INSTRUCTION SET REFERENCE, A-L
ADDSUBPS xmm1, xmm2/m128
xmm2/
m128
[127:96]
[95:64]
[63:32]
[31:0]
xmm1[127:96] +
xmm2/m128[127:96]
xmm1[95:64] - xmm2/
m128[95:64]
xmm1[63:32] +
xmm2/m128[63:32]
xmm1[31:0] xmm2/m128[31:0]
[127:96]
[95:64]
[63:32]
[31:0]
RESULT:
xmm1
OM15992
Figure 3-4. ADDSUBPS—Packed Single-FP Add/Subtract
Operation
ADDSUBPS (128-bit Legacy SSE version)
DEST[31:0]  DEST[31:0] - SRC[31:0]
DEST[63:32]  DEST[63:32] + SRC[63:32]
DEST[95:64]  DEST[95:64] - SRC[95:64]
DEST[127:96]  DEST[127:96] + SRC[127:96]
DEST[VLMAX-1:128] (Unmodified)
VADDSUBPS (VEX.128 encoded version)
DEST[31:0]  SRC1[31:0] - SRC2[31:0]
DEST[63:32]  SRC1[63:32] + SRC2[63:32]
DEST[95:64]  SRC1[95:64] - SRC2[95:64]
DEST[127:96]  SRC1[127:96] + SRC2[127:96]
DEST[VLMAX-1:128]  0
VADDSUBPS (VEX.256 encoded version)
DEST[31:0]  SRC1[31:0] - SRC2[31:0]
DEST[63:32]  SRC1[63:32] + SRC2[63:32]
DEST[95:64]  SRC1[95:64] - SRC2[95:64]
DEST[127:96]  SRC1[127:96] + SRC2[127:96]
DEST[159:128]  SRC1[159:128] - SRC2[159:128]
DEST[191:160] SRC1[191:160] + SRC2[191:160]
DEST[223:192]  SRC1[223:192] - SRC2[223:192]
DEST[255:224]  SRC1[255:224] + SRC2[255:224].
Intel C/C++ Compiler Intrinsic Equivalent
ADDSUBPS:
__m128 _mm_addsub_ps(__m128 a, __m128 b)
VADDSUBPS:
__m256 _mm256_addsub_ps (__m256 a, __m256 b)
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a generalprotection exception (#GP) will be generated.
3-46 Vol. 2A
ADDSUBPS—Packed Single-FP Add/Subtract
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Other Exceptions
See Exceptions Type 2.
ADDSUBPS—Packed Single-FP Add/Subtract
Vol. 2A 3-47
INSTRUCTION SET REFERENCE, A-L
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
Opcode/
Instruction
Op/
En
CPUID
Feature
Flag
ADX
Description
RM
64/32bit
Mode
Support
V/V
F3 0F 38 F6 /r
ADOX r32, r/m32
F3 REX.w 0F 38 F6 /r
ADOX r64, r/m64
RM
V/NE
ADX
Unsigned addition of r64 with OF, r/m64 to r64, writes OF.
Unsigned addition of r32 with OF, r/m32 to r32, writes OF.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Performs an unsigned addition of the destination operand (first operand), the source operand (second operand)
and the overflow-flag (OF) and stores the result in the destination operand. The destination operand is a generalpurpose register, whereas the source operand can be a general-purpose register or memory location. The state of
OF represents a carry from a previous addition. The instruction sets the OF flag with the carry generated by the
unsigned addition of the operands.
The ADOX instruction is executed in the context of multi-precision addition, where we add a series of operands with
a carry-chain. At the beginning of a chain of additions, we execute an instruction to zero the OF (e.g. XOR).
This instruction is supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in 64-bit
mode.
In 64-bit mode, the default operation size is 32 bits. Using a REX Prefix in the form of REX.R permits access to additional registers (R8-15). Using REX Prefix in the form of REX.W promotes operation to 64-bits.
ADOX executes normally either inside or outside a transaction region.
Note: ADOX defines the CF and OF flags differently than the ADD/ADC instructions as defined in Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A.
Operation
IF OperandSize is 64-bit
THEN OF:DEST[63:0] ← DEST[63:0] + SRC[63:0] + OF;
ELSE OF:DEST[31:0] ← DEST[31:0] + SRC[31:0] + OF;
FI;
Flags Affected
OF is updated based on result. CF, SF, ZF, AF and PF flags are unmodified.
Intel C/C++ Compiler Intrinsic Equivalent
unsigned char _addcarryx_u32 (unsigned char c_in, unsigned int src1, unsigned int src2, unsigned int *sum_out);
unsigned char _addcarryx_u64 (unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned __int64 *sum_out);
SIMD Floating-Point Exceptions
None
3-48 Vol. 2A
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
#GP(0)
For an illegal address in the SS segment.
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
selector.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
For an illegal address in the SS segment.
#GP(0)
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
ADOX — Unsigned Integer Addition of Two Operands with Overflow Flag
Vol. 2A 3-49
INSTRUCTION SET REFERENCE, A-L
AESDEC—Perform One Round of an AES Decryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DE /r
AESDEC xmm1, xmm2/m128
RM
V/V
AES
Perform one round of an AES decryption flow,
using the Equivalent Inverse Cipher, operating
on a 128-bit data (state) from xmm1 with a
128-bit round key from xmm2/m128.
VEX.NDS.128.66.0F38.WIG DE /r
VAESDEC xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform one round of an AES decryption flow,
using the Equivalent Inverse Cipher, operating
on a 128-bit data (state) from xmm2 with a
128-bit round key from xmm3/m128; store
the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the
round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and
store the result in the destination operand.
Use the AESDEC instruction for all but the last decryption round. For the last decryption round, use the AESDECLAST instruction.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESDEC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
STATE ← InvMixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESDEC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
STATE ← InvMixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] ← 0
3-50 Vol. 2A
AESDEC—Perform One Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDEC:
__m128i _mm_aesdec (__m128i, __m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESDEC—Perform One Round of an AES Decryption Flow
Vol. 2A 3-51
INSTRUCTION SET REFERENCE, A-L
AESDECLAST—Perform Last Round of an AES Decryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DF /r
AESDECLAST xmm1, xmm2/m128
RM
V/V
AES
Perform the last round of an AES decryption
flow, using the Equivalent Inverse Cipher,
operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DF /r
VAESDECLAST xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform the last round of an AES decryption
flow, using the Equivalent Inverse Cipher,
operating on a 128-bit data (state) from
xmm2 with a 128-bit round key from
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the
round key from the second source operand, operating on a 128-bit data (state) from the first source operand, and
store the result in the destination operand.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESDECLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESDECLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← InvShiftRows( STATE );
STATE ← InvSubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] ← 0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESDECLAST:
3-52 Vol. 2A
__m128i _mm_aesdeclast (__m128i, __m128i)
AESDECLAST—Perform Last Round of an AES Decryption Flow
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESDECLAST—Perform Last Round of an AES Decryption Flow
Vol. 2A 3-53
INSTRUCTION SET REFERENCE, A-L
AESENC—Perform One Round of an AES Encryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DC /r
AESENC xmm1, xmm2/m128
RM
V/V
AES
Perform one round of an AES encryption flow,
operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DC /r
VAESENC xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform one round of an AES encryption flow,
operating on a 128-bit data (state) from
xmm2 with a 128-bit round key from the
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs a single round of an AES encryption flow using a round key from the second source
operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination
operand.
Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENCCLAST instruction.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESENC
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← ShiftRows( STATE );
STATE ← SubBytes( STATE );
STATE ← MixColumns( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESENC
STATE  SRC1;
RoundKey  SRC2;
STATE  ShiftRows( STATE );
STATE  SubBytes( STATE );
STATE  MixColumns( STATE );
DEST[127:0]  STATE XOR RoundKey;
DEST[VLMAX-1:128]  0
3-54 Vol. 2A
AESENC—Perform One Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENC:
__m128i _mm_aesenc (__m128i, __m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESENC—Perform One Round of an AES Encryption Flow
Vol. 2A 3-55
INSTRUCTION SET REFERENCE, A-L
AESENCLAST—Perform Last Round of an AES Encryption Flow
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DD /r
AESENCLAST xmm1, xmm2/m128
RM
V/V
AES
Perform the last round of an AES encryption
flow, operating on a 128-bit data (state) from
xmm1 with a 128-bit round key from
xmm2/m128.
VEX.NDS.128.66.0F38.WIG DD /r
VAESENCLAST xmm1, xmm2, xmm3/m128
RVM V/V
Both AES
and
AVX flags
Perform the last round of an AES encryption
flow, operating on a 128-bit data (state) from
xmm2 with a 128 bit round key from
xmm3/m128; store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
This instruction performs the last round of an AES encryption flow using a round key from the second source
operand, operating on 128-bit data (state) from the first source operand, and store the result in the destination
operand.
128-bit Legacy SSE version: The first source operand and the destination operand are the same and must be an
XMM register. The second source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.
Operation
AESENCLAST
STATE ← SRC1;
RoundKey ← SRC2;
STATE ← ShiftRows( STATE );
STATE ← SubBytes( STATE );
DEST[127:0] ← STATE XOR RoundKey;
DEST[VLMAX-1:128] (Unmodified)
VAESENCLAST
STATE  SRC1;
RoundKey  SRC2;
STATE  ShiftRows( STATE );
STATE  SubBytes( STATE );
DEST[127:0]  STATE XOR RoundKey;
DEST[VLMAX-1:128]  0
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESENCLAST:
3-56 Vol. 2A
__m128i _mm_aesenclast (__m128i, __m128i)
AESENCLAST—Perform Last Round of an AES Encryption Flow
INSTRUCTION SET REFERENCE, A-L
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
AESENCLAST—Perform Last Round of an AES Encryption Flow
Vol. 2A 3-57
INSTRUCTION SET REFERENCE, A-L
AESIMC—Perform the AES InvMixColumn Transformation
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 DB /r
AESIMC xmm1, xmm2/m128
RM
V/V
AES
Perform the InvMixColumn transformation on
a 128-bit round key from xmm2/m128 and
store the result in xmm1.
VEX.128.66.0F38.WIG DB /r
VAESIMC xmm1, xmm2/m128
RM
V/V
Both AES
and
AVX flags
Perform the InvMixColumn transformation on
a 128-bit round key from xmm2/m128 and
store the result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Perform the InvMixColumns transformation on the source operand and store the result in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location.
Note: the AESIMC instruction should be applied to the expanded AES round keys (except for the first and last round
key) in order to prepare them for decryption using the “Equivalent Inverse Cipher” (defined in FIPS 197).
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESIMC
DEST[127:0] ← InvMixColumns( SRC );
DEST[VLMAX-1:128] (Unmodified)
VAESIMC
DEST[127:0]  InvMixColumns( SRC );
DEST[VLMAX-1:128]  0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESIMC:
__m128i _mm_aesimc (__m128i)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-58 Vol. 2A
If VEX.vvvv ≠ 1111B.
AESIMC—Perform the AES InvMixColumn Transformation
INSTRUCTION SET REFERENCE, A-L
AESKEYGENASSIST—AES Round Key Generation Assist
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A DF /r ib
AESKEYGENASSIST xmm1, xmm2/m128, imm8
RMI
V/V
AES
Assist in AES round key generation using an 8
bits Round Constant (RCON) specified in the
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
VEX.128.66.0F3A.WIG DF /r ib
VAESKEYGENASSIST xmm1, xmm2/m128, imm8
RMI
V/V
Both AES
and
AVX flags
Assist in AES round key generation using 8
bits Round Constant (RCON) specified in the
immediate byte, operating on 128 bits of data
specified in xmm2/m128 and stores the
result in xmm1.
Instruction Operand Encoding
Op/En
Operand 1
Operand2
Operand3
Operand4
RMI
ModRM:reg (w)
ModRM:r/m (r)
imm8
NA
Description
Assist in expanding the AES cipher key, by computing steps towards generating a round key for encryption, using
128-bit data specified in the source operand and an 8-bit round constant specified as an immediate, store the
result in the destination operand.
The destination operand is an XMM register. The source operand can be an XMM register or a 128-bit memory location.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Operation
AESKEYGENASSIST
X3[31:0] ← SRC [127: 96];
X2[31:0] ← SRC [95: 64];
X1[31:0] ← SRC [63: 32];
X0[31:0] ← SRC [31: 0];
RCON[31:0] ← ZeroExtend(Imm8[7:0]);
DEST[31:0] ← SubWord(X1);
DEST[63:32 ] ← RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64] ← SubWord(X3);
DEST[127:96] ← RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128] (Unmodified)
AESKEYGENASSIST—AES Round Key Generation Assist
Vol. 2A 3-59
INSTRUCTION SET REFERENCE, A-L
VAESKEYGENASSIST
X3[31:0]  SRC [127: 96];
X2[31:0]  SRC [95: 64];
X1[31:0]  SRC [63: 32];
X0[31:0]  SRC [31: 0];
RCON[31:0]  ZeroExtend(Imm8[7:0]);
DEST[31:0]  SubWord(X1);
DEST[63:32 ]  RotWord( SubWord(X1) ) XOR RCON;
DEST[95:64]  SubWord(X3);
DEST[127:96]  RotWord( SubWord(X3) ) XOR RCON;
DEST[VLMAX-1:128]  0;
Intel C/C++ Compiler Intrinsic Equivalent
(V)AESKEYGENASSIST:
__m128i _mm_aeskeygenassist (__m128i, const int)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-60 Vol. 2A
If VEX.vvvv ≠ 1111B.
AESKEYGENASSIST—AES Round Key Generation Assist
INSTRUCTION SET REFERENCE, A-L
AND—Logical AND
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
24 ib
AND AL, imm8
I
Valid
Valid
AL AND imm8.
25 iw
AND AX, imm16
I
Valid
Valid
AX AND imm16.
25 id
AND EAX, imm32
I
Valid
Valid
EAX AND imm32.
REX.W + 25 id
AND RAX, imm32
I
Valid
N.E.
RAX AND imm32 sign-extended to 64-bits.
80 /4 ib
AND r/m8, imm8
MI
Valid
Valid
r/m8 AND imm8.
REX + 80 /4 ib
AND r/m8*, imm8
MI
Valid
N.E.
r/m8 AND imm8.
81 /4 iw
AND r/m16, imm16
MI
Valid
Valid
r/m16 AND imm16.
81 /4 id
AND r/m32, imm32
MI
Valid
Valid
r/m32 AND imm32.
REX.W + 81 /4 id
AND r/m64, imm32
MI
Valid
N.E.
r/m64 AND imm32 sign extended to 64-bits.
83 /4 ib
AND r/m16, imm8
MI
Valid
Valid
r/m16 AND imm8 (sign-extended).
83 /4 ib
AND r/m32, imm8
MI
Valid
Valid
r/m32 AND imm8 (sign-extended).
REX.W + 83 /4 ib
AND r/m64, imm8
MI
Valid
N.E.
r/m64 AND imm8 (sign-extended).
20 /r
AND r/m8, r8
MR
Valid
Valid
r/m8 AND r8.
REX + 20 /r
AND r/m8*, r8*
MR
Valid
N.E.
r/m64 AND r8 (sign-extended).
21 /r
AND r/m16, r16
MR
Valid
Valid
r/m16 AND r16.
21 /r
AND r/m32, r32
MR
Valid
Valid
r/m32 AND r32.
REX.W + 21 /r
AND r/m64, r64
MR
Valid
N.E.
r/m64 AND r32.
22 /r
AND r8, r/m8
RM
Valid
Valid
r8 AND r/m8.
REX + 22 /r
AND r8*, r/m8*
RM
Valid
N.E.
r/m64 AND r8 (sign-extended).
23 /r
AND r16, r/m16
RM
Valid
Valid
r16 AND r/m16.
23 /r
AND r32, r/m32
RM
Valid
Valid
r32 AND r/m32.
REX.W + 23 /r
AND r64, r/m64
RM
Valid
N.E.
r64 AND r/m64.
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
I
AL/AX/EAX/RAX
imm8
NA
NA
Description
Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in
the destination operand location. The source operand can be an immediate, a register, or a memory location; the
destination operand can be a register or a memory location. (However, two memory operands cannot be used in
one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1;
otherwise, it is set to 0.
This instruction can be used with a LOCK prefix to allow the it to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
AND—Logical AND
Vol. 2A 3-61
INSTRUCTION SET REFERENCE, A-L
Operation
DEST ← DEST AND SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-62 Vol. 2A
AND—Logical AND
INSTRUCTION SET REFERENCE, A-L
ANDN — Logical AND NOT
Opcode/Instruction
Op/
En
CPUID
Feature
Flag
BMI1
Description
RVM
64/32
-bit
Mode
V/V
VEX.NDS.LZ.0F38.W0 F2 /r
ANDN r32a, r32b, r/m32
VEX.NDS.LZ. 0F38.W1 F2 /r
ANDN r64a, r64b, r/m64
RVM
V/NE
BMI1
Bitwise AND of inverted r64b with r/m64, store result in r64a.
Bitwise AND of inverted r32b with r/m32, store result in r32a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RVM
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of inverted second operand (the first source operand) with the third operand (the
second source operand). The result is stored in the first operand (destination operand).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
DEST ← (NOT SRC1) bitwiseAND SRC2;
SF ← DEST[OperandSize -1];
ZF ← (DEST = 0);
Flags Affected
SF and ZF are updated based on result. OF and CF flags are cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
ANDN — Logical AND NOT
If VEX.W = 1.
Vol. 2A 3-63
INSTRUCTION SET REFERENCE, A-L
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 54 /r
ANDPD xmm1, xmm2/m128
VEX.NDS.128.66.0F 54 /r
VANDPD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F 54 /r
VANDPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 54 /r
VANDPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 54 /r
VANDPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 54 /r
VANDPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND of packed doubleprecision floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND of packed doubleprecision floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
3-64 Vol. 2A
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i]  SRC1[i+63:i] BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i]  SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VANDPD (VEX.256 encoded version)
DEST[63:0]  SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64]  SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[191:128]  SRC1[191:128] BITWISE AND SRC2[191:128]
DEST[255:192]  SRC1[255:192] BITWISE AND SRC2[255:192]
DEST[MAX_VL-1:256]  0
VANDPD (VEX.128 encoded version)
DEST[63:0]  SRC1[63:0] BITWISE AND SRC2[63:0]
DEST[127:64]  SRC1[127:64] BITWISE AND SRC2[127:64]
DEST[MAX_VL-1:128]  0
ANDPD (128-bit Legacy SSE version)
DEST[63:0]  DEST[63:0] BITWISE AND SRC[63:0]
DEST[127:64]  DEST[127:64] BITWISE AND SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDPD __m512d _mm512_and_pd (__m512d a, __m512d b);
VANDPD __m512d _mm512_mask_and_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDPD __m512d _mm512_maskz_and_pd (__mmask8 k, __m512d a, __m512d b);
VANDPD __m256d _mm256_mask_and_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDPD __m256d _mm256_maskz_and_pd (__mmask8 k, __m256d a, __m256d b);
VANDPD __m128d _mm_mask_and_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDPD __m128d _mm_maskz_and_pd (__mmask8 k, __m128d a, __m128d b);
VANDPD __m256d _mm256_and_pd (__m256d a, __m256d b);
ANDPD __m128d _mm_and_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
Vol. 2A 3-65
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
3-66 Vol. 2A
ANDPD—Bitwise Logical AND of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 54 /r
ANDPS xmm1, xmm2/m128
VEX.NDS.128.0F 54 /r
VANDPS xmm1,xmm2,
xmm3/m128
VEX.NDS.256.0F 54 /r
VANDPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 54 /r
VANDPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 54 /r
VANDPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 54 /r
VANDPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/m128/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/m256/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in zmm2 and zmm3/m512/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Vol. 2A 3-67
INSTRUCTION SET REFERENCE, A-L
Operation
VANDPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i]  SRC1[i+31:i] BITWISE AND SRC2[31:0]
ELSE
DEST[i+31:i]  SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0;
VANDPS (VEX.256 encoded version)
DEST[31:0]  SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32]  SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64]  SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96]  SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[159:128]  SRC1[159:128] BITWISE AND SRC2[159:128]
DEST[191:160]  SRC1[191:160] BITWISE AND SRC2[191:160]
DEST[223:192]  SRC1[223:192] BITWISE AND SRC2[223:192]
DEST[255:224]  SRC1[255:224] BITWISE AND SRC2[255:224].
DEST[MAX_VL-1:256]  0;
VANDPS (VEX.128 encoded version)
DEST[31:0]  SRC1[31:0] BITWISE AND SRC2[31:0]
DEST[63:32]  SRC1[63:32] BITWISE AND SRC2[63:32]
DEST[95:64]  SRC1[95:64] BITWISE AND SRC2[95:64]
DEST[127:96]  SRC1[127:96] BITWISE AND SRC2[127:96]
DEST[MAX_VL-1:128]  0;
ANDPS (128-bit Legacy SSE version)
DEST[31:0]  DEST[31:0] BITWISE AND SRC[31:0]
DEST[63:32]  DEST[63:32] BITWISE AND SRC[63:32]
DEST[95:64]  DEST[95:64] BITWISE AND SRC[95:64]
DEST[127:96]  DEST[127:96] BITWISE AND SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
3-68 Vol. 2A
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VANDPS __m512 _mm512_and_ps (__m512 a, __m512 b);
VANDPS __m512 _mm512_mask_and_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VANDPS __m512 _mm512_maskz_and_ps (__mmask16 k, __m512 a, __m512 b);
VANDPS __m256 _mm256_mask_and_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VANDPS __m256 _mm256_maskz_and_ps (__mmask8 k, __m256 a, __m256 b);
VANDPS __m128 _mm_mask_and_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDPS __m128 _mm_maskz_and_ps (__mmask8 k, __m128 a, __m128 b);
VANDPS __m256 _mm256_and_ps (__m256 a, __m256 b);
ANDPS __m128 _mm_and_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
ANDPS—Bitwise Logical AND of Packed Single Precision Floating-Point Values
Vol. 2A 3-69
INSTRUCTION SET REFERENCE, A-L
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 55 /r
ANDNPD xmm1, xmm2/m128
VEX.NDS.128.66.0F 55 /r
VANDNPD xmm1, xmm2,
xmm3/m128
VEX.NDS.256.66.0F 55/r
VANDNPD ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.66.0F.W1 55 /r
VANDNPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 55 /r
VANDNPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
EVEX.NDS.512.66.0F.W1 55 /r
VANDNPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and
xmm3/m128/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and
ymm3/m256/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in zmm2 and
zmm3/m512/m64bcst subject to writemask k1.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND NOT of the two, four or eight packed double-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.
3-70 Vol. 2A
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VANDNPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i]  (NOT(SRC1[i+63:i])) BITWISE AND SRC2[63:0]
ELSE
DEST[i+63:i]  (NOT(SRC1[i+63:i])) BITWISE AND SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VANDNPD (VEX.256 encoded version)
DEST[63:0]  (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64]  (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[191:128]  (NOT(SRC1[191:128])) BITWISE AND SRC2[191:128]
DEST[255:192]  (NOT(SRC1[255:192])) BITWISE AND SRC2[255:192]
DEST[MAX_VL-1:256]  0
VANDNPD (VEX.128 encoded version)
DEST[63:0]  (NOT(SRC1[63:0])) BITWISE AND SRC2[63:0]
DEST[127:64]  (NOT(SRC1[127:64])) BITWISE AND SRC2[127:64]
DEST[MAX_VL-1:128]  0
ANDNPD (128-bit Legacy SSE version)
DEST[63:0]  (NOT(DEST[63:0])) BITWISE AND SRC[63:0]
DEST[127:64]  (NOT(DEST[127:64])) BITWISE AND SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VANDNPD __m512d _mm512_andnot_pd (__m512d a, __m512d b);
VANDNPD __m512d _mm512_mask_andnot_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VANDNPD __m512d _mm512_maskz_andnot_pd (__mmask8 k, __m512d a, __m512d b);
VANDNPD __m256d _mm256_mask_andnot_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VANDNPD __m256d _mm256_maskz_andnot_pd (__mmask8 k, __m256d a, __m256d b);
VANDNPD __m128d _mm_mask_andnot_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VANDNPD __m128d _mm_maskz_andnot_pd (__mmask8 k, __m128d a, __m128d b);
VANDNPD __m256d _mm256_andnot_pd (__m256d a, __m256d b);
ANDNPD __m128d _mm_andnot_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
None
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
Vol. 2A 3-71
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
3-72 Vol. 2A
ANDNPD—Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 55 /r
ANDNPS xmm1, xmm2/m128
VEX.NDS.128.0F 55 /r
VANDNPS xmm1, xmm2,
xmm3/m128
VEX.NDS.256.0F 55 /r
VANDNPS ymm1, ymm2,
ymm3/m256
EVEX.NDS.128.0F.W0 55 /r
VANDNPS xmm1 {k1}{z},
xmm2, xmm3/m128/m32bcst
EVEX.NDS.256.0F.W0 55 /r
VANDNPS ymm1 {k1}{z},
ymm2, ymm3/m256/m32bcst
EVEX.NDS.512.0F.W0 55 /r
VANDNPS zmm1 {k1}{z},
zmm2, zmm3/m512/m32bcst
Description
RVM
V/V
AVX
RVM
V/V
AVX
Return the bitwise logical AND NOT of packed single-precision
floating-point values in ymm2 and ymm3/mem.
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512VL
AVX512DQ
FV
V/V
AVX512DQ
Return the bitwise logical AND of packed single-precision
floating-point values in xmm2 and xmm3/m128/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in ymm2 and ymm3/m256/m32bcst
subject to writemask k1.
Return the bitwise logical AND of packed single-precision
floating-point values in zmm2 and zmm3/m512/m32bcst
subject to writemask k1.
Return the bitwise logical AND NOT of packed single-precision
floating-point values in xmm1 and xmm2/mem.
Return the bitwise logical AND NOT of packed single-precision
floating-point values in xmm2 and xmm3/mem.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a bitwise logical AND NOT of the four, eight or sixteen packed single-precision floating-point values from
the first source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Vol. 2A 3-73
INSTRUCTION SET REFERENCE, A-L
Operation
VANDNPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
IF (EVEX.b == 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i]  (NOT(SRC1[i+31:i])) BITWISE AND SRC2[31:0]
ELSE
DEST[i+31:i]  (NOT(SRC1[i+31:i])) BITWISE AND SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i] = 0
FI;
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VANDNPS (VEX.256 encoded version)
DEST[31:0]  (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]
DEST[63:32]  (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]
DEST[95:64]  (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]
DEST[127:96]  (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]
DEST[159:128]  (NOT(SRC1[159:128])) BITWISE AND SRC2[159:128]
DEST[191:160]  (NOT(SRC1[191:160])) BITWISE AND SRC2[191:160]
DEST[223:192]  (NOT(SRC1[223:192])) BITWISE AND SRC2[223:192]
DEST[255:224]  (NOT(SRC1[255:224])) BITWISE AND SRC2[255:224].
DEST[MAX_VL-1:256]  0
VANDNPS (VEX.128 encoded version)
DEST[31:0]  (NOT(SRC1[31:0])) BITWISE AND SRC2[31:0]
DEST[63:32]  (NOT(SRC1[63:32])) BITWISE AND SRC2[63:32]
DEST[95:64]  (NOT(SRC1[95:64])) BITWISE AND SRC2[95:64]
DEST[127:96]  (NOT(SRC1[127:96])) BITWISE AND SRC2[127:96]
DEST[MAX_VL-1:128]  0
ANDNPS (128-bit Legacy SSE version)
DEST[31:0]  (NOT(DEST[31:0])) BITWISE AND SRC[31:0]
DEST[63:32]  (NOT(DEST[63:32])) BITWISE AND SRC[63:32]
DEST[95:64]  (NOT(DEST[95:64])) BITWISE AND SRC[95:64]
DEST[127:96]  (NOT(DEST[127:96])) BITWISE AND SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)
3-74 Vol. 2A
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VANDNPS __m512 _mm512_andnot_ps (__m512 a, __m512 b);
VANDNPS __m512 _mm512_mask_andnot_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VANDNPS __m512 _mm512_maskz_andnot_ps (__mmask16 k, __m512 a, __m512 b);
VANDNPS __m256 _mm256_mask_andnot_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VANDNPS __m256 _mm256_maskz_andnot_ps (__mmask8 k, __m256 a, __m256 b);
VANDNPS __m128 _mm_mask_andnot_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VANDNPS __m128 _mm_maskz_andnot_ps (__mmask8 k, __m128 a, __m128 b);
VANDNPS __m256 _mm256_andnot_ps (__m256 a, __m256 b);
ANDNPS __m128 _mm_andnot_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
None
Other Exceptions
VEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.
ANDNPS—Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values
Vol. 2A 3-75
INSTRUCTION SET REFERENCE, A-L
ARPL—Adjust RPL Field of Segment Selector
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
63 /r
ARPL r/m16, r16
NP
N. E.
Valid
Adjust RPL of r/m16 to not less than RPL of
r16.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
ModRM:r/m (w)
ModRM:reg (r)
NA
NA
Description
Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one
segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0
and 1 of each operand.) If the RPL field of the destination operand is less than the RPL field of the source operand,
the ZF flag is set and the RPL field of the destination operand is increased to match that of the source operand.
Otherwise, the ZF flag is cleared and no change is made to the destination operand. (The destination operand can
be a word register or a memory location; the source operand must be a word register.)
The ARPL instruction is provided for use by operating-system procedures (however, it can also be used by applications). It is generally used to adjust the RPL of a segment selector that has been passed to the operating system
by an application program to match the privilege level of the application program. Here the segment selector
passed to the operating system is placed in the destination operand and segment selector for the application
program’s code segment is placed in the source operand. (The RPL field in the source operand represents the privilege level of the application program.) Execution of the ARPL instruction then ensures that the RPL of the segment
selector received by the operating system is no lower (does not have a higher privilege) than the privilege level of
the application program (the segment selector for the application program’s code segment can be read from the
stack following a procedure call).
This instruction executes as described in compatibility mode and legacy mode. It is not encodable in 64-bit mode.
See “Checking Caller Access Privileges” in Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information about the use of this instruction.
Operation
IF 64-BIT MODE
THEN
See MOVSXD;
ELSE
IF DEST[RPL] < SRC[RPL]
THEN
ZF ← 1;
DEST[RPL] ← SRC[RPL];
ELSE
ZF ← 0;
FI;
FI;
Flags Affected
The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise,
it is set to 0.
3-76 Vol. 2A
ARPL—Adjust RPL Field of Segment Selector
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
The ARPL instruction is not recognized in real-address mode.
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
The ARPL instruction is not recognized in virtual-8086 mode.
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
Not applicable.
ARPL—Adjust RPL Field of Segment Selector
Vol. 2A 3-77
INSTRUCTION SET REFERENCE, A-L
BLENDPD — Blend Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 0D /r ib
RMI
V/V
SSE4_1
Select packed DP-FP values from xmm1 and
xmm2/m128 from mask specified in imm8
and store the values into xmm1.
RVMI V/V
AVX
Select packed double-precision floating-point
Values from xmm2 and xmm3/m128 from
mask in imm8 and store the values in xmm1.
RVMI V/V
AVX
Select packed double-precision floating-point
Values from ymm2 and ymm3/m256 from
mask in imm8 and store the values in ymm1.
BLENDPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 0D /r ib
VBLENDPD xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 0D /r ib
VBLENDPD ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[3:0]
Description
Double-precision floating-point values from the second source operand (third operand) are conditionally merged
with values from the first source operand (second operand) and written to the destination operand (first operand).
The immediate bits [3:0] determine whether the corresponding double-precision floating-point value in the destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is ”1”, then
the double-precision floating-point value in the second source operand is copied, else the value in the first source
operand is copied.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
BLENDPD (128-bit Legacy SSE version)
IF (IMM8[0] = 0)THEN DEST[63:0]  DEST[63:0]
ELSE DEST [63:0]  SRC[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64]  DEST[127:64]
ELSE DEST [127:64]  SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDPD (VEX.128 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0]  SRC1[63:0]
ELSE DEST [63:0]  SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64]  SRC1[127:64]
ELSE DEST [127:64]  SRC2[127:64] FI
DEST[VLMAX-1:128]  0
3-78 Vol. 2A
BLENDPD — Blend Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VBLENDPD (VEX.256 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0]  SRC1[63:0]
ELSE DEST [63:0]  SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64]  SRC1[127:64]
ELSE DEST [127:64]  SRC2[127:64] FI
IF (IMM8[2] = 0) THEN DEST[191:128]  SRC1[191:128]
ELSE DEST [191:128]  SRC2[191:128] FI
IF (IMM8[3] = 0) THEN DEST[255:192]  SRC1[255:192]
ELSE DEST [255:192]  SRC2[255:192] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDPD:
__m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);
VBLENDPD:
__m256d _mm256_blend_pd (__m256d a, __m256d b, const int mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
BLENDPD — Blend Packed Double Precision Floating-Point Values
Vol. 2A 3-79
INSTRUCTION SET REFERENCE, A-L
BEXTR — Bit Field Extract
Opcode/Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDS.LZ.0F38.W0 F7 /r
BEXTR r32a, r/m32, r32b
VEX.NDS.LZ.0F38.W1 F7 /r
BEXTR r64a, r/m64, r64b
RMV
V/N.E.
BMI1
Description
Contiguous bitwise extract from r/m32 using r32b as control; store
result in r32a.
Contiguous bitwise extract from r/m64 using r64b as control; store
result in r64a
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (w)
ModRM:r/m (r)
VEX.vvvv (r)
NA
Description
Extracts contiguous bits from the first source operand (the second operand) using an index value and length value
specified in the second source operand (the third operand). Bit 7:0 of the second source operand specifies the
starting bit position of bit extraction. A START value exceeding the operand size will not extract any bits from the
second source operand. Bit 15:8 of the second source operand specifies the maximum number of bits (LENGTH)
beginning at the START position to extract. Only bit positions up to (OperandSize -1) of the first source operand are
extracted. The extracted bits are written to the destination register, starting from the least significant bit. All higher
order bits in the destination operand (starting at bit position LENGTH) are zeroed. The destination register is
cleared if no bits are extracted.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
START ← SRC2[7:0];
LEN ← SRC2[15:8];
TEMP ← ZERO_EXTEND_TO_512 (SRC1 );
DEST ← ZERO_EXTEND(TEMP[START+LEN -1: START]);
ZF ← (DEST = 0);
Flags Affected
ZF is updated based on the result. AF, SF, and PF are undefined. All other flags are cleared.
Intel C/C++ Compiler Intrinsic Equivalent
BEXTR:
unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start. unsigned __int32 len);
BEXTR:
unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start. unsigned __int32 len);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-80 Vol. 2A
If VEX.W = 1.
BEXTR — Bit Field Extract
INSTRUCTION SET REFERENCE, A-L
BLENDPS — Blend Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 3A 0C /r ib
RMI
V/V
SSE4_1
Select packed single precision floating-point
values from xmm1 and xmm2/m128 from
mask specified in imm8 and store the values
into xmm1.
RVMI V/V
AVX
Select packed single-precision floating-point
values from xmm2 and xmm3/m128 from
mask in imm8 and store the values in xmm1.
RVMI V/V
AVX
Select packed single-precision floating-point
values from ymm2 and ymm3/m256 from
mask in imm8 and store the values in ymm1.
BLENDPS xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F3A.WIG 0C /r ib
VBLENDPS xmm1, xmm2, xmm3/m128, imm8
VEX.NDS.256.66.0F3A.WIG 0C /r ib
VBLENDPS ymm1, ymm2, ymm3/m256, imm8
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8
Description
Packed single-precision floating-point values from the second source operand (third operand) are conditionally
merged with values from the first source operand (second operand) and written to the destination operand (first
operand). The immediate bits [7:0] determine whether the corresponding single precision floating-point value in
the destination is copied from the second source or first source. If a bit in the mask, corresponding to a word, is
“1”, then the single-precision floating-point value in the second source operand is copied, else the value in the first
source operand is copied.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: The first source operand an XMM register. The second source operand is an XMM register
or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the
corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Operation
BLENDPS (128-bit Legacy SSE version)
IF (IMM8[0] = 0) THEN DEST[31:0] DEST[31:0]
ELSE DEST [31:0]  SRC[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32]  DEST[63:32]
ELSE DEST [63:32]  SRC[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64]  DEST[95:64]
ELSE DEST [95:64]  SRC[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96]  DEST[127:96]
ELSE DEST [127:96]  SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
BLENDPS — Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-81
INSTRUCTION SET REFERENCE, A-L
VBLENDPS (VEX.128 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0]  SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32]  SRC1[63:32]
ELSE DEST [63:32]  SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64]  SRC1[95:64]
ELSE DEST [95:64]  SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96]  SRC1[127:96]
ELSE DEST [127:96]  SRC2[127:96] FI
DEST[VLMAX-1:128]  0
VBLENDPS (VEX.256 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] SRC1[31:0]
ELSE DEST [31:0]  SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32]  SRC1[63:32]
ELSE DEST [63:32]  SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64]  SRC1[95:64]
ELSE DEST [95:64]  SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96]  SRC1[127:96]
ELSE DEST [127:96]  SRC2[127:96] FI
IF (IMM8[4] = 0) THEN DEST[159:128]  SRC1[159:128]
ELSE DEST [159:128]  SRC2[159:128] FI
IF (IMM8[5] = 0) THEN DEST[191:160]  SRC1[191:160]
ELSE DEST [191:160]  SRC2[191:160] FI
IF (IMM8[6] = 0) THEN DEST[223:192]  SRC1[223:192]
ELSE DEST [223:192]  SRC2[223:192] FI
IF (IMM8[7] = 0) THEN DEST[255:224]  SRC1[255:224]
ELSE DEST [255:224]  SRC2[255:224] FI.
Intel C/C++ Compiler Intrinsic Equivalent
BLENDPS:
__m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);
VBLENDPS:
__m256 _mm256_blend_ps (__m256 a, __m256 b, const int mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4.
3-82 Vol. 2A
BLENDPS — Blend Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 15 /r
RM0
V/V
SSE4_1
Select packed DP FP values from xmm1 and
xmm2 from mask specified in XMM0 and
store the values in xmm1.
RVMR V/V
AVX
Conditionally copy double-precision floatingpoint values from xmm2 or xmm3/m128 to
xmm1, based on mask bits in the mask
operand, xmm4.
RVMR V/V
AVX
Conditionally copy double-precision floatingpoint values from ymm2 or ymm3/m256 to
ymm1, based on mask bits in the mask
operand, ymm4.
BLENDVPD xmm1, xmm2/m128 , <XMM0>
VEX.NDS.128.66.0F3A.W0 4B /r /is4
VBLENDVPD xmm1, xmm2, xmm3/m128, xmm4
VEX.NDS.256.66.0F3A.W0 4B /r /is4
VBLENDVPD ymm1, ymm2, ymm3/m256, ymm4
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM0
ModRM:reg (r, w)
ModRM:r/m (r)
implicit XMM0
NA
RVMR
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[7:4]
Description
Conditionally copy each quadword data element of double-precision floating-point value from the second source
operand and the first source operand depending on mask bits defined in the mask register operand. The mask bits
are the most significant bit in each quadword element of the mask register.
Each quadword element of the destination operand is copied from:
•
•
the corresponding quadword element in the second source operand, if a mask bit is “1”; or
the corresponding quadword element in the first source operand, if a mask bit is “0”
The register assignment of the implicit mask operand for BLENDVPD is defined to be the architectural register
XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute BLENDVPD with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.
VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source
operand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. VEX.W must be 0, otherwise, the instruction will #UD.
VBLENDVPD permits the mask to be any XMM or YMM register. In contrast, BLENDVPD treats XMM0 implicitly as the
mask and do not support non-destructive destination operation.
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
Vol. 2A 3-83
INSTRUCTION SET REFERENCE, A-L
Operation
BLENDVPD (128-bit Legacy SSE version)
MASK  XMM0
IF (MASK[63] = 0) THEN DEST[63:0]  DEST[63:0]
ELSE DEST [63:0]  SRC[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64]  DEST[127:64]
ELSE DEST [127:64]  SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPD (VEX.128 encoded version)
MASK  SRC3
IF (MASK[63] = 0) THEN DEST[63:0]  SRC1[63:0]
ELSE DEST [63:0]  SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64]  SRC1[127:64]
ELSE DEST [127:64]  SRC2[127:64] FI
DEST[VLMAX-1:128]  0
VBLENDVPD (VEX.256 encoded version)
MASK  SRC3
IF (MASK[63] = 0) THEN DEST[63:0]  SRC1[63:0]
ELSE DEST [63:0]  SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64]  SRC1[127:64]
ELSE DEST [127:64]  SRC2[127:64] FI
IF (MASK[191] = 0) THEN DEST[191:128]  SRC1[191:128]
ELSE DEST [191:128]  SRC2[191:128] FI
IF (MASK[255] = 0) THEN DEST[255:192]  SRC1[255:192]
ELSE DEST [255:192]  SRC2[255:192] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDVPD:
__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);
VBLENDVPD:
__m128 _mm_blendv_pd (__m128d a, __m128d b, __m128d mask);
VBLENDVPD:
__m256 _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Exceptions Type 4; additionally
#UD
3-84 Vol. 2A
If VEX.W = 1.
BLENDVPD — Variable Blend Packed Double Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Opcode/
Instruction
Op/
En
64/32-bit CPUID
Mode
Feature
Flag
Description
66 0F 38 14 /r
RM0
V/V
SSE4_1
Select packed single precision floating-point
values from xmm1 and xmm2/m128 from
mask specified in XMM0 and store the values
into xmm1.
RVMR V/V
AVX
Conditionally copy single-precision floatingpoint values from xmm2 or xmm3/m128 to
xmm1, based on mask bits in the specified
mask operand, xmm4.
RVMR V/V
AVX
Conditionally copy single-precision floatingpoint values from ymm2 or ymm3/m256 to
ymm1, based on mask bits in the specified
mask register, ymm4.
BLENDVPS xmm1, xmm2/m128, <XMM0>
VEX.NDS.128.66.0F3A.W0 4A /r /is4
VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4
VEX.NDS.256.66.0F3A.W0 4A /r /is4
VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM0
ModRM:reg (r, w)
ModRM:r/m (r)
implicit XMM0
NA
RVMR
ModRM:reg (w)
VEX.vvvv (r)
ModRM:r/m (r)
imm8[7:4]
Description
Conditionally copy each dword data element of single-precision floating-point value from the second source
operand and the first source operand depending on mask bits defined in the mask register operand. The mask bits
are the most significant bit in each dword element of the mask register.
Each quadword element of the destination operand is copied from:
•
•
the corresponding dword element in the second source operand, if a mask bit is “1”; or
the corresponding dword element in the first source operand, if a mask bit is “0”
The register assignment of the implicit mask operand for BLENDVPS is defined to be the architectural register
XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute BLENDVPS with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed.
VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are YMM registers. The second source
operand can be a YMM register or a 256-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. VEX.W must be 0, otherwise, the instruction will #UD.
VBLENDVPS permits the mask to be any XMM or YMM register. In contrast, BLENDVPS treats XMM0 implicitly as the
mask and do not support non-destructive destination operation.
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-85
INSTRUCTION SET REFERENCE, A-L
Operation
BLENDVPS (128-bit Legacy SSE version)
MASK  XMM0
IF (MASK[31] = 0) THEN DEST[31:0]  DEST[31:0]
ELSE DEST [31:0]  SRC[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32]  DEST[63:32]
ELSE DEST [63:32]  SRC[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64]  DEST[95:64]
ELSE DEST [95:64]  SRC[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96]  DEST[127:96]
ELSE DEST [127:96]  SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPS (VEX.128 encoded version)
MASK  SRC3
IF (MASK[31] = 0) THEN DEST[31:0]  SRC1[31:0]
ELSE DEST [31:0]  SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32]  SRC1[63:32]
ELSE DEST [63:32]  SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64]  SRC1[95:64]
ELSE DEST [95:64]  SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96]  SRC1[127:96]
ELSE DEST [127:96]  SRC2[127:96] FI
DEST[VLMAX-1:128]  0
VBLENDVPS (VEX.256 encoded version)
MASK  SRC3
IF (MASK[31] = 0) THEN DEST[31:0]  SRC1[31:0]
ELSE DEST [31:0]  SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32]  SRC1[63:32]
ELSE DEST [63:32]  SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64]  SRC1[95:64]
ELSE DEST [95:64]  SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96]  SRC1[127:96]
ELSE DEST [127:96]  SRC2[127:96] FI
IF (MASK[159] = 0) THEN DEST[159:128]  SRC1[159:128]
ELSE DEST [159:128]  SRC2[159:128] FI
IF (MASK[191] = 0) THEN DEST[191:160]  SRC1[191:160]
ELSE DEST [191:160]  SRC2[191:160] FI
IF (MASK[223] = 0) THEN DEST[223:192]  SRC1[223:192]
ELSE DEST [223:192]  SRC2[223:192] FI
IF (MASK[255] = 0) THEN DEST[255:224]  SRC1[255:224]
ELSE DEST [255:224]  SRC2[255:224] FI
Intel C/C++ Compiler Intrinsic Equivalent
BLENDVPS:
__m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);
VBLENDVPS:
__m128 _mm_blendv_ps (__m128 a, __m128 b, __m128 mask);
VBLENDVPS:
__m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask);
SIMD Floating-Point Exceptions
None
3-86 Vol. 2A
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
See Exceptions Type 4; additionally
#UD
If VEX.W = 1.
BLENDVPS — Variable Blend Packed Single Precision Floating-Point Values
Vol. 2A 3-87
INSTRUCTION SET REFERENCE, A-L
BLSI — Extract Lowest Set Isolated Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /3
BLSI r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /3
BLSI r64, r/m64
Description
Extract lowest set bit from r/m32 and set that bit in r32.
VM
V/N.E.
BMI1
Extract lowest set bit from r/m64, and set that bit in r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Extracts the lowest set bit from the source operand and set the corresponding bit in the destination register. All
other bits in the destination operand are zeroed. If no bits are set in the source operand, BLSI sets all the bits in
the destination to 0 and sets ZF and CF.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (-SRC) bitwiseAND (SRC);
SF ← temp[OperandSize -1];
ZF ← (temp = 0);
IF SRC = 0
CF ← 0;
ELSE
CF ← 1;
FI
DEST ← temp;
Flags Affected
ZF and SF are updated based on the result. CF is set if the source is not zero. OF flags are cleared. AF and PF
flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSI:
unsigned __int32 _blsi_u32(unsigned __int32 src);
BLSI:
unsigned __int64 _blsi_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-88 Vol. 2A
If VEX.W = 1.
BLSI — Extract Lowest Set Isolated Bit
INSTRUCTION SET REFERENCE, A-L
BLSMSK — Get Mask Up to Lowest Set Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /2
BLSMSK r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /2
BLSMSK r64, r/m64
VM
V/N.E.
BMI1
Description
Set all lower bits in r32 to “1” starting from bit 0 to lowest set bit in
r/m32.
Set all lower bits in r64 to “1” starting from bit 0 to lowest set bit in
r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Sets all the lower bits of the destination operand to “1” up to and including lowest set bit (=1) in the source
operand. If source operand is zero, BLSMSK sets all bits of the destination operand to 1 and also sets CF to 1.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (SRC-1) XOR (SRC) ;
SF ← temp[OperandSize -1];
ZF ← 0;
IF SRC = 0
CF ← 1;
ELSE
CF ← 0;
FI
DEST ← temp;
Flags Affected
SF is updated based on the result. CF is set if the source if zero. ZF and OF flags are cleared. AF and PF flag are
undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSMSK:
unsigned __int32 _blsmsk_u32(unsigned __int32 src);
BLSMSK:
unsigned __int64 _blsmsk_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
BLSMSK — Get Mask Up to Lowest Set Bit
Vol. 2A 3-89
INSTRUCTION SET REFERENCE, A-L
BLSR — Reset Lowest Set Bit
Opcode/Instruction
Op/
En
VM
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI1
VEX.NDD.LZ.0F38.W0 F3 /1
BLSR r32, r/m32
VEX.NDD.LZ.0F38.W1 F3 /1
BLSR r64, r/m64
VM
V/N.E.
BMI1
Description
Reset lowest set bit of r/m32, keep all other bits of r/m32 and write
result to r32.
Reset lowest set bit of r/m64, keep all other bits of r/m64 and write
result to r64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
VM
VEX.vvvv (w)
ModRM:r/m (r)
NA
NA
Description
Copies all bits from the source operand to the destination operand and resets (=0) the bit position in the destination operand that corresponds to the lowest set bit of the source operand. If the source operand is zero BLSR sets
CF.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
temp ← (SRC-1) bitwiseAND ( SRC );
SF ← temp[OperandSize -1];
ZF ← (temp = 0);
IF SRC = 0
CF ← 1;
ELSE
CF ← 0;
FI
DEST ← temp;
Flags Affected
ZF and SF flags are updated based on the result. CF is set if the source is zero. OF flag is cleared. AF and PF flags
are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BLSR:
unsigned __int32 _blsr_u32(unsigned __int32 src);
BLSR:
unsigned __int64 _blsr_u64(unsigned __int64 src);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
3-90 Vol. 2A
If VEX.W = 1.
BLSR — Reset Lowest Set Bit
INSTRUCTION SET REFERENCE, A-L
BNDCL—Check Lower Bound
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
F3 0F 1A /r
BNDCL bnd, r/m32
F3 0F 1A /r
BNDCL bnd, r/m64
RM
V/NE
MPX
Description
Generate a #BR if the address in r/m32 is lower than the lower
bound in bnd.LB.
Generate a #BR if the address in r/m64 is lower than the lower
bound in bnd.LB.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Compare the address in the second operand with the lower bound in bnd. The second operand can be either a
register or memory operand. If the address is lower than the lower bound in bnd.LB, it will set BNDSTATUS to 01H
and signal a #BR exception.
This instruction does not cause any memory access, and does not read or write any flags.
Operation
BNDCL BND, reg
IF reg < BND.LB Then
BNDSTATUS  01H;
#BR;
FI;
BNDCL BND, mem
TEMP  LEA(mem);
IF TEMP < BND.LB Then
BNDSTATUS  01H;
#BR;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDCL void _bnd_chk_ptr_lbounds(const void *q)
Flags Affected
None
Protected Mode Exceptions
#BR
If lower bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
BNDCL—Check Lower Bound
Vol. 2A 3-91
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#BR
#UD
If lower bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Virtual-8086 Mode Exceptions
#BR
#UD
If lower bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
Same exceptions as in protected mode.
3-92 Vol. 2A
BNDCL—Check Lower Bound
INSTRUCTION SET REFERENCE, A-L
BNDCU/BNDCN—Check Upper Bound
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
F2 0F 1A /r
BNDCU bnd, r/m32
F2 0F 1A /r
BNDCU bnd, r/m64
F2 0F 1B /r
BNDCN bnd, r/m32
F2 0F 1B /r
BNDCN bnd, r/m64
RM
V/NE
MPX
RM
NE/V
MPX
RM
V/NE
MPX
Description
Generate a #BR if the address in r/m32 is higher than the upper
bound in bnd.UB (bnb.UB in 1's complement form).
Generate a #BR if the address in r/m64 is higher than the upper
bound in bnd.UB (bnb.UB in 1's complement form).
Generate a #BR if the address in r/m32 is higher than the upper
bound in bnd.UB (bnb.UB not in 1's complement form).
Generate a #BR if the address in r/m64 is higher than the upper
bound in bnd.UB (bnb.UB not in 1's complement form).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Compare the address in the second operand with the upper bound in bnd. The second operand can be either a
register or a memory operand. If the address is higher than the upper bound in bnd.UB, it will set BNDSTATUS to
01H and signal a #BR exception.
BNDCU perform 1’s complement operation on the upper bound of bnd first before proceeding with address comparison. BNDCN perform address comparison directly using the upper bound in bnd that is already reverted out of 1’s
complement form.
This instruction does not cause any memory access, and does not read or write any flags.
Effective address computation of m32/64 has identical behavior to LEA
Operation
BNDCU BND, reg
IF reg > NOT(BND.UB) Then
BNDSTATUS  01H;
#BR;
FI;
BNDCU BND, mem
TEMP  LEA(mem);
IF TEMP > NOT(BND.UB) Then
BNDSTATUS  01H;
#BR;
FI;
BNDCN BND, reg
IF reg > BND.UB Then
BNDSTATUS  01H;
#BR;
FI;
BNDCU/BNDCN—Check Upper Bound
Vol. 2A 3-93
INSTRUCTION SET REFERENCE, A-L
BNDCN BND, mem
TEMP  LEA(mem);
IF TEMP > BND.UB Then
BNDSTATUS  01H;
#BR;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDCU .void _bnd_chk_ptr_ubounds(const void *q)
Flags Affected
None
Protected Mode Exceptions
#BR
If upper bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
Real-Address Mode Exceptions
#BR
#UD
If upper bound check fails.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Virtual-8086 Mode Exceptions
#BR
If upper bound check fails.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
Same exceptions as in protected mode.
3-94 Vol. 2A
BNDCU/BNDCN—Check Upper Bound
INSTRUCTION SET REFERENCE, A-L
BNDLDX—Load Extended Bounds Using Address Translation
Opcode/
Instruction
Op/En
0F 1A /r
BNDLDX bnd, mib
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
MPX
Description
Load the bounds stored in a bound table entry (BTE) into bnd with
address translation using the base of mib and conditional on the
index of mib matching the pointer value in the BTE.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
SIB.base (r): Address of pointer
SIB.index(r)
NA
Description
BNDLDX uses the linear address constructed from the base register and displacement of the SIB-addressing form
of the memory operand (mib) to perform address translation to access a bound table entry and conditionally load
the bounds in the BTE to the destination. The destination register is updated with the bounds in the BTE, if the
content of the index register of mib matches the pointer value stored in the BTE.
If the pointer value comparison fails, the destination is updated with INIT bounds (lb = 0x0, ub = 0x0) (note: as
articulated earlier, the upper bound is represented using 1's complement, therefore, the 0x0 value of upper bound
allows for access to full memory).
This instruction does not cause memory access to the linear address of mib nor the effective address referenced by
the base, and does not read or write any flags.
Segment overrides apply to the linear address computation with the base of mib, and are used during address
translation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be
linear address. There are no segmentation checks performed on the base of mib.
The base of mib will not be checked for canonical address violation as it does not access memory.
Any encoding of this instruction that does not specify base or index register will treat those registers as zero
(constant). The reg-reg form of this instruction will remain a NOP.
The scale field of the SIB byte has no effect on these instructions and is ignored.
The bound register may be partially updated on memory faults. The order in which memory operands are loaded is
implementation specific.
Operation
base  mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value  mib.SIB.index ? mib.SIB.index : 0;
Outside 64-bit mode
A_BDE[31:0]  (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );
A_BT[31:0]  LoadFrom(A_BDE );
IF A_BT[0] equal 0 Then
BNDSTATUS  A_BDE | 02H;
#BR;
FI;
A_BTE[31:0]  (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 );
Temp_lb[31:0]  LoadFrom(A_BTE);
Temp_ub[31:0]  LoadFrom(A_BTE + 4);
Temp_ptr[31:0]  LoadFrom(A_BTE + 8);
IF Temp_ptr equal ptr_value Then
BND.LB  Temp_lb;
BND.UB  Temp_ub;
BNDLDX—Load Extended Bounds Using Address Translation
Vol. 2A 3-95
INSTRUCTION SET REFERENCE, A-L
ELSE
BND.LB  0;
BND.UB  0;
FI;
In 64-bit mode
A_BDE[63:0]  (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:20] «12 );1
A_BT[63:0]  LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS  A_BDE | 02H;
#BR;
FI;
A_BTE[63:0]  (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 );
Temp_lb[63:0]  LoadFrom(A_BTE);
Temp_ub[63:0]  LoadFrom(A_BTE + 8);
Temp_ptr[63:0]  LoadFrom(A_BTE + 16);
IF Temp_ptr equal ptr_value Then
BND.LB  Temp_lb;
BND.UB  Temp_ub;
ELSE
BND.LB  0;
BND.UB  0;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDLDX: Generated by compiler as needed.
Flags Affected
None
Protected Mode Exceptions
#BR
If the bound directory entry is invalid.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
If DS register contains a NULL segment selector.
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumerated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
3-96 Vol. 2A
BNDLDX—Load Extended Bounds Using Address Translation
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#BR
#UD
If the bound directory entry is invalid.
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#GP(0)
If the memory address (A_BDE or A_BTE) is in a non-canonical form.
#PF(fault code)
If a page fault occurs.
BNDLDX—Load Extended Bounds Using Address Translation
Vol. 2A 3-97
INSTRUCTION SET REFERENCE, A-L
BNDMK—Make Bounds
Opcode/
Instruction
Op/En
CPUID
Feature
Flag
MPX
Description
RM
64/32
bit Mode
Support
NE/V
F3 0F 1B /r
BNDMK bnd, m32
F3 0F 1B /r
BNDMK bnd, m64
RM
V/NE
MPX
Make lower and upper bounds from m64 and store them in bnd.
Make lower and upper bounds from m32 and store them in bnd.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
Description
Makes bounds from the second operand and stores the lower and upper bounds in the bound register bnd. The
second operand must be a memory operand. The content of the base register from the memory operand is stored
in the lower bound bnd.LB. The 1's complement of the effective address of m32/m64 is stored in the upper bound
b.UB. Computation of m32/m64 has identical behavior to LEA.
This instruction does not cause any memory access, and does not read or write any flags.
If the instruction did not specify base register, the lower bound will be zero. The reg-reg form of this instruction
retains legacy behavior (NOP).
RIP relative instruction in 64-bit will #UD.
Operation
BND.LB  SRCMEM.base;
IF 64-bit mode Then
BND.UB  NOT(LEA.64_bits(SRCMEM));
ELSE
BND.UB  Zero_Extend.64_bits(NOT(LEA.32_bits(SRCMEM)));
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDMKvoid * _bnd_set_ptr_bounds(const void * q, size_t size);
Flags Affected
None
Protected Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
Real-Address Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
3-98 Vol. 2A
BNDMK—Make Bounds
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0)
If the memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
Same exceptions as in protected mode.
BNDMK—Make Bounds
Vol. 2A 3-99
INSTRUCTION SET REFERENCE, A-L
BNDMOV—Move Bounds
Opcode/
Instruction
Op/En
RM
64/32
bit Mode
Support
NE/V
CPUID
Feature
Flag
MPX
66 0F 1A /r
BNDMOV bnd1, bnd2/m64
66 0F 1A /r
BNDMOV bnd1, bnd2/m128
66 0F 1B /r
BNDMOV bnd1/m64, bnd2
66 0F 1B /r
BNDMOV bnd1/m128, bnd2
RM
V/NE
MPX
MR
NE/V
MPX
MR
V/NE
MPX
Description
Move lower and upper bound from bnd2/m64 to bound register
bnd1.
Move lower and upper bound from bnd2/m128 to bound register
bnd1.
Move lower and upper bound from bnd2 to bnd1/m64.
Move lower and upper bound from bnd2 to bound register
bnd1/m128.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
MR
ModRM:r/m (w)
ModRM:reg (r)
NA
Description
BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the
destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction.
The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.
Upper Bound (UB)
BNDMOV to memory in 64-bit mode
Lower Bound (LB)
16
0
8
Upper Bound (UB)
16
BNDMOV to memory in 32-bit mode
Lower Bound (LB)
8
Byte offset
4
0
Byte offset
Figure 3-5. Memory Layout of BNDMOV to/from Memory
This instruction does not change flags.
Operation
BNDMOV register to register
DEST.LB  SRC.LB;
DEST.UB  SRC.UB;
3-100 Vol. 2A
BNDMOV—Move Bounds
INSTRUCTION SET REFERENCE, A-L
BNDMOV from memory
IF 64-bit mode THEN
DEST.LB  LOAD_QWORD(SRC);
DEST.UB  LOAD_QWORD(SRC+8);
ELSE
DEST.LB  LOAD_DWORD_ZERO_EXT(SRC);
DEST.UB  LOAD_DWORD_ZERO_EXT(SRC+4);
FI;
BNDMOV to memory
IF 64-bit mode THEN
DEST[63:0]  SRC.LB;
DEST[127:64]  SRC.UB;
ELSE
DEST[31:0]  SRC.LB;
DEST[63:32]  SRC.UB;
FI;
Intel C/C++ Compiler Intrinsic Equivalent
BNDMOV
void * _bnd_copy_ptr_bounds(const void *q, const void *r)
Flags Affected
None
Protected Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#SS(0)
#GP(0)
If the memory operand effective address is outside the SS segment limit.
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the destination operand points to a non-writable segment
If the DS, ES, FS, or GS segment register contains a NULL segment selector.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If the memory operand effective address is outside the SS segment limit.
BNDMOV—Move Bounds
Vol. 2A 3-101
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If the memory operand effective address is outside the SS segment limit.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used but the destination is not a memory operand.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#SS(0)
If the memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.
#PF(fault code)
If a page fault occurs.
3-102 Vol. 2A
BNDMOV—Move Bounds
INSTRUCTION SET REFERENCE, A-L
BNDSTX—Store Extended Bounds Using Address Translation
Opcode/
Instruction
Op/En
0F 1B /r
BNDSTX mib, bnd
MR
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
MPX
Description
Store the bounds in bnd and the pointer value in the index register of mib to a bound table entry (BTE) with address translation
using the base of mib.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
MR
SIB.base (r): Address of pointer
SIB.index(r)
ModRM:reg (r)
NA
Description
BNDSTX uses the linear address constructed from the displacement and base register of the SIB-addressing form
of the memory operand (mib) to perform address translation to store to a bound table entry. The bounds in the
source operand bnd are written to the lower and upper bounds in the BTE. The content of the index register of mib
is written to the pointer value field in the BTE.
This instruction does not cause memory access to the linear address of mib nor the effective address referenced by
the base, and does not read or write any flags.
Segment overrides apply to the linear address computation with the base of mib, and are used during address
translation to generate the address of the bound table entry. By default, the address of the BTE is assumed to be
linear address. There are no segmentation checks performed on the base of mib.
The base of mib will not be checked for canonical address violation as it does not access memory.
Any encoding of this instruction that does not specify base or index register will treat those registers as zero
(constant). The reg-reg form of this instruction will remain a NOP.
The scale field of the SIB byte has no effect on these instructions and is ignored.
The bound register may be partially updated on memory faults. The order in which memory operands are loaded is
implementation specific.
Operation
base  mib.SIB.base ? mib.SIB.base + Disp: 0;
ptr_value  mib.SIB.index ? mib.SIB.index : 0;
Outside 64-bit mode
A_BDE[31:0]  (Zero_extend32(base[31:12] « 2) + (BNDCFG[31:12] «12 );
A_BT[31:0]  LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS  A_BDE | 02H;
#BR;
FI;
A_DEST[31:0]  (Zero_extend32(base[11:2] « 4) + (A_BT[31:2] « 2 ); // address of Bound table entry
A_DEST[8][31:0]  ptr_value;
A_DEST[0][31:0]  BND.LB;
A_DEST[4][31:0]  BND.UB;
BNDSTX—Store Extended Bounds Using Address Translation
Vol. 2A 3-103
INSTRUCTION SET REFERENCE, A-L
In 64-bit mode
A_BDE[63:0]  (Zero_extend64(base[47+MAWA:20] « 3) + (BNDCFG[63:20] «12 );1
A_BT[63:0]  LoadFrom(A_BDE);
IF A_BT[0] equal 0 Then
BNDSTATUS  A_BDE | 02H;
#BR;
FI;
A_DEST[63:0]  (Zero_extend64(base[19:3] « 5) + (A_BT[63:3] « 3 ); // address of Bound table entry
A_DEST[16][63:0]  ptr_value;
A_DEST[0][63:0]  BND.LB;
A_DEST[8][63:0]  BND.UB;
Intel C/C++ Compiler Intrinsic Equivalent
BNDSTX: _bnd_store_ptr_bounds(const void **ptr_addr, const void *ptr_val);
Flags Affected
None
Protected Mode Exceptions
#BR
If the bound directory entry is invalid.
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 67H prefix is not used and CS.D=0.
If 67H prefix is used and CS.D=1.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
If DS register contains a NULL segment selector.
If the destination operand points to a non-writable segment
#PF(fault code)
If a page fault occurs.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.
If 16-bit addressing is used.
#GP(0)
If a destination effective address of the Bound Table entry is outside the DS segment limit.
#PF(fault code)
If a page fault occurs.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
1. If CPL < 3, the supervisor MAWA (MAWAS) is used; this value is 0. If CPL = 3, the user MAWA (MAWAU) is used; this value is enumerated in CPUID.(EAX=07H,ECX=0H):ECX.MAWAU[bits 21:17]. See Section 17.3.1 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
3-104 Vol. 2A
BNDSTX—Store Extended Bounds Using Address Translation
INSTRUCTION SET REFERENCE, A-L
64-Bit Mode Exceptions
#BR
#UD
If the bound directory entry is invalid.
If ModRM is RIP relative.
If the LOCK prefix is used.
If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.
#GP(0)
If the memory address (A_BDE or A_BTE) is in a non-canonical form.
If the destination operand points to a non-writable segment
#PF(fault code)
If a page fault occurs.
BNDSTX—Store Extended Bounds Using Address Translation
Vol. 2A 3-105
INSTRUCTION SET REFERENCE, A-L
BOUND—Check Array Index Against Bounds
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
62 /r
BOUND r16, m16&16
RM
Invalid
Valid
Check if r16 (array index) is within bounds
specified by m16&16.
62 /r
BOUND r32, m32&32
RM
Invalid
Valid
Check if r32 (array index) is within bounds
specified by m32&32.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
Description
BOUND determines if the first operand (array index) is within the bounds of an array specified the second operand
(bounds operand). The array index is a signed integer located in a register. The bounds operand is a memory location that contains a pair of signed doubleword-integers (when the operand-size attribute is 32) or a pair of signed
word-integers (when the operand-size attribute is 16). The first doubleword (or word) is the lower bound of the
array and the second doubleword (or word) is the upper bound of the array. The array index must be greater than
or equal to the lower bound and less than or equal to the upper bound plus the operand size in bytes. If the index
is not within bounds, a BOUND range exceeded exception (#BR) is signaled. When this exception is generated, the
saved return instruction pointer points to the BOUND instruction.
The bounds limit data structure (two words or doublewords containing the lower and upper limits of the array) is
usually placed just before the array itself, making the limits addressable via a constant offset from the beginning of
the array. Because the address of the array already will be present in a register, this practice avoids extra bus cycles
to obtain the effective address of the array bounds.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64bit Mode
THEN
#UD;
ELSE
IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)
(* Below lower bound or above upper bound *)
THEN #BR; FI;
FI;
Flags Affected
None.
Protected Mode Exceptions
#BR
If the bounds test fails.
#UD
If second operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-106 Vol. 2A
BOUND—Check Array Index Against Bounds
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#BR
#UD
If the bounds test fails.
If second operand is not a memory location.
If the LOCK prefix is used.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#BR
If the bounds test fails.
#UD
If second operand is not a memory location.
If the LOCK prefix is used.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If in 64-bit mode.
BOUND—Check Array Index Against Bounds
Vol. 2A 3-107
INSTRUCTION SET REFERENCE, A-L
BSF—Bit Scan Forward
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BC /r
BSF r16, r/m16
RM
Valid
Valid
Bit scan forward on r/m16.
0F BC /r
BSF r32, r/m32
RM
Valid
Valid
Bit scan forward on r/m32.
REX.W + 0F BC /r
BSF r64, r/m64
RM
Valid
N.E.
Bit scan forward on r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Searches the source operand (second operand) for the least significant set bit (1 bit). If a least significant 1 bit is
found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a
memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source
operand. If the content of the source operand is 0, the content of the destination operand is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
IF SRC = 0
THEN
ZF ← 1;
DEST is undefined;
ELSE
ZF ← 0;
temp ← 0;
WHILE Bit(SRC, temp) = 0
DO
temp ← temp + 1;
OD;
DEST ← temp;
FI;
Flags Affected
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags
are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-108 Vol. 2A
BSF—Bit Scan Forward
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
BSF—Bit Scan Forward
Vol. 2A 3-109
INSTRUCTION SET REFERENCE, A-L
BSR—Bit Scan Reverse
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BD /r
BSR r16, r/m16
RM
Valid
Valid
Bit scan reverse on r/m16.
0F BD /r
BSR r32, r/m32
RM
Valid
Valid
Bit scan reverse on r/m32.
REX.W + 0F BD /r
BSR r64, r/m64
RM
Valid
N.E.
Bit scan reverse on r/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Searches the source operand (second operand) for the most significant set bit (1 bit). If a most significant 1 bit is
found, its bit index is stored in the destination operand (first operand). The source operand can be a register or a
memory location; the destination operand is a register. The bit index is an unsigned offset from bit 0 of the source
operand. If the content source operand is 0, the content of the destination operand is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
IF SRC = 0
THEN
ZF ← 1;
DEST is undefined;
ELSE
ZF ← 0;
temp ← OperandSize – 1;
WHILE Bit(SRC, temp) = 0
DO
temp ← temp - 1;
OD;
DEST ← temp;
FI;
Flags Affected
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared. The CF, OF, SF, AF, and PF, flags
are undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-110 Vol. 2A
BSR—Bit Scan Reverse
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
BSR—Bit Scan Reverse
Vol. 2A 3-111
INSTRUCTION SET REFERENCE, A-L
BSWAP—Byte Swap
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F C8+rd
BSWAP r32
O
Valid*
Valid
Reverses the byte order of a 32-bit register.
REX.W + 0F C8+rd
BSWAP r64
O
Valid
N.E.
Reverses the byte order of a 64-bit register.
NOTES:
* See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
O
opcode + rd (r, w)
NA
NA
NA
Description
Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction is provided for converting littleendian values to big-endian format and vice versa. To swap bytes in a word value (16-bit register), use the XCHG
instruction. When the BSWAP instruction references a 16-bit register, the result is undefined.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
IA-32 Architecture Legacy Compatibility
The BSWAP instruction is not supported on IA-32 processors earlier than the Intel486™ processor family. For
compatibility with this instruction, software should include functionally equivalent code for execution on Intel
processors earlier than the Intel486 processor family.
Operation
TEMP ← DEST
IF 64-bit mode AND OperandSize = 64
THEN
DEST[7:0] ← TEMP[63:56];
DEST[15:8] ← TEMP[55:48];
DEST[23:16] ← TEMP[47:40];
DEST[31:24] ← TEMP[39:32];
DEST[39:32] ← TEMP[31:24];
DEST[47:40] ← TEMP[23:16];
DEST[55:48] ← TEMP[15:8];
DEST[63:56] ← TEMP[7:0];
ELSE
DEST[7:0] ← TEMP[31:24];
DEST[15:8] ← TEMP[23:16];
DEST[23:16] ← TEMP[15:8];
DEST[31:24] ← TEMP[7:0];
FI;
Flags Affected
None.
Exceptions (All Operating Modes)
#UD
3-112 Vol. 2A
If the LOCK prefix is used.
BSWAP—Byte Swap
INSTRUCTION SET REFERENCE, A-L
BT—Bit Test
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F A3 /r
BT r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag.
0F A3 /r
BT r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag.
REX.W + 0F A3 /r
BT r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag.
0F BA /4 ib
BT r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag.
0F BA /4 ib
BT r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag.
REX.W + 0F BA /4 ib
BT r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset (specified by the second operand) and stores the value of the bit in the CF flag. The bit base operand
can be a register or a memory location; the bit offset operand can be a register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode).
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit operands) of the immediate bit offset are stored in the immediate bit offset field, and the highorder bits are shifted and combined with the byte displacement in the addressing mode by the assembler. The
processor will ignore the high order bits if they are not zero.
When accessing a bit in memory, the processor may access 4 bytes starting from the memory address for a 32-bit
operand size, using by the following relationship:
Effective Address + (4 ∗ (BitOffset DIV 32))
Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship:
Effective Address + (2 ∗ (BitOffset DIV 16))
It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit
addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOV instructions to load from or store to these addresses, and use the register form of these instructions to manipulate the
data.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit operands. See the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
BT—Bit Test
Vol. 2A 3-113
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The CF flag contains the value of the selected bit. The ZF flag is unaffected. The OF, SF, AF, and PF flags are
undefined.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-114 Vol. 2A
BT—Bit Test
INSTRUCTION SET REFERENCE, A-L
BTC—Bit Test and Complement
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F BB /r
BTC r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and complement.
0F BB /r
BTC r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and complement.
REX.W + 0F BB /r
BTC r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and complement.
0F BA /7 ib
BTC r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and complement.
0F BA /7 ib
BTC r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and complement.
REX.W + 0F BA /7 ib
BTC r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and complement.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and complements the selected
bit in the bit string. The bit base operand can be a register or a memory location; the bit offset operand can be a
register or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset);
Flags Affected
The CF flag contains the value of the selected bit before it is complemented. The ZF flag is unaffected. The OF, SF,
AF, and PF flags are undefined.
BTC—Bit Test and Complement
Vol. 2A 3-115
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-116 Vol. 2A
BTC—Bit Test and Complement
INSTRUCTION SET REFERENCE, A-L
BTR—Bit Test and Reset
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F B3 /r
BTR r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and clear.
0F B3 /r
BTR r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and clear.
REX.W + 0F B3 /r
BTR r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and clear.
0F BA /6 ib
BTR r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and clear.
0F BA /6 ib
BTR r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and clear.
REX.W + 0F BA /6 ib
BTR r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and clear.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and clears the selected bit in the
bit string to 0. The bit base operand can be a register or a memory location; the bit offset operand can be a register
or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← 0;
Flags Affected
The CF flag contains the value of the selected bit before it is cleared. The ZF flag is unaffected. The OF, SF, AF, and
PF flags are undefined.
BTR—Bit Test and Reset
Vol. 2A 3-117
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-118 Vol. 2A
BTR—Bit Test and Reset
INSTRUCTION SET REFERENCE, A-L
BTS—Bit Test and Set
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F AB /r
BTS r/m16, r16
MR
Valid
Valid
Store selected bit in CF flag and set.
0F AB /r
BTS r/m32, r32
MR
Valid
Valid
Store selected bit in CF flag and set.
REX.W + 0F AB /r
BTS r/m64, r64
MR
Valid
N.E.
Store selected bit in CF flag and set.
0F BA /5 ib
BTS r/m16, imm8
MI
Valid
Valid
Store selected bit in CF flag and set.
0F BA /5 ib
BTS r/m32, imm8
MI
Valid
Valid
Store selected bit in CF flag and set.
REX.W + 0F BA /5 ib
BTS r/m64, imm8
MI
Valid
N.E.
Store selected bit in CF flag and set.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r, w)
imm8
NA
NA
Description
Selects the bit in a bit string (specified with the first operand, called the bit base) at the bit-position designated by
the bit offset operand (second operand), stores the value of the bit in the CF flag, and sets the selected bit in the
bit string to 1. The bit base operand can be a register or a memory location; the bit offset operand can be a register
or an immediate value:
•
If the bit base operand specifies a register, the instruction takes the modulo 16, 32, or 64 of the bit offset
operand (modulo size depends on the mode and register size; 64-bit operands are available only in 64-bit
mode). This allows any bit position to be selected.
•
If the bit base operand specifies a memory location, the operand represents the address of the byte in memory
that contains the bit base (bit 0 of the specified byte) of the bit string. The range of the bit position that can be
referenced by the offset operand depends on the operand size.
See also: Bit(BitBase, BitOffset) on page 3-11.
Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memory operand. See “BT—Bit Test” in this chapter for more information on
this addressing mechanism.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
Operation
CF ← Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) ← 1;
Flags Affected
The CF flag contains the value of the selected bit before it is set. The ZF flag is unaffected. The OF, SF, AF, and PF
flags are undefined.
BTS—Bit Test and Set
Vol. 2A 3-119
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the destination operand points to a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-120 Vol. 2A
BTS—Bit Test and Set
INSTRUCTION SET REFERENCE, A-L
BZHI — Zero High Bits Starting with Specified Bit Position
Opcode/Instruction
Op/
En
RMV
64/32
-bit
Mode
V/V
CPUID
Feature
Flag
BMI2
VEX.NDS.LZ.0F38.W0 F5 /r
BZHI r32a, r/m32, r32b
VEX.NDS.LZ.0F38.W1 F5 /r
BZHI r64a, r/m64, r64b
RMV
V/N.E.
BMI2
Description
Zero bits in r/m32 starting with the position in r32b, write result to
r32a.
Zero bits in r/m64 starting with the position in r64b, write result to
r64a.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMV
ModRM:reg (w)
ModRM:r/m (r)
VEX.vvvv (r)
NA
Description
BZHI copies the bits of the first source operand (the second operand) into the destination operand (the first
operand) and clears the higher bits in the destination according to the INDEX value specified by the second source
operand (the third operand). The INDEX is specified by bits 7:0 of the second source operand. The INDEX value is
saturated at the value of OperandSize -1. CF is set, if the number contained in the 8 low bits of the third operand
is greater than OperandSize -1.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
Operation
N ← SRC2[7:0]
DEST ← SRC1
IF (N < OperandSize)
DEST[OperandSize-1:N] ← 0
FI
IF (N > OperandSize - 1)
CF ← 1
ELSE
CF ← 0
FI
Flags Affected
ZF, CF and SF flags are updated based on the result. OF flag is cleared. AF and PF flags are undefined.
Intel C/C++ Compiler Intrinsic Equivalent
BZHI:
unsigned __int32 _bzhi_u32(unsigned __int32 src, unsigned __int32 index);
BZHI:
unsigned __int64 _bzhi_u64(unsigned __int64 src, unsigned __int32 index);
SIMD Floating-Point Exceptions
None
Other Exceptions
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”, Table 2-29; additionally
#UD
If VEX.W = 1.
BZHI — Zero High Bits Starting with Specified Bit Position
Vol. 2A 3-121
INSTRUCTION SET REFERENCE, A-L
CALL—Call Procedure
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
E8 cw
CALL rel16
M
N.S.
Valid
Call near, relative, displacement relative to next
instruction.
E8 cd
CALL rel32
M
Valid
Valid
Call near, relative, displacement relative to next
instruction. 32-bit displacement sign extended to
64-bits in 64-bit mode.
FF /2
CALL r/m16
M
N.E.
Valid
Call near, absolute indirect, address given in r/m16.
FF /2
CALL r/m32
M
N.E.
Valid
Call near, absolute indirect, address given in r/m32.
FF /2
CALL r/m64
M
Valid
N.E.
Call near, absolute indirect, address given in r/m64.
9A cd
CALL ptr16:16
D
Invalid
Valid
Call far, absolute, address given in operand.
9A cp
CALL ptr16:32
D
Invalid
Valid
Call far, absolute, address given in operand.
FF /3
CALL m16:16
M
Valid
Valid
Call far, absolute indirect address given in m16:16.
In 32-bit mode: if selector points to a gate, then RIP
= 32-bit zero extended displacement taken from
gate; else RIP = zero extended 16-bit offset from
far pointer referenced in the instruction.
FF /3
CALL m16:32
M
Valid
Valid
In 64-bit mode: If selector points to a gate, then RIP
= 64-bit displacement taken from gate; else RIP =
zero extended 32-bit offset from far pointer
referenced in the instruction.
REX.W + FF /3
CALL m16:64
M
Valid
N.E.
In 64-bit mode: If selector points to a gate, then RIP
= 64-bit displacement taken from gate; else RIP =
64-bit offset from far pointer referenced in the
instruction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
D
Offset
NA
NA
NA
M
ModRM:r/m (r)
NA
NA
NA
Description
Saves procedure linking information on the stack and branches to the called procedure specified using the target
operand. The target operand specifies the address of the first instruction in the called procedure. The operand can
be an immediate value, a general-purpose register, or a memory location.
This instruction can be used to execute four types of calls:
•
Near Call — A call to a procedure in the current code segment (the segment currently pointed to by the CS
register), sometimes referred to as an intra-segment call.
•
Far Call — A call to a procedure located in a different segment than the current code segment, sometimes
referred to as an inter-segment call.
•
Inter-privilege-level far call — A far call to a procedure in a segment at a different privilege level than that
of the currently executing program or procedure.
•
Task switch — A call to a procedure located in a different task.
The latter two call types (inter-privilege-level call and task switch) can only be executed in protected mode. See
“Calling Procedures Using Call and RET” in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for additional information on near, far, and inter-privilege-level calls. See Chapter 7,
“Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information on performing task switches with the CALL instruction.
3-122 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
Near Call. When executing a near call, the processor pushes the value of the EIP register (which contains the offset
of the instruction following the CALL instruction) on the stack (for use later as a return-instruction pointer). The
processor then branches to the address in the current code segment specified by the target operand. The target
operand specifies either an absolute offset in the code segment (an offset from the base of the code segment) or a
relative offset (a signed displacement relative to the current value of the instruction pointer in the EIP register; this
value points to the instruction following the CALL instruction). The CS register is not changed on near calls.
For a near call absolute, an absolute offset is specified indirectly in a general-purpose register or a memory location
(r/m16, r/m32, or r/m64). The operand-size attribute determines the size of the target operand (16, 32 or 64
bits). When in 64-bit mode, the operand size for near call (and all near branches) is forced to 64-bits. Absolute
offsets are loaded directly into the EIP(RIP) register. If the operand size attribute is 16, the upper two bytes of the
EIP register are cleared, resulting in a maximum instruction pointer size of 16 bits. When accessing an absolute
offset indirectly using the stack pointer [ESP] as the base register, the base value used is the value of the ESP
before the instruction executes.
A relative offset (rel16 or rel32) is generally specified as a label in assembly code. But at the machine code level, it
is encoded as a signed, 16- or 32-bit immediate value. This value is added to the value in the EIP(RIP) register. In
64-bit mode the relative offset is always a 32-bit immediate value which is sign extended to 64-bits before it is
added to the value in the RIP register for the target calculation. As with absolute offsets, the operand-size attribute
determines the size of the target operand (16, 32, or 64 bits). In 64-bit mode the target operand will always be 64bits because the operand size is forced to 64-bits for near branches.
Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in real- address or virtual-8086 mode, the
processor pushes the current value of both the CS and EIP registers on the stack for use as a return-instruction
pointer. The processor then performs a “far branch” to the code segment and offset specified with the target
operand for the called procedure. The target operand specifies an absolute far address either directly with a pointer
(ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). With the pointer method, the
segment and offset of the called procedure is encoded in the instruction using a 4-byte (16-bit operand size) or 6byte (32-bit operand size) far address immediate. With the indirect method, the target operand specifies a memory
location that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size) far address. The operand-size
attribute determines the size of the offset (16 or 32 bits) in the far address. The far address is loaded directly into
the CS and EIP registers. If the operand-size attribute is 16, the upper two bytes of the EIP register are cleared.
Far Calls in Protected Mode. When the processor is operating in protected mode, the CALL instruction can be used to
perform the following types of far calls:
•
•
•
Far call to the same privilege level
Far call to a different privilege level (inter-privilege level call)
Task switch (far call to another task)
In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access
rights determine the type of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in protected mode is very similar
to one carried out in real-address or virtual-8086 mode. The target operand specifies an absolute far address either
directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The
operand- size attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment
selector and its descriptor are loaded into CS register; the offset from the instruction is loaded into the EIP register.
A call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the same
privilege level. Using this mechanism provides an extra level of indirection and is the preferred method of making
calls between 16-bit and 32-bit code segments.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a call gate. The segment selector specified by the target operand identifies the call gate. The target
operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly
with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code
segment and the new instruction pointer (offset) from the call gate descriptor. (The offset from the target operand
is ignored when a call gate is used.)
CALL—Call Procedure
Vol. 2A 3-123
INSTRUCTION SET REFERENCE, A-L
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to
the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a
segment at the same privilege level, no stack switch occurs.) On the new stack, the processor pushes the segment
selector and stack pointer for the calling procedure’s stack, an optional set of parameters from the calling procedures stack, and the segment selector and instruction pointer for the calling procedure’s code segment. (A value in
the call gate descriptor determines how many parameters to copy to the new stack.) Finally, the processor
branches to the address of the procedure being called within the new code segment.
Executing a task switch with the CALL instruction is similar to executing a call through a call gate. The target
operand specifies the segment selector of the task gate for the new task activated by the switch (the offset in the
target operand is ignored). The task gate in turn points to the TSS for the new task, which contains the segment
selectors for the task’s code and stack segments. Note that the TSS also contains the EIP value for the next instruction that was to be executed before the calling task was suspended. This instruction pointer value is loaded into the
EIP register to re-start the calling task.
The CALL instruction can also specify the segment selector of the TSS directly, which eliminates the indirection of
the task gate. See Chapter 7, “Task Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A, for information on the mechanics of a task switch.
When you execute at task switch with a CALL instruction, the nested task flag (NT) is set in the EFLAGS register and
the new TSS’s previous task link field is loaded with the old task’s TSS selector. Code is expected to suspend this
nested task by executing an IRET instruction which, because the NT flag is set, automatically uses the previous
task link to return to the calling task. (See “Task Linking” in Chapter 7 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A, for information on nested tasks.) Switching tasks with the CALL instruction differs in this regard from JMP instruction. JMP does not set the NT flag and therefore does not expect an IRET
instruction to suspend the task.
Mixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit code segments, use a call gate. If
the far call is from a 32-bit code segment to a 16-bit code segment, the call should be made from the first 64
KBytes of the 32-bit code segment. This is because the operand-size attribute of the instruction is set to 16, so only
a 16-bit return address offset can be saved. Also, the call should be made using a 16-bit call gate so that 16-bit
values can be pushed on the stack. See Chapter 21, “Mixing 16-Bit and 32-Bit Code,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3B, for more information.
Far Calls in Compatibility Mode. When the processor is operating in compatibility mode, the CALL instruction can be
used to perform the following types of far calls:
•
•
•
Far call to the same privilege level, remaining in compatibility mode
Far call to the same privilege level, transitioning to 64-bit mode
Far call to a different privilege level (inter-privilege level call), transitioning to 64-bit mode
Note that a CALL instruction can not be used to cause a task switch in compatibility mode since task switches are
not supported in IA-32e mode.
In compatibility mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine
the type of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in compatibility mode is very
similar to one carried out in protected mode. The target operand specifies an absolute far address either directly
with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size
attribute determines the size of the offset (16 or 32 bits) in the far address. The new code segment selector and its
descriptor are loaded into CS register and the offset from the instruction is loaded into the EIP register. The difference is that 64-bit mode may be entered. This specified by the L bit in the new code segment descriptor.
Note that a 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code
segment at the same privilege level. However, using this mechanism requires that the target code segment
descriptor have the L bit set, causing an entry to 64-bit mode.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target
3-124 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
operand can specify the call gate segment selector either directly with a pointer (ptr16:16 or ptr16:32) or indirectly
with a memory location (m16:16 or m16:32). The processor obtains the segment selector for the new code
segment and the new instruction pointer (offset) from the 16-byte call gate descriptor. (The offset from the target
operand is ignored when a call gate is used.)
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the stack switch. (Note that when using
a call gate to perform a far call to a segment at the same privilege level, an implicit stack switch occurs as a result
of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use a segment base of 0x0,
the limit is ignored, and the default stack size is 64-bits. The full value of RSP is used for the offset, of which the
upper 32-bits are undefined.) On the new stack, the processor pushes the segment selector and stack pointer for
the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code
segment. (Parameter copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the
procedure being called within the new code segment.
Near/(Far) Calls in 64-bit Mode. When the processor is operating in 64-bit mode, the CALL instruction can be used to
perform the following types of far calls:
•
•
•
Far call to the same privilege level, transitioning to compatibility mode
Far call to the same privilege level, remaining in 64-bit mode
Far call to a different privilege level (inter-privilege level call), remaining in 64-bit mode
Note that in this mode the CALL instruction can not be used to cause a task switch in 64-bit mode since task
switches are not supported in IA-32e mode.
In 64-bit mode, the processor always uses the segment selector part of the far address to access the corresponding
descriptor in the GDT or LDT. The descriptor type (code segment, call gate) and access rights determine the type
of call operation to be performed.
If the selected descriptor is for a code segment, a far call to a code segment at the same privilege level is
performed. (If the selected code segment is at a different privilege level and the code segment is non-conforming,
a general-protection exception is generated.) A far call to the same privilege level in 64-bit mode is very similar to
one carried out in compatibility mode. The target operand specifies an absolute far address indirectly with a
memory location (m16:16, m16:32 or m16:64). The form of CALL with a direct specification of absolute far
address is not defined in 64-bit mode. The operand-size attribute determines the size of the offset (16, 32, or 64
bits) in the far address. The new code segment selector and its descriptor are loaded into the CS register; the offset
from the instruction is loaded into the EIP register. The new code segment may specify entry either into compatibility or 64-bit mode, based on the L bit value.
A 64-bit call gate (described in the next paragraph) can also be used to perform a far call to a code segment at the
same privilege level. However, using this mechanism requires that the target code segment descriptor have the L
bit set.
When executing an inter-privilege-level far call, the code segment for the procedure being called must be accessed
through a 64-bit call gate. The segment selector specified by the target operand identifies the call gate. The target
operand can only specify the call gate segment selector indirectly with a memory location (m16:16, m16:32 or
m16:64). The processor obtains the segment selector for the new code segment and the new instruction pointer
(offset) from the 16-byte call gate descriptor. (The offset from the target operand is ignored when a call gate is
used.)
On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The
segment selector for the new stack segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the stack switch.
Note that when using a call gate to perform a far call to a segment at the same privilege level, an implicit stack
switch occurs as a result of entering 64-bit mode. The SS selector is unchanged, but stack segment accesses use
a segment base of 0x0, the limit is ignored, and the default stack size is 64-bits. (The full value of RSP is used for
the offset.) On the new stack, the processor pushes the segment selector and stack pointer for the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code segment. (Parameter
copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the procedure being called
within the new code segment.
CALL—Call Procedure
Vol. 2A 3-125
INSTRUCTION SET REFERENCE, A-L
Operation
IF near call
THEN IF near relative call
THEN
IF OperandSize = 64
THEN
tempDEST ← SignExtend(DEST); (* DEST is rel32 *)
tempRIP ← RIP + tempDEST;
IF stack not large enough for a 8-byte return address
THEN #SS(0); FI;
Push(RIP);
RIP ← tempRIP;
FI;
IF OperandSize = 32
THEN
tempEIP ← EIP + DEST; (* DEST is rel32 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(EIP);
EIP ← tempEIP;
FI;
IF OperandSize = 16
THEN
tempEIP ← (EIP + DEST) AND 0000FFFFH; (* DEST is rel16 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 2-byte return address
THEN #SS(0); FI;
Push(IP);
EIP ← tempEIP;
FI;
ELSE (* Near absolute call *)
IF OperandSize = 64
THEN
tempRIP ← DEST; (* DEST is r/m64 *)
IF stack not large enough for a 8-byte return address
THEN #SS(0); FI;
Push(RIP);
RIP ← tempRIP;
FI;
IF OperandSize = 32
THEN
tempEIP ← DEST; (* DEST is r/m32 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(EIP);
EIP ← tempEIP;
FI;
IF OperandSize = 16
THEN
tempEIP ← DEST AND 0000FFFFH; (* DEST is r/m16 *)
IF tempEIP is not within code segment limit THEN #GP(0); FI;
3-126 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
FI;
IF stack not large enough for a 2-byte return address
THEN #SS(0); FI;
Push(IP);
EIP ← tempEIP;
FI;rel/abs
FI; near
IF far call and (PE = 0 or (PE = 1 and VM = 1)) (* Real-address or virtual-8086 mode *)
THEN
IF OperandSize = 32
THEN
IF stack not large enough for a 6-byte return address
THEN #SS(0); FI;
IF DEST[31:16] is not zero THEN #GP(0); FI;
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST[47:32]; (* DEST is ptr16:32 or [m16:32] *)
EIP ← DEST[31:0]; (* DEST is ptr16:32 or [m16:32] *)
ELSE (* OperandSize = 16 *)
IF stack not large enough for a 4-byte return address
THEN #SS(0); FI;
Push(CS);
Push(IP);
CS ← DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)
EIP ← DEST[15:0]; (* DEST is ptr16:16 or [m16:16]; clear upper 16 bits *)
FI;
FI;
IF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*)
THEN
IF segment selector in target operand NULL
THEN #GP(0); FI;
IF segment selector index not within descriptor table limits
THEN #GP(new code segment selector); FI;
Read type and access rights of selected segment descriptor;
IF IA32_EFER.LMA = 0
THEN
IF segment type is not a conforming or nonconforming code segment, call
gate, task gate, or TSS
THEN #GP(segment selector); FI;
ELSE
IF segment type is not a conforming or nonconforming code segment or
64-bit call gate,
THEN #GP(segment selector); FI;
FI;
Depending on type and access rights:
GO TO CONFORMING-CODE-SEGMENT;
GO TO NONCONFORMING-CODE-SEGMENT;
GO TO CALL-GATE;
GO TO TASK-GATE;
GO TO TASK-STATE-SEGMENT;
FI;
CALL—Call Procedure
Vol. 2A 3-127
INSTRUCTION SET REFERENCE, A-L
CONFORMING-CODE-SEGMENT:
IF L bit = 1 and D bit = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF DPL > CPL
THEN #GP(new code segment selector); FI;
IF segment not present
THEN #NP(new code segment selector); FI;
IF stack not large enough for return address
THEN #SS(0); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN
tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
segment limit)
THEN #GP(0); FI;
IF tempEIP is non-canonical
THEN #GP(0); FI;
IF OperandSize = 32
THEN
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE
IF OperandSize = 16
THEN
Push(CS);
Push(IP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE (* OperandSize = 64 *)
Push(CS); (* Padded with 48 high-order bits *)
Push(RIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
RIP ← tempEIP;
FI;
FI;
END;
NONCONFORMING-CODE-SEGMENT:
IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1
THEN GP(new code segment selector); FI;
IF (RPL > CPL) or (DPL ≠ CPL)
THEN #GP(new code segment selector); FI;
IF segment not present
THEN #NP(new code segment selector); FI;
IF stack not large enough for return address
3-128 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
THEN #SS(0); FI;
tempEIP ← DEST(Offset);
IF OperandSize = 16
THEN tempEIP ← tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
segment limit)
THEN #GP(0); FI;
IF tempEIP is non-canonical
THEN #GP(0); FI;
IF OperandSize = 32
THEN
Push(CS); (* Padded with 16 high-order bits *)
Push(EIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE
IF OperandSize = 16
THEN
Push(CS);
Push(IP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
EIP ← tempEIP;
ELSE (* OperandSize = 64 *)
Push(CS); (* Padded with 48 high-order bits *)
Push(RIP);
CS ← DEST(CodeSegmentSelector);
(* Segment descriptor information also loaded *)
CS(RPL) ← CPL;
RIP ← tempEIP;
FI;
FI;
END;
CALL-GATE:
IF call gate (DPL < CPL) or (RPL > DPL)
THEN #GP(call-gate selector); FI;
IF call gate not present
THEN #NP(call-gate selector); FI;
IF call-gate code-segment selector is NULL
THEN #GP(0); FI;
IF call-gate code-segment selector index is outside descriptor table limits
THEN #GP(call-gate code-segment selector); FI;
Read call-gate code-segment descriptor;
IF call-gate code-segment descriptor does not indicate a code segment
or call-gate code-segment descriptor DPL > CPL
THEN #GP(call-gate code-segment selector); FI;
IF IA32_EFER.LMA = 1 AND (call-gate code-segment descriptor is
not a 64-bit code segment or call-gate code-segment descriptor has both L-bit and D-bit set)
THEN #GP(call-gate code-segment selector); FI;
IF call-gate code segment not present
CALL—Call Procedure
Vol. 2A 3-129
INSTRUCTION SET REFERENCE, A-L
THEN #NP(call-gate code-segment selector); FI;
IF call-gate code segment is non-conforming and DPL < CPL
THEN go to MORE-PRIVILEGE;
ELSE go to SAME-PRIVILEGE;
FI;
END;
MORE-PRIVILEGE:
IF current TSS is 32-bit
THEN
TSSstackAddress ← (new code-segment DPL ∗ 8) + 4;
IF (TSSstackAddress + 5) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 4);
NewESP ← 4 bytes loaded from (TSS base + TSSstackAddress);
ELSE
IF current TSS is 16-bit
THEN
TSSstackAddress ← (new code-segment DPL ∗ 4) + 2
IF (TSSstackAddress + 3) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← 2 bytes loaded from (TSS base + TSSstackAddress + 2);
NewESP ← 2 bytes loaded from (TSS base + TSSstackAddress);
ELSE (* current TSS is 64-bit *)
TSSstackAddress ← (new code-segment DPL ∗ 8) + 4;
IF (TSSstackAddress + 7) > current TSS limit
THEN #TS(current TSS selector); FI;
NewSS ← new code-segment DPL; (* NULL selector with RPL = new CPL *)
NewRSP ← 8 bytes loaded from (current TSS base + TSSstackAddress);
FI;
FI;
IF IA32_EFER.LMA = 0 and NewSS is NULL
THEN #TS(NewSS); FI;
Read new code-segment descriptor and new stack-segment descriptor;
IF IA32_EFER.LMA = 0 and (NewSS RPL ≠ new code-segment DPL
or new stack-segment DPL ≠ new code-segment DPL or new stack segment is not a
writable data segment)
THEN #TS(NewSS); FI
IF IA32_EFER.LMA = 0 and new stack segment not present
THEN #SS(NewSS); FI;
IF CallGateSize = 32
THEN
IF new stack does not have room for parameters plus 16 bytes
THEN #SS(NewSS); FI;
IF CallGate(InstructionPointer) not within new code-segment limit
THEN #GP(0); FI;
SS ← newSS; (* Segment descriptor information also loaded *)
ESP ← newESP;
CS:EIP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
temp ← parameter count from call gate, masked to 5 bits;
Push(parameters from calling procedure’s stack, temp)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
3-130 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
ELSE
IF CallGateSize = 16
THEN
IF new stack does not have room for parameters plus 8 bytes
THEN #SS(NewSS); FI;
IF (CallGate(InstructionPointer) AND FFFFH) not in new code-segment limit
THEN #GP(0); FI;
SS ← newSS; (* Segment descriptor information also loaded *)
ESP ← newESP;
CS:IP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
temp ← parameter count from call gate, masked to 5 bits;
Push(parameters from calling procedure’s stack, temp)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE (* CallGateSize = 64 *)
IF pushing 32 bytes on the stack would use a non-canonical address
THEN #SS(NewSS); FI;
IF (CallGate(InstructionPointer) is non-canonical)
THEN #GP(0); FI;
SS ← NewSS; (* NewSS is NULL)
RSP ← NewESP;
CS:IP ← CallGate(CS:InstructionPointer);
(* Segment descriptor information also loaded *)
Push(oldSS:oldESP); (* From calling procedure *)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
FI;
FI;
CPL ← CodeSegment(DPL)
CS(RPL) ← CPL
END;
SAME-PRIVILEGE:
IF CallGateSize = 32
THEN
IF stack does not have room for 8 bytes
THEN #SS(0); FI;
IF CallGate(InstructionPointer) not within code segment limit
THEN #GP(0); FI;
CS:EIP ← CallGate(CS:EIP) (* Segment descriptor information also loaded *)
Push(oldCS:oldEIP); (* Return address to calling procedure *)
ELSE
If CallGateSize = 16
THEN
IF stack does not have room for 4 bytes
THEN #SS(0); FI;
IF CallGate(InstructionPointer) not within code segment limit
THEN #GP(0); FI;
CS:IP ← CallGate(CS:instruction pointer);
(* Segment descriptor information also loaded *)
Push(oldCS:oldIP); (* Return address to calling procedure *)
ELSE (* CallGateSize = 64)
IF pushing 16 bytes on the stack touches non-canonical addresses
THEN #SS(0); FI;
CALL—Call Procedure
Vol. 2A 3-131
INSTRUCTION SET REFERENCE, A-L
IF RIP non-canonical
THEN #GP(0); FI;
CS:IP ← CallGate(CS:instruction pointer);
(* Segment descriptor information also loaded *)
Push(oldCS:oldIP); (* Return address to calling procedure *)
FI;
FI;
CS(RPL) ← CPL
END;
TASK-GATE:
IF task gate DPL < CPL or RPL
THEN #GP(task gate selector); FI;
IF task gate not present
THEN #NP(task gate selector); FI;
Read the TSS segment selector in the task-gate descriptor;
IF TSS segment selector local/global bit is set to local
or index not within GDT limits
THEN #GP(TSS selector); FI;
Access TSS descriptor in GDT;
IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)
THEN #GP(TSS selector); FI;
IF TSS not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
TASK-STATE-SEGMENT:
IF TSS DPL < CPL or RPL
or TSS descriptor indicates TSS not available
THEN #GP(TSS selector); FI;
IF TSS is not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
Flags Affected
All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur.
3-132 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
If the target offset in destination operand is beyond the new code segment limit.
If the segment selector in the destination operand is NULL.
If the code segment selector in the gate is NULL.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
selector.
#GP(selector)
If a code segment or gate or TSS selector index is outside descriptor table limits.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, call gate, task gate, or task
state segment.
If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than
the RPL of the call-gate, task-gate, or TSS’s segment selector.
If the segment descriptor for a segment selector from a call gate does not indicate it is a code
segment.
If the segment selector from a call gate is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a call gate is greater than the CPL.
If the segment selector for a TSS has its local/global bit set for local.
If a TSS segment descriptor specifies that the TSS is busy or not available.
#SS(0)
If pushing the return address, parameters, or stack segment pointer onto the stack exceeds
the bounds of the stack segment, when no stack switch occurs.
If a memory operand effective address is outside the SS segment limit.
#SS(selector)
If pushing the return address, parameters, or stack segment pointer onto the stack exceeds
the bounds of the stack segment, when a stack switch occurs.
If the SS register is being loaded as part of a stack switch and the segment pointed to is
marked not present.
If stack segment does not have room for the return address, parameters, or stack segment
pointer, when stack switch occurs.
#NP(selector)
If a code segment, data segment, stack segment, call gate, task gate, or TSS is not present.
#TS(selector)
If the new stack segment selector and ESP are beyond the end of the TSS.
If the new stack segment selector is NULL.
If the RPL of the new stack segment selector in the TSS is not equal to the DPL of the code
segment being accessed.
If DPL of the stack segment descriptor for the new stack segment is not equal to the DPL of the
code segment descriptor.
If the new stack segment is not a writable data segment.
If segment-selector index for stack segment is outside descriptor table limits.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the target offset is beyond the code segment limit.
#UD
CALL—Call Procedure
If the LOCK prefix is used.
Vol. 2A 3-133
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code)
If a page fault occurs.
If the target offset is beyond the code segment limit.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
#GP(selector)
If a memory address accessed by the selector is in non-canonical space.
#GP(0)
If the target offset in the destination operand is non-canonical.
64-Bit Mode Exceptions
#GP(0)
If a memory address is non-canonical.
If target offset in destination operand is non-canonical.
If the segment selector in the destination operand is NULL.
If the code segment selector in the 64-bit gate is NULL.
#GP(selector)
If code segment or 64-bit call gate is outside descriptor table limits.
If code segment or 64-bit call gate overlaps non-canonical space.
If the segment descriptor pointed to by the segment selector in the destination operand is not
for a conforming-code segment, nonconforming-code segment, or 64-bit call gate.
If the segment descriptor pointed to by the segment selector in the destination operand is a
code segment and has both the D-bit and the L- bit set.
If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the
segment’s segment selector is greater than the CPL.
If the DPL for a conforming-code segment is greater than the CPL.
If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
If the upper type field of a 64-bit call gate is not 0x0.
If the segment selector from a 64-bit call gate is beyond the descriptor table limits.
If the DPL for a code-segment obtained from a 64-bit call gate is greater than the CPL.
If the code segment descriptor pointed to by the selector in the 64-bit gate doesn't have the Lbit set and the D-bit clear.
If the segment descriptor for a segment selector from the 64-bit call gate does not indicate it
is a code segment.
#SS(0)
If pushing the return offset or CS selector onto the stack exceeds the bounds of the stack
segment when no stack switch occurs.
If a memory operand effective address is outside the SS segment limit.
If the stack address is in a non-canonical form.
#SS(selector)
If pushing the old values of SS selector, stack pointer, EFLAGS, CS selector, offset, or error
code onto the stack violates the canonical boundary when a stack switch occurs.
#NP(selector)
If a code segment or 64-bit call gate is not present.
#TS(selector)
If the load of the new RSP exceeds the limit of the TSS.
#UD
(64-bit mode only) If a far call is direct to an absolute address in memory.
If the LOCK prefix is used.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
3-134 Vol. 2A
CALL—Call Procedure
INSTRUCTION SET REFERENCE, A-L
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to
Quadword
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
98
CBW
NP
Valid
Valid
AX ← sign-extend of AL.
98
CWDE
NP
Valid
Valid
EAX ← sign-extend of AX.
REX.W + 98
CDQE
NP
Valid
N.E.
RAX ← sign-extend of EAX.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Double the size of the source operand by means of sign extension. The CBW (convert byte to word) instruction
copies the sign (bit 7) in the source operand into every bit in the AH register. The CWDE (convert word to doubleword) instruction copies the sign (bit 15) of the word in the AX register into the high 16 bits of the EAX register.
CBW and CWDE reference the same opcode. The CBW instruction is intended for use when the operand-size attribute is 16; CWDE is intended for use when the operand-size attribute is 32. Some assemblers may force the
operand size. Others may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of the
operand-size attribute to determine the size of values to be converted.
In 64-bit mode, the default operation size is the size of the destination register. Use of the REX.W prefix promotes
this instruction (CDQE when promoted) to operate on 64-bit operands. In which case, CDQE copies the sign (bit
31) of the doubleword in the EAX register into the high 32 bits of RAX.
Operation
IF OperandSize = 16 (* Instruction = CBW *)
THEN
AX ← SignExtend(AL);
ELSE IF (OperandSize = 32, Instruction = CWDE)
EAX ← SignExtend(AX); FI;
ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)
RAX ← SignExtend(EAX);
FI;
Flags Affected
None.
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword
Vol. 2A 3-135
INSTRUCTION SET REFERENCE, A-L
CLAC—Clear AC Flag in EFLAGS Register
Opcode/
Instruction
Op /
En
64/32 bit
Mode
Support
CPUID
Feature
Flag
Description
0F 01 CA
NP
V/V
SMAP
Clear the AC flag in the EFLAGS register.
CLAC
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the AC flag bit in EFLAGS register. This disables any alignment checking of user-mode data accesses. If the
SMAP bit is set in the CR4 register, this disallows explicit supervisor-mode data accesses to user-mode pages.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute CLAC when
CPL > 0 cause #UD.
Operation
EFLAGS.AC ← 0;
Flags Affected
AC cleared. Other flags are unaffected.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
Virtual-8086 Mode Exceptions
#UD
The CLAC instruction is not recognized in virtual-8086 mode.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If the CPL > 0.
If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.
3-136 Vol. 2A
CLAC—Clear AC Flag in EFLAGS Register
INSTRUCTION SET REFERENCE, A-L
CLC—Clear Carry Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
F8
CLC
NP
Valid
Valid
Clear CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the CF flag in the EFLAGS register. Operation is the same in all modes.
Operation
CF ← 0;
Flags Affected
The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
CLC—Clear Carry Flag
If the LOCK prefix is used.
Vol. 2A 3-137
INSTRUCTION SET REFERENCE, A-L
CLD—Clear Direction Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
FC
CLD
NP
Valid
Valid
Clear DF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in all modes.
Operation
DF ← 0;
Flags Affected
The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
3-138 Vol. 2A
If the LOCK prefix is used.
CLD—Clear Direction Flag
INSTRUCTION SET REFERENCE, A-L
CLFLUSH—Flush Cache Line
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F AE /7
CLFLUSH m8
M
Valid
Valid
Flushes cache line containing m8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the
linear address specified with the memory operand. If that cache line contains modified data at any level of the
cache hierarchy, that data is written back to memory. The source operand is a byte memory location.
The availability of CLFLUSH is indicated by the presence of the CPUID feature flag CLFSH
(CPUID.01H:EDX[bit 19]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8
through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions
assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh
instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative
fetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with
respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references
the cache line).
Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked
read-modify-write instructions, fence instructions, and executions of CLFLUSHOPT to the same cache line.1 They
are not ordered with respect to executions of CLFLUSHOPT to different cache lines.
The CLFLUSH instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load (and in addition, a CLFLUSH instruction is allowed to flush a linear address in an executeonly segment). Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSH instruction may always cause transactional abort with Transactional
Synchronization Extensions (TSX). The CLFLUSH instruction is not expected to be commonly used inside typical
transactional regions. However, programmers must not rely on CLFLUSH instruction to force a transactional abort,
since whether they cause transactional abort is implementation dependent.
The CLFLUSH instruction was introduced with the SSE2 extensions; however, because it has its own CPUID feature
flag, it can be implemented in IA-32 processors that do not include the SSE2 extensions. Also, detecting the presence of the SSE2 extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is implemented in the processor.
CLFLUSH operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line(SRC);
Intel C/C++ Compiler Intrinsic Equivalents
CLFLUSH:
void _mm_clflush(void const *p)
1. Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction.
All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above.
CLFLUSH—Flush Cache Line
Vol. 2A 3-139
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Real-Address Mode Exceptions
#GP
#UD
If any part of the operand lies outside the effective address space from 0 to FFFFH.
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If CPUID.01H:EDX.CLFSH[bit 19] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
3-140 Vol. 2A
CLFLUSH—Flush Cache Line
INSTRUCTION SET REFERENCE, A-L
CLFLUSHOPT—Flush Cache Line Optimized
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
66 0F AE /7
CLFLUSHOPT m8
M
Valid
Valid
Flushes cache line containing m8.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Invalidates from every level of the cache hierarchy in the cache coherence domain the cache line that contains the
linear address specified with the memory operand. If that cache line contains modified data at any level of the
cache hierarchy, that data is written back to memory. The source operand is a byte memory location.
The availability of CLFLUSHOPT is indicated by the presence of the CPUID feature flag CLFLUSHOPT
(CPUID.(EAX=7,ECX=0):EBX[bit 23]). The aligned cache line size affected is also indicated with the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions
assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types). PREFETCHh
instructions can be used to provide the processor with hints for this speculative behavior. Because this speculative
fetching can occur at any time and is not tied to instruction execution, the CLFLUSH instruction is not ordered with
respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references
the cache line).
Executions of the CLFLUSHOPT instruction are ordered with respect to fence instructions and to locked readmodify-write instructions; they are also ordered with respect to the following accesses to the cache line being
invalidated: writes, executions of CLFLUSH, and executions of CLFLUSHOPT. They are not ordered with respect to
writes, executions of CLFLUSH, or executions of CLFLUSHOPT that access other cache lines; to enforce ordering
with such an operation, software can insert an SFENCE instruction between CFLUSHOPT and that operation.
The CLFLUSHOPT instruction can be used at all privilege levels and is subject to all permission checking and faults
associated with a byte load (and in addition, a CLFLUSHOPT instruction is allowed to flush a linear address in an
execute-only segment). Like a load, the CLFLUSHOPT instruction sets the A bit but not the D bit in the page tables.
In some implementations, the CLFLUSHOPT instruction may always cause transactional abort with Transactional
Synchronization Extensions (TSX). The CLFLUSHOPT instruction is not expected to be commonly used inside
typical transactional regions. However, programmers must not rely on CLFLUSHOPT instruction to force a transactional abort, since whether they cause transactional abort is implementation dependent.
CLFLUSHOPT operation is the same in non-64-bit modes and 64-bit mode.
Operation
Flush_Cache_Line_Optimized(SRC);
Intel C/C++ Compiler Intrinsic Equivalents
CLFLUSHOPT:void _mm_clflushopt(void const *p)
CLFLUSHOPT—Flush Cache Line Optimized
Vol. 2A 3-141
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Real-Address Mode Exceptions
#GP
If any part of the operand lies outside the effective address space from 0 to FFFFH.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
#UD
If CPUID.(EAX=7,ECX=0):EBX.CLFLUSHOPT[bit 23] = 0.
If the LOCK prefix is used.
If an instruction prefix F2H or F3H is used.
3-142 Vol. 2A
CLFLUSHOPT—Flush Cache Line Optimized
INSTRUCTION SET REFERENCE, A-L
CLI — Clear Interrupt Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
FA
CLI
NP
Valid
Valid
Clear interrupt flag; interrupts disabled when
interrupt flag cleared.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags
are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts. The IF flag and the
CLI and STI instruction have no affect on the generation of exceptions and NMI interrupts.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the
EFLAGS register, leaving IF unaffected. Table 3-7 indicates the action of the CLI instruction depending on the
processor operating mode and the CPL/IOPL of the running program or procedure.
Operation is the same in all modes.
Table 3-7. Decision Table for CLI Results
PE
VM
IOPL
CPL
PVI
VIP
VME
CLI Result
0
X
X
X
X
X
X
IF = 0
1
0
≥ CPL
X
X
X
X
IF = 0
1
0
< CPL
3
1
X
X
VIF = 0
1
0
< CPL
<3
X
X
X
GP Fault
1
0
< CPL
X
0
X
X
GP Fault
1
1
3
X
X
X
X
IF = 0
1
1
<3
X
X
X
1
VIF = 0
1
1
<3
X
X
X
0
GP Fault
NOTES:
* X = This setting has no impact.
Operation
IF PE = 0
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF VM = 0;
THEN
IF IOPL ≥ CPL
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))
THEN
VIF ← 0; (* Reset Virtual Interrupt Flag *)
ELSE
#GP(0);
CLI — Clear Interrupt Flag
Vol. 2A 3-143
INSTRUCTION SET REFERENCE, A-L
FI;
FI;
ELSE (* VM = 1 *)
IF IOPL = 3
THEN
IF ← 0; (* Reset Interrupt Flag *)
ELSE
IF (IOPL < 3) AND (VME = 1)
THEN
VIF ← 0; (* Reset Virtual Interrupt Flag *)
ELSE
#GP(0);
FI;
FI;
FI;
FI;
Flags Affected
If protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equal to or less than the IOPL; otherwise, it is not affected. Other flags are unaffected.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; CLI clears the VIF flag in the
EFLAGS register, leaving IF unaffected. Other flags are unaffected.
Protected Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD
If the LOCK prefix is used.
3-144 Vol. 2A
CLI — Clear Interrupt Flag
INSTRUCTION SET REFERENCE, A-L
CLTS—Clear Task-Switched Flag in CR0
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
0F 06
CLTS
NP
Valid
Valid
Clears TS flag in CR0.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system
procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in realaddress mode to allow initialization for protected mode.
The processor sets the TS flag every time a task switch occurs. The flag is used to synchronize the saving of FPU
context in multitasking applications. See the description of the TS flag in the section titled “Control Registers” in
Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for more information
about this flag.
CLTS operation is the same in non-64-bit modes and 64-bit mode.
See Chapter 25, “VMX Non-Root Operation,” of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3C, for more information about the behavior of this instruction in VMX non-root operation.
Operation
CR0.TS[bit 3] ← 0;
Flags Affected
The TS flag in CR0 register is cleared.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
CLTS is not recognized in virtual-8086 mode.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#GP(0)
If the CPL is greater than 0.
#UD
If the LOCK prefix is used.
CLTS—Clear Task-Switched Flag in CR0
Vol. 2A 3-145
INSTRUCTION SET REFERENCE, A-L
CLWB—Cache Line Write Back
Opcode/
Instruction
Op/
En
66 0F AE /6
CLWB m8
M
64/32 bit
Mode
Support
V/V
CPUID
Feature Flag
Description
CLWB
Writes back modified cache line containing m8, and may
retain the line in cache hierarchy in non-modified state.
Instruction Operand Encoding1
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Writes back to memory the cache line (if modified) that contains the linear address specified with the memory
operand from any level of the cache hierarchy in the cache coherence domain. The line may be retained in the
cache hierarchy in non-modified state. Retaining the line in the cache hierarchy is a performance optimization
(treated as a hint by hardware) to reduce the possibility of cache miss on a subsequent access. Hardware may
choose to retain the line at any of the levels in the cache hierarchy, and in some cases, may invalidate the line from
the cache hierarchy. The source operand is a byte memory location.
The availability of CLWB instruction is indicated by the presence of the CPUID feature flag CLWB (bit 24 of the EBX
register, see “CPUID — CPU Identification” in this chapter). The aligned cache line size affected is also indicated
with the CPUID instruction (bits 8 through 15 of the EBX register when the initial value in the EAX register is 1).
The memory attribute of the page containing the affected line has no effect on the behavior of this instruction. It
should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory types).
PREFETCHh instructions can be used to provide the processor with hints for this speculative behavior. Because this
speculative fetching can occur at any time and is not tied to instruction execution, the CLWB instruction is not
ordered with respect to PREFETCHh instructions or any of the speculative fetching mechanisms (that is, data can
be speculatively loaded into a cache line just before, during, or after the execution of a CLWB instruction that references the cache line).
CLWB instruction is ordered only by store-fencing operations. For example, software can use an SFENCE, MFENCE,
XCHG, or LOCK-prefixed instructions to ensure that previous stores are included in the write-back. CLWB instruction need not be ordered by another CLWB or CLFLUSHOPT instruction. CLWB is implicitly ordered with older stores
executed by the logical processor to the same address.
For usages that require only writing back modified data from cache lines to memory (do not require the line to be
invalidated), and expect to subsequently access the data, software is recommended to use CLWB (with appropriate
fencing) instead of CLFLUSH or CLFLUSHOPT for improved performance.
The CLWB instruction can be used at all privilege levels and is subject to all permission checking and faults associated with a byte load. Like a load, the CLWB instruction sets the accessed flag but not the dirty flag in the page
tables.
In some implementations, the CLWB instruction may always cause transactional abort with Transactional Synchronization Extensions (TSX). CLWB instruction is not expected to be commonly used inside typical transactional
regions. However, programmers must not rely on CLWB instruction to force a transactional abort, since whether
they cause transactional abort is implementation dependent.
Operation
Cache_Line_Write_Back(m8);
Flags Affected
None.
1. ModRM.MOD != 011B
3-146 Vol. 2A
CLWB—Cache Line Write Back
INSTRUCTION SET REFERENCE, A-L
C/C++ Compiler Intrinsic Equivalent
CLWB void _mm_clwb(void const *p);
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)
For a page fault.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#GP
If any part of the operand lies outside the effective address space from 0 to FFFFH.
Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)
For a page fault.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#UD
If the LOCK prefix is used.
If CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24] = 0.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
For a page fault.
CLWB—Cache Line Write Back
Vol. 2A 3-147
INSTRUCTION SET REFERENCE, A-L
CMC—Complement Carry Flag
Opcode
Instruction
Op/
En
64-bit
Mode
Compat/ Description
Leg Mode
F5
CMC
NP
Valid
Valid
Complement CF flag.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Complements the CF flag in the EFLAGS register. CMC operation is the same in non-64-bit modes and 64-bit mode.
Operation
EFLAGS.CF[bit 0]← NOT EFLAGS.CF[bit 0];
Flags Affected
The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected.
Exceptions (All Operating Modes)
#UD
3-148 Vol. 2A
If the LOCK prefix is used.
CMC—Complement Carry Flag
INSTRUCTION SET REFERENCE, A-L
CMOVcc—Conditional Move
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 47 /r
CMOVA r16, r/m16
RM
Valid
Valid
Move if above (CF=0 and ZF=0).
0F 47 /r
CMOVA r32, r/m32
RM
Valid
Valid
Move if above (CF=0 and ZF=0).
REX.W + 0F 47 /r
CMOVA r64, r/m64
RM
Valid
N.E.
Move if above (CF=0 and ZF=0).
0F 43 /r
CMOVAE r16, r/m16
RM
Valid
Valid
Move if above or equal (CF=0).
0F 43 /r
CMOVAE r32, r/m32
RM
Valid
Valid
Move if above or equal (CF=0).
REX.W + 0F 43 /r
CMOVAE r64, r/m64
RM
Valid
N.E.
Move if above or equal (CF=0).
0F 42 /r
CMOVB r16, r/m16
RM
Valid
Valid
Move if below (CF=1).
0F 42 /r
CMOVB r32, r/m32
RM
Valid
Valid
Move if below (CF=1).
REX.W + 0F 42 /r
CMOVB r64, r/m64
RM
Valid
N.E.
Move if below (CF=1).
0F 46 /r
CMOVBE r16, r/m16
RM
Valid
Valid
Move if below or equal (CF=1 or ZF=1).
0F 46 /r
CMOVBE r32, r/m32
RM
Valid
Valid
Move if below or equal (CF=1 or ZF=1).
REX.W + 0F 46 /r
CMOVBE r64, r/m64
RM
Valid
N.E.
Move if below or equal (CF=1 or ZF=1).
0F 42 /r
CMOVC r16, r/m16
RM
Valid
Valid
Move if carry (CF=1).
0F 42 /r
CMOVC r32, r/m32
RM
Valid
Valid
Move if carry (CF=1).
REX.W + 0F 42 /r
CMOVC r64, r/m64
RM
Valid
N.E.
Move if carry (CF=1).
0F 44 /r
CMOVE r16, r/m16
RM
Valid
Valid
Move if equal (ZF=1).
0F 44 /r
CMOVE r32, r/m32
RM
Valid
Valid
Move if equal (ZF=1).
REX.W + 0F 44 /r
CMOVE r64, r/m64
RM
Valid
N.E.
Move if equal (ZF=1).
0F 4F /r
CMOVG r16, r/m16
RM
Valid
Valid
Move if greater (ZF=0 and SF=OF).
0F 4F /r
CMOVG r32, r/m32
RM
Valid
Valid
Move if greater (ZF=0 and SF=OF).
REX.W + 0F 4F /r
CMOVG r64, r/m64
RM
V/N.E.
NA
Move if greater (ZF=0 and SF=OF).
0F 4D /r
CMOVGE r16, r/m16
RM
Valid
Valid
Move if greater or equal (SF=OF).
0F 4D /r
CMOVGE r32, r/m32
RM
Valid
Valid
Move if greater or equal (SF=OF).
REX.W + 0F 4D /r
CMOVGE r64, r/m64
RM
Valid
N.E.
Move if greater or equal (SF=OF).
0F 4C /r
CMOVL r16, r/m16
RM
Valid
Valid
Move if less (SF≠ OF).
0F 4C /r
CMOVL r32, r/m32
RM
Valid
Valid
Move if less (SF≠ OF).
REX.W + 0F 4C /r
CMOVL r64, r/m64
RM
Valid
N.E.
Move if less (SF≠ OF).
0F 4E /r
CMOVLE r16, r/m16
RM
Valid
Valid
Move if less or equal (ZF=1 or SF≠ OF).
0F 4E /r
CMOVLE r32, r/m32
RM
Valid
Valid
Move if less or equal (ZF=1 or SF≠ OF).
REX.W + 0F 4E /r
CMOVLE r64, r/m64
RM
Valid
N.E.
Move if less or equal (ZF=1 or SF≠ OF).
0F 46 /r
CMOVNA r16, r/m16
RM
Valid
Valid
Move if not above (CF=1 or ZF=1).
0F 46 /r
CMOVNA r32, r/m32
RM
Valid
Valid
Move if not above (CF=1 or ZF=1).
REX.W + 0F 46 /r
CMOVNA r64, r/m64
RM
Valid
N.E.
Move if not above (CF=1 or ZF=1).
0F 42 /r
CMOVNAE r16, r/m16
RM
Valid
Valid
Move if not above or equal (CF=1).
0F 42 /r
CMOVNAE r32, r/m32
RM
Valid
Valid
Move if not above or equal (CF=1).
REX.W + 0F 42 /r
CMOVNAE r64, r/m64
RM
Valid
N.E.
Move if not above or equal (CF=1).
0F 43 /r
CMOVNB r16, r/m16
RM
Valid
Valid
Move if not below (CF=0).
0F 43 /r
CMOVNB r32, r/m32
RM
Valid
Valid
Move if not below (CF=0).
REX.W + 0F 43 /r
CMOVNB r64, r/m64
RM
Valid
N.E.
Move if not below (CF=0).
0F 47 /r
CMOVNBE r16, r/m16
RM
Valid
Valid
Move if not below or equal (CF=0 and ZF=0).
CMOVcc—Conditional Move
Vol. 2A 3-149
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 47 /r
CMOVNBE r32, r/m32
RM
Valid
Valid
Move if not below or equal (CF=0 and ZF=0).
REX.W + 0F 47 /r
CMOVNBE r64, r/m64
RM
Valid
N.E.
Move if not below or equal (CF=0 and ZF=0).
0F 43 /r
CMOVNC r16, r/m16
RM
Valid
Valid
Move if not carry (CF=0).
0F 43 /r
CMOVNC r32, r/m32
RM
Valid
Valid
Move if not carry (CF=0).
REX.W + 0F 43 /r
CMOVNC r64, r/m64
RM
Valid
N.E.
Move if not carry (CF=0).
0F 45 /r
CMOVNE r16, r/m16
RM
Valid
Valid
Move if not equal (ZF=0).
0F 45 /r
CMOVNE r32, r/m32
RM
Valid
Valid
Move if not equal (ZF=0).
REX.W + 0F 45 /r
CMOVNE r64, r/m64
RM
Valid
N.E.
Move if not equal (ZF=0).
0F 4E /r
CMOVNG r16, r/m16
RM
Valid
Valid
Move if not greater (ZF=1 or SF≠ OF).
0F 4E /r
CMOVNG r32, r/m32
RM
Valid
Valid
Move if not greater (ZF=1 or SF≠ OF).
REX.W + 0F 4E /r
CMOVNG r64, r/m64
RM
Valid
N.E.
Move if not greater (ZF=1 or SF≠ OF).
0F 4C /r
CMOVNGE r16, r/m16
RM
Valid
Valid
Move if not greater or equal (SF≠ OF).
0F 4C /r
CMOVNGE r32, r/m32
RM
Valid
Valid
Move if not greater or equal (SF≠ OF).
REX.W + 0F 4C /r
CMOVNGE r64, r/m64
RM
Valid
N.E.
Move if not greater or equal (SF≠ OF).
0F 4D /r
CMOVNL r16, r/m16
RM
Valid
Valid
Move if not less (SF=OF).
0F 4D /r
CMOVNL r32, r/m32
RM
Valid
Valid
Move if not less (SF=OF).
REX.W + 0F 4D /r
CMOVNL r64, r/m64
RM
Valid
N.E.
Move if not less (SF=OF).
0F 4F /r
CMOVNLE r16, r/m16
RM
Valid
Valid
Move if not less or equal (ZF=0 and SF=OF).
0F 4F /r
CMOVNLE r32, r/m32
RM
Valid
Valid
Move if not less or equal (ZF=0 and SF=OF).
REX.W + 0F 4F /r
CMOVNLE r64, r/m64
RM
Valid
N.E.
Move if not less or equal (ZF=0 and SF=OF).
0F 41 /r
CMOVNO r16, r/m16
RM
Valid
Valid
Move if not overflow (OF=0).
0F 41 /r
CMOVNO r32, r/m32
RM
Valid
Valid
Move if not overflow (OF=0).
REX.W + 0F 41 /r
CMOVNO r64, r/m64
RM
Valid
N.E.
Move if not overflow (OF=0).
0F 4B /r
CMOVNP r16, r/m16
RM
Valid
Valid
Move if not parity (PF=0).
0F 4B /r
CMOVNP r32, r/m32
RM
Valid
Valid
Move if not parity (PF=0).
REX.W + 0F 4B /r
CMOVNP r64, r/m64
RM
Valid
N.E.
Move if not parity (PF=0).
0F 49 /r
CMOVNS r16, r/m16
RM
Valid
Valid
Move if not sign (SF=0).
0F 49 /r
CMOVNS r32, r/m32
RM
Valid
Valid
Move if not sign (SF=0).
REX.W + 0F 49 /r
CMOVNS r64, r/m64
RM
Valid
N.E.
Move if not sign (SF=0).
0F 45 /r
CMOVNZ r16, r/m16
RM
Valid
Valid
Move if not zero (ZF=0).
0F 45 /r
CMOVNZ r32, r/m32
RM
Valid
Valid
Move if not zero (ZF=0).
REX.W + 0F 45 /r
CMOVNZ r64, r/m64
RM
Valid
N.E.
Move if not zero (ZF=0).
0F 40 /r
CMOVO r16, r/m16
RM
Valid
Valid
Move if overflow (OF=1).
0F 40 /r
CMOVO r32, r/m32
RM
Valid
Valid
Move if overflow (OF=1).
REX.W + 0F 40 /r
CMOVO r64, r/m64
RM
Valid
N.E.
Move if overflow (OF=1).
0F 4A /r
CMOVP r16, r/m16
RM
Valid
Valid
Move if parity (PF=1).
0F 4A /r
CMOVP r32, r/m32
RM
Valid
Valid
Move if parity (PF=1).
REX.W + 0F 4A /r
CMOVP r64, r/m64
RM
Valid
N.E.
Move if parity (PF=1).
0F 4A /r
CMOVPE r16, r/m16
RM
Valid
Valid
Move if parity even (PF=1).
0F 4A /r
CMOVPE r32, r/m32
RM
Valid
Valid
Move if parity even (PF=1).
REX.W + 0F 4A /r
CMOVPE r64, r/m64
RM
Valid
N.E.
Move if parity even (PF=1).
3-150 Vol. 2A
CMOVcc—Conditional Move
INSTRUCTION SET REFERENCE, A-L
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 4B /r
CMOVPO r16, r/m16
RM
Valid
Valid
Move if parity odd (PF=0).
0F 4B /r
CMOVPO r32, r/m32
RM
Valid
Valid
Move if parity odd (PF=0).
REX.W + 0F 4B /r
CMOVPO r64, r/m64
RM
Valid
N.E.
Move if parity odd (PF=0).
0F 48 /r
CMOVS r16, r/m16
RM
Valid
Valid
Move if sign (SF=1).
0F 48 /r
CMOVS r32, r/m32
RM
Valid
Valid
Move if sign (SF=1).
REX.W + 0F 48 /r
CMOVS r64, r/m64
RM
Valid
N.E.
Move if sign (SF=1).
0F 44 /r
CMOVZ r16, r/m16
RM
Valid
Valid
Move if zero (ZF=1).
0F 44 /r
CMOVZ r32, r/m32
RM
Valid
Valid
Move if zero (ZF=1).
REX.W + 0F 44 /r
CMOVZ r64, r/m64
RM
Valid
N.E.
Move if zero (ZF=1).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
The CMOVcc instructions check the state of one or more of the status flags in the EFLAGS register (CF, OF, PF, SF,
and ZF) and perform a move operation if the flags are in a specified state (or condition). A condition code (cc) is
associated with each instruction to indicate the condition being tested for. If the condition is not satisfied, a move
is not performed and execution continues with the instruction following the CMOVcc instruction.
These instructions can move 16-bit, 32-bit or 64-bit values from memory to a general-purpose register or from one
general-purpose register to another. Conditional moves of 8-bit register operands are not supported.
The condition for each CMOVcc mnemonic is given in the description column of the above table. The terms “less”
and “greater” are used for comparisons of signed integers and the terms “above” and “below” are used for
unsigned integers.
Because a particular state of the status flags can sometimes be interpreted in two ways, two mnemonics are
defined for some opcodes. For example, the CMOVA (conditional move if above) instruction and the CMOVNBE
(conditional move if not below or equal) instruction are alternate mnemonics for the opcode 0F 47H.
The CMOVcc instructions were introduced in P6 family processors; however, these instructions may not be
supported by all IA-32 processors. Software can determine if the CMOVcc instructions are supported by checking
the processor’s feature information with the CPUID instruction (see “CPUID—CPU Identification” in this chapter).
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
temp ← SRC
IF condition TRUE
THEN
DEST ← temp;
FI;
ELSE
IF (OperandSize = 32 and IA-32e mode active)
THEN
DEST[63:32] ← 0;
FI;
FI;
CMOVcc—Conditional Move
Vol. 2A 3-151
INSTRUCTION SET REFERENCE, A-L
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-152 Vol. 2A
CMOVcc—Conditional Move
INSTRUCTION SET REFERENCE, A-L
CMP—Compare Two Operands
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
3C ib
CMP AL, imm8
I
Valid
Valid
Compare imm8 with AL.
3D iw
CMP AX, imm16
I
Valid
Valid
Compare imm16 with AX.
3D id
CMP EAX, imm32
I
Valid
Valid
Compare imm32 with EAX.
REX.W + 3D id
CMP RAX, imm32
I
Valid
N.E.
Compare imm32 sign-extended to 64-bits
with RAX.
80 /7 ib
CMP r/m8, imm8
MI
Valid
Valid
Compare imm8 with r/m8.
REX + 80 /7 ib
CMP r/m8*, imm8
MI
Valid
N.E.
Compare imm8 with r/m8.
81 /7 iw
CMP r/m16, imm16
MI
Valid
Valid
Compare imm16 with r/m16.
81 /7 id
CMP r/m32, imm32
MI
Valid
Valid
Compare imm32 with r/m32.
REX.W + 81 /7 id
CMP r/m64, imm32
MI
Valid
N.E.
Compare imm32 sign-extended to 64-bits
with r/m64.
83 /7 ib
CMP r/m16, imm8
MI
Valid
Valid
Compare imm8 with r/m16.
83 /7 ib
CMP r/m32, imm8
MI
Valid
Valid
Compare imm8 with r/m32.
REX.W + 83 /7 ib
CMP r/m64, imm8
MI
Valid
N.E.
Compare imm8 with r/m64.
38 /r
CMP r/m8, r8
MR
Valid
Valid
Compare r8 with r/m8.
MR
Valid
N.E.
Compare r8 with r/m8.
*
*
REX + 38 /r
CMP r/m8 , r8
39 /r
CMP r/m16, r16
MR
Valid
Valid
Compare r16 with r/m16.
39 /r
CMP r/m32, r32
MR
Valid
Valid
Compare r32 with r/m32.
REX.W + 39 /r
CMP r/m64,r64
MR
Valid
N.E.
Compare r64 with r/m64.
3A /r
CMP r8, r/m8
RM
Valid
Valid
Compare r/m8 with r8.
*
*
REX + 3A /r
CMP r8 , r/m8
RM
Valid
N.E.
Compare r/m8 with r8.
3B /r
CMP r16, r/m16
RM
Valid
Valid
Compare r/m16 with r16.
3B /r
CMP r32, r/m32
RM
Valid
Valid
Compare r/m32 with r32.
REX.W + 3B /r
CMP r64, r/m64
RM
Valid
N.E.
Compare r/m64 with r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r)
ModRM:r/m (r)
NA
NA
MR
ModRM:r/m (r)
ModRM:reg (r)
NA
NA
MI
ModRM:r/m (r)
imm8
NA
NA
I
AL/AX/EAX/RAX (r)
imm8
NA
NA
Description
Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register
according to the results. The comparison is performed by subtracting the second operand from the first operand
and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as
an operand, it is sign-extended to the length of the first operand.
The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based on the results of a CMP instruction.
Appendix B, “EFLAGS Condition Codes,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, shows the relationship of the status flags and the condition codes.
CMP—Compare Two Operands
Vol. 2A 3-153
INSTRUCTION SET REFERENCE, A-L
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
Operation
temp ← SRC1 − SignExtend(SRC2);
ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-154 Vol. 2A
CMP—Compare Two Operands
INSTRUCTION SET REFERENCE, A-L
CMPPD—Compare Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F C2 /r ib
CMPPD xmm1, xmm2/m128, imm8
VEX.NDS.128.66.0F.WIG C2 /r ib
VCMPPD xmm1, xmm2, xmm3/m128,
imm8
VEX.NDS.256.66.0F.WIG C2 /r ib
VCMPPD ymm1, ymm2, ymm3/m256,
imm8
EVEX.NDS.128.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, xmm2,
xmm3/m128/m64bcst, imm8
RVMI
V/V
AVX
RVMI
V/V
AVX
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, ymm2,
ymm3/m256/m64bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 C2 /r ib
VCMPPD k1 {k2}, zmm2,
zmm3/m512/m64bcst{sae}, imm8
FV
V/V
AVX512F
Description
Compare packed double-precision floating-point values
in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed double-precision floating-point values
in xmm3/m128/m64bcst and xmm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Compare packed double-precision floating-point values
in ymm3/m256/m64bcst and ymm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Compare packed double-precision floating-point values
in zmm3/m512/m64bcst and zmm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Performs a SIMD compare of the packed double-precision floating-point values in the second source operand and
the first source operand and returns the results of the comparison to the destination operand. The comparison
predicate operand (immediate byte) specifies the type of comparison performed on each pair of packed values in
the two source operands.
EVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is an opmask register.
Comparison results are written to the destination operand under the writemask k2. Each comparison result is a
single mask bit of 1 (comparison true) or 0 (comparison false).
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source
operand (third operand) can be a YMM register or a 256-bit memory location. The destination operand (first
operand) is a YMM register. Four comparisons are performed with results written to the destination operand. The
result of each comparison is a quadword mask of all 1s (comparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The
second source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAX_VL1:128) of the corresponding ZMM destination register remain unchanged. Two comparisons are performed with
results written to bits 127:0 of the destination operand. The result of each comparison is a quadword mask of all
1s (comparison true) or all 0s (comparison false).
CMPPD—Compare Packed Double-Precision Floating-Point Values
Vol. 2A 3-155
INSTRUCTION SET REFERENCE, A-L
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed. Two comparisons are performed with results written to bits 127:0 of the destination operand.
The comparison predicate operand is an 8-bit immediate:
•
For instructions encoded using the VEX or EVEX prefix, bits 4:0 define the type of comparison to be performed
(see Table 3-1). Bits 5 through 7 of the immediate are reserved.
•
For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see the
first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions
Predicate
imm8
Value
Description
EQ_OQ (EQ)
0H
Equal (ordered, non-signaling)
False
False
True
False
No
LT_OS (LT)
1H
Less-than (ordered, signaling)
False
True
False
False
Yes
LE_OS (LE)
2H
Less-than-or-equal (ordered, signaling)
False
True
True
False
Yes
Unordered (non-signaling)
False
False
False
True
No
UNORD_Q (UNORD) 3H
Result: A Is 1st Operand, B Is 2nd Operand Signals
#IA on
A<B
A=B
Unordered1 QNAN
A >B
NEQ_UQ (NEQ)
4H
Not-equal (unordered, non-signaling)
True
True
False
True
No
NLT_US (NLT)
5H
Not-less-than (unordered, signaling)
True
False
True
True
Yes
NLE_US (NLE)
6H
Not-less-than-or-equal (unordered, signaling)
True
False
False
True
Yes
ORD_Q (ORD)
7H
Ordered (non-signaling)
True
True
True
False
No
EQ_UQ
8H
Equal (unordered, non-signaling)
False
False
True
True
No
NGE_US (NGE)
9H
Not-greater-than-or-equal (unordered,
signaling)
False
True
False
True
Yes
NGT_US (NGT)
AH
Not-greater-than (unordered, signaling)
False
True
True
True
Yes
FALSE_OQ(FALSE)
BH
False (ordered, non-signaling)
False
False
False
False
No
NEQ_OQ
CH
Not-equal (ordered, non-signaling)
True
True
False
False
No
GE_OS (GE)
DH
Greater-than-or-equal (ordered, signaling)
True
False
True
False
Yes
GT_OS (GT)
EH
Greater-than (ordered, signaling)
True
False
False
False
Yes
TRUE_UQ(TRUE)
FH
True (unordered, non-signaling)
True
True
True
True
No
EQ_OS
10H
Equal (ordered, signaling)
False
False
True
False
Yes
LT_OQ
11H
Less-than (ordered, nonsignaling)
False
True
False
False
No
LE_OQ
12H
Less-than-or-equal (ordered, nonsignaling)
False
True
True
False
No
UNORD_S
13H
Unordered (signaling)
False
False
False
True
Yes
NEQ_US
14H
Not-equal (unordered, signaling)
True
True
False
True
Yes
NLT_UQ
15H
Not-less-than (unordered, nonsignaling)
True
False
True
True
No
NLE_UQ
16H
Not-less-than-or-equal (unordered, nonsignaling)
True
False
False
True
No
ORD_S
17H
Ordered (signaling)
True
True
True
False
Yes
EQ_US
18H
Equal (unordered, signaling)
False
False
True
True
Yes
NGE_UQ
19H
Not-greater-than-or-equal (unordered, nonsignaling)
False
True
False
True
No
3-156 Vol. 2A
CMPPD—Compare Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Table 3-1. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.)
Predicate
imm8
Value
Description
Result: A Is 1st Operand, B Is 2nd Operand Signals
#IA on
A >B
A<B
A=B
Unordered1 QNAN
NGT_UQ
1AH
Not-greater-than (unordered, nonsignaling)
False
True
True
True
No
FALSE_OS
1BH
False (ordered, signaling)
False
False
False
False
Yes
NEQ_OS
1CH
Not-equal (ordered, signaling)
True
True
False
False
Yes
GE_OQ
1DH
Greater-than-or-equal (ordered, nonsignaling)
True
False
True
False
No
GT_OQ
1EH
Greater-than (ordered, nonsignaling)
True
False
False
False
No
TRUE_US
1FH
True (unordered, signaling)
True
True
True
True
Yes
NOTES:
1. If either operand A or B is a NAN.
The unordered relationship is true when at least one of the two source operands being compared is a NaN; the
ordered relationship is true when neither source operand is a NaN.
A subsequent computational instruction that uses the mask result in the destination operand as an input operand
will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask
of all 1s corresponds to a QNaN.
Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”,
“not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either
by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison)
or by using software emulation. When using software emulation, the program must swap the operands (copying
registers when necessary to protect the data that will now be in the destination), and then perform the compare
using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7
(Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2A) under the heading Emulation.
Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand
CMPPD instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-2. Compiler should treat reserved
Imm8 values as illegal syntax.
Table 3-2. Pseudo-Op and CMPPD Implementation
:
Pseudo-Op
CMPPD Implementation
CMPEQPD xmm1, xmm2
CMPPD xmm1, xmm2, 0
CMPLTPD xmm1, xmm2
CMPPD xmm1, xmm2, 1
CMPLEPD xmm1, xmm2
CMPPD xmm1, xmm2, 2
CMPUNORDPD xmm1, xmm2
CMPPD xmm1, xmm2, 3
CMPNEQPD xmm1, xmm2
CMPPD xmm1, xmm2, 4
CMPNLTPD xmm1, xmm2
CMPPD xmm1, xmm2, 5
CMPNLEPD xmm1, xmm2
CMPPD xmm1, xmm2, 6
CMPORDPD xmm1, xmm2
CMPPD xmm1, xmm2, 7
The greater-than relations that the processor does not implement require more than one instruction to emulate in
software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to
the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-3, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand
pseudo-ops in addition to the four-operand VCMPPD instruction. See Table 3-3, where the notations of reg1 reg2,
and reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal
CMPPD—Compare Packed Double-Precision Floating-Point Values
Vol. 2A 3-157
INSTRUCTION SET REFERENCE, A-L
syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPD instructions
in a similar fashion by extending the syntax listed in Table 3-3.
Table 3-3. Pseudo-Op and VCMPPD Implementation
:
Pseudo-Op
CMPPD Implementation
VCMPEQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0
VCMPLTPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1
VCMPLEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 2
VCMPUNORDPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 3
VCMPNEQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 4
VCMPNLTPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 5
VCMPNLEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 6
VCMPORDPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 7
VCMPEQ_UQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 8
VCMPNGEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 9
VCMPNGTPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0AH
VCMPFALSEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0BH
VCMPNEQ_OQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0CH
VCMPGEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0DH
VCMPGTPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0EH
VCMPTRUEPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 0FH
VCMPEQ_OSPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 10H
VCMPLT_OQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 11H
VCMPLE_OQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 12H
VCMPUNORD_SPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 13H
VCMPNEQ_USPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 14H
VCMPNLT_UQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 15H
VCMPNLE_UQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 16H
VCMPORD_SPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 17H
VCMPEQ_USPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 18H
VCMPNGE_UQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 19H
VCMPNGT_UQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1AH
VCMPFALSE_OSPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1BH
VCMPNEQ_OSPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1CH
VCMPGE_OQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1DH
VCMPGT_OQPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1EH
VCMPTRUE_USPD reg1, reg2, reg3
VCMPPD reg1, reg2, reg3, 1FH
3-158 Vol. 2A
CMPPD—Compare Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
CASE (COMPARISON PREDICATE) OF
0: OP3  EQ_OQ; OP5  EQ_OQ;
1: OP3  LT_OS; OP5  LT_OS;
2: OP3  LE_OS; OP5  LE_OS;
3: OP3  UNORD_Q; OP5  UNORD_Q;
4: OP3  NEQ_UQ; OP5  NEQ_UQ;
5: OP3  NLT_US; OP5  NLT_US;
6: OP3  NLE_US; OP5  NLE_US;
7: OP3  ORD_Q; OP5  ORD_Q;
8: OP5  EQ_UQ;
9: OP5  NGE_US;
10: OP5  NGT_US;
11: OP5  FALSE_OQ;
12: OP5  NEQ_OQ;
13: OP5  GE_OS;
14: OP5  GT_OS;
15: OP5  TRUE_UQ;
16: OP5  EQ_OS;
17: OP5  LT_OQ;
18: OP5  LE_OQ;
19: OP5  UNORD_S;
20: OP5  NEQ_US;
21: OP5  NLT_UQ;
22: OP5  NLE_UQ;
23: OP5  ORD_S;
24: OP5  EQ_US;
25: OP5  NGE_UQ;
26: OP5  NGT_UQ;
27: OP5  FALSE_OS;
28: OP5  NEQ_OS;
29: OP5  GE_OQ;
30: OP5  GT_OQ;
31: OP5  TRUE_US;
DEFAULT: Reserved;
ESAC;
CMPPD—Compare Packed Double-Precision Floating-Point Values
Vol. 2A 3-159
INSTRUCTION SET REFERENCE, A-L
VCMPPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
CMP  SRC1[i+63:i] OP5 SRC2[63:0]
ELSE
CMP  SRC1[i+63:i] OP5 SRC2[i+63:i]
FI;
IF CMP = TRUE
THEN DEST[j]  1;
ELSE DEST[j]  0; FI;
ELSE
DEST[j]  0
; zeroing-masking only
FI;
ENDFOR
DEST[MAX_KL-1:KL]  0
VCMPPD (VEX.256 encoded version)
CMP0  SRC1[63:0] OP5 SRC2[63:0];
CMP1  SRC1[127:64] OP5 SRC2[127:64];
CMP2  SRC1[191:128] OP5 SRC2[191:128];
CMP3  SRC1[255:192] OP5 SRC2[255:192];
IF CMP0 = TRUE
THEN DEST[63:0]  FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0]  0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64]  FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64]  0000000000000000H; FI;
IF CMP2 = TRUE
THEN DEST[191:128]  FFFFFFFFFFFFFFFFH;
ELSE DEST[191:128]  0000000000000000H; FI;
IF CMP3 = TRUE
THEN DEST[255:192]  FFFFFFFFFFFFFFFFH;
ELSE DEST[255:192]  0000000000000000H; FI;
DEST[MAX_VL-1:256]  0
VCMPPD (VEX.128 encoded version)
CMP0  SRC1[63:0] OP5 SRC2[63:0];
CMP1  SRC1[127:64] OP5 SRC2[127:64];
IF CMP0 = TRUE
THEN DEST[63:0]  FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0]  0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64]  FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64]  0000000000000000H; FI;
DEST[MAX_VL-1:128]  0
3-160 Vol. 2A
CMPPD—Compare Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
CMPPD (128-bit Legacy SSE version)
CMP0  SRC1[63:0] OP3 SRC2[63:0];
CMP1  SRC1[127:64] OP3 SRC2[127:64];
IF CMP0 = TRUE
THEN DEST[63:0]  FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0]  0000000000000000H; FI;
IF CMP1 = TRUE
THEN DEST[127:64]  FFFFFFFFFFFFFFFFH;
ELSE DEST[127:64]  0000000000000000H; FI;
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCMPPD __mmask8 _mm512_cmp_pd_mask( __m512d a, __m512d b, int imm);
VCMPPD __mmask8 _mm512_cmp_round_pd_mask( __m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm512_mask_cmp_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm);
VCMPPD __mmask8 _mm512_mask_cmp_round_pd_mask( __mmask8 k1, __m512d a, __m512d b, int imm, int sae);
VCMPPD __mmask8 _mm256_cmp_pd_mask( __m256d a, __m256d b, int imm);
VCMPPD __mmask8 _mm256_mask_cmp_pd_mask( __mmask8 k1, __m256d a, __m256d b, int imm);
VCMPPD __mmask8 _mm_cmp_pd_mask( __m128d a, __m128d b, int imm);
VCMPPD __mmask8 _mm_mask_cmp_pd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);
VCMPPD __m256 _mm256_cmp_pd(__m256d a, __m256d b, int imm)
(V)CMPPD __m128 _mm_cmp_pd(__m128d a, __m128d b, int imm)
SIMD Floating-Point Exceptions
Invalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1.
Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
CMPPD—Compare Packed Double-Precision Floating-Point Values
Vol. 2A 3-161
INSTRUCTION SET REFERENCE, A-L
CMPPS—Compare Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F C2 /r ib
CMPPS xmm1, xmm2/m128,
imm8
VEX.NDS.128.0F.WIG C2 /r ib
VCMPPS xmm1, xmm2,
xmm3/m128, imm8
VEX.NDS.256.0F.WIG C2 /r ib
VCMPPS ymm1, ymm2,
ymm3/m256, imm8
EVEX.NDS.128.0F.W0 C2 /r ib
VCMPPS k1 {k2}, xmm2,
xmm3/m128/m32bcst, imm8
RVMI
V/V
AVX
RVMI
V/V
AVX
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.0F.W0 C2 /r ib
VCMPPS k1 {k2}, ymm2,
ymm3/m256/m32bcst, imm8
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.0F.W0 C2 /r ib
VCMPPS k1 {k2}, zmm2,
zmm3/m512/m32bcst{sae}, imm8
FV
V/V
AVX512F
Description
Compare packed single-precision floating-point values in
xmm2/m128 and xmm1 using bits 2:0 of imm8 as a
comparison predicate.
Compare packed single-precision floating-point values in
xmm3/m128 and xmm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed single-precision floating-point values in
ymm3/m256 and ymm2 using bits 4:0 of imm8 as a
comparison predicate.
Compare packed single-precision floating-point values in
xmm3/m128/m32bcst and xmm2 using bits 4:0 of imm8 as
a comparison predicate with writemask k2 and leave the
result in mask register k1.
Compare packed single-precision floating-point values in
ymm3/m256/m32bcst and ymm2 using bits 4:0 of imm8 as
a comparison predicate with writemask k2 and leave the
result in mask register k1.
Compare packed single-precision floating-point values in
zmm3/m512/m32bcst and zmm2 using bits 4:0 of imm8 as
a comparison predicate with writemask k2 and leave the
result in mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Performs a SIMD compare of the packed single-precision floating-point values in the second source operand and
the first source operand and returns the results of the comparison to the destination operand. The comparison
predicate operand (immediate byte) specifies the type of comparison performed on each of the pairs of packed
values.
EVEX encoded versions: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand (first operand) is an opmask register.
Comparison results are written to the destination operand under the writemask k2. Each comparison result is a
single mask bit of 1 (comparison true) or 0 (comparison false).
VEX.256 encoded version: The first source operand (second operand) is a YMM register. The second source operand
(third operand) can be a YMM register or a 256-bit memory location. The destination operand (first operand) is a
YMM register. Eight comparisons are performed with results written to the destination operand. The result of each
comparison is a doubleword mask of all 1s (comparison true) or all 0s (comparison false).
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The
second source operand (second operand) can be an XMM register or 128-bit memory location. Bits (MAX_VL1:128) of the corresponding ZMM destination register remain unchanged. Four comparisons are performed with
results written to bits 127:0 of the destination operand. The result of each comparison is a doubleword mask of all
1s (comparison true) or all 0s (comparison false).
3-162 Vol. 2A
CMPPS—Compare Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed. Four comparisons are performed with results written to bits 127:0 of the destination operand.
The comparison predicate operand is an 8-bit immediate:
•
For instructions encoded using the VEX prefix and EVEX prefix, bits 4:0 define the type of comparison to be
performed (see Table 3-1). Bits 5 through 7 of the immediate are reserved.
•
For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see
the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
The unordered relationship is true when at least one of the two source operands being compared is a NaN; the
ordered relationship is true when neither source operand is a NaN.
A subsequent computational instruction that uses the mask result in the destination operand as an input operand
will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask
of all 1s corresponds to a QNaN.
Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”,
“not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either
by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison)
or by using software emulation. When using software emulation, the program must swap the operands (copying
registers when necessary to protect the data that will now be in the destination), and then perform the compare
using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7
(Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2A) under the heading Emulation.
Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand
CMPPS instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-4. Compiler should treat reserved
Imm8 values as illegal syntax.
Table 3-4. Pseudo-Op and CMPPS Implementation
:
Pseudo-Op
CMPPS Implementation
CMPEQPS xmm1, xmm2
CMPPS xmm1, xmm2, 0
CMPLTPS xmm1, xmm2
CMPPS xmm1, xmm2, 1
CMPLEPS xmm1, xmm2
CMPPS xmm1, xmm2, 2
CMPUNORDPS xmm1, xmm2
CMPPS xmm1, xmm2, 3
CMPNEQPS xmm1, xmm2
CMPPS xmm1, xmm2, 4
CMPNLTPS xmm1, xmm2
CMPPS xmm1, xmm2, 5
CMPNLEPS xmm1, xmm2
CMPPS xmm1, xmm2, 6
CMPORDPS xmm1, xmm2
CMPPS xmm1, xmm2, 7
The greater-than relations that the processor does not implement require more than one instruction to emulate in
software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to
the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-5, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand
pseudo-ops in addition to the four-operand VCMPPS instruction. See Table 3-5, where the notation of reg1 and
reg2 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal
syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPPS instructions
in a similar fashion by extending the syntax listed in Table 3-5.
:
CMPPS—Compare Packed Single-Precision Floating-Point Values
Vol. 2A 3-163
INSTRUCTION SET REFERENCE, A-L
Table 3-5. Pseudo-Op and VCMPPS Implementation
Pseudo-Op
CMPPS Implementation
VCMPEQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0
VCMPLTPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1
VCMPLEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 2
VCMPUNORDPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 3
VCMPNEQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 4
VCMPNLTPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 5
VCMPNLEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 6
VCMPORDPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 7
VCMPEQ_UQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 8
VCMPNGEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 9
VCMPNGTPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0AH
VCMPFALSEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0BH
VCMPNEQ_OQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0CH
VCMPGEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0DH
VCMPGTPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0EH
VCMPTRUEPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 0FH
VCMPEQ_OSPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 10H
VCMPLT_OQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 11H
VCMPLE_OQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 12H
VCMPUNORD_SPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 13H
VCMPNEQ_USPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 14H
VCMPNLT_UQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 15H
VCMPNLE_UQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 16H
VCMPORD_SPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 17H
VCMPEQ_USPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 18H
VCMPNGE_UQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 19H
VCMPNGT_UQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1AH
VCMPFALSE_OSPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1BH
VCMPNEQ_OSPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1CH
VCMPGE_OQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1DH
VCMPGT_OQPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1EH
VCMPTRUE_USPS reg1, reg2, reg3
VCMPPS reg1, reg2, reg3, 1FH
3-164 Vol. 2A
CMPPS—Compare Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
CASE (COMPARISON PREDICATE) OF
0: OP3  EQ_OQ; OP5  EQ_OQ;
1: OP3  LT_OS; OP5  LT_OS;
2: OP3  LE_OS; OP5  LE_OS;
3: OP3  UNORD_Q; OP5  UNORD_Q;
4: OP3  NEQ_UQ; OP5  NEQ_UQ;
5: OP3  NLT_US; OP5  NLT_US;
6: OP3  NLE_US; OP5  NLE_US;
7: OP3  ORD_Q; OP5  ORD_Q;
8: OP5  EQ_UQ;
9: OP5  NGE_US;
10: OP5  NGT_US;
11: OP5  FALSE_OQ;
12: OP5  NEQ_OQ;
13: OP5  GE_OS;
14: OP5  GT_OS;
15: OP5  TRUE_UQ;
16: OP5  EQ_OS;
17: OP5  LT_OQ;
18: OP5  LE_OQ;
19: OP5  UNORD_S;
20: OP5  NEQ_US;
21: OP5  NLT_UQ;
22: OP5  NLE_UQ;
23: OP5  ORD_S;
24: OP5  EQ_US;
25: OP5  NGE_UQ;
26: OP5  NGT_UQ;
27: OP5  FALSE_OS;
28: OP5  NEQ_OS;
29: OP5  GE_OQ;
30: OP5  GT_OQ;
31: OP5  TRUE_US;
DEFAULT: Reserved
ESAC;
CMPPS—Compare Packed Single-Precision Floating-Point Values
Vol. 2A 3-165
INSTRUCTION SET REFERENCE, A-L
VCMPPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i  j * 32
IF k2[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
CMP  SRC1[i+31:i] OP5 SRC2[31:0]
ELSE
CMP  SRC1[i+31:i] OP5 SRC2[i+31:i]
FI;
IF CMP = TRUE
THEN DEST[j]  1;
ELSE DEST[j]  0; FI;
ELSE
DEST[j]  0
; zeroing-masking onlyFI;
FI;
ENDFOR
DEST[MAX_KL-1:KL]  0
VCMPPS (VEX.256 encoded version)
CMP0  SRC1[31:0] OP5 SRC2[31:0];
CMP1  SRC1[63:32] OP5 SRC2[63:32];
CMP2  SRC1[95:64] OP5 SRC2[95:64];
CMP3  SRC1[127:96] OP5 SRC2[127:96];
CMP4  SRC1[159:128] OP5 SRC2[159:128];
CMP5  SRC1[191:160] OP5 SRC2[191:160];
CMP6  SRC1[223:192] OP5 SRC2[223:192];
CMP7  SRC1[255:224] OP5 SRC2[255:224];
IF CMP0 = TRUE
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0]  000000000H; FI;
IF CMP1 = TRUE
THEN DEST[63:32]  FFFFFFFFH;
ELSE DEST[63:32] 000000000H; FI;
IF CMP2 = TRUE
THEN DEST[95:64]  FFFFFFFFH;
ELSE DEST[95:64]  000000000H; FI;
IF CMP3 = TRUE
THEN DEST[127:96]  FFFFFFFFH;
ELSE DEST[127:96]  000000000H; FI;
IF CMP4 = TRUE
THEN DEST[159:128]  FFFFFFFFH;
ELSE DEST[159:128]  000000000H; FI;
IF CMP5 = TRUE
THEN DEST[191:160]  FFFFFFFFH;
ELSE DEST[191:160]  000000000H; FI;
IF CMP6 = TRUE
THEN DEST[223:192]  FFFFFFFFH;
ELSE DEST[223:192] 000000000H; FI;
IF CMP7 = TRUE
THEN DEST[255:224]  FFFFFFFFH;
ELSE DEST[255:224]  000000000H; FI;
DEST[MAX_VL-1:256]  0
3-166 Vol. 2A
CMPPS—Compare Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
VCMPPS (VEX.128 encoded version)
CMP0  SRC1[31:0] OP5 SRC2[31:0];
CMP1  SRC1[63:32] OP5 SRC2[63:32];
CMP2  SRC1[95:64] OP5 SRC2[95:64];
CMP3  SRC1[127:96] OP5 SRC2[127:96];
IF CMP0 = TRUE
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0]  000000000H; FI;
IF CMP1 = TRUE
THEN DEST[63:32]  FFFFFFFFH;
ELSE DEST[63:32]  000000000H; FI;
IF CMP2 = TRUE
THEN DEST[95:64]  FFFFFFFFH;
ELSE DEST[95:64]  000000000H; FI;
IF CMP3 = TRUE
THEN DEST[127:96]  FFFFFFFFH;
ELSE DEST[127:96] 000000000H; FI;
DEST[MAX_VL-1:128]  0
CMPPS (128-bit Legacy SSE version)
CMP0  SRC1[31:0] OP3 SRC2[31:0];
CMP1  SRC1[63:32] OP3 SRC2[63:32];
CMP2  SRC1[95:64] OP3 SRC2[95:64];
CMP3  SRC1[127:96] OP3 SRC2[127:96];
IF CMP0 = TRUE
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0]  000000000H; FI;
IF CMP1 = TRUE
THEN DEST[63:32]  FFFFFFFFH;
ELSE DEST[63:32]  000000000H; FI;
IF CMP2 = TRUE
THEN DEST[95:64]  FFFFFFFFH;
ELSE DEST[95:64]  000000000H; FI;
IF CMP3 = TRUE
THEN DEST[127:96]  FFFFFFFFH;
ELSE DEST[127:96] 000000000H; FI;
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCMPPS __mmask16 _mm512_cmp_ps_mask( __m512 a, __m512 b, int imm);
VCMPPS __mmask16 _mm512_cmp_round_ps_mask( __m512 a, __m512 b, int imm, int sae);
VCMPPS __mmask16 _mm512_mask_cmp_ps_mask( __mmask16 k1, __m512 a, __m512 b, int imm);
VCMPPS __mmask16 _mm512_mask_cmp_round_ps_mask( __mmask16 k1, __m512 a, __m512 b, int imm, int sae);
VCMPPD __mmask8 _mm256_cmp_ps_mask( __m256 a, __m256 b, int imm);
VCMPPS __mmask8 _mm256_mask_cmp_ps_mask( __mmask8 k1, __m256 a, __m256 b, int imm);
VCMPPS __mmask8 _mm_cmp_ps_mask( __m128 a, __m128 b, int imm);
VCMPPS __mmask8 _mm_mask_cmp_ps_mask( __mmask8 k1, __m128 a, __m128 b, int imm);
VCMPPS __m256 _mm256_cmp_ps(__m256 a, __m256 b, int imm)
CMPPS __m128 _mm_cmp_ps(__m128 a, __m128 b, int imm)
SIMD Floating-Point Exceptions
Invalid if SNaN operand and invalid if QNaN and predicate as listed in Table 3-1.
Denormal
CMPPS—Compare Packed Single-Precision Floating-Point Values
Vol. 2A 3-167
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
3-168 Vol. 2A
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INSTRUCTION SET REFERENCE, A-L
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
A6
CMPS m8, m8
NP
Valid
Valid
For legacy mode, compare byte at address DS:(E)SI with
byte at address ES:(E)DI; For 64-bit mode compare byte
at address (R|E)SI to byte at address (R|E)DI. The status
flags are set accordingly.
A7
CMPS m16, m16
NP
Valid
Valid
For legacy mode, compare word at address DS:(E)SI
with word at address ES:(E)DI; For 64-bit mode
compare word at address (R|E)SI with word at address
(R|E)DI. The status flags are set accordingly.
A7
CMPS m32, m32
NP
Valid
Valid
For legacy mode, compare dword at address DS:(E)SI at
dword at address ES:(E)DI; For 64-bit mode compare
dword at address (R|E)SI at dword at address (R|E)DI.
The status flags are set accordingly.
REX.W + A7
CMPS m64, m64
NP
Valid
N.E.
Compares quadword at address (R|E)SI with quadword
at address (R|E)DI and sets the status flags accordingly.
A6
CMPSB
NP
Valid
Valid
For legacy mode, compare byte at address DS:(E)SI with
byte at address ES:(E)DI; For 64-bit mode compare byte
at address (R|E)SI with byte at address (R|E)DI. The
status flags are set accordingly.
A7
CMPSW
NP
Valid
Valid
For legacy mode, compare word at address DS:(E)SI
with word at address ES:(E)DI; For 64-bit mode
compare word at address (R|E)SI with word at address
(R|E)DI. The status flags are set accordingly.
A7
CMPSD
NP
Valid
Valid
For legacy mode, compare dword at address DS:(E)SI
with dword at address ES:(E)DI; For 64-bit mode
compare dword at address (R|E)SI with dword at
address (R|E)DI. The status flags are set accordingly.
REX.W + A7
CMPSQ
NP
Valid
N.E.
Compares quadword at address (R|E)SI with quadword
at address (R|E)DI and sets the status flags accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Compares the byte, word, doubleword, or quadword specified with the first source operand with the byte, word,
doubleword, or quadword specified with the second source operand and sets the status flags in the EFLAGS register
according to the results.
Both source operands are located in memory. The address of the first source operand is read from DS:SI, DS:ESI
or RSI (depending on the address-size attribute of the instruction is 16, 32, or 64, respectively). The address of the
second source operand is read from ES:DI, ES:EDI or RDI (again depending on the address-size attribute of the
instruction is 16, 32, or 64). The DS segment may be overridden with a segment override prefix, but the ES
segment cannot be overridden.
At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands” form and the “nooperands” form. The explicit-operands form (specified with the CMPS mnemonic) allows the two source operands
to be specified explicitly. Here, the source operands should be symbols that indicate the size and location of the
source values. This explicit-operand form is provided to allow documentation. However, note that the documentation provided by this form can be misleading. That is, the source operand symbols must specify the correct type
(size) of the operands (bytes, words, or doublewords, quadwords), but they do not have to specify the correct loca-
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
Vol. 2A 3-169
INSTRUCTION SET REFERENCE, A-L
tion. Locations of the source operands are always specified by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers, which must be loaded correctly before the compare string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword versions of the CMPS instructions.
Here also the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using
REX.W).
After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the
setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the
DF flag is 1, the registers decrement.) The registers increment or decrement by 1 for byte operations, by 2 for word
operations, 4 for doubleword operations. If operand size is 64, RSI and RDI registers increment by 8 for quadword
operations.
The CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the REP prefix for block comparisons. More often, however, these instructions will be used in a LOOP construct that takes some action based on the
setting of the status flags before the next comparison is made. See “REP/REPE/REPZ /REPNE/REPNZ—Repeat
String Operation Prefix” in Chapter 4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B, for a description of the REP prefix.
In 64-bit mode, the instruction’s default address size is 64 bits, 32 bit address size is supported using the prefix
67H. Use of the REX.W prefix promotes doubleword operation to 64 bits (see CMPSQ). See the summary chart at
the beginning of this section for encoding data and limits.
Operation
temp ← SRC1 - SRC2;
SetStatusFlags(temp);
IF (64-Bit Mode)
THEN
IF (Byte comparison)
THEN IF DF = 0
THEN
(R|E)SI ← (R|E)SI + 1;
(R|E)DI ← (R|E)DI + 1;
ELSE
(R|E)SI ← (R|E)SI – 1;
(R|E)DI ← (R|E)DI – 1;
FI;
ELSE IF (Word comparison)
THEN IF DF = 0
THEN
(R|E)SI ← (R|E)SI + 2;
(R|E)DI ← (R|E)DI + 2;
ELSE
(R|E)SI ← (R|E)SI – 2;
(R|E)DI ← (R|E)DI – 2;
FI;
ELSE IF (Doubleword comparison)
THEN IF DF = 0
THEN
(R|E)SI ← (R|E)SI + 4;
(R|E)DI ← (R|E)DI + 4;
ELSE
(R|E)SI ← (R|E)SI – 4;
(R|E)DI ← (R|E)DI – 4;
FI;
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INSTRUCTION SET REFERENCE, A-L
ELSE (* Quadword comparison *)
THEN IF DF = 0
(R|E)SI ← (R|E)SI + 8;
(R|E)DI ← (R|E)DI + 8;
ELSE
(R|E)SI ← (R|E)SI – 8;
(R|E)DI ← (R|E)DI – 8;
FI;
FI;
ELSE (* Non-64-bit Mode *)
IF (byte comparison)
THEN IF DF = 0
THEN
(E)SI ← (E)SI + 1;
(E)DI ← (E)DI + 1;
ELSE
(E)SI ← (E)SI – 1;
(E)DI ← (E)DI – 1;
FI;
ELSE IF (Word comparison)
THEN IF DF = 0
(E)SI ← (E)SI + 2;
(E)DI ← (E)DI + 2;
ELSE
(E)SI ← (E)SI – 2;
(E)DI ← (E)DI – 2;
FI;
ELSE (* Doubleword comparison *)
THEN IF DF = 0
(E)SI ← (E)SI + 4;
(E)DI ← (E)DI + 4;
ELSE
(E)SI ← (E)SI – 4;
(E)DI ← (E)DI – 4;
FI;
FI;
FI;
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
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INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
3-172 Vol. 2A
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands
INSTRUCTION SET REFERENCE, A-L
CMPSD—Compare Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F C2 /r ib
CMPSD xmm1, xmm2/m64, imm8
VEX.NDS.128.F2.0F.WIG C2 /r ib
VCMPSD xmm1, xmm2,
xmm3/m64, imm8
EVEX.NDS.LIG.F2.0F.W1 C2 /r ib
VCMPSD k1 {k2}, xmm2,
xmm3/m64{sae}, imm8
RVMI
V/V
AVX
T1S
V/V
AVX512F
Description
Compare low double-precision floating-point value in
xmm2/m64 and xmm1 using bits 2:0 of imm8 as comparison
predicate.
Compare low double-precision floating-point value in
xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison
predicate.
Compare low double-precision floating-point value in
xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison
predicate with writemask k2 and leave the result in mask
register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Compares the low double-precision floating-point values in the second source operand and the first source operand
and returns the results in of the comparison to the destination operand. The comparison predicate operand (immediate operand) specifies the type of comparison performed.
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The
second source operand (second operand) can be an XMM register or 64-bit memory location. Bits (MAX_VL-1:64)
of the corresponding YMM destination register remain unchanged. The comparison result is a quadword mask of all
1s (comparison true) or all 0s (comparison false).
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 64-bit memory location. The result is stored in the low quadword of the destination operand; the high quadword is filled with the contents of the high quadword of the first
source operand. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed. The comparison result is a quadword mask of all 1s (comparison true) or all 0s (comparison false).
EVEX encoded version: The first source operand (second operand) is an XMM register. The second source operand
can be a XMM register or a 64-bit memory location. The destination operand (first operand) is an opmask register.
The comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false), written to the destination
starting from the LSB according to the writemask k2. Bits (MAX_KL-1:128) of the destination register are cleared.
The comparison predicate operand is an 8-bit immediate:
•
For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison to be performed (see
Table 3-1). Bits 5 through 7 of the immediate are reserved.
•
For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see
the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
The unordered relationship is true when at least one of the two source operands being compared is a NaN; the
ordered relationship is true when neither source operand is a NaN.
A subsequent computational instruction that uses the mask result in the destination operand as an input operand
will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask
of all 1s corresponds to a QNaN.
Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”,
“not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either
by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison)
CMPSD—Compare Scalar Double-Precision Floating-Point Value
Vol. 2A 3-173
INSTRUCTION SET REFERENCE, A-L
or by using software emulation. When using software emulation, the program must swap the operands (copying
registers when necessary to protect the data that will now be in the destination), and then perform the compare
using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7
(Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2A) under the heading Emulation.
Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand
CMPSD instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-6. Compiler should treat reserved
Imm8 values as illegal syntax.
Table 3-6. Pseudo-Op and CMPSD Implementation
:
Pseudo-Op
CMPSD Implementation
CMPEQSD xmm1, xmm2
CMPSD xmm1, xmm2, 0
CMPLTSD xmm1, xmm2
CMPSD xmm1, xmm2, 1
CMPLESD xmm1, xmm2
CMPSD xmm1, xmm2, 2
CMPUNORDSD xmm1, xmm2
CMPSD xmm1, xmm2, 3
CMPNEQSD xmm1, xmm2
CMPSD xmm1, xmm2, 4
CMPNLTSD xmm1, xmm2
CMPSD xmm1, xmm2, 5
CMPNLESD xmm1, xmm2
CMPSD xmm1, xmm2, 6
CMPORDSD xmm1, xmm2
CMPSD xmm1, xmm2, 7
The greater-than relations that the processor does not implement require more than one instruction to emulate in
software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to
the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-7, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand
pseudo-ops in addition to the four-operand VCMPSD instruction. See Table 3-7, where the notations of reg1 reg2,
and reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal
syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSD instructions
in a similar fashion by extending the syntax listed in Table 3-7.
Table 3-7. Pseudo-Op and VCMPSD Implementation
:
Pseudo-Op
CMPSD Implementation
VCMPEQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0
VCMPLTSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1
VCMPLESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 2
VCMPUNORDSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 3
VCMPNEQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 4
VCMPNLTSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 5
VCMPNLESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 6
VCMPORDSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 7
VCMPEQ_UQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 8
VCMPNGESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 9
VCMPNGTSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0AH
VCMPFALSESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0BH
VCMPNEQ_OQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0CH
VCMPGESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0DH
3-174 Vol. 2A
CMPSD—Compare Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
Table 3-7. Pseudo-Op and VCMPSD Implementation
Pseudo-Op
CMPSD Implementation
VCMPGTSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0EH
VCMPTRUESD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 0FH
VCMPEQ_OSSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 10H
VCMPLT_OQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 11H
VCMPLE_OQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 12H
VCMPUNORD_SSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 13H
VCMPNEQ_USSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 14H
VCMPNLT_UQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 15H
VCMPNLE_UQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 16H
VCMPORD_SSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 17H
VCMPEQ_USSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 18H
VCMPNGE_UQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 19H
VCMPNGT_UQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1AH
VCMPFALSE_OSSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1BH
VCMPNEQ_OSSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1CH
VCMPGE_OQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1DH
VCMPGT_OQSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1EH
VCMPTRUE_USSD reg1, reg2, reg3
VCMPSD reg1, reg2, reg3, 1FH
Software should ensure VCMPSD is encoded with VEX.L=0. Encoding VCMPSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
Operation
CASE (COMPARISON PREDICATE) OF
0: OP3 EQ_OQ; OP5 EQ_OQ;
1: OP3 LT_OS; OP5 LT_OS;
2: OP3 LE_OS; OP5 LE_OS;
3: OP3 UNORD_Q; OP5 UNORD_Q;
4: OP3 NEQ_UQ; OP5 NEQ_UQ;
5: OP3 NLT_US; OP5 NLT_US;
6: OP3 NLE_US; OP5 NLE_US;
7: OP3 ORD_Q; OP5 ORD_Q;
8: OP5 EQ_UQ;
9: OP5 NGE_US;
10: OP5 NGT_US;
11: OP5 FALSE_OQ;
12: OP5 NEQ_OQ;
13: OP5 GE_OS;
14: OP5 GT_OS;
15: OP5 TRUE_UQ;
16: OP5 EQ_OS;
17: OP5 LT_OQ;
18: OP5 LE_OQ;
19: OP5 UNORD_S;
20: OP5 NEQ_US;
21: OP5 NLT_UQ;
CMPSD—Compare Scalar Double-Precision Floating-Point Value
Vol. 2A 3-175
INSTRUCTION SET REFERENCE, A-L
22: OP5 NLE_UQ;
23: OP5 ORD_S;
24: OP5 EQ_US;
25: OP5 NGE_UQ;
26: OP5 NGT_UQ;
27: OP5 FALSE_OS;
28: OP5 NEQ_OS;
29: OP5 GE_OQ;
30: OP5 GT_OQ;
31: OP5 TRUE_US;
DEFAULT: Reserved
ESAC;
VCMPSD (EVEX encoded version)
CMP0  SRC1[63:0] OP5 SRC2[63:0];
IF k2[0] or *no writemask*
THEN
IF CMP0 = TRUE
THEN DEST[0]  1;
ELSE DEST[0]  0; FI;
ELSE
DEST[0]  0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1]  0
CMPSD (128-bit Legacy SSE version)
CMP0 DEST[63:0] OP3 SRC[63:0];
IF CMP0 = TRUE
THEN DEST[63:0] FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] 0000000000000000H; FI;
DEST[MAX_VL-1:64] (Unmodified)
VCMPSD (VEX.128 encoded version)
CMP0 SRC1[63:0] OP5 SRC2[63:0];
IF CMP0 = TRUE
THEN DEST[63:0] FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] 0000000000000000H; FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCMPSD __mmask8 _mm_cmp_sd_mask( __m128d a, __m128d b, int imm);
VCMPSD __mmask8 _mm_cmp_round_sd_mask( __m128d a, __m128d b, int imm, int sae);
VCMPSD __mmask8 _mm_mask_cmp_sd_mask( __mmask8 k1, __m128d a, __m128d b, int imm);
VCMPSD __mmask8 _mm_mask_cmp_round_sd_mask( __mmask8 k1, __m128d a, __m128d b, int imm, int sae);
(V)CMPSD __m128d _mm_cmp_sd(__m128d a, __m128d b, const int imm)
SIMD Floating-Point Exceptions
Invalid if SNaN operand, Invalid if QNaN and predicate as listed in Table 3-1 Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-176 Vol. 2A
CMPSD—Compare Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CMPSS—Compare Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RMI
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F C2 /r ib
CMPSS xmm1, xmm2/m32, imm8
VEX.NDS.128.F3.0F.WIG C2 /r ib
VCMPSS xmm1, xmm2, xmm3/m32,
imm8
EVEX.NDS.LIG.F3.0F.W0 C2 /r ib
VCMPSS k1 {k2}, xmm2,
xmm3/m32{sae}, imm8
RVMI
V/V
AVX
T1S
V/V
AVX512F
Description
Compare low single-precision floating-point value in
xmm2/m32 and xmm1 using bits 2:0 of imm8 as
comparison predicate.
Compare low single-precision floating-point value in
xmm3/m32 and xmm2 using bits 4:0 of imm8 as
comparison predicate.
Compare low single-precision floating-point value in
xmm3/m32 and xmm2 using bits 4:0 of imm8 as
comparison predicate with writemask k2 and leave the
result in mask register k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RMI
ModRM:reg (r, w)
ModRM:r/m (r)
Imm8
NA
RVMI
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
Imm8
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
Imm8
Description
Compares the low single-precision floating-point values in the second source operand and the first source operand
and returns the results of the comparison to the destination operand. The comparison predicate operand (immediate operand) specifies the type of comparison performed.
128-bit Legacy SSE version: The first source and destination operand (first operand) is an XMM register. The
second source operand (second operand) can be an XMM register or 32-bit memory location. Bits (MAX_VL-1:32)
of the corresponding YMM destination register remain unchanged. The comparison result is a doubleword mask of
all 1s (comparison true) or all 0s (comparison false).
VEX.128 encoded version: The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 32-bit memory location. The result is stored in the low 32 bits
of the destination operand; bits 128:32 of the destination operand are copied from the first source operand. Bits
(MAX_VL-1:128) of the destination ZMM register are zeroed. The comparison result is a doubleword mask of all 1s
(comparison true) or all 0s (comparison false).
EVEX encoded version: The first source operand (second operand) is an XMM register. The second source operand
can be a XMM register or a 32-bit memory location. The destination operand (first operand) is an opmask register.
The comparison result is a single mask bit of 1 (comparison true) or 0 (comparison false), written to the destination
starting from the LSB according to the writemask k2. Bits (MAX_KL-1:128) of the destination register are cleared.
The comparison predicate operand is an 8-bit immediate:
•
For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison to be performed (see
Table 3-1). Bits 5 through 7 of the immediate are reserved.
•
For instruction encodings that do not use VEX prefix, bits 2:0 define the type of comparison to be made (see
the first 8 rows of Table 3-1). Bits 3 through 7 of the immediate are reserved.
The unordered relationship is true when at least one of the two source operands being compared is a NaN; the
ordered relationship is true when neither source operand is a NaN.
A subsequent computational instruction that uses the mask result in the destination operand as an input operand
will not generate an exception, because a mask of all 0s corresponds to a floating-point value of +0.0 and a mask
of all 1s corresponds to a QNaN.
Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”, “greater-than-or-equal”,
“not-greater than”, and “not-greater-than-or-equal relations” predicates. These comparisons can be made either
CMPSS—Compare Scalar Single-Precision Floating-Point Value
Vol. 2A 3-177
INSTRUCTION SET REFERENCE, A-L
by using the inverse relationship (that is, use the “not-less-than-or-equal” to make a “greater-than” comparison)
or by using software emulation. When using software emulation, the program must swap the operands (copying
registers when necessary to protect the data that will now be in the destination), and then perform the compare
using a different predicate. The predicate to be used for these emulations is listed in the first 8 rows of Table 3-7
(Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 2A) under the heading Emulation.
Compilers and assemblers may implement the following two-operand pseudo-ops in addition to the three-operand
CMPSS instruction, for processors with “CPUID.1H:ECX.AVX =0”. See Table 3-8. Compiler should treat reserved
Imm8 values as illegal syntax.
Table 3-8. Pseudo-Op and CMPSS Implementation
:
Pseudo-Op
CMPSS Implementation
CMPEQSS xmm1, xmm2
CMPSS xmm1, xmm2, 0
CMPLTSS xmm1, xmm2
CMPSS xmm1, xmm2, 1
CMPLESS xmm1, xmm2
CMPSS xmm1, xmm2, 2
CMPUNORDSS xmm1, xmm2
CMPSS xmm1, xmm2, 3
CMPNEQSS xmm1, xmm2
CMPSS xmm1, xmm2, 4
CMPNLTSS xmm1, xmm2
CMPSS xmm1, xmm2, 5
CMPNLESS xmm1, xmm2
CMPSS xmm1, xmm2, 6
CMPORDSS xmm1, xmm2
CMPSS xmm1, xmm2, 7
The greater-than relations that the processor does not implement require more than one instruction to emulate in
software and therefore should not be implemented as pseudo-ops. (For these, the programmer should reverse the
operands of the corresponding less than relations and use move instructions to ensure that the mask is moved to
the correct destination register and that the source operand is left intact.)
Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates shown in Table 3-7, software emulation is no longer needed. Compilers and assemblers may implement the following three-operand
pseudo-ops in addition to the four-operand VCMPSS instruction. See Table 3-9, where the notations of reg1 reg2,
and reg3 represent either XMM registers or YMM registers. Compiler should treat reserved Imm8 values as illegal
syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined constants to support a simpler intrinsic interface. Compilers and assemblers may implement three-operand pseudo-ops for EVEX encoded VCMPSS instructions
in a similar fashion by extending the syntax listed in Table 3-9.
Table 3-9. Pseudo-Op and VCMPSS Implementation
:
Pseudo-Op
CMPSS Implementation
VCMPEQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0
VCMPLTSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1
VCMPLESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 2
VCMPUNORDSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 3
VCMPNEQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 4
VCMPNLTSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 5
VCMPNLESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 6
VCMPORDSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 7
VCMPEQ_UQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 8
VCMPNGESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 9
VCMPNGTSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0AH
VCMPFALSESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0BH
VCMPNEQ_OQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0CH
VCMPGESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0DH
3-178 Vol. 2A
CMPSS—Compare Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
Table 3-9. Pseudo-Op and VCMPSS Implementation
Pseudo-Op
CMPSS Implementation
VCMPGTSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0EH
VCMPTRUESS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 0FH
VCMPEQ_OSSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 10H
VCMPLT_OQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 11H
VCMPLE_OQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 12H
VCMPUNORD_SSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 13H
VCMPNEQ_USSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 14H
VCMPNLT_UQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 15H
VCMPNLE_UQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 16H
VCMPORD_SSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 17H
VCMPEQ_USSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 18H
VCMPNGE_UQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 19H
VCMPNGT_UQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1AH
VCMPFALSE_OSSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1BH
VCMPNEQ_OSSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1CH
VCMPGE_OQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1DH
VCMPGT_OQSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1EH
VCMPTRUE_USSS reg1, reg2, reg3
VCMPSS reg1, reg2, reg3, 1FH
Software should ensure VCMPSS is encoded with VEX.L=0. Encoding VCMPSS with VEX.L=1 may encounter unpredictable behavior across different processor generations.
Operation
CASE (COMPARISON PREDICATE) OF
0: OP3 EQ_OQ; OP5 EQ_OQ;
1: OP3 LT_OS; OP5 LT_OS;
2: OP3 LE_OS; OP5 LE_OS;
3: OP3 UNORD_Q; OP5 UNORD_Q;
4: OP3 NEQ_UQ; OP5 NEQ_UQ;
5: OP3 NLT_US; OP5 NLT_US;
6: OP3 NLE_US; OP5 NLE_US;
7: OP3 ORD_Q; OP5 ORD_Q;
8: OP5 EQ_UQ;
9: OP5 NGE_US;
10: OP5 NGT_US;
11: OP5 FALSE_OQ;
12: OP5 NEQ_OQ;
13: OP5 GE_OS;
14: OP5 GT_OS;
15: OP5 TRUE_UQ;
16: OP5 EQ_OS;
17: OP5 LT_OQ;
18: OP5 LE_OQ;
19: OP5 UNORD_S;
20: OP5 NEQ_US;
21: OP5 NLT_UQ;
CMPSS—Compare Scalar Single-Precision Floating-Point Value
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INSTRUCTION SET REFERENCE, A-L
22: OP5 NLE_UQ;
23: OP5 ORD_S;
24: OP5 EQ_US;
25: OP5 NGE_UQ;
26: OP5 NGT_UQ;
27: OP5 FALSE_OS;
28: OP5 NEQ_OS;
29: OP5 GE_OQ;
30: OP5 GT_OQ;
31: OP5 TRUE_US;
DEFAULT: Reserved
ESAC;
VCMPSS (EVEX encoded version)
CMP0  SRC1[31:0] OP5 SRC2[31:0];
IF k2[0] or *no writemask*
THEN
IF CMP0 = TRUE
THEN DEST[0]  1;
ELSE DEST[0]  0; FI;
ELSE
DEST[0]  0
; zeroing-masking only
FI;
DEST[MAX_KL-1:1]  0
CMPSS (128-bit Legacy SSE version)
CMP0 DEST[31:0] OP3 SRC[31:0];
IF CMP0 = TRUE
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0] 00000000H; FI;
DEST[MAX_VL-1:32] (Unmodified)
VCMPSS (VEX.128 encoded version)
CMP0 SRC1[31:0] OP5 SRC2[31:0];
IF CMP0 = TRUE
THEN DEST[31:0] FFFFFFFFH;
ELSE DEST[31:0] 00000000H; FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
Intel C/C++ Compiler Intrinsic Equivalent
VCMPSS __mmask8 _mm_cmp_ss_mask( __m128 a, __m128 b, int imm);
VCMPSS __mmask8 _mm_cmp_round_ss_mask( __m128 a, __m128 b, int imm, int sae);
VCMPSS __mmask8 _mm_mask_cmp_ss_mask( __mmask8 k1, __m128 a, __m128 b, int imm);
VCMPSS __mmask8 _mm_mask_cmp_round_ss_mask( __mmask8 k1, __m128 a, __m128 b, int imm, int sae);
(V)CMPSS __m128 _mm_cmp_ss(__m128 a, __m128 b, const int imm)
SIMD Floating-Point Exceptions
Invalid if SNaN operand, Invalid if QNaN and predicate as listed in Table 3-1, Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-180 Vol. 2A
CMPSS—Compare Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CMPXCHG—Compare and Exchange
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F B0/r
MR
Valid
Valid*
Compare AL with r/m8. If equal, ZF is set and r8 is loaded into
r/m8. Else, clear ZF and load r/m8 into AL.
MR
Valid
N.E.
Compare AL with r/m8. If equal, ZF is set and r8 is loaded into
r/m8. Else, clear ZF and load r/m8 into AL.
MR
Valid
Valid*
Compare AX with r/m16. If equal, ZF is set and r16 is loaded
into r/m16. Else, clear ZF and load r/m16 into AX.
MR
Valid
Valid*
Compare EAX with r/m32. If equal, ZF is set and r32 is loaded
into r/m32. Else, clear ZF and load r/m32 into EAX.
MR
Valid
N.E.
Compare RAX with r/m64. If equal, ZF is set and r64 is loaded
into r/m64. Else, clear ZF and load r/m64 into RAX.
CMPXCHG r/m8, r8
REX + 0F B0/r
CMPXCHG r/m8**,r8
0F B1/r
CMPXCHG r/m16, r16
0F B1/r
CMPXCHG r/m32, r32
REX.W + 0F B1/r
CMPXCHG r/m64, r64
NOTES:
* See the IA-32 Architecture Compatibility section below.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
MR
ModRM:r/m (r, w)
ModRM:reg (r)
NA
NA
Description
Compares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two
values are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the
destination operand is loaded into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the
interface to the processor’s bus, the destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is
written into the destination. (The processor never produces a locked read without also producing a locked write.)
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
IA-32 Architecture Compatibility
This instruction is not supported on Intel processors earlier than the Intel486 processors.
Operation
(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)
TEMP ← DEST
IF accumulator = TEMP
THEN
ZF ← 1;
DEST ← SRC;
ELSE
ZF ← 0;
accumulator ← TEMP;
DEST ← TEMP;
FI;
CMPXCHG—Compare and Exchange
Vol. 2A 3-181
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is
cleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.
Protected Mode Exceptions
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-182 Vol. 2A
CMPXCHG—Compare and Exchange
INSTRUCTION SET REFERENCE, A-L
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F C7 /1 m64
M
Valid
Valid*
Compare EDX:EAX with m64. If equal, set ZF and load
ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.
M
Valid
N.E.
Compare RDX:RAX with m128. If equal, set ZF and load
RCX:RBX into m128. Else, clear ZF and load m128 into
RDX:RAX.
CMPXCHG8B m64
REX.W + 0F C7 /1 m128
CMPXCHG16B m128
NOTES:
*See IA-32 Architecture Compatibility section below.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
Description
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand
(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored
in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX).
The destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For
the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the
low-order 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the highorder 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the
interface to the processor’s bus, the destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is
written into the destination. (The processor never produces a locked read without also producing a locked write.)
In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that
CMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the
beginning of this section for encoding data and limits. For information on the CPUID flag that indicates
CMPXCHG16B, see page 3-206.
IA-32 Architecture Compatibility
This instruction encoding is not supported on Intel processors earlier than the Pentium processors.
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
Vol. 2A 3-183
INSTRUCTION SET REFERENCE, A-L
Operation
IF (64-Bit Mode and OperandSize = 64)
THEN
TEMP128 ← DEST
IF (RDX:RAX = TEMP128)
THEN
ZF ← 1;
DEST ← RCX:RBX;
ELSE
ZF ← 0;
RDX:RAX ← TEMP128;
DEST ← TEMP128;
FI;
FI
ELSE
TEMP64 ← DEST;
IF (EDX:EAX = TEMP64)
THEN
ZF ← 1;
DEST ← ECX:EBX;
ELSE
ZF ← 0;
EDX:EAX ← TEMP64;
DEST ← TEMP64;
FI;
FI;
FI;
Flags Affected
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and
OF flags are unaffected.
Protected Mode Exceptions
#UD
If the destination is not a memory operand.
#GP(0)
If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
Real-Address Mode Exceptions
#UD
If the destination operand is not a memory location.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
3-184 Vol. 2A
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
INSTRUCTION SET REFERENCE, A-L
Virtual-8086 Mode Exceptions
#UD
If the destination operand is not a memory location.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
If memory operand for CMPXCHG16B is not aligned on a 16-byte boundary.
If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.
#UD
If the destination operand is not a memory location.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes
Vol. 2A 3-185
INSTRUCTION SET REFERENCE, A-L
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 2F /r
COMISD xmm1, xmm2/m64
VEX.128.66.0F.WIG 2F /r
VCOMISD xmm1, xmm2/m64
RM
V/V
AVX
EVEX.LIG.66.0F.W1 2F /r
VCOMISD xmm1, xmm2/m64{sae}
T1S
V/V
AVX512F
Description
Compare low double-precision floating-point values in
xmm1 and xmm2/mem64 and set the EFLAGS flags
accordingly.
Compare low double-precision floating-point values in
xmm1 and xmm2/mem64 and set the EFLAGS flags
accordingly.
Compare low double-precision floating-point values in
xmm1 and xmm2/mem64 and set the EFLAGS flags
accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Compares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and
operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point
invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals
an invalid numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
COMISD (all versions)
RESULT OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF  111;
GREATER_THAN: ZF,PF,CF  000;
LESS_THAN: ZF,PF,CF  001;
EQUAL: ZF,PF,CF  100;
ESAC;
OF, AF, SF 0; }
3-186 Vol. 2A
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)
VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comile_sd (__m128d a, __m128d b)
VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comige_sd (__m128d a, __m128d b)
VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)
SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
Vol. 2A 3-187
INSTRUCTION SET REFERENCE, A-L
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 2F /r
COMISS xmm1, xmm2/m32
VEX.128.0F.WIG 2F /r
VCOMISS xmm1, xmm2/m32
RM
V/V
AVX
EVEX.LIG.0F.W0 2F /r
VCOMISS xmm1, xmm2/m32{sae}
T1S
V/V
AVX512F
Description
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Compare low single-precision floating-point values in
xmm1 and xmm2/mem32 and set the EFLAGS flags
accordingly.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1S
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Compares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered,
greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result
is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.
The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
COMISS (all versions)
RESULT OrderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
UNORDERED: ZF,PF,CF  111;
GREATER_THAN: ZF,PF,CF  000;
LESS_THAN: ZF,PF,CF  001;
EQUAL: ZF,PF,CF  100;
ESAC;
OF, AF, SF  0; }
3-188 Vol. 2A
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
VCOMISS int _mm_comieq_ss (__m128 a, __m128 b)
VCOMISS int _mm_comilt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comile_ss (__m128 a, __m128 b)
VCOMISS int _mm_comigt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comige_ss (__m128 a, __m128 b)
VCOMISS int _mm_comineq_ss (__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
Vol. 2A 3-189
INSTRUCTION SET REFERENCE, A-L
CPUID—CPU Identification
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F A2
CPUID
NP
Valid
Valid
Returns processor identification and feature
information to the EAX, EBX, ECX, and EDX
registers, as determined by input entered in
EAX (in some cases, ECX as well).
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction operates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The
instruction’s output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well).
For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value
and the Vendor Identification String in the appropriate registers:
MOV EAX, 00H
CPUID
Table 3-8 shows information returned, depending on the initial value loaded into the EAX register.
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX
is higher than the maximum input value for basic or extended function for that processor then the data for the
highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:
CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)
CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)
If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution
guarantees that any modifications to flags, registers, and memory for previous instructions are completed before
the next instruction is fetched and executed.
See also:
“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.
3-190 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction
Initial EAX
Value
Information Provided about the Processor
Basic CPUID Information
0H
01H
EAX
Maximum Input Value for Basic CPUID Information.
EBX
“Genu”
ECX
“ntel”
EDX
“ineI”
EAX
Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).
EBX
Bits 07 - 00: Brand Index.
Bits 15 - 08: CLFLUSH line size (Value ∗ 8 = cache line size in bytes; used also by CLFLUSHOPT).
Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*.
Bits 31 - 24: Initial APIC ID.
ECX
Feature Information (see Figure 3-7 and Table 3-10).
EDX
Feature Information (see Figure 3-8 and Table 3-11).
NOTES:
* The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC
IDs reserved for addressing different logical processors in a physical package. This field is only valid if
CPUID.1.EDX.HTT[bit 28]= 1.
02H
03H
EAX
Cache and TLB Information (see Table 3-12).
EBX
Cache and TLB Information.
ECX
Cache and TLB Information.
EDX
Cache and TLB Information.
EAX
Reserved.
EBX
Reserved.
ECX
Bits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
EDX
Bits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
value in this register is reserved.)
NOTES:
Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use
the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.
CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.
Deterministic Cache Parameters Leaf
04H
NOTES:
Leaf 04H output depends on the initial value in ECX.*
See also: “INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level” on page 214.
EAX
CPUID—CPU Identification
Bits 04 - 00: Cache Type Field.
0 = Null - No more caches.
1 = Data Cache.
2 = Instruction Cache.
3 = Unified Cache.
4-31 = Reserved.
Vol. 2A 3-191
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Bits 07 - 05: Cache Level (starts at 1).
Bit 08: Self Initializing cache level (does not need SW initialization).
Bit 09: Fully Associative cache.
Bits 13 - 10: Reserved.
Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**, ***.
Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical
package**, ****, *****.
EBX
Bits 11 - 00: L = System Coherency Line Size**.
Bits 21 - 12: P = Physical Line partitions**.
Bits 31 - 22: W = Ways of associativity**.
ECX
Bits 31-00: S = Number of Sets**.
EDX
Bit 00: Write-Back Invalidate/Invalidate.
0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this
cache.
1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing
this cache.
Bit 01: Cache Inclusiveness.
0 = Cache is not inclusive of lower cache levels.
1 = Cache is inclusive of lower cache levels.
Bit 02: Complex Cache Indexing.
0 = Direct mapped cache.
1 = A complex function is used to index the cache, potentially using all address bits.
Bits 31 - 03: Reserved = 0.
NOTES:
* If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if subleaf n returns EAX[4:0] as 0.
** Add one to the return value to get the result.
***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache.
**** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique
Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of
bits of the initial APIC ID.
***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.
MONITOR/MWAIT Leaf
05H
EAX
Bits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
EBX
Bits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity).
Bits 31 - 16: Reserved = 0.
ECX
Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.
Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.
Bits 31 - 02: Reserved.
3-192 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
EDX
Bits 03 - 00: Number of C0* sub C-states supported using MWAIT.
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT.
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT.
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT.
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT.
Bits 23 - 20: Number of C5* sub C-states supported using MWAIT.
Bits 27 - 24: Number of C6* sub C-states supported using MWAIT.
Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.
NOTE:
* The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI Cstates.
Thermal and Power Management Leaf
06H
EAX
Bit 00: Digital temperature sensor is supported if set.
Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).
Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
Bit 03: Reserved.
Bit 04: PLN. Power limit notification controls are supported if set.
Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
Bit 06: PTM. Package thermal management is supported if set.
Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,
IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
Bit 12: Reserved.
Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are
supported if set.
Bits 31 - 15: Reserved.
EBX
Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.
Bits 31 - 04: Reserved.
ECX
Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The
capability to provide a measure of delivered processor performance (since last reset of the counters), as
a percentage of the expected processor performance when running at the TSC frequency.
Bits 02 - 01: Reserved = 0.
Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set
and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
Bits 31 - 04: Reserved = 0.
EDX
Reserved = 0.
CPUID—CPU Identification
Vol. 2A 3-193
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)
07H
Sub-leaf 0 (Input ECX = 0). *
EAX
Bits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.
EBX
Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
Bit 01: IA32_TSC_ADJUST MSR is supported if 1.
Bit 02: SGX. Supports Intel® Software Guard Extensions (Intel® SGX Extensions) if 1.
Bit 03: BMI1.
Bit 04: HLE.
Bit 05: AVX2.
Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.
Bit 08: BMI2.
Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.
Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context
identifiers.
Bit 11: RTM.
Bit 12: RDT-M. Supports Intel® Resource Director Technology (Intel® RDT) Monitoring capability if 1.
Bit 13: Deprecates FPU CS and FPU DS values if 1.
Bit 14: MPX. Supports Intel® Memory Protection Extensions if 1.
Bit 15: RDT-A. Supports Intel® Resource Director Technology (Intel® RDT) Allocation capability if 1.
Bits 17:16: Reserved.
Bit 18: RDSEED.
Bit 19: ADX.
Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
Bits 22 - 21: Reserved.
Bit 23: CLFLUSHOPT.
Bit 24: CLWB.
Bit 25: Intel Processor Trace.
Bits 28 - 26: Reserved.
Bit 29: SHA. supports Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) if 1.
Bits 31 - 30: Reserved.
ECX
Bit 00: PREFETCHWT1.
Bit 01: Reserved.
Bit 02: UMIP. Supports user-mode instruction prevention if 1.
Bit 03: PKU. Supports protection keys for user-mode pages if 1.
Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).
Bits 16 - 5: Reserved.
Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
Bit 22: RDPID. Supports Read Processor ID if 1.
Bits 29 - 23: Reserved.
Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.
Bit 31: Reserved.
EDX
Reserved.
NOTE:
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
exceeds the value that sub-leaf 0 returns in EAX.
3-194 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Direct Cache Access Information Leaf
09H
EAX
Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
EBX
Reserved.
ECX
Reserved.
EDX
Reserved.
Architectural Performance Monitoring Leaf
0AH
EAX
Bits 07 - 00: Version ID of architectural performance monitoring.
Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor.
Bits 23 - 16: Bit width of general-purpose, performance monitoring counter.
Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events.
EBX
Bit 00: Core cycle event not available if 1.
Bit 01: Instruction retired event not available if 1.
Bit 02: Reference cycles event not available if 1.
Bit 03: Last-level cache reference event not available if 1.
Bit 04: Last-level cache misses event not available if 1.
Bit 05: Branch instruction retired event not available if 1.
Bit 06: Branch mispredict retired event not available if 1.
Bits 31 - 07: Reserved = 0.
ECX
Reserved = 0.
EDX
Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1).
Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID > 1).
Reserved = 0.
Extended Topology Enumeration Leaf
0BH
NOTES:
Most of Leaf 0BH output depends on the initial value in ECX.
The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.
Output value in ECX[7:0] always equals input value in ECX[7:0].
For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.
If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >
n also return 0 in ECX[15:8].
EAX
Bits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.
All logical processors with the same next level ID share current level.
Bits 31 - 05: Reserved.
EBX
Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped
by Intel**.
Bits 31- 16: Reserved.
ECX
Bits 07 - 00: Level number. Same value in ECX input.
Bits 15 - 08: Level type***.
Bits 31 - 16: Reserved.
EDX
Bits 31- 00: x2APIC ID the current logical processor.
NOTES:
* Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
CPUID—CPU Identification
Vol. 2A 3-195
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this
field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors
available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software
and platform hardware configurations.
*** The value of the “level type” field is not related to level numbers in any way, higher “level type” values do not mean higher levels. Level type field has the following encoding:
0: Invalid.
1: SMT.
2: Core.
3-255: Reserved.
Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)
0DH
NOTES:
Leaf 0DH main leaf (ECX = 0).
EAX
Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if
EAX[n] is 1.
Bit 00: x87 state.
Bit 01: SSE state.
Bit 02: AVX state.
Bits 04 - 03: MPX state.
Bits 07 - 05: AVX-512 state.
Bit 08: Used for IA32_XSS.
Bit 09: PKRU state.
Bits 31 - 10: Reserved.
EBX
Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by
enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area
are not enabled.
ECX
Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the
XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in
XCR0.
EDX
Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if
EDX[n] is 1.
Bits 31 - 00: Reserved.
Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
0DH
3-196 Vol. 2A
EAX
Bit 00: XSAVEOPT is available.
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
Bit 02: Supports XGETBV with ECX = 1 if set.
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
Bits 31 - 04: Reserved.
EBX
Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
ECX
Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be
set to 1 only if ECX[n] is 1.
Bits 07 - 00: Used for XCR0.
Bit 08: PT state.
Bit 09: Used for XCR0.
Bits 31 - 10: Reserved.
EDX
Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can
be set to 1 only if EDX[n] is 1.
Bits 31 - 00: Reserved.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
0DH
NOTES:
Leaf 0DH output depends on the initial value in ECX.
Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the
XCR0 register or the IA32_XSS MSR.
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 ≤ n ≤ 31) is invalid
if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 ≤ n ≤ 63) is invalid if
sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
EAX
Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state
feature associated with a valid sub-leaf index, n.
EBX
Bits 31 - 0: The offset in bytes of this extended state component’s save area from the beginning of the
XSAVE/XRSTOR area.
This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
ECX
Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear
if bit n is instead supported in XCR0.
Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component
located on the next 64-byte boundary following the preceding state component (otherwise, it is located
immediately following the preceding state component).
Bits 31 - 02 are reserved.
This field reports 0 if the sub-leaf index, n, is invalid*.
EDX
This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.
EAX
Reserved.
EBX
Bits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.
ECX
Reserved.
EDX
Bit 00: Reserved.
Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.
Bits 31 - 02: Reserved.
L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)
0FH
NOTES:
Leaf 0FH output depends on the initial value in ECX.
EAX
Reserved.
EBX
Bits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
ECX
Maximum range (zero-based) of RMID of this resource type.
EDX
Bit 00: Supports L3 occupancy monitoring if 1.
Bit 01: Supports L3 Total Bandwidth monitoring if 1.
Bit 02: Supports L3 Local Bandwidth monitoring if 1.
Bits 31 - 03: Reserved.
CPUID—CPU Identification
Vol. 2A 3-197
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.
EAX
Reserved.
EBX
Bit 00: Reserved.
Bit 01: Supports L3 Cache Allocation Technology if 1.
Bit 02: Supports L2 Cache Allocation Technology if 1.
Bits 31 - 03: Reserved.
ECX
Reserved.
EDX
Reserved.
L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAX
Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
Bits 31 - 05: Reserved.
EBX
Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECX
Bit 00: Reserved.
Bit 01: Updates of COS should be infrequent if 1.
Bit 02: Code and Data Prioritization Technology supported if 1.
Bits 31 - 03: Reserved.
EDX
Bits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)
10H
NOTES:
Leaf 10H output depends on the initial value in ECX.
EAX
Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
Bits 31 - 05: Reserved.
EBX
Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
ECX
Bits 31 - 00: Reserved.
EDX
Bits 15 - 00: Highest COS number supported for this ResID.
Bits 31 - 16: Reserved.
Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)
NOTES:
Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
12H
3-198 Vol. 2A
EAX
Bit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions.
Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions.
Bit 31 - 02: Reserved.
EBX
Bit 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.
ECX
Bit 31 - 00: Reserved.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
EDX
Bit 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is
2^(EDX[7:0]).
Bit 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]).
Bits 31 - 16: Reserved.
Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)
NOTES:
Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
12H
EAX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.
EBX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.
ECX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.
EDX
Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.
Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
NOTES:
Leaf 12H sub-leaf 2 or higher (ECX >= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type
listed below.
12H
EAX
Bit 03 - 00: Sub-leaf Type
0000b: Indicates this sub-leaf is invalid.
0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the
Enclave Page Cache (EPC) section.
All other type encodings are reserved.
Type
0000b. This sub-leaf is invalid.
EDX:ECX:EBX:EAX return 0.
Type
0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.
EAX[11:04]: Reserved (enumerate 0).
EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.
EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section.
EBX[31:20]: Reserved.
ECX[03:00]: EPC section property encoding defined as follows:
If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
If EAX[3:0] 0001b, then this section has confidentiality and integrity protection.
All other encodings are reserved.
ECX[11:04]: Reserved (enumerate 0).
ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved
Memory.
EDX[31:20]: Reserved.
CPUID—CPU Identification
Vol. 2A 3-199
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)
NOTES:
Leaf 14H main leaf (ECX = 0).
14H
EAX
Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.
EBX
Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH
MSR can be accessed.
Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.
Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across
warm reset.
Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.
Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and
IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.
Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn),
enabling Power Event Trace packet generation.
Bit 31 - 06: Reserved.
ECX
Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output
scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.
Bit 02: If 1, indicates support of Single-Range Output scheme.
Bit 03: If 1, indicates support of output to Trace Transport subsystem.
Bit 30 - 04: Reserved.
Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base component.
EDX
Bits 31 - 00: Reserved.
Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)
14H
EAX
Bits 02 - 00: Number of configurable Address Ranges for filtering.
Bits 15 - 03: Reserved.
Bits 31 - 16: Bitmap of supported MTC period encodings.
EBX
Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings.
Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.
ECX
Bits 31 - 00: Reserved.
EDX
Bits 31 - 00: Reserved.
Time Stamp Counter and Nominal Core Crystal Clock Information Leaf
15H
3-200 Vol. 2A
NOTES:
If EBX[31:0] is 0, the TSC/”core crystal clock” ratio is not enumerated.
EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
If ECX is 0, the nominal core crystal clock frequency is not enumerated.
“TSC frequency” = “core crystal clock frequency” * EBX/EAX.
The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
EAX
Bits 31 - 00: An unsigned integer which is the denominator of the TSC/”core crystal clock” ratio.
EBX
Bits 31 - 00: An unsigned integer which is the numerator of the TSC/”core crystal clock” ratio.
ECX
Bits 31 - 00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.
EDX
Bits 31 - 00: Reserved = 0.
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
Processor Frequency Information Leaf
16H
EAX
Bits 15 - 00: Processor Base Frequency (in MHz).
Bits 31 - 16: Reserved =0.
EBX
Bits 15 - 00: Maximum Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
ECX
Bits 15 - 00: Bus (Reference) Frequency (in MHz).
Bits 31 - 16: Reserved = 0.
EDX
Reserved.
NOTES:
* Data is returned from this interface in accordance with the processor's specification and does not reflect
actual values. Suitable use of this data includes the display of processor information in like manner to the
processor brand string and for determining the appropriate range to use when displaying processor
information e.g. frequency history graphs. The returned information should not be used for any other
purpose as the returned information does not accurately correlate to information / counters returned by
other processor interfaces.
While a processor may support the Processor Frequency Information leaf, fields that return a value of
zero are not supported.
System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)
17H
NOTES:
Leaf 17H main leaf (ECX = 0).
Leaf 17H output depends on the initial value in ECX.
Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.
Leaf 17H is valid if MaxSOCID_Index >= 3.
Leaf 17H sub-leaves 4 and above are reserved.
EAX
Bits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
EBX
Bits 15 - 00: SOC Vendor ID.
Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration
scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.
Bits 31 - 17: Reserved = 0.
ECX
Bits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.
EDX
Bits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.
System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)
17H
EAX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EBX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
ECX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
EDX
Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
NOTES:
Leaf 17H output depends on the initial value in ECX.
SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.
The complete SOC Vendor Brand String is constructed by concatenating in ascending order of
EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
CPUID—CPU Identification
Vol. 2A 3-201
INSTRUCTION SET REFERENCE, A-L
Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX > MaxSOCID_Index)
17H
NOTES:
Leaf 17H output depends on the initial value in ECX.
EAX
Bits 31 - 00: Reserved = 0.
EBX
Bits 31 - 00: Reserved = 0.
ECX
Bits 31 - 00: Reserved = 0.
EDX
Bits 31 - 00: Reserved = 0.
Unimplemented CPUID Leaf Functions
40000000H
4FFFFFFFH
Invalid. No existing or future CPU will return processor identification or feature information if the initial
EAX value is in the range 40000000H to 4FFFFFFFH.
Extended Function CPUID Information
80000000H EAX
Maximum Input Value for Extended Function CPUID Information.
EBX
Reserved.
ECX
Reserved.
EDX
Reserved.
80000001H EAX
Extended Processor Signature and Feature Bits.
EBX
Reserved.
ECX
Bit 00: LAHF/SAHF available in 64-bit mode.
Bits 04 - 01: Reserved.
Bit 05: LZCNT.
Bits 07 - 06: Reserved.
Bit 08: PREFETCHW.
Bits 31 - 09: Reserved.
EDX
Bits 10 - 00: Reserved.
Bit 11: SYSCALL/SYSRET available in 64-bit mode.
Bits 19 - 12: Reserved = 0.
Bit 20: Execute Disable Bit available.
Bits 25 - 21: Reserved = 0.
Bit 26: 1-GByte pages are available if 1.
Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.
Bit 28: Reserved = 0.
Bit 29: Intel® 64 Architecture available if 1.
Bits 31 - 30: Reserved = 0.
80000002H EAX
EBX
ECX
EDX
Processor Brand String.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000003H EAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
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Table 3-8. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value
Information Provided about the Processor
80000004H EAX
EBX
ECX
EDX
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
Processor Brand String Continued.
80000005H EAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Reserved = 0.
80000006H EAX
EBX
Reserved = 0.
Reserved = 0.
ECX
EDX
Bits 07 - 00: Cache Line size in bytes.
Bits 11 - 08: Reserved.
Bits 15 - 12: L2 Associativity field *.
Bits 31 - 16: Cache size in 1K units.
Reserved = 0.
NOTES:
* L2 associativity field encodings:
00H - Disabled.
01H - Direct mapped.
02H - 2-way.
04H - 4-way.
06H - 8-way.
08H - 16-way.
0FH - Fully associative.
80000007H EAX
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
Bits 07 - 00: Reserved = 0.
Bit 08: Invariant TSC available if 1.
Bits 31 - 09: Reserved = 0.
80000008H EAX
Linear/Physical Address size.
Bits 07 - 00: #Physical Address Bits*.
Bits 15 - 08: #Linear Address Bits.
Bits 31 - 16: Reserved = 0.
EBX
ECX
EDX
Reserved = 0.
Reserved = 0.
Reserved = 0.
NOTES:
* If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should
come from this field.
INPUT EAX = 0: Returns CPUID’s Highest Value for Basic Processor Information and the Vendor Identification String
When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for
returning basic processor information. The value is returned in the EAX register and is processor specific.
CPUID—CPU Identification
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INSTRUCTION SET REFERENCE, A-L
A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is “GenuineIntel” and is expressed:
EBX ← 756e6547h (* “Genu”, with G in the low eight bits of BL *)
EDX ← 49656e69h (* “ineI”, with i in the low eight bits of DL *)
ECX ← 6c65746eh (* “ntel”, with n in the low eight bits of CL *)
INPUT EAX = 80000000H: Returns CPUID’s Highest Value for Extended Processor Information
When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recognizes for returning extended processor information. The value is returned in the EAX register and is processor
specific.
IA32_BIOS_SIGN_ID Returns Microcode Update Signature
For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update
signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
INPUT EAX = 01H: Returns Model, Family, Stepping Information
When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example:
model, family, and processor type for the Intel Xeon processor 5100 series is as follows:
•
•
•
Model — 1111B
Family — 0101B
Processor Type — 00B
See Table 3-9 for available processor type values. Stepping IDs are provided as needed.
31
28 27
20 19
Extended
Family ID
EAX
16 15 14 13 12 11
Extended
Model ID
8 7
Family
ID
4
Model
3
0
Stepping
ID
Extended Family ID (0)
Extended Model ID (0)
Processor Type
Family (0FH for the Pentium 4 Processor Family)
Model
Reserved
OM16525
Figure 3-6. Version Information Returned by CPUID in EAX
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Table 3-9. Processor Type Field
Type
Encoding
Original OEM Processor
00B
®
Intel OverDrive Processor
01B
Dual processor (not applicable to Intel486 processors)
10B
Intel reserved
11B
NOTE
See Chapter 19 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,
for information on identifying earlier IA-32 processors.
The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display
using the following rule:
IF Family_ID ≠ 0FH
THEN DisplayFamily = Family_ID;
ELSE DisplayFamily = Extended_Family_ID + Family_ID;
(* Right justify and zero-extend 4-bit field. *)
FI;
(* Show DisplayFamily as HEX field. *)
The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a
display using the following rule:
IF (Family_ID = 06H or Family_ID = 0FH)
THEN DisplayModel = (Extended_Model_ID « 4) + Model_ID;
(* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)
ELSE DisplayModel = Model_ID;
FI;
(* Show DisplayModel as HEX field. *)
INPUT EAX = 01H: Returns Additional Information in EBX
When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:
•
Brand index (low byte of EBX) — this number provides an entry into a brand string table that contains brand
strings for IA-32 processors. More information about this field is provided later in this section.
•
CLFLUSH instruction cache line size (second byte of EBX) — this number indicates the size of the cache line
flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the
Pentium 4 processor.
•
Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the
processor during power up. This field was introduced in the Pentium 4 processor.
INPUT EAX = 01H: Returns Feature Information in ECX and EDX
When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.
•
•
Figure 3-7 and Table 3-10 show encodings for ECX.
Figure 3-8 and Table 3-11 show encodings for EDX.
For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.
NOTE
Software must confirm that a processor feature is present using feature flags returned by CPUID
prior to using the feature. Software should not depend on future offerings retaining all features.
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INSTRUCTION SET REFERENCE, A-L
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
ECX
3 2 1
0
0
RDRAND
F16C
AVX
OSXSAVE
XSAVE
AES
TSC-Deadline
POPCNT
MOVBE
x2APIC
SSE4_2 — SSE4.2
SSE4_1 — SSE4.1
DCA — Direct Cache Access
PCID — Process-context Identifiers
PDCM — Perf/Debug Capability MSR
xTPR Update Control
CMPXCHG16B
FMA — Fused Multiply Add
SDBG
CNXT-ID — L1 Context ID
SSSE3 — SSSE3 Extensions
TM2 — Thermal Monitor 2
EIST — Enhanced Intel SpeedStep® Technology
SMX — Safer Mode Extensions
VMX — Virtual Machine Extensions
DS-CPL — CPL Qualified Debug Store
MONITOR — MONITOR/MWAIT
DTES64 — 64-bit DS Area
PCLMULQDQ — Carryless Multiplication
SSE3 — SSE3 Extensions
OM16524b
Reserved
Figure 3-7. Feature Information Returned in the ECX Register
Table 3-10. Feature Information Returned in the ECX Register
Bit #
Mnemonic
Description
0
SSE3
Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this
technology.
1
PCLMULQDQ
PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.
2
DTES64
64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.
3
MONITOR
MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.
4
DS-CPL
CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the
Debug Store feature to allow for branch message storage qualified by CPL.
5
VMX
Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.
6
SMX
Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See
Chapter 6, “Safer Mode Extensions Reference”.
7
EIST
Enhanced Intel SpeedStep® technology. A value of 1 indicates that the processor supports this
technology.
8
TM2
Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.
9
SSSE3
A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A
value of 0 indicates the instruction extensions are not present in the processor.
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Table 3-10. Feature Information Returned in the ECX Register (Contd.)
Bit #
Mnemonic
Description
10
CNXT-ID
L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode
or shared mode. A value of 0 indicates this feature is not supported. See definition of the
IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
11
SDBG
A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
12
FMA
A value of 1 indicates the processor supports FMA extensions using YMM state.
13
CMPXCHG16B
CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the
“CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes” section in this chapter for a
description.
14
xTPR Update
Control
xTPR Update Control. A value of 1 indicates that the processor supports changing
IA32_MISC_ENABLE[bit 23].
15
PDCM
Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance
and debug feature indication MSR IA32_PERF_CAPABILITIES.
16
Reserved
Reserved
17
PCID
Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that
software may set CR4.PCIDE to 1.
18
DCA
A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped
device.
19
SSE4.1
A value of 1 indicates that the processor supports SSE4.1.
20
SSE4.2
A value of 1 indicates that the processor supports SSE4.2.
21
x2APIC
A value of 1 indicates that the processor supports x2APIC feature.
22
MOVBE
A value of 1 indicates that the processor supports MOVBE instruction.
23
POPCNT
A value of 1 indicates that the processor supports the POPCNT instruction.
24
TSC-Deadline
A value of 1 indicates that the processor’s local APIC timer supports one-shot operation using a
TSC deadline value.
25
AESNI
A value of 1 indicates that the processor supports the AESNI instruction extensions.
26
XSAVE
A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states
feature, the XSETBV/XGETBV instructions, and XCR0.
27
OSXSAVE
A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV
instructions to access XCR0 and to support processor extended state management using
XSAVE/XRSTOR.
28
AVX
A value of 1 indicates the processor supports the AVX instruction extensions.
29
F16C
A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.
30
RDRAND
A value of 1 indicates that processor supports RDRAND instruction.
31
Not Used
Always returns 0.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
EDX
PBE–Pend. Brk. EN.
TM–Therm. Monitor
HTT–Multi-threading
SS–Self Snoop
SSE2–SSE2 Extensions
SSE–SSE Extensions
FXSR–FXSAVE/FXRSTOR
MMX–MMX Technology
ACPI–Thermal Monitor and Clock Ctrl
DS–Debug Store
CLFSH–CLFLUSH instruction
PSN–Processor Serial Number
PSE-36 – Page Size Extension
PAT–Page Attribute Table
CMOV–Conditional Move/Compare Instruction
MCA–Machine Check Architecture
PGE–PTE Global Bit
MTRR–Memory Type Range Registers
SEP–SYSENTER and SYSEXIT
APIC–APIC on Chip
CX8–CMPXCHG8B Inst.
MCE–Machine Check Exception
PAE–Physical Address Extensions
MSR–RDMSR and WRMSR Support
TSC–Time Stamp Counter
PSE–Page Size Extensions
DE–Debugging Extensions
VME–Virtual-8086 Mode Enhancement
FPU–x87 FPU on Chip
Reserved
OM16523
Figure 3-8. Feature Information Returned in the EDX Register
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INSTRUCTION SET REFERENCE, A-L
Table 3-11. More on Feature Information Returned in the EDX Register
Bit #
Mnemonic
Description
0
FPU
Floating Point Unit On-Chip. The processor contains an x87 FPU.
1
VME
Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the
feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS
with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
2
DE
Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional
trapping of accesses to DR4 and DR5.
3
PSE
Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the
feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and
PTEs.
4
TSC
Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
5
MSR
Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are
supported. Some of the MSRs are implementation dependent.
6
PAE
Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table
entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of
4 Mbyte pages if PAE bit is 1.
7
MCE
Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the
feature. This feature does not define the model-specific implementations of machine-check error logging,
reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor
version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
8
CX8
CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly
locked and atomic).
9
APIC
APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to
memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some
processors permit the APIC to be relocated).
10
Reserved
Reserved
11
SEP
SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.
12
MTRR
Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe
what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are
supported.
13
PGE
Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries
that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
14
MCA
Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine
errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting
MSRs are supported.
15
CMOV
Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is
present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
16
PAT
Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range
Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear
address on a 4KB granularity.
17
PSE-36
36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with
32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in
bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to
40 bits in size.
18
PSN
Processor Serial Number. The processor supports the 96-bit processor identification number feature and the
feature is enabled.
19
CLFSH
CLFLUSH Instruction. CLFLUSH Instruction is supported.
20
Reserved
Reserved
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INSTRUCTION SET REFERENCE, A-L
Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)
Bit #
Mnemonic
Description
21
DS
Debug Store. The processor supports the ability to write debug information into a memory resident buffer.
This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see
Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3C).
22
ACPI
Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that
allow processor temperature to be monitored and processor performance to be modulated in predefined duty
cycles under software control.
23
MMX
Intel MMX Technology. The processor supports the Intel MMX technology.
24
FXSR
FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and
restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an
operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
25
SSE
SSE. The processor supports the SSE extensions.
26
SSE2
SSE2. The processor supports the SSE2 extensions.
27
SS
Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its
own cache structure for transactions issued to the bus.
28
HTT
Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in
the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the
value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is
valid for the package.
29
TM
Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).
30
Reserved
Reserved
31
PBE
Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the
stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the
processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the
IA32_MISC_ENABLE MSR enables this capability.
INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX
When CPUID executes with EAX set to 02H, the processor returns information about the processor’s internal TLBs,
cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form
and fall into the following categories:
•
The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value
and not interpret it as an informational descriptor.
•
The most significant bit (bit 31) of each register indicates whether the register contains valid information (set
to 0) or is reserved (set to 1).
•
If a register contains valid information, the information is contained in 1 byte descriptors. There are four types
of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table
3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX
registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,
prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general
descriptor type (FFH) and not report any byte descriptor of “cache type” via CPUID leaf 2.
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INSTRUCTION SET REFERENCE, A-L
Table 3-12. Encoding of CPUID Leaf 2 Descriptors
Value
Type
Description
00H
General
01H
TLB
Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
02H
TLB
Instruction TLB: 4 MByte pages, fully associative, 2 entries
03H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 64 entries
04H
TLB
Data TLB: 4 MByte pages, 4-way set associative, 8 entries
05H
TLB
Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
06H
Cache
1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
08H
Cache
1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
09H
Cache
1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
0AH
Cache
1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0BH
TLB
0CH
Cache
1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
0DH
Cache
1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
Null descriptor, this byte contains no information
Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0EH
Cache
1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
1DH
Cache
2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
21H
Cache
2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
22H
Cache
3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
23H
Cache
3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
24H
Cache
2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
25H
Cache
3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
29H
Cache
3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
2CH
Cache
1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
30H
Cache
1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
40H
Cache
No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
41H
Cache
2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
42H
Cache
2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
43H
Cache
2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
44H
Cache
2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
45H
Cache
2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
46H
Cache
3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
47H
Cache
3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
48H
Cache
2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
49H
Cache
3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model
06H);
2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
4AH
Cache
3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
4BH
Cache
3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
4CH
Cache
3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
4DH
Cache
3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
4EH
Cache
2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
4FH
TLB
Instruction TLB: 4 KByte pages, 32 entries
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Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
Value
Type
Description
50H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
51H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
52H
TLB
Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
55H
TLB
Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
56H
TLB
Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
57H
TLB
Data TLB0: 4 KByte pages, 4-way associative, 16 entries
59H
TLB
Data TLB0: 4 KByte pages, fully associative, 16 entries
5AH
TLB
Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
5BH
TLB
Data TLB: 4 KByte and 4 MByte pages, 64 entries
5CH
TLB
Data TLB: 4 KByte and 4 MByte pages,128 entries
5DH
TLB
Data TLB: 4 KByte and 4 MByte pages,256 entries
60H
Cache
61H
TLB
Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H
TLB
Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte
pages, 4-way set associative, 4 entries
64H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 512 entries
66H
Cache
1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
67H
Cache
1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
68H
Cache
1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
6AH
Cache
uTLB: 4 KByte pages, 8-way set associative, 64 entries
6BH
Cache
DTLB: 4 KByte pages, 8-way set associative, 256 entries
1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
6CH
Cache
DTLB: 2M/4M pages, 8-way set associative, 128 entries
6DH
Cache
DTLB: 1 GByte pages, fully associative, 16 entries
70H
Cache
Trace cache: 12 K-μop, 8-way set associative
71H
Cache
Trace cache: 16 K-μop, 8-way set associative
72H
Cache
Trace cache: 32 K-μop, 8-way set associative
76H
TLB
78H
Cache
2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
79H
Cache
2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
Instruction TLB: 2M/4M pages, fully associative, 8 entries
7AH
Cache
2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7BH
Cache
2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
7CH
Cache
2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
7DH
Cache
2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
7FH
Cache
2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
80H
Cache
2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
82H
Cache
2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
83H
Cache
2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
84H
Cache
2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
85H
Cache
2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
86H
Cache
2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
87H
Cache
2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size
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INSTRUCTION SET REFERENCE, A-L
Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
Value
Type
Description
A0H
DTLB
B0H
TLB
Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
B1H
TLB
Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
B2H
TLB
Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
B3H
TLB
Data TLB: 4 KByte pages, 4-way set associative, 128 entries
B4H
TLB
Data TLB1: 4 KByte pages, 4-way associative, 256 entries
B5H
TLB
Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H
TLB
Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
BAH
TLB
Data TLB1: 4 KByte pages, 4-way associative, 64 entries
C0H
TLB
Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
C1H
STLB
Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H
DTLB
DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries
C3H
STLB
Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way,
16 entries.
C4H
DTLB
DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
CAH
STLB
Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
D0H
Cache
3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size
D1H
Cache
3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size
D2H
Cache
3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size
D6H
Cache
3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size
D7H
Cache
3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size
DTLB: 4k pages, fully associative, 32 entries
D8H
Cache
3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size
DCH
Cache
3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size
DDH
Cache
3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size
DEH
Cache
3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size
E2H
Cache
3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size
E3H
Cache
3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size
E4H
Cache
3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
EAH
Cache
3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
EBH
Cache
3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
ECH
Cache
3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
F0H
Prefetch
64-Byte prefetching
F1H
Prefetch
128-Byte prefetching
FFH
General
CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters
Example 3-1. Example of Cache and TLB Interpretation
The first member of the family of Pentium 4 processors returns the following information about caches and TLBs
when the CPUID executes with an input value of 2:
EAX
EBX
ECX
EDX
66 5B 50 01H
0H
0H
00 7A 70 00H
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INSTRUCTION SET REFERENCE, A-L
Which means:
•
•
The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.
•
Bytes 1, 2, and 3 of register EAX indicate that the processor has:
The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register
contains valid 1-byte descriptors.
— 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.
— 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.
— 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.
•
•
The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.
Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:
— 00H - NULL descriptor.
— 70H - Trace cache: 12 K-μop, 8-way set associative.
— 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.
— 00H - NULL descriptor.
INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level
When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data
that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid
index values start from 0.
Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an
index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally
defined fields reported by deterministic cache parameters are documented in Table 3-8.
This Cache Size in Bytes
= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)
= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)
The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical
package. This information is constant for all valid index values. Software can query the raw data reported by
executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in
Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
INPUT EAX = 05H: Returns MONITOR and MWAIT Features
When CPUID executes with EAX set to 05H, the processor returns information about features available to
MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with
MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power management. See Table 3-8.
INPUT EAX = 06H: Returns Thermal and Power Management Features
When CPUID executes with EAX set to 06H, the processor returns information about thermal and power management features. See Table 3-8.
INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information
When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum
input value for sub-leaves that contain extended feature flags. See Table 3-8.
When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),
the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest
leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.
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INPUT EAX = 09H: Returns Direct Cache Access Information
When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabilities. See Table 3-8.
INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features
When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural
performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see
Table 3-8) is greater than Pn 0. See Table 3-8.
For each version of architectural performance monitoring capability, software must enumerate this leaf to discover
the programming facilities and the architectural performance events available in the processor. The details are
described in Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3C.
INPUT EAX = 0BH: Returns Extended Topology Information
When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumeration data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported
by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.
INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information
When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector
representation of all processor state extensions that are supported in the processor and storage size requirements
of the XSAVE/XRSTOR area. See Table 3-8.
When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns
information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.
See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves
and obtain size and offset information for each processor extended state save area:
For i = 2 to 62 // sub-leaf 1 is reserved
IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX
Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;
FI;
INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information
When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector
representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID
values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds
to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that software must use to query QoS monitoring capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns information software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the
IA32_QM_CTR MSR.
INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information
When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector
representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit
1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or
ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns information about available classes of service and range of QoS mask MSRs that software can use to configure each
class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.
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INPUT EAX = 12H: Returns Intel SGX Enumeration Information
When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capabilities. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attributes. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX
Enclave Page Cache. See Table 3-8.
INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information
When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor
Trace extensions. See Table 3-8.
When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in
CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor
Trace. See Table 3-8.
INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information
When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp
Counter and Core Crystal Clock. See Table 3-8.
INPUT EAX = 16H: Returns Processor Frequency Information
When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Information. See Table 3-8.
INPUT EAX = 17H: Returns System-On-Chip Information
When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor
Attribute Enumeration. See Table 3-8.
METHODS FOR RETURNING BRANDING INFORMATION
Use the following techniques to access branding information:
1. Processor brand string method.
2. Processor brand index; this method uses a software supplied brand string table.
These two methods are discussed in the following sections. For methods that are available in early processors, see
Section: “Identification of Earlier IA-32 Processors” in Chapter 19 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1.
The Processor Brand String Method
Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software
should execute this algorithm on all Intel 64 and IA-32 processors.
This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor
Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.
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INSTRUCTION SET REFERENCE, A-L
Input: EAX=
0x80000000
CPUID
IF (EAX & 0x80000000)
CPUID
Function
Supported
False
Processor Brand
String Not
Supported
True
Processor Brand
String Supported
True ≥
Extended
EAX Return Value =
Max. Extended CPUID
Function Index
IF (EAX Return Value
≥ 0x80000004)
OM15194
Figure 3-9. Determination of Support for the Processor Brand String
How Brand Strings Work
To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input
value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-terminated.
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INSTRUCTION SET REFERENCE, A-L
Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.
Table 3-13. Processor Brand String Returned with Pentium 4 Processor
EAX Input Value
80000002H
80000003H
80000004H
Return Values
ASCII Equivalent
EAX = 20202020H
“
”
EBX = 20202020H
“ ”
ECX = 20202020H
“ ”
EDX = 6E492020H
“nI ”
EAX = 286C6574H
“(let”
EBX = 50202952H
“P )R”
ECX = 69746E65H
“itne”
EDX = 52286D75H
“R(mu”
EAX = 20342029H
“ 4 )”
EBX = 20555043H
“ UPC”
ECX = 30303531H
“0051”
EDX = 007A484DH
“\0zHM”
Extracting the Processor Frequency from Brand Strings
Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the
processor brand string.
Scan "Brand String" in
Reverse Byte Order
"zHM", or
"zHG", or
"zHT"
Match
Substring
IF Substring Matched
Determine "Freq"
and "Multiplier"
True
False
If "zHM"
If "zHG"
Determine "Multiplier"
Determine "Freq"
Processor Base
Frequency =
"Freq" x "Multiplier"
If "zHT"
Scan Digits
Until Blank
In Reverse Order
Report Error
Multiplier = 1 x 106
Multiplier = 1 x 109
Multiplier = 1 x 1012
Reverse Digits
To Decimal Value
"Freq" = X.YZ if
Digits = "ZY.X"
OM15195
Figure 3-10. Algorithm for Extracting Processor Frequency
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The Processor Brand Index Method
The brand index method (introduced with Pentium® III Xeon® processors) provides an entry point into a brand
identification table that is maintained in memory by system software and is accessible from system- and user-level
code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official
Intel family and model number of a processor.
When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can
then use this index to locate the brand identification string for the processor in the brand identification table. The
first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not
support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand
index method is no longer supported. Use brand string method instead.
Table 3-14 shows brand indices that have identification strings associated with them.
Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings
Brand Index
Brand String
00H
This processor does not support the brand identification feature
01H
Intel(R) Celeron(R) processor1
02H
Intel(R) Pentium(R) III processor1
03H
Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)
processor
04H
Intel(R) Pentium(R) III processor
06H
Mobile Intel(R) Pentium(R) III processor-M
07H
Mobile Intel(R) Celeron(R) processor1
08H
Intel(R) Pentium(R) 4 processor
09H
Intel(R) Pentium(R) 4 processor
0AH
Intel(R) Celeron(R) processor1
0BH
Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP
0CH
Intel(R) Xeon(R) processor MP
0EH
Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor
0FH
Mobile Intel(R) Celeron(R) processor1
11H
Mobile Genuine Intel(R) processor
12H
Intel(R) Celeron(R) M processor
13H
Mobile Intel(R) Celeron(R) processor1
14H
Intel(R) Celeron(R) processor
15H
Mobile Genuine Intel(R) processor
16H
Intel(R) Pentium(R) M processor
17H
Mobile Intel(R) Celeron(R) processor1
18H – 0FFH
RESERVED
NOTES:
1. Indicates versions of these processors that were introduced after the Pentium III
IA-32 Architecture Compatibility
CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the
Intel486 processor.
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INSTRUCTION SET REFERENCE, A-L
Operation
IA32_BIOS_SIGN_ID MSR ← Update with installed microcode revision number;
CASE (EAX) OF
EAX = 0:
EAX ← Highest basic function input value understood by CPUID;
EBX ← Vendor identification string;
EDX ← Vendor identification string;
ECX ← Vendor identification string;
BREAK;
EAX = 1H:
EAX[3:0] ← Stepping ID;
EAX[7:4] ← Model;
EAX[11:8] ← Family;
EAX[13:12] ← Processor type;
EAX[15:14] ← Reserved;
EAX[19:16] ← Extended Model;
EAX[27:20] ← Extended Family;
EAX[31:28] ← Reserved;
EBX[7:0] ← Brand Index; (* Reserved if the value is zero. *)
EBX[15:8] ← CLFLUSH Line Size;
EBX[16:23] ← Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
EBX[24:31] ← Initial APIC ID;
ECX ← Feature flags; (* See Figure 3-7. *)
EDX ← Feature flags; (* See Figure 3-8. *)
BREAK;
EAX = 2H:
EAX ← Cache and TLB information;
EBX ← Cache and TLB information;
ECX ← Cache and TLB information;
EDX ← Cache and TLB information;
BREAK;
EAX = 3H:
EAX ← Reserved;
EBX ← Reserved;
ECX ← ProcessorSerialNumber[31:0];
(* Pentium III processors only, otherwise reserved. *)
EDX ← ProcessorSerialNumber[63:32];
(* Pentium III processors only, otherwise reserved. *
BREAK
EAX = 4H:
EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-8. *)
EBX ← Deterministic Cache Parameters Leaf;
ECX ← Deterministic Cache Parameters Leaf;
EDX ← Deterministic Cache Parameters Leaf;
BREAK;
EAX = 5H:
EAX ← MONITOR/MWAIT Leaf; (* See Table 3-8. *)
EBX ← MONITOR/MWAIT Leaf;
ECX ← MONITOR/MWAIT Leaf;
EDX ← MONITOR/MWAIT Leaf;
BREAK;
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EAX = 6H:
EAX ← Thermal and Power Management Leaf; (* See Table 3-8. *)
EBX ← Thermal and Power Management Leaf;
ECX ← Thermal and Power Management Leaf;
EDX ← Thermal and Power Management Leaf;
BREAK;
EAX = 7H:
EAX ← Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)
EBX ← Structured Extended Feature Flags Enumeration Leaf;
ECX ← Structured Extended Feature Flags Enumeration Leaf;
EDX ← Structured Extended Feature Flags Enumeration Leaf;
BREAK;
EAX = 8H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = 9H:
EAX ← Direct Cache Access Information Leaf; (* See Table 3-8. *)
EBX ← Direct Cache Access Information Leaf;
ECX ← Direct Cache Access Information Leaf;
EDX ← Direct Cache Access Information Leaf;
BREAK;
EAX = AH:
EAX ← Architectural Performance Monitoring Leaf; (* See Table 3-8. *)
EBX ← Architectural Performance Monitoring Leaf;
ECX ← Architectural Performance Monitoring Leaf;
EDX ← Architectural Performance Monitoring Leaf;
BREAK
EAX = BH:
EAX ← Extended Topology Enumeration Leaf; (* See Table 3-8. *)
EBX ← Extended Topology Enumeration Leaf;
ECX ← Extended Topology Enumeration Leaf;
EDX ← Extended Topology Enumeration Leaf;
BREAK;
EAX = CH:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = DH:
EAX ← Processor Extended State Enumeration Leaf; (* See Table 3-8. *)
EBX ← Processor Extended State Enumeration Leaf;
ECX ← Processor Extended State Enumeration Leaf;
EDX ← Processor Extended State Enumeration Leaf;
BREAK;
EAX = EH:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
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EAX = FH:
EAX ← Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
ECX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
EDX ← Intel Resource Director Technology Monitoring Enumeration Leaf;
BREAK;
EAX = 10H:
EAX ← Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Resource Director Technology Allocation Enumeration Leaf;
ECX ← Intel Resource Director Technology Allocation Enumeration Leaf;
EDX ← Intel Resource Director Technology Allocation Enumeration Leaf;
BREAK;
EAX = 12H:
EAX ← Intel SGX Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel SGX Enumeration Leaf;
ECX ← Intel SGX Enumeration Leaf;
EDX ← Intel SGX Enumeration Leaf;
BREAK;
EAX = 14H:
EAX ← Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)
EBX ← Intel Processor Trace Enumeration Leaf;
ECX ← Intel Processor Trace Enumeration Leaf;
EDX ← Intel Processor Trace Enumeration Leaf;
BREAK;
EAX = 15H:
EAX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)
EBX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
ECX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
EDX ← Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
BREAK;
EAX = 16H:
EAX ← Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)
EBX ← Processor Frequency Information Enumeration Leaf;
ECX ← Processor Frequency Information Enumeration Leaf;
EDX ← Processor Frequency Information Enumeration Leaf;
BREAK;
EAX = 17H:
EAX ← System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)
EBX ← System-On-Chip Vendor Attribute Enumeration Leaf;
ECX ← System-On-Chip Vendor Attribute Enumeration Leaf;
EDX ← System-On-Chip Vendor Attribute Enumeration Leaf;
BREAK;
EAX = 80000000H:
EAX ← Highest extended function input value understood by CPUID;
EBX ← Reserved;
ECX ← Reserved;
EDX ← Reserved;
BREAK;
EAX = 80000001H:
EAX ← Reserved;
EBX ← Reserved;
ECX ← Extended Feature Bits (* See Table 3-8.*);
EDX ← Extended Feature Bits (* See Table 3-8. *);
BREAK;
3-222 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
= 80000002H:
EAX ← Processor Brand String;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000003H:
EAX ← Processor Brand String, continued;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000004H:
EAX ← Processor Brand String, continued;
EBX ← Processor Brand String, continued;
ECX ← Processor Brand String, continued;
EDX ← Processor Brand String, continued;
BREAK;
EAX = 80000005H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX = 80000006H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Cache information;
EDX ← Reserved = 0;
BREAK;
EAX = 80000007H:
EAX ← Reserved = 0;
EBX ← Reserved = 0;
ECX ← Reserved = 0;
EDX ← Reserved = Misc Feature Flags;
BREAK;
EAX = 80000008H:
EAX ← Reserved = Physical Address Size Information;
EBX ← Reserved = Virtual Address Size Information;
ECX ← Reserved = 0;
EDX ← Reserved = 0;
BREAK;
EAX >= 40000000H and EAX <= 4FFFFFFFH:
DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
(* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
EAX ← Reserved; (* Information returned for highest basic information leaf. *)
EBX ← Reserved; (* Information returned for highest basic information leaf. *)
ECX ← Reserved; (* Information returned for highest basic information leaf. *)
EDX ← Reserved; (* Information returned for highest basic information leaf. *)
BREAK;
ESAC;
EAX
Flags Affected
None.
CPUID—CPU Identification
Vol. 2A 3-223
INSTRUCTION SET REFERENCE, A-L
Exceptions (All Operating Modes)
#UD
If the LOCK prefix is used.
In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruction results in an invalid opcode (#UD) exception being generated.
3-224 Vol. 2A
CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-L
CRC32 — Accumulate CRC32 Value
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F2 0F 38 F0 /r
RM
Valid
Valid
Accumulate CRC32 on r/m8.
RM
Valid
N.E.
Accumulate CRC32 on r/m8.
RM
Valid
Valid
Accumulate CRC32 on r/m16.
RM
Valid
Valid
Accumulate CRC32 on r/m32.
RM
Valid
N.E.
Accumulate CRC32 on r/m8.
RM
Valid
N.E.
Accumulate CRC32 on r/m64.
CRC32 r32, r/m8
F2 REX 0F 38 F0 /r
CRC32 r32, r/m8*
F2 0F 38 F1 /r
CRC32 r32, r/m16
F2 0F 38 F1 /r
CRC32 r32, r/m32
F2 REX.W 0F 38 F0 /r
CRC32 r64, r/m8
F2 REX.W 0F 38 F1 /r
CRC32 r64, r/m64
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
Description
Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial
11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The
source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If
the destination is an r64 register, then the 32-bit result is stored in the least significant double word and
00000000H is stored in the most significant double word of the r64 register.
The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least
significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result
of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new
input data in the source operand. Data contained in the source operand is processed in reflected bit order. This
means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and
so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination
operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the
least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.
Operation
Notes:
BIT_REFLECT64: DST[63-0] = SRC[0-63]
BIT_REFLECT32: DST[31-0] = SRC[0-31]
BIT_REFLECT16: DST[15-0] = SRC[0-15]
BIT_REFLECT8: DST[7-0] = SRC[0-7]
MOD2: Remainder from Polynomial division modulus 2
CRC32 — Accumulate CRC32 Value
Vol. 2A 3-225
INSTRUCTION SET REFERENCE, A-L
CRC32 instruction for 64-bit source operand and 64-bit destination operand:
TEMP1[63-0]  BIT_REFLECT64 (SRC[63-0])
TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[95-0]  TEMP1[63-0] « 32
TEMP4[95-0]  TEMP2[31-0] « 64
TEMP5[95-0]  TEMP3[95-0] XOR TEMP4[95-0]
TEMP6[31-0]  TEMP5[95-0] MOD2 11EDC6F41H
DEST[31-0]  BIT_REFLECT (TEMP6[31-0])
DEST[63-32]  00000000H
CRC32 instruction for 32-bit source operand and 32-bit destination operand:
TEMP1[31-0]  BIT_REFLECT32 (SRC[31-0])
TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[63-0]  TEMP1[31-0] « 32
TEMP4[63-0]  TEMP2[31-0] « 32
TEMP5[63-0]  TEMP3[63-0] XOR TEMP4[63-0]
TEMP6[31-0]  TEMP5[63-0] MOD2 11EDC6F41H
DEST[31-0]  BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 16-bit source operand and 32-bit destination operand:
TEMP1[15-0]  BIT_REFLECT16 (SRC[15-0])
TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[47-0]  TEMP1[15-0] « 32
TEMP4[47-0]  TEMP2[31-0] « 16
TEMP5[47-0]  TEMP3[47-0] XOR TEMP4[47-0]
TEMP6[31-0]  TEMP5[47-0] MOD2 11EDC6F41H
DEST[31-0]  BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 8-bit source operand and 64-bit destination operand:
TEMP1[7-0]  BIT_REFLECT8(SRC[7-0])
TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0]  TEMP1[7-0] « 32
TEMP4[39-0]  TEMP2[31-0] « 8
TEMP5[39-0]  TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0]  TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0]  BIT_REFLECT (TEMP6[31-0])
DEST[63-32]  00000000H
CRC32 instruction for 8-bit source operand and 32-bit destination operand:
TEMP1[7-0]  BIT_REFLECT8(SRC[7-0])
TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0]  TEMP1[7-0] « 32
TEMP4[39-0]  TEMP2[31-0] « 8
TEMP5[39-0]  TEMP3[39-0] XOR TEMP4[39-0]
TEMP6[31-0]  TEMP5[39-0] MOD2 11EDC6F41H
DEST[31-0]  BIT_REFLECT (TEMP6[31-0])
Flags Affected
None
3-226 Vol. 2A
CRC32 — Accumulate CRC32 Value
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )
unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )
unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )
unsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )
SIMD Floating Point Exceptions
None
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Real-Address Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Virtual 8086 Mode Exceptions
#GP(0)
If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0)
If the memory address is in a non-canonical form.
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)
For a page fault.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
If LOCK prefix is used.
CRC32 — Accumulate CRC32 Value
Vol. 2A 3-227
INSTRUCTION SET REFERENCE, A-L
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point
Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F E6 /r
CVTDQ2PD xmm1, xmm2/m64
VEX.128.F3.0F.WIG E6 /r
VCVTDQ2PD xmm1, xmm2/m64
RM
V/V
AVX
VEX.256.F3.0F.WIG E6 /r
VCVTDQ2PD ymm1, xmm2/m128
RM
V/V
AVX
EVEX.128.F3.0F.W0 E6 /r
VCVTDQ2PD xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.F3.0F.W0 E6 /r
VCVTDQ2PD ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.F3.0F.W0 E6 /r
VCVTDQ2PD zmm1 {k1}{z},
ymm2/m256/m32bcst
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512F
Description
Convert two packed signed doubleword integers from
xmm2/mem to two packed double-precision floatingpoint values in xmm1.
Convert two packed signed doubleword integers from
xmm2/mem to two packed double-precision floatingpoint values in xmm1.
Convert four packed signed doubleword integers from
xmm2/mem to four packed double-precision floatingpoint values in ymm1.
Convert 2 packed signed doubleword integers from
xmm2/m128/m32bcst to eight packed double-precision
floating-point values in xmm1 with writemask k1.
Convert 4 packed signed doubleword integers from
xmm2/m128/m32bcst to 4 packed double-precision
floating-point values in ymm1 with writemask k1.
Convert eight packed signed doubleword integers from
ymm2/m256/m32bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,
four or eight packed double-precision floating-point values in the destination operand (the first operand).
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX
embedded rounding is ignored.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-228 Vol. 2A
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
X3
SRC
DEST
X3
X2
X2
X1
X1
X0
X0
Figure 3-11. CVTDQ2PD (VEX.256 encoded version)
Operation
VCVTDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
k  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] 
Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
Vol. 2A 3-229
INSTRUCTION SET REFERENCE, A-L
VCVTDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
k  j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] 
Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i] 
Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTDQ2PD (VEX.256 encoded version)
DEST[63:0]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256]  0
VCVTDQ2PD (VEX.128 encoded version)
DEST[63:0]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128]  0
CVTDQ2PD (128-bit Legacy SSE version)
DEST[63:0]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);
VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);
CVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)
CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)
3-230 Vol. 2A
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Other Exceptions
VEX-encoded instructions, see Exceptions Type 5;
EVEX-encoded instructions, see Exceptions Type E5.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values
Vol. 2A 3-231
INSTRUCTION SET REFERENCE, A-L
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point
Values
Opcode
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
0F 5B /r
CVTDQ2PS xmm1, xmm2/m128
VEX.128.0F.WIG 5B /r
VCVTDQ2PS xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.0F.WIG 5B /r
VCVTDQ2PS ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.0F.W0 5B /r
VCVTDQ2PS xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.0F.W0 5B /r
VCVTDQ2PS ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.0F.W0 5B /r
VCVTDQ2PS zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert four packed signed doubleword integers from
xmm2/mem to four packed single-precision floatingpoint values in xmm1.
Convert four packed signed doubleword integers from
xmm2/mem to four packed single-precision floatingpoint values in xmm1.
Convert eight packed signed doubleword integers from
ymm2/mem to eight packed single-precision floatingpoint values in ymm1.
Convert four packed signed doubleword integers from
xmm2/m128/m32bcst to four packed single-precision
floating-point values in xmm1with writemask k1.
Convert eight packed signed doubleword integers from
ymm2/m256/m32bcst to eight packed single-precision
floating-point values in ymm1with writemask k1.
Convert sixteen packed signed doubleword integers
from zmm2/m512/m32bcst to sixteen packed singleprecision floating-point values in zmm1with writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen
packed single-precision floating-point values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-232 Vol. 2A
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
ELSE
SET_RM(MXCSR.RM);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
FI;
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] 
Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] 
Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+31:i] 
Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
Vol. 2A 3-233
INSTRUCTION SET REFERENCE, A-L
VCVTDQ2PS (VEX.256 encoded version)
DEST[31:0]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
DEST[159:128]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
DEST[MAX_VL-1:256]  0
VCVTDQ2PS (VEX.128 encoded version)
DEST[31:0]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128]  0
CVTDQ2PS (128-bit Legacy SSE version)
DEST[31:0]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);
VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);
VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);
VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);
CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)
CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-234 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword
Integers
Opcode
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F E6 /r
CVTPD2DQ xmm1, xmm2/m128
VEX.128.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.F2.0F.WIG E6 /r
VCVTPD2DQ xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z},
xmm2/m128/m64bcst
EVEX.256.F2.0F.W1 E6 /r
VCVTPD2DQ xmm1 {k1}{z},
ymm2/m256/m64bcst
EVEX.512.F2.0F.W1 E6 /r
VCVTPD2DQ ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1.
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1.
Convert four packed double-precision floating-point
values in ymm2/mem to four signed doubleword
integers in xmm1.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two signed
doubleword integers in xmm1 subject to writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four signed
doubleword integers in xmm1 subject to writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight signed
doubleword integers in ymm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed signed
doubleword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-235
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)
Operation
VCVTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
3-236 Vol. 2A
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
VCVTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
ELSE
DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
VCVTPD2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[95:64] Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])
DEST[127:96] Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)
DEST[MAX_VL-1:128]0
VCVTPD2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[MAX_VL-1:64]0
CVTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[127:64] 0
DEST[MAX_VL-1:128] (unmodified)
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-237
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);
VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);
VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)
CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-238 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2D /r
RM
Valid
Valid
Convert two packed double-precision floatingpoint values from xmm/m128 to two packed
signed doubleword integers in mm.
CVTPD2PI mm, xmm/m128
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid
exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPD1PI:
__m64 _mm_cvtpd_pi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Other Exceptions
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTPD2PI—Convert Packed Double-Precision FP Values to Packed Dword Integers
Vol. 2A 3-239
INSTRUCTION SET REFERENCE, A-L
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5A /r
CVTPD2PS xmm1, xmm2/m128
VEX.128.66.0F.WIG 5A /r
VCVTPD2PS xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG 5A /r
VCVTPD2PS xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 5A /r
VCVTPD2PS xmm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 5A /r
VCVTPD2PS ymm1 {k1}{z},
zmm2/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two single-precision
floating-point values in xmm1.
Convert two packed double-precision floating-point
values in xmm2/mem to two single-precision
floating-point values in xmm1.
Convert four packed double-precision floating-point
values in ymm2/mem to four single-precision
floating-point values in xmm1.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two singleprecision floating-point values in xmm1with
writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four singleprecision floating-point values in xmm1with
writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight singleprecision floating-point values in ymm1with
writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed single-precision floating-point values in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAX_VL1:256/128/64) of the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-240 Vol. 2A
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-13. VCVTPD2PS (VEX.256 encoded version)
Operation
VCVTPD2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN
DEST[i+31:i]  Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
Vol. 2A 3-241
INSTRUCTION SET REFERENCE, A-L
VCVTPD2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])
ELSE
DEST[i+31:i]  Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
VCVTPD2PS (VEX.256 encoded version)
DEST[31:0]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[95:64]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])
DEST[127:96]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)
DEST[MAX_VL-1:128]  0
VCVTPD2PS (VEX.128 encoded version)
DEST[31:0]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[MAX_VL-1:64]  0
CVTPD2PS (128-bit Legacy SSE version)
DEST[31:0]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[127:64]  0
DEST[MAX_VL-1:128] (unmodified)
3-242 Vol. 2A
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);
VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);
VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);
VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);
VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)
CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision, Underflow, Overflow, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values
Vol. 2A 3-243
INSTRUCTION SET REFERENCE, A-L
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2A /r
RM
Valid
Valid
Convert two packed signed doubleword
integers from mm/mem64 to two packed
double-precision floating-point values in xmm.
CVTPI2PD xmm, mm/m64*
NOTES:
*Operation is different for different operand sets; see the Description section.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed doubleprecision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. In addition, depending on the operand configuration:
•
For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this
instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before
the CVTPI2PD instruction is executed.
•
For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take
x87 FPU exceptions.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PD:
__m128d _mm_cvtpi32_pd(__m64 a)
SIMD Floating-Point Exceptions
None
Other Exceptions
See Table 22-6, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception,” in
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
3-244 Vol. 2A
CVTPI2PD—Convert Packed Dword Integers to Packed Double-Precision FP Values
INSTRUCTION SET REFERENCE, A-L
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2A /r
RM
Valid
Valid
Convert two signed doubleword integers
from mm/m64 to two single-precision
floating-point values in xmm.
CVTPI2PS xmm, mm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed singleprecision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. The results are stored in the low quadword of the destination operand, and the high quadword
remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
(* High quadword of destination unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PS:
__m128 _mm_cvtpi32_ps(__m128 a, __m64 b)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTPI2PS—Convert Packed Dword Integers to Packed Single-Precision FP Values
Vol. 2A 3-245
INSTRUCTION SET REFERENCE, A-L
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed
Doubleword Integer Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5B /r
CVTPS2DQ xmm1, xmm2/m128
VEX.128.66.0F.WIG 5B /r
VCVTPS2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG 5B /r
VCVTPS2DQ ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W0 5B /r
VCVTPS2DQ xmm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.256.66.0F.W0 5B /r
VCVTPS2DQ ymm1 {k1}{z},
ymm2/m256/m32bcst
EVEX.512.66.0F.W0 5B /r
VCVTPS2DQ zmm1 {k1}{z},
zmm2/m512/m32bcst{er}
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512VL
AVX512F
FV
V/V
AVX512F
Description
Convert four packed single-precision floating-point values
from xmm2/mem to four packed signed doubleword
values in xmm1.
Convert four packed single-precision floating-point values
from xmm2/mem to four packed signed doubleword
values in xmm1.
Convert eight packed single-precision floating-point values
from ymm2/mem to eight packed signed doubleword
values in ymm1.
Convert four packed single precision floating-point values
from xmm2/m128/m32bcst to four packed signed
doubleword values in xmm1 subject to writemask k1.
Convert eight packed single precision floating-point values
from ymm2/m256/m32bcst to eight packed signed
doubleword values in ymm1 subject to writemask k1.
Convert sixteen packed single-precision floating-point
values from zmm2/m512/m32bcst to sixteen packed
signed doubleword values in zmm1 subject to writemask
k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-246 Vol. 2A
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTPS2DQ (encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO 15
i  j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
ELSE
DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
Vol. 2A 3-247
INSTRUCTION SET REFERENCE, A-L
VCVTPS2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)
DEST[159:128] Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])
DEST[191:160] Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])
DEST[223:192] Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])
DEST[255:224] Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])
VCVTPS2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] 0
CVTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);
VCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);
VCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);
VCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);
VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)
CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-248 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision
Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
0F 5A /r
CVTPS2PD xmm1, xmm2/m64
VEX.128.0F.WIG 5A /r
VCVTPS2PD xmm1, xmm2/m64
RM
V/V
AVX
VEX.256.0F.WIG 5A /r
VCVTPS2PD ymm1, xmm2/m128
RM
V/V
AVX
EVEX.128.0F.W0 5A /r
VCVTPS2PD xmm1 {k1}{z},
xmm2/m64/m32bcst
EVEX.256.0F.W0 5A /r
VCVTPS2PD ymm1 {k1}{z},
xmm2/m128/m32bcst
EVEX.512.0F.W0 5A /r
VCVTPS2PD zmm1 {k1}{z},
ymm2/m256/m32bcst{sae}
HV
V/V
AVX512VL
AVX512F
HV
V/V
AVX512VL
HV
V/V
AVX512F
Description
Convert two packed single-precision floating-point values in
xmm2/m64 to two packed double-precision floating-point
values in xmm1.
Convert two packed single-precision floating-point values in
xmm2/m64 to two packed double-precision floating-point
values in xmm1.
Convert four packed single-precision floating-point values
in xmm2/m128 to four packed double-precision floatingpoint values in ymm1.
Convert two packed single-precision floating-point values in
xmm2/m64/m32bcst to packed double-precision floatingpoint values in xmm1 with writemask k1.
Convert four packed single-precision floating-point values
in xmm2/m128/m32bcst to packed double-precision
floating-point values in ymm1 with writemask k1.
Convert eight packed single-precision floating-point values
in ymm2/m256/b32bcst to eight packed double-precision
floating-point values in zmm1 with writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
HV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed single-precision floating-point values in the source operand (second operand)
to two, four or eight packed double-precision floating-point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory
location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
Vol. 2A 3-249
INSTRUCTION SET REFERENCE, A-L
X3
SRC
DEST
X3
X2
X2
X1
X1
X0
X0
Figure 3-14. CVTPS2PD (VEX.256 encoded version)
Operation
VCVTPS2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
k  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+63:i] 
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTPS2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 64
k  j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+63:i] 
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
ELSE
DEST[i+63:i] 
Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
FI;
ELSE
3-250 Vol. 2A
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTPS2PD (VEX.256 encoded version)
DEST[63:0]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256]  0
VCVTPS2PD (VEX.128 encoded version)
DEST[63:0]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128]  0
CVTPS2PD (128-bit Legacy SSE version)
DEST[63:0]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);
VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);
VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);
VCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);
VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)
CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3.
#UD
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values
Vol. 2A 3-251
INSTRUCTION SET REFERENCE, A-L
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2D /r
RM
Valid
Valid
Convert two packed single-precision floatingpoint values from xmm/m64 to two packed
signed doubleword integers in mm.
CVTPS2PI mm, xmm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX technology register. When the source operand is an XMM register, the two single-precision floating-point values are
contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded
according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum
signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer
is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floatingpoint exception is pending, the exception is handled before the CVTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPS2PI:
__m64 _mm_cvtps_pi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
3-252 Vol. 2A
CVTPS2PI—Convert Packed Single-Precision FP Values to Packed Dword Integers
INSTRUCTION SET REFERENCE, A-L
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
Opcode/
Instruction
Op /
En
F2 0F 2D /r
CVTSD2SI r32, xmm1/m64
F2 REX.W 0F 2D /r
CVTSD2SI r64, xmm1/m64
VEX.128.F2.0F.W0 2D /r
VCVTSD2SI r32, xmm1/m64
VEX.128.F2.0F.W1 2D /r
VCVTSD2SI r64, xmm1/m64
EVEX.LIG.F2.0F.W0 2D /r
VCVTSD2SI r32, xmm1/m64{er}
EVEX.LIG.F2.0F.W1 2D /r
VCVTSD2SI r64, xmm1/m64{er}
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
RM
V/N.E.
SSE2
RM
V/V
AVX
RM
V/N.E.1
AVX
T1F
V/V
AVX512F
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer r32.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer signextended into r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit
memory location. The destination operand is a general-purpose register. When the source operand is an XMM
register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.
See the summary chart at the beginning of this section for encoding data and limits.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
Vol. 2A 3-253
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSD2SI (EVEX encoded version)
IF SRC *is register* AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0]  Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
DEST[31:0]  Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI
(V)CVTSD2SI
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SI int _mm_cvtsd_i32(__m128d);
VCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);
VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);
VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);
CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);
CVTSD2SI int _mm_cvtsd_si32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD
3-254 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
INSTRUCTION SET REFERENCE, A-L
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision
Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5A /r
CVTSD2SS xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5A /r
VCVTSD2SS xmm1,xmm2,
xmm3/m64
EVEX.NDS.LIG.F2.0F.W1 5A /r
VCVTSD2SS xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Convert one double-precision floating-point value in
xmm2/m64 to one single-precision floating-point value
in xmm1.
Convert one double-precision floating-point value in
xmm3/m64 to one single-precision floating-point value
and merge with high bits in xmm2.
Convert one double-precision floating-point value in
xmm3/m64 to one single-precision floating-point value
and merge with high bits in xmm2 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a double-precision floating-point value in the “convert-from” source operand (the second operand in
SSE2 version, otherwise the third operand) to a single-precision floating-point value in the destination operand.
When the “convert-from” operand is an XMM register, the double-precision floating-point value is contained in the
low quadword of the register. The result is stored in the low doubleword of the destination operand. When the
conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged. The destination operand is an XMM register.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM
register or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
Vol. 2A 3-255
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSD2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[31:0]  Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[31:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[31:0]  0
FI;
FI;
DEST[127:32]  SRC1[127:32]
DEST[MAX_VL-1:128]  0
VCVTSD2SS (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
CVTSD2SS (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);
(* DEST[MAX_VL-1:32] Unmodified *)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);
VCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);
VCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);
CVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-256 Vol. 2A
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 2A /r
CVTSI2SD xmm1, r32/m32
F2 REX.W 0F 2A /r
CVTSI2SD xmm1, r/m64
RM
V/N.E.
SSE2
VEX.NDS.128.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32
RVM
V/V
AVX
VEX.NDS.128.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64
RVM
V/N.E.1
AVX
EVEX.NDS.LIG.F2.0F.W0 2A /r
VCVTSI2SD xmm1, xmm2, r/m32
T1S
V/V
AVX512F
EVEX.NDS.LIG.F2.0F.W1 2A /r
VCVTSI2SD xmm1, xmm2, r/m64{er}
T1S
V/N.E.1
AVX512F
Description
Convert one signed doubleword integer from
r32/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
Convert one signed doubleword integer from
r/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
Convert one signed doubleword integer from
r/m32 to one double-precision floating-point
value in xmm1.
Convert one signed quadword integer from r/m64
to one double-precision floating-point value in
xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”
source operand to a double-precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers.
128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The “convertfrom” source operand (the second operand) is a general-purpose register or memory location. The destination is
an XMM register Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a generalpurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)
of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.
VEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.
Software should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
Vol. 2A 3-257
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSI2SD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0]  Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0]  Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64]  SRC1[127:64]
DEST[MAX_VL-1:128]  0
VCVTSI2SD (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
CVTSI2SD
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[63:0] Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);
VCVTSI2SD __m128d _mm_cvt_roundi32_sd(__m128d s, int a, int r);
VCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);
VCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);
CVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);
CVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3 if W1, else Type 5.
EVEX-encoded instructions, see Exceptions Type E3NF if W1, else Type E10NF.
3-258 Vol. 2A
CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2A /r
CVTSI2SS xmm1, r/m32
F3 REX.W 0F 2A /r
CVTSI2SS xmm1, r/m64
VEX.NDS.128.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32
VEX.NDS.128.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64
EVEX.NDS.LIG.F3.0F.W0 2A /r
VCVTSI2SS xmm1, xmm2, r/m32{er}
EVEX.NDS.LIG.F3.0F.W1 2A /r
VCVTSI2SS xmm1, xmm2, r/m64{er}
RM
V/N.E.
SSE
RVM
V/V
AVX
RVM
V/N.E.1
AVX
T1S
V/V
AVX512F
T1S
V/N.E.1
AVX512F
Description
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
Convert one signed doubleword integer from r/m32
to one single-precision floating-point value in xmm1.
Convert one signed quadword integer from r/m64
to one single-precision floating-point value in xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the “convert-from”
source operand to a single-precision floating-point value in the destination operand (first operand). The “convertfrom” source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords
are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input
value. The “convert-from” source operand (the second operand) is a general-purpose register or memory location.
Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be a generalpurpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)
of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
Vol. 2A 3-259
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSI2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0]  Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32]  SRC1[127:32]
DEST[MAX_VL-1:128]  0
VCVTSI2SS (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] SRC1[127:32]
DEST[MAX_VL-1:128] 0
CVTSI2SS (128-bit Legacy SSE version)
IF 64-Bit Mode And OperandSize = 64
THEN
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
DEST[31:0] Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:32] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);
VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);
VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);
VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);
CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);
CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);
SIMD Floating-Point Exceptions
Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3NF.
3-260 Vol. 2A
CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision
Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F 5A /r
CVTSS2SD xmm1, xmm2/m32
VEX.NDS.128.F3.0F.WIG 5A /r
VCVTSS2SD xmm1, xmm2,
xmm3/m32
EVEX.NDS.LIG.F3.0F.W0 5A /r
VCVTSS2SD xmm1 {k1}{z}, xmm2,
xmm3/m32{sae}
RVM
V/V
AVX
T1S
V/V
AVX512F
Description
Convert one single-precision floating-point value in
xmm2/m32 to one double-precision floating-point value
in xmm1.
Convert one single-precision floating-point value in
xmm3/m32 to one double-precision floating-point value
and merge with high bits of xmm2.
Convert one single-precision floating-point value in
xmm3/m32 to one double-precision floating-point value
and merge with high bits of xmm2 under writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Converts a single-precision floating-point value in the “convert-from” source operand to a double-precision
floating-point value in the destination operand. When the “convert-from” source operand is an XMM register, the
single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the
low quadword of the destination operand.
128-bit Legacy SSE version: The “convert-from” source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destination operand is an XMM register.
VEX.128 and EVEX encoded versions: The “convert-from” source operand (the third operand) can be an XMM
register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL1:128) of the destination register are zeroed.
Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
Operation
VCVTSS2SD (EVEX encoded version)
IF k1[0] or *no writemask*
THEN
DEST[63:0]  Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0] = 0
FI;
FI;
DEST[127:64]  SRC1[127:64]
DEST[MAX_VL-1:128]  0
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
Vol. 2A 3-261
INSTRUCTION SET REFERENCE, A-L
VCVTSS2SD (VEX.128 encoded version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:128] 0
CVTSS2SD (128-bit Legacy SSE version)
DEST[63:0] Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[MAX_VL-1:64] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);
VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);
VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);
VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);
VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);
CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);
SIMD Floating-Point Exceptions
Invalid, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.
3-262 Vol. 2A
CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2D /r
CVTSS2SI r32, xmm1/m32
F3 REX.W 0F 2D /r
CVTSS2SI r64, xmm1/m32
VEX.128.F3.0F.W0 2D /r
VCVTSS2SI r32, xmm1/m32
VEX.128.F3.0F.W1 2D /r
VCVTSS2SI r64, xmm1/m32
EVEX.LIG.F3.0F.W0 2D /r
VCVTSS2SI r32, xmm1/m32{er}
EVEX.LIG.F3.0F.W1 2D /r
VCVTSS2SI r64, xmm1/m32{er}
RM
V/N.E.
SSE
RM
V/V
AVX
RM
V/N.E.1
AVX
T1F
V/V
AVX512F
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.
See the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
Vol. 2A 3-263
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTSS2SI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0]  Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0]  Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
(V)CVTSS2SI (Legacy and VEX.128 encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
DEST[63:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SI int _mm_cvtss_i32( __m128 a);
VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);
VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);
VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
3-264 Vol. 2A
CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
INSTRUCTION SET REFERENCE, A-L
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Doubleword Integers
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F E6 /r
CVTTPD2DQ xmm1, xmm2/m128
VEX.128.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.66.0F.WIG E6 /r
VCVTTPD2DQ xmm1, ymm2/m256
RM
V/V
AVX
EVEX.128.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z},
xmm2/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.66.0F.W1 E6 /r
VCVTTPD2DQ xmm1 {k1}{z},
ymm2/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.66.0F.W1 E6 /r
VCVTTPD2DQ ymm1 {k1}{z},
zmm2/m512/m64bcst{sae}
FV
V/V
AVX512F
Description
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1 using truncation.
Convert two packed double-precision floating-point
values in xmm2/mem to two signed doubleword
integers in xmm1 using truncation.
Convert four packed double-precision floating-point
values in ymm2/mem to four signed doubleword
integers in xmm1 using truncation.
Convert two packed double-precision floating-point
values in xmm2/m128/m64bcst to two signed
doubleword integers in xmm1 using truncation subject
to writemask k1.
Convert four packed double-precision floating-point
values in ymm2/m256/m64bcst to four signed
doubleword integers in xmm1 using truncation subject
to writemask k1.
Convert eight packed double-precision floating-point
values in zmm2/m512/m64bcst to eight signed
doubleword integers in ymm1 using truncation subject
to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed signed doubleword integers in the destination operand (first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of
the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-265
INSTRUCTION SET REFERENCE, A-L
SRC
DEST
X3
X2
0
X1
X3
X0
X2
X1
X0
Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)
Operation
VCVTTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
3-266 Vol. 2A
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
VCVTTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j  0 TO KL-1
i  j * 32
k  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
ELSE
DEST[i+31:i] 
Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL/2]  0
VCVTTPD2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[95:64] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])
DEST[127:96] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)
DEST[MAX_VL-1:128]0
VCVTTPD2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[MAX_VL-1:64]0
CVTTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[127:64] 0
DEST[MAX_VL-1:128] (unmodified)
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
Vol. 2A 3-267
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);
VCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);
CVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-268 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-L
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword
Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
66 0F 2C /r
RM
Valid
Valid
Convert two packer double-precision floatingpoint values from xmm/m128 to two packed
signed doubleword integers in mm using
truncation.
CVTTPD2PI mm, xmm/m128
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 128-bit memory location. The destination operand is an MMX technology register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] ← Convert_Double_Precision_Floating_Point_To_Integer32_
Truncate(SRC[127:64]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTTPD1PI:
__m64 _mm_cvttpd_pi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Mode Exceptions
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTTPD2PI—Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers
Vol. 2A 3-269
INSTRUCTION SET REFERENCE, A-L
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed
Signed Doubleword Integer Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F3 0F 5B /r
CVTTPS2DQ xmm1, xmm2/m128
VEX.128.F3.0F.WIG 5B /r
VCVTTPS2DQ xmm1, xmm2/m128
RM
V/V
AVX
VEX.256.F3.0F.WIG 5B /r
VCVTTPS2DQ ymm1, ymm2/m256
RM
V/V
AVX
EVEX.128.F3.0F.W0 5B /r
VCVTTPS2DQ xmm1 {k1}{z},
xmm2/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.256.F3.0F.W0 5B /r
VCVTTPS2DQ ymm1 {k1}{z},
ymm2/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.512.F3.0F.W0 5B /r
VCVTTPS2DQ zmm1 {k1}{z},
zmm2/m512/m32bcst {sae}
FV
V/V
AVX512F
Description
Convert four packed single-precision floating-point
values from xmm2/mem to four packed signed
doubleword values in xmm1 using truncation.
Convert four packed single-precision floating-point
values from xmm2/mem to four packed signed
doubleword values in xmm1 using truncation.
Convert eight packed single-precision floating-point
values from ymm2/mem to eight packed signed
doubleword values in ymm1 using truncation.
Convert four packed single precision floating-point
values from xmm2/m128/m32bcst to four packed
signed doubleword values in xmm1 using truncation
subject to writemask k1.
Convert eight packed single precision floating-point
values from ymm2/m256/m32bcst to eight packed
signed doubleword values in ymm1 using truncation
subject to writemask k1.
Convert sixteen packed single-precision floating-point
values from zmm2/m512/m32bcst to sixteen packed
signed doubleword values in zmm1 using truncation
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
FV
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
3-270 Vol. 2A
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
Operation
VCVTTPS2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
THEN DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j  0 TO 15
i  j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1)
THEN
DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
ELSE
DEST[i+31:i] 
Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VCVTTPS2DQ (VEX.256 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)
DEST[159:128] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])
DEST[191:160] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])
DEST[223:192] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])
DEST[255:224] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
Vol. 2A 3-271
INSTRUCTION SET REFERENCE, A-L
VCVTTPS2DQ (VEX.128 encoded version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] 0
CVTTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);
VCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);
VCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);
VCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)
CVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD
3-272 Vol. 2A
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values
INSTRUCTION SET REFERENCE, A-L
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword
Integers
Opcode/
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
0F 2C /r
RM
Valid
Valid
Convert two single-precision floating-point
values from xmm/m64 to two signed
doubleword signed integers in mm using
truncation.
CVTTPS2PI mm, xmm/m64
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is
an XMM register, the two single-precision floating-point values are contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTTPS2PI:
__m64 _mm_cvttps_pi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
CVTTPS2PI—Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers
Vol. 2A 3-273
INSTRUCTION SET REFERENCE, A-L
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed
Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 2C /r
CVTTSD2SI r32, xmm1/m64
F2 REX.W 0F 2C /r
CVTTSD2SI r64, xmm1/m64
RM
V/N.E.
SSE2
VEX.128.F2.0F.W0 2C /r
VCVTTSD2SI r32, xmm1/m64
RM
V/V
AVX
VEX.128.F2.0F.W1 2C /r
VCVTTSD2SI r64, xmm1/m64
T1F
V/N.E.1
AVX
EVEX.LIG.F2.0F.W0 2C /r
VCVTTSD2SI r32, xmm1/m64{sae}
T1F
V/V
AVX512F
EVEX.LIG.F2.0F.W1 2C /r
VCVTTSD2SI r64, xmm1/m64{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed doubleword integer in r32
using truncation.
Convert one double-precision floating-point value from
xmm1/m64 to one signed quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general
purpose register. When the source operand is an XMM register, the double-precision floating-point value is
contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
3-274 Vol. 2A
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer
INSTRUCTION SET REFERENCE, A-L
Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.
Operation
(V)CVTTSD2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0]  Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
ELSE
DEST[31:0]  Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);
VCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);
VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);
VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);
CVTTSD2SI int _mm_cvttsd_si32( __m128d a);
CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
CVTTSD2SI—Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer
Vol. 2A 3-275
INSTRUCTION SET REFERENCE, A-L
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
F3 0F 2C /r
CVTTSS2SI r32, xmm1/m32
F3 REX.W 0F 2C /r
CVTTSS2SI r64, xmm1/m32
RM
V/N.E.
SSE
VEX.128.F3.0F.W0 2C /r
VCVTTSS2SI r32, xmm1/m32
RM
V/V
AVX
VEX.128.F3.0F.W1 2C /r
VCVTTSS2SI r64, xmm1/m32
RM
V/N.E.1
AVX
EVEX.LIG.F3.0F.W0 2C /r
VCVTTSS2SI r32, xmm1/m32{sae}
T1F
V/V
AVX512F
EVEX.LIG.F3.0F.W1 2C /r
VCVTTSS2SI r64, xmm1/m32{sae}
T1F
V/N.E.1
AVX512F
Description
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed doubleword integer in r32
using truncation.
Convert one single-precision floating-point value from
xmm1/m32 to one signed quadword integer in r64
using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
T1F
ModRM:reg (w)
ModRM:r/m (r)
NA
NA
Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword
integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The
source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,
the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.
3-276 Vol. 2A
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
INSTRUCTION SET REFERENCE, A-L
Operation
(V)CVTTSS2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0]  Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
ELSE
DEST[31:0]  Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
FI;
Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2SI int _mm_cvttss_i32( __m128 a);
VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);
VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);
VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);
CVTTSS2SI int _mm_cvttss_si32( __m128 a);
CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);
SIMD Floating-Point Exceptions
Invalid, Precision
Other Exceptions
See Exceptions Type 3; additionally
#UD
If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.
CVTTSS2SI—Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
Vol. 2A 3-277
INSTRUCTION SET REFERENCE, A-L
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
99
CWD
NP
Valid
Valid
DX:AX ← sign-extend of AX.
99
CDQ
NP
Valid
Valid
EDX:EAX ← sign-extend of EAX.
REX.W + 99
CQO
NP
Valid
N.E.
RDX:RAX← sign-extend of RAX.
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Instruction Operand Encoding
Description
Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign
extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction
copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction
copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruction (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position
in the RDX register.
The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ
instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO
instruction can be used to produce a double quadword dividend from a quadword before a quadword division.
The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the
operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers
may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these
mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the
size of values to be converted, regardless of the mnemonic used.
In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same
opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.
Operation
IF OperandSize = 16 (* CWD instruction *)
THEN
DX ← SignExtend(AX);
ELSE IF OperandSize = 32 (* CDQ instruction *)
EDX ← SignExtend(EAX); FI;
ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)
RDX ← SignExtend(RAX); FI;
FI;
Flags Affected
None
Exceptions (All Operating Modes)
#UD
3-278 Vol. 2A
If the LOCK prefix is used.
CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword
INSTRUCTION SET REFERENCE, A-L
DAA—Decimal Adjust AL after Addition
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
27
DAA
NP
Invalid
Valid
Decimal adjust AL after addition.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and
destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts
the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the
CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
old_AL ← AL;
old_CF ← CF;
CF ← 0;
IF (((AL AND 0FH) > 9) or AF = 1)
THEN
AL ← AL + 6;
CF ← old_CF or (Carry from AL ← AL + 6);
AF ← 1;
ELSE
AF ← 0;
FI;
IF ((old_AL > 99H) or (old_CF = 1))
THEN
AL ← AL + 60H;
CF ← 1;
ELSE
CF ← 0;
FI;
FI;
Example
ADD
DAA
DAA
AL, BL
Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX
After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000
Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000
After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111
Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000
After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101
DAA—Decimal Adjust AL after Addition
Vol. 2A 3-279
INSTRUCTION SET REFERENCE, A-L
Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see
the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
3-280 Vol. 2A
If in 64-bit mode.
DAA—Decimal Adjust AL after Addition
INSTRUCTION SET REFERENCE, A-L
DAS—Decimal Adjust AL after Subtraction
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
2F
DAS
NP
Invalid
Valid
Decimal adjust AL after subtraction.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
NP
NA
NA
NA
NA
Description
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the
implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that
subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL
register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD
result. If a decimal borrow is detected, the CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.
Operation
IF 64-Bit Mode
THEN
#UD;
ELSE
old_AL ← AL;
old_CF ← CF;
CF ← 0;
IF (((AL AND 0FH) > 9) or AF = 1)
THEN
AL ← AL - 6;
CF ← old_CF or (Borrow from AL ← AL − 6);
AF ← 1;
ELSE
AF ← 0;
FI;
IF ((old_AL > 99H) or (old_CF = 1))
THEN
AL ← AL − 60H;
CF ← 1;
FI;
FI;
Example
SUB
AL, BL
DAA
Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX
After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111
Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111
After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111
Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result
(see the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
DAS—Decimal Adjust AL after Subtraction
Vol. 2A 3-281
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
#UD
If the LOCK prefix is used.
64-Bit Mode Exceptions
#UD
3-282 Vol. 2A
If in 64-bit mode.
DAS—Decimal Adjust AL after Subtraction
INSTRUCTION SET REFERENCE, A-L
DEC—Decrement by 1
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
FE /1
DEC r/m8
M
Valid
Valid
Decrement r/m8 by 1.
REX + FE /1
DEC r/m8
*
M
Valid
N.E.
Decrement r/m8 by 1.
FF /1
DEC r/m16
M
Valid
Valid
Decrement r/m16 by 1.
FF /1
DEC r/m32
M
Valid
Valid
Decrement r/m32 by 1.
REX.W + FF /1
DEC r/m64
M
Valid
N.E.
Decrement r/m64 by 1.
48+rw
DEC r16
O
N.E.
Valid
Decrement r16 by 1.
48+rd
DEC r32
O
N.E.
Valid
Decrement r32 by 1.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (r, w)
NA
NA
NA
O
opcode + rd (r, w)
NA
NA
NA
Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be
a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.
(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of
1.)
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).
Otherwise, the instruction’s 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to
additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
See the summary chart at the beginning of this section for encoding data and limits.
Operation
DEST ← DEST – 1;
Flags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
Protected Mode Exceptions
#GP(0)
If the destination operand is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
DEC—Decrement by 1
Vol. 2A 3-283
INSTRUCTION SET REFERENCE, A-L
Real-Address Mode Exceptions
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Virtual-8086 Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used but the destination is not a memory operand.
3-284 Vol. 2A
DEC—Decrement by 1
INSTRUCTION SET REFERENCE, A-L
DIV—Unsigned Divide
Opcode
Instruction
Op/
En
64-Bit
Mode
Compat/ Description
Leg Mode
F6 /6
DIV r/m8
M
Valid
Valid
Unsigned divide AX by r/m8, with result
stored in AL ← Quotient, AH ← Remainder.
REX + F6 /6
DIV r/m8*
M
Valid
N.E.
Unsigned divide AX by r/m8, with result
stored in AL ← Quotient, AH ← Remainder.
F7 /6
DIV r/m16
M
Valid
Valid
Unsigned divide DX:AX by r/m16, with result
stored in AX ← Quotient, DX ← Remainder.
F7 /6
DIV r/m32
M
Valid
Valid
Unsigned divide EDX:EAX by r/m32, with
result stored in EAX ← Quotient, EDX ←
Remainder.
REX.W + F7 /6
DIV r/m64
M
Valid
N.E.
Unsigned divide RDX:RAX by r/m64, with
result stored in RAX ← Quotient, RDX ←
Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
M
ModRM:r/m (w)
NA
NA
NA
Description
Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand
(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can
be a general-purpose register or a memory location. The action of this instruction depends on the operand size
(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magnitude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is
applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in
RAX, the remainder in RDX.
See the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.
Table 3-15. DIV Action
Operand Size
Dividend
Divisor
Quotient
Remainder
Maximum
Quotient
Word/byte
AX
r/m8
AL
AH
255
Doubleword/word
DX:AX
r/m16
AX
DX
65,535
Quadword/doubleword
EDX:EAX
r/m32
EAX
EDX
232 − 1
Doublequadword/
RDX:RAX
r/m64
RAX
RDX
264 − 1
quadword
DIV—Unsigned Divide
Vol. 2A 3-285
INSTRUCTION SET REFERENCE, A-L
Operation
IF SRC = 0
THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)
THEN
temp ← AX / SRC;
IF temp > FFH
THEN #DE; (* Divide error *)
ELSE
AL ← temp;
AH ← AX MOD SRC;
FI;
ELSE IF OperandSize = 16 (* Doubleword/word operation *)
THEN
temp ← DX:AX / SRC;
IF temp > FFFFH
THEN #DE; (* Divide error *)
ELSE
AX ← temp;
DX ← DX:AX MOD SRC;
FI;
FI;
ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
THEN
temp ← EDX:EAX / SRC;
IF temp > FFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
EAX ← temp;
EDX ← EDX:EAX MOD SRC;
FI;
FI;
ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
THEN
temp ← RDX:RAX / SRC;
IF temp > FFFFFFFFFFFFFFFFH
THEN #DE; (* Divide error *)
ELSE
RAX ← temp;
RDX ← RDX:RAX MOD SRC;
FI;
FI;
FI;
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are undefined.
3-286 Vol. 2A
DIV—Unsigned Divide
INSTRUCTION SET REFERENCE, A-L
Protected Mode Exceptions
#DE
If the source operand (divisor) is 0
If the quotient is too large for the designated register.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
Real-Address Mode Exceptions
#DE
If the source operand (divisor) is 0.
If the quotient is too large for the designated register.
#GP
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If the LOCK prefix is used.
Virtual-8086 Mode Exceptions
#DE
If the source operand (divisor) is 0.
If the quotient is too large for the designated register.
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made.
#UD
If the LOCK prefix is used.
Compatibility Mode Exceptions
Same exceptions as in protected mode.
64-Bit Mode Exceptions
#SS(0)
If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)
If the memory address is in a non-canonical form.
#DE
If the source operand (divisor) is 0
#PF(fault-code)
If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is made while the
current privilege level is 3.
#UD
If the LOCK prefix is used.
If the quotient is too large for the designated register.
DIV—Unsigned Divide
Vol. 2A 3-287
INSTRUCTION SET REFERENCE, A-L
DIVPD—Divide Packed Double-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
66 0F 5E /r
DIVPD xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG 5E /r
VDIVPD xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.66.0F.WIG 5E /r
VDIVPD ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.66.0F.W1 5E /r
VDIVPD xmm1 {k1}{z}, xmm2,
xmm3/m128/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.66.0F.W1 5E /r
VDIVPD ymm1 {k1}{z}, ymm2,
ymm3/m256/m64bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.66.0F.W1 5E /r
VDIVPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}
FV
V/V
AVX512F
Description
Divide packed double-precision floating-point values
in xmm1 by packed double-precision floating-point
values in xmm2/mem.
Divide packed double-precision floating-point values
in xmm2 by packed double-precision floating-point
values in xmm3/mem.
Divide packed double-precision floating-point values
in ymm2 by packed double-precision floating-point
values in ymm3/mem.
Divide packed double-precision floating-point values
in xmm2 by packed double-precision floating-point
values in xmm3/m128/m64bcst and write results to
xmm1 subject to writemask k1.
Divide packed double-precision floating-point values
in ymm2 by packed double-precision floating-point
values in ymm3/m256/m64bcst and write results to
ymm1 subject to writemask k1.
Divide packed double-precision floating-point values
in zmm2 by packed double-precision FP values in
zmm3/m512/m64bcst and write results to zmm1
subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD divide of the double-precision floating-point values in the first source operand by the floatingpoint values in the second source operand (the third operand). Results are written to the destination operand (the
first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source
operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper
bits (MAX_VL-1:256) of the corresponding destination are zeroed.
VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source
operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper
bits (MAX_VL-1:128) of the corresponding destination are zeroed.
128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128bit memory location. The destination is the same as the first source operand. The upper bits (MAX_VL-1:128) of the
corresponding destination are unmodified.
3-288 Vol. 2A
DIVPD—Divide Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
; refer to Table 2-4 in the Intel® Architecture Instruction Set Extensions Programming Reference
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 64
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+63:i]  SRC1[i+63:i] / SRC2[63:0]
ELSE
DEST[i+63:i]  SRC1[i+63:i] / SRC2[i+63:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+63:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+63:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VDIVPD (VEX.256 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[191:128] SRC1[191:128] / SRC2[191:128]
DEST[255:192] SRC1[255:192] / SRC2[255:192]
DEST[MAX_VL-1:256] 0;
VDIVPD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] 0;
DIVPD (128-bit Legacy SSE version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] (Unmodified)
DIVPD—Divide Packed Double-Precision Floating-Point Values
Vol. 2A 3-289
INSTRUCTION SET REFERENCE, A-L
Intel C/C++ Compiler Intrinsic Equivalent
VDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);
VDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);
DIVPD __m128d _mm_div_pd (__m128d a, __m128d b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
3-290 Vol. 2A
DIVPD—Divide Packed Double-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
DIVPS—Divide Packed Single-Precision Floating-Point Values
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE
0F 5E /r
DIVPS xmm1, xmm2/m128
VEX.NDS.128.0F.WIG 5E /r
VDIVPS xmm1, xmm2, xmm3/m128
RVM
V/V
AVX
VEX.NDS.256.0F.WIG 5E /r
VDIVPS ymm1, ymm2, ymm3/m256
RVM
V/V
AVX
EVEX.NDS.128.0F.W0 5E /r
VDIVPS xmm1 {k1}{z}, xmm2,
xmm3/m128/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.256.0F.W0 5E /r
VDIVPS ymm1 {k1}{z}, ymm2,
ymm3/m256/m32bcst
FV
V/V
AVX512VL
AVX512F
EVEX.NDS.512.0F.W0 5E /r
VDIVPS zmm1 {k1}{z}, zmm2,
zmm3/m512/m32bcst{er}
FV
V/V
AVX512F
Description
Divide packed single-precision floating-point values
in xmm1 by packed single-precision floating-point
values in xmm2/mem.
Divide packed single-precision floating-point values
in xmm2 by packed single-precision floating-point
values in xmm3/mem.
Divide packed single-precision floating-point values
in ymm2 by packed single-precision floating-point
values in ymm3/mem.
Divide packed single-precision floating-point values
in xmm2 by packed single-precision floating-point
values in xmm3/m128/m32bcst and write results to
xmm1 subject to writemask k1.
Divide packed single-precision floating-point values
in ymm2 by packed single-precision floating-point
values in ymm3/m256/m32bcst and write results to
ymm1 subject to writemask k1.
Divide packed single-precision floating-point values
in zmm2 by packed single-precision floating-point
values in zmm3/m512/m32bcst and write results to
zmm1 subject to writemask k1.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
FV
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Performs a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source
operand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the
second source operand (the third operand). Results are written to the destination operand (the first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.
DIVPS—Divide Packed Single-Precision Floating-Point Values
Vol. 2A 3-291
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
FOR j  0 TO KL-1
i  j * 32
IF k1[j] OR *no writemask*
THEN
IF (EVEX.b = 1) AND (SRC2 *is memory*)
THEN
DEST[i+31:i]  SRC1[i+31:i] / SRC2[31:0]
ELSE
DEST[i+31:i]  SRC1[i+31:i] / SRC2[i+31:i]
FI;
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[i+31:i] remains unchanged*
ELSE
; zeroing-masking
DEST[i+31:i]  0
FI
FI;
ENDFOR
DEST[MAX_VL-1:VL]  0
VDIVPS (VEX.256 encoded version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[159:128] SRC1[159:128] / SRC2[159:128]
DEST[191:160]SRC1[191:160] / SRC2[191:160]
DEST[223:192] SRC1[223:192] / SRC2[223:192]
DEST[255:224] SRC1[255:224] / SRC2[255:224].
DEST[MAX_VL-1:256] 0;
VDIVPS (VEX.128 encoded version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] 0
3-292 Vol. 2A
DIVPS—Divide Packed Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-L
DIVPS (128-bit Legacy SSE version)
DEST[31:0] SRC1[31:0] / SRC2[31:0]
DEST[63:32] SRC1[63:32] / SRC2[63:32]
DEST[95:64] SRC1[95:64] / SRC2[95:64]
DEST[127:96] SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)
Intel C/C++ Compiler Intrinsic Equivalent
VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);
VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);
DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal
Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.
DIVPS—Divide Packed Single-Precision Floating-Point Values
Vol. 2A 3-293
INSTRUCTION SET REFERENCE, A-L
DIVSD—Divide Scalar Double-Precision Floating-Point Value
Opcode/
Instruction
Op /
En
RM
64/32
bit Mode
Support
V/V
CPUID
Feature
Flag
SSE2
F2 0F 5E /r
DIVSD xmm1, xmm2/m64
VEX.NDS.128.F2.0F.WIG 5E /r
VDIVSD xmm1, xmm2, xmm3/m64
RVM
V/V
AVX
EVEX.NDS.LIG.F2.0F.W1 5E /r
VDIVSD xmm1 {k1}{z}, xmm2,
xmm3/m64{er}
T1S
V/V
AVX512F
Description
Divide low double-precision floating-point value in
xmm1 by low double-precision floating-point value
in xmm2/m64.
Divide low double-precision floating-point value in
xmm2 by low double-precision floating-point value
in xmm3/m64.
Divide low double-precision floating-point value in
xmm2 by low double-precision floating-point value
in xmm3/m64.
Instruction Operand Encoding
Op/En
Operand 1
Operand 2
Operand 3
Operand 4
RM
ModRM:reg (r, w)
ModRM:r/m (r)
NA
NA
RVM
ModRM:reg (w)
VEX.vvvv
ModRM:r/m (r)
NA
T1S
ModRM:reg (w)
EVEX.vvvv
ModRM:r/m (r)
NA
Description
Divides the low double-precision floating-point value in the first source operand by the low double-precision
floating-point value in the second source operand, and stores the double-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 64-bit memory location. The first source
and destination are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL1:64) of the corresponding ZMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits
127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword
element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low quadword element of the destination is updated according to the writemask.
Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpredictable behavior across different processor generations.
3-294 Vol. 2A
DIVSD—Divide Scalar Double-Precision Floating-Point Value
INSTRUCTION SET REFERENCE, A-L
Operation
VDIVSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
THEN
SET_RM(EVEX.RC);
ELSE
SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
THEN
DEST[63:0]  SRC1[63:0] / SRC2[63:0]
ELSE
IF *merging-masking*
; merging-masking
THEN *DEST[63:0] remains unchanged*
ELSE
; zeroing-masking
THEN DEST[63:0]  0
FI;
FI;
DEST[127:64]  SRC1[127:64]
DEST[MAX_VL-1:128]  0
VDIVSD (VEX.128 encoded version)
DEST[63:0] SRC1[63:0] / SRC2[63:0]
DEST[127:64] SRC1[127:64]
DEST[MAX_VL-1:1