Intel® Arria® 10 Transceiver PHY User Guide

Intel® Arria® 10 Transceiver PHY
User Guide
Updated for Intel® Quartus® Prime Design Suite: 17.1
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UG-01143 | 2017.11.06
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Contents
Contents
1 Arria® 10 Transceiver PHY Overview ..............................................................................7
1.1 Device Transceiver Layout.......................................................................................8
1.1.1 Arria 10 GX Device Transceiver Layout..........................................................9
1.1.2 Arria 10 GT Device Transceiver Layout........................................................ 14
1.1.3 Arria 10 GX and GT Device Package Details ................................................ 16
1.1.4 Arria 10 SX Device Transceiver Layout........................................................ 16
1.1.5 Arria 10 SX Device Package Details............................................................ 18
1.2 Transceiver PHY Architecture Overview................................................................... 19
1.2.1 Transceiver Bank Architecture.....................................................................19
1.2.2 PHY Layer Transceiver Components............................................................ 24
1.2.3 Transceiver Phase-Locked Loops.................................................................27
1.2.4 Clock Generation Block (CGB)....................................................................28
1.3 Calibration........................................................................................................... 28
2 Implementing Protocols in Arria 10 Transceivers.......................................................... 30
2.1 Transceiver Design IP Blocks.................................................................................. 30
2.2 Transceiver Design Flow.........................................................................................31
2.2.1 Select and Instantiate the PHY IP Core.........................................................31
2.2.2 Configure the PHY IP Core..........................................................................33
2.2.3 Generate the PHY IP Core.......................................................................... 34
2.2.4 Select the PLL IP Core............................................................................... 34
2.2.5 Configure the PLL IP Core......................................................................... 36
2.2.6 Generate the PLL IP Core .......................................................................... 37
2.2.7 Reset Controller ....................................................................................... 37
2.2.8 Create Reconfiguration Logic...................................................................... 37
2.2.9 Connect the PHY IP to the PLL IP Core and Reset Controller............................ 38
2.2.10 Connect Datapath ................................................................................. 38
2.2.11 Make Analog Parameter Settings .............................................................. 38
2.2.12 Compile the Design................................................................................. 39
2.2.13 Verify Design Functionality....................................................................... 39
2.3 Arria 10 Transceiver Protocols and PHY IP Support....................................................39
2.4 Using the Arria 10 Transceiver Native PHY IP Core..................................................... 43
2.4.1 Presets.................................................................................................... 46
2.4.2 General and Datapath Parameters .............................................................. 46
2.4.3 PMA Parameters.......................................................................................49
2.4.4 Enhanced PCS Parameters .........................................................................53
2.4.5 Standard PCS Parameters......................................................................... 60
2.4.6 PCS Direct ............................................................................................. 65
2.4.7 Dynamic Reconfiguration Parameters........................................................... 65
2.4.8 PMA Ports............................................................................................... 70
2.4.9 Enhanced PCS Ports................................................................................. 74
2.4.10 Standard PCS Ports................................................................................. 84
2.4.11 IP Core File Locations.............................................................................. 89
2.4.12 Unused Transceiver RX Channels............................................................... 91
2.4.13 Unsupported Features..............................................................................92
2.5 Interlaken...........................................................................................................92
2.5.1 Metaframe Format and Framing Layer Control Word......................................93
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2.5.2 Interlaken Configuration Clocking and Bonding.............................................95
2.5.3 How to Implement Interlaken in Arria 10 Transceivers.................................. 101
2.5.4 Design Example...................................................................................... 104
2.5.5 Native PHY IP Parameter Settings for Interlaken......................................... 105
2.6 Ethernet............................................................................................................ 109
2.6.1 Gigabit Ethernet (GbE) and GbE with IEEE 1588v2...................................... 110
2.6.2 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC
Variants................................................................................................ 122
2.6.3 10GBASE-KR PHY IP Core ........................................................................133
2.6.4 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core........................................ 162
2.6.5 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core........................................197
2.6.6 XAUI PHY IP Core....................................................................................212
2.6.7 Acronyms..............................................................................................226
2.7 PCI Express (PIPE)............................................................................................. 227
2.7.1 Transceiver Channel Datapath for PIPE....................................................... 228
2.7.2 Supported PIPE Features.......................................................................... 229
2.7.3 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes.................... 238
2.7.4 How to Implement PCI Express (PIPE) in Arria 10 Transceivers..................... 244
2.7.5 Native PHY IP Parameter Settings for PIPE ................................................ 246
2.7.6 fPLL IP Parameter Core Settings for PIPE.................................................... 251
2.7.7 ATX PLL IP Parameter Core Settings for PIPE ..............................................253
2.7.8 Native PHY IP Ports for PIPE.................................................................... 255
2.7.9 fPLL Ports for PIPE...................................................................................263
2.7.10 ATX PLL Ports for PIPE............................................................................264
2.7.11 Preset Mappings to TX De-emphasis.........................................................265
2.7.12 How to Place Channels for PIPE Configurations.......................................... 266
2.7.13 PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate................ 273
2.7.14 Using Transceiver Toolkit (TTK)/System Console/Reconfiguration Interface
to manually tune Arria 10 PCIe designs (Hard IP(HIP) and PIPE) (For
debug only)...........................................................................................276
2.8 CPRI.................................................................................................................278
2.8.1 Transceiver Channel Datapath and Clocking for CPRI....................................279
2.8.2 Supported Features for CPRI ...................................................................280
2.8.3 Word Aligner in Manual Mode for CPRI........................................................282
2.8.4 How to Implement CPRI in Arria 10 Transceivers......................................... 283
2.8.5 Native PHY IP Parameter Settings for CPRI................................................ 284
2.9 Other Protocols...................................................................................................288
2.9.1 Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations
of Enhanced PCS.................................................................................... 288
2.9.2 Using the Basic/Custom, Basic/Custom with Rate Match Configurations of
Standard PCS........................................................................................ 299
2.9.3 Design Considerations for Implementing Arria 10 GT Channels...................... 318
2.9.4 How to Implement PCS Direct Transceiver Configuration Rule........................ 323
2.10 Simulating the Transceiver Native PHY IP Core...................................................... 324
2.10.1 NativeLink Simulation Flow..................................................................... 325
2.10.2 Scripting IP Simulation...........................................................................330
2.10.3 Custom Simulation Flow......................................................................... 331
3 PLLs and Clock Networks............................................................................................. 335
3.1 PLLs.................................................................................................................. 337
3.1.1 Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs................... 337
3.1.2 ATX PLL................................................................................................. 338
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3.1.3 fPLL.......................................................................................................347
3.1.4 CMU PLL................................................................................................ 356
3.2 Input Reference Clock Sources.............................................................................360
3.2.1 Dedicated Reference Clock Pins................................................................ 362
3.2.2 Receiver Input Pins..................................................................................362
3.2.3 PLL Cascading as an Input Reference Clock Source...................................... 363
3.2.4 Reference Clock Network..........................................................................363
3.2.5 Global Clock or Core Clock as an Input Reference Clock................................ 363
3.3 Transmitter Clock Network...................................................................................363
3.3.1 x1 Clock Lines........................................................................................ 364
3.3.2 x6 Clock Lines........................................................................................ 365
3.3.3 xN Clock Lines........................................................................................ 367
3.3.4 GT Clock Lines........................................................................................ 369
3.4 Clock Generation Block........................................................................................ 371
3.5 FPGA Fabric-Transceiver Interface Clocking............................................................. 372
3.6 Transmitter Data Path Interface Clocking................................................................ 374
3.7 Receiver Data Path Interface Clocking.................................................................... 375
3.8 Unused/Idle Clock Line Requirements.................................................................... 377
3.9 Channel Bonding.................................................................................................377
3.9.1 PMA Bonding.......................................................................................... 377
3.9.2 PMA and PCS Bonding..............................................................................379
3.9.3 Selecting Channel Bonding Schemes.......................................................... 380
3.9.4 Skew Calculations................................................................................... 381
3.10 PLL Feedback and Cascading Clock Network.......................................................... 381
3.11 Using PLLs and Clock Networks........................................................................... 386
3.11.1 Non-bonded Configurations.....................................................................386
3.11.2 Bonded Configurations........................................................................... 391
3.11.3 Implementing PLL Cascading...................................................................396
3.11.4 Mix and Match Example..........................................................................397
3.11.5 Timing Closure Recommendations............................................................401
4 Resetting Transceiver Channels................................................................................... 402
4.1 When Is Reset Required? .................................................................................... 402
4.2 Transceiver PHY Implementation........................................................................... 403
4.3 How Do I Reset?................................................................................................. 404
4.3.1 Model 1: Default Model............................................................................ 404
4.3.2 Model 2: Acknowledgment Model...............................................................413
4.3.3 Transceiver Blocks Affected by Reset and Powerdown Signals........................ 417
4.4 Using the Transceiver PHY Reset Controller............................................................. 418
4.4.1 Parameterizing the Transceiver PHY Reset Controller IP................................ 420
4.4.2 Transceiver PHY Reset Controller Parameters.............................................. 420
4.4.3 Transceiver PHY Reset Controller Interfaces................................................ 423
4.4.4 Transceiver PHY Reset Controller Resource Utilization................................... 426
4.5 Using a User-Coded Reset Controller......................................................................426
4.5.1 User-Coded Reset Controller Signals.......................................................... 427
4.6 Combining Status or PLL Lock Signals ................................................................... 428
4.7 Timing Constraints for Bonded PCS and PMA Channels............................................. 428
5 Arria 10 Transceiver PHY Architecture......................................................................... 431
5.1 Arria 10 PMA Architecture....................................................................................431
5.1.1 Transmitter............................................................................................ 431
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Contents
5.1.2 Receiver.................................................................................................434
5.1.3 Loopback............................................................................................... 444
5.2 Arria 10 Enhanced PCS Architecture......................................................................445
5.2.1 Transmitter Datapath.............................................................................. 446
5.2.2 Receiver Datapath.................................................................................. 455
5.3 Arria 10 Standard PCS Architecture...................................................................... 463
5.3.1 Transmitter Datapath...............................................................................464
5.3.2 Receiver Datapath................................................................................... 469
5.4 Arria 10 PCI Express Gen3 PCS Architecture.......................................................... 479
5.4.1 Transmitter Datapath.............................................................................. 480
5.4.2 Receiver Datapath................................................................................... 481
5.4.3 PIPE Interface.........................................................................................482
6 Reconfiguration Interface and Dynamic Reconfiguration ........................................... 484
6.1 Reconfiguring Channel and PLL Blocks....................................................................484
6.2 Interacting with the Reconfiguration Interface......................................................... 485
6.2.1 Reading from the Reconfiguration Interface................................................ 487
6.2.2 Writing to the Reconfiguration Interface..................................................... 487
6.3 Configuration Files.............................................................................................. 488
6.4 Multiple Reconfiguration Profiles............................................................................ 491
6.5 Embedded Reconfiguration Streamer..................................................................... 492
6.6 Arbitration..........................................................................................................494
6.7 Recommendations for Dynamic Reconfiguration.......................................................497
6.8 Steps to Perform Dynamic Reconfiguration............................................................. 498
6.9 Direct Reconfiguration Flow.................................................................................. 501
6.10 Native PHY IP or PLL IP Core Guided Reconfiguration Flow...................................... 501
6.11 Reconfiguration Flow for Special Cases................................................................. 503
6.11.1 Switching Transmitter PLL .....................................................................503
6.11.2 Switching Reference Clocks.....................................................................505
6.12 Changing PMA Analog Parameters.......................................................................509
6.12.1 Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow.................. 512
6.12.2 Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow... 513
6.12.3 CTLE Settings in Triggered Adaptation Mode..............................................513
6.12.4 Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow.... 515
6.13 Ports and Parameters.........................................................................................517
6.14 Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks....................... 524
6.15 Embedded Debug Features................................................................................. 526
6.15.1 Altera Debug Master Endpoint................................................................. 526
6.15.2 Optional Reconfiguration Logic................................................................ 526
6.16 Using Data Pattern Generators and Checkers........................................................ 532
6.16.1 Using PRBS Data Pattern Generator and Checker...................................... 532
6.16.2 Using Pseudo Random Pattern Mode.........................................................541
6.17 Timing Closure Recommendations....................................................................... 542
6.18 Unsupported Features........................................................................................ 545
6.19 Arria 10 Transceiver Register Map....................................................................... 546
7 Calibration................................................................................................................... 547
7.1 Reconfiguration Interface and Arbitration with PreSICE Calibration Engine ..................547
7.2 Calibration Registers............................................................................................549
7.2.1 Avalon-MM Interface Arbitration Registers.................................................. 549
7.2.2 Transceiver Channel Calibration Registers................................................... 550
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Contents
7.2.3 Fractional PLL Calibration Registers............................................................550
7.2.4 ATX PLL Calibration Registers....................................................................551
7.2.5 Capability Registers................................................................................. 551
7.2.6 Rate Switch Flag Register......................................................................... 553
7.3 Power-up Calibration........................................................................................... 554
7.4 User Recalibration............................................................................................... 556
7.4.1 Recalibration After Transceiver Reference Clock Frequency or Data Rate
Change................................................................................................. 559
7.5 Calibration Example.............................................................................................561
7.5.1 ATX PLL Recalibration.............................................................................. 561
7.5.2 Fractional PLL Recalibration...................................................................... 561
7.5.3 CDR/CMU PLL Recalibration...................................................................... 562
7.5.4 PMA Recalibration....................................................................................562
8 Analog Parameter Settings......................................................................................... 563
8.1
8.2
8.3
8.4
Making Analog Parameter Settings using the Assignment Editor.................................563
Updating Quartus Settings File with the Known Assignment..................................... 563
Analog Parameter Settings List.............................................................................564
Receiver General Analog Settings......................................................................... 566
8.4.1 XCVR_A10_RX_LINK...............................................................................566
8.4.2 XCVR_A10_RX_TERM_SEL.......................................................................567
8.4.3 XCVR_VCCR_VCCT_VOLTAGE - RX.............................................................567
8.5 Receiver Analog Equalization Settings................................................................... 568
8.5.1 CTLE Settings......................................................................................... 568
8.5.2 VGA Settings.......................................................................................... 571
8.5.3 Decision Feedback Equalizer (DFE) Settings............................................... 572
8.6 Transmitter General Analog Settings..................................................................... 574
8.6.1 XCVR_A10_TX_LINK............................................................................... 574
8.6.2 XCVR_A10_TX_TERM_SEL........................................................................ 575
8.6.3 XCVR_A10_TX_COMPENSATION_EN......................................................... 575
8.6.4 XCVR_VCCR_VCCT_VOLTAGE - TX............................................................. 576
8.6.5 XCVR_A10_TX_SLEW_RATE_CTRL............................................................. 577
8.7 Transmitter Pre-Emphasis Analog Settings............................................................. 578
8.7.1 XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T.............................................578
8.7.2 XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T.............................................578
8.7.3 XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP.........................................579
8.7.4 XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP........................................ 579
8.7.5 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T.......................... 580
8.7.6 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T.......................... 580
8.7.7 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP...................... 581
8.7.8 XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP...................... 582
8.8 Transmitter VOD Settings..................................................................................... 582
8.8.1 XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL.............................................. 582
8.9 Dedicated Reference Clock Settings....................................................................... 583
8.9.1 XCVR_A10_REFCLK_TERM_TRISTATE........................................................583
8.9.2 XCVR_A10_TX_XTX_PATH_ANALOG_MODE.................................................584
8.10 Unused Transceiver RX Channels Settings............................................................. 584
9 Document Revision History for Current Release ......................................................... 585
9.1 Document Revision History for Previous Releases.................................................... 586
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1 Arria® 10 Transceiver PHY Overview
This user guide provides details about the Arria® 10 transceiver physical (PHY) layer
architecture, PLLs, clock networks, and transceiver PHY IP. It also provides protocol
specific implementation details and describes features such as transceiver reset and
dynamic reconfiguration of transceiver channels and PLLs.
Intel® Arria 10 FPGAs offer up to 96 GX transceiver channels with integrated advanced
high speed analog signal conditioning and clock data recovery techniques for chip-tochip, chip-to-module, and backplane applications.
The Arria 10 GX and SX devices have GX transceiver channels that can support data
rates up to 17.4 Gbps for chip-to-chip applications and 12.5 Gbps for backplane
applications.
The Arria 10 GT device has up to 6 GT transceiver channels, that can support data
rates up to 25.8 Gbps for short reach chip-to-chip and chip-to-module applications.
Additionally, the GT devices have GX transceiver channels that can support data rates
up to 17.4 Gbps for chip-to-chip and 12.5 Gbps for backplane applications. If all 6 GT
channels are used in GT mode, then the GT device also has up to 54 GX transceiver
channels.
The Arria 10 transceivers support reduced power modes with data rates up to 11.3
Gbps (chip-to-chip) for critical power sensitive designs. In GX devices that have
transceivers on both sides of the device, each side can be operated independently in
standard and reduced power modes. You can achieve transmit and receive data rates
below 1.0 Gbps with oversampling.
Table 1.
Data Rates Supported by GX Transceiver Channel Type
Device Variant
Standard Power Mode
Chip-to-Chip
SX
(3)
GX(3)
GT
(4)
(1), (2)
Backplane
Reduced Power Mode
(1), (2)
Chip-to-Chip
1.0 Gbps to 17.4 Gbps
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 11.3 Gbps
1.0 Gbps to 17.4 Gbps
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 11.3 Gbps
1.0 Gbps to 17.4 Gbps
1.0 Gbps to 12.5 Gbps
1.0 Gbps to 11.3 Gbps
(1)
To operate GX transceiver channels at designated data rates in standard and reduced power
modes, apply the corresponding core and periphery power supplies. Refer to the Arria 10
Device Datasheet for more details.
(2)
The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For
transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter. For
receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
(3)
For SX and GX device variants, the maximum transceiver data rates are specified for the
fastest (–1) transceiver speed grade.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
1 Arria® 10 Transceiver PHY Overview
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Table 2.
Data Rates Supported by GT Transceiver Channel Type
Device Variant
(4)
Data Rates(5),
(2)
Chip-to-Chip
GT
Note:
Backplane
1.0 Gbps to 25.8 Gbps
1.0 Gbps to 12.5 Gbps
The device data rates depend on the device speed grade. Refer to Intel Arria 10
Device Datasheet for details on available speed grades and supported data rates.
Related Links
•
Intel Arria 10 Device Datasheet
•
Intel Arria 10 Device Overview
1.1 Device Transceiver Layout
Figure 1.
Arria 10 FPGA Architecture Block Diagram
PCI Express Gen3 Hard IP
PLLs
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
Transceiver Channels
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
I/O PLLs
Core Logic Fabric
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Transceiver Channels
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
PLLs
PCI Express Gen3 Hard IP
PCI Express Gen3 Hard IP
The transceiver channels are placed on the left side periphery in most Arria 10 devices. For larger Arria 10
devices, additional transceiver channels are placed on the right side periphery.
(4)
For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver
speed grade.
(5)
Because the GT transceiver channels are designed for peak performance, they do not have a
reduced power mode of operation.
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1.1.1 Arria 10 GX Device Transceiver Layout
The largest Arria 10 GX device includes 96 transceiver channels. A column array of
eight transceiver banks on the left and the right side periphery of the device is shown
in the following figure. Each transceiver bank has six transceiver channels. Some
devices have transceiver banks with only three channels. The transceiver banks with
only three channels are the uppermost transceiver banks. Arria 10 devices also include
PCI Express Hard IP blocks.
The figures below illustrate different transceiver bank layouts for Arria 10 GX device
variants.
For more information about PCIe* Hard IP transceiver placements, refer to Related
Information at the end of this section.
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Figure 2.
Arria 10 GX Devices with 96 Transceiver Channels and Four PCIe Hard IP
Blocks
GXBL1J
Transceiver
Bank
GX 115 UF45
GX 090 UF45
Transceiver
Bank
GXBR4J
Transceiver
Bank
GXBL1I
Transceiver
Bank
Transceiver
Bank
GXBR4I
GXBL1H
Transceiver
Bank
Transceiver
Bank
GXBR4H
GXBL1G
Transceiver
Bank
Transceiver
Bank
GXBR4G
GXBL1F
Transceiver
Bank
Transceiver
Bank
GXBR4F
GXBL1E
Transceiver
Bank
Transceiver
Bank
GXBR4E
GXBL1D
Transceiver
Bank
Transceiver
Bank
GXBR4D
GXBL1C
(1)
Transceiver
Bank
Transceiver
Bank
GXBR4C
(2)
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 96 transceiver channels and four PCIe Hard IP blocks.
Intel® Arria® 10 Transceiver PHY User Guide
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CH5
CH4
CH3
CH2
CH1
CH0
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Figure 3.
Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard
IP Blocks.
GXBL1H
Transceiver
Bank
GXBL1G
Transceiver
Bank
GXBL1F
Transceiver
Bank
GXBL1E
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
(1)
GX 115 SF45
GX 090 SF45
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
GX 115 NF45
GX 090 NF45
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
PCIe
Gen1 - Gen3
Hard IP
Transceiver
Bank
GXBR4H
Transceiver
Bank
GXBR4G
Transceiver
Bank
GXBR4F
Transceiver
Bank
GXBR4E
Transceiver
Bank
GXBR4D
Transceiver
Bank
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
GXBR4C
(2)
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 72 transceiver channels and four PCIe Hard IP blocks.
Arria 10 GX device with 48 transceiver channels and four PCIe Hard IP blocks.
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Figure 4.
Arria 10 GX Devices with 66 Transceiver Channels and Three PCIe Hard IP
Blocks
GXBL1H
Transceiver
Bank
GXBL1G
GX 115 RF40
GX 090 RF40
Transceiver
Bank
GXBR4J
Transceiver
Bank
Transceiver
Bank
GXBR4I
GXBL1F
Transceiver
Bank
Transceiver
Bank
GXBR4H
GXBL1E
Transceiver
Bank
Transceiver
Bank
GXBR4G
GXBL1D
Transceiver
Bank
Transceiver
Bank
GXBR4F
GXBL1C
(1)
Transceiver
Bank
Transceiver
Bank
GXBR4E
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
PCIe
Gen1 - Gen3
Hard IP
Notes:
(1) Nomenclature of left column bottom transceiver banks always ends with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 66 transceiver channels and three PCIe Hard IP blocks.
Intel® Arria® 10 Transceiver PHY User Guide
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(2)
Transceiver
Bank
CH2
CH1
CH0
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
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Figure 5.
Arria 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe
Hard IP Blocks
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1J
GX 115 NF40
GX 090 NF40
GX 066 NF40
GX 057 NF40
Transceiver
Bank
GXBL1I
Transceiver
Bank
GXBL1H
Transceiver
Bank
GXBL1G
Transceiver
Bank
GXBL1F
Transceiver
Bank
GXBL1E
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
GX 066 KF40
GX 057 KF40
GX 066 KF35
GX 057 KF35
GX 048 KF35
PCIe
Gen1 - Gen3
Hard IP
GX 115 HF34
GX 090 HF34
GX 066 HF34
GX 057 HF34
GX 048 HF34
GX 032 HF35
GX 032 HF34
GX 027 HF35
GX 027 HF34
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 48 transceiver channels and two PCIe Hard IP blocks.
Arria 10 GX device with 36 transceiver channels and two PCIe Hard IP blocks.
Arria 10 GX device with 24 transceiver channels and two PCIe Hard IP blocks.
Intel® Arria® 10 Transceiver PHY User Guide
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Figure 6.
Arria 10 GX Devices with 12 Transceiver Channels and One PCIe Hard IP
Block
CH5
CH4
CH3
CH2
CH1
CH0
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
GX 048 EF29
GX 032 EF29
GX 027 EF29
GX 032 EF27
GX 027 EF27
GX 022 EF29
GX 022 EF27
GX 016 EF29
GX 016 EF27
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with 12 transceiver channels and one PCIe Hard IP block.
Figure 7.
Arria 10 GX Devices with 6 Transceiver Channels and One PCIe Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C
Transceiver
Bank
PCIe Hard IP (1)
GX 022 CU19
GX 016 CU19
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with CvP capabilities.
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 GX device with six transceiver channels and one PCIe Hard IP block.
Related Links
•
Intel Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.2 Arria 10 GT Device Transceiver Layout
The Arria 10 GT device has 72 transceiver channels and four PCI Express Hard IP
blocks. A total of 6 GT transceiver channels that can support data rates up to 25.8
Gbps.
In the GT device, transceiver banks GXBL1E, GXBL1G, and GXBL1H each contain two
GT transceiver channels. Transceiver banks GXBL1E and GXBL1H channels 3 and 4 can
be used as GT or GX transceiver channel. Transceiver bank GXBL1G channels 0 and 1
can be used as GT or GX transceiver channels. When none of the GT capable
transceiver channels are used as GT transceiver channels, the entire transceiver
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channels in the bank can be reconfigured as GX transceiver channels. However, when
any of the GT capable transceiver channels in transceiver banks GXBL1E, GXBL1G,
and GXBL1H is enabled as a GT transceiver channel, the remaining channels in the
transceiver bank cannot be used with the exception of the other GT capable channel in
the transceiver bank.
If you're using GT transceivers in bank GXBL1E, then the adjacent PCIe Hard IP block
cannot be used.
Figure 8.
Arria 10 GT Device with 72 Transceiver Channels and Four PCIe Hard IP
Blocks
CH5
CH4
CH3
CH2
CH1
CH0
GX or Restricted
GT or GX
GT or GX
GX or Restricted
GX or Restricted
GX or Restricted
GT Channels
Capable of Short
Reach 25.8 Gbps
Transceiver
Bank
CH5
CH4
CH3
CH2
CH1
CH0
GX or Restricted
GX or Restricted
GX or Restricted
GX or Restricted
GT or GX
GT or GX
GXBL1H
Transceiver
Bank
GXBL1G
Transceiver
Bank
GXBL1F
Transceiver
Bank
GXBL1E
Transceiver
Bank (3)
GXBL1D
Transceiver
Bank
GXBL1C
(1)
Transceiver
Bank
GT 115 SF45
GT 090 SF45
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
Hard IP
GXBR4H
Transceiver
Bank
GXBR4G
Transceiver
Bank
GXBR4F
Transceiver
Bank
GXBR4E
Transceiver
Bank
GXBR4D
Transceiver
Bank
GXBR4C
(2)
Notes:
(1) Nomenclature of left column bottom transceiver banks always end with “C”.
(2) Nomenclature of right column bottom transceiver banks may end with “C”, “D”, or “E”.
(3) If a GT channel is used in transceiver bank GXBL1E, the PCIe Hard IP adjacent to GXBL1F and GXBL1E cannot be used.
Legend:
GT transceiver channels (channel 0, 1, 3, and 4).
GX transceiver channels (channel 2 and 5) with usage restrictions.
GX transceiver channels without usage restrictions.
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
The GT device has 72 transceiver channels, which include 6 GT transceiver channels
supporting data rates greater than 17.4 Gbps. If all 6 GT transceiver channels are
used in GT mode, then there will be 54 GX transceiver channels that can drive chip to
chip data rates up to 17.4 Gbps and backplanes at data rates up to 12.5 Gbps and 12
GX channels that are unusable.
In the GT device, the GX transceiver channels on the entire right side can be used in
standard or reduced power mode. In GT devices where none of the GT channels are
used to operate in GT data rates above 17.4 Gbps, the transceiver channels on either
the entire right side or entire left side can be used as GX channels in standard or
reduced power mode.
Related Links
•
Intel Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
Intel® Arria® 10 Transceiver PHY User Guide
15
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•
Intel Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.3 Arria 10 GX and GT Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Arria 10 GX and GT devices.
Table 3.
Package Details for GX Devices with Transceivers and Hard IP Blocks Located
on the Left Side Periphery of the Device
•
Package U19: 19mm x 19mm package; 484 pins.
•
Package F27: 27mm x 27mm package; 672 pins.
•
Package F29: 29mm x 29mm package; 780 pins.
•
Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
•
Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver
channels.
Device
U19
F27
F29
F34
F35
K F40
N F40
Transceiver Count, PCIe Hard IP Block Count
GX 016
6, 1
12, 1
12, 1
GX 022
6, 1
12, 1
12, 1
GX 027
12, 1
12, 1
24, 2
24, 2
GX 032
12, 1
12, 1
24, 2
24, 2
12, 1
24, 2
36, 2
GX 057
24, 2
36, 2
36, 2
48, 2
GX 066
24, 2
36, 2
36, 2
48, 2
GX 090
24, 2
48, 2
GX 115
24, 2
48, 2
GX 048
Table 4.
Device
Package Details for GX and GT Devices with Transceivers and Hard IP Blocks
Located on the Left and Right Side Periphery of the Device
•
Package F40: 40 mm x 40 mm package size; 1517 pins. R = 66 transceiver channels.
•
Package F45: 45mm x 45mm package size; 1932 pins. N = 48 transceiver channels, S = 72 transceiver
channels, U = 96 transceiver channels.
•
If you're using GT transceivers in bank GXBL1E, the nth adjacent PCIe Hard IP block cannot be used.
R F40
N F45
S F45
U F45
Transceiver Count, PCIe Hard IP Block Count
GX 090
66, 3
48, 4
72, 4
96, 4
GX 115
66, 3
48, 4
72, 4
96, 4
GT 090
72, 4
GT 115
72, 4
1.1.4 Arria 10 SX Device Transceiver Layout
The largest SX device includes 48 transceiver channels. All SX devices include GX
transceiver channel type. The transceiver banks in SX devices are located on the left
side periphery of the device.
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For more information about PCIe Hard IP transceiver placements, refer to Related
Information at the end of this section.
Figure 9.
Arria 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP
Blocks
CH5
CH4
CH3
CH2
CH1
CH0
GXBL1J
Transceiver
Bank
GXBL1I
Transceiver
Bank
GXBL1H
Transceiver
Bank
GXBL1G
Transceiver
Bank
GXBL1F
Transceiver
Bank
GXBL1E
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
SX 066 NF40
SX 057 NF40
SX 066 KF40
SX 066 KF35
SX 057 KF40
SX 057 KF35
SX 048 KF35
PCIe
Gen1 - Gen3
Hard IP
SX 066 HF34
SX 057 HF34
SX 048 HF34
SX 032 HF35
SX 032 HF34
SX 027 HF35
SX 027 HF34
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1- Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with 48 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 36 transceiver channels and two PCIe Hard IP blocks.
Arria 10 SX device with 24 transceiver channels and two PCIe Hard IP blocks.
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Figure 10.
Arria 10 SX Device with 12 Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
PCIe
Gen1 - Gen3
Hard IP
(with CvP)
SX 048 EF29
SX 032 EF29
SX 032 EF27
SX 027 EF29
SX 027 EF27
SX 022 EF29
SX 022 EF27
SX 016 EF29
SX 016 EF27
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with 12 transceiver channels and one Hard IP block.
Figure 11.
Arria 10 SX Device with Six Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Transceiver
Bank
GXBL1C
Transceiver
Bank
PCIe Hard IP (1)
SX 022 CU19
SX 016 CU19
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with Configuration via Protocol (CvP) capabilities.
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with six transceiver channels and one PCIe Hard IP block.
Related Links
•
Intel Arria 10 Avalon-ST Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
•
Intel Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
1.1.5 Arria 10 SX Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Arria 10 SX devices.
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Table 5.
Device
Package Details for SX Devices with Transceivers and Hard IP Blocks Located
on the Left Side Periphery of the Device
•
Package U19: 19mm x 19mm package; 484 pins.
•
Package F27: 27mm x 27mm package; 672 pins.
•
Package F29: 29mm x 29mm package; 780 pins.
•
Packages F34 and F35: 35 mm x 35 mm package size; 1152 pins.
•
Package F40: 40 mm x 40 mm package size; 1517 pins. K = 36 transceiver channels, N = 48 transceiver
channels.
U19
F27
F29
F34
F35
K F40
N F40
Transceiver Count, PCIe Hard IP Block Count
SX 016
6, 1
12, 1
12, 1
SX 022
6, 1
12, 1
12, 1
SX 027
12, 1
12, 1
24, 2
24, 2
SX 032
12, 1
12, 1
24, 2
24, 2
12, 1
24, 2
36, 2
SX 057
24, 2
36, 2
36, 2
48, 2
SX 066
24, 2
36, 2
36, 2
48, 2
SX 048
1.2 Transceiver PHY Architecture Overview
A link is defined as a single entity communication port. A link can have one or more
transceiver channels. A transceiver channel is synonymous with a transceiver lane.
For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of
10.3125 Gbps. A 40GBASE-R link has four transceiver channels. Each transceiver
channel operates at a lane data rate of 10.3125 Gbps. Four transceiver channels give
a total collective link bandwidth of 41.25 Gbps (40 Gbps before and after 64B/66B
Physical Coding Sublayer (PCS) encoding and decoding).
1.2.1 Transceiver Bank Architecture
The transceiver bank is the fundamental unit that contains all the functional blocks
related to the device's high speed serial transceivers.
Each transceiver bank includes six transceiver channels in all devices except for the
devices with 66 transceiver channels. Devices with 66 transceiver channels have both
six channel and three channel transceiver banks. The uppermost transceiver bank on
the left and the right side of these devices is a three channel transceiver bank. All
other devices contain only six channel transceiver banks.
The figures below show the transceiver bank architecture with the phase locked loop
(PLL) and clock generation block (CGB) resources available in each bank.
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Figure 12.
Three-Channel GX Transceiver Bank Architecture
Three-Channel GX Transceiver Bank
CH2
PMA
Channel PLL
(CDR Only)
Clock
Distribution
Network
PCS
Local CGB2
fPLL0
CH1
PMA
Channel PLL
(CMU/CDR)
CH0
PMA
Channel PLL
(CDR Only)
Note:
FPGA Core
Fabric
PCS
Local CGB1
Master
CGB0
PCS
Local CGB0
ATX
PLL0
This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 13.
Six-Channel GX Transceiver Bank Architecture
Six-Channel GX Transceiver Bank
CH5
PMA
Channel PLL
(CDR Only)
Clock
Distribution
Network
PCS
Local CGB5
fPLL1
CH4
PMA
Channel PLL
(CMU/CDR)
CH3
PMA
Channel PLL
(CDR Only)
CH2
PMA
Channel PLL
(CDR Only)
PCS
Local CGB4
Master
CGB1
PCS
Local CGB3
ATX
PLL1
FPGA Core
Fabric
PCS
Local CGB2
fPLL0
CH1
PMA
Channel PLL
(CMU/CDR)
CH0
PMA
Channel PLL
(CDR Only)
Note:
PCS
Local CGB1
Master
CGB0
PCS
Local CGB0
ATX
PLL0
This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 14.
GT Transceiver Bank Architecture
In the GT device, the transceiver banks GXBL1E, GXBL1G, and GXBL1H include GT channels.
Six-Channel GT Transceiver Bank GXBL1G
CH5
PMA
Channel PLL
(CDR Only)
Clock
Distribution
Network
PCS
Local CGB5
fPLL1
CH4
PMA
Channel PLL
(CMU/CDR)
CH3
PMA
Channel PLL
(CDR Only)
CH2
PMA
Channel PLL
(CDR Only)
PCS
Local CGB4
Master
CGB1
PCS
Local CGB3
ATX
PLL1
FPGA Core
Fabric
PCS
Local CGB2
fPLL0
CH1
PMA
Channel PLL
(CMU/CDR)
CH0
PMA
Channel PLL
(CDR Only)
PCS
Local CGB1
Master
CGB0
PCS
Local CGB0
ATX
PLL0
Legend
GT/GX Channel
Note:
GX Channel
This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
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Figure 15.
GT Transceiver Bank Architecture for Banks GXBL1E and GXBL1H
Six-Channel GT
Transceiver Banks GXBL1E and GXBL1H
CH5
PMA
Channel PLL
(CDR Only)
Clock
Distribution
Network
PCS
Local CGB5
fPLL1
CH4
PMA
Channel PLL
(CMU/CDR)
CH3
PMA
Channel PLL
(CDR Only)
CH2
PMA
Channel PLL
(CDR Only)
PCS
Local CGB4
Master
CGB1
PCS
Local CGB3
ATX
PLL1
FPGA Core
Fabric
PCS
Local CGB2
fPLL0
CH1
PMA
Channel PLL
(CMU/CDR)
CH0
PMA
Channel PLL
(CDR Only)
PCS
Local CGB1
Master
CGB0
PCS
Local CGB0
ATX
PLL0
Legend
GT/GX Channel
Note:
GX Channel
This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
The transceiver channels perform all the required PHY layer functions between the
FPGA fabric and the physical medium. The high speed clock required by the
transceiver channels is generated by the transceiver PLLs. The master and local clock
generation blocks (CGBs) provide the necessary high speed serial and low speed
parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.
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Related Links
•
PLLs and Clock Networks on page 335
•
Transceiver Basics
Online training course for transceivers.
1.2.2 PHY Layer Transceiver Components
Transceivers in Arria 10 devices support both Physical Medium Attachment (PMA) and
Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.
A PMA is the transceiver's electrical interface to the physical medium. The transceiver
PMA consists of standard blocks such as:
•
serializer/deserializer (SERDES)
•
clock and data recovery PLL
•
analog front end transmit drivers
•
analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS
blocks are fed by multiple clock networks driven by high performance PLLs. In PCS
Direct configuration, the data flow is through the PCS block, but all the internal PCS
blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA
fabric.
1.2.2.1 The GX Transceiver Channel
Figure 16.
GX Transceiver Channel in Full Duplex Mode.
FPGA Fabric
Transmitter PCS
Transmitter PMA
Standard PCS
Serializer
PCIe Gen3 PCS
(1)
KR FEC
(1)
Enhanced PCS
Soft PIPE
(Optional)
Hard IP
(Optional)
PCS Direct
Receiver PMA
Receiver PCS
Standard PCS
CDR
Deserializer
(1)
PCIe Gen3 PCS
KR FEC
(1)
Enhanced PCS
PCS Direct
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
Arria 10 GX transceiver channels have three types of PCS blocks that together support
continuous data rates between 1.0 Gbps and 17.4 Gbps.
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Table 6.
PCS Types Supported by GX Transceiver Channels
PCS Type
Data Rate
Standard PCS
1.0 Gbps to 12 Gbps
Enhanced PCS
1.0 Gbps
PCIe Gen3 PCS
8 Gbps
Note:
(6)
to 17.4 Gbps
1.
The GX channel can also operate in PCS Direct configuration for data rates from
1.0 Gbps to 17.4 Gbps. To operate GX transceiver channels in PCS Direct
designated data rates, refer to the Intel Arria 10 Device Datasheet for more
details on power supply, speed grade, and transceiver configurations requirement.
2.
The minimum operational data rate is 1.0 Gbps for both the transmitter and
receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be
applied at the transmitter. For receiver data rates less than 1.0 Gbps,
oversampling must be applied at the receiver.
3.
To operate GX transceiver channels with the PCS at designated data rates, refer to
the Intel Arria 10 Device Datasheet for more details on power supply, speed
grade, and transceiver configurations requirement.
Related Links
Intel Arria 10 Device Datasheet
1.2.2.2 The GT Transceiver Channel
The GT transceiver channels are used for supporting data rates from 17.4 Gbps to
25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary
configuration used to support GT data rates from 17.4 Gbps to 25.8 Gbps.
Alternatively, the Enhanced PCS in Basic low latency configuration can also be used to
support GT data rates from 17.4 Gbps to 25.8 Gbps. The GT transceiver channels can
also be configured as GX transceiver channels. When they are configured as GX
transceiver channels, the Standard PCS, Enhanced PCS, and PCIe Gen3 PCS are
available and they support data rates from 1.0 Gbps to 17.4 Gbps.
(6)
Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
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Figure 17.
GT Transceiver Channel in Full Duplex Mode Operating Between 17.4 Gbps
and 25.8 Gbps
Serializer
FPGA Fabric
Transmitter PCS
Transmitter PMA
(2)
KR FEC
Standard PCS
(3)
PCIe Gen3 PCS
(3)
Enhanced PCS
(1)
(2)
PCS Direct
Receiver PMA
CDR
Deserializer
Receiver PCS
(2)
KR FEC
Standard PCS
(3)
PCIe Gen3 PCS
(3)
Enhanced PCS
(2)
(1)
PCS Direct
Notes:
(1) The Enhanced PCS must be configured in Basic low latency mode to support data rate range from 17.4 Gbps to 25.8 Gbps.
(2) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(3) The Standard PCS and PCIe Gen3 PCS blocks are available when the GT channel is configured as a GX transceiver channel.
Table 7.
PCS Types and Data Rates Supported by GT Channel Configurations
GT Channel Configuration
GT
GX
Note:
PCS Type
Data Rates Supported
Standard PCS
Not available for GT configuration
Enhanced PCS
17.4 Gbps to 25.8 Gbps(7)
PCIe Gen3 PCS
Not available for GT configuration
Standard PCS
1.0 Gbps to 12 Gbps
Enhanced PCS
1.0 Gbps
PCIe Gen3 PCS
8 Gbps
(8)
to 17.4 Gbps
1.
The GT channels can also operate in PCS Direct configuration for data rates from
1.0 Gbps to 25.8 Gbps. The PCS Direct datapath that bypasses all PCS blocks is
the primary configuration used to support GT data rates from 17.4 Gbps to 25.8
Gbps. To operate GX and GT transceiver channels in PCS Direct designated data
rates, refer to the Intel Arria 10 Device Datasheet for more details on power
supply, speed grade, and transceiver configurations requirement.
2.
The minimum operational data rate is 1.0 Gbps for both the transmitter and
receiver. For transmitter data rates less than 1.0 Gbps, oversampling must be
applied at the transmitter. For receiver data rates less than 1.0 Gbps,
oversampling must be applied at the receiver.
3.
To operate GX and GT transceiver channels with the PCS at designated data rates,
refer to the Intel Arria 10 Device Datasheet for more details on power supply,
speed grade, and transceiver configurations requirement.
(7)
The Enhanced PCS must be configured in Basic low latency mode to support data rate range
from 17.4 Gbps to 25.8 Gbps.
(8)
Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
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Related Links
Intel Arria 10 Device Datasheet
1.2.3 Transceiver Phase-Locked Loops
Each transceiver channel in Arria 10 devices has direct access to three types of high
performance PLLs:
•
Advanced Transmit (ATX) PLL
•
Fractional PLL (fPLL)
•
Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB)
drive the transceiver channels.
Related Links
PLLs on page 337
For more information on transceiver PLLs in Arria 10 devices.
1.2.3.1 Advanced Transmit (ATX) PLL
An advanced transmit (ATX ) PLL is a high performance PLL. It supports both integer
frequency synthesis and coarse resolution fractional frequency synthesis. The ATX PLL
is the transceiver channel’s primary transmit PLL. It can operate over the full range of
supported data rates required for high data rate applications.
Related Links
•
ATX PLL on page 338
For more information on ATX PLL.
•
ATX PLL IP Core on page 342
For details on implementing the ATX PLL IP.
1.2.3.2 Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock
frequencies for 12.5 Gbps and lower data rate applications. fPLLs support both integer
frequency synthesis and fine resolution fractional frequency synthesis. Unlike the ATX
PLL, the fPLL can also be used to synthesize frequencies that can drive the core
through the FPGA fabric clock networks.
Related Links
•
fPLL on page 347
For more information on fPLL.
•
fPLL IP Core on page 350
For details on implementing the fPLL IP.
1.2.3.3 Channel PLL (CMU/CDR PLL)
A channel PLL resides locally within each transceiver channel. Its primary function is
clock and data recovery in the transceiver channel when the PLL is used in clock data
recovery (CDR) mode. The channel PLLs of channel 1 and 4 can be used as transmit
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PLLs when configured in clock multiplier unit (CMU) mode. The channel PLLs of
channel 0, 2, 3, and 5 cannot be configured in CMU mode and therefore cannot be
used as transmit PLLs.
Related Links
•
CMU PLL on page 356
For more information on CMU PLL.
•
CMU PLL IP Core on page 358
For information on implementing CMU PLL IP.
1.2.4 Clock Generation Block (CGB)
In Arria 10 devices, there are two types of clock generation blocks (CGBs):
•
Master CGB
•
Local CGB
Transceiver banks with six transceiver channels have two master CGBs. Master CGB1
is located at the top of the transceiver bank and master CGB0 is located at the bottom
of the transceiver bank. Transceiver banks with three channels have only one master
CGB. The master CGB divides and distributes bonded clocks to a bonded channel
group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN
clock network.
Each transceiver channel has a local CGB. The local CGB is used for dividing and
distributing non-bonded clocks to its own PCS and PMA blocks.
Related Links
Clock Generation Block on page 371
For more information on clock generation block.
1.3 Calibration
Arria 10 FPGAs contain a dedicated calibration engine to compensate for process
variations. The calibration engine calibrates the analog portion of the transceiver to
allow both the transmitter and receiver to operate at optimum performance.
The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the
CLKUSR clock must be free running and stable at the start of FPGA configuration to
successfully complete the calibration process and for optimal transceiver performance.
Note:
For more information about CLKUSR electrical characteristics, refer to Intel Arria 10
Device Datasheet. The CLKUSR can also be used as an FPGA configuration clock. For
information about configuration requirements for the CLKUSR pin, refer to the
Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices
chapter in the Arria 10 Core Fabric and General-Purpose I/O Handbook. For more
information about calibration, refer to the Calibration chapter. For more information
about CLKUSR pin requirements, refer to the Intel Arria 10 GX, GT, and SX Device
Family Pin Connection Guidelines.
Related Links
•
Intel Arria 10 Device Datasheet
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•
Configuration, Design Security, and Remote System Upgrades in Arria 10 Devices
•
Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines
Intel® Arria® 10 Transceiver PHY User Guide
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2 Implementing Protocols in Arria 10 Transceivers
2.1 Transceiver Design IP Blocks
Figure 18.
Arria 10 Transceiver Design Fundamental Building Blocks
Reset controller is used for resetting the
transceiver channels.
Transceiver PHY
Reset Controller (2)
Transceiver PLL IP core provides a clock source
to clock networks that drive the transceiver
channels. In Arria 10 devices, PLL IP Core
is separate from the transceiver PHY IP core.
Avalon master allows access to Avalon-MM
reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access
the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates
reconfiguration by performing reads and writes
through the Avalon-MM interface.
This block can be either a MAC IP core, or
a frame generator / analyzer or a
data generator / analyzer.
Transceiver
PLL IP Core
Master/Local
Clock
Generation
Block
Avalon-MM Master
MAC IP Core /
Data Generator /
Data Analyzer
Analog and Digital
Reset Bus
Non-Bonded and
Bonded Clocks
Avalon-MM
Interface
Reset Ports
Transceiver PHY IP Core
(1)
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver
channels functions for all communication
protocols.
Reconfiguration
Registers
Parallel Data Bus
Note:
(1) The Transceiver PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core, XAUI PHY IP Core, and so on)
(2) You can either design your own reset controller or use the Transceiver PHY Reset Controller.
Legend:
Intel generated IP block
User created IP block
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
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2.2 Transceiver Design Flow
Figure 19.
Transceiver Design Flow
Note:
The design examples on the Intel FPGA wiki page provide useful guidance for developing your own design.
However, the content on the Intel FPGA wiki page is not guaranteed by Intel.
Select PHY IP Core
Configure the PHY IP Core
Generate the Transceiver PHY Reset Controller
or create your own User-Coded Reset Controller
Generate PHY IP Core
Select PLL IP Core
Configure the PLL IP Core
Create reconfiguration logic
(if needed)
Generate PLL IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus Prime Settings File
Compile Design
Verify Design Functionality
Related Links
http://www.alterawiki.com
2.2.1 Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Arria 10 Transceiver Protocols and PHY IP Support section to decide which
PHY IP to select to implement your protocol.
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You can create your Quartus Prime project first, and then instantiate the various IPs
required for your design. In this case, specify the location to save your IP HDL files.
The current version of the PHY IP does not have the option to set the speed grade.
Specify the device family and speed grade when you create the Quartus Prime project.
You can also instantiate the PHY IP directly to evaluate the various features.
To instantiate a PHY IP:
1.
Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
At the top of the IP Catalog window, select Arria 10 device family
4. In IP Catalog, under Library ➤ Interface Protocols, select the appropriate PHY
IP and then click Add.
5. In the New IP Instance Dialog Box, provide the IP instance name.
6. Select Arria 10 device family.
7.
Select the appropriate device and click OK.
The PHY IP Parameter Editor window opens.
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Figure 20.
Arria 10 Transceiver PHY Types
Related Links
Arria 10 Transceiver Protocols and PHY IP Support on page 39
2.2.2 Configure the PHY IP Core
Configure the PHY IP core by selecting the valid parameters for your design. The valid
parameter settings are different for each protocol. Refer to the appropriate protocol's
section for selecting valid parameters for each protocol.
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
For information on Native PHY IP.
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•
Interlaken on page 92
•
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 110
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on
page 122
•
10GBASE-KR PHY IP Core on page 133
•
1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core on page 162
•
PCI Express (PIPE) on page 227
•
CPRI on page 278
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS on page 288
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 299
•
Design Considerations for Implementing Arria 10 GT Channels on page 318
2.2.3 Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
1.
Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3.
Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4.
In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5.
Click Generate.
The Quartus Prime software generates a <phy ip instance name> folder, <phy ip
instance name>_sim folder, <phy ip instance name>.qip file, <phy ip instance
name>.qsys file, and <phy ip instance name>.v file or <phy ip instance name>.vhd
file. This <phy ip instance name>.v file is the top level design file for the PHY IP and is
placed in the <phy ip instance name>/synth folder. The other folders contain lower
level design files used for simulation and compilation.
Related Links
IP Core File Locations on page 89
For more information about IP core file structure
2.2.4 Select the PLL IP Core
Arria 10 devices have three types of PLL IP cores:
•
Advanced Transmit (ATX) PLL IP core.
•
Fractional PLL (fPLL) IP core.
•
Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
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Select the appropriate PLL IP for your design. For additional details, refer to the PLLs
and Clock Networks chapter.
To instantiate a PLL IP:
1.
Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
At the top of the IP Catalog window, select Arria 10 device family
4. In IP Catalog, under Library ➤ Basic Functions ➤ Clocks, PLLs, and Resets
➤ PLL choose the PLL IP ( Arria 10 fPLL, Arria 10 Transceiver ATX PLL, or
Arria 10 Transceiver CMU PLL) you want to include in your design and then
click Add.
5. In the New IP Instance Dialog Box, provide the IP instance name.
6.
Select Arria 10 device family.
7.
Select the appropriate device and click OK.
The PLL IP GUI window opens.
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Figure 21.
Arria 10 Transceiver PLL Types
Related Links
PLLs on page 337
2.2.5 Configure the PLL IP Core
Understand the available PLLs, clock networks, and the supported clocking
configurations. Configure the PLL IP to achieve the adequate data rate for your design.
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Related Links
•
ATX PLL IP Core on page 342
•
fPLL IP Core on page 350
•
CMU PLL IP Core on page 358
•
Using PLLs and Clock Networks on page 386
2.2.6 Generate the PLL IP Core
After configuring the PLL IP core, complete the following steps to generate the PLL IP
core.
1.
Click the Generate HDL button in the Parameter Editor window. The
Generation dialog box opens.
2. In Synthesis options, under Create HDL design for synthesis select Verilog
or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware
description language you selected under Synthesis options.
4.
In Output Directory, select Clear output directories for selected generation
targets if you want to clear any previous IP generation files from the selected
output directory.
5.
Click Generate.
The Quartus ® Prime software generates a <pll ip core instance name> folder, <pll ip
core instance name>_sim folder, <pll ip core instance name>.qip file, <pll ip core
instance name>.qsys, and <pll ip core instance name>.v file or <pll ip core instance
name>.vhd file. The <pll ip core instance name>.v file is the top level design file for
the PLL IP core and is placed in the <pll ip core instance name>/ synth folder. The
other folders contain lower level design files used for simulation and compilation.
Related Links
IP Core File Locations on page 89
For more information about IP core file structure
2.2.7 Reset Controller
There are two methods to reset the transceivers in Arria 10 devices:
•
Use the Transceiver PHY Reset Controller.
•
Create your own reset controller that follows the recommended reset sequence.
Related Links
Resetting Transceiver Channels on page 402
2.2.8 Create Reconfiguration Logic
Dynamic reconfiguration is the ability to dynamically modify the transceiver channels
and PLL settings during device operation. To support dynamic reconfiguration, your
design must include an Avalon master that can access the dynamic reconfiguration
registers using the Avalon-MM interface.
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The Avalon-MM master enables PLL and channel reconfiguration. You can dynamically
adjust the PMA parameters, such as differential output voltage swing (Vod), and preemphasis settings. This adjustment can be done by writing to the Avalon-MM
reconfiguration registers through the user generated Avalon-MM master.
For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface
and Dynamic Reconfiguration chapter.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
2.2.9 Connect the PHY IP to the PLL IP Core and Reset Controller
Connect the PHY IP, PLL IP core, and the reset controller. Write the top level module to
connect all the IP blocks.
All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy
instance name>.vhd, and in the <phy_instance_name>_bb.v file.
For more information about description of the ports, refer to the ports tables in the
PLLs, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels
chapters.
Related Links
•
Enhanced PCS Ports on page 74
•
Standard PCS Ports on page 84
•
Resetting Transceiver Channels on page 402
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
PLLs and Clock Networks on page 335
2.2.10 Connect Datapath
Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core
or to a data generator / analyzer or a frame generator / analyzer.
2.2.11 Make Analog Parameter Settings
Make analog parameter settings to I/O pins using the Assignment Editor or updating
the Quartus Prime Settings File.
After verifying your design functionality, make pin assignments and PMA analog
parameter settings for the transceiver pins.
1.
Assign FPGA pins to all the transceiver and reference clock I/O pins. For more
details, refer to the Arria 10 Pin Connection Guidelines.
2.
Set the analog parameters to the transmitter, receiver, and reference clock pins
using the Assignment Editor.
All of the pin assignments and analog parameters set using the Pin Planner and
the Assignment Editor are saved in the <top_level_project_name>.qsf file. You
can also directly modify the Quartus Settings File (.qsf) to set PMA analog
parameters.
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Related Links
•
Analog Parameter Settings on page 563
•
Arria 10 Pin Connection Guidelines
2.2.12 Compile the Design
To compile the transceiver design, add the <phy_instancename>.qip files for all the IP
blocks generated using the IP Catalog to the Quartus Prime project library. You can
alternatively add the .qsys and .qip variants of the IP cores.
Note:
If you add both the .qsys and the .qip file into the Quartus Prime project, the
software generates an error.
Related Links
Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design
For more information about compilation details.
2.2.13 Verify Design Functionality
Simulate your design to verify the functionality of your design. For more details, refer
to Simulating the Native Transceiver PHY IP Core section.
Related Links
•
Simulating the Transceiver Native PHY IP Core on page 324
•
Quartus Prime Handbook - Volume 3: Verification
Information about design simulation and verification.
2.3 Arria 10 Transceiver Protocols and PHY IP Support
Table 8.
Arria 10 Transceiver Protocols and PHY IP Support
Protocol Preset
(10)
Protocol
Transceiver PHY IP
Core
PCS Support
Transceiver
Configuration Rule(9)
PCIe Gen3 x1, x2, x4,
x8
Native PHY IP core
(PIPE)/Hard IP for PCI
Express (11)
Standard and Gen3
Gen3 PIPE
PCIe PIPE Gen3 x1
PCIe PIPE Gen3 x8
PCIe Gen2 x1, x2, x4,
x8
Native PHY IP (PIPE)
core/Hard IP for PCI
Express (11)
Standard
Gen2 PIPE
PCIe PIPE Gen2 x1
PCIe PIPE Gen2 x8
PCIe Gen1 x1, x2, x4,
x8
Native PHY IP (PIPE)
core/Hard IP for PCI
Express (11)
Standard
Gen1 PIPE
User created
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(11)
Hard IP for PCI Express is also available as a separate IP core.
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Protocol Preset
(10)
Protocol
Transceiver PHY IP
Core
PCS Support
Transceiver
Configuration Rule(9)
1000BASE-X Gigabit
Ethernet
Native PHY IP core
Standard
GbE
GIGE - 1.25 Gbps
1000BASE-X Gigabit
Ethernet with 1588
Native PHY IP core
Standard
GbE 1588
GIGE - 1.25 Gbps
1588
10GBASE-R
Native PHY IP core
Enhanced
10GBASE-R
10GBASE-R Low
Latency
10GBASE-R 1588
Native PHY IP core
Enhanced
10GBASE-R 1588
10GBASE-R 1588
10GBASE-R with KR
FEC
Native PHY IP core
Enhanced
10GBASE-R w/KR FEC
10GBASE-R w/KR FEC
10GBASE-KR and
1000BASE-X
1G/10GbE and
10GBASE-KR PHY
IP(12)
Standard and
Enhanced
Not applicable
BackPlane_wo_1588
LineSide (optical)
LineSide(optical)_158
8
40GBASE-R
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
Low Latency Enhanced
PCS (13)
40GBASE-R with FEC/
40GBASE-KR4 (14)
Native PHY IP core
Enhanced
Basic w/KR FEC
User created
100GBASE-R via
CAUI-4/CPPI-4/BP and
CEI-25G
Native PHY IP core
Enhanced and PCS
Direct
Basic (Enhanced
PCS) / PCS Direct
Low Latency GT(15)
100GBASE-R via CAUI
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
Low Latency Enhanced
PCS (16)
100GBASE-R via CAUI
with FEC
Native PHY IP core
Enhanced
Basic w/KR FEC
User created
XAUI
XAUI PHY IP core
Soft PCS
Not applicable
Not applicable
SPAUI
Native PHY IP core
Standard and
Enhanced
Basic/Custom
(Standard PCS)
User created
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(12)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training,
auto speed negotiation, and sequencer functions.
(13)
To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of
data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(14)
Link training, auto speed negotiation and sequencer functions are not included in the Native
PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP.
(15)
Low Latency GT protocol preset requires some modification to implement CAUI-4/CPPI-4/BP-4
and CEI-25G.
(16)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the
number of data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
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Protocol
Transceiver PHY IP
Core
PCS Support
Transceiver
Configuration Rule(9)
Protocol Preset
(10)
Basic (Enhanced PCS)
DDR XAUI
Native PHY IP core
Standard and
Enhanced
Basic/Custom
(Standard PCS)
Basic (Enhanced PCS)
User created
Interlaken (CEI-6G/
11G) (17)
Native PHY IP core
Enhanced
Interlaken
Interlaken
10x12.5Gbps
Interlaken
6x10.3Gbps
Interlaken
1x6.25Gbps
OTU-4 (100G) via
OTL4.10/OIF SFI-S
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
SFI-S 64:64 4x11.3
Gbps(18)
OTU-3 (40G) via
OTL3.4/OIF SFI-5.2/
SFI-5.1
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
OTU-2 (10G) via SFP
+/SFF-8431/CEI-11G
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
OTU-2 (10G) via OIF
SFI-5.1s
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
OTU-1 (2.7G)
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.2/STL256.4
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SONET/SDH STS-768/
STM-256 (40G) via
OIF SFI-5.1
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SONET/SDH STS-192/
STM-64 (10G) via SFP
+/SFF-8431/CEI-11G
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SONET/SDH STS-192/
STM-64 (10G) via OIF
SFI-5.1s/SxI-5/
SFI-4.2
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SONET STS-96 (5G)
via OIF SFI-5.1s
Native PHY IP core
Enhanced
Basic/Custom
(Standard PCS)
SONET/SDH OC-96
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(17)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in
the design example.
(18)
To implement OTU-4 (100G) via OTL4.10/OIF SFI-S using SFI-S 64:64 4x11.3Gbps preset,
change the number of data channels to 10 for OTL4.10 or user desired number of channels
and datarate implemented for SFI-S.
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Transceiver PHY IP
Core
PCS Support
Transceiver
Configuration Rule(9)
SONET/SDH STS-48/
STM-16 (2.5G) via
SFP/TFI-5.1
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
SONET/SDH OC-48
SONET/SDH STS-12/
STM-4 (0.622G) via
SFP/TFI-5.1
Native PHY IP core(19)
Standard
Basic/Custom
(Standard PCS)
SONET/SDH OC-12
Intel QPI 1.1/2.0
Native PHY IP core
PCS Direct
PCS Direct
User created
SD-SDI/HD-SDI/3GSDI
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
3G/HD SDI NTSC
3G/HD SDI PAL
Vx1
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
1.25G/ 2.5G
10G GPON/EPON
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
2.5G/1.25G GPON/
EPON
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
16G/10G Fibre
Channel
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
8G/4G/2G/1G Fibre
Channel
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
EDR Infiniband x1, x4
Native PHY IP core
Enhanced (low latency
mode)
PCS Direct
Basic (Enhanced PCS)
PCS Direct
User created
FDR/FDR-10 Infiniband
x1, x4, x12
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SDR/DDR/QDR
Infiniband x1, x4, x12
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
CPRI v6.1 12.16512/
CPRI v6.0 10.1376 Gbps
Native PHY IP core
Enhanced
10GBASE-R 1588
10GBASE-R
User created
CPRI 4.2/OBSAI RP3
v4.2
Native PHY IP core
Standard
CPRI (Auto) / CPRI
(Manual)
CPRI 9.8Gbps Auto
Mode
DisplayPort
(20)
Protocol Preset
(10)
Protocol
continued...
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(19)
The minimum operational data rate is 1.0 Gbps for both the transmitter and receiver. For
transmitter data rates less than 1.0 Gbps, oversampling must be applied at the transmitter.
For receiver data rates less than 1.0 Gbps, oversampling must be applied at the receiver.
(20)
To meet DisplayPort TX electrical full compliance to VESA DisplayPort Standard version 1.3 and
VESA DisplayPort PHY Compliance Specification version 1.2b , VCCT_GXB & VCCR_GXB needs
to be 1.03V or higher. Test Refer to AN745: Design Guidelines for DisplayPort and HDMI
Interfaces for further details.
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Protocol
Transceiver PHY IP
Core
PCS Support
Transceiver
Configuration Rule(9)
Protocol Preset
(10)
CPRI 9.8 Gbps Manual
Mode
SRIO 2.2/1.3
Native PHY IP core
Standard
Basic/Custom with
Rate Match(Standard
PCS)
Serial Rapid IO 1.25
Gbps
SAS 3.0
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
SATA 3.0/2.0/1.0 and
SAS 2.0/1.1/1.0
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
SAS Gen2/Gen1.1/
Gen1
SATA Gen3/Gen2/
Gen1
HiGig/HiGig+/HiGig2/
HiGig2+
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
JESD204A / JESD204B
Native PHY IP core
Standard and
Enhanced
Basic/Custom
(Standard PCS) Basic
(Enhanced PCS)(21)
User created
ASI
Native PHY IP core
Standard
Basic/Custom
(Standard PCS)
User created
SPI-5 (100G) / SPI-5
(50G)
Native PHY IP core
Enhanced
Basic (Enhanced PCS)
User created
Custom and other
protocols
Native PHY IP core
Standard and
Enhanced
PCS Direct
Basis/Custom
(Standard PCS)
Basic (Enhanced PCS)
Basic/Custom with
Rate Match (Standard
PCS)
PCS Direct
User created
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
AN745: Design Guidelines for DisplayPort and HDMI Interfaces
2.4 Using the Arria 10 Transceiver Native PHY IP Core
This section describes the use of the Intel-provided Arria 10 Transceiver Native PHY IP
core. This Native PHY IP core provides direct access to Arria 10 transceiver PHY
features.
Use the Native PHY IP core to configure the transceiver PHY for your protocol
implementation. To instantiate the IP, click Tools ➤ IP Catalog to select your IP core
variation. Use the Parameter Editor to specify the IP parameters and configure the
PHY IP for your protocol implementation. To quickly configure the PHY IP, select a
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(21)
For JESD204B, Enhanced PCS is used when the data rate is above 12.0 Gbps
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preset that matches your protocol configuration as a starting point. Presets are PHY IP
configuration settings for various protocols that are stored in the IP Parameter
Editor. Presets are explained in detail in the Presets section below.
You can also configure the PHY IP by selecting an appropriate Transceiver
Configuration Rule. The transceiver configuration rules check the valid combinations
of the PCS and PMA blocks in the transceiver PHY layer, and report errors or warnings
for any invalid settings.
Use the Native PHY IP core to instantiate the following PCS options:
•
Standard PCS
•
Enhanced PCS
•
PCIe Gen3 PCS
•
PCS Direct
Based on the Transceiver Configuration Rule that you select, the PHY IP core selects
the appropriate PCS. The PHY IP core allows you to select all the PCS blocks if you
intend to dynamically reconfigure from one PCS to another. Refer to General and
Datapath Parameters section for more details on how to enable PCS blocks for
dynamic reconfiguration. Refer to the How to Place Channels for PIPE Configuration
section or the PCIE solutions guides on restrictions on placement of transceiver
channels next to active banks with PCI Express interfaces that are Gen3 capable..
After you configure the PHY IP core in the Parameter Editor, click Generate HDL to
generate the IP instance. The top level file generated with the IP instance includes all
the available ports for your configuration. Use these ports to connect the PHY IP core
to the PLL IP core, the reset controller IP core, and to other IP cores in your design.
Figure 22.
Native PHY IP Core Ports and Functional Blocks
Enhanced PCS
Transmit Parallel Data
Receive Parallel Data
Reset Signals
Transmit
PMA
Transmit Serial Data
Receive
PMA
Receive Serial Data
Standard PCS
PCIe Gen3 PCS
PCS-Direct
Reconfiguration Interface
Transmit and Receive Clocks
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44
Reconfiguration
Registers
Nios II
Calibration
Calibration Signals
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Figure 23.
Native PHY IP Core Parameter Editor
General
Options
Documentation
Common
PMA Options
Datapath
Options
Presets
PMA/PCS, Dynamic Reconfiguration, Optional Analog PMA Settings, and General Options
Note:
Although the Quartus Prime software provides legality checks, the supported FPGA
fabric to PCS interface widths and the supported data rates are pending
characterization.
Related Links
•
Configure the PHY IP Core on page 33
•
Interlaken on page 92
•
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 110
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on
page 122
•
10GBASE-KR PHY IP Core on page 133
•
1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core on page 162
•
PCI Express (PIPE) on page 227
•
CPRI on page 278
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS on page 288
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 299
•
Design Considerations for Implementing Arria 10 GT Channels on page 318
•
PMA Parameters on page 49
•
Presets on page 46
•
General and Datapath Parameters on page 46
•
Enhanced PCS Ports on page 74
•
Standard PCS Ports on page 84
•
PMA Ports on page 70
•
How to Place Channels for Pipe Configuration on page 266
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2.4.1 Presets
You can select preset settings for the Native PHY IP core defined for each protocol. Use
presets as a starting point to specify parameters for your specific protocol or
application.
To apply a preset to the Native PHY IP core, double-click on the preset name. When
you apply a preset, all relevant options and parameters are set in the current instance
of the Native PHY IP core. For example, selecting the Interlaken preset enables all
parameters and ports that the Interlaken protocol requires.
Selecting a preset does not prevent you from changing any parameter to meet the
requirements of your design. Any changes that you make are validated by the design
rules for the transceiver configuration rules you specified, not the selected preset.
Note:
Selecting a preset clears any prior selections user has made so far.
2.4.2 General and Datapath Parameters
You can customize your instance of the Native PHY IP core by specifying parameter
values. In the Parameter Editor, the parameters are organized in the following
sections for each functional block and feature:
Table 9.
•
General, Common PMA Options, and Datapath Options
•
TX PMA
•
RX PMA
•
Standard PCS
•
Enhanced PCS
•
PCS Direct Datapath
•
Dynamic Reconfiguration
•
Analog PMA Settings (Optional)
•
Generation Options
General, Common PMA Options, and Datapath Options
Parameter
Message level for rule
violations
Value
error
warning
Description
Specifies the messaging level for parameter rule violations.
Selecting error causes all rule violations to prevent IP generation.
Selecting warning displays all rule violations as warnings in the
message window and allows IP generation despite the violations.
(22)
VCCR_GXB and
VCCT_GXB supply voltage
0_9V, 1_0V, 1_1V
for the Transceiver
Transceiver Link Type
Selects the VCCR_GXB and VCCT_GXB supply voltage for the
Transceiver.
Note: This option is only used for GUI rule validation. Use
Quartus Prime Setting File (.qsf) assignments to set this
parameter in your static design.
sr, lr
Selects the type of transceiver link. sr-Short Reach (Chip-to-chip
communication), lr-Long Reach (Backplane communication).
continued...
(22)
Although you can generate the PHY with warnings, you can not compile the PHY in Quartus
Prime.
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Parameter
Value
Description
Note: This option is only used for GUI rule validation. Use
Quartus Prime Setting File (.qsf) assignments to set this
parameter in your static design.
Transceiver
configuration rules
User Selection
Specifies the valid configuration rules for the transceiver.
This parameter specifies the configuration rule against which the
Parameter Editor checks your PMA and PCS parameter settings
for specific protocols. Depending on the transceiver configuration
rule selected, the Parameter Editor validates the parameters and
options selected by you and generates error messages or warnings
for all invalid settings.
To determine the transceiver configuration rule to be selected for
your protocol, refer to Table 8 on page 39 Transceiver
Configuration Rule Parameters table for more details about each
transceiver configuration rule.
This parameter is used for rule checking and is not a preset. You
need to set all parameters for your protocol implementation.
PMA configuration
rules
Basic
SATA/SAS
QPI
GPON
Specifies the configuration rule for PMA.
Select Basic for all other protocol modes except for SATA, GPON,
and QPI.
SATA (Serial ATA) can be used only if the Transceiver
configuration rule is set to Basic/Custom (Standard PCS).
GPON can be used only if the Transceiver configuration rule is
set to Basic (Enhanced PCS).
QPI can be used only if the Transceiver configuration rule is
set to PCS Direct.
Transceiver mode
TX/RX Duplex
TX Simplex
RX Simplex
Specifies the operational mode of the transceiver.
• TX/RX Duplex : Specifies a single channel that supports both
transmission and reception.
• TX Simplex : Specifies a single channel that supports only
transmission.
• RX Simplex : Specifies a single channel that supports only
reception.
The default is TX/RX Duplex.
Number of data
channels
1 – <n>
Specifies the number of transceiver channels to be implemented.
The maximum number of channels available, ( <n> ), depends on
the package you select.
The default value is 1.
Data rate
< valid Transceiver data
rate >
Specifies the data rate in megabits per second (Mbps).
continued...
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Parameter
Value
Description
Enable datapath and
interface
reconfiguration
On/Off
When you turn this option on, you can preconfigure and
dynamically switch between the Standard PCS, Enhanced PCS, and
PCS direct datapaths.
The default value is Off.
Enable simplified data
interface
On/Off
By default, all 128-bits are ports for the tx_parallel_data and
rx_parallel_data buses are exposed. You must understand the
mapping of data and control signals within the interface. Refer to
the Enhanced PCS TX and RX Control Ports section for details
about mapping of data and control signals.
When you turn on this option, the Native PHY IP core presents a
simplified data and control interface between the FPGA fabric and
transceiver. Only the sub-set of the 128-bits that are active for a
particular FPGA fabric width are ports.
The default value is Off.(23)
Provide separate
interface for each
channel
On/Off
When selected the Native PHY IP core presents separate data,
reset and clock interfaces for each channel rather than a wide bus.
Table 10.
Transceiver Configuration Rule Parameters
Transceiver Configuration Setting
Description
Basic/Custom (Standard PCS)
Enforces a standard set of rules within the Standard PCS. Select these rules to
implement custom protocols requiring blocks within the Standard PCS or
protocols not covered by the other configuration rules.
Basic/Custom w /Rate Match
(Standard PCS)
Enforces a standard set of rules including rules for the Rate Match FIFO within
the Standard PCS. Select these rules to implement custom protocols requiring
blocks within the Standard PCS or protocols not covered by the other
configuration rules.
CPRI (Auto)
Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Auto. In Auto mode, the word aligner is set to deterministic latency.
CPRI (Manual)
Enforces rules required by the CPRI protocol. The receiver word aligner mode is
set to Manual. In Manual mode, logic in the FPGA fabric controls the word
aligner.
GbE
Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588
Enforces rules for the 1 GbE protocol with support for Precision time protocol
(PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE
Enforces rules for a Gen1 PCIe
MAC and Data Link Layer.
Gen2 PIPE
Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a soft MAC
and Data Link Layer.
Gen3 PIPE
Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a soft MAC
and Data Link Layer.
Basic (Enhanced PCS)
Enforces a standard set of rules within the Enhanced PCS. Select these rules to
implement protocols requiring blocks within the Enhanced PCS or protocols not
covered by the other configuration rules.
Interlaken
Enforces rules required by the Interlaken protocol.
10GBASE-R
Enforces rules required by the 10GBASE-R protocol.
®
PIPE interface that you can connect to a soft
continued...
(23)
This option cannot be used, if you intend to dynamically reconfigure between PCS datapaths,
or reconfigure the interface of the transceiver.
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Transceiver Configuration Setting
Description
10GBASE-R 1588
Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
10GBASE-R w/KR FEC
Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
40GBASE-R w/KR FEC
Enforces rules required by the 40GBASE-R protocol with the KR FEC block
enabled.
Basic w/KR FEC
Enforces a standard set of rules required by the Enhanced PCS when you enable
the KR FEC block. Select this rule to implement custom protocols requiring
blocks within the Enhanced PCS or protocols not covered by the other
configuration rules.
PCS Direct
Enforces rules required by the PCS Direct mode. In this configuration the data
flows through the PCS channel, but all the internal PCS blocks are bypassed. If
required, the PCS functionality can be implemented in the FPGA fabric.
Related Links
•
Device Transceiver Layout on page 8
•
Enhanced PCS TX and RX Control Ports on page 81
2.4.3 PMA Parameters
You can specify values for the following types of PMA parameters:
TX PMA
•
TX Bonding Options
•
TX PLL Options
•
TX PMA Optional Ports
RX PMA
Table 11.
•
RX CDR Options
•
Equalization
•
RX PMA Optional Ports
TX Bonding Options
Parameter
TX channel bonding
mode
Value
Description
Not bonded
PMA only bonding
PMA and PCS bonding
Selects the bonding mode to be used for the channels specified.
Bonded channels use a single TX PLL to generate a clock that
drives multiple channels, reducing channel-to-channel skew. The
following options are available:
Not bonded: In a non-bonded configuration, only the high speed
serial clock is expected to be connected from the TX PLL to the
Native PHY IP core. The low speed parallel clock is generated by
the local clock generation block (CGB) present in the transceiver
channel. For non-bonded configurations, because the channels are
not related to each other and the feedback path is local to the PLL,
the skew between channels cannot be calculated.
PMA only bonding: In PMA bonding, the high speed serial clock
is routed from the transmitter PLL to the master CGB. The master
CGB generates the high speed and low parallel clocks and the local
CGB for each channel is bypassed. Refer to the Channel Bonding
section for more details.
PMA and PCS bonding : In a PMA and PCS bonded
configuration, the local CGB in each channel is bypassed and the
parallel clocks generated by the master CGB are used to clock the
continued...
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Parameter
Value
Description
network. The master CGB generates both the high and low speed
clocks. The master channel generates the PCS control signals and
distributes to other channels through a control plane block.
The default value is Not bonded.
Refer to Channel Bonding section in PLLs and Clock Networks
chapter for more details.
PCS TX channel
bonding master
Auto, 0 to <number of
channels> -1
Specifies the master PCS channel for PCS bonded configurations.
Each Native PHY IP core instance configured with bonding must
specify a bonding master. If you select Auto, the Native PHY IP
core automatically selects a recommended channel.
The default value is Auto. Refer to the PLLs and Clock Networks
chapter for more information about the TX channel bonding
master.
Actual PCS TX channel
bonding master
0 to <number of
channels> -1
This parameter is automatically populated based on your selection
for the PCS TX channel bonding master parameter. Indicates
the selected master PCS channel for PCS bonded configurations.
Table 12.
TX PLL Options
Parameter
Value
Description
TX local clock division
factor
1, 2, 4, 8
Specifies the value of the divider available in the transceiver
channels to divide the TX PLL output clock to generate the correct
frequencies for the parallel and serial clocks.
Number of TX PLL
clock inputs per
channel
1, 2, 3 , 4
Specifies the number of TX PLL clock inputs per channel. Use this
parameter when you plan to dynamically switch between TX PLL
clock sources. Up to four input sources are possible.
Initial TX PLL clock
input selection
0 to <number of TX
PLL clock inputs> -1
Specifies the initially selected TX PLL clock input. This parameter
is necessary when you plan to switch between multiple TX PLL
clock inputs.
Table 13.
TX PMA Optional Ports
Parameter
Value
Description
Enable
tx_pma_analog_reset_ack
port
On/Off
Enables the optional tx_pma_analog_reset_ack output port.
This port should not be used for register mode data transfers.
Enable tx_pma_clkout port
On/Off
Enables the optional tx_pma_clkout output clock. This is the low
speed parallel clock from the TX PMA. The source of this clock is
the serializer. It is driven by the PCS/PMA interface block. (24)
Enable tx_pma_div_clkout
port
On/Off
Enables the optional tx_pma_div_clkout output clock. This
clock is generated by the serializer. You can use this to drive core
logic, to drive the FPGA - transceivers interface.
If you select a tx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
select a tx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA high serial clock. This clock is
commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as 66:40
applications.
tx_pma_div_clkout division
factor
Disabled, 1, 2,
33, 40, 66
Selects the division factor for the tx_pma_div_clkout output
clock when enabled. (25)
continued...
(24)
This clock should not be used to clock the FPGA - transceivers interface. This clock may be
used as a reference clock to an external clock cleaner.
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Parameter
Value
Description
Enable
tx_pma_iqtxrx_clkout port
On/Off
Enables the optional tx_pma_iqtxrx_clkout output clock. This
clock can be used to cascade the TX PMA output clock to the input
of a PLL.
Enable tx_pma_elecidle
port
On/Off
Enables the tx_pma_elecidle port. When you assert this port,
the transmitter is forced into an electrical idle condition. This port
has no effect when the transceiver is configured for PCI Express.
Enable tx_pma_qpipullup
port (QPI)
On/Off
Enables the tx_pma_qpipullup control input port. Use this port
only for Quick Path Interconnect (QPI) applications.
Enable tx_pma_qpipulldn
port (QPI)
On/Off
Enables the tx_pma_qpipulldn control input port. Use this port
only for QPI applications.
Enable tx_pma_txdetectrx
port (QPI)
On/Off
Enables the tx_pma_txdetectrx control input port. The receiver
detect block in the TX PMA detects the presence of a receiver at
the other end of the channel. After receiving a
tx_pma_txdetectrx request the receiver detect block initiates
the detection process. Use this port only in QPI applications.
Enable tx_pma_rxfound
port (QPI)
On/Off
Enables the tx_pma_rxfound status output port. The receiver
detect block in TX PMA detects the presence of a receiver at the
other end by using the tx_pma_txdetectrx input. The
tx_pma_rxfound port reports the status of the detection
operation. Use this port only in QPI applications.
Enable rx_seriallpbken port
On/Off
Enables the optional rx_seriallpbken control input port. The
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Table 14.
RX CDR Options
Parameter
Value
Description
Number of CDR
reference clocks
1-5
Specifies the number of CDR reference clocks. Up to 5 sources are
possible.
The default value is 1.
Use this feature when you want to dynamically re-configure CDR
reference clock source.
Selected CDR
reference clock
0 to <number of CDR
reference clocks> -1
Specifies the initial CDR reference clock. This parameter
determines the available CDR references used.
The default value is 0.
Selected CDR
reference clock
frequency
< data rate dependent >
Specifies the CDR reference clock frequency. This value depends
on the data rate specified.
PPM detector
threshold
100
300
500
1000
Specifies the PPM threshold for the CDR. If the PPM between the
incoming serial data and the CDR reference clock, exceeds this
threshold value, the CDR loses lock.
The default value is 1000.
Table 15.
Equalization
Parameters
CTLE adaptation mode
Value
Manual
Description
Specifies the Continuous Time Linear Equalization (CTLE)
operation mode.
continued...
(25)
The default value is Disabled.
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Parameters
Value
Description
For manual mode, set the CTLE options through the Assignment
Editor, or modify the Quartus Settings File (.qsf), or write to the
reconfiguration registers using the Avalon Memory-Mapped
(Avalon-MM) interface.
Refer to Continuous Time Linear Equalization (CTLE) on page 436
section in Arria 10 Transceiver Architecture chapter for more
details about CTLE architecture. Refer to How to Enable CTLE and
DFE on page 440 for more details on supported adaptation
modes.
DFE adaptation mode
Adaptation enabled
Manual, Disabled
Specifies the operating mode for the Decision Feedback
Equalization (DFE) block in the RX PMA.
The default value is Disabled.
For manual mode, you can set the DFE options through the
Assignment Editor, or by modifying the Quartus Settings File
(.qsf), or write to the reconfiguration registers using the AvalonMM interface.
Refer to the Decision Feedback Equalization (DFE) on page 438
section in the Arria 10 Transceiver PHY Architecture chapter for
more details about DFE. Refer to How to Enable CTLE and DFE on
page 440 for more details on supported adaptation modes.
Number of fixed DFE
taps
3, 7 , 11
Specifies the number of fixed DFE taps. Select the number of
taps depending on the loss in your transmission channel and the
type of equalization required.
Table 16.
RX PMA Optional Ports
Parameters
Value
Description
Enable
rx_analog_reset_ack
port
On/Off
Enables the optional rx_analog_reset_ack output. This port
should not be used for register mode data transfers.
Enable rx_pma_clkout
port
On/Off
Enables the optional rx_pma_clkout output clock. This port is
the recovered parallel clock from the RX clock data recovery
(CDR). (26)
Enable
rx_pma_div_clkout
port
On/Off
Enables the optional rx_pma_div_clkout output clock. The
deserializer generates this clock. Use this to drive core logic, to
drive the RX PCS-to-FPGA fabric interface, or both.
If you select a rx_pma_div_clkout division factor of 1 or 2, this
clock output is derived from the PMA parallel clock. If you select a
rx_pma_div_clkout division factor of 33, 40, or 66, this clock is
derived from the PMA serial clock. This clock is commonly used
when the interface to the RX FIFO runs at a different rate than the
PMA parallel clock frequency, such as 66:40 applications.
rx_pma_div_clkout
division factor
Disabled, 1, 2, 33, 40,
66
Selects the division factor for the rx_pma_div_clkout output
clock when enabled. (27)
Enable
rx_pma_iqtxrx_clkout
port
On/Off
Enables the optional rx_pma_iqtxrx_clkout output clock. This
clock can be used to cascade the RX PMA output clock to the input
of a PLL.
Enable rx_pma_clkslip
port
On/Off
Enables the optional rx_pma_clkslip control input port. A rising
edge on this signal causes the RX serializer to slip the serial data
by one clock cycle, or 2 unit intervals (UI).
continued...
(26)
This clock should not be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
(27)
The default value is Disabled.
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Parameters
Value
Description
Enable
rx_pma_qpipulldn port
(QPI)
On/Off
Enables the rx_pma_qpipulldn control input port. Use this port
only for QPI applications.
Enable
rx_is_lockedtodata
port
On/Off
Enables the optional rx_is_lockedtodata status output port.
This signal indicates that the RX CDR is currently in lock to data
mode or is attempting to lock to the incoming data stream. This is
an asynchronous output signal.
Enable
rx_is_lockedtoref port
On/Off
Enables the optional rx_is_lockedtoref status output port.
This signal indicates that the RX CDR is currently locked to the
CDR reference clock. This is an asynchronous output signal.
Enable
rx_set_lockedtodata
port and
rx_set_lockedtoref
ports
On/Off
Enables the optional rx_set_lockedtodata and
rx_set_lockedtoref control input ports. You can use these
Enable rx_seriallpbken
port
On/Off
Enables the optional rx_seriallpbken control input port. The
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Enable PRBS (Pseudo
Random Bit Sequence)
verifier control and
status port
On/Off
Enables the optional rx_prbs_err, rx_prbs_clr, and
rx_prbs_done control ports. These ports control and collect
control ports to manually control the lock mode of the RX CDR.
These are asynchronous input signals.
status from the internal PRBS verifier.
Related Links
•
PLLs and Clock Networks on page 335
•
Channel Bonding on page 377
•
Continuous Time Linear Equalization (CTLE) on page 436
•
Decision Feedback Equalization (DFE) on page 438
•
Analog Parameter Settings on page 563
•
How to Enable CTLE and DFE on page 440
2.4.4 Enhanced PCS Parameters
This section defines parameters available in the Native PHY IP core GUI to customize
the individual blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the
Transceiver Configuration Rule , if the specified settings violate the protocol
standard, the Native PHY IP core Parameter Editor prints error or warning
messages.
Note:
For detailed descriptions about the optional ports that you can enable or disable, refer
to the Enhanced PCS Ports section.
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Table 17.
Enhanced PCS Parameters
Parameter
Range
Description
Enhanced PCS / PMA
interface width
32, 40, 64
Specifies the interface width between the Enhanced PCS and the
PMA.
FPGA fabric /Enhanced
PCS interface width
32, 40, , 64, 66, 67
Specifies the interface width between the Enhanced PCS and the
FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits from the
TX and RX parallel data. The block synchronizer determines the
block boundary of the 66-bit word, with lower 2 bits from the
control bus.
The 67-bit FPGA fabric to PCS interface width uses the 64-bits from
the TX and RX parallel data. The block synchronizer determines the
block boundary of the 67-bit word with lower 3 bits from the control
bus.
Enable Enhanced PCS
low latency mode
On/Off
Enables the low latency path for the Enhanced PCS. When you turn
on this option, the individual functional blocks within the Enhanced
PCS are bypassed to provide the lowest latency path from the PMA
through the Enhanced PCS. When enabled, this mode is applicable
for GX devices. Intel recommends not enabling it for GT devices.
Enable RX/TX FIFO
double width mode
On/Off
Enables the double width mode for the RX and TX FIFOs. You can
use double width mode to run the FPGA fabric at half the frequency
of the PCS.
Table 18.
Enhanced PCS TX FIFO Parameters
Parameter
TX FIFO Mode
Range
Description
Phase-Compensation
Register
Interlaken
Basic
Fast Register
Specifies one of the following modes:
• Phase Compensation: The TX FIFO compensates for the clock
phase difference between the read clock rx_clkout and the
write clocks tx_coreclkin or tx_clkout. You can tie
tx_enh_data_valid to 1'b1.
•
Register: The TX FIFO is bypassed. The tx_parallel_data,
tx_control and tx_enh_data_valid are registered at the
FIFO output. Assert tx_enh_data_valid port 1'b1 at all
times. The user must connect the write clock tx_coreclkin to
the read clock tx_clkout.
•
Interlaken: The TX FIFO acts as an elastic buffer. In this mode,
there are additional signals to control the data flow into the
FIFO. Therefore, the FIFO write clock frequency does not have
to be the same as the read clock frequency. You can control
writes to the FIFO with tx_enh_data_valid. By monitoring
the FIFO flags, you can avoid the FIFO full and empty
conditions. The Interlaken frame generator controls reads.
Basic: The TX FIFO acts as an elastic buffer. This mode allows
driving write and read side of FIFO with different clock
frequencies. tx_coreclkin or rx_coreclkin must have a
minimum frequency of the lane data rate divided by 66. The
frequency range for tx_coreclkin or rx_coreclkin is (data
rate/32) - (data rate/66). For best results, Intel recommends
that tx_coreclkin or rx_coreclkin = (data rate/32).
Monitor FIFO flag to control write and read operations. For
additional details refer to Enhanced PCS FIFO Operation on page
296 section
Fast Register: The TX FIFO allows a higher maximum
frequency (fMAX) between the FPGA fabric and the TX PCS at the
expense of higher latency.
•
•
TX FIFO partially full
threshold
10, 11, 12, 13
Specifies the partially full threshold for the Enhanced PCS TX FIFO.
Enter the value at which you want the TX FIFO to flag a partially
full status.
continued...
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Parameter
Range
Description
TX FIFO partially
empty threshold
2, 3, 4, 5
Specifies the partially empty threshold for the Enhanced PCS TX
FIFO. Enter the value at which you want the TX FIFO to flag a
partially empty status.
Enable tx_enh_fifo_full
port
On / Off
Enables the tx_enh_fifo_full port. This signal indicates when the
TX FIFO is full. This signal is synchronous to tx_coreclkin.
Enable
tx_enh_fifo_pfull port
On / Off
Enables the tx_enh_fifo_pfull port. This signal indicates when
the TX FIFO reaches the specified partially full threshold. This
signal is synchronous to tx_coreclkin.
Enable
tx_enh_fifo_empty
port
On / Off
Enables the tx_enh_fifo_empty port. This signal indicates when
the TX FIFO is empty. This signal is synchronous to
tx_coreclkin.
Enable
tx_enh_fifo_pempty
port
On / Off
Enables the tx_enh_fifo_pempty port. This signal indicates when
the TX FIFO reaches the specified partially empty threshold. This
signal is synchronous to tx_coreclkin.
Table 19.
Enhanced PCS RX FIFO Parameters
Parameter
RX FIFO Mode
Range
Phase-Compensation
Register
Interlaken
10GBASE-R
Basic
Description
Specifies one of the following modes for Enhanced PCS RX FIFO:
• Phase Compensation: This mode compensates for the clock
phase difference between the read clocks rx_coreclkin or
tx_clkout and the write clock rx_clkout.
•
Register : The RX FIFO is bypassed. The
rx_parallel_data, rx_control, and
rx_enh_data_valid are registered at the FIFO output. The
FIFO's read clock rx_coreclkin and write clock rx_clkout
•
•
•
are tied together.
Interlaken: Select this mode for the Interlaken protocol. To
implement the deskew process, you must implement an FSM
that controls the FIFO operation based on FIFO flags. In this
mode the FIFO acts as an elastic buffer.
10GBASE-R: In this mode, data passes through the FIFO
after block lock is achieved. OS (Ordered Sets) are deleted and
Idles are inserted to compensate for the clock difference
between the RX PMA clock and the fabric clock of +/- 100 ppm
for a maximum packet length of 64000 bytes.
Basic: In this mode, the RX FIFO acts as an elastic buffer. This
mode allows driving write and read side of FIFO with different
clock frequencies. tx_coreclkin or rx_coreclkin must
have a minimum frequency of the lane data rate divided by
66. The frequency range for tx_coreclkin or
rx_coreclkin is (data rate/32) - (data rate/66). The
gearbox data valid flag controls the FIFO read enable. You can
monitor the rx_enh_fifo_pfull and rx_enh_fifo_empty
flags to determine whether or not to read from the FIFO. For
additional details refer to Enhanced PCS FIFO Operation on
page 296.
Note: The flags are for Interlaken and Basic modes only. They
should be ignored in all other cases.
RX FIFO partially full
threshold
18-29
Specifies the partially full threshold for the Enhanced PCS RX
FIFO. The default value is 23.
RX FIFO partially
empty threshold
2-10
Specifies the partially empty threshold for the Enhanced PCS RX
FIFO. The default value is 2.
Enable RX FIFO
alignment word
deletion (Interlaken)
On / Off
When you turn on this option, all alignment words (sync words),
including the first sync word, are removed after frame
synchronization is achieved. If you enable this option, you must
also enable control word deletion.
continued...
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Parameter
Range
Description
Enable RX FIFO control
word deletion
(Interlaken)
On / Off
When you turn on this option, Interlaken control word removal is
enabled. When the Enhanced PCS RX FIFO is configured in
Interlaken mode, enabling this option, removes all control words
after frame synchronization is achieved. Enabling this option
requires that you also enable alignment word deletion.
Enable
rx_enh_data_valid port
On / Off
Enables the rx_enh_data_valid port. This signal indicates when
RX data from RX FIFO is valid. This signal is synchronous to
rx_coreclkin.
Enable rx_enh_fifo_full
port
On / Off
Enables the rx_enh_fifo_full port. This signal indicates when
the RX FIFO is full. This is an asynchronous signal.
Enable
rx_enh_fifo_pfull port
On / Off
Enables the rx_enh_fifo_pfull port. This signal indicates when
the RX FIFO has reached the specified partially full threshold. This
is an asynchronous signal.
Enable
rx_enh_fifo_empty
port
On / Off
Enables the rx_enh_fifo_empty port. This signal indicates when
the RX FIFO is empty. This signal is synchronous to
rx_coreclkin.
Enable
rx_enh_fifo_pempty
port
On / Off
Enables the rx_enh_fifo_pempty port. This signal indicates
when the RX FIFO has reached the specified partially empty
threshold. This signal is synchronous to rx_coreclkin.
Enable rx_enh_fifo_del
port (10GBASE-R)
On / Off
Enables the optional rx_enh_fifo_del status output port. This
signal indicates when a word has been deleted from the rate
match FIFO. This signal is only used for 10GBASE-R transceiver
configuration rule. This is an asynchronous signal.
Enable
rx_enh_fifo_insert port
(10GBASE-R)
On / Off
Enables the rx_enh_fifo_insert port. This signal indicates when
a word has been inserted into the rate match FIFO. This signal is
only used for 10GBASE-R transceiver configuration rule. This
signal is synchronous to rx_coreclkin.
Enable
rx_enh_fifo_rd_en port
On / Off
Enables the rx_enh_fifo_rd_en input port. This signal is
enabled to read a word from the RX FIFO. This signal is
synchronous to rx_coreclkin.
Enable
rx_enh_fifo_align_val
port (Interlaken)
On / Off
Enables the rx_enh_fifo_align_val status output port. Only
used for Interlaken transceiver configuration rule. This signal is
synchronous to rx_clkout.
Enable
rx_enh_fifo_align_clr
port (Interlaken)
On / Off
Enables the rx_enh_fifo_align_clr input port. Only used for
Interlaken. This signal is synchronous to rx_clkout.
Table 20.
Interlaken Frame Generator Parameters
Parameter
Range
Description
Enable Interlaken
frame generator
On / Off
Enables the frame generator block of the Enhanced PCS.
Frame generator
metaframe length
5-8192
Specifies the metaframe length of the frame generator. This
metaframe length includes 4 framing control words created by the
frame generator.
Enable Frame
Generator Burst
Control
On / Off
Enables frame generator burst. This determines whether the
frame generator reads data from the TX FIFO based on the input
of port tx_enh_frame_burst_en.
continued...
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Parameter
Range
Description
Enable tx_enh_frame
port
On / Off
Enables the tx_enh_frame status output port. When the
Interlaken frame generator is enabled, this signal indicates the
beginning of a new metaframe. This is an asynchronous signal.
Enable
tx_enh_frame_diag_st
atus port
On / Off
Enables the tx_enh_frame_diag_status 2-bit input port.
When the Interlaken frame generator is enabled, the value of this
signal contains the status message from the framing layer
diagnostic word. This signal is synchronous to tx_clkout.
Enable
tx_enh_frame_burst_e
n port
On / Off
Enables the tx_enh_frame_burst_en input port. When burst
control is enabled for the Interlaken frame generator, this signal is
asserted to control the frame generator data reads from the TX
FIFO. This signal is synchronous to tx_clkout.
Table 21.
Interlaken Frame Synchronizer Parameters
Parameter
Range
Description
Enable Interlaken
frame synchronizer
On / Off
When you turn on this option, the Enhanced PCS frame
synchronizer is enabled.
Frame synchronizer
metaframe length
5-8192
Specifies the metaframe length of the frame synchronizer.
Enable rx_enh_frame
port
On / Off
Enables the rx_enh_frame status output port. When the
Interlaken frame synchronizer is enabled, this signal indicates the
beginning of a new metaframe. This is an asynchronous signal.
Enable
rx_enh_frame_lock
port
On / Off
Enables the rx_enh_frame_lock output port. When the
Interlaken frame synchronizer is enabled, this signal is asserted to
indicate that the frame synchronizer has achieved metaframe
delineation. This is an asynchronous output signal.
Enable
rx_enh_frame_diag_st
atus port
On / Off
Enables therx_enh_frame_diag_status output port. When the
Interlaken frame synchronizer is enabled, this signal contains the
value of the framing layer diagnostic word (bits [33:32]). This is a
2 bit per lane output signal. It is latched when a valid diagnostic
word is received. This is an asynchronous signal.
Table 22.
Interlaken CRC32 Generator and Checker Parameters
Parameter
Range
Description
Enable Interlaken TX
CRC-32 Generator
On / Off
When you turn on this option, the TX Enhanced PCS datapath
enables the CRC32 generator function. CRC32 can be used as a
diagnostic tool. The CRC contains the entire metaframe including
the diagnostic word.
Enable Interlaken TX
CRC-32 generator
error insertion
On / Off
When you turn on this option, the error insertion of the interlaken
CRC-32 generator is enabled. Error insertion is cycle-accurate.
When this feature is enabled, the assertion of tx_control[8] or
tx_err_ins signal causes the CRC calculation during that word is
incorrectly inverted, and thus, the CRC created for that metaframe
is incorrect.
Enable Interlaken RX
CRC-32 checker
On / Off
Enables the CRC-32 checker function.
Enable
rx_enh_crc32_err port
On / Off
When you turn on this option, the Enhanced PCS enables the
rx_enh_crc32_err port. This signal is asserted to indicate that
the CRC checker has found an error in the current metaframe.
This is an asynchronous signal.
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Table 23.
10GBASE-R BER Checker Parameters
Parameter
Range
Description
Enable
rx_enh_highber port
(10GBASE-R)
On / Off
Enables the rx_enh_highber port. For 10GBASE-R transceiver
configuration rule, this signal is asserted to indicate a bit error
rate higher than 10 -4 . Per the 10GBASE-R specification, this
occurs when there are at least 16 errors within 125 μs. This is an
asynchronous signal.
Enable
rx_enh_highber_clr_c
nt port (10GBASE-R)
On / Off
Enables the rx_enh_highber_clr_cnt input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted
to clear the internal counter. This counter indicates the number of
times the BER state machine has entered the "BER_BAD_SH"
state. This is an asynchronous signal.
Enable
rx_enh_clr_errblk_cou
nt port (10GBASE-R)
On / Off
Enables the rx_enh_clr_errblk_count input port. For the
10GBASE-R transceiver configuration rule, this signal is asserted
to clear the internal counter. This counter indicates the number of
the times the RX state machine has entered the RX_E state. For
protocols with FEC block enabled, this signal is asserted to reset
the status counters within the RX FEC block. This is an
asynchronous signal.
Table 24.
64b/66b Encoder and Decoder Parameters
Parameter
Range
Description
Enable TX 64b/66b
encoder (10GBASE-R)
On / Off
When you turn on this option, the Enhanced PCS enables the TX
64b/66b encoder.
Enable RX 64b/66b
decoder (10GBASE-R)
On / Off
When you turn on this option, the Enhanced PCS enables the RX
64b/66b decoder.
Enable TX sync header
error insertion
On / Off
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition
testing on the receiver. When error insertion is enabled and the
error flag is set, the encoding sync header for the current word is
generated incorrectly. If the correct sync header is 2'b01 (control
type), 2'b00 is encoded. If the correct sync header is 2'b10 (data
type), 2'b11 is encoded.
Table 25.
Scrambler and Descrambler Parameters
Parameter
Range
Description
Enable TX scrambler
(10GBASE-R/
Interlaken)
On / Off
Enables the scrambler function. This option is available for the
Basic (Enhanced PCS) mode, Interlaken, and 10GBASE-R
protocols. You can enable the scrambler in Basic (Enhanced PCS)
mode when the block synchronizer is enabled and with 66:32,
66:40, or 66:64 gear box ratios.
TX scrambler seed
(10GBASE-R/
Interlaken)
User-specified 58-bit
value
You must provide a non-zero seed for the Interlaken protocol. For
a multi-lane Interlaken Transceiver Native PHY IP, the first lane
scrambler has this seed. For other lanes' scrambler, this seed is
increased by 1 per each lane. The initial seed for 10GBASE-R is
0x03FFFFFFFFFFFFFF. This parameter is required for the
10GBASE-R and Interlaken protocols.
Enable RX descrambler
(10GBASE-R/
Interlaken)
On / Off
Enables the descrambler function. This option is available for Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols. You
can enable the descrambler in Basic (Enhanced PCS) mode with
the block synchronizer enabled and with 66:32, 66:40, or 66:64
gear box ratios.
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Table 26.
Interlaken Disparity Generator and Checker Parameters
Parameter
Range
Description
Enable Interlaken TX
disparity generator
On / Off
When you turn on this option, the Enhanced PCS enables the
disparity generator. This option is available for the Interlaken
protocol.
Enable Interlaken RX
disparity checker
On / Off
When you turn on this option, the Enhanced PCS enables the
disparity checker. This option is available for the Interlaken
protocol.
Enable Interlaken TX
random disparity bit
On / Off
Enables the Interlaken random disparity bit. When enabled, a
random number is used as disparity bit which saves one cycle of
latency.
Table 27.
Block Synchronizer Parameters
Parameter
Range
Description
Enable RX block
synchronizer
On / Off
When you turn on this option, the Enhanced PCS enables the RX
block synchronizer. This options is available for the Basic
(Enhanced PCS) mode, Interlaken, and 10GBASE-R protocols.
Enable
rx_enh_blk_lock port
On / Off
Enables the rx_enh_blk_lock port. When you enable the block
synchronizer, this signal is asserted to indicate that the block
delineation has been achieved.
Table 28.
Gearbox Parameters
Parameter
Range
Description
Enable TX data bitslip
On / Off
When you turn on this option, the TX gearbox operates in bitslip
mode. The tx_enh_bitslip port controls number of bits which TX
parallel data slips before going to the PMA.
Enable TX data polarity
inversion
On / Off
When you turn on this option, the polarity of TX data is inverted.
This allows you to correct incorrect placement and routing on the
PCB.
Enable RX data bitslip
On / Off
When you turn on this option, the Enhanced PCS RX block
synchronizer operates in bitslip mode. When enabled, the
rx_bitslip port is asserted on the rising edge to ensure that RX
parallel data from the PMA slips by one bit before passing to the
PCS.
Enable RX data
polarity inversion
On / Off
When you turn on this option, the polarity of the RX data is
inverted. This allows you to correct incorrect placement and
routing on the PCB.
Enable tx_enh_bitslip
port
On / Off
Enables the tx_enh_bitslip port. When TX bit slip is enabled,
this signal controls the number of bits which TX parallel data slips
before going to the PMA.
Enable rx_bitslip port
On / Off
Enables the rx_bitslip port. When RX bit slip is enabled, the
rx_bitslip signal is asserted on the rising edge to ensure that
RX parallel data from the PMA slips by one bit before passing to
the PCS. This port is shared between Standard PCS and Enhanced
PCS.
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Table 29.
KR-FEC Parameters
Parameter
Range
Description
Enable RX KR-FEC
error marking
On/Off
When you turn on this option, the decoder asserts both sync bits
(2'b11) when it detects an uncorrectable error. This feature
increases the latency through the KR-FEC decoder.
Error marking type
10G, 40G
Specifies the error marking type (10G or 40G).
Enable KR-FEC TX
error insertion
On/Off
Enables the error insertion feature of the KR-FEC encoder. This
feature allows you to insert errors by corrupting data starting a bit
0 of the current word.
KR-FEC TX error
insertion spacing
User Input (1 bit to 15
bit)
Specifies the spacing of the KR-FEC TX error insertion.
Enable tx_enh_frame
port
On/Off
Enables the tx_enh_frame port.
Enable rx_enh_frame
port
On/Off
Enables the rx_enh_frame port.
Enable
rx_enh_frame_diag_st
atus port
On/Off
Enables the rx_enh_frame_diag_status port.
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
•
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS on page 288
•
Interlaken on page 92
•
10GBASE-KR PHY IP Core on page 133
•
Enhanced PCS Ports on page 74
•
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on
page 122
2.4.5 Standard PCS Parameters
This section provides descriptions of the parameters that you can specify to customize
the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer
to the sections of this user guide that describe support for these protocols.
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Table 30.
Standard PCS Parameters
Note:
Parameter
Standard PCS/PMA
interface width
For detailed descriptions of the optional ports that you can enable or disable, refer to the
Standard PCS Ports on page 84 section.
Range
8, 10, 16, 20
Description
Specifies the data interface width between the Standard PCS and
the transceiver PMA.
FPGA fabric/Standard
TX PCS interface width
8, 10, 16, 20, 32, 40
Shows the FPGA fabric to TX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard TX PCS datapath.
FPGA fabric/Standard
RX PCS interface width
8, 10, 16, 20, 32, 40
Shows the FPGA fabric to RX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard RX PCS datapath.
On / Off
Enables the low latency path for the Standard PCS. Some of the
functional blocks within the Standard PCS are bypassed to provide
the lowest latency. You cannot turn on this parameter while using
the Basic/Custom w/Rate Match (Standard PCS) specified for
Transceiver configuration rules.
Enable Standard PCS
low latency mode
Table 31.
Standard PCS FIFO Parameters
Parameter
Range
Description
TX FIFO mode
low_latency
register_fifo
fast_register
Specifies the Standard PCS TX FIFO mode. The following modes
are available:
• low_latency: This mode adds 2-3 cycles of latency to the TX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
• fast_register: This mode allows a higher maximum frequency
(fMAX) between the FPGA fabric and the TX PCS at the expense
of higher latency.
RX FIFO mode
low_latency
register_fifo
The following modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the RX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI or
1588.
Enable
tx_std_pcfifo_full port
On / Off
Enables the tx_std_pcfifo_full port. This signal indicates
when the standard TX phase compensation FIFO is full. This signal
is synchronous with tx_coreclkin.
Enable
tx_std_pcfifo_empty
port
On / Off
Enables the tx_std_pcfifo_empty port. This signal indicates
when the standard TX phase compensation FIFO is empty. This
signal is synchronous with tx_coreclkin.
Enable
rx_std_pcfifo_full port
On / Off
Enables the rx_std_pcfifo_full port. This signal indicates
when the standard RX phase compensation FIFO is full. This signal
is synchronous with rx_coreclkin.
Enable
rx_std_pcfifo_empty
port
On / Off
Enables the rx_std_pcfifo_empty port. This signal indicates
when the standard RX phase compensation FIFO is empty. This
signal is synchronous with rx_coreclkin.
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Table 32.
Byte Serializer and Deserializer Parameters
Parameter
Range
Description
Enable TX byte
serializer
Disabled
Serialize x2
Serialize x4
Specifies the TX byte serializer mode for the Standard PCS. The
transceiver architecture allows the Standard PCS to operate at
double or quadruple the data width of the PMA serializer. The byte
serializer allows the PCS to run at a lower internal clock frequency
to accommodate a wider range of FPGA interface widths.
Serialize x4 is only applicable for PCIe protocol implementation.
Enable RX byte
deserializer
Disabled
Deserialize x2
Deserialize x4
Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to
operate at double or quadruple the data width of the PMA
deserializer. The byte deserializer allows the PCS to run at a lower
internal clock frequency to accommodate a wider range of FPGA
interface widths. Deserialize x4 is only applicable for PCIe
protocol implementation.
Table 33.
8B/10B Encoder and Decoder Parameters
Parameter
Range
Description
Enable TX 8B/10B
encoder
On / Off
When you turn on this option, the Standard PCS enables the TX
8B/10B encoder.
Enable TX 8B/10B
disparity control
On / Off
When you turn on this option, the Standard PCS includes disparity
control for the 8B/10B encoder. You can force the disparity of the
8B/10B encoder using the tx_forcedisp control signal.
Enable RX 8B/10B
decoder
On / Off
When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Table 34.
Rate Match FIFO Parameters
Parameter
Range
Description
Disabled
Basic 10-bit PMA
width
Basic 20-bit PMA
width
GbE
PIPE
PIPE 0 ppm
Specifies the operation of the RX rate match FIFO in the Standard
PCS.
Rate Match FIFO in Basic (Single Width) Mode on page 305
RX rate match insert/
delete -ve pattern (hex)
User-specified 20 bit
pattern
Specifies the -ve (negative) disparity value for the RX rate match
FIFO as a hexadecimal string.
RX rate match insert/
delete +ve pattern (hex)
User-specified 20 bit
pattern
Specifies the +ve (positive) disparity value for the RX rate match
FIFO as a hexadecimal string.
Enable rx_std_rmfifo_full
port
On / Off
Enables the optional rx_std_rmfifo_full port.
Enable
rx_std_rmfifo_empty port
On / Off
Enables the rx_std_rmfifo_empty port.
PCI Express* Gen3 rate
match FIFO mode
Bypass
0 ppm
600 ppm
Specifies the PPM tolerance for the PCI Express Gen3 rate match
FIFO.
RX rate match FIFO mode
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Rate Match FIFO Basic (Double Width) Mode on page 307
Rate Match FIFO for GbE on page 115
Transceiver Channel Datapath for PIPE on page 228
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Table 35.
Word Aligner and Bitslip Parameters
Parameter
Range
Description
Enable TX bitslip
On / Off
When you turn on this option, the PCS includes the bitslip
function. The outgoing TX data can be slipped by the
number of bits specified by the
tx_std_bitslipboundarysel control signal.
Enable tx_std_bitslipboundarysel
port
On / Off
Enables the tx_std_bitslipboundarysel control signal.
bitslip
manual (PLD
controlled)
synchronous state
machine
deterministic
latency
Specifies the RX word aligner mode for the Standard PCS.
The word aligned width depends on the PCS and PMA width,
and whether or not 8B/10B is enabled.
Refer to "Word Aligner" for more information.
RX word aligner pattern length
7, 8, 10, 16, 20,
32, 40
Specifies the length of the pattern the word aligner uses for
alignment.
Refer to "RX Word Aligner Pattern Length" table in "Word
Aligner". It shows the possible values of "Rx Word Aligner
Pattern Length" in all available word aligner modes.
RX word aligner pattern (hex)
User-specified
RX word aligner mode
Number of word alignment
patterns to achieve sync
Number of invalid words to lose
sync
Number of valid data words to
decrement error count
Specifies the word alignment pattern in hex.
0-255
Specifies the number of valid word alignment patterns that
must be received before the word aligner achieves
synchronization lock. The default is 3.
0-63
Specifies the number of invalid data codes or disparity
errors that must be received before the word aligner loses
synchronization. The default is 3.
0-255
Specifies the number of valid data codes that must be
received to decrement the error counter. If the word aligner
receives enough valid data codes to decrement the error
count to 0, the word aligner returns to synchronization lock.
Enable fast sync status reporting
for deterministic Latency SM
On / Off
When enabled, the rx_syncstatus asserts high
immediately after the deserializer has completed slipping
the bits to achieve word alignment. When it is not selected,
rx_syncstatus will assert after the cycle slip operation is
complete and the word alignment pattern is detected by the
PCS (i.e. rx_patterndetect is asserted). This parameter
is only applicable when the selected protocol is CPRI (Auto).
Enable rx_std_wa_patternalign
port
On / Off
Enables the rx_std_wa_patternalign port. When the
word aligner is configured in manual mode and when this
signal is enabled, the word aligner aligns to next incoming
word alignment pattern.
Enable rx_std_wa_a1a2size port
On / Off
Enables the optional rx_std_wa_a1a2size control input
port.
Enable
rx_std_bitslipboundarysel port
On / Off
Enables the optional rx_std_bitslipboundarysel status
output port.
Enable rx_bitslip port
On / Off
Enables the rx_bitslip port. This port is shared between
the Standard PCS and Enhanced PCS.
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Table 36.
Bit Reversal and Polarity Inversion
Parameter
Range
Description
Enable TX bit reversal
On / Off
When you turn on this option, the 8B/10B Encoder reverses TX
parallel data before transmitting it to the PMA for serialization.
The transmitted TX data bit order is reversed. The normal order
is LSB to MSB. The reverse order is MSB to LSB. During the
operation of the circuit, this setting can be changed through
dynamic reconfiguration.
Enable TX byte reversal
On / Off
When you turn on this option, the 8B/10B Encoder reverses the
byte order before transmitting data. This function allows you to
reverse the order of bytes that were erroneously swapped. The
PCS can swap the ordering of either one of the 8- or 10-bit
words, when the PCS/PMA interface width is 16 or 20 bits. This
option is not valid under certain Transceiver configuration
rules.
Enable TX polarity
inversion
On / Off
When you turn on this option, the tx_std_polinv port controls
polarity inversion of TX parallel data to the PMA. When you turn
on this parameter, you also need to turn on the Enable
tx_polinv port.
Enable tx_polinv port
On / Off
When you turn on this option, the tx_polinv input control port
is enabled. You can use this control port to swap the positive and
negative signals of a serial differential link, if they were
erroneously swapped during board layout.
Enable RX bit reversal
On / Off
When you turn on this option, the word aligner reverses RX
parallel data. The received RX data bit order is reversed. The
normal order is LSB to MSB. The reverse order is MSB to LSB.
This setting can be changed through dynamic reconfiguration.
When you enable Enable RX bit reversal, you must also enable
Enable rx_std_bitrev_ena port.
Enable rx_std_bitrev_ena
port
On / Off
When you turn on this option and assert the
rx_std_bitrev_ena control port, the RX data order is
reversed. The normal order is LSB to MSB. The reverse order is
MSB to LSB.
Enable RX byte reversal
On / Off
When you turn on this option, the word aligner reverses the byte
order, before storing the data in the RX FIFO. This function allows
you to reverse the order of bytes that are erroneously swapped.
The PCS can swap the ordering of either one of the 8- or 10-bit
words, when the PCS / PMA interface width is 16 or 20 bits. This
option is not valid under certain Transceiver configuration
rules.
When you enable Enable RX byte reversal, you must also
select the Enable rx_std_byterev_ena port.
Enable
rx_std_byterev_ena port
On / Off
When you turn on this option and assert the
rx_std_byterev_ena input control port, the order of the
individual 8- or 10-bit words received from the PMA is swapped.
Enable RX polarity
inversion
On / Off
When you turn on this option, the rx_std_polinv port inverts
the polarity of RX parallel data. When you turn on this
parameter, you also need to enable Enable rx_polinv port.
Enable rx_polinv port
On / Off
When you turn on this option, the rx_polinv input is enabled.
You can use this control port to swap the positive and negative
signals of a serial differential link if they were erroneously
swapped during board layout.
Enable rx_std_signaldetect
port
On / Off
When you turn on this option, the optional
rx_std_signaldetect output port is enabled. This signal is
required for the PCI Express protocol. If enabled, the signal
threshold detection circuitry senses whether the signal level
present at the RX input buffer is above the signal detect
continued...
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Parameter
Range
Description
threshold voltage that you specified. You can specify the signal
detect threshold using a Quartus Prime Assignment Editor or by
modifying the Quartus Settings File (.qsf)
Table 37.
PCIe Ports
Parameter
Range
Description
Enable PCIe dynamic
datarate switch ports
On / Off
When you turn on this option, the pipe_rate, pipe_sw, and
pipe_sw_done ports are enabled. You should connect these ports
to the PLL IP core instance in multi-lane PCIe Gen2 and Gen3
configurations. The pipe_sw and pipe_sw_done ports are only
available for multi-lane bonded configurations.
Enable PCIe
pipe_hclk_in and
pipe_hclk_out ports
On / Off
When you turn on this option, the pipe_hclk_in, and
pipe_hclk_out ports are enabled. These ports must be
connected to the PLL IP core instance for the PCI Express
configurations.
Enable PCIe Gen3
analog control ports
On / Off
When you turn on this option, the pipe_g3_txdeemph and
pipe_g3_rxpresenthint ports are enabled. You can use these
ports for equalization for Gen3 configurations.
Enable PCIe electrical
idle control and status
ports
On / Off
Enable PCIe
pipe_rx_polarity port
On / Off
When you turn on this option, the pipe_rx_eidleinfersel and
pipe_rx_elecidle ports are enabled. These ports are used for
PCI Express configurations.
When you turn on this option, the pipe_rx_polarity input
control port is enabled. You can use this option to control channel
signal polarity for PCI Express configurations. When the Standard
PCS is configured for PCIe, the assertion of this signal inverts the
RX bit polarity. For other Transceiver configuration rules the
optional rx_polinv port inverts the polarity of the RX bit stream.
Related Links
•
Standard PCS Ports on page 84
•
Word Aligner on page 469
2.4.6 PCS Direct
Table 38.
PCS Direct Datapath Parameters
Parameter
PCS Direct interface width
Range
8, 10, 16, 20, 32, 40, 64
Description
Specifies the data interface width between the PLD and
the transceiver PMA.
2.4.7 Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels
and PLLs without powering down the device. Each transceiver channel and PLL
includes an Avalon-MM slave interface for reconfiguration. This interface provides
direct access to the programmable address space of each channel and PLL. Because
each channel and PLL includes a dedicated Avalon-MM slave interface, you can
dynamically modify channels either concurrently or sequentially. If your system does
not require concurrent reconfiguration, you can parameterize the Transceiver Native
PHY IP to share a single reconfiguration interface.
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You can use dynamic reconfiguration to change many functions and features of the
transceiver channels and PLLs. For example, you can change the reference clock input
to the TX PLL. You can also change between the Standard and Enhanced datapaths.
Table 39.
Dynamic Reconfiguration
Parameter
Value
Description
Enable dynamic
reconfiguration
On/Off
When you turn on this option, the dynamic reconfiguration
interface is enabled.
Share reconfiguration
interface
On/Off
When you turn on this option, the Transceiver Native PHY IP
presents a single Avalon-MM slave interface for dynamic
reconfiguration for all channels. In this configuration, the upper
[n-1:10] address bits of the reconfiguration address bus specify
the channel. The channel numbers are binary encoded. Address
bits [9:0] provide the register offset address within the
reconfiguration space for a channel.
Enable Altera Debug
Master Endpoint
On/Off
When you turn on this option, the Transceiver Native PHY IP
includes an embedded Altera Debug Master Endpoint (ADME) that
connects internally to the Avalon-MM slave interface for dynamic
reconfiguration. The ADME can access the reconfiguration space of
the transceiver. It can perform certain test and debug functions
via JTAG using the System Console. This option requires you to
enable the Share reconfiguration interface option for
configurations using more than one channel.
Separate
reconfig_waitrequest
from the status of
AVMM arbitration with
PreSICE
On/Off
When enabled, the reconfig_waitrequest will not indicate the
status of AVMM arbitration with PreSICE. The AVMM arbitration
status will be reflected in a soft status register bit. This feature
requires that the "Enable control and status registers" feature
under "Optional Reconfiguration Logic" be enabled.
Table 40.
Optional Reconfiguration Logic
Parameter
Enable capability
registers
Value
On/Off
Description
Enables capability registers that provide high level information about the
configuration of the transceiver channel.
Set user-defined IP
identifier
User-defined
Enable control and
status registers
On/Off
Enables soft registers to read status signals and write control signals on the
PHY interface through the embedded debug.
Enable PRBS (Pseudo
Random Binary
Sequence) soft
accumulators
On/Off
Enables soft logic for performing PRBS bit and error accumulation when the
hard PRBS generator and checker are used.
Table 41.
Sets a user-defined numeric identifier that can be read from the
user_identifier offset when the capability registers are enabled.
Configuration Files
Parameter
Value
Description
Configuration file
prefix
<prefix>
Here, the file prefix to use for generated configuration files is
specified. Each variant of the Transceiver Native PHY IP should use
a unique prefix for configuration files.
Generate
SystemVerilog
package file
On/Off
When you turn on this option, the Transceiver Native PHY IP
generates a SystemVerilog package file,
reconfig_parameters.sv. This file contains parameters defined
with the attribute values required for reconfiguration.
continued...
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Parameter
Value
Description
Generate C header file
On/Off
When you turn on this option, the Transceiver Native PHY IP
generates a C header file, reconfig_parameters.h. This file
contains macros defined with the attribute values required for
reconfiguration.
Generate MIF (Memory
Initialization File)
On/Off
When you turn on this option, the Transceiver Native PHY IP
generates a MIF, reconfig_parameters.mif. This file contains the
attribute values required for reconfiguration in a data format.
Include PMA analog
settings in
configuration files
On/Off
When enabled, the IP allows you to configure the PMA analog
settings that are selected in the Analog PMA settings (Optional)
tab. These settings will be included in your generated
configuration files.
Note: You must still specify the analog settings for your current
configuration using Quartus Prime Setting File (.qsf)
assignments in Quartus. This option does not remove the
requirement to specify Quartus Prime Setting File (.qsf)
assignments for your analog settings. Refer to the Analog
Parameter Settings chapter in the Arria 10 Transceiver PHY
User Guide for details on using the QSF assignments.
Table 42.
Configuration Profiles
Parameter
Value
Description
Enable
multiple
reconfiguratio
n profiles
On/Off
When enabled, you can use the GUI to store multiple configurations. This information is
used by Quartus to include the necessary timing arcs for all configurations during timing
driven compilation. The Native PHY generates reconfiguration files for all of the stored
profiles. The Native PHY also checks your multiple reconfiguration profiles for
consistency to ensure you can reconfigure between them. Among other things this
checks that you have exposed the same ports for each configuration.(28)
Enable
embedded
reconfiguratio
n streamer
On/Off
Enables the embedded reconfiguration streamer, which automates the dynamic
reconfiguration process between multiple predefined configuration profiles. This is
optional and increases logic utilization. The PHY includes all of the logic and data
necessary to dynamically reconfigure between pre-configured profiles.
Generate
reduced
reconfiguratio
n files
On/Off
When enabled, The Native PHY generates reconfiguration report files containing only the
attributes or RAM data that are different between the multiple configured profiles. The
reconfiguration time decreases with the use of reduced .mif files.
Number of
reconfiguratio
n profiles
1-8
Specifies the number of reconfiguration profiles to support when multiple reconfiguration
profiles are enabled.
Selected
reconfiguratio
n profile
0-7
Selects which reconfiguration profile to store/load/clear/refresh, when clicking the
relevant button for the selected profile.
Store
configuration
to selected
profile
-
Clicking this button saves or stores the current Native PHY parameter settings to the
profile specified by the Selected reconfiguration profile parameter.
Load
configuration
from selected
profile
-
Clicking this button loads the current Native PHY with parameter settings from the
stored profile specified by the Selected reconfiguration profile parameter.
continued...
(28)
For more information on timing closure, refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter.
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Parameter
Value
Description
Clear selected
profile
-
Clicking this button clears or erases the stored Native PHY parameter settings for the
profile specified by the Selected reconfiguration profile parameter. An empty profile
will default to the current parameter settings of the Native PHY.
Clear all
profiles
-
Clicking this button clears the Native PHY parameter settings for all the profiles.
Refresh
selected
profile
-
Clicking this button is equivalent to clicking the Load configuration from selected
profile and Store configuration to selected profile buttons in sequence. This
operation loads the Native PHY parameter settings from stored profile specified by the
Selected reconfiguration profile parameter and subsequently stores or saves the
parameters back to the profile.
Table 43.
Analog PMA Settings (Optional) for Dynamic Reconfiguration
Parameter
Value
Description
TX Analog PMA Settings
Analog Mode (Load Intelrecommended Default
settings)
Cei_11100_lr to xfp_9950
Selects the analog protocol mode to pre-select the
TX pin swing settings (VOD, Pre-emphasis, and
Slew Rate). After loading the pre-selected values
in the GUI, if one or more of the individual TX pin
swing settings need to be changed, then enable
the option to override the Intel-recommended
defaults to individually modify the settings.
Override Intel-recommended
Analog Mode Default settings
On/Off
Enables the option to override the Intelrecommended settings for the selected TX Analog
Mode for one or more TX analog parameters.
Output Swing Level (VOD)
0-31
Selects the transmitter programmable output
differential voltage swing.
Pre-Emphasis First Pre-Tap
Polarit
Fir_pre_1t_neg
Fir_pre_1t_pos
Selects the polarity of the first pre-tap for preemphasis.
Pre-Emphasis First Pre-Tap
Magnitude
0-16
Pre-Emphasis Second PreTap Polarity
Fir_pre_2t_neg
Fir_pre_2t_pos
Pre-Emphasis Second PreTap Magnitude
0-7
Pre-Emphasis First Post-Tap
Polarity
Fir_post_1t_neg
Fir_post_1t_pos
Pre-Emphasis First Post-Tap
Magnitude
0-25
(29)
(30)
(31)
Selects the magnitude of the first pre-tap for preemphasis
Selects the polarity of the second pre-tap for preemphasis.
Selects the magnitude of the second pre-tap for
pre-emphasis.
Selects the polarity of the first post-tap for preemphasis
Selects the magnitude of the first post-tap for
pre-emphasis.
continued...
(29)
For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter
Settings chapter.
(30)
For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter
Settings chapter.
(31)
For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter
Settings chapter.
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Parameter
Value
Description
Pre-Emphasis Second PostTap Polarity
Fir_post_2t_neg
Fir_post_2t_pos
Pre-Emphasis Second PostTap Magnitude
0-12
Slew Rate Control
slew_r0 to slew_r5
Selects the slew rate of the TX output signal. Valid
values span from slowest to the fastest rate.
High-Speed Compensation
Enable/Disable
Enables the power-distribution network (PDN)
induced inter-symbol interference (ISI)
compensation in the TX driver. When enabled, it
reduces the PDN induced ISI jitter, but increases
the power consumption.
On-Chip termination
r_r1
r_r2
Selects the on-chip TX differential termination.
Override Intel-recommended
Default settings
On/Off
Enables the option to override the Intelrecommended settings for one or more RX analog
parameters
CTLE (Continuous Time
Linear Equalizer) mode
non_s1_mode
S1_mode
Selects between the RX high gain mode
non_s1_mode or RX high data rate mode
s1_mode for the Continuous Time Linear
Equalizer (CTLE).
DC gain control of high gain
mode CTLE
No_dc_gain to stg4_gain7
Selects the DC gain of the Continuous Time Linear
Equalizer (CTLE) in high gain mode
AC Gain Control of High Gain
Mode CTLE
radp_ctle_acgain_4s_0 to
radp_ctle_acgain_4s_28
Selects the AC gain of the Continuous Time Linear
Equalizer (CTLE) in high gain mode when CTLE is
in manual mode.
AC Gain Control of High Data
Rate Mode CTLE
radp_ctle_eqz_1s_sel_0 to
Radp_ctle_eqz_1s_sel_15
Selects the AC gain of the Continuous Time Linear
Equalizer (CTLE) in high data rate mode when
CTLE is in manual mode.
Variable Gain Amplifier
(VGA) Voltage Swing Select
radp_vga_sel_0 to
radp_vga_sel_7
Selects the Variable Gain Amplifier (VGA) output
voltage swing when both the CTLE and DFE blocks
are in manual mode
Decision Feedback Equalizer
(DFE) Fixed Tap 1 Coefficient
radp_dfe_fxtap1_0 to
radp_dfe_fxtap1_127
Selects the co-efficient of the fixed tap 1 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode
Decision Feedback Equalizer
(DFE) Fixed Tap 2 Coefficient
radp_dfe_fxtap2_0 to
radp_dfe_fxtap2_127
Selects the co-efficient of the fixed tap 2 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode
Decision Feedback Equalizer
(DFE) Fixed Tap 3 Coefficient
radp_dfe_fxtap3_0 to
radp_dfe_fxtap3_127
Selects the co-efficient of the fixed tap 3 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 4 Coefficient
radp_dfe_fxtap4_0 to
radp_dfe_fxtap4_63
Selects the co-efficient of the fixed tap 4 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
(32)
Selects the polarity of the second post-tap for
pre-emphasis.
Selects the magnitude of the second post-tap for
pre-emphasis
RX Analog PMA settings
continued...
(32)
For more information refer to Available Options table in the
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter
Settings chapter.
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Parameter
Value
Description
Decision Feedback Equalizer
(DFE) Fixed Tap 5 Coefficient
radp_dfe_fxtap5_0 to
radp_dfe_fxtap5_63
Selects the co-efficient of the fixed tap 5 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 6 Coefficient
radp_dfe_fxtap6_0 to
radp_dfe_fxtap6_31
Selects the co-efficient of the fixed tap 6 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 7 Coefficient
radp_dfe_fxtap7_0 to
radp_dfe_fxtap7_31
Selects the co-efficient of the fixed tap 7 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 8 Coefficient
radp_dfe_fxtap8_0 to
radp_dfe_fxtap8_31
Selects the co-efficient of the fixed tap 8 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 9 Coefficient
radp_dfe_fxtap9_0 to
radp_dfe_fxtap9_31
Selects the co-efficient of the fixed tap 9 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 10 Coefficient
radp_dfe_fxtap10_0 to
radp_dfe_fxtap10_31
Selects the co-efficient of the fixed tap 10 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
Decision Feedback Equalizer
(DFE) Fixed Tap 11 Coefficient
radp_dfe_fxtap11_0 to
radp_dfe_fxtap11_31
Selects the co-efficient of the fixed tap 11 of the
Decision Feedback Equalizer (DFE) when
operating in manual mode.
On-Chip termination
R_ext0, r_r1, r_r2
Selects the on-chip RX differential termination.
Table 44.
Generation Options
Parameter
Value
Generate parameter
documentation file
On/Off
Description
When you turn on this option, generation produces a CommaSeparated Value (.csv ) file with descriptions of the Transceiver
Native PHY IP parameters.
Related Links
•
Analog Parameter Settings on page 563
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T on page 580
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T on page 580
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP on page 581
•
XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP on page 582
•
Reconfiguration Interface and Dynamic Reconfiguration on page 484
•
Transmitter Pre-Emphasis First Pre-Tap Value on page 578
•
Transmitter Pre-Emphasis Second Pre-Tap Value on page 578
•
Transmitter Pre-Emphasis First Post-Tap Value on page 579
•
Transmitter Pre-Emphasis Second Post-Tap Value on page 579
2.4.8 PMA Ports
This section describes the PMA and calibration ports for the Arria 10 Transceiver Native
PHY IP core.
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The following tables, the variables represent these parameters:
Table 45.
•
<n>—The number of lanes
•
<d>—The serialization factor
•
<s>—The symbol size
•
<p>—The number of PLLs
TX PMA Ports
Name
Direction
Clock Domain
Description
tx_serial_data[<n>
-1:0]
Input
N/A
This is the serial data output of the TX PMA.
tx_serial_clk0
Input
Clock
This is the serial clock from the TX PLL. The frequency of this
clock depends on the data rate and clock division factor. This
clock is for non bonded channels only. For bonded channels
use the tx_bonding_clocks clock TX input.
tx_bonding_clocks[
<n><6>-1:0]
Input
Clock
This is a 6-bit bus which carries the low speed parallel clock
per channel. These clocks are outputs from the master CGB.
Use these clocks for bonded channels only.
Optional Ports
tx_serial_clk1
tx_serial_clk2
tx_serial_clk3
tx_serial_clk4
Inputs
Clocks
These are the serial clocks from the TX PLL. The frequency of
these clocks depends on the data rate and clock division
factor. These additional ports are enabled when you specify
more than one TX PLL.
tx_analog_reset_ac
k
Output
Asynchronous
Enables the optional tx_pma_analog_reset_ack output.
This port should not be used for register mode data transfers
tx_pma_clkout
Output
Clock
This clock is the low speed parallel clock from the TX PMA. It
is available when you turn on Enable tx_pma_clkout port
in the Transceiver Native PHY IP core Parameter Editor. (33)
tx_pma_div_clkout
Output
Clock
If you specify a tx_pma_div_clkout division factor of 1 or
2, this clock output is derived from the PMA parallel clock
(low speed parallel clock). If you specify a
tx_pma_div_clkout division factor of 33, 40, or 66, this
clock is derived from the PMA serial clock. This clock is
commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as
66:40 applications.
tx_pma_iqtxrx_clko
ut
Output
Clock
This port is available if you turn on Enable tx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used to
cascade the TX PMA output clock to the input of a PLL.
tx_pma_elecidle[<n
>-1:0]
Input
Asynchronous
When you assert this signal, the transmitter is forced to
electrical idle. This port has no effect when you configure the
transceiver for the PCI Express protocol.
tx_pma_qpipullup[<
n>-1:0]
Input
Asynchronous
This port is available if you turn on Enable
tx_pma_qpipullup port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
continued...
(33)
This clock is not to be used to clock the FPGA - transceiver interface. This clock may be used
as a reference clock to an external clock cleaner.
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Name
Direction
Clock Domain
Description
tx_pma_qpipulldn[<
n>-1:0]
Input
Asynchronous
This port is available if you turn on Enable
tx_pma_qpipulldn port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick Path
Interconnect (QPI) applications.
tx_pma_txdetectrx[
<n>-1:0]
Input
Asynchronous
This port is available if you turn on Enable
tx_pma_txdetectrx port (QPI) in the Transceiver Native
PHY IP core Parameter Editor. When asserted, the receiver
detect block in TX PMA detects the presence of a receiver at
the other end of the channel. After receiving the
tx_pma_txdetectrx request, the receiver detect block
initiates the detection process. Use this port for Quick Path
Interconnect (QPI) applications only.
tx_pma_rxfound[<n>
-1:0]
Output
Synchronous to
This port is available if you turn on Enable
tx_rxfound_pma port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. When asserted, indicates that
the receiver detect block in TX PMA has detected a receiver
at the other end of the channel. Use this port for Quick Path
Interconnect (QPI) applications only.
rx_coreclkin or
rx_clkout based
on the
configuration.
rx_seriallpbken[<n
>-1:0]
Table 46.
Input
Asynchronous
This port is available if you turn on Enable rx_seriallpbken
port in the Transceiver Native PHY IP core Parameter
Editor. The assertion of this signal enables the TX to RX
serial loopback path within the transceiver. This signal can be
enabled in Duplex or Simplex mode. If enabled in Simplex
mode, you must drive the signal on both the TX and RX
instances from the same source. Otherwise the design fails
compilation.
RX PMA Ports
Name
Direction
Clock Domain
Description
rx_serial_data[<n>
-1:0]
Input
N/A
Specifies serial data input to the RX PMA.
rx_cdr_refclk0
Input
Clock
Specifies reference clock input to the RX clock data recovery
(CDR) circuitry.
Optional Ports
rx_cdr_refclk1–
rx_cdr_refclk4
Input
Clock
Specifies reference clock inputs to the RX clock data recovery
(CDR) circuitry.
rx_analog_reset_ac
k
Output
Asynchronous
Enables the optional rx_pma_analog_reset_ack output. This
port should not be used for register mode data transfers.
rx_pma_clkout
Output
Clock
This clock is the recovered parallel clock from the RX CDR
circuitry.
rx_pma_div_clkout
Output
Clock
The deserializer generates this clock. This is used to drive core
logic, PCS-to-FPGA fabric interface, or both. If you specify a
rx_pma_div_clkout division factor of 1 or 2, this clock output
is derived from the PMA parallel clock (low speed parallel
clock). If you specify a rx_pma_div_clkout division factor of
33, 40, or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the RX FIFO
runs at a different rate than the PMA parallel clock (low speed
parallel clock) frequency, such as 66:40 applications.
rx_pma_iqtxrx_clko
ut
Output
Clock
This port is available if you turn on Enable rx_
pma_iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used to
cascade the RX PMA output clock to the input of a PLL.
continued...
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Name
Direction
Clock Domain
Description
rx_pma_clkslip
Output
Clock
When asserted, indicates that the deserializer has either
skipped one serial bit or paused the serial clock for one cycle to
achieve word alignment. As a result, the period of the parallel
clock could be extended by 1 unit interval (UI) during the clock
slip operation.
rx_pma_qpipulldn[<
n>-1:0]
Input
Asynchronous
This port is only used for Quick Path Interconnect (QPI)
applications.
rx_is_lockedtodat
a[<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
incoming data, rx_serial_data.
rx_is_lockedtoref[
<n>-1:0]
Output
rx_clkout
When asserted, indicates that the CDR PLL is locked to the
input reference clock.
rx_set_locktodata[
<n>-1:0]
Input
Asynchronous
This port provides manual control of the RX CDR circuitry.
rx_set_locktoref[<
n>-1:0]
Input
Asynchronous
This port provides manual control of the RX CDR circuitry.
rx_seriallpbken[<n
>-1:0]
Input
Asynchronous
This port is available if you turn on Enable rx_ seriallpbken
port in the Transceiver Native PHY IP core Parameter Editor.
The assertion of this signal enables the TX to RX serial
loopback path within the transceiver. This signal is enabled in
Duplex or Simplex mode. If enabled in Simplex mode, you
must drive the signal on both the TX and RX instances from
the same source. Otherwise the design fails compilation.
rx_prbs_done[<n>-1
:0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates the verifier has aligned and captured
consecutive PRBS patterns and the first pass through a
polynomial is complete.
rx_prbs_err[<n>-1:
0]
Output
rx_coreclkin
or rx_clkout
When asserted, indicates an error only after the
rx_prbs_done signal has been asserted. This signal gets
asserted for three parallel clock cycles for every error that
occurs. Errors can only occur once per word.
rx_prbs_err_clr[<n
>-1:0]
Input
rx_coreclkin
or rx_clkout
When asserted, clears the PRBS pattern and deasserts the
rx_prbs_done signal.
Table 47.
Calibration Status Ports
Name
Direction
Clock Domain
Description
tx_cal_busy[<n>-1:0]
Output
Asynchronous
When asserted, indicates that the initial TX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed. You must hold the
channel in reset until calibration completes.
rx_cal_busy[<n>-1:0]
Output
Asynchronous
When asserted, indicates that the initial RX
calibration is in progress. For both initial and
manual recalibration, this signal will be asserted
during calibration and will deassert after
calibration is completed.
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Table 48.
Reset Ports
Name
Clock Domain(34)
Direction
Description
tx_analogreset[<n>-1:
0]
Input
Asynchronous
Resets the analog TX portion of the transceiver
PHY.
tx_digitalreset[<n>-1
:0]
Input
Asynchronous
Resets the digital TX portion of the transceiver
PHY.
rx_analogreset[<n>-1:
0]
Input
Asynchronous
Resets the analog RX portion of the transceiver
PHY.
rx_digitalreset[<n>-1
:0]
Input
Asynchronous
Resets the digital RX portion of the transceiver
PHY.
2.4.9 Enhanced PCS Ports
Figure 24.
Enhanced PCS Interfaces
The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
Nios Hard
Calibration IP
TX PMA
Serial Data
Clocks
QPI
Optional Ports
tx_serial_clk0
(from TX PLL)
reconfig_reset
reconfig_clk
reconfig_avmm
Reconfiguration
Registers
TX Enhanced PCS
TX Parallel Data, Control, Clocks
Enhanced PCS TX FIFO
Interlaken Frame Generator
Serializer
Clock
Generation
Block
tx_analog_reset
rx_analog_reset
RX PMA
Serial Data
Optional Ports
CDR Control
QPI
Clocks
PRBS
Bitslip
CDR
RX Enhanced PCS
Deserializer
RX Parallel Data, Control, Clocks
Enhanced PCS RX FIFO
Interlaken Frame Synchronizer
10GBASE-R BER Checker
Bitslip
In the following tables, the variables represent these parameters:
(34)
•
<n>—The number of lanes
•
<d>—The serialization factor
•
<s>— The symbol size
•
<p>—The number of PLLs
Although the reset ports are not synchronous to any clock domain, Intel recommends that you
synchronize the reset ports with the system clock.
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Table 49.
Enhanced TX PCS: Parallel Data, Control, and Clocks
Name
Direction
Clock Domain
Description
tx_parallel_data[
<n>128-1:0]
Input
Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
TX parallel data inputs from the FPGA fabric to the TX PCS. If
you select Enable simplified interface in the Transceiver
Native PHY IP Parameter Editor, tx_parallel_data
includes only the bits required for the configuration you specify.
You must ground the data pins that are not active. For single
width configuration, the following bits are active:
• 32-bit FPGA fabric to PCS interface width:
tx_parallel_data[31:0]. Ground [127:32].
• 40-bit FPGA fabric to PCS interface width:
tx_parallel_data[39:0]. Ground [127:40].
• 64-bit FPGA fabric to PCS interface width:
tx_parallel_data[63:0] Ground [127:64].
For double width configuration, the following bits are active:
• 40-bit FPGA fabric to PCS interface width: data[103:64],
[39:0]. Ground [127:104], [63:40].
• 64-bit FPGA fabric to PCS interface width: data[127:64],
[63:0].
Double-width mode is not supported for 32-bit, 50-bit, and 67bit FPGA fabric to PCS interface widths.
unused_tx_paralle
l_data
Input
tx_clkout
Port is enabled, when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of tx_parallel_data. Refer to tx_parallel_data to
identify the bits you need to ground.
tx_control[<n><3>
-1:0] or
tx_control[<n><18
>-1:0]
Input
Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
tx_control bits will have different functionality depending on
unused_tx_contro
l[<n> <15>-1:0]
tx_err_ins
Input
Input
the transceiver configuration rule selected. When Simplified
data interface is enabled, the number of bits in this bus will
change, as the unused bits will be shown as part of the
unused_tx_control port.
Refer to Enhanced PCS TX and RX Control Ports on page 81
section for more details.
Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
This port is enabled when you enable Enable simplified data
interface. Connect all of these bits to 0. When Enable
simplified data interface is disabled, the unused bits are a
part of the tx_control.
tx_coreclkin
For the Interlaken protocol, you can use this bit to insert the
synchronous header and CRC32 errors if you have turned on
Enable simplified data interface.
When asserted, the synchronous header for that cycle word is
replaced with a corrupted one. A CRC32 error is also inserted if
Enable Interlaken TX CRC-32 generator error insertion is
turned on. The corrupted sync header is 2'b00 for a control
word, and 2'b11 for a data word. For CRC32 error insertion, the
word used for CRC calculation for that cycle is incorrectly
inverted, causing an incorrect CRC32 in the Diagnostic Word of
the Metaframe.
Note that a synchronous header error and a CRC32 error
cannot be created for the Framing Control Words because the
Frame Control Words are created in the frame generator
Refer to tx_control to identify the bits you need to ground.
continued...
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Name
Direction
Clock Domain
Description
embedded in TX PCS. Both the synchronous header error and
the CRC32 errors are inserted if the CRC-32 error insertion
feature is enabled in the Transceiver Native PHY IP GUI.
tx_coreclkin
Input
Clock
The FPGA fabric clock. Drives the write side of the TX FIFO. For
the Interlaken protocol, the frequency of this clock could be
from datarate/67 to datarate/32. Using frequency lower than
this range can cause the TX FIFO to underflow and result in
data corruption.
tx_clkout
Output
Clock
This is a parallel clock generated by the local CGB for non
bonded configurations, and master CGB for bonded
configurations. This clocks the blocks of the TX Enhanced PCS.
The frequency of this clock is equal to the datarate divided by
PCS/PMA interface width.
Table 50.
Enhanced RX PCS: Parallel Data, Control, and Clocks
Name
Direction
Clock Domain
Description
rx_parallel_data[<n
>128-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
RX parallel data from the RX PCS to the FPGA fabric. If you
select, Enable simplified data interface in the Transceiver
Native PHY IP GUI, rx_parallel_data includes only the bits
required for the configuration you specify. Otherwise, this
interface is 128 bits wide.
When FPGA fabric to PCS interface width is 64 bits, the
following bits are active for interfaces less than 128 bits. You
can leave the unused bits floating or not connected.
• 32-bit FPGA fabric to PCS width: data[31:0].
• 40-bit FPGA fabric to PCS width: data[39:0].
• 64-bit FPGA fabric to PCS width: data[63:0].
When the FPGA fabric to PCS interface width is 128 bits, the
following bits are active:
• 40-bit FPGA fabric to PCS width: data[103:64], [39:0].
• 64-bit FPGA fabric to PCS width: data[127:0].
unused_rx_parallel_
data
Output
rx_clkout
This signal specifies the unused data when you turn on Enable
simplified data interface. When simplified data interface is
not set, the unused bits are a part of rx_parallel_data.
You can leave the unused data outputs floating or not
connected.
rx_control[<n>
<20>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
Indicates whether the rx_parallel_data bus is control or
data.
Refer to the Enhanced PCS TX and RX Control Ports on page
81 section for more details.
unused_rx_control[<
n>10-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
These signals only exist when you turn on Enable simplified
data interface. When simplified data interface is not set, the
unused bits are a part of rx_control. These outputs can be
left floating.
continued...
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Name
Direction
Clock Domain
Description
(rx_coreclk
in or
rx_clkout)
rx_coreclkin
Input
Clock
The FPGA fabric clock. Drives the read side of the RX FIFO. For
Interlaken protocol, the frequency of this clock could be from
datarate/67 to datarate/32.
rx_clkout
Output
Clock
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Enhanced PCS. The
frequency of this clock is equal to data rate divided by
PCS/PMA interface width.
Table 51.
Enhanced PCS TX FIFO
Name
Direction
Clock Domain
Description
tx_enh_data_valid[<n>1:0]
Input
Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates that the TX data is valid.
Connect this signal to 1'b1 for 10GBASE-R without 1588.
For 10GBASE-R with 1588, you must control this signal
based on the gearbox ratio. For Basic and Interlaken, you
need to control this port based on TX FIFO flags so that
the FIFO does not underflow or overflow.
Refer to Enhanced PCS FIFO Operation on page 296 for
more details.
tx_enh_fifo_full[<n>-1
:0]
Output
Synchronous to
the clock driving
the write side of
the FIFO
(tx_coreclkin
or tx_clkout)
Assertion of this signal indicates the TX FIFO is full.
Because the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296 for
more details.
tx_enh_fifo_pfull[<n>1:0]
Output
Synchronous to
the clock driving
the write side of
the FIFO
This signal gets asserted when the TX FIFO reaches its
partially full threshold. Because the depth is always
constant, you can ignore this signal for the phase
compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296 for
more details.
tx_coreclkin
or tx_clkout
tx_enh_fifo_empty[<n>1:0]
Output
Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
tx_enh_fifo_pempty[<n>
-1:0]
Output
Synchronous to
the clock driving
the write side of
the FIFO
tx_coreclkin
or tx_clkout
Table 52.
When asserted, indicates that the TX FIFO is empty. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296 for
more details.
When asserted, indicates that the TX FIFO has reached its
specified partially empty threshold. When you turn this
option on, the Enhanced PCS enables the
tx_enh_fifo_pempty port, which is asynchronous. This
signal gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal for
the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296 for
more details.
Enhanced PCS RX FIFO
Name
rx_enh_data_valid[<n>
-1:0]
Direction
Output
Clock Domain
Synchronous to
the clock driving
the read side of
Description
When asserted, indicates that rx_parallel_data is
valid. Discard invalid RX parallel data
whenrx_enh_data_valid signal is low.
continued...
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Name
Direction
Clock Domain
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_full[<n>1:0]
Output
Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_pfull[<n>
-1:0]
Output
Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_empty[<n>
-1:0]
Output
Synchronous to
the clock driving
the read side of
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_pempty[<n
>-1:0]
rx_enh_fifo_del[<n>-1
:0]
Output
Output
Synchronous to
the clock driving
the read side of
the FIFO
Description
This option is available when you select the following
parameters:
• Enhanced PCS Transceiver configuration rules
specifies Interlaken
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Phase
compensation
• Enhanced PCS Transceiver configuration rules
specifies Basic, and RX FIFO mode is Register
Refer to Enhanced PCS FIFO Operation on page 296
for more details.
When asserted, indicates that the RX FIFO is full. This
signal gets asserted for 2 to 3 clock cycles.Because
the depth is always constant, you can ignore this
signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296
for more details.
When asserted, indicates that the RX FIFO has
reached its specified partially full threshold. This signal
gets asserted for 2 to 3 clock cycles. Because the
depth is always constant, you can ignore this signal
for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296
for more details.
When asserted, indicates that the RX FIFO is empty.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296
for more details.
rx_coreclkin
or rx_clkout
When asserted, indicates that the RX FIFO has
reached its specified partially empty threshold.
Because the depth is always constant, you can ignore
this signal for the phase compensation mode.
Refer to Enhanced PCS FIFO Operation on page 296
for more details.
Synchronous to
the clock driving
the read side of
the FIFO
When asserted, indicates that a word has been deleted
from the RX FIFO. This signal gets asserted for 2 to 3
clock cycles. This signal is used for the 10GBASE-R
protocol.
rx_coreclkin
or rx_clkout
rx_enh_fifo_insert[<n
>-1:0]
Output
Synchronous to
the clock driving
the read side of
the FIFO
When asserted, indicates that a word has been
inserted into the RX FIFO. This signal is used for the
10GBASE-R protocol.
rx_coreclkin
or rx_clkout
rx_enh_fifo_rd_en[<n>
-1:0]
Output
Synchronous to
the clock driving
the read side of
the FIFO
For Interlaken only, when this signal is asserted, a
word is read form the RX FIFO. You need to control
this signal based on RX FIFO flags so that the FIFO
does not underflow or overflow.
rx_coreclkin
or rx_clkout
rx_enh_fifo_align_va
l[<n>-1:0]
Input
Synchronous to
the clock driving
the read side of
When asserted, indicates that the word alignment
pattern has been found. This signal is only valid for
the Interlaken protocol.
continued...
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Name
Direction
Clock Domain
Description
the FIFO
rx_coreclkin
or rx_clkout
rx_enh_fifo_align_cl
r[<n>-1:0]
Input
Synchronous to
the clock driving
the read side of
the FIFO
When asserted, the FIFO resets and begins searching
for a new alignment pattern. This signal is only valid
for the Interlaken protocol. Assert this signal for at
least 4 cycles.
rx_coreclkin
or rx_clkout
Table 53.
Interlaken Frame Generator, Synchronizer, and CRC32
Name
Direction
Clock Domain
Description
tx_enh_frame[<n>-1:0]
Output
tx_clkout
Asserted for 2 or 3 parallel clock cycles to indicate the
beginning of a new metaframe.
tx_enh_frame_diag_stat
us[<n> 2-1:0]
Input
tx_clkout
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This message is
inserted into the next diagnostic word generated by the
frame generator block. This bus must be held constant for 5
clock cycles before and after the tx_enh_frame pulse. The
following encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
tx_enh_frame_burst_en[
<n>-1:0]
Input
tx_clkout
If Enable frame burst is enabled, this port controls frame
generator data reads from the TX FIFO to the frame
generator. It is latched once at the beginning of each
Metaframe. If the value of tx_enh_frame_burst_en is 0,
the frame generator does not read data from the TX FIFO
for current Metaframe. Instead, the frame generator inserts
SKIP words as the payload of Metaframe. When
tx_enh_frame_burst_en is 1, the frame generator reads
data from the TX FIFO for the current Metaframe. This port
must be held constant for 5 clock cycles before and after
the tx_enh_frame pulse.
rx_enh_frame[<n>-1:0]
Output
rx_clkout
When asserted, indicates the beginning of a new received
Metaframe. This signal is pulse stretched.
rx_enh_frame_lock[<n>1:0]
Output
rx_clkout
When asserted, indicates the Frame Synchronizer state
machine has achieved Metaframe delineation. This signal is
pulse stretched.
rx_enh_frame_diag_stat
us[2 <n>-1:0]
Output
rx_clkout
Drives the lane status message contained in the framing
layer diagnostic word (bits[33:32]). This signal is latched
when a valid diagnostic word is received in the end of the
Metaframe while the frame is locked. The following
encodings are defined:
• Bit[1]: When 1, indicates the lane is operational. When
0, indicates the lane is not operational.
• Bit[0]: When 1, indicates the link is operational. When
0, indicates the link is not operational.
rx_enh_crc32_err[<n>-1
:0]
Output
rx_clkout
When asserted, indicates a CRC error in the current
Metaframe. Asserted at the end of current Metaframe. This
signal gets asserted for 2 or 3 cycles.
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Table 54.
10GBASE-R BER Checker
Name
Direction
Clock Domain
Description
rx_enh_highber[<n>-1:0
]
Output
rx_clkout
When asserted, indicates a bit error rate that is greater
than 10 -4. For the 10GBASE-R protocol, this BER rate
occurs when there are at least 16 errors within 125 µs.
This signal gets asserted for 2 to 3 clock cycles.
rx_enh_highber_clr_cn
t[<n>-1:0]
Input
rx_clkout
When asserted, clears the internal counter that indicates
the number of times the BER state machine has entered
the BER_BAD_SH state.
rx_enh_clr_errblk_coun
t[<n>-1:0] (10GBASE-R
Input
rx_clkout
When asserted the error block counter resets to 0.
Assertion of this signal clears the internal counter that
counts the number of times the RX state machine has
entered the RX_E state. In modes where the FEC block is
enabled, the assertion of this signal resets the status
counters within the RX FEC block.
and FEC)
Table 55.
Block Synchronizer
Name
Direction
Clock Domain
Output
rx_clkout
Direction
Clock Domain
rx_bitslip[<n>-1:0]
Input
rx_clkout
The rx_parallel_data slips 1 bit for every positive edge
of the rx_bitslip input. Keep the minimum interval
between rx_bitslip pulses to at least 20 cycles. The
maximum shift is < pcswidth -1> bits, so that if the PCS is
64 bits wide, you can shift 0-63 bits.
tx_enh_bitslip[<n>-1:0
]
Input
rx_clkout
The value of this signal controls the number of bits to slip
the tx_parallel_data before passing to the PMA.
Direction
Clock Domain
tx_enh_frame[<n>-1:0]
Output
tx_clkout
Asynchronous status flag output of TX KR-FEC that signifies
the beginning of generated KR FEC frame
rx_enh_frame[<n>-1:0]
Output
rx_clkout
Asynchronous status flag output of RX KR-FEC that
signifies the beginning of received KR FEC frame
rx_enh_frame_diag_stat
us
Output
rx_clkout
Asynchronous status flag output of RX KR-FEC that
indicates the status of the current received frame.
• 00: No error
• 01: Correctable Error
• 10: Un-correctale error
• 11: Reset condition/pre-lock condition
rx_enh_blk_lock<n>-1:0
]
Table 56.
When asserted, indicates that block synchronizer has
achieved block delineation. This signal is used for
10GBASE-R and Interlaken.
Gearbox
Name
Table 57.
Description
Description
KR-FEC
Name
Related Links
•
ATX PLL IP Core on page 342
•
CMU PLL IP Core on page 358
•
fPLL IP Core on page 350
•
Ports and Parameters on page 517
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Description
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•
Transceiver PHY Reset Controller Interfaces on page 423
2.4.9.1 Enhanced PCS TX and RX Control Ports
This section describes the tx_control and rx_control bit encodings for different
protocol configurations.
When Enable simplified data interface is ON, all of the unused ports shown in the
tables below, appear as a separate port. For example: It appears as
unused_tx_control/ unused_rx_control port.
Enhanced PCS TX Control Port Bit Encodings
Table 58.
Bit Encodings for Interlaken
Name
Bit
tx_control
Functionality
[1:0]
[2]
[7:3]
Synchronous header
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Inversion control
A logic low indicates that the built-in disparity
generator block in the Enhanced PCS maintains
the Interlaken running disparity.
Unused
[8]
Insert synchronous header error or
CRC32
[17:9]
Table 59.
Description
You can use this bit to insert synchronous header
error or CRC32 errors. The functionality is similar
to tx_err_ins. Refer to tx_err_ins signal
description for more details.
Unused
Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Name
Bit
tx_control
Table 60.
Functionality
[0]
XGMII control signal for parallel_data[7:0]
[1]
XGMII control signal for parallel_data[15:8]
[2]
XGMII control signal for parallel_data[23:16]
[3]
XGMII control signal for parallel_data[31:24]
[4]
XGMII control signal for parallel_data[39:32]
[5]
XGMII control signal for parallel_data[47:40]
[6]
XGMII control signal for parallel_data[55:48]
[7]
XGMII control signal for parallel_data[63:56]
[17:8]
Unused
Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Name
tx_control
Bit
[1:0]
[17:2]
Functionality
Synchronous header
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Unused
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Table 61.
Bit Encodings for Basic Double Width Mode
For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header.
Name
Bit
tx_control
Functionality
[1:0]
Synchronous header
[8:2]
Unused
[10:9]
[17:11]
Table 62.
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Synchronous header
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Unused
Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name
Bit
tx_control
Functionality
[1:0]
[2]
Description
Synchronous header
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Inversion control
A logic low indicates that built-in disparity
generator block in the Enhanced PCS maintains
the running disparity.
Enhanced PCS RX Control Port Bit Encodings
Table 63.
Bit Encodings for Interlaken
Name
rx_control
Bit
Functionality
Description
[1:0]
Synchronous header
The value 2'b01 indicates a data
word. The value 2'b10 indicates a
control word.
[2]
Inversion control
A logic low indicates that the builtin disparity generator block in the
Enhanced PCS maintains the
Interlaken running disparity. In the
current implementation, this bit is
always tied logic low (1'b0).
[3]
Payload word location
A logic high (1'b1) indicates the
payload word location in a
metaframe.
[4]
Synchronization word location
A logic high (1'b1) indicates the
synchronization word location in a
metaframe.
[5]
Scrambler state word location
A logic high (1'b1) indicates the
scrambler word location in a
metaframe.
[6]
SKIP word location
A logic high (1'b1) indicates the
SKIP word location in a metaframe.
[7]
Diagnostic word location
A logic high (1'b1) indicates the
diagnostic word location in a
metaframe.
continued...
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Name
Table 64.
Bit
Functionality
Description
[8]
Synchronization header error, metaframe error,
or CRC32 error status
A logic high (1'b1) indicates
synchronization header error,
metaframe error, or CRC32 error
status.
[9]
Block lock and frame lock status
A logic high (1'b1) indicates that
block lock and frame lock have
been achieved.
[19:10]
Unused
Bit Encodings for 10GBASE-R , 10GBASE-KR with FEC
Name
Bit
rx_control
Table 65.
Functionality
[0]
XGMII control signal for parallel_data[7:0]
[1]
XGMII control signal for parallel_data[15:8]
[2]
XGMII control signal for parallel_data[23:16]
[3]
XGMII control signal for parallel_data[31:24]
[4]
XGMII control signal for parallel_data[39:32]
[5]
XGMII control signal for parallel_data[47:40]
[6]
XGMII control signal for parallel_data[55:48]
[7]
XGMII control signal for parallel_data[63:56]
[19:8]
Unused
Bit Encodings for Basic Single Width Mode
For basic single width mode, the total word length is 66-bit with 64-bit data and 2-bit synchronous header.
Bit
Name
rx_control
[1:0]
Synchronous header
[7:2]
Unused
[9:8]
Synchronous header error status
[19:10]
Table 66.
Functionality
Description
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Unused
Bit Encodings for Basic Double Width Mode
For basic double width mode, total word length is 66-bit with 128-bit data, and 4-bit synchronous header.
Name
rx_control
Bit
Functionality
Description
[1:0]
Synchronous header
The value 2'b01 indicates a data word. The
value 2'b10 indicates a control word.
[7:2]
Unused
[8]
Synchronous header error status
Active-high status signal that indicates a
synchronous header error.
[9]
Block lock is achieved
Active-high status signal indicating when block
lock is achieved.
[11:10]
Synchronous header
The value 2'b01 indicates a data word. The
value 2'b10 indicates a control word.
continued...
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Name
Table 67.
Bit
Functionality
Description
[17:12]
Unused
[18]
Synchronous header error status
Active-high status signal that indicates a
synchronous header error.
[19]
Block lock is achieved
Active-high status signal indicating when Block
Lock is achieved.
Bit Encodings for Basic Mode
In this case, the total word length is 67-bit with 64-bit data and 2-bit synchronous header.
Name
Bit
rx_control
[1:0]
[2]
Functionality
Description
Synchronous header
The value 2'b01 indicates a data word. The value
2'b10 indicates a control word.
Inversion control
A logic low indicates that built-in disparity
generator block in the Enhanced PCS maintains
the running disparity.
2.4.10 Standard PCS Ports
Figure 25.
Transceiver Channel using the Standard PCS Ports
Standard PCS ports will appear, if either one of the transceiver configuration modes is selected that uses
Standard PCS or if Data Path Reconfiguration is selected even if the transceiver configuration is not one of
those that uses Standard PCS.
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
Nios Hard
Calibration IP
TX PMA
Serial Data
Clocks
QPI
PCIe
Optional Ports
tx_serial_clk0
(from TX PLL)
Reconfiguration
Registers
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TX Standard PCS
Parallel Data, Control, Clocks
TX FIFO
8B/10B Encoder/Decoder
PCIe
Serializer
Clock
Generation
Block
tx_analog_reset
rx_analog_reset
RX PMA
Serial Data
Optional Ports
CDR Control
QPI
Clocks
PRBS
Bit & Byte Reversal
Polarity Inversion
CDR
reconfig_reset
reconfig_clk
reconfig_avmm
Deserializer
RX Standard PCS
Parallel Data, Control, Clocks
RX FIFO
Rate Match FIFO
Word Aligner & Bitslip
PCIe
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In the following tables, the variables represent these parameters:
Table 68.
•
<n>—The number of lanes
•
<w>—The width of the interface
•
<d>—The serialization factor
•
<s>— The symbol size
•
<p>—The number of PLLs
TX Standard PCS: Data, Control, and Clocks
Name
Direction
Clock Domain
Description
tx_parallel_data[<n>
128-1:0]
Input
tx_clkout
TX parallel data input from the FPGA fabric to the TX PCS.
unused_tx_parallel_d
ata
Input
tx_clkout
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data
interface is not set, the unused bits are a part of
tx_parallel_data. Connect all these bits to 0. If you do
not connect the unused data bits to 0, then TX parallel data
may not be serialized correctly by the Native PHY IP core.
tx_coreclkin
Input
Clock
The FPGA fabric clock. This clock drives the write port of the
TX FIFO.
tx_clkout
Output
Clock
This is the parallel clock generated by the local CGB for non
bonded configurations, and master CGB for bonded
configuration. This clocks the tx_parallel_data from the
FPGA fabric to the TX PCS.
Table 69.
RX Standard PCS: Data, Control, Status, and Clocks
Name
Direction
Clock Domain
Description
rx_parallel_data[<n>
128-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
RX parallel data from the RX PCS to the FPGA fabric. For
each 128-bit word of rx_parallel_data, the data bits
correspond to rx_parallel_data[7:0] when 8B/10B
decoder is enabled and rx_parallel_data[9:0] when
8B/10B decoder is disabled.
unused_rx_parallel_da
ta
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclk
in or
rx_clkout)
This signal specifies the unused data when you turn on
Enable simplified data interface. When simplified data
interface is not set, the unused bits are a part of
rx_parallel_data. These outputs can be left floating.
rx_clkout
Output
Clock
The low speed parallel clock recovered by the transceiver RX
PMA, that clocks the blocks in the RX Standard PCS.
rx_coreclkin
Input
Clock
RX parallel clock that drives the read side clock of the RX
FIFO.
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Table 70.
Standard PCS FIFO
Name
Direction
Clock Domain
tx_std_pcfifo_full[<n
>-1:0]
Output
Synchronous
to the clock
driving the
write side of
the FIFO
(tx_coreclki
n or
tx_clkout)
Indicates when the standard TX FIFO is full.
tx_std_pcfifo_empty[<
n>-1:0]
Output
Synchronous
to the clock
driving the
write side of
the FIFO
(tx_coreclki
n or
tx_clkout)
Indicates when the standard TX FIFO is empty.
rx_std_pcfifo_full[<n
>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclki
n or
rx_clkout)
Indicates when the standard RX FIFO is full.
rx_std_pcfifo_empty[<
n>-1:0]
Output
Synchronous
to the clock
driving the
read side of
the FIFO
(rx_coreclki
n or
rx_clkout)
Indicates when the standard RX FIFO is empty.
Table 71.
Description
Rate Match FIFO
Name
Direction
Clock Domain
rx_std_rmfifo_full[<n
>-1:0]
Output
Asynchronous
Rate match FIFO full flag. When asserted the rate match
FIFO is full. You must synchronize this signal. This port is
only used for GigE mode.
rx_std_rmfifo_empty[<
n>-1:0]
Output
Asynchronous
Rate match FIFO empty flag. When asserted, match FIFO is
empty. You must synchronize this signal. This port is only
used for GigE mode.
rx_rmfifostatus[<n>-1
:0]
Output
Asynchronous
Indicates FIFO status. The following encodings are defined:
• 2'b00: Normal operation
• 2'b01: Deletion, rx_std_rmfifo_full = 1
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Description
•
2'b10: Insertion, rx_std_rmfifo_empty = 1
•
2'b11: Full. rx_rmfifostatus is a part of
rx_parallel_data. rx_rmfifostatus corresponds
to rx_parallel_data[14:13].
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Table 72.
8B/10B Encoder and Decoder
Name
tx_datak
Direction
Clock Domain
Input
tx_clkout
Description
tx_datak is exposed if 8B/10B enabled and simplified data
interface is set.When 1, indicates that the 8B/10B encoded
word of tx_parallel_data is control. When 0, indicates that
the 8B/10B encoded word of tx_parallel_data is data.
tx_datak is a part of tx_parallel_data when simplified
data interface is not set.
tx_forcedisp[<n>(<w>/
<s>-1:0]
Input
Asynchronous
This signal allows you to force the disparity of the 8B/10B
encoder. When "1", forces the disparity of the output data to
the value driven on tx_dispval. When "0", the current
running disparity continues. tx_forcedisp is a part of
tx_parallel_data. tx_forcedisp corresponds to
tx_parallel_data[9].
tx_dispval[<n>(<w>/
<s>-1:0]
Input
Asynchronous
Specifies the disparity of the data. When 0, indicates positive
disparity, and when 1, indicates negative disparity.
tx_dispval is a part of tx_parallel_data. tx_dispval
corresponds to tx_dispval[10].
rx_datak[<n><w>/
<s>-1:0]
Output
rx_clkout
rx_datak is exposed if 8B/10B is enabled and simplified
rx_errdetect[<n><w>/
<s>-1:0]
Output
data interface is set. When 1, indicates that the 8B/10B
decoded word of rx_parallel_data is control. When 0,
indicates that the 8B/10B decoded word of
rx_parallel_data is data. rx_datak is a part of
rx_parallel_data when simplified data interface is not
set.
Synchronous to
the clock
driving the
read side of the
FIFO
(rx_coreclki
n or
rx_clkout)
When asserted, indicates a code group violation detected on
the received code group. Used along with rx_disperr
signal to differentiate between code group violation and
disparity errors. The following encodings are defined for
rx_errdetect/rx_disperr:
•
•
•
2'b00: no error
2'b10: code group violation
2'b11: disparity error. rx_errdetect is a part of
rx_parallel_data. For each 128-bit word,
rx_errdetect corresponds to
rx_parallel_data[9].
rx_disperr[<n><w>/
<s>-1:0]
Output
Synchronous to
the clock
driving the
read side of the
FIFO
(rx_coreclki
n or
rx_clkout)
When asserted, indicates a disparity error on the received
code group. rx_disperr is a part of rx_parallel_data.
For each 128-bit word, rx_disperr corresponds to
rx_parallel_data[11].
rx_runningdisp[<n><w>
/<s>-1:0]
Output
Synchronous to
the clock
driving the
read side of the
FIFO
(rx_coreclki
n or
rx_clkout)
When high, indicates that rx_parallel_data was received
with negative disparity. When low, indicates that
rx_parallel_data was received with positive disparity.
rx_runningdisp is a part of rx_parallel_data. For
each 128 bit word, rx_runningdisp corresponds to
rx_parallel_data[15].
rx_patterndetect[<n><
w>/<s>-1:0]
Output
Asynchronous
When asserted, indicates that the programmed word
alignment pattern has been detected in the current word
boundary. rx_patterndetect is a part of
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Name
Direction
Clock Domain
Description
rx_parallel_data. For each 128-bit word,
rx_patterndetect corresponds to
rx_parallel_data[12].
rx_syncstatus[<n><w>/
<s>-1:0]
Table 73.
Output
Asynchronous
When asserted, indicates that the conditions required for
synchronization are being met. rx_syncstatus is a part of
rx_parallel_data. For each 128-bit word,
rx_syncstatus corresponds to rx_parallel_data[10].
Word Aligner and Bitslip
Name
Direction
Clock Domain
Description
tx_std_bitslipboundary
sel[5 <n>-1:0]
Input
Asynchronous
Bitslip boundary selection signal. Specifies the number of
bits that the TX bit slipper must slip.
rx_std_bitslipboundary
sel[5 <n>-1:0]
Output
Asynchronous
This port is used in deterministic latency word aligner mode.
This port reports the number of bits that the RX block
slipped. This port values should be taken into consideration
in either Deterministic Latency Mode or Manual Mode of
Word Aligner.
rx_std_wa_patternalig
n[<n>-1:0]
Input
Synchronous
to rx_clkout
Active when you place the word aligner in manual mode. In
manual mode, you align words by asserting
rx_std_wa_patternalign. When the PCS-PMA Interface
width is 10 bits, rx_std_wa_patternalign is level
sensitive. For all the other PCS-PMA Interface widths,
rx_std_wa_patternalign is positive edge sensitive.
You can use this port only when the word aligner is
configured in manual or deterministic latency mode.
When the word aligner is in manual mode, and the PCS-PMA
interface width is 10 bits, this is a level sensitive signal. In
this case, the word aligner monitors the input data for the
word alignment pattern, and updates the word boundary
when it finds the alignment pattern.
For all other PCS-PMA interface widths, this signal is edge
sensitive.This signal is internally synchronized inside the
PCS using the PCS parallel clock and should be asserted for
at least 2 clock cycles to allow synchronization.
rx_std_wa_a1a2size[<n>
-1:0]
Input
Asynchronous
Used for the SONET protocol. Assert when the A1 and A2
framing bytes must be detected. A1 and A2 are SONET
backplane bytes and are only used when the PMA data
width is 8 bits.
rx_bitslip[<n>-1:0]
Input
Asynchronous
Used when word aligner mode is bitslip mode. When the
Word Aligner is in either Manual (PLD controlled),
Synchronous State Machine or Deterministic Latency ,the
rx_bitslip signal is not valid and should be tied to 0.
For every rising edge of the rx_std_bitslip signal, the
word boundary is shifted by 1 bit. Each bitslip removes the
earliest received bit from the received data.
Table 74.
Bit Reversal and Polarity Inversion
Name
Direction
Clock Domain
Description
rx_std_byterev_ena[<n>
-1:0]
Input
Asynchronous
This control signal is available when the PMA width is 16 or
20 bits. When asserted, enables byte reversal on the RX
interface. Used if the MSB and LSB of the transmitted data
are erroneously swapped.
rx_std_bitrev_ena[<n>1:0]
Input
Asynchronous
When asserted, enables bit reversal on the RX interface. Bit
order may be reversed if external transmission circuitry
transmits the most significant bit first. When enabled, the
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Name
Direction
Clock Domain
Description
receive circuitry receives all words in the reverse order. The
bit reversal circuitry operates on the output of the word
aligner.
tx_polinv[<n>-1:0]
Input
Asynchronous
When asserted, the TX polarity bit is inverted. Only active
when TX bit polarity inversion is enabled.
rx_polinv[<n>-1:0]
Input
Asynchronous
When asserted, the RX polarity bit is inverted. Only active
when RX bit polarity inversion is enabled.
rx_std_signaldetect[<n
>-1:0]
Output
Asynchronous
When enabled, the signal threshold detection circuitry
senses whether the signal level present at the RX input
buffer is above the signal detect threshold voltage. You can
specify the signal detect threshold using a Quartus Prime
Settings File (.qsf) assignment. This signal is required for
the PCI Express, SATA and SAS protocols.
Related Links
•
ATX PLL IP Core on page 342
•
CMU PLL IP Core on page 358
•
fPLL IP Core on page 350
•
Ports and Parameters on page 517
•
Transceiver PHY Reset Controller Interfaces on page 423
•
Analog Parameter Settings on page 563
2.4.11 IP Core File Locations
When you generate your Transceiver Native PHY IP, the Quartus® Prime software
generates the HDL files that define your instance of the IP. In addition, the Quartus
Prime software generates an example Tcl script to compile and simulate your design in
the ModelSim simulator. It also generates simulation scripts for Synopsys* VCS,
Aldec* Active-HDL, Aldec Riviera-Pro, and Cadence* Incisive Enterprise.
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Figure 26.
Directory Structure for Generated Files
<Project Directory>
<your_ip_or_system_name>.qsys - Top-level IP variation file
<your_ip_or_system_name>.sopcinfo
<your_ip_name> - IP core variation files
<your_ip_name>.cmp - VHDL component declaration file
<your_ip_name>_bb - Verilog HDL black-box EDA synthesis file
<your_ip_name>_inst - IP instantiation template file
<your_ip_name>.ppf - XML I/O pin information file
<your_ip_name>.qip - Lists IP synthesis files
<your_ip_name>.sip - Lists files for simulation
<your_ip_name>.v or .vhd - Greybox timing netlist
sim - IP simulation files
<your_ip_name>.v or .vhd - Top-level simulation file
aldec- Simulator setup scripts
cadence - Simulator setup scripts
mentor - Simulator setup scripts
synopsys - Simulator setup scripts
synth - IP synthesis files
<your_ip_name>.v or .vhd - Top-level IP synthesis file
<IP subcore> - IP subcore files
sim
<HDL files>
synth
<HDL files>
The following table describes the directories and the most important files for the
parameterized Transceiver Native PHY IP core and the simulation environment. These
files are in clear text.
Table 75.
Transceiver Native PHY Files and Directories
File Name
Description
<project_dir>
The top-level project directory.
<your_ip_name> .v or .vhd
The top-level design file.
<your_ip_name> .qip
A list of all files necessary for Quartus Prime compilation.
continued...
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File Name
Description
<your_ip_name> .bsf
A Block Symbol File (.bsf) for your Transceiver Native PHY
instance.
<project_dir>/<your_ip_name>/
The directory that stores the HDL files that define the
Transceiver Native PHY IP.
<project_dir>/sim
The simulation directory.
<project_dir>/sim/aldec
Simulation files for Riviera-PRO simulation tools.
<project_dir>/sim/cadence
Simulation files for Cadence simulation tools.
<project_dir>/sim/mentor
Simulation files for Mentor simulation tools.
<project_dir>/sim/synopsys
Simulation files for Synopsys simulation tools.
<project_dir>/synth
The directory that stores files used for synthesis.
The Verilog and VHDL Transceiver Native PHY IP cores have been tested with the
following simulators:
•
ModelSim SE
•
Synopsys VCS MX
•
Cadence NCSim
If you select VHDL for your transceiver PHY, only the wrapper generated by the
Quartus Prime software is in VHDL. All the underlying files are written in Verilog or
SystemVerilog. To enable simulation using a VHDL-only ModelSim license, the
underlying Verilog and SystemVerilog files for the Transceiver Native PHY IP are
encrypted so that they can be used with the top-level VHDL wrapper without using a
mixed-language simulator.
For more information about simulating with ModelSim, refer to the Mentor Graphics
ModelSim and QuestaSim Support chapter in volume 3 of the Quartus Prime
Handbook.
The Transceiver Native PHY IP cores do not support the NativeLink feature in the
Quartus Prime software.
Related Links
•
Simulating the Transceiver Native PHY IP Core on page 324
•
Mentor Graphics ModelSim and QuestaSim Support
2.4.12 Unused Transceiver RX Channels
To prevent performance degradation of unused transceiver RX channels over time, the
following assignments must be added to an Arria 10 device QSF. You can either use a
global assignment or per-pin assignments.
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
or
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to
pin_name
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When you perform this procedure, the Intel Quartus Prime software instantiates the
clock data recovery (CDR) PLL corresponding to each unused receiver channel. The
CDR uses CLKUSR as reference clock and is configured to run at 1 Gbps. To use
CLKUSR as reference clock, the pin must be assigned a 100- to 125 MHz clock. When
you implement these assignments, it causes a power consumption increase per
receiver channel. Please contact your local support center for details.
Related Links
Unused/Idle Clock Line Requirements on page 377
2.4.13 Unsupported Features
Native PHY should not be included in QXP.
2.5 Interlaken
Interlaken is a scalable, channelized chip-to-chip interconnect protocol.
The key advantages of Interlaken are scalability and low I/O count compared to earlier
protocols such as SPI 4.2. Other key features include flow control, low overhead
framing, and extensive integrity checking. Interlaken operates on 64-bit data words
and 3 control bits, which are striped round-robin across the lanes. The protocol
accepts packets on 256 logical channels and is expandable to accommodate up to
65,536 logical channels. Packets are split into small bursts that can optionally be
interleaved. The burst semantics include integrity checking and per logical channel
flow control.
The Interlaken interface is supported with 1 to 48 lanes running at data rates up to
12.5 Gbps per lane on Arria 10 devices. Interlaken is implemented using the Enhanced
PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP
vendors and third-party IP suppliers.
Arria 10 devices provide three preset variations for Interlaken in the Arria 10
Transceiver Native PHY IP Parameter Editor:
•
Interlaken 10x12.5 Gbps
•
Interlaken 1x6.25 Gbps
•
Interlaken 6x10.3 Gbps
Depending on the line rate, the enhanced PCS can use a PMA to PCS interface width of
32, 40, or 64 bits.
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Figure 27.
Transceiver Channel Datapath and Clocking for Interlaken
This figure assumes the serial data rate is 12.5 Gbps and the PMA width is 40 bits.
Enhanced PCS
TX FIFO
Interlaken
Frame Generator
64 bits
data +
3 bits
control
186.57 MHz
to 312.5MHz
PRP
Generator
tx_clkout
Transcode
Encoder
KR FEC
Encoder
KR FEC
TX Gearbox
KR FEC
Scrambler
Parallel Clock (312.5 MHz)
Serial Clock (6.25 GHz)
tx_coreclkin
PRBS
Generator
Interlaken
CRC32 Generator
64B/66B Encoder
and TX SM
Scrambler
TX
Gearbox
40
FPGA
Fabric
Interlaken
Disparity Generator
Transmitter Enhanced PCS
Serializer
tx_serial_data
Transmitter PMA
tx_pma_div_clkout
Receiver Enhanced PCS
Enhanced PCS
RX FIFO
Interlaken
CRC32 Checker
186.57 MHz
to 312.5MHz
PRP
Verifier
Div 40
64 bits
data +
3 bits
control
rx_clkout
Parallel Clock (312.5 MHz)
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
10GBASE-R
BER Checker
Clock Generation Block (CGB)
(6.25 GHz) =
Data rate/2
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
rx_coreclkin
PRBS
Verifier
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler
Block
Synchronizer
RX
Gearbox
40
Interlaken
Disparity Checker
rx_pma_div_clkout
Deserializer
CDR
rx_serial_data
Receiver PMA
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Related Links
•
Interlaken Protocol Definition v1.2
•
Interlaken Look-Aside Protocol Definition, v1.1
2.5.1 Metaframe Format and Framing Layer Control Word
The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words.
However, for stability and performance, Intel recommends you set the frame length to
no less than 128 words. In simulation, use a smaller metaframe length to reduce
simulation times. The payload of a metaframe could be pure data payload and a
Burst/Idle control word from the MAC layer.
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Figure 28.
Framing Layer Metaframe Format
Control and
Data Words
Diagnostic
Synchronization
Scrambler State
SKP
Diagnostic
Synchronization
Scrambler State
SKP
Metaframe Length
The framing control words include:
•
Synchronization (SYNC)—for frame delineation and lane alignment (deskew)
•
Scrambler State (SCRM)—to synchronize the scrambler
•
Skip (SKIP)—for clock compensation in a repeater
•
Diagnostic (DIAG)—provides per-lane error check and optional status message
To form a metaframe, the Enhanced PCS frame generator inserts the framing control
words and encapsulates the control and data words read from the TX FIFO as the
metaframe payload.
Figure 29.
Interlaken Synchronization and Scrambler State Words Format
bx10 b011110
h0F678F678F678F6
bx10 b001010
Scrambler State
66 63
58 57
Figure 30.
0
Interlaken Skip Word Format
bx10 b000111 h21E h1E h1E h1E h1E h1E h1E
66 63
58 57 48 47 40
0
The DIAG word is comprised of a status field and a CRC-32 field. The 2-bit status is
defined by the Interlaken specification as:
•
•
Bit 1 (Bit 33): Lane health
—
1: Lane is healthy
—
0: Lane is not healthy
Bit 0 (Bit 32): Link health
—
1: Link is healthy
—
0: Link is not healthy
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The tx_enh_frame_diag_status[1:0] input from the FPGA fabric is inserted into
the Status field each time a DIAG word is created by the framing generator.
Figure 31.
Interlaken Diagnostic Word
bx10 b011001
h000000
Status
66 63
58 57
34 33 32 31
CRC32
0
2.5.2 Interlaken Configuration Clocking and Bonding
The Arria 10 Interlaken PHY layer solution is scalable and has flexible data rates. You
can implement a single lane link or bond up to 48 lanes together. You can choose a
lane data rate up to 17.4 Gbps for GX devices and 25.8 Gbps for GT devices. You can
also choose between different reference clock frequencies, depending on the PLL used
to clock the transceiver. Refer to the Arria 10 Device Datasheet for the minimum and
maximum data rates that Arria 10 transceivers can support at different speed grades.
You can use an ATX PLL or fPLL to provide the clock for the transmit channel. An ATX
PLL has better jitter performance compared to an fPLL. You can use the CMU PLL to
clock only the non-bonded Interlaken transmit channels. However, if you use the CMU
PLL, you lose one RX transceiver channel.
For the multi-lane Interlaken interface, TX channels are usually bonded together to
minimize the transmit skew between all bonded channels. Currently, xN bonding and
PLL feedback compensation bonding schemes are available to support a multi-lane
Interlaken implementation. If the system tolerates higher channel-to-channel skew,
you can choose to not bond the TX channels.
To implement bonded multi-channel Interlaken, all channels must be placed
contiguously. The channels may all be placed in one bank (if not greater than six
lanes) or they may span several banks.
Related Links
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
Arria 10 Device Datasheet
2.5.2.1 xN Clock Bonding Scenario
The following figure shows a xN bonding example supporting 10 lanes. Each lane is
running at 12.5 Gbps. The first six TX channels reside in one transceiver bank and the
other four TX channels reside in the adjacent transceiver bank. The ATX PLL provides
the serial clock to the master CGB. The CGB then provides parallel and serial clocks to
all of the TX channels inside the same bank and other banks through the xN clock
network.
Because of xN clock network skew, the maximum achievable data rate decreases
when TX channels span several transceiver banks.
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Figure 32.
10X12.5 Gbps xN Bonding
Native PHY Instance
(10 Ch Bonded 12.5 Gbps)
Transceiver PLL
Instance (6.25 GHz)
ATX PLL
Master
CGB
Transceiver Bank 1
xN
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Transceiver Bank 2
TX Channel
TX Channel
TX Channel
TX Channel
Related Links
•
Implementing x6/xN Bonding Mode on page 392
For detailed information on xN bonding limitations
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
2.5.2.2 TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State
Machine
The Interlaken configuration sets the enhanced PCS TX and RX FIFOs in Interlaken
elastic buffer mode. In this mode of operation, TX and RX FIFO control and status port
signals are provided to the FPGA fabric. Connect these signals to the MAC layer as
required by the protocol. Based on these FIFO status and control signals, you can
implement the multi-lane deskew alignment state machine in the FPGA fabric to
control the transceiver RX FIFO block.
Note:
You must also implement the soft bonding logic to control the transceiver TX FIFO
block.
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2.5.2.2.1 TX FIFO Soft Bonding
The MAC layer logic and TX soft bonding logic control the writing of the Interlaken
word to the TX FIFO with tx_enh_data_valid (functions as a TX FIFO write enable)
by monitoring the TX FIFO flags (tx_fifo_full, tx_fifo_pfull,
tx_fifo_empty, tx_fifo_pempty, and so forth). On the TX FIFO read side, a read
enable is controlled by the frame generator. If tx_enh_frame_burst_en is asserted
high, the frame generator reads data from the TX FIFO.
A TX FIFO pre-fill stage must be implemented to perform the TX channel soft bonding.
The following figure shows the state of the pre-fill process.
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Figure 33.
TX Soft Bonding Flow
Exit from
tx_digitalreset
Deassert all lanes tx_enh_frame_burst_en
Assert all lanes tx_enh_data_valid
All lanes
full?
no
yes
Deassert all lanes
tx_enh_data_valid
Any lane
send new frame?
tx_enh_frame
asserted?
no
yes
Wait for extra 16
tx_coreclkin cycles
no
All lanes
full?
yes
TX FIFO pre-fill
completed
The following figure shows that after deasserting tx_digitalreset, TX soft bonding
logic starts filling the TX FIFO until all lanes are full.
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Figure 34.
TX FIFO Pre-fill (6-lane Interface)
Deassert tx_digitalreset
tx_digitalreset
3f
tx_enh_data_valid 00
tx_enh_fifo_full 00
tx_enh_fifo_pfull 00
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_enh_fifo_cnt
tx_enh_frame
tx_enh_frame_burst_en
00
3f
00
3f
3f
3f
3f
000000
00
00
00
1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff
3f
00
Deassert burst_en for all Lanes and Fill
TX FIFO Until all Lane FIFOs Are Full
After the TX FIFO pre-fill stage completes, the transmit lanes synchronize and the MAC
layer begins to send valid data to the transceiver’s TX FIFO. You must never allow the
TX FIFO to overflow or underflow. If it does, you must reset the transceiver and repeat
the TX FIFO pre-fill stage.
For a single lane Interlaken implementation, TX FIFO soft bonding is not required. You
can begin sending an Interlaken word to the TX FIFO after tx_digitalreset
deasserts.
The following figure shows the MAC layer sending valid data to the Native PHY after
the pre-fill stage. tx_enh_frame_burst_en is asserted, allowing the frame
generator to read data from the TX FIFO. The TX MAC layer can now control
tx_enh_data_valid and write data to the TX FIFO based on the FIFO status signals.
Figure 35.
MAC Sending Valid Data (6-lane Interface)
tx_digitalreset
tx_enh_data_valid
tx_enh_fifo_full
tx_enh_fifo_pfull
00
00
3f
3f
tx_enh_fifo_empty 00
tx_enh_fifo_pempty 00
tx_enh_fifo_cnt ffffff
tx_enh_frame 00
tx_enh_frame_burst_en 3f
3f
00
00
00
3f
3f
00
After the Pre-fill Stage, Assert burst_en.
The Frame Generator Reads Data from
the TX FIFO for the Next Metaframe
The User Logic Asserts data_valid
to Send Data to the TX FIFO Based
on the FIFO Status
The TX FIFO
Writes Backpressure
2.5.2.2.2 RX Multi-lane FIFO Deskew State Machine
Add deskew logic at the receiver side to eliminate the lane-to-lane skew created at the
transmitter of the link partner, PCB, medium, and local receiver PMA.
Implement a multi-lane alignment deskew state machine to control the RX FIFO
operation based on available RX FIFO status flags and control signals.
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Figure 36.
State Flow of the RX FIFO Deskew
Exit from
rx_digitalreset
Deassert all Lane’s rx_enh_fifo_rd_en
All Lane’s
rx_enh_fifo_pempty
Deasserted?
no
Assert rx_enh_fifo_align_clr for at
least 4 rx_coreclkin Cycles
yes
All Lane’s
rx_enh_fifo_pfull
Deasserted?
no
yes
RX FIFO Deskew
Completed
Each lane's rx_enh_fifo_rd_en should remain deasserted before the RX FIFO
deskew is completed. After frame lock is achieved (indicated by the assertion of
rx_enh_frame_lock; this signal is not shown in the above state flow), data is
written into the RX FIFO after the first alignment word (SYNC word) is found on that
channel. Accordingly, the RX FIFO partially empty flag (rx_enh_fifo_pempty) of
that channel is asserted. The state machine monitors the rx_enh_fifo_pempty and
rx_enh_fifo_pfull signals of all channels. If the rx_enh_fifo_pempty signals
from all channels deassert before any channels rx_enh_fifo_pfull assert, which
implies the SYNC word has been found on all lanes of the link, the MAC layer can start
reading from all the RX FIFO by asserting rx_enh_fifo_rd_en simultaneously.
Otherwise, if the rx_enh_fifo_pfull signal of any channel asserts high before the
rx_enh_fifo_pempty signals deassertion on all channels, the state machine needs
to flush the RX FIFO by asserting rx_enh_fifo_align_clr high for 4 cycles and
repeating the soft deskew process.
The following figure shows one RX deskew scenario. In this scenario, all of the RX
FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted.
This indicates the deskew is successful and the FPGA fabric starts reading data from
the RX FIFO.
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Figure 37.
RX FIFO Deskew
After deskew is successful, the user
logic asserts rd_en for all lanes to start
reading data from the RX FIFO.
rx_enh_fifo_full 00
rx_enh_fifo_empty 3f
rx_enh_fifo_rd_en 00
1e
00
3f
rx_enh_data_valid 00
rx_enh_fifo_pfull 00
rx_enh_fifo_pempty 3f
rx_enh_frame_lock 00
[5]
[4]
Each Lane Is
[3]
Frame-Locked
[2]
in a Different
Cycle
[1]
[0]
rx_enh_fifo_align_val 00
rx_enh_fifo_align_clr 00
3f
3f
1e
21
00
3b 3f
21
data_valid is asserted,
indicating that the RX FIFO
is outputting valid data.
Deassertion of pempty
of all lanes before any
lane pfull goes high,
which means the deskew
is complete.
3f
2.5.3 How to Implement Interlaken in Arria 10 Transceivers
You should be familiar with the Interlaken protocol, Enhanced PCS and PMA
architecture, PLL architecture, and the reset controller before implementing the
Interlaken protocol PHY layer.
Arria 10 devices provide three preset variations for Interlaken in the IP Parameter
Editor:
•
Interlaken 10x12.5 Gbps
•
Interlaken 1x6.25 Gbps
•
Interlaken 6x10.3 Gbps
1.
Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog
(Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤ Arria
10 Transceiver Native PHY).
Refer to Select and Instantiate the PHY IP Core on page 31 for more details.
2. Select Interlaken from the Transceiver configuration rules list located under
Datapath Options, depending on which protocol you are implementing.
3.
Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Interlaken Transceiver Configuration Rules.... Or you can use the protocol presets
described in Transceiver Native PHY Presets. You can then modify the settings to
meet your specific requirements.
4.
Click Generate to generate the Native PHY IP (this is your RTL file).
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Figure 38.
Signals and Ports of Native PHY IP for Interlaken
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
Reconfiguration
Registers
Hard
Calibration Block
TX Enhanced PCS
TX PMA
32/40/64
tx_serial_data
Serializer
tx_serial_clk or
tx_bonding_clocks[5:0]
(from TX PLL)
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_clkout
tx_coreclkin
tx_control[17:0] (1)
tx_parallel_data[127:0] (1)
tx_enh_data_valid
tx_enh_frame_burst_en
tx_enh_frame_diag_status[1:0]
tx_enh_frame
tx_enh_fifo_cnt[3:0]
tx_enh_fifo_full
tx_enh_fifo_pfull
tx_enh_fifo_empty
tx_enh_fifo_pempty
tx_analog_reset
rx_analog_reset
RX PMA
rx_serialloopback
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
RX Enhanced PCS
32/40/64
CDR
Deserializer
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0] (2)
rx_control[19:0] (2)
rx_enh_fifo_rd_en
rx_enh_data_valid
rx_enh_fifo_align_val
rx_enh_fifo_align_clr
rx_enh_frame
rx_enh_fifo_cnt[3:0]
rx_enh_fifo_full
rx_enh_fifo_pfull
rx_enh_fifo_empty
rx_enh_fifo_pempty
rx_enh_frame_diag_status[1:0]
rx_enh_frame_lock
rx_enh_crc32_err
rx_enh_blk_lock
Notes:
(1) The width of tx_parallel_data and tx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
tx_parallel_data = 64 bits and tx_control = 3 bits. The width shown here is without simplified interface.
(2) The width of rx_parallel_data and rx_control depends on whether the simplified interface is enabled or not. If the simplified interface is enabled, then
rx_parallel_data = 64 bits and rx_control = 10 bits. The width shown here is without simplified interface.
5.
Configure and instantiate your PLL.
6.
Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7.
Implement a TX soft bonding logic and an RX multi-lane alignment deskew state
machine using fabric logic resources for multi-lane Interlaken implementation.
8. Connect the Native PHY IP to the PLL IP and the reset controller.
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Figure 39.
Connection Guidelines for an Interlaken PHY Design
This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel
FPGA Wiki website.
For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in
the design example. The white blocks are your test logic or MAC layer logic.
PLL and CGB Reset
Reset
Controller
PLL IP
TX/RX Analog/Digital Reset
Pattern
Generator
Figure 40.
TX FIFO Control
TX Data Stream
Arria 10
Transceiver
Native PHY
RX FIFO Status
RX
Deskew
Control and Status
Pattern
Verifier
9.
TX FIFO Status
TX Soft
Bonding
Control and Status
TX Clocks
RX FIFO Control
RX Data Stream
Simulate your design to verify its functionality.
24 Lanes Bonded Interlaken Link, TX Direction
To show more details, three different time segments are shown with the same zoom level.
tx_ready
Asserted
pll_locked
tx_analogreset
tx_clkout[0]
tx_clkout
tx_digitalreset
tx_ready[0]
tx_ready
tx_enh_data_valid[0]
tx_enh_data_valid
tx_enh_fifo_full
tx_enh_frame[0]
tx_enh_frame
tx_enh_frame_burst_en[0]
tx_enh_frame_burst_en
tx_parallel_data
tx_control
tx_enh_fifo_empty
tx_enh_fifo_pempty
Pre-Fill Completed
Assert burst_en for
All Lanes
Pre-Fill
Stage
24`h000000
24`h000000
Send Data
Based on
FIFO Flags
24`h000000
24`h000000
24`h000000
24`h000000
24`...
24`hffffff
24`hffffff
24`h000000
24`hffffff
24`h000000
24`hffffff
24`hffffff
24`h000000
24`h000000
24`h000000
24`hffffff
24`...
24`hffffff
24`hffffff
24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`hffffff
24`hffffff
24`h000000
24`h000...
24`h000000
24`h000000
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`hffffff
1536`h0123456789abcdef01234567
72`h249249249249249249
24`h000000
24`h000000
1536`hbd212...
24 lanes bonded Interlaken link, TX direction
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Figure 41.
24 Lanes Bonded Interlaken Link, RX Direction
To show more details, three different time segments are shown with different zoom level.
Some Lanes pfull Signal Is Asserted
before All Lanes pempty is Deasserted;
RX Deskew Fails. Need to Realign
rx_ready
Asserted
rx_clkout[0]
rx_digitalreset
rx_ready
rx_enh_blk_lock
rx_enh_frame_lock
rx_enh_fifo_pfull[0]
rx_enh_fifo_pfull
rx_enh_fifo_pempty
rx_enh_fifo_align_clr
rx_enh_fifo_align_val
rx_enh_fifi_rd_en
rx_enh_data_valid
rx_parallel_data
rx_control
24`hffffff
24`h000000
24`h000000
24`h000000
24`h00... 24`h000000
24`hff... 24`hffffff
24`hffffff
24`h0... 24`h000001
24`h000000
24`hffffff
24`h000000
24`h000000
24`h000000
24`h000000
1536`h0100009c0100
240`h0441104411044
24`h000000
24`hffffff
24`hfffffe
24`h000000
24`h00...
24`h000001
24`h000000
24`h000000
All Lanes pfull Low and All
Lanes pempty Deasserted
RX Deskew Complete
24`h000000
24`hffffff
24`hffffff
24`hffffff
24`h000000 24`h00..
24`hffffff
24`hffffff
24`h00..
1536`h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000
240`h044110441104404411044110441104411044110441104411044110441104411
24`h000000
24`hffffff
24`h000000
24`h000000
24`hffffff
24`h000000
24`h000000
1536`h01000...
240`h044110...
Assert align_clr
to Re-Align
24`h000000
24`hffffff 24`h00.. 24`hffffff
24`hffffff 24`h00.. 24`hffffff
1536`h1e...
240`h90a... 240`h826...
Start Reading Data
Based on FIFO Flags
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Enhanced PCS Ports on page 74
For detailed information about the available ports in the Interlaken protocol
2.5.4 Design Example
Intel provides a PHY layer-only design example to help you integrate an Interlaken
PHY into your complete design.
The TX soft bonding logic is included in the design example. Intel recommends that
you integrate this module into your design.
The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design
Examples Wiki page.
Note:
The design examples on the Wiki page provide useful guidance for developing your
own designs, but they are not guaranteed by Intel. Use them with caution.
Related Links
Interlaken Design Example
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2.5.5 Native PHY IP Parameter Settings for Interlaken
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 76.
General and Datapath Parameters
Parameter
Value
Message level for rule violations
error
warning
Transceiver configuration rules
Interlaken
PMA configuration rules
basic
Transceiver mode
TX / RX Duplex
TX Simplex
RX Simplex
Number of data channels
1 to 96
Data rate
Up to 17.4 Gbps for GX devices
(Depending on Enhanced PCS to PMA interface width
selection)
Enable datapath and interface reconfiguration
On / Off
Enable simplified data interface
On / Off
Provide separate interface for each channel
On / Off
Table 77.
TX PMA Parameters
Parameter
Value
TX channel bonding mode
Not bonded
PMA-only bonding
PMA and PCS bonding
PCS TX channel bonding master
If TX channel bonding mode is set to PMA and PCS
bonding, then:
Auto, 0, 1, 2, 3,...,[Number of data channels – 1]
Actual PCS TX channel bonding master
If TX channel bonding mode is set to PMA and PCS
bonding, then:
0, 1, 2, 3,...,[Number of data channels – 1]
TX local clock division factor
If TX channel bonding mode is not bonded, then:
1, 2, 4, 8
Number of TX PLL clock inputs per channel
If TX channel bonding mode is not bonded, then:
1, 2, 3, 4
Initial TX PLL clock input selection
0
Enable tx_pma_clkout port
On / Off
Enable tx_pma_div_clkout port
On / Off
tx_pma_div_clkout division factor
When Enable tx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port
On / Off
Enable tx_pma_qpipullup port (QPI)
Off
continued...
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Parameter
Value
Enable tx_pma_qpipulldn port (QPI)
Off
Enable tx_pma_txdetectrx port (QPI)
Off
Enable tx_pma_rxfound port (QPI)
Off
Enable rx_seriallpbken port
On / Off
Table 78.
RX PMA Parameters
Parameter
Value
Number of CDR reference clocks
1 to 5
Selected CDR reference clock
0 to 4
Selected CDR reference clock frequency
Select legal range defined by the Quartus Prime software
PPM detector threshold
100, 300, 500, 1000
CTLE adaptation mode
manual,
DFE adaptation mode
adaptation enabled, manual, disabled
Number of fixed dfe taps
3, 7
Enable rx_pma_clkout port
On / Off
Enable rx_pma_div_clkout port
On / Off
rx_pma_div_clkout division factor
When Enable rx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port
On / Off
Enable rx_pma_qpipulldn port (QPI)
Off
Enable rx_is_lockedtodata port
On / Off
Enable rx_is_lockedtoref port
On / Off
Enable rx_set_locktodata and rx_set_locktoref ports
On / Off
Enable rx_seriallpbken port
On / Off
Enable PRBS verifier control and status ports
On / Off
Table 79.
Enhanced PCS Parameters
Parameter
Value
Enhanced PCS / PMA interface width
32, 40, 64
FPGA fabric / Enhanced PCS interface width
67
Enable 'Enhanced PCS' low latency mode
Allowed when the PMA interface width is 32 and preset
variations for data rate is 10.3125 Gbps or 6.25 Gbps;
otherwise Off
Enable RX/TX FIFO double-width mode
Off
TX FIFO mode
Interlaken
TX FIFO partially full threshold
8 to 15
TX FIFO partially empty threshold
1 to 8
Enable tx_enh_fifo_full port
On / Off
continued...
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Parameter
Value
Enable tx_enh_fifo_pfull port
On / Off
Enable tx_enh_fifo_empty port
On / Off
Enable tx_enh_fifo_pempty port
On / Off
RX FIFO mode
Interlaken
RX FIFO partially full threshold
from 10-29 (no less than pempty_threshold+8)
RX FIFO partially empty threshold
2 to 10
Enable RX FIFO alignment word deletion (Interlaken)
On / Off
Enable RX FIFO control word deletion (Interlaken)
On / Off
Enable rx_enh_data_valid port
On / Off
Enable rx_enh_fifo_full port
On / Off
Enable rx_enh_fifo_pfull port
On / Off
Enable rx_enh_fifo_empty port
On / Off
Enable rx_enh_fifo_pempty port
On / Off
Enable rx_enh_fifo_del port (10GBASE-R)
Off
Enable rx_enh_fifo_insert port (10GBASE-R)
Off
Enable rx_enh_fifo_rd_en port
On
Enable rx_enh_fifo_align_val port (Interlaken)
On / Off
Enable rx_enh_fifo_align_clr port (Interlaken)
On
Table 80.
Interlaken Frame Generator Parameters
Parameter
Value
Enable Interlaken frame generator
On
Frame generator metaframe length
5 to 8192 (Intel recommends a minimum metaframe
length of 128)
Enable frame generator burst control
On
Enable tx_enh_frame port
On
Enable tx_enh_frame_diag_status port
On
Enable tx_enh_frame_burst_en port
On
Table 81.
Interlaken Frame Synchronizer Parameters
Parameter
Value
Enable Interlaken frame synchronizer
On
Frame synchronizer metaframe length
5 to 8192 (Intel recommends a minimum metaframe
length of 128)
Enable rx_enh_frame port
On
Enable rx_enh_frame_lock port
On / Off
Enable rx_enh_frame_diag_status port
On / Off
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Table 82.
Interlaken CRC-32 Generator and Checker Parameters
Parameter
Value
Enable Interlaken TX CRC-32 generator
On
Enable Interlaken TX CRC-32 generator error
insertion
On / Off
Enable Interlaken RX CRC-32 checker
On
Enable rx_enh_crc32_err port
On / Off
Table 83.
Scrambler and Descrambler Parameters
Parameter
Value
Enable TX scrambler (10GBASE-R / Interlaken)
On
TX scrambler seed (10GBASE-R / Interlaken)
0x1 to 0x3FFFFFFFFFFFFFF
Enable RX descrambler (10GBASE-R / Interlaken)
On
Table 84.
Interlaken Disparity Generator and Checker Parameters
Parameter
Value
Enable Interlaken TX disparity generator
On
Enable Interlaken RX disparity checker
On
Enable Interlaken TX random disparity bit
On / Off
Table 85.
Block Sync Parameters
Parameter
Value
Enable RX block synchronizer
On
Enable rx_enh_blk_lock port
On / Off
Table 86.
Gearbox Parameters
Parameter
Value
Enable TX data bitslip
Off
Enable TX data polarity inversion
On / Off
Enable RX data bitslip
Off
Enable RX data polarity inversion
On / Off
Enable tx_enh_bitslip port
Off
Enable rx_bitslip port
Off
Table 87.
Dynamic Reconfiguration Parameters
Parameter
Value
Enable dynamic reconfiguration
On / Off
Share reconfiguration interface
On / Off
Enable Altera Debug Master Endpoint
On / Off
continued...
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Parameter
Value
Separate reconfig_waitrequest from the status of
AVMM arbitration with PreSICE
On / Off
Enable capability registers
On / Off
Set user-defined IP indentifier:
0 to 255
Enable control and status registers
On / Off
Enable prbs soft accumulators
On / Off
Table 88.
Configuration Files Parameters
Parameter
Value
Configuration file prefix
—
Generate SystemVerilog package file
On / Off
Generate C header file
On / Off
Generate MIF (Memory Initialization File)
On / Off
Include PMA analog settings in configuration files
On / Off
Table 89.
Configuration Profiles Parameters
Parameter
Value
Enable multiple reconfiguration profiles
On / Off
Enable embedded reconfiguration streamer
On / Off
Generate reduced reconfiguration files
On / Off
Number of reconfiguration profiles
1 to 8
Selected reconfiguration profile
1 to 7
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
2.6 Ethernet
The Ethernet standard comprises many different PHY standards with variations in
signal transmission medium and data rates. The 1G/10GbE and 10GBASE-KR PHY IP
Core enables Ethernet connectivity at 1 Gbps and 10 Gbps over backplanes. The
10GBASE-KR PHY IP is also known as the Backplane Ethernet PHY IP. It includes link
training and auto negotiation to support the IEEE Backplane Ethernet standard.
Transceiver Configuration Rule/IP
Data Rate
1G
•
•
Gigabit Ethernet
Gigabit Ethernet 1588
10G
•
•
•
•
10GBASE-R
10GBASE-R 1588
10GBASE-R with KR FEC
10GBASE-KR PHY IP
1G/10G
1G/10G Ethernet PHY IP
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2.6.1 Gigabit Ethernet (GbE) and GbE with IEEE 1588v2
Gigabit Ethernet (GbE) is a high-speed local area network technology that provides
data transfer rates of about 1 Gbps. GbE builds on top of the ethernet protocol, but
increases speed tenfold over Fast Ethernet. IEEE 802.3 defines GbE as an intermediate
(or transition) layer that interfaces various physical media with the media access
control (MAC) in a Gigabit Ethernet system. Gigabit Ethernet PHY shields the MAC
layer from the specific nature of the underlying medium and is divided into three sublayers shown in the following figure.
Figure 42.
GbE PHY Connection to IEEE 802.3 MAC and RS
LAN
CSMA/CD
LAYERS
Higher Layers
OSI
Reference
Model
Layers
LLC (Logical Link Control)
or other MAC Client
MAC Control (Optional)
Media Access Control (MAC)
Application
Reconciliation
Presentation
RECONCILIATION
Session
GMII
Transport
PCS
PMA
Network
PMD
Data Link
Physical
MDI
Medium
1 Gbps
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PHY
Sublayers
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Figure 43.
Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with
IEEE 1588v2
Transmitter Standard PCS
Transmitter PMA
Byte Serializer (3)
8B/10B Encoder
8
TX
FIFO (1)
TX Bit Slip
Serializer
tx_serial_data
10
FPGA
Fabric
PRBS
Generator
625 MHz
125 MHz
tx_coreclkin
tx_clkout
125 MHz
/2
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
rx_clkout
8
RX
FIFO (1)
Byte
Deserializer (4)
8B/10B Decoder
125 MHz
Parallel Clock
(From Clock
Divider)
Rate Match FIFO (2)
Parallel Clock
(Recovered)
Word Aligner
Deserializer
CDR
rx_serial_data
10
rx_coreclkin
125 MHz
tx_clkout
rx_clkout or
tx_clkout
/2
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB) (5)
625 MHz
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Serial Clock
Notes:
1. This block is set in low latency mode for GbE and register_fifo mode for GbE with IEEE 1588v2.
2. The rate match FIFO of the hard PCS is disabled for GbE with IEEE 1588v2 because it is not able to acheive deterministic latency. It is also disabled for Triple-speed Ethernet (TSE) configurations that require an auto-negotiation sequency.
The insertion/deletion operation could break the auto-negotiation functionality due to the rate matching of different frequency PPM scenarios.The soft rate match FIFO is constructed in the GbE Serial Gigabit Media Independent Interface
(SGMII) IP core.
3. The byte serializer can be enabled or disabled.
4. The byte deserializer can be enabled or disabled.
5. The CGB is in the Native PHY.
Note:
The Native PHY only supports basic PCS functions. The Native PHY does not support
auto-negotiation state machine, collision-detect, and carrier-sense. If required, you
must implement these functions in the FPGA fabric or external circuits.
GbE with IEEE 1588v2
GbE with IEEE 1588v2 provides a standard method to synchronize devices on a
network with submicrosecond precision. To improve performance, the protocol
synchronizes slave clocks to a master clock so that events and time stamps are
synchronized in all devices. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
The TX FIFO and RX FIFO are set to register_fifo mode for GbE with IEEE 1588v2.
Related Links
Triple-Speed Ethernet IP Function User Guide.
For more information about the IEEE 1588v2 implementation in GbE PHY and MAC,
and design examples.
2.6.1.1 8B/10B Encoding for GbE, GbE with IEEE 1588v2
The 8B/10B encoder clocks 8-bit data and 1-bit control identifiers from the transmitter
phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded
data is sent to the PMA.
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The IEEE 802.3 specification requires GbE to transmit Idle ordered sets (/I/)
continuously and repetitively whenever the gigabit media-independent interface
(GMII) is Idle. This transmission ensures that the receiver maintains bit and word
synchronization whenever there is no active data to be transmitted.
For the GbE protocol, the transmitter replaces any /Dx.y/ following a /K28.5/ comma
with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on
the current running disparity. The exception is when the data following the /K28.5/ is /
D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before
the /K28.5/ is positive, an /I1/ ordered set is generated. If the running disparity is
negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the
opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the
same as the beginning running disparity immediately preceding transmission of the
Idle code. This sequence ensures a negative running disparity at the end of an Idle
ordered set. A /Kx.y/ following a /K28.5/ does not get replaced.
Note:
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for I1 and I2
ordered sets). D21.5 (/C1/) is not replaced.
Figure 44.
Idle Ordered-Set Generation Example
Clock (i)
tx_datain (i)
tx_dataout (o)
K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
K28.5
D21.5
Dx.y
Dx.y
K28.5
D5.6
K28.5
D16.2
K28.5
D16.2
K28.5
D21.5
Ordered Set (o)
/I1/
/I2/
/I2/
/C1/
Legend:
(i) = Input signal
(o) = Output signal
Related Links
8B/10B Encoder on page 466
2.6.1.1.1 Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
After deassertion of tx_digitalreset, the transmitters automatically transmit at
least three /K28.5/ comma code groups before transmitting user data on the
tx_parallel_data port. This transmission could affect the synchronization state
machine behavior at the receiver.
Depending on when you start transmitting the synchronization sequence, there could
be an even or odd number of /Dx.y/ code groups transmitted between the last of the
three automatically sent /K28.5/ code groups and the first /K28.5/ code group of the
synchronization sequence. If there is an even number of /Dx.y/code groups received
between these two /K28.5/ code groups, the first /K28.5/ code group of the
synchronization sequence begins at an odd code group boundary. The synchronization
state machine treats this as an error condition and goes into the loss of
synchronization state.
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Figure 45.
Reset Condition
n
n+1
n+2
n+3
n+4
K28.5
Dx.y
Dx.y
K28.5
Dx.y
clock
tx_digitalreset
tx_parallel_data
K28.5
xxx
K28.5
K28.5
K28.5
Dx.y
K28.5
Dx.y
User transmitted synchronization sequence
Automatically transmitted /K28.5/
User transmitted data
2.6.1.2 Word Alignment for GbE, GbE with IEEE 1588v2
The word aligner for the GbE and GbE with IEEE 1588v2 protocols is configured in
automatic synchronization state machine mode. The software automatically configures
the synchronization state machine to indicate synchronization when the receiver
receives three consecutive synchronization ordered sets. A synchronization ordered
set is a /K28.5/ code group followed by an odd number of valid /Dx.y/ code groups.
The fastest way for the receiver to achieve synchronization is to receive three
continuous {/K28.5/, /Dx.y/} ordered sets.
The GbE PHY IP core signals receiver synchronization status on the rx_syncstatus
port of each channel. A high on the rx_syncstatus port indicates that the lane is
synchronized; a low on the rx_syncstatus port indicates that the lane has fallen out
of synchronization. The receiver loses synchronization when it detects three invalid
code groups separated by less than three valid code groups or when it is reset.
Table 90.
Synchronization State Machine Parameter Settings for GbE
Synchronization State Machine Parameter
Setting
Number of word alignment patterns to achieve sync
3
Number of invalid data words to lose sync
3
Number of valid data words to decrement error count
3
The following figure shows rx_syncstatus high when three consecutive ordered sets
are sent through rx_parallel_data.
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Figure 46.
rx_syncstatus High
Three Consecutive Ordered Sets Received to Achieve Synchronization
rx_parallel_data
bc
c5
bc
50
bc
50
8c
8d
00
8c
8d
rx_datak
rx_syncstatus
rx_patterndetect
rx_disperr
rx_errdetect
Related Links
Word Aligner on page 469
2.6.1.3 8B/10B Decoding for GbE, GbE with IEEE 1588v2
The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data
value and 1-bit control value as output.
Figure 47.
Decoding for GbE
Dx.y(0x8d), Dx.y(0xa4), K28.5(0xbc), and Dx.y(0x50) are received at rx_parallel_data. /K28.5/ is set as
the word alignment pattern. rx_patterndetect goes high whenever it detects /K28.5/(0xbc). rx_datak is
high when bc is received, indicating that the decoded word is a control word. Otherwise, rx_datak is low.
rx_runningdisp is high for 0x8d, indicating that the decoded word has negative disparity and 0xa4 has
positive disparity.
rx_datak
rx_parallel_data 8d
a4
bc
50
8d
rx_patterndetect
rx_disperr
rx_errdetect
rx_runningdisp
Related Links
8B/10B Decoder on page 476
Intel® Arria® 10 Transceiver PHY User Guide
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a4
bc
50
8d
a4
bc
50
8d
a4
bc
50
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2.6.1.4 Rate Match FIFO for GbE
The rate match FIFO compensates frequency Part-Per-Million (ppm) differences
between the upstream transmitter and the local receiver reference clock up to 125
MHz ± 100 ppm difference.
Note:
200 ppm total is only true if calculated as (125 MHz + 100 ppm) - (125 MHz - 100
ppm) = 200 ppm. By contrast, (125 MHz + 0 ppm) - (125 MHz - 200 ppm) is out of
specification.
The GbE protocol requires the transmitter to send idle ordered sets /I1/ (/K28.5/
D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps (IPG) adhering to the rules
listed in the IEEE 802.3-2008 specification.
The rate match operation begins after the synchronization state machine in the word
aligner indicates synchronization is acquired by driving the rx_syncstatus signal
high. The rate matcher deletes or inserts both symbols /K28.5/ and /D16.2/ of
the /I2/ ordered sets as a pair in the operation to prevent the rate match FIFO from
overflowing or underflowing. The rate match operation can insert or delete as
many /I2/ ordered sets as necessary.
The following figure shows a rate match deletion operation example where three
symbols must be deleted. Because the rate match FIFO can only delete /I2/ ordered
sets, it deletes two /I2/ ordered sets (four symbols deleted).
Figure 48.
Rate Match FIFO Deletion
/I2/ SKP Symbol Deleted
datain
dataout
F irst /I2 / Ordered S et
S econd /I2 / Ordered S et
Third /I2 / Ordered S et
Dx .y
K 28 .5
D 16 .2
K 28 .5
K 28 .5
Dx .y
K 28 .5
D 16 .2
Dx .y
D 16 .2
D 16 .2
Dx .y
The following figure shows an example of rate match FIFO insertion in the case where
one symbol must be inserted. Because the rate match FIFO can only insert /I2/
ordered sets, it inserts one /I2/ ordered set (two symbols inserted).
Figure 49.
Rate Match FIFO Insertion
dataout
datain
First /I2/ Ordered Set
Second /I2/ Ordered Set
Dx .y
K 28 .5
D 16 .2
K 28 .5
D 16 .2
Dx .y
K 28 .5
D 16 .2
K 28 .5
D 16 .2
/I2/ SKP Symbol Inserted
K 28 .5
D 16 .2
Dx .y
rx_std_rmfifo_full and rx_std_rmfifo_empty are forwarded to the FPGA
fabric to indicate rate match FIFO full and empty conditions.
The rate match FIFO does not delete code groups to overcome a FIFO full condition. It
asserts the rx_std_rmfifo_full flag for at least two recovered clock cycles to
indicate rate match FIFO full. The following figure shows the rate match FIFO full
condition when the write pointer is faster than the read pointer.
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Figure 50.
Rate Match FIFO Full Condition
tx_parallel_data
2D
2E
2F
30
31
32
33
34
35
36
37
38
rx_parallel_data
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
rx_std_rmfifo_full
The rx_std_rmfifo_full status flag indicates
that the FIFO is full at this time
The rate match FIFO does not insert code groups to overcome the FIFO empty
condition. It asserts the rx_std_rmfifo_empty flag for at least two recovered clock
cycles to indicate that the rate match FIFO is empty. The following figure shows the
rate match FIFO empty condition when the read pointer is faster than the write
pointer.
Figure 51.
Rate Match FIFO Empty Condition
tx_parallel_data
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
rx_parallel_data
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
00
01
02
rx_std_rmfifo_empty
The rx_std_rmfifo_empty status flag indicates
that the FIFO is empty at this time
In the case of rate match FIFO full and empty conditions, you must assert the
rx_digitalreset signal to reset the receiver PCS blocks.
Related Links
Rate Match FIFO on page 475
2.6.1.5 How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing the GbE protocol.
1.
Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
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Refer to Select and Instantiate the PHY IP Core on page 31.
2. Select GbE or GbE 1588 from the Transceiver configuration rules list located
under Datapath Options, depending on which protocol you are implementing.
Figure 52.
3.
Use the parameter values in the tables in Native PHY IP Parameter Settings for
GbE and GbE with IEEE 1588v2 on page 118 as a starting point. Or, you can use
the protocol presets described in Transceiver Native PHY Presets. Use the
GIGE-1.25 Gbps preset for GbE, and the GIGE-1.25 Gbps 1588 preset for GbE
1588. You can then modify the setting to meet your specific requirements.
4.
Click Generate to generate the Native PHY IP core top-level RTL file.
Signals and Ports for Native PHY IP Configured for GbE or GbE with IEEE
1588v2
Generating the IP core creates signals and ports based on your parameter settings.
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers
TX Standard PCS
TX PMA
tx_serial_data
tx_serial_clk0
(from TX PLL)
Serializer
10
Local Clock
Generation
Block
Deserializer
tx_digitalreset
gmii_tx_ctrl
gmii_tx_d[7:0]
gmii_tx_clk
tx_clkout
tx_analogreset
rx_analogreset
RX PMA
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
reconfig_reset
reconfig_clk
reconfig_avmm
RX Standard PCS
10
CDR
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus
unused_rx_parallel_data[111:0]
rx_digitalreset
gmii_rx_ctrl
gmii_rx_d[7:0]
gmii_rx_clk
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
Note:
1. rx_rmfifostatus is not available in the GbE with 1588 configuration.
5.
6.
Instantiate and configure your PLL.
Instantiate a transceiver reset controller.
You can use your own reset controller or use the Native PHY Reset Controller IP
core.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in the figure below to connect the ports.
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Figure 53.
Connection Guidelines for a GbE/GbE with IEEE 1588v2 PHY Design
tx_parallel_data
reset
pll_ref_clk
Pattern
Generator
pll_powerdown (2)
rx_ready
Reset
Controller
tx_analogreset
rx_digitalreset
rx_analogreset
tx_ready
rx_is_lockedtodata
rx_cal_busy
clk
reset
pll_cal_busy (1)
reset
tx_serial_data
rx_serial_data
tx_clkout
tx_digitalreset
pll_locked
PLL
tx_datak
rx_cdr_refclk
Arria 10
Transceiver
Native
PHY
tx_cal_busy
rx_parallel_data
Pattern
Checker
rx_datak
rx_clkout
tx_serial_clk
Note:
1. The pll_cal_busy signal is not available when using the CMU PLL.
2. The pll_powerdown signal is not available separately for user control when using the fPLL.
The reset controller handles PLL reset for the fPLL.
8.
Simulate your design to verify its functionality.
Related Links
•
Arria 10 Standard PCS Architecture on page 463
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Standard PCS Ports on page 84
Port definitions for the Transceiver Native PHY Standard Datapath
2.6.1.6 Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
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Table 91.
General and Datapath Options
The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general
and datapath options to customize the transceiver.
Parameter
Value
Message level for rule violations
error
warning
Transceiver configuration rules
GbE (for GbE)
GbE 1588 (for GbE with IEEE 1588v2)
TX/RX Duplex
TX Simplex
RX Simplex
Transceiver mode
Number of data channels
1 to 96
1250 Mbps
Data rate
Enable datapath and interface reconfiguration
On/Off
Enable simplified data interface
On/Off
Table 92.
TX PMA Parameters
Parameter
TX channel bonding mode
Value
Not bonded
TX local clock division factor
1, 2, 4, 8
Number of TX PLL clock inputs per channel
1, 2, 3, 4
Initial TX PLL clock input selection
0 to 3
Enable tx_pma_clkout port
On/Off
Enable tx_pma_div_clkout port
On/Off
tx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port
On/Off
Enable tx_pma_qpipullup port (QPI)
On/Off
Enable tx_pma_qpipulldn port (QPI)
On/Off
Enable tx_pma_txdetectrx port (QPI)
On/Off
Enable tx_pma_rxfound port (QPI)
On/Off
Enable rx_seriallpbken port
On/Off
Table 93.
RX PMA Parameters
Parameter
Value
Number of CDR reference Clocks
1 to 5
Selected CDR reference clock
0 to 4
Selected CDR reference clock frequency
Select legal range defined by the Quartus Prime
software
PPM detector threshold
100, 300, 500, 1000
CTLE adaptation mode
manual
continued...
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Parameter
DFE adapatation mode
Value
disabled
Number of fixed dfe taps
N/A
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
On/Off
On/Off
rx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 66
Enable rx_pma_iqtxrx_clkout port
On/Off
Enable rx_pma_clkslip port
On/Off
Enable rx_pma_qpipulldn port (QPI)
Off
Enable rx_is_lockedtodata port
On/Off
Enable rx_is_lockedtoref port
On/Off
Enable rx_set_locktodata and rx_set_locktoref ports
On/Off
Enable rx_seriallpbken port
On/Off
Enable PRBS verifier control and status ports
On/Off
Table 94.
Standard PCS Parameters
Parameters
Standard PCS / PMA interface width
Value
10
FPGA fabric / Standard TX PCS interface width
8
FPGA fabric / Standard RX PCS interface width
8
Enable Standard PCS low latency mode
Off
TX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
RX FIFO mode
low latency (for GbE)
register_fifo (for GbE with IEEE 1588v2)
Enable tx_std_pcfifo_full port
On/Off
Enable tx_std_pcfifo_empty port
On/Off
Enable rx_std_pcfifo_full port
On/Off
Enable rx_std_pcfifo_empty port
On/Off
TX byte serializer mode
Disabled
RX byte deserializer mode
Disabled
Enable TX 8B/10B encoder
On
Enable TX 8B/10B disparity control
Enable RX 8B/10B decoder
RX rate match FIFO mode
RX rate match insert / delete -ve pattern (hex)
On/Off
On
gige (for GbE)
disabled (for GbE with IEEE 1588v2)
0x000ab683 (/K28.5/D2.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
continued...
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Parameters
RX rate match insert / delete +ve pattern (hex)
Value
0x000a257c (/K28.5/D16.2/) (for GbE)
0x00000000 (disabled for GbE with IEEE
1588v2)
Enable rx_std_rmfifo_full port
On/Off
(option disabled for GbE with IEEE 1588v2)
Enable rx_std_rmfifo_empty port
On/Off
(option disabled for GbE with IEEE 1588v2)
PCI Express Gen3 rate match FIFO mode
Bypass
Enable TX bit slip
Off
Enable tx_std_bitslipboundarysel port
RX word aligner mode
On/Off
Synchronous state machine
RX word aligner pattern length
7
RX word aligner pattern (hex)
0x000000000000007c (Comma) (for 7-bit
aligner pattern length), 0x000000000000017c
(/K28.5/) (for 10-bit aligner pattern length)
Number of word alignment patterns to achieve sync
3
Number of invalid data words to lose sync
3
Number of valid data words to decrement error count
3
Enable fast sync status reporting for deterministic latency SM
On/Off
Enable rx_std_wa_patternalign port
Off
Enable rx_std_wa_a1a2size port
Off
Enable rx_std_bitslipboundarysel port
Off
Enable rx_bitslip port
Off
Enable TX bit reversal
Off
Enable TX byte reversal
Off
Enable TX polarity inversion
On/Off
Enable tx_polinv port
On/Off
Enable RX bit reversal
Off
Enable rx_std_bitrev_ena port
Off
Enable RX byte reversal
Off
Enable rx_std_byterev_ena port
Off
Enable RX polarity inversion
On/Off
Enable rx_polinv port
On/Off
Enable rx_std_signaldetect port
On/Off
All options under PCIe Ports
Off
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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2.6.2 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with
FEC Variants
10GBASE-R PHY is the Ethernet-specific physical layer running at a 10.3125-Gbps
data rate as defined in Clause 49 of the IEEE 802.3-2008 specification. Arria 10
transceivers can implement 10GBASE-R variants like 10GBASE-R with IEEE 1588v2,
and with forward error correction (FEC).
The 10GBASE-R parallel data interface is the 10 Gigabit Media Independent Interface
(XGMII) that interfaces with the Media Access Control (MAC), which has the optional
Reconciliation Sub-layer (RS).
Figure 54.
10GBASE-R PHY as Part of the IEEE802.3-2008 Open System Interconnection
(OSI)
LAN
CSMA/CD
LAYERS
Higher Layers
Logical Link Control (LLC) or other MAC Client
MAC Control (Optional)
OSI Reference
Model Layers
Media Access Control (MAC)
Application
Reconciliation
Presentation
XGMII
Session
10GBASE-R
PHY
Transport
10GBASE-R PCS
10GBASE-R FEC (Optional)
Network
PMA
Data Link
PMD
MDI
Physical
To 10GBASE-R PHY
(Point-to-Point Link)
Medium
10GBASE-R
(PCS, FEC, PMA, PMD)
Legend
MDI: Medium Dependent Interface
PCS: Physical Coding Sublayer
PHY: Physical Layer Device
PMA: Physical Medium Attachment
PMD: Physical Medium Dependent
FEC: Forwarad Error Correction
XGMII: 10 GB Media Independent Interface
10GBASE-R is a single-channel protocol that runs independently. You can configure
the transceivers to implement 10GBASE-R PHY functionality by using the presets of
the Native PHY IP. The 10GBASE-R PHY IP is compatible with the 10-Gbps Ethernet
MAC Megacore Function. The complete PCS and PHY solutions can be used to interface
with a third-party PHY MAC layer as well.
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The following 10GBASE-R variants area available from presets:
•
10GBASE-R
•
10GBASE-R Low Latency
•
10GBASE-R Register Mode
•
10GBASE-R w/ KR-FEC
Intel recommends that you use the presets for selecting the suitable 10GBASE-R
variants directly if you are configuring through the Native PHY IP core.
Transceiver Channel Datapath and Clocking for 10GBASE-R
Transmitter Enhanced PCS
FPGA
Fabric
TX
Data &
Control
Enhanced PCS
TX FIFO
(3)
Interlaken
Frame Generator
64
Interlaken
CRC32 Generator
66
64 + 8
PRP
Generator
Parallel Clock
tx_coreclkin
PRBS
Generator
64B/66B Encoder
and TX SM
Scrambler
(self sync) mode
Interlaken
Disparity Generator
TX
Gearbox
Serializer
tx_serial_data
40
10.3125 Gbps
@ 156.25 MHz
from XGMII
rx_coreclkin
Transmitter PMA
@ 156.25 MHz
from XGMII
tx_clkout
Transcode
Encoder
KR FEC
Encoder
KR FEC
TX Gearbox
KR FEC
Scrambler
@ 257.8125 MHz (2)
tx_pma_div_clkout
Receiver Enhanced PCS
PRBS
Verifier
64
Enhanced PCS
RX FIFO
(4)
RX
Data &
Control
Interlaken
CRC32 Checker
Interlaken
Frame Sync
Descrambler
Interlaken
Disparity Checker
66
Block
Synchronizer
RX
Gearbox
CDR
40
64B/66B Decoder
and RX SM
rx_pma_div_clkout
Deserializer
rx_serial_data
Receiver PMA
5156.25 MHz (data rate/2) (1)
64 + 8
PRP
Verifier
Parallel Clock
rx_clkout
10GBASE-R
BER Checker
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
@ 257.8125 MHz (2)
KR FEC
Block Sync
Figure 55.
Clock Generation Block (CGB)
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
3. This block is in Phase Compensation mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
4. This block is in 10GBASE-R mode for the 10GBASE-R configuration and register mode for the 10GBASE-R with 1588 configuration.
10GBASE-R with IEEE 1588v2
When choosing the 10GBASE-R PHY with IEEE 1588v2 mode preset, the hard TX and
RX FIFO are set to register mode. The output clock frequency of tx_clkout and
rx_clkout to the FPGA fabric is based on the PCS-PMA interface width. For example,
if the PCS-PMA interface is 40-bit, tx_clkout and rx_clkout run at 10.3125
Gbps/40-bit = 257.8125 MHz.
The 10GBASE-R PHY with IEEE 1588v2 creates the soft TX phase compensation FIFO
and the RX clock compensation FIFO in the FPGA core so that the effective XGMII data
is running at 156.25 MHz interfacing with the MAC layer.
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The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10
transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP
is used for precise synchronization of clocks in applications such as:
•
Distributed systems in telecommunications
•
Power generation and distribution
•
Industrial automation
•
Robotics
•
Data acquisition
•
Test equipment
•
Measurement
The protocol is applicable to systems communicating by local area networks including,
but not limited to, Ethernet. The protocol enables heterogeneous systems that include
clocks of various inherent precision, resolution, and stability to synchronize to a
grandmaster clock.
Figure 56.
Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2
Transmitter PMA
Transmitter Enhanced PCS
FPGA
Fabric
PRBS
Generator
Soft Phase
Compensation
FIFO
64 (data) + 8 (control)
tx_coreclkin
Register Mode
Interlaken
Frame Generator
64
Interlaken
CRC32 Generator
66
64B/66B Encoder
and TX SM
Scrambler
(self sync) mode
Interlaken
Disparity Generator
TX
Gearbox
Serializer
tx_serial_data
40
10.3125 Gbps
TX XGMII
@ 156.25 MHz
PRP
Generator
Parallel Clock
tx_clkout
Transcode
Encoder
KR FEC
Encoder
KR FEC
TX Gearbox
KR FEC
Scrambler
@ 257.8125 MHz (2)
tx_pma_div_clkout
Receiver Enhanced PCS
Register Mode
Soft Clock
Compensation
FIFO
PRP
Verifier
Parallel Clock
rx_clkout
10GBASE-R
BER Checker
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
@ 257.8125 MHz (2)
Clock Generation Block (CGB)
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Notes:
1. Value based on the clock division factor chosen.
2. Value calculated as data rate / PCS-PMA interface width.
10GBASE-R with FEC
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64 (data) + 8 (control)
rx_coreclkin
PRBS
Verifier
64
Interlaken
CRC32 Checker
Interlaken
Frame Sync
Descrambler
Interlaken
Disparity Checker
66
Block
Synchronizer
RX
Gearbox
CDR
40
64B/66B Decoder
and RX SM
rx_pma_div_clkout
Deserializer
rx_serial_data
5156.25 MHz (data rate/2) (1)
Receiver PMA
RX XGMII
@ 156.25 MHz
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Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR
PHY. This provides a coding gain to increase the link budget and BER performance on
a broader set of backplane channels as defined in Clause 69. It provides additional
margin to account for variations in manufacturing and environment conditions. The
additional TX FEC sublayer:
•
Receives data from the TX PCS
•
Transcodes 64b/66b words
•
Performs encoding/framing
•
Scrambles and sends the FEC data to the PMA
The RX FEC sublayer:
•
Receives data from the PMA
•
Performs descrambling
•
Achieves FEC framing synchronization
•
Decodes and corrects data where necessary and possible
•
Recodes 64b/66b words and sends the data to the PCS
The 10GBASE-R with KR FEC protocol is a KR FEC sublayer placed between the PCS
and PMA sublayers of the 10GBASE-R physical layer.
Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC
FPGA
Fabric
tx_coreclkin
@ 156.25 MHz
from XGMII
KR FEC
TX Gearbox
Transcode
Encoder
tx_pma_div_clkout
Receiver Enhanced PCS
Receiver PMA
rx_rcvd_clk
PRBS
Verifier
rx_pma_clk
Enhanced PCS
RX FIFO
(5)
RX
Data &
Control
Interlaken
CRC32 Checker
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler
Block
Synchronizer
RX
Gearbox
64
Interlaken
Disparity Checker
rx_pma_div_clkout
Deserializer
CDR
@ 156.25 MHz
from XGMII
tx_clkout
KR FEC
rx_serial_data
Enhanced PCS
TX FIFO
(4)
Parallel Clock (161.1 MHz) (3)
tx_krfec_clk
KR FEC
Encoder
tx_pma_clk
64 + 8
PRP
Generator
KR FEC
Scrambler
tx_hf_clk
TX
Data &
Control
rx_coreclkin
PRBS
Generator
64
Interlaken
Frame Generator
66
Interlaken
CRC32 Generator
Interlaken
Disparity Generator
TX
Gearbox
Serializer
tx_serial_data
64
64B/66B Encoder
and TX SM
Transmitter Enhanced PCS
Scrambler
Transmitter PMA
5156.25 MHz (data rate/2) (1)
64 + 8
PRP
Verifier
rx_krfec_clk
rx_clkout
Parallel Clock (161.1 MHz) (3)
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
10GBASE-R
BER Checker
KR FEC
Block Sync
Figure 57.
KR FEC
tx_serial_clk0
(5156.25 MHz) =
Data rate/2
Clock Generation Block (CGB)
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
ATX PLL
fPLL
CMU PLL
Serial Clock
Input Reference Clock
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate/FPGA fabric - PCS interface width
3. Value is calculated as data rate/PCS-PMA interface width
4. For 10GBASE-R with KR FEC, TX FIFO is in phase compensation mode
5. For 10GBASE-R with KR FEC, RX FIFO is in 10GBASE-R mode
The CMU PLL or the ATX PLLs generate the TX high speed serial clock.
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Figure 58.
Clock Generation and Distribution for 10GBASE-R with FEC Support
Example using a 64-bit PCS-PMA interface width.
10GBASE-R Hard IP Transceiver Channel
TX
64 Bit Data
8 Bit Control
64
TX PCS
TX PMA
161.13 MHz
TX PLL
10.3125 Gbps
Serial
pll_ref_clk
644.53125 MHz
RX
64 Bit Data
8 Bit Control
156.25 MHz
rx_coreclkin
64
RX PCS
161.13 MHz
RX PMA
10.3125 Gbps
Serial
fPLL
8/33
2.6.2.1 The XGMII Clocking Scheme in 10GBASE-R
The XGMII interface, specified by IEEE 802.3-2008, defines the 32-bit data and 4-bit
wide control character. These characters are clocked between the MAC/RS and the PCS
at both the positive and negative edge (double data rate – DDR) of the 156.25 MHz
interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the
IEEE 802.3-2008 specification. Instead, they support a 64-bit data and 8-bit control
single data rate (SDR) interface between the MAC/RS and the PCS.
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Figure 59.
XGMII Interface (DDR) and Transceiver Interface (SDR) for 10GBASE-R
Configurations
XGMII Transfer (DDR)
Interface Clock (156.25) MHz
TXD/RXD[31:0]
D0
D1
D2
D3
D4
D5
D6
TXC/RXC[3:0]
C0
C1
C2
C3
C4
C5
C6
Transceiver Interface (SDR)
Interface Clock (156.25) MHz
Note:
TXD/RXD[63:0]
{D1, D0}
{D3, D2}
{D5, D4}
TXC/RXC[7:0]
{C1, C0}
{C3, C2}
{C5, C4}
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between
the 10GBASE-R PCS and the Ethernet MAC/RS.
The dedicated reference clock input to the variants of the 10GBASE-R PHY can be run
at either 322.265625 MHz or 644.53125 MHz.
For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of
TX phase compensation FIFO (PCS data) and the write clock of TX phase
compensation FIFO (XGMII data in the FPGA fabric). This can be achieved by using the
same reference clock as the transceiver dedicated reference clock input as well as the
reference clock input for a core PLL (fPLL, for example) to produce the XGMII clock.
The same core PLL can be used to drive the RX XGMII data. This is because the RX
clock compensation FIFO is able to handle the frequency PPM difference of ±100 ppm
between RX PCS data driven by the RX recovered clock and RX XGMII data.
Note:
10GBASE-R is the single-channel protocol that runs independently. Therefore Intel
recommends that you use the presets for selecting the suitable 10GBASE-R variants
directly. If it is being configured through the Native PHY IP, the channel bonding option
should be disabled. Enabling the channel bonding for multiple channels could degrade
the link performance in terms of TX jitter eye and RX jitter tolerance.
2.6.2.1.1 TX FIFO and RX FIFO
In 10GBASE-R configuration, the TX FIFO behaves as a phase compensation FIFO and
the RX FIFO behaves as a clock compensation FIFO.
In 10GBASE-R with 1588 configuration, both the TX FIFO and the RX FIFO are used in
register mode. The TX phase compensation FIFO and the RX clock compensation FIFO
are constructed in the FPGA fabric by the PHY IP automatically.
In 10GBASE-R with KR FEC configuration, you use the TX FIFO in phase compensation
mode and the RX FIFO behaves as a clock compensation FIFO.
Related Links
Arria 10 Enhanced PCS Architecture on page 445
For more information about the Enhanced PCS Architecture
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2.6.2.2 How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and
10GBASE-R with FEC in Arria 10 Transceivers
You should be familiar with the 10GBASE-R and PMA architecture, PLL architecture,
and the reset controller before implementing the 10GBASE-R, 10GBASE-R with IEEE
1588v2, or 10GBASE-R with FEC Transceiver Configuration Rules.
You must design your own MAC and other layers in the FPGA to implement the
10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver
Configuration Rule using the Native PHY IP.
1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 31 for more details.
2. Select 10GBASE-R, 10GBASE-R 1588, or 10GBASE-R with KR FEC from the
Transceiver configuration rule list located under Datapath Options,
depending on which protocol you are implementing.
3. Use the parameter values in the tables in Transceiver Native PHY Parameters for
the 10GBASE-R Protocol as a starting point. Or, you can use the protocol presets
described in Transceiver Native PHY Presets. Select 10GBASE-R Register Mode
for 10GBASE-R with IEEE 1588v2. You can then modify the settings to meet
your specific requirements.
4. Click Generate to generate the Native PHY IP core RTL file.
Figure 60.
Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with
IEEE 1588v2, and 10GBASE-R with FEC
Generating the IP core creates signals and ports based on your parameter settings.
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
Nios Hard
Calibration IP
Reconfiguration
Registers
TX PMA
tx_serial_data
tx_serial_clk0 (from TX PLL)
Serializer
TX Enhanced PCS
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_fifo_flags
Clock
Generation
Block
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digitalreset
xgmii_tx_c[7:0] (2)
xgmii_tx_d[63:0] (2)
xgmii_tx_clk
1’b1 (1)
tx_analogreset
rx_analogreset
RX PMA
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
CDR
Deserializer
RX Enhanced PCS
rx_clkout
rx_coreclkin
rx_enh_blk_lock
rx_enh_highber
rx_fifo_flags
rx_parallel_data[127:0]
rx_control[19:0]
Notes:
1. For 10GBASE-R with 1588 configurations, this signal is user-controlled.
2. For 10GBASE-R with 1588 configurations, this signal is connected from the output of TX FIFO in the FPGA fabric.
5.
Instantiate and configure your PLL.
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rx_digitalreset
xgmii_rx_clk
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6.
Create a transceiver reset controller. You can use your own reset controller or use
the Arria 10 Transceiver Native PHY Reset Controller IP.
7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller.
Figure 61.
Connection Guidelines for a 10GBASE-R or 10GBASE-R with FEC PHY Design
Reset
Controller
PLL IP
To MAC/RS
through XGMII
Interface
64d + 8c
Arria 10 Transceiver
Native PHY
Figure 62.
Medium
Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
To MAC/RS
through XGMII
Interface
PLL IP
64d + 8c
64d + 8c
8.
FIFO in the
FPGA core
for TX
Reset
Controller
Arria 10 Transceiver
Native PHY
Medium
FIFO in the
FPGA core
for RX
Simulate your design to verify its functionality.
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Enhanced PCS Ports on page 74
For detailed information about the available ports in the 10GBASE-R 1588
protocol.
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2.6.2.3 Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE
1588v2, and 10GBASE-R with FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 95.
General and Datapath Parameters
The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath
options to customize the transceiver.
Parameter
Range
Message level for rule violations
error, warning
Transceiver Configuration Rule
10GBASE-R
10GBASE-R 1588
10GBASE-R with KR FEC
Transceiver mode
TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels
1 to 96
Data rate
10312.5 Mbps
Enable datapath and interface reconfiguration
Off
Enable simplified data interface
On
Off
Table 96.
TX PMA Parameters
Parameter
Range
TX channel bonding mode
Not bonded
TX local clock division factor
1, 2, 4, 8
Number of TX PLL clock inputs per channel
1, 2, 3, 4
Initial TX PLL clock input selection
0
Table 97.
RX PMA Parameters
Parameter
Range
Number of CDR reference clocks
1 to 5
Selected CDR reference clock
0 to 4
Selected CDR reference clock frequency
322.265625 MHz and 644.53125 MHz
PPM detector threshold
100, 300, 500, 1000
CTLE adaptation mode
manual
DFE adaptation mode
adaptation enabled, manual, disabled
Number of fixed DFE taps
3, 7, 11
Table 98.
Enhanced PCS Parameters
Parameter
Enhanced PCS/PMA interface width
Range
32, 40, 64
continued...
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Parameter
Range
Note: 10GBASE-R with KR-FEC allows 64 only.
FPGA fabric/Enhanced PCS interface width
66
Enable Enhanced PCS low latency mode
On
Off
Enable RX/TX FIFO double-width mode
Off
TX FIFO mode
•
•
TX FIFO partially full threshold
11
TX FIFO partially empty threshold
2
RX FIFO mode
•
•
RX FIFO partially full threshold
23
RX FIFO partially empty threshold
2
Table 99.
Phase Compensation (10GBASE-R and 10GBASE-R
with KR FEC)
Register or Fast register (10GBASE-R with 1588)
10GBASE-R (10GBASE-R and 10GBASE-R with KR FEC)
Register (10GBASE-R with 1588)
64B/66B Encoder and Decoder Parameters
Parameter
Range
Enable TX 64B/66B encoder
On
Enable RX 64B/66B decoder
On
Enable TX sync header error insertion
On
Off
Table 100.
Scrambler and Descrambler Parameters
Parameter
Range
Enable TX scrambler (10GBASE-R / Interlaken)
On
TX scrambler seed (10GBASE-R / Interlaken)
0x03ffffffffffffff
Enable RX descrambler (10GBASE-R / Interlaken)
On
Table 101.
Block Sync Parameters
Parameter
Range
Enable RX block synchronizer
On
Enable rx_enh_blk_lock port
On
Off
Table 102.
Gearbox Parameters
Parameter
Range
Enable TX data polarity inversion
On
Off
Enable RX data polarity inversion
On
Off
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Table 103.
Dynamic Reconfiguration Parameters
Parameter
Range
Enable dynamic reconfiguration
On
Off
Share reconfiguration interface
On
Off
Enable Altera Debug Master Endpoint
On
Off
De-couple reconfig_waitrequest from calibration
On
Off
Table 104.
Configuration Files Parameters
Parameter
Range
Configuration file prefix
—
Generate SystemVerilog package file
On
Off
Generate C header file
On
Off
Generate MIF (Memory Initialization File)
On
Off
Table 105.
Generation Options Parameters
Parameter
Range
Generate parameter documentation file
On
Off
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
2.6.2.4 Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2
Transceiver Configurations
Figure 63.
High BER
This figure shows the rx_enh_highber status signal going high when there are errors on the
rx_parallel_data output.
rx_parallel_data
rx_control
tx_parallel_data
tx_control
rx_enh_highber
1122334455667788h
Intel® Arria® 10 Transceiver PHY User Guide
132
1122324455667788h 112233405566F788h
00h
1122334455667788h
00h
0h
1122334455667788h
1h
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Figure 64.
Block Lock Assertion
This figure shows the assertion on rx_enh_blk_lock signal when the Receiver detects the block delineation.
rx_parallel_data
rx_control
tx_parallel_data
tx_control
rx_enh_highber
rx_ready
rx_enh_block_lock
0100009C0100009Ch
0707070707070707h
11h
FFh
0707070707070707h
FFh
0h
1h
0h
1h
The following figures show Idle insertion and deletion.
Figure 65.
IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Before Insertion
rx_parallel_data[79:0]
FD000000000004AEh
BBBBBB9CDDDDDD9Ch
00000000000000FBh
AAAAAAAAAAAAAAAAh
BBBBBB9CDDDDDD9Ch
0707070707070707h
00000000000000FBh
After Insertion
rx_parallel_data[79:0]
FD000000000004AEh
Idle Inserted
Figure 66.
IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
Before Deletion
00000000000004AEh
rx_parallel_data[79:0] 00000000000004ADh
0707070707FD0000h
000000FB07070707h
After Deletion
rx_parallel_data[79:0]
00000000000004ADh
00000000000004AEh
AAAAAAAA000000FBh
0707070707FD0000h
Idle Deleted
Figure 67.
OS Word Deletion
This figure shows the deletion of Ordered set word in the receiver data stream.
Before Deletion
DDDDDD9CDDDDDD9Ch
00000000000000FBh
rx_parallel_data[79:0] FD000000000004AEh
AAAAAAAAAAAAAAAAh
After Deletion
rx_parallel_data[79:0]
FD000000000004AEh
000000FBDDDDDD9Ch
AAAAAAAA00000000h
00000000AAAAAAAAh
OS Deleted
2.6.3 10GBASE-KR PHY IP Core
The 10GBASE-KR Ethernet PHY IP core supports the following features of Ethernet
standards:
•
Auto negotiation for backplane Ethernet as defined in Clause 73 of the IEEE 802.3
2008 Standard. The 10GBASE-KR Ethernet PHY IP Function can auto negotiate
between 1000BASE-X, 1000BASE-KR , and 1000BASE-KR with FEC.
•
10GBASE-KR Ethernet protocol with link training as defined in Clause 72 of the
IEEE 802.3 2008 Standard. In addition to the link-partner TX tuning as defined in
Clause 72, this PHY also automatically configures the local device RX interface to
achieve less than 10-12 bit error rate (BER) target.
•
Gigabit Media Independent Interface (GMII) to connect PHY with media access
control (MAC) as defined in Clause 35 of the IEEE 802.3 2008 Standard
•
Forward Error Correction (FEC) as defined in Clause 74 of the IEEE 802.3 2008
Standard
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The Backplane Ethernet 10GBASE-KR PHY IP core includes the following new modules
to enable operation over a backplane:
•
Link Training (LT)— The LT mechanism allows the 10GBASE-KR PHY to
automatically configure the link-partner TX PMDs for the lowest Bit Error Rate
(BER). LT is defined in Clause 72 of IEEE Std 802.3ap-2007.
•
Auto negotiation (AN)—The 10GBASE-KR PHY IP core can auto-negotiate between
1000BASE-KX (1GbE) and 10GBASE-KR (10GbE) PHY types. The AN function is
mandatory for Backplane Ethernet. It is defined in Clause 73 of the IEEE Std
802.3ap-2007.
•
Forward Error Correction (FEC)—FEC function is an optional feature defined in
Clause 74 of IEEE 802.3ap-2007. It provides an error detection and correction
mechanism.
Related Links
•
IEEE Std 802.3ap-2008 Standard
•
Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.3.1 10GBASE-KR PHY Release Information
Table 106.
10GBASE-KR PHY Release Information
Item
Description
Version
16.0
Release Date
May 2016
Ordering Codes
IP-10GBASEKRPHY (IP)
IPR-10GBASEKRPHY (Renewal)
Product ID
0106
Vendor ID
6AF7
2.6.3.2 10GBASE-KR PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the IP.
The following table shows the typical expected resource utilization for selected
configurations using the Quartus Prime software v15.1 for Arria 10 devices. The
numbers of ALMs and logic registers are rounded up to the nearest 100.
Table 107.
10GBASE-KR PHY Performance and Resource Utilization
Variant
ALMs
ALUTs
Registers
M20K
10GBASE-KR PHY
2400
3750
3100
1
10GBASE-KR PHY with FEC
2400
3750
3100
1
2.6.3.3 10GBASE-KR Functional Description
The following figure shows the supporting components inside the 10GBASE-KR PHY IP
core.
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Figure 68.
10GBASE-KR PHY IP Core Block Diagram
10GBASE-KR PHY IP
Register
Access
Avalon-MM
Registers
Nios II Sequencer
Interface
HSSI Reconfiguration
Requests
XGMII_TX_CLK
TX_GMII_DATA
TX_XGMII_DATA
8+2
GbE
PCS
Native PHY
1588
FIFO
64 + 8
tx_pld_clk
Auto-Negotiation
Clause 73
Link Training
Clause 72
Nios II LT Interface
40/32
Standard TX PCS
TX PMA
tx_pma_clk
64 + 8
Enhanced TX PCS
32
tx_pld_clk
tx_pma_clk
64 + 8
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
1588
FIFO
Standard RX PCS
rx_pld_clk
rx_pma_clk
40/32
Enhanced RX PCS
rx_pld_clk
XGMII_RX_CLK
RX_GMII_DATA
Soft Logic
Note:
8+2
Hard Logic
GbE
PCS
RX PMA
rx_pma_clk
Divide by 33/1/2
Unused
The 10GBASE-KR PHY IP core does not support backplane applications with IEEE 1588
Precision Time Protocol.
The 10GBASE-KR PHY IP core includes the following components:
Standard and Enhanced PCS Datapaths
The Enhanced PCS and PMA inside the Native PHY are configured to be the 10GBASER PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters for more
details on how these blocks support 1G, 10G protocols and FEC.
Auto Negotiation, IEEE 802.3 Clause 73
The auto negotiation (AN) is needed to synchronize the start time of the link training
on both sides of the link partners. This ensures that the link training can be done
effectively within the 500 ms of the specified timeframe as required.
Link Training (LT), IEEE 802.3 Clause 72
Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72
standard training procedure. This IP includes:
•
training frame lock that is different from the regular 64b/66b frame_lock
•
training frame generation
•
the control channel codec
•
Local Device (LD) coefficient update
•
Link Partner (LP) coefficient generation
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Reconfiguration Block
The Reconfiguration Block performs Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The Avalon-MM master accepts requests from the PMA or PCS
controller. It performs the Read-Modify-Write or Write commands on the Avalon-MM
interface. The PCS controller receives rate change requests from the Sequencer and
translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Eight compile-time configuration modes are supported. The configuration modes
include one set of four with reference clock at 322 MHz and one set of four with
reference clock at 644 MHz. Each set of four consists of all combinations of FEC
sublayer on/off.
Figure 69.
Reconfiguration Block Details
MGMT_CLK
(2)
rcfg_data
rcfg_data
rcfg_data
PCS
Reconfiguration
Interface
rcfg_data
PCS
Controller
(1)
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM
Decoder
PMA Controller
HSSI
Reconfiguration
Requests
Avalon-MM Bus
TX EQ Controller
PMA
Reconfiguration
Interface
DFE Controller
Avalon-MM reconfig_busy Signal
CTLE Controller
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
•
Arria 10 Standard PCS Architecture on page 463
2.6.3.4 Parameterizing the 10GBASE-KR PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. When you select the Backplane-KR
variant, the Link Training (LT) and Auto Negotiation (AN) tabs appear. The 1Gb/
10Gb Ethernet variant (1G/10GbE) does not implement the LT and AN functions.
Complete the following steps to parameterize the 10GBASE-KR PHY IP core in the
parameter editor:
1.
Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
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Refer to Select and Instantiate the PHY IP Core on page 31.
2. Select Backplane-KR from the IP variant list located under Ethernet Intel
FPGA IP Core Type.
3.
Use the parameter values in the tables in 10GBASE-R Parameters on page 138,
10GBASE-KR Auto-Negotiation and Link Training Parameters on page 138, and
10GBASE-KR Optional Parameters on page 139 as a starting point. You can then
modify the setting to meet your specific requirements.
4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL
file.
Note:
You might observe timing violations. If the timing path is within the IP, you can ignore
these violations. This will be fixed in a future release of the Intel Quartus Prime
software.
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
10GBASE-KR Auto-Negotiation and Link Training Parameters on page 138
2.6.3.4.1 General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 108.
General Options Parameters
Parameter Name
Options
Description
Enable internal PCS
reconfiguration logic
On
Off
This parameter is only an option when SYNTH_SEQ = 0. When
set to 0, it does not include the reconfiguration module or
expose the start_pcs_reconfig or rc_busy ports. When set
to 1, it provides a simple interface to initiate reconfiguration
between 1G and 10G modes.
Enable IEEE 1588 Precision
Time Protocol
On
Off
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
Enable M20K block ECC
protection
On
Off
When you turn on this parameter, you enable error correction
code (ECC) support on the embedded Nios CPU system. This
parameter is only valid for the backplane variant.
Enable tx_pma_clkout port
On
Off
When you turn on this parameter, the tx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_pma_clkout port
On
Off
When you turn on this parameter, the rx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_divclk port
On
Off
When you turn on this parameter, the tx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_divclk port
On
Off
When you turn on this parameter, the rx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_clkout port
On
Off
When you turn on this parameter, the tx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
continued...
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Parameter Name
Options
Description
Enable rx_clkout port
On
Off
When you turn on this parameter, the rx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable Hard PRBS support
and ADME support
On
Off
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
Reference clock frequency
644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
When you turn this option on, the core includes the
rx_block_lock and rx_hi_ber output.
Include FEC sublayer
On
Off
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS. This is applicable
only for the 10G mode.
Set FEC_ability bit on
power up and reset
On
Off
When you turn on this parameter, the core sets the Assert KR
FEC Ability bit (0xB0[16]) FEC ability bit during power up
On
Off
When you turn on this parameter, the core sets the KR FEC
Request bit (0xB0[18]) during power up and reset, causing
the core to request the FEC ability during Auto Negotiation. This
option is required for FEC functionality.
Set FEC_Enable bit on
power up and reset
and reset, causing the core to assert the FEC ability. This option
is required for FEC functionality.
Related Links
Clock and Reset Interfaces on page 141
2.6.3.4.2 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC
options also allow you to specify the FEC ability.
Table 109.
10GBASE-R Parameters
Parameter Name
Options
Description
10GbE Reference clock
frequency
644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
When you turn on this parameter, the core includes the
rx_block_lock and rx_hi_ber ports.
Table 110.
FEC Options
Parameter Name
Include FEC sublayer
Options
On
Off
Description
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS.
2.6.3.4.3 10GBASE-KR Auto-Negotiation and Link Training Parameters
Table 111.
Auto Negotiation and Link Training Settings
Name
Enable Auto-Negotiation
Range
On
Description
Enables or disables the Auto-Negotiation feature.
continued...
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Name
Range
Description
Off
Pause ability-C0
On
Off
Depends upon MAC. Local device pause capability C2:0 = D12:10 of
AN word.
C0 is the same as PAUSE.
Pause ability-C1
On
Off
Depends upon MAC. Local device pause capability C2:0 = D12:10 of
AN word.
C1 is the same as ASM_DIR.
Enable Link Training
On
Off
Enables or disables the Link Training feature.
Maximum bit error count
15, 31, 63,
127, 255,
511, 1023
Specifies the number of bit errors for the error counter expected
during each step of the link training. If the number of errors exceeds
this number for each step, the core returns an error. The number of
errors depends upon the amount of time for each step and the
quality of the physical link media.
The default value is 511.
Number of frames to send
before sending actual data
127, 255
This timer is started when the local receiver is trained and detects
that the remote receiver is ready to receive data. The local physical
medium dependent (PMD) layer delivers wait_timer additional
training frames to ensure that the link partner correctly detects the
local receiver state.
The default value is 127.
2.6.3.4.4 10GBASE-KR Optional Parameters
Table 112.
Optional Parameters
In the following table, the exact correspondence between numerical values and voltages is pending
characterization of the Native PHY.
Value
Name
Description
PHY Management clock
(MGMT_CLK) frequency in
MHz
100-162
Determines the value of the Link Fail Inhibit timer in IEEE 802.3
clause 73.10.2.
• 500 - 510 ms for BASE-R
• 40 – 50 ms for GbE, XAUI
The default value is 125.
VMAXRULE VOD tap MAX
Rule
0-31
Specifies the maximum VOD. The default value is 30.
VMINRULE Device VMIN
Rule
0-31
Specifies the minimum VOD. The default value is 6.
VODMINRULE VOD tap
MIN Rule
0-31
Specifies the minimum VOD for the first tap. The default value is 14.
VPOSTRULE
0-38
Specifies the maximum value that the internal algorithm for preemphasis will ever test in determining the optimum post-tap setting.
The default value is 25.
VPRERULE
0-31
Specifies the maximum value that the internal algorithm for preemphasis will ever test in determining the optimum pre-tap setting.
The default value is 16.
PREMAINVAL Preset VOD
tap Value
0-31
Specifies the Preset VOD value. This value is set by the Preset
command of the link training protocol, defined in Clause
72.6.10.2.3.1 of the Link Training protocol. This is the value from
which the algorithm starts. The default value is 30.
PREPOSTVAL
0-31
Specifies the preset Post-tap value. The default value is 0.
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Name
Value
Description
PREPREVAL
0-15
Specifies the preset Pre-tap value. The default value is 0.
INITMAINVAL Init VOD
tap Value
0-31
Specifies the initial VOD value. This value is set by the Initialize
command of the link training protocol, defined in Clause
72.6.10.2.3.2 of IEEE Std 802.3ap–2007. The default value is 25.
INITPOSTVAL Init Post
tap Value
0-38
Specifies the initial Post-tap value. The default value is 13.
INITPREVAL Init Pre tap
Value
0-15
Specifies the initial Pre-tap value. The default value is 3.
2.6.3.4.5 Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners
that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation,
if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner,
the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until
it detects a valid 1G or 10GbE pattern.
Table 113.
Speed Detection
Parameter Name
Options
Description
Enable automatic speed
detection
On
Off
When you turn this option On, the core includes the Sequencer
block that sends reconfiguration requests to detect 1G or 10GbE
when the Auto Negotiation block is not able to detect AN data.
Avalon-MM clock frequency
100-162 MHz
Specifies the clock frequency for phy_mgmt_clk.
Link fail inhibit time for
10Gb Ethernet
504 ms
Specifies the time before link_status is set to FAIL or OK. A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 500-510 ms. For
more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for
1Gb Ethernet
40-50 ms
Specifies the time before link_status is set to FAIL or OK . A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port
On
Off
Enables or disables the PCS-Mode port.
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2.6.3.5 10GBASE-KR PHY Interfaces
Figure 70.
10GBASE-KR Top-Level Signals
10GBASE-KR Top-Level Ports
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
XGMII
Interfaces
mgmt_clk
mgmt_clk_reset
mgmt_address[10:0]
mgmt_writedata[31:0]
mgmt_readdata[31:0]
mgmt_write
mgmt_read
mgmt_waitrequest
Avalon-MM PHY
Management
Interface
tx_serial_clk_10g
rx_cdr_ref_clk_10g
tx_pma_clkout
rx_pma_clkout
tx_clkout
rx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
Clocks and
Reset
Interface
rx_serial_data
tx_serial_data
rx_block_lock
rx_hi_ber
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
rx_syncstatus
lcl_rf
rx_clkslip
rx_latency_adj_10g[11:0]
tx_latency_adj_10g[11:0]
rx_data_ready
Transceiver
Serial Data
Status
The block diagram shown in the GUI labels the external pins with the interface type
and places the interface name inside the box. The interface type and name are used in
the _hw.tcl file. If you turn on Show signals, the block diagram displays all toplevel signal names.
Related Links
Component Interface Tcl Reference
For more information about _hw.tcl files
2.6.3.5.1 Clock and Reset Interfaces
Table 114.
Clock and Reset Signals
Signal Name
Direction
Description
tx_serial_clk_10g
Input
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g
Input
High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock
is not required if GbE is not used. The frequency of this clock is 625
MHz.
rx_cdr_ref_clk_10g
Input
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
rx_cdr_ref_clk_1g
Input
1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock
is only required if 1G is enabled.
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Signal Name
Direction
Description
tx_pma_clkout
Output
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
rx_pma_clkout
Output
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
tx_clkout
Output
XGMII/GMII TX clock for the TX parallel data source interface. This
clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
rx_clkout
Output
XGMII RX clock for the RX parallel data source interface. This clock
frequency is 257.81 in 10G mode, and 161.13 MHz with FEC
enabled.
tx_pma_div_clkout
Output
The divided 33 clock from the TX serializer. You can use this clock for
the for xgmii_tx_clk or xgmii_rx_clk. The frequency is 156.25
MHz for 10G. The frequencies are the same whether or not you
enable FEC.
rx_pma_div_clkout
Output
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not
you enable FEC. This clock is not used for clocking the 10G RX
datapath.
tx_analogreset
Input
Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
Input
tx_digitalreset
Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
Input
rx_analogreset
Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
Input
rx_digitalreset
Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
Input
usr_seq_reset
Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk.
Related Links
•
Input Reference Clock Sources on page 360
•
PLLs on page 337
2.6.3.5.2 Data Interfaces
Table 115.
XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name
Direction
Clock Domain
Description
10GbE XGMII Data Interface
xgmii_tx_dc[71:0
]
Input
xgmii_tx_clk
Input
Synchronous to
xgmii_tx_clk
Clock signal
XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
Clock for single data rate (SDR) XGMII TX interface to the
MAC. It should connect to xgmii_rx_clk. This clock can be
connected to the tx_div_clkout; however, Intel
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Signal Name
Direction
Clock Domain
Description
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
xgmii_rx_dc[71:0
]
Output
xgmii_rx_clk
Input
Synchronous to
xgmii_rx_clk
Clock signal
RX XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
Clock for SDR XGMII RX interface to the MAC. This clock can
be connected to the tx_div_clkout ; however, Intel
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
2.6.3.5.3 XGMII Mapping to Standard SDR XGMII Data
Table 116.
TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
SDR XGMII Signal Name
Description
xgmii_tx_dc[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_tx_dc[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_tx_dc[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_tx_dc[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_tx_dc[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_tx_dc[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_tx_dc[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_tx_dc[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_tx_dc[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_tx_dc[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_tx_dc[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_tx_dc[53]
xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_tx_dc[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_tx_dc[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_tx_dc[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_tx_dc[71]
xgmii_sdr_ctrl[7]
Lane 7 control
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Table 117.
RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
XGMII Signal Name
Description
xgmii_rx_dc[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc[53]
xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc[71]
xgmii_sdr_ctrl[7]
Lane 7 control
2.6.3.5.4 Serial Data Interface
Table 118.
Serial Data Signals
Signal Name
Direction
Description
rx_serial_data
Input
RX serial input data
tx_serial_data
Output
TX serial output data
2.6.3.5.5 Control and Status Interfaces
Table 119.
Control and Status Signals
Signal Name
led_link
Direction
Output
Clock Domain
Synchronous to
Description
When asserted, indicates successful link synchronization.
tx_clkout
led_disp_err
Output
Synchronous to
rx_clkout
led_an
Output
Synchronous to
rx_clkout
Disparity error signal indicating a 10-bit running disparity
error. Asserted for one rx_clkout_1g cycle when a
disparity error is detected. A running disparity error
indicates that more than the previous and perhaps the
current received group had an error.
Clause 37 Auto-negotiation status. The PCS function
asserts this signal when auto-negotiation completes.
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Signal Name
led_panel_link
Direction
Output
Clock Domain
Synchronous to
mgmt_clk
Description
When asserted, this signal indicates the following
behavior:
Mode
rx_block_lock
Output
Synchronous to
rx_clkout
rx_hi_ber
Output
Synchronous to
rx_clkout
Behavior
1000 Base-X without Autonegotiation
When asserted, indicates
successful link
synchronization.
SGMII mode without Autonegotiation
When asserted, indicates
successful link
synchronization.
1000 Base-X with Autonegotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
SGMII mode with MAC
mode Auto-negotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
Asserted to indicate that the block synchronizer has
established synchronization.
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10-4.
rx_is_lockedtodat
a
Output
Asynchronous signal
When asserted, indicates the RX channel is locked to input
data.
tx_cal_busy
Output
Synchronous to
When asserted, indicates that the TX channel is being
calibrated.
mgmt_clk
rx_cal_busy
Output
Synchronous to
mgmt_clk
When asserted, indicates that the RX channel is being
calibrated.
tx_pcfifo_error_1
g
Output
N/A
When asserted, indicates that the standard PCS TX phase
compensation FIFO is either full or empty.
rx_pcfifo_error_1
g
Output
N/A
When asserted, indicates that the Standard PCS RX phase
compensation FIFO is either full or empty.
lcl_rf
Input
Synchronous to
When asserted, indicates a Remote Fault (RF).The MAC
sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault register
(0xC2) records this error.
xgmii_tx_clk
rx_clkslip
Input
Asynchronous signal
When asserted, the deserializer either skips one serial bit
or pauses the serial clock for one cycle to achieve word
alignment. As a result, the period of the parallel clock
could be extended by 1 unit interval (UI) during the clock
slip operation.This is an optional control input signal.
rx_data_ready
Output
Synchronous to
When asserted, indicates that the MAC can begin sending
data to the PHY.
xgmii_rx_clk
rx_latency_adj_10
g[15:0]
Output
Synchronous to
xgmii_rx_clk
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
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Signal Name
Direction
tx_latency_adj_10
g[15:0]
Output
rx_latency_adj_1
g[21:0]
Output
tx_latency_adj_1
g[21:0]
Output
Clock Domain
Synchronous to
Description
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
xgmii_tx_clk
Synchronous to
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
gmii_rx_clk
Synchronous to
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
gmii_tx_clk
2.6.3.5.6 Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change
between 1G and 10G data rates.
Table 120.
Dynamic Reconfiguration Interface Signals
Signal Name
Direction
Output
rc_busy
Clock Domain
Synchronous to
mgmt_clk
start_pcs_reconf
ig
Input
mode_1g_10gbar
Input
Synchronous to
mgmt_clk
Synchronous to
mgmt_clk
Description
When asserted, indicates that reconfiguration is in
progress. Synchronous to the mgmt_clk. This signal is
only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration logic
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk. This signal is only exposed
under the following condition:
• Turn on Enable internal PCS reconfiguration logic
This signal selects either the 1G or 10G tx-parallel-data
going to the PCS. It is only used for the 1G/10G
application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.3.6 Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 121.
Avalon-MM Interface Signals
Signal Name
Direction
Clock Domain
Description
mgmt_clk
Input
Clock
The clock signal that controls the Avalon-MM PHY management
interface. If you plan to use the same clock for the PHY
management interface and transceiver reconfiguration, you must
restrict the frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
mgmt_clk_res
et
Input
Asynchronous reset
Resets the PHY management interface. This signal is active high
and level sensitive.
mgmt_addr[10
:0]
Input
Synchronous to
11-bit Avalon-MM address.
mgmt_clk
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Signal Name
Direction
mgmt_writeda
ta[31:0]
Input
mgmt_readdat
a[31:0]
Output
mgmt_write
Input
Clock Domain
Synchronous to
Description
Input data.
mgmt_clk
Synchronous to
Output data.
mgmt_clk
Synchronous to
Write signal. Active high.
mgmt_clk
Input
mgmt_read
Synchronous to
Read signal. Active high.
mgmt_clk
mgmt_waitreq
uest
Output
Synchronous to
mgmt_clk
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted,
control signals to the Avalon-MM slave interface must remain
constant.
Related Links
Avalon Interface Specifications
2.6.3.6.1 10GBASE-KR PHY Register Definitions
The Avalon-MM slave interface signals provide access to the control and status
registers.
The following table specifies the control and status registers that you can access over
the Avalon-MM PHY management interface. A single address space provides access to
all registers.
Note:
Unless otherwise indicated, the default value of all registers is 0.
Note:
Writing to reserved or undefined register addresses may have undefined side effects.
Table 122.
10GBASE-KR Register Definitions
Word
Addr
0x4B0
Bit
R/W
Name
Description
0
RW
Reset SEQ
When set to 1, resets the 10GBASE-KR sequencer (auto rate
detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation, Link Training or both if AN and LT are
enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces
these modes. This reset self clears.
1
RW
Disable AN Timer
Auto-Negotiation disable timer. If disabled ( Disable AN
Timer = 1) , AN may get stuck and require software support
to remove the ABILITY_DETECT capability if the link partner
does not include this feature. In addition, software may have
to take the link out of loopback mode if the link is stuck in the
ACKNOWLEDGE_DETECT state. To enable this timer set
Disable AN Timer = 0.
2
RW
Disable LF Timer
When set to 1, disables the Link Fail timer. When set to 0, the
Link Fault timer is enabled.
3
RW
fail_lt_if_ber
When set to 1, the last LT measurement is a non-zero
number. Treat this as a failed run. 0 = normal.
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Word
Addr
Bit
7:4
R/W
RW
Name
SEQ Force Mode[3:0]
Description
Forces the sequencer to a specific protocol. Must write the
Reset SEQ bit to 1 for the Force to take effect. The following
encodings are defined:
• 0000: No force
• 0001: GigE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
0x4B0
0x4B1
0x4B2
8
RW
Enable Arria 10
Calibration
When set to 1, it enables the Arria 10 HSSI reconfiguration
calibration as part of the PCS dynamic reconfiguration. 0 skips
the calibration when the PCS is reconfigured.
11:9
RW
Reserved
—
12
RW
LT failure response
When set to 1, LT failure causes the PHY to go into data
mode. When set to 0, LT failure restarts auto-negotiation (if
enabled). If auto-negotiation is not enabled, the PHY will
restart LT.
16
RW
KR FEC enable 171.0
When set to 1, FEC is enabled. When set to 0, FEC is
disabled. Resets to the CAPABLE_FEC parameter value.
17
RW
KR FEC enable err
ind 171.1
When set to 1, KR PHY FEC decoding errors are signaled to
the PCS. When set to 0, FEC errors are not signaled to the
PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18
RW
KR FEC request
When set to 1, enables the FEC request. When this bit
changes, you must assert the Reset SEQ bit (0x4B0[0]) to
renegotiate with the new value. When set to 0, disables the
FEC request.
0
R
SEQ Link Ready
When asserted, the sequencer is indicating that the link is
ready.
1
R
SEQ AN timeout
When asserted, the sequencer has had an Auto Negotiation
timeout. This bit is latched and is reset when the sequencer
restarts Auto Negotiation.
2
R
SEQ LT timeout
When set, indicates that the Sequencer has had a timeout.
13:8
R
SEQ Reconfig
Mode[5:0]
Specifies the Sequencer mode for PCS reconfiguration. The
following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GigE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit 13, mode[5]: 10G FEC mode
16
R
KR FEC ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY supports
FEC. Set as parameter SYNTH_FEC. For more information,
refer to Clause 45.2.1.84 of IEEE 802.3ap-2007.
17
R
KR FEC err ind
ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY is capable
of reporting FEC decoding errors to the PCS. For more
information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0:10
—
Reserved
—
11
RW
KR FEC TX Error
Insert
Writing a 1 inserts one error pulse into the TX FEC depending
on the Transcoder and Burst error settings. This bit self
clears.
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Word
Addr
Bit
31:12
R/W
—
0x4B5 to
0x4BF
0x4C0
Name
Description
Reserved
—
Reserved for 40G KR
Intentionally left empty for address compatibility with 40G
MAC + PHY KR solutions.
0
RW
AN enable
When set to 1, enables Auto Negotiation function. The default
value is 1. For additional information, refer to 7.0.12 in
Clause 73.8 Management Register Requirements, of IEEE
802.3ap-2007.
1
RW
AN base pages ctrl
When set to 1, the user base pages are enabled. You can
send any arbitrary data via the user base page low/high bits.
When set to 0, the user base pages are disabled and the state
machine generates the base pages to send.
2
RW
AN next pages ctrl
When set to 1, the user next pages are enabled. You can send
any arbitrary data via the user next page low/high bits. When
set to 0, the user next pages are disabled. The state machine
generates the null message to send as next pages.
3
RW
Local device remote
fault
When set to 1, the local device signals Remote Faults in the
Auto Negotiation pages. When set to 0, a fault has not
occurred.
4
RW
Force TX nonce value
When set to 1, forces the TX nonce value to support some
UNH testing modes. When set to 0, this is normal operation.
5
RW
Override AN
Parameters Enable
When set to 1, overrides the AN_TECH, AN_FEC, and
AN_PAUSE parameters and uses the bits in 0xC3 instead. You
must reset the Sequencer to reconfigure and restart into Auto
Negotiation mode. When set to 0, this is normal operation
and is used with 0x4B0 bit 0 and 0x4C3 bits[30:16].
0x4C1
0x4C2
0
RW
Reset AN
When set to 1, resets all the 10GBASE-KR Auto Negotiation
state machines. This bit is self-clearing.
4
RW
Restart AN TX SM
When set to 1, restarts the 10GBASE-KR TX state machine.
This bit self clears. This bit is active only when the TX state
machine is in the Auto Negotiation state. For more
information, refer to 7.0.9 in Clause 73.8 Management
Register Requirements of IEEE 802.3ap-2007.
8
RW
AN Next Page
When asserted, new next page info is ready to send. The data
is in the XNP TX registers. When 0, the TX interface sends
null pages. This bit self clears. Next Page (NP) is encoded in
bit D15 of Link Codeword. For more information, refer to
Clause 73.6.9 and 7.16.15 of Clause 45.2.7.6 of IEEE
802.3ap-2007.
1
RO
AN page received
When set to 1, a page has been received. When 0, a page has
not been received. The current value clears when the register
is read. For more information, refer to 7.1.6 in Clause 73.8 of
IEEE 802.3ap-2007.
2
RO
AN Complete
When asserted, Auto-Negotiation has completed. When 0,
Auto Negotiation is in progress. For more information, refer to
7.1.5 in Clause 73.8 of IEEE 802.3ap-2007.
3
RO
AN ADV Remote Fault
When set to 1, fault information has been sent to the link
partner. When 0, a fault has not occurred. The current value
clears when the register is read. Remote Fault (RF) is encoded
in bit D13 of the base Link Codeword. For more information,
refer to Clause 73.6.7 of and 7.16.13 of IEEE 802.3ap-2007.
4
RO
AN RX SM Idle
When set to 1, the Auto-Negotiation state machine is in the
idle state. Incoming data is not Clause 73 compatible. When
0, the Auto-Negotiation is in progress.
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Word
Addr
0x4C2
0x4C3
Bit
R/W
Name
Description
5
RO
AN Ability
When set to 1, the transceiver PHY is able to perform Auto
Negotiation. When set to 0, the transceiver PHY i s not able to
perform Auto Negotiation. If your variant includes Auto
Negotiation, this bit is tied to 1. For more information, refer
to 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
6
RO
AN Status
When set to 1, link is up. When 0, the link is down. The
current value clears when the register is read. For more
information, refer to 7.1.2 of Clause 45 of IEEE
802.3ap-2007.
7
RO
LP AN Ability
When set to 1, the link partner is able to perform Auto
Negotiation. When 0, the link partner is not able to perform
Auto-Negotiation. For more information, refer to 7.1.0 of
Clause 45 of IEEE 802.3ap-2007.
8
RO
FEC negotiated –
enable FEC from SEQ
When set to 1, PHY is negotiated to perform FEC. When set to
0, PHY is not negotiated to perform FEC.
9
RO
Seq AN Failure
When set to 1, a sequencer Auto Negotiation failure has been
detected. When set to 0, an Auto Negotiation failure has not
been detected.
17:12
RO
KR AN Link
Ready[5:0]
Provides a one-hot encoding of an_receive_idle = true
and link status for the supported link as described in Clause
73.10.1. The following encodings are defined:
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
15:0
RW
User base page low
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation base pages ctrl bit is set. The following bits
are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce which are set by the state machine
• [4:0]: Selector
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX
state machine.
21:16
RW
Override
AN_TECH[5:0]
AN_TECH value with which to override the current value. The
following bits are defined:
• Bit-16 = AN_TECH[0]= 1000BASE-KX
•
Bit-17 = AN_TECH[1] = XAUI
•
Bit-18 = AN_TECH[2] = 10GBASE-KR
•
Bit-19 = AN_TECH[3] = 40G
•
Bit-20 = AN_TECH[4] = CR-4
•
Bit-21 = AN_TECH[5] = 100G
You must set 0x4C0 bit-5 for this to take effect .
25:24
RW
Override AN_FEC[1:0]
AN_FEC value with which to override the current value. The
following bits are defined:
• Bit-24 = AN_ FEC [0] = Capability
•
Bit-25 = AN_ FEC [1] = Request
You must set 0x4C0 bit-5 for this to take effect.
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Word
Addr
Bit
30:28
R/W
RW
Name
Override
AN_PAUSE[2:0]
Description
AN_PAUSE value with which to override the current value. The
following bits are defined:
• Bit-28 = AN_PAUSE [0] = Pause Ability
•
Bit-29 = AN_PAUSE [1] = Asymmetric Direction
•
Bit-30 = AN_PAUSE [2] = Reserved
You must set 0x4C0 bit-5 for this to take effect.
0x4C4
31:0
RW
User base page high
0x4C5
15:0
RW
User Next page low
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation base pages ctrl bit is set. The following bits
are defined:
• [29:5]: Correspond to page bits 45:21 which are the
technology ability.
• [4:0]: Correspond to bits 20:16 which are TX nonce bits.
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX
state machine.
The Auto Negotiation TX state machine uses these bits if the
AN Next Page control bit is set. The following bits are
defined:
• [15]: next page bit
• [14]: ACK controlled by the state machine
• [13]: Message Page (MP) bit
• [12]: ACK2 bit
• [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is
generated by the Auto-Negotiation TX state machine.
0x4C6
31:0
RW
User Next page high
The Auto Negotiation TX state machine uses these bits if the
Auto Negotiation next pages ctrl bit is set. Bits [31:0]
correspond to page bits [47:16]. Bit 49, the PRBS bit, is
generated by the Auto Negotiation TX state machine.
0x4C7
15:0
RO
LP base page low
The AN RX state machine receives these bits from the link
partner. The following bits are defined:
• [15] Next page bit
• [14] ACK which is controlled by the state machine
• [13] RF bit
• [12:10] Pause bits
• [9:5] Echoed Nonce which are set by the state machine
• [4:0] Selector
0x4C8
31:0
RO
LP base page high
The AN RX state machine receives these bits from the link
partner. The following bits are defined:
• [31:30]: Reserved
• [29:5]: Correspond to page bits [45:21] which are the
technology ability
• [4:0]: Correspond to bits [20:16] which are TX Nonce bits
0x4C9
15:0
RO
LP Next page low
The AN RX state machine receives these bits from the link
partner. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the state machine
• [13]: MP bit
• [12] ACK2 bit
• [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007.
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Word
Addr
Bit
R/W
Name
Description
0x4CA
31:0
RO
LP Next page high
The AN RX state machine receives these bits from the link
partner. Bits [31:0] correspond to page bits [47:16]
0x4CB
24:0
RO
AN LP ADV
Tech_A[24:0]
Received technology ability field bits of Clause 73 Auto
Negotiation. The 10GBASE-KR PHY supports A0 and A2. The
following protocols are defined:
• A0 1000BASE-KX
• A1 10GBASE-KX4
• A2 10GBASE-KR
• A3 40GBASE-KR4
• A4 40GBASE-CR4
• A5 100GBASE-CR10
• A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base
page ability registers (7.19-7.21) of Clause 45 of IEEE
802.3ap-2007.
26:25
RO
AN LP ADV FEC_F[1:0]
Received FEC ability bits FEC (F0:F1) is encoded in bits
D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is
FEC requested. See Clause 73.6.5 of IEEE 802.3ap-2007 for
details.
27
RO
AN LP ADV Remote
Fault
Received Remote Fault (RF) ability bits. RF is encoded in bit
D13 of the base link codeword in Clause 73 AN. For more
information, refer to Clause 73.6.7 of IEEE 802.3ap-2007.
30:28
RO
AN LP ADV Pause
Ability_C[2:0]
Received pause ability bits. Pause (C0:C1) is encoded in bits
D11:D10 of the base link codeword in Clause 73 AN as
follows:
• C0 is the same as PAUSE as defined in Annex 28B
• C1 is the same as ASM_DIR as defined in Annex 28B
• C2 is reserved
0
RW
Link Training enable
When 1, enables the 10GBASE-KR start-up protocol. When 0,
disables the 10GBASE-KR start-up protocol. The default value
is 1. For more information, refer to Clause 72.6.10.3.1 and
10GBASE-KR PMD control register bit (1.150.1) of IEEE
802.3ap-2007.
1
RW
dis_max_wait_tmr
When set to 1, disables the LT max_wait_timer. Used for
characterization mode when setting much longer BER timer
values. The default value is 0.
2
RW
Reserved
Reserved
3
RW
Reserved
Reserved
7:4
RW
main_step_cnt [3:0]
Specifies the number of equalization steps for each main tap
update. There are about 20 settings for the internal algorithm
to test. The valid range is 1-15. The default value is 4'b0001.
11:8
RW
prepost_step_cnt
[3:0]
Specifies the number of equalization steps for each pre- and
post-tap update. From 16-31 steps are possible. The default
value is 4'b0001.
14:12
RW
equal_cnt [2:0]
Adds hysteresis to the error count to avoid local minimums.
The following values are defined:
• 000 = 0
• 001 = 2
• 010 = 4
• 011 = 8
• 100 = 16
0x4D0
0x4D0
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Word
Addr
Bit
R/W
Name
Description
• 101 = 32
• 110 = 64
• 111 = 128
The default value is 101.
0x4D0
15
RW
disable Initialize
PMA on
max_wait_timeout
When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not
initialized upon entry into the Training_Failure state. This
happens when max_wait_timer_done, which sets
training_failure = true (reg 0xD2 bit 3). Used for UNH
testing. When set to 0, PMA values are initialized upon entry
into Training_Failure state. Refer to Figure 72-5 of IEEE
802.3ap-2007 for more details. The default value is 0.
16
RW
Ovride LP Coef
enable
When set to 1, overrides the link partner's equalization
coefficients; software changes the update commands sent to
the link partner TX equalizer coefficients. When set to 0, uses
the Link Training logic to determine the link partner
coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0]. The
default value is 0.
17
RW
Ovride Local RX Coef
enable
When set to 1, overrides the local device equalization
coefficients generation protocol. When set, the software
changes the local TX equalizer coefficients. When set to 0,
uses the update command received from the link partner to
determine local device coefficients. Used with 0x4D1 bit-8 and
0x4D4 bits[23:16]. The default value is 0.
18
RW
VOD Training Enable
Defines whether or not to skip adjustment of the link
partner’s VOD (main tap) during link training. The following
values are defined:
• 1 = Exercise VOD (main tap) adjustment during link
training
• 0 = Skip VOD (main tap) adjustment during link training
The default value is 0.
19
RW
Bypass DFE
Defines whether or not Decision Feedback Equalization (DFE)
is enabled at the end of link training. The following values are
defined:
• 1 = Bypass continuous adaptive DFE at the end of link
training
• 0 = Enable continuous adaptive DFE at the end of link
training
The default value for simulation is 1. The default value for
hardware is 0.
21:20
RW
dfe_freeze_mode
Defines the behavior of DFE taps at the end of link training
• 00 = do not freeze any DFE taps
• 01 = Freeze all DFE taps
• 10 = reserved
• 11 = reserved
The default value is 01.
Note: These bits will be effective only when bit [19] is set to
0.
0x4D0
22
RW
adp_ctle_vga_mode
Defines whether or not CTLE/VGA adaptation is in adaptive or
manual mode. The following values are defined:
• 0 = CTLE sweep before start of TX-EQ during link training.
• 1 = manual CTLE mode. Link training algorithm sets fixed
CTLE value, as specified in bits [28:24]. The default value
is 1 for simulation. .
The default value is 0 for hardware.
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Word
Addr
0x4D1
0x4D2
Bit
R/W
Name
Description
28:24
RW
Manual CTLE
Defines the CTLE value used by the link training algorithm
when in manual CTLE mode. These bits are only effective
when 0x4D0[22] is set to 1.
The default value is 1.
31:29
RW
Manual VGA
Defines the VGA value used by the link training algorithm
when in manual VGA mode. These bits are only effective
when 0x4D0[22] is set to 1.
The default value is 4 for simulation. The default value is 7 for
hardware.
0
RW
Restart Link
training
When set to 1, resets the 10GBASE-KR start-up protocol.
When set to 0, continues normal operation. This bit self
clears. For more information, refer to the state variable
mr_restart_training as defined in Clause 72.6.10.3.1
and 10GBASE-KR PMD control register bit (1.150.0) IEEE
802.3ap-2007.
4
RW
Updated TX Coef new
When set to 1, there are new link partner coefficients
available to send. The LT logic starts sending the new values
set in 0x4D4 bits[7:0] to the remote device. When set to 0,
continues normal operation. This bit self clears. Must enable
this override in 0x4D0 bit16.
8
RW
Updated RX coef new
When set to 1, new local device coefficients are available. The
LT logic changes the local TX equalizer coefficients as
specified in 0x4D4 bits[23:16]. When set to 0, continues
normal operation. This bit self clears. Must enable the
override in 0x4D0 bit17.
21:20
RW
Reserved
Reserved
0
RO
Link Trained Receiver status
When set to 1, the receiver is trained and is ready to receive
data. When set to 0, receiver training is in progress. For more
information, refer to the state variable rx_trained as defined
in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
1
RO
Link Training Frame
lock
When set to 1, the training frame delineation has been
detected. When set to 0, the training frame delineation has
not been detected. For more information, refer to the state
variable frame_lock as defined in Clause 72.6.10.3.1 of IEEE
802.3ap-2007.
2
RO
Link Training Startup protocol status
When set to 1, the start-up protocol is in progress. When set
to 0, start-up protocol has completed. For more information,
refer to the state training as defined in Clause 72.6.10.3.1 of
IEEE 802.3ap-2007.
3
RO
Link Training
failure
When set to 1, a training failure has been detected. When set
to 0, a training failure has not been detected For more
information, refer to the state variable training_failure as
defined in Clause 72.6.10.3.1 of IEEE 802.3ap-2007.
4
RO
Link Training Error
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
5
RO
Link Training Frame
lock Error
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5
are the same as the initial parameter value, the frame lock
error was unrecoverable.
6
RO
RXEQ Frame Lock Loss
Frame lock not detected at some point during RXEQ, possibly
triggering conditional RXEQ mode.
7
RO
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit
at each step in the Fine-grained Tuning mode.
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Word
Addr
0x4D3
0x4D4
0x4D4
Bit
R/W
Name
Description
9:0
RW
ber_time_frames
Specifies the number of training frames to examine for bit
errors on the link for each step of the equalization settings.
Used only when ber_time_k_frames is 0.The following values
are defined:
• A value of 2 is about 103 bytes
• A value of 20 is about 104 bytes
• A value of 200 is about 105 bytes
The default value for simulation is 2'b11. The default value for
hardware is 0.
19:10
RW
ber_time_k_frames
Specifies the number of thousands of training frames to
examine for bit errors on the link for each step of the
equalization settings. Set ber_time_m_frames = 0 for time/
bits to match the following values:
• A value of 3 is about 107 bits = about 1.3 ms
• A value of 25 is about 108 bits = about 11ms
• A value of 250 is about 109 bits = about 11 0ms
The default value for simulation is 0. The default value for
hardware is 0xF.
29:20
RW
ber_time_m_frames
Specifies the number of millions of training frames to examine
for bit errors on the link for each step of the equalization
settings. Set ber_time_k_frames = 4'd1000 = 0x43E8 for
time/bits to match the following values:
• A value of 3 is about 1010 bits = about 1.3 seconds
• A value of 25 is about 10 11 bits = about 11 seconds
• A value of 250 is about 1012 bits = about 110 seconds
5:0
RO or
RW
LD coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training
frame sent from the local device control channel. Normally,
the bits in this register are read-only; however, when you
override training by setting the Ovride Coef enable
control bit, these bits become writable. The following fields
are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD coefficient
update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE
802.3ap-2007.
6
RO or
RW
LD Initialize
Coefficients
When set to 1, requests the link partner coefficients be set to
configure the TX equalizer to its INITIALIZE state. When set
to 0, continues normal operation. For more information, refer
to 10G BASE-KR LD coefficient update register bits (1.154.12)
in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
7
RO or
RW
LD Preset
Coefficients
When set to 1, requests the link partner coefficients be set to
a state where equalization is turned off. When set to 0 the
link operates normally. For more information, refer to 10G
BASE-KR LD coefficient update register bit (1.154.13) in
Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE
802.3ap-2007.
13:8
RO
LD coefficient
status[5:0]
Status report register for the contents of the second, 16-bit
word of the training frame most recently sent from the local
device control channel. The following fields are defined:
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Word
Addr
Bit
R/W
Name
Description
•
[5:4]: Coefficient (post-tap)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD status report
register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
0x4D4
0x4D4
14
RO
Link Training ready
- LD Receiver ready
When set to 1, the local device receiver has determined that
training is complete and is prepared to receive data. When set
to 0, the local device receiver is requesting that training
continue. Values for the receiver ready bit are defined in
Clause 72.6.10.2.4.4. For more information, refer to 10G
BASE-KR LD status report register bit (1.155.15) in Clause
45.2.1.81 of IEEE 802.3ap-2007.
21:16
RO or
RW
LP coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training
frame most recently received from the control channel.
Normally the bits in this register are read only; however,
when training is disabled by setting low the KR Training
enable control bit, these bits become writable. The following
fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP coefficient
update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE
802.3ap-2007.
22
RO or
RW
LP Initialize
Coefficients
When set to 1, the local device transmit equalizer coefficients
are set to the INITIALIZE state. When set to 0, normal
operation continues. The function and values of the initialize
bit are defined in Clause 72.6.10.2.3.2. For more information,
refer to 10G BASE-KR LP coefficient update register bits
(1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
23
RO or
RW
LP Preset
Coefficients
When set to 1, the local device TX coefficients are set to a
state where equalization is turned off. Preset coefficients are
used. When set to 0, the local device operates normally. The
function and values of the preset bit are defined in
72.6.10.2.3.1. The function and values of the initialize bit are
defined in Clause 72.6.10.2.3.2. For more information, refer
to 10G BASE-KR LP coefficient update register bits (1.152.13)
in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
29:24
RO
LP coefficient
status[5:0]
Status report register reflects the contents of the second, 16bit word of the training frame most recently received from the
control channel: The following fields are defined:
continued...
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Word
Addr
Bit
R/W
Name
Description
•
[5:4]: Coefficient (+1)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP status report
register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
0x4D5
0x4D5
0x4D6
30
RO
LP Receiver ready
When set to 1, the link partner receiver has determined that
training is complete and is prepared to receive data. When set
to 0, the link partner receiver is requesting that training
continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to 10G BASE-KR
LP status report register bits (1.153.15) in Clause 45.2.1.79
of IEEE 802.3ap-2007.
4:0
R
LT VOD setting
Stores the most recent TX VOD setting trained by the link
partner's RX based on the LT coefficient update logic driven
by Clause 72. It reflects Link Partner commands to fine-tune
the TX preemphasis taps.
13:8
R
LT Post-tap setting
Stores the most recent TX post-tap setting trained by the link
partner’s RX based on the LT coefficient update logic driven
by Clause 72. It reflects Link Partner commands to fine-tune
the TX pre-emphasis taps.
20:16
R
LT Pre-tap setting
Store the most recent TX pre-tap setting trained by the link
partner’s RX based on the LT coefficient update logic driven
by Clause 72. It reflects Link Partner commands to fine-tune
the TX pre-emphasis taps.
27:24
R
RXEQ CTLE Setting
Most recent ctle_rc setting sent to the reconfig bundle
during RX equalization.
29:28
R
RXEQ CTLE Mode
Most recent ctle_mode setting sent to the reconfig bundle
during RX equalization.
31:30
R
RXEQ DFE Mode
Most recent dfe_mode setting sent to the reconfig bundle
during RX equalization.
4:0
RW
LT VODMAX ovrd
Override value for the VMAXRULE parameter. When enabled,
this value substitutes for the VMAXRULE to allow channelby-channel override of the device settings. This only affects
the local device TX output for the channel specified.
This value must be greater than the INITMAINVAL
parameter for proper operation. Note this will also override
the PREMAINVAL parameter value.
5
RW
LT VODMAX ovrd
Enable
When set to 1, enables the override value for the VMAXRULE
parameter stored in the LT VODMAX ovrd register field.
12:8
RW
LT VODMin ovrd
Override value for the VODMINRULE parameter. When
enabled, this value substitutes for the VMINRULE to allow
channel-by-channel override of the device settings. This
override only effects the local device TX output for this
channel.
The value to be substituted must be less than the
INITMAINVAL parameter and greater than the VMINRULE
parameter for proper operation.
continued...
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Word
Addr
Bit
R/W
Name
Description
13
RW
LT VODMin ovrd
Enable
When set to 1, enables the override value for the
VODMINRULE parameter stored in the LT VODMin ovrd
register field.
21:16
RW
LT VPOST ovrd
Override value for the VPOSTRULE parameter. When
enabled, this value substitutes for the VPOSTRULE to allow
channel-by-channel override of the device settings. This
override only effects the local device TX output for this
channel.
The value to be substituted must be greater than the
INITPOSTVAL parameter for proper operation.
22
RW
LT VPOST ovrd Enable
When set to 1, enables the override value for the
VPOSTRULE parameter stored in the LT VPOST ovrd
register field.
28:24
RW
LT VPre ovrd
Override value for the VPRERULE parameter. When enabled,
this value substitutes for the VPOSTRULE to allow channelby-channel override of the device settings. This override only
effects the local device TX output for this channel.
The value to be substituted must be greater than the
INITPREVAL parameter for proper operation.
29
RW
LT VPre ovrd Enable
When set to 1, enables the override value for the VPRERULE
parameter stored in the LT VPre ovrd register field.
Reserved for 40G KR
Left empty for address compatibility with 40G MAC+PHY KR
solution.
0x4D6
to 0x4FF
2.6.3.6.2 Hard Transceiver PHY Registers
Table 123.
Addr
0x000-0
x3FF
Hard Transceiver PHY Registers
Bit
[9:0]
Access
RW
Name
Access to HSSI
registers
Description
All registers in the physical coding sub-layer (PCS) and physical
media attachment (PMA) that you can dynamically reconfigure
are in this address space. Refer to the Arria 10 Dynamic
Transceiver Reconfiguration chapter for further information.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
2.6.3.6.3 Enhanced PCS Registers
Table 124.
Enhanced PCS Registers
Addr
Bit
Access
Name
Description
0x480
31:0
RW
Indirect_addr
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
0x481
2
RW
RCLR_ERRBLK_CNT
Error block counter clear register. When set to 1, clears
the RCLR_ERRBLK_CNT register. When set to 0, normal
operation continues.
3
RW
RCLR_BER_COUNT
BER counter clear register. When set to 1, clears the
RCLR_BER_COUNT register. When set to 0, normal
operation continues.
continued...
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Addr
Bit
0x482
Access
Name
Description
1
RO
HI_BER
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
2
RO
BLOCK_LOCK
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
3
RO
TX_FIFO_FULL
When set to 1, the TX_FIFO is full.
4
RO
RX_FIFO_FULL
When set to 1, the RX_FIFO is full.
7
RO
Rx_DATA_READY
When set to 1, indicates the PHY is ready to receive
data.
2.6.3.6.4 PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data
interface, and provide status information.
Table 125.
1G Data Mode
Addr
Bit
0x4A8
0x4A9
Table 126.
0x461
Name
Description
0
RW
tx_invpolarity
When set, the TX interface inverts the polarity of
the TX data to the 8B/10B encoder.
1
RW
rx_invpolarity
When set, the RX channels inverts the polarity of
the received data to the 8B/10B decoder.
2
RW
rx_bitreversal_enable
When set, enables bit reversal on the RX interface
to the word aligner.
3
RW
rx_bytereversal_enable
When set, enables byte reversal on the RX interface
to the byte deserializer.
4
RW
force_electrical_idle
When set, forces the TX outputs to electrical idle.
0
R
rx_syncstatus
When set, the word aligner is synchronized.
1
R
rx_patterndetect
GbE word aligner detected comma.
2
R
rx_rlv
Run length violation.
3
R
rx_rmfifodatainserted
Rate match FIFO inserted code group.
4
R
rx_rmfifodatadeleted
Rate match FIFO deleted code group.
5
R
rx_disperr
RX 8B10B disparity error.
6
R
rx_errdetect
RX 8B10B error detected.
PMA Registers
Address
0x444
R/W
Bit
R/W
Name
Description
1
RW
reset_tx_digital
Writing a 1 asserts the internal TX digital reset signal. You
must write a 0 to clear the reset condition.
2
RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal to be
asserted. You must write a 0 to clear the reset condition.
3
RW
reset_rx_digital
Writing a 1 causes the internal RX digital reset signal to be
asserted. You must write a 0 to clear the reset condition.
0
RW
phy_serial_loopback
Writing a 1 puts the channel in serial loopback mode.
continued...
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Address
Bit
R/W
Name
Description
0x464
0
RW
pma_rx_set_locktoda
ta
When set, programs the RX clock data recovery (CDR) PLL
to lock to the incoming data.
0x465
0
RW
pma_rx_set_locktore
f
When set, programs the RX CDR PLL to lock to the reference
clock.
0x466
0
RO
pma_rx_is_lockedtod
ata
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode.
0x467
0
RO
pma_rx_is_lockedtor
ef
When asserted, indicates that the RX CDR PLL is locked to
the reference clock.
2.6.3.7 Creating a 10GBASE-KR Design
Follow these steps to create a 10GBASE-KR design.
1.
Generate the 10GBASE-KR PHY with the required parameterization.
The 10GBASE-KR PHY IP core includes a reconfiguration block. The reconfiguration
block provides the Avalon-MM interface to access the PHY registers.
2.
Instantiate a reset controller. You can generate a Transceiver Reset Controller IP
core from the IP Catalog. You must connect the Transceiver Reset Controller IP
core and 10GBASE-KR PHY IP core power and reset signals.
3.
Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 10GBASE-KR
PHY and TX PLLs. For the 1G data rate you can use either fPLL, ATX PLL, or CMU
PLL. For the 10G data rate you can use ATX PLL or CMU PLL.
4.
Generate a fPLL to create the 156.25 MHz XGMII clock from the 10G reference
clock.
5.
Use the tx_pma_divclk from the 10GBASE-KR PHY or generate a fPLL to create
the 156.25 MHz XGMII clock from the 10G reference clock.
Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory
Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10
devices.
6.
Complete the design by creating a top level module to connect all the IP
(10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.
Related Links
•
fPLL on page 347
•
CMU PLL on page 356
•
ATX PLL on page 338
•
Using the Transceiver PHY Reset Controller on page 418
•
10GBASE-KR Functional Description on page 134
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2.6.3.8 Design Example
Figure 71.
PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side
(1G/10G) Ethernet Channels
A10_DE_WRAPPER
Management
Master
ISSP
Clock and
Reset
Test Harness
XGMII
Test
Harness
Source
XGMII
Source
JTAG-toAvalon-MM
Master
TH0_ADDR = 0xF nnn
XGMII
Sink
XGMII
Sink
XGMII
GEN
XGMII
GEN
XGMII
CHK
XGMII
CHK
TH1_ADDR
... = 0xE nnn
...
A10_IP_WRAPPER
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
KR PHY IP
Registers CSR
Avalon-MM Slave
Registers CSR
NF
KR PHY IP
Reconfiguration
Avalon-MM Slave
NF Hard PHY Registers CSR
Native
KR PHY IP
ReconfigurationNF
Avalon-MMRegisters
Slave CSR
STD
Native Hard PHY Avalon-MM Slave
Reconfiguration
1588 Soft
TX PMA
TX PCS
FIFOs
Native Hard PHY
1588 Soft
STD
Native Hard PHY
FIFOs 1588 Soft
Sequencer
TX PMA
TX PCS
STD
FIFOs
TX PMA
TX PCS STD
Sequencer
TX PMA
10-GB
TX PCS
GMII
Sequencer
TX PCS
RS
Sequencer
10-GB
GMII
TX PCS
10-GB
RS
GMII
TX PCS 10-GB
Auto Neg
RS
GMII
TX PCS
cls 73
RS STD
Auto Neg
RX PCS
cls 73
STD
Auto Neg
Link Training
RX PCS
cls 73 Auto Neg
STD
cls 72
cls 73
RX PCS STD
Link Training
cls 72
RX PCS
10-GB
Link Training
RX PMA
RX PCS
cls 72Link Training
10-GB
RX PMA
cls 72
RX PCS
10-GB
RX PMA
RX PCS 10-GB
RX PMA
Divide
RX PCS
KR PHY IP
CH0: PHY_ADDR = 0x0
CH1: PHY_ADDR = 0x1
CH2: PHY_ADDR = 0x2
CH3: PHY_ADDR = 0x3
A10
Reconfiguration
Divide
Divide
Divide
Related Links
•
Arria 10 Transceiver PHY Design Examples
•
10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
2.6.3.9 Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported
simulators for this Quartus Prime software release:
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•
ModelSim Verilog
•
ModelSim VHDL
•
VCS Verilog
•
VCS VHDL
•
NCSIM Verilog
•
NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime
software optionally generates an IP functional simulation model.
2.6.4 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core
The Ethernet standard comprises many different PHY standards with variations in
signal transmission medium and data rates.
The 1G/10Gbps Ethernet PHY IP core targets the reconfigurable 10-Mbps/100-Mbps/1Gbps/10-Gbps data rates with one core dynamically. This Ethernet PHY interfaces to
1G/10GbE dual speed SFP+ pluggable modules, 10MB–10GbE 10GBASE-T, and 10MB/
100MB/1000MB 1000BASE-T copper external PHY devices to drive CAT-6/7 shielded
twisted pair cables, and chip-to-chip interfaces.
The 1G/10 Gbps Ethernet PHY (1G/10GbE ) IP function allows you to support the
following features of Ethernet standards:
•
1 GbE protocol as defined in Clause 36 of the IEEE 802.3-2008 Standard
•
GMII to connect the PHY with a media access control (MAC) as defined in Clause
35 of the IEEE 802.3-2008 Standard
•
Gigabit Ethernet Auto-negotiation as defined in Clause 37 of the IEEE 802.3-2008
Standard
•
10GBASE-R Ethernet protocol as defined in Clause 49 of the IEEE 802.3-2008
Standard
•
Single data rate (64 data bits and 8 control bits) XGMII to provide simple and
inexpensive interconnection between the MAC and the PHY as defined in Clause 46
of the IEEE 802.3-2008 Standard
•
SGMII 10-Mbps/100-Mbps/1-Gbps data rate where 10-Mbps/100-Mbps MII to
connect physical media with the MAC as defined in Clause 22 of the IEEE
802.3-2008 Standard
•
Forward Error correction(FEC) as defined in Clause 74 of the IEEE 802.3-2008
Standard
•
Precision time protocol (PTP) as defined in the IEEE 1588 Standard
The 1G/10Gbps Ethernet PHY IP Core allows you to implement the 1GbE protocol
using the Standard PCS and to implement the 10GbE protocol using Enhanced PCS
and PMA. You can switch dynamically between the 1G and 10G data rates using
dynamic reconfiguration to reprogram the core. Or, you can use the speed detection
option to automatically switch data rates based on received data.
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Figure 72.
Top Level Modules of the 1G/10GbE PHY IP Function
The Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data.
Intel Device with 10.3125-Gbps Transceivers
1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
TX XGMII Data
@156.25 MHz
To/From
1G/10Gb
Ethernet
MAC
Optional
1588 TX and
RX Latency
Adjust 1G
and 10G
PCS Reconfig
Request
Avalon-MM
PHY Management
Interface
RX XGMII Data
10 Gb
Ethernet
Enhanced PCS
w FEC
TX GMII/MII Data
@ 125 MHz
1 GigE
PCS
RX GMII Data
257.8 MHz
161.1 MHz
40 64
1 Gb SFP /
10 Gb SFP+
or XFP /
1G/10 Gb SFP+
Module/
RX Standard PHY
Serial
Product
Data
40 64 1.25 Gb/
10.3125 Gb
Hard PMA
1 Gb
Ethernet
Standard
PCS
Link
Status
Sequencer
(Optional)
To/From Modules in the PHY MegaCore
Control and Status
Registers
TX
Serial
Data
Reconfiguration
Block
ATX/CMU
TX PLL
For
10 GbE
322.265625 MHz
or 644.53125 MHz
Reference Clock
CMU
or fPLL
TX PLL
For 1 GbE
125 MHz
Reference Clock
Legend
Hard IP
1G/ 10 Gb
Ethernet
Network
Interface
Soft IP
Red = With FEC Option
An Avalon-MM slave interface provides access to the 1G/10GbE PHY IP Core registers.
These registers control many of the functions of the other blocks. Many of these bits
are defined in Clause 45 of IEEE 802.3ap-2008 Standard.
Related Links
•
IEEE Std 802.3ap-2008 Standard
•
Standard for a Precision Clock Synchronization Protocol for Networked
Measurement and Control Systems
2.6.4.1 1G/10GbE PHY Release Information
This topic provides information about this release of the 1G/10GbE PHY IP Core.
Table 127.
1G/10GbE Release Information
Item
Description
Version
16.0
Release Date
May 2016
Ordering Codes
IP-1G10GBASER (primary)
IPR-1G10GBASER (renewal code)
Product ID
0107
Vendor ID
6AF7
2.6.4.2 1G/10GbE PHY Performance and Resource Utilization
This topic provides performance and resource utilization for the 1G/10GbE PHY IP core
in Arria 10 devices.
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The following table shows the typical expected resource utilization for selected
configurations using the Quartus Prime software version 15.1. The numbers of ALMs
and logic registers are rounded up to the nearest 50.
Table 128.
1GbE/10GbE PHY Performance and Resource Utilization
Variant
ALMs
ALUTs
Registers
M20K
1G/10GbE PHY with IEEE 1588 v2
2650
3950
5100
6
1G/10GbE PHY
1500
2350
2850
2
1G/10GbE PHY with FEC
1500
2350
2850
2
2.6.4.3 1G/10GbE PHY Functional Description
Figure 73.
1G/10GbE PHY Block Diagram
Avalon-MM
User PCS Reconfiguration
Registers
MGMT_CLK
Sequencer
(Auto-Speed
Detect)
TX_GMII_DATA
PCS Reconfiguration I/F
PMA Reconfiguration I/F
8+2
GigE
PCS
XGMII_TX_CLK
TX_XGMII_DATA
1588
FIFO
64 + 8
Reconfiguration
Block
HSSI Reconfiguration Requests
Native PHY
40/32
Standard TX PCS
TX PMA
tx_pld_clk tx_pma_clk
Auto-Negotiation
Clause 73
Link Training
Clause 72
66
Enhanced TX PCS
40
tx_pld_clk tx_pma_clk
40
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
1588
FIFO
rx_pld_clk rx_pma_clk
XGMII_RX_CLK
RX_GMII_DATA
Standard RX PCS
8+2
GigE
PCS
40/32
Enhanced RX PCS
RX PMA
rx_pld_clk rx_pma_clk
RX_PMA_CLKOUT
RX_DIV_CLKOUT
Soft Logic
Divide by 33/1/2
Hard Logic
Not Available
Standard and Enhanced PCS Datapaths
The Standard PCS and PMA inside the Native PHY are configured as the Gigabit
Ethernet PHY. The Enhanced PCS and PMA inside the Native PHY are configured as the
10GBASE-R PHY. Refer to the Standard PCS and Enhanced PCS architecture chapters
for more details.
Sequencer
The Sequencer controls the start-up sequence of the PHY IP, including reset and
power-on. It selects which PCS (1G or 10G) and PMA interface is active. The
Sequencer interfaces to the reconfiguration block to request a change from one data
rate to the other data rate.
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GigE PCS
The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII
functionality.
Soft Enhanced PCS FIFO for IEEE 1588v2
In IEEE 1588v2 mode, the enhanced PCS FIFOs for both TX and RX are constructed in
soft IP to include the latency information via the latency adjustment ports. For more
information about the required latency information in the MAC as part of the Precision
Time Protocol implementation, refer to the 10-Gbps Ethernet MAC IP Function User
Guide.
Reconfiguration Block
The reconfiguration logic performs the Avalon-MM writes to the PHY for both PCS and
PMA reconfiguration. The following figure shows the details of the reconfiguration
blocks. The Avalon-MM master accepts requests from the PMA or PCS controller. It
performs the Read-Modify-Write or Write commands using the Avalon-MM interface.
The PCS controller receives data rate change requests from the Sequencer and
translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Figure 74.
Reconfiguration Block Details
The 1G/10GbE PHY IP core is very flexible. For example, you can configure it with or without IEEE 1588v2, and
with or without FEC in the enhanced PCS datapath.
MGMT_CLK
(2)
rcfg_data
rcfg_data
rcfg_data
PCS
Reconfiguration
Interface
PCS
Controller
rcfg_data
(1)
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM
Decoder
PMA Controller
HSSI
Reconfiguration
Requests
Avalon-MM Bus
TX EQ Controller
PMA
Reconfiguration
Interface
DFE Controller
Avalon-MM reconfig_busy Signal
CTLE Controller
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
•
Arria 10 Standard PCS Architecture on page 463
•
Arria 10 PMA Architecture on page 431
•
10-Gbps Ethernet MAC IP Function User Guide.
For more information about latency in the MAC as part of the Precision Time
Protocol implementation.
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2.6.4.4 Clock and Reset Interfaces
You can use a fPLL or a CMU PLL to generate the clock for the TX PMA for the 1G data
rate. For the 10G data rate, you can use the ATX PLL or the CMU PLL. For the 1G data
rate, the frequency of the TX and RX clocks is 125 MHz, which is 1/8 of the MAC data
rate. For the 10G data rate, the frequency of TX and RX clocks is 156.25 MHz, 1/64 of
the MAC data rate. You can generate the 156.25 MHz clock directly by using a fPLL, or
you can divide the clock from TX PLL by 33. The 1G/10GbE PHY does not support
bonded clocks.
The following figure provides an overview of the clocking for this core.
Figure 75.
Clocks for Standard and 10G PCS and TX PLLs
1GbE/10GbE PHY
GMII TX
Data & Control SGMII
PCS
tx_coreclkin_1g
125 MHz
8+1
10 TX data
Standard TX PCS
TX PMA
tx_pld_clk tx_pma_clk
tx_pld_clk
64 + 8
XGMII TX Data & Control
fractional
PLL
(instantiate
separately)
GMII RX
Data & Control SGMII
PCS
red = datapath includes FEC
Enhanced TX PCS
64 + 8
xgmii_tx_clk
156.25 MHz
Standard RX PCS
rx_pld_clk
rx_coreclkin_1g
125 MHz
XGMII RX Data & Control
xgmii_rx_clk
156.25 MHz
64 + 8
40
TX PLL
64
TX data
TX PLL
tx_pld_clk tx_pma_clk
8+1
10
RX PMA
60
64 + 8
rx_pld_clk rx_pma_clk
pll_ref_clk_1g
125 MHz
pll_ref_clk_10g
644.53125 MHz
or
322.265625 MHz
RX data
rx_pma_clk
Enhanced RX PCS
TX serial data
serial data
recovered clk
125 MHz
40 257.8125 MHz (1)
161.1 MHz (2)
Notes:
1. 257.8125 MHz is for 10GbE.
2. 161.1 MHz is the FEC clock for 10GbE.
The following table describes the clock and reset signals.
Table 129.
Clock and Reset Signals
Signal Name
Direction
Description
tx_serial_clk_10g
Input
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g
Input
The clock from the external 1G PLL to drive the TX high speed serial
interface (HSSI) circuits. Connected to the tx_serial_clk input of
the native PHY.
rx_cdr_ref_clk_10g
Input
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
rx_cdr_refclk_1g
Input
The RX 1G PLL reference clock to drive the RX HSSI circuits.
Connected to the rx_cdr_refclk input of the native PHY.
mgmt_clk
Input
Avalon-MM clock and control system clock. Its frequency range is
100 MHz to 125 MHz.
mgmt_clk_reset
Input
When asserted, it resets the whole PHY.
continued...
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Signal Name
Direction
Description
xgmii_tx_clk
Input
Clock for XGMII TX interface with MAC. Can be connected to
tx_div_clkout. This drives the tx_coreclkin port of the Native
PHY.
xgmii_rx_clk
Input
The clock for the XGMII RX interface with the MAC. Intel
recommends connecting it directly to a PLL for use with TSE. This
drives rx_coreclkin of the native PHY. Its frequency is 156.25 or
312.5 MHz.
tx_clkout
Output
Transmit parallel clock. It is sourced from
out_pld_pcs_tx_clk_out on the HSSI. This could be used to
provide the XGMII clocks or the GMII clocks, though if the PHY is
reconfigured, the frequency will change. Its frequency is 125,
156.25, 161, 258, or 312.5 MHz.
rx_clkout
Output
Receive parallel clock. It is sourced from
out_pld_pcs_rx_clk_out on the HSSI. If the PHY is reconfigured,
the frequency will change. Its frequency is 125, 156.25, 161, 258, or
312.5 MHz.
tx_pma_clkout
Output
Transmit PMA clock. This is the clock for the 1588 mode TX FIFO and
the 1G TX and RX PCS parallel data interface. Note: Use
tx_div_clkout or xgmii_tx_clk for 10G TX datapath clocking.
This clock is provided for the 1G mode GMII/MII data and SyncE
mode where the clock can be used as a reference to lock an external
clock source. Its frequency is 125, 161, or 258 MHz.
rx_pma_clkout
Output
Receive PMA clock. This is the clock for the 1588 mode RX FIFO and
the 1G RX FIFO. Note: Use tx_div_clkout or xgmii_rx_clk for
10G RX datapath clocking. This clock is provided for the SyncE mode
where the clock can be used as a reference to lock an external clock
source. Its frequency is 125, 161, or 258 MHz.
tx_div_clk
Output
This is the transmit div33 clock, which is sourced from the Native
PHY tx_pma_div_clkout. It could be connected to the
xgmii_tx_clk and xgmii_rx_clk clock inputs to drive the MAC
interface, though if the PHY is reconfigured to 1G mode, the
frequency will change. Its frequency is 125, 156.25, or 312.5 MHz.
rx_div_clk
Output
This is the receive div33 clock, which is recovered from the received
data. It drives the Auto Negotiation (AN) and Link Training (LT) logic
and is sourced from the Native PHY rx_pma_div_clkout port.
Note: Use tx_clkout or xgmii_rx_clk for 10G TX datapath
clocking. If the PHY is reconfigured to 1G mode, the frequency will
change. Its frequency is 125, 156.25, or 312.5 MHz.
calc_clk_1g
Input
This is the clock for the GIGE PCS 1588 mode. To achieve high
accuracy for all speed modes, the recommended frequency for
calc_clk_1g is 80 MHz. In addition, the 80 MHz clock should have
the same parts per million (ppm) as the 125 MHz pll_ref_clk_1g
input. The random error without a rate match FIFO mode is:
• ±1 ns at 1000 Mbps
• ± 5 ns at 100 Mbps
• ± 25 ns at 10 Mbps
tx_analogreset
Input
Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
tx_digitalreset
Input
Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
rx_analogreset
Input
Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
continued...
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Signal Name
Direction
Description
rx_digitalreset
Input
Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
usr_seq_reset
Input
Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk.
rx_data_ready
Output
When asserted, indicates that you can start to send the 10G data.
Synchronous to xgmii_rx_clk.
Related Links
•
Input Reference Clock Sources on page 360
•
PLLs on page 337
2.6.4.5 Parameterizing the 1G/10GbE PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the
Backplane-KR or 1Gb/10Gb Ethernet variant. The 1Gb/10Gb Ethernet variant
(1G/10GbE) does not implement the link training and auto-negotiation functions.
Complete the following steps to parameterize the 1Gb/10Gb Ethernet PHY IP core in
the parameter editor:
1.
Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 31.
2. Select 1Gb/10Gb Ethernet from the IP variant list located under Ethernet
Intel FPGA IP Core Type.
Note:
3.
Use the parameter values in the tables in 10GBASE-R Parameters on page 138,
10M/100M/1Gb Ethernet Parameters on page 170 , Speed Detection Parameters
on page 140, and PHY Analog Parameters on page 171 as a starting point. Or, you
can select the BackPlane_wo_1588 option in the Presets tab on the right side
of the IP Parameter Editor. You can then modify the setting to meet your specific
requirements.
4.
Click Generate HDL to generate the 1Gb/10Gb Ethernet IP core top-level HDL
file.
You might observe timing violations. If the timing path is within the IP, you can ignore
these violations. This will be fixed in a future release of the Intel Quartus Prime
software.
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
General Options on page 137
•
10GBASE-R Parameters on page 138
•
10M/100M/1Gb Ethernet Parameters on page 170
•
Speed Detection Parameters on page 140
•
PHY Analog Parameters on page 171
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2.6.4.5.1 General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 130.
General Options Parameters
Parameter Name
Options
Description
Enable internal PCS
reconfiguration logic
On
Off
This parameter is only an option when SYNTH_SEQ = 0. When
set to 0, it does not include the reconfiguration module or
expose the start_pcs_reconfig or rc_busy ports. When set
to 1, it provides a simple interface to initiate reconfiguration
between 1G and 10G modes.
Enable IEEE 1588 Precision
Time Protocol
On
Off
When you turn on this parameter, you enable the IEEE 1588
Precision Time Protocol logic for both 1G and 10G modes.
Enable M20K block ECC
protection
On
Off
When you turn on this parameter, you enable error correction
code (ECC) support on the embedded Nios CPU system. This
parameter is only valid for the backplane variant.
Enable tx_pma_clkout port
On
Off
When you turn on this parameter, the tx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_pma_clkout port
On
Off
When you turn on this parameter, the rx_pma_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_divclk port
On
Off
When you turn on this parameter, the tx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_divclk port
On
Off
When you turn on this parameter, the rx_divclk port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable tx_clkout port
On
Off
When you turn on this parameter, the tx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable rx_clkout port
On
Off
When you turn on this parameter, the rx_clkout port is
enabled. Refer to the Clock and Reset Interfaces section for
more information about this port.
Enable Hard PRBS support
and ADME support
On
Off
When you turn on this parameter, you enable the ADME and
Hard PRBS data generation and checking logic in the Native PHY.
The transceiver toolkit (TTK) requires ADME to be enabled in the
Native PHY IP core.
Reference clock frequency
644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
rx_block_lock and rx_hi_ber output.
Include FEC sublayer
On
Off
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS. This is applicable
only for the 10G mode.
Set FEC_ability bit on
power up and reset
On
Off
When you turn on this parameter, the core sets the Assert KR
FEC Ability bit (0xB0[16]) FEC ability bit during power up
On
Off
When you turn on this parameter, the core sets the KR FEC
Request bit (0xB0[18]) during power up and reset, causing
the core to request the FEC ability during Auto Negotiation. This
option is required for FEC functionality.
Set FEC_Enable bit on
power up and reset
When you turn this option on, the core includes the
and reset, causing the core to assert the FEC ability. This option
is required for FEC functionality.
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Related Links
Clock and Reset Interfaces on page 141
2.6.4.5.2 10GBASE-R Parameters
The 10GBASE-R parameters specify basic features of the 10GBASE-R PCS. The FEC
options also allow you to specify the FEC ability.
Table 131.
10GBASE-R Parameters
Parameter Name
Options
Description
10GbE Reference clock
frequency
644.53125 MHz
322.265625 MHz
Specifies the input reference clock frequency. The default is
322.265625 MHz.
Enable additional control
and status ports
On
Off
When you turn on this parameter, the core includes the
rx_block_lock and rx_hi_ber ports.
Table 132.
FEC Options
Parameter Name
Include FEC sublayer
Options
On
Off
Description
When you turn on this parameter, the core includes logic to
implement FEC and a soft 10GBASE-R PCS.
2.6.4.5.3 10M/100M/1Gb Ethernet Parameters
The 10M/100M/1GbE parameters allow you to specify options for the MII interface and
the 1GbE data rate.
Table 133.
10M/100M/1Gb Ethernet
Parameter Name
Options
Description
Enable 1Gb Ethernet
protocol
On
Off
When you turn this option on, the core includes the GMII
interface and related logic.
Enable 10Mb/100Mb
Ethernet functionality
On
Off
When you turn this option on, the core includes the MII PCS. It
also supports 4-speed mode to implement a 10M/100M interface
to the MAC for the GbE line rate.
PHY ID (32 bits)
32-bit value
An optional 32-bit value that serves as a unique identifier for a
particular type of PCS. The identifier includes the following
components:
• Bits 3-24 of the Organizationally Unique Identifier (OUI)
assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which is
0x00000000.
PHY core version (16 bits)
16-bit value
This is an optional 16-bit value that identifies the PHY core
version.
2.6.4.5.4 Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners
that support 1G/10GbE but have disabled Auto-Negotiation. During Auto-Negotiation,
if AN cannot detect Differential Manchester Encoding (DME) pages from a link partner,
the Sequencer reconfigures to 1GbE and 10GbE modes (Speed/Parallel detection) until
it detects a valid 1G or 10GbE pattern.
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Table 134.
Speed Detection
Parameter Name
Options
Description
Enable automatic speed
detection
On
Off
When you turn this option On, the core includes the Sequencer
block that sends reconfiguration requests to detect 1G or 10GbE
when the Auto Negotiation block is not able to detect AN data.
Avalon-MM clock frequency
100-162 MHz
Specifies the clock frequency for phy_mgmt_clk.
Link fail inhibit time for
10Gb Ethernet
504 ms
Specifies the time before link_status is set to FAIL or OK. A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 500-510 ms. For
more information, refer to "Clause 73 Auto Negotiation for
Backplane Ethernet" in IEEE Std 802.3ap-2007.
Link fail inhibit time for
1Gb Ethernet
40-50 ms
Specifies the time before link_status is set to FAIL or OK . A
link fails if the link_fail_inhibit_time has expired before
link_status is set to OK. The legal range is 40-50 ms.
Enable PCS-Mode port
On
Off
Enables or disables the PCS-Mode port.
2.6.4.5.5 PHY Analog Parameters
You can specify analog parameters using the Intel Quartus Prime Assignment Editor,
the Pin Planner, or the Intel Quartus Prime Settings File (.qsf).
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2.6.4.6 1G/10GbE PHY Interfaces
Figure 76.
1G/10GbE PHY Top-Level Signals
1G/10GbE Top-Level Signals
XGMII
GMII
Interfaces
Avalon-MM PHY
Management
Interface
Clocks and
Reset
Interface
xgmii_tx_dc[71:0]
xgmii_tx_clk
xgmii_rx_dc[71:0]
xgmii_rx_clk
gmii_tx_d[7:0]
gmii_rx_d[7:0]
gmii_tx_en
gmii_tx_err
gmii_rx_err
gmii_rx_dv
mgmt_clk
mgmt_clk_reset
mgmt_address[10:0]
mgmt_writedata[31:0]
mgmt_readdata[31:0]
mgmt_write
mgmt_read
mgmt_waitrequest
tx_serial_clk_1g
tx_serial_clk_10g
rx_cdr_ref_clk_10g
rx_cdr_ref_clk_1g
tx_pma_clkout
rx_pma_clkout
tx_clkout
rx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
usr_seq_reset
rx_serial_data
tx_serial_data
led_char_err
led_link
led_disp_err
led_an
led_panel_link
rx_block_lock
rx_hi_ber
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
rx_syncstatus
tx_pcfifo_error_1g
rx_pcfifo_error_1g
rx_clkslip
rx_data_ready
rx_latency_adj_1g[21:0]
tx_latency_adj_1g[21:0]
mii_tx_d[3:0]
mii_tx_en
mii_tx_err
mii_rx_d[3:0]
mii_rx_dv
mii_rx_err
mii_col
mii_crs
Transceiver
Serial Data
Status
MII
Interfaces
The block diagram shown in the parameter editor labels the external pins with the
interface type and places the interface name inside the box. The interface type and
name are provided in the _hw.tcl file. If you turn on Show signals, the block
diagram displays all top-level signal names. For more information about _hw.tcl
files, refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel
Quartus Prime Handbook.
Note:
Intel is deprecating some of the signals shown in this figure. The descriptions of these
signals identifies them as not functional.
Related Links
Component Interface Tcl Reference
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2.6.4.6.1 Clock and Reset Interfaces
Table 135.
Clock and Reset Signals
Signal Name
Direction
Description
tx_serial_clk_10g
Input
High speed clock from the 10G PLL to drive 10G PHY TX PMA. The
frequency of this clock is 5.15625 GHz.
tx_serial_clk_1g
Input
High speed clock from 1G PLL to drive the 1G PHY TX PMA. This clock
is not required if GbE is not used. The frequency of this clock is 625
MHz.
rx_cdr_ref_clk_10g
Input
10G PHY RX PLL reference clock. This clock frequency can be
644.53125 MHz or 322.2656 MHz.
rx_cdr_ref_clk_1g
Input
1G PHY RX PLL reference clock. The frequency is 125 MHz. This clock
is only required if 1G is enabled.
tx_pma_clkout
Output
Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
rx_pma_clkout
Output
Clock used to drive the 10G RX PCS and 1G RX PCS parallel data. For
example, when the hard PCS is reconfigured to the 10G mode
without FEC enabled, the frequency is 257.81 MHz. The frequency is
161.13 MHz for 10G with FEC enabled.
tx_clkout
Output
XGMII/GMII TX clock for the TX parallel data source interface. This
clock frequency is 257.81 MHz in 10G mode, and 161.13 MHz with
FEC enabled.
rx_clkout
Output
XGMII RX clock for the RX parallel data source interface. This clock
frequency is 257.81 in 10G mode, and 161.13 MHz with FEC
enabled.
tx_pma_div_clkout
Output
The divided 33 clock from the TX serializer. You can use this clock for
the for xgmii_tx_clk or xgmii_rx_clk. The frequency is 156.25
MHz for 10G. The frequencies are the same whether or not you
enable FEC.
rx_pma_div_clkout
Output
The divided 33 clock from CDR recovered clock. The frequency is
156.25 MHz for 10G. The frequencies are the same whether or not
you enable FEC. This clock is not used for clocking the 10G RX
datapath.
tx_analogreset
Input
Resets the analog TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
tx_digitalreset
Input
Resets the digital TX portion of the transceiver PHY. Synchronous to
mgmt_clk.
rx_analogreset
Input
Resets the analog RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
rx_digitalreset
Input
Resets the digital RX portion of the transceiver PHY. Synchronous to
mgmt_clk.
Input
usr_seq_reset
Resets the sequencer. Initiates a PCS reconfiguration, and may
restart AN, LT or both if these modes are enabled. Synchronous to
mgmt_clk.
Related Links
•
Input Reference Clock Sources on page 360
•
PLLs on page 337
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2.6.4.6.2 Data Interfaces
Table 136.
XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name
Direction
Clock Domain
Description
10GbE XGMII Data Interface
xgmii_tx_dc[71:0
]
Input
xgmii_tx_clk
Input
xgmii_rx_dc[71:0
]
Output
xgmii_rx_clk
Input
Synchronous to
xgmii_tx_clk
XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
Clock signal
Clock for single data rate (SDR) XGMII TX interface to the
MAC. It should connect to xgmii_rx_clk. This clock can be
connected to the tx_div_clkout; however, Intel
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
Synchronous to
RX XGMII data and control for 8 lanes. Each lane consists of 8
bits of data and 1 bit of control.
xgmii_rx_clk
Clock signal
Clock for SDR XGMII RX interface to the MAC. This clock can
be connected to the tx_div_clkout ; however, Intel
recommends that you connect it to a PLL for use with the
Triple Speed Ethernet IP function. The frequency is 125 MHz
for 1G and 156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you enable FEC.
2.6.4.6.3 XGMII Mapping to Standard SDR XGMII Data
Table 137.
TX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit TX XGMII data bus format is different than the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
SDR XGMII Signal Name
Description
xgmii_tx_dc[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_tx_dc[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_tx_dc[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_tx_dc[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_tx_dc[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_tx_dc[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_tx_dc[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_tx_dc[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_tx_dc[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_tx_dc[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_tx_dc[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_tx_dc[53]
xgmii_sdr_ctrl[5]
Lane 5 control
continued...
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Signal Name
SDR XGMII Signal Name
Description
xgmii_tx_dc[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_tx_dc[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_tx_dc[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_tx_dc[71]
xgmii_sdr_ctrl[7]
Lane 7 control
Table 138.
RX XGMII Mapping to Standard SDR XGMII Interface
The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the
mapping of this non-standard format to the standard SDR XGMII interface.
Signal Name
XGMII Signal Name
Description
xgmii_rx_dc[7:0]
xgmii_sdr_data[7:0]
Lane 0 data
xgmii_rx_dc[8]
xgmii_sdr_ctrl[0]
Lane 0 control
xgmii_rx_dc[16:9]
xgmii_sdr_data[15:8]
Lane 1 data
xgmii_rx_dc[17]
xgmii_sdr_ctrl[1]
Lane 1 control
xgmii_rx_dc[25:18]
xgmii_sdr_data[23:16]
Lane 2 data
xgmii_rx_dc[26]
xgmii_sdr_ctrl[2]
Lane 2 control
xgmii_rx_dc[34:27]
xgmii_sdr_data[31:24]
Lane 3 data
xgmii_rx_dc[35]
xgmii_sdr_ctrl[3]
Lane 3 control
xgmii_rx_dc[43:36]
xgmii_sdr_data[39:32]
Lane 4 data
xgmii_rx_dc[44]
xgmii_sdr_ctrl[4]
Lane 4 control
xgmii_rx_dc[52:45]
xgmii_sdr_data[47:40]
Lane 5 data
xgmii_rx_dc[53]
xgmii_sdr_ctrl[5]
Lane 5 control
xgmii_rx_dc[61:54]
xgmii_sdr_data[55:48]
Lane 6 data
xgmii_rx_dc[62]
xgmii_sdr_ctrl[6]
Lane 6 control
xgmii_rx_dc[70:63]
xgmii_sdr_data[63:56]
Lane 7 data
xgmii_rx_dc[71]
xgmii_sdr_ctrl[7]
Lane 7 control
2.6.4.6.4 GMII Interface
The GMII interface signals drive data to and from the PHY.
Table 139.
GMII Interface Ports
Signal Name
Direction
Description
gmii_tx_d[7:0]
Input
Data to be encoded and sent to the link partner. This signal
is clocked with tx_clkout.
gmii_tx_en
Input
The GMII TX control signal. Synchronous to tx_clkout.
gmii_tx_err
Input
The GMII TX error signal. Synchronous to tx_clkout.
gmii_rx_d[7:0]
Output
Data to be encoded and sent to the link partner. This signal
is clocked with tx_clkout.
gmii_rx_dv
Output
The GMII RX control signal. Synchronous to tx_clkout.
continued...
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Signal Name
Direction
Description
gmii_rx_err
Output
The GMII RX error signal. Synchronous to tx_clkout.
led_char_err
Output
10-bit character error. Asserted for one rx_clkout_1g
cycle when an erroneous 10-bit character is detected.
led_link
Output
When asserted, this signal indicates successful link
synchronization.
led_disp_err
Output
When asserted, this signal indicates a 10-bit running
disparity error. Asserted for one rx_clkout_1g cycle when
a disparity error is detected. A running disparity error
indicates that errors were detected on more received
groups than the previous and possibly current groups.
led_an
Output
This signal indicates the auto-negotiation status. The PCS
function asserts this signal when an autonegotiation
completes.
2.6.4.6.5 Serial Data Interface
Table 140.
Serial Data Signals
Signal Name
Direction
Description
rx_serial_data
Input
RX serial input data
tx_serial_data
Output
TX serial output data
2.6.4.6.6 Control and Status Interfaces
Table 141.
Control and Status Signals
Signal Name
led_link
Direction
Output
Clock Domain
Synchronous to
Description
When asserted, indicates successful link synchronization.
tx_clkout
led_disp_err
Output
Synchronous to
rx_clkout
led_an
Output
Synchronous to
rx_clkout
led_panel_link
Output
Synchronous to
mgmt_clk
Disparity error signal indicating a 10-bit running disparity
error. Asserted for one rx_clkout_1g cycle when a
disparity error is detected. A running disparity error
indicates that more than the previous and perhaps the
current received group had an error.
Clause 37 Auto-negotiation status. The PCS function
asserts this signal when auto-negotiation completes.
When asserted, this signal indicates the following
behavior:
Mode
1000 Base-X without Autonegotiation
Behavior
When asserted, indicates
successful link
synchronization.
continued...
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Signal Name
Direction
Clock Domain
Description
Mode
rx_block_lock
Output
Synchronous to
rx_clkout
rx_hi_ber
Output
Synchronous to
rx_clkout
Behavior
SGMII mode without Autonegotiation
When asserted, indicates
successful link
synchronization.
1000 Base-X with Autonegotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
SGMII mode with MAC
mode Auto-negotiation
Clause 37 Auto-negotiation
status. The PCS function
asserts this signal when
auto-negotiation completes.
Asserted to indicate that the block synchronizer has
established synchronization.
Asserted by the BER monitor block to indicate a Sync
Header high bit error rate greater than 10-4.
rx_is_lockedtodat
a
Output
Asynchronous signal
When asserted, indicates the RX channel is locked to input
data.
tx_cal_busy
Output
Synchronous to
When asserted, indicates that the TX channel is being
calibrated.
mgmt_clk
rx_cal_busy
Output
Synchronous to
mgmt_clk
When asserted, indicates that the RX channel is being
calibrated.
tx_pcfifo_error_1
g
Output
N/A
When asserted, indicates that the standard PCS TX phase
compensation FIFO is either full or empty.
rx_pcfifo_error_1
g
Output
N/A
When asserted, indicates that the Standard PCS RX phase
compensation FIFO is either full or empty.
lcl_rf
Input
Synchronous to
When asserted, indicates a Remote Fault (RF).The MAC
sends this fault signal to its link partner. Bit D13 of the
Auto Negotiation Advanced Remote Fault register
(0xC2) records this error.
xgmii_tx_clk
rx_clkslip
Input
Asynchronous signal
When asserted, the deserializer either skips one serial bit
or pauses the serial clock for one cycle to achieve word
alignment. As a result, the period of the parallel clock
could be extended by 1 unit interval (UI) during the clock
slip operation.This is an optional control input signal.
rx_data_ready
Output
Synchronous to
When asserted, indicates that the MAC can begin sending
data to the PHY.
xgmii_rx_clk
rx_latency_adj_10
g[15:0]
Output
Synchronous to
xgmii_rx_clk
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the RX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
continued...
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Signal Name
Direction
tx_latency_adj_10
g[15:0]
Output
rx_latency_adj_1
g[21:0]
Output
tx_latency_adj_1
g[21:0]
Output
Clock Domain
Synchronous to
xgmii_tx_clk
Synchronous to
gmii_rx_clk
Synchronous to
gmii_tx_clk
Description
When you enable 1588, this signal outputs the real time
latency in XGMII clock cycles (156.25 MHz) for the TX
PCS and PMA datapath for 10G mode. Bits 0 to 9
represent the fractional number of clock cycles. Bits 10 to
15 represent the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the RX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
When you enable 1588, this signal outputs the real time
latency in GMII clock cycles (125 MHz) for the TX PCS and
PMA datapath for 1G mode. Bits 0 to 9 represent the
fractional number of clock cycles. Bits 10 to 21 represent
the number of clock cycles.
2.6.4.6.7 MII
Table 142.
MII Signals
Name
Directi
on
Description
MII Transmit Interface
mii_tx_d[3:0]
Input
MII transmit data bus.
mii_tx_en
Input
Assert this signal to indicate that the data on mii_tx_d[3:0]is valid.
mii_tx_err
Input
Assert this signal to indicate to the PHY device that the frame sent is invalid.
mii_rx_d[3:0]
Output
MII receive data bus.
mii_rx_dv
Output
Asserted to indicate that the data on mii_rx_d[3:0]is valid. The signal stays
asserted during frame reception, from the first preamble byte until the last byte of
the CRC field is received.
mii_rx_err
Output
Asserted by the PHY to indicate that the current frame contains errors.
mii_col
Output
Collision detection. Asserted by the PCS function to indicate that a collision was
detected during frame transmission.
mii_crs
Output
Carrier sense detection. Asserted by the PCS function to indicate that a transmit or
receive activity is detected on the Ethernet line.
MII Receive Interface
2.6.4.6.8 Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change
between 1G and 10G data rates.
Table 143.
Dynamic Reconfiguration Interface Signals
Signal Name
rc_busy
Direction
Output
Clock Domain
Synchronous to
mgmt_clk
Description
When asserted, indicates that reconfiguration is in
progress. Synchronous to the mgmt_clk. This signal is
only exposed under the following condition:
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Signal Name
Direction
Clock Domain
Description
•
start_pcs_reconf
ig
Input
mode_1g_10gbar
Input
Synchronous to
mgmt_clk
Synchronous to
mgmt_clk
Turn on Enable internal PCS reconfiguration logic
When asserted, initiates reconfiguration of the PCS.
Sampled with the mgmt_clk. This signal is only exposed
under the following condition:
• Turn on Enable internal PCS reconfiguration logic
This signal selects either the 1G or 10G tx-parallel-data
going to the PCS. It is only used for the 1G/10G
application (variant) under the following circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
2.6.4.7 Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 144.
Avalon-MM Interface Signals
Signal Name
Direction
Clock Domain
Description
mgmt_clk
Input
Clock
The clock signal that controls the Avalon-MM PHY management
interface. If you plan to use the same clock for the PHY
management interface and transceiver reconfiguration, you must
restrict the frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
mgmt_clk_res
et
Input
Asynchronous reset
Resets the PHY management interface. This signal is active high
and level sensitive.
mgmt_addr[10
:0]
Input
Synchronous to
11-bit Avalon-MM address.
mgmt_writeda
ta[31:0]
Input
mgmt_readdat
a[31:0]
Output
mgmt_write
Input
mgmt_clk
Synchronous to
Input data.
mgmt_clk
Synchronous to
Output data.
mgmt_clk
Synchronous to
Write signal. Active high.
mgmt_clk
Input
mgmt_read
Synchronous to
Read signal. Active high.
mgmt_clk
mgmt_waitreq
uest
Output
Synchronous to
mgmt_clk
When asserted, indicates that the Avalon-MM slave interface is
unable to respond to a read or write request. When asserted,
control signals to the Avalon-MM slave interface must remain
constant.
Related Links
Avalon Interface Specifications
2.6.4.7.1 Register Definitions
The Avalon-MM master interface signals provide access to the control and status
registers.
The following table specifies the control and status registers that you can access over
the Avalon-MM interface. A single address space provides access to all registers.
Note:
Unless otherwise indicated, the default value of all registers is 0.
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Note:
Do not write to any register that is not specified.
Table 145.
1G/10GbE Register Definitions
Word
Addr
0x4B0
0x4B1
Bit
R/W
Name
Description
0
RW
Reset SEQ
When set to 1, resets the 10GBASE-KR sequencer (auto rate
detect logic), initiates a PCS reconfiguration, and may restart
Auto-Negotiation (AN), Link Training (LT), or both if AN and LT are
enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these
modes. This reset self clears.
1
RW
Disable AN Timer
AN disable timer. If disabled ( Disable AN Timer = 1) , AN
may get stuck and require software support to remove the
ABILITY_DETECT capability if the link partner does not include
this feature. In addition, software may have to take the link out of
loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT
state. To enable this timer set Disable AN Timer = 0.
2
RW
Disable LF Timer
When set to 1, disables the Link Fail timer. When set to 0, the
Link Fault timer is enabled.
3
RW
fail_lt_if_ber
When set to 1, the last LT measurement is a non-zero number.
Treat this as a failed run. 0 = Normal.
7:4
RW
SEQ Force Mode[2:0]
Other than the "No force" mode (0x4B0[7:4] = 4'b0000), you
must write the Reset SEQ (0x4B0[0]) to 1 when switching to the
required data mode by changing (forcing) the 0x4B0[7:4] bits.
The following encodings are defined:
• 0000: No force
• 0001: GbE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
8
RW
Enable Arria 10
Calibration
When set to 1, it enables the Arria 10 HSSI reconfiguration
calibration as part of the PCS dynamic reconfiguration. 0 skips the
calibration when the PCS is reconfigured.
16
RW
KR FEC enable 171.0
When set to 1, FEC is enabled. When set to 0, FEC is disabled.
Resets to the CAPABLE_FEC parameter value.
17
RW
KR FEC enable err
ind 171.1
When set to 1, KR PHY FEC decoding errors are signaled to the
PCS. When set to 0, FEC errors are not signaled to the PCS. See
Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18
RW
KR FEC request
When set to 1, enables the FEC request. When this bit changes,
you must assert the Reset SEQ bit (0x4B0[0]) to renegotiate
with the new value. When set to 0, disables the FEC request.
0
R
SEQ Link Ready
When asserted, the sequencer indicates the link is ready.
1
R
SEQ AN timeout
When asserted, the sequencer has had an AN timeout. This bit is
latched and is reset when the sequencer restarts AN.
2
R
SEQ LT timeout
When set, indicates that the sequencer has had a timeout.
13:8
R
SEQ Reconfig
Mode[5:0]
Specifies the sequencer mode for PCS reconfiguration. The
following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GbE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 10G FEC mode
continued...
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Word
Addr
0x4B2
Bit
R/W
0x4C0
0x4C1
0x4C2
Description
16
R
KR FEC ability
170.0
When set to 1, indicates that the 10GBASE-KR PHY supports FEC.
Set as parameter SYNTH_FEC. For more information, refer to
Clause 45.2.1.84 of IEEE 802.3ap-2007.
17
R
KR FEC err ind
ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY is capable of
reporting FEC decoding errors to the PCS. For more information,
refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0:10
RW
Reserved
—
11
RWSC
KR FEC TX Error
Insert
Writing a 1 inserts one error pulse into the TX FEC depending on
the transcoder and burst error settings.
31:15
RWSC
Reserved
—
Reserved for 40G KR
Intentionally left empty for address compatibility with 40G MAC +
PHY KR solutions.
0x4B5
to
0x4BF
(35)
Name
0
RW
AN enable
When set to 1, enables the AN function. The default value is 1.
For additional information, refer to bit 7.0.12 in Clause 73.8
Management Register Requirements of IEEE 802.3ap-2007.
1
RW
AN base pages ctrl
When set to 1, the user base pages are enabled. You can send
any arbitrary data via the user base page low/high bits. When set
to 0, the user base pages are disabled and the state machine
generates the base pages to send.
2
RW
AN next pages ctrl
When set to 1, the user next pages are enabled. You can send
any arbitrary data via the user next page low/high bits. When set
to 0, the user next pages are disabled. The state machine
generates the null message to send as next pages.
3
RW
Local device remote
fault
When set to 1, the local device signals Remote Faults in the AN
pages. When set to 0, a fault has not occurred.
4
RW
Force TX nonce
value
When set to 1, forces the TX nonce value to support some UNH
testing modes. When set to 0, this is normal operation.
5
RW
Override AN
Parameters Enable
When set to 1, overrides the AN_TECH, AN_FEC, and AN_PAUSE
parameters and uses the bits in 0xC3 instead. You must reset the
Sequencer to reconfigure and restart into AN mode. When set to
0, this is normal operation and is used with 0xB0 bit 0 and 0xC3
bits[30:16].
0
RW
Reset AN
When set to 1, resets all the 10GBASE-KR AN state machines.
This bit is self clearing.
4
RW
Restart AN TX SM
When set to 1, restarts the 10GBASE-KR TX state machine. This
bit self clears and is active only when the TX state machine is in
the AN state. For more information, refer to bit 7.0.9 in Clause
73.8 Management Register Requirements of IEEE 802.3ap-2007.
8
RW
AN Next Page
When asserted, new next page (NP) info is ready to send. The
data is in the XNP TX registers. When 0, the TX interface sends
null pages. This bit self clears. NP is encoded in bit D15 of Link
Codeword. For more information, refer to Clause 73.6.9 and bit
7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
1
RO
AN page received
When set to 1, a page has been received. When 0, a page has not
been received. The current value clears when the register is read.
For more information, refer to bit 7.1.6 in Clause 73.8 of IEEE
802.3ap-2007.
continued...
(35)
These register bits are only applicable to the 10GBASE-KR mode.
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Word
Addr
0x4C2
0x4C3
Bit
R/W
Name
Description
2
RO
AN Complete
When asserted, AN has completed. When 0, AN is in progress. For
more information, refer to bit 7.1.5 in Clause 73.8 of IEEE
802.3ap-2007.
3
RO
AN ADV Remote Fault
When set to 1, fault information has been sent to the link partner.
When 0, a fault has not occurred. The current value clears when
the register is read. Remote Fault (RF) is encoded in bit D13 of
the base Link Codeword. For more information, refer to Clause
73.6.7 of and bit 7.16.13 of IEEE 802.3ap-2007.
4
RO
AN RX SM Idle
When set to 1, the AN state machine is in the idle state. Incoming
data is not Clause 73 compatible. When 0, the AN is in progress.
5
RO
AN Ability
When set to 1, the transceiver PHY is able to perform AN. When
set to 0, the transceiver PHY is not able to perform AN. If your
variant includes AN, this bit is tied to 1. For more information,
refer to bits 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
6
RO
AN Status
When set to 1, link is up. When 0, the link is down. The current
value clears when the register is read. For more information, refer
to bit 7.1.2 of Clause 45 of IEEE 802.3ap-2007.
7
RO
LP AN Ability
When set to 1, the link partner is able to perform AN. When 0,
the link partner is not able to perform AN. For more information,
refer to bit 7.1.0 of Clause 45 of IEEE 802.3ap-2007.
8
RO
FEC negotiated –
enable FEC from SEQ
When set to 1, the PHY is negotiated to perform FEC. When set to
0, the PHY is not negotiated to perform FEC.
9
RO
Seq AN Failure
When set to 1, a sequencer AN failure has been detected. When
set to 0, an AN failure has not been detected.
17:12
RO
KR AN Link
Ready[5:0]
Provides a one-hot encoding of an_receive_idle = true and
link status for the supported link as described in Clause 73.10.1.
The following encodings are defined:
• 6'b000000: 1000BASE-KX
• 6'b000001: 10GBASE-KX4
• 6'b000100: 10GBASE-KR
• 6'b001000: 40GBASE-KR4
• 6'b010000: 40GBASE-CR4
• 6'b100000: 100GBASE-CR10
15:0
RW
User base page low
The AN TX state machine uses these bits if the AN base pages ctrl
bit is set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK, controlled by the SM
• [13]: Remote Fault bit
• [12:10]: Pause bits
• [9:5]: Echoed nonce, set by the state machine
• [4:0]: Selector
The auto generation TX state machine generates the PRBS bit 49.
21:16
RW
Override
AN_TECH[5:0]
AN_TECH value to override. The following bits are defined:
• Bit-16 = AN_TECH[0]= 1000BASE-KX
• Bit-18 = AN_TECH[2] = 10GBASE-KR
You must set 0xC0 bit-5 for this to take effect .
25:24
RW
Override
AN_FEC[1:0]
AN_FEC value to override. The following bits are defined:
• Bit-24 = AN_FEC [0] = Capability
• Bit-25 = AN_FEC [1] = Request
You must set 0xC0 bit-5 for this to take effect.
continued...
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Word
Addr
Bit
30:28
R/W
RW
Name
Override
AN_PAUSE[2:0]
Description
AN_PAUSE value to override. The following bits are defined:
• Bit-28 = AN_PAUSE [0] = Pause Ability
•
Bit-29 = AN_PAUSE [1] = Asymmetric Direction
•
Bit-30 = AN_PAUSE [2] = Reserved
You must set 0xC0 bit-5 for this to take effect.
0x4C4
31:0
RW
User base page high
The AN TX state machine uses these bits if the AN base pages ctrl
bit is set. The following bits are defined:
• [29:5]: Correspond to page bits 45:21, the technology ability.
• [4:0]: Correspond to bits 20:16, the TX nonce bits.
The AN TX state machine generates the PRBS bit 49.
0x4C5
15:0
RW
User Next page low
The AN TX state machine uses these bits if the AN next pages ctrl
bit is set. The following bits are defined:
• [15]: Next page bit
• [14]: ACK, controlled by the state machine
• [13]: Message Page (MP) bit
• [12]: ACK2 bit
• [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is
generated by the AN TX state machine.
0x4C6
31:0
RW
User Next page high
The AN TX state machine uses these bits if the AN next pages ctrl
bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the
PRBS bit, is generated by the AN TX state machine.
0x4C7
15:0
RO
LP base page low
The AN RX state machine receives these bits from the link
partner. The following bits are defined:
• [15] Next page bit
• [14] ACK, which is controlled by the state machine
• [13] RF bit
• [12:10] Pause bits
• [9:5] Echoed nonce which are set by the state machine
• [4:0] Selector
0x4C8
31:0
RO
LP base page high
The AN RX state machine received these bits from the link
partner. The following bits are defined:
• [31:30]: Reserved
• [29:5]: Correspond to page bits [45:21], the technology
ability
• [4:0]: Correspond to bits [20:16], the TX Nonce bits
0x4C9
15:0
RO
LP Next page low
The AN RX state machine receives these bits from the link
partner. The following bits are defined:
• [15]: Next page bit
• [14]: ACK which is controlled by the state machine
• [13]: MP bit
• [12] ACK2 bit
• [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page
encodings of IEEE 802.3ap-2007.
0x4CA
31:0
RO
LP Next page high
The AN RX state machine receives these bits from the link
partner. Bits [31:0] correspond to page bits [47:16].
0x4CB
24:0
RO
AN LP ADV
Tech_A[24:0]
Received technology ability field bits of Clause 73 AutoNegotiation. The 10GBASE-KR PHY supports A0 and A2. The
following protocols are defined:
continued...
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Word
Addr
Bit
R/W
Name
Description
• A0 1000BASE-KX
• A1 10GBASE-KX4
• A2 10GBASE-KR
• A3 40GBASE-KR4
• A4 40GBASE-CR4
• A5 100GBASE-CR10
• A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page
ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
0x4D0
0x4D0
26:25
RO
AN LP ADV
FEC_F[1:0]
Received FEC ability bits (F0:F1) is encoded in bits D46:D47 of
the base Link Codeword. F0 is FEC ability. F1 is FEC requested.
See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
27
RO
AN LP ADV Remote
Fault
Received Remote Fault (RF) ability bits. RF is encoded in bit D13
of the base link codeword in Clause 73 AN. For more information,
refer to Clause 73.6.7 and bits AN LP base page ability register
AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE
802.3ap-2007.
30:28
RO
AN LP ADV Pause
Ability_C[2:0]
Received pause ability bits. Pause (C0:C1) is encoded in bits
D11:D10 of the base link codeword in Clause 73 AN as follows:
• C0 is the same as PAUSE as defined in Annex 28B
• C1 is the same as ASM_DIR as defined in Annex 28B
• C2 is reserved
For more information, refer to bits AN LP base page ability
registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
0
RW
Link Training
enable
When 1, enables the 10GBASE-KR start-up protocol. When 0,
disables the 10GBASE-KR start-up protocol. The default value is
1. For more information, refer to Clause 72.6.10.3.1 and
10GBASE-KR PMD control register bit (1.150.1) of IEEE
802.3ap-2007.
1
RW
dis_max_wait_tmr
When set to 1, disables the LT max_wait_timer . Used for
characterization mode when setting much longer bit error rate
(BER) timer values.
2
RW
quick_mode
When set to 1, only the init and preset values calculate the best
BER.
3
RW
pass_one
When set to 1, the BER algorithm considers more than the first
local minimum when searching for the lowest BER. The default
value is 1.
7:4
RW
main_step_cnt [3:0]
Specifies the number of equalization steps for each main tap
update. There are about 20 settings for the internal algorithm to
test. The valid range is 1-15. The default value is 4'b0010.
11:8
RW
prpo_step_cnt [3:0]
Specifies the number of equalization steps for each pre- and posttap update. From 16-31 steps are possible. The default value is
4'b0001.
14:12
RW
equal_cnt [2:0]
Adds hysteresis to the error count to avoid local minimums. The
following values are defined:
• 000 = 0
• 001 = 1
• 010 = 2
• 011 = 3
• 100 = 4
• 101 = 8
• 110 = 16
• 111 = Reserved
continued...
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Word
Addr
Bit
R/W
Name
Description
The default value is 010.
0x4D0
0x4D1
0x4D2
15
RW
disable Initialize
PMA on
max_wait_timeout
When set to 1, PMA values (VOD, pre-tap, post-tap) are not
initialized upon entry into the Training_Failure state. This
happens when max_wait_timer_done, which sets
training_failure = true (reg 0xD2 bit 3). Used for University
of New Hampshire (UNH) testing. When set to 0, PMA values are
initialized upon entry into Training_Failure state. Refer to
Figure 72-5 of IEEE 802.3ap-2007 for more details.
16
RW
Ovride LP Coef
enable
When set to 1, overrides the link partner's equalization
coefficients; software changes the update commands sent to the
link partner TX equalizer coefficients. When set to 0, uses the Link
Training logic to determine the link partner coefficients. Used with
0x4D1 bit-4 and 0x4D4 bits[7:0].
17
RW
Ovride Local RX
Coef enable
When set to 1, overrides the local device equalization coefficients
generation protocol. When set, the software changes the local TX
equalizer coefficients. When set to 0, uses the update command
received from the link partner to determine local device
coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The
default value is 1.
22
RW
adp_ctle_mode
Reserved. Default = 000
28:24
RW
Manual ctle
Reserved
31:29
RW
max_post_step[2:0]
Reserved
0
RW
Restart Link
training
When set to 1, resets the 10GBASE-KR start-up protocol. When
set to 0, continues normal operation. This bit self clears. For more
information, refer to the state variable mr_restart_training as
defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control
register bit (1.150.0) IEEE 802.3ap-2007.
4
RW
Updated TX Coef new
When set to 1, there are new link partner coefficients available to
send. The LT logic starts sending the new values set in 0x4D4
bits[7:0] to the remote device. When set to 0, continues normal
operation. This bit self clears. Must enable this override in 0x4D0
bit 16.
8
RW
Updated RX coef new
When set to 1, new local device coefficients are available. The LT
logic changes the local TX equalizer coefficients as specified in
0x4D4 bits[23:16]. When set to 0, continues normal operation.
This bit self clears. Must enable the override in 0x4D0 bit17.
0
RO
Link Trained Receiver status
When set to 1, the receiver is trained and is ready to receive
data. When set to 0, receiver training is in progress. For more
information, refer to the state variable rx_trained as defined in
Clause 72.6.10.3.1 and bit 10GBASE-KR PMD control register bit
10GBASE_KR PMD status register bit (1.151.0) of IEEE
802.3ap-2007.
1
RO
Link Training Frame
lock
When set to 1, the training frame delineation has been detected.
When set to 0, the training frame delineation has not been
detected. For more information, refer to the state variable
frame_lock as defined in Clause 72.6.10.3.1 and 10GBASE_KR
PMD status register bit 10GBASE_KR PMD status register bit
(1.151.1) of IEEE 802.3ap-2007.
2
RO
Link Training
Start-up protocol
status
When set to 1, the start-up protocol is in progress. When set to 0,
start-up protocol has completed. For more information, refer to
the state training as defined in Clause 72.6.10.3.1 and
10GBASE_KR PMD status register bit (1.151.2) of IEEE
802.3ap-2007.
continued...
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Word
Addr
0x4D3
0x4D4
Bit
R/W
Name
Description
3
RO
Link Training
failure
When set to 1, a training failure has been detected. When set to
0, a training failure has not been detected. For more information,
refer to the state variable training_failure as defined in Clause
72.6.10.3.1 and bit 10GBASE_KR PMD status register bit
(1.151.3) of IEEE 802.3ap-2007.
4
RO
Link Training Error
When set to 1, excessive errors occurred during Link Training.
When set to 0, the BER is acceptable.
5
RO
Link Training Frame
lock Error
When set to 1, indicates a frame lock was lost during Link
Training. If the tap settings specified by the fields of 0x4D5 are
the same as the initial parameter value, the frame lock error was
unrecoverable.
6
RO
RXEQ Frame Lock
Loss
Frame lock not detected at some point during RXEQ, possibly
triggering conditional RXEQ mode.
7
RO
CTLE Fine-grained
Tuning Error
Could not determine the best CTLE due to maximum BER limit at
each step in the fine-grained tuning mode.
9:0
RW
ber_time_frames
Specifies the number of training frames to examine for bit errors
on the link for each step of the equalization settings. Used only
when ber_time_k_frames is 0. The following values are
defined:
• A value of 2 is about 103 bytes
• A value of 20 is about 104 bytes
• A value of 200 is about 105 bytes
The default value for simulation is 2'b11. The default value for
hardware is 0.
19:10
RW
ber_time_k_frames
Specifies the number of thousands of training frames to examine
for bit errors on the link for each step of the equalization settings.
Set ber_time_m_frames = 0 for time/bits to match the
following values:
• A value of 3 is about 107 bits = About 1.3 ms
• A value of 25 is about 108 bits = About 11 ms
• A value of 250 is about 109 bits = About 110 ms
The default value for simulation is 0. The default value for
hardware is 0x415.
29:20
RW
ber_time_m_frames
Specifies the number of millions of training frames to examine for
bit errors on the link for each step of the equalization settings.
Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to
match the following values:
• A value of 3 is about 1010 bits = About 1.3 seconds
• A value of 25 is about 10 11 bits = About 11 seconds
• A value of 250 is about 1012 bits = About 110 seconds
5:0
RO or
RW
LD coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training frame
sent from the local device control channel. Normally, the bits in
this register are read-only; however, when you override training
by setting the Ovride Coef enable control bit, these bits
become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
continued...
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Word
Addr
Bit
R/W
Name
Description
For more information, refer to bit 10G BASE-KR LD coefficient
update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE
802.3ap-2007.
0x4D4
6
RO or
RW
LD Initialize
Coefficients
When set to 1, requests the link partner coefficients be set to
configure the TX equalizer to its INITIALIZE state. When set to 0,
continues normal operation. For more information, refer to 10G
BASE-KR LD coefficient update register bits (1.154.12) in Clause
45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
7
RO or
RW
LD Preset
Coefficients
When set to 1, requests the link partner coefficients be set to a
state where equalization is turned off. When set to 0 the link
operates normally. For more information, refer to bit 10GBASE-KR
LD coefficient update register bit (1.154.13) in Clause 45.2.1.80.3
and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
13:8
RO
LD coefficient
status[5:0]
Status report register for the contents of the second, 16-bit word
of the training frame most recently sent from the local device
control channel. The following fields are defined:
• [5:4]: Coefficient (post-tap)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LD status report
register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
14
RO
Link Training ready
- LD Receiver ready
When set to 1, the local device receiver has determined that
training is complete and it is prepared to receive data. When set
to 0, the local device receiver requests that training continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LD
status report register bit (1.155.15) in Clause 45.2.1.81 of IEEE
802.3ap-2007.
21:16
RO or
RW
LP coefficient
update[5:0]
Reflects the contents of the first 16-bit word of the training frame
most recently received from the control channel.
Normally the bits in this register are read only; however, when
training is disabled by setting low the KR training enable control
bit, these bits become writable. The following fields are defined:
• [5: 4]: Coefficient (+1) update
— 2'b11: Reserved
— 2'b01: Increment
— 2'b10: Decrement
— 2'b00: Hold
• [3:2]: Coefficient (0) update (same encoding as [5:4])
• [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LP coefficient
update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE
802.3ap-2007.
22
RO or
RW
LP Initialize
Coefficients
When set to 1, the local device transmit equalizer coefficients are
set to the INITIALIZE state. When set to 0, normal operation
continues. The function and values of the initialize bit are defined
in Clause 72.6.10.2.3.2. For more information, refer to bit
10GBASE-KR LP coefficient update register bits (1.152.12) in
Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
continued...
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Word
Addr
0x4D4
0x4D5
0x4D5
0x4D6
Bit
R/W
Name
Description
23
RO or
RW
LP Preset
Coefficients
When set to 1, the local device TX coefficients are set to a state
where equalization is turned off. Preset coefficients are used.
When set to 0, the local device operates normally. The function
and values of the preset bit are defined in 72.6.10.2.3.1. The
function and values of the initialize bit are defined in Clause
72.6.10.2.3.2. For more information, refer to bit 10GBASE-KR LP
coefficient update register bits (1.152.13) in Clause 45.2.1.78.3
of IEEE 802.3ap-2007.
29:24
RO
LP coefficient
status[5:0]
Status report register reflecting the contents of the second, 16-bit
word of the training frame most recently received from the
control channel. The following fields are defined:
• [5:4]: Coefficient (+1)
— 2'b11: Maximum
— 2'b01: Minimum
— 2'b10: Updated
— 2'b00: Not updated
• [3:2]: Coefficient (0) (same encoding as [5:4])
• n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to bit 10GBASE-KR LP status report
register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
30
RO
LP Receiver ready
When set to 1, the link partner receiver has determined that
training is complete and is prepared to receive data. When set to
0, the link partner receiver is requesting that training continue.
Values for the receiver ready bit are defined in Clause
72.6.10.2.4.4. For more information, refer to bit 10GBASE-KR LP
status report register bits (1.153.15) in Clause 45.2.1.79 of IEEE
802.3ap-2007.
4:0
R
LT VOD setting
Stores the most recent VOD setting that LT specified. It reflects
Link Partner commands to fine-tune the VOD.
13:8
R
LT Post-tap setting
Stores the most recent post-tap setting that LT specified. It
reflects Link Partner commands to fine-tune the TX pre-emphasis
taps.
20:16
R
LT Pre-tap setting
Stores the most recent pre-tap setting that LT specified. It
reflects Link Partner commands to fine-tune the TX pre-emphasis
taps.
27:24
R
RXEQ CTLE Setting
Most recent ctle_rc setting sent to the reconfig bundle during
RX equalization.
29:28
R
RXEQ CTLE Mode
Most recent ctle_mode setting sent to the reconfig bundle
during RX equalization.
31:30
R
RXEQ DFE Mode
Most recent dfe_mode setting sent to the reconfig bundle during
RX equalization.
4:0
RW
LT VODMAX ovrd
Override value for the VMAXRULE parameter. When enabled, this
value substitutes for the VMAXRULE to allow channel-by-channel
override of the device settings. This only effects the local device
TX output for the channel specified.
This value must be greater than the INITMAINVAL parameter for
proper operation. Note this will also override the PREMAINVAL
parameter value.
5
RW
LT VODMAX ovrd
Enable
When set to 1, enables the override value for the VMAXRULE
parameter stored in the LT VODMAX ovrd register field.
continued...
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Word
Addr
Bit
12:8
R/W
RW
Name
LT VODMin ovrd
Description
Override value for the VODMINRULE parameter. When enabled,
this value substitutes for the VMINRULE to allow channel-bychannel override of the device settings. This override only effects
the local device TX output for this channel.
The value to be substituted must be less than the INITMAINVAL
parameter and greater than the VMINRULE parameter for proper
operation.
13
RW
LT VODMin ovrd
Enable
When set to 1, enables the override value for the VODMINRULE
parameter stored in the LT VODMin ovrd register field.
21:16
RW
LT VPOST ovrd
Override value for the VPOSTRULE parameter. When enabled, this
value substitutes for the VPOSTRULE to allow channel-by-channel
override of the device settings. This override only effects the local
device TX output for this channel.
The value to be substituted must be greater than the
INITPOSTVAL parameter for proper operation.
22
RW
LT VPOST ovrd
Enable
When set to 1, enables the override value for the VPOSTRULE
parameter stored in the LT VPOST ovrd register field.
28:24
RW
LT VPre ovrd
Override value for the VPRERULE parameter. When enabled, this
value substitutes for the VPOSTRULE to allow channel-by-channel
override of the device settings. This override only effects the local
device TX output for this channel.
The value greater than the INITPREVAL parameter for proper
operation.
29
RW
0x4D6
to
0x4FF
LT VPre ovrd Enable
When set to 1, enables the override value for the VPRERULE
parameter stored in the LT VPre ovrd register field.
Reserved for 40G KR
Left empty for address compatibility with 40G MAC+PHY KR
solution.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
2.6.4.7.2 Hard Transceiver PHY Registers
Table 146.
Addr
0x000-0
x3FF
Hard Transceiver PHY Registers
Bit
[9:0]
Access
RW
Name
Access to HSSI
registers
Description
All registers in the physical coding sub-layer (PCS) and physical
media attachment (PMA) that you can dynamically reconfigure
are in this address space. Refer to the Arria 10 Dynamic
Transceiver Reconfiguration chapter for further information.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
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2.6.4.7.3 Enhanced PCS Registers
Table 147.
Enhanced PCS Registers
Addr
Bit
Access
Name
Description
0x480
31:0
RW
Indirect_addr
Because the PHY implements a single channel, this
register must remain at the default value of 0 to specify
logical channel 0.
0x481
2
RW
RCLR_ERRBLK_CNT
Error block counter clear register. When set to 1, clears
the RCLR_ERRBLK_CNT register. When set to 0, normal
operation continues.
3
RW
RCLR_BER_COUNT
BER counter clear register. When set to 1, clears the
RCLR_BER_COUNT register. When set to 0, normal
operation continues.
0x482
1
RO
HI_BER
High BER status. When set to 1, the PCS reports a high
BER. When set to 0, the PCS does not report a high
BER.
2
RO
BLOCK_LOCK
Block lock status. When set to 1, the PCS is locked to
received blocks. When set to 0, the PCS is not locked to
received blocks.
3
RO
TX_FIFO_FULL
When set to 1, the TX_FIFO is full.
4
RO
RX_FIFO_FULL
When set to 1, the RX_FIFO is full.
7
RO
Rx_DATA_READY
When set to 1, indicates the PHY is ready to receive
data.
2.6.4.7.4 Arria 10 GMII PCS Registers
Addr
0x490
0x491
0x494
(1000BASEX mode)
Bit
R/W
Name
Description
9
RW
RESTART_AUTO_ NEGOTIATION
Set this bit to 1 to restart the Clause 37 autonegotiation (AN) sequence. For normal operation, set
this bit to the default 0 value. This bit is self-clearing.
12
RW
AUTO_NEGOTIATION_ ENABLE
Set this bit to 1 to enable Clause 37 AN. The default
value is 1.
15
RW
Reset
Set this bit to 1 to generate a synchronous reset pulse
which resets all the PCS state machines, comma
detection function, and the 8B/10B encoder and
decoder. For normal operation, set this bit to 0. This
bit self clears.
2
R
LINK_STATUS
A value of 1 indicates that a valid link is operating. A
value of 0 indicates an invalid link. If link
synchronization is lost, this bit is 0.
3
R
AUTO_NEGOTIATION_ ABILITY
A value of 1 indicates that the PCS function supports
Clause 37 AN.
5
R
AUTO_NEGOTIATION_ COMPLETE
A value of 1 indicates the following status:
• The AN process is complete.
• The AN control registers are valid.
5
RW
FD
Full-duplex mode enable for the local device. Set to 1
for full-duplex support.
6
RW
HD
Half-duplex mode enable for the local device. Set to 1
for half-duplex support. This bit should always be set
to 0 for the KR PHY IP.
continued...
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Addr
Bit
R/W
8:7
RW
PS2,PS1
Pause support for the local device. The following
encodings are defined for PS1/PS2:
• PS1=0 / PS2=0: Pause is not supported
• PS1=0 / PS2=1: Asymmetric pause toward link
partner
• PS1=1 / PS2=0: Symmetric pause
• PS1=1 / PS2=1: Pause is supported on TX and RX
13:
12
RW
RF2,RF1
Remote fault condition for local device. The following
encodings are defined for RF1/RF2:
• RF1=0 / RF2=0: No error, link is valid (reset
condition)
• RF1=0 / RF2=1: Offline
• RF1=1 / RF2=0: Failure condition
• RF1=1 / RF2=1: AN error
14
R0
ACK
Acknowledge for local device. A value of 1 indicates
that the device has received three consecutive
matching ability values from its link partner.
15
RW
NP
Next page. In the device ability register, this bit is
always set to 0.
5
R
FD
Full-duplex mode enable for the link partner. This bit
must be 1 because only full duplex is supported.
6
R
HD
Half-duplex mode enable for the link partner. A value
of 1 indicates support for half duplex. This bit must be
0 because half-duplex mode is not supported.
8:7
R
PS2,PS1
Specifies pause support for link partner. The following
encodings are defined for PS1/PS2:
• PS1=0 / PS2=0: Pause is not supported
• PS1=0 / PS2=1: Asymmetric pause toward link
partner
• PS1=1 / PS2=0: Symmetric pause
• PS1=1 / PS2=1: Pause is supported on TX and RX
13:
12
R
RF2,RF1
Remote fault condition for link partner. The following
encodings are defined for RF1/RF2:
• RF1=0 / RF2=0: No error, link is valid (reset
condition)
• RF1=0 / RF2=1: Offline
• RF1=1 / RF2=0: Failure condition
• RF1=1 / RF2=1: AN error
14
R
ACK
Acknowledge for link partner. A value of 1 indicates
that the device has received three consecutive
matching ability values from its link partner.
15
R
NP
Next page. In link partner register. When set to 0, the
link partner has a Next Page to send. When set to 1,
the link partner does not send a Next Page. Next Page
is not supported in AN.
0x494
(SGMII
mode)
14
RO
ACK
Local device acknowledge. Value as specified in IEEE
802.3z standard.
0x495
(SGMII
mode)
11:
10
RO
Speed[1:0]
Link partner speed:
• 00: copper interface speed is 10 Mbps
• 01: copper interface speed is 100 Mbps
• 10: copper interface speed is 1 Gigabit
• 11: reserved
0x495
(1000BASEX mode)
Name
Description
continued...
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Addr
Bit
12
R/W
RO
Name
COPPER_DUPLEX_STATUS
Description
Link partner capability:
• 1: copper interface is capable of full-duplex
operation
• 0: copper interface is capable of half-duplex
operation
Note: The PHY IP Core does not support half duplex
operation because it is not supported in SGMII
mode of the 1G/10G PHY IP core.
14
RO
ACK
Link partner acknowledge. Value as specified in IEEE
802.3z standard.
15
RO
COPPER_LINK_STATUS
Link partner status:
• 1: copper interface link is up
• 0: copper interface link is down
0
R
LINK_PARTNER_AUTO_NEGOTIATIO
N_ABLE
Set to 1, indicates that the link partner supports AN.
The default value is 0.
1
R
PAGE_RECEIVE
A value of 1 indicates that a new page has been
received with new partner ability available in the
register partner ability. The default value is 0 when
the system management agent performs a read
access.
0x4A2
15:
0
RW
Link timer[15:0]
Low-order 16 bits of the 21-bit auto-negotiation link
timer. Each timer step corresponds to 8 ns (assuming
a 125 MHz clock). The total timer corresponds to 16
ms. The reset value sets the timer to 10 ms for
hardware mode and 10 us for simulation mode.
0x4A3
4:0
RW
Link timer[20:16]
High-order 5 bits of the 21-bit auto-negotiation link
timer.
0x4A4
0
RW
SGMII_ENA
Determines the PCS function operating mode. Setting
this bit to 1b'1 enables SGMII mode. Setting this bit
to 1b'0 enables 1000BASE-X gigabit mode.
1
RW
USE_SGMII_AN
In SGMII mode, setting this bit to 1b'1 configures the
PCS with the link partner abilities advertised during
auto-negotiation. If this bit is set to 1b'0, the PCS
function should be configured with the SGMII_SPEED
and SGMII_DUPLEX bits.
3:2
RW
SGMII_SPEED
SGMII speed. When the PCS operates in SGMII mode
(SGMII_ENA = 1) and is not programmed for
automatic configuration (USE_SGMII_AN = 0), the
following encodings specify the speed :
• 2'b00: 10 Mbps
• 2'b01: 100 Mbps
• 2'b10: Gigabit
• 2'b11: Reserved
0x496
These bits are not used when SGMII_ENA = 0or
USE_SGMII_AN = 1.
4
RW
SGMII half-duplex
When set to 1, enables half-duplex mode for 10/100
Mbps speed. This bit is ignored when SGMII_ENA = 0
or USE_SGMII_AN = 1. These bits are only valid when
you enable the SGMII mode only and not the
clause-37 auto-negotiation mode.
2.6.4.7.5 PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data
interface, and provide status information.
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Table 148.
1G Data Mode
Addr
Bit
0x4A8
0x4A9
Table 149.
Name
Description
0
RW
tx_invpolarity
When set, the TX interface inverts the polarity of
the TX data to the 8B/10B encoder.
1
RW
rx_invpolarity
When set, the RX channels inverts the polarity of
the received data to the 8B/10B decoder.
2
RW
rx_bitreversal_enable
When set, enables bit reversal on the RX interface
to the word aligner.
3
RW
rx_bytereversal_enable
When set, enables byte reversal on the RX interface
to the byte deserializer.
4
RW
force_electrical_idle
When set, forces the TX outputs to electrical idle.
0
R
rx_syncstatus
When set, the word aligner is synchronized.
1
R
rx_patterndetect
GbE word aligner detected comma.
2
R
rx_rlv
Run length violation.
3
R
rx_rmfifodatainserted
Rate match FIFO inserted code group.
4
R
rx_rmfifodatadeleted
Rate match FIFO deleted code group.
5
R
rx_disperr
RX 8B10B disparity error.
6
R
rx_errdetect
RX 8B10B error detected.
PMA Registers
Address
0x444
R/W
Bit
R/W
Name
Description
1
RW
reset_tx_digital
Writing a 1 asserts the internal TX digital reset signal. You
must write a 0 to clear the reset condition.
2
RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal to be
asserted. You must write a 0 to clear the reset condition.
3
RW
reset_rx_digital
Writing a 1 causes the internal RX digital reset signal to be
asserted. You must write a 0 to clear the reset condition.
0x461
0
RW
phy_serial_loopback
Writing a 1 puts the channel in serial loopback mode.
0x464
0
RW
pma_rx_set_locktoda
ta
When set, programs the RX clock data recovery (CDR) PLL
to lock to the incoming data.
0x465
0
RW
pma_rx_set_locktore
f
When set, programs the RX CDR PLL to lock to the reference
clock.
0x466
0
RO
pma_rx_is_lockedtod
ata
When asserted, indicates that the RX CDR PLL is locked to
the RX data, and that the RX CDR has changed from LTR to
LTD mode.
0x467
0
RO
pma_rx_is_lockedtor
ef
When asserted, indicates that the RX CDR PLL is locked to
the reference clock.
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2.6.4.7.6 Speed Change Summary
Table 150.
Speed Change Summary
Speed Change
1GbE and 10GBASE-R
Speed Change Method
Interface Signals
Detailed Information
•
•
Refer to Dynamic Reconfiguration
Interface.
Figure 77 on page 195
SGMII (10M, 100M and 1GbE)
Avalon-MM bus
Table 124 on page 158
1GbE, 10GBASE-R, and 10GBASE-R
with FEC
Avalon-MM bus
Table 145 on page 180
Note:
You can configure the static speed while generating the IP core using the IP Parameter
Editor.
Related Links
Dynamic Reconfiguration Interface on page 146
2.6.4.8 Creating a 1G/10GbE Design
Follow these steps to create a 1G/10GbE design using the 1G/10GbE PHY IP.
1. Generate the 1G/10GbE PHY with the required parameterization.
The 1G/10GbE PHY IP Core includes reconfiguration logic. This logic provides the
Avalon-MM interface that you can use to read and write to PHY registers. All read
and write operations must adhere to the Avalon specification.
2. Instantiate a reset controller using the Transceiver Reset Controller Intel FPGA IP
Core in the IP Catalog. Connect the power and reset signals between the 1G/
10GbE PHY and the reset controller.
3.
Instantiate one TX PLL for the 1G data rate and one TX PLL for the 10G data rate.
Connect the high speed serial clock and PLL lock signals between 1G/10GbE PHY
and TX PLLs. You can use any combination of fPLLs, ATX, or CMU PLLs.
4. Use the tx_pma_divclk from 1G/10GbE PHY or generate a fPLL to create the
156.25 MHz XGMII clock from the 10G reference clock.
No Memory Initialization Files (.mif) are required for the 1G/10GbE design in
Arria 10 devices.
5. Complete the design by creating a top level module to connect all the IP (1G/
10GbE PHY IP, PLL IP and Reset Controller) blocks.
Related Links
•
fPLL on page 347
•
CMU PLL on page 356
•
ATX PLL on page 338
•
Using the Transceiver PHY Reset Controller on page 418
•
1G/10GbE PHY Functional Description on page 164
2.6.4.9 Design Guidelines
Consider the following guidelines while designing with 1G/10GbE PHY.
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Using the 1G/10GbE PHY without the Sequencer
The sequencer brings up channel-based initial datapath and performs parallel
detection. To use the 1G/10GbE PHY without the sequencer, turn off the Enable
automatic speed detection parameter.
Turning off the sequencer results in the following additional ports:
•
rc_busy
•
start_pcs_reconfig
•
mode_1g_10gbar
These ports perform manual reconfiguration. The following figure shows how these
ports are used for 1G and 10G configuration.
Figure 77.
Timing for Reconfiguration without the Sequencer
mgmt_clk
rc_busy
start_pcs_reconfig
mode_1g_10bar
2.6.4.10 Channel Placement Guidelines
The channels of multi-channel 1G/10G designs do not need to be placed contiguously.
However, channels instantiated in different transceiver banks require PLLs in the same
bank.
Related Links
Arria 10 Avalon-MM Interface for PCIe* Solutions
2.6.4.11 Design Example
Intel provides a design example to assist you in integrating your Ethernet PHY IP into
your complete design.
The MAC and PHY design example instantiates the 1G/10GbE PHY IP along with the
1G/10G Ethernet MAC and supporting logic. It is part of the Quartus II software
installation and is located in the <quartus2_install_dir>/ip subdirectory. For more
information about this example design, refer to the 10-Gbps Ethernet MAC IP Function
User Guide.
A design example that instantiates the 1G/10G PHY and its supporting logic is
available on the Intel FPGA wiki. The following figure shows the block diagram of the
1G/10GbE PHY-only design example. The default configuration includes two channels
for backplane Ethernet and two channels for line-side (1G/10G) applications.
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Figure 78.
1G/10GbE PHY Only Design Example
A10_DE_WRAPPER
Test Harness
Management
Master
JTAG-toAvalon-MM
Master
ISSP
Clock and
Reset
XGMII
Test
Harness
Source
XGMII
Source
TH0_ADDR = 0xF nnn
XGMII
Sink
XGMII
Sink
XGMII
GEN
XGMII
GEN
XGMII
CHK
XGMII
CHK
TH1_ADDR
... = 0xE nnn
...
A10_IP_WRAPPER
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0
CH1: PHY_ADDR = 0x1
CH2: PHY_ADDR = 0x2
CH3: PHY_ADDR = 0x3
1G/10GbE PHY IP
Registers CSR
Avalon-MM Slave
NF
Registers CSR
KR PHY IP
Reconfiguration
Avalon-MM Slave
NF
Native
Hard
PHY Registers CSR
1588 Soft
KR PHY IP
ReconfigurationNF
Avalon-MMRegisters
Slave CSR
FIFOs
Native Hard PHY Avalon-MM Slave
STD
Reconfiguration
1588 Soft
TX
PMA
TX PCS
FIFOs
Native Hard PHY
1588 Soft
STD
Native Hard PHY
FIFOs 1588 Soft
Sequencer
TX PMA
TX PCS
STD
FIFOs
TX
PMA
TX PCS STD
Sequencer
TX PMA
10-GB
TX PCS
GMII
Sequencer
TX PCS
RS
Sequencer
10-GB
GMII
TX PCS
10-GB
RS
GMII
TX PCS 10-GB
RS
GMII
TX PCS
RS STD
Auto Neg
RX PCS
cls 73
STD
Auto Neg
RX PCS
cls 73 Auto Neg
STD
cls 73
RX PCS STD
Link Training
cls 72
RX PCS
10-GB
Link Training
RX PMA
RX PCS
cls 72Link Training
10-GB
RX PMA
cls 72
RX PCS
10-GB
RX PMA
RX PCS 10-GB
RX PMA
Divide
RX PCS
KR PHY IP
nnn
nnn
nnn
nnn
A10
Reconfiguration
Divide
Divide
Divide
Related Links
Arria 10 Transceiver PHY Design Examples
2.6.4.12 Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported
simulators for this Quartus Prime software release:
•
ModelSim Verilog
•
ModelSim VHDL
•
VCS Verilog
•
VCS VHDL
•
NCSIM Verilog
•
NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime
software optionally generates an IP functional simulation model.
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2.6.4.13 TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The
necessary Synopsys Design Constraints File (.sdc) timing constraints are included in
the top-level wrapper file.
2.6.5 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
2.6.5.1 About 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core
The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements the Ethernet
protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard. The PHY IP core
consists of a physical coding sublayer (PCS) function and an embedded physical media
attachment (PMA). You can dynamically switch the PHY operating speed.
Figure 79.
Block Diagram of the PHY IP Core
Intel Device with Serial Transceivers
1G/2.5G/5G/10G Multi-rate Ethernet PHY
Native PHY Hard IP
LL Ethernet
10G MAC
TX Serial
TX
GMII / XGMII
Soft PCS
Hard PCS
External
PHY
PMA
RX
GMII / XGMII
User
Application Avalon-MM
Interface
Legend
Hard IP
Soft Logic
RX Serial
Configuration
Registers
Transceiver
Reset
Controller
TX
Serial Clock
Reconfiguration Block
PLL
for 1 GbE
RX CDR
Reference
Clock
PLL
for 2.5 GbE
125-MHz
Reference Clock
PLL
for 10 GbE
322-MHz
Reference Clock
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
Recommended Reset Sequence on page 404
•
Low Latency Ethernet 10G MAC User Guide
Describes the Low Latency Ethernet 10G MAC IP Core.
2.6.5.1.1 Features
Table 151.
PHY Features
Feature
Description
Multiple operating speeds
1G, 2.5G, 5G, and 10G.
MAC-side interface
16-bit GMII for 1G and 2.5G.
continued...
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Feature
Description
32-bit XGMII for 1G/2.5G/5G/10G (USXGMII).
64-bit XGMII for 10G.
Network-side interface
1.25 Gbps for 1G.
3.125 Gbps for 2.5G.
10.3125 Gbps for 1G/2.5G/5G/10G (USXGMII).
Avalon® Memory-Mapped (Avalon-MM)
interface
Provides access to the configuration registers of the PHY.
PCS function
1000BASE-X for 1G and 2.5G.
10GBASE-R for 10G.
USXGMII PCS for 1G/2.5G/5G/10G
Auto-negotiation
Implements clause 37. Supported in 1GbE only.
USXGMII Auto-negotiation supported in the 1G/2.5G/5G/10G (USXGMII)
configuration.
IEEE 1588v2
Provides the required latency to the MAC if the MAC enables the IEEE
1588v2 feature.
Sync-E
Provides the clock for Sync-E implementation.
2.6.5.1.2 Release Information
Table 152.
PHY Release Information
Item
Description
Version
16.0
Release Date
May 2016
Ordering Codes
IP-10GMRPHY
Product ID
00E4
Vendor ID
6AF7
Open Core Plus
Supported
2.6.5.1.3 Device Family Support
Operating Mode
Device Family
Arria 10
Arria V GX/GT/SX/ST
Other device families
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Support Level
2.5G
1G/2.5G
1G/2.5G/5G/10G
Final
2.5G
1G/2.5G
Final
No support
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Definition: Device Support Level
Intel FPGA IP cores provide the following support for Intel FPGA device families:
•
Preliminary support—Intel verifies the IP core with preliminary timing models for
this device family. The IP core meets all functional requirements, but might still be
undergoing timing analysis for the device family. This IP core can be used in
production designs with caution.
•
Final support—Intel verifies the IP core with final timing models for this device
family. The IP core meets all functional and timing requirements for the device
family. This IP core is ready to be used in production designs.
2.6.5.1.4 Resource Utilization
The following estimates are obtained by compiling the PHY IP core with the Intel
Quartus Prime software.
Table 153.
Resource Utilization
Device
Arria 10
Speed
ALMs
ALUTs
Logic Registers
Memory Block
550
750
1200
2 (M20K)
1G/2.5G with IEEE
1588v2 enabled
1200
1850
2550
2 (M20K)
1G/2.5G/5G/10G
1150
1500
2550
6 (M20K)
1G/2.5G/5G/10G
(USXGMII)
650
800
1500
3 (M20K)
1G/2.5G
2.6.5.2 Using the IP Core
The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installation
process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet IP core from the
library and parameterize it using the IP parameter editor.
2.6.5.2.1 Parameter Settings
You customize the PHY IP core by specifying the parameters in the parameter editor in
the Intel Quartus Prime software. The parameter editor enables only the parameters
that are applicable to the selected speed.
Table 154.
1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters
Name
Speed
Value
2.5G
1G/2.5G
1G/2.5G/5G/10G
Description
The operating speed of the PHY.
Enable IEEE 1588 Precision
Time Protocol
On, Off
Select this parameter for the PHY to provide latency
information to the MAC. The MAC requires this
information if it enables the IEEE 1588v2 feature.
This parameter is enabled only for 2.5G and 1G/2.5G.
Connect to MGBASE-T PHY
On, Off
Select this option when the external PHY is MGBASE-T
compatible.
This parameter is enabled for 2.5G, 1G/2.5G, and 1G/
2.5G/10G (MGBASE-T) modes.
continued...
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Name
Value
Connect to NBASE-T PHY
On, Off
PHY ID (32 bit)
Reference clock frequency for
10 GbE (MHz)
Description
Select this option when the external PHY is NBASE-T
compatible.
This parameter is enabled for 1G/2.5G/5G/10G
(USXGMII) modes.
32-bit value
An optional 32-bit unique identifier:
• Bits 3 to 24 of the Organizationally Unique Identifier
(OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value, which is
0x00000000.
322.265625, 644.53125
Specify the frequency of the reference clock for 10GbE.
Selected TX PMA local clock
division factor for 1 GbE
1, 2, 4, 8
Selected TX PMA local clock
division factor for 2.5 GbE
1, 2
Enable Altera Debug Master
Endpoint
On, Off
Available in Native PHY and TX PLL IP parameter editors.
When enabled, the Altera Debug Master Endpoint
(ADME) is instantiated and has access to the Avalon-MM
interface of the Native PHY. You can access certain test
and debug functions using System Console with the
ADME. Refer to the Embedded Debug Features section
for more details about ADME.
Enable capability registers
On, Off
Available in Native PHY and TX PLL IP parameter editors.
Enables capability registers. These registers provide
high-level information about the transceiver channel's /
PLL's configuration.
User-specified
Available in Native PHY and TX PLL IP parameter editors.
Sets a user-defined numeric identifier that can be read
from the user_identifier offset when the capability
registers are enabled.
Enable control and status
registers
On, Off
Available in Native PHY and TX PLL IP parameter editors.
Enables soft registers for reading status signals and
writing control signals on the PHY /PLL interface through
the ADME or reconfiguration interface.
Enable PRBS soft
accumulators
On, Off
Available in Native PHY IP parameter editor only.
Enables soft logic to perform PRBS bit and error
accumulation when using the hard PRBS generator and
checker.
Set user-defined IP identifier
This parameter is the local clock division factor in the 1G
mode. It is directly mapped to the Native PHY IP Core
GUI options.
This parameter is the local clock division factor in the
2.5G mode. It is directly mapped to the Native PHY IP
Core GUI options.
Related Links
Embedded Debug Features on page 526
2.6.5.2.2 Timing Constraints
Constrain the PHY based on the fastest speed. For example, if you configure the PHY
as 1G/2.5G, constrain it based on 2.5G.
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For the 1G/2.5G/5G/10G operating mode, constrain the PHY for the 10G datapath as
well as the 1G/2.5G datapath. Refer to the example provided:
<Installation Directory>/ip/altera/ethernet/alt_mge_phy/example/
alt_mge_phy_multi_speed_10g.sdc.
2.6.5.2.3 Changing the PHY's Speed
You can change the PHY's speed through the reconfiguration block.
1.
The user application initiates the speed change by writing to the corresponding
register of the reconfiguration block.
2.
The reconfiguration block performs the following steps:
•
In Arria 10 devices:
a.
Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet
PHY IP core to the requested speed.
b.
Reads the generated .mif file for the configuration settings and configures
the transceiver accordingly.
The .mif files, alt_mge_phy_reconfig_parameters_CFG*.mif, are
generated in the <IP working directory>/
altera_xcvr_native_a10_<version>/synth/reconfig directory.
3.
c.
Selects the corresponding transceiver PLL.
d.
Triggers the transceiver recalibration.
The reconfiguration block triggers the PHY reset through the transceiver reset
controller.
2.6.5.3 Configuration Registers
You can access the 16-bit configuration registers via the Avalon-MM interface. These
configuration registers apply only to 2.5G and 1G/2.5G operating modes.
Observe the following guidelines when accessing the registers:
Table 155.
Addr
0x00
•
Do not write to reserved or undefined registers.
•
When writing to the registers, perform read-modify-write to ensure that reserved
or undefined register bits are not overwritten.
PHY Register Definitions
Name
control
Description
Access
HW Reset
Value
RWC
0
•
Bit [15]: RESET. Set this bit to 1 to trigger a soft
reset.
The PHY clears the bit when the reset is completed.
The register values remain intact during the reset.
•
Bit[14]: LOOPBACK. Set this bit to 1 to enable
loopback on the serial interface.
RW
0
•
Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bit
to 1 to enable auto-negotiation.
Auto-negotiation is supported only in 1GbE.
Therefore, set this bit to 0 when you switch to a
speed other than 1GbE.
RW
0
continued...
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Addr
0x01
Name
status
Description
Access
HW Reset
Value
RWC
0
•
Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bit
to 1 to restart auto-negotiation.
The PHY clears the bit as soon as auto-negotiation is
restarted.
•
The rest of the bits are reserved.
—
—
•
Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of
"1" indicates that the auto-negotiation is completed.
RO
0
•
Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of
"1" indicates that the PCS function supports autonegotiation.
RO
1
•
Bit [2]: LINK_STATUS. A value of "0" indicates that
the link is lost. Value of 1 indicates that the link is
established.
RO
0
•
The rest of the bits are reserved.
—
—
0x02:0x03
phy_identifier
The value set in the PHY_IDENTIFIER parameter.
RO
Value of
PHY_IDEN
TIFIER
parameter
0x04
dev_ability
Use this register to advertise the device abilities during
auto-negotiation.
—
—
RW
00
RW
11
RW
1
—
—
The device abilities of the link partner during autonegotiation.
—
—
•
Bit [14]: ACK. A value of "1" indicates that the link
partner has received three consecutive matching
ability values from the device.
RO
0
•
Bits [13:12]: RF. The remote fault.
RO
0
•
Bits [13:12]: RF. Specify the remote fault.
—
—
—
—
•
partner_ability
No error.
Link failure.
Offline.
Auto-negotiation error.
Bits [8:7]: PS. Specify the PAUSE support.
—
—
—
—
0x05
00:
01:
10:
11:
00: No PAUSE.
01: Symmetric PAUSE.
10: Asymmetric PAUSE towards the link partner.
11: Asymmetric and symmetric PAUSE towards
the link device.
•
Bit [5]: FD. Ensure that this bit is always set to 1.
•
The rest of the bits are reserved.
—
—
—
—
00:
01:
10:
11:
No error.
Link failure.
Offline.
Auto-negotiation error.
continued...
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Addr
Name
Description
•
Bits [8:7]: PS. The PAUSE support.
—
—
—
—
0x06
0x07
an_expansion
Access
HW Reset
Value
RO
0
00: No PAUSE.
01: Symmetric PAUSE.
10: Asymmetric PAUSE towards the link partner.
11: Asymmetric and symmetric PAUSE towards
the link device.
•
Bit [6]: HD. A value of "1" indicates that half-duplex
is supported.
RO
0
•
Bit [5]: FD. A value of "1" indicates that full-duplex
is supported.
RO
0
•
The rest of the bits are reserved.
—
—
The PCS capabilities and auto-negotiation status.
—
—
Bit [1]: PAGE_RECEIVE. A value of "1" indicates that
the partner_ability register has been updated. This bit is
automatically cleared once it is read.
RO
0
Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE. A
value of "1" indicates that the link partner supports
auto-negotiation.
RO
0
RO
0
The PHY does not support the next page feature. These
registers are always set to 0.
RO
0
—
—
device_next_page
0x08
partner_next_pag
e
0x09:0x0F
Reserved
—
0x10
scratch
Provides a memory location to test read and write
operations.
RW
0
0x11
rev
The current version of the PHY IP core.
RO
Current
version of
the PHY
0x12:0x13
link_timer
21-bit auto-negotiation link timer.
• Offset 0x12: link_timer[15:0]. Bits [8:0] are always
be set to 0.
• Offset 0x13: link_timer[20:16] occupies the lower 5
bits. The remaining 11 bits are reserved and must
always be set to 0.
RW
0
0x14:0x1F
Reserved
—
—
—
0x400
usxgmii_control
Control Register
—
—
RW
0x0
RW
0x1
Bit [0]: USXGMII_ENA:
•
•
0: 10GBASE-R mode
1: USXGMII mode
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA
is set to 1:
• 0: Disables USXGMII Auto-Negotiation and manually
configures the operating speed with the
USXGMII_SPEED register.
•
1: Enables USXGMII Auto-Negotiation, and
automatically configures operating speed with link
partner ability advertised during USXGMII AutoNegotiation.
continued...
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Addr
Name
Description
Access
HW Reset
Value
Bit [4:2]: USXGMII_SPEED is the operating speed of
the PHY in USXGMII mode and USE_USXGMII_AN is set
to 0.
• 3’b000: Reserved
• 3’b001: Reserved
• 3’b010: 1G
• 3’b011: 10G
• 3’b100: 2.5G
• 3’b101: 5G
• 3’b110: Reserved
• 3’b111: Reserved
RW
0x0
—
—
RWC
(hardw
are
selfclear)
0x0
Bit [15:10]: Reserved
—
—
Bit [30:16]: Reserved
—
—
Status Register
—
—
Bit [1:0]: Reserved
—
—
Bit [2]: LINK_STATUS indicates link status for USXGMII
all speeds
• 1: Link is established
• 0: Link synchronization is lost, a 0 is latched
RO
0x0
Bit [3]: Reserved
—
—
Bit [4]: Reserved
—
—
Bit [5]: AUTO_NEGOTIATION_COMPLETE
RO
0x0
Bit [15:6]: Reserved
—
—
Bit [31:16]: Reserved
—
—
Bit [8:5]: Reserved
Bit [9]: RESTART_AUTO_NEGOTIATION
Write 1 to restart Auto-Negotiation sequence The bit is
cleared by hardware when Auto-Negotiation is
restarted.
0x401
usxgmii_status
A value of 1 indicates the Auto-Negotiation process is
completed.
0x402:0x404
Reserved
—
—
—
0x405
usxgmii_partner_
ability
Device abilities advertised to the link partner during
Auto-Negotiation
—
—
Bit [0]: Reserved
—
—
Bit [6:1]: Reserved
—
—
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
RO
0x0
RO
0x0
Indicates whether or not energy efficient ethernet (EEE)
clock stop is supported.
• 0: Not supported
• 1: Supported
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
• 0: Not supported
• 1: Supported
continued...
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Addr
Name
Description
Access
HW Reset
Value
RO
0x0
RO
0x0
Bit [13]: Reserved
—
—
Bit [14]: ACKNOWLEDGE
RO
0x0
RO
0x0
Bit [31:16]: Reserved
—
—
—
—
[19:14
]: RW
[13:0]:
RO
[19:14]:
0x1F
[13:0]:
0x0
Bit [11:9]: SPEED
•
•
•
•
•
•
•
•
3'b000:
3'b001:
3'b010:
3'b011:
3'b100:
3'b101:
3'b110:
3'b111:
10M
100M
1G
10G
2.5G
5G
Reserved
Reserved
Bit [12]: DUPLEX
Indicates the duplex mode.
• 0: Half duplex
• 1: Full duplex
A value of 1 indicates that the device has received three
consecutive matching ability values from its link partner.
Bit [15]: LINK
Indicates the link status.
• 0: Link down
• 1: Link up
0x406:0x411
Reserved
—
0x412
usxgmii_link_tim
er
Auto-Negotiation link timer. Sets the link timer value in
bit [19:14] from 0 to 2 ms in approximately 0.05-ms
steps. You must program the link timer to ensure that it
matches the link timer value of the external NBASE-T
PHY IP Core.
The reset value sets the link timer to approximately 1.6
ms.
Bits [13:0] are reserved and always set to 0.
0x413:0x41F
Reserved
—
—
—
0x461
phy_serial_loopb
ack
Configures the transceiver serial loopback in the PMA
from TX to RX.
—
—
RW
0x0
Bit [15:1]: Reserved
—
—
Bit [31:16]: Reserved
—
—
Bit [0]
• 0: Disables the PHY serial loopback
• 1: Enables the PHY serial loopback
2.6.5.3.1 Register Map
You can access the 16-bit/32-bit configuration registers
interface.
(36)
(36)
via the Avalon-MM
These registers are identical to the Intel Arria 10 variation of 1G/2.5G/5G/10G Multi-rate
Ethernet PHY IP core.
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Table 156.
Register Map
Address Range
Usage
Bit
Configuration
0x00 : 0x1F
1000BASE-X/SGMII
16
2.5G, 1G/2.5G, 10M/
100M/1G/2.5, 10M/
100M/1G/2.5G/10G
(MGBASE-T), 1G/2.5G/10G
(MGBASE-T)
0x400 : 0x41F
USXGMII
32
1G/2.5G/5G/10G (USXGMII)
0x461
Serial Loopback
32
1G/2.5G/5G/10G (USXGMII)
2.6.5.3.2 Definition: Register Access
Table 157.
Types of Register Access
Access
Definition
RO
Read only.
RW
Read and write.
RWC
Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined
instruction. The IP core clears the bit(s) upon executing the instruction.
2.6.5.4 Interface Signals
Figure 80.
PHY Interface Signals
Serial
Interface
Avalon-MM
Control & Status
Interface
tx_serial_clk
rx_cdr_refclk
rx_cdr_refclk1
rx_pma_clkout
tx_serial_data
rx_serial_data
csr_clk
csr_address[4:0]
csr_write
csr_read
csr_writedata[] (i)
csr_readdata[] (i)
csr_waitrequest
xcvr_mode[1:0]
operating_speed[2:0]
latency_measure_clk
Reset
Status
Interface
reset
pll_powerdown
tx_digitalreset
rx_digitalreset
tx_analogreset
rx_analogreset
led_link
led_char_err
led_disp_err
led_an
rx_block_lock
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PHY
tx_clkout
gmii16b_tx_d[15:0]
gmii16b_tx_en[1:0]
gmii16b_tx_err[1:0]
gmii16b_tx_latency[21:0]
rx_clkout
gmii16b_rx_d[15:0]
gmii16b_rx_dv[1:0]
gmii16b_rx_err[1:0]
gmii16b_rx_latency[21:0]
xgmii_tx_coreclkin
xgmii_tx_control[7:0]
xgmii_tx_data[63:0]
xgmii_tx_valid
xgmii_rx_coreclkin
xgmii_rx_control[7:0]
xgmii_rx_data[63:0]
xgmii_rx_valid
TX GMII
RX GMII
TX XGMII
RX XGMII
rx_is_lockedtodata
tx_cal_busy
rx_cal_busy
reconfig_clk
reconfig_reset
reconfig_address[9:0]
reconfig_write
reconfig_read
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_waitrequest
Transceiver Status &
Reconfiguration Interface
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2.6.5.4.1 Clock and Reset Signals
Table 158.
Clock and Reset Signals
Signal Name
Direction
Width
Output
1
Description
Clock signals
tx_clkout
GMII TX clock, derived from
tx_serial_clk[1:0]. Provides 156.25 MHz
timing reference for 2.5GbE; 62.5 MHz for 1GbE.
Output
1
GMII RX clock, derived from
tx_serial_clk[1:0]. Provides 156.25 MHz
timing reference for 2.5GbE; 62.5 MHz for 1GbE.
csr_clk
Input
1
Clock for the Avalon-MM control and status
interface. Intel recommends 125 – 156.25 MHz for
this clock.
xgmii_tx_coreclkin
Input
1
XGMII TX clock. Provides 156.25 MHz timing
reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode. Synchronous to
tx_serial_clk with zero ppm.
xgmii_rx_coreclkin
Input
1
XGMII RX clock. Provides 156.25 MHz timing
reference for 10GbE and 312.5 MHz for 1G/
2.5G/5G/10G (USXGMII) mode.
latency_measure_clk
Input
1
Sampling clock for measuring the latency of the
16-bit GMII datapath. This clock operates at 80
MHz and is available only when the IEEE 1588v2
feature is enabled.
tx_serial_clk
Input
1-3
rx_cdr_refclk
Input
1
125-MHz RX CDR reference clock for 1GbE and
2.5GbE
rx_cdr_refclk_1
Input
1
RX CDR reference clock for 10GbE. The frequency
of this clock can be either 322.265625 MHz or
644.53125 MHz, as specified by the Reference
clock frequency for 10 GbE (MHz) parameter
setting.
Output
1
Recovered clock from CDR, operates at the
following frequency:
• 1GbE: 125 MHz
• 2.5GbE: 312.5 MHz
• 5GbE/10GbE: 322.265625 MHz
reset
Input
1
Active-high global reset. Assert this signal to
trigger an asynchronous global reset.
tx_analogreset
Input
1
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the analog block on the TX
path.
rx_clkout
rx_pma_clkout
Serial clock from transceiver PLLs.
• 2.5GbE: Connect bit [0] to the transceiver PLL.
This clock operates at 1562.5 MHz.
• 1GbE: Connect bit [1] to the transceiver PLL.
This clock operates at 625 MHz.
• 10GbE: Connect bit [2] to the transceiver PLL.
This clock operates at 5156.25 MHz.
• 1G/2.5G/5G/10G (USXGMII) mode: Connect bit
[0] to 5156.25 MHz.
Reset signals
continued...
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Signal Name
Direction
Width
Description
tx_digitalreset
Input
1
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the TX
path.
rx_analogreset
Input
1
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the receiver CDR.
rx_digitalreset
Input
1
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the RX
path.
2.6.5.4.2 Operating Mode and Speed Signals
Table 159.
Transceiver Mode and Operating Speed Signals
Signal Name
Direction
Width
Input
2
Connect this signal to the reconfiguration block.
Use the values below to set the speed:
• 0x0 = 1G
• 0x1 = 2.5G
• 0x3 = 10G
Output
3
Connect this signal to the MAC. This signal
provides the current operating speed of the PHY:
• 0x0 = 10G
• 0x1 = 1G
• 0x4 = 2.5G
• 0x5 = 5G
xcvr_mode
operating_speed
Description
2.6.5.4.3 GMII Signals
The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz
respectively.
Table 160.
GMII Signals
Signal Name
Direction
Width
Description
TX GMII signals—synchronous to tx_clkout
gmii16b_tx_d
Input
16
gmii16b_tx_en
Input
2
TX data from the MAC. The MAC sends the lower
byte first followed by the upper byte.
When asserted, indicates the start of a new frame
from the MAC. Bit[0] corresponds to
gmii16b_tx_d[7:0]; bit[1] corresponds to
gmii16b_tx_d[15:8].
This signal remains asserted until the PHY receives
the last byte of the data frame.
gmii16b_tx_err
Input
2
When asserted, indicates an error. Bit[0]
corresponds to gmii16b_tx_err[7:0]; bit[1]
corresponds to gmii16b_tx_err[15:8].
The bits can be asserted at any time during a
frame transfer to indicate an error in the current
frame.
continued...
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Signal Name
gmii16b_tx_latency
Direction
Width
Description
Output
22
The latency of the PHY excluding the PMA block on
the TX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock
cycles.
This signal is available when only the Enable IEEE
1588 Precision Time Protocol parameter is
selected.
RX data to the MAC. The PHY sends the lower byte
first followed by the upper byte. Rate matching is
done by the PHY on the RX data from the RX
recovered clock to rx_clkout.
RX GMII signals—synchronous to rx_clkout
gmii16b_rx_d
Output
16
gmii16b_rx_err
Output
2
When asserted, indicates an error. Bit[0]
corresponds to gmii16b_rx_err[7:0]; bit[1]
corresponds to gmii16b_rx_err[15:8].
The bits can be asserted at any time during a
frame transfer to indicate an error in the current
frame.
gmii16b_rx_dv
Output
2
When asserted, indicates the start of a new frame.
Bit[0] corresponds to gmii16b_rx_d[7:0]; bit[1]
corresponds to gmii16b_rx_d[15:8].
This signal remains asserted until the PHY sends
the last byte of the data frame.
gmii16b_rx_latency
Output
22
The latency of the PHY excluding the PMA block on
the RX datapath:
• Bits [21:10]: The number of clock cycles.
• Bits [9:0]: The fractional number of clock
cycles.
This signal is available only when the Enable IEEE
1588 Precision Time Protocol parameter is
selected.
2.6.5.4.4 XGMII Signals
The XGMII supports 10GbE at 156.25 MHz.
Table 161.
XGMII Signals
Signal Name
Direction
Width
Description
TX XGMII signals—synchronous to xgmii_tx_coreclkin
xgmii_tx_data
Input
64, 32
xgmii_tx_control
Input
8, 4
TX data from the MAC. The MAC sends the data in
the following order: bits[7:0], bits[15:8], and so
forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
TX control from the MAC:
• xgmii_tx_control[0] corresponds to
xgmii_tx_data[7:0]
•
xgmii_tx_control[1] corresponds to
xgmii_tx_data[15:8]
• ... and so forth.
The width is:
continued...
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Signal Name
Direction
Width
Description
•
•
xgmii_tx_valid
Output
1
8 bits for 1G/2.5G/10G configurations.
4 bits for 1G/2.5G/5G/10G configurations.
Indicates valid data on xgmii_tx_control and
xgmii_tx_data from the MAC.
Your logic/MAC must toggle the valid data as
shown below:
Speed
Toggle Rate
1G
Asserted once every 10
clock cycles
2.5G
Asserted once every 4
clock cycles
5G
Asserted once every 2
clock cycles
10G
Always asserted
RX XGMII signals—synchronous to xgmii_rx_coreclkin
xgmii_rx_data
Output
64, 32
xgmii_rx_control
Output
8, 4
RX data to the MAC. The PHY sends the data in the
following order: bits[7:0], bits[15:8], and so forth.
The width is:
• 64 bits for 1G/2.5G/10G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations.
RX control to the MAC.
• xgmii_rx_control[0] corresponds to
xgmii_rx_data[7:0]
•
xgmii_rx_control[1] corresponds to
xgmii_rx_data[15:8]
• ... and so forth.
The width is:
• 8 bits for 1G/2.5G/10G configurations.
• 4 bits for 1G/2.5G/5G/10G configurations.
xgmii_rx_valid
Output
1
Indicates valid data on xgmii_rx_control and
xgmii_rx_data from the MAC.
The toggle rate from the PHY is shown in the table
below.
Note: The toggle rate may vary when the start of
a packet is received or when rate match
occurs inside the PHY. You should not
expect the valid data pattern to be fixed.
Speed
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Toggle Rate
1G
Asserted once every 10
clock cycles
2.5G
Asserted once every 4
clock cycles
5G
Asserted once every 2
clock cycles
10G
Always asserted
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2.6.5.4.5 Status Signals
Table 162.
Status Signals
Signal Name
Direction
Width
Description
led_char_err
Output
1
Asserted when a 10-bit character error is detected
in the RX data.
led_link
Output
1
Asserted when the link synchronization for 1GbE or
2.5GbE is successful
led_disp_err
Output
1
Asserted when a 10-bit running disparity error is
detected in the RX data.
led_an
Output
1
Asserted when auto-negotiation is completed.
rx_block_lock
Output
1
Asserted when the link synchronization for 10GbE
is successful.
2.6.5.4.6 Serial Interface Signals
The serial interface connects to an external device.
Table 163.
Serial Interface Signals
Signal Name
Direction
Width
tx_serial_data
Output
1
TX data.
Description
rx_serial_data
Input
1
RX data.
2.6.5.4.7 Transceiver Status and Reconfiguration Signals
Table 164.
Control and Status Signals
Signal Name
Direction
Width
Description
rx_is_lockedtodata
Output
1
Asserted when the CDR is locked to the RX data.
tx_cal_busy
Output
1
Asserted when TX calibration is in progress.
rx_cal_busy
Output
1
Asserted when RX calibration is in progress.
Transceiver reconfiguration signals for Arria 10 devices
reconfig_clk
Input
1
reconfig_reset
Input
1
reconfig_address
Input
10
reconfig_write
Input
1
reconfig_read
Input
1
reconfig_writedata
Input
32
reconfig_readdata
Output
32
reconfig_waitrequest
Output
1
Reconfiguration signals connected to the
reconfiguration block. The reconfig_clk signal
provides the timing reference for this interface.
2.6.5.4.8 Avalon-MM Interface Signals
The Avalon-MM interface is an Avalon-MM slave port. This interface uses word
addressing and provides access to the 16-bit configuration registers of the PHY.
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Table 165.
Avalon-MM Interface Signals
Signal Name
Direction
Width
Description
csr_address
Input
5, 11
Use this bus to specify the register address to read
from or write to. The width is:
• 5 bits for 2.5G and 1G/2.5G configurations.
• 11 bits for 1G/2.5G/5G/10G configurations.
csr_read
Input
1
Output
16, 32
csr_write
Input
1
csr_writedata
Input
16, 32
Data to be written to the specified register. The
data is written only when the csr_waitrequest
signal is deasserted. The width is:
• 16 bits for 2.5G and 1G/2.5G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations. The
upper 16 bits are reserved.
Output
1
When asserted, indicates that the PHY is busy and
not ready to accept any read or write requests.
• When you have requested for a read or write,
keep the control signals to the Avalon-MM
interface constant while this signal is asserted.
The request is complete when it is deasserted.
• This signal can be high or low during idle cycles
and reset. Therefore, the user application must
not make any assumption of its assertion state
during these periods.
csr_readdata
csr_waitrequest
Assert this signal to request a read operation.
Data read from the specified register. The data is
valid only when the csr_waitrequest signal is
deasserted. The width is:
• 16 bits for 2.5G and 1G/2.5G configurations.
• 32 bits for 1G/2.5G/5G/10G configurations. The
upper 16 bits are reserved.
Assert this signal to request a write operation.
2.6.6 XAUI PHY IP Core
In a XAUI configuration, the transceiver channel data path is configured using a soft
PCS. The XAUI configuration provides the transceiver channel datapath, clocking, and
channel placement guidelines. You can implement a XAUI link using the IP Catalog.
Under Ethernet in the Interfaces menu, select the XAUI PHY IP core. The XAUI PHY IP
core implements the XAUI PCS in soft logic.
XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined
in the IEEE 802.3ae-2008 specification. The XAUI PHY uses the XGMII interface to
connect to the IEEE802.3 MAC and Reconciliation Sublayer (RS). The IEEE
802.3ae-2008 specification requires the XAUI PHY link to support:
•
A 10 Gbps data rate at the XGMII interface
•
Four lanes each at 3.125 Gbps at the PMD interface
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Figure 81.
XAUI and XGMII Layers
LAN Carrier Sense Multiple
Access/Collision Detect (CSMA/CD)
Layers
Higher Layers
Logical Link Control (LLC)
OSI
Reference
Model Layers
MAC Control (Optional)
Media Access Control (MAC)
Application
Reconciliation
Presentation
Session
Transport
10 Gigabit Media Independent Interface
Optional
XGMII
Extender
XGMII Extender Sublayer
10 Gigabit Attachment Unit Interface
XGMII Extender Sublayer
10 Gigabit Media Independent Interface
Network
PCS
Data Link
PMA
Physical Layer Device
PMD
Physical
Medium Dependent Interface
Medium
10 Gbps
Intel's XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend
the operational distance of the XGMII interface and reduce the number of interface
signals.
XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC
function and the Ethernet standard PHY component to one meter. The XAUI PHY IP
core accepts 72-bit data (single data rate–SDR XGMII) from the application layer at
156.25 Mbps. The serial interface runs at 4 × 3.125 Gbps.
Figure 82.
XAUI PHY IP Core
XAUI PHY IP
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status
XAUI PHY IP Core
4
PCS
8B/10B
Word Aligner
Phase Comp
Hard PMA
4
4 x 3.125 Gbps serial
Intel's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and
Reduced XAUI (RXAUI) support is MorethanIP (MTIP).
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XAUI does not support open compute project (OCP) networking.
Related Links
•
IEEE 802.3 Clause 48
•
MorethanIP
2.6.6.1 Transceiver Datapath in a XAUI Configuration
The XAUI PHY IP core is partially implemented in soft logic inside the FPGA core. You
must ensure that your channel placement is compatible with the soft PCS
implementation.
Figure 83.
Transceiver Channel Datapath for XAUI Configuration
The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.
Portable solution using Custom PHY or Native PHY
Transmitter Standard PCS
20
Transmitter PMA Ch1
Transmitter Standard PCS
20
Transmitter PMA Ch0
10
Receiver PMA
10
Deserializer
10
Word Aligner
20
Byte
Deserializer
20
RX Phase
Compensation
FIFO
20
Deskew FIFO
20
Rate Match FIFO
8B/10B
Decoder
Receiver Standard PCS
16
tx_serial_data
8B/10B Encoder
16
Channel 1
Channel 0
Serializer
Soft PCS
Soft PCS
Transmitter PMA Ch2
Transmitter Standard PCS
Byte Serializer
Channel 1
Channel 0
Transmitter PMA Ch3
Transmitter Standard PCS
Channel 2
rx_serial_data
Channel 3
Soft PCS
Soft PCS
TX Phase
Compensation
FIFO
Channel 3
Channel 2
CDR
FPGA Fabric
2.6.6.2 XAUI Supported Features
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between
the XAUI PCS and the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8bit data and a 1-bit control code at both the positive and negative edge (double data
rate) of the 156.25 MHz interface clock.
Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support
the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification.
Instead, they transfer 16-bit data and the 2-bit control code on each of the four XAUI
lanes. The transfer occurs only at the positive edge (single data rate) of the 156.25
MHz interface clock.
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Figure 84.
Implementation of the XGMII Specification in Arria 10 Devices Configuration
The ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive
xgmii_tx_clk and xgmii_rx_clk. Both the ATX PLL and the FPLL must be clocked by the same reference
clock to maintain 0 ppm.
XGMII Transfer (DDR)
Interface Clock (156.25 MHz)
8-bit
Lane 0
D0
D1
D2
D3
Lane 1
D0
D1
D2
D3
Lane 2
D0
D1
D2
D3
Lane 3
D0
D1
D2
D3
Arria 10 Soft PCS Interface (SDR)
Interface Clock (156.25 MHz)
16-bit
Lane 0
{D1, D0}
{D3, D2}
Lane 1
{D1, D0}
{D3, D2}
Lane 2
{D1, D0}
{D3, D2}
Lane 3
{D1, D0}
{D3, D2}
8B/10B Encoding/Decoding
Each of the four lanes in a XAUI configuration supports an independent 8B/10B
encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification.
8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial
data stream to five. This limit ensures DC balance as well as enough transitions for the
receiver CDR to maintain a lock to the incoming data.
The XAUI PHY IP core provides status signals to indicate both running disparity and
the 8B/10B code group error.
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Transmitter and Receiver State Machines
In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver
state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008
specification.
The transmitter state machine performs the following functions in conformance with
the 10GBASE-X PCS:
•
Encoding the XGMII data to PCS code groups
•
Converting Idle ||I|| ordered sets into Sync ||K||, Align ||A||, and Skip ||R||
ordered sets
The receiver state machine performs the following functions in conformance with the
10GBASE-X PCS:
•
Decoding the PCS code groups to XGMII data
•
Converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets into Idle ||I||
ordered sets
Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements
the receiver synchronization state diagram shown in Figure 48-7 of the
IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner
is synchronized to a valid word boundary.
Deskew
The lane aligner block in the receiver PCS implements the receiver deskew state
diagram shown in Figure 48-8 of the IEEE 802.3-2008 specification.
The lane aligner starts the deskew process only after the word aligner block in each of
the four XAUI lanes indicates successful synchronization to a valid word boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in
the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm
difference between the remote transmitter and the local receiver. It compensates by
inserting and deleting Skip ||R|| columns, depending on the ppm difference.
The clock compensation operation begins after:
•
The word aligner in all four XAUI lanes indicates successful synchronization to a
valid word boundary.
•
The lane aligner indicates a successful lane deskew.
The rate match FIFO provides status signals to indicate the insertion and deletion of
the Skip ||R|| column for clock rate compensation.
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2.6.6.3 XAUI PHY Release Information
Table 166.
XAUI Release Information
Item
Description
Version
16.0
Release Date
November 2016
Product ID
00D7
Vendor ID
6AF7
2.6.6.4 XAUI PHY Device Family Support
IP cores provide either final or preliminary support for target Intel device families.
These terms have the following definitions:
Table 167.
•
Final support—Verified with final timing models for this device.
•
Preliminary support—Verified with preliminary timing models for this device.
Device Family Support
Device Family
Support
XAUI
Arria 10
Preliminary
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2.6.6.5 Transceiver Clocking and Channel Placement Guidelines in XAUI
Configuration
Transceiver Clocking
Figure 85.
Transceiver Clocking for XAUI Configuration Without Phase Compensation
FIFO Enabled
The external ATX PLL generates the transmitter serial and parallel clocks for the four XAUI channels. You must
instantiate the PLL and connect it to XAUI. The x6 clock line carries the transmitter serial and parallel clocks to
the PMA and PCS of each of the four channels.
XAUI PHY IP Core
8B/10B Encoder
16
20
Channel 1
Transmitter Standard PCS
Channel 0
Transmitter PMA Ch 1
Transmitter Standard PCS
20
Transmitter PMA Ch 0
tx_serial_data
Soft PCS
Soft PCS
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter Standard PCS
Serializer
Channel 1
Channel 0
Transmitter Standard PCS
Channel 3
Channel 2
Byte Serializer
Soft PCS
Soft PCS
TX Phase
Compensation
FIFO
Channel 3
Channel 2
10
Parallel Clock
/2
xgmii_rx_clk
Parallel Clock
/2
Parallel Clock
(Recovered) from Channel 0
10
CDR
10
Receiver PMA
Deserializer
20
Word Aligner
20
Byte Deserializer
RX Phase
Compensation
FIFO
Deskew FIFO
20
Rate Match FIFO
16
8B/10B
Decoder
Receiver Standard PCS
rx_serial_data
xgmii_tx_clk
Parallel Clock (Recovered)
Master Clock Generation Block
(1)
ATX PLL
Serial Clock
(From the ×1 Clock Lines)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
1. Use the ATX PLL as the transmit PLL for XAUI support in Arria 10 devices.
Note:
When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver
channel. This ensures that the serial clock is running at 3.125 Gbps while the input
reference clock is 156.25 MHz.
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Figure 86.
Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO
Enabled
When phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-ST
interface.
Parallel Clock
Parallel Clock (x6 Network)
Serial Clock
Parallel Recovered Clock
Parallel Recovered Clock 2
Serial Recovered Clock
8B/10B Encoder
Idle Converter
Transmitter PMA
Serializer
MAC
Transmitter Standard PCS
Soft PCS
TX Phase
Compensation
FIFO
32/64b
Avalon-ST
Adapter
XAUI PHY IP Core
Receiver Standard PCS
Receiver PMA
36/72b
XGMII
Adapter
156.25 MHz
Parallel Recovered Clock 2 (1)
CDR
Parallel Recovered Clock
Serial Recovered Clock
fPLL
REFCLK
Deserializer
Word Aligner
RX Phase
Compensation
FIFO
Deskew FIFO
8B/10B
Decoder
Rate Match FIFO
Idle Rep
156.25 MHz
312.5 MHz
156.25 MHz
xgmii_tx_clk 156.25 MHz
156.25 MHz
ATX PLL
Parallel Clock (x6 Network)
x1 Network
Master CGB
Serial Clock (x6 Network)
Note:
1. One recovered clock drives four XAUI channels.
2.6.6.6 XAUI PHY Performance and Resource Utilization
The following table lists the typical expected device resource utilization for different
configurations using the current version of the Quartus II software targeting an Arria
10 device. The numbers of combinational ALUTs and logic registers are rounded to the
nearest 100.
Table 168.
XAUI PHY Performance and Resource Utilization
Implementation
Soft XAUI
Number of 3.125
Gbps Channels
4
Combinational ALUTs
1700
Dedicated Logic
Registers
1700
M20K Memory Blocks
3
2.6.6.7 Parameterizing the XAUI PHY
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Complete the following steps to configure the XAUI PHY IP core in the IP Catalog:
1.
For Which device family will you be using?, select Arria 10.
2. Click Installed IP ➤ Library ➤ Interface Protocols ➤ Ethernet ➤ XAUI PHY.
3.
Use the tabs on the IP Catalog to select the options required for the protocol.
4.
Refer to the following topics to learn more about the parameters:
a.
General Parameters
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b.
Analog Parameters
c.
Advanced Options Parameters
5. Click Finish to generate your customized XAUI PHY IP core.
Related Links
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
•
XAUI PHY General Parameters on page 220
•
Analog Parameter Settings on page 563
•
XAUI PHY Advanced Options Parameters on page 220
2.6.6.7.1 XAUI PHY General Parameters
This section describes the settings available on the General Options tab.
Table 169.
General Options
Name
Value
Description
Device family
Arria 10
The target device family.
XAUI interface type
Soft XAUI
Implements the PCS in soft logic and the PMA in
hard logic. Includes four channels.
Enable Sync-E support
On / Off
Shows separate reference clocks for CDR PLL
and TX PLL.
Number of XAUI interfaces
1
Specifies the number of XAUI interfaces. Only 1
is available in the current release.
2.6.6.7.2 XAUI PHY Advanced Options Parameters
This section describes the settings available on the Advanced Options tab.
Table 170.
Advanced Options
Name
Value
Description
Include control and status
ports
On / Off
If you turn this option on, the top-level IP core includes the
status signals and digital resets shown in XAUI Top-Level Signals
—Soft PCS and PMA and XAUI Top-Level Signals—Hard IP PCS
and PMA. If you turn this option off, you can access control and
status information using the Avalon-MM interface to the control
and status registers. The default setting is off.
Enable dynamic
reconfiguration
On / Off
When you turn this option on, you can connect the dynamic
reconfiguration ports to an external reconfiguration module.
Enable rx_recovered_clk pin
On / Off
When you turn this option on, the RX recovered clock signal is an
output signal.
Enable phase compensation
FIFO
On / Off
Enables the phase compensation FIFO to allow different clocks on
the xgmii interface.
2.6.6.8 XAUI PHY Ports
The following figure illustrates the top-level signals of the XAUI PHY IP core for the
soft IP implementation.
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Figure 87.
XAUI Top-Level Signals—Soft PCS and PMA
XAUI Top-Level Signals
xgmii_tx_dc[71:0]
xgmii_tx_clk
SDR TX XGMII
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
xgmii_rx_dc[71:0]
xgmii_rx_clk
xgmii_rx_inclk
SDR RX XGMII
rx_channelaligned
rx_disperr[7:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
Avalon-MM PHY
Management
Interface
pll_locked_i
pll_powerdown_o
tx_bonding_clock[5:0]
pll_cal_busy_i
PLL
RX Status
Optional
reconfig_clk
reconfig_reset
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
reconfig_write
reconfig_read
reconfig_waitrequest
pll_ref_clk
cdr_ref_clk
Clocks
Transceiver
Serial Data
Avalon-MM
Dynamic
Reconfiguration
PMA
Channel
Controller
rx_recovered_clk[3:0]
rx_ready
tx_ready
2.6.6.9 XAUI PHY Interfaces
The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface
implements a simple version of the Avalon-ST protocol. The interface does not include
ready or valid signals. Consequently, the sources always drive data and the sinks must
always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer to
the Avalon Interface Specifications.
Depending on the parameters you choose, the application interface runs at either
156.25 Mbps or 312.5 Mbps. At either frequency, data is only driven on the rising edge
of clock. To meet the bandwidth requirements, the datapath is eight bytes wide with
eight control bits, instead of the standard four bytes of data and four bits of control.
The XAUI PHY IP core treats the datapath as two, 32-bit data buses and includes logic
to interleave them, starting with the low-order bytes.
Figure 88.
Interleaved SDR XGMII Data Mapping
Original XGMII Data
[63:56]
[55:48]
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0]
[15:8]
[39:32]
[7:0]
Interleaved Result
[63:56]
[31:24]
[55:48]
[23:16]
[47:40]
Related Links
Avalon Interface Specifications
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2.6.6.9.1 SDR XGMII TX Interface
Table 171.
SDR TX XGMII Interface
Signal Name
Direction
Description
Input
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control. Synchronous to mgmt_clk.
xgmii_tx_dc[71:0]
•
•
•
•
Input
xgmii_tx_clk
Lane
Lane
Lane
Lane
0–[7:0]/[8], [43:36]/[44]
1–[16:9]/[17], [52:45]/[53]
2–[25:18]/[26], [61:54]/[62]
3–[34:27]/[35],[70:63]/[71]
The XGMII SDR TX clock which runs at 156.25 MHz.
2.6.6.9.2 SDR XGMII RX Interface
Table 172.
SDR RX XGMII Interface
Signal Name
Direction
Description
Output
Contains 4 lanes of data and control for XGMII. Each lane consists of
16 bits of data and 2 bits of control. Synchronous to mgmt_clk.
xgmii_rx_dc_[71:0]
•
•
•
•
xgmii_rx_clk
xgmii_rx_inclk
Output
Input
Lane
Lane
Lane
Lane
0–[7:0]/[8], [43:36]/[44]
1–[16:9]/[17], [52:45]/[53]
2–[25:18]/[26], [61:54]/[62]
3–[34:27]/[35],[70:63]/[71]
The XGMII SDR RX clock which runs at 156.25 MHz.
The XGMII SDR RX input clock which runs at 156.25 MHz. This port
is only available when Enable phase compensation FIFO is
selected.
2.6.6.9.3 Transceiver Serial Data Interface
The XAUI transceiver serial data interface has four lanes of serial data for both the TX
and RX interfaces. This interface runs at 3.125 Gbps. There is no separate clock signal
because it is encoded in the data.
Table 173.
Serial Data Interface
Signal Name
Direction
xaui_rx_serial_data[3:0]
Input
xaui_tx_serial_data[3:0]
Output
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Description
Serial input data.
Serial output data.
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2.6.6.9.4 XAUI PHY Clocks, Reset, and Powerdown Interfaces
Figure 89.
Clock Inputs and Outputs for IP Core with Soft PCS
phy_mgmt_clk
pll_ref_clk
XAUI Soft IP Core
pll_ref_clk
xgmii_tx_clk
xgmii_rx_clk
Soft PCS
pma_tx_clkout
pma_pll_inclk
pma_rx_clkout
sysclk
4
PMA
tx_clkout
rx_recovered_clk
4
4 x 3.125 Gbps serial
Table 174.
Clock and Reset Signals
Signal Name
Direction
Description
Input
pll_ref_clk
This is a 156.25 MHz reference clock that is used by the CDR
logic.
2.6.6.9.5 XAUI PHY PMA Channel Controller Interface
Table 175.
PMA Channel Controller Signals
Signal Name
Direction
Description
rx_recovered_clk[3:0]
Output
This is the RX clock, which is recovered from the received data
stream.
rx_ready
Output
Indicates PMA RX has exited the reset state and the transceiver
can receive data. Synchronous to mgmt_clk.
tx_ready
Output
Indicates PMA TX has exited the reset state and the transceiver
can transmit data. Synchronous to mgmt_clk.
Input
pll_cal_busy_i
Indicates the PLL calibration status.
2.6.6.9.6 XAUI PHY Optional PMA Control and Status Interface
Use the Avalon-MM PHY Management interface to read the state of the optional PMA
control and status signals available in the XAUI PHY IP core registers. In some cases
you may need to know the instantaneous value of a signal to ensure correct
functioning of the XAUI PHY. In such cases, you can include the required signal in the
top-level module of your XAUI PHY IP core.
Table 176.
Optional Control and Status Signals—Soft IP Implementation
Signal Name
Direction
Description
rx_channelaligned
Output
When asserted, indicates that all 4 RX channels are
aligned. Synchronous to mgmt_clk. This signal is
asserted when the RX lanes are fully aligned and ready
to receive data.
rx_disperr[7:0]
Output
Received 10-bit code or data group has a disparity
error. It is paired with rx_errdetect which is also
asserted when a disparity error occurs. The
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Signal Name
Direction
Description
rx_disperr signal is 2 bits wide per channel for a
total of 8 bits per XAUI link. Synchronous to
mgmt_clk.
rx_errdetect[7:0]
Output
When asserted, indicates an 8B/10B code group
violation. It is asserted if the received 10-bit code
group has a code violation or disparity error. Use
rx_errdetect with the rx_disperr signal to
differentiate between a code violation error, a disparity
error, or both. The rx_errdetect signal is 2 bits
wide per channel for a total of 8 bits per XAUI link.
Synchronous to mgmt_clk.
rx_syncstatus[7:0]
Output
Synchronization indication. RX synchronization is
indicated on the rx_syncstatus port of each
channel. The rx_syncstatus signal is 2 bits per
channel for a total of 8 bits per hard XAUI link. The
rx_syncstatus signal is 1 bit per channel for a total
of 4 bits per soft XAUI link. Synchronous to
mgmt_clk.
2.6.6.10 XAUI PHY Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the XAUI PHY IP core
PCS, PMA, and transceiver reconfiguration registers.
Table 177.
Signals in the Avalon-MM PHY Management Interface
Signal Name
Direction
Description
phy_mgmt_clk
Input
Avalon-MM clock input.
phy_mgmt_clk_reset
Input
Global reset signal that resets the entire XAUI PHY. This
signal is active high and level sensitive.
phy_mgmt_addr[8:0]
Input
9-bit Avalon-MM address.
phy_mgmt_writedata[31:0]
Input
32-bit input data.
phy_mgmt_readdata[31:0]
Output
32-bit output data.
phy_mgmt_write
Input
Write signal. Asserted high.
phy_mgmt_read
Input
Read signal. Asserted high.
phy_mgmt_waitrequest
Output
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write request.
When asserted, control signals to the Avalon-MM slave
interface must remain constant.
For more information about the Avalon-MM interface, including timing diagrams, refer
to the Avalon Interface Specification.
The following table specifies the registers that you can access using the Avalon-MM
PHY management interface using word addresses and a 32-bit embedded processor. A
single address space provides access to all registers.
Note:
Writing to reserved or undefined register addresses may have undefined side effects.
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Table 178.
Word
Addr
XAUI PHY IP Core Registers
Bits
R/W
Register Name
Description
Reset Control Registers–Automatic Reset Controller
0x041
[31:0]
RW
reset_ch_bitmask
Bit mask for reset registers at addresses 0x042 and
0x044. The default value is all 1s. You can reset
channel <n> when bit<n> = 1.
0x042
[1:0]
W
reset_control(write)
Writing a 1 to bit 0 initiates a TX digital reset using
the reset controller module. The reset affects
channels enabled in the reset_ch_bitmask. Writing
a 1 to bit 1 initiates a RX digital reset of channels
enabled in the reset_ch_bitmask. This bit selfclears.
R
reset_status(read)
Reading bit 0 returns the status of the reset controller
TX ready bit. Reading bit 1 returns the status of the
reset controller RX ready bit. This bit self-clears.
Reset Controls –Manual Mode
0x044
[31:4,0
]
RW
Reserved
It is safe to write 0s to reserved bits.
[1]
RW
reset_tx_digital
Writing a 1 causes the internal TX digital reset signal
to be asserted, resetting all channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
[2]
RW
reset_rx_analog
Writing a 1 causes the internal RX analog reset signal
to be asserted, resetting the RX analog logic of all
channels enabled in reset_ch_bitmask. You must
write a 0 to clear the reset condition.
[3]
RW
reset_rx_digital
Writing a 1 causes the RX digital reset signal to be
asserted, resetting the RX digital channels enabled in
reset_ch_bitmask. You must write a 0 to clear the
reset condition.
PMA Control and Status Registers
0x061
[31:0]
RW
phy_serial_loopback
Writing a 1 to channel <n> puts channel <n> in
serial loopback mode. For information about pre- or
post-CDR serial loopback modes, refer to Loopback
Modes.
0x064
[31:0]
RW
pma_rx_set_locktodata
When set, programs the RX CDR PLL to lock to the
incoming data. Bit <n> corresponds to channel <n>.
0x065
[31:0]
RW
pma_rx_set_locktoref
When set, programs the RX CDR PLL to lock to the
reference clock. Bit <n> corresponds to channel <n>.
0x066
[31:0]
RO
pma_rx_is_lockedtodata
When asserted, indicates that the RX CDR PLL is
locked to the RX data, and that the RX CDR has
changed from LTR to LTD mode. Bit <n> corresponds
to channel <n>.
0x067
[31:0]
RO
pma_rx_is_lockedtoref
When asserted, indicates that the RX CDR PLL is
locked to the reference clock. Bit <n> corresponds to
channel <n>.
XAUI PCS
0x084
[31:16]
N/A
Reserved
N/A
[15:8]
R
Reserved
N/A
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Word
Addr
Bits
R/W
[7:0]
Register Name
syncstatus[7:0]
Description
Records the synchronization status of the
corresponding bit. The RX sync status register has 1
bit per channel for a total of 4 bits per soft XAUI link;
soft XAUI uses bits 0–3. Reading the value of the
syncstatus register clears the bits.
From block: Word aligner
0x085
[31:16]
N/A
[15:8]
R
[7:0]
Reserved
N/A
errdetect[7:0]
When set, indicates that a received 10-bit code group
has an 8B/10B code violation or disparity error. Use
errdetect with disperr to differentiate between a
code violation error, a disparity error, or both. There
are 2 bits per RX channel for a total of 8 bits per XAUI
link. Reading the value of the errdetect register
clears the bits.
From block: 8B/10B decoder
disperr[7:0]
Indicates that the received 10-bit code or data group
has a disparity error. When set, the corresponding
errdetect bits are also set. There are 2 bits per RX
channel for a total of 8 bits per XAUI link. Reading the
value of the errdetect register clears the bits.
From block: 8B/10B decoder
0x08a
[0]
RW
simulation_flag
Setting this bit to 1 shortens the duration of reset and
loss timer when simulating. Intel recommends that
you keep this bit set for simulation.
Related Links
Avalon Interface Specifications
2.6.6.11 XAUI PHY TimeQuest SDC Constraint
Refer to the "Timing Constraints for Bonded PCS and PMA Channels" section for the
Synopsis Design Constraints (SDC) for XAUI.
Related Links
Timing Constraints for Bonded PCS and PMA Channels on page 428
2.6.7 Acronyms
This table defines some commonly used Ethernet acronyms.
Table 179.
Ethernet Acronyms
Acronym
Definition
AN
Auto-Negotiation in Ethernet as described in Clause 73 of IEEE 802.3ap-2007.
BER
Bit Error Rate.
DME
Differential Manchester Encoding.
FEC
Forward error correction.
GMII
Gigabit Media Independent Interface.
KR
Short hand notation for Backplane Ethernet with 64b/66b encoding.
continued...
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Acronym
Definition
LD
Local Device.
LT
Link training in backplane Ethernet Clause 72 for 10GBASE-KR and 40GBASE-KR4.
LP
Link partner, to which the LD is connected.
MAC
Media Access Control.
MII
Media independent interface.
OSI
Open System Interconnection.
PCS
Physical Coding Sublayer.
PHY
Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA.
PMA
Physical Medium Attachment.
PMD
Physical Medium Dependent.
SGMII
Serial Gigabit Media Independent Interface.
WAN
Wide Area Network.
XAUI
10 Gigabit Attachment Unit Interface.
2.7 PCI Express (PIPE)
You can use Arria 10 transceivers to implement a complete PCI Express solution for
Gen1, Gen2, and Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively.
Configure the transceivers for PCIe functionality using one of the following methods:
•
Arria 10 Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and
PHY/MAC layers. The Hard IP solution contains dedicated hard logic, which
connects to the transceiver PHY interface.
Note: For more information, refer to the Arria 10 Avalon-ST Interface for PCIe
Solutions User Guide.
•
Native PHY IP Core in PIPE Gen1/Gen2/Gen3 Transceiver Configuration
Rules
Use the Native PHY IP (Native PHY IP Core) to configure the transceivers in PCIe
mode, giving access to the PIPE interface (commonly called PIPE mode in
transceivers). This mode enables you to connect the transceiver to a third-party
MAC to create a complete PCIe solution.
The PIPE specification (version 3.0) provides implementation details for a PCIecompliant physical layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3
supports x1, x2, x4, or x8 operation for a total aggregate bandwidth ranging from
2 to 64 Gbps. In a x1 configuration, the PCS and PMA blocks of each channel are
clocked and reset independently. The x2, x4, and x8 configurations support
channel bonding for two-lane, four-lane, and eight-lane links. In these bonded
channel configurations, the PCS and PMA blocks of all bonded channels share
common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall
link bandwidth. Gen3 modes use 128b/130b encoding, which has an overhead of less
than 2%. Gen1 and Gen2 modes use the Standard PCS, and Gen3 mode uses the
Gen3 PCS for its operation.
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Table 180.
Transceiver Solutions
Support
Arria 10 Hard IP for PCI Express
Native PHY IP Core for PCI Express
(PIPE)
Gen1, Gen2, and Gen3 data rates
Yes
Yes
MAC, data link, and transaction layer
Yes
Transceiver interface
User implementation in FPGA fabric
Hard IP through PIPE 3.0 based
interface
•
•
PIPE 2.0 for Gen1 and Gen2
PIPE 3.0 based for Gen3 with Gen1/
Gen2 support
Related Links
•
Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express
•
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
2.7.1 Transceiver Channel Datapath for PIPE
Figure 90.
Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
Transmitter Standard PCS
Transmitter PMA
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
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PCI Express Hard IP
Receiver PMA
PIPE Interface
PRBS
Generator
PRBS
Verifier
FPGA
Fabric
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Figure 91.
Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations
Transmitter PMA
Transmitter Gen3 PCS
Gearbox
FPGA
Fabric
Transmitter Standard PCS
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
PRBS
Generator
Receiver Gen3 PCS
Rate Match
FIFO
Block
Synchronizer
PCI Exxpress Hard IP
PIPE Interface
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
PRBS
Verifier
2.7.2 Supported PIPE Features
PIPE Gen1, Gen2, and Gen3 configurations support different features.
Table 181.
Supported Features for PIPE Configurations
Protocol Feature
Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
Gen3
(8 Gbps)
x1, x2, x4, x8 link configurations
Yes
Yes
Yes
PCIe-compliant synchronization state machine
Yes
Yes
Yes
±300 ppm (total 600 ppm) clock rate compensation
Yes
Yes
Yes
Transmitter driver electrical idle
Yes
Yes
Yes
Receiver detection
Yes
Yes
Yes
8B/10B encoding/decoding disparity control
Yes
Yes
No
128b/130b encoding/decoding
No
No
Yes (supported
through the
Gearbox)
Scrambling/Descrambling
No
No
Yes
(implemented
in FPGA fabric)
(37)
Power state management
Yes
Yes
Yes
Receiver PIPE status encoding pipe_rxstatus[2:0]
Yes
Yes
Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate
No
Yes
No
continued...
(37)
You must enable scrambling/descrambling in Gen1/Gen2 when using Arria 10 PCIe Gen3
configurations.
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Protocol Feature
Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
Gen3
(8 Gbps)
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps
signaling rate
No
No
Yes
Dynamic transmitter margining for differential output voltage
control
No
Yes
Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB
No
Yes
Yes
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and
equalization
No
No
Yes
PCS PMA interface width (bits)
10
10
32
Implement in FPGA
fabric
Implement in
FPGA fabric
Implement in
FPGA fabric
Receiver Electrical Idle Inference (EII)
Related Links
•
PCIe Gen3 PCS Architecture on page 479
For more information about PIPE Gen3.
•
Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
•
Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0
2.7.2.1 Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data,
control, and status signals between the PHY-MAC layer and the transceiver channel
PCS and PMA blocks. The PIPE configuration is based on the PIPE 2.0 specification. If
you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in
the FPGA fabric.
2.7.2.1.1 Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
In a PIPE configuration, Native PHY IP Core provides an input signal pipe_rate
[1:0] that is functionally equivalent to the RATE signal specified in the PCIe
specification. A change in value from 2'b00 to 2'b01 on this input signal pipe_rate
[1:0] initiates a data rate switch from Gen1 to Gen2. A change in value from 2'b01
to 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1.
2.7.2.1.2 Transmitter Electrical Idle Generation
The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical
idle state when the electrical idle input signal is asserted. During electrical idle, the
transmitter buffer differential and common mode output voltage levels are compliant
with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain
power states.
Note:
For more information about input signal levels required in different power states, refer
to Power State Management in the next section.
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2.7.2.1.3 Power State Management
Table 182.
Power States Defined in the PCIe Specification
To minimize power consumption, the physical layer device must support the following power states.
Power States
Description
P0
Normal operating state during which packet data is transferred on the PCIe link.
P0s, P1, and P2
The PHY-MAC layer directs the physical layer to transition into these low-power states.
The PIPE interface in Arria 10 transceivers provides a pipe_powerdown input port for
each transceiver channel configured in a PIPE configuration.
The PCIe specification requires the physical layer device to implement power-saving
measures when the P0 power state transitions to the low power states. Arria 10
transceivers do not implement these power-saving measures except for putting the
transmitter buffer in electrical idle mode in the lower power states.
2.7.2.1.4 8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and
Status State Machine (LTSSM) enters the Polling.Compliance substate. The
Polling.Compliance substate assesses if the transmitter is electrically compliant with
the PCIe voltage and timing specifications.
2.7.2.1.5 Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status
signal pipe_rx_status[2:0]. This status signal is used by the PHY-MAC layer for its
operation. The PIPE interface block receives status signals from the transceiver
channel PCS and PMA blocks, and encodes the status on the pipe_rx_status[2:0]
signal to the FPGA fabric. The encoding of the status signals on the
pipe_rx_status[2:0] signal conforms to the PCIe specification.
2.7.2.1.6 Receiver Detection
The PIPE interface block in Arria 10 transceivers provides an input signal
pipe_tx_detectrx_loopback for the receiver detect operation. The PCIe protocol
requires this signal to be high during the Detect state of the LTSSM. When the
pipe_tx_detectrx_loopback signal is asserted in the P1 power state, the PIPE
interface block sends a command signal to the transmitter driver in that channel to
initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must
always be in the electrical idle state. After receiving this command signal, the receiver
detect circuitry creates a step voltage at the output of the transmitter buffer. The time
constant of the step voltage on the trace increases if an active receiver that complies
with the PCIe input impedance requirements is present at the far end. The receiver
detect circuitry monitors this time constant to determine if a receiver is present.
Note:
For the receiver detect circuitry to function reliably, the transceiver on-chip
termination must be used. Also, the AC-coupling capacitor on the serial link and the
receiver termination values used in your system must be compliant with the PCIe Base
Specification 2.0.
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The PIPE core provides a 1-bit PHY status signal pipe_phy_status and a 3-bit
receiver status signal pipe_rx_status[2:0] to indicate whether a receiver is
detected, as per the PIPE 2.0 specifications.
2.7.2.1.7 Gen1 and Gen2 Clock Compensation
In compliance with the PIPE specification, Arria 10 receiver channels have a rate
match FIFO to compensate for small clock frequency differences up to ±300 ppm
between the upstream transmitter and the local receiver clocks.
Consider the following guidelines for PIPE clock compensation:
•
Insert or delete one SKP symbol in an SKP ordered set.
•
Minimum limit is imposed on the number of SKP symbols in SKP ordered set after
deletion. An ordered set may have an empty COM case after deletion.
•
Maximum limit is imposed on the number of the SKP symbols in the SKP ordered
set after insertion. An ordered set may have more than five symbols after
insertion.
•
For INSERT/DELETE cases: The flag status appears on the COM symbol of the SKP
ordered set where insertion or deletion occurs.
•
For FULL/EMPTY cases: The flag status appears where the character is inserted or
deleted.
Note: When the PIPE interface is on, it translates the value of the flag to the
appropriate pipe_rx_status signal.
•
Figure 92.
The PIPE mode also has a “0 ppm” configuration option that you can use in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
Rate Match Deletion
This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be
deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.
SKP Symbol
Deleted
First SKP Ordered Set
Second SKP Ordered Set
rmfifo_input_data
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
rx_parallel_data
K28.5
Dx.y
K28.5
K28.0
K28.0
Dx.y
pipe_rx_status[2:0]
3’b010
xxx
3’b010
xxx
xxx
xxx
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K28.0
Dx.y
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Figure 93.
Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be
inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
First SKP Ordered Set
Second SKP Ordered Set
rmfifo_input_data
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.0
K28.0
rx_parallel_data
K28.5
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
pipe_rx_status[2:0]
3’b001
xxx
xxx
xxx
3’b001
xxx
xxx
xxx
xxx
xxx
SKP Symbol Inserted
Figure 94.
Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and
drives pipe_rx_status[2:0] = 3'b101 synchronous to the subsequent data byte. The figure below shows
the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data byte
D4.
Figure 95.
tx_parallel_data
D1
D2
D3
D4
D5
D6
D7
D8
rx_parallel_data
D1
D2
D3
D4
D6
D7
D8
xx
pipe_rx_status[2:0]
xxx
xxx
xxx
xxx
3’b101
xxx
xxx
xxx
xx
xx
Rate Match FIFO Empty
The rate match FIFO automatically inserts /K30.7/ (9'h1FE) after the data byte that causes the FIFO to become
empty and drives pipe_rx_status[2:0] = 3'b110 synchronous to the inserted /K30.7/ (9'h1FE). The figure
below shows rate match FIFO empty condition in PIPE mode. The rate match FIFO becomes empty after
reading out data byte D3.
tx_parallel_data
D1
D2
D3
D4
D5
D6
rx_parallel_data
D1
D2
D3
/K.30.7/
D4
D5
pipe_rx_status[2:0]
xxx
xxx
xxx
3’b110
xxx
xxx
PIPE 0 ppm
The PIPE mode also has a "0 ppm" configuration option that can be used in
synchronous systems. The Rate Match FIFO Block is not expected to do any clock
compensation in this configuration, but latency will be minimized.
2.7.2.1.8 PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for
Gen1, Gen2, and Gen3 data rates. The received serial data passes through the
receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is
then looped back to the transmitter serializer and transmitted out through the
transmitter buffer. The received data is also available to the FPGA fabric through the
rx_parallel_data port. This loopback mode is based on PCIe specification 2.0.
Arria 10 devices provide an input signal pipe_tx_detectrx_loopback to enable
this loopback mode.
Note:
This is the only loopback option supported in PIPE configurations.
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PCIe Reverse Parallel Loopback Mode Datapath
Transmitter Standard PCS
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
PRBS
Generator
Reverse Parallel
Loopback Path
Receiver PMA
FPGA
Fabric
Receiver Standard PCS
PCI Express Hard IP
Transmitter PMA
PIPE Interface
Figure 96.
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
PRBS
Verifier
Related Links
•
Arria 10 Standard PCS Architecture on page 463
•
Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0
2.7.2.2 Gen3 Features
The following subsections describes the Arria 10 transceiver block support for PIPE
Gen3 features.
The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based
interface controls PHY functions such as transmission of electrical idle, receiver
detection, and speed negotiation and control.
2.7.2.2.1 Auto-Speed Negotiation
PIPE Gen3 mode enables ASN between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3
(8.0 Gbps) signaling data rates. The signaling rate switch is accomplished through
frequency scaling and configuration of the PMA and PCS blocks using a fixed 32-bit
wide PIPE 3.0-based interface.
The PMA switches clocks between Gen1, Gen2, and Gen3 data rates. For a non bonded
x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded
x2, x4, x8 and x16 channels, the ASN module selects the master channel to control
the rate switch. The master channel distributes the speed change request to the other
PMA and PCS channels.
The PCIe Gen3 speed negotiation process is initiated when Hard IP or the FPGA fabric
requests a rate change. The ASN then places the PCS in reset, and dynamically shuts
down the clock paths to disengage the current active state PCS (either Standard PCS
or Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects
the correct PCS clock paths and datapath selection in the multiplexers. The ASN block
then sends a request to the PMA block to switch the data rate, and waits for a rate
change done signal for confirmation. When the PMA completes the rate change and
sends confirmation to the ASN block, the ASN enables the clock paths to engage the
new PCS block and releases the PCS reset. Assertion of the pipe_phy_status signal
by the ASN block indicates the successful completion of this process.
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Note:
In Native PHY IP core - PIPE configuration, you must set pipe_rate[1:0]to initiate
the transceiver datarate switch sequence.
2.7.2.2.2 Rate Switch
This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps),
Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes.
In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3
PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE
interface clock rate is adjusted to match the data throughput when a rate switch is
requested.
Table 183.
PIPE Gen3 32 bit PCS Clock Rates
PCIe Gen3 Capability Mode
Enabled
Gen1
Gen2
Gen3
Lane data rate
2.5 Gbps
5 Gbps
8 Gbps
PCS clock frequency
250 MHz
500 MHz
250 MHz
FPGA fabric IP clock
frequency
62.5 MHz
125 MHz
250 MHz
PIPE interface width
32-bit
32-bit
32-bit
pipe_rate [1:0]
2'b00
2'b01
2'b10
Figure 97.
Rate Switch Change
The block-level diagram below shows a high level connectivity between ASN and Standard PCS and Gen3 PCS.
Control Plane
Bonding Up
Standard PCS
PCS/PMA INF
Gen3 PCS
Gen3 ASN
(Gen1, Gen2, Gen3)
pipe_rate[1:0]
from FPGA Fabric
PMA
pipe_sw
pipe_sw_done
PHYSTATUS
GEN
PHYSTATUS
GEN
pipe_phy_status
TX
FIFO
/2
(for Gen1 Only)
pll_pcie_clk
Control Plane
Bonding Down
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The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows:
1.
The PHY-MAC layer implemented in FPGA fabric requests a rate change through
pipe_rate[1:0].
2.
The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts
the PCS reset.
3.
The ASN asserts the clock shutdown signal to the Standard PCS and Gen3 PCS to
dynamically shut down the clock.
4.
When the rate changes to or from the Gen3 speed, the ASN asserts the clock and
data multiplexer selection signals.
5.
The ASN uses a pipe_sw[1:0] output signal to send a rate change request to
the PMA.
6. The ASN continuously monitors the pipe_sw_done[1:0] input signal from the
PMA.
7.
After the ASN receives the pipe_sw_done[1:0] signal, it deasserts the clock
shut down signals to release the clock.
8. The ASN deasserts the PCS reset.
9. The ASN sends the speed change completion to the PHY-MAC interface. This is
done through the pipe_phy_status signal to PHY-MAC interface.
Figure 98.
Speed Change Sequence
pipe_tx_elecidle
pipe_rate[1:0]
00
10
pipe_sw[1:0]
00
10
pipe_sw_done[1:0]
00
10
pipe_phy_status
2.7.2.2.3 Gen3 Transmitter Electrical Idle Generation
In the PIPE 3.0-based interface, you can place the transmitter in electrical idle during
low power states. Before the transmitter enters electrical idle, you must send the
Electrical Idle ordered set, consisting of 16 symbols with value 0x66. During electrical
idle, the transmitter differential and common mode voltage levels are based on the
PCIe Base Specification 3.0.
2.7.2.2.4 Gen3 Clock Compensation
Enable this mode from the Parameter Editor when using the Gen3 PIPE transceiver
configuration rule.
To accommodate PCIe protocol requirements and to compensate for clock frequency
differences of up to ±300 ppm between source and termination equipment, receiver
channels have a rate match FIFO. The rate match FIFO adds or deletes four SKP
characters (32 bits) to keep the FIFO from becoming empty or full. If the rate match
FIFO is almost full, the FIFO deletes four SKP characters. If the rate match FIFO is
nearly empty, the FIFO inserts a SKP character at the start of the next available SKP
ordered set. The pipe_rx_status [2:0] signal indicates FIFO full, empty, insertion
and deletion.
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Note:
Refer to the Gen1 and Gen2 Clock Compensation section for waveforms.
Related Links
Gen1 and Gen2 Clock Compensation on page 232
2.7.2.2.5 Gen3 Power State Management
The PCIe base specification defines low power states for PHY layer devices to minimize
power consumption. The Gen3 PCS does not implement these power saving measures,
except when placing the transmitter driver in electrical idle in the low power state. In
the P2 low power state, the transceivers do not disable the PIPE block clock.
Figure 99.
P1 to P0 Transition
The figure below shows the transition from P1 to P0 with completion provided by pipe_phy_status.
tx_coreclkin
pipe_powerdown
P1
P0
pipe_phy_status
2.7.2.2.6 CDR Control
The CDR control block performs the following functions:
•
Controls the PMA CDR to obtain bit and symbol alignment
•
Controls the PMA CDR to deskew within the allocated time
•
Generates status signals for other PCS blocks
The PCIe base specification requires that the receiver L0s power state exit time be a
maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3 signaling rates. The
transceivers have an improved CDR control block to accommodate fast lock times.
Fast lock times are necessary for the CDR to relock to the new multiplier/divider
settings when entering or exiting Gen3 speeds.
2.7.2.2.7 Gearbox
As per the PIPE 3.0 specification, for every 128 bits that are moved across the Gen3
PCS, the PHY must transmit 130 bits of data. Intel uses the pipe_tx_data_valid
signal every 16 blocks of data to transmit the built-up backlog of 32 bits of data.
The 130-bit block is received as follows in the 32-bit data path: 34 (32+2-bit sync
header), 32, 32, 32. During the first cycle, the gearbox converts the 34-bit input data
to 32-bit data. During the next three clock cycles, the gearbox merges bits from
adjacent cycles. For the gearbox to work correctly, a gap must be provided in the data
for every 16 shifts because each shift contains two extra bits for converting the initial
34 bits to 32 bits in the gearbox. After 16 shifts, the gearbox has an extra 32 bits of
data that are transmitted out. This requires a gap in the input data stream, which is
achieved by driving pipe_tx_data_valid low for one cycle after every 16 blocks of
data.
Figure 100. Gen3 Data Transmission
tx_coreclkin
pipe_tx_sync_hdr 10
pipe_tx_blk_start
pipe_tx_data_valid
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2.7.3 How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes
Figure 101. Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode
X1 Network
6
fPLL1
CGB
Ch 5
CDR
ATX PLL1
6
Master
CGB1
CGB
Ch 4
CDR
4
6
CGB
Ch 3
CDR
Path for Clocking in
Gen1/Gen2 x1 Mode
6
CGB
fPLL0
Ch 2
CDR
Master
CGB0
4
6
CGB
Ch 1
CDR
ATX PLL0
6
CGB
Ch 0
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x1 mode.
2. Gen1/Gen2 x1 mode uses the ATX PLL or fPLL.
3. Gen1/Gen2 x1 can use any channel from the given bank for which the ATX PLL or fPLL is enabled.
4. Use the pll_pcie_clk from either the ATX PLL or fPLL. This is the hclk required by the PIPE interface.
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Path for Clocking in
Gen1/Gen2 x1 Mode
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Figure 102. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode
XN
Network
X6
Network
Ch 5
CGB
6
6
6
Connections Done
via X1 Network
CDR
6
Ch 4
CGB
fPLL1
Master
CGB
CDR
6
Ch 3
CGB
ATX PLL1
CDR
Ch 2
CGB
CDR
Ch 1
CGB
Master
CGB
CDR
6
Ch 0
CGB
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 x4 modes use the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6. In this case the Master PCS channel is logical channel 3 (physical channel 4).
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Figure 103. Use ATX PLL or fPLL for Gen1/Gen2 x8 Mode
CGB
6
6
6
CDR
6
CGB
Master
CGB
Ch 5
Ch 4
CDR
6
CGB
Ch 3
CDR
Connections Done
via X1 Network
CGB
fPLL1
Master
CGB
Use Any
One PLL
Transceiver
bank
CDR
6
CGB
ATX PLL1
Ch 2
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
CDR
CGB
Master
CGB
6
Notes:
1. Figure shown is just one possible combination for the PCIe Gen1/Gen2 x8 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.
4. Gen1/Gen2 x8 mode uses the ATX PLL or fPLL only.
5. Use the pll_pcie_clk from either the ATX or fPLL. This is the hclk required by the PIPE interface.
6. In this case the Master PCS channel is logical channel 4 (Ch 1 in the top bank).
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Ch 4
CDR
Transceiver
bank
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Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode
X1 Network
6
fPLL1
CGB
Ch 5
CDR
ATX PLL1
6
Master
CGB1
CGB
Ch 4
CDR
4
6
CGB
Ch 3
CDR
6
CGB
fPLL0
Ch 2
CDR
Master
CGB0
4
6
CGB
Ch 1
CDR
ATX PLL0
6
CGB
Ch 0
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.
2. Gen1/Gen2 modes use the fPLL only.
3. Gen3 mode uses the ATX PLL only.
4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
5. Select the number of TX PLLs (2) in the Native PHY IP core wizard.
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Figure 105. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 Mode
X6
Network
XN
Network
CGB
6
6
6
Connections Done
via X1 Network
CDR
6
CGB
fPLL1
Master
CGB
Ch 4
CDR
6
CGB
ATX PLL1
Ch 5
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Master
CGB
Ch 1
CDR
6
CGB
Ch 0
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x4 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines.
4. Gen1/Gen2 modes use the fPLL only.
5. Gen3 mode uses the ATX PLL only.
6. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
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Figure 106. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x8 Mode
CGB
6
6
6
CDR
6
CGB
Master
CGB
Ch 5
Ch 4
CDR
6
CGB
Ch 3
CDR
Connections Done
via X1 Network
CGB
fPLL1
Master
CGB
Transceiver
bank
CDR
6
CGB
ATX PLL1
Ch 2
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
CDR
CGB
Master
CGB
6
Ch 4
Transceiver
bank
CDR
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x8 mode.
2. The x6 and xN clock networks are used for channel bonding applications.
3. Each master CGB drives one set of x6 clock lines. The x6 lines further drive the xN lines.
4. Gen1/Gen2 x8 modes use the fPLL only.
5. Gen3 mode uses the ATX PLL only.
6. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
Related Links
•
Using PLLs and Clock Networks on page 386
For more information about implementing clock configurations and configuring
PLLs.
•
PIPE Design Example
For more information about the PLL configuration for PCIe.
•
Transmit PLL recommendation based on Data rates on page 337
For more information about ATX PLL placement restrictions
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2.7.4 How to Implement PCI Express (PIPE) in Arria 10 Transceivers
You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL
architecture, and the reset controller before implementing the PCI Express protocol.
1.
Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core.
Refer to Select and Instantiate the PHY IP Core on page 31 for more details.
2. Select Gen1/Gen2/Gen3 PIPE from the Arria 10 Transceiver configuration
rules list, located under Datapath Options.
3. Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
PCI Express Transceiver Configurations Rules as a starting point. Alternatively, you
can use Arria 10 Transceiver Native PHY Presets . You can then modify the
settings to meet your specific requirements.
4.
Click Finish to generate the Native PHY IP (this is your RTL file).
5.
Instantiate and configure your PLL.
6.
Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in Transceiver Native PHY IP Ports for PCI Express Transceiver
Configuration Rules to connect the ports.
8. Simulate your design to verify its functionality.
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Figure 107. Connection Guidelines for a PIPE Gen3 Design
pll_pcie_clk
tx_serial_clk
(1)
tx_bonding_clocks
pipe_hclk_in
rx_cal_busy
rx_islockedtoref
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
pll_locked
pll_cal_busy
pll_powerdown
mcgb_aux_clk
Arria 10
Transceiver
Native PHY
tx_cal_busy
tx_bonding_clocks
fPLL
(Gen1/Gen2)
pll_cal_busy
ATX PLL
and Master
CGB (Gen3)
pll_locked
pll_refclk
tx_ready
rx_ready
clock
reset
Reset Controller (2)
Notes:
(1). If you enable the input pll_cal_busy port in the Transceiver PHY Reset Controller, you
can connect the pll_cal_busy output signals from the PLLs directly to the input
port on the reset-controller without ORing the tx_cal_busy and pll_cal_busy
signals.
(2).
a. If you are using the Transceiver PHY Reset Controller, you must configure the TX digital
reset mode and RX digital reset mode to Manual to avoid resetting the Auto Speed
Negotiation (ASN) block which handles the rate switch whenever the channel PCS
is reset.
b. When the TX digitalreset is in Auto mode, the associated tx_digitalreset controller
automatically resets whenever the pll_locked signal is deasserted. When in Manual
mode, the associated tx_digitalreset controller is not reset when the pll_locked signal
is deasserted, allowing the user to choose what to do.
c. When the RX digitalreset is in Auto mode, the associated rx_digitalreset controller
automatically resets whenever the rx_is_lockedtodata signal is deasserted. When in
Manual mode, the associated rx_digitalreset controller is not reset when the
rx_is_lockedtodata signal is deasserted, allowing the user to choose what to do.
d. If the resets are configured to Auto mode for PIPE designs, then the digital reset
will get asserted automatically when the lock signal is deasserted.
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Recommendations:
Intel recommends that you not reset the PLL and channels (TX and RX) when using
the PIPE mode of Native PHY. This is to avoid resetting the Auto Speed Negotiation
(ASN) block in the PCS.
Related Links
•
PLLs on page 337
For information about PLL architecture and implementation details.
•
Arria 10 Standard PCS Architecture on page 463
•
Resetting Transceiver Channels on page 402
For information about the Reset controller and implementation details.
2.7.5 Native PHY IP Parameter Settings for PIPE
Table 184.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
Parameter
Message level for rule violations
Error
Error
Error
VCCR_GXB and VCCT_GXB
supply voltage for the
Transceiver
Gen1: 1_1V, 1_0V, 0_9V
Gen2: 1_1V, 1_0V, 0_9V
Gen3: 1_1V, 1_0V, 0_9V
Transceiver link type
Gen1: sr,lr
Gen2: sr,lr
Gen3: sr,lr
Transceiver configuration rules
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
PMA configuration rules
Basic
Basic
Basic
Transceiver mode
TX / RX Duplex
TX / RX Duplex
TX / RX Duplex
Number of data channels
Gen1
Gen1
Gen1
Gen1
Gen2
Gen2
Gen2
Gen2
Gen3
Gen3
Gen3
Gen3
Common PMA Options
Datapath Options
x1:
x2:
x4:
x8:
1
2
4
8
channel
channels
channels
channels
x1:
x2:
x4:
x8:
1
2
4
8
channel
channels
channels
channels
x1:
x2:
x4:
x8:
1
2
4
8
channel
channels
channels
channels
Data rate
2.5 Gbps
5 Gbps
5 Gbps(38)
Enable datapath and interface
reconfiguration
Optional
Optional
Optional
Enable simplified data interface
Provide separate interface for
each channel
Optional
(39)
Optional
Optional
(39)
Optional
Optional
(39)
Optional
(38)
The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for 8 Gbps.
(39)
Refer to Table 191 on page 261 for bit settings when simplified data interface is enabled.
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Table 185.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
TX Bonding Options
TX channel bonding mode
PCS TX channel bonding master
Default PCS TX channel bonding master
Nonbonded (x1)
PMA & PCS Bonding
Auto
Gen1
Gen1
Gen1
Gen1
(40)
x1:
x2:
x4:
x8:
Nonbonded (x1)
PMA & PCS Bonding
Auto
0
1
2
4
Gen1
Gen1
Gen1
Gen1
(40)
x1:
x2:
x4:
x8:
Nonbonded (x1)
PMA & PCS Bonding
Auto
0
1
2
4
Gen1
Gen1
Gen1
Gen1
(40)
x1:
x2:
x4:
x8:
0
1
2
4
TX PLL Options
TX local clock division factor
1
1
Number of TX PLL clock inputs per
channel
1
1
Initial TX PLL clock input selection
1
Gen3 x1: 2
All other modes: 1
0
0
Gen1 / Gen2 clock
connection should be
used for Initial clock
input selection in
Gen3x1
All other modes: 0
Enable tx_analog_reset_ack port
Optional
Optional
Optional
Enable tx_pma_clkout port
Optional
Optional
Optional
Enable tx_pma_div_clkout port
Optional
Optional
Optional
tx_pma_div_clkout division factor
Optional
Optional
Optional
Enable tx_pma_elecidle port
Off
Off
Off
Enable tx_pma_qpipullup port (QPI)
Off
Off
Off
Enable tx_pma_qpipulldn port (QPI)
Off
Off
Off
Enable tx_pma_txdetectrx port (QPI)
Off
Off
Off
Enable tx_pma_rxfound port (QPI)
Off
Off
Off
Enable rx_seriallpbken port
Off
Off
Off
TX PMA Optional Ports
(40)
Setting this parameter is placement-dependent. In AUTO mode, the Native PHY IP Parameter
Editor will select the middle-most channel of the configuration as the default PCS TX channel
bonding master. You must ensure that this selected channel is physically placed as Ch1 or Ch4
of the transceiver bank. Else, use the manual selection for the PCS TX channel bonding master
to select a channel that can be physically placed as Ch1 or Ch4 of the transceiver bank. Refer
to section How to place channels for PIPE configurations for more details.
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Table 186.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX
PMA
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
Number of CDR reference clocks
1
1
1
Selected CDR reference clock
0
0
0
100, 125 MHz
100, 125 MHz
100, 125 MHz
1000
1000
1000
Manual / Triggered
Manual / Triggered
Manual / Triggered
Disabled
Disabled
Disabled
NA
NA
NA
Enable rx_analog_reset_ack port
Optional
Optional
Optional
Enable rx_pma_clkout port
Optional
Optional
Optional
Enable rx_pma_div_clkout port
Optional
Optional
Optional
rx_pma_div_clkout division factor
Optional
Optional
Optional
Enable rx_pma_clkslip port
Optional
Optional
Optional
Off
Off
Off
Enable rx_is_lockedtodata port
Optional
Optional
Optional
Enable rx_is_lockedtoref port
Optional
Optional
Optional
Enable rx_set_locktodata and
rx_set_locktoref ports
Optional
Optional
Optional
Enable rx_seriallpbken port
Optional
Optional
Optional
Enable PRBS Verifier Control and Status
ports
Optional
Optional
Optional
RX CDR Options
Selected CDR reference clock frequency
PPM detector threshold
Equalization
CTLE adaptation mode
Note:
Triggered adaptation mode is
used only for PCIe Gen3.
DFE adaptation mode
Number of fixed dfe taps
RX PMA Optional Ports
Enable rx_pma_qpipulldn port (QPI)
Table 187.
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes Standard PCS
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
10
10
10(41)
Standard PCS configurations
Standard PCS / PMA interface width
continued...
(41)
The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA
width of 32.
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Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
FPGA Fabric / Standard TX PCS interface
width
8, 16
16
32
FPGA Fabric / Standard RX PCS interface
width
8, 16
16
32
Off
Off
Off
TX FIFO mode
low_latency
low_latency
low_latency
RX FIFO mode
low_latency
low_latency
low_latency
Enable tx_std_pcfifo_full port
Optional
Optional
Optional
Enable tx_std_pcfifo_empty port
Optional
Optional
Optional
Enable rx_std_pcfifo_full port
Optional
Optional
Optional
Enable rx_std_pcfifo_empty port
Optional
Optional
Optional
TX byte serializer mode
Disabled, Serialize x2
Serialize x2
Serialize x4
RX byte deserializer mode
Disabled, Serialize x2
Serialize x2
Deserialize x4
Enable TX 8B/10B encoder
Enabled
Enabled
Enabled
Enable TX 8B/10B disparity control
Enabled
Enabled
Enabled
Enable RX 8B/10B decoder
Enabled
Enabled
Enabled
Enable Standard PCS low latency mode
Standard PCS FIFO
Byte Serializer and Deserializer
8B/10B Encoder and Decoder
Rate Match FIFO
Rate Match FIFO mode
PIPE, PIPE 0ppm
PIPE, PIPE 0ppm
PIPE, PIPE 0ppm
RX rate match insert / delete -ve pattern
(hex)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/
K28.0/)
RX rate match insert / delete +ve
pattern (hex)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83
(K28.5/K28.0/)
Enable rx_std_rmfifo_full port
Optional
Optional
Optional
Enable rx_std_rmfifo_empty port
Optional
Optional
Optional
Bypass
Bypass
600
Off
Off
Off
Optional
Optional
Optional
Synchronous State
Machine
Synchronous State
Machine
Synchronous State
Machine
RX word aligner pattern length
10
10
10
RX word aligner pattern (hex)
0x0000 00000000017c (/
K28.5/)
0x0000 00000000017c (/
K28.5/)
0x0000
00000000017c(/
K28.5/)
PCI Express Gen 3 rate match FIFO
mode
Word Aligner and Bit Slip
Enable TX bit slip
Enable tx_std_bitslipboundarysel
port
RX word aligner mode
continued...
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Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE
3
3
3
Number of invalid data words to lose
sync
16
16
16
Number of valid data words to
decrement error count
15
15
15
Optional
Optional
Optional
Off
Off
Off
Optional
Optional
Optional
Off
Off
Off
Enable TX bit reversal
Off
Off
Off
Enable TX byte reversal
Off
Off
Off
Enable TX polarity inversion
Off
Off
Off
Enable tx_polinv port
Off
Off
Off
Enable RX bit reversal
Off
Off
Off
Enable rx_std_bitrev_ena port
Off
Off
Off
Enable RX byte reversal
Off
Off
Off
Enable rx_std_byterev_ena port
Off
Off
Off
Enable RX polarity inversion
Off
Off
Off
Enable rx_polinv port
Off
Off
Off
Optional
Optional
Optional
Off
Enabled
Enabled
Enabled
Enabled
Enabled
Enable PCIe Gen3 analog control ports
Off
Off
Enabled
Enable PCIe electrical idle control and
status ports
Enabled
Enabled
Enabled
Enable PCIe pipe_rx_polarity port
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Number of word alignment patterns to
achieve sync
Enable rx_std_wa_patternalign port
Enable rx_std_wa_a1a2size port
Enable rx_std_bitslipboundarysel
port
Enable rx_bitslip port
Bit Reversal and Polarity Inversion
Enable rx_std_signaldetect port
PCIe Ports
Enable PCIe dynamic datarate switch
ports
Enable PCIe pipe_hclk_in and
pipe_hclk_out ports
Dynamic reconfiguration
Enable dynamic reconfiguration
Note:
The signals in the left-most column are automatically mapped to a subset of a 128-bit
tx_parallel_data word when the Simplified Interface is enabled.
Related Links
•
How to Place Channels for PIPE Configurations on page 266
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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•
Bit Mappings When the Simplified Interface Is Disabled on page 261
2.7.6 fPLL IP Parameter Core Settings for PIPE
Table 188.
Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE (For Gen1/
Gen2 speeds)
PLL
General
fPLL mode
Transceiver
Transceiver
Transceiver
Protocol Mode
PCIe Gen 1
PCIe Gen 2
PCIe Gen 2
Message level for rule
violation
Error
Error
Error
Number of PLL reference
clocks
1
1
1
Selected reference clock
source
0
0
0
Enable fractional mode
Disable
Disable
Disable
Enable manual counter
configuration
Disable
Disable
Disable
Enable ATX to fPLL cascade
clock input port
Disable
Disable
Disable
Low, Medium, High
Low, Medium, High
Low, Medium, High
Direct
Direct
Direct
PLL output frequency
1250MHz
2500MHz
2500MHz
PLL datarate
2500Mbps
5000Mbps
5000Mbps
PLL integer reference clock
frequency
100 MHz, 125 MHZ
100 MHz, 125 MHZ
100 MHz, 125 MHZ
Settings
Bandwidth
Feedback
Operation mode
Output frequency
Transceiver usage
Master Clock Generation Block (MCGB)
Include master clock
generation block
Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
Clock division factor
N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Enable x6/xN non-bonded
high-speed clock output port
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
N/A for x2,x4, x8
Enable PCIe clock switch
interface
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
continued...
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Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE (For Gen1/
Gen2 speeds)
Number of auxiliary MCGB
clock input ports
N/A for x1
0 for x2, x4, x8
N/A for x1
0 for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
MCGB input clock frequency
1250MHz
2500MHz
2500MHz
MCGB output data rate
2500Mbps
5000Mbps
5000Mbps
Enable bonding clock output
ports
N/A for x1 design
Enable for x2, x4, x8
N/A for x1 design
Enable for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Enable feedback
compensation bonding
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
PMA interface width
N/A for x1 design
10 for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
N/A for x1
N/A for x2, x4, x8
Enable dynamic
reconfiguration
Disable
Disable
Disable
Enable Altera Debug Master
Endpoint
Disable
Disable
Disable
Separate avmm_busy from
reconfig_waitrequest
N/A
N/A
N/A
Bonding
Dynamic Reconfiguration
Optional Reconfiguration Logic
Enable capability registers
N/A
N/A
N/A
Set user-defined IP identifier
N/A
N/A
N/A
Enable control and status
registers
N/A
N/A
N/A
Configuration file prefix
N/A
N/A
N/A
Generate SystemVerilog
package file
N/A
N/A
N/A
Generate C Header file
N/A
N/A
N/A
Generate MIF (Memory
Initialize file)
N/A
N/A
N/A
Enable
Enable
Enable
Configuration Files
Generation Options
Generate parameter
documentation file
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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2.7.7 ATX PLL IP Parameter Core Settings for PIPE
Table 189.
Parameters for Arria 10 ATX PLL IP core in PIPE Gen1, Gen2, Gen3 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE (For Gen3
speed)
PLL
General
Message level for rule violations
Error
Error
Error
Protocol Mode
PCIe Gen 1
PCIe Gen 2
PCIe Gen 3
Bandwidth
Low, medium, high
Low, medium, high
Low, medium, high
Number of PLL reference clocks
1
1
1
Selected reference clock source
0
0
0
Primary PLL clock output buffer
GX clock output buffer
GX clock output buffer
GX clock output buffer
Enable PLL GX clock output port
Enable
Enable
Enable
Enable PLL GT clock output port
Disable
Disable
Disable
Enable PCIe clock output port
pll_pcie_clk
Enable
Enable
Disable (Use the pll_pcie_clk
output port from the fPLL to
drive the hclk)
Enable ATX to fPLL cascade clock output
port
Disable
Disable
Disable
PLL output frequency
1250MHz
2500MHz
4000MHz
PLL output datarate
2500Mbps
5000Mbps
8000Mbps
Enable fractional mode
Disable
Disable
Disable
PLL integer reference clock frequency
100MHz, 125MHZ
100MHz, 125MHZ
100MHz, 125MHZ
Configure counters manually
Disable
Disable
Disable
Multiple factor (M counter)
N/A
N/A
N/A
Divide factor (N counter)
N/A
N/A
N/A
Divide factor (L counter)
N/A
N/A
N/A
Include master clock generation block
Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Disable for x1
Enable for x2, x4, x8
Clock division factor
N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
Enable x6/xN non-bnded high speed
clock output port
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
N/A for x1
Disable for x2, x4, x8
Enable PCIe clock switch interface
N/A for x1
Disable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
Ports
Output Frequency
Master Clock Generation Block
MCGB
continued...
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Parameter
Gen1 PIPE
Gen2 PIPE
Gen3 PIPE (For Gen3
speed)
Number of auxiliary MCGB clock input
ports
N/A for x1
0 for x2, x4, x8
N/A for x1
0 for x2, x4, x8
N/A for x1
1 for x2, x4, x8
MCGB input clock frequency
1250 MHz
2500 MHz
4000 MHz
MCGB output data rate
2500 Mbps
5000 Mbps
8000 Mbps
Enable bonding clock output ports
N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
N/A for x1
Enable for x2, x4, x8
Enable feedback compensation bonding
N/A for x1 design
Disable for x2, x4, x8
N/A for x1 design
Disable for x2, x4, x8
Disable for x1
Disable for x2, x4, x8
PMA interface width
N/A for x1 design
10 for x2, x4, x8
N/A for x1 design
10 for x2, x4, x8
N/A for x1
10 for x2, x4, x8
Enable dynamic reconfiguration
Disable
Disable
Disable
Enable Altera Debug Master Endpoint
Disable
Disable
Disable
Separate avmm_busy from
reconfig_waitrequest
N/A
N/A
N/A
Enable capability registers
N/A
N/A
N/A
Set user-defined IP identifier
N/A
N/A
N/A
Enable control and status registers
N/A
N/A
N/A
Configuration file prefix
N/A
N/A
N/A
Generate SystemVerilog package file
N/A
N/A
N/A
Generate C Header file
N/A
N/A
N/A
Generate MIF (Memory Initialize file)
N/A
N/A
N/A
Enable
Enable
Enable
Bonding
Dynamic Reconfiguration
Optional Reconfiguration Logic
Configuration Files
Generation Options
Generate parameter documentation file
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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2.7.8 Native PHY IP Ports for PIPE
Figure 108. Signals and Ports of Native PHY IP for PIPE
Arria 10 Transceiver Native PHY
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digitalreset
tx_datak [3:0], [1:0], or [0]
tx_parallel_data [31:0], [15:0], or [7:0]
tx_coreclkin
tx_clkout
pipe_rx_elecidle [(N-1):0]
pipe_phy_status [(N-1):0]
pipe_rx_data_valid [(N-1):0]
pipe_rx_sync_hdr [(2N-1):0]
pipe_rx_blk_start [(N-1):0]
pipe_rate [1:0]
pipe_g3_tx_deemph [(18N-1):0]
pipe_g3_rxpresethint [(3N-1):0]
pipe_sw_done [1:0]
pipe_rx_polarity [(N-1):0]
pipe_tx_elecidle [(4N-1):0]
pipe_tx_detectrx_loopback [(N-1):0]
pipe_powerdown [(2N-1):0]
pipe_rx_eidleinfersel [(3N-1):0]
pipe_tx_sync_hdr [(2N-1):0]
pipe_tx_data_valid [(N-1):0]
pipe_tx_blk_start [(N-1):0]
pipe_tx_deemph [(N-1):0]
tx_bonding_clocks[(6n-1):0]
Reconfiguration
Registers
TX Standard PCS
tx_datak [3:0], [1:0], or [0]
tx_parallel_data[31:0],[15:0],or[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
Nios II Hard
Calibration IP
tx_cal_busy
rx_cal_busy
TX PMA
10
Serializer
tx_serial_data
pipe_hclk_out [0]
pipe_hclk_in [0] (from TX PLL)
pipe_tx_compliance [(4N-1):0]
pipe_tx_margin [(3N-1):0]
pipe_tx_swing [(N-1):0]
pipe_rx_valid [(N-1):0]
pipe_rx_status [(3N-1):0]
pipe_sw [1:0]
PIPE Interface
-
Local CGB
(for X1 Modes Only
tx_serial_data
tx_analogreset
rx_analogreset
rx_digitalreset
rx_datak [3:0], [1:0], or [0]
rx_parallel_data [31:0], [15:0], or [7:0]
rx_clkout
rx_coreclkin
rx_syncstatus
RX Standard PCS
rx_datak [3:0], [1:0], or [0]
rx_parallel_data[31:0],[15:0],or[7:0]
rx_clkout
rx_coreclkin
rx_syncstatus
unused_rx_parallel_data[118:0]
RX PMA
Deserializer
CDR
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Gen1/Gen2/Gen3 - Black
Gen2/Gen3 - Red
Gen3 - Blue
Note: N is the number of PCIe channels
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Table 190.
Ports for Arria 10 Transceiver Native PHY in PIPE Mode
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Direction
Clock Domain
Description
Clocks
rx_cdr_refclk0
In
N/A
tx_serial_clk0/
In
N/A
tx_serial_clk1
The 100/125 MHz input reference clock
source for the PHY's TX PLL and RX CDR.
The high speed serial clock generated by the
PLL.
Note: For Gen3 x1 ONLY tx_serial_clk1
is used.
pipe_hclk_in[0]
In
N/A
The 500 MHz clock used for the ASN block.
This clock is generated by the PLL,
configured for Gen1/Gen2.
Note: For Gen3 designs, use from the fPLL
that is used for Gen1/Gen2.
pipe_hclk_out[0]
Out
N/A
The 500 MHz clock output provided to the
PHY - MAC interface.
PIPE Input from PHY - MAC Layer
The TX parallel data driven from the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2
this is 16 bits. For Gen3 this is 32 bits.
tx_parallel_data[31:0],
[15:0], or [7:0]
tx_datak[3:0], [1:0], or
[0]
In
tx_coreclkin
Note: unused_tx_parallel_data should
be tied to '0'.
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for
additional details.
The data and control indicator for the
transmitted data.
For Gen1 or Gen2, when 0, indicates that
tx_parallel_data is data, when 1,
indicates that tx_parallel_data is
control.
In
tx_coreclkin
For Gen3, bit[0] corresponds to
tx_parallel_data[7:0], bit[1]
corresponds to tx_parallel_data[15:8],
and so on.
Active High. Refer to table Bit Mappings when
the Simplified Interface is Disabled for
additional details.
pipe_tx_sync_hdr[(2N-1)
:0](42)
In
tx_coreclkin
For Gen3, indicates whether the 130-bit
block transmitted is a Data or Control
Ordered Set Block.
The following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set Block
This value is read when
pipe_tx_blk_start = 1b'1.
Refer to Lane Level Encoding in the PCI
Express Base Specification, Rev. 3.0 for a
detailed explanation of data transmission and
reception using 128b/130b encoding and
decoding.
continued...
(42)
N is the number of PCIe channels.
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Port
Direction
Clock Domain
Description
Not used for Gen1 and Gen2 data rates.
Active High
pipe_tx_blk_start[(N-1)
:0]
pipe_tx_elecidle[(4N-1)
:0]
pipe_tx_detectrx_loopba
ck [(N-1):0]
pipe_tx_compliance[(4N1):0]
In
In
In
In
tx_coreclkin
For Gen3, specifies the start block byte
location for TX data in the 128-bit block data.
Used when the interface between the PCS
and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
Asynchronous
Forces the transmit output to electrical idle.
Refer to the Intel PHY Interface for PCI
Express (PIPE) for timing diagrams.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane. For
example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_elecidle[7:0] =
{{2{tx_elecidle_ch3}},
{2{tx_elecidle_ch2}},{2{tx_elecidle_ch1}},
{2{tx_elecidle_ch0}}} where tx_elecidle_*
is the output signal from MAC.
Gen3 - Width of signal is 4 bits/lane. For
example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_elecidle[15:0] =
{{4{tx_elecidle_ch3}},
{4{tx_elecidle_ch2}},{4{tx_elecidle_ch1}},
{4{tx_elecidle_ch0}}} where tx_elecidle_*
is the output signal from MAC.
Active High
tx_coreclkin
Instructs the PHY to start a receive detection
operation. After power-up, asserting this
signal starts a loopback operation. Refer to
section 6.4 of the Intel PHY Interface for PCI
Express (PIPE) for a timing diagram.
Active High
tx_coreclkin
Asserted for one cycle to set the running
disparity to negative. Used when transmitting
the compliance pattern. Refer to section 6.11
of the Intel PHY Interface for PCI Express
(PIPE) Architecture for more information.
Gen1 - Width of signal is 1 bit/lane.
Gen2 - Width of signal is 2 bits/lane.
For example, if the MAC connected to PIPE
Gen2x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_compliance[7:0] =
{{2{tx_compliance_ch3}},
{2{tx_compliance _ch2}},
{2{tx_compliance_ch1}}, {2{tx_compliance
_ch0}}}. Where tx_compliance_* is the
output signal from MAC.
Gen3 - Width of signal is 4 bits/lane.
For example, if the MAC connected to PIPE
Gen3x4 has 1bit/lane, then you can use the
following mapping to connect to PIPE:
{pipe_tx_compliance[15:0]= {{4{tx_
compliance _ch3}}, {4{tx_ compliance
continued...
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Port
Direction
Clock Domain
Description
_ch2}}, {4{tx_ compliance _ch1}}, {4{tx_
compliance _ch0}}}. Where tx_ compliance
_* is the output signal from MAC.
Active High
pipe_rx_polarity[(N-1):
0]
pipe_powerdown[(2N-1):
0]
pipe_tx_margin[(3N-1):
0]
pipe_tx_swing[(N-1):0]
In
In
In
In
Asynchronous
When 1'b1, instructs the PHY layer to invert
the polarity on the received data.
Active High
tx_coreclkin
Requests the PHY to change its power state
to the specified state. The Power States are
encoded as follows:
2'b00: P0 - Normal operation.
2'b01: P0s - Low recovery time, power
saving state.
2'b10: P1 - Longer recovery time, lower
power state .
2'b11: P2 - Lowest power state.
tx_coreclkin
Transmit VOD margin selection. The PHY-MAC
sets the value for this signal based on the
value from the Link Control 2 Register. The
following encodings are defined:
3'b000: Normal operating range
3'b001: Full swing: 800 - 1200 mV; Half
swing: 400 - 700 mV.
3'b010:-3'b011: Reserved.
3'b100-3'b111: Full swing: 200 - 400mV;
Half swing: 100 - 200 mV else reserved.
tx_coreclkin
Indicates whether the transceiver is using
Full swing or Half swing voltage as defined by
the pipe_tx_margin.
1'b0-Full swing.
1'b1-Half swing.
pipe_tx_deemph[(N-1):0]
pipe_g3_tx_deemph[(18N1):0]
In
In
Asynchronous
Asynchronous
Transmit de-emphasis selection. In PCI
Express Gen2 (5 Gbps) mode it selects the
transmitter de-emphasis:
1'b0: –6 dB.
1'b1: –3.5 dB.
The pipe_g3_tx_deemph port is used to
select the link partners transmitter deemphasis during equalization. The 18 bits
specify the following coefficients:
[5:0]: C-1
[11:6]: C0
[17:12]: C+1
Refer to Preset Mappings to TX De-emphasis
on page 265 for presets to TX de-emphasis
mappings. In Gen3 capable designs, the TX
de-emphasis for Gen2 data rate is always -6
dB. The TX de-emphasis for Gen1 data rate
is always -3.5 dB.
Refer to section 6.6 of Intel PHY Interface for
PCI Express (PIPE) Architecture for more
information.
Note: Intel recommends transmitting Preset
P8 coefficients for Arria 10 receiver to
recover data successfully.
continued...
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Port
pipe_g3_rxpresethint[(3
N-1):0]
pipe_rx_eidleinfersel[(
3N-1):0]
Direction
In
In
Clock Domain
Description
Asynchronous
This is used to trigger CTLE adaptation in
Phase2 (EP) /Phase 3 (RP) to achieve
receiver Bit Error Rate (BER) that is less than
10-12.
Gen3 capable design at Gen1/Gen2 speeds:
This should be set to 3’b000.
Gen3 capable design at Gen3 speed: Refer to
section “PHY IP Core for PCIe (PIPE) Link
Equalization for Gen3 Data Rate” for details
on when to set/reset this port.
Asynchronous
When asserted high, the electrical idle state
is inferred instead of being identified using
analog circuitry to detect a device at the
other end of the link. The following encodings
are defined:
3'b0xx: Electrical Idle Inference not required
in current LTSSM state.
3'b100: Absence of COM/SKP OS in 128 ms.
3'b101: Absence of TS1/TS2 OS in 1280 UI
interval for Gen1 or Gen2.
3'b110: Absence of Electrical Idle Exit in
2000 UI interval for Gen1 and 16000 UI
interval for Gen2.
3'b111: Absence of Electrical Idle exit in 128
ms window for Gen1.
Note: Recommended to implement Receiver
Electrical Idle Inference (EII) in FPGA
fabric.
pipe_rate[1:0]
pipe_sw_done[1:0]
pipe_tx_data_valid[(N-1
):0]
In
In
In
Asynchronous
The 2-bit encodings defined in the following
list:
2'b00: Gen1 rate (2.5 Gbps)
2'b01: Gen2 rate (5.0 Gbps)
2'b10: Gen3 rate (8.0 Gbps)
N/A
Signal from the Master clock generation
buffer, indicating that the rate switch has
completed. Use this signal for bonding mode
only.
For non-bonded applications, this signal is
internally connected to the local CGB.
tx_coreclkin
For Gen3, this signal is deasserted by the
MAC to instruct the PHY to ignore
tx_parallel_data for current clock cycle.
A value of 1'b1 indicates the PHY should use
the data. A value of 0 indicates the PHY
should not use the data.
Active High
PIPE Output to PHY - MAC Layer
rx_parallel_data[31:0],
[15:0], or [7:0]
Out
rx_coreclkin
rx_datak[3:0], [1:0], or
[0]
Out
rx_coreclkin
The RX parallel data driven to the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2
this is 16 bits only. For Gen3 this is 32
bits.Refer to Bit Mappings When the
Simplified Interface is Disabled for more
details.
The data and control indicator.
continued...
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Port
Direction
Clock Domain
Description
For Gen1 or Gen2, when 0, indicates that
rx_parallel_data is data, when 1,
indicates that rx_parallel_data is
control.
For Gen3, Bit[0] corresponds to
rx_parallel_data[7:0], Bit[1]
corresponds to rx_parallel_data[15:8],
and so on. Refer to tableBit Mappings When
the Simplified Interface is Disabled for more
details.
pipe_rx_sync_hdr[(2N-1)
:0]
pipe_rx_blk_start[(N-1)
:0]
Out
Out
rx_coreclkin
For Gen3, indicates whether the 130-bit
block being transmitted is a Data or Control
Ordered Set Block. The following encodings
are defined:
2'b10: Data block
2'b01: Control Ordered Set block
This value is read when
pipe_rx_blk_start = 4'b0001. Refer to
Section 4.2.2.1. Lane Level Encoding in the
PCI Express Base Specification, Rev. 3.0 for
a detailed explanation of data transmission
and reception using 128b/130b encoding and
decoding.
rx_coreclkin
For Gen3, specifies the start block byte
location for RX data in the 128-bit block
data. Used when the interface between the
PCS and PHY-MAC (FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data rates.
Active High
pipe_rx_data_valid[(N-1
):0]
Out
rx_coreclkin
For Gen3, this signal is deasserted by the
PHY to instruct the MAC to ignore
rx_parallel_data for current clock cycle.
A value of 1'b1 indicates the MAC should use
the data. A value of 1'b0 indicates the MAC
should not use the data.
Active High
pipe_rx_valid[(N-1):0]
Out
rx_coreclkin
Asserted when RX data and control are valid.
pipe_phy_status[(N-1):
0]
Out
rx_coreclkin
Signal used to communicate completion of
several PHY requests.
Active High
continued...
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Port
Direction
Clock Domain
Description
pipe_rx_elecidle[(N-1):
0]
Out
Asynchronous
When asserted, the receiver has detected an
electrical idle.
Active High
rx_coreclkin
Signal encodes receive status and error
codes for the receive data stream and
receiver detection. The following encodings
are defined:
3'b000 - Receive data OK
3'b001 - 1 SKP added
3'b010 - 1 SKP removed
3'b011 - Receiver detected
3'b100 - Either 8B/10B or 128b/130b decode
error and (optionally) RX disparity error
3'b101 - Elastic buffer overflow
3'b110 - Elastic buffer underflow
3'b111 - Receive disparity error, not used if
disparity error is reported using 3'b100.
N/A
Signal to clock generation buffer indicating
the rate switch request. Use this signal for
bonding mode only.
For non-bonded applications this signal is
internally connected to the local CGB.
Active High. Refer to Table 191 on page 261
Bit Mappings When the Simplified Interface is
Disabled for more details.
pipe_rx_status[(3N-1):
0]
pipe_sw[1:0]
Table 191.
Out
Out
Bit Mappings When the Simplified Interface Is Disabled
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter values.
Signal Name
Gen1 (TX Byte
Serializer and RX
Byte Deserializer
disabled)
Gen1 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode)
Gen3
tx_parallel_data
tx_parallel_dat
a[7:0]
tx_parallel_data[29
:22,7:0]
tx_parallel_data[40:33,29:22,18
:11,7:0]
tx_datak
tx_parallel_dat
a[8]
tx_parallel_data[30
,8]
tx_parallel_data[41,30,19,8]
pipe_tx_compliance
tx_parallel_dat
a[9]
tx_parallel_data[31
,9]
tx_parallel_data[42,31,20,9]
pipe_tx_elecidle
tx_parallel_dat
a[10]
tx_parallel_data[32
,10]
tx_parallel_data[43,32,21,10]
pipe_tx_detectrx_loop
bacK
tx_parallel_dat
a[46]
tx_parallel_data[46
]
tx_parallel_data[46]
pipe_powerdown
tx_parallel_dat
a[48:47]
tx_parallel_data[48
:47]
tx_parallel_data[48:47]
pipe_tx_margin
tx_parallel_dat
a[51:49]
tx_parallel_data[51
:49]
tx_parallel_data[51:49]
pipe_tx_swing
tx_parallel_dat
a[53]
tx_parallel_data[53
]
tx_parallel_data[53]
continued...
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Signal Name
Gen1 (TX Byte
Serializer and RX
Byte Deserializer
disabled)
Gen1 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2
mode)
Gen3
rx_parallel_data
rx_parallel_dat
a[7:0]
rx_parallel_data[39
:32,7:0]
rx_parallel_data[55:48,39:32,23
:16,7:0]
rx_datak
rx_parallel_dat
a[8]
rx_parallel_data[40
,8]
rx_parallel_data[56,40,24,8]
rx_syncstatus
rx_parallel_dat
a[10]
rx_parallel_data[42
,10]
rx_parallel_data[58,42,26,10]
pipe_phy_status
rx_parallel_dat
a[65]
rx_parallel_data[65
]
rx_parallel_data[65]
pipe_rx_valid
rx_parallel_dat
a[66]
rx_parallel_data[66
]
rx_parallel_data[66]
pipe_rx_status
rx_parallel_dat
a[69:67]
rx_parallel_data[69
:67]
rx_parallel_data[69:67]
pipe_tx_deemph
N/A
tx_parallel_data[52
]
pipe_tx_sync_hdr
N/A
N/A
tx_parallel_data[55:54]
pipe_tx_blk_start
N/A
N/A
tx_parallel_data[56]
pipe_tx_data_valid
N/A
N/A
tx_parallel_data[60]
pipe_rx_sync_hdr
N/A
N/A
rx_parallel_data[71:70]
pipe_rx_blk_start
N/A
N/A
rx_parallel_data[72]
pipe_rx_data_valid
N/A
N/A
rx_parallel_data[76]
N/A
Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more
information.
Related Links
•
PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate on page 273
•
Intel PHY Interface for PCI Express (PIPE) Architecture
•
Bit Mappings When the Simplified Interface is Disabled on page 261
•
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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2.7.9 fPLL Ports for PIPE
Table 192.
fPLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Direction Clock Domain
Description
Pll_powerdown
Input
Asynchronous
Resets the PLL when asserted high. Needs to be connected
to a dynamically controlled signal (the Transceiver PHY
Reset Controller pll_powerdown output if using this Intel
FPGA IP).
Pll_reflck0
Input
N/A
Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
tx_serial_clk
Output
N/A
High speed serial clock output port for GX channels.
Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to
the tx_serial_clk input of the native PHY IP.
For Gen1x2, x4, x8, use the tx_bonding_clocks output
port to connect to the Native PHY IP.
For Gen2x2, x4, x8, use the tx_bonding_clocks output
port to connect to the Native PHY IP.
For Gen3x1, connect the output from this port to one of
the two tx_serial_clk input ports on the native PHY IP.
For Gen3x2, x4, x8, connect the output from this port to
the Auxiliary Master CGB clock input port of the ATX PLL IP.
pll_locked
Output
Asynchronous
Active high status signal which indicates if PLL is locked.
pll_pcie_clk
Output
N/A
This is the hclk required for PIPE interface.
For Gen1x1, x2, x4, x8 use this port to drive the hclk for
the PIPE interface.
For Gen2x1, x2, x4, x8 use this port to drive the hclk for
the PIPE interface.
For Gen3x1, x2, x4, x8, use the pll_pcie_clk from fPLL
(configured as Gen1/Gen2) as the hclk for the PIPE
interface.
Pll_cal_busy
Output
Asynchronous
Status signal which is asserted high when PLL calibration is
in progress.
If this port is not enabled in Transceiver PHY Reset
Controller, then perform logical OR with this signal and the
tx_cal_busy output signal from Native PHY to input the
tx_cal_busy on the reset controller IP.
Mcgb_rst
Input
Asynchronous
Master CGB reset control.
mcgb_aux_clk0
Input
N/A
Used for Gen3 to switch between fPLL/ATX PLL during link
speed negotiation. For gen3x2, x4, x8 use the
mcgb_aux_clk input port on the ATX PLL.
tx_bonding_clocks[6n-1:0]]
Output
N/A
Optional 6-bit bus which carries the low speed parallel
clock outputs from the Master CGB. It is used for channel
bonding, and represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2, x4, x8 connect the output from this port to
the tx_bonding_clocks input on Native PHY.
For Gen2x1, this port is disabled.
For Gen2x2, x4, x8 connect the output from this port to
the tx_bonding_clocks input on Native PHY.
For Gen3x1, this port is disabled.
continued...
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Port
Direction Clock Domain
Description
For Gen3x2, x4, x8, use the tx_bonding_clocks output
from the ATX PLL to connect to the tx_bonding_clocks
input of the Native PHY.
Input
pcie_sw[1:0]
Asynchronous
2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A
For Gen 2x2, x4, x8 connect the pipe_sw output from
Native PHY to this port.
For Gen3x2, x4, x8 connect the pipe_sw output from the
Native PHY to this port.
For Gen3x2, x4, x8, this port is not used. You must use the
pipe_sw from Native PHY to drive the pcie_sw input port
on the ATX PLL.
Output
pcie_sw_done[1:0]
Asynchronous
2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2, x4, x8 connect the pcie_sw_done output
from ATX PLL to the pipe_sw_done input of Native PHY .
For Gen3x2, x4, x8 connect the pcie_sw_done output
from ATX PLL to the pipe_sw_done input of Native PHY.
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
2.7.10 ATX PLL Ports for PIPE
Table 193.
ATX PLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Direction Clock Domain
Description
Pll_powerdown
Input
Asynchronous
Resets the PLL when asserted high. Needs to be connected to a
dynamically controlled signal (the Transceiver PHY Reset
Controller pll_powerdown output if using this Intel FPGA IP.
Pll_reflck0
Input
N/A
Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
tx_serial_clk
Output
N/A
High speed serial clock output port for GX channels. Represents
the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to the
tx_serial_clk input of the native PHY IP.
For Gen1x2, x4, x8, use the tx_bonding_clocks output port to
connect to the Native PHY.
For Gen2x2, x4, x8, use the tx_bonding_clocks output port to
connect to the Native PHY.
For Gen3x1, connect the output from this port to one of the two
tx_serial_clk input ports on the native PHY IP.
For Gen3x2, x4, x8, this port is not used. Use the tx_serial_clk
output from the fPLL to drive the Auxiliary Master CGB clock
input port of the ATX PLL.
pll_locked
Output
Asynchronous
Active high status signal which indicates if PLL is locked.
pll_pcie_clk
Output
N/A
This is the hclk required for PIPE interface.
continued...
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Port
Direction Clock Domain
Description
For Gen1x1,x2,x4,x8 use this port to drive the hclk for the PIPE
interface.
For Gen2x1,x2,x4,x8 use this port to drive the hclk for the PIPE
interface.
For Gen3x1,x2,x4,x8, this port is not used. Use the
pll_pcie_clk from fPLL (configured as Gen1/Gen2) as the
hclk for the PIPE interface.
Pll_cal_busy
Output
Asynchronous
Status signal which is asserted high when PLL calibration is in
progress. If this port is not enabled in the Transceiver PHY
Reset Controller, then perform logical OR with this signal and
the tx_cal_busy output signal from Native PHY to input the
tx_cal_busy on the reset controller IP.
Mcgb_rst
Input
Asynchronous
Master CGB reset control.
mcgb_aux_clk0
Input
N/A
Used for Gen3 to switch.
between fPLL/ATX PLL during link speed negotiation.
For gen3x2,x4,x8 use the tx_serial_clk output port from
fPLL (configured for Gen1/Gen2) to drive the mcgb_aux_clk
input port on the ATX PLL.
tx_bonding_clocks[5:0]
Output
N/A
Optional 6-bit bus which carries the low speed parallel clock
outputs from the Master CGB. Used for channel bonding, and
represents the x6/xN clock network.
For Gen1x1, this port is disabled.
For Gen1x2,x4,x8 connect the output from this port to the
tx_bonding_clocks input on Native PHY.
For Gen2x1, this port is disabled
For Gen2x2,x4,x8 connect the output from this port to
tx_bonding_clocks input on Native PHY.
For Gen3x1, this port is disabled.
For Gen3x2,x4,x8 use the tx_bonding_clocks output from
the ATX PLL to connect to the tx_bonding_clocks input of
the Native PHY.
pcie_sw[1:0]
Input
Asynchronous
2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4,x8 connect the pipe_sw output from Native
PHY to this port.
For Gen3x2,x4,x8 use the pipe_sw output from Native PHY to
drive this port.
pcie_sw_done[1:0]
Output
Asynchronous
2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen2x2, x4, x8 connect the pcie_sw_done output from
ATX PLL to pipe_sw_done input of Native PHY .
For Gen3x2, x4, x8 pcie_sw_done output from ATX PLL to
pipe_sw_done input of Native PHY.
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
2.7.11 Preset Mappings to TX De-emphasis
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Table 194.
Arria 10 Preset Mappings to TX De-emphasis
Preset
C+1
C0
C-1
0
001111
101101
000000
1
001010
110010
000000
2
001100
110000
000000
3
001000
110100
000000
4
000000
111100
000000
5
000000
110110
000110
6
000000
110100
001000
7
001100
101010
000110
8
001000
101100
001000
9
000000
110010
001010
10
010110
100110
000000
The pipe_g3_txdeemph port is used to select the link partner’s transmitter deemphasis during equalization. The 18 bits specify the following coefficients:
[5:0]: C-1
[11:6]: C0
[17:12]: C+1
Note:
Intel recommends transmitting Preset P8 coefficients for Arria 10 receiver to recover
data successfully.
2.7.12 How to Place Channels for PIPE Configurations
Instead of the fitter or software model, the hardware dictates all the placement
restrictions. The restrictions are listed below:
•
The channels must be contiguous for bonded designs.
•
The master CGB is the only way to access x6 lines and must be used in bonded
designs. The local CGB cannot be used to route clock signals to slave channels
because the local CGB does not have access to x6 lines.
•
When implementing a Gen3-capable PIPE configuration in a -2 or -3 core speed
grade, you cannot place the Logical PCS Master Channel in a location adjacent to
the Hard IP (HIP).
•
Non PCIe-Channels that are placed next to active banks with PIPE interfaces that
are Gen3 capable have the following restrictions
—
When VCCR_GXB and VCCT_GXB are set to 1.03 V or 1.12 V, the maximum
data rate supported for the non-PCIe channels in those banks is 12.5 Gbps for
chip-to-chip applications. These channels cannot be used to drive backplanes
or for GT rates.
—
When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in
those banks cannot be used.
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For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the
PCIe User Guide.
For ATX PLL placement restrictions, refer to the section "Transmit PLL
Recommendations Based on Data Rates" of PLLs and Clock Networks chapter.
Related Links
•
Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
•
PLLs and Clock Networks on page 335
2.7.12.1 Master Channel in Bonded Configurations
For PCIe, both the PMA and PCS must be bonded. There is no need to specify the PMA
Master Channel because of the separate Master CGB in the hardware. However, you
must specify the PCS Master Channel through the Native PHY. You can choose any one
of the data channels (part of the bonded group) as the logical PCS Master Channel.
Note:
Whichever channel you pick as the PCS master, the fitter will select physical CH1 or
CH4 of a transceiver bank as the master channel. This is because the ASN and Master
CGB connectivity only exists in the hardware of these two channels of the transceiver
bank.
Table 195.
Logical PCS Master Channel for PIPE Configuration
(43)
PIPE Configuration
Logical PCS Master Channel # (default)
x1
0(43)
x2
1(43)
x4
2(43)
x8
4
(43)
Ensure that the Logical PCS Master Channel aligns with Physical Channel 1 or 4 in a given
transceiver bank.
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The following figures show the default configurations:
Figure 109. x2 Configuration
CH5
fPLL
Master
CGB
CH4
CH3
CH2
fPLL
Master
CGB
CH1
CH0
CH5
Transceiver bank
ATX
PLL
fPLL
Master
CGB
CH4
CH3
CH2
Note:
ATX
PLL
ATX
PLL
Transceiver bank
fPLL
1
CH1
Master CH
0
CH0
Data CH
Logical
Channel
Physical
Channel
Master
CGB
ATX
PLL
The physical channel 0 aligns with logical channel 0. The logical PCS Master Channel 1
is specified as Physical Channel 1.
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Figure 110. x4 Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 4.
CH5
fPLL
Master
CGB
CH4
CH3
CH2
fPLL
Master
CGB
CH1
CH0
3
CH5
Data CH
2
CH4
Master CH
1
CH3
Data CH
0
CH2
Data CH
CH1
CH0
Logical
Channel
ATX
PLL
Transceiver bank
ATX
PLL
fPLL
Master
CGB
ATX
PLL
Transceiver bank
fPLL
Master
CGB
ATX
PLL
Physical
Channel
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Figure 111. x8 Configuration
For x8 configurations, Intel recommends you choose a master channel that is a maximum of four channels
away from the farthest slave channel.
CH5
fPLL
Master
CGB
CH4
CH3
CH2
Note:
ATX
PLL
fPLL
7
CH1
Data CH
6
CH0
Data CH
5
CH5
Data CH
4
CH4
Master CH
3
CH3
Data CH
2
CH2
Data CH
1
CH1
Data CH
0
CH0
Data CH
Logical
Channel
Physical
Channel
Master
CGB
Transceiver bank
ATX
PLL
fPLL
Master
CGB
ATX
PLL
Transceiver bank
fPLL
Master
CGB
ATX
PLL
The physical channel 0 aligns with logical channel 0. The logical PCS master channel 4
is specified as Physical channel 4.
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Figure 112. x4 Alternate Configuration
The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master
Channel number 2 must be specified as Physical channel 1.
CH5
fPLL
Master
CGB
CH4
CH3
Transceiver bank
3
CH2
Data CH
2
CH1
Master CH
1
CH0
Data CH
0
CH5
Data CH
CH4
fPLL
Master
CGB
Master
CGB
CH2
CH0
Logical
Channel
ATX
PLL
fPLL
CH3
CH1
ATX
PLL
ATX
PLL
Transceiver bank
fPLL
Master
CGB
ATX
PLL
Physical
Channel
As indicated in the figures above, the fitter picks either physical CH1 or CH4 as the
PCS master in bonded configurations for PIPE.
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Figure 113. x4 Configuration with the Master Channel Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is
adjacent to a Hard IP.
3
2
1
0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Logical Physical
Channel Channel
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Hard
IP
Data CH
Master CH
Data CH
Data CH
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
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Figure 114. x4 Configuration with the Master Channel not Adjacent to a Hard IP
The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is
not adjacent to a Hard IP.
3
2
1
0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
CH5
CH4
CH3
CH2
CH1
CH0
Data CH
Master CH
Data CH
Data CH
Hard
IP
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
fPLL
Master CGB ATX
PLL
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Logical Physical
Channel Channel
2.7.13 PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate
Gen3 mode requires TX and RX link equalization because of the data rate, the channel
characteristics, receiver design, and process variations. The link equalization process
allows the Endpoint and Root Port to adjust the TX and RX setup of each lane to
improve signal quality. This process results in Gen3 links with a receiver Bit Error Rate
(BER) that is less than 10-12.
For detailed information about the four-stage link equalization procedure for 8.0 GT/s
data rate, refer to Section 4.2.3 in the PCI Express Base Specification, Rev 3.0. A new
LTSSM state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3
equalization. Phases 2 and 3 of link equalization are optional. Each link must progress
through all four phases, even if no adjustments occur. If you skip Phases 2 and 3, you
will speed up link training at the expense of link BER optimization.
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Phase 0
Phase 0 includes the following steps:
1.
The upstream component enters Phase 0 of equalization during
Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the
downstream component. EQ TS2 training sets may be sent at 2.5 GT/s or 5 GT/s.
2. The downstream component enters Phase 0 of equalization after exiting
Recovery.Speed at 8 GT/s. It receives the starting presets from the training
sequences and applies them to its transmitter. At this time, the upstream
component has entered Phase 1 and is operating at 8 GT/s.
3.
To move to Phase 1, the receiver must have a BER < 10-4. The receiver should be
able to decode enough consecutive training sequences.
4.
In order to move to Equalization Phase 1, the downstream component must detect
training sets with Equalization Control (EC) bits set to 2’b01.
Phase 1
During Phase 1 of the equalization process, the link partners exchange Full Swing (FS)
and Low Frequency (LF) information. These values represent the upper and lower
bounds for the TX coefficients. The receiver uses this information to calculate and
request the next set of transmitter coefficients.
1. The upstream component moves to EQ Phase 2 when training sets with EC bits set
to 1’b0 are captured on all lanes. It also sends EC=2’b10, starting pre-cursor,
main cursor, and post-cursor coefficients.
2. The downstream component moves to EQ Phase 2 after detecting these new
training sets.
Use the pipe_g3_txdeemph[17:0] port to select the transmitter de-emphasis. The
18 bits specify the following coefficients:
•
[5:0]: C-1
•
[11:6]: C0
•
[17:12]: C+1
Refer to Preset Mappings to TX De-emphasis for the mapping between presets and TX
de-emphasis.
Phase 2 (Optional)
During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use
Preset bit determines whether the Endpoint uses presets for coarse resolution or
coefficients for fine resolution.
If you are using the PHY IP Core for PCI Express (PIPE) as the Root Port, the Endpoint
can tune the Root Port TX coefficients.
The tuning sequence typically includes the following steps:
1. The Endpoint receives the starting presets from the Phase 2 training sets sent by
the Root Port.
2.
The circuitry in the Endpoint receiver determines the BER. It calculates the next
set of transmitter coefficients using FS and LF. It also embeds this information in
the Training Sets for the Link Partner to apply to its transmitter.
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The Root Port decodes these coefficients and presets, performs legality checks for
the three transmitter coefficient rules and applies the settings to its transmitter
and also sends them in the Training Sets. The default Full Swing (FS) value
advertised by the Intel device is 60 and Low Frequency (LF) is 20. The three rules
for transmitter coefficients are:
a.
|C-1| <= Floor (FS/4)
b.
|C-1|+C0+|C+1| = FS
c.
C0-|C-1|-|C+1 |>= LF
Where: C0 is the main cursor (boost), C-1 is the pre-cursor (pre-shoot), and C+1 is
the post-cursor (de-emphasis).
3. This process is repeated until the downstream component's receiver achieves a
BER of < 10-12
Phase 3 (Optional)
During this phase, the Root Port tunes the Endpoint’s transmitter. This process is
analogous to Phase 2 but operates in the opposite direction.
After Phase 3 tuning is complete, the Root Port moves to Recovery.RcvrLock, sending
EC=2’b00, and the final coefficients or preset agreed upon in Phase 2. The Endpoint
moves to Recovery.RcvrLock using the final coefficients or preset agreed upon in
Phase 3.
Recommendations for Tuning Link
To improve the BER of the receiver, Intel recommends that you turn on CTLE in
triggered mode during Phase 2 Equalization for Endpoints or Phase 3 Equalization for
Root Ports.
Use the port pipe_g3_txdeemph[17:0] to transmit the coefficients corresponding
to the Gen3 presets. Intel recommends transmitting Preset P8 coefficients for A10
receiver to recover data successfully. The pipe_g3_txdeemph is used to select the
link partner’s transmitter de-emphasis during equalization.
Use the port pipe_g3_rxpresethint[2:0] to turn on CTLE in triggered mode
during equalization phases.
Table 196.
CTLE mode for Gen1/Gen2 speeds of Gen3 capable design
Use this table to drive the pipe_g3_rxpresethint port and set the CTLE in manual mode when operating at
Gen1/Gen2 speeds of a Gen3 capable design.
Supported CTLE - mode Manual. To use CTLE in manual mode
Gen3 capable design running at Gen1/Gen2
speeds during
Power up
•
During power up, set pipe_g3_rxpresethint[2:0] = 3’b000
•
•
You can use the default CTLE 4S AC Gain set by Quartus (or)
Set the manual CTLE 4S AC Gain using QSF assignments
Down train to Gen1/Gen2 (directed or not) and
subsequent re-entry to Gen3
•
On entry to Gen1/2, set pipe_g3_rxpresethint[2:0] = 3’b000
•
•
You can use the default CTLE 4S AC Gain set by Quartus (or)
Set the manual CTLE 4S AC Gain using QSF assignments
Down train to Gen1/Gen2
•
On entry to Gen1/2, set pipe_g3_rxpresethint[2:0] = 3’b000
•
•
You can use the default CTLE 4S AC Gain set by Quartus (or)
Set the manual CTLE 4S AC Gain using QSF assignments
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Note:
Intel does not support use of CTLE in adaptive mode for Gen1/Gen2 speeds. You must
use CTLE in manual mode.
Table 197.
CTLE mode for Gen3 speed of Gen3 capable design
Use this table to drive the pipe_g3_rxpresethint port and set the CTLE mode to adaptation mode when
operating at Gen3 speed for Gen3 capable designs.
Gen3 capable design
running at Gen3 speed
during
1st time entry to Gen3
Supported CTLE - mode Triggered adaptation. To use CTLE in adaptation mode, Set
•
In EQ Phase2/3, after far end TX preset/coefficient requests are completed, set
pipe_g3_rxpresethint = 3’b111 and link needs to stay in Recovery for at least 12ms for
Redoing EQ in Gen3
Re-entry to Gen3 after
down train to Gen1/
Gen2 (directed or not)
Note:
•
CTLE adaptation
If there is not enough time in EQ phases, delay can be inserted in Recovery.RcvrLock after
the EQ
•
After that, pipe_g3_rxpresethint should remain 3’b111 for Gen3 even in Recovery
•
pipe_g3_rxpresethint should be set to 3’b000 in EQ Phase2/3 entry
•
Follow the same procedure as first time link up to Gen3
•
On subsequent entry to Gen3, set pipe_g3_rxpresethint[2:0] = 3’b111 when there is
valid data and wait for 12ms in Recovery state for CTLE adaptation
Intel recommends that you use CTLE in adaptive mode for Gen3 speed. If you want to
use CTLE in manual mode for Gen3 speed, then you must set
pipe_g3_rxpresethint[2:0] = 3’b000 and set the CTLE 4S AC gain value
•
You can use the default CTLE 4S AC Gain set by Quartus (or)
•
Set the manual CTLE 4S AC Gain using QSF assignments
Related Links
•
Preset Mappings to TX De-emphasis on page 265
•
Continuous Time Linear Equalization (CTLE) on page 436
•
PCI Express Base Specification
•
PIPE Specification
2.7.14 Using Transceiver Toolkit (TTK)/System Console/Reconfiguration
Interface to manually tune Arria 10 PCIe designs (Hard IP(HIP) and
PIPE) (For debug only)
Table 198.
Manual tuning of TX analog settings for PCIe channels
To manually tune TX channels of the Arria 10 PCIe designs using TTK/System Console/Reconfiguration
Interface, you must set the following attributes
Attribute
user_fir_coe
ff_ctrl_sel
0x105[7]
Default value in PCIe
mode
1’b1
Value to be set to use TTK/
System Console
1’b0
Description
Mux to select between static vs
dynamic (port) control
• 0 for static setting (to use TTK/
system console for manual
tuning)
• 1 for dynamic control (PCIe
mode)
continued...
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Attribute
Default value in PCIe
mode
Value to be set to use TTK/
System Console
Description
Setting this mux will affect VOD,
pre tap and post tap attributes
pre_emp_swit
ching_ctrl_p
re_tap_1t
0x107[4:0]
Controlled by coefficients
on the port
pre_emp_sign
_pre_tap_1t
0x107[5]
negative
vod_output_s
wing_ctrl
0x109[4:0]
Controlled by coefficients
on the port
vod_output_swing_ctrl register
pipe_g3_txdeemph
setting
pre_emp_swit
ching_ctrl_1
st_post_tap
0x105[4:0]
Controlled by coefficients
on the port
pre_emp_sign
_1st_post_ta
p 0x105[6]
pipe_g3_txdeemph
Depends on value set by
pre_emp_switching_ctrl_pre_
tap_1t register setting
Depends on value set by
Sets 1st Pre tap sign
• - 1 negative (default for PCIe
mode)
• 0 positive
pre_emp_sign_pre_tap_1t
register setting
pipe_g3_txdeemph
Negative
Sets 1st Pre tap value
• Direct mapped
Depends on value set by
Depends on value set by
pre_emp_switching_ctrl_1st_
post_tap register setting
Depends on value set by
pre_emp_sign_1st_post_tapreg
ister setting
Output swing
• Direct mapped
Sets 1st Post tap value
• Direct mapped
Set 1st Post tap sign
• - 1 negative (default for PCIe
mode)
• - 0 positive
Note:
You must set the attribute user_fir_coeff_ctrl_sel located at register address
0x105[7] back to 1’b1 to allow the Arria 10 PCI Express PIPE design to listen to the
port pipe_g3_txdeemph[17:0] on each channel for normal PCIe operation.
Table 199.
Manual tunning of RX analog settings for PCIe channels
To manually tune RX channels of the Arria 10 PCI Express designs using TTK/System Console/Reconfiguration
Interface, you must set the following attribute
Attribute
Default value in PCIe
mode
Value to be set to use TTK/
System Console
Description
rrx_pcie_eqz
0x161[2]
1’b1
1’b0
Mux to select between static vs
dynamic control
• 0 for static setting (use for
manual tuning)
• 1 for dynamic control (PCIe
mode)
Setting this mux will affect the CTLE
4s gain and 1s gain values
adp_4s_ctle_
bypass
0x167[0]
1’b0
•
Mux to select between CTLE 4S
manual mode vs adaptive mode
• 0 for CTLE 4S adaptive mode
• 1 for CTLE 4S manual mode
•
1’b0 for Gen3 for Adaptive 4S
CTLE
1’b1 for Gen1/Gen2 for Manual
4S CTLE
continued...
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Attribute
Default value in PCIe
mode
Value to be set to use TTK/
System Console
Description
adp_ctle_acg
ain_4s
0x167[5:1]
5’b0
Depends on the value set by
adp_ctle_acgain_4s Register setting
Set CTLE manual 4S AC gain
• Direct mapped
Adp_status_s
el
0x14C[5:0]
Set the mux to 6’b011011
Set the mux to 6’b011011
Sets the test mux to read the CTLE
converged values from 0x177[3:0]
Test_mux
0x177[3:0]
Read values. Map 4 bit
value read out to 5 bit
gain values
Read values. Map 4 bit value read
out to 5 bit gain values
Reflects the converged values from
CTLE adaptation
Note:
You must set the attribute rrx_pcie_eqz located at register address 0x161[2] back
to 1’b1 to allow the Arria 10 PCIe PIPE design to listen to the port
pipe_g3_rxpresethint[2:0] on each channel for normal PCIe operation.
Related Links
•
Analog Parameter Settings on page 563
•
Debugging Transceiver Links with Transceiver Toolkit
•
Arria 10 Register Map
2.8 CPRI
The common public radio interface (CPRI) is a high-speed serial interface developed
for wireless network radio equipment controller (REC) to uplink and downlink data
from available remote radio equipment (RE).
The CPRI protocol defines the interface of radio base stations between the REC and
the RE. The physical layer supports both the electrical interfaces (for example,
traditional radio base stations) and the optical interface (for example, radio base
stations with a remote radio head). The scope of the CPRI specification is restricted to
the link interface only, which is a point-to-point interface. The link has all the features
necessary to enable a simple and robust usage of any given REC and RE network
topology, including a direct interconnection of multiport REs.
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2.8.1 Transceiver Channel Datapath and Clocking for CPRI
Figure 115. Transceiver Channel Datapath and Clocking for CPRI
Transmitter Standard PCS
Transmitter PMA
32
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
40
FPGA
Fabric
PRBS
Generator
245 MHz
tx_coreclkin
tx_clkout
245 MHz
/2, /4
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
32
RX
FIFO
Byte
Deserializer
Parallel Clock
(Recovered)
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
40
rx_coreclkin
rx_clkout
245 MHz
Parallel Clock
(From Clock
Divider)
tx_clkout
245 MHz
rx_clkout or
tx_clkout
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Table 200.
Channel Width Options for Supported Serial Data Rates
Channel Width (FPGA-PCS Fabric)
Serial Data
Rate
(Mbps)
8/10 Bit Width
16/20 Bit Width
8-Bit
16-Bit
16-Bit
32-Bit
614.4(44)
Yes
Yes
N/A
N/A
1228.8
Yes
Yes
Yes
Yes
2457.6
Yes
Yes
Yes
Yes
3072
Yes
Yes
Yes
Yes
4915.2
N/A
N/A
Yes
Yes
6144
N/A
N/A
Yes
Yes
9830.4
N/A
N/A
N/A
Yes
Table 201.
Interface Width Options for 10.1376 Gbps and 12.16512 Gbps Data Rates
Serial Data Rate
(Mbps)
(44)
Serial Clock
Interface Width
FPGA fabric - Enhanced PCS (bit)
Enhanced PCS - PMA (bit)
10137.6
66
32, 40, 64
12165.12
66
40, 64
Over-sampling is required to implement 614.4Mbps
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2.8.1.1 TX PLL Selection for CPRI
Choose a transmitter PLL that fits your required data rate.
Table 202.
TX PLL Supported Data Rates
ATX and fPLL support the clock bonding feature.
TX PLLs
Note:
Supported Data Rate (Mbps)
ATX
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12
fPLL
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6, 12165.12
CMU
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 8110.08, 9830.4, 10137.6
•
Channels that use the CMU PLL cannot be bonded. The CMU PLL that provides the
clock can only drive channels in the transceiver bank where it resides.
•
Over-sampling is required to implement 614.4Mbps.
2.8.1.2 Auto-Negotiation
When auto-negotiation is required, the channels initialize at the highest supported
frequency and switch to successively lower data rates if frame synchronization is not
achieved. If your design requires auto-negotiation, choose a base data rate that
minimizes the number of PLLs required to generate the clocks required for data
transmission.
By selecting an appropriate base data rate, you can change data rates by changing the
local clock generation block (CGB) divider. If a single base data rate is not possible,
you can use an additional PLL to generate the required data rates.
Table 203.
Recommended Base Data Rates and Clock Generation Blocks for Available
Data Rates
Data Rate (Mbps)
Base Data Rate (Mbps)
Local CGB Divider
1228.8
9830.4
8
2457.6
9830.4
4
3072.0
6144.0
2
4915.2
9830.4
2
6144.0
6144.0
1
9830.4
9830.4
1
2.8.2 Supported Features for CPRI
The CPRI protocol places stringent requirements on the amount of latency variation
that is permissible through a link that implements these protocols.
CPRI (Auto) and CPRI (Manual) transceiver configuration rules are both available for
CPRI designs. Both modes use the same functional blocks, but the configuration mode
of the word aligner is different between the Auto and Manual modes. In CPRI (Auto)
mode, the word aligner works in deterministic mode. In CPRI (Manual) mode, the
word aligner works in manual mode.
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To avoid transmission interference in time division multiplexed systems, every radio in
a cell network requires accurate delay estimates with minimal delay uncertainty. Lower
delay uncertainty is always desired for increased spectrum efficiency and bandwidth.
The Arria 10 devices are designed with features to minimize the delay uncertainty for
both RECs and REs.
2.8.2.1 Word Aligner in Deterministic Latency Mode for CPRI
The deterministic latency state machine in the word aligner reduces the known delay
variation from the word alignment process. It automatically synchronizes and aligns
the word boundary by slipping one half of a serial clock cycle (1UI) in the deserializer.
Incoming data to the word aligner is aligned to the boundary of the word alignment
pattern (K28.5).
Figure 116. Deterministic Latency State Machine in the Word Aligner
Clock-Slip
Control
Parallel
Clock
From RX CDR
Deterministic Latency
Synchronization State Machine
Deserializer
To 8B/10B Decoder
When using deterministic latency state machine mode, assert
rx_std_wa_patternalign to initiate the pattern alignment after the reset sequence
is complete. This is an edge-triggered signal in all cases except one: when the word
aligner is in manual mode and the PMA width is 10, in which case
rx_std_wa_patternalign is level sensitive.
Figure 117. Word Aligner in Deterministic Mode Waveform
rx_clkout
rx_std_wa_patternalign
rx_parallel_data
rx_errdetect
rx_disperr
rx_patterndetect
rx_syncstatus
f1e4b6e4
1101
1101
0000
0000
b9dbf1db
0000
0000
915d061d
1010
1010
e13f913f
1000
1000
7a4ae24a
0010
0000
bbae9b10
1010
1010
bcbcbcbc
0000
0000
1111
1111
95cd3c50
91c295cd
0000
Related Links
Word Aligner on page 469
2.8.2.1.1 Transmitter and Receiver Latency
The latency variation from the link synchronization function (in the word aligner block)
is deterministic with the rx_bitslipboundaryselectout port. Additionally, you
can use the tx_bitslipboundaryselect port to fix the round trip transceiver
latency for port implementation in the remote radio head to compensate for latency
variation in the word aligner block. The tx_bitslipboundaryselect port is
available to control the number of bits to be slipped in the transmitter serial data
stream. You can optionally use the tx_bitslipboundaryselect port to round the
round-trip latency to a whole number of cycles.
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When using the byte deserializer, additional logic is required in the FPGA fabric to
determine if the comma byte is received in the lower or upper byte of the word. The
delay is dependent on the word in which the comma byte appears.
2.8.3 Word Aligner in Manual Mode for CPRI
When configuring the word aligner in CPRI (Manual), the word aligner parses the
incoming data stream for a specific alignment character. After rx_digitalreset
deasserts, asserting the rx_std_wa_patternalign triggers the word aligner to look
for the predefined word alignment pattern or its complement in the received data
stream. It is important to note that the behavior of the word aligner in Manual mode
operates in different ways depending on the PCS-PMA interface width.
Table 204.
Word Aligner Signal Status Behaviors in Manual Mode
PCS-PMA Interface Width
rx_std_wa_patternalign
rx_syncstatus Behavior
Behavior
rx_patterndetect
Behavior
10
Level sensitive
One parallel clock cycle (When
three control patterns are
detected)
One parallel clock cycle
20
Edge sensitive
Remains asserted until next
rising edge of
One parallel clock cycle
rx_std_wa_patternalign
PCS-PMA Width = 10
When the PCS-PMA interface width is 10, 3 consecutive word alignment patterns found
after the initial word alignment in a different word boundary causes the word aligner
to resynchronize to this new word boundary if the rx_std_wa_patternalign
remains asserted; rx_std_wa_patternalign is level sensitive. If you deassert
rx_std_wa_patternalign, the word aligner maintains the current word boundary
even when it finds the alignment pattern in a new word boundary. When the word
aligner is synchronized to the new word boundary, rx_patterndetect and
rx_syncstatus are asserted for one parallel clock cycle.
PCS-PMA Width =20
When the PMA-PCS width is 20, any alignment pattern found after the initial alignment
in a different word boundary causes the word aligner to resynchronize to this new
word boundary on the rising edge of rx_std_wa_patternalign;
rx_std_wa_patternalign is edge sensitive. The word aligner will maintain the
current word boundary until the next rising edge of rx_std_wa_patternalign.
When the word aligner is synchronized to the new word boundary,
rx_patterndetect will assert for one parallel clock cycle and rx_syncstatus will
remain asserted until the next rising edge of rx_std_wa_patternalign.
Figure 118. Word Aligner in Manual Alignment Mode Waveform
rx_clkout
rx_std_wa_patternalign
rx_parallel_data 0... f1e4b6e4 b9dbf1db 915d061d e13f913f
rx_patterndetect 0
rx_syncstatus 0000
Related Links
Word Aligner on page 469
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282
7a4ae24a bcbc7b78
1100
1100
bcbcbcbc
1111
1111
95cd3c50 91c295cd
0000
ded691c2
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2.8.4 How to Implement CPRI in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing your CPRI protocol.
1.
Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 31 for more details.
2. Select CPRI (Auto) or CPRI (Manual) from the Transceiver configuration
rules list located under Datapath Options, depending on which protocol you are
implementing.
3.
Use the parameter values in the tables in Native PHY IP Parameter Settings for
CPRI on page 284 as a starting point. Or, you can use the protocol presets
described in Preset Configuration Options. You can then modify the setting to meet
your specific requirements.
4. Click Generate to generate the Native PHY IP (this is your RTL file).
Figure 119. Signals and Ports of Native PHY IP for CPRI
Arria 10 Transceiver Native PHY
tx_cal_busy
rx_cal_busy
NIOS
Hard Calibration IP
Reconfiguration
Registers
TX PMA
tx_serial_data
tx_serial_clk0
(from TX PLL)
Serializer
TX Standard PCS
10/20
Local Clock
Generation
Block
Deserializer
tx_digital_reset
tx_datak[1:0]
tx_parallel_data[15:0]
tx_coreclkin
tx_clkout
tx_analog_reset
rx_analog_reset
RX PMA
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
tx_datak
tx_parallel_data
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
reconfig_reset
reconfig_clk
reconfig_avmm
RX Standard PCS
10/20
CDR
5.
Instantiate and configure your PLL.
6.
Create a transceiver reset controller.
rx_datak
rx_parallel_data
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
unused_rx_parallel_data[118:0]
rx_digital_reset
rx_datak[1:0]
rx_parallel_data[15:0]
rx_clkout
rx_coreclkin
rx_errdetect[1:0]
rx_disperr[1:0]
rx_runningdisp[1:0]
rx_patterndetect[1:0]
rx_syncstatus[1:0]
rx_std_wa_patternalign
unused_rx_parallel_data[118:0]
You can use your own reset controller or use the Native PHY Reset Controller IP.
7.
Connect the Native PHY IP to the PLL IP core and the reset controller. Use the
information in the following figure to connect the ports.
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Figure 120. Connection Guidelines for a CPRI PHY Design
clk
tx_ready
reset
rx_ready
Reset Controller
pll_sel
pll_refclk
pll_locked
PLL IP Core
rx_digitalreset
rx_analogreset
tx_digitalreset
tx_analogreset
rx_cal_busy
rx_is_lockedtodata
tx_cal_busy
pll_cal_busy
tx_serialclk0
rx_cdr_refclk
Data
Generator
Data
Verifier
8.
tx_clkout
tx_parallel_data
tx_serial_data
Arria 10 Transceiver Native PHY
rx_serial_data
rx_clkout
rx_parallel_data
Simulate your design to verify its functionality.
Related Links
•
Arria 10 Standard PCS Architecture on page 463
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Standard PCS Ports on page 84
Port definitions for the Transceiver Native PHY Standard Datapath
2.8.5 Native PHY IP Parameter Settings for CPRI
Table 205.
General and Datapath Options
The first two sections of the Parameter Editor for the Native PHY IP provide a list of general and datapath
options to customize the transceiver.
Parameter
Message level for rule violations
Value
error
continued...
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Parameter
Value
warning
Transceiver configuration rules
PMA configuration rules
basic
Transceiver mode
TX/RX Duplex
Number of data channels
1-36
Data rate
1228.8 Mbps
2457.6 Mbps
3072 Mbps
4915.2 Mbps
6144 Mbps
8110.08 Mbps
9830.4 Mbps
10137.6 Mbps(45)
12165.12 Mbps(45)
Enable datapath and interface reconfiguration
Off
Enable simplified data interface
On
Table 206.
TX PMA Parameters
Parameter
TX channel bonding mode
Value
Not Bonded / PMA Bonding Only / PMA
and PCS Bonding
TX local clock division factor
1
Number of TX PLL clock inputs per channel
1
Initial TX PLL clock input selection
0
Enable tx_pma_clkout port
Off
Enable tx_pma_div_clkout port
On
tx_pma_div_clkout division factor
(45)
CPRI (Auto)
CPRI (Manual)
2
Enable tx_pma_elecidle port
Off
Enable tx_pma_qpipullup port (QPI)
Off
Enable tx_pma_qpipulldn port (QPI)
Off
Enable tx_pma_txdetectrx port (QPI)
Off
Enable tx_pma_rxfound port (QPI)
Off
Enable rx_seriallpbken port
Off
10137.6 Mbps and 12165.12 Mbps are implemented by selecting 10GBase-R or 10GBase-R
1588 under Transceiver configuration rules. The Enhanced PCS is selected when the CPRI data
rate is 10137.6 Mbps and above.
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Table 207.
RX PMA Parameters
Parameter
Value
Number of CDR reference clocks
1
Selected CDR reference clock
0
Selected CDR reference clock frequency
Select legal range defined by the Quartus Prime
software
PPM detector threshold
1000
CTLE adaptation mode
manual
DFE adaptation mode
disabled
Number of fixed dfe taps
3
Enable rx_pma_clkout port
Off
Enable rx_pma_div_clkout port
On
rx_pma_div_clkout division factor
2
Enable rx_pma_clkslip port
Off
Enable rx_pma_qpipulldn port (QPI)
Off
Enable rx_is_lockedtodata port
On
Enable rx_is_lockedtoref port
On
Enable rx_set_locktodata and rx_set_locktoref ports
Off
Enable rx_seriallpbken port
Off
Enable PRBS verifier control and status ports
Off
Table 208.
Standard PCS Parameters
Parameters
Value
Standard PCS / PMA interface width
20
FPGA fabric / Standard TX PCS interface width
32
FPGA fabric / Standard RX PCS interface width
32
Enable 'Standard PCS' low latency mode
Off
TX FIFO mode
register_fifo
RX FIFO mode
register_fifo
Enable tx_std_pcfifo_full port
Off
Enable tx_std_pcfifo_empty port
Off
Enable rx_std_pcfifo_full port
Off
Enable rx_std_pcfifo_empty port
Off
TX byte serializer mode
Serialize x2
RX byte deserializer mode
Deserialize x2
Enable TX 8B/10B encoder
On
Enable TX 8B/10B disparity control
Off
Enable RX 8B/10B decoder
On
continued...
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Parameters
Value
RX rate match FIFO mode
Disabled
RX rate match insert / delete -ve pattern (hex)
0x00000000
RX rate match insert / delete +ve pattern (hex)
0x00000000
Enable rx_std_rmfifo_full port
Off
Enable rx_std_rmfifo_empty port
Off
PCI Express Gen3 rate match FIFO mode
Bypass
Enable TX bit slip
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable tx_std_bitslipboundarysel port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
RX word aligner mode
deterministic latency (CPRI Auto
configuration)
manual (FPGA fabric controlled) (CPRI
Manual configuration)
RX word aligner pattern length
10
RX word aligner pattern (hex)
0x000000000000017c
Number of word alignment patterns to achieve sync
3
(46)
Number of invalid data words to lose sync
3
(46)
Number of valid data words to decrement error count
3
(46)
Enable fast sync status reporting for deterministic latency SM
On / Off
Enable rx_std_wa_patternalign port
On / Off
Enable rx_std_wa_a1a2size port
Off
Enable rx_std_bitslipboundarysel port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable rx_bitslip port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
All options under Bit Reversal and Polarity Inversion
Off
All options under PCIe Ports
Off
Table 209.
Dynamic Reconfiguration
Parameter
Value
Enable dynamic reconfiguration
Off
Share reconfiguration interface
Off
Enable Altera Debug Master Endpoint
Off
Enable embedded debug
Off
Enable capability registers
Off
Set user-defined IP identifier
0
continued...
(46)
These are unused when the transceiver PHY is in CPRI mode.
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Parameter
Value
Enable control and status registers
Off
Enable prbs soft accumulators
Off
Configuration file prefix
altera_xcvr_native_a10
Generate SystemVerilog package file
Off
Generate C header file
Off
Generate MIF (Memory Initialization File)
Off
Table 210.
Generation Options
Parameter
Generate parameter documentation file
Value
On
2.9 Other Protocols
2.9.1 Using the "Basic (Enhanced PCS)" and "Basic with KR FEC"
Configurations of Enhanced PCS
You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G
or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration rule allows
access to the Enhanced PCS with full user control over the transceiver interfaces,
parameters, and ports.
You can configure the transceivers for Basic functionality using the Native PHY IP
Basic (Enhanced PCS) transceiver configuration rule.
Basic with KR FEC is a KR FEC sublayer support with a low latency physical coding
sublayer (PCS). The KR FEC sublayer increases the bit error rate (BER) performance of
a link. This mode can run up to a data rate of 25.8 Gbps. Use this configuration to
implement applications with low latency or low BER requirements or applications such
as 10 Gbps, 40 Gbps or 100 Gbps Ethernet over backplane (10GBASE-KR protocol).
The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE
802.3ap-2007. FEC provides an error detection and correction mechanism that allows
noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10-12. The
FEC sublayer provides additional link margin by compensating for variations in
manufacturing and environmental conditions. To distinguish it from other FEC
mechanisms (for example, Optical Transport Network FEC), FEC as defined in Clause
74 of IEEE 802.3ap-2007 is called KR FEC.
Note:
This configuration supports the FIFO in phase compensation and register modes, and
KR FEC PCS blocks. You can implement all other required logic for your specific
application, such as standard or proprietary protocol multi-channel alignment, either
in the FPGA fabric in soft IP or use Intel's 10GBASE-KR PHY IP core product as full
solutions in the FPGA.
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Figure 121. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS)
Configuration
Interlaken
CRC32 Generator
32-bit
data
PRP
Generator
tx_clkout
Transcode
Encoder
KR FEC
Encoder
KR FEC
TX Gearbox
KR FEC
Scrambler
Parallel Clock (322.265625 MHz)
322.265625 MHz
tx_coreclkin
PRBS
Generator
64B/66B Encoder
and TX SM
32
Scrambler (3)
TX
Gearbox
Serializer
(10.3125 Gbps)
tx_serial_data
32
Enhanced PCS
TX FIFO
FPGA
Fabric
Interlaken
Frame Generator
Transmitter Enhanced PCS
Interlaken
Disparity Generator
Transmitter PMA
tx_pma_div_clkout
Receiver Enhanced PCS
Enhanced PCS
RX FIFO
32-bit
data
322.265625 MHz
rx_coreclkin
PRBS
Verifier
Interlaken
CRC32 Checker
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler (3)
Interlaken
Disparity Checker
32
Block
Synchronizer (1)
32
RX
Gearbox
rx_pma_div_clkout
Deserializer
CDR
rx_serial_data
Receiver PMA
PRP
Verifier
rx_clkout
10GBASE-R
BER Checker
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
Parallel Clock (322.265625 MHz)
Clock Generation Block (CGB)
(5156.25 MHz) =
Data rate/2 (2)
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
ATX PLL
fPLL
CMU PLL
Serial Clock
Input Reference Clock
Notes:
1. Can be enabled or disabled based on the gearbox ratio selected
2. Depends on the value of the clock division factor chosen
3. To use the Scrambler and Descrambler, you must use a 66:32, 66:40, or 66:64 gear ratio and the Block Synchronizer must be enabled
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Figure 122. Transceiver Channel Datapath and Clocking for a Basic with KR FEC
Configuration
Clock frequencies in this figure are examples based on a 10.3125 Gbps data rate.
FPGA
Fabric
Transmitter Enhanced PCS
KR FEC
Encoder
KR FEC
TX Gearbox
Transcode
Encoder
tx_clkout
KR FEC
tx_pma_div_clkout
Enhanced PCS
RX FIFO
Interlaken
CRC32 Checker
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler
Block
Synchronizer
RX
Gearbox
PRBS
Verifier
/64
RX
Data &
Control
PRP
Verifier
64 + 2
rx_coreclkin
@ 156.25 MHz
rx_rcvd_clk
Interlaken
Disparity Checker
rx_pma_div_clkout
Deserializer
CDR
rx_serial_data
Enhanced PCS
TX FIFO
156.25 MHz (2)
Receiver Enhanced PCS
Receiver PMA
rx_pma_clk
Interlaken
Frame Generator
PRP
Generator
Parallel Clock (161.13 MHz) (3)
tx_krfec_clk
KR FEC
Scrambler
tx_pma_clk
64 + 2
tx_coreclkin
@ 156.25 MHz
PRBS
Generator
Interlaken
CRC32 Generator
64B/66B Encoder
and TX SM
Scrambler
TX
Gearbox
Serializer
tx_serial_data
64
tx_hf_clk
5156.25 MHz (10.3125 Gbps data rate/2) (1)
TX
Data &
Control
Interlaken
Disparity Generator
Transmitter PMA
156.25 MHz (2)
Parallel Clock (161.13 MHz) (3)
rx_clkout
rx_krfec_clk
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
10GBASE-R
BER Checker
KR FEC
tx_serial_clk0
(5156.25 MHz) =
Data rate/2
Clock Generation Block (CGB)
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Notes:
1. Value is based on the clock division factor chosen
2. Value is calculated as data rate on parallel interface/FPGA fabric - PCS interface width
3. Value is calculated as data rate on serial interface/PCS-PMA interface width
2.9.1.1 How to Implement the Basic (Enhanced PCS) and Basic with KR FEC
Transceiver Configuration Rules in Arria 10 Transceivers
You should be familiar with the Basic (Enhanced PCS) and PMA architecture, PLL
architecture, and the reset controller before implementing the Basic (Enhanced PCS)
or Basic with KR FEC Transceiver Configuration Rule.
1.
Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 31 for more details.
2. Select Basic (Enhanced PCS) or Basic with KR FEC from the Transceiver
Configuration Rules list located under Datapath Options.
3.
Use the parameter values in the tables in Transceiver Native PHY IP Parameters for
Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules as a
starting point. Or, you can use the protocol presets described in Transceiver Native
PHY Presets. You can then modify the settings to meet your specific requirements.
4.
Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with
KR FEC Configurations
tx_cal_busy
rx_cal_busy
NIOS
Hard Calibration IP
TX PMA
tx_serial_data
Reconfiguration
Registers
TX Enhanced PCS
tx_digital_reset
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
Serializer
Clock
Generation
Block
tx_serial_clk0
(from TX PLL)
RX PMA
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_analog_reset
rx_analog_reset
RX Enhanced PCS
Deserializer
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0]
CDR
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0]
rx_cdr_refclk0
5.
Configure and instantiate the PLL.
6.
Create a transceiver reset controller. You can use your own reset controller or use
the Transceiver PHY Reset Controller.
7.
Connect the Native PHY IP core to the PLL IP core and the reset controller.
Figure 124. Connection Guidelines for a Basic (Enhanced PCS) Transceiver Design
PLL IP Core
Design
Testbench
Reset
Controller
32-bit data
(32:32
gearbox ratio)
Arria 10 Transceiver
Native PHY
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Figure 125. Connection Guidelines for a Basic with KR FEC Transceiver Design
PLL IP Core
Reset
Controller
Design
Testbench
64d + 2c
Arria 10 Transceiver
Native PHY
8.
Simulate your design to verify its functionality.
Related Links
•
Arria 10 Enhanced PCS Architecture on page 445
For more information about Enhanced PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Enhanced PCS Ports on page 74
For detailed information about the available ports in the Basic protocol.
2.9.1.2 Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic
with KR FEC
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 211.
General and Datapath Parameters
The first two sections of the Parameter Editor for the Transceiver Native PHY provide a list of general and
datapath options to customize the transceiver.
Range
Parameter
Message level for rule violations
error, warning
Transceiver configuration rules
Basic (Enhanced PCS), Basic w/KR FEC
PMA configuration rules
Basic, QPI, GPON
Transceiver mode
TX / RX Duplex, TX Simplex, RX Simplex
Number of data channels
1 to 96
Data rate
GX transceiver channel: 1 Gbps
(47)
to 17.4 Gbps
continued...
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Parameter
Range
GT transceiver channel: 1 Gbps
Enable datapath and interface reconfiguration
On / Off
Enable simplified data interface
On / Off
Table 212.
(47)
to 25.8 Gbps
(48)
TX PMA Parameters
Parameter
Range
TX channel bonding mode
Not bonded, PMA only bonding, PMA and PCS bonding
PCS TX channel bonding master
Auto, 0 to n-1, n (where n = the number of data channels)
Actual PCS TX channel bonding master
n-1 (where n = the number of data channels)
TX local clock division factor
1, 2, 4, 8
Number of TX PLL clock inputs per channel
1, 2, 3, 4
Initial TX PLL clock input selection
0
Enable tx_pma_clkout port
On / Off
Enable tx_pma_div_clkout port
On / Off
tx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port
On / Off
Enable tx_pma_qpipullup port (QPI)
On / Off
Enable tx_pma_qpipulldn port (QPI)
On / Off
Enable tx_pma_txdetectrx port (QPI)
On / Off
Enable tx_pma_rxfound port (QPI)
On / Off
Enable rx_serialpbken port
On / Off
Table 213.
RX PMA Parameters
Parameter
Range
Number of CDR reference clocks
1 to 5
Selected CDR reference clock
0 to 4
Selected CDR reference clock frequency
For Basic (Enhanced PCS): Depends on the data rate
parameter
For Basic with KR FEC: 50 to 800
PPM detector threshold
100, 300, 500, 1000
CTLE adaptation mode
manual
DFE adaptation mode
adaptation enabled, manual, disabled
Number of fixed dfe taps
3, 7
Enable rx_pma_clkout port
On / Off
continued...
(47)
Applies when operating in reduced power modes. For standard power modes, the Enhanced
PCS minimum data rate is 1600 Mbps.
(48)
The Enhanced PCS must be configured in basic mode to support this data rate range.
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Parameter
Range
Enable rx_pma_div_clkout port
On / Off
rx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port
On / Off
Enable rx_pma_qpipulldn port (QPI)
On / Off
Enable rx_is_lockedtodata port
On / Off
Enable rx_is_lockedtoref port
On / Off
Enable rx_set_locktodata and rx_set_locktoref ports
On / Off
Enable rx_serialpbken port
On / Off
Enable PRBS verifier control and status ports
On / Off
Table 214.
Enhanced PCS Parameters
Parameter
Enhanced PCS/PMA interface width
Range
32, 40, 64
Note: Basic with KR FEC allows 64 only
FPGA fabric/Enhanced PCS interface width
32, 40, 50, 64, 66, 67
Note: Basic with KR FEC allows 66 only
Enable Enhanced PCS low latency mode
On / Off
Enable RX/TX FIFO double width mode
On / Off
TX FIFO mode
Phase compensation, Register, Interlaken, Basic, Fast
register
Note: Only Basic Enhanced and Basic Enhanced with
KRFEC are valid.
TX FIFO partially full threshold
10, 11, 12, 13, 14, 15
TX FIFO partially empty threshold
1, 2, 3, 4, 5
Enable tx_enh_fifo_full port
On / Off
Enable tx_enh_fifo_pfull port
On / Off
Enable tx_enh_fifo_empty port
On / Off
Enable tx_enh_fifo_pempty port
On / Off
RX FIFO mode
Phase Compensation, Register, Basic
RX FIFO partially full threshold
0 to 31
RX FIFO partially empty threshold
0 to 31
Enable RX FIFO alignment word deletion (Interlaken)
On / Off
Enable RX FIFO control word deletion (Interlaken)
On / Off
Enable rx_enh_data_valid port
On / Off
Enable rx_enh_fifo_full port
On / Off
Enable rx_enh_fifo_pfull port
On / Off
Enable rx_enh_fifo_empty port
On / Off
Enable rx_enh_fifo_pempty port
On / Off
continued...
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Parameter
Range
Enable rx_enh_fifo_del port (10GBASE-R)
On / Off
Enable rx_enh_fifo_insert port (10GBASE-R)
On / Off
Enable rx_enh_fifo_rd_en port (Interlaken)
On / Off
Enable rx_enh_fifo_align_val port (Interlaken)
On / Off
Enable rx_enh_fifo_align_cir port (Interlaken)
On / Off
Enable TX 64b/66b encoder
On / Off
Enable RX 64b/66b decoder
On / Off
Enable TX sync header error insertion
On / Off
Enable RX block synchronizer
On / Off
Enable rx_enh_blk_lock port
On / Off
Enable TX data bitslip
On / Off
Enable TX data polarity inversion
On / Off
Enable RX data bitslip
On / Off
Enable RX data polarity inversion
On / Off
Enable tx_enh_bitslip port
On / Off
Enable rx_bitslip port
On / Off
Enable RX KR-FEC error marking
On / Off
Error marking type
10G, 40G
Enable KR-FEC TX error insertion
On / Off
KR-FEC TX error insertion spacing
On / Off
Enable tx_enh_frame port
On / Off
Enable rx_enh_frame port
On / Off
Enable rx_enh_frame_dian_status port
On / Off
Table 215.
Dynamic Reconfiguration Parameters
Parameter
Range
Enable dynamic reconfiguration
On / Off
Share reconfiguration interface
On / Off
Enable Altera Debug Master Endpoint
On / Off
Enable embedded debug
On / Off
Enable capability registers
On / Off
Set user-defined IP identifier
number
Enable control and status registers
On / Off
Enable prbs soft accumulators
On / Off
Configuration file prefix
text string
Generate SystemVerilog package file
On / Off
Generate C header file
On / Off
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Table 216.
Generate Options Parameters
Parameter
Generate parameter documentation file
Range
On / Off
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
2.9.1.3 How to Enable Low Latency in Basic Enhanced PCS
In the Parameter Editor, use the following settings to enable low latency:
1.
Select the Enable 'Enhanced PCS' low latency mode option.
2.
Select one of the following gear ratios:
Single-width mode: 32:32, 40:40, 64:64, 66:40, 66:64, or 64:32
Double-width mode: 40:40, 64:64, or 66:64
3.
Select Phase_compensation in the TX and RX FIFO mode list.
4. If you need the Scrambler and Descrambler features, enable Block Synchronize
and use the 66:32, 66:40, or 66:64 gear ratio.
2.9.1.4 Enhanced PCS FIFO Operation
Phase Compensation Mode
Phase compensation mode ensures correct data transfer between the core clock and
parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must
be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in
this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can
tie tx_fifo_wr_en or rx_data_valid to 1.
Basic Mode
Basic mode allows you to drive the write and read side of a FIFO with different clock
frequencies. tx_coreclkin or rx_coreclkin must have a minimum frequency of
the lane data rate divided by 66. The frequency range for tx_coreclkin or
rx_coreclkin is (data rate/32) to (data rate/66). For best results, Intel
recommends that tx_coreclkin or rx_coreclkin be set to (data rate/32). Monitor
the FIFO flag to control write and read operations.
For TX FIFO, assert tx_enh_data_valid with the tx_fifo_pfull signal going low.
This can be done with the following example assignment:
assign tx_enh_data_valid = ~tx_fifo_pfull;
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Figure 126. TX FIFO Basic Mode Operation
tx_clkout (read side)
tx_coreclk (write side)
tx_parallel_data[63:0]
64’d0
64’d1
64’d2
64’d3
64’d4
64’d5
64’d6
64’d7
64’d8
64’d9
64’ha
tx_digitalreset
tx_enh_datavalid
tx_fifo_pempty
tx_fifo_full
tx_fifo_pfull
For RX FIFO, assert rx_enh_read_en with the rx_fifo_pempty signal going low.
This can be done with the following example assignment:
assign rx_enh_read_en = ~rx_fifo_pempty;
Figure 127. RX FIFO Basic Mode Operation
rx_clkout (write side)
rx_coreclkin (read side)
rx_parallel_data[63:0]
64’d0
64’d1
64’d2
64’d3
64’d4
64’d5
64’d6
64’d7
64’d8
64’d9
64’ha
rx_digitalreset
rx_enh_read_en
rx_fifo_pfull
rx_fifo_empty
rx_fifo_pempty
If you are using even gear ratios, the rx_enh_data_valid signal is always high. For
uneven gear ratios, rx_enh_data_valid toggles. RX parallel data is valid when
rx_enh_data_valid is high. Discard invalid RX parallel data when the
rx_enh_datavalid signal is low.
Register and Fast Register Mode
This FIFO mode is used for protocols, which require deterministic latency. You can tie
tx_fifo_wr_en to 1.
2.9.1.5 TX Data Bitslip
The bit slip feature in the TX gearbox allows you to slip the transmitter bits before
they are sent to the serializer.
The value specified on the TX bit slip bus indicates the number of bit slips. The
minimum slip is one UI. The maximum number of bits slipped is equal to the FPGA
fabric-to-transceiver interface width minus 1. For example, if the FPGA fabric-totransceiver interface width is 64 bits, the bit slip logic can slip a maximum of 63 bits.
Each channel has 6 bits to determine the number of bits to slip. The TX bit slip bus is
a level-sensitive port, so the TX serial data is bit slipped statically by TX bit slip port
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assignments. Each TX channel has its own TX bit slip assignment and the bit slip
amount is relative to the other TX channels. You can improve lane-to-lane skew by
assigning TX bit slip ports with proper values.
The following figure shows the effect of slipping tx_serial_data[0] by one UI to
reduce the skew with tx_serial_data[1]. After the bit slip, tx_serial_data[0]
and tx_serial_data[1] are aligned.
Figure 128. TX Bit Slip
tx_serial_clock
1 UI
tx_enh_bitslip[0] 0000000
tx_serial_data[0] (Before)
tx_enh_bitslip[0] 0000001
tx_serial_data[0] (After)
tx_serial_data[1]
2.9.1.6 TX Data Polarity Inversion
Use the TX data polarity inversion feature to swap the positive and negative signals of
a serial differential link if they were erroneously swapped during board layout. To
enable TX data polarity inversion, select the Enable TX data polarity inversion
option in the Gearbox section of Platform Designer (Standard). It can also be
dynamically controlled with dynamic reconfiguration.
2.9.1.7 RX Data Bitslip
The RX data bit slip in the RX gearbox allows you to slip the recovered data. An
asynchronous active high edge on the rx_bitslip port changes the word boundary,
shifting rx_parallel_data one bit at a time. Use the rx_bitslip port with its own
word aligning logic. Assert the rx_bitslip signal for at least two parallel clock cycles
to allow synchronization. You can verify the word alignment by monitoring
rx_parallel_data. Using the RX data bit slip feature is optional.
Figure 129. RX Bit Slip
rx_clkout
rx_bitslip
rx_parallel_data[63:0]
64’d0
64’d1
2.9.1.8 RX Data Polarity Inversion
Use the RX data polarity inversion feature to swap the positive and negative signals of
a serial differential link if they were erroneously swapped during board layout. To
enable RX data polarity inversion, select the Enable RX data polarity inversion
option in the Gearbox section of Platform Designer (Standard). It can also be
dynamically controlled with dynamic reconfiguration.
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2.9.2 Using the Basic/Custom, Basic/Custom with Rate Match
Configurations of Standard PCS
Use one of the following transceiver configuration rules to implement protocols such as
SONET/SDH, SDI/HD, SATA, or your own custom protocol:
•
Basic protocol
•
Basic protocol with low latency enabled
•
Basic with rate match protocol
Figure 130. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate
Match Configurations
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width
is 10 bits.
Transmitter Standard PCS
Transmitter PMA
16
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
10
FPGA
Fabric
PRBS
Generator
625 MHz (2)
tx_coreclkin
tx_clkout
125 MHz (1)
62.5 MHz (1)
/2
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
8B/10B Decoder
125 MHz (1)
Parallel Clock
(From Clock
Divider)
Rate Match FIFO (3)
Parallel Clock
(Recovered)
Word Aligner
Deserializer
CDR
rx_serial_data
10
16
rx_coreclkin
rx_clkout
62.5 MHz (1)
tx_clkout
rx_clkout or
tx_clkout
/2
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Serial Clock
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width =1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
3. This block is only enabled when using the Basic with Rate Match transceiver configuration rule.
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targetted data rate, you can optionally bypass the byte serializer
and deserializer blocks.
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Figure 131. Transceiver Channel Datapath and Clocking for Basic Configuration with Low
Latency Enabled
The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width
is 10 bits.
Transmitter Standard PCS
Transmitter PMA
16
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
10
FPGA
Fabric
PRBS
Generator
625 MHz (2)
tx_coreclkin
tx_clkout
125 MHz (1)
62.5 MHz (1)
/2
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
Parallel Clock
(Recovered)
125 MHz (1)
Parallel Clock
(From Clock
Divider)
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
10
16
rx_coreclkin
rx_clkout
62.5 MHz (1)
tx_clkout
rx_clkout or
tx_clkout
/2
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Serial Clock
Notes:
1. The parallel clock (tx_clkout or rx_clkout) is calculated as data rate/PCS-PMA interface width = 1250/10 = 125 MHz.
When the Byte Serializer is set to Serialize x2 mode, tx_clkout and rx_clkout become 1250/20 = 62.5 MHz.
2. The serial clock is calculated as data rate/2. The PMA runs on a dual data rate clock.
In low latency modes, the transmitter and receiver FIFOs are always enabled.
Depending on the targeted data rate, you can optionally bypass the byte serializer and
deserializer blocks.
Related Links
Arria 10 Standard PCS Architecture on page 463
2.9.2.1 Word Aligner Manual Mode
To use this mode:
1. Set the RX word aligner mode to Manual (FPGA Fabric controlled).
2.
Set the RX word aligner pattern length option according to the PCS-PMA
interface width.
3. Enter a hexadecimal value in the RX word aligner pattern (hex) field.
This mode adds rx_patterndetect and rx_syncstatus. You can select the
Enable rx_std_wa_patternalign port option to enable
rx_std_wa_patternalign. An active high on rx_std_wa_patternalign re-aligns
the word aligner one time.
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Note:
•
rx_patterndetect is asserted whenever there is a pattern match.
•
rx_syncstatus is asserted after the word aligner achieves synchronization.
•
rx_std_wa_patternalign is asserted to re-align and resynchronize.
•
If there is more than one channel in the design, rx_patterndetect,
rx_syncstatus and rx_std_wa_patternalign become buses in which each
bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data.
The following timing diagrams demonstrate how to use the ports and show the
relationship between the various control and status signals. In the top waveform,
rx_parallel_data is initially misaligned. After asserting the
rx_std_wa_patternalign signal, it becomes aligned. The bottom waveform shows
the behavior of the rx_syncstatus signal when rx_parallel_data is already
aligned.
Figure 132. Manual Mode when the PCS-PMA Interface Width is 8 Bits
tx_parallel_data = 8'hBC and the word aligner pattern = 8'hBC
rx_std_wa_patternalign
tx_parallel_data bc
rx_parallel_data 00
bc
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
tx_parallel_data bc
rx_parallel_data bc
rx_patterndetect
rx_syncstatus
In manual alignment mode, the word alignment operation is manually controlled with
the rx_std_wa_patternalign input signal or the rx_enapatternalign register.
The word aligner operation is level-sensitive to rx_enapatternalign. The word
aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it realigns to the new word boundary.
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Figure 133. Manual Mode when the PCS-PMA Interface Width is 10 Bits
tx_parallel_data = 10'h3BC and the word aligner pattern = 10'h3BC
rx_std_wa_patternalign
tx_parallel_data
3bc
rx_parallel_data
000
3bc
rx_patterndetect
rx_syncstatus
rx_std_wa_patternalign
tx_parallel_data
3bc
rx_parallel_data
3bc
rx_patterndetect
rx_syncstatus
Figure 134. Manual Mode when the PCS-PMA Interface Width is 16 Bits
tx_parallel_data = 16'hF3BC and the word aligner pattern = 16'hF3BC
rx_std_wa_patternalign
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
f3bc
0000
00
00
rx_std_wa_patternalign
tx_parallel_data
rx_parallel_data
rx_patterndetect
rx_syncstatus
f3bc
f3bc
01
11
f3bc
01
11
11
00
11
Figure 135. Manual Mode when the PCS-PMA Interface Width is 20 Bits
tx_parallel_data = 20'hFC3BC and the word aligner pattern = 20'hFC3BC
rx_std_wa_patternalign
tx_parallel_data
fc3bc
rx_parallel_data
0000
fc3bc
rx_patterndetect
00
01
rx_syncstatus
00
11
11
11
rx_std_wa_patternalign
tx_parallel_data
fc3bc
rx_parallel_data
fc3bc
rx_patterndetect
01
rx_syncstatus
11
00
11
2.9.2.2 Word Aligner Synchronous State Machine Mode
To use this mode:
•
Select the Enable TX 8B/10B encoder option.
•
Select the Enable RX 8B/10B decoder option.
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The 8B/10B encoder and decoder add the following additional ports:
•
tx_datak
•
rx_datak
•
rx_errdetect
•
rx_disperr
•
rx_runningdisp
1. Set the RX word aligner mode to synchronous state machine.
2.
Set the RX word aligner pattern length option according to the PCS-PMA
interface width.
3.
Enter a hexadecimal value in the RX word aligner pattern (hex) field.
The RX word aligner pattern is the 8B/10B encoded version of the data pattern. You
can also specify the number of word alignment patterns to achieve synchronization,
the number of invalid data words to lose synchronization, and the number of valid
data words to decrement error count. This mode adds two additional ports:
rx_patterndetect and rx_syncstatus.
Note:
•
rx_patterndetect is asserted whenever there is a pattern match.
•
rx_syncstatus is asserted after the word aligner achieves synchronization.
•
rx_std_wa_patternalign is asserted to re-align and re-synchronize.
•
If there is more than one channel in the design, tx_datak, rx_datak,
rx_errdetect, rx_disperr, rx_runningdisp, rx_patterndetect, and
rx_syncstatus become buses in which each bit corresponds to one channel.
You can verify this feature by monitoring rx_parallel_data.
Figure 136. Synchronization State Machine Mode when the PCS-PMA Interface Width is
20 Bits
rx_std_wa_patternalign
tx_datak 11
tx_parallel_data bc02
rx_parallel_data 0000
rx_datak 00
02bc
01
rx_errdetect 11
00
rx_disperr 11
00
rx_runningdisp 00
11
rx_patterndetect 00
01
rx_syncstatus 00
00
11
00
11
00
11
11
2.9.2.3 RX Bit Slip
To use the RX bit slip, select Enable rx_bitslip port and set the word aligner mode to
bit slip. This adds rx_bitslip as an input control port. An active high edge on
rx_bitslip slips one bit at a time. When rx_bitslip is toggled, the word aligner
slips one bit at a time on every active high edge. Assert the rx_bitslip signal for at
least two parallel clock cycles to allow synchronization. You can verify this feature by
monitoring rx_parallel_data.
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The RX bit slip feature is optional and may or may not be enabled.
Figure 137. RX Bit Slip in 8-bit Mode
tx_parallel_data = 8'hbc
rx_std_bitslipboundarysel 01111
rx_bitslip
tx_parallel_data bc
rx_parallel_data 00
97
cb
e5
f2
79
bc
Figure 138. RX Bit Slip in 10-bit Mode
tx_parallel_data = 10'h3bc
rx_std_bitslipboundarysel
01111
rx_bitslip
tx_parallel_data 3bc
rx_parallel_data 000
1de
0ef
277
33b
39d
3ce
1e7
2f3
379
3bc
Figure 139. RX Bit Slip in 16-bit Mode
tx_parallel_data = 16'hfcbc
rx_std_bitslipboundarysel
00001
00010
00011
00100
00101
00110
cbcf
e5e7
f2f3
f979
fcbc
rx_bitslip
tx_parallel_data
fcbc
rx_parallel_data
979f
Figure 140. RX Bit Slip in 20-bit Mode
tx_parallel_data = 20'h3fcbc
rx_std_bitslipboundarysel
00001
00010
00011
00100
00101
00110
00111
01000
f2f0f
f9787
fcbc3
de5e1
ff2f0
7f978
3fcbc
rx_bitslip
tx_parallel_data
3fcbc
rx_parallel_data
e5e1f
2.9.2.4 RX Polarity Inversion
Receiver polarity inversion can be enabled in low latency, basic, and basic rate match
modes.
To enable the RX polarity inversion feature, select the Enable RX polarity inversion
and Enable rx_polinv port options.
This mode adds rx_polinv. If there is more than one channel in the design,
rx_polinv is a bus in which each bit corresponds to a channel. As long as
rx_polinv is asserted, the RX data received has a reverse polarity.
You can verify this feature by monitoring rx_parallel_data.
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Figure 141. RX Polarity Inversion
rx_polinv
tx_parallel_data 11111100001110111100
rx_parallel_data 11111100001...
00000011110001000011
11111100001110111100
rx_patterndetect 01
rx_syncstatus 11
2.9.2.5 RX Bit Reversal
The RX bit reversal feature can be enabled in low latency, basic, and basic rate match
mode. The word aligner is available in any mode, bit slip, manual, or synchronous
state machine.
To enable this feature, select the Enable RX bit reversal and Enable
rx_std_bitrev_ena port options. This adds rx_std_bitrev_ena. If there is more
than one channel in the design, rx_std_bitrev_ena becomes a bus in which each
bit corresponds to a channel. As long as rx_std_bitrev_ena is asserted, the RX
data received by the core shows bit reversal.
You can verify this feature by monitoring rx_parallel_data.
Figure 142. RX Bit Reversal
rx_std_bitrev_ena
tx_parallel_data 11111100001110111100
rx_parallel_data 11111100001110111100
00111101110000111111
11111100001110111100
rx_patterndetect 01
00
01
rx_syncstatus 11
2.9.2.6 RX Byte Reversal
The RX byte reversal feature can be enabled in low latency, basic, and basic rate
match mode. The word aligner is available in any mode.
To enable this feature, select the Enable RX byte reversal and Enable
rx_std_byterev_ena port options. This adds rx_std_byterev_ena. If there is
more than one channel in the design, rx_std_byterev_ena becomes a bus in which
each bit corresponds to a channel. As long as rx_std_byterev_ena is asserted, the
RX data received by the core shows byte reversal.
You can verify this feature by monitoring rx_parallel_data.
Figure 143. RX Byte Reversal
rx_std_byterev_ena
tx_parallel_data 11111100001110111100
rx_parallel_data 111111... 11101111001111110000
11111100001110111100
rx_patterndetect 01
01
10
rx_syncstatus 11
2.9.2.7 Rate Match FIFO in Basic (Single Width) Mode
Only the rate match FIFO operation is covered in these steps.
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1.
Select basic (single width) in the RX rate match FIFO mode list.
2.
Enter values for the following parameters.
Parameter
Value
Description
RX rate match insert/delete +ve
pattern (hex)
20 bits of data specified
as a hexadecimal string
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
RX rate match insert/delete –ve
pattern (hex)
20 bits of data specified
as a hexadecimal string
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
ve (volt encodes) are NRZ_L conditions where +ve encodes 0 and –ve encodes 1.
ve is a running disparity (+/–RD) specifically used with the rate matcher.
Depending on the ppm difference (which is defined by protocol) between the
recovered clock and the local clock, the rate matcher adds or deletes a maximum
of four skip patterns (neutral disparity). The net neutrality is conserved even after
the skip word insertion or deletion because the control words alternate between
positive and negative disparity.
In the following figure, the first skip cluster has a /K28.5/ control pattern followed
by two /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control
pattern followed by four /K28.0/ skip patterns. The rate match FIFO deletes only
one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip
pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from
the second cluster for a total of three skip patterns deletion requirement.
The rate match FIFO can insert a maximum of four skip patterns in a cluster, if
there are no more than five skip patterns in the cluster after insertion.
Figure 144. Rate Match FIFO Deletion with Three Skip Patterns Required for Deletion
First Skip Cluster
Second Skip Cluster
tx_parallel_data
K28.5
K28.0
K28.0
K28.5
K28.0
K28.0
rx_parallel_data
K28.5
K28.0
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Three Skip Patterns Deleted
Note: /K28.5/ is the control pattern and /K28.0/ is the skip pattern
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/
is the skip pattern. The first skip cluster has a /K28.5/ control pattern followed by
three /K28.0/ skip patterns. The second skip cluster has a /K28.5/ control pattern
followed by two /K28.0/ skip patterns. The rate match FIFO inserts only two /
K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip
patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the
second cluster for a total of three skip patterns to meet the insertion requirement.
Figure 145. Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion
First Skip Cluster
Second Skip Cluster
tx_parallel_data
K28.5
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
Dx.y
rx_parallel_data
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.0
Three Skip Patterns Inserted
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K28.0
K28.0
Dx.y
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The following figure shows the deletion of D5 when the upstream transmitter
reference clock frequency is greater than the local receiver reference clock
frequency. It asserts rx_std_rmfifo_full for one parallel clock cycle while the
deletion takes place.
Figure 146. Rate Match FIFO Becoming Full After Receiving D5
tx_parallel_data
D1
D2
D3
D4
D5
D6
D7
D8
rx_parallel_data
D1
D2
D3
D4
D6
D7
D8
xx
xx
xx
rx_std_rmfifo_full
The following figure shows the insertion of skip symbols when the local receiver
reference clock frequency is greater than the upstream transmitter reference clock
frequency. It asserts rx_std_rmfifo_empty for one parallel clock cycle while
the insertion takes place.
Figure 147. Rate Match FIFO Becoming Empty After Receiving D3
tx_parallel_data
D1
D2
D3
D4
D5
D6
rx_parallel_data
D1
D2
D3
/K30.7/
D4
D5
rx_std_rmfifo_empty
2.9.2.8 Rate Match FIFO Basic (Double Width) Mode
1. Select basic (double width) in the RX rate match FIFO mode list.
2.
Enter values for the following parameters.
Value
Description
RX rate match insert/delete +ve
pattern (hex)
20 bits of data specified
as a hexadecimal string
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
RX rate match insert/delete -ve
pattern (hex)
20 bits of data specified
as a hexadecimal string
The first 10 bits correspond to the skip pattern and the
last 10 bits correspond to the control pattern. The skip
pattern must have neutral disparity.
Parameter
The rate match FIFO can delete as many pairs of skip patterns from a cluster as
necessary to avoid the rate match FIFO from overflowing. The rate match FIFO
can delete a pair of skip patterns only if the two 10-bit skip patterns appear in the
same clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip
patterns appear straddled on the MSByte of a clock cycle and the LSByte of the
next clock cycle, the rate match FIFO cannot delete the pair of skip patterns.
In the following figure, the first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle followed by one /
K28.0/ skip pattern in the LSByte of the next clock cycle. The rate match FIFO
cannot delete the two skip patterns in this skip cluster because they do not appear
in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in
the MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the
next two cycles. The rate match FIFO deletes both pairs of /K28.0/ skip patterns
(for a total of four skip patterns deleted) from the second skip cluster to meet the
three skip pattern deletion requirement.
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The rate match FIFO can insert as many pairs of skip patterns into a cluster
necessary to avoid the rate match FIFO from under running. The 10-bit skip
pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Figure 148. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion
/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
First Skip Cluster
Two Pairs of Skip
Patterns Deleted
Second Skip Cluster
tx_parallel_data[19:10]
Dx.y
K28.0
Dx.y
K28.5
K28.0
K28.0
Dx.y
tx_parallel_data[9:0]
Dx.y
K28.5
K28.0
Dx.y
K28.0
K28.0
Dx.y
rx_parallel_data[19:0]
Dx.y
K28.0
Dx.y
K28.5
Dx.y
rx_parallel_data[9:0]
Dx.y
K28.5
K28.0
Dx.y
Dx.y
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/
is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match
FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip
pattern insertion requirement.
Figure 149. Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion
First Skip Cluster
Second Skip Cluster
tx_parallel_data[19:10]
Dx.y
K28.0
Dx.y
K28.5
K28.0
K28.0
tx_parallel_data[9:0]
Dx.y
K28.5
Dx.y
Dx.y
K28.0
K28.0
rx_parallel_data[19:0]
Dx.y
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
rx_parallel_data[9:0]
Dx.y
K28.5
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
The following figure shows the deletion of the 20-bit word D7D8.
Figure 150. Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6
tx_parallel_data[19:0]
D2
D4
D6
D8
D10
D12
tx_parallel_data[9:0]
D1
D3
D5
D7
D9
D11
rx_parallel_data[19:10]
D2
D4
D6
D10
D12
xx
rx_parallel_data[9:0]
D1
D3
D5
D9
D11
xx
rx_std_rmfifo_full
The following figure shows the insertion of two skip symbols.
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Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6
tx_parallel_data[19:0]
D2
D4
D6
D8
D10
D12
tx_parallel_data[9:0]
D1
D3
D5
D7
D9
D11
rx_parallel_data[19:10]
D2
D4
D6
/K30.7/
D8
D10
rx_parallel_data[9:0]
D1
D3
D5
/K30.7/
D7
D9
rx_std_rmfifo_empty
2.9.2.9 8B/10B Encoder and Decoder
To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX
8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS
tab in the IP Editor. Platform Designer (Standard) allows implementing the 8B/10B
decoder in RX-only mode.
The following ports are added:
•
tx_datak
•
rx_datak
•
rx_runningdisp
•
rx_disperr
•
rx_errdetect
rx_datak and tx_datak indicate whether the parallel data is a control word or a
data word. The incoming 8-bit data (tx_parallel_data) and the control identifier
(tx_datak) are converted into a 10-bit data. After a power on reset, the 8B/10B
encoder takes the 10-bit data from the RD- column. Next, the encoder chooses the
10-bit data from the RD+ column to maintain neutral disparity. The running disparity
is shown by rx_runningdisp.
2.9.2.10 8B/10B TX Disparity Control
The Disparity Control feature controls the running disparity of the output from the
8B/10B Decoder.
To enable TX Disparity Control, select the Enable TX 8B/10B Disparity Control
option. The following ports are added:
•
tx_forcedisp—a control signal that indicates whether a disparity value has to
be forced or not
•
tx_dispval—a signal that indicates the value of the running disparity that is
being forced
When the number of data channels is more than 1, tx_forcedisp and tx_dispval
are shown as buses in which each bit corresponds to one channel.
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The following figure shows the current running disparity being altered in Basic singlewidth mode by forcing a positive disparity /K28.5/ when it was supposed to be a
negative disparity /K28.5/. In this example, a series of /K28.5/ code groups are
continuously being sent. The stream alternates between a positive running disparity
(RD+) /K28.5/ and a negative running disparity (RD-) /K28.5/ to maintain a neutral
overall disparity. The current running disparity at time n + 3 indicates that the /K28.5/
in time n + 4 should be encoded with a negative disparity. Because tx_forcedisp is
high at time n + 4, and tx_dispval is low, the /K28.5/ at time n + 4 is encoded as a
positive disparity code group.
Figure 152. 8B/10B TX Disparity Control
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BC
BC
BC
BC
BC
BC
BC
BC
Current Running Disparity
RD–
RD+
RD–
RD+
RD+
RD–
RD+
RD–
dataout[9:0]
17C
283
17C
283
283
17C
283
17C
clock
tx_in[7:0]
tx_ctrlenable
tx_forcedisp
tx_dispval
2.9.2.11 How to Enable Low Latency in Basic
In the Arria 10 Transceiver Native PHY IP Parameter Editor, use the following settings
to enable low latency:
1.
Select the Enable 'Standard PCS' low latency mode option.
2.
Select either low_latency or register FIFO in the TX FIFO mode list.
3.
Select either low_latency or register FIFO in the RX FIFO mode list.
4.
Select either Disabled or Serialize x2 in the TX byte serializer mode list.
5.
Select either Disabled or Serialize x2 in the RX byte deserializer mode list.
6.
Ensure that RX rate match FIFO mode is disabled.
7.
Set the RX word aligner mode to bitslip.
8.
Set the RX word aligner pattern length to 7 or 16.
Note: TX bitslip, RX bitslip, bit reversal, and polarity inversion modes are
supported.
2.9.2.12 TX Bit Slip
To use the TX bit slip, select the Enable TX bitslip and Enable
tx_std_bitslipboundarysel port options. This adds the
tx_std_bitslipboundarysel input port. The TX PCS automatically slips the
number of bits specified by tx_std_bitslipboundarysel. There is no port for TX
bit slip. If there is more than one channel in the design,
tx_std_bitslipboundarysel ports are multiplied by the number of channels. You
can verify this feature by monitoring the tx_parallel_data port.
Enabling the TX bit slip feature is optional.
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Note:
The rx_parallel_data values in the following figures are based on the TX and RX
bit reversal features being disabled.
Figure 153. TX Bit Slip in 8-bit Mode
tx_parallel_data = 8'hbc. tx_std_bitslipboundarysel = 5'b00001 (bit slip by 1 bit).
tx_std_bitslipboundarysel 00001
tx_parallel_data bc
rx_parallel_data 79
Figure 154. TX Bit Slip in 10-bit Mode
tx_parallel_data = 10'h3bc. tx_std_bitslipboundarysel = 5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel 00011
tx_parallel_data 3bc
rx_parallel_data 1e7
Figure 155. TX Bit Slip in 16-bit Mode
tx_parallel_data = 16'hfcbc. tx_std_bitslipboundarysel =5'b00011 (bit slip by 3 bits).
tx_std_bitslipboundarysel 00011
tx_parallel_data fcbc
rx_parallel_data 5e7f
Figure 156. TX Bit Slip in 20-bit Mode
tx_parallel_data = 20'hF3CBC. tx_std_bitslipboundarysel = 5'b00111 (bit slip by 7 bits).
tx_std_bitslipboundarysel 00111
tx_parallel_data f3cbc
rx_parallel_data e5e1f
2.9.2.13 TX Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be
swapped during board layout. Solutions such as a board respin or major updates to
the PLD logic can be expensive. The transmitter polarity inversion feature is provided
to correct this situation.
Transmitter polarity inversion can be enabled in low latency, basic, and basic rate
match modes.
To enable TX polarity inversion, select the Enable tx_polinv port option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
This mode adds tx_polinv. If there is more than one channel in the design,
tx_polinv is a bus with each bit corresponding to a channel. As long as tx_polinv
is asserted, the TX data transmitted has a reverse polarity.
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2.9.2.14 TX Bit Reversal
The TX bit reversal feature can be enabled in low latency, basic, and basic rate match
mode. The word aligner is available in any mode. This feature is parameter-based, and
creates no additional ports. If there is more than one channel in the design, all
channels have TX bit reversal.
To enable TX bit reversal, select the Enable TX bit reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
Figure 157. TX Bit Reversal
tx_parallel_data 11111100001110111100
rx_parallel_data 00000...
00111101110000111111
2.9.2.15 TX Byte Reversal
The TX byte reversal feature can be enabled in low latency, basic, and basic rate
match mode. The word aligner is available in any mode. This feature is parameterbased, and creates no additional ports. If there is more than one channel in the
design, all channels have TX byte reversal.
To enable TX byte reversal, select the Enable TX byte reversal option in Platform
Designer (Standard). It can also be dynamically controlled with dynamic
reconfiguration.
Figure 158. TX Byte Reversal
tx_parallel_data 11111100001110111100
rx_parallel_data 00000000...
11101111001111110000
2.9.2.16 How to Implement the Basic, Basic with Rate Match Transceiver
Configuration Rules in Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture,
and the reset controller before implementing your Basic protocol IP.
1.
Open the IP Catalog and select the Native PHY IP.
Refer to Select and Instantiate the PHY IP Core on page 31.
2. Select Basic/Custom (Standard PCS) or Basic/Custom w/Rate Match
(Standard PCS) from the Transceiver configuration rules list located under
Datapath Options depending on which configuration you want to use.
3.
Use the parameter values in the tables in Transceiver Native PHY IP Parameter
Settings for the Basic Protocol as a starting point. Or, you can use the protocol
presets described in Transceiver Native PHY Presets. You can then modify the
setting to meet your specific requirements.
4. Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 159. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match
Configurations
Arria 10 Transceiver Native PHY
reconfig_reset
reconfig_clk
reconfig_avmm
Reconfiguration
Registers
Nios Hard
Calibration IP
TX Standard PCS
tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
tx_digital_reset
tx_datak
tx_parallel_data[7:0]
tx_clkout
tx_cal_busy
rx_cal_busy
TX PMA
10
Serializer
tx_serial_data
Central/Local
Clock Divider
tx_analog_reset
tx_serial_clk0 (from TX PLL)
rx_analog_reset
RX Standard PCS
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
unused_rx_parallel_data[113:0]
rx_digital_reset
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
RX PMA
10
Deserializer
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
CDR
Note:
1. Only applies when using the Basic with Rate Match transceiver configuration rule.
5.
Instantiate and configure your PLL.
6.
Create a transceiver reset controller.
7.
Connect the Native PHY IP to the PLL IP and the reset controller. Use the
information in Transceiver Native PHY Ports for the Protocol to connect the ports.
Figure 160. Connection Guidelines for a Basic/Custom Design
tx_parallel_data
reset
pll_ref_clk
Pattern
Generator
pll_powerdown
rx_ready
tx_serial_data
rx_serial_data
rx_cdr_refclk
tx_digital_reset
pll_locked
PLL IP
tx_datak
tx_clkout
Reset
Controller
tx_analog_reset
rx_digital_reset
rx_analog_reset
tx_ready
clk
rx_is_lockedtoref
reset
rx_is_lockedtodata
Arria 10
Transceiver
Native
PHY
rx_parallel_data
reset
Pattern
Checker
rx_datak
rx_clkout
tx_serial_clk
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
For
Reconfiguration
cal_busy
8.
Simulate your design to verify its functionality.
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Related Links
•
Arria 10 Standard PCS Architecture on page 463
For more information about Standard PCS architecture
•
Arria 10 PMA Architecture on page 431
For more information about PMA architecture
•
Using PLLs and Clock Networks on page 386
For more information about implementing PLLs and clocks
•
PLLs on page 337
PLL architecture and implementation details
•
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
•
Standard PCS Ports on page 84
Port definitions for the Transceiver Native PHY Standard Datapath
2.9.2.17 Native PHY IP Parameter Settings for Basic, Basic with Rate Match
Configurations
This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 217.
General and Datapath Options Parameters
Parameter
Range
Message level for rule violations
error
warning
Transceiver configuration rules
Basic/Custom (Standard PCS)
Basic/Custom w/Rate Match (Standard
PCS)
PMA configuration rules
basic
TX/RX Duplex
TX Simplex
RX Simplex
Transceiver mode
Number of data channels
1 to 96
Data rate
611 Mbps to 12 Gbps
Enable datapath and interface reconfiguration
On/Off
Enable simplified data interface
On/Off
Table 218.
TX PMA Parameters
Parameter
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
Range
Not bonded
PMA-only bonding
PMA and PCS bonding
Auto, n-1 (where n = the number of data
channels)
n-1 (where n = the number of data channels)
continued...
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Parameter
Range
TX local clock division factor
1, 2, 4, 8
Number of TX PLL clock inputs per channel
1, 2, 3, 4
Initial TX PLL clock input selection
0 (Depends on the Number of TX PLL clock
inputs per channel value)
Enable tx_pma_clkout port
On/Off
Enable tx_pma_div_clkout port
On/Off
tx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port
On/Off
Enable tx_pma_qpipullup port (QPI)
On/Off
Enable tx_pma_qpipulldn port (QPI)
On/Off
Enable tx_pma_txdetectrx port (QPI)
On/Off
Enable tx_pma_rxfound port (QPI)
On/Off
Enable rx_seriallpbken port
On/Off
Table 219.
RX PMA Parameters
Parameter
Range
Number of CDR reference clocks
1, 2, 3, 4, 5
Selected CDR reference clock
0, 1, 2, 3, 4
Selected CDR reference clock frequency
Legal range defined by Quartus Prime software
PPM detector threshold
100, 300, 500, 1000
CTLE adaptation mode
manual
DFE adaptation mode
disabled
Number of fixed dfe taps
3, 7
Enable rx_pma_clkout port
On/Off
Enable rx_pma_div_clkout port
On/Off
rx_pma_div_clkout division factor
Disabled, 1, 2, 33, 40, 50, 66
Enable rx_pma_clkslip port
On/Off
Enable rx_pma_qpipulldn port (QPI)
On/Off
Enable rx_is_lockedtodata port
On/Off
Enable rx_is_lockedtoref port
On/Off
Enable rx_set_locktodata and rx_set_locktoref ports
On/Off
Enable rx_seriallpbken port
On/Off
Enable PRBS verifier control and status ports
On/Off
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Table 220.
Standard PCS Parameters
Parameter
Standard PCS / PMA interface width
Range
8, 10, 16, 20
FPGA fabric / Standard TX PCS interface width
8, 10, 16, 20, 32, 40
FPGA fabric / Standard RX PCS interface width
8, 10, 16, 20, 32, 40
Enable 'Standard PCS' low latency mode
On/Off
Off (for Basic with Rate Match)
TX FIFO mode
low_latency
register_fifo
fast_register
RX FIFO Mode
low_latency
register_fifo
Enable tx_std_pcfifo_full port
On/Off
Enable tx_std_pcfifo_empty port
On/Off
Enable rx_std_pcfifo_full port
On/Off
Enable rx_std_pcfifo_empty port
On/Off
TX byte serializer mode
Disabled
Serialize x2
Serialize x4
RX byte deserializer mode
Disabled
Deserialize x2
Deserialize x4
Enable TX 8B/10B encoder
On/Off
Enable TX 8B/10B disparity control
On/Off
Enable RX 8B/10B decoder
On/Off
RX rate match FIFO mode
Disabled
Basic 10-bit PMA (for Basic with Rate Match)
Basic 20-bit PMA (for Basic with Rate Match)
RX rate match insert/delete -ve pattern (hex)
User-defined value
RX rate match insert/delete +ve pattern (hex)
User-defined value
Enable rx_std_rmfifo_full port
On/Off
Enable rx_std_rmfifo_empty port
On/Off
PCI Express* Gen 3 rate match FIFO mode
Bypass
Enable TX bit slip
On/Off
Enable tx_std_bitslipboundarysel port
On/Off
RX word aligner mode
bitslip
manual (PLD controlled)
synchronous state machine
RX word aligner pattern length
7, 8, 10, 16, 20, 32, 40
RX word aligner pattern (hex)
User-defined value
Number of word alignment patterns to achieve sync
0-255
continued...
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Parameter
Range
Number of invalid data words to lose sync
0-63
Number of valid data words to decrement error count
0-255
Enable fast sync status reporting for deterministic latency SM
On/Off
Enable rx_std_wa_patternalign port
On/Off
Enable rx_std_wa_a1a2size port
On/Off
Enable rx_std_bitslipboundarysel port
On/Off
Enable rx_bitslip port
On/Off
Enable TX bit reversal
On/Off
Enable TX byte reversal
On/Off
Enable TX polarity inversion
On/Off
Enable tx_polinv port
On/Off
Enable RX bit reversal
On/Off
Enable rx_std_bitrev_ena port
On/Off
Enable RX byte reversal
On/Off
Enable rx_std_byterev_ena port
On/Off
Enable RX polarity inversion
On/Off
Enable rx_polinv port
On/Off
Enable rx_std_signaldetect port
On/Off
Enable PCIe dynamic datarate switch ports
Off
Enable PCIe pipe_hclk_in and pipe_hclk_out ports
Off
Enable PCIe Gen 3 analog control ports
Off
Enable PCIe electrical idle control and status ports
Off
Enable PCIe pipe_rx_polarity port
Off
Table 221.
Dynamic Reconfiguration Parameters
Parameter
Range
Enable dynamic reconfiguration
On/Off
Share reconfiguration interface
On/Off
Enable Altera Debug Master Endpoint
On/Off
Table 222.
Generation Options Parameters
Parameter
Range
Generate parameter documentation file
On/Off
Related Links
Using the Arria 10 Transceiver Native PHY IP Core on page 43
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2.9.3 Design Considerations for Implementing Arria 10 GT Channels
This section provides information on using the Arria 10 GT transceiver channels .
GT channels can be used in Enhanced PCS basic mode and PCS-Direct configuration to
support 25.8 Gbps. When GT channels are used in PCS-Direct configuration, the PCS
blocks are bypassed. The serializer/deserializer in GT channels supports 64 bit and
128 bit serialization factors.
2.9.3.1 Transceiver PHY IP
Arria 10 GT transceiver channels are implemented using the Native PHY IP with the
Basic (Enhanced PCS) transceiver configuration rule.
•
To support 25.8 Gbps, the Enhanced PCS must be configured in basic mode with
the low latency check box unselected. To configure the Enhanced PCS, do not
enable any functional blocks in the Enhanced PCS (that is, disable Block
Synchronizer, Gearbox, Scrambler, and Encoder).
•
You can also use the PCS-Direct mode for 25.8 Gbps.
You can bundle several GT transceiver channels with one Native PHY IP instantiation,
but you must instantiate a separate ATX PLL IP for every ATX PLL used.
2.9.3.2 PLL and GT Transceiver Channel Clock Lines
The ATX PLL is used to provide the clock source for the GT transceiver channels. Each
ATX PLL has two dedicated GT clock lines which connect the PLL directly to the GT
transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest
of the clock network for higher performance.
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Figure 161. GT Channel Configuration
CGB
Ch 5
CDR
CGB
Ch 4
CMU or CDR
ATX PLL1
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
ATX PLL0
Ch 1
CMU or CDR
CGB
Ch 0
CDR
When both the channels 0 and 1 are configured as GT channels, they are driven by
the same ATX PLL and have to be configured to run at the same data rates. This is
also true for channels 3 and 4 when they are configured as GT channels.
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Note:
•
GT channel bonding is not supported.
•
For optimum performance of GT channel, the reference clock of ATX PLL is
recommended to be from a dedicated reference clock pin in the same bank.
Related Links
Input Reference Clock Sources on page 360
2.9.3.3 Reset Controller
Each GT channel instantiated will have independent analog and digital reset ports.
Refer to the Resetting Transceiver Channels chapter for more details on designing a
reset controller to reset these ports.
Related Links
Resetting Transceiver Channels on page 402
Reset controller general information and implementation details
2.9.3.4 How to Implement Designs for Data Rates Above 17.4 Gbps Using
Enhanced PCS in Low Latency Mode
•
You should be familiar with the Enhanced PCS and PMA architecture, PLL
architecture, and the reset controller.
•
Make sure you have selected an Arria 10 GT device for the project
1. Select Tools ➤ IP Catalog ➤ Interface Protocols ➤ Transceiver PHY ➤ Arria
10 Transceiver Native PHY. Refer to Select and Instantiate the PHY IP Core on
page 31 for detailed steps.
2.
Set VCCR_GXB and VCCT_GXB to 1.1V. Note these settings will be overridden by
the QSF file settings which should also be set to 1.1V. QII will make sure the
actual voltage prescribed is in line with pin connection guidelines and the Arria10
Data Sheet.
3. Select Basic (Enhanced PCS) from the Transceiver configuration rules list
located under Datapath Options.
4. Use the parameter values in the tables in Transceiver Native PHY IP Parameters
Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the
Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can
use the protocol presets described in Transceiver Native PHY Presets. You can then
modify the settings to meet your specific requirements.
•
Ensure that the data rate is set to 25781.25 Mbps. To achieve the higher data
rates, use Enhanced PCS basic mode with the low latency option unchecked.
Select a CDR reference clock to match your data rate. Use Phase
compensation FIFO modes.
•
Make sure DFE is disabled from Rx PMA settings.
•
Set the Enhanced PCS / PMA interface width to 64 bits.
•
Set the FPGA fabric / Enhanced PCS interface width to 64 bits.
•
You can enable RX/TX FIFO double width mode to create a FPGA fabric / PCS
interface width of 128 bits.
•
Click Finish to generate the Native PHY IP (this is your RTL file).
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Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver
Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS
Interface width of 128 bits
tx_cal_busy
rx_cal_busy
NIOS
Hard Calibration IP
TX PMA
tx_serial_data
Reconfiguration
Registers
TX Enhanced PCS
Serializer
tx_digital_reset
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_serial_clk0
(from TX PLL)
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_control[17:0]
tx_parallel_data[127:0]
tx_coreclkin
tx_clkout
tx_enh_data_valid
tx_analog_reset
rx_analog_reset
RX PMA
RX Enhanced PCS
Deserializer
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
CDR
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0]
rx_digital_reset
rx_clkout
rx_coreclkin
rx_parallel_data[127:0]
rx_control[19:0]
refclk
5.
Select Tools ➤ IP Catalog ➤ Basic Functions ➤ Clocks ➤ PLLs and Resets ➤
PLL ➤ Arria 10 Transceiver ATX PLL. Refer to Instantiating the ATX PLL IP Core
on page 342 for detailed steps.
6. Configure the ATX PLL IP using the Parameter Editor.
•
Select the GT clock output buffer.
•
Enable the PLL GT clock output port.
•
Set the PLL output clock frequency to the Native PHY IP recommended
frequency.
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Figure 163. ATX PLL IP with GT Clock Lines Enabled
7.
Create a transceiver reset controller. Refer to Resetting Transceiver Channels on
page 402 for more details about configuring the reset IP core.
8.
Connect the Native PHY IP core to the PLL IP core and the reset controller.
The ATX PLL's port tx_serial_clk_gt represents the dedicated GT clock lines.
Connect this port to the Native PHY IP core's tx_serial_clk0 port. The Quartus
Prime software will automatically use the dedicated GT clocks instead of the x1
clock network.
2.9.3.5 Arria 10 GT Channel Usage
All Arria 10 GT devices have a total of six GT transceiver channels to support 25.8
Gbps.
Arria 10 GT devices have three transceiver banks that support up to two GT channels.
Each channel can operate as a duplex channel, TX only, or RX only channel.
Transceiver banks GXBL1E and GXBL1H each contain two GT transceiver channels:
Ch3 and Ch4. Transceiver bank GXBL1G contains two GT transceiver channels: Ch0
and Ch1. Channels 2 and 5 on any bank can only be configured as GX transceiver
channels.
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Table 223.
Valid Permutations for GT and GX Channel Configuration in Transceiver Bank
GXBL1G for Channels 0, 1, and 2
GT Transceiver Channel
Configuration A
Configuration B
Configuration C
Configuration D
Ch2
Unusable
Unusable
Unusable
GX
Ch1
GT
GT
Unusable
GX
Ch0
GT
Unusable
GT
GX
Notes on grouping channels Ch0, Ch1, and Ch2:
Table 224.
•
If channels 0 and 1 are configured as GT channels, channel 2 is unusable
(Configuration A).
•
If either channel 0 or 1 is configured as a GT channel, the remaining channels are
unusable (Configurations B and C).
•
If channels 0 and 1 are not configured as GT channels, this grouping can be all
configured as GX channels (Configuration D).
•
If either channel 0 or 1 is used as a GT channel, then the ATX PLL adjacent to
channel 0 and 1 must be reserved for GT channel configurations.
Valid Permutations for GT and GX Channel Configuration in Transceiver Banks
GXBL1E and GXBL1H for Channels 3, 4, and 5
GT Transceiver Channel
Configuration A
Configuration B
Configuration C
Configuration D
Ch5
Unusable
Unusable
Unusable
GX
Ch4
GT
GT
Unusable
GX
Ch3
GT
Unusable
GT
GX
Notes on grouping channels Ch3, Ch4, and Ch5:
•
If channels 3 and 4 are configured as GT channels, channel 5 is unusable
(Configuration A).
•
If either channel 3 or 4 is configured as a GT channel, the remaining channels are
unusable (Configurations B and C).
•
If channels 3 and 4 are not configured as GT channels, this grouping can be all
configured as GX channels (Configuration D).
•
If either channel 3 or 4 is used as a GT channel, then the ATX PLL adjacent to
channel 3 and 4 must be reserved for GT channel configurations.
2.9.4 How to Implement PCS Direct Transceiver Configuration Rule
You should be familiar with PCS Direct architecture, PMA architecture, PLL
architecture, and the reset controller before implementing PCS Direct Transceiver
Configuration Rule.
1.
Open the IP Catalog and select Arria 10 Transceiver Native PHY IP. Refer to
Select and Instantiate the PHY IP Core on page 31 for detailed steps.
2.
Select PCS Direct from the Transceiver configuration rules list located under
Datapath Options.
3.
Configure your Native PHY IP.
4.
Click Generate to generate the Native PHY IP (this is your RTL file).
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5.
Instantiate and configure your PLL.
6.
Create a transceiver reset controller. You can use your own controller or use the
Transceiver PHY Reset Controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller.
Figure 164. Connection Guidelines for a PCS Direct PHY Design
tx_ready
clk
reset
rx_ready
Reset Controller
pll_sel
pll_refclk
pll_locked
PLL IP Core
rx_digitalreset
rx_analogreset
tx_digitalreset
tx_analogreset
rx_cal_busy
rx_is_lockedtodata
tx_cal_busy
pll_cal_busy
tx_serialclk0
rx_cdr_refclk
Data
Generator
Data
Verifier
8.
tx_clkout
tx_parallel_data
Arria 10 Transceiver Native PHY
rx_clkout
tx_serial_data
rx_serial_data
rx_parallel_data
Simulate your design to verify its functionality.
2.10 Simulating the Transceiver Native PHY IP Core
Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime
software supports register transfer level (RTL) and gate-level simulation in both
ModelSim - Intel FPGA Edition and third-party simulators. You run simulations using
your Quartus Prime project files.
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The following simulation flows are available:
•
NativeLink—This flow simplifies simulation by allowing you to start a simulation
from the Quartus Prime software. This flow automatically creates a simulation
script and compiles design files, IP simulation model files, and Intel simulation
library models.
Note: The Quartus Prime Pro Edition software does not support NativeLink RTL
simulation
•
Scripting IP Simulation—In this flow you perform the following actions:
1. Run the ip-setup-simulation utility to generate a single simulation script that
compiles simulation files for all the underlying IPs in your design. This script
needs to be regenerated whenever you upgrade or modify IPs in the design.
2. You create a top-level simulation script for compiling your testbench files and
simulating the testbench. It will source the script generated in the first action.
You do not have to modify this script even if you upgrade or modify the IPs in
your design.
•
Custom Flow—This flow allows you to customize simulation for more complex
requirements. You can use this flow to compile design files, IP simulation model
files, and Intel simulation library models manually.
You can simulate the following netlist:
•
The RTL functional netlist—This netlist provides cycle-accurate simulation using
Verilog HDL, SystemVerilog, and VHDL design source code. Intel and third-party
EDA vendors provide the simulation models.
Prerequisites to Simulation
Before you can simulate your design, you must have successfully passed Quartus
Prime Analysis and Synthesis.
Related Links
Simulating Intel FPGA Designs
2.10.1 NativeLink Simulation Flow
The NativeLink settings available in the Quartus Prime software allow you to specify
your simulation environment, simulation scripts, and testbenches. The Quartus Prime
software saves these settings in your project. After you specify the NativeLink
settings, you can start simulations easily from the Quartus Prime software.
2.10.1.1 How to Use NativeLink to Specify a ModelSim Simulation
Complete the following steps to specify the directory path and testbench settings for
your simulator:
1.
On the Tools menu, click Options, and then click EDA Tool Options.
2. Browse to the directory for your simulator. The following table lists the directories
for supported simulators:
Table 225.
Simulator Path
Simulator
Mentor Graphics* ModelSim - Intel FPGA Edition
Path
<drive>:\<simulator install path>\win32aloem (Windows)
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Simulator
Path
/<simulator install path>/bin (Linux*)
3. On the Assignments menu, click Settings.
4.
In the Category list, under EDA Tool Settings select Simulation.
5. In the Tool name list, select your simulator.
Note: ModelSim refers to ModelSim SE and PE. These simulators use the same
commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel
FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription
Edition.
6. In the Output directory, browse to the directory for your output files.
7. To map illegal HDL characters, turn on Map illegal HDL characters.
8. To filter netlist glitches , turn on Enable glitch filtering.
9. Complete the following steps to specify additional options for NativeLink
automation:
a.
Turn on Compile test bench.
b.
Click Test Benches.
The Test Benches dialog box appears.
c.
Click New.
d.
Under Create new test bench settings, for Test bench name type the test
bench name. For Top level module in the test bench, type the top-level module
name. These names should match the actual test bench module names.
e.
Select Use test bench to perform VHDL timing simulation and specify the
name of your design instance under Design instance name in test bench.
f.
Under the Simulation period, turn on Run simulation until all vector
stimuli are used.
g.
Under Test bench and simulation files, select your test bench file from your
folder. Click Add.
h.
Click OK.
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2.10.1.2 How to Use NativeLink to Run a ModelSim RTL Simulation
Figure 165. NativeLink Simulation Flow Diagram
Specify EDA Simulator &
Simulator Directory
Run RTL Functional or
Gate-Level Simulation
Does
Simulation Give
Expected Results?
Yes
No
Debug Design &
Make RTL Changes
Run Quartus Prime
Analysis and Elaboration
Define Control Signals Using
In-System Sources & Probes
Run Simulation
Does
Simulation Give
Expected Results?
Yes
No
Simulation Complete
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Complete the following steps to run an RTL functional simulation:
1.
Open your Quartus Prime project.
2.
On the Tools menu, select Run Simulation Tool, then select RTL Simulation or
Gate Level Simulation.
3. Run Quartus Prime Analysis and Elaboration and re-instantiate control signals that
you defined using the In-System Sources and Probe Editor. The In-System Sources
and Probe Editor can only access the pins of the device. Consequently, you must
route any signal that you want to observe to the top-level of your design.
4. To monitor additional signals, highlight the desired instances or nodes in
Instance, and right-click Add wave.
5. Select Simulate and then Run.
6.
Specify the simulation duration.
7.
Complete the following steps to restart the simulation:
a.
On the Simulate menu, select restart, then click ok.
This action clears the existing waves.
b.
Highlight run and select the appropriate options to run the simulation.
Related Links
Simulating the Transceiver Native PHY IP Core on page 324
2.10.1.3 How to Use NativeLink to Specify Third-Party RTL Simulators
The following figure illustrates the high-level steps for using the NativeLink with ThirdParty EDA RTL simulator.
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Figure 166. Using NativeLink with Third-Party Simulators
Specify EDA Simulator &
Simulator Directory
Perform
Functional Simulation
Does
Simulation Give
Expected Results?
Yes
No
Debug Design &
Make RTL Changes
Run Quartus Prime
Analysis and Elaboration
Start Simulator, Compile
Design and Testbench
Load Design &
Run Simulation
No
Does
Simulation Give
Expected Results?
Yes
Simulation Complete
Complete the following steps to specify the directory path and testbench settings for
your simulator:
Table 226.
1.
On the Tools menu, click Options, and then click EDA Tool Options.
2.
Browse to the directory for your simulator. The following table lists the directories
for supported third-party simulators:
Simulator Path
Simulator
Path
Mentor Graphics ModelSim
Mentor Graphics QuestaSim*
<drive>:\<simulator install path>\win32 (Windows)
/<simulator install path>/bin (Linux)
Synopsys VCS/VCS MX
/<simulator install path>/bin (Linux)
Cadence Incisive Enterprise
/<simulator install path>/tools/bin (Linux)
Aldec Active-HDL
<drive>:\<simulator install path>\bin (Windows)
continued...
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Simulator
Aldec Riviera-Pro
3.
Path
/<simulator install path>/bin (Linux)
On Assignments menu, click Settings.
4. In the Category list, under EDA Tool Settings, select Simulation.
5.
In the Tool name list, select your simulator.
6.
To enable your simulator, on the Tools menu, click Options and then click
License Setup . Make necessary changes for EDA tool licenses.
7.
Compile your design and testbench files.
8.
Load the design and run the simulation in the EDA tool.
To learn more about third-party simulators, click on the appropriate link below.
Related Links
•
Mentor Graphics ModelSim and QuestaSim Support
•
Synopsys VCS and VCS MX Support
•
Cadence Incisive Enterprise Simulator Support
•
Aldec Active-HDL and Riviera-Pro Support
2.10.2 Scripting IP Simulation
The Intel Quartus Prime software supports the use of scripts to automate simulation
processing in your preferred simulation environment. You can use your preferred
scripting methodology to control simulation.
Intel recommends the use of a version-independent top-level simulation script to
control design, testbench, and IP core simulation. Because Quartus Prime-generated
simulation file names may change.
You can use the ip-setup simulation utility to generate or regenerate underlying setup
scripts after any software or IP version upgrade or regeneration. Use of a top-level
script and ip-setup-simulation eliminates the requirement to manually update
simulation scripts.
2.10.2.1 Generating a Combined Simulator Setup Script
Platform Designer (Standard) system generation creates the interconnect between
components. It also generates files for synthesis and simulation, including the .spd
files necessary for the ip-setup-simulation utility.
The Intel Quartus Prime software provides utilities to help you generate and update IP
simulation scripts. You can use the ip-setup-simulation utility to generate a combined
simulator setup script, for all Intel FPGA IP in your design, for each supported
simulator. You can subsequently rerun ip-setup-simulation to automatically update the
combined script. Each simulator's combined script file contains a rudimentary template
that you can adapt for integration of the setup script into a top-level simulation script.
Related Links
Intel Quartus Prime Standard Edition Handbook Volume 3: Verification
Provides more information about the steps to generate top-level simulation script.
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2.10.3 Custom Simulation Flow
The custom simulation flow allows you to customize the simulation process for more
complex simulation requirements. This flow allows you to control the following aspects
of your design:
•
Component binding
•
Compilation order
•
Run commands
•
IP cores
•
Simulation library model files
The following figure illustrates the steps for custom flow simulation. If you use a
simulation script, you can automate some of the steps.
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Figure 167. Custom flow Simulation
Compile Sim Model Libs
Using Sim Lib Compiler
Start Simulator & Open
Quartus Prime Project
Compile Design, Testbench,
& Simulation Libraries
Load Design
& Run Simulation
Does
Simulation Give
Expected Results?
Yes
No
Debug Design &
Make RTL Changes
Compile Design, Testbench,
& Simulation Libraries
Load Design &
Run Simulation
Does
Simulation Give
Expected Results?
Yes
No
Simulation Complete
2.10.3.1 How to Use the Simulation Library Compiler
The Simulation Library Compiler compiles Intel simulation libraries for supported
simulation tools, and saves the simulation files in the output directory you specify.
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Note:
Because the ModelSim - Intel FPGA Edition software provides precompiled simulation
libraries, you do not have to compile simulation libraries if you are using the software.
Complete the following steps to compile the simulation model libraries using the
Simulation Library Compiler:
1. On the Tools menu, click Launch Simulation Library Compiler.
2. Under EDA simulation tool, for the Tool name, select your simulation tool.
3. Under Executable location, browse to the location of the simulation tool you
specified. You must specify this location before you can run the EDA Simulation
Library Compiler.
4. Under Library families, select one or more family names and move them to the
Selected families list.
5.
Under Library language, select Verilog, VHDL, or both.
6. In the Output directory field, specify a location to store the compiled libraries.
7.
Click Start Compilation.
Complete the following steps to add the simulation files to your project:
1. On the Assignments menu, click Settings.
2.
In the Category list, select Files.
3. Click Browse to open the Select File dialog box and select one or more files in
the Files list to add to your project.
4. Click Open, and then Add to add the selected file(s) to your project.
5.
Click OK to close the Settings dialog box.
Related Links
•
Preparing for EDA Simulation
•
Intel FPGA Simulation Models
2.10.3.2 Custom Simulation Scripts
You can automate simulations by creating customized scripts. You can generate scripts
manually. In addition, you can use NativeLink to generate a simulation script as a
template and then make the necessary changes. The following table shows a list of
script directories NativeLink generates.
Table 227.
Custom Simulation Scripts for Third Party RTL Simulation
Simulator
Simulation File
Use
Mentor Graphics
ModelSim or
QuestaSim
/simulation/ modelsim/
modelsim_setup.do
Or
mentor/msim_setup.tcl
Source directly with your simulator. Run do msim_setup.tcl,
followed by ld_debug. If you have more than one IP, each IP has
a dedicated msim_setup.tcl file. Make sure that you combine
all the files included in the msim_setup.tcl files into one
common msim_setup.tcl file.
Aldec Riviera Pro
/simulation/ aldec/
rivierapro_setup.tcl
Source directly with your simulator
.
continued...
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Simulator
Simulation File
Use
Synopsys VCS
/simulation/synopsys/vcs/
vcs_setup.sh
Add your testbench file name to this file to pass the testbench file
to VCS using the –file option. If you specify a testbench file for
NativeLink and do not choose to simulate, NativeLink generates a
script that runs VCS.
Synopsys VCS MX
/simulation/synopsys/
vcsmx/vcsmx_setup.sh
Run this script at the command line using quartus_sh–t
<script>. Any testbench you specify with NativeLink is included
in this script.
Cadence Incisive
(NCSim)
/simulation/cadence/
ncsim_setup.sh
Run this script at the command line using quartus_sh –t
<script>. Any testbench you specify with NativeLink is included in
this script.
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3 PLLs and Clock Networks
This chapter describes the transceiver phase locked loops (PLLs), internal clocking
architecture, and the clocking options for the transceiver and the FPGA fabric
interface.
As shown in the following figure, transceiver banks can have either three or six
transceiver channels. For every three channels, you get one advanced transmit (ATX)
PLL, one fractional PLL (fPLL), and one Master clock generation block (CGB). Refer to
the Device Transceiver Layout section to identify which devices have three channel
transceiver banks.
The Arria 10 transceiver clocking architecture supports both bonded and non-bonded
transceiver channel configurations. Channel bonding is used to minimize the clock
skew between multiple transceiver channels. For Arria 10 transceivers, the term
bonding can refer to PMA bonding as well as PMA and PCS bonding. Refer to the
Channel Bonding section for more details.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
3 PLLs and Clock Networks
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Figure 168. Arria 10 PLLs and Clock Networks
x1 Clock Lines
CH2
x6 Clock Lines
xN Clock Lines
Transceiver
Bank
CDR
Local CGB
fPLL
CH1
CH0
CDR/CMU
Local CGB
ATX
PLL
CDR
Master
CGB
Local CGB
Transceiver
Bank
CH5
CDR
Local CGB
fPLL
CH4
CH3
CDR/CMU
Local CGB
ATX
PLL
CDR
Master
CGB
Local CGB
CH2
CDR
Local CGB
fPLL
CH1
CH0
CDR/CMU
Local CGB
ATX
PLL
CDR
Master
CGB
Local CGB
Related Links
•
Channel Bonding on page 377
•
Device Transceiver Layout on page 8
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•
Using PLLs and Clock Networks on page 386
Information on how to use PLL IP to implement bonded and non-bonded
transceiver designs.
3.1 PLLs
Table 228.
Transmit PLLs in Arria 10 Devices
PLL Type
Characteristics
Advanced Transmit (ATX) PLL
•
•
•
•
Fractional PLL (fPLL)
Clock Multiplier Unit (CMU) PLL or Channel PLL
(49)
Best jitter performance
LC tank based voltage controlled oscillator (VCO)
Supports fractional synthesis mode (in cascade mode
only)
Used for both bonded and non-bonded channel
configurations
•
•
•
Ring oscillator based VCO
Supports fractional synthesis mode
Used for both bonded and non-bonded channel
configurations
•
•
Ring oscillator based VCO
Used as an additional clock source for non-bonded
applications
Figure 169. Transmit PLL Recommendation Based on Data Rates
Related Links
Refer to Using PLL and Clock Networks section for guidelines and usage on page 386
3.1.1 Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs
ATX PLL-to-ATX PLL Spacing Guidelines
For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs
apart (skip 6).
(49)
The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmit PLL or as a
clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can
only be used as a CDR.
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For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz) and drive GX channels, they
must be placed 4 ATX PLLs apart (skip 3).
For ATX PLL VCO frequencies between 11.4 GHz and 14.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz) and drive GT channels, they
must be placed 3 ATX PLLs apart (skip 2).
For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4
ATX PLL apart (skip 3).
Note:
If these spacing rules are violated, Intel Quartus Prime issues a critical warning.
When two ATX PLLs are being used, and you meet the following two conditions in your
applications:
•
One of the ATX PLL re-calibration process is triggered.
•
The other channel (that is clocked by another ATX PLL) is in data transmission
mode.
You must place the two ATX PLLs 7 ATX PLLs apart (skip 6). ATX PLLs between the 2
active ATX PLLs should not be used.
ATX PLL-to-fPLL Spacing Guidelines
If you are using both ATX PLL and fPLL, and you meet the below two conditions in
your applications:
•
When ATX PLL VCO frequency and fPLL VCO frequency is within 50MHz.
•
ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
The ATX PLL and fPLL must be separated at least by 1 ATX PLL in between.
If you are using both ATX PLL and fPLL, and you meet the below two conditions in
your applications:
•
fPLL user re-calibration process is triggered.
•
ATX PLL is used to drive protocol which includes OTU2, OTU2e, SDH/Sonet_9953/
OC192/STM64, 10G GPON or protocol that has jitter integration start range
<1MHz and data rate > 3Gbps.
then the ATX PLL and fPLL must be separated at least by 1 ATX PLL in between
(regardless of the ATX PLL and fPLL VCO frequency offset).
3.1.2 ATX PLL
The ATX PLL contains LC tank-based voltage controlled oscillators (VCOs). These LC
VCOs have different frequency ranges to support a continuous range of operation.
When driving the Transceiver directly, the ATX PLL only supports the integer mode. In
cascade mode, the ATX PLL only supports fractional mode.
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Figure 170. ATX PLL Block Diagram
Lock
Detector
pll_locked
2
CP &
LF
L Counter
VCO
2
Refclk
Multiplexer
Dedicated reference clock pin
Reference clock network
Receiver input pin
Output of another PLL with PLL cascading
Global clock or core clock
Input reference
clock
/2
Up
N Counter
refclk
Down
PFD
fbclk
M Counter
Delta Sigma
Modulator (1)
Note: (1) The Delta Sigma Modulator is enaged only when the ATX PLL is used in fractional mode.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
•
Dedicated reference clock pin
•
Reference clock network
•
Receiver input pin
•
Output of another PLL with PLL cascading
•
Global clock or the core clock network
The input reference clock to the dedicated reference clock pin is a differential signal.
Intel recommends using the dedicated reference clock pin as the input reference clock
source for the best jitter performance. The input reference clock must be stable and
free-running at device power-up for proper PLL operation and PLL calibration. If the
reference clock is not available at device power-up, then you must recalibrate the PLL
when the reference clock is available.
Note:
Sourcing reference clock from a cascaded PLL output, global clock or core clock
network will introduce additional jitter to the ATX PLL ouput. Refer to KDB "How do I
compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL
reference clock?" for more details.
The ATX PLL calibration is clocked by the CLKUSR clock which must be stable and
available for calibration to proceed. Refer to the Calibration section for more details
about the CLKUSR clock.
Reference Clock Multiplexer
The reference clock (refclk) multiplexer selects the reference clock to the PLL from
the various reference clock sources available.
N Counter
The N counter divides the refclk mux's output. The division factors supported are 1,
2, 4, and 8.
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Phase Frequency Detector (PFD)
The reference clock(refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block are supplied as
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the refclk and fbclk inputs. It is used to align the refclk signal at the
output of the N counter to the feedback clock (fbclk) signal. The PFD generates an
"Up" signal when the reference clock's falling edge occurs before the feedback clock's
falling edge. Conversely, the PFD generates a "Down" signal when the feedback clock's
falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter
The PFD output is used by the charge pump and loop filter (CP and LF) to generate a
control voltage for the VCO. The charge pump translates the "Up" or "Down" pulses
from the PFD into current pulses. The current pulses are filtered through a low pass
filter into a control voltage that drives the VCO frequency. The charge pump, loop
filter, and VCO settings determine the bandwidth of the ATX PLL.
Lock Detector
The lock detector block indicates when the reference clock and the feedback clock are
phase aligned. The lock detector generates an active high pll_locked signal to
indicate that the PLL is locked to its input reference clock.
Voltage Controlled Oscillator
The voltage controlled oscillator (VCO) used in the ATX PLL is LC tank based. The
output of charge pump and loop filter serves as an input to the VCO. The output
frequency of the VCO depends on the input control voltage. The output frequency is
adjusted based on the output voltage of the charge pump and loop filter.
L Counter
The L counter divides the differential clocks generated by the ATX PLL. The L counter
is not in the feedback path of the PLL.
M Counter
The M counter's output is the same frequency as the N counter's output. The VCO
frequency is governed by the equation:
VCO freq = 2 * M * input reference clock/N
An additional divider divides the high speed serial clock output of the VCO by 2 before
it reaches the M counter.
The M counter supports division factors in a continuous range from 8 to 127 in integer
frequency synthesis mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The fractional mode is only supported when the ATX PLL is configured as a cascade
source for OTN and SDI protocols. The delta sigma modulator is used in fractional
mode. It modulates the M counter divide value over time so that the PLL can perform
fractional frequency synthesis. In fractional mode, the M value is as follows: .
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M (integer) + K/2^32, where K is the Fractional multiply factor (K) in the ATX PLL IP
Parameter Editor
K legal values are 1 through 2^32-1 and can only be manually entered in the ATX PLL
IP Parameter Editor in Quartus Prime software.
The output frequencies can be exact when the ATX PLL is configured in fractional
mode. Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 Ghz
VCO frequency, not all desired fractional values can be achieved exactly. The lock
signal is not available, when configured in fractional mode in k-precision mode (K <
0.1 or K > 0.9).
Multiple Reconfiguration Profiles
Under the ATX PLL IP Parameter Editor Dynamic Reconfiguration tab, in the
Configuration Profiles section, multiple reconfiguration profiles can be enabled. This
allows to create, store, and analyze the parameter settings for multiple configurations
or profiles of the ATX PLL IP.
The ATX PLL IP GUI can generate configuration files (SystemVerilog, C header or MIF)
for a given configuration. With the multi reconfiguration profile options enabled, the
ATX PLL IP Parameter Editor can produce configuration files for all of the profiles
simultaneously. In addition, by enabling the reduced reconfiguration files generation,
the IP Parameter Editor will produce a reduced configuration file by internally
comparing the corresponding parameter settings of all the profiles and identifying the
differences.
Embedded Reconfiguration Streamer
This option enables a push-button flow to reconfigure between multiple configurations
or profiles. Here are the steps to follow:
1.
Multiple reconfiguration profiles creation
•
In the ATX PLL IP GUI, create configurations for each profiles using the multiprofile feature.
2. Reconfiguration report files
•
3.
4.
The IP GUI generates the reconfiguration report files that contain parameter
and register settings for all the selected profiles. If the reduced reconfiguration
files option is selected, the IP parameter editor will compare the settings
between the profiles and generate reduced report files which only contain the
differences.
Select “Enable embedded reconfiguration streamer logic” in the GUI to generate
the following:
•
Necessary HDL files to perform streaming.
•
The individual report files for each profile, an SystemVerilog package file with
configuration data for all the profiles concatenated together which is used to
initialize the configuration ROM
Generate the ATX PLL IP and control the reconfiguration streamer using the AVMM
master.
Related Links
•
Calibration on page 547
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•
How do I compensate for the jitter of PLL cascading or non-dedicated clock path
for Arria 10 PLL reference clock?
3.1.2.1 Instantiating the ATX PLL IP Core
The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the
hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3.
In IP Catalog, under Library ➤ Transceiver PLL ➤ , select Arria 10
Transceiver ATX PLL and click Add.
4.
In the New IP Instance dialog box, provide the IP instance name.
5.
Select the Arria 10 device family.
6.
Select the appropriate device and click OK.
The ATX PLL IP core Parameter Editor window opens.
3.1.2.2 ATX PLL IP Core
Table 229.
ATX PLL Configuration Options, Parameters, and Settings
Parameter
Message level for rule violations
Protocol mode
Range
Description
Error
Warning
Specifies the messaging level to use for parameter rule
violations.
• Error—Causes all rule violations to prevent IP
generation.
• Warning—Displays all rule violations as warnings and will
allow IP generation in spite of violations.
Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
UPI TX
SAS TX
Bandwidth
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all other
parameters for your protocol.
Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Number of PLL reference clocks
1 to 5
Specifies the number of input reference clocks for the ATX
PLL.
You can use this parameter for data rate reconfiguration.
Selected reference clock source
0 to 4
Specifies the initially selected reference clock input to the
ATX PLL.
Primary PLL clock output buffer
GX clock output
buffer
GT clock output
buffer
Specifies which PLL output is active initially.
• If GX is selected, turn ON "Enable PLL GX clock
output port".
• If GT is selected, turn ON “Enable PLL GT clock
output port".
On/Off
Enables the GX output port which feeds x1 clock lines.
Enable PLL GX clock output port
(50)
continued...
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Parameter
Range
Description
You must select this parameter for PLL output frequency
less than 8.7 GHz, or if you intend to reconfigure the PLL to
a frequency below 8.7 GHz.
Turn ON this port if GX is selected in the "Primary PLL
clock output buffer".
Enable PCIe clock output port
On/Off
Exposes the pll_pcie_clk port used for PCI Express.
The port should be connected to the pipe_hclk_input
port.
Enable ATX to FPLL cascade clock
output port
On/Off
Enables the ATX to FPLL cascade clock output port.
Enable fref and clklow port(51).
On/Off
Enables fref and clklow ports for external lock detector.
PLL output frequency
Refer to Intel
Arria 10 Device
Datasheet .
Use this parameter to specify the target output frequency
for the PLL.
PLL integer reference clock
frequency
Refer to the GUI
Selects the input reference clock frequency for the PLL.
Multiply factor (M-Counter)
Read only
For
OTN_cascade or
SDI_cascade,
refer to the GUI.
Displays the M-counter value.
Specifies the M-counter value (In SDI_cascade or
OTN_cascade Protocol mode only).
Divide factor (N-Counter)
Read only
For
SDI_cascade or
OTN_cascade,
refer to the GUI.
Displays the N-counter value.
For SDI_cascade or OTN_cascade, refer to the GUI.
Divide factor (L-Counter)
Read only
Displays the L-counter value.
Predivide factor (L-Cascade
Predivider)
Refer to the GUI
Specifies the L-cascade predivider value. This value must be
2 for a VCO frequency greater than 10.46 GHz and 1 for a
VCO frequency less than 10.46GHz. (In SDI_cascade or
OTN_cascade Protocol mode only).
Fractional multiply factor (K)
Read only
Displays the actual K-counter value. This parameter is only
available in fractional mode.
Table 230.
ATX PLL—Master Clock Generation Block Parameters and Settings
Parameter
Include Master Clock Generation
Block (52)
Range
On/Off
Description
When enabled, includes a master CGB as a part of the ATX
PLL IP core. The PLL output drives the Master CGB.
continued...
(50)
You can enable both the GX clock output port and the GT clock output port. However, only one
port can be in operation at any given time. You can switch between the two ports using PLL
reconfiguration.
(51)
The fPLL fref and clklow signals should only be used with the Intel external soft lock
detection logic.
(52)
Manually enable the MCGB for bonding applications.
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Parameter
Range
Description
This is used for x6/xN bonded and non-bonded modes.
Clock division factor
1, 2, 4, 8
Divides the master CGB clock input before generating
bonding clocks.
Enable x6/xN non-bonded highspeed clock output port
On/Off
Enables the master CGB serial clock output port used for
x6/xN non-bonded modes.
Enable PCIe clock switch interface
On/Off
Enables the control signals for the PCIe clock switch
circuitry. Used for PCIe clock rate switching.
0, 1
Auxiliary input is used to implement the PCIe Gen3
protocol.
Number of auxiliary MCGB clock
input ports
MCGB input clock frequency
Read only
Displays the master CGB's input clock frequency.
MCGB output data rate.
Read only
Displays the master CGB's output data rate.
Enable bonding clock output ports
On/Off
Enables the tx_bonding_clocks output ports of the
master CGB used for channel bonding.
This option should be turned ON for bonded designs.
Enable feedback compensation
bonding
On/Off
Enables this setting when using feedback compensation
bonding. For more details about feedback compensation
bonding, refer to the PLL Feedback Compensation Bonding
section later in the document.
8, 10, 16, 20,
32, 40, 64
Specifies PMA-PCS interface width.
Match this value with the PMA interface width selected for
the Native PHY IP core. You must select a proper value for
generating bonding clocks for the Native PHY IP core.
PMA interface width
Table 231.
ATX PLL—Dynamic Reconfiguration
Parameter
Range
Description
Enable reconfiguration
On/Off
Enables the PLL reconfiguration interface. Enables the
simulation models and adds Avalon compliant ports for
reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off
When you turn on this option, the Transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave
interface for dynamic reconfiguration. The ADME can access
the reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On/Off
When enabled, the reconfig_waitrequest will not
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status will be reflected in a soft status
register bit. (Only available if "Enable control and status
registers feature" is enabled).
Enable capability registers
On/Off
Enables capability registers that provide high-level
information about the ATX PLL's configuration.
Set user-defined IP identifier
Enable control and status registers
Configuration file prefix
User-defined
Sets a user-defined numeric identifier that can be read from
the user_identifier offset when the capability registers
are enabled.
On/Off
Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Enter the prefix name for the configuration files to be
generated.
continued...
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Parameter
Range
Description
Generate SystemVerilog package
file
On/Off
Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
Generate C header file
On/Off
Generates a C header file containing all relevant parameters
used by the PLL.
Enable multiple reconfiguration
profiles
On/Off
Enables multiple configuration profiles to be stored.
Enable embedded reconfiguration
streamer
On/Off
Enables embedded reconfiguration streamer which
automates the dynamic reconfiguration process between
multiple predefined configuration profiles.
Generate reduced reconfiguration
files
On/Off
When enabled, the IP generates reconfiguration report files
containing only the setting differences between the multiple
reconfiguration profiles
Number of reconfiguration profiles
1 to 8
Specifies the number of reconfiguration profiles
Store current configuration to
profile
0 to 7
Specifies which configuration profile to modify (store, load,
clear or refresh) when clicking the corresponding action
button.
Generate MIF (Memory Initialize
File)
Table 232.
Generates a MIF file which contains the current
configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
ATX PLL—Generation Options
Parameter
Generate parameter
documentation file
Table 233.
On/Off
Range
Description
On/Off
Generates a .csv file which contains descriptions of ATX PLL
IP core parameters and values.
ATX PLL IP Core Ports
Port
Direction
Clock Domain
pll_powerdown
Input
Asynchronous
pll_refclk0
Input
N/A
Reference clock input port 0.
There are a total of five reference clock
input ports. The number of reference
clock ports available depends on the
Number of PLL reference clocks
parameter.
pll_refclk1
Input
N/A
Reference clock input port 1.
pll_refclk2
Input
N/A
Reference clock input port 2.
pll_refclk3
Input
N/A
Reference clock input port 3.
pll_refclk4
Input
N/A
Reference clock input port 4.
Output
N/A
High speed serial clock output port for
GX channels. Represents the x1 clock
network.
tx_serial_clk
Description
Resets the PLL when asserted high.
Needs to be connected to a
dynamically controlled signal (the
Transceiver PHY Reset Controller
pll_powerdown output if using this
Intel FPGA IP).
continued...
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Port
Direction
Clock Domain
Description
tx_serial_clk_gt
Output
N/A
High speed serial clock output port for
GT channels. Represents the GT clock
network.
pll_locked
Output
Asynchronous
pll_pcie_clk
Output
N/A
Used for PCIe.
reconfig_clk0
Input
N/A
Optional Avalon interface clock. Used
for PLL reconfiguration. The
reconfiguration ports appear only if the
Enable Reconfiguration parameter is
selected in the PLL IP Core GUI. When
this parameter is not selected, the
ports are set to OFF internally.
reconfig_reset0
Input
reconfig_clk0
Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0
Input
reconfig_clk0
Active high write enable signal.
reconfig_read0
Input
reconfig_clk0
Active high read enable signal.
reconfig_address0[9:0]
Input
reconfig_clk0
10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0]
Input
reconfig_clk0
32-bit data bus. Carries the write data
to the specified address.
reconfig_readdata0[31:0]
Output
reconfig_clk0
32-bit data bus. Carries the read data
from the specified address.
reconfig_waitrequest0
Output
reconfig_clk0
Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy
Output
Asynchronous
Status signal which is asserted high
when PLL calibration is in progress.
Active high status signal which
indicates if the PLL is locked.
(53)
OR this signal with tx_cal_busy port
before connecting to the reset
controller IP.
mcgb_rst
Input
Asynchronous
Master CGB reset control.
Deassert this reset at the same time as
pll_powerdown .
mcgb_aux_clk0
Input
N/A
Used for PCIe implementation to switch
between fPLL and ATX PLL during link
speed negotiation.
tx_bonding_clocks[5:0]
Output
N/A
Optional 6-bit bus which carries the
low speed parallel clock outputs from
the master CGB. Each transceiver
channel in a bonded group has this 6bit bus.
Used for channel bonding, and
represents the x6/xN clock network.
mcgb_serial_clk
Output
N/A
High speed serial clock output for
x6/xN non-bonded configurations.
continued...
(53)
Connect this clock to hclk in PCIe applications.
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Port
Direction
Clock Domain
Description
Input
Asynchronous
2-bit rate switch control input used for
PCIe protocol implementation.
pcie_sw_done[1:0]
Output
Asynchronous
2-bit rate switch status output used for
PCIe protocol implementation.
atx_to_fpll_cascade_clk
Output
N/A
The ATX PLL output clock is used to
drive fPLL reference clock input (only
available in SDI_cascade or
OTN_cascade protocol mode).
Output
N/A
Clklow output for external lock
detection. It can be exposed by
selecting the Enable clklow and fref
port
Output
N/A
Fref output for external lock detection.
It can be exposed by selecting the
Enable clklow and fref port.
pcie_sw[1:0]
ext_lock_detect_clklow
ext_lock_detect_fref
(54)
(54)
Related Links
•
Calibration on page 28
•
Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon specification.
Refer to the Avalon specification for more details about these ports.
•
Intel Arria 10 Device Datasheet
Refer to the Intel Arria 10 Device Datasheet for more details about the PLL
output frequency range.
•
Reconfiguration Interface and Dynamic Reconfiguration on page 484
•
Reconfiguring Channel and PLL Blocks on page 484
•
Steps to Perform Dynamic Reconfiguration on page 498
•
Intel Arria 10 device fPLL reports an unlocked condition
3.1.3 fPLL
There are two fPLLs in each transceiver bank with six channels (one located at the top
and the other at the bottom of the bank). Transceiver banks with three channels have
only one fPLL.
Figure 171. fPLL Block Diagram
Refclk
Multiplexer
Dedicated Reference Clock Pin
Reference Clock Network
Receiver Input Pin
Output of Another PLL with PLL Cascading
Global Clock or Core Clock
Input
Reference
Clock
L Counter
/1, 2, 4, 8
N Counter
refclk
PFD
Up
Down
Charge
Pump and
Loop Filter
VCO
M Counter
/2
Delta Sigma
Modulator
fbclk
/2
(54)
C Counter
The fPLL fref and clklow signals should only be used with the Intel external soft lock
detection logic.
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When in core mode, for the fPLL to generate output clocks with a fixed frequency and
phase relation to an input reference clock, the Enable phase alignment option must
be selected. In the fractional frequency mode, the fPLL supports data rates from 1
Gbps to 12.5 Gbps.
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
•
Dedicated reference clock pin
•
Reference clock network
•
Receiver input pin
•
Output of another PLL with PLL cascading
•
Global clock or the core clock network
The input reference clock is a differential signal. Intel recommends using the
dedicated reference clock pin as the input reference clock source for best jitter
performance. For protocol jitter compliance at data rates > 10 Gbps, Intel
recommends using the dedicated reference clock pin in the same triplet with the fPLL
as the input reference clock source.The input reference clock must be stable and freerunning at device power-up for proper PLL operation. If the reference clock is not
available at device power-up, then you must recalibrate the PLL when the reference
clock is available.
Note:
Sourcing reference clock from a cascaded PLL output, global clock or core clock
network will introduce additional jitter to the fPLL ouput. Refer to KDB "How do I
compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL
reference clock?" for more details.
The fPLL calibration is clocked by the CLKUSR clock, which must be stable and
available for the calibration to proceed. Refer to the Calibration on page 547 section
for details about PLL calibration and CLKUSR clock.
Reference Clock Multiplexer
The refclk mux selects the reference clock to the PLL from the various available
reference clock sources.
N Counter
The N counter divides the reference clock (refclk) mux's output. The N counter
division helps lower the loop bandwidth or reduce the frequency within the phase
frequency detector's (PFD) operating range. The N counter supports division factors
from 1 to 32.
Phase Frequency Detector
The reference clock (refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block are supplied as an
inputs to the PFD. The output of the PFD is proportional to the phase difference
between the refclk and fbclk inputs. The PFD aligns the fbclk to the refclk.
The PFD generates an "Up" signal when the reference clock's falling edge occurs
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before the feedback clock's falling edge. Conversely, the PFD generates a "Down"
signal when the feedback clock's falling edge occurs before the reference clock's falling
edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control
voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a
control voltage that drives the VCO frequency.
Voltage Controlled Oscillator
The fPLL has a ring oscillator based VCO. The VCO transforms the input control
voltage into an adjustable frequency clock.
VCO freq = 2 * M * Input reference clock/N. (N and M are the N counter and M
counter division factors.)
L Counter
The L counter divides the VCO's clock output. When the fPLL acts as a transmit PLL,
the output of the L counter drives the clock generation block (CGB) and the TX PMA
via the X1 clock lines.
M Counter
The M counter divides the VCO's clock output. The M counter can select any VCO
phase. The outputs of the M counter and N counter have same frequency. M counter
range is 8 to 127 in integer mode and 11 to 123 in fractional mode.
Delta Sigma Modulator
The delta sigma modulator is used in fractional mode. It modulates the M counter
divide value over time so that the PLL can perform fractional frequency synthesis.
In fractional mode, the M value is as follows:
M (integer) + K/2^32, where K is the fractional multiply factor (K) in the fPLL IP
Parameter Editor. The legal values of K are greater than 1% and less than 99% of the
full range of 2^32 and can only be manually entered in the fPLL IP Parameter Editor in
the Quartus Prime software.
The output frequencies can be exact when the fPLL is configured in fractional mode.
Due to the K value 32-bit resolution, translating to 1.63 Hz step for a 7 GHz VCO
frequency, not all desired fractional values can be achieved exactly. The lock signal is
not available, when configured in fractional mode in the K-precision mode (K < 0.1 or
K > 0.9).
C Counter
The fPLL C counter division factors range from 1 to 512.
Dynamic Phase Shift
The dynamic phase shift block allows you to adjust the phase of the C counters in user
mode. In fractional mode, dynamic phase shift is only available for the C counters.
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Latency
The C counters can be configured to select any VCO phase and a delay of up to 128
clock cycles. The selected VCO phase can be changed dynamically.
Related Links
•
Calibration on page 547
•
Calibration on page 547
Details about PLL calibration
•
How do I compensate for the jitter of PLL cascading or non-dedicated clock path
for Arria 10 PLL reference clock?
3.1.3.1 Instantiating the fPLL IP Core
The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One
instance of the fPLL IP core represents one fPLL in the hardware.
1. Open the Quartus Prime software.
2. Click Tools ➤ IP Catalog.
3. In IP Catalog, under Library ➤ Transceiver PLL , select Arria 10 Transceiver
fPLL IP core and click Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The fPLL IP core Parameter Editor window opens.
3.1.3.2 fPLL IP Core
Table 234.
fPLL IP Core Configuration Options, Parameters, and Settings
Parameters
fPLL Mode
Protocol Mode
Enable fractional mode
Range
Description
Core
Cascade Source
Transceiver
Specifies the fPLL mode of operation.
Select Core to use fPLL as a general purpose PLL to drive
the FPGA core clock network.
Select Cascade Source to connect an fPLL to another PLL
as a cascading source.
Select Transceiver to use an fPLL as a transmit PLL for the
transceiver block.
Basic
PCIe* Gen1
PCIe Gen2
PCIe Gen3
SDI_cascade
OTN_cascade
SDI_direct
SATA TX
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all parameters
for your protocol.
On/Off
Enables the fractional frequency mode.
This enables the PLL to output frequencies which are not
integral multiples of the input reference clock.
continued...
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Parameters
Range
Description
Enable physical output clock
parameters
On/Off
Selecting this option allows you to manually specify M, N, C
and L counter values.
Enable clklow and fref ports(55)
On/Off
Enables fref and clklow clock ports for external lock
detector. In Transceiver mode when "enable fractional
mode" and "SDI_direct" prot_mode are selected,
pll_locked port is not available and user can create
external lock detector using fref and clklow clock ports.
Refer to the GUI
Specifies the desired PLL input reference clock frequency.
Desired Reference clock frequency
Actual reference clock frequency
Read-only
Displays the actual PLL input reference clock frequency.
Number of PLL reference clocks
1 to 5
Specify the number of input reference clocks for the fPLL.
New parameter: Selected reference
clock source
0 to 4
Specifies the initially selected reference clock input to the
fPLL.
Bandwidth
Low
Medium
High
Operation mode
Multiply factor (M-counter)
Direct
Feedback
compensation
bonding
8 to 127
(integer mode)
11 to 123
(fractional
mode)
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Specifies the feedback operation mode for the fPLL.
Specifies the multiply factor (M-counter).
Divide factor (N-counter)
1 to 31
Specifies the divide factor (N-counter).
Divide factor (L-counter)
1, 2, 4, 8
Specifies the divide factor (L-counter).
Divide factor (K-counter)
User defined
Specifies the divide factor (K-counter).
PLL output frequency
Read-only
Displays the target output frequency for the PLL.
PLL Datarate
Read-only
Displays the PLL datarate.
Table 235.
fPLL—Master Clock Generation Block Parameters and Settings
Parameters
Include Master Clock Generation
Block
Clock division factor
Range
Description
On/Off
When enabled, includes a master CGB as a part of the fPLL
IP core. The PLL output drives the master CGB.
This is used for x6/xN bonded and non-bonded modes.
1, 2, 4, 8
Divides the master CGB clock input before generating
bonding clocks.
Enable x6/xN non-bonded highspeed clock output port
On/Off
Enables the master CGB serial clock output port used for
x6/xN non-bonded modes.
Enable PCIe clock switch interface
On/Off
Enables the control signals used for PCIe clock switch
circuitry.
MCGB input clock frequency
Read only
Displays the master CGB’s required input clock frequency.
You cannot set this parameter.
continued...
(55)
The fPLL fref and clklow signals should only be used with the Intel external soft lock
detection logic.
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Parameters
MCGB output data rate
Range
Description
Read only
Displays the master CGB’s output data rate. You cannot set
this parameter.
This value is calculated based on MCGB input clock
frequency and MCGB clock division factor.
Enable bonding clock output ports
On/Off
Enables the tx_bonding_clocks output ports of the
Master CGB used for channel bonding.
You must enable this parameter for bonded designs.
Enable feedback compensation
bonding
On/Off
Enables the feedback output path of the master CGB used
for feedback compensation bonding. When enabled, the
feedback connections are automatically handled by the PLL
IP.
8, 10, 16, 20,
32, 40, 64
Specifies the PMA-PCS interface width.
Match this value with the PMA interface width selected for
the Native PHY IP core. You must select a proper value for
generating bonding clocks for the Native PHY IP core.
PMA interface width
Table 236.
fPLL—Dynamic Reconfiguration Parameters and Settings
Parameter
Range
Description
Enable reconfiguration
On/Off
Enables the PLL reconfiguration interface. Enables the
simulation models and adds more ports for reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off
When you turn this option ON, the transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint
(ADME) that connects internally to the Avalon-MM slave
interface for dynamic reconfiguration. The ADME can access
the reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On/Off
When enabled, the reconfig_waitrequest will not
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status will be reflected in a soft status
register bit. (Only available if "Enable control and status
registers feature" is enabled).
Enable capability registers
On/Off
Enables capability registers that provide high-level
information about the fPLL's configuration.
Set user-defined IP identifier
Enable control and status registers
Sets a user-defined numeric identifier that can be read from
the user_identifier offset when the capability registers
are enabled.
On/Off
Configuration file prefix
Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Enter the prefix name for the configuration files to be
generated.
Generate SystemVerilog package
file
On/Off
Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
Generate C header file
On/Off
Generates a C header file containing all relevant parameters
used by the PLL.
Generate MIF (Memory Initialize
File)
On/Off
Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
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Table 237.
Clock Switchover (between Dynamic Reconfiguration and General Options)
Clock Switchover Parameter
Range
Description
Create a second input clock
pllrefclk1
On/Off
Turn on this parameter to have a
backup clock attached to your fPLL that
can switch with your original reference
clock
Second Reference Clock Frequency
User Defined
Specifies the second reference clock
frequency for fPLL
Switchover Mode
Automatic Switchover
Specifies how Input frequency
switchover will be handled. Automatic
Switchover will use built in circuitry to
detect if one of your input clocks has
stopped toggling and switch to the
other.
Manual Switchover will create an
EXTSWITCH signal which can be used
to manually switch the clock by
asserting high for at least 3 cycles.
Automatic Switchover with Manual
Override will perform act as Automatic
Switchover until the EXTSWITCH goes
high, in which case it will switch and
ignore any automatic switches as long
as EXTSWITCH stays high
Manual Switchover
Automatic Switchover with Manual
Override
Switchover Delays
0 to 7
Adds a specific amount of cycle delay
to the Switchover Process.
Create an active_clk signal to
indicate the input clock in use
On/Off
This parameter creates an output that
indicates which input clock is currently
in use by the PLL. Low indicates
refclk, High indicates refclk1.
Create a clkbad signal for each of
the input clocks
On/Off
This parameter creates two clkbad
outputs, one for each input clock. Low
indicates the CLK is working, High
indicates the CLK is not working.
Table 238.
fPLL - Generation Options
Parameter
Generates parameter
documentation file
Table 239.
Direction
On/Off
Description
Generates a .csv file that contains descriptions of all the
fPLL parameters and values.
fPLL IP Core Ports
Port
Direction
Clock Domain
Description
pll_powerdown
input
Asynchronous
pll_refclk0
input
N/A
Reference clock input port 0.
There are five reference clock input
ports. The number of reference clock
ports available depends on the
Number of PLL reference clocks
parameter.
pll_refclk1
input
N/A
Reference clock input port 1.
Resets the PLL when asserted high.
Needs to be connected to a
dynamically controlled signal (the
Transceiver PHY Reset Controller
pll_powerdown output if using this
Intel FPGA IP).
continued...
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Port
Direction
Clock Domain
pll_refclk2
input
N/A
Reference clock input port 2.
pll_refclk3
input
N/A
Reference clock input port 3.
pll_refclk4
input
N/A
Reference clock input port 4.
tx_serial_clk
output
N/A
High speed serial clock output port
for GX channels. Represents the x1
clock network.
pll_locked
output
Asynchronous
Active high status signal which
indicates if PLL is locked.
hssi_pll_cascade_clk
output
N/A
fPLL cascade clock output port
pll_pcie_clk
output
N/A
Used for PCIe.
reconfig_clk0
input
N/A
Optional Avalon interface clock. Used
for PLL reconfiguration.
reconfig_reset0
input
reconfig_clk0
Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0
input
reconfig_clk0
Active high write enable signal.
reconfig_read0
input
reconfig_clk0
Active high read enable signal.
reconfig_address0[9:0]
input
reconfig_clk0
10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0]
input
reconfig_clk0
32-bit data bus. Carries the write
data to the specified address.
reconfig_readdata0[31:0]
output
reconfig_clk0
32-bit data bus. Carries the read
data from the specified address.
reconfig_waitrequest0
output
reconfig_clk0
Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy
output
Asynchronous
Status signal which is asserted high
when PLL calibration is in progress.
Perform logical OR with this signal
and the tx_cal_busy port on the
reset controller IP.
mcgb_rst
input
Asynchronous
Master CGB reset control.
Deassert this reset at the same time
as pll_powerdown .
mcgb_aux_clk0
input
N/A
Used for PCIe to switch between
fPLL/ATX PLL during link speed
negotiation.
tx_bonding_clocks[5:0]
output
N/A
Optional 6-bit bus which carries the
low speed parallel clock outputs from
the Master CGB.
Used for channel bonding, and
represents the x6/xN clock network.
mcgb_serial_clk
output
N/A
High speed serial clock output for
x6/xN non-bonded configurations.
input
Asynchronous
2-bit rate switch control input used
for PCIe protocol implementation.
pcie_sw[1:0]
Description
continued...
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Port
Direction
Clock Domain
output
Asynchronous
input
N/A
Enables fPLL to ATX PLL cascading
clock input port.
fpll_to_fpll_cascade_clk
output
N/A
fPLL to fPLL cascade output port
(only in Core mode)
active_clk
output
N/A
Creates an output signal that
indicates the input clock being used
by the PLL. A logic Low on this signal
indicates refclk0 is being used and
a logic High indicates refclk1 is
being used (only in Core mode with
Clock Switchover enabled)
outclk0
output
N/A
Core output clock 0. (only in Core
mode)
There are four core fPLL output clock
output ports. The number of output
clock available depends on the
Selected reference clock source
outclk1
output
N/A
Core output clock 1. (only in Core
mode)
outclk2
output
N/A
Core output clock 2. (only in Core
mode)
outclk3
output
N/A
Core output clock 3. (only in Core
mode)
output
N/A
Clklow output for external lock
detection. It can be exposed by
selecting the Enable clklow and
fref port.
output
N/A
Fref output for external lock
detection It can be exposed by
selecting the Enable clklow and
fref port.
phase_reset
input
N/A
Dynamic phase shift reset input
signal. To be connected to DPS soft
IP phase_reset output.
phase_en
input
N/A
Dynamic phase shift enable input
signal. To be connected to DPS soft
IP phase_en output.
updn
input
N/A
Dynamic phase shift updn input
signal. To be connected to DPS soft
IP updn output.
cntsel[3:0]
input
N/A
Dynamic phase shift counter bus. To
be connected to DPS soft IP cntsel
output bus.
pcie_sw_done[1:0]
atx_to_fpll_cascade_clk
ext_lock_detect_clklow
ext_lock_detect_fref
(56)
(56)
Description
2-bit rate switch status output used
for PCIe protocol implementation.
Related Links
(56)
•
Calibration on page 28
•
Reconfiguration Interface and Dynamic Reconfiguration on page 484
The fPLL fref and clklow signals should only be used with the Intel external soft lock
detection logic.
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•
Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon
Specification. Refer to the Avalon Specification for more details about these
ports.
•
Intel Arria 10 device fPLL reports an unlocked condition
3.1.4 CMU PLL
The clock multiplier unit (CMU) PLL resides locally within each transceiver channel.The
channel PLL's primary function is to recover the receiver clock and data in the
transceiver channel. In this case the PLL is used in clock and data recovery (CDR)
mode.
When the channel PLL of channels 1 or 4 is configured in the CMU mode, the channel
PLL can drive the local clock generation block (CGB) of its own channel, then the
channel cannot be used as a receiver.
The CMU PLL from transceiver channel 1 and channel 4 can also be used to drive other
transceiver channels within the same transceiver bank. The CDR of channels 0, 2, 3,
and 5 cannot be configured as a CMU PLL.
For datarates lower than 6 Gbps, the local CGB divider has to be engaged (TX local
division factor in transceiver PHY IP under the TX PMA tab) .
Figure 172. CMU PLL Block Diagram
User Control
(LTR/LTD)
Lock to
Reference
Controller
CP &
LF
Refclk
Multiplexer
Reference clock network
Input reference
clock
Receiver input pin
N Counter
Lock to Reference
Lock
Detector
refclk
Up
VCO
PLL Lock Status
L Counter
Output
Down
PFD
fbclk
M Counter
Input Reference Clock
The input reference clock for a CMU PLL can be sourced from either the reference
clock network or a receiver input pin. The input reference clock is a differential signal.
For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the
dedicated reference clock pin in the same triplet with the CMU PLL as the input
reference clock source.The input reference clock must be stable and free-running at
device power-up for proper PLL operation. If the reference clock is not available at
device power-up, then you must recalibrate the PLL when the reference clock is
available. Refer to the Calibration section for details about PLL calibration and the
CLKUSR clock requirement.
Note:
The CMU PLL calibration is clocked by the CLKUSR clock which must be stable and
available for calibration to proceed. Refer to the Calibration section for more details
about the CLKUSR clock.
Reference Clock Multiplexer (Refclk Mux)
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The refclk mux selects the input reference clock to the PLL from the various reference
clock sources available.
N Counter
The N counter divides the refclk mux's output. The N counter division helps lower the
loop bandwidth or reduce the frequency to within the phase frequency detector's
(PFD) operating range. Possible divide ratios are 1 (bypass), 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock (refclk) signal at the output of the N counter block and the
feedback clock (fbclk) signal at the output of the M counter block is supplied as an
input to the PFD. The PFD output is proportional to the phase difference between the
two inputs. It aligns the input reference clock (refclk) to the feedback clock
(fbclk). The PFD generates an "Up" signal when the reference clock's falling edge
occurs before the feedback clock's falling edge. Conversely, the PFD generates a
"Down" signal when feedback clock's falling edge occurs before the reference clock's
falling edge.
Charge Pump and Loop Filter (CP + LF)
The PFD output is used by the charge pump and loop filter to generate a control
voltage for the VCO. The charge pump translates the "Up"/"Down" pulses from the
PFD into current pulses. The current pulses are filtered through a low pass filter into a
control voltage which drives the VCO frequency.
Voltage Controlled Oscillator (VCO)
The CMU PLL has a ring oscillator based VCO. For VCO frequency range, refer to the
datasheet.
L Counter
The L counter divides the differential clocks generated by the CMU PLL.
M Counter
The M counter is used in the PFD's feedback path. The output of the L counter is
connected to the M counter. The combined division ratios of the L counter and the M
counter determine the overall division factor in the PFD's feedback path.
Lock Detector (LD)
The lock detector indicates when the CMU PLL is locked to the desired output's phase
and frequency. The lock detector XORs the "Up"/"Down" pulses and indicates when the
M counter's output and N counter's output are phase-aligned.
The reference clock (refclk) and feedback clock (fbclk) are sent to the PCS's ppm
detector block. There is a pre-divider to lower the frequency in case the frequency is
too high.
Related Links
•
Calibration on page 547
•
Intel Arria 10 Device Datasheet
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3.1.4.1 Instantiating CMU PLL IP Core
The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in
hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
1.
Open the Quartus Prime software.
2.
Click Tools ➤ IP Catalog.
3.
In IP Catalog, under Library ➤ Transceiver PLL , select Arria 10 Transceiver
CMU PLL and click Add.
4. In the New IP Instance Dialog Box, provide the IP instance name.
5.
Select Arria 10 device family.
6.
Select the appropriate device and click OK.
The CMU PLL IP core Parameter Editor window opens.
3.1.4.2 CMU PLL IP Core
Table 240.
CMU PLL Parameters and Settings
Parameters
Range
Description
Message level for rule violations
Error
Warning
Specifies the messaging level to use for parameter rule
violations.
• Error - Causes all rule violations to prevent IP
generation.
• Warning - Displays all rule violations as warnings and
will allow IP generation in spite of violations.
Bandwidth
Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the expense of
decreased jitter rejection.
Number of PLL reference clocks
1 to 5
Specifies the number of input reference clocks for the CMU
PLL.
You can use this parameter for data rate reconfiguration.
Selected reference clock source
0 to 4
Specifies the initially selected reference clock input to the
CMU PLL.
TX PLL Protocol mode
BASIC
PCIe
This parameter governs the rules for correct protocol
specific settings. Certain features of the PLL are only
available for specific protocol configuration rules. This
parameter is not a preset .
You must set all the other parameters for your protocol.
PLL reference clock frequency
Refer to the GUI
Selects the input reference clock frequency for the PLL.
PLL output frequency
Refer to the GUI
Specify the target output frequency for the PLL.
Multiply factor (M-Counter)
Read only
Displays the M-multiplier value.
Divide factor (N-Counter)
Read only
Displays the N-counter value.
Divide factor (L-Counter)
Read only
Displays the L-counter value.
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Table 241.
CMU PLL—Dynamic Reconfiguration
Parameters
Range
Description
Enable dynamic reconfiguration
On/Off
Enables the PLL reconfiguration interface. Enables the
simulation models and adds more ports for reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off
When you turn this option On, the transceiver PLL IP core
includes an embedded Altera Debug Master Endpoint that
connects internally to the Avalon-MM slave interface for
dynamic reconfiguration. The ADME can access the
reconfiguration space of the transceiver. It can perform
certain test and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Separate reconfig_waitrequest
from the status of AVMM
arbitration with PreSICE
On/Off
When enabled, the reconfig_waitrequest will not
indicate the status of AVMM arbitration with PreSICE. The
AVMM arbitration status will be reflected in a soft status
register bit. (Only available if "Enable control and status
registers feature" is enabled).
Enable capability registers
On/Off
Enables capability registers that provide high- level
information about the CMU PLL's configuration.
Set user-defined IP identifier
Enable control and status registers
Sets a user-defined numeric identifier that can be read from
the user_identifier offset when the capability registers
are enabled.
On/Off
Configuration file prefix
Enables soft registers for reading status signals and writing
control signals on the PLL interface through the embedded
debug logic.
Enter the prefix name for the configuration files to be
generated.
Generate SystemVerilog package
file
On/Off
Generates a SystemVerilog package file containing all
relevant parameters used by the PLL.
Generate C header file
On/Off
Generates a C header file containing all relevant parameters
used by the PLL.
Generate MIF (Memory Initialize
File)
On/Off
Generates a MIF file that contains the current configuration.
Use this option for reconfiguration purposes in order to
switch between different PLL configurations.
Table 242.
CMU PLL—Generation Options
Parameters
Generate parameter
documentation file
Table 243.
Range
Description
On/Off
Generates a .csv file which contains the descriptions of all
CMU PLL parameters and values.
CMU PLL IP Ports
Port
Range
Clock Domain
Description
pll_powerdown
input
Asynchronous
pll_refclk0
input
N/A
Reference clock input port 0.
There are 5 reference clock input
ports. The number of reference clock
ports available depends on the
Number of PLL reference clocks
parameter.
pll_refclk1
input
N/A
Reference clock input port 1.
pll_refclk2
input
N/A
Reference clock input port 2.
Resets the PLL when asserted high.
continued...
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Port
Range
Clock Domain
Description
pll_refclk3
input
N/A
Reference clock input port 3.
pll_refclk4
input
N/A
Reference clock input port 4.
tx_serial_clk
output
N/A
High speed serial clock output port for
GX channels. Represents the x1 clock
network.
pll_locked
output
Asynchronous
reconfig_clk0
input
N/A
reconfig_reset0
input
reconfig_clk0
Used to reset the Avalon interface.
Asynchronous to assertion and
synchronous to deassertion.
reconfig_write0
input
reconfig_clk0
Active high write enable signal.
reconfig_read0
input
reconfig_clk0
Active high read enable signal.
reconfig_address0[9:0]
input
reconfig_clk0
10-bit address bus used to specify
address to be accessed for both read
and write operations.
reconfig_writedata0[31:0]
input
reconfig_clk0
32-bit data bus. Carries the write data
to the specified address.
reconfig_readdata0[31:0]
output
reconfig_clk0
32-bit data bus. Carries the read data
from the specified address.
reconfig_waitrequest0
output
reconfig_clk0
Indicates when the Avalon interface
signal is busy. When asserted, all
inputs must be held constant.
pll_cal_busy
output
Asynchronous
Active high status signal which
indicates if PLL is locked.
Optional Avalon interface clock. Used
for PLL reconfiguration. The
reconfiguration ports appear only if the
Enable Reconfiguration parameter is
selected in the PLL IP Core GUI. When
this parameter is not selected, the
ports are set to OFF internally.
Status signal that is asserted high
when PLL calibration is in progress.
Perform logical OR with this signal and
the tx_cal_busy port on the reset
controller IP.
Related Links
•
Calibration on page 28
•
Reconfiguration Interface and Dynamic Reconfiguration on page 484
•
Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon
Specification. Refer to the Avalon Specification for more details about these
ports.
3.2 Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference
clock source to generate the clocks required for transceiver operation. The input
reference clock must be stable and free-running at device power-up for proper PLL
calibrations.
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Arria 10 transceiver PLLs have five possible input reference clock sources, depending
on jitter requirements:
•
Dedicated reference clock pins
•
Reference clock network
•
The output of another fPLL with PLL cascading
•
Receiver input pins
•
Global clock or core clock
(57)
(57)
For the best jitter performance, Intel recommends placing the reference clock as close
as possible, to the transmit PLL. For protocol jitter compliance at data rates > 10
Gbps, place the reference clock pin in the same triplet as the transmit PLL.
The following protocols require the reference clock to be placed in same bank as the
transmit PLL:
Note:
•
OTU2e, OTU2, OC-192 and 10G PON
•
6G and 12G SDI
Sourcing reference clock from a cascaded PLL output, global clock or core clock
network will introduce additional jitter to transmit PLL ouput. Refer to KDB "How do I
compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL
reference clock?" for more details.
For optimum performance of GT channel, the reference clock of transmit PLL is
recommended to be from a dedicated reference clock pin in the same bank.
Figure 173. Input Reference Clock Sources
Reference Clock
Network
Input
Reference
Clock
Dedicated
refclk
pin
(2)
Serial Clock
fPLL or ATX PLL
RX pin 2
(3)
RX pin 1
RX pin 0
fPLL
Global or
Core Clock
(1)
Note : (1) You can choose only one of the three RX pins to be used as an input reference clock source. Any RX pin on the same side
of the device can be used as an input reference clock.
(2) Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network.
Reference clock network can then drive the CMU PLL.
(3) The output of another PLL can be used as an input reference clock source during PLL cascading. Arria 10 transceivers support fPLL to fPLL cascading.
Note:
(57)
•
In Arria 10 devices, the FPGA fabric core clock network can be used as an input
reference source for any PLL type.
•
To successfully complete the calibration process, the reference clocks driving the
PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of
FPGA configuration. Otherwise, recalibration will be necessary.
Not available for CMU.
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Related Links
Calibration on page 547
For more information about the calibration process
3.2.1 Dedicated Reference Clock Pins
To minimize the jitter, the advanced transmit (ATX) PLL and the fractional PLL (fPLL)
can source the input reference clock directly from the reference clock buffer without
passing through the reference clock network. The input reference clock is also fed into
the reference clock network.
Figure 174. Dedicated Reference Clock Pins
There are two dedicated reference clock (refclk) pins available in each transceiver bank. The bottom refclk
pin feeds the bottom ATX PLL, fPLL, and CMU PLL. The top refclk pin feeds the top ATX PLL, fPLL, and CMU
PLL. The dedicated reference clock pins can also drive the reference clock network.
Reference Clock
Network
fPLL1
CH5
CDR PLL
CH4
CMU PLL
From PLL
Cascading Clock
Network
Reference Clock
Network
CH3
CDR PLL
ATX PLL1
From PLL Feedback
and Cascading Clock
Network
fPLL0
CH2
CDR PLL
From PLL
Cascading Clock
Network
CH1
CMU PLL
CH0
CDR PLL
Refclk
Reference Clock
Network
Input Reference Clock to the PLLs
Can Come from Either the Reference
Clock Network or the PLL Feedback
and Cascading Clock Network
ATX PLL0
From PLL Feedback
and Cascading Clock
Network
Refclk
ATX and fPLL Can Receive the
Input Reference Clock from a
Dedicated refclk Pin
3.2.2 Receiver Input Pins
Receiver input pins can be used as an input reference clock source to transceiver PLLs.
However, they cannot be used to drive core fabric.
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The receiver input pin drives the feedback and cascading clock network, which can
then feed any number of transmitter PLLs on the same side of the device. When a
receiver input pin is used as an input reference clock source, the clock data recovery
(CDR) block of that channel is not available. As indicated in Figure 173 on page 361,
only one RX differential pin pair per three channels can be used as an input reference
clock source at any given time.
3.2.3 PLL Cascading as an Input Reference Clock Source
In PLL cascading, PLL outputs are connected to the feedback and cascading clock
network. The input reference clock to the first PLL can be sourced from the same
network. In this mode, the output of one PLL drives the reference clock input of
another PLL. PLL cascading can generate frequency outputs not normally possible with
a single PLL solution. The transceiver in Arria 10 devices support fPLL to fPLL
cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to
fPLL cascading is available to OTN and SDI protocols only.
Note:
•
To successfully complete the calibration process, the reference clocks driving the
PLLs (ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of
FPGA configuration. Otherwise, recalibration will be necessary.
•
When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration
on the fPLL is required. Refer to "User Recalibration" section in "Calibration"
chapter for more information.
Related Links
Calibration on page 547
For more information about the calibration process
3.2.4 Reference Clock Network
The reference clock network distributes a reference clock source to either the entire
left or right side of the FPGA where the transceivers reside. This allows any reference
clock pin to drive any transmitter PLL on the same side of the device. Designs using
multiple transmitter PLLs which require the same reference clock frequency and are
located along the same side of the device, can share the same dedicated reference
clock (refclk) pin.
3.2.5 Global Clock or Core Clock as an Input Reference Clock
The global clock or the core clock can be used as an input reference clock for any PLL
type.
The global or core clock network routes the clock directly to the PLL. In this case the
PLL reference clock network is not used. For best performance, use the dedicated
reference clock pins or the reference clock network.
3.3 Transmitter Clock Network
The transmitter clock network routes the clock from the transmitter PLL to the
transmitter channel. It provides two types of clocks to the transmitter channel:
•
High Speed Serial clock—high-speed clock for the serializer.
•
Low Speed Parallel clock—low-speed clock for the serializer and the PCS.
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In a bonded channel configuration, both the serial clock and the parallel clock are
routed from the transmitter PLL to the transmitter channel. In a non-bonded channel
configuration, only the serial clock is routed to the transmitter channel, and the
parallel clock is generated locally within the channel. To support various bonded and
non-bonded clocking configurations, four types of transmitter clock network lines are
available:
•
x1 clock lines
•
x6 clock lines
•
xN clock lines
•
GT clock lines
Related Links
Unused/Idle Clock Line Requirements on page 377
For more information about unused or idle transceiver clock lines in the design.
3.3.1 x1 Clock Lines
The x1 clock lines route the high speed serial clock output of a PLL to any channel
within a transceiver bank. The low speed parallel clock is then generated by that
particular channel's local clock generation block (CGB). Non-bonded channel
configurations use the x1 clock network.
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two
channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank.
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Figure 175. x1 Clock Lines
x1 Network
CGB
Ch 5
fPLL1
Master
CGB
CDR
CGB
ATX PLL1
Ch 4
CMU or CDR
CGB
Ch 3
CDR
CGB
fPLL0
Ch 2
CDR
Master
CGB
CGB
Ch 1
CMU or CDR
ATX PLL0
CGB
Ch 0
CDR
3.3.2 x6 Clock Lines
The x6 clock lines route the clock within a transceiver bank. The x6 clock lines are
driven by the master CGB. The master CGB can only be driven by the ATX PLL or the
fPLL. Because the CMU PLLs cannot drive the master CGB, the CMU PLLs cannot be
used for bonding purposes. There are two x6 clock lines per transceiver bank, one for
each master CGB. Any channel within a transceiver bank can be driven by the x6 clock
lines.
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For bonded configuration mode, the low speed parallel clock output of the master CGB
is used and the local CGB within each channel is bypassed. For non-bonded
configurations, the master CGB also provides a high speed serial clock output to each
channel without bypassing the local CGB within each channel.
The x6 clock lines also drive the xN clock lines which route the clocks to the
neighboring transceiver banks.
Figure 176. x6 Clock Lines
x6
Network
x6
Top
x6
Bottom
CGB
Ch 5
CDR
CGB
Ch 4
CMU or CDR
Master
CGB
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CMU or CDR
Master
CGB
CGB
Ch 0
CDR
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3.3.3 xN Clock Lines
The xN clock lines route the transceiver clocks across multiple transceiver banks.
The master CGB drives the x6 clock lines and the x6 clock lines drive the xN clock
lines. There are two xN clock lines: xN Up and xN Down. xN Up clock lines route the
clocks to transceiver banks located above the master CGB and xN Down clock lines
route the clocks to transceiver banks located below the master CGB. The xN clock
lines can be used in both bonded and non-bonded configurations. For bonded
configurations, the low speed parallel clock output of the master CGB is used, and the
local CGB within each channel is bypassed. For non-bonded configurations, the master
CGB provides a high speed serial clock output to each channel.
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Figure 177. xN Clock Network
xN Up
xN Down
x6
Top
x6
Bottom
CGB
Ch 5
CDR
CGB
Ch 4
CMU or CDR
Master
CGB1
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CMU or CDR
Master
CGB0
CGB
Ch 0
CDR
xN Up
xN Down
The maximum channel span of a xN clock network is two transceiver banks above and
two transceiver banks below the bank that contains the driving PLL and the master
CGB. A maximum of 30 channels can be used in a single bonded or non-bonded xN
group.
The maximum data rate supported by the xN clock network while driving channels in
either the bonded or non-bonded mode depends on the voltage used to drive the
transceiver banks.
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Related Links
•
Implementing x6/xN Bonding Mode on page 392
•
x6/xN Bonding on page 377
•
Intel Arria 10 Device Datasheet
3.3.4 GT Clock Lines
GT clock lines are dedicated clock lines available only in Arria 10 GT devices.
Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the
transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and
4, and the bottom ATX PLL drives channels 0 and 1. These connections bypass the rest
of the clock network for higher performance. These channels can be used only for
non-bonded configurations.
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Figure 178. GT Clock Lines
CGB
Ch 5
CDR
CGB
Ch 4
CMU or CDR
ATX PLL1
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
ATX PLL0
Ch 1
CMU or CDR
CGB
Ch 0
CDR
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3.4 Clock Generation Block
In Arria 10 devices, there are two types of clock generation blocks (CGBs)
•
Local clock generation block (local CGB)
•
Master clock generation block (master CGB)
Each transmitter channel has a local clock generation block (CGB). For non-bonded
channel configurations, the serial clock generated by the transmit PLL drives the local
CGB of each channel. The local CGB generates the parallel clock used by the serializer
and the PCS.
There are two standalone master CGBs within each transceiver bank. The master CGB
provides the same functionality as the local CGB within each transceiver channel. The
output of the master CGB can be routed to other channels within a transceiver bank
using the x6 clock lines. The output of the master CGB can also be routed to channels
in other transceiver banks using the xN clock lines. Each transmitter channel has a
multiplexer to select its clock source from either the local CGB or the master CGB.
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Figure 179. Clock Generation Block and Clock Network
The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network, or
the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the fPLL 1 drives
the x1 network which in turn drives the master CGB. The master CGB then drives the x6 clock network which
routes the clocks to the local channels. As shown by the blue highlighted path, the ATX PLL 0 can also drive the
x1 clock network which can directly feed a channel's local CGB. In this case, the low speed parallel clock is
generated by the local CGB.
x1
Network
xN
Up
xN
Down
x6
Top
x6
Bottom
fPLL 1
CGB
CDR
ATX PLL 1
CGB
fPLL 0
Ch 5
Ch 4
CMU or CDR
Master
CGB1
CGB
ATX PLL 0
Ch 3
CDR
CGB
Ch 2
Transceiver
Bank
CDR
CGB
Ch 1
CMU or CDR
Master
CGB0
CGB
Ch 0
CDR
3.5 FPGA Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric
into the transceiver and clock signals from the transceiver into the FPGA fabric. These
clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock
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networks in the FPGA core. If the Global Signal is set to Off, it does not choose any of
the previously mentioned clock networks. Instead, it chooses directly from the local
routing between transceiver and FPGA fabric.
The transmitter channel forwards a parallel output clock tx_clkout to the FPGA
fabric to clock the transmitter data and control signals. The receiver channel forwards
a parallel output clock rx_clkout to the FPGA fabric to clock the data and status
signals from the receiver into the FPGA fabric. Based on the receiver channel
configuration, the parallel output clock is recovered from either the receiver serial data
or the rx_clkout clock (in configurations without the rate matcher) or the
tx_clkout clock (in configurations with the rate matcher).
Figure 180. FPGA Fabric - Transceiver Interface Clocking
Transmitter Standard PCS
Transmitter PMA
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
PRBS
Generator
tx_coreclkin
tx_clkout
/2, /4
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
Parallel Clock
(Recovered)
rx_coreclkin
rx_clkout
tx_clkout
Parallel Clock
(From Clock
Divider)
rx_clkout or
tx_clkout
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
CMU PLL /
ATX PLL /
fPLL
Clock Divider
Serializer
Parallel and Serial Clocks
/66
Serial Clock
/40
Input Reference Clock
/33
/2
Serial Clock tx_clkout
(from CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
tx_pma_div_clkout
Deserializer
/66
/40
/33
CDR Recovered
Clock
/2
rx_pma_div_clkout
rx_clkout
The divided versions of the tx_clkout and rx_clkout are available as
tx_pma_div_clkout and rx_pma_div_clkout, respectively.
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The output frequency of tx_pma_div_clkout and rx_pma_div_clkout can be one
of the following:
Note:
•
A divided down version of the tx_clkout or rx_clkout respectively, where
divide by 1 and divide by 2 ratios are available.
•
A divided down version of the serializer clock where divide by 33, 40, and 66
ratios are available.
Refer to the "TX PMA Optional Ports" table in PMA Parameters section for details about
selecting the division factor.
These clocks can be used to meet core timing by operating the TX and RX FIFO in
double-width mode, as this halves the required clock frequency at the PCS to/from
FPGA interface. These clocks can also be used to clock the core side of the TX and RX
FIFOs when the Enhanced PCS Gearbox is used.
For example, if you use the Enhanced PCS Gearbox with a 66:40 ratio, then you can
use tx_pma_div_clkout with a divide-by-33 ratio to clock the write side of the TX
FIFO, instead of using a PLL to generate the required clock frequency, or using an
external clock source.
Related Links
PMA Parameters on page 49
3.6 Transmitter Data Path Interface Clocking
The clocks generated by the PLLs are used to clock the channel PMA and PCS blocks.
The clocking architecture is different for the standard PCS and the enhanced PCS.
Figure 181. Transmitter Standard PCS and PMA Clocking
The master or the local CGB provides the high speed serial clock to the serializer of the transmitter PMA, and
the low speed parallel clock to the transmitter PCS.
Transmitter Standard PCS
Transmitter PMA
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
PRBS
Generator
tx_coreclkin
tx_clkout
/2, /4
tx_clkout
tx_pma_div_clkout
From Receiver Standard PCS
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Serial Clock
Input Reference Clock
In the Standard PCS, for configurations that do not use the byte serializer, the parallel
clock is used by all the blocks up to the read side of the TX phase compensation FIFO.
For configurations that use the byte serializer block, the clock divided by 2 or 4 is used
by the byte serializer and the read side of the TX phase compensation FIFO. The clock
used to clock the read side of the TX phase compensation FIFO is also forwarded to
the FPGA fabric to provide an interface between the FPGA fabric and the transceiver.
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If the tx_clkout that is forwarded to the FPGA fabric is used to clock the write side
of the phase compensation FIFO, then both sides of the FIFO have 0 ppm frequency
difference because it is the same clock that is used.
If you use a different clock than the tx_clkout to clock the write side of the phase
compensation FIFO, then you must ensure that the clock provided has a 0 ppm
frequency difference with respect to the tx_clkout.
Figure 182. Transmitter Enhanced PCS and PMA Clocking
The master or local CGB provides the serial clock to the serializer of the transmitter PMA, and the parallel clock
to the transmitter PCS.
Transmitter Enhanced PCS
Enhanced PCS
TX FIFO
Interlaken
Frame Generator
TX
Data &
Control
tx_coreclkin
PRBS
Generator
Interlaken
CRC32 Generator
64B/66B Encoder
and TX SM
Scrambler
Interlaken
Disparity Generator
FPGA
Fabric
TX
Gearbox
Serializer
tx_serial_data
Transmitter PMA
PRP
Generator
Parallel Clock
Transcode
Encoder
KR FEC
Encoder
KR FEC
Scrambler
KR FEC
TX Gearbox
tx_clkout
tx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
In the Enhanced PCS, the parallel clock is used by all the blocks up to the read side of
the TX phase compensation FIFO. The clocks of all channels in bonded configuration
are forwarded. You can pick tx_clkout[0] as the source for clocking their TX logic in
core.
For the enhanced PCS, the transmitter PCS forwards the following clocks to the FPGA
fabric:
tx_clkout for each transmitter channel in non-bonded and bonded configuration. In
bonded configuration, any tx_clkout can be used depending on your core timing
requirements.
You can clock the transmitter datapath interface using one of the following methods:
•
Quartus Prime selected transmitter datapath interface clock
•
User-selected transmitter datapath interface clock
3.7 Receiver Data Path Interface Clocking
The CDR block present in the PMA of each channel recovers the serial clock from the
incoming data. The CDR block also divides the recovered serial clock to generate the
recovered parallel clock. Both the recovered serial and the recovered parallel clocks
are used by the deserializer. The receiver PCS can use the following clocks based on
the configuration of the receiver channel:
•
Recovered parallel clock from the CDR in the PMA.
•
Parallel clock from the clock divider used by the transmitter PCS (if enabled) for
that channel.
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For configurations that use the byte deserializer block, the clock divided by 2 or 4 is
used by the byte deserializer and the write side of the RX phase compensation FIFO.
Figure 183. Receiver Standard PCS and PMA Clocking
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
Parallel Clock
(Recovered)
FPGA
Fabric
rx_coreclkin
rx_clkout
tx_clkout
Parallel Clock
(From Clock
Divider)
rx_clkout or
tx_clkout
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Serial Clock
Parallel and Serial Clock
All configurations that use the standard PCS channel must have a 0 ppm phase
difference between the receiver datapath interface clock and the read side clock of the
RX phase compensation FIFO.
Figure 184. Receiver Enhanced PCS and PMA Clocking
Interlaken
CRC32 Checker
Enhanced PCS
RX FIFO
rx_coreclkin
PRBS
Verifier
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler
Block
Synchronizer
RX
Gearbox
Interlaken
Disparity Checker
rx_pma_div_clkout
Deserializer
CDR
rx_serial_data
FPGA
Fabric
Receiver Enhanced PCS
Receiver PMA
PRP
Verifier
rx_clkout
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
10GBASE-R
BER Checker
Parallel Clock
Serial Clock
Parallel and Serial Clock
The receiver PCS forwards the following clocks to the FPGA fabric:
•
rx_clkout — for each receiver channel when the rate matcher is not used.
•
tx_clkout — for each receiver channel when the rate matcher is used.
You can clock the receiver datapath interface using one of the following methods:
•
Quartus Prime selected receiver datapath interface clock
•
User-selected receiver datapath interface clock
Related Links
Unused or Idle Clock Line Requirements on page 377
For more information about unused or idle transceiver clock lines in design.
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3.8 Unused/Idle Clock Line Requirements
Unused or idle transceiver clock lines can degrade if the devices are powered up to
normal operating conditions and not configured. This affects designs that will configure
transceiver RX channels to use the idle clock lines at a later date by using dynamic
reconfiguration or a new device programming file. Clock lines affected are unused, or
idle RX serial clock lines. Active RX serial clock lines and non-transceiver circuits are
not impacted by this issue.
In order to prevent the performance degradation, for idle transceiver RX channels,
recompile designs with Intel Quartus Prime version 16.1 or later with the assignment
described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz
clock. For used transceiver TX and RX channels, do not assert the analog reset signals
indefinitely.
Related Links
Unused Transceiver channels Settings on page 584
For more information about unused or idle transceiver clock lines in the design. It
describes the unused or idle RX serial clock lines assignments in the qsf file.
3.9 Channel Bonding
For Arria 10 devices, two types of bonding modes are available:
Note:
•
PMA bonding
•
PMA and PCS bonding
Channel bonding is not supported by GT channels.
Related Links
Resetting Transceiver Channels on page 402
Refer to the Timing Constraints for Bonded PCS and PMA Channels section in the
Resetting Transceiver Channels chapter for additional details.
3.9.1 PMA Bonding
PMA bonding reduces skew between PMA channels. In PMA bonding, only the PMA
portion of the transceiver datapath is skew compensated and the PCS is not skew
compensated.
In Arria 10 devices, there are two PMA bonding schemes:
•
x6/xN bonding
•
PLL feedback compensation bonding
In either case, the channels in the bonded group need not be placed contiguously.
3.9.1.1 x6/xN Bonding
In x6/xN bonding mode, a single transmit PLL is used to drive multiple channels.
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The steps below explain the x6/xN bonding process:
1.
The ATX PLL or the fPLL generates a high speed serial clock.
2.
The PLL drives the high speed serial clock to the master CGB via the x1 clock
network.
3.
The master CGB drives the high speed serial and the low speed parallel clock into
the x6 clock network.
4. The x6 clock network feeds the TX clock multiplexer for the transceiver channels
within the same transceiver bank. The local CGB in each transceiver channel is
bypassed.
5.
To drive the channels in adjacent transceiver banks, the x6 clock network drives
the xN clock network. The xN clock network feeds the TX clock mutiplexer for the
transceiver channels in these adjacent transceiver banks.
x6/xN Bonding Disadvantages
x6/xN Bonding has the following disadvantages:
•
The maximum data rate is restricted based on the transceiver supply voltage.
Refer to Arria 10 Device Data Sheet.
•
The maximum channel span is limited to two transceiver banks above and below
the bank containing the transmit PLL. Thus, the maximum span of 30 channels is
supported.
Related Links
•
xN Clock Lines on page 367
•
Arria 10 Device Datasheet
3.9.1.2 PLL Feedback Compensation Bonding
In PLL feedback compensation bonding, channels are divided into bonded groups
based on physical location with a three-channel or six-channel transceiver bank. All
channels within the same six-channel transceiver bank are assigned to the same
bonded group.
In PLL feedback compensation bonding, each bonded group is driven by its own set of
high-speed serial and low-speed parallel clocks. Each bonded group has its own PLL
and master CGB. To maintain the same phase relationship, the PLL and master CGB
for different groups share the same reference clocks.
The steps below explain the PLL feedback compensation bonding process:
1.
The same input reference clock drives the local PLL in each three-channel or sixchannel transceiver bank.
2. The local PLL for the bonding group drives the master CGB.
3. The master CGB feeds the x6 clock lines. The master CGB drives the transceiver
channels in the bonding group via the x6 clock network.
4. The parallel output of the master CGB is the feedback input to the PLL.
5. In this mode, all channels are phase aligned to the same input reference clock.
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PLL Feedback Compensation Bonding Advantages over x6/xN Bonding Mode
•
There is no data rate restriction. The x6 clock network used for PLL feedback
compensation bonding can run up to the maximum data rate of the device used.
•
There is no channel span limitation. It is possible to bond the entire side of the
device using PLL feedback compensation.
PLL Feedback Compensation Bonding Disadvantages over x6/xN Bonding
Mode
Note:
•
It uses more resources compared to x6/xN bonding. One PLL and one master CGB
are used per transceiver bank. This causes higher power consumption compared
to x6/xN bonding.
•
The skew is higher compared to x6/xN bonding. The reference clock skew between
each transceiver bank is higher than the skew contributed by the xN clock network
in x6/xN bonding.
•
Because the feedback clock for the PLL comes from the master CGB and not from
the PLL, the PLL feedback compensation bonding mode has a reference clock
limitation. The PLL's N-counter (reference clock divider) is bypassed resulting in
only one valid reference clock frequency for a given data rate.
•
Feedback compensation bonding only supports integer mode.
In order to minimize the reference clock skew for PLL feedback compensation bonding,
use a reference clock input near the center of the bonded group.
x6/xN Bonding Advantages over PLL Feedback Compensation Bonding
•
x6/xN uses less resources compared to PLL feedback compensation bonding. Only
one PLL and one master CGB are required to drive all channels in the bonded
group.
•
x6/xN has lower skew compared to PLL feedback compensation bonding.
Related Links
Implementing PLL Feedback Compensation Bonding Mode on page 393
3.9.2 PMA and PCS Bonding
PMA and PCS bonding reduces skew between both the PMA and PCS outputs within a
group of channels.
For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For
PCS bonding, some of the PCS control signals within the bonded group are skew
aligned using dedicated hardware inside the PCS.
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Figure 185. PMA and PCS Bonding
Starting
Delay (Cycles)
Distribution
Delay (Cycles)
2
4
Slave PCS
Channel
PMA
4
2
Slave PCS
Channel
PMA
6
0
Master PCS
Channel
PMA
4
2
Slave PCS
Channel
PMA
2
4
Slave PCS
Channel
PMA
0
6
Slave PCS
Channel
PMA
For PMA and PCS bonding, the concept of master and slave channels is used. One PCS
channel in the bonded group is selected as the master channel and all others are slave
channels. To ensure that all channels start transmitting data at the same time and in
the same state, the master channel generates a start condition. This condition is
transmitted to all slave channels. The signal distribution of this start condition incurs a
two parallel clock cycle delay. Because this signal travels sequentially through each
PCS channel, this delay is added per channel. The start condition used by each slave
channel is delay compensated based on the slave channel's distance from the master
channel. This results in all channels starting on the same clock cycle.
The transceiver PHY IP automatically selects the center channel to be the master PCS
channel. This minimizes the total starting delay for the bonded group. For PLL
feedback compensation bonding up to all channels on one side can be bonded if the
master PCS channel is placed in the center of the bonded group.
Note:
Because the PMA and PCS bonding signals travel through each PCS block, the PMA and
PCS bonded groups must be contiguously placed. The channel order needs to be
maintained when doing the pin assignments to the dedicated RX serial inputs and TX
serial outputs (for example: PIN_BC7 and PIN_BC8 for GXBR4D_TX_CH0p and
GXBR4D_TX_CH0n TX serial outputs). Channels need to be placed in an ascending
order from bottom to top. Swapping of channels, when doing pin assignments, leads
to errors.
3.9.3 Selecting Channel Bonding Schemes
In Arria 10 devices, select PMA and PCS bonding for bonded protocols that are
explicitly supported by the hard PCS blocks. For example, PCI Express, SFI-S, and
40GBASE-KR.
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Select PMA-only bonding when a bonded protocol is not explicitly supported by the
hard PCS blocks. For example, for Interlaken protocol, PMA-only bonding is used and a
soft PCS bonding IP is implemented in the FPGA fabric.
3.9.4 Skew Calculations
To calculate the maximum skew between the channels, the following parameters are
used:
•
PMA to PCS datapath interface width (S)
•
Maximum difference in number of parallel clock cycles between deassertion of
each channel's FIFO reset (N).
To calculate the channel skew, the following five scenarios are considered:
•
Non-bonded
In this case, both the PMA and PCS are non-bonded. Skew ranges from 0 UI to
[(S-1) + N*S] UI.
•
PMA bonding using x6 / xN clock network
In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI + x6/xN
clock skew.
•
PMA bonding using the PLL feedback compensation clock network
In this case, the PCS is non-bonded. Skew ranges from [0 to (N*S)] UI +
(reference clock skew) + (x6 clock skew).
•
PMA and PCS bonding using the x6 / xN clock network
Skew = x6 / xN clock skew.
•
PMA and PCS bonding using PLL feedback compensation clock network
Skew = (reference clock skew) + (x6 clock skew).
3.10 PLL Feedback and Cascading Clock Network
The PLL feedback and cascading clock network spans the entire side of the device, and
is used for PLL feedback compensation bonding and PLL cascading.
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Figure 186. PLL Feedback and Cascading Clock Network
Transceiver Bank
fPLL1
C
Connection (1)
PLL Feedback and Cascading Clock Network
0
1
2
3
fbclk
refclk
ATX PLL 1
refclk
Connection (3)
fbclk
Master CGB1
Connection (4)
Bidirectional
Tristate Buffer
fPLL0
C
refclk
fbclk
Connection (2)
ATX PLL 0
refclk
fbclk
Master CGB0
Bidirectional
Tristate Buffer
Legend
refclk Lines
fbclk Lines
C, M, and CGB Outputs
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PLL Feedback Compensation Bonding
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To support PLL feedback compensation bonding and PLL cascading, the following
connections are present:
1.
The C counter output of the fPLL drives the feedback and cascading clock
network.
2.
The feedback and cascading clock network drives the feedback clock input of
all PLLs.
3. The feedback and cascading clock network drives the reference clock input of
all PLLs.
4.
The master CGB’s parallel clock output drives the feedback and cascading
clock network.
For PLL cascading, connections (1) and (3) are used to connect the output of one PLL
to the reference clock input of another PLL.
The transceivers in Arria 10 devices support fPLL to fPLL, and ATX PLL to fPLL
(via dedicated ATX PLL to fPLL cascade path) cascading. Only maximum two
PLLs allowed in the cascading chain.
Note:
When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on
the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for
more information.
For PLL feedback compensation bonding, connections (2) and (4) are used to connect
the master CGB's parallel clock output to the PLL feedback clock input port.
PLL feedback compensation bonding can be used instead of xN bonding. The primary
difference between PLL feedback compensation and xN bonding configurations, is for
PLL feedback compensation, the bonded interface is broken down into smaller groups
of 6 bonded channels within a transceiver bank. A PLL within each transceiver bank
(ATX PLL or fPLL) is used as a transmit PLL. All the transmit PLLs share the same input
reference clock.
In xN bonding configurations, one PLL is used for each bonded group. In PLL feedback
compensation bonding, one PLL is used for each transceiver bank that the bonded
group spans. There are no data rate limitations in PLL feedback compensation
bonding, other than the natural data rate limitations of the transceiver channel and
the PLL.
For feedback compensation bonding, the low-speed parallel clock must be the same
frequency as the reference clock for the PLL.
fPLL Driving the Core
The fPLL can be used to drive the FPGA fabric. To ensure phase alignment between the
input reference clock and the fPLL output clock, the fPLL needs to be configured in
integer mode. Refer to the following figures when doing dynamic reconfiguration.
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Figure 187. Fractional and not Phase Aligned
refclk
N Counter
PFD
VCO
/2
L Counter
/2
fPLL M Counter
C Counters
Phase
Multiplexer
Figure 188. Integer and Phase Aligned
refclk
N Counter
PFD
VCO
/2
L Counter
/2
fPLL M Counter
C Counters
Phase
Multiplexer
PLL Feedback Clock Network
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Figure 189. Integer Mode phase aligned and external feedback
pm_iqtxrx_t[5:0]
fPLL 1
C
refclk
fbclk
0
1
2
3
4
5
fpll_t_iqtxrxclk
pm_iqtxrxclk_top[5:0]
6
pm_iqtxrxclk_top[3:0]
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
PMA_RX_CLK
PMA_TX_CLK
RX pin (1)
4
Ch5
fbclk
refclk
ch5_iqtxrxclk_2
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch5_iqtxrxclk_5
Ch4
ch4_iqtxrxclk_4
pm_iqtxrxclk_top[5:0]
fbclk
4
refclk
pm_iqtxrxclk_top[3:0]
6
ch4_iqtxrxclk_4
Ch3
fbclk
refclk
ch3_iqtxrxclk_0
pm_iqtxrxclk_top[5:0]
4
pm_iqtxrxclk_top[3:0]
6
ch3_iqtxrxclk_5
LCPLL 1
M
refclk
fbclk
lc_t_iqtxrxclk
pm_iqtxrxclk_top[5:0]
6
pm_iqtxrxclk_top[3:0]
4
Master
CGB 1
Note: (1) RX pin used as reference clock
You must recalibrate the fPLL when you enable the phase alignment option.
1.
Modify the fPLL IP to enable fPLL reconfiguration
•
2.
Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic
reconfiguration.
Create logics in the core to perform following steps:
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3.
•
Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL to select internal
feedback.
•
Read-Modify-Write 0x1 to offset address 0x100 of the fPLL, then Read-ModifyWrite 0x1 to offset address 0x000 of the fPLL to request PreSICE to recalibrate
the fPLL.
•
Monitor bit 1 of offset address of 0x280 of the fPLL and wait until this bit
changes to zero. This indicates recalibration is completed. Ensure the fPLL
achieves lock.
•
Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL to select the
external feedback path.
Monitor the fPLL lock signal, wait until the fPLL achieves lock.
Related Links
•
User Recalibration on page 556
•
Implementing PLL Cascading on page 396
3.11 Using PLLs and Clock Networks
In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must
instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging
is no longer performed by the Quartus Prime software. This gives you more control,
transparency, and flexibility in the design process. You can specify the channel
configuration and PLL usage.
Related Links
PLLs and Clock Networks on page 335
3.11.1 Non-bonded Configurations
In a non-bonded configuration, only the high speed serial clock is routed from the
transmitter PLL to the transmitter channel. The low speed parallel clock is generated
by the local clock generation block (CGB) present in the transceiver channel. For nonbonded configurations, because the channels are not related to each other and the
feedback path is local to the PLL, the skew between channels cannot be calculated.
Also, the skew introduced by the clock network is not compensated.
3.11.1.1 Implementing Single Channel x1 Non-Bonded Configuration
In x1 non-bonded configuration, the PLL source is local to the transceiver bank and
the x1 clock network is used to distribute the clock from the PLL to the transmitter
channel.
For a single channel design, a PLL is used to provide the clock to a transceiver
channel.
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Figure 190. PHY IP Core and PLL IP Core Connection for Single Channel x1 Non-Bonded
Configuration Example
Transceiver PLL
Instance (5 GHz)
Native PHY Instance
(1 CH Non-Bonded 10 Gbps)
PLL
TX Channel
To implement this configuration, instantiate a PLL IP core and a PHY IP core and
connect them together as shown in the above figure.
Steps to implement a Single Channel x1 Non-Bonded Configuration
1.
Instantiate the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to use in your
design.
•
2.
Refer to Instantiating the ATX PLL IP Core on page 342 or Instantiating CMU
PLL IP Core on page 358 or Instantiating the fPLL IP Core on page 350 for
detailed steps.
Configure the PLL IP core using the IP Parameter Editor.
•
For ATX PLL IP core, do not include the Master CGB.
•
For fPLL IP core, set the PLL feedback operation mode to direct.
•
For CMU PLL IP core, specify the reference clock and the data rate. No special
configuration rule is required.
3. Configure the Native PHY IP core using the IP Parameter Editor .
•
4.
Set the Native PHY IP Core TX Channel bonding mode to Non Bonded .
Connect the PLL IP core to the Native PHY IP core. Connect the tx_serial_clk
output port of the PLL to IP to the corresponding tx_serial_clk0 input port of
the Native PHY IP core. This port represents the input to the local CGB of the
channel. The tx_serial_clk for the PLL represents the high speed serial clock
generated by the PLL.
3.11.1.2 Implementing Multi-Channel x1 Non-Bonded Configuration
This configuration is an extension of the x1 non-bonded case. In the following
example, 10 channels are connected to two instances of the PLL IP core. Two PLL
instances are required because PLLs using the x1 clock network can only span the 6
channels within the same transceiver bank. A second PLL instance is required to
provide the clock to the remaining 4 channels.
Because 10 channels are not bonded and are unrelated, you can use a different PLL
type for the second PLL instance. It is also possible to use more than two PLL IP cores
and have different PLLs driving different channels. If some channels are running at
different data rates, then you need different PLLs driving different channels.
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Figure 191. PHY IP Core and PLL IP Core Connection for Multi-Channel x1 Non-Bonded
Configuration
Transceiver PLL
Instance (5 GHz)
fPLL
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
Transceiver PLL
Instance (5 GHz)
fPLL
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Steps to implement a Multi-Channel x1 Non-Bonded Configuration
1.
Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in
your design and instantiate the PLL IP core.
•
2.
3.
Refer to Instantiating the ATX PLL IP Core on page 342 or Instantiating CMU
PLL IP Core on page 358 or Instantiating the fPLL IP Core on page 350 for
detailed steps.
Configure the PLL IP core using the IP Parameter Editor
•
For the ATX PLL IP core do not include the Master CGB. If your design uses the
ATX PLL IP core and more than 6 channels, the x1 Non-Bonded Configuration
is not a suitable option. Multi-channel xN Non-Bonded or Multi-Channel x1/xN
Non-Bonded are the required configurations when using the ATX PLL IP core
and more than 6 channels in the Native PHY IP core.
•
Refer to Figure 192 on page 389 Implementing Multi-Channel xN Non-Bonded
Configuration section or the Figure 193 on page 391 Multi-Channel x1/xN NonBonded Example.
•
For the fPLL IP core, set the PLL feedback operation mode to direct.
•
For the CMU PLL IP core, specify the reference clock and the data rate. No
special configuration rule is required.
Configure the Native PHY IP core using the IP Parameter Editor
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•
Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
•
Set the number of channels as per your design requirement. In this example,
the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
•
The tx_serial_clk output port of the PLL IP core represents the high
speed serial clock.
•
The Native PHY IP core has 10 (for this example) tx_serial_clk input
ports. Each port corresponds to the input of the local CGB of the transceiver
channel.
•
As shown in the figure above, connect the first 6 tx_serial_clk input to
the first transceiver PLL instance.
•
Connect the remaining 4 tx_serial_clk input to the second transceiver
PLL instance.
3.11.1.3 Implementing Multi-Channel xN Non-Bonded Configuration
Using the xN non-bonded configuration reduces the number of PLL resources and the
reference clock sources used.
Figure 192. PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded
Configuration
In this example, the same PLL is used to drive 10 channels across two transceiver banks.
Transceiver PLL
Instance (5 GHz)
ATX PLL
x1
Master
CGB
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
x6
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
xN
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
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Steps to implement a multi-channel xN non-bonded configuration
1.
You can use either the ATX PLL or fPLL for multi-channel xN non-bonded
configuration.
•
Refer to Instantiating the ATX PLL IP Core on page 342 or Instantiating the
fPLL IP Core on page 350 for detailed steps.
•
Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL
can be used for this example.
2.
Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block .
3.
Configure the Native PHY IP core using the IP Parameter Editor
4.
•
Set the Native PHY IP core TX Channel bonding mode to Non-Bonded .
•
Set the number of channels as per your design requirement. In this example,
the number of channels is set to 10.
Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
•
In this case, the PLL IP core has mcgb_serial_clk output port. This
represents the xN clock line.
•
The Native PHY IP core has 10 (for this example) tx_serial_clk input
ports. Each port corresponds to the input of the local CGB of the transceiver
channel.
•
As shown in the figure above, connect the mcgb_serial_clk output port of
the PLL IP core to the 10 tx_serial_clk input ports of the Native PHY IP
core.
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Figure 193. Multi-Channel x1/xN Non-Bonded Example
The ATX PLL IP core has a tx_serial_clk output port. This port can optionally be used to clock the six
channels within the same transceiver bank as the PLL. These channels are clocked by the x1 network. The
remaining four channels outside the transceiver bank are clocked by the xN clock network.
Transceiver PLL
Instance (5 GHz)
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
x1
ATX PLL
TX Channel
TX Channel
CGB
xN
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
3.11.2 Bonded Configurations
In a bonded configuration, both the high speed serial and low speed parallel clocks are
routed from the transmitter PLL to the transmitter channel. In this case, the local CGB
in each channel is bypassed and the parallel clocks generated by the master CGB are
used to clock the network.
In bonded configurations, the transceiver clock skew between the channels is
minimized. Use bonded configurations for channel bonding to implement protocols
such as PCIe and XAUI.
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3.11.2.1 Implementing x6/xN Bonding Mode
Figure 194. PHY IP Core and PLL IP Core Connection for x6/xN Bonding Mode
Transceiver PLL
Instance (5 GHz)
ATX PLL
x1
Native PHY Instance
(10 CH x6/xN Bonding 10 Gbps)
Master
CGB
x6
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
x6
TX Channel
xN
TX Channel
xN
TX Channel
xN
TX Channel
xN
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
Steps to implement a x6/xN bonded configuration
1.
You can instantiate either the ATX PLL or the fPLL for x6/xN bonded configuration.
•
Refer to Instantiating the ATX PLL IP Core on page 342 or Instantiating the
fPLL IP Core on page 350 for detailed steps. Because the CMU PLL cannot
drive the Master CGB, only the ATX PLL or fPLL can be used for bonded
configurations.
2.
Configure the PLL IP core using the IP Parameter Editor. Enable Include
Master Clock Generation Block and Enable bonding clock output ports.
3.
Configure the Native PHY IP core using the IP Parameter Editor .
•
Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding .
•
Set the number of channels required by your design. In this example, the
number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core.
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•
In this case, the PLL IP core has tx_bonding_clocks output bus with width
[5:0].
•
The Native PHY IP core has tx_bonding_clocks input bus with width [5:0]
multiplied by the number of transceiver channels (10 in this case). For 10
channels, the bus width will be [59:0].
Note: While connecting tx_bonding_clocks, leave tx_serial_clk open
to avoid any Intel Quartus Prime software fitter errors.
•
Note:
Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for
the input port connection is .tx_bonding_clocks
({10{tx_bonding_clocks_output}}) .
Although the above diagram looks similar to the 10-channel non-bonded configuration
example, the clock input ports on the transceiver channels bypass the local CGB in
x6/xN bonding configuration. This internal connection is taken care of when the
Native PHY channel bonding mode is set to Bonded.
Figure 195. x6/xN Bonding Mode —Internal Channel Connections
CGB
(1)
CDR
CGB
(1)
Ch 1
CDR
CGB
(1)
Ch 2
Ch 0
CDR
Note: (1) The local CGB is bypassed by the clock input ports in bonded mode.
Related Links
xN Clock Lines on page 367
Information on xN Clock Network Span.
3.11.2.2 Implementing PLL Feedback Compensation Bonding Mode
In this bonding mode, the channel span limitations of xN bonding mode are removed.
This is achieved by dividing all channels into multiple bonding groups.
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Figure 196. PHY IP Core and PLL IP Core Connection for PLL Feedback Compensation
Bonding
Transceiver PLL
Instance (5 GHz)
fPLL
CGB
Native PHY Instance
(10 CH Bonded 10 Gbps)
x6
TX Channel
TX Channel
Feedback Clock
TX Channel
TX Channel
TX Channel
Transceiver PLL
Instance (5 GHz)
Reference clock
fPLL
CGB
TX Channel
x6
Feedback Clock
TX Channel
TX Channel
TX Channel
TX Channel
Legend:
TX channels placed in the same transceiver bank.
TX channels placed in the adjacent transceiver bank.
The data rate is limited by the x6 network speed limit. A disadvantage of using PLL
feedback compensation bonding is that it consumes more PLL resources. Each
transceiver bank consumes one PLL and one master CGB.
In PLL feedback compensation bonding mode, the N counter (reference clock divider)
is bypassed in order to ensure that the reference clock skew is minimized between the
PLLs in the bonded group. Because the N counter is bypassed, the PLL reference clock
has a fixed value for any given data rate.
The PLL IP Core Parameter Editor window displays the required data rate in the
PLL reference clock frequency drop down menu.
Steps to implement a PLL Feedback Compensation Bonding Configuration
1. Instantiate the PLL IP core (ATX PLL or fPLL) you want to use in your design. Refer
to Instantiating the ATX PLL IP Core on page 342 or Instantiating the fPLL IP Core
on page 350 for detailed steps. Because the CMU PLL cannot drive the master
CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding.
2.
Configure the PLL IP core using the IP Parameter Editor.
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•
If you use the ATX PLL, set the following configuration settings:
—
—
Under the Master Clock Generation Block Tab
•
Enable Include Master Clock Generation Block.
•
Turn ON Enable Bonding Clock output ports.
•
Turn ON Enable feedback compensation bonding.
Under the Dynamic Reconfiguration Tab
•
•
Turn ON Enable dynamic reconfiguration
If you use the fPLL, set the following configuration settings:
—
Under the PLL Tab
•
—
Under the Master Clock Generation Block Tab
•
—
Set the PLL Feedback type to feedback compensation bonding.
Turn ON Enable Bonding Clock output ports.
Under the Dynamic Reconfiguration Tab
•
Turn ON Enable dynamic reconfiguration
3. Configure the Native PHY IP core using the IP Parameter Editor
•
Set the Native PHY IP core TX Channel bonding mode to either PMA
bonding or PMA/PCS bonding.
•
Turn ON Enable dynamic reconfiguration
4. Create a top level wrapper to connect the PLL IP cores to Native PHY IP core.
•
In this case, the PLL IP core has tx_bonding_clocks output bus with width
[5:0].
•
The Native PHY IP core has tx_bonding_clocks input bus with width [5:0]
multiplied by the number of channels in a transceiver bank. (six channels in
the transceiver bank).
•
Unlike the x6/xN bonding mode, for this mode, the PLL should be instantiated
multiple times. (One PLL is required for each transceiver bank that is a part of
the bonded group.) Instantiate a PLL for each transceiver bank used.
•
Connect the tx_bonding_clocks output from each PLL to (up to) six
channels in the same transceiver bank.
•
Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of transceiver channels used in the bonding group.
Steps to recalibrate the PLL after power up calibration
1.
Dynamic reconfigure the PLL to change the feedback from the master CGB to
feedback from PLL.
•
For ATX PLL, Read-Modify-Write 0x1 to offset address 0x110[2] of the ATX
PLL.
•
For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL.
2.
Recalibrate the PLL.
3.
After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure
the PLL to change the feedback to master CGB.
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•
For ATX PLL, Read-Modify-Write 0x0 to offset address 0x110[2] of the ATX
PLL.
•
For fPLL, Read-Modify-Write 0x0 to offset address 0x126[0] of the fPLL.
4. Recalibrate TX PMA of all the bonded channels driven by the ATX PLL or the fPLL.
Note:
For this 10-channel example, two ATX PLLs are instantiated. Six channels of the
tx_bonding_clocks on the Native PHY IP core are connected to the first ATX PLL
and the remaining four channels are connected to the second ATX PLL's
tx_bonding_clock outputs.
Related Links
•
ATX PLL Recalibration on page 561
•
Fractional PLL Recalibration on page 561
•
PMA Recalibration on page 562
3.11.3 Implementing PLL Cascading
In PLL cascading, the output of the first PLL feeds the input reference clock to the
second PLL.
For example, if the input reference clock has a fixed frequency, and the desired data
rate was not an integer multiple of the input reference clock, the first PLL can be used
to generate the correct reference clock frequency. This output is fed as the input
reference clock to the second PLL. The second PLL generates the clock frequency
required for the desired data rate.
The transceivers in Arria 10 devices support fPLL to fPLL cascading. For OTN and SDI
applications, there is a dedicated clock path for cascading ATX PLL to fPLL in Arria 10
production silicon. Only maximum two PLLs are allowed in the cascading chain.
Note:
When the fPLL is used as a cascaded fPLL (downstream fPLL), a user recalibration on
the fPLL is required. Refer to "User Recalibration" section in "Calibration" chapter for
more information.
Figure 197. PLL Cascading
fPLL (Cascade Source)
pll_refclk0
pll_powerdown
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pll_locked
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Steps to implement fPLL to fPLL cascading:
1.
Instantiate the fPLL IP core. Refer to Instantiating the fPLL IP Core on page 350
for detailed steps.
2.
Set the following configuration settings for the fPLL IP core in the Parameter
Editor:
•
Set the fPLL Mode to Cascade Source.
•
Set the Desired output clock frequency.
3. Instantiate the fPLL IP core (the second PLL in PLL cascading configuration). Refer
to Instantiating the fPLL IP Core on page 350 for detailed steps.
4. Configure the second fPLL IP core for the desired data rate and the reference clock
frequency. Set reference clock frequency for the second fPLL same as the output
frequency of the first fPLL.
5. Connect the fPLL IP core (cascade source) to fPLL IP core (transceiver PLL) as
shown in the above figure. Ensure the following connections:
•
The fPLL has an output port hssi_pll_cascade_clk. Connect this port to
the second fPLL's pll_refclk0 port.
6.
Set the source (upstream) fPLL bandwidth to Low setting and the destination
(downstream) fPLL bandwidth to High setting.
7.
If the input reference clock is available at device power-up, the first PLL will be
calibrated during the power-up calibration. The second PLL need to be
recalibrated. Refer to the User Recalibration section. If the input reference clock is
not available at device power-up, then re-run the calibration for the first PLL. After
the first PLL has been calibrated, re-calibrate the second PLL.
Notes:
•
No special configuration is required for the Native PHY instance.
•
ATX PLL to fPLL cascading mode is added to address the OTN and SDI jitter
requirement. In this mode, ATX PLL generates a relatively high and clean
reference frequency in fractional mode. The reference is driving the fPLL, which is
running in integer mode. Overall cascaded two PLLs, synthesize a needed
frequency for a given data rate.
Related Links
User Recalibration on page 556
3.11.4 Mix and Match Example
In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL
IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data
rates. The following design example illustrates PLL sharing and both bonded and nonbonded clocking configurations.
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Figure 198. Mix and Match Design Example
Transceiver Bank
ATX PLL
6.25 GHz
x6
MCGB
Transceiver Bank
xN
fPLL
5.15625 GHz
x1
Transceiver Bank
x1
fPLL, 625 MHz
Transceiver Bank
fPLL
2.5 GHz
ATX PLL
4 GHz
mcgb_aux_clk0
MCGB
Transceiver Bank
Legend
Interlaken12.5G
10GBASE-KR
1.25G/9.8G/10.3125G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
10GBASE-KR
10GBASE-KR
10GBASE-KR
10GBASE-KR
1.25G
1.25G
1.25G
1.25G
x1
fPLL, 5.15625 GHz
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
Interlaken 12.5G
x6
xN
1.25G GbE
1.25G GbE
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
PCIe Gen 1/2/3 x8
Unused
Unused
1.25G GbE
PCIe Gen 1/2/3
Unused channel
PLL Instances
In this example, two ATX PLL instances and five fPLL instances are used. Choose an
appropriate reference clock for each PLL instance. The IP Catalog lists the available
PLLs.
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Use the following data rates and configuration settings for PLL IP cores:
•
Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz
—
Enable the Master CGB and bonding output clocks.
•
Transceiver PLL instance 1: fPLL with output clock frequency of 5.1625 GHz
•
Transceiver PLL instance 2: fPLL with output clock frequency of 5.1625 GHz
•
Transceiver PLL instance 3: fPLL with output clock frequency of 0.625 GHz
—
•
Select the Use as Transceiver PLL option.
Transceiver PLL instance 4: fPLL with output clock frequency of 2.5 GHz
—
Select Enable PCIe* clock output port option.
—
Select Use as Transceiver PLL option.
•
—
•
•
Set Protocol Mode to PCIe Gen2.
Select the Use as Core PLL option
Set the Desired frequency to 500 MHz with a phase shift of 0 ps.
Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz
—
Enable Master CGB and bonding output clocks.
—
Select Enable PCIe clock switch interface option.
—
Set Number of Auxiliary MCGB Clock Input ports to 1.
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Native PHY IP Core Instances
In this example, four Transceiver Native PHY IP core instances and four 10GBASE-KR
PHY IP instances are used. Use the following data rates and configuration settings for
the PHY IPs:
•
•
•
•
12.5 Gbps Interlaken with a bonded group of 10 channels
—
Set the Interlaken 10x12.5 Gbps preset from the Arria 10 Transceiver Native
PHY IP core GUI.
—
Refer to Interlaken on page 92 for more details.
Custom multi-data rate 1.25G/9.8G/10.3125 Gbps non-bonded group of four
channels
—
Set the Number of data channels to 4.
—
Set TX channel bonding to Not Bonded.
—
Under the TX PMA tab, set the Number of TX PLL clock inputs per
channel to 3.
—
Under the RX PMA tab, set the Number of CDR reference clocks to 3.
1.25 Gbps Gigabit Ethernet with a non-bonded group of two channels
—
Set the GIGE-1.25Gbps preset from the Arria 10 Transceiver Native PHY IP
core GUI.
—
Change the Number of data channels to 2.
PCIe Gen3 with a bonded group of 8 channels
—
Set the PCIe PIPE Gen3x8 preset from the Arria 10 Transceiver Native PHY
IP core GUI.
—
Under TX Bonding options, set the PCS TX channel bonding master to
channel 5.
Note: The PCS TX channel bonding master must be physically placed in
channel 1 or channel 4 within a transceiver bank. In this example, the
5th channel of the bonded group is physically placed at channel 1 in the
transceiver bank.
—
•
Refer to PCI Express (PIPE) on page 227 for more details.
10.3125 Gbps 10GBASE-KR non-bonded group of 4 channels
—
Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY IP four times, with
one instance for each channel.
—
Refer to 10GBASE-KR PHY IP Core on page 133 for more details.
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Connection Guidelines for PLL and Clock Networks
•
For 12.5 Gbps Interlaken with a bonded group of 10 channels, connect the
tx_bonding_clocks to the transceiver PLL's tx_bonding_clocks output port.
Make this connection for all 10 bonded channels. This connection uses a master
CGB and the x6 / xN clock line to reach all the channels in the bonded group.
•
Connect the tx_serial_clk port of the first two instances of the 10GBASE-KR
PHY IP to the tx_serial_clk port of PLL instance 1 (fPLL at 5.1625 GHz). This
connection uses the x1 clock line within the transceiver bank.
•
Connect the tx_serial_clk port of the remaining two instances of the
10GBASE-KR PHY IP to the tx_serial_clk port of the PLL instance 2 (fPLL at
5.1625 GHz). This connection uses the x1 clock line within the transceiver bank.
•
Connect the three tx_serial_clk ports for the custom multi-data rate PHY IP as
follows:
—
•
Connect tx_serial_clk0 port to the tx_serial_clk port of PLL instance 2
(fPLL at 5.1625 GHz). This PLL instance is shared with the two 10GBASE-KR
PHY IP channels and also uses the x1 clock line within the transceiver bank.
Connect the 1.25 Gbps Gigabit Ethernet non-bonded PHY IP instance to the
tx_serial_clk port of the PLL instance 5. Make this connection twice, one for
each channel. This connection uses the x1 clock line within the transceiver bank.
•
Connect the PCIe Gen3 bonded group of 8 channels as follows:
—
Connect the tx_bonding_clocks of the PHY IP to the tx_bonding_clocks
port of the Transceiver PLL Instance 6. Make this connection for each of the 8
bonded channels.
—
Connect the pipe_sw_done of the PHY IP to the pipe_sw port of the
transceiver PLL instance 6.
—
Connect the pll_pcie_clk port of the PLL instance 5 to the PHY IP's
pipe_hclk_in port.
—
Connect tx_serial_clk port of the PLL instance 5 to the mcgb_aux_clk0
port of the PLL instance 6. This connection is required as a part of the PCIe
speed negotiation protocol.
3.11.5 Timing Closure Recommendations
Register mode is harder to close timing in Arria 10 devices. Intel recommends using
negative edge capture on the RX side for periphery to core transfers greater than 240
MHz. To be specific, capture on a negative edge clock in the core and then
immediately transfer to a positive edge clock.
•
Use PCLK clock network for frequencies up to 250 MHz.
•
Local routing is recommended for higher frequencies.
For core to periphery transfers on TX targeting higher frequencies (beyond 250 MHz),
Intel recommends using TX Fast Register mode as the PCS FIFO mode. This is the
mode with PCLK that should be used by default for most 10GbE 1588 modes and 9.8
Gbps/10.1376 Gbps CPRI mode.
•
You can use local routing to get up to 320 MHz in Register mode for the highest
speed grade.
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4 Resetting Transceiver Channels
To ensure that transceiver channels are ready to transmit and receive data, you must
properly reset the transceiver PHY. Intel recommends a reset sequence that ensures
the physical coding sublayer (PCS) and physical medium attachment (PMA) in each
transceiver channel initialize and function correctly. You can either use the Transceiver
PHY Reset Controller or create your own reset controller.
4.1 When Is Reset Required?
You can reset the transmitter (TX) and receiver (RX) data paths independently or
together. The recommended reset sequence requires reset and initialization of the PLL
driving the TX or RX channels, as well as the TX and RX datapaths. A reset is required
after any of the following events:
Table 244.
Reset Conditions
Event
Reset Requirement
Device power up and
configuration
Requires reset to the transceiver PHY and the associated PLLs to a known initialize state.
PLL reconfiguration
Requires reset to ensure that the PLL acquires lock and also to reset the PHY. Both the
PLL and the transmitter channel must be held in reset before performing PLL
reconfiguration.
PLL reference clock frequency
change
Requires reset to the PLL to ensure PLL lock. You must also reset the PHY.
PLL recalibration
Requires reset to the PLL to ensure PLL lock. You must also reset the PHY. Both the PLL
and the transmitter channel must be held in reset before performing PLL recalibration.
PLL lock loss or recovery
Requires reset after a PLL acquired lock from a momentary loss of lock. You must also
reset the PHY.
Channel dynamic
reconfiguration
Requires holding the channel in reset before performing a dynamic reconfiguration that
causes rate change. A PLL reset is not required during channel reconfiguration.
Optical module connection
Requires reset of RX to ensure lock of incoming data.
RX CDR lock mode change
Requires reset of the RX channel any time the RX clock and data recovery (CDR) block
switches from lock-to-reference to lock-to-data RX channel.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
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4.2 Transceiver PHY Implementation
Figure 199. Typical Transceiver PHY Implementation
clk_usrpin
tre_reset_in
reset_out_1
Transmit
PLL
Receiver
PMA
tre_reset_req
pll_powerdown
pll_locked
pll_cal_busy (1)
rx_analogreset_ack (2)
Transmitter
PMA
reset_req_1
tx_analogreset_ack (2)
Receiver
PCS
tre_reset_in
user reset
tx_cal_busy (1)
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
Transmitter
PCS
reset_out_0
(user-coded
or Intel IP)
tre_reset_req
clock
Transceiver PHY Instance
reset_req_0
Reset Controller
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
Transceiver Reset Sequencer Inferred Block
Optional
Notes:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.
(2) tx_analogreset_ack and rx_analogreset_ack are status signals from the Transceiver PHY IP core when these ports are enabled for manual user implementation of Model 2.
Transceiver Reset Endpoints—The Transceiver PHY IP core contains Transceiver
Reset Endpoints (TREs)(58).
Transceiver Reset Sequencer—The Quartus Prime software detects the presence of
TREs and automatically inserts only one Transceiver Reset Sequencer (TRS)(58). The
tx_analogreset and rx_analogreset requests from the reset controller (User
coded or Transceiver PHY Reset Controller) is received by the TREs. The TRE sends the
reset request to the TRS for scheduling. TRS schedules all the requested PMA resets
and sends them back to TREs. You can use either Transceiver PHY Reset Controller or
your own reset controller. However, for the TRS to work correctly, the required timing
duration must be followed. See Figure 200 on page 405 for required timing duration.
Note:
•
The TRS IP is an inferred block and is not visible in the RTL. You have no control
over this block.
CLKUSR connection—The clock to the TRS must be stable and free-running
(100-125 MHz). By default, the Quartus Prime software automatically connects the
TRS clock input to the CLKUSR pin on the device. If you are using the CLKUSR pin for
your own logic (feeding it to the core), you must instantiate
altera_a10_xcvr_clock_module:
altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk));
For more information about the CLKUSR pin, refer to the Arria 10 Pin Connection
Guidelines.
(58)
There is only one centralized TRS instantiated for one or more Native PHY.
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Note:
To successfully complete the calibration process, the reference clocks driving the PLLs
(ATX PLL, fPLL, CDR/CMU PLL) must be stable and free running at start of FPGA
configuration. Otherwise, recalibration will be necessary.
Related Links
•
Arria 10 Pin Connection Guidelines
•
Calibration on page 547
For more information about the calibration process
4.3 How Do I Reset?
You reset a transceiver PHY or PLL by integrating a reset controller in your system
design to initialize the PCS and PMA blocks. You can save time by using the Intelprovided Transceiver PHY Reset Controller IP core, or you can implement your own
reset controller that follows the recommended reset sequence. You can design your
own reset controller if you require individual control of each signal for reset or need
additional control or status signals as part of the reset functionality.
You can choose from two models for resetting the transceivers, based on your
applications:
•
Model 1—Default model (Minimum Assertion Time Requirement)
Choose the Arria 10 Default Settings preset for the Transceiver PHY Reset
Controller IP.
The chapter Transceiver Reset Control in Arria 10 Devices explains the default
model in detail.
•
Model 2—Acknowledgment model
This model uses an event-driven mechanism. The model is used for applications
with strict timing requirements.
4.3.1 Model 1: Default Model
4.3.1.1 Recommended Reset Sequence
How to Enable Model 1
Choose the Figure 200 on page 405 for the Transceiver PHY Reset Controller IP. This
populates the reset duration fields with the correct values required by the transceiver
reset sequencer (TRS).
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Figure 200. Arria 10 Default Settings Preset
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Figure 201. Transmitter and Receiver Reset Sequence
1
Transmit
or
Receive
2
FPGA Device
Power Up/Operation
3
Ensure Calibration
Completed
4
PLL,TX/RX Analog
Reset Asserted
5
Wait for required time and all gating
conditions and release PLL/Analog
resets
6
Associated PLL/CDR
Locked
7
Release TX/RX
Digital Reset
8
TX/RX Reset
Completed
4.3.1.1.1 Resetting the Transmitter During Device Operation
Follow this reset sequence to reset the PLL or the analog or digital blocks of the
transmitter at any point during the device operation. Use this reset sequence to
reestablish a link or after dynamic reconfiguration. The following steps detail the
transmitter reset sequence during device operation. The step numbers correspond to
the numbers in the following figure.
1.
Perform the following steps:
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a.
Assert tx_analogreset, pll_powerdown, and tx_digitalreset while
pll_cal_busy and tx_cal_busy are low.
b.
Deassert pll_powerdown after a minimum duration of 70 μs.
c.
Deassert tx_analogreset. This step can be done at the same time or after
you deassert pll_powerdown.
2. The pll_locked signal goes high after the TX PLL acquires lock. Wait for a
minimum of 70 μs after deasserting tx_analogreset to monitor the
pll_locked signal.
3.
Deassert tx_digitalreset, after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset
duration after tx_analogreset is deasserted.
Note: You must reset the PCS blocks by asserting tx_digitalreset, every time
you assert pll_powerdown and tx_analogreset.
Figure 202. Transmitter Reset Sequence During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
treq
treq
tx_analogreset
pll_powerdown
pll_locked
ttx_digitalreset (1)
tx_digitalreset
treq= 70 μs
1
2
3
Note:
(1) The Arria 10 Default setting presets tx_digitalreset to 70 μs.
(2) Area in gray is don’t care logic state.
Related Links
Arria 10 Device Datasheet
4.3.1.1.2 Resetting the Receiver During Device Operation
Follow this reset sequence to reset the analog or digital blocks of the receiver at any
point during the device operation. Use this reset to re-establish a link or after dynamic
reconfiguration.
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Clock Data Recovery in Auto Lock Mode
The step numbers correspond to the numbers in the following figure:
1.
Assert rx_analogreset and rx_digitalreset. Ensure that rx_cal_busy is
low. You must reset the PCS by asserting rx_digitalreset every time you
assert rx_analogreset.
2. Deassert rx_analogreset after a minimum duration of 70 μs.
3. Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before
deasserting rx_digitalreset.
Figure 203. Resetting the Receiver During Device Operation (Auto Mode)
Device Power Up
rx_cal_busy
treq
rx_analogreset
t LTD min 4 μs
rx_is_lockedtodata
rx_digitalreset
treq = 70 μs
Note:
1
2
3
rx_is_lockedtodata will toggle when there is no data at the receiver input.
rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted.
Clock Data Recovery in Manual Lock Mode
Use the clock data recovery (CDR) manual lock mode to override the default CDR
automatic lock mode depending on your design requirements.
Related Links
"Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP
Core User Guide.
Refer to the description of the rx_digitalreset signal in the "Top-Level Signals"
table for information about using the manual lock mode.
Control Settings for CDR Manual Lock Mode
Use the following control settings to set the CDR lock mode:
Table 245.
Control Settings for the CDR in Manual Lock Mode
rx_set_locktoref
rx_set_locktodata
0
0
Automatic
1
0
Manual-RX CDR LTR
X
1
Manual-RX CDR LTD
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Resetting the Transceiver in CDR Manual Lock Mode
The numbers in this list correspond to the numbers in the following figure, which
guides you through the steps to put the CDR in manual lock mode.
1.
Make sure that the calibration is complete (rx_cal_busy is low) and the
transceiver goes through the initial reset sequence. The rx_digitalreset and
rx_analogreset signals should be low. The rx_is_lockedtoref is a don't
care and can be either high or low. The rx_is_lockedtodata and rx_ready
signals should be high, indicating that the transceiver is out of reset. Alternatively,
you can start directly with the CDR in manual lock mode after the calibration is
complete.
2. Assert the rx_set_locktoref signal high to switch the CDR to the lock-toreference mode. The rx_is_lockedtodata status signal is deasserted. Assert
the rx_digitalreset signal high at the same time or after
rx_set_lockedtoref is asserted if you use the user-coded reset. When the
Transceiver PHY reset controller is used, the rx_digitalreset is automatically
asserted.
3. After the rx_digitalreset signal gets asserted, the rx_ready status signal is
deasserted.
4.
Assert the rx_set_locktodata signal high, tLTR_LTD_Manual (minimum 15 μs)
after the CDR is locked to reference. rx_is_locktoref should be high and
stable for a minimum tLTR_LTD_Manual (15 μs), before asserting
rx_set_locktodata. This is required to filter spurious glitches on
rx_is_lockedtoref. The rx_is_lockedtodata status signal gets asserted,
which indicates that the CDR is now set to LTD mode.
The rx_is_lockedtoref status signal can be a high or low and can be ignored
after asserting rx_set_locktodata high after the CDR is locked to reference.
5. Deassert the rx_digitalreset signal after a minimum of tLTD_Manual (4 μs).
6.
If you are using the Transceiver PHY Reset Controller, the rx_ready status signal
gets asserted after the rx_digitalreset signal is deasserted. This indicates
that the receiver is now ready to receive data with the CDR in manual mode.
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Figure 204. Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock
Mode
Control Signals
2
rx_set_locktoref
t LTD_Manual
rx_set_locktodata
rx_digitalreset
1
rx_analogreset
1
4
2
t LTD_Manual
5
Status Signals
rx_is_lockedtoref
1
rx_is_lockedtodata
1
rx_ready
1
4
2
4
6
3
rx_cal_busy
4.3.1.1.3 Resetting the Transceiver Channel During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset, pll_powerdown, tx_digitalreset,
rx_analogreset, and rx_digitalreset. Ensure that pll_cal_busy,
tx_cal_busy, and rx_cal_busy are low.
2.
Deassert pll_powerdown and tx_analogreset at the same time, after a
minimum duration of 70 μs.
3. The pll_locked signal goes high after the TX PLL acquires lock. Wait for a
minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked
signal.
4.
Deassert tx_digitalreset after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset
(minimum of 70 μs) duration after tx_analogreset is deasserted.
5.
Deassert rx_analogreset after deasserting tx_analogreset.
6.
Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before
deasserting rx_digitalreset.
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Figure 205. Resetting the Transceiver Channel During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
rx_cal_busy
treq
treq
tx_analogreset
pll_powerdown
pll_locked
tx_digitalreset
t rx_digitalreset min 70 μs
rx_analogreset
rx_is_lockedtodata
rx_digitalreset
treq = 70 μs
1
2
3
t LTD min 4 μs
4
5
6
4.3.1.1.4 Dynamic Reconfiguration of Channel Using the Default Model
TX Channel
The numbers in this list correspond to the numbers in the following figure.
1.
Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while
pll_cal_busy and tx_cal_busy are low.
2. Perform dynamic reconfiguration after minimum 70 μs of asserting
tx_analogreset.
3. Deassert pll_powerdown after performing a dynamic reconfiguration.
Deassert tx_analogreset. This step can be done at the same time or after you
deassert pll_powerdown.
4.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for
minimum 70 μs after deasserting tx_analogreset to monitor the pll_locked
signal.
5.
Deassert tx_digitalreset after pll_locked goes high. The
tx_digitalreset signal must stay asserted for a minimum ttx_digitalreset
duration after tx_analogreset is deasserted.
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Figure 206. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
treq
Legal
Reconfiguration
Window
treq
tx_analogreset
pll_powerdown
pll_locked
ttx_digitalreset (1)
tx_digitalreset
treq = 70 μs
1
2
3
4
5
Note:
(1) The Arria 10 Default setting presets ttx_digitalreset to 70 μs.
(2) Area in gray is don’t care zone.
RX Channel
The numbers in this list correspond to the numbers in the following figure.
1.
2.
Assert rx_analogreset and rx_digitalreset. Ensure that rx_cal_busy is
low. You must reset the PCS by asserting rx_digitalreset every time you
assert rx_analogreset.
Perform dynamic reconfiguration after minimum 70 μs of asserting
rx_analogreset.
3. Deassert rx_analogreset after performing dynamic reconfiguration.
4.
The rx_is_lockedtodata signal goes high after the CDR acquires lock.
5.
Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before
deasserting rx_digitalreset.
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Figure 207. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up
rx_cal_busy
treq
Legal
Reconfiguration
Window
rx_analogreset
t LTD min 4 μs
rx_is_lockedtodata
rx_digitalreset
treq = 70 μs
1
2
3
4
5
4.3.2 Model 2: Acknowledgment Model
The acknowledgment model uses an event-driven mechanism. It is used for
applications with strict timing requirements. Instead of waiting for a minimum
assertion time of 70 μs for tx_analogreset and rx_analogreset, you must wait
to receive the acknowledgment from the Transceiver Native PHY IP core to ensure
successful assertion and deassertion of the analog resets.
To enable the acknowledgment model, enable the following ports in the Transceiver
Native PHY IP core:
•
Enable the tx_analog_reset_ack port in the TX PMA
Figure 208. Enabling the tx_analog_reset_ack Port
•
Enable the rx_analog_reset_ack port in the RX PMA
Figure 209. Enabling the rx_analog_reset_ack Port
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Note:
tx_analog_reset_ack and rx_analog_reset_ack must be treated as
asynchronous signals. You must pass them through a synchronizer before sending
them to control logic.
4.3.2.1 Recommended Reset Sequence
4.3.2.1.1 Resetting the Transmitter During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while
pll_cal_busy and tx_cal_busy are low.
2. Wait for tx_analogreset_ack to go high, to ensure successful assertion of
tx_analogreset. tx_analogreset_ack goes high when TRS has successfully
completed the reset request for assertion.
a.
Deassert pll_powerdown after tpll_powerdown.
b.
Deassert tx_analogreset. This step can be done at the same time or after
you deassert pll_powerdown.
3. Wait for tx_analogreset_ack to go low, to ensure successful deassertion of
tx_analogreset. tx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
4.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for
tx_analogreset_ack to go low before monitoring the pll_locked signal.
5. Deassert tx_digitalreset a minimum ttx_digitalreset time after pll_locked
goes high.
Figure 210. Transmitter Reset Sequence During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
tx_analogreset_ack
pll_powerdown
pll_locked
ttx_digitalreset
tx_digitalreset
1
2
Note:
(1) Area in gray is don’t care logic state.
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4.3.2.1.2 Resetting the Receiver During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert rx_analogreset and rx_digitalreset while rx_cal_busy is low.
2.
Wait for rx_analogreset_ack to go high, to ensure successful assertion of
rx_analogreset. rx_analogreset_ack goes high when TRS has successfully
completed the reset request for assertion.
a.
Deassert rx_analogreset.
3. Wait for rx_analogreset_ack to go low, to ensure successful deassertion of
rx_analogreset. rx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
4.
The rx_is_lockedtodata signal goes high after the CDR acquires lock.
5. Ensure rx_is_lockedtodata is asserted for tLTD (minimum of 4 μs) before
deasserting rx_digitalreset.
Figure 211. Receiver Reset Sequence During Device Operation
Device Power Up
rx_cal_busy
rx_analogreset
rx_analogreset_ack
t LTD min 4 μs
rx_is_lockedtodata
rx_digitalreset
1
2
3
4
5
4.3.2.1.3 Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment
Model
The numbers in this list correspond to the numbers in the following figure.
1.
Assert tx_analogreset, pll_powerdown, and tx_digitalreset, while
pll_cal_busy and tx_cal_busy are low.
2. Wait for tx_analogreset_ack to go high, to ensure successful assertion of
tx_analogreset. tx_analogreset_ack goes high when TRS has successfully
completed the reset request for assertion.
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a.
Perform dynamic reconfiguration.
b.
Deassert pll_powerdown after tpll_powerdown.
c.
Deassert tx_analogreset. This step can be done at the same time or after
you deassert pll_powerdown.
3. Wait for tx_analogreset_ack to go low, to ensure successful deassertion of
tx_analogreset. tx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
4.
The pll_locked signal goes high after the TX PLL acquires lock. Wait for
tx_analogreset_ack to go low before monitoring the pll_locked signal.
5.
Deassert tx_digitalreset a minimum ttx_digitalreset time after pll_locked
goes high.
Figure 212. Dynamic Reconfiguration of Transmitter Channel During Device Operation
Device Power Up
pll_cal_busy
tx_cal_busy
tx_analogreset
tx_analogreset_ack
Legal
Reconfiguration
Window
pll_powerdown
pll_locked
ttx_digitalreset
tx_digitalreset
1
2
3 4
5
Note:
(1) Area in gray is don’t care zone.
4.3.2.1.4 Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
The numbers in this list correspond to the numbers in the following figure.
1.
Assert rx_analogreset and rx_digitalreset while rx_cal_busy is low.
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a.
Wait for rx_analogreset_ack to go high, to ensure successful assertion of
rx_analogreset. rx_analogreset_ack goes high when TRS has
successfully completed the reset request for assertion.
b.
Deassert rx_analogreset.
2. Wait for rx_analogreset_ack to go low, to ensure successful deassertion of
rx_analogreset. rx_analogreset_ack goes low when TRS has successfully
completed the reset request for deassertion.
3.
Ensure rx_is_lockedtodata signal goes high after the CDR is locked to data.
Wait for rx_analogreset_ack to go low before monitoring
rx_is_lockedtodata signal.
4.
Deassert rx_digitalreset after a minimum of tLTD (minimum of 4 μs) after
rx_is_lockedtodata goes high.
Figure 213. Dynamic Reconfiguration of Receiver Channel During Device Operation
Device Power Up
rx_cal_busy
rx_analogreset
rx_analogreset_ack
Legal
Reconfiguration
Window
rx_is_lockedtodata
t LTD min 4 μs
rx_digitalreset
1
2
3
4
4.3.3 Transceiver Blocks Affected by Reset and Powerdown Signals
You must reset the digital PCS each time you reset the analog PMA or PLL. However,
you can reset the digital PCS block alone.
Table 246.
Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver
Block
pll_powerdown
CMU PLL
Yes
ATX PLL
Yes
fPLL
Yes
CDR
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
Yes
Receiver
Standard PCS
Yes
Receiver
Enhanced PCS
Yes
continued...
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Transceiver
Block
pll_powerdown
tx_analogreset
tx_digitalreset
rx_analogreset
Receiver PMA
rx_digitalreset
Yes
Receiver PCIe
Gen3 PCS
Yes
Transmitter
Standard PCS
Yes
Transmitter
Enhanced PCS
Yes
Transmitter PMA
Yes
Transmitter PCIe
Gen3 PCS
Yes
Related Links
User Recalibration on page 556
4.4 Using the Transceiver PHY Reset Controller
Transceiver PHY Reset Controller is a configurable IP core that resets transceivers
mainly in response to PLL lock activity. You can use this IP core rather than creating
your own user-coded reset controller. You can define a custom reset sequence for the
IP core. You can also modify the IP cores's generated clear text Verilog HDL file to
implement custom reset logic.
The Transceiver PHY Reset Controller handles all transceiver reset sequencing and
supports the following options:
•
Separate or shared reset controls per channel in response to PLL lock activity
•
Separate controls for the TX and RX channels and PLLs
•
Synchronization of the reset inputs
•
Hysteresis for PLL locked status inputs
•
Configurable reset timing
•
Automatic or manual reset recovery mode in response to loss of PLL lock
You should create your own reset controller if the Transceiver PHY Reset Controller IP
does not meet your requirements, especially when you require independent
transceiver channel reset. The following figure illustrates the typical use of the
Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance
and the transmit PLL.
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Figure 214. Transceiver PHY Reset Controller System Diagram
Status Signals
Transmitter
PCS
tre_reset_in
reset_out_1
rx_analogreset_ack (2)
Receiver
PMA
tre_reset_req
tx_analogreset_ack (2)
tre_reset_in
Receiver
PCS
Transmitter
PMA
reset_req_1
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
reset_out_0
reset
Transceiver PHY Instance
tre_reset_req
clock
rx_ready
tx_analogreset
tx_digitalreset
Reset Controller rx_analogreset
rx_digitalreset
(user-coded
or Intel IP)
reset_req_0
tx_ready
pll_tx_cal_busy
pll_powerdown
pll_locked
tx_cal_busy (1)
Transmit
PLL
clk_usrpin
pll_cal_busy (1)
Transceiver Reset Sequencer Inferred Block
Optional
Note:
(1) You can logical OR the pll_cal_busy and tx_cal_busy signals.
pll_tx_cal_busy connects to the controller’s tx_cal_busy input port.
(2) The
. ports are inputs for user logic that implement Model 2. The ports can be used as status monitoring for Model 1 implementation.
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The Transceiver PHY Reset Controller IP core connects to the Transceiver PHY and the
Transmit PLL. The Transceiver PHY Reset Controller IP core receives status from the
Transceiver PHY and the Transmit PLL. Based on the status signals or the reset input,
it generates TX and RX reset signals to the Transceiver PHY and TX PLL.
The tx_ready signal indicates whether the TX PMA exits the reset state, and if the TX
PCS is ready to transmit data. The rx_ready signal indicates whether the RX PMA
exits the reset state, and if the RX PCS is ready to receive data. You must monitor
these signals to determine when the transmitter and receiver are out of the reset
sequence.
4.4.1 Parameterizing the Transceiver PHY Reset Controller IP
This section lists steps to configure the Transceiver PHY Reset Controller IP Core in the
IP Catalog. You can customize the following Transceiver PHY Reset Controller
parameters for different modes of operation by clicking Tools ➤ IP Catalog.
To parameterize and instantiate the Transceiver PHY Reset Controller IP core:
1. For Device Family, select your target device from the list.
2. Click Installed IP ➤ Library ➤ Interface Protocols ➤ Transceiver PHY ➤
Transceiver PHY Reset Controller.
3.
Select the options required for your design. For a description of these options,
refer to the Transceiver PHY Reset Controller Parameters.
4.
Click Finish. The wizard generates files representing your parameterized IP
variation for synthesis and simulation.
4.4.2 Transceiver PHY Reset Controller Parameters
The Quartus Prime software provides a GUI to define and instantiate a Transceiver PHY
Reset Controller to reset transceiver PHY and external PLL.
Table 247.
General Options
Name
Range
Description
Number of transceiver channels
1-1000
Specifies the number of channels that connect to
the Transceiver PHY Reset Controller IP core. The
upper limit of the range is determined by your
FPGA architecture.
Number of TX PLLs
1-1000
Specifies the number of TX PLLs that connect to
the Transceiver PHY Reset Controller IP core.
Input clock frequency
1-500 MHz
Input clock to the Transceiver PHY Reset Controller
IP core. The frequency of the input clock in MHz.
The upper limit on the input clock frequency is the
frequency achieved in timing closure.
Synchronize reset input
On /Off
When On, the Transceiver PHY Reset Controller
synchronizes the reset to the Transceiver PHY
Reset Controller input clock before driving it to the
internal reset logic. When Off, the reset input is
not synchronized.
Use fast reset for simulation
On /Off
When On, the Transceiver PHY Reset Controller
uses reduced reset counters for simulation.
continued...
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Name
Separate interface per
channel/PLL
Range
On /Off
Description
When On, the Transceiver PHY Reset Controller
provides a separate reset interface for each
channel and PLL.
TX PLL
Enable TX PLL reset control
On /Off
When On, the Transceiver PHY Reset Controller IP
core enables the reset control of the TX PLL. When
Off, the TX PLL reset control is disabled.
pll_powerdown duration
1-999999999
Specifies the duration of the PLL powerdown period
in ns. The value is rounded up to the nearest clock
cycle. The default value is 1000 ns.
Synchronize reset input for PLL
powerdown
On /Off
When On, the Transceiver PHY Reset Controller
synchronizes the PLL powerdown reset with the
Transceiver PHY Reset Controller input clock. When
Off, the PLL powerdown reset is not synchronized.
TX Channel
Enable TX channel reset control
On /Off
When On, the Transceiver PHY Reset Controller
enables the control logic and associated status
signals for TX reset. When Off, disables TX reset
control and status signals.
Use separate TX reset per channel
On /Off
When On, each TX channel has a separate reset.
When Off, the Transceiver PHY Reset Controller
uses a shared TX reset controller for all channels.
TX digital reset mode
Auto, Manual, Expose
Port
Specifies the Transceiver PHY Reset Controller
behavior when the pll_locked signal is
deasserted. The following modes are available:
• Auto—The associated tx_digitalreset
controller automatically resets whenever the
pll_locked signal is deasserted. Intel
recommends this mode.
• Manual—The associated tx_digitalreset
controller is not reset when the pll_locked
signal is deasserted, allowing you to choose
corrective action.
• Expose Port—The tx_manual signal is a toplevel signal of the IP core. You can dynamically
change this port to Auto or Manual. (1=
Manual , 0 = Auto)
tx_analogreset duration
1-999999999
Specifies the time in ns to continue to assert
tx_analoglreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset.
tx_digitalreset duration
1-999999999
Specifies the time in ns to continue to assert the
tx_digitalreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset. The default value for Model 2 is 20
ns.
pll_locked input hysteresis
0-999999999
Specifies the amount of hysteresis in ns to add to
the pll_locked status input to filter spurious
unreliable assertions of the pll_locked signal. A
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Name
Range
Description
value of 0 adds no hysteresis. A higher value filters
glitches on the pll_locked signal. Intel
recommends that the amount of hysteresis be
longer than tpll_lock_max_time.
RX Channel
Enable RX channel reset control
On /Off
When On, each RX channel has a separate reset
input. When Off, each RX channel uses a shared
RX reset input for all channels. This implies that if
one of the RX channels is not locked, all the other
RX channels will be held in reset until all RX
channels are locked. Digital reset stays asserted
until all RX channels have acquired lock.
Use separate RX reset per channel
On /Off
When On, each RX channel has a separate reset
input. When Off, uses a shared RX reset controller
for all channels.
RX digital reset mode
Auto, Manual, Expose
Port
Specifies the Transceiver PHY Reset Controller
behavior when the PLL lock signal is deasserted.
The following modes are available:
• Auto—The associated rx_digitalreset
controller automatically resets whenever the
rx_is_lockedtodata signal is deasserted.
rx_analogreset duration
1-999999999
•
Manual—The associated rx_digitalreset
controller is not reset when the
rx_is_lockedtodata signal is deasserted,
allowing you to choose corrective action.
•
Expose Port—The rx_manual signal is a toplevel signal of the IP core. If the core includes
separate reset control for each RX channel,
each RX channel uses its respective
rx_is_lockedtodata signal for automatic
reset control; otherwise, the inputs are ANDed
to provide internal status for the shared reset
controller.
Specifies the time in ns to continue to assert the
rx_analogreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 40 ns.
Note: Model 1 requires this to be set to 70 µs.
Select the Arria 10 Default Settings
preset.
rx_digitalreset duration
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1-999999999
Specifies the time in ns to continue to assert the
rx_digitalreset after the reset input and all
other gating conditions are removed. The value is
rounded up to the nearest clock cycle. The default
value is 4000 ns.
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4.4.3 Transceiver PHY Reset Controller Interfaces
This section describes the top-level signals for the Transceiver PHY Reset Controller IP
core.
The following figure illustrates the top-level signals of the Transceiver PHY Reset
Controller IP core. Many of the signals in the figure become buses if you choose
separate reset controls. The variables in the figure represent the following
parameters:
•
<n>—The number of lanes
•
<p>—The number of PLLs
Figure 215. Transceiver PHY Reset Controller IP Core Top-Level Signals
Generating the IP core creates signals and ports based on your parameter settings.
Transceiver PHY Reset Controller Top-Level Signals
PLL and
Calibration
Status
PLL
Control
Clock
and Reset
pll_locked[<p>–1:0]
pll_select[<p*n>–1:0] (1)
tx_cal_busy[<n>–1:0]
rx_cal_busy[<n>–1:0]
rx_is_lockedtodata[<n>–1:0]
tx_manual[<n>–1:0]
rx_manual[<n>–1:0]
tx_digitalreset[<n>–1:0]
tx_analogreset[<n>–1:0]
tx_ready[<n>–1:0]
rx_digitalreset[<n>–1:0]
rx_analogreset[<n>–1:0]
rx_ready[<n>–1:0]
pll_powerdown[<p>–1:0]
clock
reset
TX and RX
Resets and Status
PLL Powerdown
Note:
(1) n=1 for pll_select signal width when a single TX reset sequence is used for all channels.
Note:
PLL control is available when you enable the Expose Port parameter.
Table 248.
Top-Level Signals
This table describes the signals in the above figure in the order that they are shown in the figure.
Signal Name
Direction
Clock Domain
Description
pll_locked[<p>-1:0]
Input
Asynchronous
Provides the PLL locked status input from each PLL.
When asserted, indicates that the TX PLL is locked.
When deasserted, the PLL is not locked. There is one
signal per PLL.
pll_select[<p*n>-1:0]
Input
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Set to zero when not
using multiple PLLs.
When you select Use separate TX reset per
channel, this bus provides enough inputs to specify an
index for each pll_locked signal to listen to for each
channel. When Use separate TX reset per channel
is disabled, the pll_select signal is used for all
channels.
n=1 when a single TX reset sequence is used for all
channels.
tx_cal_busy[<n> -1:0]
Input
Asynchronous
This is the calibration status signal that results from
the logical OR of pll_cal_busy and tx_cal_busy
signals. The signal goes high when either the TX PLL or
Transceiver PHY initial calibration is active. It will not
be asserted if you manually re-trigger the calibration
IP. The signal goes low when calibration is completed.
This signal gates the TX reset sequence. The width of
this signals depends on the number of TX channels.
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Signal Name
Direction
Clock Domain
Description
rx_cal_busy[<n> -1:0]
Input
Asynchronous
This is calibration status signal from the Transceiver
PHY IP core. When asserted, the initial calibration is
active. When deasserted, calibration has completed. It
will not be asserted if you manually re-trigger the
calibration IP. This signal gates the RX reset sequence.
The width of this signals depends on the number of RX
channels.
rx_is_lockedtodata[<n
>-1:0]
Input
Synchronous to CDR
Provides the rx_is_lockedtodata status from each
RX CDR. When asserted, indicates that a particular RX
CDR is ready to receive input data. If you do not
choose separate controls for the RX channels, these
inputs are ANDed together internally to provide a
single status signal.
tx_manual[<n>-1:0]
Input
Asynchronous
This optional signal places tx_digitalreset
controller under automatic or manual control. When
asserted, the associated tx_digitalreset controller
logic does not automatically respond to deassertion of
the pll_locked signal. However, the initial
tx_digitalreset sequence still requires a one-time
rising edge on pll_locked before proceeding. When
deasserted, the associated tx_digitalreset
controller automatically begins its reset sequence
whenever the selected pll_locked signal is
deasserted.
rx_manual[<n> -1:0]
Input
Asynchronous
This optional signal places rx_digitalreset logic
controller under automatic or manual control. In
manual mode, the rx_digitalreset controller does
not respond to the assertion or deassertion of the
rx_is_lockedtodata signal. The
rx_digitalreset controller asserts rx_ready when
the rx_is_lockedtodata signal is asserted.
clock
Input
N/A
A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is
driven. If a free running clock is not available, hold
reset until the system clock is stable.
reset
Input
Asynchronous
Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs
are asserted. Holding the reset input signal asserted
holds all other reset outputs asserted. An option is
available to synchronize with the system clock. In
synchronous mode, the reset signal needs to stay
asserted for at least (2) clock cycles by default.
tx_digitalreset[<n>-1
:0]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when any of the following conditions is true:
• reset is asserted
•
•
•
pll_powerdown is asserted
pll_cal_busy is asserted
tx_cal_busy is asserted
•
PLL has not reached the initial lock (pll_locked
deasserted)
•
pll_locked is deasserted and tx_manual is
deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
tx_digitalreset.
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Signal Name
tx_analogreset[<n>-1:
0]
Direction
Output
Clock Domain
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Description
Analog reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when reset is asserted.
This signal follows pll_powerdown, which is
deasserted after pll_locked goes high.
tx_ready[<n>-1:0]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the TX reset sequence is
complete. This signal is deasserted while the TX reset
is active. It is asserted a few clock cycles after the
deassertion of tx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of TX channels.
rx_digitalreset[<n>
-1:0]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Digital reset for RX. The width of this signal depends
on the number of channels. This signal is asserted
when any of the following conditions is true:
• reset is asserted
•
•
•
rx_analogreset is asserted
rx_cal_busy is asserted
rx_is_lockedtodata is deasserted and
rx_manual is deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
rx_digitalreset.
rx_analogreset
[<n>-1:0]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Analog reset for RX. When asserted, resets the RX CDR
and the RX PMA blocks of the transceiver PHY. This
signal is asserted when any of the following conditions
is true:
• reset is asserted
•
rx_cal_busy is asserted
The width of this signal depends on the number of
channels.
rx_ready[<n>-1:0]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Status signal to indicate when the RX reset sequence is
complete. This signal is deasserted while the RX reset
is active. It is asserted a few clock cycles after the
deassertion of rx_digitalreset. Some protocol
implementations may require you to monitor this signal
prior to sending data. The width of this signal depends
on the number of RX channels.
pll_powerdown[<p>-1:0
]
Output
Synchronous to the
Transceiver PHY Reset
Controller input clock.
Asserted to power down a transceiver PLL circuit. When
asserted, the selected TX PLL is reset.
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Usage Examples for pll_select
•
If a single channel can switch between three TX PLLs, the pll_select signal
indicates which one of the selected three TX PLL's pll_locked signal is used to
communicate the PLL lock status to the TX reset sequence. In this case, to select
the 3-bits wide pll_locked port, the pll_select port is 2-bits wide.
•
If three channels are instantiated with three TX PLLs and with a separate TX reset
sequence per channel, the pll_select field is 6-bits wide (2-bits per channel).
In this case, pll_select [1:0] represents channel 0, pll_select[3:2]
represents channel 1, and pll_select[5:4] represents channel 2. For each
channel, a separate pll_locked signal indicates the PLL lock status.
•
If three channels are instantiated with three TX PLLs and with a single TX reset
sequence for all three channels, then pll_select field is 2-bits wide. In this
case, the same pll_locked signal indicates the PLL lock status for all three
channels.
•
If one channel is instantiated with one TX PLL, pll_select field is 1-bit wide.
Connect pll_select to logic 0.
•
If three channels are instantiated with only one TX PLL and with a separate TX
reset sequence per channel, the pll_select field is 3-bits wide. In this case,
pll_select should be set to 0 since there is only one TX PLL available.
4.4.4 Transceiver PHY Reset Controller Resource Utilization
This section describes the estimated device resource utilization for two configurations
of the transceiver PHY reset controller. The exact resource count varies by Quartus
Prime version number, as well as by optimization options.
Table 249.
Reset Controller Resource Utilization
Configuration
Combination ALUTs
Logic Registers
Single transceiver channel
approximately 50
approximately 50
Four transceiver channels, shared TX reset, separate RX resets
approximately 100
approximately 150
4.5 Using a User-Coded Reset Controller
You can design your own user-coded reset controller instead of using Transceiver PHY
Reset Controller. Your user-coded reset controller must provide the following
functionality for the recommended reset sequence:
•
A clock signal input for your reset logic
•
Holds the transceiver channels in reset by asserting the appropriate reset control
signals
•
Checks the PLL status (for example, checks the status of pll_locked and
pll_cal_busy)
Note:
You must ensure a stable reference clock is present at the PLL transmitter before
releasing pll_powerdown.
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4.5.1 User-Coded Reset Controller Signals
Refer to the signals in the following figure and table for implementation of a usercoded reset controller.
Figure 216. User-Coded Reset Controller, Transceiver PHY, and TX PLL Interaction
clock
User-Coded
Reset
Controller
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
pll_powerdown
pll_locked
pll_cal_busy
tx_cal_busy
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
Transceiver PHY Instance
Transmitter
PCS
Receiver
PCS
Transmitter
PMA
Receiver
PMA
You can logical OR the pll_cal_busy
and tx_cal_busy signals.
Transmit
PLL
Table 250.
User-coded Reset Controller, Transceiver PHY, and TX PLL Signals
Signal Name
Direction
Description
pll_powerdown
Output
Resets the TX PLL when asserted high.
tx_analogreset
Output
Resets the TX PMA when asserted high.
tx_digitalreset
Output
Resets the TX PCS when asserted high.
rx_analogreset
Output
Resets the RX PMA when asserted high.
rx_digitalreset
Output
Resets the RX PCS when asserted high.
clock
Input
Clock signal for the user-coded reset controller. You can use the system
clock without synchronizing it to the PHY parallel clock. The upper limit on
the input clock frequency is the frequency achieved in timing closure.
pll_cal_busy
Input
A high on this signal indicates the PLL is being calibrated.
pll_locked
Input
A high on this signal indicates that the TX PLL is locked to the ref clock.
tx_cal_busy
Input
A high on this signal indicates that TX calibration is active. If you have
multiple PLLs, you can OR their pll_cal_busy signals together.
rx_is_lockedtodata
Input
A high on this signal indicates that the RX CDR is in the lock-to-data (LTD)
mode.
rx_cal_busy
Input
A high on this signal indicates that RX calibration is active.
rx_is_lockedtoref
Input
A high on this signal indicates that the RX CDR is in the lock-to-reference
(LTR) mode. This signal may toggle or be deasserted when the CDR is in
LTD mode.
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4.6 Combining Status or PLL Lock Signals
You can combine multiple PHY status signals before feeding into the reset controller as
shown below.
Figure 217. Combining Multiple PHY Status Signals
tx_cal_busy signals
from channels
Note:
To reset controller
tx_cal_busy input port
AND
OR
This configuration also applies to the rx_cal_busy signals.
When using multiple PLLs, you can logical AND the pll_locked signals feeding the
reset controller. Similarly, you can logical OR the pll_cal_busy signals to the reset
controller tx_cal_busy port as shown below.
Figure 218. Multiple PLL Configuration
pll_lock signals
from PLLs
pll_cal_busy and
tx_cal_busy
signals
AND
AND
OR
To reset controller
pll_locked input port
To reset controller
tx_cal_busy input port
Resetting different channels separately requires multiple reset controllers. For
example, a group of channels configured for Interlaken requires a separate reset
controller from another group of channels that are configured for optical
communication.
4.7 Timing Constraints for Bonded PCS and PMA Channels
For designs that use TX PMA and PCS Bonding, the digital reset signal
(tx_digitalreset) to all TX channels within a bonded group must meet a
maximum skew tolerance imposed by physical routing. This skew tolerance is one-half
the TX parallel clock cycle (tx_clkout). This requirement is not necessary for TX
PMA Bonding or for RX PCS channels.
Note:
If the design is not able to meet the maximum skew tolerance requirement with a
positive margin, Intel recommends reassigning the channels locations that are not
adjacent to the PCIe Hard IP block.
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Figure 219. Physical Routing Delay Skew in Bonded Channels
FPGA Fabric
PHY Reset
Controller
tx_digitalreset
TX
Channel[ n - 1]
TX
Channel[1]
Bonded TX
Channels
TX
Channel[0]
You must provide a Synopsys Design Constraint (SDC) for the reset signals to
guarantee that your design meets timing requirements. The Quartus Prime software
generates an .sdc file when you generate the Transceiver Native PHY IP core.
This .sdc contains basic false paths for most asynchronous signals, including resets.
In the case of bonded designs, this file contains examples for maximum skew on
bonded designs. This .sdc file contains an example false_path and an example
max_skew constraint for the tx_digitalreset signals.
All modified IP constraints from a generated .sdc file must be moved to the project’s
main .sdc file, because changes will be lost if the IP is regenerated.
This skew is present whether you tie all tx_digitalresets together, or you control
them separately. If your design includes the Transceiver PHY Reset Controller IP core,
you can substitute your instance and interface names for the generic names shown in
the example.
Example 1.
SDC Constraint for TX Digital Reset When Bonded Clocks Are Used
set_max_skew -from *<IP_INSTANCE_NAME> *tx_digitalreset*r_reset
-to *pld_pcs_interface* <1/2 coreclk period in ps>
In the above example, you must make the following substitutions:
•
<IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance
or PHY IP instance
•
<½ coreclk period in ps>—substitute half of the clock period of your design in
picoseconds
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If your design has custom reset logic, replace the
*<IP_INSTANCE_NAME>*tx_digitalreset*r_reset with the source register for
the TX PCS reset signal, tx_digitalreset.
For more information about the set_max_skew constraint, refer to the SDC and
Timing Analyzer API Reference Manual.
Related Links
SDC and Timing Analyzer API Reference Manual
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5 Arria 10 Transceiver PHY Architecture
5.1 Arria 10 PMA Architecture
The Physical Medium Attachment (PMA) acts as the analog front end for the Arria 10
transceivers.
The PMA receives and transmits high-speed serial data depending on the transceiver
channel configuration. All serial data transmitted and received passes through the
PMA.
5.1.1 Transmitter
The transmitter takes the parallel data and serializes it to create a high-speed serial
data stream. The transmitter portion of the PMA is composed of the transmitter
serializer and the transmitter buffer. The serializer clock is provided from the
transmitter PLL.
Figure 220. Transmitter PMA Block Diagram
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Serial
Clock
Parallel
Data
Serializer
Parallel
Clock
Transmitter
PCS
Clock
Generation
Block
Parallel
Data
FPGA
Fabric
Transmitter
PLL
Input
Reference
Clock
5.1.1.1 Serializer
The serializer converts the incoming low-speed parallel data from the transceiver PCS
or FPGA fabric to high-speed serial data and sends the data to the transmitter buffer.
The channel serializer supports the following serialization factors: 8, 10, 16, 20, 32,
40, and 64.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
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Figure 221. Serializer Block
The serializer block sends out the least significant bit (LSB) of the input data first.
Dn
LSB
D0
D1
D2
Dn
Serial
Data
Serializer
Serial
Clock
Parallel
Clock
D2
Parallel
Data
D1
D0
5.1.1.2 Transmitter Buffer
The transmitter buffer includes the following circuitry:
•
High Speed Differential I/O
•
Programmable differential output voltage (VOD)
—
•
Main tap
Programmable four-tap pre-emphasis circuitry
—
Two pre-cursor taps
—
Two post-cursor taps
•
Power distribution network (PDN) induced inter-symbol interference (ISI)
compensation
•
Internal termination circuitry
•
Receiver detect capability to support PCI Express and Quick Path Interconnect
(QPI) configurations
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Figure 222. Transmitter Buffer
To Serial Data
Output Pins
(tx_serial_data)
Programmable
Pre-Emphasis
and VOD
R1*
Receiver
Detect
On-Chip
Termination
R1*
85Ω, 100Ω, OFF
TX
V CM
R1* - Half of the actual on-chip termination selected.
5.1.1.2.1 High Speed Differential I/O
To improve performance, the Arria 10 transmitter uses a new architecture in the
output buffer—High Speed Differential I/O. You should select "High Speed Differential
I/O" for I/O standard of Arria 10 transmitter pin in Quartus Prime Assignment Editor
or QSF file.
5.1.1.2.2 Programmable Output Differential Voltage
You can program the differential output voltage (output swing) to handle different
channel losses and receiver requirements. There are 31 differential VOD settings up to
VCCT power supply level. The step size is 1/30 of the VCCT power supply level.
Figure 223. VOD (Differential) Signal Level
Differential Waveform
+VP
V OD (Differential)
0 V Differential
–V N
V OD (Differential) = V P - V N
Related Links
•
XCVR_A10_RX_TERM_SEL on page 567
•
For more information, refer to Arria 10 Pre-Emphasis and Output Swing Settings
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5.1.1.2.3 Programmable Pre-Emphasis
Pre-emphasis can maximize the eye at the far-end receiver. The programmable preemphasis module in each transmit buffer amplifies high frequencies in the transmit
data signal, to compensate for attenuation in the transmission media.
The pre-tap pre-emphasizes the bit before the transition and de-emphasizes the
remaining bits. A different polarity on pre-tap does the opposite.
Table 251.
Pre-Emphasis Taps
All four pre-emphasis taps provide inversion control, shown by negative values.
Pre-Emphasis Tap
Number of Settings
Channel Loss Compensation (dB)
Second pre-tap
15
2.31
First pre-tap
33
6.62
First post-tap
51
15.56
Second post-tap
25
4.44
You can set pre-emphasis taps through the Quartus Assignment Editor, the Avalon-MM
registers, and the QSF settings.
Related Links
For more information, refer to Arria 10 Pre-Emphasis and Output Swing Settings
5.1.1.2.4 Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI)
compensation
Arria 10 Transmitter driver includes a compensation circuitry to reduce PDN induced
ISI jitter. You can enable this compensation circuitry to reduce jitter through QSF
setting, Quartus Assignment Editor or Avalon-MM interface. The power consumption
will increase when you enable the compensation.
5.1.1.2.5 Programmable Transmitter On-Chip Termination (OCT)
Transmitter buffers include programmable on-chip differential termination of 85Ω,
100Ω, or OFF. You can set the OCT value through the Quartus Assignment Editor and
the Avalon-MM registers.
Related Links
Arria 10 Register Map
5.1.2 Receiver
The receiver deserializes the high-speed serial data, creates a parallel data stream for
either the receiver PCS or the FPGA fabric, and recovers the clock information from
the received data.
The receiver portion of the PMA is comprised of the receiver buffer, the clock data
recovery (CDR) unit, and the deserializer.
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Figure 224. Receiver PMA Block Diagram
Receiver PMA
Receiver Serial
Differential Input
Data
Receiver
Buffer
Serial
Data
CDR
Serial
Data
Deserializer
Parallel
Data
Receiver
PCS
Parallel Data
to FPGA Core
Serial Clock
Parallel Clock
5.1.2.1 Receiver Buffer
The receiver input buffer receives serial data from rx_serial_data and feeds the
serial data to the clock data recovery (CDR) unit and deserializer.
Figure 225. Receiver Buffer
CTLE
From Serial Data
Input Pins
(rx_serial_data)
VGA
RX
Termination
85Ω, 100Ω, OFF
To CDR
and DFE
Adaptive Parametric
Tuning Engine
RX
V CM
The receiver buffer supports the following features:
•
Programmable common mode voltage (VCM)
•
Programmable differential On-Chip Termination (OCT)
•
Signal Detector
•
Continuous Time Linear Equalization (CTLE)
•
Variable Gain Amplifiers (VGA)
•
Adaptive Parametric Tuning Engine
•
Decision Feedback Equalization (DFE)
5.1.2.1.1 Programmable Common Mode Voltage (VCM)
The receiver buffer has on-chip biasing circuitry to establish the required VCM at the
receiver input.
The Quartus Prime software automatically chooses the optimal setting for RX VCM.
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Note:
On-chip biasing circuitry is available only if you select OCT. If you select external
termination, you must implement off-chip biasing circuitry to establish the VCM at the
receiver input buffer.
Manual VCM adjustment is not supported and is only adjusted by calibrations.
5.1.2.1.2 Programmable Differential On-Chip Termination (OCT)
Receiver buffers include programmable on-chip differential termination of 85Ω, 100Ω,
or OFF.
You can disable OCT and use external termination. If you select external termination,
the receiver common mode is tri-stated. Common mode is based on the external
termination connection. You will also need to implement off-chip biasing circuitry to
establish the VCM at the receiver buffer.
5.1.2.1.3 Signal Detector
You can enable the optional signal threshold detection circuitry. If enabled, this option
senses whether the signal level present at the receiver input buffer is above the signal
detect threshold voltage that you specified in the assignment editor.
5.1.2.1.4 Continuous Time Linear Equalization (CTLE)
The CTLE boosts the signal that is attenuated due to channel characteristics. Each
receiver buffer has independently programmable equalization circuits. These
equalization circuits amplify the high-frequency component of the incoming signal by
compensating for the low-pass characteristics of the physical medium. The CTLE can
support both DC and AC gain.
DC gain circuitry provides an equal amplification to the incoming signal across the
frequency spectrum. AC gain circuitry provides amplification to the high-frequency
spectrum gain of the incoming signal.
Arria 10 transceivers support dual mode CTLE.
High Gain Mode
High gain mode supports data rate up to 17.4 Gbps. This mode provides both AC and
DC gain. There are two bandwidth settings available for this mode.
•
Full Bandwidth—This mode has a peaking frequency of 6.25 GHz offering AC gain
around 15 dB.
•
Medium Bandwidth—This mode has a peaking frequency of 3.125 GHz offering AC
gain around 20 dB.
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Figure 226. CTLE DC and AC Gain Conceptualization
Gain
(dB)
DC Gain
Control
Frequency
AC Gain
Control
Gain
(dB)
Frequency
Note:
Final equalization curves will be available in the Arria 10 device datasheet.
High Data Rate Mode
High Data Rate Mode is a low power mode that supports data rates up to 25.8 Gbps. It
is the default mode if none of the modes are selected in the Quartus Assignment
Editor or Quartus Settings File (.qsf). This mode provides an alternative path for high
gain mode. High Data Rate Mode can be used to compensate for the loss similar to
CEI 28G VSR. High data rate mode supports four bandwidth modes: Full, threefourths, one-half, and one-fourth bandwidth modes. Full bandwidth mode can provide
AC peaking at approximately 8 dB at a peaking frequency of 14 GHz. High data rate
mode can be operated in three-fourths, one-half, and one-fourth bandwidth with 9
GHz, 5 GHz, and 2.5 GHz peaking frequencies. In high data rate mode, AC gain values
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and DC gain values cannot be controlled individually as done in high gain mode. The
recommended AC gain values in high data rate mode include the appropriate setting
of DC gain to get the required peaking at respective peaking frequencies.
CTLE can only be supported in manual mode. CTLE mode and CTLE gain can be set
through Quartus Assignment Editor or Quartus Settings File and Avalon MM registers.
Related Links
•
How to Enable CTLE and DFE on page 440
•
Arria 10 Device Datasheet
•
Arria 10 Register Map
5.1.2.1.5 Variable Gain Amplifier (VGA)
Arria 10 channels have a variable gain amplifier to optimize the signal amplitude prior
to the CDR sampling. VGA can only be operated in manual mode. VGA gain can be
selected through Quartus Assignment Editor or Quartus Setting File (qsf) or the
Avalon MM register. You must set VGA manually for all combinations of CTLE and DFE
modes.
Figure 227. VGA Frequency Response for Different Gain Settings
6
Magnitude
(dB)
-4
Frequency (Hz)
Related Links
How to Enable CTLE and DFE on page 440
5.1.2.1.6 Decision Feedback Equalization (DFE)
DFE amplifies the high frequency components of a signal without amplifying the noise
content. It compensates for inter-symbol interference (ISI). DFE minimizes postcursor ISI by adding or subtracting weighted versions of the previously received bits
from the current bit. DFE works in synchronization with the TX pre-emphasis and
downstream RX CTLE. This enables the RX CDR to receive the correct data that was
transmitted through a lossy and noisy backplane.
The DFE advantage over CTLE is improved Signal to Noise Ratio (SNR). DFE amplifies
the power of the high frequency components without amplifying the noise power.
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Figure 228. Signal ISI
ISI+
ISI-
Precursor
Cursor
Postcursor
Notes:
• An ideal pulse response is a single data point at the cursor.
• Real world pulse response is non-zero before the cursor (precursor) and after the
cursor (postcursor).
• ISI occurs when the data sampled at precursor or postcursor is not zero.
The DFE circuit stores delayed versions of the data. The stored bit is multiplied by a
coefficient and then summed with the incoming signal. The polarity of each coefficient
is programmable.
The DFE architecture supports eleven fixed taps.
The eleven fixed taps translate to the DFE capable of removing the ISI from the next
11 bits, beginning from the current bit.
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Figure 229. Channel Pulse Response
Signal at the
Channel Input
V
Region of Influence
for Fixed Taps
Transmission Medium
Signal at the
Channel Output
1 UI
Note:
t
The pulse at the output of the channel shows a long decaying tail. Frequencydependent losses and quality degradation affects other signals.
Supported modes for DFE:
•
Disabled Mode:
—
•
Manual Mode:
—
•
DFE disabled mode is similar to DFE manual mode, except all DFE tap values
in this mode are set to zero. DFE tap values can be set in Assignment
Editor/.qsf or using Avalon MM interface.
In this mode, manual DFE tap values can be set in Assignment Editor/.qsf or
using Avalon MM interface.
Adaptation Enabled Mode:
—
In this adaptation mode, DFE tap values are controlled by the Adaptive
Parametric Tuning Engine. This mode uses the converged DFE tap values given
by the Adaptive Parametric Tuning Engine.
Related Links
How to Enable CTLE and DFE on page 440
5.1.2.1.7 How to Enable CTLE and DFE
Table 252.
Summary of Receiver Equalization Modes
Receiver Equalization
Modes
CTLE adaptation mode
Manual, Triggered (use the triggered mode for PCIe Gen3
only)
DFE adaptation mode
Adaptation enabled, Manual, Disabled
Number of fixed DFE taps
3, 7, 11
Follow these steps to trigger DFE adaptation:
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1.
Request user access to the internal configuration bus by writing 0x2 to offset
address 0x0[7:0].
2. Monitor and wait for avmm_waitrequest to be deasserted (logic low) if "Seperate
reconfig_waitrequest from PreCISE" option is disabled. Otherwise, monitor
and wait for register bit 0x281 bit[2] to go low if "Seperate
reconfig_waitrequest from PreCISE" and "Enable control and status
registers" option is enabled.
3. Select adaptation control by Read-Modify-Write 0x1 to bit[4] of address 0x149.
4. Enable adaptation trigger by Read-Modify-Write 0x1 to bit[6] of address 0x100.
5. Release the internal configuration bus to PreSICE by writing 0x1 to offset address
0x0[7:0].
6. Repeat step 2.
7. Monitor DFE adaptation completion by checking register bit 0x100 bit[6] to go low.
This confirms DFE trigger adaptation routine is complete.
Related Links
Analog Parameter Settings on page 563
Configuration Methods
Configure the modes using one of the following methods:
Method 1 - Using Arria 10 Transceiver Native PHY IP Core
1. Select the CTLE/DFE mode in the RX PMA tab of the PHY IP Core
2.
Compile the design
3.
Choose one the following:
•
If CTLE or DFE is in Manual mode, set the CTLE gain value or DFE taps using
one of the following ways:
a.
Assignment Editor/.qsf- Recompile the design to make these values
effective.
Refer to Analog Parameter Settings for more details about Receiver
Equalization Settings.
b.
Avalon-MM (AVMM) Interface - Value written through AVMM interface take
precedence over values defined in Assignment Editor. Use this method to
dynamically set values and hence avoid re-compilation.
Refer to Arria 10 Transceiver Register Map for more details on AVMM
interface and to perform dynamic read/write.
Method 2 - Using AVMM Interface
1.
Any changes you make using AVMM interface take precedence over what was
configured in Native PHY IP GUI and/or Assignment Editor.
a.
For CTLE and DFE in Manual mode, set the CTLE gain value or DFE Taps using
the reconfiguration interface. The values are written dynamically and do not
require design re-compilation.
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Refer to Arria 10 Register Map for details on the specific registers that set the
CTLE gain values/DFE taps.
b.
For dynamically changing DFE and CTLE Adaptation modes, refer to CTLE
Settings in Triggered Adaptation Mode, Arria 10 Register Map and Arria 10
Adaptation Tool for the list of adaptation registers. Use the reconfiguration
interface to change the register settings.
Note: You must set VGA manually for all combinations of CTLE mode and DFE
modes.
Related Links
•
CTLE Settings in Triggered Adaptation Mode
•
Arria 10 Register Map
Arria 10 Adaptation Tool is a separate tab in the Arria 10 Register Map.
5.1.2.2 Clock Data Recovery (CDR) Unit
The PMA of each channel includes a channel PLL that you can configure as a receiver
clock data recovery (CDR) for the receiver. You can also configure the channel PLL of
channels 1 and 4 as a clock multiplier unit (CMU) PLL for the transmitter in the same
bank.
Figure 230. Channel PLL Configured as CDR
Channel PLL
rx_is_lockedtodata
LTR/LTD
Controller
Recovered Clock
/2
Phase
Detector
(PD)
rx_serial_data
refclk
N
Divider
(1)
Phase
Frequency
Detector
(PFD)
Down
Up
Up
Charge Pump
&
Loop Filter
Down
Voltage
Controlled
Oscillator
(VCO)
Lock
Detect
L
Divider
(1)
Serial Clock
rx_is_lockedtoref
M
Divider
(1)
Note:
1. The Quartus® Prime Pro Edition software automatically chooses the optimal values.
5.1.2.2.1 Lock-to-Reference Mode
In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input
reference clock. The PFD controls the charge pump that tunes the VCO in the CDR.
The rx_is_lockedtoref status signal is asserted active high to indicate that the
CDR has locked to the phase and frequency of the receiver input reference clock.
Note:
The phase detector (PD) is inactive in LTR mode.
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5.1.2.2.2 Lock-to-Data Mode
During normal operation, the CDR must be in LTD mode to recover the clock from the
incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data
at the receiver input. Depending on the phase difference between the incoming data
and the CDR output clock, the PD controls the CDR charge pump that tunes the VCO.
Note:
The PFD is inactive in LTD mode. The rx_is_lockedtoref status signal toggles
randomly and is not significant in LTD mode.
After switching to LTD mode, the rx_is_lockedtodata status signal is asserted.
The actual lock time depends on the transition density of the incoming data and the
parts per million (ppm) difference between the receiver input reference clock and the
upstream transmitter reference clock. The rx_is_lockedtodata signal toggles until
the CDR sees valid data; therefore, you should hold receiver PCS logic in reset
(rx_digitalreset) for a minimum of 4 µs after rx_is_lockedtodata remains
continuously asserted.
5.1.2.2.3 CDR Lock Modes
You can configure the CDR in either automatic lock mode or manual lock mode. By
default, the Quartus Prime software configures the CDR in automatic lock mode.
Automatic Lock Mode
In automatic lock mode, the CDR initially locks to the input reference clock (LTR
mode). After the CDR locks to the input reference clock, the CDR locks to the
incoming serial data (LTD mode) when the following conditions are met:
•
The signal threshold detection circuitry indicates the presence of valid signal levels
at the receiver input buffer when rx_std_signaldetect is enabled.
•
The CDR output clock is within the configured ppm frequency threshold setting
with respect to the input reference clock (frequency locked).
•
The CDR output clock and the input reference clock are phase matched within
approximately 0.08 unit interval (UI) (phase locked).
If the CDR does not stay locked to data because of frequency drift or severe amplitude
attenuation, the CDR switches back to LTR mode.
Manual Lock Mode
The PPM detector and phase relationship detector reaction times can be too long for
some applications that require faster CDR lock time. You can manually control the CDR
to reduce its lock time using two optional input ports (rx_set_locktoref and
rx_set_locktodata).
Table 253.
Relationship Between Optional Input Ports and the CDR Lock Mode
CDR Lock Mode
rx_set_locktoref
rx_set_locktodata
0
0
Automatic
1
0
Manual-RX CDR LTR
X
1
Manual-RX CDR LTD
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5.1.2.3 Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes the data using the low-speed
parallel recovered clock. The deserializer forwards the deserialized data to the receiver
PCS or FPGA fabric.
The deserializer supports the following deserialization factors: 8, 10, 16, 20, 32, 40,
and 64.
Figure 231. Deserializer Block Diagram
The deserializer block sends out the LSB of the input data first.
Dn
Serial
Data
LSB
Dn
D2
D1
Deserializer
D0
Serial
Clock
Parallel
Data
D2
Parallel
Clock
D1
D0
5.1.3 Loopback
The PMA supports serial, diagnostic, and reverse loopback paths.
Figure 232. Serial Loopback Path
The serial loopback path sets the CDR to recover the data from serializer while data from receiver serial input
pin is ignored by CDR. The transmitter buffer sends data normally.
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Parallel
Data
Serializer
Parallel
Clock
Serial
Loopback
Serial
Clock
Transmitter
PCS
Parallel Data
from FPGA Core
Clock
Generation
Block
Input
Reference
Clock
Transmitter
PLL
Receiver PMA
Receiver Serial
Differential Input
Data
Receiver
Buffer
Serial
Data
CDR
Serial
Data
Serial Clock
Parallel Clock
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Deserializer
Parallel
Data
Receiver
PCS
Parallel Data
to FPGA Core
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Figure 233. Reverse Serial Loopback Path/Pre CDR
Transmitter PMA
Transmitter Serial
Differential Output
Data
Serial
Data
Transmitter
Buffer
Diagnostic
Loopback
Parallel
Data
Serializer
Parallel
Clock
Transmitter
PCS
Parallel Data
from FPGA Core
Clock
Generation
Block
Serial
Clock
Input
Reference
Clock
Transmitter
PLL
Receiver PMA
Receiver Serial
Differential Input
Data
Serial
Data
Receiver
Buffer
CDR
Serial
Data
Deserializer
Parallel
Data
Receiver
PCS
Parallel Data
to FPGA Core
Serial Clock
Parallel Clock
Note: TX pre-emp is not supported in pre-CDR loopback. TX pre-emp is recommended to set to zero for all taps.
Figure 234. Reverse Serial Loopback Path/Post CDR
The reverse serial loopback path sets the transmitter buffer to transmit data fed directly from the CDR
recovered data. Data from the serializer is ignored by the transmitter buffer.
Transmitter PMA
Transmitter Serial
Differential Output
Data
Transmitter
Buffer
Serial
Data
Parallel
Data
Serializer
Parallel
Clock
Reverse
Loopback
Serial
Clock
Receiver PMA
Receiver Serial
Differential Input
Data
Receiver
Buffer
Transmitter
PCS
Clock
Generation
Block
Serial
Data
Serial
Data
Deserializer
CDR
Parallel Data
from FPGA core
Input
Reference
Clock
Transmitter
PLL
Parallel
Data
Receiver
PCS
Parallel Data
to FPGA core
Serial Clock
Parallel Clock
5.2 Arria 10 Enhanced PCS Architecture
You can use the Enhanced PCS to implement multiple protocols that operate at around
10 Gbps or higher line rates.
The Enhanced PCS provides the following functions:
•
Performs functions common to most serial data industry standards, such as word
alignment, block synchronization, encoding/decoding, and framing, before data is
sent or received off-chip through the PMA
•
Handles data transfer to and from the FPGA fabric
•
Internally handles data transfer to and from the PMA
•
Provides frequency compensation
•
Performs channel bonding for multi-channel low skew applications
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Figure 235. Enhanced PCS Datapath Diagram
Transmitter Enhanced PCS
Enhanced PCS
TX FIFO
Interlaken
Frame Generator
TX
Data &
Control
tx_coreclkin
PRBS
Generator
Interlaken
CRC32 Generator
64B/66B Encoder
and TX SM
Scrambler
Interlaken
Disparity Generator
FPGA
Fabric
TX
Gearbox
Serializer
tx_serial_data
Transmitter PMA
PRP
Generator
Parallel Clock
Transcode
Encoder
KR FEC
Encoder
KR FEC
TX Gearbox
KR FEC
Scrambler
tx_clkout
tx_pma_div_clkout
Receiver Enhanced PCS
Enhanced PCS
RX FIFO
Interlaken
CRC32 Checker
RX
Data &
Control
rx_coreclkin
PRBS
Verifier
64B/66B Decoder
and RX SM
Interlaken
Frame Sync
Descrambler
Block
Synchronizer
RX
Gearbox
Interlaken
Disparity Checker
rx_pma_div_clkout
Deserializer
CDR
rx_serial_data
Receiver PMA
PRP
Verifier
Parallel Clock
rx_clkout
Transcode
Decoder
KR FEC RX
Gearbox
KR FEC
Decoder
KR FEC
Descrambler
KR FEC
Block Sync
10GBASE-R
BER Checker
Clock Generation Block (CGB)
ATX PLL
fPLL
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Related Links
Implementing Protocols in Arria 10 Transceivers on page 30
5.2.1 Transmitter Datapath
5.2.1.1 Enhanced PCS TX FIFO
The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS
and the FPGA fabric. The TX FIFO can operate for phase compensation between the
channel PCS and FPGA fabric. You can also use the TX FIFO as an elastic buffer to
control the input data flow, using tx_enh_data_valid. The TX FIFO also allows
channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.
You can set the TX FIFO partially full and empty thresholds through the Transceiver
and PLL Address Map. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for more details.
The TX FIFO supports the following operating modes:
•
Phase Compensation mode
•
Register mode
•
Interlaken mode
•
Basic mode
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
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5.2.1.1.1 Phase Compensation Mode
In Phase Compensation mode, the TX Core FIFO decouples phase variations between
tx_coreclkin and PCS_clkout_x2(tx). In this mode, read and write of the TX
Core FIFO can be driven by clocks from asynchronous clock sources but must be same
frequency. You can use tx_coreclkin (FPGA fabric clock) or tx_clkout1 (TX
parallel clock) to clock the write side of the TX Core FIFO.
Note:
Phase Compensation mode, TX parallel data is valid for every low speed clock cycle,
and tx_enh_data_valid signal should be tied with 1'b1.
Note:
Phase Compensation can also be used in double rate transfer mode, where the FPGA
fabric data width is doubled to allow the FPGA fabric clock to run at half rate. The
double rate transfer mode is set in the Native PHY IP Parameter Editor. Refer to the
"Transmitter Data Path Interface Clocking" and "Receiver Data Path Interface Clocking"
sections in the PLLs and Clock Networks chapter for details about the clock
frequencies, when using FIFO single and double rate transfer mode.
Related Links
•
Transmitter Data Path Interface Clocking on page 374
•
Receiver Data Path Interface Clocking on page 375
5.2.1.1.2 Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock.
In Register mode, tx_parallel_data (data), tx_control (indicates whether
tx_parallel_data is a data or control word), and tx_enh_data_valid (data
valid) are registered at the FIFO output.
Note:
Intel recommends that you implement a soft FIFO in the FPGA fabric with a minimum
of 32 words under the following conditions:
•
When the Enhanced PCS TX FIFO is set to register mode.
•
When using the recovered clock to drive the core logic.
•
When there is no soft FIFO being generated along with the IP Catalog.
5.2.1.1.3 Interlaken Mode
In Interlaken mode, the TX Core FIFO operates as an elastic buffer. In this mode, you
have additional signals to control the data flow into the FIFO. Therefore, the FIFO
write clock frequency does not have to be the same as the read clock frequency. You
control the writing to the TX Core FIFO with tx_fifo_wr_en by monitoring the FIFO
flags. The goal is to prevent the FIFO from becoming full or empty. On the read side,
read enable is controlled by the Interlaken frame generator.
5.2.1.1.4 Basic Mode
In Basic mode, the TX Core FIFO operates as an elastic buffer, where buffer depths
can vary. This mode allows driving write and read side of TX Core FIFO with different
clock frequencies. Monitor the FIFO flag to control write and read operations. For TX
Core FIFO, assert tx_fifo_wr_en with tx_fifo_pempty signal going low.
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5.2.1.2 Interlaken Frame Generator
The Interlaken frame generator block takes the data from the TX FIFO and
encapsulates the payload and burst/idle control words from the FPGA fabric with the
framing layer’s control words (synchronization word, scrambler state word, skip word,
and diagnostic word) to form a metaframe. The Native PHY IP Parameter Editor allows
you to set the metaframe length from five 8-byte words to a maximum value of 8192
(64Kbyte words).
Use the same value on frame generator metaframe length for the transmitter and
receiver.
Figure 236. Interlaken Frame Generator
The Interlaken frame generator implements the Interlaken protocol.
Interlaken
Frame
Generator
64-Bit Data
1-Bit Control
From TX FIFO
To Interlaken
CRC-32 Generator
66-Bit Blocks
Payload
Synchronization
Scrambler
State Word
Skip Word
66 65 64 63
0 66
0 66
Data
Sync Header
Inversion Bit (Place Holder for Bit Inversion Information)
Used for Clock Compensation in a Repeater
Used to Synchronize the Scrambler
Used to Align the Lanes of the Bundle
0 Di
Provides Per
Lane Error Check
and Optional Status
Message
5.2.1.3 Interlaken CRC-32 Generator
The Interlaken CRC-32 generator block receives data from the Interlaken frame
generator and calculates the cyclic redundancy check (CRC) code for each block of
data. This CRC code value is stored in the CRC32 field of the diagnostic word. CRC-32
provides a diagnostic tool for each lane. This helps to trace the errors on the interface
back to an individual lane.
The CRC-32 calculation covers most of the metaframe, including the diagnostic word,
except the following:
•
Bits [66:64] of each word
•
58-bit scrambler state within the scrambler state word
•
32-bit CRC-32 field within the diagnostic word
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Figure 237. Interlaken CRC-32 Generator
The Interlaken CRC-32 generator implements the Interlaken protocol.
Interlaken
CRC-32
Generator
From the Interlaken Frame Generator
Metaframes with Embedded
CRC-32 Code to Scrambler
Di
Metaframe
Sy
67
SB
0 67
SK
Payload
0 67
Di
66
Sy
SB
SK
Sy
SB
SK
Payload
Sy
0
66
Total Data for CRC-32 Calculation
31
SB
SK
0
Total Data for CRC-32 Calculation
Calculated CRC-32 Value
Inserted in the 32 Bits
of Diagnostic Word
5.2.1.4 64B/66B Encoder and Transmitter State Machine (TX SM)
The 64B/66B encoder is used to achieve DC-balance and sufficient data transitions for
clock recovery. It encodes 64-bit XGMII data and 8-bit XGMII control into 10GBASE-R
66-bit control or data blocks in accordance with Clause 49 of the IEEE802.3-2008
specification.
The 66-bit encoded data contains two overhead sync header bits that the receiver PCS
uses for block synchronization and bit-error rate (BER) monitoring. The sync header is
01 for data blocks and 10 for control blocks. Sync headers are not scrambled and are
used for block synchronization. (The sync headers 00 and 11 are not used, and
generate an error if seen.) The remainder of the block contains the payload. The
payload is scrambled and the sync header bypasses the scrambler.
The encoder block also has a state machine (TX SM) designed in accordance with the
IEEE802.3-2008 specification. The TX SM ensures valid packet construction on data
sent from the MAC layer. It also performs functions such as transmitting local faults
under reset, as well as transmitting error codes when the 10GBASE-R PCS rules are
violated.
Note:
The 64B/66B encoder is available to implement the 10GBASE-R protocol.
Figure 238. Example Data Pattern for 64B/66B Encoding
TXC<0:3> TXD<0:31> XGMII
XGMII
data
f07070707
f07070707
8 fb D 1D 2D 3
0 D 4D 5D 6D 7
0 D 0D 1D 2D 3
0 D 4D 5D 6D 7
1 D 0D 1D 2fd
f07070707
PCS
C 0C 1C 2C 3C 4C 5C 6C 7
Data
0
66-bit
encoded
data
S 0D 1D 2D 3D 4D 5D 6D 7
D 0D 1D 2T 3C 0C 1C 2C 3
63
10 1e 000000 00000000
0
D 0D 1D 2D 3D 4D 5D 6D 7
10
78 D 1D 2D 3D 4D 5D 6D 7
01
D 0D 1D 2D 3D 4D 5D 6D 7
10
b4 D 0D 1D 2 00000000
65
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64B/66B Encoder Reset Condition
The tx_digitalreset signal resets the 64B/66B encoder. During the reset
condition, the 64B/66B encoder does not output any signal in contrast with the
8B/10B encoder.
5.2.1.5 Pattern Generators
The Arria 10 transceivers contain hardened generators and checkers to provide a
simple and easy way to verify and characterize high speed links. Hardening the
pattern generators and checkers save FPGA core logic resources. The following pattern
generator blocks are supported in Arria 10:
Note:
•
Pseudo Random Binary Sequence (PRBS)
•
Pseudo Random Pattern (PRP)
The pattern generators and checkers are supported for non-bonded channels only.
The pattern generators or checkers are enabled by writing to the respective register
bits of the Transceiver. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for configuration details.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
5.2.1.5.1 PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS)
You can use Arria 10 pseudo-random bit sequence PRBS generator to simulate traffic
without developing or fully implementing any upper layer of a protocol stack. The
PRBS generator in Arria 10 devices is a shared hardened block between the Standard
and Enhanced datapaths through the PCS instead of being two unique instances: one
for Standard PCS and one for the Enhanced PCS. There is only one set of control
signals and registers for using this feature. The data lines from the various PCSes and
shared PRBS, are muxed before they are sent to the PMA. When the PRBS generator is
enabled, the data on the PRBS data lines is selected to be sent to the PMA. At any
instant, either the data from the PCS or the data generated from the PRBS generator,
is sent to the PMA.
The PRBS generator can be configured for two widths of the PCS-PMA interface: 10
bits and 64 bits. PRBS9 is available in 10-bit and 64-bit PCS-PMA widths. All other
PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS generator
patterns can only be used when PCS-PMA interface width is configured to 10 bits or 64
bits.
Table 254.
Supported PRBS Patterns
PRBS Pattern
PRBS7:
x7
PRBS9:
x9
+
x6
+1
+
x5
+1
PRBS15:
x15
PRBS23:
x23
PRBS31:
x31
10 bit PCS-PMA width
64 bit PCS-PMA width
Yes
Yes
Yes
+
x14
+1
Yes
+
x18
+1
Yes
+
x28
+1
Yes
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PRBS test patterns may be considered equivalent to "noise". Use these patterns to
test the transceiver link with a noisy signal by placing the transceiver in loopback
mode.
Use PRBS7 and PRBS9 to test transceiver links with linear impairments, and with 8B/
10B.
Use PRBS15 for jitter evaluation.
Use PRBS23 or PRBS31 for jitter evaluation (data-dependent jitter) of non-8B/10B
links, such as SDH/SONET/OTN jitter testers. Most 40G, 100G, and 10G applications
use PRBS31 for link evaluation.
Figure 239. PRBS Generator for Serial Implementation of PRBS9 Pattern
S0
S1
S4
S5
S8
PRBS Output
Note:
All supported PRBS generators are similar to the PRBS9 generator.
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for
configuration details.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
5.2.1.5.2 Pseudo-Random Pattern Generator
The pseudo-random pattern (PRP) generator is specifically designed for the 10GBASER and 1588 protocols. The PRP generator block operates in conjunction with the
scrambler to generate pseudo-random patterns for the TX and RX tests in the 10G
Ethernet mode. You can use the Arria 10 Pseudo Random Pattern (PRP) generator in
the scrambler to generate random data pattern and seed that the scrambler can use.
The PRP mode is a test mode of the scrambler. Two seeds are available to seed the
scrambler: all 0s or two local fault-ordered sets. The seed will be used in the
scrambler to produce the pattern. PRP is only available when the scrambler is enabled.
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for
configuration details.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
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5.2.1.6 Scrambler
The scrambler randomizes data to create transitions to DC-balance the signal and help
CDR circuits. The scrambler uses a x58 + x39 +1 polynomial and supports both
synchronous scrambling used for Interlaken and asynchronous (also called selfsynchronized) scrambling used for the 10GBASE-R protocol.
The asynchronous (self-synchronizing) mode does not require an initialization seed.
Except for the two sync header bits in each 66-bit data block, the entire 64-bit
payload is scrambled by feeding it into a linear feedback shift register (LFSR)
continuously to generate scrambled data while the sync-header bits bypass the
scrambler. The initial seed is set to all 1s. You can change the seed for the 10GBASE-R
protocol using the Native PHY IP Parameter Editor.
Figure 240. Asynchronous Scrambler in Serial Implementation
IN
S0
S1
S2
S38
S39
S56
S57
OUT
In synchronous mode, the scrambler is initially reset to different programmable seeds
on each lane. The scrambler then runs by itself. Its current state is XOR’d with the
data to generate scrambled data. A data checker in the scrambler monitors the data to
determine if it should be scrambled or not. If a synchronization word is found, it is
transmitted without scrambling. If a Scrambler State Word is detected, the current
scramble state is written into the 58-bit scramble state field in the Scrambler State
Word and sent over the link. The receiver uses this scramble state to synchronize the
descrambler. The seed is automatically set for Interlaken protocol.
Figure 241. Synchronous Scrambler Showing Different Programmable Seeds
S0
LFSR Seed
S37
S38
S57
0
37
57
38
OUT
IN
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5.2.1.7 Interlaken Disparity Generator
The Interlaken disparity generator block is in accordance with the Interlaken protocol
specification and provides a DC-balanced data output.
The Interlaken protocol solves the unbounded baseline wander, or DC imbalance, of
the 64B/66B coding scheme used in 10Gb Ethernet by inverting the transmitted data.
The disparity generator monitors the transmitted data and makes sure that the
running disparity always stays within a ±96-bit bound. It adds the 67th bit (bit 66) to
signal the receiver whether the data is inverted or not.
Table 255.
Inversion Bit Definition
Bit 66
Note:
Interpretation
0
Bits [63:0] are not inverted; the receiver processes this word without modification
1
Bits [63:0] are inverted; the receiver inverts the bits before processing this word
The Interlaken disparity generator is available to implement the Interlaken protocol.
5.2.1.8 TX Gearbox, TX Bitslip and Polarity Inversion
The TX gearbox adapts the PCS data width to the smaller bus width of the PCS-PMA
interface (Gearbox Reduction). It supports different ratios (FPGA fabric-PCS Interface
Width: PCS-PMA Interface Width) such as 66:32, 66:40, 64:32, 40:40, 32:32, 64:64,
67:64, and 66:64. The gearbox mux selects a group of consecutive bits from the input
data bus depending on the gearbox ratio and the data valid control signals.
The TX gearbox also has a bit slipping feature to adjust the data skew between
channels. The TX parallel data is slipped on the rising edge of tx_enh_bitslip
before it is passed to the PMA. The maximum number of the supported bitslips is PCS
data width-1 and the slip direction is from MSB to LSB and from current to previous
word.
Figure 242. TX Bitslip
tx_enh_bitslip = 2 and PCS width of gearbox is 67
You can use transmitter data polarity inversion to invert the polarity of every bit of the
input data word to the serializer in the transmitter path. The inversion has the same
effect as swapping the positive and negative signals of the differential TX buffer. This
is useful if these signals are reversed on the board or backplane layout. Enable
polarity inversion through the Native PHY IP Parameter Editor.
5.2.1.9 KR FEC Blocks
The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10GKRFEC and 40G-KRFEC of the IEEE 802.3 specification. The KR FEC implements the
Forward Error Correction (FEC) sublayer, a sublayer between the PCS and PMA
sublayers.
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Most data transmission systems, such as Ethernet, have minimum requirements for
the bit error rate (BER). However, due to channel distortion or noise in the channel,
the required BER may not be achievable. In these cases, adding a forward error
control correction can improve the BER performance of the system.
The FEC sublayer is optional and can be bypassed. When used, it can provide
additional margin to allow for variations in manufacturing and environmental
conditions. FEC can achieve the following objectives:
•
Support a forward error correction mechanism for the 10GBASE-R/KR and
40GBASE-R/KR protocols.
•
Support the full duplex mode of operation of the Ethernet MAC.
•
Support the PCS, PMA, and Physical Medium Dependent (PMD) sublayers defined
for the 10GBASE-R/KR and 40GBASE-R/KR protocols.
•
Support up to the maximum transceiver data rate on any protocol that is 64/66bit encoded.
With KR FEC, the BER performance of the system can be improved.
Transcode Encoder
The KR forward error correction (KR FEC) transcode encoder block performs the
64B/66B to 65-bit transcoder function by generating the transcode bit. The transcode
bit is generated from a combination of 66 bits after the 64B/66B encoder which
consists of a 2-bit synchronization header (S0 and S1) and a 64-bit payload (D0, D1,
…, D63). To ensure a DC-balanced pattern, the transcode word is generated by
performing an XOR function on the second synchronization bit S1 and payload bit D8.
The transcode bit becomes the LSB of the 65-bit pattern output of the transcode
encoder.
Figure 243. Transcode Encoder
66-Bit Input
D63
...
D9
D8
...
D0
S1
D9
D8
...
D0
S1^D8
S0
65-Bit Output
D63
...
KR FEC Encoder
FEC (2112,2080) is an FEC code specified in Clause 74 of the IEEE 802.3 specification.
The code is a shortened cyclic code (2112, 2080). For each block of 2080 message
bits, another 32 parity checks are generated by the encoder to form a total of 2112
bits. The generator polynomial is:
g(x) = x32 + x23 + x21 + x11 + x2 +1
KR FEC Scrambler
The KR FEC scrambler block performs scrambling based on the generation polynomial
x58 + x39 +1, which is necessary for establishing FEC block synchronization in the
receiver and to ensure DC balance.
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KR FEC TX Gearbox
The KR FEC TX gearbox converts 65-bit input words to 64-bit output words to
interface the KR FEC encoder with the PMA. This gearbox is different from the TX
gearbox used in the Enhanced PCS. The KR FEC TX gearbox aligns with the FEC block.
Because the encoder output (also the scrambler output) has its unique word size
pattern, the gearbox is specially designed to handle that pattern.
5.2.2 Receiver Datapath
5.2.2.1 RX Gearbox, RX Bitslip, and Polarity Inversion
The RX gearbox adapts the PMA data width to the larger bus width of the PCS channel
(Gearbox Expansion). It supports different ratios (PCS-PMA interface width : FPGA
fabric–PCS interface width) such as 32:66, 40:66, 32:67, 32:64, 40:40, 32:32, 64:64,
67:64, and 66:64 and a bit slipping feature.
RX bitslip is engaged when the RX block synchronizer or rx_bitslip is enabled to
shift the word boundary. On the rising edge of the bitslip signal of the RX block
synchronizer or rx_bitslip from the FPGA fabric, the word boundary is shifted by
one serial bit or 1UI. Each bit slip removes the earliest received bit from the received
data.
Figure 244. RX Bitslip
rx_bitslip is toggled two times, which shifts the rx_parallel_data boundary two bits.
rx_clkout
tx_ready
rx_ready
tx_parallel_data (hex) 00000001
rx_bitslip
rx_parallel_data (hex)
00000000
00100000
The first rising edge of
rx_bitslip makes 1 serial bit
00200000
00400000
The second rising edge of rx_bitslip
makes another serial bit slip.
The receiver gearbox can invert the polarity of the incoming data. This is useful if the
receiver signals are reversed on the board or backplane layout. Enable polarity
inversion through the Native PHY IP Parameter Editor.
Data valid generation logic is essential for gearbox operation. Each block of data is
accompanied by rx_enh_data_valid data valid signal which “qualifies” the block as
valid or not. The data valid toggling pattern is dependent on the data width conversion
ratio. For example, if the ratio is 66:40, the data valid signal is high in 20 out of 33
cycles or approximately 2 out of 3 cycles and the pattern repeats every 33
rx_clkout RX low-speed parallel clock cycles.
5.2.2.2 Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of
the 10GBASE-R protocol or a 67-bit word in the case of the Interlaken protocol. The
incoming data stream is slipped one bit at a time until a valid synchronization header
(bits 65 and 66) is detected in the received data stream. After the predefined number
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of synchronization headers (as required by the protocol specification) is detected, the
block synchronizer asserts rx_enh_blk_lock (block lock status signal) to other
receiver PCS blocks down the receiver datapath and to the FPGA fabric.
Note:
The block synchronizer is designed in accordance with Interlaken Protocol specification
(as described in Figure 13 of Interlaken Protocol Definition v1.2) and 10GBASE-R
protocol specification (as described in IEEE 802.3-2008 clause-49).
5.2.2.3 Interlaken Disparity Checker
The Interlaken disparity checker examines the received inversion bit inserted by the
far end disparity generator, to determine whether to reverse the inversion process of
the Interlaken disparity generation.
Note:
The Interlaken disparity checker is available to implement the Interlaken protocol.
5.2.2.4 Descrambler
The descrambler block descrambles received data to regenerate unscrambled data
using the x58 + x39 +1 polynomial. Like the scrambler, it operates in asynchronous
mode or synchronous mode.
Related Links
Scrambler on page 452
5.2.2.5 Interlaken Frame Synchronizer
The Interlaken frame synchronizer delineates the metaframe boundaries and searches
for each of the framing layer control words: Synchronization, Scrambler State, Skip,
and Diagnostic. When four consecutive synchronization words have been identified,
the frame synchronizer achieves the frame locked state. Subsequent metaframes are
then checked for valid synchronization and scrambler state words. If four consecutive
invalid synchronization words or three consecutive mismatched scrambler state words
are received, the frame synchronizer loses frame lock. In addition, the frame
synchronizer provides rx_enh_frame_lock (receiver metaframe lock status) to the
FPGA fabric.
Note:
The Interlaken frame synchronizer is available to implement the Interlaken protocol.
5.2.2.6 64B/66B Decoder and Receiver State Machine (RX SM)
The 64B/66B decoder reverses the 64B/66B encoding process. The decoder block also
contains a state machine (RX SM) designed in accordance with the IEEE802.3-2008
specification. The RX SM checks for a valid packet structure in the data sent from the
remote side. It also performs functions such as sending local faults to the Media
Access Control (MAC)/Reconciliation Sublayer (RS) under reset and substituting error
codes when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Note:
The 64B/66B decoder is available to implement the 10GBASE-R protocol.
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5.2.2.6.1 PRBS Checker
You can use Arria 10 pseudo-random bit stream (PRBS) checker to easily characterize
high-speed links without developing or fully implementing any upper layer of a
protocol stack. The PRBS checker in Arria 10 devices is a shared hardened block
between the Standard and Enhanced datapaths. Hence, there is only one set of control
signals and registers for this feature.
You can use the PRBS checker block to verify the pattern generated by the PRBS
generator. The PRBS checker can be configured for two widths of the PCS-PMA
interface: 10 bits and 64 bits. PRBS9 is available in both 10-bit and 64-bit PCS-PMA
widths. All other PRBS patterns are available in 64-bit PCS-PMA width only. The PRBS
checker patterns can only be used when the PCS-PMA interface width is configured to
10 bits or 64 bits.
The pseudo-random bit stream (PRBS) block verifies the pattern generated by the
PRBS generator. The verifier supports the 64-bit PCS-PMA interface. PRBS7 supports
64-bit width only. PRBS9 supports 10-bit PMA data width to allow testing at a lower
data rate.
Table 256.
Supported PRBS Patterns
PRBS Pattern
PRBS7:
x7
PRBS9:
x9
+
x6
+1
+
x5
+1
PRBS15:
x15
PRBS23:
x23
PRBS31:
x31
10 bit PCS-PMA width
64 bit PCS-PMA width
Yes
Yes
Yes
+
x14
+1
Yes
+
x18
+1
Yes
+
x28
+1
Yes
Figure 245. PRBS9 Verify Serial Implementation
PRBS datain
S0
S1
S4
S5
S8
PRBS Error
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The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done—Indicates the PRBS sequence has completed one full cycle. It
stays high until you reset it with rx_prbs_err_clr.
•
rx_prbs_err—Goes high if an error occurs. This signal is pulse-extended to
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr—Used to reset the rx_prbs_err signal.
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
5.2.2.7 Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R
1588 protocol modes. The PRP verifier block operates in conjunction with the
descrambler. The PRP verifier monitors the output of the descrambler when block
synchronization is achieved.
The rx_prbs_err error signal is shared between the PRBS checker and the PRP
verifier.
The PRP verifier:
•
Searches for a test pattern (two local faults, or all 0s) or its inverse
•
Tracks the number of mismatches with a 16-bit error counter
Figure 246. PRP Verifier
Error
Counter
error_count
Descrambler
Test Pattern
Detect
Pseudo Random
Verifier
Refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter for
configuration details.
Related Links
Reconfiguration Interface and Dynamic Reconfiguration on page 484
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5.2.2.8 10GBASE-R Bit-Error Rate (BER) Checker
The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R
protocol specification as described in IEEE 802.3-2008 clause-49. After block lock
synchronization is achieved, the BER checker starts to count the number of invalid
synchronization headers within a 125-μs period. If more than 16 invalid
synchronization headers are observed in a 125-μs period, the BER checker provides
the status signal rx_enh_highber to the FPGA fabric, indicating a high bit error rate
condition.
When the optional control input rx_enh_highber_clr_cnt is asserted, the internal
counter for the number of times the BER state machine has entered the
"BER_BAD_SH" state is cleared.
When the optional control input rx_enh_clr_errblk_count is asserted, the
internal counter for the number of times the RX state machine has entered the "RX_E"
state for the 10GBASE-R protocol is cleared. In modes where the FEC block in
enabled, the assertion of this signal resets the status counters within the RX FEC
block.
Note:
The 10GBASE-R BER checker is available to implement the 10GBASE-R protocol.
5.2.2.9 Interlaken CRC-32 Checker
The Interlaken CRC-32 checker verifies that the data transmitted has not been
corrupted between the transmit PCS and the receive PCS. The CRC-32 checker
calculates the 32-bit CRC for the received data and compares it against the CRC value
that is transmitted within the diagnostic word. rx_enh_crc32_err (CRC error signal)
is sent to the FPGA fabric.
5.2.2.10 Enhanced PCS RX FIFO
The Enhanced PCS RX FIFO is designed to compensate for the phase and/or clock
difference between the receiver channel PCS and the FPGA fabric. It can operate as a
phase-compensation, clock-compensation, elastic buffer, or a deskew FIFO in
Interlaken mode. The RX FIFO has a width of 74 bits and a depth of 32 words for all
protocols.
The RX FIFO supports the following modes:
•
Phase Compensation mode
•
Register mode
•
Interlaken mode (deskew FIFO)
•
10GBASE-R mode (clock compensation FIFO)
•
Basic mode (elastic buffer FIFO)
5.2.2.10.1 Phase Compensation Mode
The RX FIFO compensates for the phase difference between the read clock and write
clocks. rx_clkout (RX parallel low-speed clock) clocks the write side of the RX FIFO.
rx_coreclkin (FPGA fabric clock) or rx_clkout clocks the read side of the RX
FIFO.
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When phase compensation is used in double-width mode, the FPGA data width is
doubled to allow the FPGA fabric clock to run at half rate, similar to the TX FIFO phase
compensation in double-width mode.
Depth of RX FIFO is constant in this mode, therefore RX FIFO flag status can be
ignored. You can tie tx_enh_data_valid with one.
5.2.2.10.2 Register Mode
The Register Mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock.
In Register mode, rx_parallel_data (data), rx_control indicates whether
rx_parallel_data is a data or control word, and rx_enh_data_valid (data valid)
are registered at the FIFO output. The RX FIFO in register mode has one register
stage or one parallel clock latency.
Note:
Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of
32 words under the following conditions:
•
When the Enhanced PCS RX FIFO is set to register mode.
•
When using the recovered clock to drive the core logics.
•
When there is no soft FIFO being generated along with the IP Catalog.
5.2.2.10.3 Interlaken Mode
In Interlaken mode, the RX FIFO operates as an Interlaken deskew FIFO. To
implement the deskew process, implement an FSM that controls the FIFO operation
based on available FPGA input and output flags.
For example, after frame lock is achieved, data is written after the first alignment
word (SYNC word) is found on that channel. As a result, rx_enh_fifo_pempty (FIFO
partially empty flag ) of that channel goes low. You must monitor the
rx_enh_fifo_pempty and rx_enh_fifo_pfull flags of all channels. If
rx_enh_fifo_pempty flags from all channels deassert before any
rx_enh_fifo_pfull flag asserts, which implies alignment word has been found on
all lanes of the link, you start reading from all the FIFOs by asserting
rx_enh_fifo_rd_en. Otherwise, if a rx_enh_fifo_pfull flag from any channel
goes high before a rx_enh_fifo_pempty flag deassertion on all channels, you must
reset the FIFO by toggling the rx_enh_fifo_align_clr signal and repeating the
process.
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Figure 247. RX FIFO as Interlaken Deskew FIFO
FPGA Fabric Interface
rx_enh_fifo_align_clr
rx_enh_fifo_rd_en
User
Deskew
FSM
rx_enh_fifo_pempty
RX FIFO
rx_enh_fifo_pfull
5.2.2.10.4 10GBASE-R Mode
In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the
block synchronizer achieves block lock, data is sent through the FIFO. Idle ordered
sets (OS) are deleted and Idles are inserted to compensate for the clock difference
between the RX low speed parallel clock and the FPGA fabric clock (±100 ppm for a
maximum packet length of 64,000 bytes).
Idle OS Deletion
Deletion of Idles occurs in groups of four OS (when there are two consecutive OS)
until the rx_enh_fifo_pfull flag deasserts. Every word—consisting of a lower word
(LW) and an upper word (UW)—is checked for whether it can be deleted by looking at
both the current and previous words.
For example, the current LW can be deleted if it is Idle and the previous UW is not a
Terminate.
Table 257.
Conditions Under Which a Word Can be Deleted
In this table X=don’t care, T=Terminate, I=Idle, and OS=order set.
Deletable
Case
Word
Previous
Current
Lower Word
1
UW
!T
X
LW
X
2
UW
OS
LW
X
UW
Upper Word
1
2
Output
!T
X
I
X
X
X
OS
X
OS
X
X
X
I
X
X
LW
X
!T
X
!T
UW
X
OS
X
X
LW
X
OS
X
OS
If only one word is deleted, data shifting is necessary because the datapath is two
words wide. After two words have been deleted, the FIFO stops writing for one cycle
and a synchronous flag (rx_control[8]) appears on the next block of 8-byte data.
There is also an asynchronous status signal rx_enh_fifo_del, which does not go
through the FIFO.
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Figure 248. IDLE Word Deletion
This figure shows the deletion of IDLE words from the receiver data stream.
Before Deletion
00000000000004AEh
rx_parallel_data[79:0] 00000000000004ADh
0707070707FD0000h
000000FB07070707h
After Deletion
rx_parallel_data[79:0]
00000000000004ADh
00000000000004AEh
AAAAAAAA000000FBh
0707070707FD0000h
Idle Deleted
Figure 249. OS Word Deletion
This figure shows the deletion of Ordered set words in the receiver data stream.
Before Deletion
rx_parallel_data[79:0]
FD000000000004AEh
DDDDDD9CDDDDDD9Ch
00000000000000FBh
AAAAAAAAAAAAAAAAh
000000FBDDDDDD9Ch
AAAAAAAA00000000h
00000000AAAAAAAAh
After Deletion
rx_parallel_data[79:0]
FD000000000004AEh
OS Deleted
Idle Insertion
Idle insertion occurs in groups of 8 Idles when the rx_enh_fifo_pempty flag is
deasserted. Idles can be inserted following Idles or OS. Idles are inserted in groups of
8 bytes. Data shifting is not necessary. There is a synchronous status
rx_enh_fifo_insert signal that is attached to the 8-byte Idles being inserted.
Table 258.
Cases Where Two Idle Words are Inserted
In this table X=don’t care, S=start, OS=order set, I-DS=idle in data stream, and I-In=idle inserted. In cases 3
and 4, the Idles are inserted between the LW and UW.
Case
Word
Input
1
UW
I-DS
I-DS
I-In
LW
X
X
I-In
UW
OS
OS
I-In
LW
X
X
I-In
UW
S
I-In
S
LW
I-DS
I-DS
I-In
UW
S
I-In
S
LW
OS
OS
I-In
2
3
4
Output
Figure 250. IDLE Word Insertion
This figure shows the insertion of IDLE words in the receiver data stream.
Before Insertion
rx_parallel_data[79:0]
FD000000000004AEh
BBBBBB9CDDDDDD9Ch
00000000000000FBh
AAAAAAAAAAAAAAAAh
BBBBBB9CDDDDDD9Ch
0707070707070707h
00000000000000FBh
After Insertion
rx_parallel_data[79:0]
FD000000000004AEh
Idle Inserted
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5.2.2.10.5 Basic Mode
In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can
vary. This mode allows driving write and read side of RX FIFO with different clock
frequencies. Monitor the FIFO flag to control write and read operations. For RX FIFO,
assert rx_enh_read_en signal with rx_fifo_pfull signal going low.
5.2.2.11 RX KR FEC Blocks
KR FEC Block Synchronization
You can obtain FEC block delineation for the RX KR FEC by locking onto correctly
received FEC blocks with the KR FEC block synchronization. You can also use the KR
FEC up to the maximum transceiver data rate on any protocol that is 64/66-bit
encoded.
Note:
The KR FEC block synchronization is available to implement the 10GBASE-KR protocol.
KR FEC Descrambler
The KR FEC descrambler block descrambles received data to regenerate unscrambled
data using the x58 + x39 +1 polynomial. Before the block boundary in the KR FEC sync
block is detected, the data at the input of the descrambler is sent directly to the KR
FEC decoder. When the boundary is detected, the aligned word from the KR FEC sync
block is descrambled with the Pseudo Noise (PN) sequence and then sent to the KR
FEC decoder.
KR FEC Decoder
The KR FEC decoder block performs the FEC (2112, 2080) decoding function by
analyzing the received 32 65-bit blocks for errors. It can correct burst errors of 11 bits
or less per FEC block.
KR FEC RX Gearbox
The KR FEC RX gearbox block adapts the PMA data width to the larger bus width of
the PCS channel. It supports a 64:65 ratio.
Transcode Decoder
The transcode decoder block performs the 65-bit to 64B/66B reconstruction function
by regenerating the 64B/66B synchronization header.
5.3 Arria 10 Standard PCS Architecture
The standard PCS can operate at a data rate of up to 10.8 Gbps. Protocols such as PCI
Express, CPRI 4.2+, GigE, IEEE 1588 are supported in Hard PCS while the other
protocols can be implemented using Basic/Custom (Standard PCS) transceiver
configuration rules.
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Figure 251. Standard PCS Datapath Diagram
Transmitter Standard PCS
Transmitter PMA
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
TX Bit Slip
Serializer
tx_serial_data
PRBS
Generator
tx_coreclkin
tx_clkout
/2, /4
tx_clkout
tx_pma_div_clkout
Receiver PMA
Receiver Standard PCS
RX
FIFO
Byte
Deserializer
Parallel Clock
(From Clock
Divider)
8B/10B Decoder
Rate Match FIFO
Word Aligner
Deserializer
CDR
rx_serial_data
Parallel Clock
(Recovered)
rx_coreclkin
rx_clkout
tx_clkout
rx_clkout or
tx_clkout
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
ATX PLL
CMU PLL
fPLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
Parallel and Serial Clock
Serial Clock
5.3.1 Transmitter Datapath
5.3.1.1 TX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures
reliable transfer of data and status signals. It compensates for the phase difference
between the FPGA fabric clock and tx_clkout (the low-speed parallel clock). The TX
FIFO has a depth of 8 and operates in low latency mode, register mode, and fast
register mode.
Figure 252. TX FIFO Block Diagram
Datapath to Byte Serializer,
8B/10B Encoder,
or Serializer
TX
FIFO
rd_clk
tx_clkout
Datapath from FPGA Fabric
or PIPE Interface
wr_clk
tx_coreclkin
You can control the write port using tx_clkout or tx_coreclkin. Use the
tx_clkout signal for a single channel and tx_coreclkin when using multiple
channels. The TX FIFO is shared with PCIe Gen3 and Enhanced PCS data paths.
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5.3.1.1.1 TX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency (latency uncertainty) when
connecting it with the FPGA fabric. The FIFO empty and the FIFO full threshold values
are made closer so that the depth of the FIFO decreases, which in turn decreases the
latency.
5.3.1.1.2 TX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock. The register mode incurs only
one clock cycle of latency when interfacing to the FPGA fabric.
5.3.1.1.3 TX FIFO Fast Register Mode
This mode allows a higher maximum frequency (fMAX) between the FPGA fabric and
the TX PCS by enabling the optional fast register interface with additional latency.
5.3.1.2 Byte Serializer
In certain applications, the FPGA fabric cannot operate at the same clock rate as the
transmitter channel (PCS) because the transmitter channel is capable of operating at
higher clock rates compared to the FPGA fabric. The byte serializer allows the
transmitter channel to operate at higher data rates while keeping the FPGA fabric
interface clock rate below its maximum limit. This is accomplished by increasing the
channel width two or four times (FPGA fabric-to-PCS interface width) and dividing the
clock (tx_clkout) rate by 2 or 4. The byte serializer can be disabled, or operate in
Serialize x2 or Serialize x4 modes.
Figure 253. Byte Serializer Block Diagram
dataout
(to the 8B/10 Encoder
or the TX Bit Slip)
tx_clkout
Byte
Serializer
datain (from the TX FIFO)
/2,
/4
Related Links
•
Resetting Transceiver Channels on page 402
•
Implementing Protocols in Arria 10 Transceivers on page 30
5.3.1.2.1 Bonded Byte Serializer
The bonded byte serializer is available in Arria 10 devices, and is used in applications
such as PIPE, CPRI, and custom applications where multiple channels are grouped
together. The bonded byte serializer is implemented by bonding all the control signals
to prevent skew induction between channels during byte serialization. In this
configuration, one of the channels acts as master and the remaining channels act as
slaves.
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5.3.1.2.2 Byte Serializer Disabled Mode
In disabled mode, the byte serializer is bypassed. The data from the TX FIFO is
directly transmitted to the 8B/10B encoder, TX Bitslip, or Serializer, depending on
whether or not the 8B/10B encoder and TX Bitslip are enabled. Disabled mode is used
in low speed applications such as GigE, where the FPGA fabric and the TX standard
PCS can operate at the same clock rate.
5.3.1.2.3 Byte Serializer Serialize x2 Mode
The serialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In serialize x2 mode, the byte serializer serializes 16-bit, 20-bit (when 8B/10B
encoder is not enabled), 32-bit, and 40-bit (when 8B/10B encoder is not enabled)
input data into 8-bit, 10-bit, 16-bit, and 20-bit data, respectively. As the parallel data
width from the TX FIFO is halved, the clock rate is doubled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards tx_parallel_data[15:0] first,
followed by tx_parallel_data[31:16].
Related Links
PCI Express (PIPE) on page 227
For more information about using the Serialize x2 mode in the PCIe protocol.
5.3.1.2.4 Byte Serializer Serialize x4 Mode
The serialize x4 mode is used in high-speed applications such as the PCIe Gen3
protocol mode, where the FPGA fabric cannot operate as fast as the TX PCS.
In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the
parallel data width from the TX FIFO is divided four times, the clock rate is
quadrupled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards tx_parallel_data[7:0] first,
followed by tx_parallel_data[15:8], tx_parallel_data[23:16] and
tx_parallel_data[31:24].
Related Links
PCI Express (PIPE) on page 227
For more information about using the Serialize x4 mode in the PCIe protocol.
5.3.1.3 8B/10B Encoder
The 8B/10B encoder takes in 8-bit data and 1-bit control as input and converts them
into a 10-bit output. The 8B/10B encoder automatically performs running disparity
check for the 10-bit output. Additionally, the 8B/10B encoder can control the running
disparity manually using the tx_forcedisp and tx_dispval ports.
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Figure 254. 8B/10B Encoder Block Diagrams
When the PCS-PMA Interface Width is 20 bits
When the PCS-PMA Interface Width is 10 bits
To the Serializer
From the Byte Serializer
datain[7:0]
To the Serializer
8B/10B Encoder
From the Byte Serializer
datain[15:8]
tx_datak
dataout[9:0]
8B/10B Encoder
tx_forcedisp
tx_datak[1]
MSB
Encoding
dataout[19:10]
tx_forcedisp[1]
tx_dispval
tx_dispval[1]
datain[7:0]
tx_datak[0]
LSB
Encoding
dataout[9:0]
tx_forcedisp[0]
tx_dispval[0]
When the PCS-PMA interface width is 10 bits, one 8B/10B encoder is used to convert
the 8-bit data into a 10-bit output. When the PCS-PMA interface width is 20 bits, two
cascaded 8B/10B encoders are used to convert the 16-bit data into a 20-bit output.
The first eight bits (LSByte) is encoded by the first 8B/10B encoder and the next eight
bits (MSByte) is encoded by the second 8B/10B encoder. The running disparity of the
LSByte is calculated first and passed on to the second encoder to calculate the running
disparity of the MSByte.
Note:
You cannot enable the 8B/10B encoder when the PCS-PMA interface width is 8 bits or
16 bits.
5.3.1.3.1 8B/10B Encoder Control Code Encoding
Figure 255. Control Code Encoding Diagram
tx_clkout
tx_parallel_data[15:0]
tx_datak[1:0]
Code Group
D3.4
8378
BCBC
0
1
D24.3
D28.5
0F00
BF3C
0
K28.5
D15.0
D0.0
D31.5
D28.1
The tx_datak signal indicates whether the 8-bit data being sent at the
tx_parallel_data port should be a control word or a data word. When tx_datak
is high, the 8-bit data is encoded as a control word (Kx.y). When tx_datak is low,
the 8-bit data is encoded as a data word (Dx.y). Depending upon the PCS-PMA
interface width, the width of tx_datak is either 1 bit or 2 bits. When the PCS-PMA
interface width is 10 bits, tx_datak is a 1-bit word. When the PCS-PMA interface
width is 20 bits, tx_datak is a 2-bit word. The LSB of tx_datak corresponds to the
LSByte of the input data sent to the 8B/10B encoder and the MSB corresponds to the
MSByte of the input data sent to the 8B/10B encoder.
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Related Links
Refer to Specifications & Additional Information for more information about 8B/10B
encoder codes.
5.3.1.3.2 8B/10B Encoder Reset Condition
The tx_digitalreset signal resets the 8B/10B encoder. During the reset condition,
the 8B/10B encoder outputs K28.5 continuously until tx_digitalreset goes low.
5.3.1.3.3 8B/10B Encoder Idle Character Replacement Feature
The idle character replacement feature is used in protocols such as Gigabit Ethernet,
which requires the running disparity to be maintained during idle sequences. During
these idle sequences, the running disparity has to be maintained such that the first
byte of the next packet always starts when the running disparity of the current packet
is negative.
When an ordered set, which consists of two code-groups, is received by the 8B/10B
encoder, the second code group will be converted into /I1/ or /I2 so that the final
running disparity of the data code-group is negative. The first code group is /K28.5/
and the second code group is a data code-group other than /D21.5/ or /D2.2/. The
ordered set /I1/ (/K28.5/D5.6/) is used to flip the running disparity and /I2/ (/K28.5/
D16.2/) is used to preserve the running disparity.
5.3.1.3.4 8B/10B Encoder Current Running Disparity Control Feature
The 8B/10B encoder performs a running disparity check on the 10-bit output data.
The running disparity can also be controlled using tx_forcedisp and tx_dispval.
When the PCS-PMA interface width is 10 bits, tx_forcedisp and tx_dispval are
one bit each. When the PCS-PMA interface width is 20 bits, tx_forcedisp and
tx_dispval are two bits each. The LSB of tx_forcedisp and tx_dispval
corresponds to the LSByte of the input data and the MSB corresponds to the MSByte
of the input data.
5.3.1.3.5 8B/10B Encoder Bit Reversal Feature
Figure 256. 8B/10B Encoder Bit Reversal Feature
Output
Data
7
0
Bit Reversal Mode
(8B/10B Encoder)
Input
Data
0
7
The bit reversal feature reverses the order of the bits of the input data. Bit reversal is
performed at the output of the 8B/10B Encoder and is available even when the
8B/10B Encoder is disabled. For example, if the input data is 20-bits wide, bit reversal
switches bit [0] with bit [19], bit [1] with bit [18] and so on.
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5.3.1.3.6 8B/10B Encoder Byte Reversal Feature
Figure 257. 8B/10B Encoder Byte Reversal Feature
B
8
Output
Data
A
15 0
Byte Reversal Mode Input
(8B/10B Encoder) Data
7
A
0
B
7 8
15
The byte reversal feature is available only when the PCS-PMA interface width is 16 bits
or 20 bits. Byte reversal is performed at the output of the 8B/10B Encoder and is
available even when the 8B/10B Encoder is disabled. This feature swaps the LSByte
with the MSByte. For example, when the PCS-PMA interface width is 16-bits, [7:0] bits
(LSByte) gets swapped with [15:8] bits (MSByte).
5.3.1.4 Polarity Inversion Feature
The polarity inversion feature is used in situations where the positive and the negative
signals of a serial differential link are erroneously swapped during board layout. You
can control this feature through tx_polinv port, by enabling the Enable TX
Polarity Inversion option under the Standard PCS tab of the Native PHY IP Core. The
polarity inversion feature inverts the value of each bit of the input data. For example,
if the input data is 00101001, then the data gets changed to 11010110 after polarity
inversion.
5.3.1.5 Pseudo-Random Binary Sequence (PRBS) Generator
Note:
Refer to the PRBS Generator section in the Enhanced PCS Architecture chapter.
Related Links
Arria 10 Enhanced PCS Architecture on page 445
5.3.1.6 TX Bit Slip
The TX bit slip allows the word boundary to be controlled by
tx_std_bitslipboundarysel. The TX bit slip feature is used in applications, such
as CPRI, which has a data rate greater than 6 Gbps. The maximum number of the
supported bit slips is PCS data width-1 and the slip direction is from MSB to LSB and
from current to previous word.
5.3.2 Receiver Datapath
5.3.2.1 Word Aligner
The word aligner receives the serial data from the PMA and realigns the serial data to
have the correct word boundary according to the word alignment pattern configured.
This word alignment pattern can be 7, 8, 10, 16, 20, 32 and 40 bits in length.
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Depending on your PCS-PMA interface width, the word aligner can be configured in
one of the following modes:
•
Bit slip
•
Manual alignment
•
Synchronous state machine
•
Deterministic latency
Figure 258. Word Aligner Conditions and Modes
Word
Aligner
Single
Width
Double
Width
8 Bit
Bit Slip Manual
10 Bit
Bit Slip
Deterministic
Latency (1)
16 Bit
Synchronous
State Machine
Manual
Bit Slip Manual
20 Bit
Bit Slip
Deterministic
Latency (1)
Synchronous
State Machine
Manual
Note:
1. This option is available in CPRI mode.
5.3.2.1.1 Word Aligner Bit Slip Mode
In bit slip mode, the word aligner operation is controlled by rx_bitslip, which has
to be held for two parallel clock cycles. At every rising edge of rx_bitslip, the bit
slip circuitry slips one bit into the received data stream, effectively shifting the word
boundary by one bit. Pattern detection is not used in bit slipping mode; therefore,
rx_syncstatus is not valid in this mode.
5.3.2.1.2 Word Aligner Manual Mode
In manual alignment mode, the word aligner operation is controlled by
rx_std_wa_patternalign. The word aligner operation is edge-sensitive or levelsensitive to rx_std_wa_patternalign, depending upon the PCS-PMA interface
width selected.
Table 259.
Word Aligner rx_std_wa_patternalign Behavior
PCS-PMA Interface Width
rx_std_wa_patternalign Behavior
8
Rising edge sensitive
10
Level sensitive
16
Rising edge sensitive
20
Rising edge sensitive
If rx_std_wa_patternalign is asserted, the word aligner looks for the
programmed word alignment pattern in the received data stream. It updates the word
boundary if it finds the word alignment pattern in a new word boundary. If
rx_std_wa_patternalign is deasserted, the word aligner maintains the current
word boundary even when it sees the word alignment pattern in a new word
boundary.
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The rx_syncstatus and rx_patterndetect signals, with the same latency as the
datapath, are forwarded to the FPGA fabric to indicate the word aligner status.
After receiving the first word alignment pattern after rx_std_wa_patternalign is
asserted, both rx_syncstatus and rx_patterndetect are driven high for one
parallel clock cycle. Any word alignment pattern received thereafter in the same word
boundary causes only rx_patterndetect to go high for one clock cycle. Any word
alignment pattern received thereafter in a different word boundary causes the word
aligner to re-align to the new word boundary only if rx_std_wa_patternalign is
asserted. The word aligner asserts rx_syncstatus for one parallel clock cycle
whenever it re-aligns to the new word boundary.
5.3.2.1.3 Word Aligner Synchronous State Machine Mode
In synchronous state machine mode, when the programmed number of valid
synchronization code groups or ordered sets is received, rx_syncstatus is driven
high to indicate that synchronization is acquired. The rx_syncstatus signal is
constantly driven high until the programmed number of erroneous code groups is
received without receiving intermediate good groups, after which rx_syncstatus is
driven low.
The word aligner indicates loss of synchronization (rx_syncstatus remains low)
until the programmed number of valid synchronization code groups are received
again.
5.3.2.1.4 Word Aligner Deterministic Latency Mode
In deterministic latency mode, the state machine removes the bit level latency
uncertainty. The deserializer of the PMA creates the bit level latency uncertainty as it
comes out of reset.
The PCS performs pattern detection on the incoming data from the PMA. The PCS
aligns the data, after it indicates to the PMA the number of serial bits to clock slip the
boundary.
If the incoming data has to be realigned, rx_std_wa_patternalign must be
reasserted to initiate another pattern alignment. Asserting
rx_std_wa_patternalign can cause the word align to lose synchronization if
already achieved. This may cause rx_syncstatus to go low.
Table 260.
PCS-PMA Interface Widths and Protocol Implementations
PCS-PMA Interface Width
Protocol Implementations
8
Basic
10
•
•
•
•
•
16
Basic
20
•
•
•
Basic
Basic rate match
CPRI
PCIe Gen1 and Gen2
GigE
CPRI
Basic
Basic rate match
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5.3.2.1.5 Word Aligner Pattern Length for Various Word Aligner Modes
Table 261.
PCS-PMA
Interface
Width
8
Word Aligner Pattern Length for Various Word Aligner Modes
Supported Word
Aligner Modes
Bit slip
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
8
rx_std_wa_patt
ernalign has no
rx_syncstatus
rx_patterndetect
behavior
behavior
N/A
N/A
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
N/A
N/A
Asserted high for
one parallel clock
cycle when the
word aligner aligns
to a new boundary.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
—
—
Stays high as long
as the
synchronization
conditions are
satisfied.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabricasserted BITSLIP
signal toggles.
Manual
8, 16
Word alignment is
controlled by
rx_std_wa_patt
ernalign and is
edge-sensitive to
this signal.
10
Bit slip
7
rx_std_wa_patt
ernalign has no
effect on word
alignment. The
single width word
aligner updates the
word boundary,
only when the
FPGA fabricasserted BITSLIP
signal toggles.
Manual
7, 10
Word alignment is
controlled by
rx_std_wa_patt
ernalign and is
level-sensitive to
this signal.
Deterministic latency
(CPRI mode only)
10
Word alignment is
controlled by
rx_std_wa_patt
ernalign (edgesensitive to this
signal) and the
state machine
works in
conjunction with
PMA to achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
Synchronous State
Machine
7, 10
rx_std_wa_patt
ernalign has no
effect on word
alignment.
continued...
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PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
rx_patterndetect
behavior
behavior
appears in the
current word
boundary.
16
Bit slip
16
rx_std_wa_patt
ernalign has no
N/A
N/A
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabricasserted BITSLIP
signal toggles.
Manual
8, 16, 32
Word alignment is
controlled by
rising-edge of
rx_std_wa_patt
ernalign.
rx_std_wa_patt
ernalign until a
new word
alignment pattern
is received.
20
Bit slip
7
rx_std_wa_patt
ernalign has no
N/A
N/A
Stays high after
the word aligner
aligns to the word
alignment pattern.
Goes low on
receiving a rising
edge on
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
effect on word
alignment. The
double width word
aligner updates the
word boundary,
only when the
FPGA fabricasserted BITSLIP
signal toggles.
Manual
7, 10, 20, 40
Word alignment is
controlled by rising
edge of
rx_std_wa_patt
ernalign.
rx_std_wa_patt
ernalign until a
new word
alignment pattern
is received.
Deterministic latency
(CPRI mode only)
10
Word alignment is
controlled by
—
—
rx_std_wa_patt
ernalign (edgesensitive to this
signal) and the
deterministic
latency state
machine which
controls the PMA to
continued...
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PCS-PMA
Interface
Width
Supported Word
Aligner Modes
Supported
Word Aligner
Pattern
Lengths
rx_std_wa_patte
rnalign behavior
rx_syncstatus
rx_patterndetect
behavior
behavior
Stays high as long
as the
synchronization
conditions are
satisfied.
Asserted high for
one parallel clock
cycle when the word
alignment pattern
appears in the
current word
boundary.
achieve
deterministic
latency on the RX
path for CPRI and
OBSAI applications.
Synchronous State
Machine
7, 10, 20
FPGA fabric-driven
rx_std_wa_patt
ernalign signal
has no effect on
word alignment.
5.3.2.1.6 Word Aligner RX Bit Reversal Feature
The RX bit reversal feature reverses the order of the data received from the PMA. It is
performed at the output of the Word Aligner and is available even when the Word
Aligner is disabled. If the data received from the PMA is a 10-bit data width, the bit
reversal feature switches bit [0] with bit [9], bit [1] with bit [8], and so on. For
example, if the 10-bit data is 1000010011, the bit reversal feature, when enabled,
changes the data to 1100100001.
5.3.2.1.7 Word Aligner RX Byte Reversal Feature
The RX byte reversal feature is available only when the PCS-PMA interface width is 16
bits or 20 bits. This feature reverses the order of the data received from the PMA. RX
byte reversal reverses the LSByte of the received data with its MSByte and vice versa.
If the data received is 20-bits, bits[0..9] are swapped with bits[10..20] so that the
resulting 20-bit data is [[10..20],[0..9]]. For example, if the 20-bit data is
11001100001000011111, the byte reversal feature changes the data to
10000111111100110000.
5.3.2.2 RX Polarity Inversion Feature
The RX polarity inversion feature inverts each bit of the data received from the PMA. If
the data received is a 10-bit data. Bit[0] content is inverted to its complement,
~bit[0], bit[1] is inverted to its complement, ~bit[1], bit[2] is inverted to its
complement, ~bit[2], and so on. For example, if the 10-bit data is 1111100000, the
polarity inversion feature inverts it to 0000011111.
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5.3.2.3 Rate Match FIFO
The rate match FIFO compensates for the frequency differences between the local
clock and the recovered clock up to ± 300 ppm by inserting and deleting skip/idle
characters in the data stream. The rate match FIFO has several different protocol
specific modes of operation. All of the protocol specific modes depend upon the
following parameters:
•
Rate match deletion—occurs when the distance between the write and read
pointers exceeds a certain value due to write clock having a higher frequency than
the read clock.
•
Rate match insertion—occurs when the distance between the write and the read
pointers becomes less than a certain value due to the read clock having a higher
frequency than the write clock.
•
Rate match full—occurs when the write pointer wraps around and catches up to
the slower-advancing read pointer.
•
Rate match empty—occurs when the read pointer catches up to the sloweradvancing write pointer.
Rate match FIFO operates in six modes:
•
Basic single width
•
Basic double width
•
GigE
•
PIPE
•
PIPE 0 ppm
•
PCIe
Related Links
•
Rate Match FIFO in Basic (Single Width) Mode on page 305
For more information about implementing rate match FIFO in basic single width
mode.
•
Rate Match FIFO Basic (Double Width) Mode on page 307
For more information about implementing rate match FIFO in basic double
width mode.
•
How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers on page
116
For more information about implementing rate match FIFO in GigE mode.
•
PCI Express (PIPE) on page 227
For more information about implementing rate match FIFO in PCIe mode.
•
How to Implement PCI Express (PIPE) in Arria 10 Transceivers on page 244
For more information about implementing rate match FIFO in PIPE mode.
•
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS on page 299
•
How to Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver
Native PHY IP Core on page 299
For more information about implementing rate match FIFO for each mode.
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5.3.2.4 8B/10B Decoder
The general functionality for the 8B/10B decoder is to take a 10-bit encoded value as
input and produce an 8-bit data value and a 1-bit control value as output. In
configurations with the rate match FIFO enabled, the 8B/10B decoder receives data
from the rate match FIFO. In configurations with the rate match FIFO disabled, the
8B/10B decoder receives data from the word aligner. The 8B/10B decoder operates in
two conditions:
•
When the PCS-PMA interface width is 10 bits and FGPA fabric-PCS interface width
is 8 bits
•
When the PCS-PMA interface width is 20 bits and FPGA fabric-PCS interface width
is 16 bits
Figure 259. 8B/10B Decoder in Single-Width and Double-Width Mode
Single-Width Mode
Double-Width Mode
datain[19:10]
rx_dataout[15:8]
8B/10B Decoder
(MSByte)
8B/10B Decoder
(LSByte)
rx_datak
rx_errdetect
rx_disperr
rx_errdetect[1]
rx_disperr[1]
rx_dataout[7:0]
datain[9:0]
rx_datak[1]
recovered clock or
tx_clkout[0]
Current Running Disparity
rx_dataout[7:0]
datain[9:0]
8B/10B Decoder
(LSByte)
recovered clock or
tx_clkout[0]
rx_datak[0]
rx_errdetect[0]
rx_disperr[0]
recovered clock or
tx_clkout[0]
When the PCS-PMA interface width is 10 bits, only one 8B/10B decoder is used to
perform the conversion. When the PCS-PMA interface width is 20 bits, two cascaded
8B/10B decoders are used. The 10-bit LSByte of the received 20-bit encoded data is
decoded first and the ending running disparity is forwarded to the 8B/10B decoder
responsible for decoding the 10-bit MSByte. The cascaded 8B/10B decoder decodes
the 20- bit encoded data into 16-bit data + 2-bit control identifier. The MSB and LSB
of the 2-bit control identifier correspond to the MSByte and LSByte of the 16-bit
decoded data code group. The decoded data is fed to the byte deserializer or the RX
FIFO.
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5.3.2.4.1 8B/10B Decoder Control Code Encoding
Figure 260. 8B/10B Decoder in Control Code Group Detection
When the PCS-PMA Interface Width is 10 Bits
tx_clkout
TX
datain[9:0]
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D3.4
83
78
BC
BC
0F
00
BF
83
rx_datak
RX
dataout[7:0]
When the PCS-PMA Interface Width is 20 Bits
tx_clkout
TX
datain[19:10]
D3.4
D28.5
D15.0
D3.4
D3.4
D28.5
D15.0
D3.4
D24.3
K28.5
D15.0
D3.4
D24.3
K28.5
D15.0
D3.4
rx_datak[1:0]
00
01
00
01
dataout[15:0]
16’h8378
16’hBCBC
16’h8378
16’hBCBC
datain[9:0]
00
00
RX
16’h0F0F
16’h8383
16’h0F0F
16’h8383
The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or
control code group on rx_datak . If the received 10-bit code group is one of the 12
control code groups (/Kx.y/) specified in the IEEE 802.3 specification, rx_datak is
driven high. If the received 10-bit code group is a data code group (/Dx.y/),
rx_datak is driven low.
5.3.2.4.2 8B/10B Decoder Running Disparity Checker Feature
Running disparity checker resides in 8B/10B decoder module. This checker checks the
current running disparity value and error based on the rate match output.
rx_runningdisp and rx_disperr indicate positive or negative disparity and
disparity errors, respectively.
5.3.2.5 Pseudo-Random Binary Sequence (PRBS) Checker
Note:
Refer to the PRBS Checker section in the Enhanced PCS Architecture chapter.
Related Links
Arria 10 Enhanced PCS Architecture on page 445
5.3.2.6 Byte Deserializer
The byte deserializer allows the transceiver to operate at data rates higher than those
supported by the FPGA fabric. It deserializes the recovered data by multiplying the
data width two or four times, depending upon the deserialization mode selected. The
byte deserializer is optional in designs that do not exceed the FPGA fabric interface
frequency upper limit. You can bypass the byte deserializer by disabling it in the
Quartus Prime Transceiver Native PHY. The byte deserializer operates in disabled,
deserialize x2, or deserialize x4 modes.
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Figure 261. Byte Deserializer Block Diagram
Datapath from the
8B/10B Decoder,
Rate Match FIFO,
or Word Aligner
Byte
Deserializer
Low speed
parallel clock
Datapath to the RX PCS FIFO
/2,
/4
5.3.2.6.1 Byte Deserializer Disabled Mode
In disabled mode, the byte deserializer is bypassed. The data from the 8B/10B
decoder, rate match FIFO, or word aligner is directly transmitted to the RX FIFO,
depending on whether or not the 8B/10B decoder and rate match FIFO are enabled.
Disabled mode is used in low speed applications such as GigE, where the FPGA fabric
and the PCS can operate at the same clock rate.
5.3.2.6.2 Byte Deserializer Deserialize x2 Mode
The deserialize x2 mode is used in high-speed applications such as the PCIe Gen1 or
Gen2 protocol implementation, where the FPGA fabric cannot operate as fast as the TX
PCS.
In deserialize x2 mode, the byte deserializer deserializes 8-bit, 10-bit (when the
8B/10B encoder is not enabled), 16-bit, and 20-bit (when the 8B/10B encoder is not
enabled) input data into 16-bit, 20-bit, 32-bit, and 40-bit data, respectively. As the
parallel data width from the word aligner is doubled, the clock rate is halved.
5.3.2.6.3 Byte Deserializer Deserialize x4 Mode
The deserialize x4 mode is used in high-speed applications where the FPGA fabric
cannot operate as fast as the TX PCS.
In deserialize x4 mode, the byte deserializer deserializes 8-bit data into 32-bit data.
As the parallel data width from the word aligner is quadrupled, the clock rate is
divided four times.
5.3.2.6.4 Bonded Byte Deserializer
The bonded byte deserializer is also available for channel-bundled applications such as
PIPE. In this configuration, the control signals of the byte deserializers of all the
channels are bonded together. A master channel controls all the other channels to
prevent skew between the channels.
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5.3.2.7 RX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The RX FIFO interfaces between the PCS on the receiver side and the FPGA fabric and
ensures reliable transfer of data and status signals. It compensates for the phase
difference between the FPGA fabric and the PCS on the receiver side. The RX FIFO has
a depth of 8. It operates in register FIFO and low latency modes.
Figure 262. RX FIFO Block Diagram
RX
FIFO
Datapath from
Byte Deserializer, 8B/10B Decoder,
Rate Match FIFO, or Deserializer
Parallel clock
(recovered)
from clock divider
wr_clk
Datapath to FPGA Fabric
or PIPE Interface
rd_clk
rx_coreclkin
rx_clkout
5.3.2.7.1 RX FIFO Low Latency Mode
The low latency mode incurs two to three cycles of latency when connecting it with the
FPGA fabric. The FIFO empty and the FIFO full threshold values are made closer so
that the depth of the FIFO decreases, which in turn decreases the latency.
5.3.2.7.2 RX FIFO Register Mode
The register mode bypasses the FIFO functionality to eliminate the FIFO latency
uncertainty for applications with stringent latency requirements. This is accomplished
by tying the read clock of the FIFO with its write clock. The register mode incurs only
one clock cycle of latency when interfacing to the FPGA fabric.
5.4 Arria 10 PCI Express Gen3 PCS Architecture
Arria 10 architecture supports the PCIe Gen3 specification. Intel provides two options
to implement the PCI Express solution:
•
You can use the Intel Hard IP solution. This complete package provides both the
MAC layer and the physical (PHY) layer functionality.
•
You can implement the MAC in the FPGA core and connect this MAC to the
transceiver PHY through the PIPE interface.
This section will focus on the basic blocks of PIPE 3.0-based Gen3 PCS architecture.
The PIPE 3.0-based Gen3 PCS uses a 128b/130b block encoding/decoding scheme,
which is different from the 8B/10B scheme used in Gen1 and Gen2. The 130-bit block
contains a 2-bit sync header and a 128-bit data payload. For this reason, Arria 10
devices include a separate Gen3 PCS that supports functionality at Gen3 speeds. This
PIPE interface supports the seamless switching of Data and Clock between the Gen1,
Gen2, and Gen3 data rates, and provides support for PIPE 3.0 features. The PCIe
Gen3 PCS will support the PIPE interface with the Hard IP enabled, as well as with the
Hard IP bypassed.
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Figure 263. Gen3 PCS Block Diagram
TX PCIe Gen3 PCS
Standard
PCS
TX Phase
Compensation
FIFO
Gearbox
32
FPGA
Fabric
tx_coreclkin
TX
PMA
32
tx_clkout
tx_clkout
PIPE Interface
CDR
Control
/4
Auto-Speed Negotiation
Gen3 x1, x2, x4, x8
32
rx_coreclkin
RX
PMA
RX Phase
Compensation
FIFO
32
Rate Match
FIFO
Block
Synchronizer
pll_pcie_clk
RX PCIe Gen3 PCS
tx_clkout
rx_clkout or
tx_clkout
rx_clkout
Clock Generation Block (CGB)
ATX PLL
fPLL
Clock Divider
tx_clkout or rx_clkout
Serial Clock
Parallel and Serial Clocks
hclk for ASN Block
Parallel and Serial Clocks
Serial Clock
Input Reference Clock
Related Links
•
PCI Express (PIPE) on page 227
For more information about PCIe Gen1, Gen2, and Gen3 implementation and
configuration, refer to "Supported PIPE Features."
•
Intel Arria 10 Hard IP for PCIe IP Cores
5.4.1 Transmitter Datapath
This section describes the TX FIFO and the Gearbox of the Gen3 PCS transmitter.
5.4.1.1 TX FIFO (Shared with Standard and Enhanced PCS)
The TX FIFO in each channel ensures a reliable transfer of data and status signals
between the PCS channel and the FPGA fabric. The TX FIFO compensates for the
phase difference between the low speed parallel PCS clock and the FPGA fabric clock.
The RX and TX FIFOs are shared with standard and enhanced PCS. In Hard IP mode,
the TX FIFO works in register mode. In PIPE mode, the TX FIFO works in low latency
mode.
The TX FIFO operates in low latency mode in PIPE Gen1, Gen2, and Gen3
configurations. The Low Latency mode incurs 3-4 cycles of latency when connecting
with the FPGA fabric. The FIFO empty and the FIFO full threshold values are made
closer so that the depth of the FIFO decreases, which decreases the latency.
Related Links
Arria 10 Standard PCS Architecture on page 463
For more information about TX FIFO.
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5.4.1.2 Gearbox
The PCIe 3.0 base specification specifies a block size of 130 bits, with the exception of
the SKP Ordered Sets, which can be of variable length. An implementation of a 130-bit
data path takes significant resources, so the PCIe Gen3 PCS data path is implemented
as 32-bits wide. Because the TX PMA data width is fixed to 32 bits, and the block size
is 130 bits with variations, a gearbox is needed to convert 130 bits to 32 bits.
The gearbox block in the TX PCS converts the 130-bit data
( tx_parallel_data[127:0] + pipe_tx_sync_hdr[1:0]) to 32-bit data required
by the TX PMA as the datapath implementation is 32 bits to reduce usage of
resources. The 130-bit data is received as follows in the 32-bit datapath: 34 (32 + 2bit sync header), 32, 32, 32. During the first cycle the gearbox converts the 34-bit
input data to 32-bit data. During the next 3 clock cycles the gearbox will merge bits
from adjacent cycles to form the 32-bit data. In order for the gearbox to work
correctly, a gap must be provided in the data for every 16 shifts as each shift is 2 bits
for converting the initial 34-bit to 32-bit in the gearbox. After 16 shifts the gearbox
will have an extra 32-bit data that was transmitted out, and thus a gap is required in
the input data stream. This gap is achieved by driving pipe_tx_data_valid low for
one cycle after every 16 blocks of input data(tx_parallel_data).
Related Links
Gearbox on page 237
5.4.2 Receiver Datapath
This section describes the Block Synchronizer, Rate Match FIFO, and RX FIFO of the
Gen3 PCS receiver.
5.4.2.1 Block Synchronizer
PMA parallelization occurs at arbitrary word boundaries. Consequently, the parallel
data from the RX PMA CDR must be realigned to meaningful character boundaries. The
PCI Express 3.0 base specification outlines that the data is formed using 130-bit
blocks, with the exception of SKP blocks.
The SKP Ordered Set can be 66, 98, 130, 162, or 194 bits long. The block
synchronizer searches for the Electrical Idle Exit Sequence Ordered Set (or the last
number of fast training sequences (NFTS) Ordered Set) or skip (SKP) Ordered Set to
identify the correct boundary for the incoming stream and to achieve the block
alignment. The block is realigned to the new block boundary following the receipt of a
SKP Ordered Set, as it can be of variable length.
5.4.2.2 Rate Match FIFO
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clocks. Frequency differences in the order of a few
hundred PPM can corrupt the data when latching from the recovered clock domain to
the local receiver reference clock domain. The rate match FIFO compensates for small
clock frequency differences between these two clock domains by inserting or removing
SKP symbols in the data stream to keep the FIFO from going empty or full
respectively.
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The PCI Express 3.0 base specification defines that the SKP Ordered Set (OS) can be
66, 98, 130, 162, or 194 bits long. The SKP OS has the following fixed bits: 2-bit
Sync, 8-bit SKP END, and a 24-bit LFSR = 34 Bits. The Rate Match/Clock
compensation block adds or deletes the 4 SKP characters (32-bit) to keep the FIFO
from going empty or full, respectively. If the FIFO is nearly full, it deletes the 4 SKP
characters (32-bit) by disabling write whenever a SKP is found. If the FIFO is nearly
empty, the design waits for a SKP Ordered Set to start and then stops reading the
data from the FIFO, and inserts a SKP in the outgoing data. The actual FIFO core
(memory element) is in the Shared Memory block in the PCS channel.
Figure 264. Rate Match FIFO
fifo_pempty
data_out
SKP
Inserter
rd_en
data
fifo_pfull
Asynchronous
FIFO
wr_en
data
rd_clk
SKP
Deleter
data_in
wr_clk
5.4.2.3 RX FIFO (Shared with Standard and Enhanced PCS)
The RX FIFO in each channel ensures a reliable transfer of data and status signals
between the PCS channel and the FPGA fabric. The RX FIFO compensates for the
phase difference between the parallel PCS clock and the FPGA fabric clock. In PIPE
mode, the RX FIFO works in low latency mode.
Related Links
Arria 10 Standard PCS Architecture on page 463
For more information about RX FIFO.
5.4.3 PIPE Interface
This section describes the Auto Speed Negotiation and the Clock Data Recovery
Control of the PIPE interface.
5.4.3.1 Auto Speed Negotiation
Auto speed negotiation controls the operating speed of the transceiver when operating
under PIPE 3.0 modes. By monitoring the pipe_rate signal from the PHY-MAC, this
feature changes the transceiver from PIPE Gen1 operation mode to Gen2 operation
mode, or from PIPE Gen1 operation mode to Gen2 operation mode to Gen3 operation
mode, or vice versa. The PIPE interface clock rate will be adjusted to match the data
throughput.
Related Links
Rate Switch on page 235
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5.4.3.2 Clock Data Recovery Control
The CDR control feature is used for the L0s fast exit when operating in PIPE Gen3
mode. Upon detecting an Electrical Idle Ordered Set (EIOS), this feature takes manual
control of the CDR by forcing it into a lock-to-reference mode. When an exit from
electrical idle is detected, this feature moves the CDR into lock-to-data mode to
achieve fast data lock.
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6 Reconfiguration Interface and Dynamic Reconfiguration
This chapter explains the purpose and the use of the Arria 10 reconfiguration interface
that is part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
Dynamic reconfiguration is the process of dynamically modifying transceiver channels
and PLLs to meet changing requirements during device operation. Arria 10 transceiver
channels and PLLs are fully customizable, allowing a system to adapt to its operating
environment. You can customize channels and PLLs by dynamically triggering
reconfiguration during device operation or following power-up. Dynamic
reconfiguration is available for Arria 10 Transceiver Native PHY, fPLL, ATX PLL, and
CMU PLL IP cores.
Use the reconfiguration interface to dynamically change the transceiver channel or PLL
settings for the following applications:
•
Fine tuning signal integrity by adjusting TX and RX analog settings
•
Enabling or disabling transceiver channel blocks, such as the PRBS generator and
the checker
•
Changing data rates to perform auto negotiation in CPRI, SATA, or SAS
applications
•
Changing data rates in Ethernet (1G/10G) applications by switching between
standard and enhanced PCS datapaths
•
Changing TX PLL settings for multi-data rate support protocols such as CPRI
•
Changing RX CDR settings from one data rate to another
•
Switching between multiple TX PLLs for multi-data rate support
The Native PHY and Transmit PLL IP cores provide the following features that allow
dynamic reconfiguration:
•
Reconfiguration interface
•
Configuration files
•
Feature to add PMA analog settings (optional) to the Configuration files (Native
PHY only)
•
Multiple reconfiguration profiles (Native PHY and ATX PLL)
•
Embedded reconfiguration streamer (Native PHY and ATX PLL)
•
Altera Debug Master Endpoint (ADME)
•
Optional reconfiguration logic
6.1 Reconfiguring Channel and PLL Blocks
The following table lists some of the available dynamic reconfiguration features in
Arria 10 devices.
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ISO
9001:2008
Registered
6 Reconfiguration Interface and Dynamic Reconfiguration
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Table 262.
Arria 10 Dynamic Reconfiguration Feature Support
Reconfiguration
Channel Reconfiguration
Features
PMA analog features
• VOD
• Pre-emphasis
• Continuous Time Linear Equalizer (CTLE)
• Decision Feedback Equalization (DFE)
TX PLL
• TX local clock dividers
• TX PLL switching
RX CDR
• RX CDR settings
• RX CDR reference clock switching
Reconfiguration of PCS blocks within the datapath
Datapath switching
• Standard, Enhanced, PCS Direct
PLL Reconfiguration
PLL settings
• Counters
PLL reference clock switching
Related Links
Unsupported Features on page 545
6.2 Interacting with the Reconfiguration Interface
Each transceiver channel and PLL contains an Avalon Memory-Mapped (Avalon-MM)
reconfiguration interface. The reconfiguration interface provides direct access to the
programmable space of each channel and PLL. Communication with the channel and
PLL reconfiguration interface requires an Avalon-MM master. Because each channel
and PLL has its own dedicated Avalon-MM interface, you can dynamically modify
channels either concurrently or sequentially, depending on how the Avalon-MM master
is connected to the Avalon-MM reconfiguration interface.
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Figure 265. Reconfiguration Interface in Arria 10 Transceiver IP Cores
Native PHY IP Core
Avalon-MM Master
Embedded Controller in FPGA
or Embedded Processor on PCB
Ch0: Avalon
Reconfiguration
Interface
Ch1: Avalon
Reconfiguration
Interface
Transceiver PLL IP Core
Avalon
Reconfiguration
Interface
A transmit PLL instance has a maximum of one reconfiguration interface. Unlike PLL
instances, a Native PHY IP core instance can specify multiple channels. You can use a
dedicated reconfiguration interface for each channel or share a single reconfiguration
interface across all channels to perform dynamic reconfiguration.
Avalon-MM masters interact with the reconfiguration interface by performing Avalon
read and write operations to initiate dynamic reconfiguration of specific transceiver
parameters. All read and write operations must comply with Avalon-MM specifications.
Figure 266. Top-Level Signals of the Reconfiguration Interface
reconfig_clk
reconfig_reset
reconfig_read
reconfig_write
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
Native PHY IP core
or
Transceiver PLL IP core
The user-accessible Avalon-MM reconfiguration interface and PreSICE Avalon-MM
interface share a single internal configuration bus. This bus is arbitrated to get access
to the Avalon-MM interface of the channel or PLL. Refer to the Arbitration section for
more details about requesting access to and returning control of the internal
configuration bus from PreSICE.
Related Links
•
Arbitration on page 494
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•
Reconfiguration Interface and Arbitration with PreSICE Calibration Engine on page
547
•
Avalon Interface Specifications
6.2.1 Reading from the Reconfiguration Interface
Reading from the reconfiguration interface of the Transceiver Native PHY IP core or
Transceiver PLL IP core retrieves the current value at a specific address.
Figure 267. Reading from the Reconfiguration Interface
1
3
5
reconfig_clk
reconfig_address
119h
reconfig_read
2
4
reconfig_waitrequest
reconfig_readdata
Valid readdata
reconfig_write
reconfig_writedata
1. The master asserts reconfig_address and reconfig_read after the rising edge of reconfig_clk.
2. The slave asserts reconfig_waitrequest, stalling the transfer.
3. The master samples reconfig_waitrequest. Because reconfig_waitrequest is asserted, the cycle becomes a wait state and reconfig_address,
reconfig_read, and reconfig_write remain constant.
4. The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest.
5. The master samples reconfig_waitrequest and reconfig_readdata, completing the transfer.
After the reconfig_read signal is asserted, the reconfig_waitrequest signal
asserts for a few reconfig_clock cycles, then deasserts. This deassertion indicates
the reconfig_readdata bus contains valid data.
Note:
You must check for the internal configuration bus arbitration before performing
reconfiguration. Refer to the Arbitration section for more details about requesting
access to and returning control of the internal configuration bus from PreSICE.
Related Links
Arbitration on page 494
6.2.2 Writing to the Reconfiguration Interface
Writing to the reconfiguration interface of the Transceiver Native PHY IP core or TX PLL
IP core changes the data value at a specific address. All writes to the reconfiguration
interface must be read-modify-writes, because two or more features may share the
same reconfiguration address. When two or more features share the same
reconfiguration address, one feature's data bits are interleaved with another feature's
data bits.
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Figure 268. Writing to the Reconfiguration Interface
2
1
reconfig_clk
reconfig_address
119h
reconfig_write
reconfig_writedata
0000000c
reconfig_waitrequest
reconfig_read
reconfig_readdata
1. The master asserts the reconfig_address, reconfig_write, and reconfig_writedata signals.
2. The slave (channel or PLL) captures reconfig_writedata, ending the transfer.
Note:
You must check for the internal configuration bus arbitration before performing
reconfiguration. Refer to the Arbitration section for more details about requesting
access to and returning control of the internal configuration bus from PreSICE.
Related Links
•
Arbitration on page 494
•
Ports and Parameters on page 517
6.3 Configuration Files
The Arria 10 Transceiver Native PHY and Transmit PLL IP cores optionally allow