www.fairchildsemi.com
ILC7080/81
50/100mA SOT-23 CMOS RF LDO™ Regulators
Features
Description
• Ultra low 1mV dropout per 1mA load
• 1% output voltage accuracy
• Uses low ESR ceramic output capacitor to minimize noise
and output ripple
• Only 100µA ground current at 100mA load
• Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz
• Less than 80µVRMS noise at BW = 100Hz to 100kHz
• Excellent line and load transient response
• Over current / over temperature protection
• Guaranteed up to 80/150mA output current
• Industry standard five lead SOT-23 package
• Fixed 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0, 3.1V, 3.3V,
3.6V, 4.7V, 5.0V and adjustable output (ILC7081 only)
voltage options
• Metal mask option available for custom voltages between
2.5 to 5.1V
The ILC7080/81 are 50 or 100mA low dropout (LDO)
voltage regulators designed to provide a high performance
solution to low power systems.
The devices offer a typical combination of low dropout and
low quiescent current expected of CMOS parts, while
uniquely providing the low noise and high ripple rejection
characteristics usually only associated with bipolar LDO
regulators.
The devices have been optimized to meet the needs of
modern wireless communications design; Low noise, low
dropout, small size, high peak current, high noise immunity.
The ILC7080/81 are designed to make use of low cost
ceramic capacitors while outperforming other devices that
require tantalum capacitors.
Applications
•
•
•
•
Cellular phones
Wireless communicators
PDAs / palmtops / organizers
Battery powered portable electronics
Typical Applications
VOUT
5
COUT
SOT-23-5
4
CNOISE
ILC7080
ILC7081
1
2
3
VIN
ON
OFF
REV. 1.0.7 4/3/03
ILC7080/81
Pin Assignments
CNOISE
VOUT
5
SOT23-5 4
1
2
ILC7081-ADJ
1
3
GND
SOT23-5 4
5
ILC7080-xx
ILC7081-xx
VIN
VADJ
VOUT
2
VIN
ON
GND
3
ON
OFF
OFF
Adjustable Voltage Option
Fixed Voltage Option
Pin Description ILC7080/81-xx (fixed voltage version)
Pin Number
Pin Name
1
VIN
2
GND
3
ON/OFF
4
CNOISE
5
VOUT
Pin Description
Connect direct to supply
Ground pin. Local ground for CNOISE and COUT.
By applying less than 0.4V to this pin the device will be turned off.
Optional noise bypass capacitor may be connected between this pin and GND (pin
2). Do not connect CNOISE directly to the main power ground plane.
Output Voltage. Connect COUT between this pin and GND (pin 2).
Pin Description ILC7081-ADJ (adjustable voltage version)
Pin Number
Pin Name
1
VIN
Pin Description
2
GND
3
ON/OFF
4
VADJ
Voltage feedback pin to set the adjustable output voltage. Do not connect a
capacitor to this pin.
5
VOUT
Output Voltage. Connect COUT between this pin and GND (pin 2).
Connect direct to supply
Ground pin. Local ground for CNOISE and COUT.
By applying less than 0.4V to this pin the device will be turned off.
Absolute Maximum Ratings (Note 1)
Parameter
Symbol
Ratings
Units
VIN
VON/OFF
-0.3 to +13.5
-0.3 to VIN
V
Output Current
IOUT
Short circuit protected
mA
Output voltage
VOUT
-0.3 to VIN+0.3
V
PD
250
(Internally Limited)
mW
TJ(max)
-40 to +150
°C
TSTG
-40 to +125
°C
Operating Ambient Temperature
TA
-40 to +85
°C
Package Thermal Resistance
qJA
333
°C/W
Input voltage
On/Off Input voltage
Package Power Dissipation
(SOT-23-5)
Maximum Junction Temp Range
Storage Temperature
Recommended Operating Conditions
Parameter
Input Voltage
Operating Ambient Temperature
2
Min.
Typ.
Max.
Units
VOUT+VDO
VOUT+1
13
V
+85
°C
-40
REV. 1.0.7 4/3/03
ILC7080/81
Electrical Characteristics ILC7080/81AIM5
Unless otherwise specified, all limits are at TA=25°C; VIN = VOUT(NOM) +1V, IOUT = 1mA, COUT = 1µF, VON/OFF = 2V.
Boldface type denotes specifications which apply over the specified operating temperature range.
Parameter
Symbol
Input voltage Range
VIN
Output voltage
VOUT
Feedback Voltage
(ADJ version)
Line Regulation
Conditions
VOUT(NOM) +1V < VIN < 12V
VIN - VOUT
Ground Pin Current
7080 only
IOUT = 50mA
110
7081 only
IOUT = 50mA
50
IOUT = 100mA
100
IOUT = 150mA
150
IOUT = 0mA
95
IOUT = 10mA
100
IOUT = 50mA
100
IOUT = 100mA
100
IOUT = 150mA
115
IGND
7081 only
Shutdown (OFF)
Current
ON/OFF Input
Voltage
ON/OFF Pin Input
Current
Peak Output
Current (Note 4)
Output Noise
Voltage (RMS)
Ripple Rejection
ION/OFF
VON/OFF
IIN( ON/OFF)
IOUT(peak)
eN
∆VOUT/∆VIN
Dynamic Line
Regulation
Dynamic Load
Regulation
Short Circuit Current
REV. 1.0.7 4/3/03
∆VOUT(line)
∆VOUT(load)
ISC
13
0.1
7080/81
10
VON/OFF = 0V
High = Regulator On
Low = Regulator Off
VON/OFF = 0.6V, regulator OFF
VON/OFF = 2V, regulator ON
VOUT > 0.95VOUT(NOM), tpw=2ms
BW=300Hz to 50kHz, CNOISE=0.01µF
Freq. = 1kHz
Freq. = 10kHz
Freq. = 1MHz
VIN: VOUT(NOM)+1V to VOUT(NOM)+2V,
tr/tf = 2µs; IOUT = 100mA
IOUT: 0 to 100mA;
d(IOUT)/dt = 100mA/µs with
COUT = 0.47µF with
COUT = 2.2µF
VOUT = 0V
COUT = 4.7µF,
IOUT = 100mA
Max.
-1
VOUT(NOM)
+1
-1.5
1.5
-3.5
+3.5
1.215
1.240
1.265
1.202
1.278
0.007
0.014
0.032
IOUT= 0mA
(Note 4)
IOUT = 10mA
7080/81
Dropout voltage
(Note 3)
Typ.
2
IOUT = 1mA
1mA < IOUT < 100mA
1mA < IOUT < 100mA
VADJ
∆VOUT/
(VOUT*∆VIN)
Min.
0.1
1
2
25
35
125
150
75
100
150
200
225
300
200
220
220
240
220
240
240
260
260
280
2
2.0
Units
V
%
V
%/V
mV
µA
µA
V
0.6
400
0.3
1
500
mA
80
µVRMS
85
70
60
4
dB
50
25
600
µA
mV
mV
mA
3
ILC7080/81
Notes:
1. Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical
specifications do not apply when operating the device outside of its rated operating conditions.
2. Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods.
Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing.
3. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal
value measured with a 1V differential.
4. Guaranteed by design.
Operations
Instead of powering the critical circuits from the unregulated
input voltage, the CMOS RF LDO powers the internal
circuits such as the bandgap, the error amplifier and most of
the transconductance amplifier from the boot strapped regulated output voltage of the regulator. This technique offers
extremely high ripple rejection and excellent line transient
response.
4
A block diagram of the regulator circuit used in the
ILC7080/81 is shown in figure 2, which shows the input-tooutput isolation and the cascaded sequence of amplifiers that
implement the pole-zero scheme outlined above.
The ILC7080/81 were designed in a CMOS process with
some minor additions, which allow the circuit to be used at
input voltages up to 13V. The resulting circuit exceeds the
frequency response of traditional bipolar circuits. The
ILC7080/81 is very tolerant of output load conditions with
the inclusion of both short circuit and thermal overload
protection. The device has a very low dropout voltage,
typically a linear response of 1mV per milliamp of load
current, and none of the quasi-saturation characteristics of a
bipolar output device. All the good features of the frequency
response and regulation are valid right to the point where the
regulator goes out of regulation in a 4mV transition region.
Because there is no base drive, the regulator is capable of
providing high current surges while remaining in regulation.
This is shown in the high peak current of 500mA which
allows for the ILC7080/81 to be used in systems that require
short burst mode operation.
DOMINANT POLE
85 dB
OUTPUT POLE
GAIN
The ILC7080/81 LDO design is based on an advanced circuit configuration for which patent protection has been
applied. Typically it is very difficult to drive a capacitive output with an amplifier. The output capacitance produces a
pole in the feedback path, which upsets the carefully tailored
dominant pole of the internal amplifier. Traditionally the
pole of the output capacitor has been “eliminated” by reducing the output impedance of the regulator such that the pole
of the output capacitor is moved well beyond the gain bandwidth product of the regulator. In practice, this is difficult to
do and still maintain high frequency operation. Typically the
output impedance of the regulator is not simply resistive,
such that the reactive output impedance interacts with the
reactive impedance of the load resistance and capacitance.
In addition, it is necessary to place the dominant pole of the
circuit at a sufficiently low frequency such that the gain of
the regulator has fallen below unity before any of the complex interactions between the output and the load occur. The
ILC7080/81 does not try to eliminate the output pole, but
incorporates it into the stability scheme. The load and output
capacitor forms a pole, which rolls off the gain of the regulator below unity. In order to do this the output impedance of
the regulator must be high, looking like a current source.
The output stage of the regulator becomes a transconductance amplifier, which converts a voltage to a current with a
substantial output impedance. The circuit which drives the
transconductance amplifier is the error amplifier, which
compares the regulator output to the band gap reference and
produces an error voltage as the input to the transconductance amplifier. The error amplifier has a dominant pole at
low frequency and a “zero” which cancels out the effects of
the pole. The zero allows the regulator to have gain out to the
frequency where the output pole continues to reduce the gain
to unity. The configuration of the poles and zero are shown in
figure 1.
COMPENSATING
ZERO
UNITY GAIN
FREQUENCY
Figure 1. LC7080/81 RF LDO frequency response
REV. 1.0.7 4/3/03
ILC7080/81
INTERNAL VDD
VIN
CNOISE
BANDGAP
REFERENCE
VREF
TRANSCONDUCTANCE
AMPLIFIER
ERROR
AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Figure 2. ILC7080/81 RF LDO regulator block diagram
Shutdown (ON/OFF) Operation
Adjustable Output Voltage
The ILC7080/81 output can be turned off by applying 0.4V
or less to the device’s ON/OFF pin (pin 3). In shutdown
mode, the ILC7080/81 draws less than 1µA quiescent current. The output of the ILC7081 is enabled by applying 2V to
13V at the ON/OFF pin. In applications where the ILC7080/
81 output will always remain enabled, the ON/OFF pin may
be connected to VIN (pin 1). The ILC7080/81’s shutdown
circuitry includes hysteresis, as such the device will operate
properly even if a slow moving signal is applied to the ON/
OFF pin.
Figure 3 shows how an adjustable output voltage can be
easily achieved using ILC7081-ADJ. The output voltage,
VOUT is given by the following equation:
Short Circuit Protection
The ILC7080/81 output can withstand momentary short
circuit to ground. Moreover, the regulator can deliver very
high output peak current due to its 1A instantaneous short
circuit current capability.
Thermal Protection
The ILC7080/81 also includes a thermal protection circuit
which shuts down the regulator when die temperature
exceeds 150˚C due to overheating. In thermal shutdown,
once the die temperature cools to below 140˚C, the regulator
is enabled. If the die temperature is excessive due to high
package power dissipation, the regulator’s thermal circuit
will continue to pulse the regulator on and off. This is called
thermal cycling.
Excessively high die temperature may occur due to high
differential voltage across the regulator or high load current
or high ambient temperature or a combination of all three.
Thermal protection protects the regulator from such fault
conditions and is a necessary requirement in today’s designs.
In normal operation, the die temperature should be limited to
under 150˚C.
REV. 1.0.7 4/3/03
VOUT = 1.24V x (R1/R2 + 1)
R2
R1
VOUT
5 SOT23-5 4 VADJ
ILC7081-ADJ
COUT
VIN
CIN
1
2
3
ON
OFF
Figure 3. Application circuit for adjustable output voltage
For best results, a resistor value of 470kΩ or less may be
used for R2. The output voltage can be programmed from
2.5V to 12V.
Note: An external capacitor should not be connected to the
adjustable feedback pin (pin 4). Connecting an external
capacitor to pin 4 may cause regulator instability and lead to
oscillations.
5
ILC7080/81
Maximum Output Current
The maximum output current available from the ILC7080/81
is limited by the maximum package power dissipation as
well as the device’s internal current limit. For a given ambient temperature, TA, the maximum package power dissipation is given by:
PD(max) = (TJ(max) - TA) / θJA
where TJ(max) = 150˚C is the maximum junction temperature
and θJA = 333˚C/W is the package thermal resistance. For
example at TA = 85˚C ambient temperature, the maximum
package power dissipation is;
PD(max) = 195mW.
The maximum output current can be calculated from the following equation:
IOUT(max) < PD(max) / (VIN - VOUT)
For example at VIN = 6V, VOUT = 5V and TA = 85˚C, the
maximum output current is IOUT(max) < 195mA. At higher
output current, the die temperature will rise and cause the
thermal protection circuit to be enabled.
Application Hints
Figure 4 shows the typical application circuit for the
ILC7080/81.
VOUT
5 SOT23-5 4
1
2
Output Capacitor Selection
Fairchild strongly recommends the use of low ESR (equivalent
series resistance) ceramic capacitors for COUT and CNOISE. The
ILC7080/81 is stable with low ESR capacitor (as low as zero
Ω). The value of the output capacitor should be 1µF or higher.
Either ceramic chip or a tantalum capacitor may be used at the
output.
Use of ceramic chip capacitors offer significant advantages over
tantalum capacitors. A ceramic capacitor is typically considerably cheaper than a tantalum capacitor, it usually has a smaller
footprint, lower height, and lighter weight than a tantalum
capacitor. Furthermore, unlike tantalum capacitors which are
polarized and can be damaged if connected incorrectly, ceramic
capacitors are non-polarized. Low value ceramic chip capacitors
with X7R dielectric are available in the 100pF to 4.7µF range,
while high value capacitors with Y5V dielectric are available in
the 2200pF to 22µF range. Evaluate carefully before using
capacitors with Y5V dielectric because their ESR increases significantly at cold temperatures. Figure 10 shows a list of recommended ceramic capacitors for use at the output of ILC7080/81.
Note: If a tantalum output capacitor is used then for stable
operation we recommend a low ESR tantalum capacitor with
maximum rated ESR at or below 0.4Ω. Low ESR tantalum
capacitors, such as the TPS series from AVX Corporation
(www.avxcorp.com) or the T495 series from Kemet
(www.kemet.com) may be used.
In applications where a high output surge current can be
expected, use a high value but low ESR output capacitor for
superior load transient response. The ILC7080/81 is stable with
no load.
ILC7080
ILC7081
COUT
VIN
CNOISE
output voltage by a couple of hundred milivolts then the regulator may be damaged. This condition must be avoided. In many
applications a large value input capacitor, CIN, will hold VIN
higher than VOUT and decay slower than VOUT when the LDO is
powered off.
3
Noise Bypass Capacitor
ON
OFF
Figure 4. Basic application circuit for fixed output voltage
Input Capacitor
An input capacitor CIN of value 1µF or larger should be connected from VIN to the main ground plane. This will help to filter supply noise from entering the LDO. The input capacitor
should be connected as close to the LDO regulator input pin as
is practical. Using a high-value input capacitor will offer superior line transient response as well as better power supply ripple
rejection. A ceramic or tantalum capacitor may be used at the
input of the LDO regulator.
Note that there is a parasitic diode from the LDO regulator output to the input. If the input voltage swings below the regulator’s
6
In low noise applications, the self noise of the ILC7080/81 can
be decreased further by connecting a capacitor from the noise
bypass pin (pin 4) to ground (pin 2). The noise bypass pin is a
high impedance node as such, care should be taken in printed
circuit board layout to avoid noise pick-up from external
sources. Moreover, the noise bypass capacitor should have low
leakage.
Noise bypass capacitors with a value as low as 470pF may be
used. However, for optimum performance, use a 0.01µF or
larger, ceramic chip capacitor. Note that the turn on and turn off
response of the ILC7080/81 is inversely proportional to the
value of the noise bypass capacitor. For fast turn on and turn off,
use a small value noise bypass capacitor. In applications were
exceptionally low output noise is not required, consider omitting the noise bypass capacitor altogether.
REV. 1.0.7 4/3/03
ILC7080/81
The Effects of ESR (Equivalent
Series Resistance)
Printed Circuit Board Layout
Guidelines
The ESR of a capacitor is a measure of the resistance due to the
leads and the internal connections of the component. Typically
measured in mΩ (milli-ohms) it can increase to ohms in some
cases.
As was mentioned in the previous section, to take full advantage of any high performance LDO regulator requires paying
careful attention to grounding and printed circuit board
(PCB) layout.
IOUT
R*
IC
COUT
RC
5 SOT-23-5 4
CNOISE
ILC7080
ILC7081
VIN
1
R*
CIN
2
RF LDOTM
Regulator
3
I2
I1
ESR
5 SOT-23-5 4
COUT
VIN
1
V IN
2
3
RPCB
RPCB
ON
OFF
Figure 6. Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB
layout caused by the ESR and PCB resistances and the
accumulation of current flows.
Note particularly that during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and CNOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between COUT, CNOISE and the LDO regulator’s ground pin
will degrade performance of the LDO.
ON
VOUT
OFF
5
With a degree of care, the ILC7080/81 will yield outstanding
performance.
4
ILC7080/81
SOT23-5
VIN
CIN
1
2
GND2
3
GND
With this in mind low ESR components will offer better performance as LDOs may be exposed to large transients of output
voltage, and current flows through the capacitors in order to filter these transient swings. ESR is less of a problem with CIN as
the voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the resistance inherent in the PCB trace. Figure 6 shows where the additive resistance of the PCB can manifest itself. Again these
resistances may be very small, but a summation of several currents can develop detectable voltage ripple and will be amplified
by the LDO. Particularly the accumulation of current flows in
the ground plane can develop significant voltages unless care is
taken.
CNOISE
ILC7080
ILC7081
Figure 5. ESR in COUT and CNOISE
REV. 1.0.7 4/3/03
RPCB
RPCB
CNOISE
VOUT
RPCB
COUT
ON/OFF
GND1
True GND
(0V)
ILOAD
+IC
OUT
+IC
NOISE
+IGND
LOAD
With reference to the block diagram in figure 2, VOUT is fed
back to the error amplifier and is used as the supply voltage for
the internal components of the 7080/81. So any change in VOUT
will cause the error amplifier to try to compensate to maintain
VOUT at the set level and noise on VOUT will be reflected into
the supply of each internal circuit. The reference voltage, VREF,
is influenced by the CNOISE pin. Noise into this pin will add to
the reference voltage and be fed through the circuit. These factors will not cause a problem if some simple steps are taken.
Figure 5 shows where these added ESR resistances are present
in the typical LDO circuit.
VOUT IOUT
ESR
Wherever there is a combination of resistance and current, voltages will be present. The control functions of LDOs use two
voltages in order to maintain the output precisely; VOUT and
VREF.
GND3
ILOAD
Figure 7. Effects of poor circuit layout
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground current and noise bypass current return of the LDO regulator.
Note that the key difference here is that COUT and CNOISE are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
7
ILC7080/81
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
VOUT
5
CNOISE
0.01µF
4
ILC7080
SOT23-5
DC/DC
Converter
+
GND
Ground Plane
VIN
1
CIN
1µF
Ground Plane
2
3
ON/OFF
L
O
A
ESR<0.5Ω
D
Local
Ground
VBATT
COUT
4.7µF
Ground Plane
Ground Plane
Figure 8. Recommended application circuit schematic
Figure 9. Recommended application circuit layout
(not drawn to scale).
Note: ground plane is bottom layer of PCB and connects to
top layer ground connections through vias.
Evaluation Board Parts List For Printed Circuit Board Shown Above
Label
Part Number
Manufacturer
Description
U1
ILC7081AIM5-30
Fairchild Semi.
100mA RF LDOTM regulator
J1
69190-405
Berg
Connector, four position header
CIN
GRM40 Y5V 105Z16
muRata
Ceramic capacitor, 1µF,16V, SMT (size 0805)
CNOISE
ECU-V1H103KBV
Panasonic
Ceramic capacitor, 0.01µF,16V, SMT (size 0603)
COUT
GRM42-6X5R475K10
muRata
Ceramic capacitor, 4.7µF,16V, SMT (size 1206)
Grounding Recommendations
1.
Connect CIN between VIN of the ILC7080/81 and the “GROUND PLANE”.
2.
Keep the ground side of COUT and CNOISE connected to the “LOCAL GROUND” and not directly to the “GROUND
PLANE”.
3.
On multilayer boards use component side copper for grounding around the ILC7080/81 and connect back to a “GROUND
PLANE” using vias.
4.
If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the
control signals. The star should radiate from where the power supply enters the PCB.
Layout Considerations
1.
Place all RF LDO related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT as close together as possible.
2.
Keep the output capacitor COUT as close to the ILC7080/81 as possible with very short traces to the VOUT and GND pins.
3.
The traces for the related components; ILC7080/81, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor COUT can be run with minimum trace widths close to the LDO.
4.
Maintain a separate “LOCAL GROUND” remote from the “GROUND PLANE” to ensure a quiet ground near the LDO.
Figure 9 shows how this circuit can be translated into a PCB layout.
8
REV. 1.0.7 4/3/03
ILC7080/81
Recommended Ceramic Output Capacitors
COUT
Capacitor Size
IOUT
1µF
0805
0 to 100mA
X5R
C2012X5R1A105KT
TDK
“
0805
“
X7R
GRM40X7R105K010
muRata
“
0805
“
X7R
LMK212BJ105KG
Taiyo-Yuden
“
1206
“
X7R
GRM42-6X7R105K016
muRata
“
1206
“
X7R
EMK316BJ105KL
Taiyo-Yuden
“
1206
“
X5R
TMK316BJ105KL
Taiyo-Yuden
2.2µF
0805
0 to 150mA
X5R
GRM40X5R225K 6.3
muRata
“
0805
“
X5R
C2012X5R0J225KT
TDK
“
1206
“
X5R
EMK316BJ225ML
Taiyo-Yuden
4.7µF
1206
0 to 150mA
X5R
GRM42-6X5R475K010
muRata
“
1206
“
X7R
LMK316BJ475ML
Taiyo-Yuden
REV. 1.0.7 4/3/03
Dielectric
Part Number
Capacitor Vendor
9
ILC7080/81
Typical Performance Characteristics
Unless otherwise specified TA =25˚C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN.
Characterization at output currents above 50mA applies to ILC7081.
Dropout Characteristics
Output voltage vs Temperature
3.4
3.015
3.01
Output voltage (V)
VOUT = 3.3V
COUT = 0.47 µF (Ceramic)
VOUT = 3.0V
COUT = 0.47 µF (Ceramic)
IOUT = 0mA
IOUT = 10mA
IOUT = 50mA
3.3
VOUT (V)
3.005
3
2.995
3.2
7081 only
IOUT = 100mA
3.1
IOUT = 150mA
2.99
3
2.985
-50
0
50
100
3
150
3.2
Temperature (°C)
Dropout voltage vs Temperature
3.6
Dropout voltage vs IOUT
250
250
IOUT = 150mA
VOUT = 3.0V
VOUT = 3.0V
200
TA = 85°C
200
IOUT = 100mA
150
100
IOUT = 50mA
50
Dropout voltage (mV)
Dropout voltage (mV)
3.4
VIN (V)
TA = 25°C
150
100
TA = –40°C
50
IOUT = 0mA
0
0
–40
25
85
0
Temperature (°C)
6
VIN (V)
VOUT = 3.0 V
IOUT = 10mA
COUT = 0.47 µF (Ceramic)
IOUT = 50mA
IOUT = 150mA
5
VIN: tr/tf < 1 µs
VOUT = 3.0V
COUT = 2.2 µF (Ceramic)
IOUT = 100 mA
4
100
IOUT = 100mA
75
3.01
3.00
2.99
2.98
50
2
10
150
IOUT = 0mA
VOUT (V)
IGND (µA)
125
100
Line Transient Response
Ground Current vs Input voltage
150
50
Output Current (mA)
4
6
8
VIN (V)
10
12
14
5µs/div
REV. 1.0.7 4/3/03
ILC7080/81
Typical Performance Characteristics
Unless otherwise specified TA =25˚C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN.
Characterization at output currents above 50mA applies to ILC7081.
Line Transient Response ILC7081
VIN (V)
4
COUT = 0.47 µF (Ceramic)
3.01
3.01
3.00
3.00
VOUT (V)
VOUT (V)
4
2.99
2.98
VIN: tr/tf = 2 µs
VOUT = 3.0V
IOUT = 50 mA
5
VIN (V)
VIN: tr/tf = 2 µs
VOUT = 3.0V
IOUT = 100 mA
5
Line Transient Response
COUT = 0.47 µF (Ceramic)
2.99
2.98
2.97
5µs/div
5µs/div
Load Transient Response
3.04
VOUT = 3.0 V
COUT = 0.47 µF (Ceramic)
3.02
Load Transient Response ILC7081
3.15
VOUT (V)
VOUT (V)
3.06
3.00
3.10
VOUT = 3.0V
COUT = 0.47 µF (Ceramic)
3.05
3.00
IOUT (mA)
IOUT (mA)
2.98
50
1
100
1
100µs/div
100µs/div
Load Transient Response ILC7081
VOUT (V)
3.15
3.10
Short Circuit Current
VOUT = 3.0V
COUT = 1 µF || 0.47 µF (Ceramic)
VIN = 4V
Output Shorted to Gnd
1.5 at time, t = 0
3.05
ISC (A)
3.00
IOUT (mA)
2.95
Thermal Cycling
1.0
0.5
100
0
1
100µs/div
REV. 1.0.7 4/3/03
t=0
5ms/div
11
ILC7080/81
Typical Performance Characteristics
Unless otherwise specified TA =25˚C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN.
Characterization at output currents above 50mA applies to ILC7081.
On/Off Transient Response
4
2
COUT = 0.47 µF (Ceramic)
VOUT = 3.0 V
IOUT = 50mA
3
VIN (V)
VOUT = 3.0V
3 IOUT = 10mA
2
1
1
0
0
COUT = 0.47 µF (Ceramic)
1
VON/OFF
VON/OFF
VOUT (V)
On/Off Transient Response
5
0
5
0
500µs/div
200µs/div
On/Off Transient Response ILC7081
Spectral Noise Density
4
32.0
VIN (V)
VOUT = 3.0V
3 IOUT = 100mA
10.0
Noise (µV/Rt Hz)
2
1
COUT = 0.47 µF (Ceramic)
0
VON/OFF
VOUT = 3.0 V
IOUT = 50mA
CNOISE = 0.01 µF (ceramic)
17.8
5
5.6
3.2
1.0
0.6
0.3
0
COUT = 0.47 µF (Ceramic)
COUT = 1 µF (Ceramic)
1.8
0.2
COUT = 2.2 µF (Ceramic)
COUT = 4.7 µF (Ceramic)
0.1
100
200µs/div
10K
1K
100K
1M
Freq (Hz)
Spectral Noise Density
with COUT = 10µF (Ceramic)
(For Ultra Low Noise)
Spectral Noise Density
32.0
17.8
IOUT = 1mA
1.8
IOUT = 10 mA
1.0
0.6
4.2
1.8
1.2
IOUT = 100 mA
0.6
Freq (Hz)
100K
1M
VIN = 6V
2.4
0.2
10K
VIN = 4V
3.0
IOUT = 50mA
1K
VIN = 3.5V
3.6
0.3
0.1
100
12
4.8
5.6
3.2
VOUT = 3.0 V
CNOISE = 1 µF (Ceramic)
5.4
Noise (µV/Rt Hz)
Noise (µV/Rt Hz)
10.0
6.0
VOUT = 3.0 V
COUT = 0.47µF (Ceramic)
CNOISE = 0.01 µF (Ceramic)
0
100
VIN = 8V
1K
10K
100K
Freq (Hz)
REV. 1.0.7 4/3/03
ILC7080/81
Typical Performance Characteristics
Unless otherwise specified TA =25˚C, VIN =VOUT(NOM), + 1V, ON/OFF pin tied to VIN.
Characterization at output currents above 50mA applies to ILC7081.
Ripple Rejection vs Frequency
Ripple Rejection vs Frequency
100
100
VOUT = 3.0V
IOUT = 10mA
80
COUT = 4.7 µF (Ceramic)
70
VOUT = 3.0V
IOUT = 100mA
90
Ripple Rejection (dB)
Ripple Rejection (dB)
90
60
50
40
30
20
80
COUT = 4.7 µF (Ceramic)
70
60
50
40
30
20
COUT = 2.2 µF (Ceramic)
10
0
COUT = 2.2 µF (Ceramic)
10
0
1K
10K
100K
Frequency (Hz)
REV. 1.0.7 4/3/03
1M
10M
1K
10K
100K
1M
10M
Frequency (Hz)
13
ILC7080/81
Package Outline Dimensions
Dimensions shown in inches and (mm).
5-Lead plastic surface mount (SOT-23-5)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
0.055 (1.40)
0.118 (3.00)
0.102 (2.60)
PIN 1
0.037 (0.95) BSC
0.055 (1.40)
0.0393 (1.0)
0.057 (1.45)
0.035 (0.90)
0.0059 (0.15)
0.0019 (0.05)
14
0.019 (0.50)
0.0138 (0.35)
SEATING
PLANE
0.0078 (0.2)
0.0031 (0.08)
10°
0°
0.0217 (0.55)
0.0138 (0.35)
REV. 1.0.7 4/3/03
ILC7080/81
Ordering Information (TA = -40°C to +85°C)
ILC7080AIM5-xx
Output voltage (V)
Grade
2.6
A
2.7
2.8
Order Information
*Package Marking
Supplied as:
ILC7080AIM526x
CIx
3k Units on Tape and Reel
A
ILC7080AIM527x
CMx
3k Units on Tape and Reel
A
ILC7080AIM528x
CJ0x
3k Units on Tape and Reel
2.85
A
ILC7080AIM5285x
CFx
3k Units on Tape and Reel
2.9
A
ILC7080AIM529x
CKx
3k Units on Tape and Reel
3.0
A
ILC7080AIM530x
CAx
3k Units on Tape and Reel
3.1
A
ILC7080AIM531x
CLx
3k Units on Tape and Reel
3.3
A
ILC7080AIM533x
CBx
3k Units on Tape and Reel
5.0
A
ILC7080AIM550x
CCx
3k Units on Tape and Reel
* Note: First two characters identify the product and the last character identifies the lot code
ILC7081AIM5-xx
Output voltage (V)
Grade
*Package Marking
Supplied as:
2.5
A
ILC7081AIM525x
Order Information
CXx
3k Units on Tape and Reel
2.6
A
ILC7081AIM526x
CPx
3k Units on Tape and Reel
2.7
A
ILC7081AIM527x
CNx
3k Units on Tape and Reel
2.8
A
ILC7081AIM528x
CJx
3k Units on Tape and Reel
2.85
A
ILC7081AIM5285x
CVx
3k Units on Tape and Reel
2.9
A
ILC7081AIM529x
COx
3k Units on Tape and Reel
3.0
A
ILC7081AIM530x
CQx
3k Units on Tape and Reel
3.1
A
ILC7081AIM531x
CYx
3k Units on Tape and Reel
3.3
A
ILC7081AIM533x
CRx
3k Units on Tape and Reel
3.6
A
ILC7081AIM536x
CTx
3k Units on Tape and Reel
4.7
A
ILC7081AIM547x
CWx
3k Units on Tape and Reel
5.0
A
ILC7081AIM550x
CSx
3k Units on Tape and Reel
ADJ
A
ILC7081AIM5ADJx
CUx
3k Units on Tape and Reel
* Note: First two characters identify the product and the last character identifies the lot code
Summary
ILC7080AIM5xx
50mA, fixed voltage
ILC7081AIM5xx
100mA, fixed voltage
ILC7081AIM5ADJ
100mA, adjustable voltage
REV. 1.0.7 4/3/03
15
ILC7080/81
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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4/3/03 0.0m 001
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2002 Fairchild Semiconductor Corporation