tms320c6201/tms320c6701 evaluation module technical reference

TMS320C6201/6701 Evaluation Module
Technical Reference
Literature Number: SPRU305
December 1998
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
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TI assumes no liability for applications assistance, customer product design, software
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machine, or process in which such semiconductor products or services might be or are used.
Copyright  1998, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This document provides technical information that describes the TMS320C6x
(’C6x) evaluation module (EVM) functionality.
It is assumed that you are already in possession or have access to the
companion TMS320C6201/C701 EVM User’s Guide SPRU269C, for a
thorough review of how to install and operate the ’C6x EVM. For up-to-date
information on the ’C6x EVM, as well as related products, visit the ’C6000
website at:
http://www.ti.com/sc/docs/dsps/tools/c6000/index.htm.
How to Use This Manual
This reference provides the following types of information about the ’C6x EVM:
J
Chapter 1 describes the theory of operation for the ’C6x EVM
hardware, including key component identification, detailed
information about each functional area, and interface descriptions.
J
Chapter 2 describes the ’C6x EVM host software utilities.
J
Chapter 3 describes the DSP host support software. It includes a
complete API reference that allows you to write your own applications
for the ’C6x EVM and also includes example applications that use the
API calls.
- Reference material, consisting of Appendixes A through E, provides
quick reference information for the ’C6x EVM:
J
Appendix A provides the EVM connector pinouts.
J
Appendix B contains the EVM schematics.
J
Appendix C provides the EVM complex programmable logic device
(CPLD) equations.
J
Appendix D summarizes the EVM PCI configuration EEPROM.
J
Appendix E provides a glossary of terms used in this manual.
iii
Notational Conventions
Notational Conventions
This document uses the following conventions:
Program listings, program examples, and interactive displays are shown
in a special typeface. Some examples use a bold version for
emphasis; interactive displays use a bold version to distinguish
commands that you enter from items that the system displays (such as
prompts, command output, error messages, etc.).
Here is a sample program listing with the evm6x_close( ) function
highlighted for emphasis:
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
exit(–1);
}
. . .
evm6x_close( h_board );
In syntax descriptions, the instruction or command is in a bold face, and
parameters are in italics. Portions of a syntax that are in bold should be
entered as shown; portions of a syntax that are in italics describe the type
of information that should be entered. Here is an example of a command
syntax:
evm6xldr filename
Square brackets ( [ and ] ) identify an optional parameter. If you use an
optional parameter, you specify the information within the brackets; you
do not enter the brackets themselves. Here is an example of a command
that has optional parameters.
evm6xtst [options] [log_filename]
evm6xtst is the command. This command has two optional parameters,
indicated by options and log_filename.
Device pins often are represented in groups. Device pin group notation
consists of the pin name followed by brackets containing the range of pins
included in the group. A colon separates the numbers in the range. For
example, PDB[7:0] represents the 8 peripheral data bus pins (PDB7
through PDB0) on a device.
iv
Notational Conventions / Information About Cautions and Warnings
The TMS320C6x family of devices is referred to as the ’C6x. The following
abbreviations are used in this manual for TI devices on the ’C6x EVM:
Abbreviation
Device Definition
’C6201
TMS320C6201
’ALB16244
SN74ALB16244
’CBT3257
SN74CBT3257
’CBTD3384
SN74CBTD3384
’LVT125
SN74LVT125
’LVTH162245
SN74LVTH162245
Information About Cautions and Warnings
This book contains cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Read This First
v
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following books describe the ’C6x processor and related support tools. To
obtain a copy of any of these TI documents, call the Texas Instruments
Literature Response Center at (800)477–8924. When ordering, please
identify the book by its title and literature number.
TMS320C6x Assembly Language Tools User’s Guide (literature number
SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the ’C6x generation of devices.
TMS320C6x C Source Debugger User’s Guide (literature number
SPRU188) tells you how to invoke the ’C6x simulator and emulator
versions of the C source debugger interface. This book discusses
various aspects of the debugger, including command entry, code
execution, data management, breakpoints, profiling, and analysis.
TMS320C6x Optimizing C Compiler User’s Guide (literature number
SPRU187) describes the ’C6x C compiler and the assembly optimizer.
This C compiler accepts ANSI standard C source code and produces
assembly language source code for the ’C6x generation of devices. The
assembly optimizer helps you optimize your assembly code.
TMS320C62x/C67x CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the ’C62x/C67x CPU architecture,
instruction set, pipeline, and interrupts for these digital signal
processors.
TMS320C6201/C6701 Peripherals Reference Guide (literature number
SPRU190) describes common peripherals available on the
TMS320C6201/C6701 digital signal processors. This book includes
information on the internal data and program memories, the external
memory interface (EMIF), the host port, multichannel buffered serial
ports, direct memory access (DMA), clocking and phase-locked loop
(PLL), and the power-down modes.
TMS320C62x/C67x Programmer’s Guide (literature number SPRU198)
describes ways to optimize C and assembly code for the
TMS320C62x/C67x DSPs and includes application program examples.
TMS320C62x/C67x Technical Brief (literature number SPRU197) gives an
introduction to the ’C62x/C67x digital signal processors, development
tools, and third-party support.
XDS51x Emulator Installation Guide (literature number SPNU070)
describes the installation of the XDS510, XDS510PP, and
XDS510WS emulator controllers. The installation of the XDS511
emulator is also described.
vi
Trademarks
TMS320 DSP Development Support Reference Guide (literature number
SPRU011) describes the TMS320 family of digital signal processors and
the tools that support these devices. Included are code-generation tools
(compilers, assemblers, linkers, etc.) and system integration and debug
tools (simulators, emulators, evaluation modules, etc.). Also covered are
available documentation, seminars, the university program, and factory
repair and exchange.
TMS320C6x Peripheral Support Library Programmer’s Reference
(literature number SPRU273) describes the contents of the ’C6x
peripheral support library of functions and macros. It lists functions and
macros both by header file and alphabetically, provides a complete
description of each, and gives code examples to show how they are
used.
TMS320C6201 Digital Signal Processor Data Sheet (literature number
SPRS051) describes the features of the TMS320C6201 fixed-point DSP
and provides pinouts, electrical specifications, and timings for the
device.
TMS320C6701 Digital Signal Processor Data Sheet (literature number
SPRS067) describes the features of the TMS320C6701 floating-point
DSP and provides pinouts, electrical specifications, and timings for the
device.
TMS320C6201/6701 Evaluation Module Users Guide, (literature number
SPRU269C) can be accessed from the following URL:
http: //www.ti.com/sc/docs/dsps/tools/c6000/index.htm
Related Documentation
You can use the following specification to supplement this reference guide:
PCI Local Bus Specification Revision 2.1, PCI Special Interest Group,
June 1, 1995.
Trademarks
320 Hotline On-line, VelociTI, XDS510, XDS510PP, XDS510WS, and XDS511
are trademarks of Texas Instruments Incorporated.
ABEL and Synario are registered trademarks of the DATA I/O Corporation.
Altera, ByteBlaster, and MAX+ PLUS are trademarks of the Altera
Corporation.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
IBM and PC are trademarks of International Business Machines Corporation.
Read This First
vii
Running Title—Attribute Reference
Intel and Pentium are trademarks of Intel Corporation.
Microsoft, Windows, and Windows NT are registered trademarks of Microsoft
Corporation.
OpenWindows, Solaris, and SunOS are trademarks of Sun Microsystems, Inc.
SPARCstation is trademark of SPARC International, Inc., but licensed
exclusively to Sun Microsystems, Inc.
X Window System is a trademark of the Massachusetts Institute of
Technology.
viii
Obtaining Technical Support
Obtaining Technical Support
Before contacting Texas Instruments Technical Support, please have the
following information available:
Assembly number of your ’C6x EVM (D600830-0001) located on the
bottom side of the board
Revision number of your ’C6x EVM located in parentheses next to the
assembly number on the bottom side of the board
Serial number located on the bottom side of the board
Record of the ’C6x EVM confidence test utility results that identifies
potential problems and other revision numbers (software, EEPROM,
CPLD). Chapter 3, Running the Board Confidence Test, in
TMS320C6201/6701 EVM Users Guide explains how to run the test.
Computer’s PCI BIOS brand name and version number
Amount of memory in your computer system
Version of the software and operating environment you are using such as
Windows NT 4.0
Version of the code generation tools your are using
Version of the debugger you are using
If you are using Windows 95, print out a report of your system configuration
by performing the following steps:
1) Right click on the My Computer icon on the desktop.
2) Select the Properties menu item.
3) Select the Device Manager tag.
4) Select the Print button.
5) Select the System summary radio button.
6) Click on the OK button to print a system resource summary.
Have this system resource summary available when you contact technical
support.
Note:
Check the system resource summary to see if the IRQ assigned to
TI TMS320C6x EVM is shared with another device. If it is, this is probably the problem. See Appendix A, Troubleshooting, in
TMS320C6201/6701 EVM Users Guide for the corrective action.
Once you have this information ready, contact Texas Instruments Technical
Support as specified in the If You Need Assistance section that follows.
Read This First
ix
If You Need Assistance
If You Need Assistance . . .
-
World-Wide Web Sites
TI Online
Semiconductor Product Information Center (PIC)
DSP Solutions
320 Hotline On-linet
-
http://www.ti.com
http://www.ti.com/sc/docs/pic/home.htm
http://www.ti.com/dsps
http://www.ti.com/sc/docs/dsps/support.htm
North America, South America, Central America
Product Information Center (PIC)
(972) 644-5580
TI Literature Response Center U.S.A.
(800) 477-8924
Software Registration/Upgrades
(214) 638-0333
Fax: (214) 638-7742
U.S.A. Factory Repair/Hardware Upgrades
(281) 274-2285
U.S. Technical Training Organization
(972) 644-5580
DSP Hotline
(281) 274-2320
Fax: (281) 274-2324
DSP Modem BBS
(281) 274-2323
DSP Internet BBS via anonymous ftp to ftp://ftp.ti.com/pub/tms320bbs
-
Europe, Middle East, Africa
European Product Information Center (EPIC) Hotlines:
Multi-Language Support
+33 1 30 70 11 69
Email: epic@ti.com
Deutsch
+49 8161 80 33 11 or +33 1 30 70 11 68
English
+33 1 30 70 11 65
Francais
+33 1 30 70 11 64
Italiano
+33 1 30 70 11 67
EPIC Modem BBS
+33 1 30 70 11 99
European Factory Repair
+33 4 93 22 25 40
Europe Customer Training Helpline
-
Email: dsph@ti.com
Fax: +33 1 30 70 10 32
Fax: +49 81 61 80 40 10
Asia-Pacific
Literature Response Center
+852 2 956 7288
Fax: +852 2 956 2200
Hong Kong DSP Hotline
+852 2 956 7268
Fax: +852 2 956 1002
Korea DSP Hotline
+82 2 551 2804
Fax: +82 2 551 2828
Korea DSP Modem BBS
+82 2 551 2914
Singapore DSP Hotline
Fax: +65 390 7179
Taiwan DSP Hotline
+886 2 377 1450
Fax: +886 2 377 2718
Taiwan DSP Modem BBS
+886 2 376 2592
Taiwan DSP Internet BBS via anonymous ftp to ftp://dsp.ee.tit.edu.tw/pub/TI/
-
Japan
Product Information Center
+0120-81-0026 (in Japan)
+03-3457-0972 or (INTL) 813-3457-0972
DSP Hotline
+03-3769-8735 or (INTL) 813-3769-8735
DSP BBS via Nifty-Serve
Type “Go TIASP”
-
Fax: +0120-81-0036 (in Japan)
Fax: +03-3457-1259 or (INTL) 813-3457-1259
Fax: +03-3457-7071 or (INTL) 813-3457-7071
Documentation
When making suggestions or reporting errors in documentation, please include the following information that is on the title
page: the full title of the book, the publication date, and the literature number.
Mail: Texas Instruments Incorporated
Email: dsph@ti.com
Technical Documentation Services, MS 702
P.O. Box 1443
Houston, Texas 77251-1443
Note:
x
When calling a Literature Response Center to order documentation, please specify the literature number of the
book.
Contents
Contents
1
TMS320C6x EVM Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć1
Describes the TMS320C6x EVM hardware components and how they operate.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
TMS320C6x EVM Hardware Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć2
TMS320C6201/6701 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć4
DSP Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć7
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć8
1.4.1 SBSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć10
1.4.2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć11
1.4.3 Expansion Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć12
1.4.4 DSP Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć13
1.4.5 DSP EMIF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć16
Expansion Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć19
1.5.1 Expansion Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć19
1.5.2 Expansion Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć20
1.5.3 Daughterboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć22
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć24
1.6.1 PCI Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć25
1.6.2 PCI Controller Operation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć29
1.6.3 PCI Add-On Bus Operation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć30
1.6.4 PCI Slave Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć31
1.6.5 PCI Master Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć34
JTAG Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć39
Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć41
1.8.1 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć43
1.8.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć45
1.8.3 Dual DSP Clock Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć46
1.8.4 PCI Controller/JTAG TBC Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć48
1.8.5 PCI Controller/DSP Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć48
1.8.6 PCI Memory-Mapped Board Control/Status Registers . . . . . . . . . . . . . . . . . . . 1Ć50
1.8.7 DSP Memory-Mapped Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . 1Ć58
1.8.8 PCI and DSP Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć63
1.8.9 CE1 Memory Decoding/Data Transceivers Control . . . . . . . . . . . . . . . . . . . . . . 1Ć66
1.8.10 User Options Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć67
Stereo Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć70
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć75
xi
Contents
1.11
2
2.4
3.4
3.5
3.6
DSP Support Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć2
Using the DSP Support Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć3
McBSP Driver API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć4
3.3.1 McBSP Driver Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć4
3.3.2 McBSP Driver Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć5
3.3.3 McBSP Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć8
Codec Library API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć22
3.4.1 Codec Library Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć22
3.4.2 Codec Library API Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć26
Board Support Library API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć40
DSP Support Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć47
TMS320C6x EVM Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ1
Identifies the connector pins on the TMS320C6x EVM.
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
xii
Host Support Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć2
EVM Low-Level Windows Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć2
EVM Win32 DLL API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć3
2.3.1 EVM Win32 DLL API Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć3
2.3.2 EVM Win32 DLL API Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć5
EVM Host Support Software Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć46
TMS320C6x EVM DSP Support Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć1
Describes the EVM DSP support software components; provides an alphabetical summary of
the McBSP driver, codec library, and board support library API functions and examples of how
the EVM DSP support software can be used by user-generated DSP applications.
3.1
3.2
3.3
A
1Ć75
1Ć76
1Ć76
1Ć76
1Ć77
1Ć78
TMS320C6x EVM Host Support Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć1
Describes the EVM host support software components and low-level Windows drivers;
provides an alphabetical summary of the Win32 DLL API functions and examples of how the
EVM host support software can be used by user-generated Win32 applications.
2.1
2.2
2.3
3
1.10.1 3.3-V Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2 1.8-V/2.5-V Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.3 5-V Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.4 External Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.5 Fan Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C6x EVM Connector Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stereo Microphone Input Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stereo Line Input Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stereo Line Output Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPLD ISP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320C6x JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Memory Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expansion Peripheral Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AĆ2
AĆ2
AĆ3
AĆ3
AĆ4
AĆ5
AĆ6
AĆ7
Contents
A.9 External Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ8
A.10 DSP Fan Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ8
A.11 PCI Local Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ9
B
TMS320C6x EVM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B Ć1
Contains the schematics for the TMS320C6x EVM.
C
TMS320C6x EVM CPLD Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ1
Contains the CPLD equations for the TMS320C6x EVM
C.1
C.2
Overview of the EVM CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ2
EVM CPLD Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ8
D
TMS320C6x EVM PCI Configuration EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Ć1
Summarizes the contents of the EEPROM on the TMS320C6x EVM.
E
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E Ć1
Defines acronyms and key terms used in this book.
Contents
xiii
Figures
Figures
1–1
1–2
1–3
1–4
1–5
1–6
1–7
1–8
1–9
1–10
1–11
1–12
1–13
1–14
C–1
xiv
TMS320C6x EVM Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć3
TMS320C6201 Core, Peripherals, and External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć5
EMIF Data Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć9
EMIF Address Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć10
Daughterboard Envelopes and Connections on the TMS320C6x EVM . . . . . . . . . . . . . . 1Ć23
PCI Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć28
JTAG Emulation Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć40
CPLD Interfaces and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć42
Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć45
DSP Clock Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć47
Dual-Use Option Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć69
TMS320C6x EVM Stereo Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć70
McBSP0 Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć74
External Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć77
TMS320C6x EVM CPLD Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ3
Tables
Tables
1–1
1–2
1–3
1–4
1–5
1–6
1–7
1–8
1–9
1–10
1–11
1–12
1–13
1–14
1–15
1–16
1–17
1–18
1–19
1–20
1–21
1–22
1–23
1–24
1–25
1–26
1–27
1–28
1–29
1–30
1–31
1–32
1–33
1–34
1–35
3–1
Quad Clock Support Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć6
DSP Clock Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć7
TMS320C6x EVM DSP Memory Map (MAP 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć14
TMS320C6x EVM DSP Memory Map (MAP 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć15
TMS320C6x EVM CE Memory Space Initialization Summary . . . . . . . . . . . . . . . . . . . . . . 1Ć16
EMIF SDRAM Control Register Timing Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć17
EMIF SDRAM Timing Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć18
TMS320C6x EVM PCI BAR Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć26
S5933 PCI Bus Operation Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć29
PCI Add-on Bus Operation Registers Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć30
DSP HPI Registers (BAR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć32
Power Management Device Control Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć46
PCI Memory-Mapped CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć51
PCI CNTL Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć53
PCI STAT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć54
PCI SWOPT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć54
PCI SWBOOT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć55
PCI DIPOPT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć55
PCI DIPBOOT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć56
PCI DSPOPT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć56
PCI DSPBOOT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć57
PCI CPLDREV Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć57
DSP Memory-Mapped Control/Status CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć58
DSP CNTL Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć59
DSP STAT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć60
DSP DIPOPT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć60
DSP DIPBOOT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć61
DSP DSPOPT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć61
DSP DSPBOOT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć62
DSP FIFOSTAT Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć62
DSP SDCNTL Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć63
DSP Interrupts Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć65
User Options Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć67
CS4231A Audio Codec Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć71
Stereo Audio Interface Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Ć73
McBSP Driver API State Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć4
Contents
xv
Running Title—Attribute Reference
3–2
A–1
A–2
A–3
A–4
A–5
A–6
A–7
A–8
A–9
A–10
A–11
C–1
C–2
C–3
D–1
xvi
Codec Library API Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć22
TMS320C6x EVM Connectors Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ2
Stereo Microphone Input Connector J1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ2
Stereo Line Input Connector J2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ3
Stereo Line Output Connector J3 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ3
CPLD ISP J4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ4
TMS320C6x JTAG Emulation Header J5 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ5
Expansion Memory Interface J6 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ6
Expansion Peripheral Interface J7 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ7
External Power J8 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ8
DSP Fan Power J9 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ8
PCI Local Bus P1 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AĆ9
TMS320C6x EVM CPLD Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ2
TMS320C6x CPLD Pin Definitions (Numerical Pin Order) . . . . . . . . . . . . . . . . . . . . . . . . . . CĆ4
TMS320C6x CPLD Pin Definitions (Alphabetical Pin Order) . . . . . . . . . . . . . . . . . . . . . . . . . CĆ6
PCI Configuration EEPROM Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DĆ2
Examples
Examples
2–1
2–2
3–1
3–2
Win32 DLL API Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć3
EVM Win32 DLL Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Ć46
McBSP Driver API Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć5
McBSP, Audio Codec, and Board Support Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . 3Ć47
Contents
xvii
Chapter 1
TMS320C6x EVM Hardware
This chapter describes the TMS320C6x EVM hardware, its key components
and how they operate, and its various interfaces. Detailed programmer interface information such as memory maps, register definitions, interrupt usage,
and required software initialization tasks are also provided.
The hardware can be divided into 12 functional areas. Each of these areas is
discussed in detail in this chapter.
Topic
Page
1.1
TMS320C6x EVM Hardware Detailed Block Diagram . . . . . . . . . . . . . 1-2
1.2
TMS320C6201/6701 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3
DSP Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5
Expansion Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
1.6
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
1.7
JTAG Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39
1.8
Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41
1.9
Stereo Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70
1.10 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-75
1.11 Voltage Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-78
1-1
h1
1.1 TMS320C6x EVM Hardware Detailed Block Diagram
Figure 1–1 provides a detailed block diagram of the ’C6x EVM hardware. It
identifies the key components described in this chapter and shows how they
interface to each other.
1-2
Figure 1–1. TMS320C6x EVM Detailed Block Diagram
–12 V
Analog –12 V (to expansion peripheral interface)
12 V
Analog 12 V (to expansion peripheral interface)
TL750L05
5 V voltage
regulator
4-pin Molex
ext. power
connector
5V
(150 mA MAX)
Control
signals
from
CPLD
Analog 5 V
XCLKOUT2
To expansion interface
PLL
loop
filter
CY2308
zero-delay
clock buffer
Digital 5 V
5V
PT6405B
3.3 VDC
voltage
regulator
PCI bus
2-pin fan
power
connector
PT6502B
1.8/2.5 VDC
voltage
regulator
3.3 V (3A MAX)
LENDIAN,
BOOTMODE,
CLKMODE,
PLLFREQ
PLLx
SDCLK
OSC B
33.25 or 25
MHz
OSC A
’LVT125
5 V to 3.3 V
Xlat./clock edge
control & LED
buffers
MT58LC64K32
64K × 32
SBSRAM
(133 MHz)
CE2
TC59S1616
1M × 32
SDRAM
(100 MHz)
SDx
CLKIN (× 4)
CE3
TMS320C6201/6701 DSP
External
memory
interface
(EMIF)
TC59S1616
1M × 32
SDRAM
(100 MHz)
(133/160 MHz)
74F74 FF
(1/2)
16.625 MHz
JTAG
(2)
’CBT3257
2:1 MUX &
5 V to 3.3 V Xlat
SDRAM (SDA),
exp. mem. (XA),
codec &
CPLD (PBA)
(3)
’ALB16244
address
buffers
EAx
’ACT8990 JTAG
test bus controller
AT24C08A
1K × 8 serial
EEPROM
CE0
SBx
VDD2
40 or 33.35
MHz
JTAG header
(7 × 2 pins)
QS34X245
32-bit
switch
EDx
SBSRAM
SDRAM
CE0
AMCC
S5933
PCI
controller
(2) ’CBTD3384
5 V to 3.3 V Xlat.
User options
(boot mode, clock, PLL, JTAG)
12-pos DIP switch
MAX708S
voltage
supervisor
Board reset
PCI/manual reset
Manual reset
SBSRAM PD
(ZZ)
NC7SZ04
inverter
Ax
HPI
McBSP0
McBSP1
’ALB16244
control
buffer
Serial port
select from
CPLD
(2)
’CBT3257
2:1 MUX &
5 V to 3.3 V
Xlat.
Ctrl/
Status
16.9344/
24.576 MHz
XTALs
Clock control, PCI transfer control, user options control, memory decode, interrupt
control, PCI control/status registers, DSP/board reset & LED control
PCI
(AOD[7:0])
Exp. mem (XD), PCI (AOD[31:8]),
Codec & CPLD (PDB)
Expansion
memory
interface
Samtec SFM 0.050 × 0.050 in.
80-pin connector
Daughterboard
interface
Expansion
peripheral
i/f (serial,
timers, int)
CE1
Samtec SFM 0.050 × 0.050 in.
80-pin connector
Serial data/power down
CS4231A
16-bIt stereo audio codec
’CBTD3384
5 V to 3.3 V Xlat.
CE1
’CBTD3384
5 V to 3.3 V Xlat.
Registers
EPM7256S
programmable
logic (CPLD)
(4)
’LVTH
162245
data
buffers
TIM/INT
Target PCI
transfers
Master PCI transfers
3.3 V
Red
Clock select
JTAG select
CLKA DIV2
1.8/2.5 V
VDD3
LED1
Red
2.5/1.8 V (8A MAX)
User LEDs (2)
Addr/data/ctrl
To (4) SDRAMs
LED0
Green power LED
From/to CPLD
To CPLD
SDCLK
Digital 3.3 V
Power
sequence
control
Note: 3A Max. option
PLDCLK
TLC2272A
op amps
Passive filtering/mic supply
MIC IN (L/R)
LINE IN (L/R)
Passive filtering
Passive filtering
LINE OUT
(L/R)
3.5-mm
jacks
1-3
Stereo audio
interface
(on mounting
bracket)
TMS320C6201/6701 DSP
1.2 TMS320C6201/6701 DSP
The TMS320C6201/6701 DSP is the brain of the ’C6x EVM. The ’C6201/6701
DSP has the following key features:
- VelociTIt advanced very long instruction word (VLIW) architecture
J
Load/store architecture
J
Instruction packing for reduced code size
J
100% conditional instructions for faster execution
J
Intuitive, reduced instruction set computing with RISC-like instruction
set
- CPU
J
Eight independent functional units (including two 16-bit multipliers
with 32-bit results and six arithmetic logic units (ALUs) with 32/40 bit
results)
J
32 32-bit registers
J
5-ns cycle time
J
Up to eight 32-bit instructions per cycle
J
Byte-addressable with 8-, 16- and 32-bit data
J
32-bit address range
J
Little- and big-endian support
J
Saturation
J
Normalization
J
Bit-field instructions (extract, clear, left-most bit detection)
- Memory/peripherals
1-4
J
Glueless external memory interface to synchronous memories such
as SBSRAM and SDRAM
J
Glueless external memory interface to asynchronous memories such
as SRAM and EPROM
J
4-channel direct memory access (DMA)
J
Host port interface (HPI) with dedicated auxiliary DMA channel providing access to entire processor memory space
J
Two multichannel buffered serial ports (McBSPs) for direct interfacing
to telecommunication, audio, and other serial devices
TMS320C6201/6701 DSP
J
Two general-purpose timers
J
Multiply-by-4 phase locked loop (PLL) and multiply-by-1 PLL-bypass
options
J
1M-bit on-chip memory (2K × 256 bits of program memory/64K bytes
of data memory)
- Miscellaneous
J
IEEE-1149.1 (JTAG) boundary-scan compatible for emulation and
test support
J
352-lead ball grid array (BGA) package
J
0.25-micron/5-level metal process with CMOS technology
J
3.3-V I/O and 2.5-V or 1.8-V internal core voltages
Figure 1–2 shows the ’C6201 core, peripherals, and external interfaces.
Figure 1–2. TMS320C6201 Core, Peripherals, and External Interfaces
Data RAM
32-bit address
8-, 16-, 32-bit data
512K-bit RAM
23
D
32
JTAG test/
emulation
control
Program/data buses
Multichannel
buffered
serial port
DMA
’C62xx CPU core
Program fetch
Instruction dispatch
Instruction decode
Data path 1
A register file
Data path 2
B register file
Ch 0
Control
registers
Ch 2
Control
logic
Test
Emulation
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Ch 1
Interrupts
Ch 3
Auxiliary
channel
Peripheral bus
A
EMIF
Program RAM/cache
32-bit address
256-bit data
512K-bit RAM
Multichannel
buffered
serial port
Timer
16 Data
Timer
Host
port
Power management
PLL clock
generator
TMS320C6x EVM Hardware
1-5
TMS320C6201/6701 DSP
The C6x EVM may contain either a ’6201 (fixed-point) or ’6701 (floating-point)
DSP and may be operated at different frequencies. The following text describes the frequencies in terms of their relationship to a specific oscillator
(speed × 1/2, speed × 4, etc.). Table 1–1 shows the values for the oscillators
on the EVM.
Table 1–1. Quad Clock Support Frequencies
OSC A
OSC B
x1
x4
x1
x4
’C6201 EVM
33.25 MHz
133 MHz
40 MHzB
160 MHz
’C6701 EVM
25 MHz
100 MHz
33.25 MHz
133 MHz
Because the ’C6x EVM is a hardware reference design intended to provide you
with maximum flexibility, it supports all of the DSP’s external interfaces. The
’C6x EVM uses the PLL clock generator interface to support four clock rates:
OSC A 1, OSC B 1, OSC A 4, and OSC B 4. The JTAG test/emulation
interface supports both embedded and external emulation for source code debugging. The control interface resets the DSP, provides external interrupts,
chooses data endian mode, and selects the DSP’s boot method. The external
memory interface (EMIF) supports synchronous SBSRAM and SDRAM memories and asynchronous accesses to the CPLD registers, stereo audio codec, PCI controller, and expansion memory. The EMIF is also brought out to
an expansion memory interface connector for daughterboard use. The host
port interface (HPI) is used for bidirectional data transfers between the PC and
the DSP. The timer interfaces are provided on the expansion peripheral interface connector for daughterboard use. The multichannel buffered serial ports
provide interfaces to an onboard stereo audio codec and/or a daughterboard
connected to the expansion peripheral interface.
Some versions of the C6x EVM use an extremely low-profile, integrated heat
sink/fan cools the ’C6201/6701 DSP for maximum performance and reliability.
This 7.5-mm-high unit is designed for the ’C6201’s 35-mm × 35-mm BGA
package. It requires 5 VDC at 100 mA and reduces the temperature rise on the
device by 50–80% to handle the maximum dissipation of the DSP in a PCI environment that has little or no air flow. The ’C6x EVM provides a small 2-pin
power connector (J9) to supply the fan’s power.
1-6
DSP Clocks
1.3 DSP Clocks
The ’C6x EVM provides quad DSP clock support, which allows you to run
benchmarks using different clocks to determine optimal performance for a particular application.
The EVM uses two half-size oscillators, along with a TI SN74LVT125 quad bus
buffer device, to provide OSC A and OSC B CLKIN signals to the ’C6201/6701.
The use of the ’LVT125 device provides multiple functions, including 5-V to
3.3-V signal level translation, clock selection, and clock edge control with fast
rise and fall times required by the DSP.
The clock selection is made via a DIP switch during external operation or via
a software switch for internal PCI operation. Clock select control logic in the
complex programmable logic device (CPLD) controls the ’LVT125 buffer output enable that corresponds to the selected clock oscillator. The CPLD provides break-before-make clock switching between the two clock oscillators to
prevent any output contention.
The EVM provides user options for selecting the CLKIN frequency (OSC A or
OSC B) and the clock mode (multiply-by-1 or multiply-by-4 as shown in
Table 1–2). The SBSRAM clock (SSCLK) can be configured by the DSP software to be one-half the CPU clock (CLKOUT1) or the same as CLKOUT1. The
SDRAM clock (SDCLK) is always one-half of CLKOUT1. The CPLD also controls the DSP’s CLKMODE and PLLFREQ control inputs based on the clock
mode selection.
Table 1–2. DSP Clock Summary
Clock
Source
Clock Mode
SSCLK
(1/2 rate/1× rate)
SDCLK
OSC A
Multiply-by-1
16.625/OSC A MHz
1/2 OSC A
OSC B
Multiply-by-1
20/OSC B
1/2 OSC B
OSC A
Multiply-by-4
OSC A × 2/OSC A × 4
OSC A × 2
OSC B
Multiply-by-4
80 MHz†
OSC B × 2
† 1× SSCLK rate is invalid when CLKOUT1 is 160 MHz.
TMS320C6x EVM Hardware
1-7
External Memory
1.4 External Memory
The ’C6x EVM provides one bank of 64K × 32-bit words of 7.5-ns (133-MHz)
SBSRAM and two banks of 1M × 32-bit words of 10-ns (100-MHz) SDRAM.
An expansion memory connector is also provided to enable asynchronous
memory and memory-mapped devices to be added using a daughterboard.
The external SBSRAM and SDRAM devices on the board are 3.3-V devices.
The expansion memory connector is able to support both 3.3-V and 5-V devices because ’LVTH162245 5-V-tolerant buffers are used.
The EMIF address and data busses are buffered (except to the SBSRAM) to
preserve signal integrity, limit loading on the ’C6201/6701 outputs, and provide
the necessary drive to meeting timing requirements. A 32-bit bus switch device
is used to isolate the rest of the data bus during SBSRAM accesses. This isolation preserves signal integrity and allows the EVM to run the SBSRAM at the
full 133-MHz bus speed. Very fast line drivers are used to buffer the address
and control signals, which limits the loading on the DSP’s outputs. Fast data
transceivers are used to provide voltage translation and the necessary drive
to a daughterboard. Figure 1–3 and Figure 1–4 show the configuration of the
EMIF data and address bus buffering, respectively.
1-8
External Memory
Figure 1–3. EMIF Data Bus Topology
’C6201/6701
DSP
ED[31:0]
64K × 32,
133-MHz
SBSRAM
(CE0)
32-bit
bus switch
1M × 32,
100-MHz
SDRAM
D[31:0]
BANK
1
(CE3)
1M × 32,
100-MHz
SDRAM
BANK
0
(CE2)
(CE1)
XD[31:0]
’LVTH162245
AOD[31:8]
’LVTH162245
’CBTD3384
AOD[7:0]
PBD[7:0]
’LVTH162245
Legend: ED
XD
AOD
PBD
Note:
DSP EMIF data
Expansion memory data
PCI add-on data
Peripheral bus data
The transceiver signal assignments provide a functional overview only. The actual signal assignments are optimized for
layout.
TMS320C6x EVM Hardware
1-9
External Memory
Figure 1–4. EMIF Address Bus Topology
’C6201/6701
DSP
[18:2]
EA[21:2]
SBSRAM
(CE0)
[13,11:2]
(CE1)
’ALB16244
[21:2]
SDEA[13,11:2]
SDRAM
bank
0
high
SDRAM
bank
0
low
SDRAM
bank
1
high
SDRAM
bank
1
low
(CE2)
(CE2)
(CE3)
(CE3)
XEA[21:2]
’ALB16244
[21:16,6:2]
PBA[21:16,6:2]
’ALB16244
Legend: EA
DSP EMIF address
SDEA
SDRAM access
XEA
Expansion memory address
PBA
Peripheral bus address
Note:
The transceiver signal assignments provide a functional overview only. The actual signal assignments are optimized for
layout.
1.4.1
SBSRAM
The EVM provides 64K × 32-bit words of SBSRAM. The SBSRAM used on the
EVM is directly connected to the DSP with no glue logic or buffers required,
because the ’C6201 EMIF provides a direct interface to industry-standard
SBSRAM devices. The bank of SBSRAM is mapped into the DSP’s CE0
memory space, allowing it to be used for program booting, assuming that it has
been initialized by host software or the emulator. It has a 7.5-ns cycle time (133
MHz) and provides 64K × 32-bit words of memory in a single 100-pin thin
quad flat pack (TQFP) package. The pinout of this package is the same for the
128K × 32-bit word device, but it uses one extra address line. The EVM layout
supports the use of 128K × 32-bit devices.
The SBSRAM device can be clocked by the ’C6201/6701 at the CPU clock
speed when operating at 133 MHz, one-half the clock speed when operating
at 160 MHz, or at either the same as or one-half the clock speed when operating in the multiply-by-1 clock mode (OSC A and OSC B). This selection is made
1-10
External Memory
based on the setting of the SSCRT bit in the EMIF global control register. Additionally, various boot modes inherently select the clock speed used for the
SBSRAM interface. You must correctly select the SBSRAM clock rate for the
selected CPU clock rate.
The ’C6201 EMIF provides signals that directly correspond to the SBSRAM
pins. Because the ’C6201 can generate a new address every cycle, the
SBSRAM’s ADV control input, which allows the device to generate its own addresses internally, does not have to be used. This SBSRAM control input is
pulled high on the EVM.
The SBSRAM device supports a snooze power-down mode when its ZZ input
signal is a logic high. The ZZ input is controlled directly by the voltage supervisor’s logic high reset output; so, when the board is held in reset, the SBSRAM
is disabled and placed into a power-down mode. With this power management
feature, the maximum current is reduced from 110 mA to 0.5 mA. Data in the
SBSRAM is retained during the snooze mode.
1.4.2
SDRAM
The EVM provides two banks of 1M × 32-bit words of SDRAM. Each bank is
comprised of two 512K × 2 banks × 16-bit devices. The 3.3-V SDRAM used
on the ’C6x EVM requires no glue logic to interface to the DSP because the
’C6201 EMIF generates all the required SDRAM control and refresh signal sequences. The two banks of SDRAM are mapped into the DSP’s CE2 and CE3
memory spaces. Each bank uses 4M bytes of the 16M-byte address space.
One of the banks of SDRAM (CE3) resides on the back side of the board to
optimize signal routing and signal integrity.
The SDRAM devices are always clocked at one-half the CPU clock rate. This
means that when the DSP core runs at OSC A × 4, the SDRAM runs at 66.5
MHz (15 ns), and when the DSP core runs at OSC B × 4, the SDRAM runs at
80 MHz (12.5 ns). The EVM’s SDRAM devices are rated for 100-MHz operation.
The four SDRAM devices have dedicated point-to-point clocks that are driven
by a clock driver device. The clock driver provides near zero-delay PLL buffering of the DSP’s SDCLK. Two clock driver outputs are routed to the expansion
peripheral interface connector and the CPLD. Address and control signals are
buffered with TI ’ALB16244 buffers to manage the loading of these ’C6201 signals properly.
The SDRAM must be refreshed periodically to maintain its data. The ’C6x EVM
uses the DSP’s SDRAM refresh capability so the RFEN bit in the DSP’s
SDRAM control register must be set to 1. The refresh period can be a maximum of 15.625 µs.
TMS320C6x EVM Hardware
1-11
External Memory
The EVM’s CPLD includes SDRAM enable bits that are controlled via the DSP
memory-mapped SDCNTL register. After reset is released, these SDRAM enables, which are connected to the SDRAM clock enable (CKE) pins, default
to active, enabling the SDRAMs. When the board is held in reset or DSP software explicitly clears the register control bits, the SDRAMs are disabled and
placed into a power-down mode. With this power management feature, the
maximum per-device current is reduced from 120 mA to 3 mA.
An additional use of the CPLD SDRAM enable bits is the ability to independently disable the CE2 and CE3 SDRAM banks to allow these memory spaces
to be used for asynchronous expansion memory on a daughterboard. When
an SDRAM bank is disabled, the respective memory space can be used for
asynchronous expansion memory.
1.4.3
Expansion Memory
The EVM provides an asynchronous expansion memory interface connector
(J6) to allow you to add memory or memory-mapped devices via a daughterboard. The expansion memory interface is mapped into the lower 3M bytes of
the DSP’s 4M-byte asynchronous CE1 memory space. Expansion memory in
the CE1 space is addressed from 0x1000000–12FFFFF in MAP 0 and
0x1400000–16FFFFF in MAP 1 mode. The upper 1M bytes of the CE1
memory space is allocated for onboard peripherals. This division of the CE1
memory space allows both the onboard devices and the expansion memory
interface to coexist without conflicts.
Because the EVM’s stereo audio codec, PCI controller, and CPLD registers
are also accessed in the DSP’s asynchronous CE1 memory space, the CPLD
provides transceiver control logic that prevents the expansion memory space
from conflicting with the onboard use of the CE1 space. The CPLD monitors
the CE1 signal along with the upper address signals (EA[21:20]) to determine
when the lower 3M-byte expansion memory space is being accessed and enables the expansion memory transceivers accordingly. CE1 decoding in the
upper 1M byte is handled by the CPLD for control of onboard peripherals.
The EMIF CE2 and CE3 memory space enables are available on the expansion peripheral interface connector (J7). These two memory spaces can also
be used for asynchronous memory on the daughterboard when their respective SDRAM enable bits are not asserted in the CPLD register. The SDRAM
enable bits control the SDRAM clock enables, as well as enabling the expansion memory transceivers to be turned on during CE2 and CE3 memory space
accesses. This capability supports applications that do not require one or both
banks of SDRAM, but need to interface to faster or additional asynchronous
memory on a daughterboard.
1-12
External Memory
All expansion memory interface signals are buffered using TI ’LVTH buffers/
transceivers to allow both 3.3- and 5-V devices to be used on the daughterboard and to isolate the daughterboard from the onboard EMIF. The three
memory space enables (CE1–CE3) are buffered versions of the DSP outputs
and are not generated by decode logic. This allows fast daughterboard logic
to be used as required for the application without incurring additional delay.
The expansion memory transceivers isolate the daughterboard and onboard
data busses to prevent bus contention.
One potential use of the expansion memory interface is to provide nonvolatile
memory such as ROM or Flash memory on a daughterboard that can be used
for ROM boot operation. This allows the EVM to be autobooted at power up
and reset with an application stored in nonvolatile memory. The EVM can operate in this mode inside the PC or, more typically, in an external operating environment.
1.4.4
DSP Memory Maps
Table 1–3 and Table 1–4 show the ’C6x EVM DSP memory maps for MAP 0
and MAP 1 modes, respectively.
TMS320C6x EVM Hardware
1-13
External Memory
Table 1–3. TMS320C6x EVM DSP Memory Map (MAP 0)
Start Address
End Address
External
Memory
Space
00000000
0003FFFF
CE0
256K
00040000
00FFFFFF
CE0
16M – 256K
01000000
012FFFFF
CE1
3M
Asynchronous expansion memory
01300000
0130003F
CE1
64
PCI add-on registers
01300040
0130FFFF
CE1
64K – 64
01310000
01310003
CE1
4
01310004
0131FFFF
CE1
64K – 4
01320000
0132000F
CE1
16
01320010
0132FFFF
CE1
64K – 16
01330000
0137FFFF
CE1
320K
01380000
0138001F
CE1
32
01380020
0138FFFF
CE1
64K – 32
01390000
0x13FFFF
CE1
448K
Reserved
01400000
0140FFFF
N/A
64K
Internal program memory (IPM)
01410000
017FFFFF
N/A
4M – 64K
01800000
01BFFFFF
N/A
4M
Internal peripherals
01C00000
01FFFFFF
N/A
4M
Reserved
02000000
023FFFFF
CE2
4M
SDRAM (bank 0) or optional asynchronous expansion memory
02400000
02FFFFFF
CE2
12M
Reserved
03000000
033FFFFF
CE3
4M
SDRAM (bank 1) or optional asynchronous expansion memory
03400000
03FFFFFF
CE3
12M
Reserved
04000000
7FFFFFFF
N/A
1984M
Reserved
80000000
8000FFFF
N/A
64K
80010000
803FFFFF
N/A
4M–64K
80400000
FFFFFFFF
N/A
2044M
1-14
Size
(Bytes)
Description
SBSRAM
Unused
Unavailable
PCI FIFO
Unavailable
Audio codec registers
Unavailable
Reserved
DSP control/status registers
Unavailable
Reserved (future IPM)
Internal data memory (IDM)
Reserved (future IDM)
Reserved
External Memory
Table 1–4. TMS320C6x EVM DSP Memory Map (MAP 1)
Start Address
End Address
External
Memory
Space
00000000
0000FFFF
N/A
64K
00010000
003FFFFF
N/A
4M–64K
00400000
0043FFFF
CE0
256K
00440000
013FFFFF
CE0
16M – 256K
01400000
016FFFFF
CE1
3M
Asynchronous expansion memory
01700000
0170003F
CE1
64
PCI add-on registers
01700040
0170FFFF
CE1
64K – 64
01710000
01710003
CE1
4
01710004
0171FFFF
CE1
64K – 4
01720000
0172000F
CE1
16
01720010
0172FFFF
CE1
64K – 16
01730000
0177FFFF
CE1
320K
01780000
0178001F
CE1
32
01780020
0178FFFF
CE1
64K – 32
01790000
017FFFFF
CE1
448K
01800000
01BFFFFF
N/A
4M
Internal peripherals
01C00000
01FFFFFF
N/A
4M
Reserved
02000000
023FFFFF
CE2
4M
SDRAM (bank 0) or optional asynchronous expansion memory
02400000
02FFFFFF
CE2
12M
Reserved
03000000
033FFFFF
CE3
4M
SDRAM (bank 1) or optional asynchronous expansion memory
03400000
03FFFFFF
CE3
12M
Reserved
04000000
7FFFFFFF
N/A
1984M
Reserved
80000000
8000FFFF
N/A
64K
80010000
803FFFFF
N/A
4M–64K
80400000
FFFFFFFF
N/A
2044M
Size
(Bytes)
Description
Internal program memory (IPM)
Reserved (future IPM)
SBSRAM
Unused
Unavailable
PCI FIFO
Unavailable
Audio codec registers
Unavailable
Reserved
DSP control/status registers
Unavailable
Reserved
Internal data memory (IDM)
Reserved (future IDM)
Reserved
TMS320C6x EVM Hardware
1-15
External Memory
1.4.5
DSP EMIF Registers
The DSP EMIF registers must be initialized before the external memory on the
’C6x EVM can be accessed by DSP or host software. The DSP EMIF registers
must be initialized by the DSP software before it accesses external memory
in the no-boot and ROM-boot modes. When HPI-boot mode is selected, the
host software must initialize the EMIF registers via the HPI before HPI memory
accesses are performed on external memory. This section identifies the required and recommended EMIF register values for proper EVM operation.
The EMIF global control register must be initialized to enable the various DSP
output clocks and select clock polarities, the SBSRAM clock rate (one-half the
CPU clock or the same as the CPU clock), and the requester arbitration mode.
The ’C6x EVM does not use the CLKOUT1 and CLKOUT2 outputs, so these
clocks should be disabled to minimize EMI emissions. The SDCLK output
(which is used to clock the EVM’s four SDRAM devices, the CPLD, and the
daughterboard circuitry) should have its polarity identical to the DSP’s internal
SDCLK. The SBSRAM clock rate (SSCLK) can be either one-half the CPU
clock or the same as the CPU clock when the CPU clock rate is 133 MHz or
less. When the CPU clock rate is greater than133 MHz , only one-half the CPU
clock rate is valid for SSCLK. The requester arbitration mode selection is application dependent. For a one-half-rate SSCLK operation, a value of 0x3060
is recommended. For a full-rate SSCLK operation, a value of 0x3064 is recommended.
The EMIF CE space control registers for the CE0–CE3 must be initialized to
select the external memory configuration of the ’C6x EVM. The CE1 memory
space control register must be configured for a strobe period of 3 CLKOUT1
cycles for proper operation. Table 1–5 summarizes the CE space allocation of
the ’C6x EVM.
Table 1–5. TMS320C6x EVM CE Memory Space Initialization Summary
CE
Memory
Space
1-16
Control
Register
Address
Memory Type
Memory Characteristics
Control Register Value
CE0
SBSRAM
133 MHz maximum
0x1800008
0x40
CE1
PCI controller,
CPLD registers,
audio codec, and
expansion memory
32-bit async, strobe = 3
0x1800004
OSC B×4:
OSC A×4:
OSC B:
OSC A :
CE2
SDRAM (bank 0)
100 MHz maximum
0x1800010
0x30
CE3
SDRAM (bank1)
100 MHz maximum
0x1800014
0x30
0x40F40323
0x40F40323
0x10D10321
0x10D10321
External Memory
Because the ’C6x EVM includes SDRAM, the EMIF SDRAM control and timing
registers must be initialized to select timing and device width, enable refresh,
initialize the SDRAM devices, and control the SDRAM refresh period. The
SDRAM timing selection is dependent on the CPU clock speed, so the host or
DSP software must determine its clock speed to properly initialize the timing
control bits. The host and DSP can each read CPLD registers to determine the
CPU clock speed based on the clock selection (OSC A or OSC B) and clock
mode (multiply-by-1 or multiply-by-4). The SDRAM devices have a tRC (refresh/active-to-refresh/active) period of 100 ns, a tRP (precharge-to-active)
period of 30 ns, and a tRCD (active-to-read/write) period of 30 ns. Based on the
determined CPU clock period, the TRC, TRP, and TRCD fields of the EMIF
SDRAM control register can be initialized based on the CLKOUT2 period, as
summarized in Table 1–6.
Table 1–6. EMIF SDRAM Control Register Timing Fields
CPU Clock
(MHz)
CLKOUT2
Period (ns)
TRC Field
TRP Field
TRCD
Field
25
??
??
??
??
33
60
1
0
0
40
50
1
0
0
100
??
??
??
??
133
15
6
1
1
160
12.5
7
2
2
The SDRAM control register’s INIT bit must be set to 1 to initialize the SDRAM
in each CE space configured for SDRAM (CE2/CE3). The RFEN bit must be
set to 1 to enable EMIF SDRAM refreshes. The SDWID bit must also be set
to 1 to select two, 16-bit SDRAM devices per SDRAM CE space.
The SDRAM timing register, which selects the SDRAM refresh period, must
be initialized for a maximum period of 15.625 µs. The refresh period is based
on CLKOUT2 cycles, so the SDRAM timing register period must have maximum values as summarized in Table 1–7.
TMS320C6x EVM Hardware
1-17
External Memory
Table 1–7. EMIF SDRAM Timing Register Values
CPU Clock
(MHz)
CLKOUT2
Period (ns)
Maximum
Register
Value
OSC A
60
0x103
40
50
0x138
133
15
0x410
160
12.5
0x4E1
See the TMS320C6201/C6701 Peripherals Reference Guide for detailed information about the DSP’s EMIF registers.
1-18
Expansion Interfaces
1.5 Expansion Interfaces
The ’C6x EVM provides two expansion connectors that allow a daughterboard
to be connected to the board. Daughterboards can be used to extend the capabilities of the EVM and to provide custom and application-specific I/O. One expansion connector provides the DSP’s asynchronous EMIF, and the other provides access to the DSP’s peripherals and control/status signals. Both connectors also provide power to the daughterboard.
Most of the expansion connector signals are buffered so that the daughterboard cannot directly influence the operation of the EVM board. The use of TI
’LVTH and ’CBT family interface devices allows the use of either 5- or 3.3-V
devices to be used on the daughterboard.
The ’C6x EVM’s expansion memory and peripheral interfaces are provided
with two dual-row, 80-pin connectors. These surface-mount connectors are
low profile and have a 0.050-inch (1.27-mm) pitch. The recommended mating
connectors provide 0.465-inch board spacing, allowing ample space for
daughterboard components.
The expansion memory interface connector has a reference designator of J6
on the EVM. The expansion peripheral interface connector is J7. See Chapter
3, for the pinouts of the expansion connectors.
1.5.1
Expansion Memory Interface
The expansion memory interface provides the DSP’s asynchronous EMIF signals to a daughterboard. External asynchronous memories and memorymapped devices can be added to the EVM, including nonvolatile memory that
can be used to boot the EVM upon reset.
The expansion memory interface includes:
20 external address signals (EA[21:2]). All of the DSP’s 20 external address signals are available on the expansion memory interface, allowing
up to 4M bytes of external memory to be addressed. However, because
the CE1 memory space must be shared with onboard peripherals, only the
lower 3M bytes are available to a daughterboard. If CE2 or CE3 is used
for external asynchronous memory instead of SDRAM, an additional
4M bytes in each memory space can be addressed.
32 external data signals (ED[31:0]). All of the DSP’s 32 external data signals are available on the expansion memory interface to support full 32-bit
word accesses to the daughterboard.
CE1 memory space enable. The DSP’s CE1 memory space enable is
available on the expansion memory interface to allow asynchronous accesses to daughterboard memory and memory-mapped devices.
TMS320C6x EVM Hardware
1-19
Expansion Interfaces
Four byte enables (BE[3:0]). The DSP’s four byte enables are available
on the expansion memory interface to support byte (8-bit), halfword
(16-bit), and word (32-bit) daughterboard memory accesses.
Four asynchronous control signals. The DSP’s asynchronous control
signals (ARE, AWE, AOE, and ARDY) are provided to control asynchronous memory accesses to a daughterboard.
Power signals. The expansion memory interface also provides ground,
5-V, and 3.3-V power signals to the daughterboard.
1.5.2
Expansion Peripheral Interface
The expansion peripheral interface provides the DSP’s peripheral signals to
a daughterboard. This peripheral expansion capability allows serial devices
such as other codecs and communication devices to be added to the EVM via
a daughterboard.
The expansion peripheral interface includes:
Seven signals for each of the serial ports (McBSP0 and McBSP1).
The DSP’s seven McBSP1 signals are available on the expansion peripheral interface. These signals are buffered by a ’CBTD3384 device to support both 5- and 3.3-V serial devices using McBSP1 on a daughterboard.
The DSP’s seven McBSP0 signals are also available when the DSP software controls onboard ’CBT3257 multiplexers that connect them to the expansion connector rather than the audio codec. This architecture provides
a daughterboard with access to both of the DSP’s serial ports, which is
useful in many DSP applications. Because a ’CBT3257 multiplexer is
used, both 5- and 3.3-V serial devices can use McBSP0 on a daughterboard.
Two input/output signals for each of the timers (timer 0 and timer 1).
The expansion peripheral interface includes each of the DSP timers’ input
and output signals. This allows timer signals to be sent to the daughterboard, or timer input or events to be counted to come from the daughterboard. Each timer has one input and one output signal.
Interrupt, interrupt acknowledge, and identification signals. A DSP
external interrupt (XEXT_INT7) is included on the expansion peripheral interface to allow the daughterboard to interrupt the ’C6201/6701 to notify
it of data transfers and other significant events. This interrupt is pulled
down on the EVM, so the daughterboard must drive it high to interrupt the
DSP. Additionally, the DSP’s interrupt acknowledge (IACK) and interrupt
identification number signals (INUM[3:0])are available to the daughterboard.
1-20
Expansion Interfaces
Four DMA completion flags. The DMA action complete flags
(DMAC[3:0] are available to the daughterboard on the expansion peripheral interface. These pins provide a method of feedback to external logic
generating an event for each DMA channel. The DMAC pins can also be
used for general-purpose output control signals controlled from the DSP’s
DMA channel secondary control register.
Four general-purpose input/output flags. Two general-purpose control
inputs and two status outputs are brought to the expansion peripheral interface to allow the DSP to control and monitor various signals on a daughterboard. The XCNTL[0:1] and XSTAT[0:1] signals can be controlled with
DSP software by accessing the CPLD’s DSP memory-mapped CNTL and
STAT registers, respectively.
Power-down signal. The DSP’s power-down indication signal (DSP_PD)
is also brought to the expansion peripheral interface so that a daughterboard can be powered down, if desired.
Reset signal. The expansion peripheral interface also provides a reset
signal that is active low when the board is in the reset state. This allows
circuitry on the daughterboard to be set in a known state. The reset signal
is asserted for a minimum of 140 ms upon power up, via a manual reset
pushbutton or under software control. A memory-mapped register bit in
the CPLD’s CNTL register allows DSP software to directly control this reset signal.
CLKOUT2 signal for the synchronization clock. The DSP’s CLKOUT2
signal (CPU clock divide by 2) is brought out to the peripheral expansion
interface for synchronization needs on daughterboards.
Buffered CE2 and CE3 signals for possible memory space use when
the respective SDRAMs are disabled. The DSP’s CE2 and CE3
memory space decodes are buffered and brought out to the expansion peripheral interface to provide additional fast memory decodes. This can be
useful on daughterboards that have multiple devices that need fast
memory decodes. The CE2 and CE3 are dedicated to SDRAM use on the
EVM board, but the EMIF control registers can be initialized for asynchronous operation, which disables the respective SDRAM banks and allows
expansion asynchronous memory to be used instead. The CE2 and CE3
SDRAM enable bits in the CPLD’s DSP memory-mapped registers must
also be used to shut down the respective SDRAM bank and allow the
CPLD logic to enable the external data transceivers for the CE2/CE3 accesses.
Power signals. The expansion peripheral interface also provides ground,
12-V, –12-V, 5-V, and 3.3-V power signals to the daughterboard.
TMS320C6x EVM Hardware
1-21
Expansion Interfaces
1.5.3
Daughterboard
The ’C6x EVM supports the mating of a daughterboard that has two 80-pin
0.050-inch × 0.050-inch TFM-series connectors from Samtec. The recommended mating connector (part number TFM–140–32–S–D–LC) is a surfacemount connector that provides a 0.465-inch mated height.
The EVM supports two sizes of daughterboards that both use the two 80-pin
connectors. The small daughterboard measures approximately 3.15 inches ×
3.4 inches and mounts in the center of the board over the low-profile buffers
and memories. This format is intended for daughterboards that do not require
an I/O connection on the mounting bracket.
The large daughterboard measures approximately 7.5 inches × 3.4 inches
and mounts from the center of the board over to the mating connector end of
the board. This format is intended for daughterboards that require an I/O connection on the mounting bracket or need more space than the small daughterboard provides.
A daughterboard mounts with its component side down. This ensures that the
PCI height requirement is met and no components are exposed to possible
damage due to board insertions and extractions.
The EVM provides four standoff mounting holes to support daughterboard
connections. Mounting holes MT1 and MT2 support small daughterboards,
and all four mounting holes support large daughterboards. The MT1, MT2, and
MT3 mounting holes are electrically connected to the digital ground plane to
provide additional daughterboard grounding. MT4 is not electrically connected
on the EVM.
Figure 1–5 shows the small and large daughterboard envelopes, the relationship between the two expansion connectors, and the relative location of the
four mounting holes on the component side of the ’C6x EVM board.
1-22
Expansion Interfaces
Figure 1–5. Daughterboard Envelopes and Connections on the TMS320C6x EVM
22.00
(0.866)
94.00
(3.70)
5.00
(0.197)
∅6.35
(0.250)
8.00
(0.315)
MT3
29.0
(1.14)
∅3.175
(0.125)
15.24
(0.60)
15.24
(0.60)
5.00
(0.197)
5.00
(0.197)
1
4 places
MT1 2
79
J6
(Expansion memory connector)
80
Optional
I/O
connector
area
76.20
(3.00)
86.20
(3.39)
(Expansion peripheral connector)
5.00
(0.197)
J7
MT4
1
79
2
5.00
MT2 (0.197)
80
80.00
(3.15)
5.00
(0.197)
191.00
(7.52)
Notes:
1) All dimensions are shown in millimeters. Inch dimensions are shown in parentheses.
2) Drawing shows daughterboard envelopes and connections on the component side of EVM board.
3) Standard-size daughterboard is 80.0 mm × 86.2 mm (3.15 in. × 3.39 in.).
4) Full-size daughterboard is 191.0 mm × 86.2 mm (7.52 in. × 3.39 in.).
5) Daughterboard connectors are Samtec .050-in. × .050-in. Micro Strips (SFM–140–L2–S–D–LC).
6) Daughterboard mating connectors are Samtec TFM–140–32–S–D–LC.
7) Mating height is 0.465 in. (11.81 mm).
8) There are four plated holes (MT1–MT4) on the EVM for standoff mounting.
9) Mounting holes MT1–MT3 are electrically connected to digital ground.
10) Mounting hole MT4 is floated with no electrical connection.
TMS320C6x EVM Hardware
1-23
PCI Interface
1.6 PCI Interface
The ’C6x EVM’s peripheral component interconnect (PCI) interface provides
plug-and-play functionality along with the ability to support high-speed target
(slave) and initiator (master) modes of data transfers.
The plug-and-play feature of PCI is intended to eliminate the resource conflicts
associated with ISA cards that result from user configuration of addresses and
interrupts. PCI devices each provide a configuration register space within the
system that can be accessed by the host prior to it being mapped into the system memory or I/O space. Access to the configuration registers is the key to
PCI’s plug-and-play functionality. The PC’s BIOS executes configuration
cycles after reset to identify devices on the PCI bus and to determine each of
their system resource requirements, such as I/O and memory space and interrupts. PCI devices are automatically configured by the PC BIOS, to prevent
system resource conflicts. The EVM’s Windows drivers obtain information
from the EVM’s PCI controller’s configuration registers to determine where the
board is located and what interrupt it uses. This allows you to simply plug the
board into a PCI slot without setting any jumpers or switches.
The PCI bus operates synchronously at up to 33 MHz with a multiplexed 32-bit
address/data bus. The power of PCI is its support for multiple devices to master the bus and communicate in bursts at up to 132M bytes/second
(33 MHz × 4 bytes/word). A burst consists of a single 32-bit address phase,
followed by sequential 32-bit data words. Only one device can be mastering
the bus at any one time, but for the period that it does, it can burst data at that
rate if its hardware can keep up. If it is not fast enough, a ready signal is used
to throttle the transfer at the rate at which it can read or write data. Because
there are typically multiple devices on the PCI bus, such as the video controller,
they must all timeshare the bandwidth, so the effective transfer rate for each
device is typically much lower than 132M bytes/second. The key to maximizing transfer throughput on the PCI bus is to use burst transfers when possible
to avoid repetitive PCI bus arbitration and the overhead associated with singleword transfers. The PCI bridge provides a hidden central arbitration mechanism where multiple bus masters can request and be granted the bus. It also
controls the length of the bursts that each device can generate. PCI transfer
rates are very machine-dependent because burst transfer support varies
among the various bridges used in different PCs.
1-24
PCI Interface
1.6.1
PCI Interface Implementation
The ’C6x EVM implements a fully-compliant PCI Revision 2.1 interface using
an industry-standard application-specific integrated circuit (ASIC) (AMCC
part number S5933). The S5933 PCI controller interfaces directly to the PCI
bus connector (P1) and handles all of the PCI-side transactions, freeing the
EVM hardware from having to handle them directly. The ’C6x EVM’s 32-bit PCI
interface operates at up to 33 MHz in a 5-V signaling environment. The EVM
cannot be used in a 3.3-V PCI slot.
The S5933 provides PCI configuration registers that are always accessible to
host software—even before the board has been mapped into the system resources. Accesses to these configuration registers are made by host software
by specifying the device’s bus number, device number, and function number.
The PCI configuration registers are in a unique address space, so they are not
directly mapped into either the host’s I/O or memory spaces. Nonvolatile, serial
EEPROM memory on the ’C6x EVM is used to store PCI configuration information for the board including its vendor and device IDs, memory space requirements, and operational parameters. The EVM’s vendor ID is 0x104C (Texas
Instruments), and its device ID is 0x1002.
The S5933 provides a glueless interface to the serial EEPROM that can be accessed from both the host and DSP software via memory-mapped register access. The contents of the EEPROM are automatically loaded into S5933 configuration registers at power-up reset to identify the system resource requirements and operating characteristics of the EVM. This information is used by
the PC BIOS for system resource allocation.
The EVM uses an AT24C08A 1Kx8 serial EEPROM. The S5933 only requires
64 bytes for configuration information. Another 64 bytes is reserved for future
use, so there are 896 free bytes, located from offsets 0x80 to 0x3FF, that can
be used to store miscellaneous information, if desired.
The S5933 provides five base address registers (BARs). Each BAR is initialized upon power up by the nonvolatile memory to the desired size of a
memory-mapped region for the device. The BIOS overwrites the BAR values
with the address that it allocates to each region. The ’C6x EVM takes advantage of all five BARs. The first BAR (BAR0) is reserved for the PCI controller’s
operation registers. The other four BARs (BAR1–BAR4) are used to interface
to the JTAG test bus controller (TBC), EVM control and status registers, and
the ’C6201 HPI. Table 1–8 summarizes the ’C6x EVM PCI BAR definitions.
TMS320C6x EVM Hardware
1-25
PCI Interface
Table 1–8. TMS320C6x EVM PCI BAR Definitions
BAR
Number
Size
(Bytes/DWORDs)
Bus Width/Bits Used
0
64/16
32/32
S5933 PCI operation registers
1
128/32
32/16
JTAG TBC registers
2
128/32
32/8
EVM board control/status registers
3
16/4
16/32
HPI control, address, and data registers
4
256K/64K
16/32
HPI data register (with autoincrement)
Description
The S5933 provides three physical interfaces:
PCI bus
Add-on bus
A nonvolatile memory interface
Data movement can occur between the PCI bus and the add-on bus, as well
as between the add-on or PCI bus and the nonvolatile memory. Data transfers
between the PCI and add-on buses can take place through mailbox registers,
FIFOs, or the pass-through data path, which is a generic memory-mapped interface.
Mailbox registers are used to pass single 32-bit values between the host and
DSP. Interrupts can be used to indicate when the mailbox registers are full and
empty. The S5933 has eight mailboxes that are useful for passing command
and status information between the host and the DSP. There are four incoming
(host-to-DSP) and four outgoing (DSP-to-host) mailboxes. The host incoming
and the DSP outgoing mailboxes are the same internally. The DSP incoming
and the host outgoing mailboxes are the same internally. The mailbox status
can be monitored from both sides in two ways. A mailbox status register available to both sides indicates the empty/full status of bytes within the mailboxes.
The mailboxes may also be configured to generate interrupts to the host and
DSP. One outgoing and one incoming mailbox on each side can be configured
to generate interrupts.
FIFO transfers between the PCI and add-on buses can be performed under
software control or directly by hardware using the device as a bus master. This
means that the DSP software can access the S5933 FIFOs directly to read and
write data from and to the PCI bus, or it can program its DMA controller to handle the transfers automatically in the background.
The pass-through data path is used when the EVM is a PCI target for JTAG
TBC and DSP HPI transactions.
1-26
PCI Interface
The S5933 registers and FIFOs are memory mapped into both the host and
DSP memory spaces. The host can read the S5933 configuration registers to
determine where the EVM is located in physical memory and what host interrupt has been assigned to it. The host software also configures the S5933
through the registers for master bus transfers because it knows the physical
addresses of its memory buffers and other PCI devices.
The EVM is configured for PCI-initiated bus master transfers. In this configuration, the DSP cannot access the master read/write address and transfer count
registers, and the DSP cannot be interrupted when the transfer counts reach
0. The DSP can access the other S5933 registers to read/write mailboxes, determine interrupt status, and read/write the FIFOs. Because the DSP typically
uses DMA to control bus master transfers, a ’C6x DMA interrupt can be used
to indicate the end of a transfer.
The S5933 supports both PCI (INTA#) and add-on interface (IRQ#) interrupts.
This allows the host software and DSP software to be notified upon PCI
events, such as the end of bus master transfers (host only), mailbox empty/full,
and bus errors. The DSP is interrupted via its EXT_INT4 interrupt when the
S5933 asserts its IRQ interrupt. The device also allows the host to control the
system reset (SYSRST#) signal directly from software, so a software board
reset can be invoked via the PCI bus.
Figure 1–6 provides a block diagram that shows the ’C6x EVM’s PCI interface
implementation based on the S5933 PCI controller.
TMS320C6x EVM Hardware
1-27
PCI Interface
Figure 1–6. PCI Interface Implementation
PCI configuration
EEPROM
(1 K bytes)
Nonvolatile memory interface
Configuration space
registers (64 bytes)
Write FIFO
(8 × 32)
Operation
registers
’C6201/6701
DSP
Read FIFO
(8 × 32)
PCI bus
Mailbox registers
(4 × 32)
Mailbox registers
(4 × 32)
JTAG TBC
Pass-through
interface
DSP HPI
CPLD registers
AMCC S5933
PCI controller
PCI bus
1-28
Add-on bus
PCI Interface
1.6.2
PCI Controller Operation Registers
The S5933 PCI operation registers allow the host software to:
Configure the device and monitor its status
Read and write mailboxes
Reset the board
Initiate bus master transfers
Access the FIFOs
Table 1–9 identifies the S5933 PCI operation registers, along with their BAR0
offsets and access types. All registers are 32 bits wide and are addressed on
doubleword (DWORD) boundaries.
Table 1–9. S5933 PCI Bus Operation Registers
Host Byte Address
PCI Operation Register
Description
Access
BAR0 + 0x00
OMB1
Outgoing mailbox register 1
Read/write
BAR0 + 0x04
OMB2
Outgoing mailbox register 2
Read/write
BAR0 + 0x08
OMB3
Outgoing mailbox register 3
Read/write
BAR0 + 0x0C
OMB4
Outgoing mailbox register 4
Read/write
BAR0 + 0x10
IMB1
Incoming mailbox register 1
Read only
BAR0 + 0x14
IMB2
Incoming mailbox register 2
Read only
BAR0 + 0x18
IMB3
Incoming mailbox register 3
Read only
BAR0 + 0x1C
IMB4
Incoming mailbox register 4
Read only
BAR0 + 0x20
FIFO
FIFO register port (bidirectional)
Read/write
BAR0 + 0x24
MWAR
Master write address register
Read/write
BAR0 + 0x28
MWTC
Master write transfer count register
Read/write
BAR0 + 0x2C
MRAR
Master read address register
Read/write
BAR0 + 0x30
MRTC
Master read transfer count register
Read/write
BAR0 + 0x34
MBEF
Mailbox empty/full status register
Read only
BAR0 + 0x38
INTCSR
Interrupt control/status register
Read/write
BAR0 + 0x3C
MCSR
Bus master control/status register
Read/write
TMS320C6x EVM Hardware
1-29
PCI Interface
1.6.3
PCI Add-On Bus Operation Registers
The S5933 add-on bus operation registers allow the ’C6201/6701 DSP software to:
Read and write mailbox messages
Read and write FIFO data
Control interrupts
Provide read and write access to the PCI controller’s configuration
EEPROM
The PCI add-on bus operation registers are mapped into the DSP’s CE1 asynchronous memory space starting at 0x01300000 (MAP 0) or 0x01700000
(MAP 1).
Table 1–10 summarizes the S5933 PCI controller’s 64-byte bank of add-on
bus operation registers. Registers in the address offset range of 0x24–0x33
are not available because they are either under direct hardware control or are
inaccessible with PCI-initiated bus mastering.
Table 1–10. PCI Add-on Bus Operation Registers Summary
DSP Byte Address
MAP 1 (MAP 0)
Add-on Bus
Operation Register
Description
Access
01700000 (01300000)
AIMB1
Add-on incoming mailbox register 1
Read only
01700004 (01300004)
AIMB2
Add-on incoming mailbox register 2
Read only
01700008 (01300008)
AIMB3
Add-on incoming mailbox register 3
Read only
0170000C (0130000C)
AIMB4
Add-on incoming mailbox register 4
Read only
01700010 (01300010)
AOMB1
Add-on outgoing mailbox register 1
Read/write
01700014 (01300014)
AOMB2
Add-on outgoing mailbox register 2
Read/write
01700018 (01300018)
AOMB3
Add-on outgoing mailbox register 3
Read/write
0170001C (0130001C)
AOMB4
Add-on outgoing mailbox register 4
Read/write
01700020 (01300020)
AFIFO
Add-on FIFO register port
Read/write
01700024–01700033
(01300024–01300033)
–
Unavailable
None
01700034 (01300034)
AMBEF
Add-on mailbox empty/full status
Read only
01700038 (01300038)
AINT
Add-on interrupt control
Read/write
0170003C (0130003C)
AGCSTS
Add-on general control/status
Read/write
1-30
PCI Interface
The PCI add-on FIFOs can be accessed at offset 0x20 of the PCI add-on register address space (AFIFO) for general-purpose data transfers. However, the
dedicated FIFO access addresses (0x01710000/0x01310000) must be used
during PCI bus master transfers.
1.6.4
PCI Slave Support
The ’C6x EVM’s PCI slave support enables the host, or other PCI device, to
access its PCI controller, JTAG TBC, CPLD, and DSP HPI registers. Once the
base addresses of these devices are obtained by the host driver upon initialization, their registers can be accessed like system memory. When the host accesses the EVM’s slave devices, the S5933 PCI controller activates the passthrough bus to indicate that a data transfer is to take place. A state machine
controller implemented in the EVM’s CPLD manages the interface between
the S5933 and the three targets. This state machine monitors and asserts signals that result in the transfer of data between the S5933’s pass-through data
register and the target interfaces. The S5933 decouples the state machine
from the PCI bus by handling all the PCI-side transactions, so it only has to
manage the reading and writing of data between the S5933 and the targets via
the pass-through interface.
1.6.4.1
JTAG TBC
The ’C6x EVM’s onboard JTAG TBC enables host software to control the
’C6201/6701 JTAG interface for testing and emulation purposes. The debugger uses this interface to control and monitor the DSP. The ’C6x EVM debugger shipped with the EVM kit can be used for source code debugging on the
board without requiring any additional hardware, such as an XDS510.
The JTAG TBC has 24 registers that are memory mapped at DWORD offsets
starting at the address defined by the S5933’s base address register 1 (BAR1).
The TBC is a 16-bit device, so the upper 16 bits of data transfers are not used.
1.6.4.2
CPLD Registers
The ’C6x EVM’s CPLD provides nine memory-mapped board control and status registers that the host software accesses via the PCI bus. The registers are
located at DWORD offsets starting at the address defined by the S5933’s
BAR2. These registers allow the host software to control and monitor the ’C6x
EVM board. Host software can reset the TBC and the DSP, configure and poll
interrupts, monitor several board status signals, control software switches, observe DIP switch and DSP option signals, and check the revision number of
the CPLD. The CPLD registers are only eight bits wide, so the upper 24 bits
of data transfers are not used.
TMS320C6x EVM Hardware
1-31
PCI Interface
See section 1.8.6, PCI Memory-Mapped Board Control/Status Registers, for
details on the PCI memory-mapped CPLD registers.
Similar to the other target interfaces, the add-on bus state machine provides
the control signals that enable data transfers between the PCI controller and
the board control and status registers. Whenever the S5933 indicates either
a PCI read or write access to the board control and status registers (BAR2),
the state machine acknowledges it by asserting S5933 and register control
signals required to complete the data transfer. The lower eight bits of the
S5933 add-on data bus are connected to the registers. The CPLD latches the
register address during the PCI address phase and the state machine asserts
register clock enable and output enable signals. The register address decoding and enable signals are used to clock data into and read data from the nine
registers.
No voltage translation is required because the CPLD has 5-V tolerant inputs.
1.6.4.3
DSP HPI Interface
The ’C6x EVM provides DSP host port interface (HPI) access from the PCI
bus, giving host software read and write access to all of the DSP’s memory
space. The ’C6x EVM supports both random and sequential accesses using
the PCI controller’s BAR3 and BAR4 memory regions, respectively.
The three ’C6201/6701 HPI registers are memory mapped on the ’C6x EVM
at DWORD offsets starting at the address defined by the S5933’s base address register 3 (BAR3). The fourth address in the BAR3 region simply aliases
to the HPID register. The three registers map directly to the DSP’s HPI control
(HPIC), address (HPIA), and data (HPID) registers. Table 1–11 summarizes
the HPI registers mapped into BAR3.
Table 1–11. DSP HPI Registers (BAR3)
Host Byte Address
1-32
HPI Register
Description
Access
BAR3 + 0x00
HPIC
HPI control register
Read/write
BAR3 + 0x04
HPIA
HPI address register
Read/write
BAR3 + 0x08
HPID
HPI data register
Read/write
BAR3 + 0x0C
HPID
HPI data register (alias)
Read/write
PCI Interface
Before HPI data transfers are performed successfully, the HPIC register must
be properly initialized. The ’C6x EVM handles HPI data transfers with the first
half-word being the least significant word for compatibility with the little-endian
PCI bus. The ’C6201 HPIC register bit HWOB must, therefore, be set to 1 to
select this data ordering. A value of 0x00010001 should be written to the HPIC
register at BAR3 offset 0. Any subsequent writes to the HPIC register, such as
controlling host and DSP interrupts, must keep bits 0 and 16 high in the HPIC
to maintain the low-word/high-word transfer order.
The ’C6x EVM CPLD accepts data transfer requests from the S5933 PCI controller and asserts the DSP’s HPI control signals required to transfer two 16-bit
words. The CPLD also handles the HPI ready control signal monitoring, so
software handshaking is not required.
Byte enables asserted during the host write to the HPID register are transferred to the HPI byte enables (HBE[1:0]) by the ’C6x EVM’s CPLD. The ’C6x
EVM therefore supports byte, word, and doubleword data writes to anywhere
in the DSP’s memory space. This capability is useful for modifying individual
bytes and words in memory or memory-mapped registers without corrupting
the other bytes in a 32-bit word. A standard 32-bit access to the HPID register
results in all four bytes being modified in the DSP memory space. From a software perspective, the pointer to the HPID register is simply modified and cast
accordingly to perform byte and word write operations. Assuming a doubleword pointer to the HPID register is named HPI_DATA, a write access to byte
3 (MSbyte) of a 32-bit word would be performed as follows in C:
*((*unsigned char)(((unsigned long)HPI_DATA)+3)) = ByteValue;
Host access to the HPI via the BAR3 memory region therefore allows random
read and write accesses anywhere in the DSP memory space with byte, word,
and doubleword support. BAR3 accesses require that the HPIA register be updated for each transfer to a different address.
The ’C6x EVM also provides support, using the BAR4 memory region, for sequential data transfers between the host and the DSP by taking advantage of
the HPI support for read and write autoincrement accesses. This capability allows blocks of data to be moved more efficiently between the host and the DSP
without incurring the overhead associated with passing the memory address
each time.
TMS320C6x EVM Hardware
1-33
PCI Interface
The HPI data registers in BAR4 are used when data is transferred between the
host and DSP in autoincrement mode. This separate region eases the decoding and makes the transfers more efficient over the PCI bus with support for
sequential and burst transfers. The HPI controller in the CPLD does not care
about the addresses in this range, only that an access is within the address
range. All accesses to BAR4 are written directly to the HPID register, assuming
that the HPIA and HPIC registers have been initialized previously with autoincrement mode selected.
Sequential HPI data accesses with burst support is provided with host accesses to the memory-mapped region defined by BAR4. BAR4 provides a 64K
DWORD (256K byte) memory window that can be addressed as a linear array
or a circular buffer by host software. Accesses to the BAR4 memory region result in sequential data words being transferred to the HPI data register. The
BAR4 offset address is ignored, since it is assumed that the HPI’s address
autoincrement feature has been selected. If the host cannot access memory
past the 256K byte BAR4 allocation, the PCI controller ignores the request.
The ’C6x EVM’s sequential address burst support eliminates the need for the
host to arbitrate for the PCI bus as often and eliminates the need to pass the
board for every data transfer.
The burst transfers to the HPI cannot occur at the full 132M bytes/s PCI data
rate because the ’C6201/6701 HPI is not a 32-bit-wide, synchronous interface.
The HPI presents only a 16-bit interface; hardware handshaking via its ready
signal requires multiple PCI clocks per 32-bit data transfer.
Because the ’C6201/6701 is not 5-V signal tolerant, the S5933 outputs are
translated to 3.3-V-compatible signals using two TI ’CBTD3384 buffer devices.
1.6.5
PCI Master Support
The ’C6x EVM supports bus mastering of the PCI bus, enabling the EVM to
take control of the PCI bus and transfer data between the host and EVM memory. The S5933 PCI controller handles the bus mastering transfers on the
PCI bus. Transfers can be driven directly by ’C6201 software or automatically
in the background with the DMA controller. This bus mastering support allows
data transfers to be under EVM control without continuous host intervention.
The host does need to get involved initially to configure the S5933’s PCI address and transfer counters and initiate the transfer, but it is not involved at all
in the actual data transfers. The host initialization is required because only the
host knows the address of its, and other PCI devices’, memory buffers.
1-34
PCI Interface
Bus master transfers are supported by the S5933 using two on-chip FIFOs for
read and write transfers between the ’C6201/6701 and the PCI bus. Each
FIFO is 32 bits wide and 8 words deep. These FIFOs are addressed asynchronously from the DSP-side because the PCI controller and the DSP operate at
different rates. The S5933 provides two FIFO flags that indicate the status of
each FIFO (RDEMPTY/WRFULL). These FIFO flags are used to control the
flow of data to and from the DSP.
The S5933 registers and FIFOs are memory mapped into the DSP’s CE1
asynchronous memory space, along with the audio codec control registers,
DSP memory-mapped CPLD registers, and asynchronous expansion memory. State machines in the CPLD manage the interface between the ’C6201 and
the S5933 read and write FIFOs. They monitor S5933 FIFO flags and accesses by the DSP to the S5933 FIFO at address 0x1310000 (0x1710000) and
generate the external interrupts to the DSP to control the data transfers. The
FIFOs must be accessed using the dedicated memory-map address, rather
than the PCI add-on register offset, for the external interrupts to be generated.
Master read transfer support and master write transfer support are independently enabled by the DSP by setting two bits in the CPLD’s memory-mapped
FIFOSTAT register. When the PCIMREN bit (bit 1) is set, the CPLD generates
EXT_INT5 interrupts to the DSP whenever data is available to be read in the
PCI controller’s read FIFO. When the PCIMWEN bit (bit 0) is set, the CPLD
generates EXT_INT6 interrupts to the DSP whenever the write FIFO is not full
and can accept data. Typically, the DSP triggers DMA read and write transfers
on these interrupts for the most efficient transfers. However, the FIFO flags in
the CPLD’s FIFOSTAT register or the interrupts themselves can also be polled
to drive the data transfers. The PCIMREN and PCIMWEN bits must be disabled at the completion of a bus master transfer and reenabled before the next
one begins.
Both the host and DSP software must perform certain initialization and control
actions to configure the ’C6x EVM for PCI bus master transfers. The host and
DSP software actions can be performed independently and do not require any
synchronization. Depending on the application, it may be necessary for the
host software to notify the DSP software about the DSP memory space source/
destination address and number of words to be transferred. The PCI bus mastering operation begins only when both sides have completed their actions.
The following subsections identify the actions that must be performed by the
host and DSP software to perform PCI bus master transfers.
TMS320C6x EVM Hardware
1-35
PCI Interface
1.6.5.1
Host Software Actions
The ’C6x EVM is factory-configured for PCI (host) initiated bus master transfers. This means that only the host software can enable, control, and monitor
the S5933 PCI controller’s FIFO bus master on the PCI bus. The EVM uses
the PCI-initiated configuration because only the host software knows the
physical memory addresses of its memory, as well as other PCI devices’
memory. For PCI-initiated bus mastering, the host software must complete
certain actions to set up the FIFO bus mastering.
Define interrupt capabilities. The host can be interrupted independently
at the end of read and write transfers when the transfer counters reach 0.
The S5933 INTCSR register’s bits 14 and 15 must be set accordingly.
Reset FIFO flags. The FIFO state must be initialized to empty by resetting
the FIFO flags. The S5933 MCSR register’s bits 25 and 26 can be set to
reset these flags.
Define FIFO management scheme. The FIFOs must be configured for
the desired times that the S5933 should request mastering the PCI bus.
For reads, the PCI bus can be requested when there are at least one or
at least four vacant FIFO locations. For writes, the PCI can be requested
when there are at least one or at least four filled FIFO locations. The S5933
does not have to request the bus as often when four or more data words
are transferred during each bus grant period; using this FIFO management scheme improves throughput in most applications. The FIFO management scheme is selected by initializing the S5933’s MCSR register’s
bits 9 and 13.
Define PCI-to-EVM and EVM-to-PCI priority. It is recommended that
write versus read priority be set equal by setting bits 8 and 12 of the
S5933’s MCSR register.
Define transfer source/destination address. The start of the PCI-side
source address must be written to the S5933’s MRAR register for bus
master reads, and the destination address must be written to the MWAR
register for bus master writes. This address is the system’s physical
memory address that is presented on the PCI bus. This address must be
on a 32-bit word address (lower two address bits 0).
Define transfer byte count. The S5933’s MWTC and MRTC registers
must be initialized with the number of bytes to be transferred for bus master writes and bus master reads, respectively. The number of bytes must
be a multiple of four because the ’C6x EVM only supports 32-bit, bus master data transfers.
1-36
PCI Interface
Enable bus mastering. After the other actions have been done, the read
and write bus master operations can be independently enabled by setting
bits 10 and 14 of the S5933’s MCSR register. This enables the S5933’s
hardware to begin requesting the PCI bus to move data to and from its
FIFOs.
Provide DSP software with data transfer information. In most applications, the host software must notify the DSP software of the data transfer
information, such as the DSP memory space source or destination address and the number of 32-bit words to be transferred. This allows the
DSP software to initialize its DMA controller to handle the transfers from
the S5933 to its memory space properly. This data transfer information
can be sent to the DSP via the HPI or, more commonly, through the mailbox.
Provide application-specific response to end of transfer interrupt. If
interrupts were enabled, the host software must provide an interrupt service routine to handle PCI interrupts. The host software can perform an
application-specific action in response to the end-of-transfer interrupt
generated by the S5933. One example action is to prepare for the next
data transfer.
The DSP must also perform certain actions in order to for the bus mastering
to begin.
1.6.5.2
DSP Software Actions
The ’C6x EVM’s DSP software is responsible for moving the data between its
memory space and the S5933 PCI controller’s bidirectional FIFO to complete
the data transfers. The DSP typically uses DMA to handle the reading and writing of the data from and to the S5933’s FIFO. Optionally, the DSP software can
perform this data movement itself using an interrupt service routine or by polling the status of the interrupts or FIFO flags themselves.
The ’C6x EVM uses EXT_INT5 to control read bus master transfers from the
S5933 read FIFO to the DSP memory space and EXT_INT6 to control write
bus master transfers from the DSP memory space to the S5933 write FIFO.
Logic in the CPLD, when explicitly enabled by the DSP software, monitors the
FIFO flags and DSP accesses to the S5933 FIFO and controls the interrupts
to the DSP.
TMS320C6x EVM Hardware
1-37
PCI Interface
The DSP software must perform the following actions to support PCI bus mastering:
Initialize ’C6x DMA control registers. The primary DMA control register
must be configured for incrementing address modification, 32-bit elements, and split-mode disabled. The transfers must be synchronized for
reads or writes by initializing the RSYNC and WSYNC bits appropriately.
For bus master reads, read synchronization based on EXT_INT5 must be
selected. For bus master writes, write synchronization based on
EXT_INT6 must be selected.
The secondary DMA control register can be configured to interrupt the
DSP upon the transfer completion.
Initialize ’C6x DMA source/destination address register. The source
address register must be initialized for bus master writes, and the destination address register must be initialized for bus master reads.
Initialize ’C6x DMA transfer counter register. The transfer counter register’s FRAME COUNT and ELEMENT COUNT values must be set to select the number of frames and 32-bit elements that are to be transferred.
This value must match the number of transfers that the host software indicates.
Start the ’C6x DMA controller. The DMA controller can be started by writing 01b to the START bits of the primary DMA control register.
Enable CPLD master transfer support. Before bus master transfer interrupts are generated to the DSP, the respective CPLD control bits must be
set to 1 as needed. For bus master writes, the CPLD’s FIFOSTAT
PCIMWEN bit must be set to 1. For bus master reads, the PCIMREN bit
must be set to 1. These enables activate a state machine in the CPLD that
generates the external interrupts to the DSP.
Provide application-specific response to end-of-transfer interrupt. If
interrupts were disabled, the DSP software must provide an interrupt service routine to handle internal DMA block transfer complete interrupts. The
DSP software can perform an application-specific action in response to
the interrupt generated internal to the DSP. One example action is to prepare for the next data transfer.
Disable CPLD master transfer support. To disable the bus master interrupts to the DSP and put the CPLD state machine in an idle state, the PCI
bus master enable bits in the CPLD’s FIFOSTAT register must be cleared
to 0. The bus master enable bits must be disabled before another master
transfer is started.
1-38
JTAG Emulation
1.7 JTAG Emulation
The EVM provides embedded JTAG emulation, which is accessible via the PCI
bus, as well as support for an external XDS510 emulator. The selected JTAG
method is user configurable via the DIP switches when the board is operated
outside the PC or via the software switches when it is in the PC.
The TI SN74ACT8990 JTAG test bus controller (TBC) provides memorymapped control of the ’C6201/6701 JTAG interface. This allows the ’C6x EVM
debugger to be used with the EVM without an external emulator.
The ’C6x EVM’s embedded emulation support provides several benefits:
Emulation is supported without external cabling, monitor software, or consumption of user resources.
Easy access to the ’C6201 supports high-level language (HLL) debuggers, factory testing, and field diagnostics.
System boot ROMs are not needed. The host can download all necessary
program and data information through the emulation port.
The TBC is presented to the PC host software as 24 memory-mapped registers. Each register is mapped at 32-bit (DWORD) address boundaries, but
only the lower 16 bits of data words are connected to the 16-bit TBC device.
The PCI controller’s pass-through interface is used to access the slave TBC.
The CPLD includes a state machine that manages the S5933-to-TBC data
transfers via the pass-through interface.
A 14-pin (two rows of seven pins) header on the EVM (J5) supports an external
XDS510 or XDS510WS emulator connection. This connection is required for
debugging the EVM outside of a PC. Two TI CBT quad 2:1 multiplexer devices
(SN74CBT3257) are used to provide the 5-V to 3.3-V translation required from
the TBC to the ’C6201 and the selection between internal and external JTAG
emulation. The JTAG interface to the ’C6201 consists of seven signals: TMS,
TDO, TDI, TCLK, TRST, EMU1, and EMU0. The two quad multiplexer devices
are required to switch and translate seven signals. The use of the CBT devices
also allows 3.3- or 5-V external emulator connections. Figure 1–7 shows how
the DSP’s JTAG signals are selected between the TBC and the external JTAG
header using the CBT multiplexers.
TMS320C6x EVM Hardware
1-39
JTAG Emulation
Figure 1–7. JTAG Emulation Selection
SN74CBT3257
multiplexer
TMS2/EVNT0
TMS3/EVNT1
TMS5/EVNT3
74ACT8990
JTAG
TBC
EMU0 MUX
XEMU0
EMU1 MUX
TMS0
XEMU1
EMU0
TDI
TRST MUX
XTRST
TDO
TMS MUX
TCK
XTMS
EMU1
TRST
TMS
JTAG SELECT
(from CPLD)
’C6201/6701
DSP
TDI
XEMU0
TDO
XEMU1
TDI MUX
XTDI
XTRST
External
JTAG
header
XTMS
XTDO
XTDI
TCK MUX
XTCK
XTDO
XTCK
PD GND
TCK
TDO MUX
XTCK_RET
SPARE MUX
SN74CBT3257
multiplexer
5V
The TBC does not directly provide pins dedicated for the EMU0, EMU1, and
TRST signals that are present on the external JTAG header. However, the TBC
can control and monitor these signals using the available TMSx pins. The
TMS2 and TMS3 signals are used to monitor the EMU0 and EMU1 signals
from the ’C6201, respectively. The TMS5 signal is used to control the DSP’s
TRST signal. The host emulation software monitors and controls these signals
via the TBC’s PCI interface.
You can select between internal and external JTAG emulation via DIP switch
SW2–9 during external operation or via a software switch for internal PCI
operation. The selection controls the multiplexers’ select input signal
accordingly.
A 10.368-MHz JTAG clock (TCK) is provided by the XDS510 or XDS510WS
when external JTAG emulation is selected. The EVM provides a 16.625-MHz
clock when the JTAG TBC is used for embedded emulation. The 16.625-MHz
clock is derived from the EVM’s OSC A-oscillator output using a single
SN74F74 D-type flip-flop device configured for a divide-by-2 operation.
1-40
Programmable Logic
1.8 Programmable Logic
The ’C6x EVM uses a CPLD (Alterat part number EPM7256S) to implement
the board’s required glue logic and to provide control and status interfaces for
both host and DSP software. The CPLD provides the following functions:
-
Reset control
Power management
Dual DSP clock oscillator control
PCI controller/DSP interface control
PCI memory-mapped board control/status registers
DSP memory-mapped control/status registers
PCI and DSP interrupt control
CE1 memory decoding
Data transceivers control
User options control
The EPM7256S CPLD is a 208-pin plastic quad flat pack (PQFP) device that
provides 5000 usable gates, 160 user I/O pins, and a 10-ns pin-to-pin delay.
The device is EEPROM-based and is in-system programmable via a dedicated JTAG interface presented as a 10-pin header on the EVM. This header
is a factory option that is not installed.
The EPM7256S uses 5 V for internal operation and input buffers and 3.3 V for
output drivers. This provides an optimal design with fast internal speed and the
ability to interface with both 3.3- and 5-V devices on the EVM.
Figure 1–8 provides an overview of the CPLD’s functions and their associated
interfaces.
TMS320C6x EVM Hardware
1-41
Programmable Logic
Figure 1–8. CPLD Interfaces and Functions
Reset
pushbutton
Voltage
supervisor
Board/DSP reset and
power management logic
Dual DSP clock
oscillator control
PCI controller/JTAG TBC
interface control
PCI
PCI controller/DSP
interface control
controller
(HPI/EMIF)
Board
devices
Oscillator
buffer
JTAG
TBC
PCI and DSP memory-mapped
control/status registers
’C6201/6701
DIP
switches
User options
(DIP/software switches)
Interrupt control
Audio
codec
Expansion
memory
Transceivers
1-42
CE1 memory decoding/
transceivers control
DSP
Programmable Logic
1.8.1
Reset Control
The CPLD works in tandem with a Maxim MAX708S voltage supervisor to provide several types of reset signals on the ’C6x EVM.
The EVM supports several methods to reset the board, DSP, JTAG TBC, and
daughterboard. There are five reset sources:
Power-up and undervoltage resets from the voltage supervisor
Manual pushbutton reset
PCI system reset from the PCI controller
Daughterboard reset under DSP software control
DSP and TBC resets under host software control
The MAX708S voltage supervisor asserts an active low reset to the CPLD
whenever the 3.3-V supply is below 3.0 V, such as during power up and brownout conditions. Additionally, the voltage supervisor supports an external reset
control signal generated by the CPLD that forces a board reset whenever the
reset pushbutton is pressed or a PCI system or software reset is received. The
MAX708S provides an output signal that indicates when the 1.8-V/2.5-V supply has an undervoltage condition that the CPLD uses to control the DSP reset.
The DSP is held in reset whenever either its core or I/O voltage is below a defined threshold.
The S5933 PCI controller provides a SYSRST# output that causes a reset
whenever the PCI bus is reset, such as when a system is rebooted with CtrlAlt-Del or when the host software sets a bit in its MCSR register. The
SYSRST# signal provides an automatic reset signal as well as a software-controlled reset control, similar to the voltage supervisor’s support for automatic
and manual reset.
The DSP software has access to a memory-mapped CPLD register bit that directly controls the reset to the daughterboard. This daughterboard reset
(XRESET#) is asserted low during reset but defaults to an inactive high upon
release of reset. This provides a reset to the daughterboard whenever the
EVM is in reset, but it does not hold the daughterboard in reset. Subsequent
control over the daughterboard reset is exclusively under DSP software control.
Both the DSP and JTAG TBC can be individually reset under host software
control. PCI memory-mapped CPLD register bits allow the host software to directly control the reset signals to both the ’C6201 DSP and JTAG TBC. This
is useful when doing controlled booting such as an HPI boot, performing a simple DSP reset operation, or putting the TBC in a known state. During board
reset, the DSP and JTAG TBC are also held in reset. The DSP is also forced
into reset whenever the board is in reset or its core voltage is not within
TMS320C6x EVM Hardware
1-43
Programmable Logic
specification. When the board reset is released, the two register bits default
to not active so that the DSP and TBC are not held in reset in the external environment. The host software-controlled DSP and TBC resets are only available
with internal PCI operation.
The board reset is produced when either the MAX708S indicates a reset (power up, undervoltage condition, or manual switch reset) or the PCI controller indicates a reset (PCI reset or manual software reset). The MAX708S provides
two board reset signals: one active low and the other active high. The activelow board reset is routed to the CPLD, which directly controls the reset to the
DSP, JTAG TBC, and daughterboard. The CPLD also indirectly controls the
reset or power down of the audio codec via the McBSP0 multiplexer and the
SDRAM via the clock enable control signals. The active-high board reset from
the MAX708 is routed directly to the SBSRAM snooze (ZZ) input to put the device in an inactive, low-power state. When the EVM board is held in reset, it
cannot respond to host PCI accesses.
The PCI bus can only reset the PCI controller at power up and whenever the
system is reset. The BIOS only assigns the memory region addresses and the
host interrupt upon reset of the host PC.
In the PCI environment, the EVM software drivers can put several board devices in a low-power state by holding the board in reset. The PCI specification
recommends that PCI boards that dissipate more than 10 watts implement a
default power reduction mode. This can be supported under driver control.
Figure 1–9 summarizes the ’C6x EVM’s reset configuration.
1-44
Programmable Logic
Figure 1–9. Reset Configuration
3.3 V
1.8/2.5 V
MAX708S
voltage
supervisor
BRD_RST
SBSRAM ZZ
(power down)
PCI BUS
BRD_RST#
VCC2BAD#
MAN_RST#
RST#
SW_RST#
Reset
pushbutton
switch
TBC_RST#
JTAG TBC
PCI_SYSRST#
text
Data, addr
& ctrl
Data, addr
& ctrl
TMS320C6201/
6701 DSP
PCI
memorymapped
registers
DSP
memorymapped
registers
Reset logic
S5933
PCI
controller
CExSDEN
MCBSP0_SEL
XRESET#
DSP_RESET#
SDRAM
McBSP0
MUX/codec
Daughterboard
EPM7256S CPLD
1.8.2
Power Management
The PCI Local Bus Specification Revision 2.1 recommends that PCI boards
that can dissipate more than 10 watts under full operation have a power-saving
state. The ’C6x EVM CPLD includes logic that provides a power management
capability that does not require additional devices. Various devices on the
EVM can be placed in a low-power state to reduce power consumption.
The EVM’s power management feature is activated when the board is held in
reset by the host software. This is achieved when the host software asserts
the PCI controller’s SYSRST# signal (setting bit 24 of the S5933 PCI controller’s MCSR register).
TMS320C6x EVM Hardware
1-45
Programmable Logic
When the EVM board is held in reset, CPLD logic directly controls devices to
power them down or put them into a low-power state. The ’C6201 DSP is held
in reset, which forces it to power down. The SBSRAM is powered down by asserting its ZZ sleep input signal. The SDSRAM is disabled and put into a lowpower mode by deasserting its CKE clock enable input signal. The McBSP0
multiplexer is configured to power down the audio codec by asserting the codec’s PWDN input signal. Both an external reset and the DSP’s power-down
indication are provided to the expansion peripheral interface to enable powerdown support on a daughterboard. Other devices on the board, such as the
buffers, are indirectly placed into a low-power mode, since their inputs are static when the other devices are inactive. Table 1–12 lists the EVM devices that
are directly controlled by CPLD logic and the control signals that are used to
implement the power management feature of each device.
Table 1–12. Power Management Device Control Summary
1.8.3
Device
Power Management
Control Signals
DSP
RESET = 0
SBSRAM
ZZ = 1
SDRAM
CKE = 0
Audio codec
PDWN = 0
Daughterboard
XRESET = 0,
DSP_PD = 1
Dual DSP Clock Oscillator Control
The ’C6x EVM includes dual DSP clock oscillator support to enable operation
at the 160-MHz core clock rate with one-half-rate SBSRAM timing or at the full
OSC A SBSRAM clock rate. You have the flexibility to select the clock rate that
provides the best performance for your application. This clock selection can
be made with the EVM DIP switches or from host software using the support
software switches. For external operation, only the DIP switches are used to
select the clock. For internal (PCI) operation, the DIP switches are selected
for control by default unless overridden by host software using the software
switches.
1-46
Programmable Logic
The user clock selection is used by CPLD logic to control two clock buffer enables. Each clock oscillator’s output is connected to an ’LVT125 buffer that has
independent output enables. The two clock buffer outputs are connected together to drive the DSP’s CLKIN input. To provide the 2:1 clock selection function and ensure that there is no contention between the oscillators, the CPLD
logic performs a “break-before-make” function that ensures that only one clock
oscillator is driving the DSP’s CLKIN input. Figure 1–10 summarizes the DSP
clock selection configuration.
Figure 1–10. DSP Clock Selection Configuration
Clock mode/select
DIP switches
2
EPM7256S
CPLD
Clock mode/select
software switches
2
(Switch MUX
and
clock control)
OSC A
OSC_A
CLKMODE
and PLLFREQ
CLKIN
OSC_B
OSC B
CLKOUT1
OSC A or
OSC B
’C6201
DSP
’LVT125
TMS320C6x EVM Hardware
1-47
Programmable Logic
1.8.4
PCI Controller/JTAG TBC Interface Control
The CPLD includes a PCI add-on bus state machine that monitors and controls
the interfaces between the S5933 PCI controller and the PCI memory-mapped
devices on the EVM, including the JTAG TBC.
Whenever the S5933 indicates either a PCI read or write TBC access, the state
machine acknowledges it by asserting S5933 and TBC control signals required to complete the data transfer. The lower 16 bits of the S5933 add-on
data bus are connected to the TBC data bus interface. The CPLD latches the
TBC register address during the PCI address phase and the state machine asserts the TBC read and write strobes to enable data transfers.
1.8.5
PCI Controller/DSP Interface Control
The CPLD’s add-on bus state machine supports PCI transfers with the DSP’s
HPI, as well as DSP EMIF transfers with the S5933 PCI controller. These capabilities allow the host and DSP software to communicate with one another. The
host software has read/write access to the DSP’s memory space and can exchange messages with the DSP software using the S5933’s mailboxes. The
DSP software has read/write access to the host PC’s memory space and can
also exchange messages with the host software using S5933’s mailboxes.
The S5933’s bidirectional FIFOs can also be used to pass data between the
host and DSP software, although they are typically only used for bus master
transfers.
The DSP HPI can be accessed by the host software with BAR3 and BAR4 PCI
accesses. Whenever the S5933 indicates either a PCI read or write HPI access, the state machine acknowledges it by asserting S5933 and HPI control
signals required to complete the data transfer. The lower 16 bits of the S5933
add-on data bus are connected to the HPI data bus interface, with TI ’CBT devices used to translate from 5- to 3.3-V signals. The internal byte-lane switching feature of the S5933 allows the low and high words of the 32-bit PCI data
transfers to be output on the lower 16 bits of the add-on bus during the low and
high word data transfer times to the HPI. The CPLD latches the HPI register
address during the PCI address phase, and the state machine asserts the HPI
control signals to enable data transfers.
CPLD output pins are shared to support both the TBC address and HPI control
signals. Because an access can only be directed to one of the two at any one
time, the outputs can be used for both interfaces and controlled as required
for the different accesses. This is possible since the TBC address signals are
don’t cares unless the TBC read/write strobes are asserted, and the HPI control signals are don’t cares unless the HPI chip and data select signals are asserted.
1-48
Programmable Logic
HPI data transfers are 16 bits wide, so a 32-bit data transfer between the host
and DSP requires two HPI data transfers. The CPLD state machine manages
each 16-bit data transfer by controlling the appropriate byte enable and other
control signals. The state machine includes monitoring of the HPI ready output
signal to determine when the next write can proceed and when read data is
available.
Because the state machine is synchronous to the 33-MHz PCI clock, there is
a minimum of 30 ns between control signal transitions. Therefore, the maximum transfer rate between the host and DSP is defined by the required HPI
transfer protocol to transfer two 16-bit words and the 30-ns state machine
clock period.
CPLD arbitration logic allows both PCI and DSP EMIF transfers to share the
common PCI add-on bus. The add-on state machine controls DSP EMIF accesses to the S5933 controller’s registers and FIFOs. Because the state machine may be in the process of transferring data between the S5933 and another device when the DSP attempts to access the S5933, the state machine provides arbitration logic that holds off the EMIF access via the DSP’s ARDY input
until the current add-on transfer is finished. Burst transfers are finished as
soon as possible to allow EMIF accesses to have priority over the add-on bus.
Logic is also included that disables the EMIF data bus connection to the addon bus while the add-on bus is being used for other transfers to prevent data
bus contention. When an EMIF access to the S5933 is taking place, PCI transfers are held until the add-on bus is released.
The CPLD add-on bus state machine controls the add-on bus control signals
during EMIF accesses to the S5933 registers and FIFOs. When the EMIF is
granted the add-on bus, the state machine latches the register address from
the DSP’s address lines and presents them on the add-on address bus. The
other add-on bus control signals are also asserted by the state machine to provide data to the DSP EMIF data bus or to latch the data into the selected S5933
register or FIFO.
There is a 32-bit data interface between the DSP EMIF and the S5933 PCI
controller. The DSP’s EMIF 32-bit data bus is buffered with ’LVTH162245 and
’CBTD3384 devices to isolate it from the PCI add-on bus and to provide voltage translation between 5 V and 3.3 V.
TMS320C6x EVM Hardware
1-49
Programmable Logic
1.8.6
PCI Memory-Mapped Board Control/Status Registers
The CPLD’s add-on bus state machine supports PCI transfers with nine
memory-mapped board control and status registers that are also implemented
in the CPLD. These registers provide the host with the following capabilities:
Interrupt the DSP (nonmaskable interrupt)
Enable interrupts from the DSP and TBC
Reset the DSP and TBC
Monitor status of EVM devices
Read the user-option DIP switches
Select the user options via software switches
Read the selected DSP options
Read the CPLD revision number
Table 1–13 summarizes the PCI memory-mapped CPLD registers.
1-50
Table 1–13. PCI Memory-Mapped CPLD Registers
Address
Name
Description
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAR2 + 0X00
CNTL
Control
DSPNMI
RW
0 (no NMI)
TBCINTEN
RW
0 (disabled)
HINTEN
RW
0 (disabled)
TBCRDY
R
–
TBCINT
R
–
DSPHINT
R
–
TBCRST
RW
0 (no reset)
DSPRST
RW
0 (no reset)
BAR2 + 0X04
STAT
Status
–
–
–
VCC2BAD
R
–
CODECPD
R
–
DSPPD
R
–
XCNTL1
R
–
XCNTL0
R
–
USERLED1
R
–
USERLED0
R
–
BAR2 + 0X08
SWOPT
SW switch –
options
–
–
–
H_CLKMODE
RW
0 (X4)
H_CLKSEL
RW
0 (osc A)
H_ENDIAN
RW
0 (little)
H_JTAGSEL
RW
0 (ext)
H_USER2
RW
0
H_USER1
RW
0
H_USER0
RW
0
BAR2 + 0X0C
SWBOOT
SW switch –
boot mode
SWSEL
RW
0 (DIP switch)
–
–
–
–
–
–
H_BMODE4
RW
0
H_BMODE3
RW
0
H_BMODE2
RW
1
H_BMODE1
RW
0
H_BMODE0
RW
1
BAR2 + 0X10
DIPOPT
DIP switch –
options
–
–
–
S_CLKMODE
R
–
S_CLKSEL
R
–
S_ENDIAN
R
–
S_JTAGSEL
R
–
S_USER2
R
–
S_USER1
R
–
S_USER0
R
–
BAR2 + 0X14
DIPBOOT
DIP switch –
boot mode
–
–
–
–
–
–
–
–
–
S_BMODE4
R
S_BMODE3
R
S_BMODE2
R
S_BMODE1
R
S_BMODE0
R
BAR2 + 0X18
DSPOPT
DSP –
options
–
–
–
CLKMODE
R
–
CLKSEL
R
–
LENDIAN
R
–
JTAGSEL
R
–
USER2
R
–
USER1
R
–
USER0
R
–
BAR2 + 0X1C
DSPBOOT
DSP –
boot mode
–
–
–
–
–
–
–
–
–
BMODE4
R
–
BMODE3
R
–
BMODE2
R
–
BMODE1
R
–
BMODE0
R
–
BAR2 + 0X20
CPLDREV
CPLD
revision
CREV7
R
–
CREV6
R
–
CREV5
R
–
CREV4
R
–
CREV3
R
–
CREV2
R
–
CREV1
R
–
CREV0
R
–
1-51
Programmable Logic
TMS320C6x EVM Hardware
Bit 7
Programmable Logic
The following subsections describe each of the PCI memory-mapped CPLD
registers.
Note:
All register bits are active high (1) for consistency and ease of use. For example, to reset the DSP, bit 0 of the CNTL register must be set to a 1. Highlighted
register values denote the power-up default values.
1.8.6.1
PCI CNTL Register (BAR2 + 0x00)
The CNTL register enables the host software to interrupt and reset the DSP,
enable interrupts from the DSP, and monitor TBC and DSP status. The host
can be interrupted whenever the TBC or DSP host interrupts are asserted, or
it can poll the status of these interrupt signals directly. The nonmaskable interrupt (NMI) and reset bits must be manually toggled to assert and deassert the
respective signals. Table 1–14 summarizes the function of each bit in the
CNTL register. Highlighted register values denote the power-up default values.
Table 1–14. PCI CNTL Register Bit Definitions
Bit
Name
Access Description
7
DSPNMI
RW
Controls DSP’s NMI (0 = no NMI, 1 = assert NMI)
6
TBCINTEN
RW
TBC interrupt enable (0 = disable TBC interrupt, 1 = enable TBC interrupt)
5
HINTEN
RW
DSP host interrupt enable (0 = disable host interrupt, 1 = enable host interrupt)
4
TBCRDY
R
TBC ready status (0 = TBC not ready, 1 = TBC ready)
3
TBCINT
R
TBC interrupt status (0 = no TBC interrupt, 1 = TBC interrupt)
2
DSPHINT
R
DSP host interrupt status (0 = no host interrupt, 1 = host interrupt)
1
TBCRST
RW
TBC hardware reset (0 = no TBC reset, 1 = TBC reset)
0
DSPRST
RW
DSP hardware reset (0 = no DSP Reset, 1 = DSP reset)
1-52
Programmable Logic
1.8.6.2
PCI STAT Register (BAR2 + 0x04)
The STAT register enables the host software to monitor the DSP core voltage,
codec, DSP power down, daughterboard control, and user-defined LED status. Table 1–15 summarizes the function of each bit in the STAT register.
Table 1–15. PCI STAT Register Bit Definitions
Bit
Name
Access Description
7
–
–
–
6
VCC2BAD
R
DSP core voltage status (0 = core voltage OK, 1 = core voltage bad)
5
CODECPD
R
Codec power-down status (0 = codec not in power down, 1 = codec in power
down)
4
DSPPD
R
DSP power-down status (0 = DSP not in power down, 1 = DSP in power down)
3
XCNTL1
R
Control signal from DSP to daughterboard (0 = TTL low, 1 = TTL high)
2
XCNTL0
R
Control signal from DSP to daughterboard (0 = TTL low, 1 = TTL high)
1
USERLED1
R
User LED 1 status (0 = LED extinguished, 1 = LED illuminated)
0
USERLED0
R
User LED 0 status (0 = LED extinguished, 1 = LED illuminated)
1.8.6.3
PCI SWOPT Register (BAR2 + 0x08)
The SWOPT register enables the host software to override the EVM’s onboard
user option DIP switches. This capability provides software switches, which
allow the DSP options to be controlled without having to remove the PC’s cover. The values in this register are not used unless the SWSEL bit in the
SWBOOT register is set to 1. Table 1–16 summarizes the function of each bit
in the SWOPT register. Highlighted register values denote the power-up default values.
Table 1–16. PCI SWOPT Register Bit Definitions
Bit
Name
Access
–
Description
7
–
–
6
H_CLKMODE
RW
Host clock mode (0 = ×4 mode, 1 = ×1 mode)
5
H_CLKSEL
RW
Host clock select (OSC A, OSC B)
4
H_ENDIAN
RW
Host endian control (0 = little endian, 1 = big endian)
3
H_JTAGSEL
RW
Host JTAG selection (0 = external XDS510, 1 = onboard JTAG TBC)
2
H_USER2
RW
Host user-defined option 0 (0 = on, 1 = off)
1
H_USER1
RW
Host user-defined option 1 (0 = on, 1 = off)
0
H_USER0
RW
Host user-defined option 2 (0 = on, 1 = off)
TMS320C6x EVM Hardware
1-53
Programmable Logic
1.8.6.4
PCI SWBOOT Register (BAR2 + 0x0C)
The SWBOOT register enables the host software to override the EVM’s boot
mode DIP switches. This capability provides software switches, which allow
the DSP boot mode to be controlled without having to remove the PC’s cover.
The values in this register do not get used unless the SWSEL bit is set to 1.
Table 1–17 summarizes the function of each bit in the SWBOOT register.
Highlighted register values denote the power-up default values.
Table 1–17. PCI SWBOOT Register Bit Definitions
Bit
Name
Access
7
SWSEL
6
–
–
–
5
–
–
–
4
H_BMODE4
RW
Host boot mode 4 (0)
3
H_BMODE3
RW
Host boot mode 3 (0)
2
H_BMODE2
RW
Host boot mode 2 (1)
1
H_BMODE1
RW
Host boot mode 1 (0)
0
H_BMODE0
RW
Host boot mode 0 (1)
1.8.6.5
RW
Description
Software switch select (0 = DIP switches, 1 = software switches)
PCI DIPOPT Register (BAR2 + 0x10)
The DIPOPT register enables the host software to read the EVM’s onboard
user option DIP switches. Table 1–18 summarizes the function of each bit in
the DIPOPT register.
Table 1–18. PCI DIPOPT Register Bit Definitions
Bit
Name
Access
Description
7
–
–
–
6
S_CLKMODE
R
Switch clock mode (0 = ×4 mode, 1 = ×1 mode)
5
S_CLKSEL
R
Switch clock select (OSC A , OSC B)
4
S_ENDIAN
R
Switch endian control (0 = little endian, 1 = big endian)
3
S_JTAGSEL
R
Switch JTAG selection (0 = external XDS510, 1 = onboard JTAG TBC)
2
S_USER2
R
Switch user-defined option 0 (0 = on, 1 = off)
1
S_USER1
R
Switch user-defined option 1 (0 = on, 1 = off)
0
S_USER0
R
Switch user-defined option 2 (0 = on, 1 = off)
1-54
Programmable Logic
1.8.6.6
PCI DIPBOOT Register (BAR2 + 0x14)
The DIPBOOT register enables the host software to read the EVM’s onboard
boot mode DIP switches. Table 1–19 summarizes the function of each bit in
the DIPBOOT register.
Table 1–19. PCI DIPBOOT Register Bit Definitions
Bit
1.8.6.7
Name
Access
Description
7
–
–
–
6
–
–
–
5
–
–
–
4
S_BMODE4
R
Switch boot mode 4
3
S_BMODE3
R
Switch boot mode 3
2
S_BMODE2
R
Switch boot mode 2
1
S_BMODE4
R
Switch boot mode 1
0
S_BMODE4
R
Switch boot mode 0
PCI DSPOPT Register (BAR2 + 0x18)
The DSPOPT register enables the host software to read the DSP options,
which may either be from the DIP switches or the software switches, depending on which is selected. Table 1–20 summarizes the function of each bit in the
DSPOPT register.
Table 1–20. PCI DSPOPT Register Bit Definitions
Bit
Name
Access
Description
7
–
–
–
6
CLKMODE
R
Clock mode (0 = ×1 mode, 1 = ×4 mode)
5
CLKSEL
R
Clock select (OSC A or OSC B)
4
LENDIAN
R
Endian control (0 = big endian, 1 = little endian)
3
JTAGSEL
R
JTAG selection (0 = external XDS510, 1 = onboard JTAG TBC)
2
USER2
R
User-defined option 0 (0 = on, 1 = off)
1
USER1
R
User-defined option 1 (0 = on, 1 = off)
0
USER0
R
User-defined option 2 (0 = on, 1 = off)
TMS320C6x EVM Hardware
1-55
Programmable Logic
1.8.6.8
PCI DSPBOOT Register (BAR2 + 0x1C)
The DSPBOOT register enables the host software to read the DSP’s boot,
which can either be from the DIP switches or the software switches, depending
on which is selected. Table 1–21 summarizes the function of each bit in the
DSPBOOT register.
Table 1–21. PCI DSPBOOT Register Bit Definitions
Bit
1.8.6.9
Name
Access
Description
7
–
–
–
6
–
–
–
5
–
–
–
4
BMODE4
R
Boot mode 4
3
BMODE3
R
Boot mode 3
2
BMODE2
R
Boot mode 2
1
BMODE1
R
Boot mode 1
0
BMODE0
R
Boot mode 0
PCI CPLDREV Register (BAR2 + 0x20)
The CPLDREV register provides the revision of the EVM’s CPLD. This information may be useful in assisting technical support. The revision number can
be up to eight bits in length. Table 1–22 summarizes the function of each bit
in the CPLDREV register.
Table 1–22. PCI CPLDREV Register Bit Definitions
Bit
1-56
Name
Access
Description
7
CREV7
R
CPLD revision bit 7
6
CREV6
R
CPLD revision bit 6
5
CREV5
R
CPLD revision bit 5
4
CREV4
R
CPLD revision bit 4
3
CREV3
R
CPLD revision bit 3
2
CREV2
R
CPLD revision bit 2
1
CREV1
R
CPLD revision bit 1
0
CREV0
R
CPLD revision bit 0
Programmable Logic
1.8.7
DSP Memory-Mapped Control/Status Registers
The ’C6x EVM’s CPLD provides eight control and status registers that are
memory-mapped into the DSP’s CE1 memory space. All registers are eight
bits wide and are mapped into the least-significant byte of the EMIF data bus
(ED[7:0]). The registers are mapped on DWORD address boundaries for littleendian mode, but, for big-endian mode, the registers are offset by 3 to access
ED[7:0]. The memory-mapped DSP registers provide the DSP software to perform the following functions:
Control the two user-defined LEDs
Control and monitor the daughterboard
Select NMI source and enable
Select McBSP0 connection/power-down codec
Determine the interrupt status
Determine the operating environment
Read the user options DIP switches
Read the selected DSP options
Monitor and control the PCI controller FIFO
Control the two SDRAM banks
Address decoding generates the clock and output enable controls for the registers. Register clock enables are generated whenever the specific register
is being addressed. The rising edge of the EMIF AWE output is used to clock
the lower eight bits of the EMIF data bus into the registers. Data is output on
the lower eight bits of the EMIF data bus when the CPLD register space is read.
This register space is allocated 64K bytes in the CE1 memory space, as shown
in Table 1–3 and Table 1–4. The eight registers are addressed sequentially on
DWORD address boundaries.
The lower eight bits of the EMIF data bus are buffered by an ’LVTH162245
transceiver to provide the peripheral data bus (PDB[7:0]) that is connected to
the CPLD.
Table 1–23 summarizes the eight DSP memory-mapped control and status
registers implemented in the CPLD.
TMS320C6x EVM Hardware
1-57
Address
MAP 1 (MAP 0)
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01780000
(01380000)
CNTL
Control
XCNTL1
RW
0 (inactive)
XCNTL0
RW
0 (inactive)
XRESET
RW
0 (no reset)
NMIEN
RW
0 (disabled)
NMISEL
RW
0 (host)
SP0SEL
RW
0 (DB)
LED1
RW
0 (off)
LED0
RW
0 (off)
01780004
(01380004)
STAT
Status
XSTAT1
R
–
XSTAT0
R
–
DBINT
R
–
DSPNMI
R
–
CODECPD
R
–
CODECIRQ
R
–
PCIINT
R
–
PCIDET
R
–
01780008
(01380008)
DIPOPT
DIP switch –
options
–
–
–
S_CLKMODE
R
–
S_CLKSEL
R
–
S_ENDIAN
R
–
S_JTAGSEL
R
–
S_USER2
R
–
S_USER1
R
–
S_USER0
R
–
0178000C
(013C000C)
DIPBOOT
DIP switch –
boot mode
–
–
–
–
–
–
–
–
–
S_BMODE4
R
–
S_BMODE3
R
–
S_BMODE2
R
–
S_BMODE1
R
–
S_BMODE0
R
–
01780010
(01380010)
DSPOPT
DSP –
options
–
–
–
CLKMODE
R
–
CLKSEL
R
–
ENDIAN
R
–
JTAGSEL
R
–
USER2
R
–
USER1
R
–
USER0
R
–
01780014
(01380014)
DSPBOOT
DSP –
boot mode
SWSEL
R
–
–
–
–
–
–
–
BMODE4
R
–
BMODE3
R
–
BMODE2
R
–
BMODE1
R
–
BMODE0
–
01780018
(01380018
FIFOSTAT
PCI FIFO –
status/control
–
–
–
–
–
–
PCIMRINT
R
–
PCIMWINT
R
–
RDEMPTY
R
–
WRFULL
R
–
PCIMREN
RW
0 (disabled)
PCIMWEN
RW
0 (disabled)
0178001C
(0138001C)
SDCNTL
SDRAM
control
(CE2/CE3)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CE3_SDEN
RW
1 (enable)
CE2_SDEN
RW
1 (enable)
Programmable Logic
1-58
Table 1–23. DSP Memory-Mapped Control/Status CPLD Registers
Programmable Logic
The following subsections describe each of the eight DSP memory-mapped
CPLD registers.
Note:
All register bits are active high (1) for consistency and ease of use. For example, to illuminate LED0, bit 0 of the CNTL register must be set to a 1. Highlighted register values denote the power-up default values.
1.8.7.1
DSP CNTL Register (0x01380000/0x01780000)
The CNTL register enables the DSP software to control the daughterboard,
enable and select the NMI interrupt source, select the McBSP0 connection,
and control the user-defined LEDs. Table 1–24 summarizes the function of
each bit in the CNTL register. Highlighted register values denote the power-up
default values.
Table 1–24. DSP CNTL Register Bit Definitions
Bit
Name
Access Description
7
XCNTL1
RW
Control signal to daughterboard (0 = TTL low, 1 = TTL high)
6
XCNTL0
RW
Control signal to daughterboard (0 = TTL low, 1 = TTL high)
5
XRESET
RW
Daughterboard reset signal (0 = no reset, 1 = asserts active low reset)
4
NMIEN
RW
NMI interrupt enable (0 = disable NMI to DSP, 1 = enable NMI to DSP)
3
NMISEL
RW
NMI interrupt select (0 = PCI NMI register bit, 1 = codec interrupt)
2
SP0SEL
RW
McBSP0 selection (0 = daughterboard, 1 = audio codec)
1
LED1
RW
User-defined LED #1 on top of board (0 = extinguished, 1 = illuminated)
0
LED0
RW
User-defined LED #0 on bracket (0 = extinguished, 1 = illuminated)
TMS320C6x EVM Hardware
1-59
Programmable Logic
1.8.7.2
DSP STAT Register (0x1380004/0x1780004)
The STAT register enables the DSP software to monitor the daughterboard,
interrupts, audio codec status, and PCI detection indicator. Table 1–25 summarizes the function of each bit in the STAT register.
Table 1–25. DSP STAT Register Bit Definitions
Bit
Name
Access
Description
7
XSTAT1
R
Status signal from daughterboard (0 = TTL low, 1 = TTL high)
6
XSTAT0
R
Status signal from daughterboard (0 = TTL low, 1 = TTL high)
5
DBINT
R
Daughterboard interrupt status (0 = no interrupt, 1 = interrupt)
4
DSPNMI
R
DSP NMI interrupt (0 = no NMI, 1 = NMI)
3
CODECPD
R
Codec power-down status (0 = codec active, 1 = codec power down)
2
CODECIRQ
R
Codec interrupt status (0 = no interrupt, 1 = codec interrupt asserted)
1
PCIINT
R
PCI interrupt status (0 = no PCI interrupt, 1 = PCI interrupt asserted)
0
PCIDET
R
PCI detection indicator (0 = external operation, 1 = PCI operation)
1.8.7.3
DSP DIPOPT Register (0x1380008/0x1780008)
The DIPOPT register enables the DSP software to read the DIP switch user
options. Table 1–26 summarizes the function of each bit in the DIPOPT register.
Table 1–26. DSP DIPOPT Register Bit Definitions
Bit
Name
Access
Description
7
–
–
–
6
S_CLKMODE
R
Switch clock mode (0 = ×4 mode, 1 = ×1 mode)
5
S_CLKSEL
R
Switch clock select (OSC A or OSC B)
4
S_ENDIAN
R
Switch endian control (0 = little endian, 1 = big endian)
3
S_JTAGSEL
R
Switch JTAG selection (0 = external XDS510, 1 = onboard JTAG TBC)
2
S_USER2
R
User-defined switch 0 (0 = on, 1 = off)
1
S_USER1
R
User-defined switch 1 (0 = on, 1 = off)
0
S_USER0
R
User-defined switch 2 (0 = on, 1 = off)
1-60
Programmable Logic
1.8.7.4
DSP DIPBOOT Register (0x138000C/0x178000C)
The DIPBOOT register enables the DSP software to read the DIP switch boot
mode selection. Table 1–27 summarizes the function of each bit in the
DIPBOOT register.
Table 1–27. DSP DIPBOOT Register Bit Definitions
Bit
Name
Access
Description
7
–
–
–
6
–
–
–
5
–
–
–
4
S_BMODE4
R
Switch boot mode 4
3
S_BMODE3
R
Switch boot mode 3
2
S_BMODE2
R
Switch boot mode 2
1
S_BMODE1
R
Switch boot mode 1
0
S_BMODE0
R
Switch boot mode 0
1.8.7.5
DSP DSPOPT Register (0x1380010/0x1780010)
The DSPOPT register enables the DSP software to read the actual DSP options. Table 1–28 summarizes the function of each bit in the DSPOPT register.
Table 1–28. DSP DSPOPT Register Bit Definitions
Bit
Name
Access
Description
7
–
–
–
6
CLKMODE
R
Switch clock mode (0 = ×1 mode, 1 = ×4 mode)
5
CLKSEL
–
Switch clock select (OSC A or OSC B)
4
LENDIAN
R
Switch endian control (0 = big endian, 1 = little endian)
3
JTAGSEL
R
Switch JTAG selection (0 = external XDS510, 1 = onboard JTAG TBC)†
2
USER2
R
User-defined switch 2 (0 = on, 1 = off)
1
USER1
R
User-defined switch 1 (0 = on, 1 = off)
0
USER0
R
User-defined switch 0 (0 = on, 1 = off)
† Bit 3 (JTAGSEL) is always 0 when the EVM is not installed in a PCI slot.
TMS320C6x EVM Hardware
1-61
Programmable Logic
1.8.7.6
DSP DSPBOOT Register (0x1380014/0x1780014)
The DSPBOOT register enables the DSP software to read the DSP boot mode
selection. Table 1–29 summarizes the function of each bit in the DSPBOOT
register.
Table 1–29. DSP DSPBOOT Register Bit Definitions
Bit
Name
Access
Description
7
SWSEL
R
Software switch select (0 = DIP switches, 1 = software switches)
6
–
–
–
5
–
–
–
4
BMODE4
R
Boot mode 4
3
BMODE3
R
Boot mode 3
2
BMODE2
R
Boot mode 2
1
BMODE1
R
Boot mode 1
0
BMODE0
R
Boot mode 0
1.8.7.7
DSP FIFOSTAT Register (0x1380018/0x1780018)
The FIFOSTAT register enables the DSP software to determine the FIFOs’
empty/full status and enable PCI bus master external interrupts based on the
FIFOs’ status. Table 1–30 summarizes the function of each bit in the
FIFOSTAT register. Highlighted register values denote the power-up default
values.
Table 1–30. DSP FIFOSTAT Register Bit Definitions
Bit
1-62
Name
Access
Description
7
–
–
–
6
–
–
–
5
PCIMRINT
R
PCI master read interrupt (0 = inactive, 1 = active)
4
PCIMWINT
R
PCI master write interrupt (0 = inactive, 1 = active)
3
RDEMPTY
R
PCI controller read FIFO empty (0 = not empty, 1 = empty)
2
WRFULL
R
PCI controller write FIFO full (0 = not full, 1 = full)
1
PCIMREN
RW
PCI master read enable (0 = disable, 1 = enable)
0
PCIMWEN
RW
PCI master write enable (0 = disable, 1 = enable)
Programmable Logic
1.8.7.8
DSP SDCNTL Register (0x138001C/0x178001C)
The SDCNTL register enables the DSP software to enable and disable the two
banks of SDRAM individually. When an SDRAM bank is disabled, the two associated devices are put into a power-down mode, and the CE memory space
is available for asynchronous expansion memory use. Table 1–31 summarizes the function of each bit in the SDCNTL register. Highlighted register values denote the power-up default values.
Table 1–31. DSP SDCNTL Register Bit Definitions
Bit
1.8.8
Name
Access
Description
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
–
–
–
1
CE3SDEN
RW
CE3 (bank 1) SDRAM enable (0 = disable, 1 = enable)
0
CE2SDEN
RW
CE2 (bank 0) SDRAM enable (0 = disable, 1 = enable)
PCI and DSP Interrupt Control
The CPLD provides interrupt control that allows the host and DSP to interrupt
each other and supports various EVM interrupts related to the daughterboard,
PCI controller, audio codec, and JTAG TBC. The CPLD also controls DSP interrupts that are used to drive PCI bus master transfers.
The host can interrupt the DSP with three different interrupts using the following methods:
Setting the HPI control (HPIC) register DSPINT bit (DSPINT)
Setting the PCI memory-mapped control register DSPNMI bit (NMI)
Accessing a PCI controller mailbox (EXT_INT4)
The HPIC register can be accessed from the host by addressing offset 0 of PCI
BAR3. A host write to this address, with the DSPINT bit set to 1, causes a
DSPINT interrupt to the DSP. The CPLD provides a state machine that manages the data transfers between the PCI controller and the DSP HPI.
TMS320C6x EVM Hardware
1-63
Programmable Logic
The CPLD provides a PCI memory-mapped board control register (CNTL) that
can be accessed by the host at offset 0 of PCI BAR2. When the DSPNMI bit
of this register is set to 1, it causes an NMI interrupt to the DSP if the host is
selected by the DSP software as the NMI interrupt source. The DSP software
can select whether the host or the audio codec sources NMI by setting the
NMIEN and NMISEL bits in the DSP memory-mapped CNTL register provided
by the CPLD.
The host can also interrupt the DSP by writing or reading a PCI controller mailbox register mapped into PCI BAR0. The incoming and outgoing mailbox registers can generate interrupts when they become full or empty. When the selected mailbox register conditions occur, the DSP’s EXT_INT4 interrupt is asserted. The CPLD logic inverts the S5933’s IRQ# active low output signal to
generate a rising-edge EXT_INT4 signal because the DSP defaults to risingedge interrupts.
The DSP can interrupt the host by setting the HPIC register’s HINT bit to 1. This
action forces the DSP’s HINT output signal to be asserted low. The CPLD includes a falling-edge detector that generates a pulse on the S5933’s external
mailbox clock (EMBCLK) input, which causes an interrupt on INTA# to the
host. A second falling-edge detector is used to generate an interrupt to the host
when the TBC interrupt is asserted. The host software can enable HPI and
TBC interrupts via the PCI memory-mapped CNTL register.
Both the host and DSP software can poll interrupt signals by reading PCI and
DSP memory-mapped registers in the CPLD. The host can poll the DSP host
and TBC interrupts. The DSP can poll the daughterboard, host NMI, codec,
and PCI interrupts. The ability to poll interrupt signals from the software, as well
as using them to interrupt execution flow, provides flexibility to the programmer
that may be useful in various applications.
The CPLD includes two state machines that drive PCI bus master read and
write operations based on the status of the PCI controller’s read and write
FIFO flags. The PCI bus master state machines are individually enabled by the
DSP software by setting bits in the DSP memory-mapped FIFOSTAT register
implemented in the CPLD. When the PCIMREN bit is set, the master read state
machine generates EXT_INT5 interrupts to the DSP when the PCI controller’s
read FIFO flag (RDEMPTY) indicates that the read FIFO is not empty. The
DSP can respond to the external interrupt with background DMA transfers or
an interrupt service routine to read data from the PCI controller. The state machine waits for a DSP EMIF read of the FIFO before repeating the process. The
state machine must be disabled at the end of each PCI bus master read block
transfer. The CPLD provides a similar state machine for PCI bus master writes.
When the PCIMWEN bit is set, the master write state machine generates
EXT_INT6 interrupts to the DSP when the PCI controller’s write FIFO
1-64
Programmable Logic
flag (WRFULL) indicates that the write FIFO is not full. Similar to read transfers, the DSP can use background DMA or an interrupt handler to write data
to the PCI controller.
The DSP can be interrupted with four external maskable interrupts and one
nonmaskable interrupt (NMI). All DSP interrupts on the ’C6x EVM are asserted
on rising edges. Table 1–32 summarizes the DSP interrupts on the EVM.
Table 1–32. DSP Interrupts Usage
DSP Interrupt
Description of Use
EXT_INT4
PCI controller interrupts
EXT_INT5
PCI bus master reads DMA synchronization
EXT_INT6
PCI bus master writes DMA synchronization
EXT_INT7
Expansion peripheral interface (XEXT_INT7)
NMI
Host (PCI register) and audio codec (shared via CPLD logic)
EXT_INT4 indicates to the DSP that a significant event has occurred as a result of activity within the PCI controller. This activity may include mailbox full/
empty conditions, end of bus master transfers, a self-test request from the PCI
bus, and transfer errors.
EXT_INT5 and EXT_INT6 are used to synchronize PCI bus master reads and
writes, respectively. They are generated by the CPLD in response to the PCI
controller’s FIFO status. These interrupts are used to trigger the DSP’s DMA
controllers or a CPU interrupt service routine.
EXT_INT7 is provided on the expansion peripheral interface (as XEXT_INT7)
so that a daughterboard can interrupt the DSP to indicate significant events.
The NMI can be asserted by the stereo audio codec’s timer or by the host software via a memory-mapped control register on the PCI bus. The DSP software
can select the NMI source by writing to the memory-mapped control register
in the CPLD. The NMI is handled and driven by the CPLD. The codec’s timer
can be disabled if it is not used. If enabled by the DSP’s software, it could be
used as an additional timer or even a watchdog timer, providing flexibility.
TMS320C6x EVM Hardware
1-65
Programmable Logic
1.8.9
CE1 Memory Decoding/Data Transceivers Control
The CPLD decodes DSP EMIF CE1 memory accesses to control various EVM
hardware and other logic within the CPLD itself.
The EVM uses ’LVTH162245 data transceivers to provide data bus isolation
and voltage translation. These transceivers are enabled by CPLD memory decode logic based on the CE1 memory accesses. DSP EMIF accesses to the
PCI controller’s registers and FIFOs enable the PCI add-on bus transceiver.
DSP EMIF accesses to the audio codec and the CPLD registers enable the
peripheral bus transceiver. DSP EMIF accesses to the 3M-byte expansion
memory space enable the expansion bus transceiver. The direction of these
transceivers is controlled by the DSP’s output enable (AOE) signal, which defines the direction of the data access.
The CPLD provides audio codec chip select and read/write strobes when the
audio codec memory space in CE1 is accessed.
A CPLD state machine, along with combinatorial logic, is used to generate the
asynchronous ready (ARDY) signal to the DSP. Because the EVM includes different types of devices in the CE1 space, there are different timing requirements for each. The CPLD generates the ARDY signal based on the type of
CE1 memory access. For PCI controller accesses, the ARDY signal is not asserted until the add-on bus in available, unless the board is operated standalone. In stand-alone operation, the ARDY signal is always asserted for PCI
controller accesses so that the EMIF does not lock up waiting for ARDY. A state
machine is used to generate the ready indication when the audio codec and
DSP memory-mapped registers in the CPLD are accessed based on a defined
number of CLKOUT2 clock cycles. The external ready from the daughterboard
is presented to the DSP when expansion memory is accessed. The CPLD provides the ready logic that extends the asynchronous strobe time as needed for
each particular access.
The CE2 and CE3 DSP memory spaces default to two banks of 1M × 32-bit
SDRAM. However, if one or both of these banks of SDRAM are not required
for an application, and more or faster asynchronous memory or memorymapped devices are required, CE2 and CE3 can support expansion memory
on a daughterboard. The CE3SDEN and CE2SDEN bits in the CPLD’s
SDCNRL register determine whether the SDRAM banks are enabled or disabled. If a bank is disabled, it is put into a low-power mode and does not
respond to accesses. Additionally, CPLD logic enables external accesses to
asynchronous memory in these spaces by activating the expansion memory
data transceivers.
1-66
Programmable Logic
1.8.10 User Options Control
The EVM provides users options to select the DSP’s input clock source, endian and boot modes, and the JTAG emulation method. The CPLD includes
user options control logic that selects between hardware DIP switch and software switch user options. Table 1–33 summarizes the EVM user options.
Table 1–33. User Options Summary
Number of
Signals
User Option
Description
Boot mode
Selects no-boot, HPI-boot, or ROM-boot
5
Clock mode
Selects multiply-by-1 (no PLL) or multiply-by-4
(PLL) clock mode
1
Clock select
Selects OSC A or OSC B for CLKIN
1
Endian select
Selects big- or little-endian memory addressing
1
JTAG select
Selects internal or external JTAG emulation
1
User-defined
User-defined options
3
The boot mode option selects how the DSP boots upon the release of its reset
input signal. It can begin execution immediately with no boot, or it can be
booted from ROM in the CE1 space or from the host port interface (HPI). The
five control signals select the type of boot, the type of memory located at address 0, and the memory map (MAP 0 or MAP 1) that is to be used.
The clock mode selects whether the CPU clock (CLKOUT1) is the same as
CLKIN (multiply-by-1) or four times CLKIN (multiply-by-4). The ’C6201 provides two pins to select the clock mode. However, both pins have the same
value in each of these modes, so only one control signal needs to be used. The
clock mode pins are both set to 0 for multiply-by-1 mode and 1 for multiply-by-4
mode.
The clock selection determines which of two onboard clock sources is used.
The EVM provides four clock rates: OSC A and OSC A × 1, and OSC B and
OSC B × 4.
The endian selection determines whether the DSP uses little- or big-endian
byte/halfword addressing.
The JTAG selection determines whether the onboard JTAG controller or an external XDS510 emulator is to be used for debugging. When the ’C6x EVM operates outside the PC in stand-alone mode, the JTAG selection is forced by
the CPLD to external XDS510 use.
TMS320C6x EVM Hardware
1-67
Programmable Logic
Three user-defined options are provided for application use. These user options can be read by both the host and the DSP software via CPLD registers.
Because the EVM can operate in both PCI and stand-alone environments, it
must support the selection of user options in both situations. When the EVM
is operated outside the PC, DIP switches are used to configure the board.
When the EVM is in the PC, configuration is done via software switches under
software control to eliminate the need to remove the PC’s cover. This dual-use
option support is transparent because it defaults to the standard DIP switch
control but allows for software switch override, if desired. If software does not
control the configuration from the host side, the EVM uses its default switch
settings. Therefore, in external operation, the DIP switches are used exclusively for user option selections.
Figure 1–11 shows how this dual-use option support is implemented in the
EVM’s CPLD.
The EVM’s CPLD includes a multiplexer that selects between the hardware
DIP switches and PCI-controlled software switches. Upon power up, the CPLD
defaults the configuration to the DIP switch settings, providing transparent operation. Memory-mapped registers on the PCI bus allow the host EVM driver
to configure the board and DSP directly to override the hardware DIP switch
settings, if desired.
Memory-mapped registers in the CPLD allow both the host and DSP software
to observe DIP switches and the current DSP option selections. When the
EVM is under software switch control, the 12 DIP switches can be used by the
DSP software for other purposes.
Based on the selected configuration, the CPLD provides control signals to the
DSP and external hardware for clock and JTAG selection. Transparent DIP
switch configuration is provided upon power up, providing power-up defaults
without the need for software control.
1-68
Programmable Logic
Figure 1–11.Dual-Use Option Support
Selects power-up defaults
and external user options
12-position DIP switch
12
PCI
DIPOPT/DIPBOOT
registers
PCI add-on interface
PCI
SWOPT/SWBOOT
registers
PCI
DSPOPT/DSPBOOT
registers
EPM7256S
CPLD
12
12
DSP
DIPOPT/DIPBOOT
registers
24:12
MUX
12
Select
(Selects between
DIP switches and
software switches)
11
11
DSP
DSPOPT/DSPBOOT
registers
8
Clock
select
logic
2
Output buffers
2
7
1
Clock selects
(’LVT125 output enables)
To ’C6201
(BMODE, CLKMODE, LENDIAN)
JTAG control
(’CBT3257 MUX ctrl)
TMS320C6x EVM Hardware
1-69
Stereo Audio Interface
1.9 Stereo Audio Interface
The ’C6x EVM includes a stereo audio interface that has the following characteristics:
16-bit stereo audio codec with sample rates from 5.5 kHz–48 kHz
Linear (8- and 16-bit) and companded (µ-law and A-law) data formats
Support for stereo electret microphones with voltage bias
Stereo line-level input
Stereo line-level output
Input gain and output attenuation control
Three 3.5-mm (1/8-inch) stereo audio jacks
Figure 1–12 shows the configuration of the ’C6x EVM’s stereo audio interface.
The CS4231A multimedia codec provides a flexible, general-purpose audio
front-end for the EVM. The CS4231A is a 16-bit stereo device. It includes complete on-chip filtering plus analog mixing and programmable gain and attenuation. The device supports 16-bit linear, 8-bit linear, and 8-bit companded (µ-law
and A-law) data formats.
Figure 1–12. TMS320C6x EVM Stereo Audio Interface
Expansion peripheral
interface connector
Mic preamp,
biasing, & filtering
MIC IN
TI TLC2272A
audio op amp
LINE IN
Passive filter/
AC coupling
CS4231A
stereo
audio
codec
7
McBSP0
serial
’CBT3257
data/
voltage
clocks
Xlat/MUX
’C6201/6701
DSP
7
McBSP0
7
(16-bit, 5.5–48 kHz)
LINE OUT
Passive filter/
AC coupling
PDWN
3.5-mm stereo
audio jacks
’LVTH162245
16.9344
MHz
24.576
MHz
Sample rate
crystals
1-70
McBSP0
MUX control
(from CPLD)
8
Parallel control interface
Stereo Audio Interface
The CS4231A supports the following popular sample rates (in kHz):
5.5125
22.0500
6.6150
27.4286
8.0000
32.0000
9.6000
33.0750
11.025
37.8000
16.0000
44.1000
18.9000
48.0000
This wide range of sample rates is compatible with applications ranging from
telecom to pro-audio. The codec uses two crystals with frequencies of
16.9344 MHz and 24.576 MHz as sample clock master sources.
The CS4231A includes a byte-wide parallel control/status interface, which is
compatible with the ’C6201 asynchronous timing that is independent from its
serial data interface to the DSP’s McBSP0. This independent parallel interface, which is memory-mapped into the ’C6201 asynchronous CE1 space, allows the DSP to configure and monitor the codec without impacting the serial
data stream handler. This parallel interface can also be used for capture and
playback data transfers from the DSP or even the host (via the HPI).
The CS4231A audio codec presents four control/status registers mapped into
the DSP’s CE1 memory space starting at address 0x01320000 (MAP 0) or
0x01720000 (MAP 1). These four registers are all eight bits wide. They are addressed by the DSP on 32-bit word boundaries, and only the lower eight bits
are valid. Table 1–34 summarizes the four audio codec registers.
Table 1–34. CS4231A Audio Codec Registers
DSP Address
MAP 1 (MAP 0)
Audio Codec
Register
Description
Access
01720000
(01320000)
R0
Index address register
Read/write
01720004
(01320004)
R1
Indexed data register
Read/write
01720008
(01320008)
R2
Status register
Read/write
0172000C
(01320008)
R3
PIO data register
Read/write
TMS320C6x EVM Hardware
1-71
Stereo Audio Interface
The CS4231A has 32 other registers (I0–I32) that are indirectly accessed by
using the index address register mapped at 0x1320000 or 0x01720000. The
address of the indexed register is written to this register before writing or reading the data register at offset 1.
A benefit of the codec’s control interface being memory-mapped in the DSP’s
CE1 memory space is that the codec can be directly controlled from the PC
host software via the PCI-mapped HPI. This is useful in some user applications
that want to control the codec. For example, a visual control panel application
could present switches and knobs that directly control the operation of the codec in real time, including input gain, output attenuation, input selection, test
loopbacks, and more.
The CS4231A presents a 5-V TTL-compatible interface that is connected to
the DSP through low-cost, TI ’CBT3257 multiplexers on its serial interface, and
a TI ’LVTH162245 transceiver that provides the EVM’s peripheral data bus on
its parallel interface, for voltage translation.
The CS4231A includes multiple inputs that support line and microphone levels. The line input and line output jacks can be used for connecting to a stereo
source such as a compact disc or cassette tape player. The software has independent control over the left and right input selections and their gains. It also
includes a line-level output with DSP software-controllable attenuation.
Three industry-standard 3.5-mm audio jacks are located on the board’s
mounting bracket. The tip of each jack is the left audio channel, and the ring
is the right audio channel. Mono connections only use the left channel.
TI op amps are used for the microphone preamplifier and filtering. A voltage
bias is provided to support the use of battery-powered and electret microphones. Passive filtering is included on the EVM between the codec and the
audio jacks for increased performance. Ferrite beads and bypass capacitors
are used on all audio interfaces to reduce noise coupling. A separate 5-V analog supply is provided by a TI voltage regulator to reduce noise on the audio
signals.
The microphone input is designed for electret microphones that require a bias
voltage. A dynamic microphone can be used if capacitors are used to block the
bias voltage. The maximum allowable signal level to the microphone is
300 mV. The microphone interface provides an external gain of 10 dB and an
additional user-selectable codec gain of 0 dB or 20 dB.
1-72
Stereo Audio Interface
The line input signal level can be a maximum of 6 Vpp (2 Vrms). The line input
signal is attenuated 6 dB before it is presented to the codec. Internal codec
gain from 0 dB–22.5 dB can be selected. The line output signal level can be
a maximum of 3 Vpp (1 Vrms). The line output signal can be muted and
attenuated from 0 dB–94.5 dB. The line output cannot drive low-impedance
headphones or speakers (i.e. 8 or 32 ohm) directly. The line output must be
connected to 10K or greater loads. Table 1–35 summarizes the signal levels
of the input and output audio interfaces.
Table 1–35. Stereo Audio Interface Signal Levels
Audio Interface
Maximum Signal Level
Mic in with codec mic gain enabled (MGE = 1)
100 mVpp (35 mVrms)
Mic in with codec mic gain disabled (MGE = 0)
1 Vpp (350 mVrms)
Line in
6 Vpp (2.1 Vrms)
Line out
2.8 Vpp (1 Vrms)
The CS4231A includes an on-chip 16-bit timer that can be useful to the DSP
to supplement its two timers. The DSP can program a timer interval and the
codec can interrupt the DSP, or the DSP can poll the timers counter register.
The codec can be used as a watchdog timer because it is routed to the CPLD
and can generate the DSP’s nonmaskable interrupt (NMI).
The CS4231A serial interface is connected to the ‘C6201 McBSP0 interface
through a pair of TI ’CBT3257 quad 2:1 multiplexers as shown in Figure 1–13.
This configuration allows the McBSP0 serial port to be connected to either the
onboard audio codec or a daughterboard at any one time depending on your
application. This allows daughterboards to use both of the DSP’s serial ports,
which is useful for many applications that do not require the audio codec. In
addition to providing McBSP0 interface selection, one of the multiplexer outputs directly controls the codec’s power-down input signal that reduces the codec’s current from about 60 mA to 1 mA when the expansion interface is selected. The EVM defaults to the power-down state, and the audio codec’s initialization library function controls a memory-mapped register bit in the CPLD’s
CNTL register to connect the codec to the DSP’s McBSP0 interface. The
CPLD CNTL register’s SP0SEL bit must be set to 1 to activate the audio codec
and allow it to accept configuration information. If the SP0SEL bit is 0, all accesses to the audio codec are ignored, and it always returns a value of 0x80.
TMS320C6x EVM Hardware
1-73
Stereo Audio Interface
Figure 1–13. McBSP0 Selection
Codec
power down
SN74CBT3257
multiplexer
DIN
XDX0
DX0 MUX
DOUT
XDR0
CS4231A
codec
DR0 MUX
DX0
FSYNC
XFSX0
SCLK
XFSR0
FSX0 MUX
DR0
FSX0
FSR0 MUX
FSR0
MCBSP0_SEL
CLKX0
CLKR0
XDX0
XCLKX0
CLKX0 MUX
CLKS0
XDR0
XFSX0 XCLKR0
Peripheral
expansion
connector
XFSR0
XCLKS0
XCLKX0 Pull-up
XCLKR0
XCLKS0
1-74
CLKR0 MUX
CLKS0 MUX
CODEC PD
MUX
SN74CBT3257
multiplexer
Codec
power down
’C6201/6701
DSP
Power Supplies
1.10 Power Supplies
The EVM requires 1.8- or 2.5-V, 3.3-V, and 5-V supplies for its digital circuitry,
as well as 5-V and 12-V supplies for its analog circuitry. An optional daughterboard –12-V supply is brought to the peripheral expansion interface from both
the PCI bus and the external power connector. The digital 5 V and analog 12 V
are obtained from the PCI bus during internal operation or an external power
connector during external operation. The EVM’s PCI connector’s PRSNT1#
and PRSNT2# pins are configured to indicate a maximum of 25 watts power
dissipation. The EVM’s other voltages are provided by onboard switching and
linear voltage regulators that use the PCI or external 5-V and 12-V supplies
as their inputs.
The PCI controller, JTAG TBC, serial EEPROM, oscillators, CPLD core, and
’CBT buffers/multiplexers require the digital 5 V from the PCI bus or external
power connector. The audio codec and op amps require the analog 5 V, which
is derived from the 12 V with a TI TL750L05 5-V regulator. The analog 5 V also
has appropriate filtering and a separate, isolated analog ground plane to ensure a clean supply for the analog circuitry.
1.10.1 3.3-V Voltage Regulator
The DSP’s I/O buffers, SBSRAM, SDRAM, low-voltage buffers/transceivers,
and CPLD I/O buffers require 3.3 V. The 3.3-V supply is provided by an integrated switching regulator (ISR) (part number PT6405B). The PT6405B provides 3.3 V at up to 3 amps. The device’s output voltage defaults to 3.3 V, but
it can be adjusted in the range of 2.8 V–3.8 V by changing external resistors.
The EVM layout supports the ability to adjust the voltage with resistors, but
these are not installed during manufacturing. This surface-mount device is an
efficient (85%) switching regulator that is mounted flat on the board with a
0.38-inch height that is compatible with a PCI slot. This regulator is positioned
on the board so that it does not interfere with the daughterboard interface.
The PT6405B only requires a couple of external capacitors, so its external interface is similar to a linear regulator because it is a module. It therefore provides the advantages of a switching regulator (efficient and runs cool) in a
package that is easy to use, requiring no specialized layout or multiple devices
that are required by a custom switcher design. It has already been carefully
designed for minimal emissions and has been tested.
TMS320C6x EVM Hardware
1-75
Power Supplies
1.10.2 1.8-V/2.5-V Voltage Regulator
The current revision 2.x DSP core requires 2.5 V for its core, and the future
0.18 micron version will require 1.8 V. The PT6502B ISR provides up to 8 A
and is adjustable within a range of 1.3 V–2.6 V with external resistors. When
a change is made to 0.18 micron silicon, the EVM can support the 1.8-V requirement with a simple resistor value change using the PT6502B, or a smaller, PT6407B 3A device can be used since the EVM provides a dual layout for
both device packages. To support the large dynamic current requirements of
the DSP, a 680-µF external capacitor is used at the voltage regulator’s output,
along with a carefully-designed bulk and decoupling capacitor arrangement.
1.10.3 5-V Voltage Regulator
The audio codec and the analog circuitry on the EVM require a clean, 5-V analog power supply for optimal performance. A TI TL750L05 low-dropout, linear
voltage regulator that can provide up to 150 mA is used to provide the analog
5 V.
The TL750L05 requires an input voltage in the range of 6 V–26 V, so the PCI
or external 12 V is used. The audio codec requires a maximum of 60 mA on
the analog 5 V and the filter/buffer op-amps only require a few milliamps.
1.10.4 External Power Connector
The ’C6x EVM’s external power connector is an industry-standard Molex 4-pin
connector that is commonly used in PCs for disk-drive power. The external
power connector is located at the bottom of the board with its pins oriented
downward to prevent connection while the board is installed in the PC. When
the EVM operates outside the PC, the power connection is easily made at the
edge of the board.
The four pins on the connector are used for 5 V, –12 V, GND, and 12 V. The
standard disk-drive power cables do not supply –12 V, so if this is required by
a daughterboard, an appropriate power supply should be used. If –12 V is not
used on the daughterboard, then a standard disk-driver power cable can be
used.
The user-supplied, external power supply should provide the following voltages and currents:
5 VDC at 4A
12 VDC at 500 mA
–12 VDC at 100 mA (if required by a daughterboard)
These are the voltages and their respective currents available to the ’C6x EVM
in a PCI slot.
1-76
Power Supplies
Figure 1–14 shows the orientation of the external power connector pins.
Figure 1–14. External Power Connector
Molex #15–24–4041
Note:
12V
–12V
GND
5V
1
2
3
4
Drawing is not to scale.
1.10.5 Fan Power Connector
The ’C6x EVM includes a small, 2-pin connector to supply 5 V (at 100 mA) to
a low-profile, integrated heat sink/fan that attaches on top of the ’C6201 DSP.
A passive heat sink is unable to dissipate enough heat in a worst case PC environment (50° C, 0 airflow) within the 0.57-inch height constraint of a PCI card.
The integrated heat sink and fan reduces the DSP’s case temperature by
50–80%.
TMS320C6x EVM Hardware
1-77
Voltage Supervision
1.11 Voltage Supervision
The EVM’s dual-voltage supervision and reset generation are provided by a
single voltage supervisor device. The voltage supervisor monitors the 3.3-V
and 1.8- or 2.5-V power supplies, provides manual reset switch debounce, and
generates a clean, 140-ms minimum reset pulse.
Because the 1.8- or 2.5-V and 3.3-V power supplies are derived from the 5-V
power supply, they reach their values after the 5 V, and their status inherently
indicates the status of the 5 V. The board is held in reset until the two voltages
are within specification. Whenever the 3.3-V supply is below 3 V, including during power up, the device forces a reset until the threshold is met. The voltage
supervisor supports the monitoring of a secondary voltage on its power failure
input. A threshold can be set via two external resistors configured as a voltage
divider. Internally, the device triggers at 1.25 V. The resistor divider can set the
external voltage trigger accordingly to support either 1.8 V or 2.5 V during
manufacturing. The EVM is configured for a 2.3-V reset threshold for the 2.5-V
voltage supply. An external resistor is also used to ensure a valid reset output
down to 0 V.
The device also has a manual switch reset input that allows you to manually
reset the DSP. This is important, particularly for the external EVM operation.
The EVM’s CPLD asserts this manual reset input whenever you press the
manual reset pushbutton or a software reset is asserted by the PCI controller.
The voltage supervisor has two reset outputs, with one being active low and
the other being active high. The active low reset is used for CPLD initialization
and board reset control. The active high reset is used directly to control the
SBSRAM ZZ (snooze) input, which puts the SBSRAM in a power-down mode
during reset. This capability is part of the power management features that are
included on the ’C6x EVM.
1-78
Chapter 2
TMS320C6x EVM Host Support Software
This chapter describes the support software for the host that is provided with
the EVM board. This software works on Pentium-based PCs running either
Windows 95 or Windows NT 4.0. The software is installed during the EVM
board software installation operation.
With the provided low-level driver and user mode DLL, a user application on
the host can:
Reset and configure the ’C6x
Load and execute code
Send and receive messages
Send and receive data streams
Access board resources via the HPI
You can use the DLL functions described in section 2.3.2, EVM Win32 DLL API
Functions, to perform all of these operations.
Topic
Page
2.1
Host Support Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
EVM Low-Level Windows Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3
EVM Win32 DLL API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.4
EVM Host Support Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
TMS320C6x EVM Host Support Software
2-1
Host
Host Support
Support Software
Software Components
Components / EVM Low-Level Windows Drivers
2.1
Host Support Software Components
The host support software components consist of an operating-systemspecific low-level driver and a user mode Win32 DLL. The Win32 DLL provides
a consistent API for both Windows 95 and Windows NT 4.0 board access
through the low-level driver. These components are used to create and execute user mode applications for the EVM board. By using the Win32 DLL, you
can write user mode Win32 applications that execute under both operating
systems.
These components, along with user mode host example code, are installed
during the EVM software installation.
2.2 EVM Low-Level Windows Drivers
A low-level driver that is specific to the supported operating system handles
all direct access to the one or more EVM boards in a system. For Windows 95,
a Windows VxD, evm6x.vxd, is the low-level driver that provides access to the
EVM hardware. For Windows NT 4.0, a kernel mode driver, evm6x.sys, provides the EVM hardware access.
All the functionality required for control and communication with the EVM hardware is provided by a Win32 DLL, evm6x.dll, which handles the details of the
low-level driver access. This DLL presents a common Win32 API for both
Windows 95 user applications and Windows NT 4.0 user applications. Thus,
a Win32 user mode application using the Win32 DLL executes under either
operating system.
2-2
EVM Win32 DLL API
2.3
EVM Win32 DLL API
This section describes the EVM Win32 DLL data types and provides summaries, in alphabetical order, of the EVM Win32 DLL API functions.
2.3.1
EVM Win32 DLL API Data Types
Example 2–1 provides definitions for the Win32 DLL API data types.
Example 2–1. Win32 DLL API Data Types
(a) Board types
typedef enum {
TYPE_UNKNOWN = 0,
TYPE_EVM,
TYPE_MCEVM
} EVM6XDLL_BOARD_TYPE, *PEVM6XDLL_BOARD_TYPE;
The EVM6XDLL_BOARD_TYPE type definition defines the possible values
returned by the evm6x_board_type( ) function. A properly functioning EVM
board returns a board type of TYPE_EVM.
(b) Boot modes
typedef enum {
NO_BOOT = 0,
HPI_BOOT,
ROM8_BOOT,
ROM16_BOOT,
ROM32_BOOT,
NO_BOOT_MAP0,
HPI_BOOT_MAP0,
ROM8_BOOT_MAP0,
ROM16_BOOT_MAP0,
ROM32_BOOT_MAP0
} EVM6XDLL_BOOT_MODE, *PEVM6XDLL_BOOT_MODE;
The EVM6XDLL_BOOT_MODE type definition defines the valid values
passed to the evm6x_reset_dsp( ) function. These values support all of the
valid boot modes of the EVM board. The enumerations that do not explicitly
describe a ’C6x memory map use the MAP 1 memory map.
TMS320C6x EVM Host Support Software
2-3
EVM Win32 DLL API
Example 2–1. Win32 DLL API Data Types (Continued)
(c) Clock modes
typedef enum {
DSP_CLOCK_NORMAL = 0,
DSP_CLOCK_SBSRAM,
DSP_CLOCK_BX1,
DSP_CLOCK_AX1
} EVM6XDLL_CLOCK_MODE, *PEVM6XDLL_CLOCK_MODE;
The EVM6XDLL_CLOCK_MODE type definition defines the valid values
passed to the evm6x_set_board_config( ) function to set the board’s clock
configuration.
(d) Endian configuration
typedef enum {
LITTLE_ENDIAN_MODE = 0,
BIG_ENDIAN_MODE
} EVM6XDLL_ENDIAN_MODE, *PEVM6XDLL_ENDIAN_MODE;
The EVM6XDLL_ENDIAN_MODE type definition defines the valid values
passed to the evm6x_set_board_config() function to set the board’s endian
configuration.
(e) Send and retrieve messages
typedef ULONG EVM6XDLL_MESSAGE, *PEVM6XDLL_MESSAGE;
The EVM6XDLL_MESSAGE type definition defines the type used as the
message value passed to and from the EVM board. This type is used in the
evm6x_send_message() and the evm6x_retrieve_message( ) functions.
2-4
EVM Win32 DLL API
2.3.2
EVM Win32 DLL API Functions
The following alphabetical listing includes all of the Win32 DLL API functions.
Use this listing as a table of contents to the Win32 DLL API functions.
Function
Description
Page
evm6x_abort_read
Terminate the current read request
2-6
evm6x_abort_write
Terminate the current write request
2-7
evm6x_board_type
Return EVM board type
2-8
evm6x_clear_message_event
Clear the incoming message event
2-9
evm6x_close
Close a driver connection to a board
2-10
evm6x_coff_display
Display COFF section information
2-11
evm6x_coff_load
Load a COFF image into DSP memory
2-12
evm6x_cpld_read_all
Read the CPLD registers
2-14
evm6x_generate_nmi_int
Generate an NMI to a DSP
2-15
evm6x_hpi_close
Close the HPI for a DSP
2-16
evm6x_hpi_fill
Fill DSP memory using the HPI
2-17
evm6x_hpi_generate_int
Interrupt a DSP using the HPI
2-19
evm6x_hpi_open
Open the HPI for a DSP
2-20
evm6x_hpi_read
Read DSP memory using the HPI
2-21
evm6x_hpi_read_single
Read a single byte, short or long
2-23
evm6x_hpi_write
Write DSP memory using the HPI
2-25
evm6x_hpi_write_single
Write a single byte, short or long
2-26
evm6x_init_emif
Initialize the EMIF registers
2-28
evm6x_nvram_read
Read NVRAM memory on a board
2-29
evm6x_nvram_write
Write NVRAM memory on a board
2-31
evm6x_open
Open a driver connection to a board
2-32
evm6x_read
Read data from a boards PCI interface
2-33
evm6x_reset_board
Completely reset a board
2-35
evm6x_reset_dsp
Reset the DSP on a board and set boot mode
2-36
evm6x_retrieve_message
Get a message sent by a DSP
2-37
evm6x_send_message
Send a message to a DSP
2-39
evm6x_set_board_config
Set the board configuration settings
2-40
evm6x_set_timeout
Set the data transfer time out value
2-42
evm6x_unreset_dsp
Release the DSP from its reset state
2-43
evm6x_write
Write data to a boards PCI interface
2-44
TMS320C6x EVM Host Support Software
2-5
evm6x_abort_read
evm6x_abort_
read
Terminate a Pending Read Transfer
Syntax
#include <evm6xdll.h>
BOOL evm6x_abort_read(HANDLE h_device);
Description
The evm6x_abort_read( ) function terminates a pending read operation for a
target board. This can be used by one thread to terminate the pending read
operation of another thread.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_abort_read( ) function is used to abort a
read operation that has not finished. The evm6x_read call is pending in a separate thread.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/*
. . .
/*
/*
. . .
/*
2-6
Start thread to receive data */
Do something else, then check that receive is */
complete
*/
Abort read operation that is not complete */
if ( !evm6x_abort_read( h_board ) )
{
/* evm6x_abort_read() failed */
}
evm6x_abort_write
evm6x_abort_
write
Terminate a Pending Write Transfer
Syntax
#include <evm6xdll.h>
BOOL evm6x_abort_write(HANDLE h_device);
Description
The evm6x_abort_write( ) function terminates a pending write operation for a
target board. This can be used by one thread to terminate the pending write
operation of another thread.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_abort_write( ) function is used to abort a
write operation that has not finished. The evm6x_write call is pending in a separate thread.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/*
. . .
/*
/*
. . .
/*
Start thread to send data */
Do something else, then check that transfer is */
complete
*/
Abort write operation that is not complete */
if ( !evm6x_abort_write( h_board ) )
{
/* evm6x_abort_write() failed */
}
TMS320C6x EVM Host Support Software
2-7
evm6x_board_type
evm6x_board_
type
Syntax
Description
Retrieve Board Type and Version Information
#include <evm6xdll.h>
BOOL evm6x_board_type(
HANDLE
PEVM6XDLL_BOARD_TYPE
PULONG
h_device,
p_board_type,
p_rev_id);
The evm6x_board_type( ) function retrieves the board type and revision ID information that is stored in the PCI configuration space of the board. The return
value indicates the success of the function call.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The p_board_type and p_rev_id parameters are pointers to the locations
in which to place the requested information. After a successful
evm6x_board_type() function call to an EVM board is made, the location
pointed to by the p_board_type parameter contains the enumerated value
TYPE_EVM. The location pointed to by the p_rev_id parameter contains
the board’s revision ID as retrieved from the board’s PCI configuration
space. The board revision ID is used to indicate EVM board hardware revisions.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_board_type( ) function is used to retrieve
information about the board type of the open board.
#include <windows.h>
#include <stdio.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
EVM6XDLL_BOARD_TYPE
t_board_type;
ULONG
ul_rev_id;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
exit(–1);
}
if ( !evm6x_board_type( h_board, &t_board_type,
&ul_rev_id) )
{
printf( ”ERROR: evm6x_board_type() failed.\n” );
}
2-8
evm6x_clear_message_event
else
{
if ( t_board_type == TYPE_EVM )
{
printf( ”EVM Board, Revision %d.\n”, ul_rev_id );
}
else
{
printf( “Unknown board type.\n” );
}
}
evm6x_clear_
message_event
Clear the Message Event
Syntax
#include <evm6xdll.h>
BOOL evm6x_clear_message_event(HANDLE h_device);
Description
The evm6x_clear_message_event( ) function sets the message event to the
nonsignaled state. Call this function to clear out any previous events before
setting up to receive new events.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_clear_message_event( ) function is used
to clear the message event for an EVM board to the nonsignaled state.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
if ( !evm6x_clear_message_event( h_board ) )
{
/* evm6x_clear_message_event failed */
evm6x_close( h_board );
exit(–1);
}
. . .
TMS320C6x EVM Host Support Software
2-9
evm6x_close
evm6x_close
Close a Driver Connection to a Board
Syntax
#include <evm6xdll.h>
BOOL evm6x_close(HANDLE h_device);
Description
The evm6x_close( ) function closes a previously opened driver connection to
a board. The returned value is TRUE for a successful operation.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_close( ) function is used to close a previously opened driver connection to an EVM board.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
exit(–1);
}
. . .
evm6x_close( h_board );
2-10
evm6x_coff_display
evm6x_coff_
display
Display COFF Information
Syntax
#include <evm6xdll.h>
BOOL evm6x_coff_display(
char
*filename,
clear_bss_flag,
BOOL
BOOL
dump_flag);
Description
The evm6x_coff_display() function outputs COFF file information to stdout.
This information includes details for each section, including name, size, and
flags.
The filename parameter is the filename of the COFF file to be processed.
The clear_bss_flag parameter, if TRUE, causes the bss section to be set
to 0. This is not the default behavior of the DSP debugger.
The dump_flag parameter, if TRUE, causes all of the data being written
to DSP memory to be displayed to stdout. This can be a very large amount
of data.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_coff_display() function is used to display
the section information of a COFF file to stdout.
#include <windows.h>
#include <evm6xdll.h>
. . .
if ( !evm6x_coff_display( ”example.out”, FALSE, FALSE ) )
{
/* COFF display failed */
}
TMS320C6x EVM Host Support Software
2-11
evm6x_coff_load
evm6x_coff_load
Load a COFF Image to a Board Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_coff_load(
HANDLE
h_device,
LPVOID
lp_hpi,
*filename,
char
verbose_flag,
BOOL
clear_bss_flag,
BOOL
BOOL
dump_flag);
Description
The evm6x_coff_load( ) function reads a COFF image and writes the data to
DSP memory using the HPI. This function allows you to load data or executable images from a COFF file to DSP memory.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The lp_hpi parameter is either NULL or the handle returned from a successful evm6x_open_hpi( ) call. If this parameter is NULL, the function
calls evm6x_open_hpi( ) to get its own handle to the HPI then closes it before returning. If the parameter is not NULL, the function uses the provided
handle to the HPI and does not close it before returning. If the HPI is currently open, it cannot be opened again because the HPI supports only one
user at a time.
The filename parameter is the filename of the COFF file to be processed.
The verbose_flag parameter, if TRUE, causes COFF file information to be
sent to stdout during COFF file processing.
The clear_bss_flag parameter, if TRUE, causes the bss section to be set
to 0. This is not the default behavior of the DSP debugger.
The dump_flag parameter, if TRUE, causes all of the data being written
to DSP memory to be displayed to stdout. This can be a very large amount
of data.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
2-12
evm6x_coff_load
Example
In the following example, the evm6x_coff_load( ) function is used to load a
COFF executable to a DSP. The COFF executable is the file example.out, and
the verbose flag is set, which causes COFF section information to be displayed
to stdout during the load operation.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/*––––––––––––––––––––––––––––––––––*
reset DSP into HPI boot mode
configure emif registers
load COFF executable
unreset DSP
*––––––––––––––––––––––––––––––––––*/
evm6x_reset_dsp( h_board, HPI_BOOT );
evm6x_init_emif( h_board, NULL );
if ( !evm6x_coff_load( h_board, NULL, ”example.out”,
TRUE, FALSE, FALSE ) )
{
/* COFF load failed */
}
evm6x_unreset_dsp( h_board );
TMS320C6x EVM Host Support Software
2-13
evm6x_cpld_read_all
evm6x_cpld_
read_all
Return the Contents of the CPLD Registers
Syntax
#include <evm6xdll.h>
BOOL evm6x_cpld_read_all(
HANDLE
h_device,
p_reg_array);
PULONG
Description
The evm6x_cpld_read_all( ) function reads all of the CPLD registers and
stores the values into the ULONG array you provide. The low byte of each
ULONG is the only portion that is significant because the CPLD registers are
only 8 bits wide. This function is for testing and debugging purposes. General
access to the CPLD registers is not required for user programs.
The h_device parameter is the handle returned from a successful
evm6x_open()call.
The p_reg_array parameter is a pointer to the array of ULONGs that are
filled with the CPLD register contents. This array must be at least 9 elements in size to hold all of the CPLD registers of the EVM board.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_cpld_read_all( ) function reads the current state of the CPLD registers.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
ULONG
reg_array[9];
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/* read the CPLD registers */
if ( !evm6x_cpld_read_all( h_board, reg_array ) )
{
/* evm6x_cpld_read_all function failed */
}
2-14
evm6x_generate_nmi_int
evm6x_generate
_nmi_int
Generate an NMI to a DSP
Syntax
#include <evm6xdll.h>
BOOL evm6x_generate_nmi_int(HANDLE h_device);
Description
The evm6x_generate_nmi_int( ) function causes an NMI interrupt to be generated to the DSP. This interrupt can be disabled by the DSP.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_generate_nmi_int( ) function is used to
generate an NMI to the DSP on an EVM board.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/* send a NMI to the DSP */
if ( !evm6x_generate_nmi_int( h_board ) )
{
/* evm6x_generate_nmi_int function failed */
}
TMS320C6x EVM Host Support Software
2-15
evm6x_hpi_close
evm6x_hpi_
close
Close the HPI for a Board
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_close(LPVOID h_hpi_map);
Description
The evm6x_hpi_close( ) function closes an open HPI session that was started
with a successful evm6x_hpi_open( ) call.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_hpi_close( ) function is used to close the
HPI after reading from DSP memory.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_ret_len;
ULONG
ul_buffer[2];
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* read DSP memory (2 words, 32bits each) */
ul_ret_len = 8;
evm6x_hpi_read( h_hpi, ul_buffer, &ul_ret_len,
0x1f0 );
if ( !evm6x_hpi_close( h_hpi ) )
{
/* evm6x_hpi_close failed */
}
2-16
evm6x_hpi_fill
evm6x_hpi_fill
Syntax
Description
Fill DSP Memory Using the HPI
#include <evm6xdll.h>
BOOL evm6x_hpi_fill(
LPVOID
ULONG
PULONG
ULONG
h_hpi_map,
fill_value,
p_length,
dest_addr);
The evm6x_hpi_fill( ) function fills target DSP memory space with a fixed data
value. The HPI is used to access DSP memory from the host.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
The fill_value parameter is the 32-bit data value to be written to DSP
memory space.
The p_length parameter is the address of the write length. The length is
updated with the actual transfer length. The length is the number of bytes
to be transferred but must be a multiple of 4 because all transfers are 32-bit
words.
The dest_addr parameter is the fill starting address in the DSP’s memory
space. The address must be 32-bit word aligned. This address is from the
DSP’s point of view.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_hpi_fill( ) function is used to fill 31 words
(32 bits each) of DSP memory starting with address 0x1f84 with the data pattern 0x1234cdef.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_ret_len;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
TMS320C6x EVM Host Support Software
2-17
evm6x_hpi_fill
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* fill 31 words of DSP memory (32bits each) */
ul_ret_len = 0x7c;
if ( !evm6x_hpi_fill( h_hpi, 0x1234cdef, &ul_ret_len,
0x1f84 ) || (ul_ret_len != 0x7c) )
{
/* evm6x_hpi_fill() failed */
}
evm6x_hpi_close( h_hpi );
2-18
evm6x_hpi_generate_int
evm6x_hpi_
generate_int
Generate an Interrupt to a DSP Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_generate_int(LPVOID h_hpi_map);
Description
The evm6x_hpi_generate_int( ) function causes an HPI interrupt on the target
DSP.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_hpi_generate_int( ) function is used to
generate an interrupt to a DSP using the HPI.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* generate an HPI interrupt */
if ( !evm6x_hpi_generate_int( h_hpi ) )
{
/* evm6x_hpi_generate_int() failed */
}
. . .
TMS320C6x EVM Host Support Software
2-19
evm6x_hpi_open
evm6x_hpi_
open
Open the HPI for a Board
Syntax
#include <evm6xdll.h>
LPVOID evm6x_hpi_open(HANDLE h_device);
Description
The evm6x_hpi_open( ) function establishes a single connection per target
board to the HPI of a target board. After the HPI has been successfully opened,
read and write operations can be performed to DSP memory.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Note:
The various HPI accesses performed to a board’s HPI are protected by a
MUTEX. This prevents multiple operations from interfering with each other.
But, this also means that an operation may not begin immediately if another
HPI operation is in progress. This could cause an HPI interrupt to the DSP
to be delayed.
Return Value
The function returns one of the following values:
Handle
NULL
Example
Handle to be used for HPI access
Attempt to open the HPI failed
In the following example, the evm6x_hpi_open( ) function is used to open a
handle to the HPI on an EVM board. This handle is required for access to DSP
memory through the HPI using the evm6x_hpi_read( ), evm6x_hpi_write( ),
and evm6x_hpi_fill( ) functions.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_ret_len;
ULONG
ul_buffer[2];
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
2-20
evm6x_hpi_read
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* read DSP memory (2 words, 32bits each) */
ul_ret_len = 8;
if ( !evm6x_hpi_read( h_hpi, ul_buffer, &ul_ret_len,
0x1f0 ) ||
(ul_ret_len != 8) )
{
/* evm6x_hpi_read() failed */
}
evm6x_hpi_close( h_hpi );
evm6x_hpi_read
Read DSP Memory Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_read(
h_hpi_map,
LPVOID
p_buffer,
PULONG
PULONG
p_length,
ULONG
src_addr);
Description
The evm6x_hpi_read( ) function transfers data from the target DSP memory
space to host memory. The HPI is used to access DSP memory from the host.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
The p_buffer parameter is the address of the buffer to be filled by the read
operation. This address must be 32-bit word aligned.
The p_length parameter is the address of the read length. The length is
updated with the actual transfer length. The length is the number of bytes
to be transferred but must be a multiple of 4 because all transfers are 32-bit
words.
The src_addr parameter is the transfer starting address in the DSP’s
memory space. The address must be 32-bit word aligned. This address
is from the DSP’s point of view.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
TMS320C6x EVM Host Support Software
2-21
evm6x_hpi_read
Example
In the following example, the evm6x_hpi_read( ) function is used to read two
words (32 bits each) from DSP memory at address 0x1f0.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_ret_len;
ULONG
ul_buffer[2];
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* read DSP memory (2 words, 32bits each) */
ul_ret_len = 8;
if ( !evm6x_hpi_read( h_hpi, ul_buffer, &ul_ret_len,
0x1f0 ) ||
(ul_ret_len != 8) )
{
/* evm6x_hpi_read() failed */
}
evm6x_hpi_close( h_hpi );
2-22
evm6x_hpi_read_single
evm6x_hpi_read
_single
Read a Single Byte, Short or Long, Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_read_single(
LPVOID
h_hpi_map,
p_data,
LPVOID
int
i_size,
ULONG
src_addr);
Description
The evm6x_hpi_read_single( ) function reads a single 8-bit, 16-bit, or 32-bit
value from the target DSP memory space. The HPI is used to access DSP
memory from the host.
Note:
This call reads a 32-bit-aligned value from DSP memory and then returns the
appropriate portion of the 32-bit value based on the address and size of the
request. Reads smaller than 32 bits are not supported. Thus, if a read of all
the bytes of a 32-bit-aligned access will produce undesirable results, do not
use this call.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
The p_data parameter is the address of the location to be filled by the read
operation. This address must be aligned for the size of the HPI access requested.
The i_size parameter is the size of the HPI access in bytes. It can be 1 for
an 8-bit access, 2 for a 16-bit access, or 4 for a 32-bit access.
The src_addr parameter is the address in the DSP’s memory space to be
read. This address must be aligned to the requested access size. This address is from the DSP’s point of view.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
TMS320C6x EVM Host Support Software
2-23
evm6x_hpi_read_single
Example
In the following example, the evm6x_hpi_read_single( ) function reads a byte
(8 bits), a short (16 bits), and a long (32 bits) from DSP memory at addresses
0x800001c3, 0x800001ca, and 0x800001cc.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
UCHAR
uc_temp;
USHORT
us_temp;
ULONG
ul_temp;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* read a byte from DSP memory (8–bits) */
if ( !evm6x_hpi_read_single( h_hpi, &uc_temp, 1,
0x800001c3 ) )
{
/* evm6x_hpi_read_single() failed */
}
/* read a short from DSP memory (16–bits) */
if ( !evm6x_hpi_read_single( h_hpi, &us_temp, 2,
0x800001ca ) )
{
/* evm6x_hpi_read_single() failed */
}
/* read a long from DSP memory (32–bits) */
if ( !evm6x_hpi_read_single( h_hpi, &ul_temp, 4,
0x800001cc ) )
{
/* evm6x_hpi_read_single() failed */
}
evm6x_hpi_close( h_hpi );
2-24
evm6x_hpi_write
evm6x_hpi_write
Write to DSP Memory Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_write(
h_hpi_map,
LPVOID
p_buffer,
PULONG
PULONG
p_length,
dest_addr);
ULONG
Description
The evm6x_hpi_write( ) function transfers data from host memory to the target
DSP memory space. The HPI is used to access DSP memory from the host.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
The p_buffer parameter is the address of the buffer to be transferred by
the write operation. This address must be 32-bit word aligned.
The p_length parameter is the address of the write length. The length is
updated with the actual transfer length. The length is the number of bytes
to be transferred but must be a multiple of 4 because all transfers are 32-bit
words.
The dest_addr parameter is the transfer starting address in the DSP’s
memory space. The address must be 32-bit word aligned. This address
is from the DSP’s point of view.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_hpi_write( ) function is used to write two
words (32 bits each) to DSP memory at address 0x1f0.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_ret_len;
ULONG
ul_buffer[2];
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
TMS320C6x EVM Host Support Software
2-25
evm6x_hpi_write_single
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* write 2 words to DSP memory (32bits each) */
ul_ret_len = 8;
ul_buffer[0] = 0x12345678;
ul_buffer[1] = 0xfedcba98;
if ( !evm6x_hpi_write( h_hpi, ul_buffer, &ul_ret_len,
0x1f0 ) ||
(ul_ret_len != 8) )
{
/* evm6x_hpi_write() failed */
}
evm6x_hpi_close( h_hpi );
evm6x_hpi_write
_single
Write a Single Byte, Short or Long, Using the HPI
Syntax
#include <evm6xdll.h>
BOOL evm6x_hpi_write_single(
LPVOID
h_hpi_map,
ULONG
ul_data,
int
i_size,
ULONG
dest_addr);
Description
The evm6x_hpi_write_single( ) function writes a single 8-bit, 16-bit, or 32-bit
data value to the target DSP memory space. The HPI is used to access DSP
memory from the host.
Note:
Internal program memory does not support byte accesses. Thus, any write
smaller than 32 bits to internal program memory will not modify memory as
expected.
The h_hpi_map parameter is the handle returned from a successful
evm6x_hpi_open() call.
The ul_data parameter contains the value to be written to DSP memory.
The low 8 bits or 16 bits of the value will be used for those size accesses.
The i_size parameter is the size of the HPI access in bytes. It can be 1 for
an 8-bit access, 2 for a 16-bit access, or 4 for a 32-bit access.
The dest_addr parameter is the address in the DSP’s memory space to
be accessed. This address must be aligned to the requested access size.
This address is from the DSP’s point of view.
2-26
evm6x_hpi_write_single
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_hpi_write_single( ) function writes a byte
(8 bits), a short (16 bits), and a long (32 bits) to DSP memory at addresses
0x800001f1, 0x800001f6, and 0x800001e0.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
LPVOID
h_hpi;
ULONG
ul_temp;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
h_hpi = evm6x_hpi_open( h_board );
if ( h_hpi == NULL )
{
/* evm6x_hpi_open() failed */
evm6x_close( h_board );
exit(–1);
}
/* write a byte (8–bits) to DSP memory */
ul_temp = 0x3f;
if ( !evm6x_hpi_write_single( h_hpi, ul_temp, 1,
0x800001f1 ) )
{
/* evm6x_hpi_write_single() failed */
}
/* write a short (16–bits) to DSP memory */
ul_temp = 0xbeef;
if ( !evm6x_hpi_write_single( h_hpi, ul_temp, 2,
0x800001f6 ) )
{
/* evm6x_hpi_write_single() failed */
}
/* write a long (32–bits) to DSP memory */
ul_temp = 0x87654321;
if ( !evm6x_hpi_write_single( h_hpi, ul_temp, 4,
0x800001e0 ) )
{
/* evm6x_hpi_write_single() failed */
}
evm6x_hpi_close( h_hpi );
TMS320C6x EVM Host Support Software
2-27
evm6x_init_emif
evm6x_init_emif
Initialize the EMIF Registers
Syntax
#include <evm6xdll.h>
BOOL evm6x_init_emif(
h_device,
HANDLE
LPVOID
lp_hpi);
Description
The evm6x_init_emif( ) function sets the EMIF registers using HPI accesses
to the DSP memory space. This operation is used in conjunction with HPI boot
mode. Call the evm6x_reset_dsp( ) function to reset the DSP and put it into HPI
boot mode (see page 2-36). Then, before loading code to memory, call the
evm6x_init_emif() function to initialize the EMIF registers so that external
memory on the board is accessible via the HPI.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The lp_hpi parameter is the handle returned from a successful
evm6x_hpi_open() call or NULL if the HPI is not already open. If this parameter is NULL, the HPI is opened for this operation then closed at the
completion of the function. If this parameter is not NULL, the value is used
as the handle for HPI accesses and is not closed at the completion of the
function.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_init_emif( ) function is used to properly
configure the EMIF registers of the DSP for the EVM board. This step must be
done after resetting the DSP and before the DSP tries to access memory on
the EVM board.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
2-28
evm6x_nvram_read
/*––––––––––––––––––––––––––––––––––*
reset DSP into HPI boot mode
configure emif registers
load COFF executable
unreset DSP
*––––––––––––––––––––––––––––––––––*/
evm6x_reset_dsp( h_board, HPI_BOOT );
if ( !evm6x_init_emif( h_board, NULL ) )
{
/* evm6x_init_emit call failed */
}
evm6x_coff_load( h_board, NULL, ”example.out”,
FALSE, FALSE, FALSE );
evm6x_unreset_dsp( h_board );
evm6x_nvram_
read
Read a Byte of NVRAM
Syntax
#include <evm6xdll.h>
BOOL evm6x_nvram_read(
HANDLE
h_device,
USHORT
offset,
PUCHAR
p_data);
Description
The evm6x_nvram_read( ) function reads a byte from a target board’s
NVRAM.
Avoiding Simultaneous NVRAM Accesses
Make sure that NVRAM read and/or write operations do not happen at
the same time from both the host and the DSP. Simultaneous accesses
to NVRAM will result in invalid operations and will possibly corrupt data
stored in NVRAM.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The offset parameter is the NVRAM byte offset to be read.
The p_data parameter is a pointer to the location in which to place the byte
read from NVRAM.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
TMS320C6x EVM Host Support Software
2-29
evm6x_nvram_read
Example
In the following example, the evm6x_nvram_read( ) function is used to read
the byte value stored in NVRAM at offset 0x83.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
UCHAR
c_data;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
if ( !evm6x_nvram_read( h_board, 0x83, &c_data ) )
{
/* evm6x_nvram_read failed */
}
else
{
/* byte read from offset 0x83 is in c_data */
}
2-30
evm6x_nvram_write
evm6x_nvram_
write
Write a Byte to NVRAM
Syntax
#include <evm6xdll.h>
BOOL evm6x_nvram_write(
HANDLE
h_device,
USHORT
offset,
data);
UCHAR
Description
The evm6x_nvram_write( ) function writes a byte to a target board’s NVRAM.
This write operation is not allowed to the lower 0x80 bytes of NVRAM. This
space is used for PCI configuration settings and should not be modified.
Avoiding Simultaneous NVRAM Accesses
Make sure that NVRAM read and/or write operations do not happen at
the same time from both the host and the DSP. Simultaneous accesses
to NVRAM will result in invalid operations and will possibly corrupt data
stored in NVRAM.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The offset parameter is the NVRAM byte offset to be written.
The data parameter is the byte data value to be written to NVRAM.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_nvram_write( ) function is used to write
the byte value 0x3f to NVRAM at offset 0xc3.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
UCHAR
c_data;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
c_data = 0x3f;
if ( !evm6x_nvram_write( h_board, 0xc3, c_data ) )
{
/* evm6x_nvram_write failed */
}
TMS320C6x EVM Host Support Software
2-31
evm6x_open
evm6x_open
Open a Driver Connection to a Board
Syntax
#include <evm6xdll.h>
HANDLE evm6x_open(
int
board_index,
exclusive_flag);
BOOL
Description
The evm6x_open( ) function opens a driver connection to a specific EVM or
McEVM board. The returned handle is used for all further accesses to the target board.
The board_index parameter is a zero-based relative index. Valid index values depend on the number of EVM and McEVM boards in a system and
range from 0 to n–1, where n is the number of boards.
The exclusive_flag parameter indicates an exclusive open request of the
target board. An exclusive open will fail if the target board is currently
open, and additional open requests will fail for a target board that has been
opened exclusively.
Return Value
The function returns one of the following values:
HANDLE
Handle to be used for all further accesses to
the target board
INVALID_HANDLE_VALUE Operation failed
Example
In the following example, the evm6x_open( ) function is used to perform a nonexclusive open of the first EVM board in a system.
#include <windows.h>
#include <evm6xdll.h>
. . .
int
board_index;
HANDLE
h_board;
board_index = 0;
/* select the first (or only) EVM */
/* board
*/
h_board = evm6x_open( board_index, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* board open failed */
exit(–1);
}
. . .
evm6x_close( h_board );
2-32
evm6x_read
evm6x_read
Syntax
Description
Read Data from a Board
#include <evm6xdll.h>
BOOL evm6x_read(
HANDLE
PULONG
PULONG
h_device,
p_buffer,
p_length);
The evm6x_read( ) function transfers data from the DSP to the host using the
PCI bus mastering capability of the board. This transfer can take an indeterminate amount of time, depending on the DSP making data available for the
transfer. To prevent the host from waiting too long for a transfer, a time-out feature is available. Use the evm6x_set_timeout( ) function to set the time-out value (see page 2-42).
Also, a transfer can be terminated at any time using the evm6x_abort_read( )
function (see page 2-6). A transfer that has been timed out or terminated still
returns a success indication, but the length value returned is not the same as
the originally requested transfer length.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The p_buffer parameter is the address of the buffer to be filled by the read
operation. This address must be 32-bit word aligned.
The p_length parameter is the address of the read length. The length is
updated with the actual transfer length. The length is the number of bytes
to be transferred, but must be a multiple of 4 because all transfers are
32-bit words.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
TMS320C6x EVM Host Support Software
2-33
evm6x_read
Example
In the following example, the evm6x_read( ) function is used to transfer
292 bytes (73 words, 32 bits each) from the DSP into host memory using the
PCI FIFO interface provided on the EVM board. The transfer may succeed, but
be incomplete if the transfer timed out or a transfer abort request was initiated
from a separate thread. For additional information, see the evm6x_set_timeout( ) function description on page 2-42 and the evm6x_abort_read( ) function
description on page 2-6.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
ULONG
ul_length;
ULONG
ul_ret_len;
ULONG
ul_buffer[1024];
/*
/*
/*
/*
/*
/*
requested transfer
length in bytes
returned transfer
length in bytes
data buffer, must
be 32bit aligned
*/
*/
*/
*/
*/
*/
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
ul_length = 292;
ul_ret_len = ul_length;
if ( !evm6x_read( h_board, ul_buffer, &ul_ret_len ) )
{
/* evm6x_read failed. */
}
else
{
if ( ul_ret_len != ul_length )
{
/* evm6x_read incomplete */
/* this can be the result of a time out or */
/* an abort
*/
}
}
2-34
evm6x_reset_board
evm6x_reset_
board
Reset a Board
Syntax
#include <evm6xdll.h>
BOOL evm6x_reset_board(HANDLE h_device);
Description
The evm6x_reset_board( ) function causes a hardware reset pulse on the target board. The target board must be opened exclusively using the
evm6x_open() function (see page 2-32) or this function will fail. The return value indicates the success of the function call.
The h_device parameter is the handle returned from a successful exclusive evm6x_open( ) call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_reset_board( ) function is used to reset
the second EVM board in the system. This board was previously opened exclusively.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
/* open the second EVM board exclusively */
h_board = evm6x_open( 1, TRUE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board exclusively */
exit(–1);
}
if ( !evm6x_reset_board( h_board ) )
{
/* reset call failed */
}
else
{
/* reset call succeeded */
}
TMS320C6x EVM Host Support Software
2-35
evm6x_reset_dsp
evm6x_reset_dsp
Reset a DSP
Syntax
#include <evm6xdll.h>
BOOL evm6x_reset_dsp(
h_device,
HANDLE
EVM6XDLL_BOOT_MODE mode);
Description
The evm6x_reset_dsp( ) function sets the boot mode and causes a reset pulse
to only the DSP. If the boot mode is set to HPI boot, the DSP is left in a halted
state. To allow the DSP to begin executing, use the evm6x_unreset_dsp( )
function (see page 2-43). The return value indicates the success of the function call.
- The h_device parameter is the handle returned from a successful
evm6x_open() call.
- The enumerated mode parameter is the boot mode in which to reset the
DSP.
J
HPI_BOOT resets the DSP into HPI boot mode with the MAP 1
memory map.
J
HPI_BOOT_MAP0 resets into HPI boot mode with MAP 0.
J
NO_BOOT selects no boot mode with MAP 1.
J
NO_BOOT_MAP0 selects no boot mode with MAP 0.
J
The various ROMX_BOOT boot modes require that an executable
boot image is present on a daughterboard.
The usual procedure for loading and starting a DSP is:
1) Reset the DSP in HPI boot mode using the evm6x_reset_dsp( ) function.
2) Configure the DSP memory interface with HPI write calls to access the
EMIF registers. This can be accomplished with the evm6x_init_emif( )
function (see page 2-28).
3) Load the DSP program with HPI write calls using the evm6x_coff_load( )
function (see page 2-12).
4) Unreset the DSP from its halted state using the evm6x_unreset_dsp( )
function (see page 2-43).
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
2-36
evm6x_retrieve_message
Example
In the following example, the the evm6x_reset_dsp( ) function is used to place
the DSP into HPI boot mode. While in this state, the DSP accepts HPI accesses. The evm6x_unreset_dsp() function is used to release the DSP from
this state and to begin execution of DSP code. See the evm6x_unreset_dsp( )
function example on page 2-43 for more information.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
if ( !evm6x_reset_dsp(h_board, HPI_BOOT) )
{
/* DSP reset call failed */
}
else
{
/* DSP reset call succeeded */
}
evm6x_retrieve_
message
Syntax
Description
Retrieve a Message from a DSP
#include <evm6xdll.h>
BOOL evm6x_retrieve_message(
HANDLE
PEVM6XDLL_MESSAGE
h_device,
p_message);
The evm6x_retrieve_message( ) function retrieves a mailbox message from
the target DSP. This function returns FALSE if the mailbox to the host from the
DSP is not full.
This is a completely independent mailbox from that used by the
evm6x_send_message() function. Also, the receipt of a message from the
DSP can be detected by a Win32 event. The interrupt caused by an incoming
message signals an event. The name of the event signaled is the string defined
in EVM6X_GLOBAL_MESSAGE_EVENT_BASE_NAME with the board index value appended as a decimal number.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The p_message parameter is a pointer to the location to place the message from the DSP.
TMS320C6x EVM Host Support Software
2-37
evm6x_retrieve_message
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_retrieve_message( ) function is used to
check for and retrieve a 32-bit word sent by the DSP after waiting for the Win32
event signaling a message arrival. If the evm6x_retrieve_message( ) function
fails, then a message has not been sent by the DSP. However, this should not
happen in this example because the routine waits for the event signaling a new
message before retrieving the message.
#include <windows.h>
#include <stdio.h>
#include <evm6xdll.h>
. . .
HANDLE
HANDLE
EVM6XDLL_MESSAGE
int
char
h_board;
h_event;
t_message;
n_board_index;
s_buffer[80];
n_board_index = 1;
h_board = evm6x_open( n_board_index, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/* create event name and open handle to the event */
sprintf( s_buffer, ”%s%d”,
EVM6X_GLOBAL_MESSAGE_EVENT_BASE_NAME,
n_board_index );
h_event = OpenEvent( SYNCHRONIZE, FALSE, s_buffer );
/* wait for event signaling a message from the DSP */
if ( WaitForSingleObject( h_event, INFINITE )
!= WAIT_OBJECT_0 )
{
/* wait for event failed */
}
/* retrieve message sent by DSP */
if ( !evm6x_retrieve_message( h_board, &t_message ) )
{
/* evm6x_retrieve_message() failed */
/* this means that no message is available */
}
else
{
/* the 32bit value sent by the DSP is in t_message */
}
. . .
2-38
evm6x_send_message
evm6x_send_
message
Syntax
Description
Send a Message to a DSP
#include <evm6xdll.h>
BOOL evm6x_send_message(
HANDLE
PEVM6XDLL_MESSAGE
h_device,
p_message);
The evm6x_send_message( ) function sends a mailbox message to the target
DSP. This function returns FALSE if the mailbox from the host to the DSP is
not empty.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The p_message parameter is a pointer to the message to be sent to the
DSP.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_send_message( ) function is used to
send a 32-bit value, 0xfeed002f, to a DSP using the mailbox capability of the
EVM board.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
EVM6XDLL_MESSAGE
h_board;
t_message;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/* send message to DSP */
t_message = 0xfeed002f;
if ( !evm6x_send_message( h_board, &t_message ) )
{
/* evm6x_send_message() failed */
}
. . .
TMS320C6x EVM Host Support Software
2-39
evm6x_set_board_config
evm6x_set_
board_config
Syntax
Description
Set the User Board Options
#include <evm6xdll.h>
BOOL evm6x_set_board_config(
HANDLE
EVM6XDLL_CLOCK_MODE
EVM6XDLL_ENDIAN_MODE
ULONG
h_device,
e_clock_mode,
e_endian_mode,
user_bits );
The evm6x_set_board_config( ) function sets the software configuration for
the board. This includes the clock mode, the endian mode, and the user bits.
This operation is not required if the hardware DIP switch settings are to be
used. If software settings are to be used, this operation must be done before
the DSP is reset using the evm6x_reset_dsp( ) function (see page 2-36).
- The h_device parameter is the handle returned from a successful
evm6x_open() call.
- The e_clock_mode enumerated parameter is one of these values:
J
DSP_CLOCK_SBSRAM configures the DSP to run at the maximum
speed for SBSRAM accesses
J
DSP_CLOCK_NORMAL configures the DSP to run at the normal
clock speed.
J
DSP_CLOCK_AX1 configures the DSP to run at the oscillator A
multiply-by-1 clock speed.
J
DSP_CLOCK_BX1 configures the DSP to run at the oscillator B
multiply-by-1 clock speed.
- The e_endian_mode enumerated parameter is one of these values:
J
LITTLE_ENDIAN_MODE configures the DSP to run in little-endian
mode.
J
BIG_ENDIAN_MODE configures the DSP to run in big-endian mode.
- The user_bits parameter is the value to be used for the three user bits. If
the value is greater than 7, the value is not used. In this case, the hardware
DIP switch setting for the user bits is used.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
2-40
evm6x_set_board_config
Example
In the following example, the evm6x_set_board_config( ) function sets the
EVM board configuration, overriding the hardware DIP switch settings. This
must be done before resetting the DSP. In this example, the clock mode is set
to DSP_CLOCK_SBSRAM mode, which configures the DSP clock to the
speed of the SBSRAM. This allows the DSP to access SBSRAM at one clock
per access. The endian mode is set to BIG_ENDIAN_MODE, which allows the
DSP to execute software compiled and linked to run on a big-endian DSP. The
user bits are set to 0xff. The user bits set on the hardware DIP switch are used
because the user bits value is greater than 7.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/*––––––––––––––––––––––––––––––––––*
set board configuration
reset DSP into HPI boot mode
configure emif registers
load COFF executable
unreset DSP
*––––––––––––––––––––––––––––––––––*/
if ( !evm6x_set_board_config( h_board,
DSP_CLOCK_SBSRAM,
BIG_ENDIAN_MODE, 0xff ) )
{
/* evm6x_set_board_config call failed */
}
evm6x_reset_dsp( h_board, HPI_BOOT );
evm6x_init_emif( h_board, NULL );
evm6x_coff_load( h_board, NULL, ”example.out”,
FALSE, FALSE, FALSE );
evm6x_unreset_dsp( h_board);
TMS320C6x EVM Host Support Software
2-41
evm6x_set_timeout
evm6x_set_
timeout
Set the Transfer Time-Out
Syntax
#include <evm6xdll.h>
BOOL evm6x_set_timeout(
HANDLE h_device,
ULONG timeout);
Description
The evm6x_set_timeout( ) function sets the time-out value for the PCI bus
mastering data transfers. If a transfer exceeds this time-out period, the transfer
is terminated. The transfer return value indicates how much of the data was
transferred.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The timeout parameter is the number of milliseconds to wait before terminating a pending transfer. A value of 0 disables the time-out feature. The
default value at driver startup is 0.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_set_timeout( ) function is used to set the
bus master transfer time-out value to 5000 milliseconds (or 5 seconds). This
means that any transfer that takes longer than 5 seconds will terminate, returning the actual number of bytes transferred during the transfer. A transfer stalls
when data to or from the DSP is not available.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/* set the transfer timeout to 5 seconds */
if ( !evm6x_set_timeout( h_board, 5000 ) )
{
/* evm6x_set_timeout failed */
}
2-42
evm6x_unreset_dsp
evm6x_unreset_
dsp
Unreset a DSP After Using HPI Boot Mode
Syntax
#include <evm6xdll.h>
BOOL evm6x_unreset_dsp(HANDLE h_device);
Description
The evm6x_unreset_dsp( ) function releases the DSP from the halted state invoked by the evm6x_reset_dsp( ) function with the mode parameter set to HPI
boot (see page 2-36). Use this function in conjunction with an
evm6x_reset_dsp() call only. The return value indicates the success of the
function call.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
Example
In the following example, the evm6x_unreset_dsp( ) function is used to release
the DSP from the halted state that results from resetting the DSP into HPI boot
mode.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
/*––––––––––––––––––––––––––––––––––*
reset DSP into HPI boot mode
configure emif registers
load COFF executable
unreset DSP
*––––––––––––––––––––––––––––––––––*/
evm6x_reset_dsp( h_board, HPI_BOOT );
evm6x_init_emif( h_board, NULL);
evm6x_coff_load( h_board, NULL, ”example.out”,
FALSE, FALSE, FALSE );
if ( !evm6x_unreset_dsp( h_board ) )
{
/* DSP unreset call failed */
}
TMS320C6x EVM Host Support Software
2-43
evm6x_write
evm6x_write
Write Data to a Board
Syntax
#include <evm6xdll.h>
BOOL evm6x_write(
HANDLE
h_device,
p_buffer,
PULONG
p_length);
PULONG
Description
The evm6x_write( ) function transfers data from host memory to the DSP using
the PCI bus mastering capability of the board. This transfer can take an indeterminate amount of time, depending on the DSP accepting data for the transfer. To prevent the host from waiting too long for a transfer, a time-out feature
is available. Use the evm6x_set_timeout( ) function to set the time-out value
(see page 2-42).
Also, a transfer can be terminated at any time using the evm6x_abort_write( )
function (see page 2-7). A transfer that has been timed out or terminated still
returns a success indication, but the length value returned is not the same as
the originally requested transfer length.
The h_device parameter is the handle returned from a successful
evm6x_open() call.
The p_buffer parameter is the address of the buffer to be transferred by
the write operation. This address must be 32-bit word aligned.
The p_length parameter is the address of the write length. The length is
updated with the actual transfer length. The length is the number of bytes
to be transferred but must be a multiple of 4 because all transfers are 32-bit
words.
Return Value
The function returns one of the following values:
TRUE Operation succeeded
FALSE Operation failed
2-44
evm6x_write
Example
In the following example, the evm6x_write( ) function is used to send 292 bytes
(73 words, 32 bits each) from host memory to the DSP using the PCI FIFO interface provided on the EVM board. The transfer may succeed, but be incomplete if the transfer timed out or a transfer abort request was initiated from a
separate thread. For additional information, see the evm6x_set_timeout( )
function description on page 2-42 and the evm6x_abort_write( ) function description on page 2-7.
#include <windows.h>
#include <evm6xdll.h>
. . .
HANDLE
h_board;
ULONG
ul_length;
ULONG
ul_ret_len;
ULONG
ul_buffer[1024];
/*
/*
/*
/*
/*
/*
requested transfer
length in bytes
returned transfer
length in bytes
data buffer, must
be 32bit aligned
*/
*/
*/
*/
*/
*/
h_board = evm6x_open( 0, FALSE );
if ( h_board == INVALID_HANDLE_VALUE )
{
/* unable to open board */
exit(–1);
}
. . .
ul_length = 292;
ul_ret_len = ul_length;
if ( !evm6x_write( h_board, ul_buffer, &ul_ret_len ) )
{
/* evm6x_write failed. */
}
else
{
if ( ul_ret_len != ul_length )
{
/* evm6x_write incomplete */
/* this can be the result of a time out or */
/* an abort
*/
}
}
TMS320C6x EVM Host Support Software
2-45
EVM Host Support Software Example
evm6x_write
2.4 EVM Host Support Software Example
The following is a simple program that loads and runs a COFF file in the EVM.
The program illustrates the use of a number of the most basic EVM Win32 DLL
calls.
Example 2–2. EVM Win32 DLL Sample Code
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* FILENAME: HostApp.c –– Host Support Software Example
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
#include <windows.h>
#include ”evm6xdll.h”
void WriteWord2Mem( LPVOID, ULONG, ULONG );
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* main()
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
void main(int argc1, char *argv1[])
{
HANDLE hBd
= NULL; /* Board device handle
short iBd
= 0;
/* Board index
BOOL
bExcl = 1;
/* Exclusive open = TRUE
short iMp
= 0;
/* Map selector = MAP0
EVM6XDLL_BOOT_MODE mode = HPI_BOOT_MAP0;
/* DSP boot mode
LPVOID hHpi
= NULL; /* HPI interface handle
char coffNam[]= ”blink.out”;
/* COFF file name
BOOL bVerbose = 0;
/* COFF load verbose mode = FALSE
BOOL bClr
= 0;
/* Clear bss mode = FALSE
BOOL bDump
= 0;
/* Dump mode = FALSE
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Open a driver connection to a specific [Mc]EVM6x board.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
hBd = evm6x_open( iBd, bExcl );
if ( hBd == INVALID_HANDLE_VALUE ) exit(1);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Cause a hardware reset on the target board.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if ( !evm6x_reset_board(hBd) ) exit(2);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Set the boot mode and cause a DSP reset.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
mode = iMp ? HPI_BOOT : HPI_BOOT_MAP0;
if ( !evm6x_reset_dsp(hBd,mode) ) exit(3);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Establish a connection to the HPI of a target board.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
hHpi = evm6x_hpi_open(hBd);
if ( hHpi == NULL ) exit(4);
2-46
EVM Host Support Software
Example
evm6x_write
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Initialize EMIF registers
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if ( !evm6x_init_emif(hBd, hHpi) ) exit(5);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* set Aux DMA priority higher than CPU
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Due to the default priority of the auxiliary DMA channel used for
*/
/* HPI accesses, the CPU can prevent HPI accesses from completing for
*/
/* an indeterminate amount of time. This can occur when the CPU is
*/
/* very active on the external memory interface, such as while executing*/
/* code from external memory. This condition manifests itself as a
*/
/* hung PCI bus. To prevent this condition, the value 0x10 can be
*/
/* written to the DMA Auxiliary Control Register of the 6201 (at
*/
/* address 0x01840070). This elevates the priority of the auxiliary
*/
/* DMA channel above all other DMA channels and above the CPU.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
WriteWord2Mem( hHpi, 0x01840070 /*Addr*/, 0x00000010 /*Data*/ );
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Read a COFF file and write the data to DSP memory.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if (!evm6x_coff_load(hBd,hHpi,coffNam,bVerbose,bClr,bDump)) exit(8);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Close the HPI session started with evm6x_hpi_open()
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if (!evm6x_hpi_close(hHpi)) exit(9);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Release the DSP from the halted state
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if (!evm6x_unreset_dsp(hBd)) exit(10);
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Close a previously opened driver connection to a board.
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
if (!evm6x_close(hBd)) exit(11);
exit(0);
} /* end of main()
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* Write one word (32 bits) to DSP memory
*/
/*–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
void WriteWord2Mem( LPVOID hHpi, ULONG ulDataAddr, ULONG ulDataWord )
{
ULONG
ulLength;
ULONG
ulReturnedLength;
ulLength = 4;
ulReturnedLength = ulLength;
if ( !evm6x_hpi_write( hHpi, &ulDataWord,
&ulReturnedLength, ulDataAddr) ) exit(6);
if ( ulLength != ulReturnedLength ) exit(7);
}
TMS320C6x EVM Host Support Software
2-47
Chapter 3
TMS320C6x EVM DSP Support Software
This chapter describes the EVM DSP support software by providing application programming interfaces (APIs) and example code for the multichannel
buffered serial port (McBSP) driver, audio codec library, and board support
library. All of these modules use the TMS320C6x peripheral support library to
access and control internal peripheral registers. See the TMS320C6x
Peripheral Support Library Programmer’s Reference for a description of this
library.
Topic
Page
3.1
DSP Support Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Using the DSP Support Software Components . . . . . . . . . . . . . . . . . . 3-3
3.3
McBSP Driver API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.4
Codec Library API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.5
Board Support Library API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3.6
DSP Support Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
TMS320C6x EVM DSP Support Software
3-1
DSP Support Software Components
3.1 DSP Support Software Components
The DSP support software consists of the McBSP driver, the codec library, and
the board support library. The example code provided operates the CS4231A
audio codec in serial data mode, and all audio data is communicated to and
from the ’C6x via the McBSP port 0. Configuration and control of the codec is
achieved via the parallel data interface. These two modules are totally independent of one another in that the codec library makes no calls to the McBSP
driver and vice-versa. It is your responsibility to configure both peripherals for
use and to control them independently. The board support library, on the other
hand, is used by both the McBSP driver and the codec library.
The McBSP provides two types of routines for sending and receiving data. The
synchronous routines mcbsp_sync_send( ) and mcbsp_sync_receive( ) transfer data by polling the data transmit ready (DXR) and data receive ready (DRR)
bits, respectively, to determine when the next word can be written or read.
These routines are referred to as blocking because the CPU is blocked waiting
for the transfer to complete before returning control to the caller. The asynchronous routines mcbsp_async_send( ) and mcbsp_async_receive( ) use the direct memory access (DMA) engine of the ’C6x to transfer the data in the background. User-supplied callback functions are invoked upon completion of the
data transfers to signal the caller. These callback functions are invoked from
an interrupt service routine and may set a global flag, for instance, which would
indicate data is ready to be processed.
The codec library is a collection of routines that configure and control the operation of the CS4231A audio codec. The API functions correspond closely to
the functional organization of the chip. Numerous macros are defined for this
library in the file codec.h. These macros may be used as arguments to the API
functions.
The board support library provides routines for configuring and controlling the
EVM and returning status information to the caller. The module also includes
utility functions such as delay routines.
3-2
Using the DSP Support Software Components
3.2 Using the DSP Support Software Components
The DSP support software, which consists of the McBSP driver, audio codec
library, and board support library, is installed from the accompanying CD-ROM
to the \evm6x\dsp\lib directory. These components are in object format and are
supplied in the archived object library file drv6x.lib. Another file, drv6xe.lib, is
the big-endian version of the archived object library. The source for the DSP
support software is contained in the source library file drv6x.src. To extract the
source files, assuming that you have installed the ’C6x code generation tools,
enter:
ar6x –x drv6x.src
This command extracts the two makefiles in the drv6x.src file. The files
makefile and makefile.big are the little- and big-endian makefile versions, respectively. The first two lines of these files must be modified to point to your
c6xtools directory and to your ’C6x peripheral support library files. See the
TMS320C6x Peripheral Support Library Programmer’s Reference for more information about building this library in the desired mode.
To build the object files from the extracted source (*.c) files, enter one of these
commands:
For little-endian object modules
For big-endian object modules
nmake
nmake –fmakefile.big
To rebuild the object library, enter one of these commands:
nmake drv6x.lib
nmake –fmakefile.big drv6xe.lib
For little-endian object library
For big-endian object library
It is possible to build the file drv6xe.lib with little-endian object files and viceversa, so use caution when building these libraries. Any attempt to use a library
of one endian version with code of another will produce a linker error.
Example code that uses the McBSP driver, audio codec library, and board support library exists in the .\dsp\examples directory. Again, the files makefile and
makefile.big refer to the little- and big-endian makefiles, respectively. The first
two lines of these makefiles must also be modified to point to your c6xtools and
’C6x peripheral support library files. These makefiles also provide an example
of how to include the drv6x.lib file on the linker command line for userdeveloped code. See the TMS320C6x Assembly Language Tools User’s
Guide for more information about using object libraries.
The provided example code configures and uses the audio codec and McBSP
in numerous configurations, such as loopback, block capture and playback,
continuous capture and playback using ping-pong buffering, and continuous
tone generation. You can run the example code via the ’C6x EVM debugger,
or you can load the code and allow it to run using the EVM COFF loader utility
(evm6xldr). The print statements that are visible in the debugger command
window are not visible on the DOS screen when you use the COFF loader.
TMS320C6x EVM DSP Support Software
3-3
McBSP Driver API
3.3 McBSP Driver API
This section discusses the multichannel buffered serial port (McBSP) driver
API. Included in this discussion are the macros, data types, and defined functions that comprise the McBSP driver for the ’C6x EVM board.
3.3.1
McBSP Driver Macros
Table 3–1 lists the macros defined, their values, and a description of each. The
API functions that use each macro are also listed. These macros are defined
within the public header file common.h. The majority of the macros used by the
McBSP driver are defined within the ’C6x device library header file mcbsp.h.
These macros are used as bit and bit field values within registers and correspondingly within elements of the driver data types. See the TMS320C6x Peripheral Support Library Programmer’s Reference and the following section
for further information.
Table 3–1. McBSP Driver API State Macros
Macro
Description
CLOSED
0
Flags McBSP as closed
OPEN
1
Flags McBSP as open and waiting for control
BUSY
2
Flags McBSP as busy
Note:
3-4
Value
These macros are used by all McBSP driver functions.
McBSP Driver API
3.3.2
McBSP Driver Data Types
This section lists the public data types defined by the McBSP driver that are
required for accessing McBSP driver functions.
Example 3–1. McBSP Driver API Data Types
(a) McBSP device handle
typedef
Mcbsp_handle * Mcbsp_dev;
An initialized Mcbsp_handle is required for all subsequent McBSP driver calls. The data structure
Mcbsp_dev is used as a private (global static) structure that records state information for each port.
(b) McBSP callback function
typedef void Callback(Mcbsp_dev
dev,
int
status);
Callback functions are used by mcbsp_async_send( ) and mcbsp_async_receive( ) to indicate
completion of the requested action.
(c) McBSP configuration structure
typedef struct Mcbsp_config_struct
{
unsigned int
Mcbsp_tx_config
Mcbsp_rx_config
Mcbsp_srg_config
loopback;
tx;
rx;
srg;
}
Mcbsp_config;
The Mcbsp_config structure is used when calling the mcbsp_config( ) function. The element loopback
is TRUE or FALSE and is used to control the data loopback mode. The transmitter, receiver, and sample rate generator configuration values are contained in the three structure elements listed in
Example 3–1(d), Example 3–1(e), and Example 3–1(f), respectively.
TMS320C6x EVM DSP Support Software
3-5
McBSP Driver API
Example 3–1. McBSP Driver API Data Types (Continued)
(d) McBSP transmitter configuration structure
typedef struct Mcbsp_tx_config_struct
{
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
char
char
char
char
char
char
char
char
char
char
char
char
char
char
char
update;
interrupt_mode;
clock_polarity;
frame_sync_polarity;
clock_mode;
frame_sync_mode;
phase_mode;
frame_length1;
frame_length2;
word_length1;
word_length2;
companding;
frame_ignore;
data_delay;
dummy[2];
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Update Tx Parameters? T/F
SPCR(2): XRDY,Blk,Frame,SyncErr
PCR(1): Rise or Fall of CLKX
PCR(1): Active High or Low
PCR(1): External or Internal
PCR(1): External or Internal
XCR(1): Single or Dual
XCR(7): 1 to 128 wpf for phase 1
XCR(7):
”
”
phase 2
XCR(3): bits per phase 1 word
XCR(3): bits per phase 2 word
XCR(2): ALAW ULAW or MSB or LSB
XCR(1): T/F
XCR(3): 0–2 Tx data delay
pad bytes to 32 bit align
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
Mcbsp_tx_config;
The Mcbsp_tx_config structure is a substructure of Mcbsp_config and is used to assign register values for the transmitter. The corresponding bits and bit field values are shown to the right of each structure element. See the TMS320C6201/C6701 Peripherals Reference Guide for a detailed discussion
of each value.
3-6
McBSP Driver API
Example 3–1. McBSP Driver API Data Types (Continued)
(e) McBSP receiver configuration structure
typedef struct Mcbsp_rx_config_struct
{
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
char
char
char
char
char
char
char
char
char
char
char
char
char
char
char
char
update;
interrupt_mode;
justification;
clock_polarity;
frame_sync_polarity;
clock_mode;
frame_sync_mode;
phase_mode;
frame_length1;
frame_length2;
word_length1;
word_length2;
companding;
frame_ignore;
data_delay;
dummy;
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Update Rx Parameters? T/F
SPCR(2): RRDY,Blk,Frame,Syncerr
SPCR(2): RJZF, RJSE or LJZF
PCR(1): Rise or Fall of CLKX
PCR(1): Active High or Low
PCR(1): External or Internal
PCR(1): External or Internal
XCR(1): Single or Dual
XCR(7):1 to 128 wpf for phase 1
XCR(7):
”
”
phase 2
XCR(3): bits per phase 1 word
XCR(3): bits per phase 2 word
XCR(2): ALAW ULAW or MSB or LSB
XCR(1): T/F
XCR(3): 0–2 Rx data delay
pad bytes
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
Mcbsp_rx_config;
The Mcbsp_rx_config structure is a substructure of Mcbsp_config and is used to assign register values for the receiver. The corresponding bits and bit field values are shown to the right of each structure
element. See the TMS320C6201/C6701 Peripherals Reference Guide for a detailed discussion of
each value.
(f) McBSP sample rate generator configuration structure
typedef struct Mcbsp_srg_config_struct
{
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
char
char
char
char
char
short
char
char
update;
clock_sync;
clks_polarity;
clks_mode;
frame_sync_mode;
frame_period;
frame_width;
clock_divider;
/*
/*
/*
/*
/*
/*
/*
/*
Update SRGR Parameters? T/F
SRGR(1):GSYNC_OFF or GSYNC_ON
SRGR(1):rising or falling edge
SRGR(1):external or internal
SRGR(1):FSX due to DXR–XSR, FSG
SRGR(12): Frame period 1–4096
SRGR(8): 1 to 256 CLKG periods
SRGR(8): SRGR clock dvdr: 1–256
*/
*/
*/
*/
*/
*/
*/
*/
}
Mcbsp_srg_config;
The Mcbsp_srg_config structure is a substructure of Mcbsp_config and is used to assign register values for the receiver. The corresponding bits and bit field values are shown to the right of each structure
element. See the TMS320C6201/C6701 Peripherals Reference Guide for a detailed discussion of
each value.
TMS320C6x EVM DSP Support Software
3-7
McBSP Driver API
3.3.3
McBSP Driver Functions
The following alphabetical listing includes all of the McBSP driver API functions. Use this listing as a table of contents to the McBSP driver API functions.
Function
Description
Page
mcbsp_async_receive
Receive a buffer of data on the selected McBSP asynchronously
3-9
mcbsp_async_send
Send a buffer of data on the selected McBSP asynchronously
3-11
mcbsp_close
Close the selected McBSP/release the device handle
3-12
mcbsp_config
Configure the selected McBSP
3-13
mcbsp_cont_async_send
Continuously send a buffer of data on the selected McBSP
3-14
mcbsp_drv_init
Initialize the McBSP driver
3-16
mcbsp_open
Open the selected McBSP/obtain a device handle
3-17
mcbsp_reset
Reset the selected McBSP
3-18
mcbsp_stop
Stop operation of the selected McBSP
3-18
mcbsp_sync_receive
Receive a buffer of data on the selected McBSP synchronously
3-19
mcbsp_sync_send
Send a buffer of data on the selected McBSP synchronously
3-20
3-8
mcbsp_async_receive
mcbsp_async_
receive
Syntax
Receive a Buffer of Data on the Selected McBSP Asynchronously
#include <mcbspdrv.h>
int mcbsp_async_receive(
Mcbsp_dev
unsigned char
unsigned int
unsigned int
Mcbsp_dev
Callback
dev,
*p_buffer,
num_bytes,
frame_sync_enable,
frame_sync_dev,
*p_ract);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_async_receive( ) function is used to receive a buffer of data from
the indicated McBSP in an asynchronous (also known as nonblocking) manner. This routine transfers data in the background using an available direct
memory access (DMA) engine. An interrupt service routine is set up by this
routine; once the indicated number of bytes have been transferred, the
BLOCK COND bit in the DMA secondary control register triggers the enabled
DMA interrupt. This interrupt service routine can call a user-supplied callback
function, which could, for example, be used to set a global transfer flag indicating that reception is finished. You do not have access to the interrupt service
routine, only the callback function to which you provide a pointer.
Parameter dev refers to the initialized device handle returned by the
mcbsp_open() call.
The p_buffer parameter is a pointer to the buffer used to hold received
data.
The num_bytes parameter refers to the number of bytes to receive. Typically, the McBSP is configured for 32-bit transfers. In this case, num_bytes
is four times the number of 32-bit elements to receive. You must ensure
that the buffer pointed to by p_buffer is at least as large as num_bytes.
The frame_sync_enable parameter is used to enable the internal frame
sync generator. Valid values are TRUE or FALSE.
The frame_sync_dev parameter indicates which port’s frame sync generator to enable. If frame_sync_enable is FALSE, set frame_sync_dev to
NULL. In most cases, frame_sync_dev is the same as dev.
The p_ract parameter is a pointer to the user-supplied callback function.
See section 3.3.2, McBSP Driver Data Types, for the typedef Callback,
which defines the structure of the callback function.
TMS320C6x EVM DSP Support Software
3-9
mcbsp_async_receive
Return Value
The function returns one of the following values:
OK
ERROR
Example
Transfer setup succeeded
Transfer setup failed
The following code provides an example invocation assuming that the driver
has been initialized and the device has been opened and configured for an external frame sync and 32-bit transfers.
#define NUM_WORDS
128
Callback callback_function(Mcbsp_dev dev, int status)
{
printf(“Data transfer for mcbsp_async_receive() completed
with status = %d\n”,status);
return;
}
int
status;
unsigned int buffer[NUM_WORDS];
status= mcbsp_async_receive( dev0,
buffer,
NUM_WORDS * sizeof(int),
FALSE,
NULL,
callback_function
);
if (status == ERROR)
{
printf(“Error setting up data transfer with
mcbsp_sync_receive()\n”);
return(ERROR);
}
3-10
mcbsp_async_send
mcbsp_async_
send
Syntax
Send a Buffer of Data on the Selected McBSP Asynchronously
#include <mcbspdrv.h>
int mcbsp_async_send(
Mcbsp_dev
unsigned char
unsigned int
unsigned int
Mcbsp_dev
Callback
dev,
*p_buffer,
num_bytes,
frame_sync_enable,
frame_sync_dev,
*p_wact);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_async_send( ) function is used to send a buffer of data from the
indicated McBSP in an asynchronous (also known as nonblocking) manner.
This routine transfers data in the background using an available DMA engine.
An interrupt service routine is set up by this routine; once the indicated number
of bytes have been transferred, the BLOCK COND bit in the DMA secondary
control register triggers the enabled DMA interrupt. This interrupt service routine can call a user-supplied callback function, which could, for example, be
used to set a global transfer flag indicating that transmission is finished. You
do not have access to the interrupt service routine, only the callback function
to which you provide a pointer.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
The p_buffer parameter is a pointer to the buffer used to hold data to be
transmitted.
The num_bytes parameter refers to the number of bytes to send. Typically,
the McBSP is configured for 32-bit transfers. In this case, num_bytes is
four times the number of 32-bit elements to receive.
The frame_sync_enable parameter is used to enable the internal frame
sync generator. Valid values are TRUE or FALSE.
The frame_sync_dev parameter indicates which port’s frame sync generator to enable. If frame_sync_enable is FALSE, set frame_sync_dev to
NULL. In most cases, frame_sync_dev is the same as dev.
The p_wact parameter is a pointer to the user-supplied callback function.
See section 3.3.2, McBSP Driver Data Types, for the typedef Callback,
which defines the structure of the callback function.
TMS320C6x EVM DSP Support Software
3-11
mcbsp_close
Return Value
The function returns one of the following values:
OK
ERROR
Example
Transfer setup succeeded
Transfer setup failed
The following code provides an example invocation assuming that the driver
has been initialized and the device has been opened and configured for an internal frame sync and 32-bit transfers.
#define NUM_WORDS
128
Callback callback_function(Mcbsp_dev dev, int status)
{
printf(“Data transfer for mcbsp_async_send() completed
with status = %d\n”,status);
return;
}
int
status;
unsigned int buffer[NUM_WORDS];
status= mcbsp_async_send(dev0,
buffer,
NUM_WORDS * sizeof(int),
TRUE,
dev0,
callback_function
);
if (status == ERROR)
{
printf(“Error setting up data transfer with \
mcbsp_sync_send()\n”);
return(ERROR);
}
mcbsp_close
Close the Selected McBSP/Release the Device Handle
Syntax
#include <mcbspdrv.h>
void mcbsp_close(Mcbsp_dev dev);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_close( ) function closes the selected McBSP and releases its associated device handle structure.
The dev parameter is the device handle that was initialized by the
mcbsp_open() call.
Return Value
None
Example
The code in this example closes the McBSP associated with dev, allowing
another routine or thread to control its operation.
mcbsp_close(dev);
3-12
mcbsp_config
mcbsp_config
Syntax
Configure the Selected McBSP
#include <mcbspdrv.h>
int mcbsp_config(
Mcbsp_dev
Mcbsp_config
dev,
*p_mcbsp_config);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_config( ) function configures the selected McBSP. Configuration
values are passed to this routine via the Mcbsp_config structure (see section
3.3.2, McBSP Driver Data Types, for the definition of this structure). The macro
defines for the configuration structure elements are defined in the file mcbsp.h,
which is part of the ’C6x device library.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
The p_mcbsp_config parameter is a pointer to a user-initialized McBSP
configuration structure.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Configuration values are within range of their respective min/
max values.
Configuration values were greater than or less than their respective min/max values.
The code in this example configures the transmitter, receiver, and sample rate
generator for the McBSP associated with the initialized device handle dev for
use in internal loopback mode. Defines shown in this example are part of the
’C6x peripheral control library.
config.loopback
=
config.tx.update
=
config.tx.clock_polarity
=
config.tx.frame_sync_polarity=
config.tx.clock_mode
=
config.tx.frame_sync_mode
=
config.tx.phase_mode
=
config.tx.frame_length1
=
config.tx.word_length1
=
config.tx.frame_ignore
=
config.tx.data_delay
=
config.rx.update
=
config.rx.clock_polarity
=
config.rx.frame_sync_polarity=
config.rx.clock_mode
=
config.rx.frame_sync_mode
=
TRUE;
TRUE;
CLKX_POL_RISING;
FSYNC_POL_HIGH;
CLK_MODE_INT;
FSYNC_MODE_INT;
SINGLE_PHASE;
0;
WORD_LENGTH_32;
NO_FRAME_IGNORE;
DATA_DELAY1;
TRUE;
CLKR_POL_FALLING;
FSYNC_POL_HIGH;
CLK_MODE_EXT;
FSYNC_MODE_EXT;
TMS320C6x EVM DSP Support Software
3-13
mcbsp_cont_async_send
config.rx.phase_mode
= SINGLE_PHASE;
config.rx.frame_length1
= 0;
config.rx.word_length1
= WORD_LENGTH_32;
config.rx.frame_ignore
= NO_FRAME_IGNORE;
config.rx.data_delay
= DATA_DELAY1;
config.srg.update
= TRUE;
config.srg.clks_mode
= CLK_MODE_INT;
config.srg.frame_sync_mode
= FSX_DXR_TO_XSR;
config.srg.frame_width
= 1;
config.srg.clock_divider
= 0xff;
if (mcbsp_config(dev0,&config))
{
printf(”Error returned from mcbsp_config() for dev0”);
mcbsp_close(dev0);
return(ERROR);
}
mcbsp_cont_
async_send
Continuously Send a Buffer of Data on the Selected McBSP
Syntax
#include <mcbspdrv.h>
int mcbsp_cont_async_send(
dev,
Mcbsp_dev
unsigned char
*p_ping_buff,
unsigned char
*p_pong_buff,
unsigned int
num_bytes,
frame_sync_enable,
unsigned int
Mcbsp_dev
frame_sync_dev,
Callback
*p_wact);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_cont_async_send( ) function is used to repeatedly send either a
single buffer or a ping-pong type buffer in an asynchronous (also known as
nonblocking) manner. This routine transfers data in the background using an
available DMA engine. An interrupt service routine is set up by this routine;
once the indicated number of bytes have been transferred, the BLOCK COND
bit in the DMA secondary control register triggers the enabled DMA interrupt.
This interrupt service routine can call a user-supplied callback function, which
could, for example, be used to set a global transfer flag indicating another
transmission is finished. You do not have access to the interrupt service routine, only the callback function to which you provide a pointer.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
The p_ping_buffer parameter is a pointer to the buffer used to hold data
to be transmitted.
3-14
mcbsp_cont_async_send
The p_pong_buffer parameter is a pointer to the secondary transmit buffer. If this parameter is NULL, the data in p_ping_buffer is continuously
sent. If this parameter is valid, then data transmission ping-pongs between
these two buffers.
The num_bytes parameter refers to the number of bytes to send (same for
each buffer). Typically, the McBSP is configured for 32-bit transfers. In this
case, num_bytes is four times the number of 32-bit elements to receive.
The frame_sync_enable parameter is used to enable the internal frame
sync generator. Valid values are TRUE or FALSE.
The frame_sync_dev parameter indicates which port’s frame sync generator to enable. If frame_sync_enable is FALSE, set frame_sync_dev to
NULL. In most cases, frame_sync_dev is the same as dev.
The p_wact parameter is a pointer to the user-supplied callback function.
See section 3.3.2, McBSP Driver Data Types, for the typedef Callback,
which defines the structure of the callback function.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Transfer setup succeeded
Transfer setup failed
The following code provides an example invocation assuming that the driver
has been initialized and the device has been opened and configured for an internal frame sync and 32-bit transfers. This code continuously sends 16 buffers of data, eight from the ping_buff[ ] and eight from the pong_buff[ ]. To turn
off continuous operation, the callback function must set dev–>tx_dma.continuous to FALSE one block before transmission should stop.
#define NUM_WORDS
#define NUM_BUFFS
int
Callback
128
16
num_buffs_sent=
0;
callback_function(
Mcbsp_dev dev,
int
status)
{
printf(“Data transfer for mcbsp_async_send() completed
with\ status = %d\n”,status);
num_buffs_sent++;
if (num_buffs_sent == NUM_BUFFS)
mcbsp_stop(dev);
return;
}
int
status;
unsigned int ping_buff[NUM_WORDS];
unsigned int pong_buff[NUM_WORDS];
TMS320C6x EVM DSP Support Software
3-15
mcbsp_drv_init
for (i=0;i<NUM_WORDS;i++)
ping_buff[i] = i;
/* create a ramp */
for (i=0;i<NUM_WORDS;i++)
pong_buff[i] = i;
/* create a ramp */
status= mcbsp_cont_async_send( dev0,
ping_buff,
pong_buff,
NUM_WORDS * sizeof(int),
TRUE,
dev0,
callback_function
);
if (status == ERROR)
{
printf(“Error setting up data transfer with \
mcbsp_sync_send()\n”);
return(ERROR);
}
mcbsp_drv_
init
Initialize the McBSP Driver
Syntax
#include <mcbspdrv.h>
int mcbsp_drv_init(void);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_drv_init( ) function initializes the McBSP driver for use and must
be called before any other driver calls. This function allocates memory for the
port 0 and port 1 device handles and initializes structure elements to their default values.
Return Value
The function returns one of the following values:
OK
ERROR
Memory allocation succeeded
Memory allocation failed
Subsequent calls to this function simply return OK.
Example
The code in this example initializes the McBSP driver for use and is called before any other McBSP routines.
int status;
status = mcbsp_drv_init();
if (status == ERROR)
{
printf(“Error initializing the McBSP driver\n”);
return(ERROR);
}
3-16
mcbsp_open
mcbsp_open
Open the Selected McBSP/Obtain a Device Handle
Syntax
#include <mcbspdrv.h>
Mcbsp_dev mcbsp_open(int port);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_open( ) function opens the selected McBSP for use. All subsequent driver calls require an initialized Mcbsp_dev argument.
The port parameter indicates which serial port to open, with valid values
of 0 or 1.
Return Value
The function returns one of the following values:
Mcbsp_dev A valid device handle value is returned if the indicated port is
not already in use.
NULL
The indicated port is already in use.
Example
The code in this example obtains a device handle for the McBSP port 0. This
device handle is required in subsequent McBSP calls, such as mcbsp_config( )
and mcbsp_async_receive( ).
Mcbsp_dev dev0;
dev0 = mcbsp_open(0);
if (dev0 == NULL)
{
printf(“Unable to obtain a device handle for McBSP 0.”);
return(ERROR);
}
TMS320C6x EVM DSP Support Software
3-17
mcbsp_reset
mcbsp_reset
Reset the Selected McBSP
Syntax
#include <mcbspdrv.h>
void mcbsp_reset(Mcbsp_dev dev);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_reset( ) function simply resets the selected McBSP associated
with dev to its default state.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
Return Value
None
Example
The code in this example resets the associated McBSP to its default state.
mcbsp_reset(dev);
mcbsp_stop
Stop Operation of the Selected McBSP
Syntax
#include <mcbspdrv.h>
void mcbsp_stop(Mcbsp_dev dev);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_stop( ) function completely disables the selected McBSP. Both the
transmit and receive sections are disabled, as well as the sample rate and
frame sync generators.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
Return Value
None
Example
The code in this example disables the selected McBSP.
mcbsp_stop(dev);
3-18
mcbsp_sync_receive
mcbsp_sync_
receive
Syntax
Receive a Buffer of Data on the Selected McBSP Synchronously
#include <mcbspdrv.h>
int mcbsp_sync_receive(
Mcbsp_dev
unsigned char
unsigned int
unsigned int
Mcbsp_dev
int
dev,
*p_buffer,
num_bytes,
frame_sync_enable,
frame_sync_dev,
pack_data);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_sync_receive( ) function is used to receive a buffer of data from the
indicated McBSP in a synchronous (also known as blocking) manner. During
data reception, the CPU is busy polling the data receive ready (DRR) flag in
the serial port control register to determine when the next data word is available. Once the indicated number of bytes have been transferred to the buffer,
this routine returns to the caller.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
The p_buffer parameter is a pointer to the buffer used to hold received
data.
The num_bytes parameter refers to the number of bytes to receive. Typically, the McBSP is configured for 32-bit transfers. In this case, num_bytes
is four times the number of 32-bit elements to receive. You must ensure
that the buffer pointed to by p_buffer is at least as large as num_bytes.
The frame_sync_enable parameter is used to enable the internal frame
sync generator. Valid values are TRUE or FALSE.
The frame_sync_dev parameter indicates which port’s frame sync generator to enable. If frame_sync_enable is FALSE, set frame_sync_dev to
NULL. In most cases, frame_sync_dev is the same as dev.
Parameter pack_data can be used to pack received elements that are less
than 32 bits into p_buffer. Valid values for pack_data are TRUE or FALSE.
The pack_data feature can only be used when the serial port is configured
for single-phase transfers.
Return Value
The function returns one of the following values:
OK
ERROR
Transfer succeeded
Transfer failed
TMS320C6x EVM DSP Support Software
3-19
mcbsp_sync_send
Example
The following code provides an example invocation assuming that the driver
has been initialized and the device has been opened and configured for an external frame sync and 32-bit transfers.
#define NUM_WORDS
128
int
status;
unsigned int buffer[NUM_WORDS];
status= mcbsp_sync_receive(
dev0,
buffer,
NUM_WORDS * sizeof(int),
FALSE,
NULL,
FALSE);
if (status == ERROR)
{
printf(“Error receiving data with mcbsp_sync_receive()\n”);
return(ERROR);
}
mcbsp_sync_
send
Syntax
Send a Buffer of Data on the Selected McBSP Synchronously
#include <mcbspdrv.h>
int mcbsp_sync_send(
Mcbsp_dev
unsigned char
unsigned int
unsigned int
Mcbsp_dev
int
dev,
*p_buffer,
num_bytes,
frame_sync_enable,
frame_sync_dev,
packed_data);
Defined in
mcbspdrv.c as a callable C routine
Description
The mcbsp_sync_send( ) function sends a buffer of data across the indicated
McBSP in a synchronous (also known as blocking) manner. During data transmission, the CPU is busy polling the data transmit ready (DXR) flag in the serial
port control register to determine when the next element can be written. Once
the indicated number of bytes have been transferred from the buffer, this routine returns to the caller.
The dev parameter refers to the initialized device handle returned by the
mcbsp_open() call.
The p_buffer parameter is a pointer to the buffer initialized with the data
to send.
3-20
mcbsp_sync_send
The num_bytes parameter refers to the number of bytes to send. Typically,
the McBSP is configured for 32-bit transfers. In this case, num_bytes is
four times the number of 32-bit elements to send.
The frame_sync_enable parameter is used to enable the internal frame
sync generator. Valid values are TRUE or FALSE.
The frame_sync_dev parameter indicates which port’s frame sync generator to enable. If frame_sync_enable is FALSE, set frame_sync_dev to
NULL. In most cases, frame_sync_dev is the same as dev.
The packed_data parameter, if TRUE, indicates that the data in p_buffer
is packed. For element transfers of less than 32 bits, this routine sends
only the significant bits for each transfer, sign extended and justified as indicated in the mcbsp_config( ) call (see page 3-13).
Return Value
The function returns one of the following values:
OK
ERROR
Example
Transfer succeeded
Transfer failed
The following code provides an example invocation assuming that the driver
has been initialized and the device has been opened and configured for an internal frame sync (FSG) and 32-bit transfers.
#define NUM_WORDS
128
int
status;
unsigned int buffer[NUM_WORDS];
for (i=0;i<NUM_WORDS;i++)
buffer[i]= i;
/* generate ramp */
status= mcbsp_sync_send( dev0,
buffer,
NUM_WORDS * sizeof(int),
TRUE,
dev0,
FALSE);
if (status == ERROR)
{
printf(“Error sending data with mcbsp_sync_send()\n”);
return(ERROR);
}
TMS320C6x EVM DSP Support Software
3-21
Codec Library API
3.4 Codec Library API
This section discusses the audio codec library API. Included in this discussion
are the macros and defined functions that comprise the audio codec library for
the ’C6x EVM board.
3.4.1
Codec Library Macros
Table 9–2 lists the macros defined, their values, and a description of each. The
API functions that use each set of macros are also listed. These macros are
defined within the public header file codec.h.
Table 3–2. Codec Library API Macros
(a) Mode selection macros
Macro
Value
Description
CAPTURE
1
Selects capture mode for control
PLAYBACK
2
Selects playback mode for control
BOTH
3
Applies arguments to both capture and playback modes
Note:
These macros are used by the function codec_audio_data_format( ).
(b) Left/right channel selection macros
Macro
Value
LEFT
1
Selects left channel for control
RIGHT
2
Selects right channel for control
Note:
Description
These macros are used by the following functions:
codec_adc_control( )
codec_line_in_control()
codec_aux_control( )
codec_dac_control( )
(c) Auxiliary port selection macros
Macro
Value
CHAN1
1
Selects auxiliary port 1 for control
CHAN2
2
Selects auxiliary port 2 for control
Note:
3-22
Description
These macros are used by the function codec_aux_control( ).
Codec Library API
Table 3–2. Codec Library API Macros (Continued)
(d) Analog-to-digital converter (ADC) input gain macros
Macro
Value
Description
MIN_ADC_INPUT_GAIN
0.0
Minimum gain setting in dB for left and
right input ADCs
MAX_ADC_INPUT_GAIN
22.5
Maximum gain setting in dB for left and
right input ADCs
ADC_INPUT_GAIN_STEP
1.5
Gain setting resolution for left and right input ADCs
Note:
These macros are used by the function codec_adc_control( ).
(e) Auxiliary and line mixer gain macros
Macro
Value
Description
MIN_AUX_LINE_GAIN
–34.5
Minimum gain setting in dB for AUX1,
AUX2, and LINE mixer gain
MAX_AUX_LINE_GAIN
12.0
Maximum gain setting in dB for AUX1,
AUX2, and LINE mixer gain
AUX_LINE_GAIN_STEP
1.5
Gain setting resolution for AUX1, AUX2,
and LINE mixers
Note:
These macros are used by the following functions:
codec_line_in_control()
codec_aux_control( )
(f) Digital-to-analog converter (DAC) and loopback attenuation macros
Macro
Value
Description
MIN_DAC_LBACK_ATTEN
0.0
Minimum attenuation setting in dB for left
and right DACs and left and right loopback attenuators
MIN_DAC_LBACK_ATTEN
94.5
Maximum attenuation setting in dB for left
and right DACs and left and right loopback attenuators
DAC_LBACK_ATTEN_STEP
1.5
Attenuation setting resolution for DACs
and loopback attenuators
Note:
These macros are used by the following functions:
codec_dac_control( )
codec_loopback_enable()
TMS320C6x EVM DSP Support Software
3-23
Codec Library API
Table 3–2. Codec Library API Macros (Continued)
(g) ADC input selector macros
Macro
Value
Description
LINE_SEL
0
Selects LINE input as source for left or
right ADC
AUX1_SEL
1
Selects AUX1 input as source for left or
right ADC
MIC_SEL
2
Selects MIC input as source for left or
right ADC
LINE_OUT_LBACK_SEL
3
Selects LINE OUT as source for left or
right ADC
Note:
These macros are used by the function codec_adc_control( ).
(h) Capture and playback audio data format macros
Macro
Description
LINEAR_8BIT_UNSIGNED
0
Selects linear, 8-bit unsigned data format
ULAW_8BIT_COMPANDED
1
Selects µ-Law, 8-bit companded format
LINEAR_16BIT_SIGNED_LE
2
Selects linear, 16-bit signed little-endian
data format
ALAW_8BIT_COMPANDED
3
Selects A-Law, 8-bit companded format
RSVD_FORMAT
4
Reserved data format designator
ADPCM_4BIT_IMA
5
Selects ADPCM, 4-bit, IMA-compatible
data format
LINEAR_16BIT_SIGNED_BE
6
Selects linear, 16-bit signed big-endian
data format
Note:
3-24
Value
These macros are used by the function codec_audio_data_format( )
Codec Library API
Table 3–2. Codec Library API Macros (Continued)
(i) Calibration mode macros
Macro
Value
Description
NO_CAL
0
No calibration is performed after resetting
the MCE bit
CONVERTER_CAL
1
Calibrates only ADCs and DACs
DAC_CAL
2
Calibrates only the DAC interpolation filters
FULL_CAL
3
Calibrates all offsets, ADCs, DACs, and
analog mixers
Note:
These macros are used by the function codec_calibrate( ).
(j) Serial data format macros
Macro
Value
Description
SERIAL_64BIT_ENHANCED
0
Selects 64-bit enhanced serial audio data
format; contains status information
SERIAL_64BIT
1
Selects 64-bit serial audio data format;
does not contain status information
SERIAL_32BIT
2
Selects 32-bit serial audio data format;
does not contain status information
Note:
These macros are used by the function codec_serial_port_enable( ).
TMS320C6x EVM DSP Support Software
3-25
Codec Library API
3.4.2
Codec Library API Functions
The following alphabetical listing includes all of the codec library API functions.
Use this listing as a table of contents to the codec library API functions.
Function
Description
Page
codec_adc_control
Control input analog-to-digital converters
3-27
codec_audio_data_format
Assign the audio data format for both capture and playback
3-28
codec_aux_control
Control the two pairs of auxiliary inputs
3-29
codec_calibrate
Calibrate the CS4231A codec
3-30
codec_capture_disable
Disable capture mode
3-30
codec_capture_enable
Enable capture mode
3-31
codec_change_sample_rate
Set capture and playback sample rates on the CS4231A codec
3-31
codec_dac_control
Control the output digital-to-analog converters
3-32
codec_id
Return codec ID, codec version, and chip ID
3-33
codec_init
Perform required codec initialization and default configuration
3-33
codec_interrupt_disable
Disable interrupt mode
3-34
codec_interrupt_enable
Enable interrupts from CS4231A codec
3-34
codec_line_in_control
Control left and right line inputs
3-34
codec_loopback_disable
Disable loopback mode
3-35
codec_loopback_enable
Enable loopback mode
3-35
codec_playback_disable
Disable playback mode
3-36
codec_playback_enable
Enable playback mode
3-36
codec_reset
Reset codec
3-36
codec_serial_port_disable
Disable serial port transfers on CS4231A codec
3-37
codec_serial_port_enable
Enable serial port transfers on CS4231A codec
3-37
codec_set_base
Set base address for codec based on memory map and endian
mode
3-38
codec_timer
Use internal timer of codec
3-39
3-26
codec_adc_control
codec_adc_
control
Control Input ADCs
Syntax
#include <codec.h>
int codec_adc_control(
leftRightSel,
int
float
adcGain,
int
micGain,
int
sourceSel );
Defined in
codec.c as a callable C routine
Description
The codec_adc_control( ) function controls the left and right input analog-todigital converters (ADCs) in the CS4231A codec.
- The leftRightSel parameter selects between the left and right converters.
Valid defined values are LEFT and RIGHT.
- The adcGain parameter specifies the ADC gain. Valid values are
0.0 dB–22.5 dB in .5-dB increments.
- The micGain parameter indicates whether or not to enable the 20-dB mi-
crophone input gains. Valid values are either TRUE (nonzero) or FALSE
(zero).
- The sourceSel parameter selects the input source for the specified ADC.
It can be one of these values:
J
J
J
J
LINE_SEL selects LINE input as the source.
AUX1_SEL selects AUX1 input as the source.
MIC_SEL selects MIC input as the source.
LINE_OUT_LBACK_SEL selects LINE OUT as the source.
Note:
The AUX1 input selection is provided for library completeness; however, the
auxiliary inputs are not used on the EVM.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example sets the left ADC gain to 0 dB and disables the 20-dB microphone input gain. LINE is selected as the input source.
int status;
status= codec_adc_control( LEFT, 0.0, FALSE, LINE_SEL );
if (status == ERROR)
return(ERROR);
TMS320C6x EVM DSP Support Software
3-27
codec_audio_data_format
codec_audio
_data_format
Assign the Audio Data Format for Both Capture and Playback
Syntax
#include <codec.h>
int codec_audio_data_format(
unsigned char format,
int
stereo,
int
selection );
Defined in
codec.c as a callable C routine
Description
The codec_audio_data_format( ) function assigns the audio data format on the
CS4231A codec.
- The format parameter selects the data format, which can be one of the fol-
lowing defined values:
J
ULAW_8BIT_COMPANDED selects µ-Law, 8-bit companded format.
J
LINEAR_16BIT_SIGNED_LE selects linear, 16-bit signed littleendian data format.
J
ALAW_8BIT_COMPANDED selects A-Law, 8-bit companded format.
J
ADPCM_4BIT_IMA selects ADPCM, 4-bit IMA-compatible format.
J
LINEAR_16BIT_SIGNED_BE selects linear, 16-bit signed big-endian
data format.
J
LINEAR_8BIT_UNSIGNED selects linear, 8-bit unsigned data format.
- The stereo parameter selects the stereo format.
J
A value of TRUE (nonzero) selects stereo format, in which alternating
samples represent left and right channels.
J
A value of FALSE (zero) selects mono format, in which the left channel
sample occurs twice.
- The selection parameter selects the operating mode, which can be one of
the following defined values:
J
J
J
Return Value
CAPTURE selects capture mode.
PLAYBACK selects playback mode.
BOTH applies arguments to both the capture and the playback mode.
The function returns one of the following values:
OK
ERROR
3-28
Operation succeeded
Operation failed
codec_aux_control
Example
This example selects the linear 16-bit signed little-endian data format operating in stereo mode for both capture and playback.
int status;
status = codec_audio_data_format( LINEAR_16BIT_SIGNED_LE,
TRUE, BOTH);
if (status == ERROR)
return(ERROR);
codec_aux_
control
Control the Two Pairs of Auxiliary Inputs
Syntax
#include <codec.h>
int codec_aux_control(
leftRightSel,
int
int
channelSel,
float mixGain,
int
mute );
Defined in
codec.c as a callable C routine
Description
This codec_aux_control( ) function controls the two pairs of auxiliary inputs on
the CS4231A codec.
The leftRightSel parameter selects between the left and right side inputs.
Valid defined values are LEFT and RIGHT.
The channelSel parameter selects between auxiliary port 1 and auxiliary
port 2. Valid defined values are CHAN1 and CHAN2.
The mixGain parameter specifies the auxiliary input mixer gain setting.
Valid values are –34.5 dB–12.0 dB in 1.5-dB increments.
The mute parameter, if TRUE (nonzero), mutes the selected line to the
mixer.
Note:
This function is provided for library completeness; however, the auxiliary inputs are not used on the EVM.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example enables the left auxiliary 1 input mixer and sets its gain to 0 dB.
int status;
status = codec_aux_control( LEFT, CHAN1, 0.0, FALSE );
if (status == ERROR)
return(ERROR);
TMS320C6x EVM DSP Support Software
3-29
codec_calibrate
codec_calibrate
Calibrate the CS4231A Codec
Syntax
#include <codec.h>
int codec_calibrate( int calVal );
Defined in
codec.c as a callable C routine
Description
The codec_calibrate( ) function calibrates the CS4231A codec.
The calVal parameter determines the calibration mode, which can be one of
the following defined values:
CONVERTER_CAL calibrates only the ADCs and DACs.
DAC_CAL calibrates only the DAC interpolation filters.
FULL_CAL calibrates all offsets, ADCs, DACs, and analog mixers.
NO_CAL specifies that no calibration is performed after resetting the MCE
bit.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example performs a full calibration on the CS4231A codec, which means
the function calibrates all offsets, ADCs, DACs, and analog mixers.
int status;
status = codec_calibrate( FULL_CAL );
if (status == ERROR)
return(ERROR);
codec_capture_
disable
Disable Capture Mode
Syntax
#include <codec.h>
void codec_capture_disable( void );
Defined in
codec.c as a callable C routine
Description
The codec_capture_disable( ) function disables capture mode on the
CS4231A codec.
Return Value
None
3-30
codec_change_sample_rate
codec_capture_
enable
Enable Capture Mode
Syntax
#include <codec.h>
void codec_capture_enable( void );
Defined in
codec.c as a callable C routine
Description
The codec_capture_enable( ) function enables capture mode on the CS4231A
codec.
Return Value
None
codec_change_
sample_rate
Set Capture and Playback Sample Rates on the CS4231A Codec
Syntax
#include <codec.h>
int codec_change_sample_rate(
int
sampleRate,
returnFromMce );
int
Defined in
codec.c as a callable C routine
Description
The codec_change_sample_rate( ) function changes the capture and playback sample rates on the CS4231A codec.
The sampleRate parameter sets the sample rate in Hz. The given sampleRate is matched to a table of valid values, and the actual sample rate
is set to the closest value found.
The returnFromMce parameter, if TRUE, causes this function to clear the
MCE bit before returning to the caller. If FALSE, the function returns to the
caller with the codec in MCE mode.
Return Value
The function returns the actual sample rate (in Hz).
Example
This example sets the codec sample rate to the value closest to 44 kHz.
int actualSampleRate;
actualSampleRate= codec_change_sample_rate(44000,TRUE);
TMS320C6x EVM DSP Support Software
3-31
codec_dac_control
codec_dac_
control
Control the Output DACs
Syntax
#include <codec.h>
int codec_dac_control(
int
leftRightSel,
float dacAtten,
int
mute );
Defined in
codec.c as a callable C routine
Description
The codec_dac_control( ) function controls the left and right output digital-toanalog converters (DACs) on the CS4231A codec.
The leftRightSel parameter selects between the left and right DACs. Valid
defined values are LEFT and RIGHT.
The dacAtten parameter specifies the attenuation applied to the output of
the selected DAC. Valid values are 0.0 dB–94.5 dB in 1.5-dB increments.
The mute parameter, if TRUE (nonzero), mutes the selected line to the
mixer.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example enables the right output DAC and sets its attenuation to 3 dB.
int status;
status = codec_dac_control( LEFT, 3.0, FALSE );
if (status == ERROR)
return(ERROR);
3-32
codec_init
codec_id
Return Codec ID, Codec Version, and Chip ID
Syntax
#include <codec.h>
int codec_id(
int *pVersion,
int *pChipId );
Defined in
codec.c as a callable C routine
Description
The codec_id( ) function returns the codec ID, codec version, and chip ID.
The pVersion parameter is a pointer to the caller-declared integer in which
to place the chip version.
The pChipId parameter is a pointer to the caller-declared integer in which
to place the chip ID.
Return Value
The function returns the codec ID.
Example
The following example returns the codec ID.
int version;
int chipId;
int codec_id;
codec_id
codec_init
= codec_id( &version, &chipId);
Perform Required Codec Initialization and Default Configuration
Syntax
#include <codec.h>
int codec_init( void );
Defined in
codec.c as a callable C routine
Description
The codec_init( ) function initializes the CS4231A codec, sets default parameters for the codec, and calibrates it.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
The following example initializes the codec for use.
int status;
status= codec_init( );
if (status == ERROR)
return(ERROR);
TMS320C6x EVM DSP Support Software
3-33
codec_interrupt_disable
codec_interrupt_
disable
Disable Interrupt Mode
Syntax
#include <codec.h>
void codec_interrupt_disable( void );
Defined in
codec.c as a callable C routine
Description
The codec_interrupt_disable( ) function disables interrupts from the CS4231A
codec.
Return Value
None
codec_interrupt_
enable
Enable Interrupts from CS4231A Codec
Syntax
#include <codec.h>
void codec_interrupt_enable( void );
Defined in
codec.c as a callable C routine
Description
The codec_interrupt_enable( ) function enables interrupts from the CS4231A
codec.
Return Value
None
codec_line_in_
control
Control Left and Right Line Inputs
Syntax
#include <codec.h>
int codec_line_in_control(
int leftRightSel,
float mixGain,
int mute );
Defined in
codec.c as a callable C routine
Description
The codec_line_in_control( ) function controls the left and right line inputs on
the CS4231A codec.
The leftRightSel parameter selects between the left and right line inputs.
Valid defined values are LEFT and RIGHT.
The mixGain parameter specifies the line input mixer gain setting. Valid
values are –34.5 dB–12.0 dB in 1.5-dB increments.
The mute parameter, if TRUE (nonzero), mutes the selected line to the
mixer.
3-34
codec_loopback_enable
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example enables the right line input mixer and sets its gain to 0 dB.
int status;
status = codec_line_in_control( RIGHT, 0.0, FALSE);
if (status == ERROR)
return(ERROR);
codec_loopback_
disable
Disable Loopback Mode
Syntax
#include <codec.h>
void codec_loopback_disable( void );
Defined in
codec.c as a callable C routine
Description
The codec_loopback_disable( ) function disables loopback mode on the
CS4231A codec.
Return Value
None
codec_loopback_
enable
Enable Loopback Mode
Syntax
#include <codec.h>
int codec_loopback_enable( float loopbackAtten );
Defined in
codec.c as a callable C routine
Description
The codec_loopback_enable( ) function enables loopback mode on the
CS4231A codec and sets loopback attenuation.
The loopbackAtten parameter selects the loopback attenuation. Valid
values are 0.0 dB–94.5 dB in 1.5-dB increments.
Return Value
The function returns one of the following values:
OK
ERROR
Operation succeeded
Operation failed
TMS320C6x EVM DSP Support Software
3-35
codec_playback_disable
codec_playback_
disable
Disable Playback Mode
Syntax
#include <codec.h>
void codec_playback_disable( void );
Defined in
codec.c as a callable C routine
Description
The codec_playback_disable( ) function disables playback mode on the
CS4231A codec.
Return Value
None
codec_playback_
enable
Enable Playback Mode
Syntax
#include <codec.h>
void codec_playback_enable( void );
Defined in
codec.c as a callable C routine
Description
The codec_playback_enable( ) function enables playback mode on the
CS4231A codec.
Return Value
None
codec_reset
Reset Codec
Syntax
#include <codec.h>
void codec_reset( void );
Defined in
codec.c as a callable C routine
Description
The codec_reset( ) function resets the CS4231A codec by asserting then deasserting the PWDN pin. All registers are configured to their POR values.
Return Value
None
3-36
codec_serial_port_enable
codec_serial_
port_disable
Disable Serial Port Transfers on CS4231A Codec
Syntax
#include <codec.h>
int codec_serial_port_disable( void );
Defined in
codec.c as a callable C routine
Description
The codec_serial_port_disable( ) function disables the serial port on the
CS4231A codec.
Return Value
The function returns one of the following values:
OK
ERROR
codec_serial_
port_enable
Operation succeeded
Operation failed
Enable Serial Port Transfers on CS4231A Codec
Syntax
#include <codec.h>
int codec_serial_port_enable( int serialFormat );
Defined in
codec.c as a callable C routine
Description
The codec_serial_port_enable( ) function enables the serial port on the
CS4231A codec in the selected format.
- The serialFormat parameter selects the serial data format for the
CS4231A codec. Valid defined values are as follows:
Return Value
J
SERIAL_64BIT_ENHANCED selects 64-bit serial audio data format
enhanced with status information.
J
SERIAL_64BIT selects 64-bit serial audio data format with no status
information.
J
SERIAL 32BIT selects 32-bit serial audio data format with no status
information.
The function returns one of the following values:
OK
ERROR
Operation succeeded
Operation failed
TMS320C6x EVM DSP Support Software
3-37
codec_set_base
codec_set_base
Set Base Codec Address Based on Memory Map and Endian Mode
Syntax
#include <codec.h>
void codec_set_base(
int mapMode,
int littleEndian );
Defined in
codec.c as a callable C routine
Description
The codec_set_base( ) function configures the codec library for use based on
the map and endian mode selected. This function is called from evm_init( ) and
therefore does not need to be called directly (see page 3-44 for a description
of the evm_init( ) function).
The mapMode parameter indicates the current ’C6x memory map, with
valid values of 0 or 1.
The littleEndian parameter is TRUE if the ’C6x is in little-endian mode;
otherwise, it is FALSE.
Return Value
3-38
None
codec_timer
codec_timer
Use Internal Codec Timer
Syntax
#include <codec.h>
int codec_timer(
int usec,
void (*fp)(void) );
Defined in
codec.c as a callable C routine
Description
The codec_timer( ) function controls the internal CS4231A timer in either a
polled (blocking) or interrupt driven (nonblocking) fashion.
The usec parameter specifies the number of microseconds to wait.
If fp is NULL, this function returns after the specified number of microseconds. If fp is not NULL, this function returns immediately and the interrupt
service routine pointed to by fp is called after the specified number of microseconds.
Note:
The maximum time supported by this routine is 650 000 µs (0.650 s). This
is a limitation of the codec timer’s 10-µs clock period and 16-bit counter register.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example demonstrates using the codec timer in interrupt-driven mode.
Global variable timerExpired indicates to the main program that the codec timer has expired and has generated an interrupt.
interrupt void codec_timerISR( void )
{
timerExpired = TRUE;
return;
}
int timerExpired;
int status;
timerExpired = FALSE;
status= codec_timer( 100, codec_timerISR );
if (status == ERROR)
return(ERROR);
TMS320C6x EVM DSP Support Software
3-39
Board Support Library API
3.5 Board Support Library API
This section discusses the EVM board support library API. Included in this discussion are the functions defined that comprise the board library for the ’C6x
EVM board. No public macros are defined for this module.
The following alphabetical listing includes all of the board support library API
functions. Use this listing as a table of contents to the board support library API
functions.
Function
Description
Page
cpu_freq
Return current CPU frequency in MHz
3-41
delay_msec
Delay CPU for specified number of milliseconds
3-41
delay_usec
Delay CPU for specified number of microseconds
3-41
evm_codec_disable
Disconnect codec from ’C6x McBSP
3-42
evm_codec_enable
Connect codec to ’C6x McBSP
3-42
evm_db_reset
Hold daughterboard in reset
3-42
evm_db_unreset
Remove daughterboard reset
3-43
evm_default_emif_init
Initialize EMIF for EVM board to default parameters
3-43
evm_emif_init
Initialize EMIF for EVM board to clock rate-tailored values
3-43
evm_init
Initialize EVM board
3-44
evm_led_disable
Disable selected EVM LED
3-44
evm_led_enable
Enable selected EVM LED
3-45
evm_nmi_disable
Externally disable NMI
3-45
evm_nmi_enable
Externally enable NMI
3-45
evm_nmi_sel
Select the host or codec as source for NMI
3-46
3-40
delay_usec
cpu_freq
Return Current CPU Frequency in MHz
Syntax
#include <board.h>
int cpu_freq( void );
Defined in
board.c as a callable C routine
Description
The cpu_freq( ) function determines the internal CPU clock frequency by reading the CLKMODE and CLKSEL bits in the DSPOPT register of the onboard
complex programmable logic device (CPLD).
Return Value
CPU frequency in Mhz
delay_msec
Delay CPU for Indicated Number of Milliseconds
Syntax
#include <board.h>
int delay_msec( unsigned short numMsec );
Defined in
board.c as a callable C routine
Description
The delay_msec( ) function uses an available timer to delay the specified number of milliseconds before returning to the caller.
The numMsec parameter is a value between 0 and 65 535. For delay values less than 1 ms, use the delay_usec( ) function.
Return Value
The function returns one of the following values:
OK
ERROR
delay_usec
Operation succeeded
Operation failed
Delay CPU for Indicated Number of Microseconds
Syntax
#include <board.h>
int delay_usec( unsigned short numUsec );
Defined in
board.c as a callable C routine
Description
The delay_usec( ) function uses an available timer to delay the specified number of microseconds before returning to the caller.
The numUsec parameter is a value between 0 and 65 535. For delay intervals greater than 65.5 milliseconds, use the delay_msec( ) function.
Return Value
The function returns one of the following values:
OK
ERROR
Operation succeeded
Operation failed
TMS320C6x EVM DSP Support Software
3-41
evm_codec_disable
evm_codec_
disable
Disconnect Codec from ’C6x McBSP
Syntax
#include <board.h>
int evm_codec_disable( void );
Defined in
board.c as a callable C routine
Description
The evm_codec_disable( ) function disconnects the CS4231A codec from the
’C6x McBSP port 0, placing it in power-down mode. This function connects
McBSP port 0 to the daughterboard expansion connector.
Return Value
The function returns one of the following values:
OK
ERROR
evm_codec_
enable
Operation succeeded
Operation failed
Connect Codec to ’C6x McBSP
Syntax
#include <board.h>
int evm_codec_enable( void );
Defined in
board.c as a callable C routine
Description
The evm_codec_enable( ) function connects the CS4231A codec to the ’C6x
McBSP port 0, removing it from power-down mode. This function disconnects
McBSP port 0 from the daughterboard expansion connector.
Return Value
The function returns one of the following values:
OK
ERROR
evm_db_reset
Operation succeeded
Operation failed
Hold Daughterboard in Reset
Syntax
#include <board.h>
void evm_db_reset(void);
Defined in
board.c as a callable C routine
Description
The evm_db_reset( ) function enables the reset signal to the daughterboard
connector. Use the evm_db_unreset( ) function to disable the reset signal.
Return Value
None
3-42
evm_emif_init
evm_db_unreset
Remove Daughterboard Reset
Syntax
#include <board.h>
void evm_db_unreset(void);
Defined in
board.c as a callable C routine
Description
The evm_db_unreset( ) function disables the reset signal to the daughterboard
connector. Use the evm_db_reset( ) function to enable the reset signal.
Return Value
None
evm_default_
emif_init
Initialize EMIF for EVM Board to Default Parameters
Syntax
#include <board.h>
void evm_default_emif_init( void );
Defined in
board.c as a callable C routine
Description
The evm_default_emif_init( ) function initializes the EMIF to default values that
will work at any available CPU frequency.
Return Value
None
evm_emif_init
Initialize EMIF for EVM Board
Syntax
#include <board.h>
void evm_emif_init( void );
Defined in
board.c as a callable C routine
Description
The evm_emif_init( ) function initializes the EMIF to clock rate-tailored values.
Return Value
None
TMS320C6x EVM DSP Support Software
3-43
evm_init
evm_init
Initialize EVM Board
Syntax
#include <board.h>
int evm_init( void );
Defined in
board.c as a callable C routine
Description
The evm_init( ) function initializes the EVM board for use by configuring base
address variables based upon the ’C6x memory map (MAP 0 or MAP 1) and
endian mode selected, initializing the EMIF and enabling the NMI bit in the interrupt enable register. This function must be called before any other DSP support software routines.
Return Value
The function returns one of the following values:
OK
ERROR
Example
Operation succeeded
Operation failed
This example initializes the EVM board for use.
int
status;
status = evm_init( );
if (status == ERROR)
return(ERROR);
evm_led_disable
Disable Selected EVM LED
Syntax
#include <board.h>
int evm_led_disable( int ledNumber );
Defined in
board.c as a callable C routine
Description
The evm_led_disable( ) function extinguishes the selected LED on the EVM
board.
Parameter ledNumber selects the LED to extinguish. Valid values are 0
(for LED0) or 1 (for LED1).
Return Value
The function returns one of the following values:
OK
ERROR
3-44
Operation succeeded
Operation failed
evm_nmi_enable
evm_led_enable
Enable Selected EVM LED
Syntax
#include <board.h>
int evm_led_enable( int ledNumber );
Defined in
board.c as a callable C routine
Description
The evm_led_enable( ) function illuminates the selected LED on the EVM
board.
The ledNumber parameter selects the LED to illuminate. Valid values are
0 (for LED0) or 1 (for LED1).
Return Value
The function returns one of the following values:
OK
ERROR
evm_nmi_disable
Operation succeeded
Operation failed
Externally Disable NMI
Syntax
#include <board.h>
void evm_nmi_disable(void);
Defined in
board.c as a callable C routine
Description
The evm_nmi_disable( ) function externally disables the NMI source to the
’C6x by clearing the NMIEN bit in the CNTL register of the EVM CPLD.
Return Value
None
evm_nmi_enable
Externally Enable NMI
Syntax
#include <board.h>
void evm_nmi_enable( void );
Defined in
board.c as a callable C routine
Description
The evm_nmi_enable( ) function externally enables the NMI source to the ’C6x
by setting the NMIEN bit in the CNTL register of the EVM CPLD.
Return Value
None
TMS320C6x EVM DSP Support Software
3-45
evm_nmi_sel
evm_nmi_sel
Select Source for NMI
Syntax
#include <board.h>
void evm_nmi_sel( int sel );
Defined in
board.c as a callable C routine
Description
The evm_nmi_sel( ) function selects the source for the external NMI to the ’C6x
on the EVM board.
If sel is 0, the host is selected as the source for the NMI; otherwise, the
codec is selected as the source for the NMI.
Return Value
3-46
None
DSP Support Software Examples
3.6 DSP Support Software Examples
The following module provides examples of configuring and controlling the
McBSP and audio codec. The board support library is also used in the examples.
Example 3–2. McBSP, Audio Codec, and Board Support Sample Code
(a) codec_ex.c file
/****************************************************************************/
/* <CODEC_EX.C> – Example code for CODEC and McBSP use.
*/
/*
*/
/*
This module provides examples using the CS4231A audio CODEC.
*/
/*
The data interface to the CS4231A on the EVM is the McBSP.
*/
/*
*/
/* FUNCTIONS:
*/
/*
CodecExLb()
– CODEC Example: Loopback mode
*/
/*
CodecExBlkCapPb()
– CODEC Example: Block Capture and Playback
*/
/*
CodecExContTonePb() – CODEC Example: Continuous Tone Playback
*/
/*
CodecExContCapPb() – CODEC Example: Continuous Capture and Playback */
/*
*/
/* STATIC FUNCTIONS:
*/
/*
ContTonePbCallback() – Callback function.
*/
/*
GenTone()
– Synthesize tone of specified frequency
*/
/*
*/
/* GLOBAL VARIABLES DEFINED
*/
/*
None.
*/
/*
*/
/****************************************************************************/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* INCLUDES AND LOCAL DEFINES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
#include <stdio.h>
#include <stdlib.h>
#include <mcbsp.h>
/* mcbsp devlib
*/
#include <common.h>
#include <mcbspdrv.h>
/* mcbsp driver
*/
#include <board.h>
/* EVM library
*/
#include <codec.h>
/* codec library
*/
#include <mathf.h>
#include ”codec_ex.h”
#define VOICE_BAND_SAMPLE_RATE
8000 /* Hz */
#define PRO_AUDIO_SAMPLE_RATE
44100 /* Hz */
#define TONE_PB_SAMPLE_RATE
5512 /* Hz */
#define BLOCK_CAPTURE_TIME
4 /* sec */
#define CONT_CAPTURE_TIME
1 /* sec */
#define CONT_BUFF_SIZE
0x3fffc /* 1 64kword frames per block
*/
#define TONE_FREQ
1000 /* Hz
*/
#define CONT_TONE_PB_SECS
30 /* secs
*/
#define NUM_BUFFS_TO_PLAY
20
#define PRINT_DBG 0
TMS320C6x EVM DSP Support Software
3-47
DSP Support Software Examples
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* GLOBAL VARIABLES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
volatile int numBuffsPlayed;
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* FILE LOCAL (STATIC) VARIABLES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
int asyncBuffCnt;
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* FILE LOCAL (STATIC) PROTOTYPES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
void ContTonePbCallback(Mcbsp_dev dev,int status);
int GenTone(
/* RET: OK or ERROR
*/
short
*pBuffer,
/* I/O: buffer for generated data
*/
int
buffSize,
/* IN: number of shorts in buffer
*/
float
toneFreq,
/* IN: requested tone frequency (Hz) */
float
sampleRate, /* IN: current CODEC sample rate (Hz)*/
int
leftRightSel);
void AsyncTxCallback(Mcbsp_dev dev,int status);
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* FUNCTIONS
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/****************************************************************************/
/* CodecExLb – CODEC Example: Loopback mode
*/
/*
*/
/*
This function provides an example of using the CS4321A CODEC in
*/
/*
Digital Loopback Mode (DLB).
*/
/*
*/
/****************************************************************************/
int CodecExLb(
/* RET: OK or ERROR
*/
int micSel
/* IN : TRUE – mic sel, FALSE – line sel
*/
)
{
if (codec_init())
return(ERROR);
if (micSel)
{
/* A/D 0.0 dB gain, turn on 20dB mic gain, sel (L/R)MIC as inputs
*/
if (codec_adc_control(LEFT,0.0,TRUE,MIC_SEL))
return(ERROR);
if (codec_adc_control(RIGHT,0.0,TRUE,MIC_SEL))
return(ERROR);
}
else
{
/* A/D 0.0 dB gain, turn off 20dB mic gain, sel (L/R)LINE input
*/
if (codec_adc_control(LEFT,0.0,FALSE,LINE_SEL))
return(ERROR);
if (codec_adc_control(RIGHT,0.0,FALSE,LINE_SEL))
return(ERROR);
/* mute (L/R)LINE input to mixer
*/
if (codec_line_in_control(LEFT,MIN_AUX_LINE_GAIN,TRUE))
return(ERROR);
3-48
DSP Support Software Examples
if (codec_line_in_control(RIGHT,MIN_AUX_LINE_GAIN,TRUE))
return(ERROR);
}
/* D/A 0.0 dB atten, do not mute DAC outputs
if (codec_dac_control(LEFT, 0.0, FALSE))
return(ERROR);
if (codec_dac_control(RIGHT, 0.0, FALSE))
return(ERROR);
/* enable digital loopback mode with no loopback attenuation
if (codec_loopback_enable(0.0))
return(ERROR);
return(OK);
*/
*/
}
/****************************************************************************/
/* CodecExBlkCapPb – CODEC Example: Block Capture and Playback
*/
/*
*/
/*
This function provides an example of capturing a block of audio
*/
/*
data and playing it back for verification
*.
/*
*/
/****************************************************************************/
int CodecExBlkCapPb(
int
micSel,
Mcbsp_dev dev
)
{
Mcbsp_config mcbspConfig;
unsigned char *pBuffer;
int
sampleRate;
unsigned int numBytes;
int
status;
if (micSel)
sampleRate= VOICE_BAND_SAMPLE_RATE;
else
sampleRate= PRO_AUDIO_SAMPLE_RATE;
/**************************************************************************/
/* allocate buffer for capture data
*/
/**************************************************************************/
numBytes= BLOCK_CAPTURE_TIME * sampleRate * sizeof(int);
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* With USE_MALLOC set to 1, SDRAM will be used for the buffer
*/
/* With USE_MALLOC set to 0, SBSRAM will be used for the buffer
*/
/*
Note that SBSRAM will not hold much at the higher sample rate
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
#undef USE_MALLOC
#define USE_MALLOC 1
#if USE_MALLOC
pBuffer = malloc( numBytes );
#else
{
/* Explicitly use SBSRAM
*/
extern unsigned int SbsramDataSize, SbsramDataAddr;
if ( numBytes <= (unsigned int)(&SbsramDataSize) )
TMS320C6x EVM DSP Support Software
3-49
DSP Support Software Examples
{ pBuffer = (unsigned char *)(&SbsramDataAddr); }
else
{ pBuffer = NULL; }
}
#endif
if (pBuffer == NULL)
{
DEBUG(”Error allocating capture buffer in codecExBlkCapPb()”);
return(ERROR);
}
/**************************************************************************/
/* configure McBSP
*/
/**************************************************************************/
memset(&mcbspConfig,0,sizeof(mcbspConfig));
mcbspConfig.loopback
= FALSE;
mcbspConfig.tx.update
= TRUE;
mcbspConfig.tx.clock_polarity
= CLKX_POL_RISING;
mcbspConfig.tx.frame_sync_polarity= FSYNC_POL_HIGH;
mcbspConfig.tx.clock_mode
= CLK_MODE_EXT;
mcbspConfig.tx.frame_sync_mode
= FSYNC_MODE_EXT;
mcbspConfig.tx.phase_mode
= SINGLE_PHASE;
mcbspConfig.tx.frame_length1
= 0;
mcbspConfig.tx.word_length1
= WORD_LENGTH_32;
mcbspConfig.tx.frame_ignore
= NO_FRAME_IGNORE;
mcbspConfig.tx.data_delay
= DATA_DELAY0;
mcbspConfig.rx.update
= TRUE;
mcbspConfig.rx.clock_polarity
= CLKR_POL_FALLING;
mcbspConfig.rx.frame_sync_polarity= FSYNC_POL_HIGH;
mcbspConfig.rx.clock_mode
= CLK_MODE_EXT;
mcbspConfig.tx.frame_sync_mode
= FSYNC_MODE_EXT;
mcbspConfig.rx.phase_mode
= SINGLE_PHASE;
mcbspConfig.rx.frame_length1
= 0;
mcbspConfig.rx.word_length1
= WORD_LENGTH_32;
mcbspConfig.rx.frame_ignore
= NO_FRAME_IGNORE;
mcbspConfig.rx.data_delay
= DATA_DELAY0;
EXIT_ERROR(mcbsp_config(dev,&mcbspConfig));
/**************************************************************************/
/* configure CODEC
*/
/**************************************************************************/
EXIT_ERROR(codec_init());
codec_change_sample_rate(sampleRate, TRUE);
if (micSel)
{
/* A/D 0.0 dB gain, turn on 20dB mic gain, sel (L/R)MIC as inputs
*/
EXIT_ERROR(codec_adc_control(LEFT,0.0,TRUE,MIC_SEL));
EXIT_ERROR(codec_adc_control(RIGHT,0.0,TRUE,MIC_SEL));
#if PRINT_DBG
printf(”Begin speaking into the microphone when the LED illuminates.\n
”);
#endif
}
else
{
/* A/D 0.0 dB gain, turn off 20dB mic gain, sel (L/R)LINE input
*/
3-50
DSP Support Software Examples
EXIT_ERROR(codec_adc_control(LEFT,0.0,FALSE,LINE_SEL));
EXIT_ERROR(codec_adc_control(RIGHT,0.0,FALSE,LINE_SEL));
/* mute (L/R)LINE input to mixer
*/
EXIT_ERROR(codec_line_in_control(LEFT,MIN_AUX_LINE_GAIN,TRUE));
EXIT_ERROR(codec_line_in_control(RIGHT,MIN_AUX_LINE_GAIN,TRUE));
#if PRINT_DBG
printf(”Play input source when LED illuminates.\n
”);
#endif
}
/**************************************************************************/
/* begin capture process
*/
/**************************************************************************/
delay_msec(1000);
/* wait a second for user to view LED
*/
evm_led_enable(0);
evm_led_enable(1);
status= mcbsp_sync_receive(dev,pBuffer,numBytes,FALSE,NULL,FALSE);
evm_led_disable(1);
evm_led_disable(0);
EXIT_ERROR(status);
/**************************************************************************/
/* begin playback process
*/
/**************************************************************************/
delay_msec(1000);
/* pause
*/
/* D/A 0.0 dB atten, do not mute DAC outputs
*/
EXIT_ERROR(codec_dac_control(LEFT, 0.0, FALSE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, FALSE));
evm_led_enable(1);
evm_led_enable(0);
status = mcbsp_sync_send(dev,pBuffer,numBytes,FALSE,NULL,FALSE);
evm_led_disable(1);
evm_led_disable(0);
EXIT_ERROR(status);
/* mute DAC outputs
*/
EXIT_ERROR(codec_dac_control(LEFT, 0.0, TRUE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, TRUE));
#if USE_MALLOC
free(pBuffer);
#endif
return(OK);
exit_err:
#if USE_MALLOC
free(pBuffer);
#endif
return(ERROR);
}
/****************************************************************************/
/* CodecExContCapPb – CODEC Example: Continuous Capture and Playback
*/
/*
*/
/*
This function provides an example of capturing into and playing back
*/
/*
out of a buffer simultaneously.
*/
/*
*/
/****************************************************************************/
TMS320C6x EVM DSP Support Software
3-51
DSP Support Software Examples
int CodecExContCapPb(
int
micSel,
Mcbsp_dev dev
)
{
Mcbsp_config mcbspConfig;
unsigned char *pBuffer1;
int
sampleRate;
unsigned int numBytes;
int
status;
if (micSel)
sampleRate= VOICE_BAND_SAMPLE_RATE;
else
sampleRate= PRO_AUDIO_SAMPLE_RATE;
/**************************************************************************/
/* allocate buffer for capture data
*/
/**************************************************************************/
/* see HEAP_SZ in makefile */
numBytes= CONT_CAPTURE_TIME * sampleRate * sizeof(int);
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* With USE_MALLOC set to 1, SDRAM will be used for the buffer
*/
/* With USE_MALLOC set to 0, SBSRAM will be used for the buffer
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
#undef USE_MALLOC
#define USE_MALLOC 1
#if USE_MALLOC
pBuffer1 = malloc( numBytes );
#else
{
/* Explicitly use SBSRAM
*/
extern unsigned int SbsramDataSize, SbsramDataAddr;
if ( numBytes <= (unsigned int)(&SbsramDataSize) )
{ pBuffer1 = (unsigned char *)(&SbsramDataAddr); }
else
{ pBuffer1 = NULL; }
}
#endif
if (pBuffer1 == NULL)
{
DEBUG(”Error allocating capture buffer 1 in codecExContCapPb()”);
return(ERROR);
}
/**************************************************************************/
/* configure McBSP
*/
/**************************************************************************/
memset(&mcbspConfig,0,sizeof(mcbspConfig));
mcbspConfig.loopback
= FALSE;
mcbspConfig.tx.update
= TRUE;
mcbspConfig.tx.clock_polarity
= CLKX_POL_RISING;
mcbspConfig.tx.frame_sync_polarity= FSYNC_POL_HIGH;
mcbspConfig.tx.clock_mode
= CLK_MODE_EXT;
mcbspConfig.tx.frame_sync_mode
= FSYNC_MODE_EXT;
mcbspConfig.tx.phase_mode
= SINGLE_PHASE;
3-52
DSP Support Software Examples
mcbspConfig.tx.frame_length1
= 0;
mcbspConfig.tx.word_length1
= WORD_LENGTH_32;
mcbspConfig.tx.frame_ignore
= FRAME_IGNORE;
mcbspConfig.tx.data_delay
= DATA_DELAY0;
mcbspConfig.rx.update
= TRUE;
mcbspConfig.rx.clock_polarity
= CLKR_POL_FALLING;
mcbspConfig.rx.frame_sync_polarity= FSYNC_POL_HIGH;
mcbspConfig.rx.clock_mode
= CLK_MODE_EXT;
mcbspConfig.tx.frame_sync_mode
= FSYNC_MODE_EXT;
mcbspConfig.rx.phase_mode
= SINGLE_PHASE;
mcbspConfig.rx.frame_length1
= 0;
mcbspConfig.rx.word_length1
= WORD_LENGTH_32;
mcbspConfig.rx.frame_ignore
= FRAME_IGNORE;
mcbspConfig.rx.data_delay
= DATA_DELAY0;
EXIT_ERROR(mcbsp_config(dev,&mcbspConfig));
/**************************************************************************/
/* configure CODEC
*/
/**************************************************************************/
EXIT_ERROR(codec_init());
codec_change_sample_rate(sampleRate, TRUE);
if (micSel)
{
/* A/D 0.0 dB gain, turn on 20dB mic gain, sel (L/R)MIC as inputs
*/
EXIT_ERROR(codec_adc_control(LEFT,0.0,TRUE,MIC_SEL));
EXIT_ERROR(codec_adc_control(RIGHT,0.0,TRUE,MIC_SEL));
#if PRINT_DBG
printf(”Begin speaking into the microphone when the LED illuminates.\n
”);
#endif
}
else
{
/* A/D 0.0 dB gain, turn off 20dB mic gain, sel (L/R)LINE input
*/
EXIT_ERROR(codec_adc_control(LEFT,0.0,FALSE,LINE_SEL));
EXIT_ERROR(codec_adc_control(RIGHT,0.0,FALSE,LINE_SEL));
/* mute (L/R)LINE input to mixer
*/
EXIT_ERROR(codec_line_in_control(LEFT,MIN_AUX_LINE_GAIN,TRUE));
EXIT_ERROR(codec_line_in_control(RIGHT,MIN_AUX_LINE_GAIN,TRUE));
#if PRINT_DBG
printf(”Play on input source when LED illuminates.\n
”);
#endif
}
/* D/A 0.0 dB atten, do not mute DAC outputs
EXIT_ERROR(codec_dac_control(LEFT, 0.0, FALSE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, FALSE));
/* initialize globals */
numBuffsPlayed = 0;
delay_msec(1000);
while (numBuffsPlayed < NUM_BUFFS_TO_PLAY)
{
if (numBuffsPlayed % 2)
{
evm_led_disable(1);
TMS320C6x EVM DSP Support Software
*/
3-53
DSP Support Software Examples
evm_led_disable(0);
}
else
{
evm_led_enable(1);
evm_led_enable(0);
}
/***************************************************************************/
/* begin capture process
*/
/***************************************************************************/
status= mcbsp_sync_receive(dev, pBuffer1, numBytes, FALSE, NULL, FALSE);
EXIT_ERROR(status);
/***************************************************************************/
/* begin playback process
*/
/***************************************************************************/
status= mcbsp_async_send(dev,pBuffer1,numBytes,FALSE,NULL,AsyncTxCallback);
EXIT_ERROR(status);
} /* close while loop */
/* mute DAC outputs
*/
EXIT_ERROR(codec_dac_control(LEFT, 0.0, TRUE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, TRUE));
#if USE_MALLOC
free(pBuffer1);
#endif
evm_led_disable(1);
evm_led_disable(0);
return(OK);
exit_err:
#if USE_MALLOC
free(pBuffer1);
#endif
return(ERROR);
}
void AsyncTxCallback(Mcbsp_dev dev, int status)
{
numBuffsPlayed++;
return;
}
/*****************************************************************************/
/* CodecExContTonePb() – Play continuous tone
*/
/*
This function provides an example of playing back a buffer of data in
*/
/*
continuous (dma autoinitialization) mode.
*/
/*
*/
/*****************************************************************************/
int CodecExContTonePb( Mcbsp_dev dev, int leftRightSel, int duration )
{
Mcbsp_config
mcbspConfig;
int
numBytes;
int
sampleRate;
int
status;
int
i;
short
*pBuffer;
3-54
DSP Support Software Examples
sampleRate = TONE_PB_SAMPLE_RATE;
/****************************************************************************/
/* allocate buffer for audio data
*/
/****************************************************************************/
numBytes = TONE_PB_SAMPLE_RATE * sizeof(int);
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* With USE_MALLOC set to 1, SDRAM will be used for the buffer
*/
/* With USE_MALLOC set to 0, SBSRAM will be used for the buffer
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
#undef USE_MALLOC
#define USE_MALLOC 0
#if USE_MALLOC
pBuffer = (short *)(malloc( numBytes ));
#else
{
/* Explicitly use SBSRAM
*/
extern unsigned int SbsramDataSize, SbsramDataAddr;
if ( numBytes <= (unsigned int)(&SbsramDataSize) )
{ pBuffer = (short *)(&SbsramDataAddr); }
else
{ pBuffer = NULL; }
}
#endif
if (pBuffer == NULL)
{
DEBUG(”Error allocating capture buffer in codecExContTonePb()”);
return(ERROR);
}
/****************************************************************************/
/* synthesize tone
*/
/****************************************************************************/
GenTone(pBuffer,numBytes/2,(float)TONE_FREQ,(float)sampleRate,leftRightSel);
/****************************************************************************/
/* configure mcbsp transmitter
*/
/****************************************************************************/
memset(&mcbspConfig,0,sizeof(mcbspConfig));
mcbspConfig.loopback
= FALSE;
mcbspConfig.tx.update
= TRUE;
mcbspConfig.tx.clock_polarity
= CLKX_POL_RISING;
mcbspConfig.tx.frame_sync_polarity= FSYNC_POL_HIGH;
mcbspConfig.tx.clock_mode
= CLK_MODE_EXT;
mcbspConfig.tx.frame_sync_mode
= FSYNC_MODE_EXT;
mcbspConfig.tx.phase_mode
= SINGLE_PHASE;
mcbspConfig.tx.frame_length1
= 0;
mcbspConfig.tx.word_length1
= WORD_LENGTH_32;
mcbspConfig.tx.frame_ignore
= NO_FRAME_IGNORE;
mcbspConfig.tx.data_delay
= DATA_DELAY0;
mcbspConfig.rx.update
= FALSE;
mcbspConfig.srg.update
= FALSE;
EXIT_ERROR(mcbsp_config(dev,&mcbspConfig));
TMS320C6x EVM DSP Support Software
3-55
DSP Support Software Examples
/****************************************************************************/
/* configure CODEC
*/
/****************************************************************************/
EXIT_ERROR(codec_init());
codec_change_sample_rate(sampleRate, TRUE);
/* D/A 0.0 dB atten, do not mute DAC outputs
*/
EXIT_ERROR(codec_dac_control(LEFT, 0.0, FALSE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, FALSE));
numBuffsPlayed= 0;
evm_led_enable(1);
evm_led_enable(0);
status = mcbsp_cont_async_send(dev,(unsigned char *)pBuffer,NULL,
numBytes,FALSE,NULL,ContTonePbCallback );
while(1)
{
delay_msec(10);
if ( numBuffsPlayed < (duration – 1) )
{ continue; }
else
{ dev–>tx_dma.continuous= FALSE; }
if ( numBuffsPlayed >= duration )
{ break; }
}
evm_led_disable(1);
evm_led_disable(0);
/* mute DAC outputs
*/
EXIT_ERROR(codec_dac_control(LEFT, 0.0, TRUE));
EXIT_ERROR(codec_dac_control(RIGHT, 0.0, TRUE));
delay_msec(1000);
#if USE_MALLOC
free(pBuffer);
#endif
return(OK);
exit_err:
#if USE_MALLOC
free(pBuffer);
#endif
return(ERROR);
}
void ContTonePbCallback(Mcbsp_dev dev,int status)
{
numBuffsPlayed++;
return;
}
/*****************************************************************************/
/* GenTone() – Generate tone samples with indicated frequency.
/*
/*****************************************************************************/
int GenTone(
/* RET: OK or ERROR
*/
short
*pBuffer,
/* I/O: buffer for generated data
*/
int
buffSize,
/* IN: number of shorts in buffer
*/
float
toneFreq,
/* IN: requested tone frequency (Hz) */
3-56
DSP Support Software Examples
float
int
sampleRate, /*
leftRightSel)/*
IN: current CODEC sample rate (Hz) */
IN: LEFT, RIGHT, or BOTH
*/
{
int i;
float omega;
float deltaT;
short scaledVal;
memset((unsigned char *)pBuffer,0,(buffSize * sizeof(short)));
for (i=0; i< buffSize; i++)
{
omega= 2 * PI * toneFreq;
deltaT= (i/2) / sampleRate;
scaledVal= (short)(32767 * (sinf(omega*deltaT)));
if ( (leftRightSel == RIGHT) || (leftRightSel == BOTH) )
pBuffer[i] = scaledVal;
i++;
if ( (leftRightSel == LEFT) || (leftRightSel == BOTH) )
pBuffer[i]
= scaledVal;
}
return(0);
}
TMS320C6x EVM DSP Support Software
3-57
DSP Support Software Examples
(b) codec_ex.h file
/******************************************************************************/
/*
CODEC_EX.H – Codec examples header file
*/
/*
*/
/*
This is the public header file for the codec examples for the EVM
*/
/*
board.
*/
/*
*/
/* FUNCTIONS:
*/
/*
CodecExLb()
– CODEC Example: Loopback mode
*/
/*
CodecExBlkCapPb()
– CODEC Example: Block Capture and Playback
*/
/*
CodecExContTonePb() – CODEC Example: Continuous Tone Playback
*/
/*
CodecExContCapPb() – CODEC Example: Continuous Capture and Playback
*/
/*
*/
/* MACRO FUNCTIONS:
*/
/*
*/
/******************************************************************************/
#ifndef _CODEC_EX_H_
#define _CODEC_EX_H_
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* INCLUDES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* DEFINES AND MACROS
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* GLOBAL VARIABLES
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/* FUNCTIONS
*/
/*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*/
/******************************************************************************/
/* CodecExLb – CODEC Example: Loopback mode
*/
/*
*/
/*
This function provides an example of using the CS4321A CODEC in
*/
/*
Digital Loopback Mode (DLB).
*/
/*
*/
/******************************************************************************/
int CodecExLb(
/* RET: OK or ERROR
*/
int micSel
/* IN : TRUE – mic sel, FALSE – line sel
*/
);
/******************************************************************************/
/* CodecExBlkCapPb – CODEC Example: Block Capture and Playback
*/
/*
*/
/*
This function provides an example of capturing a block of audio
*/
/*
data and playing it back for verification
*/
/*
*/
/******************************************************************************/
int CodecExBlkCapPb(
int
micSel,
Mcbsp_dev dev
);
3-58
DSP Support Software Examples
/*****************************************************************************/
/* CodecExContTonePb() – Play continuous tone
*/
/*
This function provides an example of playing back a buffer of data in
*/
/*
continuous (dma autoinitialization) mode.
*/
/*
*/
/*****************************************************************************/
int CodecExContTonePb( Mcbsp_dev dev, int leftRightSel, int duration );
/*****************************************************************************/
/* CodecExContCapPb() – Capture and playback simultaneously
*/
/*****************************************************************************/
int CodecExContCapPb(
int
micSel,
Mcbsp_dev dev
);
#endif
TMS320C6x EVM DSP Support Software
3-59
DSP Support Software Examples
(c) main.c file
#include <stdio.h>
#include <string.h>
#include <common.h>
#include <mcbspdrv.h>
#include <board.h>
#include <codec.h>
#include ”codec_ex.h”
#define PRINT_DBG 0
static void led_blink( int count, int ms_period );
main()
{
int status;
Mcbsp_dev dev;
int i;
/***************************************************************************/
/* Initialize EVM
*/
/***************************************************************************/
if (evm_init())
{
printf(”ERROR returned from evm_init()\n”);
return(ERROR);
}
led_blink( 2, 1000 );
/***************************************************************************/
/* Codec Loopback Example
*/
/***************************************************************************/
#if 1
#if PRINT_DBG
printf(”\nCodec Line In Loopback example.
\n”);
#endif
status= CodecExLb( FALSE );
if (status == ERROR)
{
printf(”Error calling CodecExLb()\n”);
return(ERROR);
}
delay_msec(10000);
led_blink( 10, 200 );
#endif
/***************************************************************************/
/* Open MCBSP for subsequent Examples
*/
/***************************************************************************/
mcbsp_drv_init();
dev= mcbsp_open(0);
if (dev == NULL)
{
printf(”Error opening MCBSP 0
\n ”);
return(ERROR);
}
#if 1
/***************************************************************************/
/* Single Block Capture and Playback Example
*/
/***************************************************************************/
3-60
DSP Support Software Examples
#if PRINT_DBG
printf(”Codec Block Capture Playback example.
\n”);
#endif
status = CodecExBlkCapPb( FALSE, dev );
if (status == ERROR)
{
printf(”Error calling CodecExBlkCapPb()\n ”);
return(ERROR);
}
led_blink( 10, 200 );
#endif
#if 1
/***************************************************************************/
/* Codec simultaneous capture and playback over McBSP Example
*/
/***************************************************************************/
#if PRINT_DBG
printf(”Codec Continuous Capture Playback example.
\n”);
#endif
status = CodecExContCapPb( TRUE, dev );
if (status == ERROR)
{
printf(”Error calling CodecExContCapPb() \n ” );
return(ERROR);
}
led_blink( 10, 200 );
#endif
/***************************************************************************/
/* Codec Tone Generator using DMA autoinitialization Example
*/
/***************************************************************************/
#if 1
#if PRINT_DBG
printf(”Codec Continuous Tone Playback example.
\n”);
#endif
status = CodecExContTonePb( dev, BOTH, 5 );
if (status == ERROR)
{
printf(”Error calling CodecExContTonePb()\n ”);
return(ERROR);
}
led_blink( 10, 200 );
#endif
mcbsp_close(dev);
printf(”Thats All Folks\n”);
led_blink( 100, 100 );
return(OK);
}
static void led_blink( int count, int ms_period )
{
int
i;
for (i=0;i<count;i++)
{
evm_led_enable(0); evm_led_enable(1); delay_msec(ms_period/2);
evm_led_disable(0); evm_led_disable(1); delay_msec(ms_period/2);
}
}
TMS320C6x EVM DSP Support Software
3-61
DSP Support Software Examples
(d) link.cmd file
/* linker command file for examples (MAP 1) */
MEMORY
{
INT_PROG_MEM (RX)
: origin = 0x00000000 length = 0x00010000
SBSRAM_PROG_MEM (RX) : origin = 0x00400000 length = 0x00014000
SBSRAM_DATA_MEM (RW) : origin = 0x00414000 length = 0x0002C000
SDRAM0_DATA_MEM (RW) : origin = 0x02000000 length = 0x00400000
SDRAM1_DATA_MEM (RW) : origin = 0x03000000 length = 0x00400000
INT_DATA_MEM (RW)
: origin = 0x80000000 length = 0x00010000
}
SECTIONS
{
.vec:
load = 0x00000000
.text:
load = SBSRAM_PROG_MEM
.const:
load = INT_DATA_MEM
.bss:
load = INT_DATA_MEM
.data:
load = INT_DATA_MEM
.cinit
load = INT_DATA_MEM
.pinit
load = INT_DATA_MEM
.stack
load = INT_DATA_MEM
.far
load = INT_DATA_MEM
.sysmem
load = SDRAM0_DATA_MEM
.cio
load = INT_DATA_MEM
sbsbuf
load = SBSRAM_DATA_MEM
{ _SbsramDataAddr = .; _SbsramDataSize = 0x0002C000; }
}
3-62
Appendix
AppendixAA
TMS320C6x EVM Connector Pinouts
This appendix contains the pinout information for each connector on the
TMS320C6x EVM.
Topic
Page
A.1
TMS320C6x EVM Connector Summary . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.2
Stereo Microphone Input Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
A.3
Stereo Line Input Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.4
Stereo Line Output Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3
A.5
CPLD ISP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4
A.6
TMS320C6x JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5
A.7
Expansion Memory Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . A-6
A.8
Expansion Peripheral Interface Connector . . . . . . . . . . . . . . . . . . . . . . A-7
A.9
External Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.10 DSP Fan Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8
A.11 PCI Local Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9
A-1
TMS320C6x
TMS320C6x EVM
EVM Connector
Connector Summary
Summary / Stereo Microphone Input Jack
A.1 TMS320C6x EVM Connector Summary
There are ten connectors on the ’C6x EVM, as shown in Table A–1. The J4
CPLD ISP connector is for factory use and is not installed.
Table A–1. TMS320C6x EVM Connectors Summary
Connector
No. of
Pins
Description
Type
See
Page
J1
3
Stereo microphone input
3.5-mm audio jack
A-2
J2
3
Stereo line input
3.5-mm audio jack
A-3
J3
3
Stereo line output
3.5-mm audio jack
A-3
J4
10
CPLD ISP header
2 × 5 pin, 0.1 in.
A-4
J5
14
’C6x JTAG emulation header
2 × 7 pin, 0.1 in.
A-5
J6
80
Expansion memory interface
2 × 40 pos, 0.050-in. SMT
A-6
J7
80
Expansion peripheral interface
2 × 40 pos., 0.050-in. SMT
A-7
J8
4
External power
Molex disk drive, right-angle
A-8
J9
2
DSP fan power
Molex 1.25-mm, right-angle
A-8
P1
124
PCI local bus
Edge connector
A-9
A.2 Stereo Microphone Input Jack
Connector J1 supports a stereo microphone input. If a mono microphone is
used, then the input left (tip) channel is only used. Both microphone input channels provide a voltage bias for electret microphones. The microphone input is
the top 3.5-mm jack on the EVM’s mounting bracket (adjacent to the status
LED).
Table A–2. Stereo Microphone Input Connector J1 Pinout
A-2
J1 Pin
Signal Name
Description
Type
TIP
MIC_L
Microphone left input channel
I
RING
MIC_R
Microphone right input channel
I
SLEEVE
AGND
Audio ground
–
Running
Reference
Stereo Line Input
Jack Title—Attribute
/ Stereo Line Output
Jack
A.3 Stereo Line Input Jack
Connector J2 supports a stereo line input. The line input audio connector is the
middle 3.5-mm jack on the EVM’s mounting bracket.
Table A–3. Stereo Line Input Connector J2 Pinout
J2 Pin
Signal Name
Description
Type
TIP
LI_L
Line input left channel
I
RING
LI_R
Line input right channel
I
SLEEVE
AGND
Audio ground
–
A.4 Stereo Line Output Jack
Connector J3 supports a stereo line input. The line output audio connector is
the bottom 3.5-mm jack on the EVM’s mounting bracket.
Table A–4. Stereo Line Output Connector J3 Pinout
J3 Pin
Signal Name
Description
TIP
LO_L
Line output left channel
O
RING
LO_R
Line output right channel
O
SLEEVE
AGND
Audio ground
–
TMS320C6x EVM Connector Pinouts
Type
A-3
CPLD ISP Header
A.5 CPLD ISP Header
Connector J4 provides the CPLD’s JTAG in-system programming port that allows the EVM’s onboard logic to be reprogrammed. This connector is a 10-pin
header (two rows of five pins) with connections shown in Table A–5 to communicate with the Altera ByteBlaster parallel port cable. The 10-pin female connector on the cable is connected to the male header on the EVM. The pins
have 0.025-inch square posts with 0.100-inch spacing.
The J4 CPLD ISP connector is for factory use and is not installed.
Table A–5. CPLD ISP J4 Pinout
A-4
J4 Pin
No.
Signal Name
1
TCK
Test clock
I
2
GND
Ground
–
3
TDO
Test data output
O
4
VCC
5V
O
5
TMS
Test mode select
I
6
NC
–
–
7
NC
–
–
8
NC
–
–
9
TDI
Test data input
I
10
GND
–
–
Description
Type
TMS320C6x JTAG Emulation Header
A.6 TMS320C6x JTAG Emulation Header
Connector J5 provides the ’C6201’s emulation port based on the IEEE 1149.1
standard. This connector is a 14-pin header (two rows of seven pins) with connections shown in Table A–6 to communicate with an XDS510 emulator. Pin
6 is used for keying to ensure a proper connection.
Table A–6. TMS320C6x JTAG Emulation Header J5 Pinout
J5 Pin
No.
Signal Name
1
TMS
Test mode select
I
2
TRST
Test reset
I
3
TDI
Test data input
I
4
GND
Ground
–
5
PD (VCC)
Presence detect. Indicates that the
emulation cable is connected and the target is powered up. PD is tied to 3.3 V on
the EVM.
O
6
KEY
Not used. This pin is cut off on the J5
header. This pin is filled in on the XDS510
connector.
–
7
TDO
Test data out
O
8
GND
Ground
–
9
TCK_RET
Test clock return. Test clock input to the
emulator.
O
10
GND
Ground
–
11
TCK
Test clock. TCK is a 10.368-MHz clock
source from the emulation cable pod.
I
12
GND
Ground
–
13
EMU0
Emulation pin 0
I/O
14
EMU1
Emulation pin 1
I/O
Description
TMS320C6x EVM Connector Pinouts
Type
A-5
Expansion Memory Interface Connector
A.7 Expansion Memory Interface Connector
Connector J6 provides the ’C6201 asynchronous expansion memory interface
signals to a daughterboard that can provide additional memory and memorymapped devices.
Table A–7. Expansion Memory Interface J6 Connector Pinout
A-6
J6 Pin
No.
Signal Name
Type
J6 Pin
No.
Signal Name
Type
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
5V
XA21
XA19
XA17
XA15
GND
XA13
XA11
XA9
XA7
5V
XA5
XA3
XBE3
XBE1
GND
XD31
XD29
XD27
XD25
3.3 V
XD23
XD21
XD19
XD17
GND
XD15
XD13
XD11
XD9
GND
XD7
XD5
XD3
XD1
GND
XRE
XOE
SPARE (N/C)
GND
O
O
O
O
O
–
O
O
O
O
O
O
O
O
O
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
O
O
–
–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
5V
XA20
XA18
XA16
XA14
GND
XA12
XA10
XA8
XA6
5V
XA4
XA2
XBE2
XBE0
GND
XD30
XD28
XD26
XD24
3.3 V
XD22
XD20
XD18
XD16
GND
XD14
XD12
XD10
XD8
GND
XD6
XD4
XD2
XD0
GND
XWE
XRDY
XCE1
GND
O
O
O
O
O
–
O
O
O
O
O
O
O
O
O
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
O
I
O
–
Expansion Peripheral Interface Connector
A.8 Expansion Peripheral Interface Connector
Connector J7 provides ’C6201 expansion peripheral interface signals to a
daughterboard.
Table A–8. Expansion Peripheral Interface J7 Connector Pinout
J7 Pin
No.
Signal Name
Type
J7 Pin
No.
Signal Name
Type
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
12 V
GND
5V
GND
5V
SPARE (N/C)
RSVD (N/C)
RSVD (N/C)
SPARE (N/C)
3.3 V
XCLKX0
XFSX0
GND
XCLKR0
XFSR0
GND
XCLKX1
XFSX1
GND
XCLKR1
XFSR1
GND
TOUT0
SPARE (N/C)
TOUT1
GND
XEXT_INT7
INUM3
INUM1
XRESET
GND
XCNTL1
XSTAT1
SPARE (N/C)
XCE2
DMAC3
DMAC1
GND
GND
GND
O
–
O
–
O
–
–
–
–
O
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
–
I/O/Z
I/O/Z
–
O
–
I
–
I
O
O
O
–
O
I
–
O
O
O
–
–
–
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
–12 V
GND
5V
GND
5V
SPARE (N/C)
RSVD (N/C)
RSVD (N/C)
SPARE (N/C)
3.3 V
XCLKS0
XDX0
GND
SPARE (N/C)
XDR0
GND
XCLKS1
XDX1
GND
SPARE (N/C)
XDR1
GND
TINP0
SPARE (N/C)
TINP1
GND
IACK
INUM2
INUM0
DSP_PD
GND
XCNTL0
XSTAT0
SPARE (N/C)
XCE3
DMAC2
DMAC0
GND
XCLKOUT2
GND
O
–
O
–
O
–
–
–
–
O
I
O
–
–
I
–
I
O
–
–
I
–
O
–
I
–
O
O
O
O
–
O
I
–
O
O
O
–
O
–
TMS320C6x EVM Connector Pinouts
A-7
External Power Connector / DSP Fan Power Connector
A.9 External Power Connector
Connector J8 enables the ’C6x EVM to be connected to an external power supply during stand-alone operation.
Table A–9. External Power J8 Connector Pinout
J8 Pin
No.
Signal Name
1
12
12 VDC at 500 mA
I
2
–12
–12 VDC at 100 mA
I
3
GND
Ground
–
4
5
5 VDC at 4 A
I
Description
Type
A.10 DSP Fan Power Connector
Connector J9 provides power to the DSP cooling fan. This 2-pin connector provides 5 V at 100 mA to the fan.
Table A–10. DSP Fan Power J9 Connector Pinout
A-8
J9 Pin
No.
Signal Name
1
GND
Ground
–
2
PWR
5 VDC at 100 mA
O
Description
Type
PCI Local Bus Connector
A.11 PCI Local Bus Connector
Connector P1 provides the PCI local bus to the ’C6x EVM.
Table A–11. PCI Local Bus P1 Connector Pinout
P1 Pin
No.
Side B
Side A
P1 Pin
No.
1
–12 V
TRST#
2
TCK
12 V
3
GND
4
5
Side B
Side A
32
AD17
AD16
33
C/BE2#
3.3 V
TMS
34
GND
FRAME#
TDO
TDI
35
IRDY#
GND
5V
5V
36
3.3 V
TRDY#
6
5V
RSVD
37
DEVSEL#
GND
7
INTB#
INTC#
38
GND
STOP#
8
INTD#
INTA#
39
LOCK#
3.3 V
9
PRSNT1#
RSVD
40
PERR#
SDONE
10
RSVD
5V
41
3.3 V
SBO#
11
PRSNT2#
RSVD
42
SERR#
GND
12
GND
GND
43
3.3 V
PAR
13
GND
GND
44
C/BE1#
AD15
14
RSVD
RSVD
45
AD14
3.3 V
15
GND
RST#
46
GND
AD13
16
CLK
5V
47
AD12
AD11
17
GND
GNT#
48
AD10
GND
18
REQ#
GND
49
GND
AD9
19
5V
RSVD
50
Key
Key
20
AD31
AD30
51
Key
Key
21
AD29
3.3 V
52
AD8
C/BE0#
22
GND
AD28
53
AD7
3.3 V
23
AD27
AD26
54
3.3 V
AD6
24
AD25
GND
55
AD5
AD4
25
3.3 V
AD24
56
AD3
GND
26
C/BE3#
TDSEL
57
GND
AD2
27
AD23
3.3 V
58
AD1
AD0
28
GND
AD20
59
5V
5V
29
AD21
GND
60
ACK64#
REQ64#
30
AD19
AD18
61
5V
5V
31
3.3 V
AD16
62
5V
5V
TMS320C6x EVM Connector Pinouts
A-9
Appendix
AppendixBA
TMS320C6x EVM Schematics
This appendix contains the schematics for the TMS320C6x EVM.
B-1
TMS320C6x EVM Schematics
B-2
B-3
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-4
B-5
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-6
B-7
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-8
B-9
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-10
B-11
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-12
B-13
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-14
B-15
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-16
B-17
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-18
B-19
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-20
B-21
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-22
B-23
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-24
B-25
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-26
B-27
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-28
B-29
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-30
B-31
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-32
B-33
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-34
B-35
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-36
B-37
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
B-38
B-39
TMS320C6x EVM Schematics
TMS320C6x EVM Schematics
Appendix
AppendixCA
TMS320C6x EVM CPLD Equations
This appendix provides the complex programmable logic device (CPLD)
equations. The CPLD, which is the only programmable logic device on the
’C6x EVM, is designated as U12 on the board.
Topic
Page
C.1
Overview of the EVM CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
C.2
EVM CPLD Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-8
C-1
Overview of the EVM CPLD
C.1 Overview of the EVM CPLD
The CPLD is an Altera EPM7256SQC208–10 device that has a 208-pin PQFP
package. A summary of the pin allocation is shown in Table C–1.
Table C–1. TMS320C6x EVM CPLD Pin Summary
Pin Type
Number of Pins
Inputs
64
Bidirectional
16
Outputs
60
Unused
20
JTAG
4
5V
4
3.3 V
10
GND
14
No connects
16
Total pins
208
The EPM7256SQC208–10 CPLD provides 5000 usable gates, of which
approximately 75% are used in this design. The device contains 256 macrocells arranged in 16 logic array blocks. The maximum pin-to-pin delay is
10.5 ns. The CPLD uses 5 V for internal operation and 3.3 V for its I/O buffers.
It can interface to both 3.3- and 5-V devices.
The CPLD was designed using Synariot ABELt version 6.5 and Altera
MAX+ PLUSt II version 8.1. Synario was used to enter the design in the
ABEL hardware design language, and MAX+ PLUS II was used for design
compilation, simulation, and programming file generation.
The CPLD’s ABEL source files are modular with a top-level module and six
low-level modules as shown in Figure C–1. These seven source files are provided in section C.2, EVM CPLD Equations.
C-2
Overview of the EVM CPLD
Figure C–1. TMS320C6x EVM CPLD Source Files
EVM
top-level module
(EVM.ABL)
EVM
reset control
EVM
user control
EVM
clock selection
EVM
memory decode
EVM
interrupt control
EVM
PCI interface
(EVMRESET.ABL)
(EVMSWMUX.ABL)
(EVMCKSEL.ABL)
(EVMDECOD.ABL)
(EVMINT.ABL)
(EVMPCI.ABL)
Table C–2 provides the CPLD pin definitions in numerical pin order. Table C–3
provides the CPLD pin definitions in sequential alphabetical order.
TMS320C6x EVM CPLD Equations
C-3
Overview of the EVM CPLD
Table C–2. TMS320C6x CPLD Pin Definitions (Numerical Pin Order)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
N/C
27
BOOTMODE4
53
N/C
79
HRW
2
N/C
28
Reserved
54
N/C
80
PTNUM0
3
ARE
29
DQ6
55
CE2_SDEN
81
TBCA2_HHWIL
4
PCI_IRQ
30
TCK
56
CE3_SDEN
82
GND
5
VCC3
31
Reserved
57
Reserved
83
VCC5
6
XCNTL0
32
GND
58
CODEC_CS
84
AO_SEL
7
Reserved
33
Reserved
59
ARDY
85
VCC3
8
ED6
34
EA16
60
DSP2XD
86
CE3
9
DSP_HINT
35
BOOTMODE3
61
PCIMWR_INT
87
Reserved
10
DSP2AOD
36
DQ3
62
ED0
88
Reserved
11
ED2
37
CLKMODE
63
VCC3
89
S_BOOTMODE0
12
SP0SEL
38
JTAGSEL
64
PCI_FLT
90
RDEMPTY
13
BOOTMODE2
39
Reserved
65
LED0
91
Reserved
14
GND
40
DSP_HRDY
66
Reserved
92
AO_ADR4
15
XCNTL1
41
VCC3
67
Reserved
93
S_USER1
16
DQ2
42
PCIMRD_INT
68
CODEC_WR
94
GND
17
Reserved
43
DQ7
69
AO_BE0
95
S_USER2
18
Reserved
44
TBC_RST
70
EXT_RST
96
DB_INT
19
DQ4
45
Reserved
71
OSC_A_EN
97
EA3
20
Reserved
46
BOOTMODE1
72
GND
98
XSTAT0
21
Reserved
47
DQ1
73
OSC_B_EN
99
AO_BE1
22
DQ0
48
ED1
74
VCC5
100
BE0
23
VCC3
49
LED1
75
GND
101
AO_ADR6
24
BOOTMODE0
50
GND
76
HCS
102
AO_ADR5
25
PTBE0
51
N/C
77
ED5
103
N/C
26
LENDIAN
52
N/C
78
RDFIFO
104
N/C
C-4
Overview of the EVM CPLD
Table C–2. TMS320C6x CPLD Pin Definitions (Numerical Pin Order) (Continued)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
105
N/C
131
PCI_INT
157
N/C
183
FLOAT
106
N/C
132
MAN_RST
158
N/C
184
BPCLK
107
VCC3
133
WRFIFO
159
S_CLKSEL
185
GND
108
AO_BE3
134
GND
160
XRDY
186
VCC5
109
AO_BE2
135
DSP_RST
161
EA19
187
TBC_WR
110
BE2
136
BE3
162
EA18
188
TBCA4_HCNTL1
111
PTWR
137
HDS1
163
Reserved
189
TDO
112
XSTAT1
138
CODEC_PD
164
S_BOOTMODE4
190
PTBE3
113
PT_RDY
139
EA4
165
VCC3
191
VCC3
114
Reserved
140
EA5
166
EA17
192
TBCA3_HCNTL0
115
CLKA_DIV2
141
S_ENDIAN
167
PCI_DET
193
PTBE2
116
GND
142
CE1
168
PTNUM1
194
TBCA0_HBE0
117
EA6
143
VCC3
169
AO_ADR3
195
PTBE1
118
S_BOOTMODE2
144
DQ5
170
AO_ADR2
196
Reserved
119
CODEC_IRQ
145
S_JTAGSEL
171
Reserved
197
PT_ADR
120
SW_RST
146
S_CLKMODE
172
WRFULL
198
CODEC_RD
121
TBC_RD
147
DSPCLK
173
EA21
199
ED7
122
PC_INT
148
S_BOOTMODE1
174
GND
200
GND
123
AO_WR
149
PTBURST
175
VCC2BAD
201
TBC_INT
124
AO_RD
150
S_USER0
176
TDI
202
ED3
125
VCC3
151
S_BOOTMODE3
177
DSP_PD
203
DSP2PBD
126
EA2
152
GND
178
EA20
204
NMI
127
TMS
153
PCI_RST
179
VCC5
205
TBC_RDY
128
CE2
154
PTATN
180
GND
206
ED4
129
BE1
155
N/C
181
AWE
207
N/C
130
TBCA1_HBE1
156
N/C
182
BRD_RST
208
N/C
TMS320C6x EVM CPLD Equations
C-5
Overview of the EVM CPLD
Table C–3. TMS320C6x CPLD Pin Definitions (Alphabetical Pin Order)
C-6
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
AO_ADR2
170
CE1
142
DSP2PBD
203
GND
50
AO_ADR3
169
CE2
128
DSP2XD
60
GND
72
AO_ADR4
92
CE2_SDEN
55
DSPCLK
147
GND
75
AO_ADR5
102
CE3
86
EA16
34
GND
82
AO_ADR6
101
CE3_SDEN
56
EA17
166
GND
94
AO_BE0
69
CLKA_DIV2
115
EA18
162
GND
116
AO_BE1
99
CLKMODE
37
EA19
161
GND
134
AO_BE2
109
CODEC_CS
58
EA2
126
GND
152
AO_BE3
108
CODEC_IRQ
119
EA20
178
GND
174
AO_RD
124
CODEC_PD
138
EA21
173
GND
180
AO_SEL
84
CODEC_RD
198
EA3
97
GND
185
AO_WR
123
CODEC_WR
68
EA4
139
GND
200
ARDY
59
DB_INT
96
EA5
140
HCS
76
ARE
3
DQ0
22
EA6
117
HDS1
137
AWE
181
DQ1
47
ED0
62
HRW
79
BE0
100
DQ2
16
ED1
48
JTAGSEL
38
BE1
129
DQ3
36
ED2
11
LED0
65
BE2
110
DQ4
19
ED3
202
LED1
49
BE3
136
DQ5
144
ED4
206
LENDIAN
26
BOOTMODE0
24
DQ6
29
ED5
77
MAN_RST
132
BOOTMODE1
46
DQ7
43
ED6
8
N/C
1
BOOTMODE2
13
DSP_HINT
9
ED7
199
N/C
2
BOOTMODE3
35
DSP_HRDY
40
EXT_RST
70
N/C
51
BOOTMODE4
27
DSP_PD
177
FLOAT
183
N/C
52
BPCLK
184
DSP_RST
135
GND
14
N/C
53
BRD_RST
182
DSP2AOD
10
GND
32
N/C
54
Overview of the EVM CPLD
Table C–3. TMS320C6x CPLD Pin Definitions (Alphabetical Pin Order) (Continued)
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
N/C
103
PTBE2
193
Reserved
171
TCK
30
N/C
104
PTBE3
190
Reserved
196
TDI
176
N/C
105
PTBURST
149
S_BOOTMODE0
89
TDO
189
N/C
106
PTNUM0
80
S_BOOTMODE1
148
TMS
127
N/C
155
PTNUM1
168
S_BOOTMODE2
118
VCC2BAD
175
N/C
156
PTWR
111
S_BOOTMODE3
151
VCC3
5
N/C
157
RDEMPTY
90
S_BOOTMODE4
164
VCC3
23
N/C
158
RDFIFO
78
S_CLKMODE
146
VCC3
41
N/C
207
Reserved
7
S_CLKSEL
159
VCC3
63
N/C
208
Reserved
17
S_ENDIAN
141
VCC3
85
NMI
204
Reserved
18
S_JTAGSEL
145
VCC3
107
OSC_A_EN
71
Reserved
20
S_USER0
150
VCC3
125
OSC_B_EN
73
Reserved
21
S_USER1
93
VCC3
143
PC_INT
122
Reserved
28
S_USER2
95
VCC3
165
PCI_DET
167
Reserved
31
SP0SEL
12
VCC3
191
PCI_FLT
64
Reserved
33
SW_RST
120
VCC5
74
PCI_INT
131
Reserved
39
TBC_INT
201
VCC5
83
PCI_IRQ
4
Reserved
45
TBC_RD
121
VCC5
179
PCI_RST
153
Reserved
57
TBC_RDY
205
VCC5
186
PCIMRD_INT
42
Reserved
66
TBC_RST
44
WRFIFO
133
PCIMWR_INT
61
Reserved
67
TBC_WR
187
WRFULL
172
PT_ADR
197
Reserved
87
TBCA0_HBE0
194
XCNTL0
6
PT_RDY
113
Reserved
88
TBCA1_HBE1
130
XCNTL1
15
PTATN
154
Reserved
91
TBCA2_HHWIL
81
XRDY
160
PTBE0
25
Reserved
114
TBCA3_HCNTL0
192
XSTAT0
98
PTBE1
195
Reserved
163
TBCA4_HCNTL1
188
XSTAT1
112
TMS320C6x EVM CPLD Equations
C-7
EVM CPLD Equations
C.2 EVM CPLD Equations
The following listing provides a table of contents to the CPLD’s source files included in this section.
C-8
CPLD source file
Page
EVM.ABL
D-9
EVMRESET.ABL
D-32
EVMSWMUX.ABL
D-34
EVMCKSEL.ABL
D-37
EVMDECOD.ABL
D-39
EVMINT.ABL
D-50
EVMPCI.ABL
D-56
MODULE EVM
TITLE ’TMS320C6x EVM Top–Level Programmable Logic’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This is the top–level module for the TMS320C6x EVM’s CPLD. It
”defines the CPLD’s pin names, the low–level modules that are used,
”and all inter–module connections. All CPLD registers that are
”memory–mapped into the PCI and DSP memory spaces are implemented
”in this top–level module. The ability to float all CPLD output
”pins to support in–circuit testing is also implemented in this module.
”Sub–module prototypes
EVMRESET interface (BRD_RST_,SW_RST_,VCC2BAD_,PCI_RST_,PCI_DET_,
xreset,dsprst,tbcrst –>
MAN_RST_,DSP_RST_,TBC_RST_,EXT_RST_);
C-9
EVMSWMUX interface
(h_clkmode,h_clksel,h_endian,h_jtagsel,h_user2..h_user0,
swsel,h_bootmode4..h_bootmode0,S_CLKMODE,S_CLKSEL,
S_ENDIAN,S_JTAGSEL,S_USER2..S_USER0,
S_BOOTMODE4..S_BOOTMODE0 –>
BOOTMODE4..BOOTMODE0,CLKMODE,LENDIAN,USER2..USER0,
clksel,JTAGSEL);
EVMCKSEL interface
(CLKA_DIV2,clksel –> osc_a_, osc_b_);
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”REVISIONS
”
04/15/98 – 1. Changed CPLD_REV to 3.
”
2. Added host/DSP semaphores.
”
3. Added OSC B frequency register
”
”
03/11/98 – Changed CPLD_REV to 2
”
”
03/05/98 – Changed CPLD_REV to 1
(RESET,PCI_DET_,PCICLK,DSPCLK,
CE1_,CE2_,CE3_,ARE_,AWE_,EA21..EA16,
ao_bsy,emif_ack,XRDY,ce2sden,ce3sden,CLKMODE –>
DSP2AOD_,DSP2PBD_,DSP2XD_,are_r_,awe_r_,emif_req,
CPLD_CS,CODEC_CS_,CODEC_WR_,CODEC_RD_,ARDY);
EVMINT
interface (RESET,DSP_HINT_,TBC_INT_,PCICLK,PCI_DET_,PCI_IRQ_,
RDEMPTY,WRFULL,CODEC_IRQ, hinten, tbcinten,
dspnmi,nmisel,nmien,pcimren,pcimwen,RDFIFO_,WRFIFO_ –>
PC_INT,NMI,PCI_INT,PCIMRD_INT,PCIMWR_INT);
EVMPCI
interface (RESET,ARE_,AWE_,BE3_,BE2_,BE1_,BE0_,EA16,EA6..EA2,
PCI_DET_,PCICLK,PTATN_,PTBURST_,PTNUM1,PTNUM0,PTWR,
pt_be3_,pt_be2_,pt_be1_,pt_be0_,
pt_addr4,pt_addr3,pt_addr2,pt_addr1, pt_addr0,
TBC_RDY_,DSP_HRDY_,emif_req –>
PCI_FLT_,PT_ADR_,PT_RDY_,AO_SEL_,AO_WR_,AO_RD_,
AO_ADR6..AO_ADR2,AO_BE3_,AO_BE2_,AO_BE1_,AO_BE0_,RDFIFO_,WRFIFO_,
pcireg_oe,pcireg_ce,TBC_WR_,TBC_RD_,
HCS_,HDS1_,HRW,TBCA4_HCNTL1,TBCA3_HCNTL0,TBCA2_HHWIL,
TBCA1_HBE1_,TBCA0_HBE0_,ao_bsy,emif_ack);
”Sub–module instantiations
RESET
functional_block EVMRESET;
”Board, DSP, TBC and daughterboard resets
SW_MUX
functional_block EVMSWMUX;
”HW/SW switch selection mux
CLOCK_SEL functional_block EVMCKSEL;
”DSP clock source selection mux
DECODE
functional_block EVMDECOD;
”Address decode logic and device control
INT
functional_block EVMINT;
”Interrupt control
PCI
functional_block EVMPCI;
”PCI interface control
”INPUTS
”NOTE: Active low signals are indicated with trailing underscores.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Float Outputs Test Input
FLOAT_
pin;
”Floats all outputs to support in–circuit testing
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Resets
BRD_RST_
pin;
”Reset from voltage supervisor
SW_RST_
pin;
”Reset from push button switch
VCC2BAD_
pin;
”VCC bad from the power supervisor
PCI_RST_
pin;
”PCI system reset from PCI controller
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Clocks
DSPCLK
pin;
”DSP’s CLKOUT2
CLKA_DIV2
pin;
”DSP clock source (OSC A) divided by 2
EVM CPLD Equations
C-10
EVMDECOD interface
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From TMS320C6201 DSP
CE1_
pin;
”EMIF CE1 memory space enable
CE2_
pin;
”EMIF CE2 memory space enable
CE3_
pin;
”EMIF CE3 memory space enable
ARE_
pin;
”EMIF asynchronous memory read strobe
AWE_
pin;
”EMIF asynchronous memory write strobe
BE3_
pin;
”EMIF byte 3 enable control
BE2_
pin;
”EMIF byte 2 enable control
BE1_
pin;
”EMIF byte 1 enable control
BE0_
pin;
”EMIF byte 0 enable control
BE = [BE3_, BE2_, BE1_, BE0_];
”EMIF word address bits [21..16], [6..2]
EA21
pin;
EA20
pin;
EA19
pin;
EA18
pin;
EA17
pin;
EA16
pin;
EA6
pin;
EA5
pin;
EA4
pin;
EA3
pin;
EA2
pin;
”Low address is for register selection
EA_LO = [EA6, EA5, EA4, EA3, EA2];
DSP_HRDY_
DSP_HINT_
pin;
pin;
”DSP HPI ready
”DSP HPI host interrupt
DSP_PD
pin;
”DSP power down indication
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
C-11
”From S5933 PCI Controller
BPCLK
pin;
PTATN_
pin;
PTBURST_
pin;
PTNUM1
pin;
PTNUM0
pin;
PTWR
pin;
PCI_IRQ_
pin;
”Buffered PCI clock (33 MHz max.)
”Pass–thru attention indication
”Pass–thru burst indication
”Pass–thru region number (bit 1)
”Pass–thru region number (bit 0)
”Pass–thru access type (R=0, W=1)
”Interrupt to add–on device
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”High address is for device selection
EA_HI = [EA21, EA20, EA19, EA18, EA17, EA16];
pin;
pin;
pin;
pin;
pin;
pin;
pin;
”Pass–thru byte enable 3
”Pass–thru byte enable 2
”Pass–thru byte enable 1
”Pass–thru byte enable 0
”PCI bus detection (0=PCI, 1=Standalone)
”Read FIFO empty flag
”Write FIFO full flag
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From JTAG TBC
TBC_RDY_
TBC_INT_
pin;
pin;
”TBC ready
”TBC interrupt
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From DIP Switch
”Boot mode selection for No–boot, HPI–boot or ROM–boot
S_BOOTMODE4 pin;
”Boot mode 4 (SW2–1)
S_BOOTMODE3 pin;
”Boot mode 3 (SW2–2)
S_BOOTMODE2 pin;
”Boot mode 2 (SW2–3)
S_BOOTMODE1 pin;
”Boot mode 1 (SW2–4)
S_BOOTMODE0 pin;
”Boot mode 0 (SW2–5)
S_BOOTMODE = [S_BOOTMODE4, S_BOOTMODE3, S_BOOTMODE2, S_BOOTMODE1, S_BOOTMODE0];
S_CLKMODE
pin;
”Selects x1 (No PLL) or x4 (PLL) Clock Mode (SW2–6)
S_CLKSEL
S_ENDIAN
pin;
pin;
”Selects output of oscillator A or B (SW2–7)
”Selects big or little endian memory addressing (SW2–8)
S_JTAGSEL
S_USER2
S_USER1
S_USER0
pin;
pin;
pin;
pin;
”Selects internal or
”User–defined switch
”User–defined switch
”User–defined switch
external JTAG emulation
(S2–10)
(S2–11)
(S2–12)
(SW2–9)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From Daughterboard (Expansion Peripheral Interface)
XSTAT1
pin;
”External status 1
XSTAT0
pin;
”External status 0
DB_INT
pin;
”Daughterboard interrupt (EXT_INT7)
XRDY
pin;
”External asynchronous memory access ready
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From CS4231A Audio Codec
CODEC_IRQ
pin;
”Audio codec interrupt
CODEC_PD_
pin;
”Audio codec power down indication
EVM CPLD Equations
C-12
PTBE3_
PTBE2_
PTBE1_
PTBE0_
PCI_DET_
RDEMPTY
WRFULL
”BIDIR
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From TMS320C6201 DSP
”EMIF data bits [7..0]
ED7
pin;
ED6
pin;
ED5
pin;
ED4
pin;
ED3
pin;
ED2
pin;
ED1
pin;
ED0
pin;
ED = [ED7, ED6, ED5, ED4, ED3, ED2, ED1, ED0];
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”OUTPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To Data Buffers/Transceivers
DSP2AOD_
pin istype ’com’;
DSP2PBD_
pin istype ’com’;
DSP2XD_
pin istype ’com’;
”Connects DSP to add–on bus
”Connects DSP to peripheral bus
”Connects DSP to external bus
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
C-13
”To JTAG TBC and
TBCA0_HBE0_
TBCA1_HBE1_
TBCA2_HHWIL
TBCA3_HCNTL0
TBCA4_HCNTL1
DSP
pin
pin
pin
pin
pin
HPI
istype
istype
istype
istype
istype
’com’;
’com’;
’com’;
’com’;
’com’;
”TBC
”TBC
”TBC
”TBC
”TBC
address
address
address
address
address
bit
bit
bit
bit
bit
0
1
2
3
4
/
/
/
/
/
HPI
HPI
HPI
HPI
HPI
byte enable 0
byte enable 1
half–word select
control 0
control 1
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”From S5933 PCI Controller
”Add–on data bits [7..0]
DQ7
pin;
DQ6
pin;
DQ5
pin;
DQ4
pin;
DQ3
pin;
DQ2
pin;
DQ1
pin;
DQ0
pin;
DQ = [DQ7..DQ0];
”To HPI
HCS_
HDS1_
HRW
pin istype ’com’;
pin istype ’com’;
pin istype ’com’
”HPI chip select
”HPI data strobe 1
”HPI read (1) / write (0) select
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To JTAG TBC
TBC_WR_
TBC_RD_
TBC_RST_
pin istype ’com’;
pin istype ’com’;
pin istype ’com’;
”TBC write strobe
”TBC read strobe
”TBC hardware reset
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To S5933 PCI Controller
PCI_FLT_
pin istype
PT_ADR_
pin istype
PT_RDY_
pin istype
AO_SEL_
pin istype
AO_WR_
pin istype
AO_RD_
pin istype
’com’;
’com’;
’com’;
’com’;
’com’;
’com’;
”Float PCI controller outputs
”Pass–thru address request
”Pass–thru ready indication
”Add–on select for register access
”Add–on write strobe
”Add–on read strobe
”Add–on address bits [6..2]
AO_ADR6
pin istype ’com’;
AO_ADR5
pin istype ’com’;
AO_ADR4
pin istype ’com’;
AO_ADR3
pin istype ’com’;
AO_ADR2
pin istype ’com’;
AO_ADR = [AO_ADR6..AO_ADR2];
”Add–on byte enables [3..0]
AO_BE3_
pin istype ’com’;
AO_BE2_
pin istype ’com’;
AO_BE1_
pin istype ’com’;
AO_BE0_
pin istype ’com’;
RDFIFO_
WRFIFO_
pin istype ’com’;
pin istype ’com’;
PC_INT
pin istype ’com’;
”Read FIFO strobe
”Write FIFO strobe
”Add–on–to–PCI interrupt
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
EVM CPLD Equations
C-14
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To TMS320C6201 DSP
”Boot mode selection for No–boot, HPI–boot or ROM–boot
BOOTMODE4
pin istype ’com’;
BOOTMODE3
pin istype ’com’;
BOOTMODE2
pin istype ’com’;
BOOTMODE1
pin istype ’com’;
BOOTMODE0
pin istype ’com’;
CLKMODE
LENDIAN
NMI
PCI_INT
PCIMRD_INT
PCIMWR_INT
DSP_RST_
ARDY
pin
pin
pin
pin
pin
pin
pin
pin
istype
istype
istype
istype
istype
istype
istype
istype
’com’;
’com’;
’com’;
’com’;
’com’;
’com’;
’com’;
’com’;
”Clock mode
”Little–endian selection
”NMI interrupt from codec or host
”Interrupt from PCI controller (EXT_INT4)
”PCI master read interrupt (EXT_INT5)
”PCI master write interrupt (EXT_INT6)
”DSP reset
”EMIF asynchronous memory access ready
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To Multiplexers
OSC_A_EN_
pin istype ’com’;
OSC_B_EN_
pin istype ’com’;
”DSP oscillator A enable
”DSP oscillator B enable
JTAGSEL
pin istype ’com’;
”JTAG selection (int/ext)
SP0SEL
pin istype ’reg_d, dc, buffer’;
”McBSP0 selection
”To User LEDs
LED1_
LED0_
pin istype ’reg_d, dc, buffer’;
pin istype ’reg_d, dc, buffer’;
”User LED 1 control
”User LED 0 control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To Daughterboard (Expansion Peripheral Interface)
XCNTL1
pin istype ’reg_d, dc, buffer’; ”External control 1
XCNTL0
pin istype ’reg_d, dc, buffer’; ”External control 0
EXT_RST_
pin istype ’com’;
”External reset
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
C-15
”To CS4231A Audio Codec
CODEC_CS_
pin istype ’com’;
CODEC_WR_
pin istype ’com’;
CODEC_RD_
pin istype ’com’;
”Codec chip select
”Codec write strobe
”Codec read strobe
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
pin istype ’com’;
pin istype ’com’;
”Bank 1 (CE3) SDRAM enable (CKE)
”Bank 0 (CE2) SDRAM enable (CKE)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”To Voltage Supervisor
MAN_RST_
pin istype ’com’;
”Pushbutton or PCI system reset
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Internal Nodes
CPLD_CS
node istype ’com’;
”CPLD DSP register chip select
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Internal Registers
”DSP–mapped register bits
xreset
node istype ’reg_d, dc, buffer’; ”External (DB) reset
nmisel
node istype ’reg_d, dc, buffer’; ”NMI selection (codec/host)
nmien
node istype ’reg_d, dc, buffer’; ”NMI interrupt enable
pcimwen
node istype ’reg_d, dc, buffer’; ”PCI master write enable
pcimren
node istype ’reg_d, dc, buffer’; ”PCI master read enable
ce2sden
node istype ’reg_d, dc, buffer’; ”CE2 SDRAM enable
ce3sden
node istype ’reg_d, dc, buffer’; ”CE3 SDRAM enable
dspsem0
node istype ’reg_d, dc, buffer’; ”DSP semaphore 0
dspsem1
node istype ’reg_d, dc, buffer’; ”DSP semaphore 1
”PCI–mapped register bits
dspnmi
node istype
tbcinten
node istype
hinten
node istype
tbcrst
node istype
dsprst
node istype
h_clkmode
node istype
h_clksel
node istype
h_endian
node istype
h_jtagsel
node istype
h_user2
node istype
h_user1
node istype
h_user0
node istype
swsel
node istype
h_bootmode4 node istype
h_bootmode3 node istype
h_bootmode2 node istype
h_bootmode1 node istype
h_bootmode0 node istype
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
’reg_d,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
dc,
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
”Host NMI to DSP
”Host TBC interrupt enable
”Host DSP host interrupt enable
”Host TBC reset
”Host DSP reset
”Clock mode software switch
”Clock selection software switch
”Endian software switch
”JTAG selection software switch
”User–defined software switch 2
”User–defined software switch 1
”User–defined software switch 0
”DIP or software switch selection
”Host boot mode selection [4..0]
EVM CPLD Equations
C-16
”To SDRAMs
CE3_SDEN
CE2_SDEN
h_bootmode = [h_bootmode4..h_bootmode0] ;
hostsem0
node istype ’reg_d, dc, buffer’; ”Host semaphore 0
hostsem1
node istype ’reg_d, dc, buffer’; ”Host semaphore 1
”Registered pass–thru address used to drive address to TBC, CPLD REG and HPI.
pt_addr4
node istype ’reg_d, dc, buffer’;
pt_addr3
node istype ’reg_d, dc, buffer’;
pt_addr2
node istype ’reg_d, dc, buffer’;
pt_addr1
node istype ’reg_d, dc, buffer’;
pt_addr0
node istype ’reg_d, dc, buffer’;
pt_addr = [pt_addr4..pt_addr0] ;
”Registered pass–thru byte enables used to drive HPI BE’s.
pt_be3_
node istype ’reg_d, dc, buffer’;
pt_be2_
node istype ’reg_d, dc, buffer’;
pt_be1_
node istype ’reg_d, dc, buffer’;
pt_be0_
node istype ’reg_d, dc, buffer’;
pt_be_ = [pt_be3_,pt_be2_,pt_be1_,pt_be0_];
”Constants
h,l,x = 1, 0, .X. ;
”Revision Control
CPLD_REV
= ^h03;
”Oscillator B Frequency
OSC_B_FREQ = 0;
”0 defaults to 40 MHz
”Global reset
reset = !BRD_RST_;
”Internal active–high reset alias
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DSP–Mapped Registers
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
C-17
”Register Offsets [EA6..EA2]
MAP0
DSP_CNTL_ADR
= 0; ”CE1:0x0138xxx0
DSP_STAT_ADR
= 1; ”CE1:0x0138xxx4
DSP_DIPOPT_ADR
= 2; ”CE1:0x0138xxx8
DSP_DIPBOOT_ADR = 3; ”CE1:0x0138xxxC
DSP_DSPOPT_ADR
= 4; ”CE1:0x0138xx10
/
/
/
/
/
MAP1
0x0178xxx0
0x0178xxx4
0x0178xxx8
0x0178xxxC
0x0178xx10
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Reserved Register Values
PCI_RSVD
= ^h00;
DSP_RSVD
= ^h00;
=
=
=
=
=
=
5;
6;
7;
8;
9;
10;
”CE1:0x0138xx14
”CE1:0x0138xx18
”CE1:0x0138xx1C
”CE1:0x0138xx20
”CE1:0x0138xx24
”CE1:0x0138xx28
/
/
/
/
/
/
EVM CPLD Equations
C-18
DSP_DSPBOOT_ADR
DSP_FIFOSTAT_ADR
DSP_SDCNTL_ADR
DSP_OSCB_ADR
DSP_SEM0_ADR
DSP_SEM1_ADR
0x0178xx14
0x0178xx18
0x0178xx1C
0x0178xx20
0x0178xx24
0x0178xx28
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Bit Definitions
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
dsp_cntl
”
= [XCNTL1, XCNTL0,
RW
RW
dsp_stat
= [XSTAT1, XSTAT0, DB_INT, dspnmi,
”
dsp_dipopt
”
R
xreset, nmien, nmisel, SP0SEL, !LED1_, !LED0_];
RW
RW
RW
RW
RW
RW
R
R
!CODEC_PD_,
R
R
CODEC_IRQ, !PCI_IRQ_, !PCI_DET_];
R
R
R
= [0, S_CLKMODE, S_CLKSEL, S_ENDIAN, S_JTAGSEL, S_USER2, S_USER1, S_USER0];
R
R
R
R
R
R
R
R
dsp_dipboot = [0, 0, 0, S_BOOTMODE4, S_BOOTMODE3, S_BOOTMODE2, S_BOOTMODE1, S_BOOTMODE0];
”
R
R
R
R
R
R
R
R
dsp_dspopt = [0, CLKMODE, SW_MUX.clksel, LENDIAN, JTAGSEL, SW_MUX.USER2, SW_MUX.USER1,
SW_MUX.USER0];
”
R
R
R
R
R
R
R
R
dsp_dspboot = [swsel, 0, 0, BOOTMODE4, BOOTMODE3, BOOTMODE2, BOOTMODE1, BOOTMODE0];
”
R
R
R
R
R
R
R
R
dsp_fifostat= [0, 0, PCIMRD_INT, PCIMWR_INT, RDEMPTY, WRFULL, pcimren, pcimwen];
”
R
R
R
R
R
R
RW
RW
dsp_sdcntl = [0, 0, 0, 0, 0, 0, ce3sden, ce2sden];
”
R
R
R
R
R
R
RW
RW
dsp_sem0
”
= [0, 0, 0, 0, 0, 0, 0, dspsem0];
R R R R R R R
RW
dsp_sem1
”
= [0, 0, 0, 0, 0, 0, 0, dspsem1];
R R R R R R R
RW
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Clock enables for DSP register writes
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”CPLD_CS is active when EMIF access to 0x0138xxxx (MAP0)/0x0178xxxx (MAP1)
”EA[6..2] select register offset
dsp_cntl_ce
dsp_stat_ce
dsp_dipopt_ce
dsp_dipboot_ce
dsp_dspopt_ce
dsp_dspboot_ce
dsp_fifostat_ce
dsp_sdcntl_ce
dsp_sem0_ce
dsp_sem1_ce
=
=
=
=
=
=
=
=
=
=
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
CPLD_CS
&
&
&
&
&
&
&
&
&
&
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
(EA_LO
==
==
==
==
==
==
==
==
==
==
DSP_CNTL_ADR);
DSP_STAT_ADR);
DSP_DIPOPT_ADR);
DSP_DIPBOOT_ADR);
DSP_DSPOPT_ADR);
DSP_DSPBOOT_ADR);
DSP_FIFOSTAT_ADR);
DSP_SDCNTL_ADR);
DSP_SEM0_ADR);
DSP_SEM1_ADR);
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”PCI–Mapped Registers
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”BAR2+0x00
”BAR2+0x04
”BAR2+0x08
”BAR2+0x0C
”BAR2+0x10
”BAR2+0x14
”BAR2+0x18
”BAR2+0x1C
”BAR2+0x20
”BAR2+0x24
”BAR2+0x28
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Register bit definitions
pci_cntl
= [dspnmi, tbcinten, hinten, !TBC_RDY_, !TBC_INT_, !DSP_HINT_, tbcrst,
”
RW
RW
RW
R
R
R
RW
dsprst];
RW
pci_stat
”
= [0, !VCC2BAD_, !CODEC_PD_, DSP_PD, XCNTL1, XCNTL0, !LED1_, !LED0_];
R
R
R
R
R
R
R
pci_swopt
”
= [0, h_clkmode, h_clksel, h_endian, h_jtagsel, h_user2, h_user1, h_user0];
R
RW
RW
RW
RW
RW
RW
RW
pci_swboot
”
= [swsel, 0, 0, h_bootmode4, h_bootmode3, h_bootmode2, h_bootmode1, h_bootmode0];
RW
R R
RW
RW
RW
RW
RW
pci_dipopt
”
= [0, S_CLKMODE, S_CLKSEL, S_ENDIAN, S_JTAGSEL, S_USER2, S_USER1, S_USER0];
R
R
R
R
R
R
R
R
C-19
pci_dipboot = [0, 0, 0, S_BOOTMODE4, S_BOOTMODE3, S_BOOTMODE2, S_BOOTMODE1, S_BOOTMODE0];
”
R R R
R
R
R
R
R
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Register offsets [A6..A2]
PCI_CNTL_ADR
= 0;
PCI_STAT_ADR
= 1;
PCI_SWOPT_ADR
= 2;
PCI_SWBOOT_ADR
= 3;
PCI_DIPOPT_ADR
= 4;
PCI_DIPBOOT_ADR = 5;
PCI_DSPOPT_ADR
= 6;
PCI_DSPBOOT_ADR = 7;
PCI_CPLDREV_ADR = 8;
PCI_SEM0_ADR
= 9;
PCI_SEM1_ADR
= 10;
= [0, CLKMODE, SW_MUX.clksel, LENDIAN, JTAGSEL, SW_MUX.USER2, SW_MUX.USER1,
R
R
R
R
R
R
R
pci_dspboot = [0, 0, 0, BOOTMODE4, BOOTMODE3, BOOTMODE2, BOOTMODE1, BOOTMODE0];
”
R R R
R
R
R
R
R
pci_cpldrev = CPLD_REV;
pci_sem0
”
= [0, 0, 0, 0, 0, 0, 0, hostsem0];
R R R R R R R
RW
pci_sem1
”
= [0, 0, 0, 0, 0, 0, 0, hostsem1];
R R R R R R R
RW
pci_reserve = PCI_RSVD;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Clock enables for
pci_cntl_ce
=
pci_swopt_ce =
pci_swboot_ce =
pci_sem0_ce
=
pci_sem1_ce
=
PCI register writes
PCI.pcireg_ce & (pt_addr
PCI.pcireg_ce & (pt_addr
PCI.pcireg_ce & (pt_addr
PCI.pcireg_ce & (pt_addr
PCI.pcireg_ce & (pt_addr
==
==
==
==
==
PCI_CNTL_ADR);
PCI_SWOPT_ADR);
PCI_SWBOOT_ADR);
PCI_SEM0_ADR);
PCI_SEM1_ADR);
Equations
”=======================================================================
”
ABEL Low–level Module Connections
”=======================================================================
”The following several sections define the connections between this
”top–level ABEL source module and the low–level modules, as well as
”connections between low–level modules. These connections are similar
”to a high–level block diagram definition between modules.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”RESET I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Reset Inputs
RESET.BRD_RST_
RESET.SW_RST_
RESET.VCC2BAD_
RESET.PCI_RST_
RESET.PCI_DET_
RESET.xreset
RESET.dsprst
RESET.tbcrst
=
=
=
=
=
=
=
=
BRD_RST_;
SW_RST_;
VCC2BAD_;
PCI_RST_;
PCI_DET_;
xreset;
dsprst;
tbcrst;
R
EVM CPLD Equations
C-20
pci_dspopt
SW_MUX.USER0];
”
”Reset Outputs
MAN_RST_ = RESET.MAN_RST_;
DSP_RST_ = RESET.DSP_RST_;
TBC_RST_ = RESET.TBC_RST_;
EXT_RST_ = RESET.EXT_RST_;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”SW_MUX I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Switch Multiplexer Inputs
SW_MUX.h_clkmode
= h_clkmode;
SW_MUX.h_clksel
= h_clksel;
SW_MUX.h_endian
= h_endian;
SW_MUX.h_jtagsel
= h_jtagsel;
SW_MUX.h_user2
= h_user2;
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
h_user1;
h_user0;
swsel;
h_bootmode4;
h_bootmode3;
h_bootmode2;
h_bootmode1;
h_bootmode0;
S_CLKMODE;
S_CLKSEL;
S_ENDIAN;
S_JTAGSEL;
S_USER2;
S_USER1;
S_USER0;
S_BOOTMODE4;
S_BOOTMODE3;
S_BOOTMODE2;
S_BOOTMODE1;
S_BOOTMODE0;
C-21
”Switch Multiplexer Outputs
BOOTMODE4 = SW_MUX.BOOTMODE4;
BOOTMODE3 = SW_MUX.BOOTMODE3;
BOOTMODE2 = SW_MUX.BOOTMODE2;
BOOTMODE1 = SW_MUX.BOOTMODE1;
BOOTMODE0 = SW_MUX.BOOTMODE0;
CLKMODE
= SW_MUX.CLKMODE;
LENDIAN
= SW_MUX.LENDIAN;
JTAGSEL
= SW_MUX.JTAGSEL & !PCI_DET_; ”force ext JTAG when not in PCI slot
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
SW_MUX.h_user1
SW_MUX.h_user0
SW_MUX.swsel
SW_MUX.h_bootmode4
SW_MUX.h_bootmode3
SW_MUX.h_bootmode2
SW_MUX.h_bootmode1
SW_MUX.h_bootmode0
SW_MUX.S_CLKMODE
SW_MUX.S_CLKSEL
SW_MUX.S_ENDIAN
SW_MUX.S_JTAGSEL
SW_MUX.S_USER2
SW_MUX.S_USER1
SW_MUX.S_USER0
SW_MUX.S_BOOTMODE4
SW_MUX.S_BOOTMODE3
SW_MUX.S_BOOTMODE2
SW_MUX.S_BOOTMODE1
SW_MUX.S_BOOTMODE0
”Clock Select Inputs
CLOCK_SEL.CLKA_DIV2 = CLKA_DIV2;
CLOCK_SEL.clksel
= SW_MUX.clksel;
”Clock Select Outputs
OSC_A_EN_ = CLOCK_SEL.osc_a_;
OSC_B_EN_ = CLOCK_SEL.osc_b_;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DECODE I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Decode Inputs
DECODE.RESET
DECODE.PCI_DET_
DECODE.PCICLK
DECODE.DSPCLK
DECODE.CE1_
DECODE.CE2_
DECODE.CE3_
DECODE.ARE_
DECODE.AWE_
DECODE.EA21
DECODE.EA20
DECODE.EA19
DECODE.EA18
DECODE.EA17
DECODE.EA16
DECODE.ao_bsy
DECODE.emif_ack
DECODE.XRDY
DECODE.ce2sden
DECODE.ce3sden
DECODE.CLKMODE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
reset;
PCI_DET_;
BPCLK;
DSPCLK;
CE1_;
CE2_;
CE3_;
ARE_;
AWE_;
EA21;
EA20;
EA19;
EA18;
EA17;
EA16;
PCI.ao_bsy;
PCI.emif_ack;
XRDY;
ce2sden;
ce3sden;
SW_MUX.CLKMODE;
”Decode Outputs
DSP2AOD_ = DECODE.DSP2AOD_;
DSP2PBD_ = DECODE.DSP2PBD_;
DSP2XD_
= DECODE.DSP2XD_;
CPLD_CS
= DECODE.CPLD_CS;
CODEC_CS_ = DECODE.CODEC_CS_;
CODEC_WR_ = DECODE.CODEC_WR_;
EVM CPLD Equations
C-22
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”CLOCK_SEL I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CODEC_RD_ = DECODE.CODEC_RD_;
ARDY
= DECODE.ARDY;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”INT I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Interrupt Inputs
INT.RESET
=
INT.DSP_HINT_ =
INT.TBC_INT_ =
INT.PCICLK
=
INT.PCI_DET_ =
”Interrupt Outputs
PC_INT
=
NMI
=
PCI_INT
=
PCIMRD_INT
=
PCIMWR_INT
=
PCI_IRQ_;
RDEMPTY;
WRFULL;
CODEC_IRQ;
hinten;
tbcinten;
dspnmi;
nmisel;
nmien;
pcimren;
pcimwen;
PCI.RDFIFO_;
PCI.WRFIFO_;
INT.PC_INT;
INT.NMI;
INT.PCI_INT;
INT.PCIMRD_INT;
INT.PCIMWR_INT;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”PCI I/O Connections
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
C-23
”PCI Control
PCI.RESET
PCI.ARE_
PCI.AWE_
PCI.BE3_
PCI.BE2_
PCI.BE1_
PCI.BE0_
Inputs
= reset;
= DECODE.are_r_;
= DECODE.awe_r_;
= BE3_;
= BE2_;
= BE1_;
= BE0_;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
INT.PCI_IRQ_ =
INT.RDEMPTY =
INT.WRFULL
=
INT.CODEC_IRQ =
INT.hinten
=
INT.tbcinten =
INT.dspnmi
=
INT.nmisel
=
INT.nmien
=
INT.pcimren =
INT.pcimwen =
INT.RDFIFO_ =
INT.WRFIFO_ =
reset;
DSP_HINT_;
TBC_INT_;
BPCLK;
PCI_DET_;
=
=
=
=
=
=
=
=
=
=
=
=
=
PCI.pt_be3_ =
PCI.pt_be2_ =
PCI.pt_be1_ =
PCI.pt_be0_ =
PCI.pt_addr4 =
PCI.pt_addr3 =
PCI.pt_addr2 =
PCI.pt_addr1 =
PCI.pt_addr0 =
PCI.TBC_RDY_ =
PCI.DSP_HRDY_ =
PCI.emif_req =
”PCI Control
PCI_FLT_
PT_ADR_
PT_RDY_
AO_SEL_
AO_WR_
AO_RD_
AO_ADR6
AO_ADR5
AO_ADR4
AO_ADR3
AO_ADR2
AO_BE3_
AO_BE2_
AO_BE1_
AO_BE0_
RDFIFO_
WRFIFO_
EA16;
EA6;
EA5;
EA4;
EA3;
EA2;
PCI_DET_;
BPCLK;
PTATN_;
PTBURST_;
PTNUM1;
PTNUM0;
PTWR;
pt_be3_;
pt_be2_;
pt_be1_;
pt_be0_;
pt_addr4;
pt_addr3;
pt_addr2;
pt_addr1;
pt_addr0;
TBC_RDY_;
DSP_HRDY_;
DECODE.emif_req;
Outputs
= PCI.PCI_FLT_;
= PCI.PT_ADR_;
= PCI.PT_RDY_;
= PCI.AO_SEL_;
= PCI.AO_WR_;
= PCI.AO_RD_;
= PCI.AO_ADR6;
= PCI.AO_ADR5;
= PCI.AO_ADR4;
= PCI.AO_ADR3;
= PCI.AO_ADR2;
= PCI.AO_BE3_;
= PCI.AO_BE2_;
= PCI.AO_BE1_;
= PCI.AO_BE0_;
= PCI.RDFIFO_;
= PCI.WRFIFO_;
EVM CPLD Equations
C-24
PCI.EA16
PCI.EA6
PCI.EA5
PCI.EA4
PCI.EA3
PCI.EA2
PCI.PCI_DET_
PCI.PCICLK
PCI.PTATN_
PCI.PTBURST_
PCI.PTNUM1
PCI.PTNUM0
PCI.PTWR
TBC_WR_
TBC_RD_
HCS_
HDS1_
HRW
TBCA4_HCNTL1
TBCA3_HCNTL0
TBCA2_HHWIL
TBCA1_HBE1_
TBCA0_HBE0_
=
=
=
=
=
=
=
=
=
=
PCI.TBC_WR_;
PCI.TBC_RD_;
PCI.HCS_;
PCI.HDS1_;
PCI.HRW;
PCI.TBCA4_HCNTL1;
PCI.TBCA3_HCNTL0;
PCI.TBCA2_HHWIL;
PCI.TBCA1_HBE1_;
PCI.TBCA0_HBE0_;
”=================================================================================
” Latch Pass–Thru Address and Byte Enables
”=================================================================================
”Pass–thru address latch
”Address is latched on rising edge of PCI clock when PT_ADR_ is asserted
pt_addr.ap
= reset;
pt_addr.clk = BPCLK;
pt_addr.ce
= !PT_ADR_;
pt_addr
:= [DQ6, DQ5, DQ4, DQ3, DQ2];
”=================================================================================
” DSP–mapped Registers
”=================================================================================
C-25
”DSP–mapped
when
else
else
else
else
else
else
else
else
else
else
else
register reads
(EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
when (EA_LO ==
DSP_CNTL_ADR)
DSP_STAT_ADR)
DSP_DIPOPT_ADR)
DSP_DIPBOOT_ADR)
DSP_DSPOPT_ADR)
DSP_DSPBOOT_ADR)
DSP_FIFOSTAT_ADR)
DSP_SDCNTL_ADR)
DSP_OSCB_ADR)
DSP_SEM0_ADR)
DSP_SEM1_ADR)
then
then
then
then
then
then
then
then
then
then
then
{ED
{ED
{ED
{ED
{ED
{ED
{ED
{ED
{ED
{ED
{ED
{ED
=
=
=
=
=
=
=
=
=
=
=
=
dsp_cntl;}
dsp_stat;}
dsp_dipopt;}
dsp_dipboot;}
dsp_dspopt;}
dsp_dspboot;}
dsp_fifostat;}
dsp_sdcntl;}
OSC_B_FREQ;}
dsp_sem0;}
dsp_sem1;}
DSP_RSVD;}
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Pass–thru byte enables latch
”Byte enables are latched on rising edge of PCI clock when PT_ADR is asserted
pt_be_.ap
= reset;
pt_be_.clk
= BPCLK;
pt_be_.ce
= !PT_ADR_;
pt_be_
:= [PTBE3_,PTBE2_,PTBE1_,PTBE0_];
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DSP–mapped register writes
”Control Register (CNTL)
XCNTL1
:= ED7;
XCNTL1.ar = reset;
XCNTL1.ce = dsp_cntl_ce;
XCNTL1.clk = AWE_;
”CNTL – bit 7
”default to 0
XCNTL0
:=
XCNTL0.ar =
XCNTL0.ce =
XCNTL0.clk =
ED6;
reset;
dsp_cntl_ce;
AWE_;
”CNTL – bit 6
”default to 0
xreset
:=
xreset.ar =
xreset.ce =
xreset.clk =
ED5;
reset;
dsp_cntl_ce;
AWE_;
”CNTL – bit 5
”default to no ext. reset
nmien
:= ED4;
nmien.ar
= reset;
nmien.ce
= dsp_cntl_ce;
nmien.clk = AWE_;
”CNTL – bit 4
”default to NMI disabled
nmisel
:=
nmisel.ar =
nmisel.ce =
nmisel.clk =
ED3;
reset;
dsp_cntl_ce;
AWE_;
”CNTL – bit 3
”default to NMI from host
SP0SEL
:=
SP0SEL.ar =
SP0SEL.ce =
SP0SEL.clk =
ED2;
reset;
dsp_cntl_ce;
AWE_;
”CNTL – bit 2
”default to McBSP0 –> DB
LED1_
:= !ED1;
LED1_.ap
= reset;
LED1_.ce
= dsp_cntl_ce;
LED1_.clk = AWE_;
”CNTL – bit 1
”default to LED off
LED0_
:= !ED0;
LED0_.ap
= reset;
LED0_.ce
= dsp_cntl_ce;
LED0_.clk = AWE_;
”CNTL – bit 0
”default to LED off
EVM CPLD Equations
C-26
”DSP–mapped register output enable
”Active when EMIF read to CE1:0x01380000–0x0138FFFF range (CPLD regs)
”
(CE1:0x01780000–0x0178FFFF for MAP1)
ED.oe = CPLD_CS & !ARE_;
”PCI FIFO Status Register (FIFOSTAT)
pcimren
:= ED1;
”FIFOSTAT – bit 1
pcimren.ar = reset;
”default to PCI bus master read int disabled
pcimren.ce = dsp_fifostat_ce;
pcimren.clk= AWE_;
pcimwen
:=
pcimwen.ar =
pcimwen.ce =
pcimwen.clk=
ED0;
reset;
dsp_fifostat_ce;
AWE_;
”FIFOSTAT – bit 0
”default to PCI bus master write int disabled
”SDRAM Control Register (SDCNTL)
ce3sden
:= ED1;
”SDCNTL – bit 1
ce3sden.ap = reset;
”default to CE2 SDRAM enabled
ce3sden.ce = dsp_sdcntl_ce;
ce3sden.clk= AWE_;
CE3_SDEN
= ce3sden & !reset;
”disable SDRAM during reset for low power
ce2sden
:=
ce2sden.ap =
ce2sden.ce =
ce2sden.clk=
CE2_SDEN
=
ED0;
reset;
dsp_sdcntl_ce;
AWE_;
ce2sden & !reset;
”SDCNTL – bit 0
”default to CE3 SDRAM enabled
”disable SDRAM during reset for low power
dspsem1
:=
dspsem1.ar =
dspsem1.ce =
dspsem1.clk =
ED0;
reset # hostsem1;
dsp_sem1_ce;
AWE_;
”DSPSEM1 – bit 0
”DSP semaphore cleared at reset
”=================================================================================
” PCI–mapped Registers
”=================================================================================
”PCI–mapped register reads
C-27
when
else
else
else
else
else
else
when
when
when
when
when
when
(pt_addr
(pt_addr
(pt_addr
(pt_addr
(pt_addr
(pt_addr
(pt_addr
==
==
==
==
==
==
==
PCI_CNTL_ADR)
PCI_STAT_ADR)
PCI_SWOPT_ADR)
PCI_SWBOOT_ADR)
PCI_DIPOPT_ADR)
PCI_DIPBOOT_ADR)
PCI_DSPOPT_ADR)
then
then
then
then
then
then
then
{DQ
{DQ
{DQ
{DQ
{DQ
{DQ
{DQ
=
=
=
=
=
=
=
pci_cntl;}
pci_stat;}
pci_swopt;}
pci_swboot;}
pci_dipopt;}
pci_dipboot;}
pci_dspopt;}
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”DSP Semaphore Registers (DSPSEMx)
dspsem0
:= ED0;
”DSPSEM0 – bit 0
dspsem0.ar = reset # hostsem0; ”DSP semaphore cleared at reset
dspsem0.ce = dsp_sem0_ce;
dspsem0.clk = AWE_;
when
when
when
when
(pt_addr
(pt_addr
(pt_addr
(pt_addr
==
==
==
==
PCI_DSPBOOT_ADR)
PCI_CPLDREV_ADR)
PCI_SEM0_ADR)
PCI_SEM1_ADR)
then {DQ = pci_dspboot;}
then {DQ = pci_cpldrev;}
then {DQ = pci_sem0;}
then {DQ = pci_sem1;}
{DQ = pci_reserve;}
”PCI add–on bus output enable when pcireg_oe set active
DQ.oe = PCI.pcireg_oe;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”PCI–mapped register writes
”EVM Control Register (CNTL)
dspnmi
:= DQ7;
dspnmi.ar
= reset;
dspnmi.ce
= pci_cntl_ce;
dspnmi.clk
= BPCLK;
”CNTL – bit 7
”default to no NMI
tbcinten
:=
tbcinten.ar =
tbcinten.ce =
tbcinten.clk =
DQ6;
reset;
pci_cntl_ce;
BPCLK;
”CNTL – bit 6
”default to TBC interrupt disabled
hinten
hinten.ar
hinten.ce
hinten.clk
:=
=
=
=
DQ5;
reset;
pci_cntl_ce;
BPCLK;
”CNTL – bit 5
”default to DSP host interrupt disabled
tbcrst
tbcrst.ar
tbcrst.ce
tbcrst.clk
:=
=
=
=
DQ1;
reset;
pci_cntl_ce;
BPCLK;
”CNTL – bit 1
”default to no TBC reset
dsprst
dsprst.ar
dsprst.ce
dsprst.clk
:=
=
=
=
DQ0;
reset;
pci_cntl_ce;
BPCLK;
”CNTL – bit 0
”default to no DSP reset
”Software Switch User Options Register (SW_OPT)
h_clkmode
:= DQ6;
”SWOPT – bit 6
h_clkmode.ar = reset;
”default to x4 clock mode
h_clkmode.ce = pci_swopt_ce;
h_clkmode.clk= BPCLK;
h_clksel
:=
h_clksel.ar =
h_clksel.ce =
h_clksel.clk =
DQ5;
reset;
pci_swopt_ce;
BPCLK;
”SWOPT – bit 5
”default to OSC A–33.25 MHz
EVM CPLD Equations
C-28
else
else
else
else
else
h_endian
:= DQ4;
h_endian.ar = reset;
h_endian.ce = pci_swopt_ce;
h_endian.clk= BPCLK;
”SWOPT – bit 4
”default to little endian
h_jtagsel
:=
h_jtagsel.ar =
h_jtagsel.ce =
h_jtagsel.clk=
”SWOPT – bit 3
”default to external XDS510
DQ3;
reset;
pci_swopt_ce;
BPCLK;
h_user2
:= DQ2;
h_user2.ar
= reset;
h_user2.ce
= pci_swopt_ce;
h_user2.clk = BPCLK;
”SWOPT – bit 2
”default to USER2=0
h_user1
:= DQ1;
h_user1.ar
= reset;
h_user1.ce
= pci_swopt_ce;
h_user1.clk = BPCLK;
”SWOPT – bit 1
”default to USER1=0
h_user0
:= DQ0;
h_user0.ar
= reset;
h_user0.ce
= pci_swopt_ce;
h_user0.clk = BPCLK;
”SWOPT – bit 0
”default to USER0=0
”SWBOOT – bits 4–0
”Default to Boot Mode 5 (No–Boot,Internal, MAP1)
h_bootmode
:= [DQ4, DQ3, DQ2, DQ1, DQ0];
h_bootmode4.ar = reset;
h_bootmode3.ar = reset;
h_bootmode2.ap = reset;
h_bootmode1.ar = reset;
h_bootmode0.ap = reset;
h_bootmode.ce = pci_swboot_ce;
h_bootmode.clk = BPCLK;
C-29
”Host Semaphore
hostsem0
:=
hostsem0.ar
=
hostsem0.ce
=
hostsem0.clk =
Registers (HOSTSEMx)
DQ0;
”HOSTSEM0 – bit 0
reset # dspsem0; ”host semaphore cleared at reset
pci_sem0_ce;
BPCLK;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Software Switch Boot Mode Register (SWBOOT)
swsel
:= DQ7;
”SWBOOT – bit 7
swsel.ar
= reset;
”default to DIP switch control
swsel.ce
= pci_swboot_ce;
swsel.clk
= BPCLK;
”HOSTSEM1 – bit 0
”host semaphore cleared at reset
”=======================================================================
” Float Output Control (for testing)
”=======================================================================
”Outputs enabled when FLOAT_ is high (pull–up on board)
”Useful for in–circuit testing.
DSP2AOD_.OE
DSP2PBD_.OE
DSP2XD_.OE
TBCA0_HBE0_.OE
TBCA1_HBE1_.OE
TBCA2_HHWIL.OE
TBCA3_HCNTL0.OE
TBCA4_HCNTL1.OE
HCS_.OE
HDS1_.OE
HRW.OE
TBC_WR_.OE
TBC_RD_.OE
TBC_RST_.OE
PCI_FLT_.OE
PT_ADR_.OE
PT_RDY_.OE
AO_SEL_.OE
AO_WR_.OE
AO_RD_.OE
AO_ADR6.OE
AO_ADR5.OE
AO_ADR4.OE
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
AO_ADR3.OE
AO_ADR2.OE
AO_BE3_.OE
AO_BE2_.OE
AO_BE1_.OE
AO_BE0_.OE
WRFIFO_.OE
RDFIFO_.OE
PCIMRD_INT.OE
=
=
=
=
=
=
=
=
=
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
EVM CPLD Equations
C-30
hostsem1
:= DQ0;
hostsem1.ar
= reset # dspsem1;
hostsem1.ce
= pci_sem1_ce;
hostsem1.clk = BPCLK;
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
FLOAT_;
END
C-31
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
PCIMWR_INT.OE
PC_INT.OE
BOOTMODE0.OE
BOOTMODE1.OE
BOOTMODE2.OE
BOOTMODE3.OE
BOOTMODE4.OE
CLKMODE.OE
LENDIAN.OE
OSC_A_EN_.OE
OSC_B_EN_.OE
JTAGSEL.OE
NMI.OE
PCI_INT.OE
DSP_RST_.OE
ARDY.OE
LED1_.OE
LED0_.OE
SP0SEL.OE
XCNTL1.OE
XCNTL0.OE
CODEC_CS_.OE
CODEC_WR_.OE
CODEC_RD_.OE
CE3_SDEN.OE
CE2_SDEN.OE
EXT_RST_.OE
MAN_RST_.OE
interface (BRD_RST_,SW_RST_,VCC2BAD_,PCI_RST_,PCI_DET_,xreset,dsprst,tbcrst –>
MAN_RST_,DSP_RST_,TBC_RST_,EXT_RST_);
TITLE ’TMS320C62x EVM Reset Logic’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This module controls the various types of reset signals that
”are used on the ’C6x EVM board. Signals are generated that
”reset the board, DSP, JTAG TBC and external daughterboard
”independently. All resets are asserted upon power–up, when
”the manual reset pushbutton is pressed and when the board is
”in a software board reset under control of the host. The
”host can reset the board, DSP and TBC. The DSP can reset the
”external daughterboard.
”INPUTS
BRD_RST_
SW_RST_
VCC2BAD_
PCI_RST_
PCI_DET_
xreset
dsprst
tbcrst
pin;
pin;
pin;
pin;
pin;
pin;
pin;
pin;
”Reset from voltage supervisor
”Reset from push button switch
”VCC bad from the voltage supervisor
”Reset from PCI controller
”PCI detection (when 0)
”Ext. reset from DSP–mapped register
”DSP reset from PCI–mapped register
”TBC reset from PCI–mapped register
”OUTPUTS
MAN_RST_
DSP_RST_
TBC_RST_
EXT_RST_
pin;
pin;
pin;
pin;
”Manual reset to voltage supervisor
”DSP reset
”TBC reset
”Daughter board reset
”Contants
h,l,x = 1, 0, .X. ;
EVM CPLD Equations
C-32
MODULE EVMRESET
Equations
”––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Reset Control
”Manual Reset – Asserted when PCI or switch reset.
”NOTE: SW_RST_ will bounce during reset pushbutton use, but
”
the MAX708 voltage supervisor effectively provides a
”
debounce by holding the reset line active for
”
140–200 milliseconds after the last low value.
!MAN_RST_ = (!PCI_RST_ & !PCI_DET_) # !SW_RST_;
”DSP Reset – Asserted when DSP software reset is asserted,
”
DSP core voltage bad or board reset.
”
Allows host to control DSP reset for HPI booting.
!DSP_RST_ = dsprst # !VCC2BAD_ # !BRD_RST_;
”TBC Reset – Asserted upon host assertion or board reset.
!TBC_RST_ = tbcrst # !BRD_RST_;
”External (Daughter Board) Reset – Asserted upon
”
assertion or board reset.
!EXT_RST_ = xreset # !BRD_RST_;
DSP firmware
END
C-33
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
interface (h_clkmode,h_clksel,h_endian,h_jtagsel,h_user2..h_user0,
swsel,h_bootmode4..h_bootmode0,S_CLKMODE,S_CLKSEL,
S_ENDIAN,S_JTAGSEL,S_USER2..S_USER0,
S_BOOTMODE4..S_BOOTMODE0 –>
BOOTMODE4..BOOTMODE0,CLKMODE,LENDIAN,USER2..USER0,
clksel,JTAGSEL);
TITLE ’TMS320C6x EVM User Options (Switch) Mux’
”DWG NAME TMS320C6x Evaluation Module (EVM)
”ASSY#
D600830–0001
”PAL #
U12, 830*
”PAL TYPE Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
”COMPANY
Texas Instruments Incorporated / DNA Enterprises, Inc.
”ENGR
Brian G. Carlson
”DATE
02/21/98
”TOOLS
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This module provides multiplexing between hardware DIP switch
”user options and software switches that are controlled by the
”host software. The CPLD defaults to the use of the DIP switch
”settings at power–up and board reset. The multiplexer is
”controlled by the host software using the PCI memory–mapped
”CPLD SWBOOT register’s SWSEL bit. When SWSEL is 0, the DIP
”switches are used, and when SWSEL is 1, the software switches
”are used.
”INPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From Host (Software Switch) Inputs
h_clkmode
pin;
”Host clock mode
h_clksel
pin;
”Host clock select
h_endian
pin;
”Host endian select
h_jtagsel
pin;
”Host JTAG select
h_user2
pin;
”Host user–defined switches 2..0
h_user1
pin;
h_user0
pin;
swsel
pin;
”DIP / software switch select
h_bootmode4 pin;
”Host DSP boot mode selection
h_bootmode3 pin;
h_bootmode2 pin;
h_bootmode1 pin;
h_bootmode0 pin;
h_bootmode = [h_bootmode4..h_bootmode0];
EVM CPLD Equations
C-34
MODULE EVMSWMUX
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”From the DIP switch
S_CLKMODE
pin;
”Selects x1 (No PLL) or x4 (PLL) Clock Mode
S_CLKSEL
pin;
”Selects output of oscillator A or oscillator B
S_ENDIAN
pin;
”Selects big or little endian memory addressing
S_JTAGSEL
pin;
”Selects internal or external JTAG emulation
S_USER2
pin;
”User–defined switches 2–0
S_USER1
pin;
S_USER0
pin;
S_BOOTMODE4 pin;
”Selects No–boot, HPI–boot or ROM–boot
S_BOOTMODE3 pin;
S_BOOTMODE2 pin;
S_BOOTMODE1 pin;
S_BOOTMODE0 pin;
S_BOOTMODE = [S_BOOTMODE4..S_BOOTMODE0];
”OUTPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To TMS320C6201 DSP
BOOTMODE4
pin;
”DSP boot mode [4..0]
BOOTMODE3
pin;
BOOTMODE2
pin;
BOOTMODE1
pin;
BOOTMODE0
pin;
BOOTMODE = [BOOTMODE4..BOOTMODE0];
pin;
pin;
”DSP clock mode
”DSP little endian select
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To Internal CPLD Register
USER2
pin;
”User–defined options [2..0]
USER1
pin;
USER0
pin;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To Internal CPLD Clock Selection Logic
clksel
pin;
”DSP clock source selection
C-35
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
CLKMODE
LENDIAN
”Constants
h,l,x = 1, 0, .X. ;
Equations
”Multiplexer selects host software switches when swsel=1
”Note: h_clkmode and h_endian selections are inverted from
”
host selections to match polarity of DSP inputs.
when (swsel) then
{
CLKMODE =
clksel =
LENDIAN =
JTAGSEL =
USER2
=
USER1
=
USER0
=
BOOTMODE=
}
!h_clkmode;
h_clksel;
!h_endian;
h_jtagsel;
h_user2;
h_user1;
h_user0;
h_bootmode;
”Multiplexer selects DIP switches when swsel=0
”Note: S_CLKMODE and H_ENDIAN selections are inverted from
”
switch selections to match polarity of DSP inputs.
else
{
CLKMODE = !S_CLKMODE;
clksel = S_CLKSEL;
LENDIAN = !S_ENDIAN;
JTAGSEL = S_JTAGSEL;
USER2
= S_USER2;
USER1
= S_USER1;
USER0
= S_USER0;
BOOTMODE= S_BOOTMODE;
}
END
EVM CPLD Equations
C-36
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To JTAG Multiplexer
JTAGSEL
pin;
”JTAG selection (ext/int)
MODULE EVMCKSEL
interface (CLKA_DIV2,clksel –> osc_a_, osc_b_);
TITLE ’TMS320C6x EVM Clock Select Logic’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This module implements the DSP source clock selection. The DSP
”source clock (CLKIN) can either be 33.25 or 40 MHz. The two oscillator
”outputs are buffered using a SN74LVT125 quad buffer device which
”has independent output enable controls. The two buffered clock outputs
”are tied together. The state machine in this module ensures that only
”one clock output is enabled at any one time by implementing a
”break–before–make switch. The source clock selection can be made
”using a DIP switch (SW2–7) or a software switch (DSPBOOT–SWSEL).
”INPUTS
pin;
pin;
”Free running clk (16.625 MHz) used for clk select state machine
”Clock select at output of switch mux
”OUTPUTS
osc_a_
osc_b_
pin;
pin;
”Oscillator A buffer output enable (active low)
”Oscillator B buffer output enable (active low)
”Internal Registers
clksel_db1
clksel_db2
node istype ’reg_d, dc, buffer’;
node istype ’reg_d, dc, buffer’;
”Constants
h,l,x = 1, 0, .X. ;
”delayed clock select
”delayed clock select
C-37
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
CLKA_DIV2
clksel
”––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”NOTE: The selected clock must be enabled during reset
”
so that the DSP’s PLL locks before reset is released.
”
This means that the FF’s should be free–running without
”
being held by reset.
”––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”clksel = 0 selects oscillator A (33.25 MHz)
”clksel = 1 selects oscillator B (40.00 MHz)
”Switch mux clksel output fed to cascased D flip–flops to determine
”clock selection transition. This creates a break–before–make clock
”switch that prevents contention between the two clock buffer outputs.
clksel_db1.d
= clksel;
clksel_db1.clk = CLKA_DIV2;
clksel_db2
:= clksel_db1;
clksel_db2.clk = CLKA_DIV2;
”Oscillator A selected only when clksel low for two consecutive clocks
”This signal controls the SN74LVT125 buffer output enable for OSC A.
osc_a_ = clksel_db1 # clksel_db2;
”Oscillator B selected only when clksel high for two consecutive clocks
”This signal controls the SN74LVT125 buffer output enable for OSC B.
osc_b_ = !clksel_db1 # !clksel_db2;
END
EVM CPLD Equations
C-38
Equations
MODULE EVMDECOD
interface (RESET,PCI_DET_,PCICLK,DSPCLK,
CE1_,CE2_,CE3_,ARE_,AWE_,EA21..EA16,
ao_bsy,emif_ack,XRDY,ce2sden,ce3sden,CLKMODE –>
DSP2AOD_,DSP2PBD_,DSP2XD_,are_r_,awe_r_,emif_req,
CPLD_CS,CODEC_CS_,CODEC_WR_,CODEC_RD_,ARDY);
TITLE ’TMS320C6x EVM Memory Decode Logic’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”REVISIONS
”
03/05/98 – Modified DSP EMIF ready logic to provide ARDY for invalid
”
async accesses to non–CE1 memory spaces to prevent the
”
EMIF from locking–up at power–up when invalid code is
”
executed in the no–boot mode. Also, extended codec_rdy
”
flag assertion to maintain ARDY assertion until ARE– or
”
AWE– is deasserted to support any strobe period >= 3
”
CLKOUT1 clocks.
”INPUTS
C-39
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Voltage Supervisor
RESET
pin;
”Active high board reset
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”This module provides DSP EMIF memory decoding to control
”asynchronous memory accesses to the CE1 memory space.
The devices
”in the CE1 memory space include CPLD registers, the PCI controller,
”the audio codec and the expansion memory (daughterboard). Decode
”logic controls data bus transceivers that connect the DSP’s EMIF
”data bus to the peripheral, PCI add–on and external daughterboard
”data busses. The asynchronous ARE_ and AWE_ EMIF signals are
”synchronized for use by the PCI controller state machine. Asynchronous
”memory access ready (RDY) generation is implemented for each type
”of device access in the CE1 space. Audio codec chip select and
”read/write strobes are controlled with a state machine to ensure
”proper single–cycle and back–to–back access timing.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From TMS320C6201 DSP
DSPCLK
pin;
”DSP’s CLKOUT2
CE1_
pin;
”EMIF CE1 memory space enable
CE2_
pin;
”EMIF CE2 memory space enable
CE3_
pin;
”EMIF CE3 memory space enable
ARE_
pin;
”EMIF asynchronous memory read strobe
AWE_
pin;
”EMIF asynchronous memory write strobe
”EMIF word address bits [21..16]
EA21
pin;
EA20
pin;
EA19
pin;
EA18
pin;
EA17
pin;
EA16
pin;
EA
= [EA21, EA20, EA19, EA18, EA17, EA16];
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Add–on State Machine
ao_bsy
pin;
”Add–on state machine busy flag
emif_ack
pin;
”Add–on state machine EMIF access acknowledge
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Daughter Board
XRDY
pin;
”EMIF asynchronous memory access ready from DB
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From DSP–mapped Registers
ce2sden
pin;
”CE2 SDRAM enable
ce3sden
pin;
”CE3 SDRAM enable
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Internal Switch Multiplexer
CLKMODE
pin;
”Clock mode
”OUTPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To Data Buffer
DSP2AOD_
pin;
”Enables ED[31..0] to AOD[31..0]
DSP2PBD_
pin;
”Enables ED[7..0] to PBD[7..0]
DSP2XD_
pin;
”Enables ED[31..0] to XD[31..0]
EVM CPLD Equations
C-40
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From S5933 PCI Controller
PCI_DET_
pin;
”PCI detection indicator (0=PCI,1=Standalone)
PCICLK
pin;
”Buffered PCI clock (33 MHz max)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To Add–on State Machine
are_r_
pin istype ’reg_d, dc, buffer’; ”Synchronized ARE_
awe_r_
pin istype ’reg_d, dc, buffer’; ”Synchronized AWE_
emif_req
pin istype ’reg_d, dc, buffer’; ”Synchronized EMIF req.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To CPLD Registers
CPLD_CS
pin istype ’com’;
”CPLD DSP register chip select
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To CS4231 Audio Codec
CODEC_CS_
pin istype ’com’;
”Audio codec chip select
CODEC_WR_
pin istype ’com’;
”Audio codec write strobe
CODEC_RD_
pin istype ’com’;
”Audio codec read strobe
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To TMS320C6201 DSP
ARDY
pin istype ’com’;
”EMIF async memory access ready
”Internal Registers
dspclk2
node
codec_rdy
node
codec_rd_r node
codec_wr_r node
istype
istype
istype
istype
’reg_d,
’reg_d,
’reg_d,
’reg_d,
dc,
dc,
dc,
dc,
buffer’;
buffer’;
buffer’;
buffer’;
”CLKOUT2/2
”Audio codec ready flag
”Audio codec read reg
”Audio codec write reg
”Constants
h,l,x = 1, 0, .X. ;
”EMIF CE1_ Addresses [EA21..EA16]
PCI_REG_ADDR = [1, 1, 0, 0, 0,
PCI_FIFO_ADDR = [1, 1, 0, 0, 0,
CODEC_REG_ADDR= [1, 1, 0, 0, 1,
DSP_REG_ADDR = [1, 1, 1, 0, 0,
0];
1];
0];
0];
C-41
”Audio codec read/write strobe generation
” State Name
State Value (Bin)
ACS_IDLE
= [ 0, 0, 0, 0, 0 ];
ACS_BEGIN = [ 0, 0, 0, 0, 1 ];
ACS_DELAY1 = [ 0, 0, 0, 1, 0 ];
ACS_DELAY2 = [ 0, 0, 1, 0, 0 ];
ACS_READ1 = [ 0, 1, 0, 0, 0 ];
ACS_READ2 = [ 0, 1, 0, 0, 1 ];
”
”
”
”
MAP0
0x0130xxxx
0x0131xxxx
0x0132xxxx
0x0138xxxx
/
/
/
/
MAP1
0x0170xxxx
0x0171xxxx
0x0172xxxx
0x0178xxxx
state machine states
(Hex)
”0x00
”0x01
”0x02
”0x04
”0x08
”0x09
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Audio codec read/write strobe generation state machine (acr)
acr4, acr3, acr2, acr1, acr0 node istype ’reg_d, dc, buffer’;
acr = [acr4..acr0];
=
=
=
=
=
=
=
=
=
=
[
[
[
[
[
[
[
[
[
[
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
0,
0,
0,
0,
1,
1,
1,
0,
0,
1,
0,
0,
0,
1,
0,
0,
0,
1,
1,
0,
0,
0,
1,
0,
0,
0,
1,
0
1
0
0
1
0
0
0
1
0
];
];
];
];
];
];
];
];
];
];
”0x0A
”0x0B
”0x0C
”0x10
”0x11
”0x12
”0x14
”0x18
”0x19
”0x1A
Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DSP to Add–on, Peripheral and Expansion Bus Data Buffers Control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Connect ED[31..0] to AOD[31..0]
”ED[7..0] is connected to AOD[7..0] only when DSP2PB_ is low also.
!DSP2AOD_ = ((EA == PCI_REG_ADDR) # (EA == PCI_FIFO_ADDR)) &
!CE1_ & !ao_bsy & (!ARE_ # !AWE_);
”Connect ED[7..0] to PBD[7..0]
”Also connects ED[7..0] to AOD[7..0] when DSP2AOD_ is low.
!DSP2PBD_ = !CE1_ & EA21 & EA20 & (!ARE_ # !AWE_);
”Connects ED[31..0] to XD[31..0] (Daughter Board)
!DSP2XD_ = ((!CE1_ & !EA21)
#
(!CE1_ & !EA20)
# ”EMIF CE1_ address = $xx00xxxx–xx2xxxxx
(!CE2_ & !ce2sden) # ”EMIF CE2_ address & SDRAM disabled
(!CE3_ & !ce3sden)); ”EMIF CE3_ address & SDRAM disabled
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Async Read/Write Strobe Synchronization
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”A synchronizer is required to elimination metastability
”problems that can be caused by sampling these asynchronous signals
”when they transition within the setup period. The EMIF asynchronous
”ARE_ and AWE_ signals are synchronized to the PCI clock.
”Add–on state
are_r_.ap
=
are_r_.clk =
are_r_
:=
machine ARE_ synchronization
RESET;
PCICLK;
ARE_;
”Add–on state
awe_r_.ap
=
awe_r_.clk =
awe_r_
:=
machine AWE_ synchronization
RESET;
PCICLK;
AWE_;
EVM CPLD Equations
C-42
ACS_READ3
ACS_READ4
ACS_READ5
ACS_WRITE1
ACS_WRITE2
ACS_WRITE3
ACS_WRITE4
ACS_WRITE5
ACS_WRITE6
ACS_WRITE7
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”EMIF PCI Controller Access Request Synchronization
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Synchronize EMIF request to add–on bus (PCI register or FIFO access)
”A dual–FF synchronizer is required to elimination metastability
”problems that can be caused by sampling these asynchronous signals
”when they transition within the setup period.”
emif_req
:=
emif_req.ar =
emif_req.clk =
!CE1_ &
((EA == PCI_REG_ADDR) # (EA == PCI_FIFO_ADDR));
RESET;
PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”CPLD Register Chip Select
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CPLD_CS
= !CE1_ & (EA == DSP_REG_ADDR);
”CPLD DSP register accesses are ready when ARE_ or AWE_ goes low
when (!CE1_ & (EA == DSP_REG_ADDR)) then {
ARDY = !ARE_ # !AWE_;
}
else
C-43
”Audio codec register accesses are ready when codec_rdy set
when (!CE1_ & (EA == CODEC_REG_ADDR)) then {
ARDY = codec_rdy;
}
else
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DSP Asynchronous Memory Access ARDY Generation
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”PCI controller register or FIFO access
”PCI controller accesses are ready when the PCI state machine
”acknowledges the access.
”NOTE: If not in PCI slot, then PCI accesses do not lock up
”
the EMIF waiting for a response since ARDY is asserted
”
when PCI_DET_ is high.
when (!CE1_ & ((EA == PCI_REG_ADDR) # (EA == PCI_FIFO_ADDR))) then {
ARDY = (emif_ack & (!ARE_ # !AWE_)) # PCI_DET_;
}
else
CE1_, CE2_ or
#
# ”EMIF CE1_
# ”EMIF CE2_
”EMIF CE3_
CE3_ uses XRDY from DB
address = $xx00xxxx–xx2xxxxx
address & SDRAM disabled
address & SDRAM disable
”NOTE: ARDY is defaulted to asserted for all other CE1
”
accesses to prevent the DSP from being locked up
”
on an invalid memory access.
”BGC–03/05/98–Rev. 1– Added non–CE1 async ARDY generation to prevent
”
EMIF bus lock on invalid memory access during power–up
”
when no valid progam is in memory.
else ARDY = !CE1_ # (CE1_ & !ARE_) # (CE1_ & !AWE_);
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Generate DSPCLK2/2 for synchronization (33.25 / 40 MHz)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
dspclk2
:= !dspclk2;
dspclk2.clk = DSPCLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”CS4231A Audio Codec Interface Support
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Audio codec chip select
!CODEC_CS_ = (EA == CODEC_REG_ADDR) & !CE1_;
”Audio codec read/write strobes are internal register outputs
CODEC_RD_ = codec_rd_r;
CODEC_WR_ = codec_wr_r;
”Internal read/write strobe registers
codec_rd_r.ap = RESET # ARE_;
”default RD_ to inactive at reset
codec_rd_r.clk = dspclk2;
codec_wr_r.ap = RESET;
”default WR_ to inactive at reset
codec_wr_r.clk = dspclk2;
”Internal audio codec ready register
codec_rdy.ar
= RESET;
”default to not ready
codec_rdy.clk = dspclk2;
”Audio codec state machine for RD_/WR_ generation
acr.ar = RESET # (ARE_ & AWE_); ”default to idle state ACS_IDLE at reset
acr.clk = dspclk2;
EVM CPLD Equations
C-44
”External memory access in
when ((!CE1_ & !EA21)
(!CE1_ & !EA20)
(!CE2_ & !ce2sden)
(!CE3_ & !ce3sden))
then
{
ARDY = XRDY;
}
state_diagram acr
”––––––––––––––––––––––––––––––––––––––––––––––––
” Wait for audio codec access
”––––––––––––––––––––––––––––––––––––––––––––––––
state ACS_IDLE:
”Audio codec access not ready
codec_rdy := 0;
”Read/write strobes are inactive during idle state
codec_rd_r := 1;
codec_wr_r := 1;
”Wait for audio codec access
”Note: State machine reset will hold in this state
”
until ARE_ or AWE_ is low
”If CLKMODE is x4 mode, then all states are required to
”ensure proper back–to–back cycle delay
if (!CODEC_CS_ & !CLKMODE) then ACS_BEGIN;
else
”if CLKMODE is x1 and read, then skip to ACS_READ3
”since CLKOUT1 period is long enough to ensure proper
”back–to-back cycle delay
if (!CODEC_CS_ & !CLKMODE & !ARE_) then ACS_READ3;
else
”––––––––––––––––––––––––––––––––––––––––––––––––
” Audio codec access is in progress
”––––––––––––––––––––––––––––––––––––––––––––––––
” Delay is required between back–to–back codec
” accesses, so this it is enforced at the start
” of each cycle.
state ACS_BEGIN:
”Audio codec access not ready
codec_rdy := 0;
C-45
”Read/write strobes are inactive
codec_rd_r := 1;
codec_wr_r := 1;
goto ACS_DELAY1;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”if CLKMODE is x1 and write, then skip to ACS_WRITE5
”since CLKOUT1 period is long enough to ensure proper
”back–to-back cycle delay
if (!CODEC_CS_ & !CLKMODE & !AWE_) then ACS_WRITE5;
else ACS_IDLE;
”Read/write strobes are still inactive
codec_rd_r := 1;
codec_wr_r := 1;
goto ACS_DELAY2;
state ACS_DELAY2:
”Audio codec access not ready
codec_rdy := 0;
”Read/write strobes are still inactive
codec_rd_r := 1;
codec_wr_r := 1;
”Now determine if read or write
if (!ARE_) then ACS_READ1;
else
if (!AWE_) then ACS_WRITE1;
else
ACS_IDLE;
”––––––––––––––––––––––––––––––––––––––––––––––––
” Audio codec read access
”––––––––––––––––––––––––––––––––––––––––––––––––
state ACS_READ1:
”Audio codec access not ready
codec_rdy := 0;
”Assert read strobe to codec (write inactive)
codec_rd_r := 0;
codec_wr_r := 1;
goto ACS_READ2;
state ACS_READ2:
”Audio codec access not ready
codec_rdy := 0;
”Read strobe still asserted
codec_rd_r := 0;
codec_wr_r := 1;
goto ACS_READ3;
state ACS_READ3:
”Audio codec access not ready
codec_rdy := 0;
EVM CPLD Equations
C-46
state ACS_DELAY1:
”Audio codec access not ready
codec_rdy := 0;
”Read strobe still asserted
codec_rd_r := 0;
codec_wr_r := 1;
goto ACS_READ4;
state ACS_READ4:
”Audio codec access ready
codec_rdy := 1;
”Read strobe still asserted
codec_rd_r := 0;
codec_wr_r := 1;
goto ACS_READ5;
state ACS_READ5:
”Audio codec access ready
”BGC–03/05/98–Rev. 1–Changed codec_rdy assignment to 1
”
to support unknown strobe period.
”
This prevents the EMIF bus from
”
locking up waiting for ARDY.
codec_rdy := 1;
”Read strobe still asserted
codec_rd_r := 0;
codec_wr_r := 1;
”––––––––––––––––––––––––––––––––––––––––––––––––
” Audio codec write access
”––––––––––––––––––––––––––––––––––––––––––––––––
state ACS_WRITE1:
”Audio codec access not ready
codec_rdy := 0;
C-47
”Assert write strobe to codec (read inactive)
codec_rd_r := 1;
codec_wr_r := 0;
goto ACS_WRITE2;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Loop until ARE_ goes high
if ARE_ then ACS_IDLE with {
codec_rd_r := 1;
codec_wr_r := 1;
”BGC–03/05/98–Rev. 1–Added codec_rdy assignment to
”
clear codec_rdy flag.
codec_rdy := 0;
}
else ACS_READ5;
”Write strobe still asserted
codec_rd_r := 1;
codec_wr_r := 0;
goto ACS_WRITE3;
state ACS_WRITE3:
”Audio codec access not ready
codec_rdy := 0;
”Write strobe still asserted
codec_rd_r := 1;
codec_wr_r := 0;
goto ACS_WRITE4;
state ACS_WRITE4:
”Audio codec access not ready
codec_rdy := 0;
”Write strobe still asserted
codec_rd_r := 1;
codec_wr_r := 0;
goto ACS_WRITE5;
state ACS_WRITE5:
”Audio codec access not ready
codec_rdy := 0;
”Write strobe still asserted
codec_rd_r := 1;
codec_wr_r := 0;
goto ACS_WRITE6;
state ACS_WRITE6:
”Audio codec access ready
codec_rdy := 1;
”Deassert write strobe to latch data into codec
codec_rd_r := 1;
codec_wr_r := 1;
goto ACS_WRITE7;
EVM CPLD Equations
C-48
state ACS_WRITE2:
”Audio codec access not ready
codec_rdy := 0;
state ACS_WRITE7:
”Audio codec access ready
”BGC–03/05/98–Rev. 1–Changed codec_rdy assignment to 1
”
to support unknown strobe period.
”
This prevents the EMIF bus from
”
locking up waiting for ARDY.
codec_rdy := 1;
”Read and write strobes both high
codec_rd_r := 1;
codec_wr_r := 1;
”Loop until AWE_ goes high
if AWE_ then ACS_IDLE with {
”BGC–03/05/98–Rev. 1–Added codec_rdy assignment to
”
clear codec_rdy flag.
codec_rdy := 0;
}
else ACS_WRITE7;
END
C-49
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
interface (RESET,DSP_HINT_,TBC_INT_,PCICLK,PCI_DET_,PCI_IRQ_,
RDEMPTY,WRFULL,CODEC_IRQ, hinten, tbcinten,
dspnmi,nmisel,nmien,pcimren,pcimwen,RDFIFO_,WRFIFO_ –>
PC_INT,NMI,PCI_INT,PCIMRD_INT,PCIMWR_INT);
TITLE ’TMS320C6x EVM Interrupt Control’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This module controls interrupts to the host (via the PCI controller) and the ’C6201 DSP.
”The DSP host interrupt and the JTAG TBC interrupt can be used to interrupt the host.
”This module implements falling edge detectors to determine when these source interrupts
”occur to force a PCI mailbox interrupt in the S5933 PCI controller which causes an
”INTA# host interrupt. Logic is included to implement a DSP NMI interrupt source
”multiplexer that selects between the host and codec-controlled NMI interrupts. The
”PCI controller add-on IRQ# interrupt is passed to the DSP via its EXT_INT4 input.
”Additionally, PCI bus master read (EXT_INT5) and (EXT_INT6) interrupts are generated
”by state machines implemented in this module that monitor the PCI controller’s FIFO
”RDEMPTY and WRFULL flags to determine when data can be transferred between the
”PCI controller and the DSP memory space. These interrupts can be used by the DSP to
”trigger an interrupt service routine, or more typically, be used to trigger background DMA
”data transfers. Optionally, DSP software could even poll the state of these interrupts, or the
”FIFO flags themselves, to control the data transfers.
”INPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Voltage Supervisor
RESET
pin;
”Active high board reset
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From TMS320C6201 DSP
DSP_HINT_
pin;
”DSP HPI host interrupt
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From JTAG TBC
TBC_INT_
pin;
”TBC host interrupt
EVM CPLD Equations
C-50
MODULE EVMINT
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From PCI Controller
PCICLK
pin;
”Buffered PCI clock (33 MHz max)
PCI_DET_
pin;
”PCI detection indicator (0=PCI,1=Standalone)
PCI_IRQ_
pin;
”Interrupt to add–on device
RDEMPTY
pin;
”Read FIFO empty flag
WRFULL
pin;
”Write FIFO full flag
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From CS4231A Audio Codec
CODEC_IRQ
pin;
”Audio codec interrupt
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From PCI–mapped Registers
hinten
pin;
”HPI host interrupt enable
tbcinten
pin;
”TBC host interrupt enable
dspnmi
pin;
”DSP NMI interrupt from host
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From DSP–mapped Registers
nmisel
pin;
”NMI interrupt source selection (host/codec)
nmien
pin;
”NMI interrupt enable
pcimren
pin;
”PCI master read interrupt (EXT_INT5) enable
pcimwen
pin;
”PCI master write interrupt (EXT_INT6) enable
”OUTPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To PCI Controller
PC_INT
pin istype ’reg_d, dc, buffer’;
”Add–on to PCI interrupt
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To DSP
PCI_INT
pin istype ’com’;
”PCI–to–DSP interrupt (EXT_INT4)
NMI
pin istype ’com’;
”NMI interrupt to DSP
PCIMRD_INT pin istype ’reg_d, dc, buffer’;
”PCI master read int to DSP
PCIMWR_INT pin istype ’reg_d, dc, buffer’;
”PCI master write int to DSP
”Internal Registers
”DSP host interrupt falling edge detectors
hint_db1, hint_db2
node istype ’reg_d, dc, buffer’;
C-51
”TBC interrupt falling edge detectors
tbcint_db1, tbcint_db2
node istype ’reg_d, dc, buffer’;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Memory Decode
RDFIFO_
pin;
”Read PCI controller FIFO strobe
WRFIFO_
pin;
”Write PCI controller FIFO strobe
”PCI master read state machine
mrd_fifo1, mrd_fifo0
node istype ’reg_d, dc, buffer’;
mrd_fifo = [mrd_fifo1..mrd_fifo0];
”Constants
h,l,x = 1, 0, .X. ;
”PCI master read state machine states
MRD_IDLE
= [ 0, 0 ];
MRD_INT
= [ 0, 1 ];
MRD_WAIT
= [ 1, 0 ];
MRD_DONE
= [ 1, 1 ];
”wait for read FIFO not empty
”interrupt DSP (EXT_INT5)
”wait for EMIF read FIFO access
”read FIFO transfer complete
”PCI master write state machine states
MWR_IDLE
= [ 0, 0 ];
MWR_INT
= [ 0, 1 ];
MWR_WAIT
= [ 1, 0 ];
MWR_DONE
= [ 1, 1 ];
”wait for write FIFO not full
”interrupt DSP (EXT_INT6)
”wait for EMIF write FIFO access
”write FIFO transfer complete
Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Interrupt to Host (INTA#)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Falling edge detection of DSP host interrupt
hint_db1
:= DSP_HINT_;
hint_db2
:= hint_db1;
hint_db1.ar = RESET;
hint_db2.ar = RESET;
hint_db1.clk = PCICLK;
hint_db2.clk = PCICLK;
”Falling edge detection of TBC interrupt
tbcint_db1
:= TBC_INT_;
tbcint_db2
:= tbcint_db1;
tbcint_db1.ar = RESET;
tbcint_db2.ar = RESET;
tbcint_db1.clk = PCICLK;
tbcint_db2.clk = PCICLK;
”PC interrupt rising edge whenever DSP host interrupt
”or TBC interrupt have a falling edge
PC_INT
:= !((tbcinten & !tbcint_db1 & tbcint_db2) #
(hinten
& !hint_db1
& hint_db2));
EVM CPLD Equations
C-52
”PCI master write state machine
mwr_fifo1, mwr_fifo0
node istype ’reg_d, dc, buffer’;
mwr_fifo = [mwr_fifo1..mwr_fifo0];
PC_INT.ar
PC_INT.clk
= RESET;
= PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”NMI interrupt (from host or CODEC)
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”DSP selects NMI source of host (0) or (1) with nmisel register bit.
”NMI is only generated when the DSP enables it with the nmien register bit.
NMI = nmien & ((!nmisel & dspnmi) # (nmisel & CODEC_IRQ));
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”PCI interrupt to DSP
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Invert polarity of PCI controller’s IRQ# output.
”Only active when in PCI slot and not in reset
PCI_INT = !PCI_DET_ & !PCI_IRQ_ & !RESET;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” PCI master read control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Master read interrupt register definition (controls DSP’s EXT_INT5)
PCIMRD_INT.ar = RESET;
”Default to EXT_INT5 low
PCIMRD_INT.clk = PCICLK;
PCIMRD_INT.ce = !PCI_DET_;
”Only activate when in PCI slot
”Master read control state machine (mrd_fifo)
state_diagram mrd_fifo
”Wait for PCI master read state machine to be enabled (pcimren=1)
”and PCI controller’s read FIFO to not be empty.
state MRD_IDLE:
PCIMRD_INT := 0;
if (pcimren & !RDEMPTY) then MRD_INT;
else MRD_IDLE;
C-53
”PCI master read state machine is enabled and PCI controller’s
”read FIFO is not empty. Assert DSP’s EXT_INT5 interrupt high.
state MRD_INT:
PCIMRD_INT := 1;
”set EXT_INT5 high
goto MRD_WAIT;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Master read control state machine definition
mrd_fifo.ar
= RESET;
”Default to MRD_IDLE state
mrd_fifo.clk
= PCICLK;
mrd_fifo.ce
= !PCI_DET_;
”Only activate when in PCI slot
”DSP has read PCI FIFO or disabled the PCI master read state machine.
”Return to idle state.
state MRD_DONE:
PCIMRD_INT := 1;
”wait for master read disable
”or end of FIFO read
if (!pcimren # RDFIFO_) then MRD_IDLE;
else MRD_DONE;
Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” PCI master write control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Master write interrupt register definition (controls DSP’s EXT_INT6)
PCIMWR_INT.ar = RESET;
”Default to EXT_INT6 low
PCIMWR_INT.clk = PCICLK;
PCIMWR_INT.ce = !PCI_DET_;
”Only activate when in PCI slot
”Master write control state machine definition
mwr_fifo.ar
= RESET;
”Default to MWR_IDLE state
mwr_fifo.clk
= PCICLK;
mwr_fifo.ce
= !PCI_DET_;
”Only activate when in PCI slot
state_diagram mwr_fifo
”Wait for PCI master write state machine to be enabled (pcimwen=1)
”and PCI controller’s write FIFO to not full.
state MWR_IDLE:
PCIMWR_INT := 0;
if (pcimwen & !WRFULL) then MWR_INT;
else MWR_IDLE;
”PCI master write state machine is enabled and PCI controller’s
”write FIFO is not full. Assert DSP’s EXT_INT6 interrupt high.
state MWR_INT:
PCIMWR_INT := 1;
”set EXT_INT6 high
goto MWR_WAIT;
EVM CPLD Equations
C-54
”Wait for DSP to read FIFO at 0x1310000 or 0x1710000 or
”DSP to disable PCI master read state machine (pcimren=0).
”EXT_INT5 is held high during this state.
state MRD_WAIT:
PCIMRD_INT := 1;
”wait for master read disable
”or start of FIFO read
if (!pcimren # !RDFIFO_) then MRD_DONE;
else MRD_WAIT;
”Wait for DSP to write FIFO at 0x1310000 or 0x1710000 or
”DSP to disable PCI master write state machine (pcimwen=0).
”EXT_INT6 is held high during this state.
state MWR_WAIT:
PCIMWR_INT := 1;
”wait for master write disable
”or start of FIFO write
if (!pcimwen # !WRFIFO_) then MWR_DONE;
else MWR_WAIT;
”DSP has written PCI FIFO or disabled the PCI master write state machine.
”Return to idle state.
state MWR_DONE:
PCIMWR_INT := 1;
”wait for master write disable
”or end of FIFO write
if (!pcimwen # WRFIFO_) then MWR_IDLE;
else MWR_DONE;
END
C-55
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
interface (RESET,ARE_,AWE_,BE3_,BE2_,BE1_,BE0_,EA16,EA6..EA2,
PCI_DET_,PCICLK,PTATN_,PTBURST_,PTNUM1,PTNUM0,PTWR,
pt_be3_,pt_be2_,pt_be1_,pt_be0_,
pt_addr4,pt_addr3,pt_addr2,pt_addr1, pt_addr0,
TBC_RDY_,DSP_HRDY_,emif_req –>
PCI_FLT_,PT_ADR_,PT_RDY_,AO_SEL_,AO_WR_,AO_RD_,
AO_ADR6..AO_ADR2,AO_BE3_,AO_BE2_,AO_BE1_,AO_BE0_,RDFIFO_,WRFIFO_,
pcireg_oe,pcireg_ce,TBC_WR_,TBC_RD_,
HCS_,HDS1_,HRW,TBCA4_HCNTL1,TBCA3_HCNTL0,TBCA2_HHWIL,
TBCA1_HBE1_,TBCA0_HBE0_,ao_bsy,emif_ack);
TITLE ’TMS320C6x EVM PCI Controller Logic’
”DWG NAME
”ASSY#
”PAL #
”PAL TYPE
”COMPANY
”ENGR
”DATE
”TOOLS
TMS320C6x Evaluation Module (EVM)
D600830–0001
U12, 830*
Altera EPM7256SQC208–10 (256–Macrocells, 10–ns, 208–PQFP)
Texas Instruments Incorporated / DNA Enterprises, Inc.
Brian G. Carlson
02/21/98
Synario ABEL 6.5 / Altera Max Plus II 8.2
”DESCRIPTION
”This module controls the slave (target) interface between the
”PCI controller and the JTAG TBC, DSP HPI and CPLD PCI registers,
”as well as DSP EMIF accesses to the PCI controller which include
”PCI bus master read/write tranfers. This module consists of a
”large state machine that monitors and controls all the signals
”that are required to transfer data between the PCI controller and
”the devices on the ’C6x EVM board. The PCI controller handles
”all the PCI bus transactions, so the CPLD is not involved at all
”on the actual PCI bus. The CPLD only manages the transfers with
”the PCI controller’s add–on bus. The state machine in this module
”runs from the buffered PCI clock which has a maximum frequency of
”33 MHz.
”REVISIONS
”
04/15/98 – Modified HPI write timing to sample HRDY– before raising
”
HDS1– instead of at beginning of cycle. The previous
”
TMS320C62x Peripherals Reference Guide dated Oct 1997
”
stated on page 5–8 that HRDY– was inactive (high) when
”
HCS– was inactive. However, HRDY– is actually active (low)
”
when HCS– is inactive, so HPI writes previously got an
”
incorrect ready indication and never waited for a valid
”
ready indication with a potential for missed HPI writes.
EVM CPLD Equations
C-56
MODULE EVMPCI
”
”
”
”
”
”
”
”
”
”
”
”
03/11/98 – Modified HPI write timing to work with new ’C6201 data
sheet timing which samples HBE[1:0] on the rising edge of
HSTROBE–, instead of falling edge. This was not a problem
with Rev. 2.0 silicon. However, the BE2– and BE3– signals
do not get generated with Rev. 2.1 silicon without this
change.
03/05/98 – Modified DSP EMIF ready logic for PCI controller registers
and FIFO accesses to hold ARDY active until ARE– or AWE–
is deasserted. This allows the PCI controller to be
accessed with any strobe period >= 3 CLKOUT1 clocks.
”INPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Voltage Supervisor
RESET
pin;
”Active–high board reset
”EMIF word address bits [16], [6..2]
EA16
pin;
EA6
pin;
EA5
pin;
EA4
pin;
EA3
pin;
EA2
pin;
C-57
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From S5933 PCI Controller
PCI_DET_
pin;
”PCI bus detection (0=PCI, 1=Standalone)
PCICLK
pin;
”Buffered PCI clock (33 MHz max.)
PTATN_
pin;
”Pass–thru attention indication
PTBURST_
pin;
”Pass–thru burst indication
PTNUM1
pin;
”Pass–thru region number (bit 1)
PTNUM0
pin;
”Pass–thru region number (bit 0)
PTWR
pin;
”Pass–thru access type (R=0, W=1)
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From TMS320C6201 DSP
ARE_
pin;
”EMIF asynchronous memory read strobe
AWE_
pin;
”EMIF asynchronous memory write strobe
BE3_
pin;
”EMIF byte 3 enable control
BE2_
pin;
”EMIF byte 2 enable control
BE1_
pin;
”EMIF byte 1 enable control
BE0_
pin;
”EMIF byte 0 enable control
BE = [BE3_, BE2_, BE1_, BE0_];
pin;
pin;
pin;
pin;
pin;
pin;
pin;
pin;
pin;
”Latched pass–thru byte enables [3..0]
”Latched pass–thru address[4..0]
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From JTAG TBC
TBC_RDY_
pin;
”JTAG TBC ready
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From DSP HPI
DSP_HRDY_
pin;
”DSP HPI ready
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” From Memory Decode
emif_req
pin;
”Synchronized EMIF access request
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”OUTPUTS
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To S5933 PCI Controller
PCI_FLT_
pin istype ’com’;
”Float PCI controller outputs
PT_ADR_
pin istype ’reg_d, dc, buffer’; ”Pass–thru address request
PT_RDY_
pin istype ’reg_d, dc, buffer’; ”Pass–thru ready indication
AO_SEL_
pin istype ’reg_d, dc, buffer’; ”Add–on select for register access
AO_WR_
pin istype ’reg_d, dc, buffer’; ”Add–on write strobe
AO_RD_
pin istype ’reg_d, dc, buffer’; ”Add–on read strobe
”Add–on address bits [6..2]
AO_ADR6
pin istype ’reg_d,
AO_ADR5
pin istype ’reg_d,
AO_ADR4
pin istype ’reg_d,
AO_ADR3
pin istype ’reg_d,
AO_ADR2
pin istype ’reg_d,
AO_ADR = [AO_ADR6..AO_ADR2];
”Add–on byte enables [3..0]
AO_BE3_
pin istype ’reg_d,
AO_BE2_
pin istype ’reg_d,
AO_BE1_
pin istype ’reg_d,
AO_BE0_
pin istype ’reg_d,
dc,
dc,
dc,
dc,
dc,
buffer’;
buffer’;
buffer’;
buffer’;
buffer’;
dc,
dc,
dc,
dc,
buffer’;
buffer’;
buffer’;
buffer’;
EVM CPLD Equations
C-58
pt_be3_
pt_be2_
pt_be1_
pt_be0_
pt_addr4
pt_addr3
pt_addr2
pt_addr1
pt_addr0
RDFIFO_
WRFIFO_
pin istype ’reg_d, dc, buffer’;
pin istype ’reg_d, dc, buffer’;
”Read FIFO strobe
”Write FIFO strobe
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To PCI Memory–mapped CPLD Registers
pcireg_oe
pin istype ’reg_d, dc, buffer’; ”PCI register output enable
pcireg_ce
pin istype ’reg_d, dc, buffer’; ”PCI register clock enable
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To JTAG TBC
TBC_WR_
pin istype ’reg_d, dc, buffer’; ”TBC write strobe
TBC_RD_
pin istype ’reg_d, dc, buffer’; ”TBC read strobe
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To DSP HPI
HCS_
pin istype ’reg_d, dc, buffer’; ”HPI chip select
HDS1_
pin istype ’reg_d, dc, buffer’; ”HPI data strobe
HRW
pin istype ’reg_d, dc, buffer’; ”HPI read/write control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” To TBC and HPI
TBCA4_HCNTL1
pin istype ’reg_d, dc,buffer’; ”TBC addr / HPI byte enable 0
TBCA3_HCNTL0
pin istype ’reg_d, dc,buffer’; ”TBC addr 1 / HPI byte enable 1
TBCA2_HHWIL
pin istype ’reg_d, dc,buffer’; ”TBC addr 2 / HPI half–word sel
TBCA1_HBE1_
pin istype ’reg_d, dc,buffer’; ”TBC addr 3 / HPI control 0
TBCA0_HBE0_
pin istype ’reg_d, dc,buffer’; ”TBC addr 4 / HPI control 1
”Add–on state machine busy flag
”EMIF access acknowledge
”Internal Registers
”Add–on state machine
”Implemented with 15 bits to limit product terms and ease routing.
aos14, aos13, aos12, aos11, aos10,
aos9, aos8, aos7, aos6, aos5,
aos4, aos3, aos2, aos1, aos0
node istype ’reg_d, dc, buffer’;
aos = [aos14..aos0];
”TBC ready flag
tbcrdy
node istype ’reg_d, dc, buffer’;
”HPI ready flag (synchronized)
hrdy
node istype ’reg_d, dc, buffer’;
C-59
”HPI control [1..0]
hcntl1
node istype ’com’;
hcntl0
node istype ’com’;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Add–on busy flag
ao_bsy
pin istype ’reg_d, dc, buffer’;
emif_ack
pin istype ’reg_d, dc, buffer’;
h,l,x = 1, 0, .X. ;
”Latched pass–thru address bits
pt_addr = [pt_addr4..pt_addr0] ;
”PCI Controller BAR decode. The S5933 controls the PTNUM[1..0] signals
”to indicate which base region is being accessed.
BAR1
= !PTNUM1 & !PTNUM0;
”JTAG TBC register access
BAR2
= !PTNUM1 & PTNUM0;
”CPLD register access
BAR3
= PTNUM1 & !PTNUM0;
”DSP HPI register access
BAR4
= PTNUM1 & PTNUM0;
”DSP HPI auto–inc data access
”PCI Pass–thru Access Indications
TBC_WR
= !PTATN_ & PTWR
TBC_RD
= !PTATN_ & !PTWR
REG_WR
= !PTATN_ & PTWR
REG_RD
= !PTATN_ & !PTWR
HPI_WR
= !PTATN_ & PTWR
HPI_RD
= !PTATN_ & !PTWR
HPI_BURST_WR = !PTATN_ & PTWR
HPI_BURST_RD = !PTATN_ & !PTWR
&
&
&
&
&
&
&
&
BAR1;
BAR1;
BAR2;
BAR2;
BAR3;
BAR3;
BAR4;
BAR4;
”JTAG TBC register write
”JTAG TBC register read
”CPLD register write
”CPLD register read
”DSP HPI register write
”DSP HPI register read
”DSP HPI auto–inc data write
”DSP HPI auto–inc data read
”PCI add–on control register group
ao_cntl
= [PT_ADR_, AO_SEL_, AO_WR_, AO_RD_,
AO_ADR6, AO_ADR5, AO_ADR4, AO_ADR3, AO_ADR2,
AO_BE3_, AO_BE2_, AO_BE1_, AO_BE0_,
RDFIFO_, WRFIFO_, PT_RDY_,
pcireg_ce, pcireg_oe];
”=================================================================================
”PCI add–on control register group vectors
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”A add–on control vector is output to the S5933 PCI controller at each
”state of the defined accesses. Since the state machine executes at
”the PCI clock rate of 33 MHz, each state lasts a minimum of 30 ns.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”
P A A A A A A A A A A A A R W P p p
”
T O O O O O O O O O O O O F F T c c
”
_ _ _ _ _ _ _ _ _ _ _ _ _ I I _ i i
”
A S W R A A A A A B B B B F F R r r
”
D E R D D D D D D E E E E O O D e e
”
R L _ _ R R R R R 3 2 1 0 _ _ Y g g
”
_ _
6 5 4 3 2 _ _ _ _
_ _ _
”
c o
”
e e
EVM CPLD Equations
C-60
”Constants
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
=
=
=
=
=
[1,1,1,1,0,0,0,0,0,1,1,1,1,1,1,1,0,0];
[1,1,1,1,0,0,0,0,0,1,1,1,1,1,1,1,0,0];
[0,0,1,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
[1,0,1,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
[1,0,0,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
”TBC Write
AOC_TBC_WR1
AOC_TBC_WR2
AOC_TBC_WR3
AOC_TBC_WR4
=
=
=
=
[1,0,1,0,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
[1,0,1,0,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
[1,0,1,0,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
[1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
”TBC Read
AOC_TBC_RD1
AOC_TBC_RD2
AOC_TBC_RD3
AOC_TBC_RD4
=
=
=
=
[1,0,0,1,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
[1,0,0,1,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
[1,0,0,1,0,1,0,1,1,0,0,0,0,1,1,1,0,0]
[1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
”PCI–mapped
AOC_REG_WR1
AOC_REG_WR2
AOC_REG_WR3
Register Write
= [1,0,1,0,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
= [1,0,1,0,0,1,0,1,1,0,0,0,0,1,1,1,1,0];
= [1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
”PCI–mapped
AOC_REG_RD1
AOC_REG_RD2
AOC_REG_RD3
Register Read
= [1,0,1,1,0,1,0,1,1,0,0,0,0,1,1,1,0,0];
= [1,0,0,1,0,1,0,1,1,0,0,0,0,1,1,1,0,1];
= [1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,1];
”HPI Write (BAR3)
AOC_HPI_WR1 = [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_WR2 = [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_WR3 = [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_WR4 = [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_WR5 = [1,0,1,0,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_WR6 = [1,0,1,0,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_WR7 = [1,0,1,0,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_WR8 = [1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
”Wait for PCI/EMIF access
”EMIF access
”PCI access
”BAR4 write
”BAR4 read
C-61
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Idle
AOC_IDLE1
AOC_IDLE2
AOC_IDLE3
AOC_IDLE4
AOC_IDLE5
”HPI Burst Write (BAR4)
AOC_HPI_BWR1= [1,0,1,0,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_BWR2= [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BWR3= [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BWR4= [1,0,1,0,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BWR5= [1,0,1,0,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_BWR6= [1,0,1,0,0,1,0,1,1,0,0,1,1,1,1,0,0,0];
AOC_HPI_BWR7= [1,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_BWR8= [1,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
”HPI Burst Read (BAR4)
AOC_HPI_BRD1= [1,0,0,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_BRD2= [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BRD3= [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BRD4= [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_BRD5= [1,0,0,1,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_BRD6= [1,0,0,1,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_BRD7= [1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
AOC_HPI_BRD8= [1,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_BRD9= [1,1,1,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
”EMIF Write to PCI Controller Register
AOC_EMIF_WR1= [1,0,0,1,EA6,EA5,EA4,EA3,EA2,BE3_,BE2_,BE1_,BE0_,1,1,1,0,0];
AOC_EMIF_WR2= [1,0,1,1,EA6,EA5,EA4,EA3,EA2,BE3_,BE2_,BE1_,BE0_,1,1,1,0,0];
AOC_EMIF_WR3= [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0];
”EMIF Read from PCI Controller Register
AOC_EMIF_RD1= [1,0,1,0,EA6,EA5,EA4,EA3,EA2,BE3_,BE2_,BE1_,BE0_,1,1,1,0,0];
AOC_EMIF_RD2= [1,0,1,0,EA6,EA5,EA4,EA3,EA2,BE3_,BE2_,BE1_,BE0_,1,1,1,0,0];
”EMIF Write to FIFO
AOC_FIFO_WR1= [1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0,0];
AOC_FIFO_WR2= [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0];
”EMIF Read from FIFO
AOC_FIFO_RD1= [1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,0,0];
AOC_FIFO_RD2= [1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,0,0];
AOC_FIFO_RD3= [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0];
EVM CPLD Equations
C-62
”HPI Read (BAR3)
AOC_HPI_RD1 = [1,0,0,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_RD2 = [1,0,0,1,0,1,0,1,1,1,1,1,1,1,1,1,0,0];
AOC_HPI_RD3 = [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_RD4 = [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_RD5 = [1,0,0,1,0,1,0,1,1,1,1,0,0,1,1,1,0,0];
AOC_HPI_RD6 = [1,0,0,1,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_RD7 = [1,0,0,1,0,1,0,1,1,0,0,1,1,1,1,1,0,0];
AOC_HPI_RD8 = [1,0,1,1,0,1,0,1,1,1,1,1,1,1,1,0,0,0];
”Done
AOC_DONE
= [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0];
”TBC/HPI control register group
th_cntl= [TBC_WR_,TBC_RD_,HCS_,HDS1_,
TBCA4_HCNTL1,TBCA3_HCNTL0,TBCA2_HHWIL,
TBCA1_HBE1_,TBCA0_HBE0_];
C-63
”TBC Write
THC_TBC_WR1
THC_TBC_WR2
THC_TBC_WR3
THC_TBC_WR4
=
=
=
=
[1,1,1,1,pt_addr4..pt_addr0];
[0,1,1,1,pt_addr4..pt_addr0];
[1,1,1,1,pt_addr4..pt_addr0];
[1,1,1,1,1,1,1,1,1];
”TBC Read
THC_TBC_RD1
THC_TBC_RD2
THC_TBC_RD3
THC_TBC_RD4
=
=
=
=
[1,1,1,1,pt_addr4..pt_addr0];
[1,0,1,1,pt_addr4..pt_addr0];
[1,0,1,1,pt_addr4..pt_addr0];
[1,0,1,1,pt_addr4..pt_addr0];
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”=================================================================================
”TBC/HPI control register group vectors
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”A TBC/HPI control vector is output to the JTAG TBC and DSP HPI at each
”state of the defined accesses. Since the state machine executes at
”the PCI clock rate of 33 MHz, each state lasts a minimum of 30 ns.
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”
T T H H T T T T T
”
B B C D B B B B B
”
C C S S C C C C C
”
_ _ _ 1 A A A A A
”
W R
_ 4 3 2 1 0
”
R D
_ _ _ _ _
”
_ _
H H H H H
”
C C H B B
”
N N W E E
”
T T I 1 0
”
L L L _ _
”
1 0
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Idle
THC_IDLE1
= [1,1,1,1,1,1,1,1,1];
THC_IDLE2
= [1,1,1,1,1,1,1,1,1];
THC_IDLE3
= [1,1,1,1,1,1,1,1,1];
Register Write
= [1,1,1,1,1,1,1,1,1];
= [1,1,1,1,1,1,1,1,1];
= [1,1,1,1,1,1,1,1,1];
”PCI–mapped
THC_REG_RD1
THC_REG_RD2
THC_REG_RD3
Register Read
= [1,1,1,1,1,1,1,1,1];
= [1,1,1,1,1,1,1,1,1];
= [1,1,1,1,1,1,1,1,1];
”HPI Write (BAR3)
THC_HPI_WR1 = [1,1,0,1,1,1,1,1,1];
THC_HPI_WR2 = [1,1,0,1,hcntl1,hcntl0,0,pt_be1_,pt_be0_];
THC_HPI_WR3 = [1,1,0,0,hcntl1,hcntl0,0,pt_be1_,pt_be0_];
THC_HPI_WR4 = [1,1,0,0,hcntl1,hcntl0,0,pt_be1_,pt_be0_];
THC_HPI_WR5 = [1,1,0,1,hcntl1,hcntl0,1,pt_be1_,pt_be0_];
THC_HPI_WR6 = [1,1,0,0,hcntl1,hcntl0,1,pt_be3_,pt_be2_];
THC_HPI_WR7 = [1,1,0,1,1,1,1,pt_be3_,pt_be2_];
THC_HPI_WR8 = [1,1,1,1,1,1,1,1,1];
”HPI Read (BAR3)
THC_HPI_RD1 = [1,1,0,1,1,1,1,1,1];
THC_HPI_RD2 = [1,1,0,1,hcntl1,hcntl0,0,1,1];
THC_HPI_RD3 = [1,1,0,0,hcntl1,hcntl0,0,1,1];
THC_HPI_RD4 = [1,1,0,0,hcntl1,hcntl0,0,1,1];
THC_HPI_RD5 = [1,1,0,0,hcntl1,hcntl0,0,1,1];
THC_HPI_RD6 = [1,1,0,1,hcntl1,hcntl0,1,1,1];
THC_HPI_RD7 = [1,1,0,0,hcntl1,hcntl0,1,1,1];
THC_HPI_RD8 = [1,1,0,1,1,1,1,1,1];
”HPI Burst Write (BAR4)
THC_HPI_BWR1= [1,1,0,1,1,0,0,0,0];
THC_HPI_BWR2= [1,1,0,0,1,0,0,0,0];
THC_HPI_BWR3= [1,1,0,0,1,0,0,0,0];
THC_HPI_BWR4= [1,1,0,1,1,0,1,0,0];
THC_HPI_BWR5= [1,1,0,0,1,0,1,0,0];
THC_HPI_BWR6= [1,1,0,1,1,1,1,0,0];
THC_HPI_BWR7= [1,1,1,1,1,1,1,1,1];
THC_HPI_BWR8= [1,1,1,1,1,1,1,1,1];
”HPI Burst Read (BAR4)
THC_HPI_BRD1= [1,1,0,1,1,0,0,1,1];
THC_HPI_BRD2= [1,1,0,0,1,0,0,1,1];
THC_HPI_BRD3= [1,1,0,0,1,0,0,1,1];
THC_HPI_BRD4= [1,1,0,0,1,0,0,1,1];
THC_HPI_BRD5= [1,1,0,1,1,0,1,1,1];
EVM CPLD Equations
C-64
”PCI–mapped
THC_REG_WR1
THC_REG_WR2
THC_REG_WR3
THC_HPI_BRD6=
THC_HPI_BRD7=
THC_HPI_BRD8=
THC_HPI_BRD9=
[1,1,0,0,1,0,1,1,1];
[1,1,0,1,1,1,1,1,1];
[1,1,1,1,1,1,1,1,1];
[1,1,1,1,1,1,1,1,1];
”EMIF Write to Register
THC_EMIF_WR1= [1,1,1,1,1,1,1,1,1];
THC_EMIF_WR2= [1,1,1,1,1,1,1,1,1];
THC_EMIF_WR3= [1,1,1,1,1,1,1,1,1];
”EMIF Read from Register
THC_EMIF_RD1= [1,1,1,1,1,1,1,1,1];
THC_EMIF_RD2= [1,1,1,1,1,1,1,1,1];
”EMIF Write to FIFO
THC_FIFO_WR1= [1,1,1,1,1,1,1,1,1];
THC_FIFO_WR2= [1,1,1,1,1,1,1,1,1];
”EMIF Read from FIFO
THC_FIFO_RD1= [1,1,1,1,1,1,1,1,1];
THC_FIFO_RD2= [1,1,1,1,1,1,1,1,1];
THC_FIFO_RD3= [1,1,1,1,1,1,1,1,1];
”Done
THC_DONE
= [1,1,1,1,1,1,1,1,1];
TBC_WR1
TBC_WR2
TBC_WR3
TBC_WR4
=
=
=
=
[
[
[
[
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
];
];
];
];
”0x4100
”0x4101
”0x4102
”0x4104
TBC_RD1
TBC_RD2
TBC_RD3
TBC_RD4
=
=
=
=
[
[
[
[
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
];
];
];
];
”0x4000
”0x4001
”0x4002
”0x4004
C-65
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Add–on state machine states
”
T H HB R E F RW
SUB–STATE
STATE
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
AO_IDLE1
= [ 0, 0, 0, 0, 0, 0, 0,
0,0,0,0,0,0,0,0 ];
”0x0000
AO_IDLE2
= [ 0, 0, 0, 0, 0, 0, 0,
0,0,0,0,0,0,0,1 ];
”0x0001
AO_IDLE3
= [ 0, 0, 0, 0, 0, 0, 0,
0,0,0,0,0,0,1,0 ];
”0x0002
AO_DONE
= [ 0, 0, 0, 0, 0, 0, 0,
1,0,0,0,0,0,0,0 ];
”0x0080
=
=
=
=
=
=
=
=
[
[
[
[
[
[
[
[
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
0,0,0,0,1,0,0,0
0,0,0,1,0,0,0,0
0,0,1,0,0,0,0,0
0,1,0,0,0,0,0,0
];
];
];
];
];
];
];
];
”0x2100
”0x2101
”0x2102
”0x2104
”0x2108
”0x2110
”0x2120
”0x2140
HPI_RD1
HPI_RD2
HPI_RD3
HPI_RD4
HPI_RD5
HPI_RD6
HPI_RD7
HPI_RD8
=
=
=
=
=
=
=
=
[
[
[
[
[
[
[
[
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
0,0,0,0,1,0,0,0
0,0,0,1,0,0,0,0
0,0,1,0,0,0,0,0
0,1,0,0,0,0,0,0
];
];
];
];
];
];
];
];
”0x2000
”0x2001
”0x2002
”0x2004
”0x2008
”0x2010
”0x2020
”0x2040
HPI_BURST_WR1
HPI_BURST_WR2
HPI_BURST_WR3
HPI_BURST_WR4
HPI_BURST_WR5
HPI_BURST_WR6
HPI_BURST_WR7
HPI_BURST_WR8
=
=
=
=
=
=
=
=
[
[
[
[
[
[
[
[
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
0,0,0,0,1,0,0,0
0,0,0,1,0,0,0,0
0,0,1,0,0,0,0,0
0,1,0,0,0,0,0,0
];
];
];
];
];
];
];
];
”0x3100
”0x3101
”0x3102
”0x3104
”0x3108
”0x3110
”0x3120
”0x3140
HPI_BURST_RD1
HPI_BURST_RD2
HPI_BURST_RD3
HPI_BURST_RD4
HPI_BURST_RD5
HPI_BURST_RD6
HPI_BURST_RD7
HPI_BURST_RD8
HPI_BURST_RD9
=
=
=
=
=
=
=
=
=
[
[
[
[
[
[
[
[
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,0,0,0,0,0,0,0
0,0,0,0,0,0,0,1
0,0,0,0,0,0,1,0
0,0,0,0,0,1,0,0
0,0,0,0,1,0,0,0
0,0,0,1,0,0,0,0
0,0,1,0,0,0,0,0
0,1,0,0,0,0,0,0
1,0,0,0,0,0,0,0
];
];
];
];
];
];
];
];
];
”0x3000
”0x3001
”0x3002
”0x3004
”0x3008
”0x3010
”0x3020
”0x3040
”0x3080
REG_WR1
REG_WR2
REG_WR3
= [ 0, 0, 0,
= [ 0, 0, 0,
= [ 0, 0, 0,
1, 0, 0, 1,
1, 0, 0, 1,
1, 0, 0, 1,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
0,0,0,0,0,0,1,0 ];
”0x0900
”0x0901
”0x0902
REG_RD1
REG_RD2
REG_RD3
= [ 0, 0, 0,
= [ 0, 0, 0,
= [ 0, 0, 0,
1, 0, 0, 0,
1, 0, 0, 0,
1, 0, 0, 0,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
0,0,0,0,0,0,1,0 ];
”0x0800
”0x0801
”0x0802
EVM CPLD Equations
C-66
HPI_WR1
HPI_WR2
HPI_WR3
HPI_WR4
HPI_WR5
HPI_WR6
HPI_WR7
HPI_WR8
EMIF_WR1
EMIF_WR2
EMIF_WR3
= [ 0, 0, 0,
= [ 0, 0, 0,
= [ 0, 0, 0,
0, 1, 0, 1,
0, 1, 0, 1,
0, 1, 0, 1,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
0,0,0,0,0,0,1,0 ];
”0x0500
”0x0501
”0x0502
EMIF_RD1
EMIF_RD2
= [ 0, 0, 0,
= [ 0, 0, 0,
0, 1, 0, 0,
0, 1, 0, 0,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
”0x0400
”0x0401
FIFO_WR1
FIFO_WR2
= [ 0, 0, 0,
= [ 0, 0, 0,
0, 0, 1, 1,
0, 0, 1, 1,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
”0x0300
”0x0301
FIFO_RD1
FIFO_RD2
FIFO_RD3
= [ 0, 0, 0,
= [ 0, 0, 0,
= [ 0, 0, 0,
0, 0, 1, 0,
0, 0, 1, 0,
0, 0, 1, 0,
0,0,0,0,0,0,0,0 ];
0,0,0,0,0,0,0,1 ];
0,0,0,0,0,0,1,0 ];
”0x0200
”0x0201
”0x0202
Equations
”Assert PCI float when not in PCI slot
PCI_FLT_ = !PCI_DET_;
”PCI add–on bus output enable when pcireg_oe set to 1
pcireg_oe.ar = RESET;
pcireg_oe.clk = PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” PCI Add–on Bus Control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Add–on bus control signals
C-67
”Default active–low control signals to high at reset
PT_ADR_.ap = RESET;
PT_RDY_.ap = RESET;
AO_SEL_.ap = RESET;
AO_WR_.ap = RESET;
AO_RD_.ap = RESET;
AO_ADR.ar = RESET;
AO_BE3_.ap = RESET;
AO_BE2_.ap = RESET;
AO_BE1_.ap = RESET;
AO_BE0_.ap = RESET;
RDFIFO_.ap = RESET;
WRFIFO_.ap = RESET;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”PCI add–on bus clock enable when pcireg_ce set to 1
pcireg_ce.ar = RESET;
pcireg_ce.clk = PCICLK;
”Add–on busy flag
ao_bsy.ar = RESET;
ao_bsy.clk = PCICLK;
”EMIF acknowledgement flag
emif_ack.ar = RESET;
emif_ack.clk = PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” JTAG TBC / DSP HPI Control
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”TBC control signals
”Default active–low control signals to high at reset
TBC_WR_.ap
= RESET;
TBC_RD_.ap
= RESET;
TBCA4_HCNTL1.ap = RESET;
TBCA3_HCNTL0.ap = RESET;
TBCA2_HHWIL.ap = RESET;
TBCA1_HBE1_.ap = RESET;
TBCA0_HBE0_.ap = RESET;
”All registers are clocked by PCI clock
TBC_WR_.clk
= PCICLK;
TBC_RD_.clk
= PCICLK;
TBCA4_HCNTL1.clk= PCICLK;
TBCA3_HCNTL0.clk= PCICLK;
TBCA2_HHWIL.clk = PCICLK;
TBCA1_HBE1_.clk = PCICLK;
TBCA0_HBE0_.clk = PCICLK;
EVM CPLD Equations
C-68
”All registers are clocked by PCI clock
AO_SEL_.clk= PCICLK;
AO_WR_.clk = PCICLK;
AO_RD_.clk = PCICLK;
PT_ADR_.clk= PCICLK;
PT_RDY_.clk= PCICLK;
AO_ADR.clk = PCICLK;
AO_BE3_.clk= PCICLK;
AO_BE2_.clk= PCICLK;
AO_BE1_.clk= PCICLK;
AO_BE0_.clk= PCICLK;
RDFIFO_.clk= PCICLK;
WRFIFO_.clk= PCICLK;
”TBC ready synchronization
tbcrdy
:= !TBC_RDY_;
tbcrdy.ar
= RESET;
tbcrdy.clk = PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” DSP HPI Control Signals
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”HPI control signals default values
HCS_.ap
= RESET;
”HCS_ defaults to 1
HDS1_.ap
= RESET;
”HDS1_ defaults to 1
HRW.ar
= RESET;
”HRW defaults to 0
”HPI control signals clocked by PCI clock
HCS_.clk
= PCICLK;
HDS1_.clk = PCICLK;
HRW.clk
= PCICLK;
”HPI HCNTL[1..0] control signals
”Decode host control bits based on target address
”hcntl1 is a ’1’ for both BAR3 and BAR4 data register accesses
hcntl1 = (!PTATN_ & BAR3 & pt_addr1 & !pt_addr0) #
(!PTATN_ & BAR4);
”hcntl0 is a ’1’ for BAR3 address and data register accesses
hcntl0 = (!PTATN_ & BAR3 & pt_addr1) #
(!PTATN_ & BAR3 & pt_addr0);
”HPI ready synchronization
hrdy
:= !DSP_HRDY_;
hrdy.ar = RESET;
hrdy.clk = PCICLK;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” PCI Add–on State Machine
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
aos.ar = RESET;
”Default to AO_IDLE1 state at reset
aos.clk = PCICLK;
”Add–on state machine clocked by PCI clock
aos.ce = !PCI_DET_;
”Add–on state machine only active in PCI slot
@dcstate
C-69
”The add–on state machine drives the add–on control interface and
”TBC/HPI control interface signals according to the states and tables
”listed above.
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Host read/write is opposite polarity of PCI pass–thru read/write
HRW
:= !PTWR;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” Wait for PCI or EMIF Access Request
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Loop waiting on PTATN_ to go active or EMIF PCI controller access request
state AO_IDLE1:
ao_cntl := AOC_IDLE1;
th_cntl := THC_IDLE1;
”Check for EMIF request of PCI controller
if (emif_req) then AO_IDLE2 with {
ao_bsy := 0;
}
else
”Check for PCI pass–thru access request
if (!PTATN_ & !emif_req) then AO_IDLE3 with {
ao_bsy := 1;
}
”If no EMIF or PCI access requests, state in this state
else AO_IDLE1;
”EMIF request for PCI controller access
state AO_IDLE2:
ao_cntl := AOC_IDLE2;
th_cntl := THC_IDLE2;
ao_bsy := 0;
emif_ack:= 0;
”Determine type of EMIF PCI controller access (register read/write
”or FIFO read/write)
”Start the requested PT access.
”EMIF PCI Controller Register Write Request
if (!EA16 & !AWE_) then EMIF_WR1 with {
ao_cntl := AOC_EMIF_WR1;
}
”EMIF PCI Controller Register Read Request
else if (!EA16 & !ARE_) then EMIF_RD1 with {
ao_cntl := AOC_EMIF_RD1;
}
”EMIF PCI FIFO Write Request
else if (EA16 & !AWE_) then FIFO_WR1 with {
ao_cntl := AOC_FIFO_WR1;
}
EVM CPLD Equations
C-70
state_diagram aos
”EMIF PCI FIFO Read Request
else if (EA16 & !ARE_) then FIFO_RD1 with {
ao_cntl := AOC_FIFO_RD1;
}
”Ignore Invalid Requests
else AO_IDLE1 with {
ao_cntl := AOC_IDLE1;
}
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” PCI Pass–thru Access Requested
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Pass–thru address is latched at end of this state in pt_addr[4..0]
state AO_IDLE3:
th_cntl := THC_IDLE3;
ao_bsy := 1;
emif_ack:= 0;
”Determine type of PCI pass–thru access (TBC,Register,HPI) and
”read or write.
”TBC Write
if (TBC_WR) then TBC_WR1 with {
ao_cntl := AOC_IDLE3;
}
”PCI–mapped Register Write
else if (REG_WR) then REG_WR1 with {
ao_cntl := AOC_IDLE3;
}
”PCI–mapped Register Read
else if (REG_RD) then REG_RD1 with {
ao_cntl := AOC_IDLE3;
}
C-71
”HPI BAR3 Write
else if (HPI_WR) then HPI_WR1 with {
ao_cntl := AOC_IDLE3;
}
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”TBC Read
else if (TBC_RD) then TBC_RD1 with {
ao_cntl := AOC_IDLE3;
}
”HPI BAR4 Write
else if (HPI_BURST_WR) then HPI_BURST_WR1 with {
ao_cntl := AOC_IDLE4;
}
”HPI BAR4 Read
else if (HPI_BURST_RD) then HPI_BURST_RD1 with{
ao_cntl := AOC_IDLE5;
}
else AO_IDLE1 with {
ao_cntl := AOC_IDLE1;
}
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” JTAG TBC Register Write
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Loop until TBC is ready.
state TBC_WR1:
ao_cntl := AOC_TBC_WR1;
th_cntl := THC_TBC_WR1;
ao_bsy := 1;
emif_ack:= 0;
”Check TBC ready signal
if (tbcrdy) then TBC_WR2
else TBC_WR1;
state TBC_WR2:
ao_cntl := AOC_TBC_WR2;
th_cntl := THC_TBC_WR2;
ao_bsy := 1;
emif_ack:= 0;
goto TBC_WR3;
state TBC_WR3:
ao_cntl := AOC_TBC_WR3;
th_cntl := THC_TBC_WR3;
ao_bsy := 1;
emif_ack:= 0;
goto TBC_WR4;
EVM CPLD Equations
C-72
”HPI BAR3 Read
else if (HPI_RD) then HPI_RD1 with {
ao_cntl := AOC_IDLE3;
}
”PCI controller data is strobed into TBC register
state TBC_WR4:
ao_cntl := AOC_TBC_WR4;
th_cntl := THC_TBC_WR4;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” JTAG TBC Register Read
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Loop until TBC is ready
state TBC_RD1:
ao_cntl := AOC_TBC_RD1;
th_cntl := THC_TBC_RD1;
ao_bsy := 1;
emif_ack:= 0;
if (tbcrdy) then TBC_RD2
else TBC_RD1;
state TBC_RD3:
ao_cntl := AOC_TBC_RD3;
th_cntl := THC_TBC_RD3;
ao_bsy := 1;
emif_ack:= 0;
goto TBC_RD4;
”TBC data is latched into PCI controller
state TBC_RD4:
ao_cntl := AOC_TBC_RD4;
th_cntl := THC_TBC_RD4;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
C-73
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
state TBC_RD2:
ao_cntl := AOC_TBC_RD2;
th_cntl := THC_TBC_RD2;
ao_bsy := 1;
emif_ack:= 0;
goto TBC_RD3;
state REG_WR2:
ao_cntl := AOC_REG_WR2;
th_cntl := THC_REG_WR2;
ao_bsy := 1;
emif_ack:= 0;
goto REG_WR3;
”PCI controller data is latched into CPLD register
state REG_WR3:
ao_cntl := AOC_REG_WR3;
th_cntl := THC_REG_WR3;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” CPLD Register Read
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state REG_RD1:
ao_cntl := AOC_REG_RD1;
th_cntl := THC_REG_RD1;
ao_bsy := 1;
emif_ack:= 0;
goto REG_RD2;
state REG_RD2:
ao_cntl := AOC_REG_RD2;
th_cntl := THC_REG_RD2;
ao_bsy := 1;
emif_ack:= 0;
goto REG_RD3;
EVM CPLD Equations
C-74
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” CPLD Register Write
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state REG_WR1:
ao_cntl := AOC_REG_WR1;
th_cntl := THC_REG_WR1;
ao_bsy := 1;
emif_ack:= 0;
goto REG_WR2;
state REG_RD3:
ao_cntl := AOC_REG_RD3;
th_cntl := THC_REG_RD3;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” DSP HPI Register Write
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Assert HCS– low and register HCNTLx bits based on target address
state HPI_WR1:
ao_cntl := AOC_HPI_WR1;
th_cntl := THC_HPI_WR1;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR2;
”Assert HCS– low and setup HPI control signals
state HPI_WR2:
ao_cntl := AOC_HPI_WR2;
th_cntl := THC_HPI_WR2;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR3;
”Wait for HPI ready (after 1 clock synchronization)
”before bringing HDS1– high again
state HPI_WR4:
ao_cntl := AOC_HPI_WR4;
th_cntl := THC_HPI_WR4;
ao_bsy := 1;
emif_ack:= 0;
C-75
if (hrdy) then HPI_WR5;
else HPI_WR4;
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Assert HDS1– (HSTROBE–) low
state HPI_WR3:
ao_cntl := AOC_HPI_WR3;
th_cntl := THC_HPI_WR3;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR4;
”Assert HDS1– (HSTROBE–) low to begin 2nd 16–bit word transfer
state HPI_WR6:
ao_cntl := AOC_HPI_WR6;
th_cntl := THC_HPI_WR6;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR7;
”Bring HDS1– (HSTROBE–) high to clock in 2nd 16–bit word (triggers Aux DMA)
state HPI_WR7:
ao_cntl := AOC_HPI_WR7;
th_cntl := THC_HPI_WR7;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR8;
”Bring HCS– high and assert PT_RDY_ low to PCI controller
state HPI_WR8:
ao_cntl := AOC_HPI_WR8;
th_cntl := THC_HPI_WR8;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” DSP HPI Register Read
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Assert HCS– low and register HCNTLx bits based on target address
state HPI_RD1:
ao_cntl := AOC_HPI_RD1;
th_cntl := THC_HPI_RD1;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD2;
EVM CPLD Equations
C-76
”Bring HDS1– (HSTROBE–) high to clock in 1st 16–bit word
state HPI_WR5:
ao_cntl := AOC_HPI_WR5;
th_cntl := THC_HPI_WR5;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_WR6;
”Setup HPI control signals
state HPI_RD2:
ao_cntl := AOC_HPI_RD2;
th_cntl := THC_HPI_RD2;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD3;
”Assert HDS1– (HSTROBE–) low to request read
state HPI_RD3:
ao_cntl := AOC_HPI_RD3;
th_cntl := THC_HPI_RD3;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD4;
”Wait for data read and HPI ready clock synchronization
state HPI_RD4:
ao_cntl := AOC_HPI_RD4;
th_cntl := THC_HPI_RD4;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD5;
”When HPI is ready (data is available) goto next state
if (hrdy) then HPI_RD6;
else HPI_RD5;
”Set HDS1– high again, write 1st 16–bit data word into PCI controller
state HPI_RD6:
ao_cntl := AOC_HPI_RD6;
th_cntl := THC_HPI_RD6;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD7;
C-77
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Wait for HPI ready (1st 16–bit data word available)
state HPI_RD5:
ao_cntl := AOC_HPI_RD5;
th_cntl := THC_HPI_RD5;
ao_bsy := 1;
emif_ack:= 0;
”Set HDS1– high again, write 2nd 16–bit word into PCI controller
state HPI_RD8:
ao_cntl := AOC_HPI_RD8;
th_cntl := THC_HPI_RD8;
ao_bsy := 1;
emif_ack:= 0;
goto AO_DONE;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” DSP HPI Data Register Write (Address Auto–Inc Mode) with Burst Support
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” Assert HCS– low and setup HPI control signals
state HPI_BURST_WR1:
ao_cntl := AOC_HPI_BWR1;
th_cntl := THC_HPI_BWR1;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR2;
”Assert HDS1– (HSTROBE–) low
state HPI_BURST_WR2:
ao_cntl := AOC_HPI_BWR2;
th_cntl := THC_HPI_BWR2;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR3;
”Wait for HPI ready (after 1 clock synchronization)
”before bring HDS1– high again
state HPI_BURST_WR3:
ao_cntl := AOC_HPI_BWR3;
th_cntl := THC_HPI_BWR3;
ao_bsy := 1;
emif_ack:= 0;
if (hrdy) then HPI_BURST_WR4;
else HPI_BURST_WR3;
EVM CPLD Equations
C-78
”Assert HDS1– (HSTROBE–) low to request 2nd 16–bit data word
state HPI_RD7:
ao_cntl := AOC_HPI_RD7;
th_cntl := THC_HPI_RD7;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_RD8;
”Assert HDS1– (HSTROBE–) low to begin 2nd 16–bit word transfer
state HPI_BURST_WR4:
ao_cntl := AOC_HPI_BWR4;
th_cntl := THC_HPI_BWR4;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR5;
”Bring HDS1– (HSTROBE–) high to clock in 2nd 16–bit word (triggers Aux DMA)
state HPI_BURST_WR5:
ao_cntl := AOC_HPI_BWR5;
th_cntl := THC_HPI_BWR5;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR6;
”Bring HCS– high and assert PT_RDY_ low to PCI controller
state HPI_BURST_WR6:
ao_cntl := AOC_HPI_BWR6;
th_cntl := THC_HPI_BWR6;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR7;
”Check if another value is available from the PCI controller (burst)
state HPI_BURST_WR8:
ao_cntl := AOC_HPI_BWR8;
th_cntl := THC_HPI_BWR8;
ao_bsy := 1;
emif_ack:= 0;
case
”PT is ready with another word.
(!PTATN_ & !PTBURST_): HPI_BURST_WR1 with {}
”Burst is over. Empty the pipe.
(!PTATN_ & PTBURST_): HPI_BURST_WR1 with {}
C-79
”Burst is not over but PT is not ready with another word.
( PTATN_ & !PTBURST_): HPI_BURST_WR8 with {}
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Bring PT_RDY_ back high, wait for response from PCI controller
state HPI_BURST_WR7:
ao_cntl := AOC_HPI_BWR7;
th_cntl := THC_HPI_BWR7;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_WR8;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” DSP HPI Data Register Read (Address Auto–Inc Mode) with Burst Support
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
”Assert HCS– low and setup HPI control signals
state HPI_BURST_RD1:
ao_cntl := AOC_HPI_BRD1;
th_cntl := THC_HPI_BRD1;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD2;
”Assert HDS1– (HSTROBE–) low to request read
state HPI_BURST_RD2:
ao_cntl := AOC_HPI_BRD2;
th_cntl := THC_HPI_BRD2;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD3;
”Wait for data read and HPI ready clock synchronization
state HPI_BURST_RD3:
ao_cntl := AOC_HPI_BRD3;
th_cntl := THC_HPI_BRD3;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD4;
”Wait for HPI ready (1st 16–bit data word available)
state HPI_BURST_RD4:
ao_cntl := AOC_HPI_BRD4;
th_cntl := THC_HPI_BRD4;
ao_bsy := 1;
emif_ack:= 0;
”When HPI is ready (data is available) goto next state
if (hrdy) then HPI_BURST_RD5;
else HPI_BURST_RD4;
EVM CPLD Equations
C-80
”Burst is over and the pipe is empty.
( PTATN_ & PTBURST_): AO_DONE with {
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
}
endcase;
”Set HDS1– high again, write 1st 16–bit data word into PCI controller
state HPI_BURST_RD5:
ao_cntl := AOC_HPI_BRD5;
th_cntl := THC_HPI_BRD5;
ao_bsy := 1;
emif_ack:= 0;
if (hrdy) then HPI_BURST_RD6
else HPI_BURST_RD5;
”Assert HDS1– (HSTROBE–) low to request 2nd 16–bit data word
state HPI_BURST_RD6:
ao_cntl := AOC_HPI_BRD6;
th_cntl := THC_HPI_BRD6;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD7;
”Set HDS1– high again, write 2nd 16–bit word into PCI controller
”Assert PT_RDY_ low to end 32–bit word transfer
state HPI_BURST_RD7:
ao_cntl := AOC_HPI_BRD7;
th_cntl := THC_HPI_BRD7;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD8;
”Check if PCI controller wants another value (burst)
state HPI_BURST_RD9:
ao_cntl := AOC_HPI_BRD9;
th_cntl := THC_HPI_BRD9;
ao_bsy := 1;
emif_ack:= 0;
case
”PT is ready with another word.
(!PTATN_ & !PTBURST_): HPI_BURST_RD1 with {}
C-81
”Burst is over. Empty the pipe.
(!PTATN_ & PTBURST_): HPI_BURST_RD1 with {}
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”Bring HCS– and PT_RDY_ high, wait for response from PCI controller
state HPI_BURST_RD8:
ao_cntl := AOC_HPI_BRD8;
th_cntl := THC_HPI_BRD8;
ao_bsy := 1;
emif_ack:= 0;
goto HPI_BURST_RD9;
”Burst is over and the pipe is empty.
( PTATN_ & PTBURST_): AO_DONE with {
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
}
endcase;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” EMIF PCI Controller Register Write
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state EMIF_WR1:
ao_cntl := AOC_EMIF_WR1;
th_cntl := THC_EMIF_WR1;
ao_bsy := 0;
emif_ack:= 1;
goto EMIF_WR2;
state EMIF_WR2:
ao_cntl := AOC_EMIF_WR2;
th_cntl := THC_EMIF_WR2;
ao_bsy := 0;
emif_ack:= 1;
goto EMIF_WR3;
state EMIF_WR3:
ao_bsy := 0;
ao_cntl := AOC_EMIF_WR3;
th_cntl := THC_EMIF_WR3;
emif_ack:= 1;
if (AWE_) then AO_IDLE1 with {
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
emif_ack:= 0;
}
else EMIF_WR3;
EVM CPLD Equations
C-82
”Burst is not over but PT is not ready with another word.
( PTATN_ & !PTBURST_): HPI_BURST_RD9 with {}
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” EMIF PCI Controller Register Read
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state EMIF_RD1:
ao_cntl := AOC_EMIF_RD1;
th_cntl := THC_EMIF_RD1;
ao_bsy := 0;
emif_ack:= 1;
goto EMIF_RD2;
state EMIF_RD2:
ao_bsy := 0;
ao_cntl := AOC_EMIF_RD2;
th_cntl := THC_EMIF_RD2;
emif_ack:= 1;
if (ARE_) then AO_IDLE1 with {
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
emif_ack:= 0;
}
else EMIF_RD2;
state FIFO_WR2:
ao_bsy := 0;
emif_ack:= 1;
ao_cntl := AOC_FIFO_WR2;
th_cntl := THC_FIFO_WR2;
C-83
if (AWE_) then AO_IDLE1 with
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
emif_ack:= 0;
}
else FIFO_WR2;
{
EVM CPLD Equations
TMS320C6x EVM CPLD Equations
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” EMIF PCI Controller FIFO Write
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state FIFO_WR1:
ao_cntl := AOC_FIFO_WR1;
th_cntl := THC_FIFO_WR1;
ao_bsy := 0;
emif_ack:= 1;
goto FIFO_WR2;
state FIFO_RD2:
ao_bsy := 0;
emif_ack:= 1;
ao_cntl := AOC_FIFO_RD2;
th_cntl := THC_FIFO_RD2;
if (ARE_) then FIFO_RD3 with {
ao_cntl := AOC_FIFO_RD3;
emif_ack:= 0;
}
else FIFO_RD2;
state FIFO_RD3:
ao_cntl := AOC_FIFO_RD3;
th_cntl := THC_FIFO_RD3;
ao_bsy := 0;
emif_ack:= 0;
goto AO_IDLE1;
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” Add–on Access Done
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state AO_DONE:
ao_cntl := AOC_DONE;
th_cntl := THC_DONE;
ao_bsy := 0;
emif_ack:= 0;
goto AO_IDLE1;
END
EVM CPLD Equations
C-84
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
” EMIF PCI Controller FIFO Read
”–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
state FIFO_RD1:
ao_cntl := AOC_FIFO_RD1;
th_cntl := THC_FIFO_RD1;
ao_bsy := 0;
emif_ack:= 1;
goto FIFO_RD2;
Appendix
AppendixDA
TMS320C6x EVM PCI Configuration EEPROM
This appendix documents the EEPROM used on the ’C6x EVM to initialize the
AMCC S5933 peripheral component interconnect (PCI) controller’s configuration space registers.
The S5933 PCI controller provides the configuration registers required to support PCI’s plug-and-play capability. The initialization of these registers is performed upon power up and system reset by the S5933, which clocks serial
data in from the EEPROM using a two-wire, bidirectional data transfer. This
automatic register initialization is performed since the S5933’s SNV pin is
pulled up on the EVM to indicate that a serial nonvolatile memory device is
present.
Table D–1 summarizes the contents of the 1K-byte EEPROM. Multibyte default values are stored in least-significant-byte to most-significant-byte (littleendian) order. The 64-byte configuration information is stored in the EEPROM
locations 0x40 to 0x7F. Locations 0x00 to 0x3F are reserved for future use by
Texas Instruments. Locations 0x80 to 0x3FF are available for user-defined,
nonvolatile storage that is accessible by both host and DSP software.
D-1
TMS320C6x EVM PCI Configuration EEPROM
Table D–1. PCI Configuration EEPROM Summary
EEPROM
Offset
Register
Initialized
0x00–0x3F
–
0x40–0x41
Description
Value
Selection
Reserved for future use
All 0x00
–
VID
Vendor identification
0x104C
TI
0x42–0x043
DID
Device identification
0x1002
EVM
0x44
–
Reserved
0x00
–
0x45
–
FIFO configuration
0xE1
PCI, async
0x46–0x47
–
Reserved
0x0000
–
0x48
RID
0x00
Rev. 0 board
0x49–0x4B
CLCD
0x0B4000
Coprocessor
0x4C
–
Reserved
0x00
–
0x4D
LAT
Master latency timer
0xF8
248 clocks
0x4E
HDR
Header type
0x00
One function
0x4F
BIST
Built-in self test
0x00
No BIST
0x50–0x53
BAR0
Base address register 0
0x10E8FFC0
16 DWORDs
0x54–0x57
BAR1
Base address register 1
0xFFFFFF80
32 DWORDs
0x58–0x5B
BAR2
Base address register 2
0xFFFFFF80
32 DWORDs
0x5C–0x5F
BAR3
Base address register 3
0xBFFFFFF0
4 DWORDs
0x60–0x63
BAR4
Base address register 4
0xBFFC0000
64K DWORDs
0x64–0x67
BAR5
Base address register 5
0x00000000
Not used
0x68–0x6F
–
All 0x00
–
0x70–0x73
EXROM
0x00000000
No ROM
0x74–0x7B
–
All 0x00
–
0x7C
INTLN
Interrupt line
0xFF
Autoassign IRQ
0x7D
INTPIN
Interrupt pin
0x01
INTA#
0x7E
MINGNT
Minimum grant
0x00
No min grant
0x7F
MAXLAT
Maximum latency
0x00
No max latency
0x80–0x3FF†
–
All 0x00
–
Revision identification register
Class code register
Reserved
Expansion ROM base address
Reserved
Not used (available)
† These address offsets are available for general-purpose use. This is a total of 896 bytes.
D-2
Appendix
AppendixEA
Glossary
A
A/D: See analog-to-digital.
adaptive differential pulse code modulation (ADPCM): A speech coding
method that calculates the difference between two consecutive speech
samples and encodes it using an adaptive filter to transmit at a lower rate
than the standard 64-kbps pulse code modulation technique.
ADC: See analog-to-digital converter.
address: The logical location of program code or data stored in memory.
administrative privileges: Authority to set software and hardware access;
includes access and privileges to install, manage, and maintain system
and application software and directories on a network server or individual
computer systems.
ADPCM: See adaptive differential pulse code modulation.
A-Law companding: See compress and expand (compand).
ALU: See arithmetic logic unit.
American National Standards Institute (ANSI): A standards-setting, nongovernment organization that develops and publishes standards for voluntary use in the United States.
American Standard Code for Information Interchange (ASCII): A standard computer code for representing and exchanging alphanumeric information.
analog-to-digital (A/D): Conversion of continuously variable electrical signals to discrete or discontinuous electrical signals.
analog-to-digital converter (ADC): A converter with internal sample-andhold circuitry used to translate an analog signal to a digital signal.
E-1
Glossary
ANSI C: A version of the C programming language that conforms to the C
standards defined by the American National Standards Institute.
application programming interface (API): A set of standard software
function calls and data formats that application programs use to interact
with other applications, device-specific drivers, or the operating system.
application-specific integrated circuit (ASIC): A custom chip designed
for a specific application. It is designed by integrating standard cells from
a library.
arithmetic logic unit (ALU): The section of the computer that carries out all
arithmetic operations (addition, subtraction, multiplication, division, or
comparison) and logic functions.
ASCII: See American Standard Code for Information Interchange.
ASIC: See application-specific integrated circuit.
assembler: A software program that creates a machine language program
from a source file that contains assembly language instructions,
directives, and macros. The assembler substitutes absolute operation
codes for symbolic operation codes, and absolute or relocatable
addresses for symbolic addresses.
assert: To make a digital logic device pin active. If the pin is active low, then
a low voltage on the pin asserts it. If the pin is active high, then a high
voltage asserts it.
B
ball grid array (BGA): An integrated circuit package in which the input and
output connections are solder balls arranged in a grid pattern.
base address register (BAR): A device configuration register that defines
the start address, length, and type of memory space required by a peripheral component interconnect (PCI) device. The value written to this
register during device configuration programs its memory decoder to detect accesses within the indicated range.
basic input/output system (BIOS): A firmware program that is responsible
for power-on testing and initialization of a computer. In addition, it may
provide runtime services for operating systems.
BBS: See bulletin board service.
benchmarking: A type of program execution that allows you to track the
number of CPU cycles consumed by a specific section of code.
E-2
Glossary
BGA: See ball grid array.
big endian: An addressing protocol in which bytes are numbered from left
to right within a word. More significant bytes in a word have lower
numbered addresses. Endian ordering is specific to hardware and is determined at reset. See also little endian.
BIOS: See basic input/output system.
bit:
boot:
A binary digit, either 0 or 1.
The process of loading a program into program memory.
boot mode: The method of loading a program into program memory. The
’C6x DSP supports booting from external ROM or the host port interface
(HPI).
bulletin board service (BBS): An electronic bulletin board that allows users
to post and read messages and download software.
bus master: A device capable of initiating a data transfer with another device.
byte:
A sequence of eight adjacent bits operated upon as a unit.
C
CBT: See crossbar technology.
CD-ROM: See compact disc read-only memory.
central processing unit (CPU): The CPU is the portion of the processor involved in arithmetic, shifting, and Boolean logic operations, as well as the
generation of data- and program-memory addresses. The CPU includes
the central arithmetic logic unit (CALU), the multiplier, and the auxiliary
register arithmetic unit (ARAU).
clock cycle: A cycle based on the input from the external clock.
clock mode (clock generator): One of the modes that sets the internal
CPU clock frequency to a fraction or multiple of the frequency of the input
clock signal CLKIN.
clock modes: Options used by the clock generator to change the internal
CPU clock frequency to a fraction or multiple of the frequency of the input
clock signal.
CMOS: See complementary metal oxide semiconductor.
Glossary
E-3
Glossary
coder-decoder or compression/decompression (codec): A device that
codes in one direction of transmission and decodes in another direction
of transmission.
common object file format (COFF): A system of object files configured according to a standard developed by AT&T. These files are relocatable in
memory space. The ’C6x code generation tools generate COFF files.
compact disc read-only memory (CD-ROM): A 4.7-inch optical disk that
can hold as much as 660M bytes of digital data. A CD-ROM can store
digitized audio, image, video, text, and application data.
compiler: A translation program that converts a high-level language set of
instructions into a target machine’s assembly language.
complementary metal oxide semiconductor (CMOS): An integrated circuit technology that uses complementary transistors to efficiently charge
and discharge capacitive loads in both the positive and negative directions and dissipates power only on transitions.
complex programmable logic device (CPLD): A digital, user-configurable
integrated circuit used to implement custom logic functions.
compress and expand (compand): A quantization scheme for audio signals in which the input signal is compressed and then, after processing,
is reconstructed at the output by expansion. There are two distinct companding schemes—A-law, used in Europe, and µ-law, used in the United
States.
CPLD: See complex programmable logic device.
crossbar technology (CBT): High-speed bus-connect devices that are
useful for bus isolation, multiplexing, and voltage translation. These devices have an on-state resistance of 5 ohms and a propagation delay of
250 ps.
CPU: See central processing unit.
D
D/A: See digital-to-analog.
DAC: See digital-to-analog converter.
daughterboard: A circuit board that connects to a motherboard to provide
additional capabilities and/or interfaces. See also motherboard.
E-4
Glossary
dB: See decibels.
debugger: A software interface used to identify and eliminate mistakes in a
program.
decibels (dB): A unit for measuring the level of signal relative to a defined
reference signal that follows it. For example, the notation dBm indicates
a signal power level relative to a 1 milliwatt reference signal.
device driver: Software that enables computer hardware to communicate
with a device. A device driver may also translate data and call other drivers to actually send data to a device.
device ID: Every peripheral component interconnect (PCI) device must
have a device ID configuration register to identify itself.
digital signal processor (DSP): A semiconductor that turns analog signals—such as sound or light—into digital signals, which are discrete or
discontinuous electrical impulses, so that they can be manipulated.
digital-to-analog (D/A): Conversion of discrete or discontinuous electrical
signals to continuously variable signals. See also digital-to-analog converter.
digital-to-analog converter (DAC): A device that converts a signal represented by a series of numbers (digital) to a continuously varying signal
(analog). See also digital-to-analog.
DIP: See dual in-line package.
direct memory access (DMA): A mechanism whereby a device other than
the host processor contends for, and receives, mastery of the memory
bus so that data transfers can take place independent of the host.
DLL: See dynamic link library.
DMA: See direct memory access.
doubleword (DWORD): The PCI (host) defines a doubleword as a 32-bit
value. See also word and halfword.
driver: See device driver.
DSP: See digital signal processor.
dual in-line package (DIP): A common rectangular chip housing with leads
(pins) on both long sides.
DWORD: See doubleword.
Glossary
E-5
Glossary
dynamic link library (DLL): A Windows software library that is linked dynamically at run time, rather than statically at compile time. DLLs can be
shared among multiple applications and be replaced with newer versions
without requiring the applications to be recompiled.
E
EEPROM: See electrically-erasable programmable read-only memory.
electret microphone: A condenser microphone that requires an external
power source.
electrically-erasable programmable read-only memory (EEPROM): A
nonvolatile memory device that can be programmed in-circuit and have
its contents selectively changed. Although its name includes read-only,
it supports both read and write accesses.
electrostatic discharge (ESD): Discharge of a static charge on a surface
or body through a conductive path to ground, which can be damaging to
integrated circuits.
EMIF: See external memory interface.
erasable programmable read-only memory (EPROM): A nonvolatile
memory device that can be erased with exposure to ultraviolet light. The
device can be randomly accessed, but it is read only.
ESD: See electrostatic discharge.
evaluation module (EVM): A board and software tools that allow the user
to evaluate a specific device.
expansion interface: An interface that allows additional capabilities to be
added to a base product.
external interrupt: A hardware interrupt triggered by a specific value on a
pin.
external memory interface (EMIF): The boundary between the CPU and
external memory through which information is conveyed.
E-6
Glossary
F
first in, first out (FIFO): A queue; a data structure or hardware buffer from
which items are taken out in the same order they were put in. A FIFO is
useful for buffering a stream of data between a sender and receiver that
are not synchronized; that is, the sender and receiver are not sending
and receiving at exactly the same rate. If the rates differ by too much in
one direction for too long, the FIFO becomes either full (blocking the
sender) or empty (blocking the receiver).
flag:
A binary status indicator whose state indicates whether a particular
condition has occurred or is in effect.
Flash memory: Nonvolatile read-only memory that is electronically erasable and programmable.
H
halfword: The ’C6x DSP defines a halfword as a16-bit data value. See also
doubleword and word.
handle:
An identifier used by software to reference a file or device.
high-level language (HLL): A general-purpose language that can be used
to program a microprocessor rather than using a low-level, machinedependent language.
host: A device to which other devices (peripherals) are connected and that
generally controls those devices.
host port interface (HPI): A 16-bit parallel interface that the host uses to
access the DSP’s memory space.
I
identifier (ID): A field that contains a resource-table index, a sequence number, and a resource-type code; it identifies a kernel resource such as a
port, semaphore, or task.
IEEE 1149.1 standard: “IEEE Standard Test Access Port and BoundaryScan Architecture”, first released in 1990. See also JTAG.
Industry Standard Architecture (ISA): An industry-standard 8/16-bit bus
used in IBM compatible desktops. It provides a theoretical maximum
data transfer rate of 8.33M bytes per second.
Glossary
E-7
Glossary
initiator: When a PCI bus master has arbitrated for and won access to the
PCI bus, it becomes the initiator of a transaction.
Institute of Electrical and Electronic Engineers (IEEE): A publishing and
standards-making body focused on advancing the theory and practice
of electrical, electronics, computer engineering, and computer science.
in-system programmable (ISP): The ability to program and reprogram a
device on a circuit board.
integrated switching regulator (ISR): A complete switch-mode power
supply in a modular, board-mounted package.
internal interrupt: A hardware interrupt caused by an on-chip peripheral.
interrupt: A signal sent by hardware or software to a processor requesting
attention. An interrupt tells the processor to suspend its current operation, save the current task status, and perform a particular set of instructions. Interrupts communicate with the operating system and prioritize
tasks to be performed.
interrupt service routine: A module of code that is executed in response
to a hardware or software interrupt.
ISP: See in-system programmable.
ISR: See integrated switching regulator.
J
Joint Test Action Group (JTAG): The Joint Test Action Group was formed
in 1985 to develop economical test methodologies for systems designed
around complex integrated circuits and assembled with surface-mount
technologies. The group drafted a standard that was subsequently
adopted by IEEE as IEEE Standard 1149.1-1990, “IEEE Standard Test
Access Port and Boundary-Scan Architecture”.
K
kilohertz (kHz): One thousand hertz, or cycles per second, used to indicate
the frequency of a clock signal.
E-8
Glossary
L
latch phase: The phase of a CPU cycle during which internal values are held
constant.
light emitting diode (LED): A semiconductor chip that gives off visible or
infrared light when activated.
linker: A software tool that combines object files to a form an object module,
which can be loaded into memory and executed.
little endian: An addressing protocol in which bytes are numbered from right
to left within a word. More significant bytes in a word have higher numbered addresses. Endian ordering is specific to hardware and is determined at reset. See also big endian.
load:
To enter data into storage or working registers.
loader: A device that places an executable module into system memory.
M
mA: See milliamp.
macro: A sequence of statements or instructions that is represented by a
symbolic symbol.
µF:
See microfarad.
µ-Law companding: See compress and expand (compand).
mailbox: A 32-bit register that provides a simple communication method to
pass messages between the host and DSP software. Multiple mailboxes
are typically available to support bidirectional, multiword message transfers.
maskable interrupt: An interrupt that can be enabled or disabled through
software.
master clock output signal (CLKOUT1): The output signal of the on-chip
clock generator. The CLKOUT1 high pulse signifies the CPU’s logic
phrase (when internal values are changed), while the CLKOUT1 low
pulse signifies the CPU’s latch phase (when the values are held
constant).
McBSP: See multichannel buffered serial port.
Glossary
E-9
Glossary
megahertz (MHz): One million hertz, or cycles per second, used to indicate
the frequency of a clock signal.
memory map: A graphical representation of a computer system’s memory,
showing the locations of program space, data space, reserved space,
and other memory-resident elements.
memory-mapped register: An on-chip register mapped to an address in
memory. Some memory-mapped registers are mapped to data memory,
and some are mapped to input/output memory.
MHz: See megahertz.
microfarad (µF):
tance.
One-millionth of a farad, which is the basic unit of capaci-
microsecond (µs):
One-millionth of a second.
milliamp (mA): One-thousandth of an ampere, which is the basic unit of current.
millimeter (mm):
One-thousandth of a meter.
million instructions per second (MIPS): A unit of instruction execution
speed of a computer.
millisecond (ms): One-thousandth of a second.
millivolts root mean square (mVrms): One-thousandth of a volt root mean
square. See also volts root mean square..
MIPS: See million instructions per second.
mm: See millimeter.
most significant byte (MSbyte): The byte in a multibyte word that has the
most influence on the value of a word.
motherboard: The main circuit board that contains the processor, main
memory, circuitry, bus controller, connectors, and primary components
of the computer. See also daughterboard.
µs: See microsecond.
ms: See millisecond.
MSbyte: See most significant byte.
multichannel buffered serial port (McBSP): A standard serial port interface found on ’C6x devices. It provides full-duplex communication,
double-buffered data registers, independent transmit and receive framing and clocking, direct interface to industry-standard serial devices, internal and external clock support, and an autobuffering capability using
a DMA controller.
E-10
Glossary
multiplexing: A process of transmitting more than one set of signals at a
time over a single wire or communications link. (Also known as muxing.)
mutex: A mutual exclusion semaphore used to restrict access to a resource.
mVrms: See millivolts root mean square.
N
nanosecond (ns): One-billionth of a second, the basic unit of time.
nonmaskable interrupt (NMI): An interrupt that uses the same logic as the
maskable interrupts, but can be neither masked nor disabled. It is often
used as a soft reset.
nonvolatile random access memory (NVRAM): A type of random access
memory that retains its data when its power source is turned off, providing nonvolatile storage.
O
object file: A file that has been assembled or linked and contains machine
language object code.
off chip: A device external to the device.
on chip: An element or module internal to the device.
P
parallel debug manager (PDM): A program used for creating and controlling multiple debuggers for the purpose of debugging code in a parallelprocessing environment.
PC: Personal computer.
PCI: See peripheral component interconnect.
PCM: See pulse code modulation.
PDM: See parallel debug manager.
peripheral component interconnect (PCI): A high-speed local bus that
supports data-transfer speeds of up to 132M bytes per second at
33 MHz.
Glossary
E-11
Glossary
phase-locked loop (PLL): A unit within a system that uses phase to lock on
to a signal to ensure synchronous clocking of digital signals.
pitch: The distance between successive centers of leads of a component
package.
plastic quad flat pack (PQFP): A low-profile, surface-mount integrated circuit package that is plastic and has leads (pins) on all four sides.
PLL: See phase-locked loop.
poll:
A continuous test used by the program until a desired condition is met.
PQFP: See plastic quad flat pack.
profiling environment: A special debugger environment that provides a
method for collecting execution statistics about specific areas in application code.
pulse code modulation (PCM): The most common method of encoding an
analog voice signal into digital data. Voice signals are encoded into 8-bit
data samples at an 8-kHz sample rate, resulting in a 64-kbps digital data
stream.
R
random-access memory (RAM): A memory element that can be written to
as well as read from.
read-only memory (ROM): A semiconductor storage element containing
permanent data that cannot be changed.
ready: A task state indicating that the task either is currently executing or is
able to execute as soon as it acquires the processor.
real time: The actual time during which the physical process of computation
transpires in order that results of the computation interact with a physical
process.
reduced instruction set computer (RISC): A computer whose instruction
set and related decode mechanism are much simpler than those of
microprogrammed complex instruction set computers. The result is a
higher instruction throughput and a faster real-time interrupt service response from a smaller, cost-effective chip.
register: A small area of high-speed memory, located within a processor or
electronic device, that is used for temporarily storing data or instructions.
Each register is given a name, contains a few bytes of information, and
is referenced by programs.
E-12
Glossary
reset: A means to bring processors to known states by setting registers and
control bits to predetermined values and signaling execution to start at
a specified address.
ring 0: Highest level of privilege available on an Intel processor that defines
what data can be accessed, what code in memory can be executed, and
what machine instructions can be executed by a program. Low-level device drivers run at ring 0. See also ring 3.
ring 3: Lowest level of privilege available on an Intel processor that defines
what data can be accessed, what code in memory can be executed, and
what machine instructions can be executed by a program. High-level
user-mode applications and DLL run at ring 3. See also ring 0.
RISC: See reduced instruction set computer.
ROM: See read-only memory.
S
sample rate: The rate at which the audio codec samples audio data. Usually
specified in hertz (samples per second).
SBSRAM: See synchronous burst static random-access memory.
SDRAM: See synchronous dynamic random-access memory.
slave: Another name for the target being addressed during a PCI transaction.
static random-access memory (SRAM): Fast memory that does not require refreshing, as DRAM does. It is more expensive than DRAM,
though, and is not available in as high a density as DRAM.
structure: A collection of one or more variables grouped together under a
single name.
surface-mount technology: A method of assembling printed wiring boards
where components are mounted onto the surface rather than through
holes.
synchronous burst static random-access memory (SBSRAM): Highperformance SRAM device with accesses that are synchronized to a microprocessor clock and includes a burst address counter.
synchronous dynamic random-access memory (SDRAM): Highperformance DRAM device with accesses that are synchronized to a
microprocessor clock and support for page bursts.
syntax: The grammatical and structural rules of a language. All higher-level
programming languages possess a formal syntax.
Glossary
E-13
Glossary
T
target: When related to PCI, it is the device that is the target of a PCI transaction initiated by a PCI bus master. When related to the debugger, the DSP
is the target of an emulation access.
target memory: Physical memory in a device into which executable object
code is loaded.
test bus controller (TBC): Application-specific integrated circuit that controls an IEEE 1149.1–1990 (JTAG) serial-test bus to support production
testing and in-system microprocessor emulation. The TBC provides control of the DSP and access to all of its registers and memory.
thin quad flat pack (TQFP): A very low-profile, surface-mount integrated
circuit package that is plastic and has leads (pins) on all four sides.
thread of execution: A schedulable unit of execution in a multitasking
system. The term refers specifically to the progressive execution of a
program element; it excludes other attributes, such as the system
resources allocated to a task or process.
timer: A programmable peripheral used to generate pulses or to time
events.
TQFP: See thin quad flat pack.
transistor-transistor logic (TTL): A family of logic devices that are made
with bipolar junction transistors and resistors. A TTL low level is defined
as a voltage level below 0.4 volts. A TTL high level is defined as a voltage
level above 2.4 volts.
V
V: See volt.
Vdc: See volts direct current.
VelociTI: Architecture developed by Texas Instruments that features very
long instruction words.
vendor ID: Every PCI device must have a vendor ID configuration register
that identifies the vendor of the device.
very long instruction word (VLIW): Architecture using words between the
sizes of 256 bits and 1024 bits.
E-14
Glossary
virtual device driver (VxD): A 32-bit, ring-0 module that virtualizes hardware for ring-3 modules to provide a primary interface to hardware or
specialized software services.
VLIW: See very long instruction word.
volt (V): The unit of voltage, or potential difference.
volts direct current (Vdc):
nal.
The voltage measurement of a direct current sig-
volts peak-to-peak (Vpp): A measurement of a signal that indicates the difference between its maximum and minimum voltage values.
volts root mean square (Vrms): A measurement of a periodic signal that
indicates the effective voltage at which a direct current voltage would deliver the same average power. This measurement provides a method for
comparing the power delivered by different waveforms.
VxD: See virtual device driver.
W
Win32: The 32-bit application programming interface for both Windows 95
and Windows NT.
word: A character or bit string considered as an entity. The length of the word
is machine-dependent. The ’C6x DSP defines a word as a 16-bit data value. The PCI (host) defines a word as a 16-bit data value. See also doubleword and halfword.
X
XDS510: A hardware emulator that provides a scan-path connection to a
DSP for source code debugging.
Glossary
E-15
Index
Index
A
ADC input gain macros 3-23
ADC input selector macros 3-24
ADC_INPUT_GAIN_STEP macro 3-23
add-on FIFO register port (AFIFO) 1-29
add-on general control/status register
(AGCSTS) 1-29
add-on incoming mailbox registers
(AIMB1–AIMB4) 1-29
add-on interrupt control register (AINT) 1-29
add-on mailbox empty/full status register (AMBEF) 1-29
add-on outgoing mailbox registers
(AOMB1–AOMB4) 1-29
ADPCM_4BIT_IMA macro 3-24
AFIFO register 1-29
AGCSTS register 1-29
AIMB1–AIMB4 registers 1-29
AINT register 1-29
ALAW_8BIT_COMPANDED macro 3-24
AMBEF register 1-29
AOMB1–AOMB4 registers 1-29
assign audio data format function 3-28
assistance from TI x
asynchronous expansion memory 1-14, 1-15
See also expansion memory
audio codec
See also codec
description 1-69 to 1-73
in detailed block diagram 1-3
registers
description 1-70 to 1-71
in MAP 0 memory map 1-14
in MAP 1 memory map 1-15
summary table 1-70
sample rates supported 1-70
audio interface 1-69 to 1-73
audio jacks
description 1-71
in detailed block diagram 1-3
audio op amps
in detailed block diagram 1-3
usage 1-71
AUX_LINE_GAIN_STEP macro 3-23
AUX1_SEL macro 3-24
auxiliary and line mixer gain macros 3-23
auxiliary port selection macros 3-22
B
base address registers (BARs) 1-24 to 1-25, E-2
big-endian mode, setting 2-40
blocking routines 3-2
board
closing driver connection to 2-10
initializing 3-44
opening driver connection to 2-32
reading data from 2-33
resetting 2-35
retrieving type and version information 2-8
setting user options 2-40
writing data to 2-44
board support library, API functions summary 3-40
boot modes
definition E-3
description 1-66
setting 2-36
BOTH macro 3-22
bus master control/status register (MCSR) 1-28
Index-1
Index
bus switch
description 1-8
in detailed block diagram 1-3
in EMIF data bus topology diagram
BUSY macro 3-4
1-9
C
calibrate codec function 3-30
calibration mode macros 3-25
Callback data type 3-5
capture and playback audio data format macros 3-24
CAPTURE macro 3-22
cautions
avoiding simultaneous NVRAM accesses 2-29,
2-31
information about v
CE memory space 1-12, 1-16
CHAN1 macro 3-22
CHAN2 macro 3-22
channel selection (left/right) macros 3-22
clear message event function 2-9
CLKOUT2 1-17
clock modes
definition E-3
description 1-66
setting 2-40
clock rates 1-66, 2-40
close a driver connection function 2-10
close HPI for a board function 2-16
close McBSP and release device handle function 3-12
CLOSED macro 3-4
CNTL register 1-51, 1-58
codec
See also audio codec
assigning audio data format 3-28
calibrating 3-30, 3-33
configuring 3-33
connecting to McBSP 3-42
controlling auxiliary inputs 3-29
controlling input ADCs 3-27
controlling internal timer 3-39
controlling line inputs 3-34
controlling output DACs 3-32
Index-2
definition E-4
disabling capture mode 3-30
disabling interrupt mode 3-34
disabling loopback mode 3-35
disabling playback mode 3-36
disabling serial port transfers 3-37
disconnecting from McBSP 3-42
enabling capture mode 3-31
enabling interrupt mode 3-34
enabling loopback mode 3-35
enabling playback mode 3-36
enabling serial port transfers 3-37
initializing 3-33
registers
I0–I32 1-71
R0–R3 1-70
resetting 3-36
returning ID 3-33
sample rate crystals 1-3
selecting as source for NMI 3-46
setting base address 3-38
setting defaults 3-33
setting sample rates 3-31
codec library
API functions summary 3-26
API macros 3-22 to 3-25
codec.h header file 3-2, 3-22
codec_adc_control function 3-27
codec_audio_data_format function 3-28
codec_aux_control function 3-29
codec_calibrate function 3-30
codec_capture_disable function 3-30
codec_capture_enable function 3-31
codec_change_sample_rate function 3-31
codec_dac_control function 3-32
codec_id function 3-33
codec_init function 3-33
codec_interrupt_disable function 3-34
codec_interrupt_enable function 3-34
codec_line_in_control function 3-34
codec_loopback_disable function 3-35
codec_loopback_enable function 3-35
codec_playback_disable function 3-36
codec_playback_enable function 3-36
codec_reset function 3-36
codec_serial_port_disable function 3-37
codec_serial_port_enable function 3-37
Index
codec_set_base function 3-38
codec_timer function 3-39
COFF
definition E-4
displaying information 2-11
loading image using HPI 2-12
common.h header file 3-4
configure McBSP function 3-13
connect codec to McBSP function 3-42
connectors, pinouts A-1 to A-9
continuously send buffer function 3-14
control auxiliary inputs function 3-29
control input ADCs function 3-27
control line inputs function 3-34
control output DACs function 3-32
conventions, notational iv to v
CONVERTER_CAL macro 3-25
CPLD
definition E-4
description C-2 to C-7
equations C-1 to C-82
pin definitions C-4 to C-7
CPLD ISP header, in detailed block diagram
CPLD registers 1-30, 1-50, 2-14
CPLDREV register 1-55
CPU
definition E-3
delaying a specified number of microseconds 3-41
delaying a specified number of milliseconds 3-41
description 1-4
cpu_freq function 3-41
D
DAC and loopback attenuation macros 3-23
DAC_CAL macro 3-25
DAC_LBACK_ATTEN_STEP macro 3-23
data transfers
setting time-out value 2-42
terminating 2-6, 2-7, 2-33, 2-44
data types
McBSP driver API 3-5 to 3-7
Win32 DLL API 2-3
1-3
daughterboard
definition E-4
description 1-21 to 1-22
envelopes and connections diagram 1-22
holding in reset 3-42
purpose 1-18
removing reset 3-43
debugger, definition E-5
delay CPU (microseconds) function 3-41
delay CPU (milliseconds) function 3-41
delay_msec function 3-41
delay_usec function 3-41
device pin notation iv
DIP, definition E-5
DIP switches
in detailed block diagram 1-3
using default settings 2-40
DIPBOOT register 1-54, 1-60
DIPOPT register 1-53, 1-59
direct memory access (DMA) E-5
disable capture mode function 3-30
disable interrupts from codec function 3-34
disable loopback mode function 3-35
disable McBSP function 3-18
disable NMI source externally function 3-45
disable playback mode function 3-36
disable selected LED function 3-44
disable serial port transfers on codec function 3-37
disconnect codec from McBSP function 3-42
display COFF information function 2-11
DMA E-5
documentation
about this manual iii
how to use this manual iii
related vi to vii
driver connection
closing 2-10
opening 2-32
DSP
architecture 1-4
CNTL register 1-58
control/status registers
description 1-56
in MAP 0 memory map 1-14
in MAP 1 memory map 1-15
summary table 1-57
Index-3
Index
core voltages 1-5
core, peripherals, and external interfaces diagram 1-5
CPU features 1-4
definition E-5
description 1-4 to 1-6
DIPBOOT register 1-60
DIPOPT register 1-59
DSPBOOT register 1-61
DSPOPT register 1-60
EMIF registers 1-16 to 1-17
FIFOSTAT register 1-61
in detailed block diagram 1-3
interrupt control 1-62 to 1-64
JTAG compatibility 1-5
key features 1-4
memory features 1-4
memory maps 1-13 to 1-15
peripherals features 1-4
procedure to load and start 2-36
releasing from halted state 2-43
resetting 2-36
retrieving message from 2-37
SDCNTL register 1-62
sending message to 2-39
STAT register 1-59
unresetting 2-43
DSP clocks
dual oscillator control 1-45 to 1-46
in detailed block diagram 1-3
selecting 1-7
summary table 1-7
supported rates 1-7
DSP support software
board support library 3-40 to 3-45
codec library 3-22 to 3-38
components 3-2
example program 3-47
McBSP driver 3-4 to 3-21
using the components 3-3
DSPBOOT register 1-55, 1-61
DSPOPT register 1-54, 1-60
DSP-to-host data transfer 2-33
E
EEPROM 1-24, 1-40, D-1 to D-2, E-6
electret microphones 1-69
EMI emissions, minimizing 1-16
Index-4
EMIF
address bus 1-8, 1-10
CE space control registers 1-16
data bus 1-8, 1-9
definition E-6
global control register 1-16
in detailed block diagram 1-3
initializing registers 2-28
initializing to clock rate-tailored values 3-43
initializing to default parameters 3-43
emulation 1-38 to 1-39
enable capture mode function 3-31
enable interrupts from codec function 3-34
enable loopback mode function 3-35
enable NMI source externally function 3-45
enable playback mode function 3-36
enable selected LED function 3-45
enable serial port transfers on codec function 3-37
endian modes
description 1-66
setting 2-40
evaluation module (EVM)
connector pinouts A-1 to A-9
CPLD equations C-1 to C-82
definition E-6
description iii
schematics B-1 to B-42
evm_codec_disable function 3-42
evm_codec_enable function 3-42
evm_db_reset function 3-42
evm_db_unreset function 3-43
evm_default_emif_init function 3-43
evm_emif_init function 3-43
evm_init function 3-44
evm_led_disable function 3-44
evm_led_enable function 3-45
evm_nmi_disable function 3-45
evm_nmi_enable function 3-45
evm_nmi_sel function 3-46
evm6x.sys driver 2-2
evm6x.vxd driver 2-2
evm6x_abort_read function 2-6
evm6x_abort_write function 2-7
evm6x_board_type function 2-8
evm6x_clear_message_event function 2-9
evm6x_close function 2-10
Index
evm6x_coff_display function 2-11
evm6x_coff_load function 2-12
evm6x_cpld_read_all function 2-14
evm6x_generate_nmi_int function 2-15
evm6x_hpi_close function 2-16
evm6x_hpi_fill function 2-17
evm6x_hpi_generate_int function 2-19
evm6x_hpi_open function 2-20
evm6x_hpi_read function 2-21
evm6x_hpi_read_single function 2-23
evm6x_hpi_write function 2-25
evm6x_hpi_write_single function 2-26
evm6x_init_emif function 2-28
evm6x_nvram_read function 2-29
evm6x_nvram_write function 2-31
evm6x_open function 2-32
evm6x_read function 2-33
evm6x_reset_board function 2-35
evm6x_reset_dsp function 2-36
evm6x_retrieve_message function 2-37
evm6x_send_message function 2-39
evm6x_set_board_config function 2-40
evm6x_set_timeout function 2-42
evm6x_unreset_dsp function 2-43
evm6x_write function 2-44
EVM6XDLL_BOARD_TYPE data type 2-3
EVM6XDLL_BOOT_MODE data type 2-3
EVM6XDLL_CLOCK_MODE data type 2-4
EVM6XDLL_ENDIAN_MODE data type 2-4
EVM6XDLL_MESSAGE data type 2-4
expansion interfaces 1-18 to 1-22, E-6
expansion memory
CE memory space 1-12, 1-16
description 1-12 to 1-13
interface 1-18 to 1-19
transceivers 1-12
expansion peripheral interface
description 1-19 to 1-20
in detailed block diagram 1-3
external memory
CE memory space initialization 1-16
description 1-8 to 1-17
DSP EMIF registers 1-16 to 1-17
expansion memory 1-12 to 1-13
memory maps 1-13 to 1-15
SBSRAM 1-10 to 1-11
SDRAM 1-11 to 1-12
external power connector
description 1-75 to 1-76
drawing 1-76
in detailed block diagram 1-3
externally disable NMA function 3-45
externally enable NMA function 3-45
extinguish selected LED function 3-44
F
fan (DSP)
description 1-6, 1-76
power connector 1-3, 1-76
FIFO register 1-14, 1-15, 1-28
FIFOSTAT register 1-61
fill DSP memory using HPI function
flag, definition E-7
Flash memory 1-13, E-7
FULL_CAL macro 3-25
2-17
G
generate interrupt to DSP using HPI function
generate NMI to DSP function 2-15
2-19
H
hardware
detailed block diagram 1-3
theory of operation 1-1 to 1-80
hold daughterboard in reset function 3-42
host support software
components 2-2
example program 2-46
low-level Windows drivers 2-2
Win32 DLL API
data types 2-3
example program 2-46
functions summary 2-5
host-to-DSP data transfer 2-44
HPI
closing for a board 2-16
definition E-7
opening for a board 2-20
selecting as source for NMI 3-46
Index-5
Index
using to fill DSP memory 2-17
using to generate interrupt to DSP 2-19
using to load a COFF image 2-12
using to read DSP memory 2-21, 2-23
using to write to DSP memory 2-25, 2-26
HPI address register (HPIA)
HPI registers (BAR3)
LED, definition E-9
LEDs
disabling 3-44
enabling 3-45
in detailed block diagram 1-3
LEFT macro 3-22
LINE_OUT_LBACK_SEL macro 3-24
LINE_SEL macro 3-24
LINEAR_16BIT_SIGNED_BE macro 3-24
LINEAR_16BIT_SIGNED_LE macro 3-24
LINEAR_8BIT_UNSIGNED macro 3-24
little-endian mode, setting 2-40
load COFF image using HPI function 2-12
low-level Windows drivers 2-2
1-31
HPI control register (HPIC)
HPI data register (HPID)
L
1-31
1-31
1-31
I
I0–I32 registers
1-71
IEEE 1149.1 standard
E-7
illuminate selected LED function
3-45
incoming mailbox registers (IMB1–IMB4)
index address register (R0)
indexed data register (R1)
1-28
1-70
1-70
initialize EMIF for EVM board function
initialize EMIF registers function
3-43
2-28
initialize EMIF to default parameters function
initialize EVM board function
3-44
initialize McBSP driver function
INTCSR register
3-16
1-28
integrated switching regulator (ISR)
interface connector
internal data memory
internal peripherals
1-74, E-8
1-12
1-14, 1-15
1-14, 1-15
internal program memory
interrupt control
1-14, 1-15
1-62 to 1-64
interrupt control/status register (INTCSR)
J
JTAG
definition E-8
emulation 1-66
header 1-3
K
key features, TMS320C6201 DSP
Index-6
3-43
1-4
1-28
M
macros
codec library API 3-22
definition E-9
McBSP driver API 3-4
mailbox empty/full status register (MBEF) 1-28
master read address register (MRAR) 1-28
master read transfer count register (MRTC) 1-28
master write address register (MWAR) 1-28
master write transfer count register (MWTC) 1-28
MAX_ADC_INPUT_GAIN macro 3-23
MAX_AUX_LINE_GAIN macro 3-23
MBEF register 1-28
McBSP
definition E-10
in detailed block diagram 1-3
McBSP callback function data type 3-5
McBSP configuration structure (Mcbsp_config) data
type 3-5
McBSP device handle (Mcbsp_dev) data type 3-5
McBSP driver
API data types 3-5 to 3-7
API functions summary 3-8
API macros 3-4
asynchronous routines
description 3-2
mcbsp_async_receive function 3-9
mcbsp_async_send function 3-11
synchronous routines
description 3-2
Index
mcbsp_sync_receive function 3-19
mcbsp_sync_send function 3-20
McBSP receiver configuration structure
(Mcbsp_rx_config) data type 3-7
McBSP sample rate generator configuration structure (Mcbsp_srg_config) data type 3-7
McBSP state macros 3-4
McBSP transmitter configuration structure
(Mcbsp_tx_config) data type 3-6
mcbsp.h header file 3-4
mcbsp_async_receive function 3-9
mcbsp_async_send 3-11
mcbsp_close function 3-12
Mcbsp_config data type 3-5
mcbsp_config function 3-13
mcbsp_cont_async_send function 3-14
Mcbsp_dev data type 3-5
mcbsp_drv_init function 3-16
mcbsp_open function 3-17
mcbsp_reset function 3-18
Mcbsp_rx_config data type 3-7
Mcbsp_srg_config data type 3-7
mcbsp_stop function 3-18
mcbsp_sync_receive function 3-19
mcbsp_sync_send function 3-20
Mcbsp_tx_config data type 3-6
McBSP0
selection 1-73
signals 1-19
McBSP1 1-3, 1-19
MCSR register 1-28
memory decoding 1-65
memory maps
definition E-10
MAP 0 1-14
MAP 1 1-15
message event, clearing 2-9
MIC_SEL macro 3-24
microphone input 1-71
MIN_ADC_INPUT_GAIN macro 3-23
MIN_AUX_LINE_GAIN macro 3-23
MIN_DAC_LBACK_ATTEN macro 3-23
mode selection macros 3-22
MRAR register 1-28
MRTC register 1-28
multiplexers 1-72
MUTEX 2-20
MWAR register 1-28
MWTC register 1-28
N
NMI
definition E-11
externally disabling 3-45
externally enabling 3-45
generating to DSP 2-15
selecting source for 3-46
NO_CAL macro 3-25
nonvolatile memory 1-13
notational conventions iv to v
NVRAM
definition E-11
reading byte of 2-29
writing byte of 2-31
O
obtaining technical support ix
OMB1–OMB4 registers 1-28
op amps
description 1-71
in detailed block diagram 1-3
open driver connection function 2-32
open HPI for a board function 2-20
OPEN macro 3-4
open McBSP/obtain device handle function 3-17
oscillators 1-3, 1-7, 1-45 to 1-46
outgoing mailbox registers (OMB1–OMB4) 1-28
P
PCI
bus mastering support 1-33
CNTL register 1-51
CPLD control/status registers
CPLDREV register 1-55
definition E-11
DIPBOOT register 1-54
DIPOPT register 1-53
DSPBOOT register 1-55
DSPOPT register 1-54
1-49 to 1-55
Index-7
Index
FIFO 1-14, 1-15
interrupt control 1-62 to 1-64
slave support 1-30
STAT register 1-52
SWBOOT register 1-53
SWOPT register 1-52
PCI add-on bus, operation registers
AFIFO 1-29
AGCSTS 1-29
AIMB1–AIMB4 1-29
AINT 1-29
AMBEF 1-29
AOMB1–AOMB4 1-29
description 1-29 to 1-30
in MAP 0 memory map 1-14
in MAP 1 memory map 1-15
summary table 1-29
PCI bus
description 1-23
in detailed block diagram 1-3
PCI controller
base address registers (BARs) 1-24
description 1-24
interfaces 1-25
operation registers
FIFO 1-28
IMB1–IMB4 1-28
INTCSR 1-28
MBEF 1-28
MCSR 1-28
MRAR 1-28
MRTC 1-28
MWAR 1-28
MWTC 1-28
OMB1–OMB4 1-28
summary table 1-28
PCI interface
description 1-23
implementation 1-24 to 1-27
in detailed block diagram 1-3
plug-and-play feature 1-23
perform codec initialization and default configuration
function 3-33
pin notation iv
pinouts, connector
CPLD ISP header A-4
DSP fan power A-8
expansion memory interface A-6
expansion peripheral interface A-7
external power A-8
Index-8
JTAG emulation header A-5
PCI local bus A-9
stereo line input jack A-3
stereo line output jack A-3
stereo microphone input jack A-2
summary A-2
PIO data register (R3) 1-70
PLAYBACK macro 3-22
plug-and-play feature 1-23
power management 1-44 to 1-45, 1-77
power sequence control 1-3
power supplies 1-74 to 1-76
programmable logic
description 1-40 to 1-41
in detailed block diagram 1-3
R
R0–R3 registers 1-70
read byte of NVRAM function 2-29
read data from board function 2-33
read DSP memory using HPI function 2-21
read operation, terminating 2-6
read single byte using HPI function 2-23
receive buffer on McBSP asynchronously function 3-9
receive buffer on McBSP synchronously function 3-19
remove daughterboard reset function 3-43
requester arbitration mode 1-16
reset board function 2-35
reset codec function 3-36
reset control 1-42 to 1-44, 1-77
reset DSP function 2-36
reset McBSP function 3-18
reset pushbutton 1-77
retrieve board type and version function 2-8
retrieve message from DSP function 2-37
return codec ID function 3-33
return contents of CPLD registers function 2-14
return current CPU frequency function 3-41
RIGHT macro 3-22
ring 0 E-13
ring 3 E-13
RSVD_FORMAT macro 3-24
Index
S
sample rate crystals, codec 1-3
SBSRAM
definition E-13
description 1-10 to 1-11
in detailed block diagram 1-3
in MAP 0 memory map 1-14
in MAP 1 memory map 1-15
power management 1-11
selecting clock speed 1-10 to 1-11
schematics B-1 to B-42
SDCNTL register 1-62
SDRAM
control register 1-17
definition E-13
description 1-11
disabling 1-12
enabling 1-12
in detailed block diagram 1-3
in MAP 0 memory map 1-14
in MAP 1 memory map 1-15
power management 1-12
refreshing 1-11
selecting refresh period 1-17
timing register 1-17
select source for NMI function 3-46
send buffer on McBSP asynchronously function 3-11
send buffer on McBSP continuously function 3-14
send buffer on McBSP synchronously function 3-20
send message to DSP function 2-39
serial data format macros 3-25
SERIAL_32BIT macro 3-25
SERIAL_64BIT macro 3-25
SERIAL_64BIT_ENHANCED macro 3-25
set base codec address function 3-38
set capture and playback rates function 3-31
set transfer time-out value function 2-42
set user board options functions 2-40
setting the boot mode 2-36
signal levels, stereo audio interface 1-72
STAT register 1-52, 1-59
status register (R2) 1-70
stereo audio interface. See audio interface
stop McBSP operation function
support from TI ix, x
SWBOOT register 1-53
SWOPT register 1-52
3-18
T
technical support ix, x
terminate pending read transfer function 2-6
terminate pending write transfer function 2-7
test bus controller
definition E-14
description 1-30, 1-38
in detailed block diagram 1-3
timer
audio codec 1-72
definition E-14
delaying CPU with 3-41
timing fields, EMIF SDRAM control register 1-17
transceivers 1-65
transferring data
from DSP to host 2-33
from host to DSP 2-44
setting time-out value 2-42
TTL, definition E-14
U
ULAW_8BIT_COMPANDED macro 3-24
unreset DSP function 2-43
use internal codec timer function 3-39
user options
control 1-66
dual-use option support diagram 1-68
in detailed block diagram 1-3
summary table 1-66
user defined 1-67
V
VelociTI 1-4, E-14
very long instruction word (VLIW) 1-4, E-14
voltage regulators
description 1-74 to 1-75
in detailed block diagram 1-3
voltage supervisor
description 1-77
in detailed block diagram 1-3
Index-9
Index
W
warnings, information about
Win32 DLL API
data types 2-3
functions summary 2-5
Index-10
v
Windows drivers 2-2
write a byte of NVRAM function 2-31
write data to board function 2-44
write operation, terminating 2-7
write single byte using HPI function 2-26
write to DSP memory using HPI function 2-25