A 1.8V 89.2dB dynamic range delta-sigma modulator - J

LETTER
IEICE Electronics Express, Vol.14, No.21, 1–9
A 1.8 V 89.2 dB dynamic range
delta-sigma modulator using
an op-amp dynamic current
biasing technique
Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, and Gil-Cho Ahna)
Department of Electronic Engineering, Sogang University,
35 Baekbeom-ro, Mapo-gu, Seoul 04107, Korea
a) gcahn@sogang.ac.kr
Abstract: A third-order single-bit delta-sigma modulator is presented in
this paper. An op-amp dynamic current biasing technique is used to improve
the power-efficiency of the modulator. The voltage reference block is
integrated with the delta-sigma modulator core to avoid the use of large
off-chip bypass capacitors and to minimize pin numbers. It achieves 89.2 dB
dynamic range over 10 kHz signal bandwidth with an oversampling ratio of
128. The delta-sigma modulator core and on-chip voltage reference block
consume 880 µW and 550 µW, respectively, from a 1.8 V power supply. The
prototype chip occupies 1.26 mm2 using a 0.18 µm CMOS technology.
Keywords: delta-sigma modulator, analog-to-digital converter, op-amp
dynamic current biasing, on-chip reference voltage
Classification: Integrated circuits
References
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
[1] G.-M. Sung, et al.: “A third-order multibit switched-current delta-sigma
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[3] H. Li, et al.: “Novel single-loop multi-bit sigma-delta modulator using OTA
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[5] D. Kanemoto, et al.: “A high dynamic range and low power consumption audio
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[7] Y.-S. Kwak, et al.: “A 1.8 V 89.2 dB delta-sigma ADC for sensor interface with
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IEICE Electronics Express, Vol.14, No.21, 1–9
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© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
6272080).
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audio ADC,” IEEE J. Solid-State Circuits 43 (2008) 1195 (DOI: 10.1109/JSSC.
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(2015) 525 (DOI: 10.1109/JETCAS.2015.2502162).
Introduction
The increasing demands of high precision sensor interface for portable devices
require the development of power efficient analogue-to-digital converters (ADCs).
Among many ADC architectures, the delta-sigma modulators have been the most
suitable candidate for the high precision applications by using the oversampling
and noise-shaping properties [1, 2]. The effective way to improve the power
efficiency of the delta-sigma modulator is to reduce the power consumption of
the op-amp in the integrator since it typically consumes most of the power in the
delta-sigma modulator. A variety of power saving techniques such as the op-amp
sharing [3, 4, 5] and dynamic biasing [6] have been proposed. The op-amp sharing
technique reduces the power consumption of the modulator by sharing the op-amps
between the integrators. However, it introduces signal dependent errors due to
using extra switches at the integrating capacitors, which might degrade the linearity
of the modulator compared to using conventional switched-capacitor integrators.
This paper presents a 1.8 V 89.2 dB dynamic range (DR) third-order single-bit
delta-sigma modulator using an op-amp dynamic current biasing technique [7].
The proposed technique effectively saves the power consumption of the deltasigma modulator by dynamically optimizing the op-amp bias current. It improves
the power efficiency of the modulator while maintaining the advantages of using
conventional switched-capacitor integrators. The on-chip voltage reference block is
integrated with the delta-sigma modulator core to avoid the use of large off-chip
bypass capacitors and to minimize pin numbers.
The organization of this paper is as follows. In Section 2, the modulator
architecture is described. Next, Section 3 introduces the proposed op-amp dynamic
current biasing technique. The circuit implementation of the proposed delta-sigma
modulator is explained in Section 4 and the measurement results are presented in
Section 5. The conclusion of this paper is given in Section 6.
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IEICE Electronics Express, Vol.14, No.21, 1–9
2
Modulator architecture and circuit implementation
The z-domain block diagram of the proposed delta-sigma modulator is depicted in
Fig. 1 [8]. A single-loop and single-bit architecture is employed to achieve the
high-resolution without imposing severe matching requirements for the circuitry
[9]. A third-order noise-shaping is used for the target DR with an oversampling
ratio (OSR) of 128. Half-period delay integrators are employed to apply the
proposed op-amp dynamic current biasing technique and it will be discussed in
the following section. The transfer function of the delta-sigma modulator is given
by
YðzÞ ¼ UðzÞ z3=2
ð1 z1 Þ3
þ QðzÞ DðzÞ
DðzÞ
ð1Þ
where DðzÞ is 1 23 z1 þ 38 z2 15 z3 .
Behavioral model simulations using MATLAB are performed to determine the
gain coefficient of each integrator and to specify the op-amp DC gain requirement
[10]. The gain coefficients of each integrator are set to ½1=5; 1=4; 1=2 considering
the output swing. Fig. 2 shows the behavioral simulation results of each integrator
output histogram with a −6 dBFS input amplitude. The signal-to-quantization noise
(SQNR) versus op-amp DC gain is depicted in Fig. 3. It shows that 50 dB DC gain
is sufficient to prevent the SQNR degradation resulting from the leakage in the
integrators.
Fig. 1. Z-domain block diagram of the modulator.
Fig. 2.
3
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
Output histogram of each integrator.
Proposed op-amp dynamic current biasing technique
The schematic diagram of the first integrator is illustrated in Fig. 4. In the halfperiod delayed integrators, the required op-amp bandwidth (BW) during the
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IEICE Electronics Express, Vol.14, No.21, 1–9
Fig. 3.
Fig. 4.
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
SQNR versus op-amp DC gain.
Schematic diagram of the first integrator
integrating phase (2 ) is much higher than that of the holding phase (1 ). This is
because the op-amp output needs to be settled within the required range during the
integrating phase while the op-amp is only used to hold the charge in the feedback
capacitor during the holding phase. Therefore, in the conventional integrator using
the class-A op-amp, the bias current of the op-amp is determined by the settling
requirement during the integrating phase. However, it results in unnecessarily high
BW of the op-amp during the holding phase.
The op-amp dynamic current biasing technique is proposed in this paper. It
saves the power consumption of the half-period integrator by dynamically optimizing the bias current of the op-amp. Fig. 5 shows the schematic of the op-amp using
the proposed technique, which is based on the fully-differential folded-cascode
op-amp. The detailed operation is as follows. During the integrating phase,
switches XS1S5 are turned on. Total bias current of the op-amp during this phase
is determined to meet the integrator settling requirement. Then, during the holding
phase, switches XS1S5 are turned off and the bias current is reduced as much as
50%. Hence, the average power consumption of the op-amp is decreased by
approximately 25% compared to the conventional class-A op-amp that uses the
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IEICE Electronics Express, Vol.14, No.21, 1–9
Fig. 5.
Schematic diagram of the op-amp using the proposed dynamic
current biasing technique
constant bias current. Switches XA1A5 in Fig. 5 are turned on during all phases to
enhance the matching property of the bias currents. The voltage drops due to the on
resistance of all switches used for the proposed technique are negligibly small. The
dynamic common-mode feedback (CMFB) circuit is adopted to adjust the output
common-mode level of the fully-differential op-amp.
The simulated performance parameters of the op-amp used in the first integrator
are given in Table I. The current consumption during the integrating and holding
phase are 280 µA and 140 µA, respectively. Therefore, the average current consumption of the op-amp becomes 210 µA. The simulated closed-loop BW of the
op-amp is about 11 MHz during both integrating and holding phase in the typical
corner. Due to the decreased load capacitance and increased feedback factor during
the holding phase, the closed-loop BW of the op-amp is maintained during both
phases although its bias current is reduced during the holding phase. The op-amps
in the second and third integrator employ the same structure, while the bias currents
during both phases are scaled down according to the BW requirement.
Table I.
Simulated performance parameters of the op-amp used in the
first integrator
Operating Phase
Holding
Integrating
Bias current [uA]
140
280
Closed-loop BW [MHz]
10.85
11.15
Phase margin [degree]
84.71
86.69
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
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IEICE Electronics Express, Vol.14, No.21, 1–9
4
Circuit implementation
Fig. 6 shows the circuit implementation of the proposed delta-sigma modulator and
its timing diagram. It consists of three half-period delayed integrators, a single-bit
quantizer (a latched-comparator), a voltage reference block and a non-overlapped
clock generator. All integrators use same structure while the sampling capacitance
of the subsequent integrators are scaled, because the kT=C noise constraints
become less stringent. Table II shows the sampling capacitance of each integrator.
The master clock signal is provided externally and the other clock phases are
derived from the internal clock generator.
The voltage reference block is integrated with the delta-sigma modulator core
and Fig. 7 shows its simplified schematic diagram. The reference voltages are
generated by using the output of the bandgap reference circuit [11]. Then, these
voltages are buffered to drive the load capacitors in the modulator core. The
Schematic of the proposed delta-sigma modulator
Fig. 6.
Table II.
Sampling capacitance of each integrator
st
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
1 integrator
2nd integrator
3rd integrator
2 pF
0.5 pF
0.1 pF
Fig. 7.
On-chip voltage reference block
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op-amps in the voltage reference block employs two-stage architecture, which
consists of a telescopic and a common-source amplifier.
5
Measurement results
A prototype delta-sigma modulator was fabricated in a 0.18 µm CMOS process and
Fig. 8 shows its die photograph and layout. The prototype chip occupies 1.26 mm2
including the on-chip voltage reference circuit. The measured output spectrum with
a −4.7 dBFS 500 Hz sinusoidal input signal is shown in Fig. 9. The prototype
achieves 77.1 dB peak SNR and 77.0 dB peak SNDR. The measured output
spectrum with shorted input signal is shown in Fig. 10 and it achieves a DR of
89.2 dB. The measured SNR and SNDR versus input amplitude curve is illustrated
in Fig. 11. The power consumptions of the delta-sigma modulator core and on-chip
reference voltage block are 880 µW and 550 µW, respectively, from a 1.8 V power
supply. Table III summarizes the performance of the prototype chip and compares it
with delta-sigma modulators that use the on-chip reference voltages.
Fig. 8.
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
Fig. 9.
Die photograph and layout
Measured output spectrum with a −4.7 dBFS 500 Hz sinusoidal
input
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IEICE Electronics Express, Vol.14, No.21, 1–9
Fig. 10. Measured output spectrum with shorted input
Fig. 11. SNR and SNDR versus input signal
Table III.
This Work
[12]
[13]
[14]
Process [µm]
0.18
0.18
0.5
0.13
Fs [MHz]
2.56
2.56
1.404
26
OSR
128
64
64
130
BW [kHz]
10
20
11
100
DR [dB]
89.2
70.8
80.0
81.0
Supply voltage [V]
1.8
1.6
1.8
1.2
Total power [mW]
1.42
1.0
1.7
3.4
157.7
143.8
148.1
162.4
6
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
Summary of measured performance
FOMDR [dB]
FOM ½dB ¼ DR þ 10 log (BW/power)
Conclusion
A third-order single-loop single-bit delta-sigma modulator is presented in this
paper. The op-amp dynamic current biasing technique is employed to improve
the power efficiency of the modulator. The bandgap reference with the voltage
buffers are integrated to drive the modulator without using large off-chip bypass
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IEICE Electronics Express, Vol.14, No.21, 1–9
capacitors. The prototype chip was fabricated in a 0.18 µm CMOS process to prove
the validity of the proposed architecture.
Acknowledgments
This research was supported by the MSIP (Ministry of Science, ICT and Future
Planning), Korea, under the ITRC (Information Technology Research Center)
support program (IITP-2017-2012-0-00603) supervised by the IITP (Institute for
Information & communications Technology Promotion).
© IEICE 2017
DOI: 10.1587/elex.14.20171007
Received October 1, 2017
Accepted October 13, 2017
Publicized October 27, 2017
Copyedited November 10, 2017
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