Freescale Title of Presentation Second Line Optional

Freescale Title of Presentation Second Line Optional
Multicore T Family for
Networking, Industrial, Avionics
and Military Applications
EUF-NET-T0586
Gino Gatto | Sr. Field Application Engineer
JUNE.2014
TM
External Use
Agenda
•
QorIQ T Family Roadmap
• QorIQ T1 Family Block Diagram
−
QorIQ T1040 L2 Switch
−
QorIQ T1040 Quicc Engine
•
QorIQ T2 Family Block Diagram
• QorIQ T4 Family Block Diagram
•
−
E6500 Core Enhancement
−
MEPL Library of AltiVec Functions
Migration Between T2081 and T1040
−
Hardware Compatibility
−
Software Compatibility
−
Supporting Tools
−
Reference Documentation
TM
External Use
1
QorIQ T1 Family Block Diagram
TM
External Use
4
QorIQ T1040 Processor
Power Architecture®
e5500
256 KB
Backside
L2 Cache
32 KB
32 KB
D-Cache
I-Cache
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory Controller
Controller
Memory
Security Fuse Processor
CoreNet™ Coherency Fabric
Security Monitor
PAMU
IFC
DIU
1G 1G 1G 1G
SATA 2.0
8 Port
Switch
SATA 2.0
Buffer
Mgr.
TDM/HDLC
TDM/HDLC
2x USB 2.0 w/PHY
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
PCIe
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
PCIe
2x DUART
5.0
(XoR,
CRC)
Queue
Mgr.
PCIe
eSDHC
Security
PCIe
Power Management
Peripheral
Access Mgmt Unit
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
1G 1G 1G 1G
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Enable Convection cooled
system design
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
5
Processor
• 4x e5500, 64b, up to 1.4GHz
• Each with 256KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4x PCIe Gen2 (5Gbps) Controllers
• 2x SATA 2.0, 3Gbps
• 2x USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• Up to 4x 10/100/1000 Ethernet Controllers
• 8-Port Gigabit Ethernet Switch
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation quad-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1020 Processor
2 CORES
Power Architecture®
e5500
256 KB
Backside
L2 Cache
32 KB
32 KB
D-Cache
I-Cache
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory Controller
Controller
Memory
Security Fuse Processor
CoreNet™ Coherency Fabric
Security Monitor
PAMU
IFC
DIU
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
TDM/HDLC
TDM/HDLC
2x USB 2.0 w/PHY
Pattern
Match
Engine
2.0
SATA 2.0
SPI, GPIO
1G 1G 1G 1G
SATA 2.0
2x I2C
2xDMA
PCIe
Queue
Mgr.
PCIe
2x DUART
5.0
(XoR,
CRC)
QUICC
Engine
Parse, Classify,
Distribute
PCIe
eSDHC
Security
PCIe
Power Management
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
1G 1G 1G 1G
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Enable Convection cooled
system design
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
6
Processor
• 2x e5500, 64b, up to 1.4GHz
• Each with 256KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gbps
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• Up to 4x 10/100/1000 Ethernet Controllers
• 8-Port Gigabit Ethernet Switch
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation dual-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1042 Processor
Power Architecture®
e5500
256 KB
Backside
L2
Cache
32 KB
D-Cache
32 KB
I-Cache
Security Fuse
Processor
Security Monitor
CoreNet™ Coherency Fabric
PAMU
2x USB 2.0 w/PHY
DIU
1G 1G 1G
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
SATA 2.0
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
SATA 2.0
2.5G
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
Queue
Mgr. 2.5G
PCIe
PCIe
5.0
(XoR,
CRC)
PCIe
2x DUART
Security
PCIe
eSDHC
TDM/HDLC
TDM/HDLC
IFC
Power Management
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Target Deep Sleep 150mW
on special Part Numbers
(1/2W AC System)
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
7
Processor
• 4x e5500, 64b, up to 1.4GHz
• Each with 256 KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory Subsystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gbps
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• 5x 10/100/1000 Ethernet Controllers
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation quad-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
QorIQ T1022 Processor
2 CORES
Power Architecture®
e5500
256 KB
Backside
L2
Cache
32 KB
D-Cache
32 KB
I-Cache
Security Fuse
Processor
Security Monitor
CoreNet™ Coherency Fabric
PAMU
2x USB 2.0 w/PHY
DIU
1G 1G 1G
8 Port
Switch
Buffer
Mgr. 1G 1G 1G 1G
SATA 2.0
Pattern
Match
Engine
2.0
2xDMA
1G 1G 1G 1G
SATA 2.0
2.5G
2x I2C
SPI, GPIO
QUICC
Engine
Parse, Classify,
Distribute
Queue
Mgr. 2.5G
PCIe
PCIe
5.0
(XoR,
CRC)
PCIe
2x DUART
Security
PCIe
eSDHC
TDM/HDLC
TDM/HDLC
IFC
Power Management
256KB
Platform Cache
32/64-bit
64-bit
DDR3L/4
DDR2/3
Memory
Memory
Controller
Controller
Real Time
Debug
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
8-Lane 5GHz SERDES
Device
• 780-pin FC-PBGA package
• 23x23mm, 0.8mm pitch
Power targets
• Target Deep Sleep 150mW
on special Part Numbers
(1/2W AC System)
Datapath Acceleration
• SEC- crypto acceleration
• PME- Reg-ex Pattern Matcher
TM
External Use
8
Processor
• 2x e5500, 64b, up to 1.4GHz
• Each with 256 KB backside L2 cache
• 256KB Shared Platform Cache w/ECC
• Supports up to 64GB addressability (36 bit
physical addressing)
Memory SubSystem
• 32/64b DDR3L/4 Controller up to 1600MHz
CoreNet Switch Fabric
High Speed Serial IO
• 4 PCIe Gen2 Controllers
• SATA 2.0, 3Gb/s
• 2 USB 2.0 with PHY
Network IO
• FMan packet Parse/Classify/Distribute
• Lossless Flow Control, IEEE 1588
• 5x 10/100/1000 Ethernet Controllers
• QUICC Engine
• HDLC, 2x TDM
Green Energy Operation
• Fanless operation dual-core 1.4GHz
• Packet lossless deepsleep
• Programmable wake-on-packet
• Wake-on-timer/GPIO/USB/IRQ
Performance
QorIQ T Series: One of the Industry’s Most Scalable, PinCompatible Communications Processor Family
- Eight Virtual Cores up to 1.8GHz
T2081
- Quad-Core up to 1.4GHz
- Integrated GbE Switch
T1040
- Quad-Core up to 1.4GHz
T1042
- Dual-Core up to 1.4GHz
- Integrated GbE Switch
T1020
- Dual-Core up to 1.4GHz
Scale from dual, quad to
eight virtual cores with
QorIQ T1/T2 devices
T1022
Power
TM
External Use
9
Personality Comparison Chart
CPU
L2 Cache
Platform Cache
DDR I/F
Type/Width
10/100/1000
Ethernet (with
IEEE1588v2)
P1020,
P1011,
P1021,
P1012
P1022,
P1013
T1020
T1022
T1040
T1042
T2081
1 to 2 x e500
1 to 2 x
e500
2 x e5500
2 x e5500
4 x e5500
4 x e5500
4 x e6500/8
threads
Up to 800MHz
Up to
1200MHz
12001400MHz
1200-1400MHz
1500 1800MHz
32K I/D
32K I/D
32K I/D
32K I/D
32K I/D
32K I/D
32K I/D
256KB
256KB
256KB/Core
256KB/Core
256KB/Core
256KB/Core
2MB shared
DDR2/3
DDR2/3
256KB
DDR3L/4
256KB
DDR3L/4
256KB
DDR3L/4
256KB
DDR3L/4
512KB
DDR3/3L
16/32-bit ,
800MHz
32/64-bit,
800MHz
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
1600MT/s
32/64-bit,
2133MT/s
2x 2.5
+
5 x 10/100/1000
4x
10/100/1000
2x 2.5
+
5 x 10/100/1000
2x 2.5/10G
+
6x 1G
No
8-Port GE
Switch
No
No
Yes
Yes
Yes
No
3x
2x
4x
10/100/1000 10/100/1000 10/100/1000
Ethernet Switch
--
--
Yes
Yes
In P1021/12
No
SERDES
4 lanes
6 lanes
PCI-Exp
2 (Gen-1)
3 (Gen-1)
TDM
QUICC Engine
Package
8-Port GE
Switch
Yes
TDM and
HDLC
1200-1400MHz 1200-1400MHz
TDM and HDLC TDM and HDLC TDM and HDLC
8 lanes(5GHz) 8 lanes(5GHz)
4 (Gen-2)
4 (Gen-2)
8 lanes(5GHz)
8 lanes(5GHz)
8
lanes(10GHz)
4 (Gen-2)
4 (Gen-2)
3 (Gen2) and
1 (Gen3)
Pin Compatible
TM
External Use
10
No
Personality Comparison Chart
P1020,
P1011,
P1021,
P1012
P1022,
P1013
T1020
T1022
T1040
T1042
T2081
DIU
--
Yes
Yes
Yes
Yes
Yes
No
SATA
--
2 controller
2 controller
2 controller
2 controller
2 controller
No
1.5 or 3Gbaud
1.5 or 3Gbaud
1.5 or 3Gbaud
No
USB2.0
1.5 or 3Gbaud
2 ULPI
controllers
1.5 or 3Gbaud
2 ULPI
controllers
2 with PHY
2 with PHY
2 with PHY
2 with PHY
2 with PHY
Memory Card
SD/MMC
SD/MMC
Accelerators
SEC3.3
Power
Management
Power
Management
SEC3.3
SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC SD/MMC/SDXC
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
DPAA, PME
SEC5.0 with
Trust
Architecture
Power
Power
Power
Power
Power
Management
Management
Management
Management
Management
with Deep sleep with Deep sleep with Deep sleep with Deep sleep with Deep sleep
Package
Pin Compatible
TM
External Use
11
DPAA, PME,
DCE, SEC5.2
with Trust
Architecture
Power
Management
QorIQ T1040 L2 Switch
TM
External Use
12
T1040: Gigabit Ethernet Switch
−
−
•
BMan
I/F
Fabric
I/F
Parse, Classify,
Distribute
2.5G
MAC
IEEE 1588v2
2.5G
MAC
2.5G
MAC
IEEE 1588v2
L2- Switch
1G
MAC
QSGMII
Quad
PHY
1G
MAC
1G
MAC
1G
MAC
SGMII
4 x SGMII or
1G
MAC
SGMII
13
SGMII
External Use
SGMII
TM
SGMII
Support for Full featured L2
software stacks
SGMII
Integrated solution kit with software
reuse potential
8K MACs
4K VLANs
RMON
Counters
1G
MAC
Through switch integration, low-pin
count QSGMII connectivity and port
count / cost optimization
FMan
MACSec
2.5G
MAC
TCAM 1K
With support for latest standards
including IEEE 802.3az Energy
Efficient Ethernet (EEE)
Increased ROI - Lower TTM and
high re-use
−
•
Management
I/F
Cost savings
−
•
QMan
I/F
Power savings
−
•
Priority flow control - lossless
Lower latency and shared buffer
management
Advanced classification, shaping and
policing
2 x SGMII or
1G
MAC
1G
MAC
QSGMII
Quad
PHY
5GHz
SERDES
1G MAC
−
1G MAC
Advanced Features
1G MAC
•
Ethernet Switch Interface with Frame Manager
•
Core
Core
Core
Core
Queues
Frame Manager
2.5GE
2.5GE
1GE
1GE
1GE
Register interface
(in the configuration
space CCSR) for
control packets
8-port
Ethernet switch
Control packets are queued on the
Ethernet Switch CPU-register interface
and can be accessed (receive and
transmit) through any e5500 core. This
space is memory mapped in T1040
(CCSR space).
x2 QSGMII / x6 SGMII
SerDes x8
TM
External Use
8 L2-switch ports + 3 FMAN ports
• 2 ports of Ethernet switch is
connected to FMAN and operating
2.5 Gbps (aggregating to 5 Gbps)
OR
• 8 L2-switch ports + 4 FMAN ports. 1
port of Ethernet switch is connected
to FMAN @ 2.5 Gbps.
14
QorIQ T104x SERDES
•
QorIQ T104x device supports single 8 lane SerDes.
•
There are two PLL’s in the SerDes.
− PLL1
provides clocking for lanes A:H and Ethernet switch
− PLL2 provides clocking for Lanes C:H
− QorIQ
T104x device supports the following network protocols through
SerDes
 QSGMII
(T1040, T1020 only)
 1000 Base-KX
 SGMII 2.5G (T1042, T1022 only)
 SGMII
TM
External Use
15
Quad Serial Gigabit Media Independent Interface)
•
The QSGMII is a method of combining four SGMII lines into a
5Gbit/s interface.
• QSGMII uses significantly fewer signal lines than
four SGMII busses
1000BASE-T
100BASE-TX
VSC8574
10BASE-T
Serdes
SFP
SFP
SFP
SFP
Fiber
SFPs
Copper
SFPs
1000BASE-LX
1000BASE-T
1000BASE-SX
10/100/1000BT
100BASE-FX
TM
External Use
16
Ethernet Parallel Interfaces on QorIQ T104x Processors
•
2x RGMII or 1x MII interface supported.
• MII/RGMII selection for EC1 via RCW[EC1] field.
• MAC2 or MAC4 selection for EC1 via RCW[MAC2_GMII_SEL] field
• RGMII interface enabled for EC2 via RCW[EC2] field.
RGMII/MII
MAC2
RGMII/MII
MAC3
MAC4
MAC5
TM
External Use
RGMII/MII
MUX
Frame Manager
MAC1
17
EC2
RGMII
EC1
SW Background
•
Legacy operation:
−
−
•
L2 Control
traffic
Separate SoC – dedicated cores.
Dedicated devices, drivers, even
operating systems.
Eth
Eth
Eth
Eth
−
−
−
Switch
Driver
Ethernet
Driver
Registers
Portals
L2
Switch
DPAA
Eth
Eth
Eth
L3/L4
traffic
Eth
L2 data
traffic
T1040 operation:
−
PPC Core
−
L2 control stack (Switch)
L3/L4 network stack (Router)
L3/L4
NWStack
T1040: Switch + Router SoC (Option 1)
Share cores using affinity or partitions
(AMP)
Dedicated devices/portals for L2 and
L3/L4 traffic.
Clean separation of control and datapath traffic.
Clean separation of configuration of L2
(switch driver) and L3/L4 traffic
(network stack).
TM
External Use
18
L2 Control
traffic
L2 data
traffic
Eth
Eth
Eth
Eth
PPC Core2
−
L2 Control
Stack
MIPS Core
2 different stacks/applications
Legacy Router SoC
PPC Core1
•
External Switch
L2 Control
Stack
Switch
Driver
L3/L4
NWStack
Ethernet
Driver
Registers
Portals
L2
Switch
DPAA
Eth
Eth
Eth
Eth
L3/L4
traffic
L2-switch SW - T1040 – What we offer
Eth / SEC Driver
QM-Lib
SEC-Lib
BM-Lib
PME-Lib
VTSS Mgmt
API (GPL)
Customer
Mgmt
JSON/RPC
Customer
L2 Stack
VTSS
SMBStaX
Linux
Customer
L2 Stack
L2 Switch API
Switch Configuration
FLib
FMLib
Customer
Mgmt
Non-Linux
L2
Switch
Driver
ASF
Non-Linux
Kernel GPL
Linux Network
Stack (L3/L4)
Linux
User-Space
GPL
L2
Stack
User-Space GPL
Linux L3,L4,
SEC Control
Apps
Linux
HW
QM/BM
FM
L2 Switch
LAN-WAN
LAN-LAN
TM
External Use
19
L2 Control
Summary
•
Fully non-blocking wire speed Ethernet switch with WRED
−
−
−
−
−
−
−
•
8x 1G user facing ports
2Mbit packet memory
8k MAC addresses
4k VLAN support
Jumbo frame support (10kB)
8x QoS, 8x Queues/Port
The enterprise class switch supports features like VLAN, QoS, STP,
IGMP etc
Variety of Switch SW solutions to suit different customers
− Switch
API
− Vitesse Stack
TM
External Use
20
QorIQ T1040 QUICC Engine
TM
External Use
21
QUICC Engine in QorIQ T1040 Processors
•
•
Supports one uQE block
64MHz SYSCLK support for ProfiBUS
BRG1 BRG3
BRG1
BRG2 BRG4
CLK9
CLK11
CLK10
CLK12/CLK8
BRG2
•
Support for two TDM [TDMA, TDMB]
and two UCC [UCC1, UCC3]
BRG3
BRG4
R
X
UCC1
•
Protocols:
−
−
−
−
CLK3
T
X
HDLC, Transparent
Synchronous UART
ProfiBUS
TDM/SI
UCC3
R
X
uQUICC Engine
T
X
RX TX
•
UCC1 signals are multiplexed with
TDMA signals
• UCC3 signals are multiplexed with
TDMB signals
TM
External Use
22
TDM
A1
RX TX
TDM
B1
CLK15
Platform
/2
QorIQ T2 Family Block Diagram
TM
External Use
23
QorIQ T2080 Block Diagram
T1
T2
T1
T2
T1
T2
Power™
Power™
Power™
e6500
e6500
e6500
e6500
32 KB
32 KB
32 KB
32 KB
D-Cache I-Cache D-Cache I-Cache
32 KB
32 KB
D-Cache I-Cache
Pre-fetch
2MB Banked L2
Security Fuse Processor
Coherency Fabric
IFC
PAMU
Power Management
2x DUART
DCE
1.0
Security
5.2
(XoR,
CRC)
Queue
Mgr.
PAMU
Parse, Classify,
Distribute
HiGig/+
4x I2C
Peripheral Access Mgmt Unit
2x USB2.0 + PHY
PME
2.1
Buffer
Mgr.
RMan
4x
1 / 2.5 / 10G
4x 1G
8-Lane 10GHz SERDES
Datapath Acceleration
• SEC- crypto acceleration 10Gbps
• DCE - Data Compression Engine 17.5Gbps
• PME – Pattern Matching Engine to 10Gbps
TM
External Use
8ch
DMA
8ch
DMA
DCB
Frame Manager
SPI, GPIO
24
PAMU
Real Time Debug
8ch
DMA
PCIe
PCIe
PCIe
PCIe
Security Monitor
SDXC/eMMC
64-bit
DDR3/3L
DDR2/3
Memory
Controller
512KB
Platform
Cache
SATA2.0
32 KB
32 KB
D-Cache I-Cache
SATA2.0
T2
Power™
sRIO
sRIO
T1
Watchpoint
Cross
Trigger
Perf
Monitor
CoreNet
Trace
Aurora
8-Lane 8GHz SERDES
Processor
• 4x e6500, 64b, 1.2 - 1.8GHz
• Dual threaded, with 128b AltiVec
• 2MB shared L2; 256KB per thread
Memory Subsystem
• 512KB Platform Cache w/ECC
• 1x DDR3/3L Controllers up to 2.1GHz
• Up to 1TB addressability (40 bit physical
addressing)
• HW Data Pre-fetching
Switch Fabric
High Speed Serial IO
• 4 PCIe Controllers: two at Gen3, two at Gen2
• 1 with SR-IOV support
• x8 Gen2
• 2 sRIO Controller
• Type 9 and 11 messaging
• Interworking to DPAA via RMan
• 2 SATA 2.0 3Gb/s
• 2 USB 2.0 with PHY
Network IO
• Up to 25Gbps Simple PCD each direction
• 4x1/10GE, 4x1GE or 2.5Gb/s SGMII
• XFI, 10GBase-KR, XAUI, HiGig, HiGig+,
SGMII, RGMII, 1000Base-KX
Device
• TSMC 28HPM Process
• 25x25mm, 896 pins, 0.8mm pitch
• Power estimated at 15.2 – 25.2W (thermal)
depending on frequency
Schedule: Q3-2013 (alpha); mid-2014 qual
QorIQ T2081 Block Diagram
T1
T1
T2
T2
T1
T1
T2
T2
Power™
Power™
Power™
Power™
e6500
e6500
e6500
e6500
32 KB
32 KB
32 KB
32 KB
D-Cache I-Cache D-Cache I-Cache
32 KB
32 KB
D-Cache I-Cache
Pre-fetch
32 KB
32 KB
D-Cache I-Cache
2MB Banked L2
Security Fuse Processor
IFC
PAMU
Power Management
2x DUART
64-bit
DDR3/3L
DDR2/3
Memory
Controller
Coherency Fabric
Security Monitor
SDXC/eMMC
512KB
Platform
Cache
DCE
1.0
Security
5.2
(XoR,
CRC)
Queue
Mgr.
PAMU
Peripheral Access Mgmt Unit
Parse, Classify,
Distribute
PAMU
Real Time Debug
8ch
DMA
8ch
DMA
8ch
DMA
DCB
Watchpoint
Cross
Trigger
4x I2C
6x 1G
8-Lane 10GHz SERDES
Datapath Acceleration
• SEC- crypto acceleration 10Gbps
• DCE - Data Compression Engine 17.5Gbps
• PME – Pattern Matching Engine to 10Gbps
TM
External Use
25
PCIe
2x
2.5 / 10G
PCIe
Buffer
Mgr.
PCIe
2x USB2.0 + PHY
PME
2.1
PCIe
Frame Manager
SPI, GPIO
Perf
Monitor
CoreNet
Trace
Processor
• 4x e6500, 64b, 1.5 - 1.8GHz
• Dual threaded, with 128b AltiVec
• 2MB shared L2; 256KB per thread
Memory Subsystem
• 512KB Platform Cache w/ECC
• 1x DDR3/3L Controllers up to 2.1GHz
• Up to 1TB addressability (40 bit physical
addressing)
• HW Data Pre-fetching
Switch Fabric
High Speed Serial IO
• 4 PCIe Controllers: one at Gen3, three at Gen2
• 1 with SR-IOV support
• x8 Gen2
• 2 USB 2.0 with PHY
Network IO
• Up to 25Gbps Simple PCD each direction
• 8 MACs multiplexed over:
• 2x 10GE, 2x 2.5Gb/s SGMII, 7x GE
• XFI, 10GBase-KR, SGMII, RGMII,
1000Base-KX
Device
• TSMC 28HPM Process
• 23x23mm, 780pins, 0.8mm pitch,
pin compatible with T1042
• Power estimated at 18.7– 24.4W (thermal)
depending on frequency
Schedule: samples: 2H-2014; qual Q1-15
Quad Cores Compared
P2040
P2041
P3041
T1042
T2081
T2080
4x e500mc,
32b
4x e500mc, 32b
4x e500mc, 32b
4x e5500, 64b
4x e6500, 64b
4x e6500, 64b
4
4
4
4
8
8
667MHz –
1.2GHz
1.2 - 1.5GHz
1.2 - 1.5GHz
1.2 - 1.4GHz
1.5 - 1.8GHz
1.2 - 1.8GHz
L2
None
512kB
512kB
1MB
2MB
2MB
L3
1MB
1MB
1MB
256kB
512kB
512kB
1x DDR3/3L to
1200MT/s
1x DDR3/3L to
1333MT/s
1x DDR3/3L to
1333MT/s
1x DDR3L/4 to
1600MT/s
1x DDR3/3L to
2133MT/s
1x DDR3/3L to
2133MT/s
10 to 5GHz
10 to 5GHz
18 to 5GHz
8 to 5GHz
8 to 10GHz
16 to 10GHz
5x 1GE
10GE + 5x 1GE
10GE + 5x 1GE
5x 1GE
2x 1/10GE + 5x
1GE
4x 1/10GE + 4x
1GE
3 at Gen2
3 at Gen2
3 at Gen2
4 at Gen2
2 at Gen2 +
2 at Gen3
2 at Gen2 +
2 at Gen3
SATA2.0
2
2
2
2
No
2
USB2.0
2 w/ int. PHY
2 w/ int. PHY
2 w/ int. PHY
2 w/ int. PHY
2 w/ int. PHY
2 w/ int. PHY
2
2
2
No
No
2
Aurora
Yes
Yes
Yes
Yes
No
Yes
TDM/HDLC
No
No
No
2
No
No
Acceleration
SEC, PME
SEC, PME
SEC, PME
SEC, PME, QE
SEC, PME,
DCE
SEC, PME,
DCE
Cores
Threads
Frequency
DDR
SerDes
Enet
PCIe Cntrls
SRIO/Rman
TM
External Use
26
QorIQ T4 Family Block Diagram
TM
External Use
27
QorIQ T4240 Communications Processor
T1
T1
T2
T1
T2
Power ™
T1
T2
Power ™
e6500
e6500
Power ™
T2
T1
T1
T2
T1
T2
T1
T2
Power ™
Power ™
T1
T2
T1
T2
Power ™
Power ™
e6500
e6500
e6500
Power ™
T2
512KB
Corenet
Platform Cache
T1
T2
Power ™
T1
T2
Power ™
e6500
e6500
Power ™
e6500
Power ™
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
32 KB
e6500
e6500
e6500
e6500
32 KB I-Cache
32 KB D-Cache
32 KB I-Cache
32 KB
32 KB I-Cache
32 KB D-Cache
32 KB I-Cache
32 KB D-Cache
D-Cache
32 KB I-Cache
32 KBD-Cache
32 KB I-Cache
32 KB
32 KB I-Cache
32 KB D-Cache
32 KB I-Cache
32 KB D-Cache
D-Cache
D-Cache
I-Cache
D-Cache
I-Cache
D-Cache
D-Cache
I-Cache
64-bit
64-bit
DDR2/3
DDR3/3L
Memory
Memory
Controller
Controller
64-bit
64-bit
DDR2/3
DDR3/3L
Memory
Memory
Controller
Controller
64-bit
64-bit
DDR2/3
DDR3/3L
Memory
Memory
Controller
Controller
512KB
Corenet
Platform Cache
I-Cache
512KB
Corenet
Platform Cache
2MB Banked L2
2MB Banked L2
2MB Banked L2
Security Fuse Processor
CoreNet™ Coherency Fabric
Buffer 1/ 1/
Mgr. 10G 10G
DCB
1G 1G 1G
1G 1G 1G
HiGig
1/ 1/
10G 10G
DCB
1G 1G 1G
Device
−
−
−
•
Power targets
−
−
Aurora
Data Path Acceleration
−
SEC- crypto acceleration 40 Gbps
−
PME- Reg-ex Pattern Matcher 10Gbps
−
DCE- Data Compression Engine 20Gbps
~54W thermal max at 1.8 GHz
~42W thermal max at 1.5 GHz
TM
External Use
Perf CoreNet
Monitor Trace
16-Lane 10GHz SERDES
•
TSMC 28 HPM process
1932-pin BGA package
42.5x42.5 mm, 1.0 mm pitch
Real Time Debug
Watchpoint
Cross
Trigger
1G 1G 1G
16-Lane 10GHz SERDES
•
SATA 2.0
SPI, GPIO
HiGig
Pattern
Match
RMAN
Engine
2.0
3xDMA
SATA 2.0
2x I2C
FMan
Parse, Classify,
Distribute
sRIO
2x DUART
FMan
Parse, Classify,
Distribute
Peripheral Access
Mgmt Unit
sRIO
Security Queue
5.0
Mgr.
PCIe
SD/MMC
DCE
1.0
PAMU
PAMU
PCIe
IFC
Power Management
PAMU
PCIe
PAMU
PCIe
2x USB 2.0 w/PHY
Interlaken LA
Security Monitor
28
Processor
• 12x e6500, 64-bit, up to 1.8 GHz
• Dual threaded, with128-bit AltiVec engine
• Arranged as 3 clusters of 4 CPUs, with 2
MB L2 per cluster; 256 KB per thread
Memory SubSystem
• 1.5 MB CoreNet platform cache w/ECC
• 3x DDR3 controllers up to 1.87 GHz
• Each with up to 1 TB addressability (40
bit physical addressing)
CoreNet Switch Fabric
High-speed Serial IO
• 4 PCIe controllers, with Gen3
• SR-IOV support
• 2 sRIO controllers
• Type 9 and 11 messaging
• Interworking to DPAA via Rman
• 1 Interlaken Look-Aside at up to10 GHz
• 2 SATA 2.0 3Gb/s
• 2 USB 2.0 with PHY
Network IO
• 2 Frame Managers, each with:
• Up to 25Gbps parse/classify/distribute
• 2x10GE, 6x1GE
• HiGig, Data Center Bridging Support
• SGMII, QSGMII, XAUI, XFI
e6500 Core Enhancement
TM
External Use
29
e6500 Core Complex
•
32K
32K
T
e6500
32K
T
T
e6500
32K
32K
32K
Altivec
•
T
•
T
e6500
32K
PMC
e6500
T
PMC
T
PMC
T
•
Altivec
Altivec
PMC
Altivec
•
32K
•
•
2MB 16-way Shared L2 Cache, 4 Banks
CoreNet Interface
40-bit Address Bus 256-bit Rd & Wr Data Busses
•
CoreNet Double Data Processor Port
P3041
2.5 DMIPS
(1.5GHz)
T2080
5.4 DMIPS
(1.8GHz)
Improvement
Single Thread
3750
5940
1.6x
Core (dual T)
3750
9720
2.6x
15,000
38,880
2.6x
SoC
from P3041
•
•
64-bit Power Architecture
Up to 1.8 GHz operation
Two threads per core
Dual load/store units, one per thread
40-bit Real Address
− 1 Terabyte physical address space
Hardware Table Walk
L2 in cluster of 4 cores
− Supports Share across Cluster
− Supports L2 memory allocation to core or
thread
Power Management
− Drowsy: Core, Cluster, Altivec
− Wait-on-reservation instruction
− Traditional modes
AltiVec SIMD Unit (128b)
− 8,16,32-bit signed/unsigned integer
− 32-bit floating-point
− 192 GFLOP (2GHz)
− 8,16,32-bit Boolean
Virtualization
− Hypervisor
− LRAT

TM
External Use
30
Logical to Real Address translation mechanism for
improved hypervisor performance
Additional e6500 Enhancements
•
•
Faster FPU: 2X faster SP, 4X faster DP over e500mc
New Power ISA v.2.06 Instr
−
•
Improved Branch Prediction
−
−
•
•
−
•
•
•
•
•
•
•
Double BTB size
Better branch prediction scheme (rate increases from 95% to 98%)
Increase number of completion entries and rename registers from 14 to 16
Re-architected the memory subsystem
−
•
instructions for byte- and bit-level acceleration: Parity, population count, bit permute, compare bytes ,
FPU convert to/from 64-bit integer
Shared L2 cache with write-through L1 D cache and large store gather buffer per core
2X L2 cache size per core, effectively more with sharing
40-bit real address
PID0 field size increases from 8 to 14 bits => supports for more threads in many core systems
Enhanced MP Performance: Accelerated Atomic Operations, Optimized Barrier Instructions, Fast
intra-cluster sharing
LRAT: Accelerate hypervisor performance (10-15% for workloads running in OS on HV)
New power-reduction techniques
Drowsy core with fast wake-up (<75% power of run mode)
Option for AltiVec
Changes for debug architecture
TM
External Use
31
Multi-threading Implementation
•
•
•
Interrupts
−
Interrupts are private
−
Each thread has its own interrupt signals
Debug
−
Almost all resources are private. Internal debug works as if they are separate cores
−
External debug has option to halt both threads when one thread debug halts
Power Management
−
Power management control is per-thread (and the associated SoC programming model will
be per-thread)
−
Actual power management will only occur when both threads reach the same power
management state
−
For example, when wait occurs on one thread, fetching stops for that thread, but we don’t
go drowsy until both threads execute wait.
TM
External Use
32
e6500 Power Management Innovation
•
−
•
Focus
Wide voltage range for logic supplies to
allow frequency / power tradeoff
• Reduce energy consumption under light loads
Memory arrays on a separate power supply
• Enable rapid return to fully loaded conditions
•
Power domain hierarchy
−
Altivec within core
− Cores within cluster
− Clusters within SoC
•
• Switch supports 3 modes
• Full On
• Drowsy Mode
• Deep Nap Mode (Powered Off)
Drowsy L2 Cache
−
•
•
Do not have to save/restore processor
state to memory
Greater than 10x improvement in wakeup
response time
Bitcell leakage reduced by ~40%
Drowsy Core
Cluster 1
−
Instantaneous wakeup response with SRPG
− Controlled through software or waterfall power management
− Power <75% of Run-mode
•
Deep Nap Mode
e6500
e6500
e6500
e6500
Power
Switch
Power
Switch
Power
Switch
Power
Switch
32 32
KB KB
I-$ D-$
32 32
KB KB
I-$ D-$
32 32
KB KB
I-$ D-$
32 32
KB KB
I-$ D-$
Rail 0
(0v, Min to Max)
−
State not retained
− Power < 90% of Run-mode
Memory Rail
(0v, Nominal)
1024KB Banked L2
SW/HW
Controls
TM
External Use
33
MEPL Library of AltiVec Functions
TM
External Use
34
•
Solutions Ready Road Show
 TBD
TM
External Use
35
Overview of AltiVec Library Contents
•
Basic Linear Algebra Subprograms (BLAS)
− Standard
building blocks for performing basic vector and matrix
operations
 Level
1: scalar, vector, & vector-vector operations
 Level 2: matrix-vector operations
 Level 3: matrix-matrix operations
•
C Linear Algebra PACKage (CLAPACK) standard functions
linear algebra functions – most benefit from BLAS AltiVec
optimizations
− 1300
•
Mentor Embedded Performance Library (MEPL)
− Includes
general signal processing, FIR and IIR, FFT, convolution and
correlation, image processing, etc.
•
All in binary form as part of MEPL
TM
External Use
36
Migration Between T2081 and T1040
TM
External Use
37
Device Comparison – T1040 and T2081
TM
External Use
38
Commonalities and Differences
Features
T2081
T1040
T1042
Cores
Number of cores
4 × e6500 dual
threaded Power
Architecture
4 × e5500 Power
Architecture
4 × e5500 Power
Architecture
Architecture width
64-bit
64-bit
64-bit
Max frequency (MHz)
1800
1400
1400
DMIPS/MHz
6
3
3
Memory Size
L1 Cache
32KB I/D
32KB I/D
32KB I/D
L2 Cache
2 MB shared
256KB / core backside
256KB / core backside
CPC
512KB frontside
256KB frontside
256KB front side
Cache line size
64 Bytes
64 Bytes
64 Bytes
Memory Type
DDR3/3L @2133 MT/s
DDR3L/4 @1600 MT/s
DDR3L/4 @1600 MT/s
Maximum size of main
memory
32 GB (1Gbit x8
device)
32 GB (1Gbit x8
device)
32 GB (1Gbit x8
device)
TM
External Use
39
Commonalities and Differences (contd…)
Features
T2081
T1040
T1042
I/O
Ethernet controllers
2× XFI
6x SGMII
2x 2.5Gbps SGMII
2x RGMII
2× 5Gbps QSGMII
6x 1Gbps SGMII
2x RGMII
1x MII
5x 1Gbps SGMII
2x 2.5Gbps SGMII
2x RGMII
1x MII
SerDes lanes
8 lanes at up to 10GHz
8 lanes at up to 5 GHz
8 lanes at up to 5 GHz
PCI Express
controllers
3 × Gen 2.0 controllers
1 × Gen 3.0 controllers
4 × Gen 2.0 controllers
4 × Gen 2.0 controllers
SATA
None
2 x SATA controllers
2 x SATA controllers
TDM
None
Full duplex serial
Full duplex serial
DIU
None
12 bit RGB
12 bit RGB
CoreNet
700MHz at 256 bits
600MHz at 128 bits
600MHz at 128 bits
Ethernet switch
None
8 port
None
QE
None
HDLC, UART, TDM/SI
HDLC, UART, TDM/SI
TM
External Use
40
Commonalities and Differences (contd…)
Features
T2081
T1040
T1042
I/O
Integrated Flash
Controller (IFC)
8-/16-bit data width,
32-bit address width
8-/16-bit data width,
32-bit address width
8-/16-bit data width,
32-bit address width
Clocking
Single source clocking
None
Diff_SYSCLK/DIFF_S
YSCLK_B supported
Diff_SYSCLK/DIFF_S
YSCLK_B supported
Power Management
Deep Sleep
None
Supported
Supported
Package
780 FC-PBGA
23 mm x 23 mm
TM
External Use
41
23 mm x 23 mm
23 mm x 23 mm
Hardware Compatibility
TM
External Use
42
Identical Interfaces
The following interfaces are identical between the T2081 and T1040:
Integrated Flash Controller (IFC)
Enhanced SPI Controller (eSPI)
DUART Controller
USB Controller
TM
External Use
43
DDR Controller
•
•
•
T2081 supports DD3/3L.
T1040 supports DDR3L/4.
As DDR3L is common to both devices, it should be used for the common
board design.
DDR Calibration Resistor Values
MDIC [0]
MDIC[1]
T1040
162 ohm 1%
162 ohm 1%
T2081
187 ohm 1%
187 ohm 1%
TM
External Use
44
eSDHC Controller
•
•
•
Both T1 and T2 supports SD 3.0 specification introducing higher capacity
up to 2 TB and frequency up to 208 MHz.
A dynamic switching of I/O voltage from 3.3 V to 1.8V is required.
T2081 doesn’t support the dynamic switch, so the board level shifters are
required for common board design.
TM
External Use
45
SD Card Connections for T1/T2 Compatibility (DS and HS
Modes)
T1040/T2081
1.8 V
1.8 V
Voltage
Translator
3.3 V
3.3 V
SD
CARD
CMD, DAT[0], DAT[1:3], CLK, CD_B, WP
•
•
Other signals should be left NC
SYNC_OUT should be pulled-down with a weak
resistor or the pin should be configured for
alternate functionality
TM
External Use
46
SD Connections for T1/T2 Compatibility (SDR12, 25, 50,
104 and DDR50 Modes)
Voltage
Regulator
(1.8V)
Voltage
Regulator
(3.3V)
Voltage
Select
•
R = 10k
•
Resistor R is
only needed
when RCW
loading is
required to be
done from SD
card
SDHC_VS
R
•
•
GND
1.8V
Smart
Voltage
Translator
(3.3V/1.8V)
T1040/T2081
SDHC_CLK_SYNC_IN
CMD, DAT[0], DAT[1:3], CLK, CD_B, WP
•
DIR
•
Other signals should be left NC
SYNC_OUT should be pulled-down with a weak
resistor or the pin should be configured for
alternate functionality
TM
External Use
47
3.3V/1.8V
SD – CARD
Boot @ 3.3V
work @ 1.8V
SYNC_IN connection is needed in SDR50,
DDR50 mode only.
In SDR50, DDR50 mode all the input signals are
sampled with respect to SYNC_IN
MMC Card Connections for T1/T2 Compatibility (DS, HS,
HS200 Modes)
T1040/T2081
1.8 V
1.8 V
Voltage
Translator
3.3 V
3.3 V
MMC
(3.3V)
CMD, DAT[0], DAT[1:7], CLK, CD
•
•
•
Other signals should be left NC
SYNC_OUT should be pulled-down with a weak
resistor or the pin should be configured for
alternate functionality
Voltage translator is not needed for 1.8V MMC.
TM
External Use
48
MMC (3.3V) Connections for T1/T2 Compatibility (DDR
Mode)
1.8V
Voltage
Translator
(3.3V/1.8V)
3.3V
MMC (3.3V)
T1040/T2081
SDHC_CLK_SYNC_IN
CMD, DAT[0], DAT[1:3], CLK, CD
DIR
•
•
•
•
In DDR mode all the input signals are sampled
with respect to SYNC_IN
Other signals should be left NC
SYNC_OUT should be pulled-down with a weak resistor or the pin should be configured for alternate
functionality
Voltage translator is not needed for 1.8V MMC.
TM
External Use
49
MMC (1.8V) Connections for T1/T2 Compatibility (DDR
Mode)
1.8V
1.8V
T1040/T2081
SDHC_CLK_SYNC_OUT
MMC
(1.8V)
SDHC_CLK_SYNC_IN
CMD, DAT[0], DAT[1:7], CLK, CD
•
•
Other signals should be left NC
In DDR mode all the input signals are sampled
wrt SYNC_IN
TM
External Use
50
RGMII
•
The two RGMII interfaces are pin compatible, the configurations for RGMII mode
are different between the T2081 and T1040 devices.
•
T1040 also supports MII interface on EC1 Interface. When using MII interface,
L1VDD and LVDD are restricted to 3.3V and RGMII cannot be supported on EC1
or EC2.
TM
External Use
51
T1/T2 compatible Serdes Configurations
TM
External Use
52
T1/T2 compatible SerDes Configurations (continue)
TM
External Use
53
TEST_SEL_B Pin
•
The requirement is different for T1040 and T2081.
Device
TEST_SEL_B Requirement
T1040, T1042
Pull up to O1VDD
T1020, T1022
Pull down to GND
T2081
Pull up to OVDD
TM
External Use
54
Sense Pins
•
If the sense pins are used for the regulators, SENSEVDD should be
used. SENSEVDDC can be left floating.
Ball Location
T2081
T1040
G19
SENSEVDD
SENSEVDD
AB9
RSVD28
SENSEVDDC
TM
External Use
55
Power sequencing requirements
•
•
T1040 requires its power rails to ramp up in a specific sequence, whereas
T2081 has no such requirement.
Common board should follow T1040 hardware specification for the Power
sequencing requirements.
Case: Power ON
Step 1
I/O supplies should ramp up (1.8V, 2.5V, 3.3V).
-
PORESET should be asserted when VDDC/VDD rampup
Step 2
Core supplies (1.0V), USB_SVDD
-
I/O power should ramp before core power
Step 3
-
DDR supplies (G1VDD, X1VDD)
VDD should ramp before G1VDD
TM
External Use
56
Power Supply for Core
•
•
•
•
Core Power Island Requirements
T1040 has VDD and VDDC power domains for core and platform.
T2081 has only VDD power domain for core and platform.
The common board design should use a single rail for VDD and VDDC in
T1040.
T2081
T1040
Recommendation
VDD
VDD, VDDC
VDD and VDD should
be connected to a
common rail.
TM
External Use
57
Power Supply for I/O
TM
External Use
58
Clocking Difference
•
T1040 supports the differential pair of SYSCLK, the common board design
leaves it as floating or connect through 10K Ohm resistor to GND.
Clocking scheme
T2081
T1040
Recommendation
Single Reference clock mode
No
Yes
T1040: Supported through
DIFF_SYSCLK/DIFF_SYSCLK_B clock input pair
Multiple reference clock mode
Yes
Yes
Through separate oscillators for SYSCLK,
DDRCLK, USBCLK, SDREF_CLKn inputs.
Recommended mode for common board design.
TM
External Use
59
Exceptions
Product
PCIe
MII
on
EC1
QE
(TDM
HDLC)
Starlite
TDM
QSGMII
GE
Switch
XFI
SATA
DIU
Deep
Sleep
T1040
4 Gen 2
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
T2081
1 Gen3
3 Gen 2
NO
NO
NO
NO
NO
Yes
NO
NO
NO
TM
External Use
60
Pinout Comparison
TM
External Use
61
Pinout Comparison
This table details the differences in pinout between the T2081 and T1040
processor family and how to resolve this difference. Unless explicitly stated
otherwise, the pins on the T2081 can be connected as if a T1040 is
populated.
TM
External Use
62
Pinout Comparison
TM
External Use
63
Pinout Comparison
TM
External Use
64
Software Compatibility
TM
External Use
65
e6500 and e5500 Compatibility
•
User code runs equally well on e6500 or e5500
− Interrupts
per thread
− Soft reset per thread (hard reset per core only)
− Debug state per thread
•
Changes are hidden by OS
− L2
initialization uses a different register
− Cache locking controlled differently
•
Additional enablement for new features not present on e5500:
− 64b,
drowsy power manager, Altivec
TM
External Use
66
e5500/e6500 Caching Structure Differences
e5500
e6500
Implication
L1
32KB. Can lock per core
32kB. Can lock per core
e6500 doesn’t lock per thread
L2
128KB per core
2MB shared
There will be a somewhat different latency
profile, overall improved for e6500
L3
256KB
512kB
•
Cache changes are transparent to user application
• L1 locking is less granular in e6500
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Reset Configuration Word
•
RCW are mostly compatible. Detail listed in T1040 and T2080
reference manual.
RCW bits
T1
T2
10-15
MEM_PLL_CFG
Cutoff frequencies for the T1 and T2 differ.
24:1 async mode setting is available for T1.
176-177
SRDS_DIV_PEX
T1: 00 Train up to 5G
T2: 00 Train up to 8G
190-191
DDR_FDBK_
MUL
Reserved
242
SYS_PLL_SPD
Reserved
321
UC1_CTSB_
CDB_SEL
Reserved
418-419
EC1
Using different MAC.
T1: MAC #4 and #2
T2: MAC #3
420-421
EC2
Using different MAC.
T1: MAC #5
T2: MAC #4, #10
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Notes
Difference in driver
To limit driver configuration issues, take the following actions to simplifying
the driver configuration.
•
Number of cores
−
−
T1040: 4 single-threaded e5500 cores running at 1000MHz/1200MHz/1400MHz
T2081: 4 dual-threaded e6500 cores(8 virtual cores) running at 1200MHz/1533MHz/1800MHz
Using 1200MHz for both core
•
CPC size
−
T1040: 256-Kbyte, 8-way set associative, 64-byte coherency granule
− T2081: 512-Kbyte, 16-way set associative, 64-byte coherency granule
Use 256-Kbyte, 8-way set associative, 64-byte coherency granule
•
L2 size
−
T1040: 256KB per e5500 core, total 1MB.
−
T2081: 2MB shared by 4 e6500 cores
Use 256KB per thread
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Difference in driver (continue…)
•
DDR
−
T1040: one 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
− T2081: one 32-/64-bit DDR3/3L SDRAM memory controller with ECC and interleaving
support and Memory pre-fetch engine
Select cfg_dram_type = 1 to choose DDR3L.
•
Ethernet
−
T1040: 4 MACs from FMan and 8 MAC from Ethernet Switch. It supports two RGMII ports
using MAC4 & MAC5.
− T2081: 6 MACs from FMan(four 1G and four 1/2.5/10G) running with various combinations
with different SerDes procotols. Two RGMII ports using MAC3 & MAC4, 4 XFI ports using
MAC9,MAC10,MAC1,MAC2.
Using RGMII requires the software driver to remap the different MACs between T1
and T2, choose a pin compatible configuration for SerDes option.
•
PCIe
−
T1040: four PCI Express 2.0 controllers/ports running at up to 2.5/5GHz.
− T2081: two PCI Express 2.0 running at 2.5/5GHz and two PCI Express 3.0 controllers/ports
running at 2.5/5/8GHz.
Using 2.5/5GHz only.
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Difference in driver (continue…)
•
SATA
− T1040 has two SATA controllers supporting 1.5 and 3.0 Gbps operation, there is no
defference in software configuration.
− T2081: no support
•
QE
− T1040: support QE with two TDM interfaces. u-boot doesn't support TDM.
−
•
T2081: no support.
DIU
−
−
T1040: support LCD and HDMI interface (DIU) with 12 bit dual data rate.
T2081: no support.
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Difference in driver (continue…)
•
PAMU
− no changes in S/W.
•
DMA
− 3 in T2081 vs 2 in T1040.
•
GE switch
− if used on board add if config, only for T1040.
•
IFC
− same so no changes.
•
Single Source Clocking: USB considerations, only for T1040.
•
Deep sleep: only for T1040.
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Supporting Tools
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T1040/T2081 Software & Tools at a Glance
•
Two Reference Design Boards
− T1040RDB
− T1042RDB
•
Software Support
− Yocto
based SDK
− SDK support includes
 Legacy
features (refer SDK 1.4 release notes)
 New features
 FMAN and QE microcode
 Linux based QE drivers for TDM, UART and HDLC
•
QorIQ Configuration Suite
• CodeWarrior based debugger, flash programmer
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Reference Documentation
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Reference Documentation
T1040 Hardware Specification and Reference Manual
T2081 Hardware Specification and Reference Manual
Application Note (AN4733) T1040 to T2081 Migration Guide
T1040/T2081 Design Checklist
T1040 RDB User Manual
T1040 RDB Schematic
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