pages 26 à 50 - ABCelectronique

pages 26 à 50 - ABCelectronique
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
AM Adjustment (This should be done after FM adjustment.)
● Connection diagram (Measuring instruments)
1) Adjustment of sensitivity.
AM loop antenna
L
AM ANT
AM SG
AM
dummy
antenna
TUNER
P.C.B
ACVM
R
REC
OUT
GND
DIST. M
Oscilloscope
See page 22 for TP locations & adjustment points.
Step
Adjustment item
Signal (ANT IN)
Reception
frequency
Adjustment of
sensitivity
(630kHz)
AM ANT
630kHz
50dBµ
1kHz
30% modulation
630kHz
(B-1)
Verification of
sensitivity
AM ANT
630kHz
1080kHz
1440kHz
30% modulation
630kHz
(B-1)
1080kHz
(B-2)
1440kHz
(B-3)
3
Verification of
signal meter
AM ANT
1080kHz
90dBµ
MONO
1 kHz
30% modulation
1080kHz
(B-2)
4
Verification of
auto tuning
1
2
Adjustment
point
T2
Test point
Rating
REC OUT
Audio output should be maximized.
Repeat steps 1 and 2.
AM ANT
Distortion should be 10% or less at
each frequency.
Check to ensure that the voltage at
the ANT terminal is 54dBµ or less.
All signal meters should light.
–10dB or less
All signal meters should turn OFF.
AM ANT
60dBµ
Auto reception should be available
when the tuning key is moved UP
and DOWN.
Audio must be muted during
search.
Execution of FACTORY PRESET (Refer to page 20.) will facilitate setting reception frequency for adjustment.
25
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ IC DATA
P50/FL08
P51/FL09
P52/FL10
P53/FL11
P54/FL12
P55/FL13
P56/FL14
P57/FL15
P00/FL16
P01/FL17
P02/FL18
P03/FL19
P04/FL20
P05/FL21
P06/FL22
VSS
P07/FL23
VCC
P10/FL24
P11/FL25
P12/FL26
P13/FL27
P14/FL28
P15/FL29
P16/FL30
P17/FL31
P20/FL32
P21/FL33
P22/FL34
P23/FL35
IC501 : M30217MA-A202FP
16-bit Microcomputer
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P67/FL07
P66/FL06
P65/FL05
P64/FL04
P63/FL03
P62/FL02
P61/FL01
P60/FL00
VEE
P107/AN7
P106/AN6
P105/AN5
P104/AN4
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVCC
81
50
82
83
49
48
84
85
47
46
86
87
45
44
88
89
43
42
90
91
41
40
TOP VIEW
92
93
39
38
94
95
37
36
96
97
35
34
98
99
33
32
100
31
P24/FL36
P25/FL37
P26/FL38
P27/FL39
P30/FL40
P31/FL41
P32/FL42
P33/FL43
P34/FL44
P35/FL45
P36/FL46
P37/FL47
P40/FL48
P41/FL49
P42/FL50
P43/FL51
P44/FL52
P45/FL53
P46/FL54
P47/FL55
P97
P96
P95/CK2
P94/SO2
PP93/SI2
P92
P91
P90
CNVSS
P87
P86
/RESET
XOUT
VSS
XIN
VCC
P85/INT5
P84/INT4
P83/INT3
P82/INT2
P81/INT1
P80/INT0
P77
P76/CK1
P76/RX1
P74/TX1
P73
P72
P71
P70
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P00/FL16~
P07/FL22
77-66,64
P10/FL24~
P17/FL31
62-55
P20/FL32~
P27/FL39
54-47
P30/FL40~
P37/FL47
46-39
P40/FL48~
P47/FL55
38-31
P50/FL08~
P57/FL15
80-73
P60/FL00~
P67/FL07
88-81
P70~P73,
P74/TX1,
P75/RX1, P80/INT1~
P76/CK1, P85/INT5
P77
P86,P87
30-23
22-17,11,10
PORT 1
(P10-17)
PORT 2
(P20-27)
PORT 3
(P30-37)
PORT 4
(P40-47)
PORT 5
(P50-57)
PORT 6
(P60-67)
PORT 7
(P70-77)
P90~P92,
P93/SI2,
P94/SO2,
P95/CK2,
P96,P97
8-1
P100/AN0~
P107/AN7
98,96-90
PORT 9
(P90-97)
PORT 10
(P100-107)
I/O PORT
PORT 0
(P00-07)
INTERNAL PERIPHERAL
FUNCTION
TIMER
A/D CONVERTER
(10-bit x 8-ch)
R0H
R0H
R1H
DMAC
(2-ch)
D/A CONVERTER
(8-bit x 2-ch)
R0L
R0L
R1L
R2
R3
A0
A1
FB
SB
FOR ANALOG CIRCUIT
14,65
9
VSS CNVSS
VFD CONTROLLER (8-bit x 7)
M16C/60 SERIES CPU CORE
(16-bit)
REGISTER
89
VEE
CRC PROCESSOR (CCITT MODE)
(GENERATION MULTINOMIAL:
X15+X12+X5+1)
SI/O2(CLOCK SYNCHRONOUS)
(256-Byte AUTOMATIC TRANSFER)
SUPERVISOR TIMER
(15-bit)
16,63
VCC
SYSTEM CLOCK GENERATOR
XIN-XOUT
(2-ch)
XCIN-XCOUT
SERIAL I/O
UART0,1(UART/
CLOCK SYNCHRONOUS)
(8-bit x 2-ch)
TIMER A0 (16-bit)
TIMER A1 (16-bit)
TIMER A2 (16-bit)
TIMER A3 (16-bit)
TIMER A4 (16-bit)
TIMER B0 (16-bit)
TIMER B1 (16-bit)
TIMER B2 (16-bit)
100
AVCC
99
VREF
97
AVSS
PORT 8
(P80-87)
MEMORY
STACK POINTER
ISP
USP
ROM
VECTOR TABLE
INTB
MULTIPLIER
RAM
(FLDC, ASI/ORAM)
SYSTEM RESET
12
/RESET
SYSTEM CLOCK
15
XIN
13
XOUT
26
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC501 : M30217MA-A202FP
16-bit Microcomputer
Pin
No.
1
P97
Pin
Name
SCK
2
3
P96
P95
SDT
RCK
O Serial Data output
O Clock output for model type
32 P46/FL54
33 P45/FL53
4
/CK2
P94
RDT
distinction (*1)
O Data output for destination distinction
5
/SO2
P93
DEST
6
/SI2
P92
7
Port
I/O
Function
Pin
Port
No.
31 P47/FL55
Pin
Name
F-CE
I/O
Function
O Chip enable output
For
F-CK
F-RX
O Serial clock output
I Serial data input
flash µ-COM
write
34 P44/FL52
35 P43/FL51
F-TX
VUP
O Serial data output
O Volume up output
connector
of Tuner (*2)
O Data input for destination distinction
36 P42/FL50
37 P41/FL49
VDN
CDO
O Volume down output
I Serial data input from DIR2
/RD0
RCE
of Tuner (*2)
O Chip enable output for model type
38 P40/FL48 DVD-C/O
39 P37/FL47 DBS-C/O
I DVD/LD coaxial/optical detect input
I Fixed H
PRI
SCKD
distinction (*1)
O Serial Clock output for DIR2
40 P36/FL46
P91
I I (Over current) protection
detect input
8
9
P90
CNVSS
SID
CNVSS
O Serial data output for DIR2
For flash µ-COM write connector
41 P35/FL45
42 P34/FL44
POT-A
POT-B
10
P87
CKB
O Clock output for output port
expansion IC
43 P33/FL43
44 P32/FL42
/ST
DO
11
P86
DTB
O Data output for output port
expansion IC
45 P31/FL41
46 P30/FL40
/ICAC
PRY
O Initial clear output for AC3D2av
O Power relay output
12
13
/RESET
XOUT
/RES
XOUT
System reset
Crystal oscillator connected (10MHz)
47 P27/FL39
48 P26/FL38
SRY
ERY
O Speaker relay output
O Effect relay output
14
15
VSS
XIN
MG
MU
Ground
Crystal oscillator connected (10MHz)
49 P25/FL37
50 P24/FL36
G1
G2
O Grid 1 for FL display
O Grid 2 for FL display
O Serial Clock output
For Input
selector Tuner,
etc.
I Rotary encoder input A
I Rotary encoder input B
I Stereo input from Tuner
I Serial data input from Tuner
16
VCC
17 P85/INT5
+5BU
ERRD
+5V Power supply
I Error flag input from DIR2
51 P23/FL35
52 P22/FL34
G3
G4
O Grid 3 for FL display
O Grid 4 for FL display
18 P84/INT4
19 P83/INT3
ERRA
REM
I Data mute detect input from AC3D2av
I Remote control input
53 P21/FL33
54 P20/FL32
G5
G6
O Grid 5 for FL display
O Grid 6 for FL display
20 P82/INT2
21 P81/INT1
PDT
PSW
I Power down detect input
I Standby switch input
55 P17/FL31
56 P16/FL30
G7
G8
O Grid 7 for FL display
O Grid 8 for FL display
22 P80/INT0
23
P77
CEAC1
CEAC2
O Chip enable output 1 for AC3D2av
O Chip enable output 2 for AC3D2av
57 P15/FL29
58 P14/FL28
G9
G10
O Grid 9 for FL display
O Grid 10 for FL display
24 P76/CK1 CLKAC
25 P75/RX1 RXAC
O Serial clock output 2 for AC3D2av
I Serial data input from AV3D2av
59 P13/FL27
60 P12/FL26
G11
G12
O Grid 11 for FL display
O Grid 12 for FL display
26 P74/TX1 TXAC
27
P73
CECOD
O Serial data output for AC3D2av
O Chip enable output for CODEC ADC/DAC
61 P11/FL25
62 P10/FL24
G13
G14
O Grid 13 for FL display
O Grid 14 for FL display
28
29
P72
P71
TCE
CELC
O Chip enable output for Tuner
O Chip enable output for Input Selector
63
VCC
64 P07/FL23
+5VBU
G15
+5V power supply
O Grid 15 for FL display
30
P70
CETC
I Fixed H
65
VSS
66 P06/FL22
MG
G16
Ground
O Grid 16 for FL display
*1 Model type distinction (H=1, L=0)
DSP-A (Pin 3)
RDS (Pin 6)
0
0
DSP-A
0
1
DSP-E
1
0
RX-V496
HTR-5240
DSP-R496
1
1
RX-V496RDS
HTR 5240RDS
1
0
A,B,G,L
models
1
1
R,T
models
*2 Destination distinction of Tuner (H=1, L=0)
V1 (Pin 4)
V2 (Pin 5)
27
0
0
J
model
0
1
U,C
models
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC501 : M30217MA-A202FP
16-bit Microcomputer
Pin
Port
No.
67 P05/FL21
Pin
Name
P1
O Segment 1 for FL display
Pin
Port
No.
85 P63/FL03
Pin
Name
P19
68 P04/FL20
69 P03/FL19
P2
P3
O Segment 2 for FL display
O Segment 3 for FL display
86 P62/FL02
87 P61/FL01
P20
P21
O Segment 20 for FL display
O Segment 21 for FL display
70 P02/FL18
71 P01/FL17
P4
P5
O Segment 4 for FL display
O Segment 5 for FL display
88 P60/FL00
89
VEE
P22
VP
O Segment 22 for FL display
O Power supply for FL display
72 P00/FL16
73 P57/FL15
P6
P7
O Segment 6 for FL display
O Segment 7 for FL display
90 P107/AN7
91 P106/AN6
LIMDT
PRV
74 P56/FL14
75 P55/FL13
P8
P9
O Segment 8 for FL display
O Segment 9 for FL display
92 P105/AN5
PRD
76 P54/FL12
77 P53/FL11
P10
P11
O Segment 10 for FL display
O Segment 11 for FL display
93 P104/AN4 METER
AD value detect input
I Tuner meter AD value input
78 P52/FL10
79 P51/FL09
P12
P13
O Segment 12 for FL display
O Segment 13 for FL display
94 P103/AN3
95 P102/AN2
NC
/FMT
O No connection
O Full mute output (L: ON)
80 P50/FL08
81 P67/FL07
P14
P15
O Segment 14 for FL display
O Segment 15 for FL display
96 P101/AN1
97 AVSS
KEY2
MG
I Key 2 AD data value input
Ground
82 P66/FL06
83 P65/FL05
P16
P17
O Segment 16 for FL display
O Segment 17 for FL display
98
99
P100/AN0
VREF
KEY1
+5M
I Key 1 AD data value input
Standard power supply for AD input
84 P64/FL04
P18
O Segment 18 for FL display
100
AVCC
+5BU
I/O
Function
I/O
Function
O Segment 19 for FL display
I Limitter DC detect input
I PS (power voltage) protection
AD value detect input
I DC (power amp voltage) protection
+5V power supply
IC107 : BU2090
Serial Input/Parallel Output Driver for Output port expansion
VSS 1
16 VDD
Pin
No.
1
DATA 2
15 Q11
Q2 6
LATCH
Q1 5
OUTPUT BUFFER
(OPEN DRAIN)
Q0 4
Q3 7
Q4 8
(TOP VIEW)
12-Bit SHIFT REGISTER
CONTROL
LOGIC
CLOCK 3
VSS
Pin
Name
VSS
2
3
DATA
CLOVK
DTB
CKB
14 Q10
4
5
Q0
Q1
SW1
SW2
12 Q9
6
7
Q2
Q3
SW3
SW4
12 Q8
8
9
Q4
Q5
SW5
/CONT1
O output 4,5
O Limitter control data output 1,2
11 Q7
10
11
Q6
Q7
/CONT2
/-10dB
O
O –10dB control data output
Port
I/O
Function
Ground
I Control data input from
I Control clock input microcomputer
O Video select data for
video input
O output 1-3(*)
selector
O
O Video select data
Unconnected
10 Q6
12
Q8
(L : –10dB)
6ch GAIN O 6-ch gain control data output (L:6-ch)
9 Q5
13
14
Q9
Q10
/C-MUTE O Center mute data output (L:Mute on)
/SW-MUTE O Subwoofer mute data output (L:Mute on)
15
16
Q11
VDD
/T-MUTE O Tuner mute data output (L : Mute on)
VDD
+5V power supply
* Video input
Selector
Control
(H=High,
L=Low)
Video Input
VCR
SAT/D-TV
DVD/LD
V-AUX
SW1 SW2 SW3
(Pin4) (Pin5) (Pin6)
H
L
H
H
H
L
L
H
L
L
L
L
28
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC3 : YM3436DK (DIR2)
FS0 34
KMO
VSSA
VDDA
PCO
CTLP
CTLN
TST2
LR
LOCKN
P256
XO
XI
KM2
KM1
SKSY
/IC
23 /IC
25 CTLN
24 VDDA
27 NC
26 PCO
29 GNDA
28 CTLP
31 KM2
30 TSTN
33 FS1
32 KM0
Digital Format Interface Receiver
32
29 24 26 28 25 17 38 15 14 13
12 31
22
11
23
22 KM1
21 DOM0
EXTW 36
20 DOM1
DDIN 37
19 DIM0
LR 38
18 DIM1
TOP VIEW
VDD 39
17 TST2
ERR 40
16 GND
EMP 41
15 LOCKN
CDO 42
14 P256
CCK 43
13 XO
CLD 44
12 XI
EXTW
SEL
DDIN
ERR
CSM
EMP
FS1
FS0
SYSTEM
CLOCK
TIMING
GENERATOR
PLL
Pin
Name
DAUX
HDLT
DOUT
VFL
5
6
7
8
29
I/O
Function
VFL
8
7
6
DATA CLOCK
CONTROLLER
EIAJ (AES/EBU)
DIGITAL AUDIO
INTERFACE
DECODER
40
35
41
33
34
S/P
BUFFER
P/S
Pin
Name
/IC
VDDA
CTLN
26
27
28
29
30
PCO
NC
CTLP
GNDA
TSTN
O
KM2
KM0
I
I
I/O
I
2
16 39 30
GND
1 18 19
HDLT
CCK
Pin
No.
23
24
25
42
DAUX
DIM1
DIM0
43
3
DOUT
20
DOM1
DOM0
21
CDO
44
CLD
SKSY 11
MCA 10
MCB 9
WC 8
MCC 7
OPT 5
SYNC 6
VFL 4
DOUT 3
HDLT 2
DAUX 1
Pin
4
9
37
SERIAL INTERFACE
No.
1
2
3
4
5
MCA
MCB
WC
MCC
SYNC
OPT
10
36
VDD
TSTN
CSM 35
Function
Initial clear input from AC3D2av
Power supply
VCO control negative input
I
O
O
O
Audio data input from AC3D2av
Unconnected
Audio data output for AC3D2av
Unconnected
OPT
SYNC
MCC
WC
O
O
O
O
Unconnected
Unconnected
64fs bit clock output for AC3D2av
1fs word clock output for AC3D2av
9
10
11
12
MCB
MCA
SKSY
XI
O
O
I
I
Unconnected
256fs bit clock output for CODEC
Clock synchronization control input (Fixed H)
31
32
33
FS1
O
Unconnected
13
XO
O
Crystal oscillator connection (12.288MHz)
Crystal oscillator connection (12.288MHz)
34
35
FS0
CSM
O
I
36
EXTW
I
14
15
16
P256
LOCKN
GND
O
O
and external clock output for AC3D2av
Unconnected
PLL lock flag output for microcomputer
Ground
Unconnected
Channel status output method selection(Fixed L)
External synchronous auxiliary input word
TST2
DIM1
DIM0
DOM1
O
I
I
I
DIN
LR
VDD
ERR
EMP
I
O
17
18
19
20
37
38
39
40
41
42
CDO
O
21
DOM0
I
43
CCK
I
Serial data output for microcomputer
Serial clock input from microcomputer
22
KM1
I
44
CLD
I
Serial data input from microcomputer
Unconnected
Data input mode selection 0,1
Data output mode selection 1,0 (Fixed L)
Compulsive analog performance mode
input from AC3D2av
I
I
I
O
O
PLL phase comparison output
Unconnected
VCO control positive input (Fixed L)
Ground
Unconnected
Clock mode switching input 2,0 (Fixed L)
clock (Fixed L)
Digital audio data input
Unconnected
Power supply
Data error flag output for microcomputer
Unconnected
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
VSS
RAMD7
RAMD6
RAMD5
RAMD4
RAMD3
RAMD2
RAMD1
RAMD0
VDD1
RAMA2
SCK
SI
SO
/CS
/CSB
RAMA3
TEST
/IC
RAMA4
VSS
RAMA5
RAMA6
/SDBCK0
SURENC
KARAOKE
MUTE
CRC
NONPCM
VDD2
IC4 : YSS918D-F (AC3D2av)
DSP + AC-3(Dolby Digital)/ Pro Logic/ DTS Digital Surround Decoder
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VDD
SDWCK0
SDBCK0
SDIA0
SDIA1
RAMA1
RAMA0
RAMWEN
RAMOEN
VSS
VDD
IPORT7
IPORT6
IPORT5
IPORT4
IPORT3
IPORT2
IPORT1
IPORT0
VSS
81
50
82
83
49
48
84
85
47
46
86
87
45
44
88
89
43
42
TOP VIEW
90
91
PVSS
SDWCK1
SDBCK1
SDOB0
SDOB1
SDOB2
RAMA7
RAMA8
RAMA9
VDD2
VSS
OPORT7
OPORT6
OPORT5
OPORT4
OPORT3
OPORT2
OPORT1
OPORT0
VDD1
41
40
92
93
39
38
94
95
37
36
96
97
35
34
98
99
33
32
100
31
65 /CSB
OPORT0~7
~
39
32
69 SCK
68 SI
67 SO
66 /CS
~
92
99
IPORT0~7
VDD1
RAMCEN
RAMA16
RAMA15
SDIB0
SDIB1
SDIB2
XI
XO
VSS
AVDD
SDIB3
TEST
TEST
OVFB
DTSDATA
AC3DATA
SDOB3
CPO
AVSS
VDD
SDOA2
SDOA1
SDOA0
RAMA14
RAMA13
RAMA12
RAMA1
1
RAMA10
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MICROPROCESSOR
INTERFACE
CONTROL
SIGNALS
CONTROL
SIGNALS
SDIBCKSEL
SDOBCKSEL
SDIB INTERFACE
SDOB INTERFACE
L,R
Ls,Rs
C,LFE
SDIBSEL
STREAM0~7
EXTERNAL RAM
INTERFACE
OPERATING
CLOCK (25MHz)
DELAY
RAM
RAMOEN 89
87,86,70,64,61,
59,58,44~42,
29~25,4,3
RAMCEN 2
79
72
45 SDOB2
18 SDOB3
15 OVFB
RAMWEN 88
RAMD0~7
5
6
7
12
SDIBO
SDIB1
SDIB2
SDIB3
~
46 SDOB1
DATA
RAM
ERAMUSE
SDOA0 24
SDOA1 23
SDOA2 22
XO 9
CPO 19
PLL
24x16
SUB DSP
47 SDOB0
RAMA0~16
24x24
MAIN DSP
AC-3/
PRO LOGIC/
DTS
DECODER
SDIBCKSEL
SDOA INTERFACE
SDIA INTERFACE
INPUT
BUFFER
XI 8
56
55
54
53
17
16
52
CRC
SURENC
KARAOKE
MUTE
CRC
AC3DATA
DTSDATA
NONPCM
SDIASEL
SDI : SERIAL DATA INPUT
SDO : SERIAL DATA OUTPUT
SDIA1 85
48 SDBCK1
49 SDWCK1
CONTROL REGISTERS
/SDBCK0 57
SDBCK0 83
SDWCK0 82
SDIA0 84
COEFFICIENT
PROGRAM
RAM
30
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC4 : YSS918D-F (AC3D2av)
DSP + AC-3(Dolby Digital)/ Pro Logic/ DTS Digital Surround Decoder
No.
Name
Function
VDD1
RAMCEN
O
+5V power supply
RAM chip enable output terminal (normally unconnected)
3
4
RAMA16
RAMA15
O
O
RAM address output terminal 16, connected to external 1M SRAM address
RAM address output terminal 15, connected to external 1M SRAM address
5
6
SDIB0
SDIB1
I
I
Serial data input B terminal 0 (normally connected to ground)
Serial data input B terminal 1 (normally connected to ground)
7
8
SDIB2
XI
I
I
Serial data input B terminal 2 (normally connected to ground)
9
XO
O
Crystal oscillator connection (normally unconnected)
10
11
VSS
AVDD
12
13
SDIB3
TEST
14
15
16
17
TEST
OVFB
DTSDATA
AC3DATA
O
O
O
18
19
SDOB3
CPO
O
20
21
AVSS
VDD
22
23
SDOA2
SDOA1
O
O
Serial data output A terminal 2 (normally unconnected)
Serial data output A terminal 1 (normally unconnected)
24
25
SDOA0
RAMA14
O
O
Serial data output A terminal 0 (normally unconnected)
RAM address terminal 14 output terminal, connected to external 1M SRAM address
26
27
RAMA13
RAMA12
O
O
RAM address terminal 13 output terminal, connected to external 1M SRAM address
RAM address terminal 12 output terminal, connected to external 1M SRAM address
28
29
RAMA11
RAMA10
O
O
RAM address terminal 11 output terminal, connected to external 1M SRAM address
RAM address terminal 10 output terminal, connected to external 1M SRAM address
30
31
VSS
VDD1
32
33
34
OPORT0
OPORT1
OPORT2
O
O
O
Output expansion port terminal 0, digital input selector A output
Output expansion port terminal 1, digital input selector B output (DIB*)
Output expansion port terminal 2, connected to external CODEC initial clear input
35
36
OPORT3
OPORT4
O
O
Output expansion port terminal 3, connected to external DIR2 compulsive analog performance mode input
Output expansion port terminal 4, connected to external DIR2 initial clear input
37
38
OPORT5
OPORT6
O
O
Output expansion port terminal 5 (normally unconnected)
Output expansion port terminal 6 (normally unconnected)
39
40
OPORT7
VSS
O
Output expansion port terminal 7 (normally unconnected)
Ground
41
42
VDD2
RAMA9
O
+3V power supply
RAM address output terminal 9 , connected to external 1M SRAM address
43
44
RAMA8
RAMA7
O
O
RAM address output terminal 8 , connected to external 1M SRAM address
RAM address output terminal 7 , connected to external 1M SRAM address
45
46
SDOB2
SDOB1
O
O
Serial data output B terminal 2, connected to external CODEC PCM audio data output
Serial data output B terminal 1, connected to external CODEC PCM audio data output
47
48
SDOB0
SDBCK1
O
I
Serial data output B terminal 0, connected to external CODEC PCM audio data output
Serial data bit clock input terminal 1, connected to external DIR2 64fs bit clock output
49
50
SDWCK1
VSS
I
Serial data word clock input terminal 1, connected to external DIR2 1fs word clock output
Ground
* Digital input
Selector Control
(H=High, L=Low)
31
I/O
1
2
Crystal oscillator connection or external clock input terminal, connected to external DIR2 external clock output
Ground
+3V power supply
I
O
Serial data input B terminal 3 (normally unconnected)
Test terminal (normally unconnected)
Test terminal (normally unconnected)
Overflow detect terminal (normally unconnected)
DTS data detect terminal (normally unconnected)
AC-3 data detect terminal (normally unconnected)
Serial data output B terminal 3 (normally unconnected)
PLL output terminal (connected to AVSS through external analog filter)
Ground
+3V power supply
Ground
+5V power supply
Digital Input DIB(Pin33)
DVD/LD
SAT/D-TV
L
H
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC4 : YSS918D-F (AC3D2av)
DSP + AC-3(Dolby Digital)/ Pro Logic/ DTS Digital Surround Decoder
No.
Name
I/O
Function
51
VDD2
52
53
NONPCM
CRC
O
O
Non-PCM data output terminal (normally unconnected)
CRC output terminal (normally unconnected)
54
55
MUTE
KARAOKE
O
O
Mute output terminal, connected to external microcomputer data mute detect input
Karaoke output terminal (normally unconnected)
56
57
SURENC
/SDBCK0
O
O
Surround encoder output terminal (normally unconnected)
Inverted signal of serial data bit clock output terminal 0 (normally unconnected)
58
59
RAMA6
RAMA5
O
O
RAM address output terminal 6, connected to external 1M SRAM address
RAM address output terminal 5, connected to external 1M SRAM address
60
61
VSS
RAMA4
O
Ground
RAM address output terminal 4, connected to external 1M SRAM address
62
63
/IC
TEST
I
Initial clear input terminal, connected to external microcomputer initial clear output
Test terminal (normally unconnected)
64
65
RAMA3
/CSB
O
I
RAM address output terminal 3, connected to external 1M SRAM address
Chip select B input terminal, connected to external microcomputer chip enable output 2
66
67
/CS
SO
I
O
Chip select input terminal, connected to external microcomputer chip enable output 1
Serial data output terminal, connected to external microcomputer serial data input
68
69
SI
SCK
I
I
Serial data input terminal, connected to external microcomputer serial data output
Serial clock input terminal, connected to external microcomputer serial clock output
70
71
RAMA2
VDD1
O
RAM address output terminal 2, connected to external 1M SRAM address
+5V power supply
72
73
RAMD0
RAMD1
I/O
I/O
RAM data bus terminal 0, connected to external 1M SRAM data
RAM data bus terminal 1, connected to external 1M SRAM data
74
75
RAMD2
RAMD3
I/O
I/O
RAM data bus terminal 2, connected to external 1M SRAM data
RAM data bus terminal 3, connected to external 1M SRAM data
76
77
RAMD4
RAMD5
I/O
I/O
RAM data bus terminal 4, connected to external 1M SRAM data
RAM data bus terminal 5, connected to external 1M SRAM data
78
79
RAMD6
RAMD7
I/O
I/O
RAM data bus terminal 6, connected to external 1M SRAM data
RAM data bus terminal 7, connected to external 1M SRAM data
80
81
VSS
VDD2
82
83
SDWCK0
SDBCK0
I
I
Serial data word clock input terminal 0, connected to external DIR2 1fs word clock output
Serial data bit clock input terminal 0, connected to external DIR2 64fs bit clock output
84
SDIA0
I
Serial data input A terminal 0, AC-3/DTS bit stream (or PCM) data input, connected to external DIR2
audio data output
85
86
SDIA1
RAMA1
I
O
Serial data input A terminal 1 (normally connected to ground)
RAM address output terminal 1, connected to external 1M SRAM address
87
88
RAMA0
RAMWEN
O
O
RAM address output terminal 0, connected to external 1M SRAM address
RAM write enable output terminal, connected to external 1M SRAM write enable
89
90
RAMOEN
VSS
O
RAM output enable output terminal, connected to external 1M SRAM output enable
Ground
91
92
VDD
IPORT7
I
+3V power supply
Input expansion port terminal 7 (normally connected to ground)
93
94
IPORT6
IPORT5
I
I
Input expansion port terminal 6 (normally connected to ground)
Input expansion port terminal 5 (normally connected to ground)
95
96
IPORT4
IPORT3
I
I
Input expansion port terminal 4 (normally connected to ground)
Input expansion port terminal 3, Front mix select (H:Outside, L:Inside)
97
98
IPORT2
IPORT1
I
I
Input expansion port terminal 2, RF select(H:Exist, L:None)
Input expansion port terminal 1, DTS select (H:DTS (YSS918), L:Non DTS (YSS908))
99
100
IPORT0
VSS
I
Input expansion port terminal 0, SRAM select (H:1M, L:256K)
Ground
+3V power supply
Ground
+3V power supply
32
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC5 : M5M51288BKJ-20LTEL (1M SRAM)
131072-word x 8 bit High Speed Static RAM
A3
2
31 A2
A4
3
30 CE2
A5
4
29 /WE
A6
5
28 A1
A7
6
27 A0
A8
7
26 A16
A9
8
A10
9
24 /OE
A11 10
23 A14
A12 11
22 /CE1
A13 12
21 D8
D1 13
20 D7
D2 14
19 D6
D3 15
18 D5
GND 16
17 D4
NOTE)
A0-A16:
D1-D8:
/CE1,CE2:
/OE:
/WE:
/CE1 CE2 /WE /OE
28
31
2
3
4
5
6
18
512
7
2048
8
9
10
11
12
23
25
26
256
COLUMN ADDRESS
DECODER
16
COLUMN INPUT
BUFFER
/CE1 22
Address input
Data input/output
Chip enable input
Output enable input
Write enable input
Mode
Data I/O
CE2 30
Power
X
Non-selectable
High impedance
On
H
X
X
X
Non-selectable
High impedance
Standby
L
H
L
X
Write mode
Input
On
L
H
H
L
Read mode
Output
On
L
H
H
H
High impedance
On
L: Low level
X: Don't care
32 VCC
16 GND
131072-word x 8-bit
MEMORY ARRAY
(512-row X 2048-column)
COLUMN I/O
A9
A10
A11
A12
A13
A14
A15
A16
X
NOTE) H: High Level
27
25 A15
L
X
33
TOP VIEW
A0
A1
A2
A3
A4
A5
A6
A7
A8
CHIP SELECT
/WE 29
WRITE CONTROL
/OE 24
OUTPUT CONTROL
I/O DATA CONTROL
32 VCC
ROW ADDRESS
DECODER
1
ROW INPUT
BUFFER
NC
13 D1
14 D2
15 D3
17 D4
18 D5
19 D6
20 D7
21 D8
RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
IC6: CS4227-KQ CODEC. ADC/DAC)
1
33
SDIN2
SCLK
38
HOLD
2
32
SDIN3
SDIN1
34
CCLK
3
31
CLKOUT
SDIN2
33
CDOUT
4
30
SDIN3
32
OVL
CDIN
5
29
XTO
TOP VIEW
24
AOUT4
AIN2L 11
23
AOUT3
AOUT2 22
AIN3L 10
AOUT1 21
AOUT5
AGND2 20
AOUT6
25
VA+ 19
26
9
AGND1 18
8
NC 17
/PDN
AIN3R
CMOUT 16
/DEM
AINAUX 15
XTI
27
AIN1L 14
28
7
AIN1R 13
6
AIN2R 12
/CS
SPI/I2C
SDOUT1
36
SDOUT2
35
OVL
30
/DEM
7
Pin
Pin
Name
DATAUX
HOLD
CCLK
I/O
MUX
I
I/O
I
DATAUX terminal (Connected to digital ground)
HOLD terminal (Connected to digital ground)
Control clock input terminal,
19
VOLTAGE
REFERENCE
21
AOUT1
DAC#2
VOLUME
CONTROL
22
AOUT2
DAC#3
VOLUME
CONTROL
23
AOUT3
DAC#4
VOLUME
CONTROL
24
AOUT4
DAC#5
VOLUME
CONTROL
25
AOUT5
DAC#6
VOLUME
CONTROL
26
AOUT6
15
AINAUX
14
AIN1L
13
AIN1R
11
AIN2L
12
AIN2R
10
AIN3L
9
AIN3R
18
AGND1
20
AGND2
LEFT
ADC
RIGHT
ADC
AUXILIARY INPUT
31
28
29
2
1
CLKOUT
XTI
XTO
HOLD
44
43
DATAUX LRCKAUX SCLKAUX
41
Pin
Pin
No.
Name
23
24
AOUT3
AOUT4
O
O
Analog output terminal 3,4, L,Rch
analog output for REAR
25
26
AOUT5
AOUT6
O
O
27
28
/DEM
XTI
I
I
Analog output terminal 5,6, L,Rch
analog output for CENTER, LFE
/DEM terminal (Connected to digital ground)
Cryatal input terminal, 256fs bit clock
29
30
XTO
OVL
O
O
from DIR2
XTO terminal (Unconnected)
OVL terminal (Unconnected)
31
32
CLKOUT
SDIN3
O
I
CLKOUT terminal (Unconnected)
Serial data input terminal, 3,2,1,
33
34
SDIN2
SDIN1
I
I
PCM audio data from AC3D2av
35
36
SDOUT2
SDOUT1
O
O
SDOUT2 terminal (Unconnected)
Serial data output terminal1,
I/O
Function
CDOUT
CDIN
O
I
6
/CS
I
serial data from microcomputer
Chip select input terminal, codec
7
8
SPI/I2C
/PDN
I
I
9
10
AIN3R
AIN3L
I/O
I/O
AIN3R terminal (Unconnected)
Lch analog input/output terminal 3,2, Lch
11
12
AIN2L
AIN2R
I/O
I/O
positive, negative input from input selector
Rch analog input/output terminal 2,1, Rch
13
14
AIN1R
AIN1L
I
I
negative, positive input from input selector
AIN1L terminal (Unconnected)
37
LRCK
I/O
audio data for DIR2
L,Rch clock input/output terminal,
15
16
AINAUX
CMOUT
I
O
AINAUX terminal (Unconnected)
Center mute output terminal
38
SCLK
I/O
1fs word clock from DIR2
Serial clock input/output terminal,
17
18
NC
AGND1
Non connection terminal
Analog ground
39
DGND2
64fs bit clock from DIR2
Digital ground
19
20
VA+
AGND2
+5V Analog power supply
Analog ground
40
41
VD+
DGND1
+5V digital power supply
Digital ground
21
22
AOUT1
AOUT2
Analog output terminal 1,2, L,Rch analog
output for MAIN
39
DGND1 DGND2
4
5
O
O
CMOUT
VOLUME
CONTROL
serial clock from microcomputer
CDOUT terminal (Unconnected)
Control data input terminal,
chip enable from microcomputer
SPI/I2C terminal (Connected to digital ground)
Power down input terminal, initial clear
from AC3D2av
16
DAC#1
MONO
ADC
DEM
27
Function
40
CONTROL PORT
CLOCK OSC/
DIVIDER
No.
1
2
3
VD+ VA–
INPUT MUX
DATAUX
SPI/I2C
6
ANALOG LOW PASS AND
OUTPUT STAGE
37
/CS
5
INPUT
GAIN
LRCK
CDIN
4
DIGITAL FILTERS
8
CDOUT
3
DIGITAL FILTERS
/PDN
CCLK
SERIAL AUDIO DATA INTERFACE
34 SDIN1
35 SDOUT2
36 SDOUT1
37 LRCK
38 SCLK
39 DGND2
40 VD+
41 DGND1
42 NC
43 SCLKAUX
44 LRCKAUX
6-channel 20-bit Codec providing A/D, D/A Converter
42
43
44
NC
SCLKAUX I/O
LRCKAUX I/O
Non connection terminal
SCLKAUX terminal (Connected to digital ground)
LRCKAUX terminal (Connected to digital ground)
34
DSP-R496/RX-V496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ DISPLAY DATA
● V501 : 16-BT-71GK (V4193300)
y
1
PATTERN AREA
• PIN CONNECTION
Pin No.
1
2
3
4
5
6
7
8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
9
CONNECTION F1 F1 NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP Fd Fd NP NP P22 P21 P20 P19
Pin No.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CONNECTION P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 NP NP 16G 15G 14G 13G 12G
Pin No.
NOTE 1) F1, F2......... Filament
2) NP............... No pin
3) P1~P22....... Segment
4) 1G~16G....... Grid
5) Fd terminals are to be supplied
through 51kΩ from Ec.
6) Field of vision is a minimum of
23° from the lower side.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
CONNECTION 11G 10G 9G 8G 7G 6G 5G 4G 3G 2G 1G NP NP F2 F2
• GRID ASSIGNMENT
1G
16G
t
t
a
a
h
f
3G
4G
5G
6G
7G
8G
9G
10G
11G
12G
13G
14G
15G
h
j
g
e
2G
k
f
b
j
g
m
n
r
e
c
k
b
B1
m
B2
B5
S1
c
p
S2
p
d
(1G-5G,
B4
B3
n
r
(15G)
d
(6G)
7G~14G)
(13G)
• ANODE CONNECTION
14G
13G
12G
11G
10G
(TUNER)
a
a
a
a
a
a
a
a
a
a
a
a
a
a
(CD)
b
b
b
b
b
b
b
b
b
b
b
b
b
b
P3
(PHONO)
c
c
c
c
c
c
c
c
c
c
c
c
c
c
P4
(TAPE/MD)
d
d
d
d
d
d
d
d
d
d
d
d
d
d
e
16G
P1
P2
(LEFT)
15G
(RIGHT)
P5
(CBL/SAT)
e
e
e
e
e
e
e
e
e
e
e
e
e
P6
(V-AUX)
f
f
f
f
f
f
f
f
f
f
f
f
f
f
P7
(VCR)
g
g
g
g
g
g
g
g
g
g
g
g
g
g
P8
(SAT/D-TV)
h
h
h
h
h
h
h
h
h
h
h
h
h
h
P9
(DVD/LD)
j
j
j
j
j
j
j
j
j
j
j
j
j
j
P10
S1
k
k
k
k
k
k
k
k
k
k
k
k
k
k
m
m
m
m
m
m
m
m
m
m
m
m
m
m
n
n
n
n
n
n
n
n
n
n
n
n
n
n
p
p
p
p
p
p
p
p
p
p
p
p
p
p
r
r
r
r
r
r
r
r
r
r
r
r
r
r
t
t
t
t
t
t
t
t
t
t
t
t
t
t
–
–
–
–
–
–
–
–
–
B1
–
–
–
–
–
–
–
–
–
B2
–
–
–
–
–
–
–
–
–
B3
–
–
–
–
–
–
–
–
–
B4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P11
P12
(PS)
P13
P14
(PTY)
P15
P16
(RT)
P17
P18
(CT)
P19
P20
P21
P22
35
9G 8G 7G 6G 5G 4G 3G 2G 1G
–
–
–
–
–
–
–
–
–
–
–
–
–
–
B5
S2
–
■ BLOCK DIAGRAM (1/2)
• See page E-61/J-57 → SCHEMATIC DIAGRAM
[INPUT (2/2)]
• See page E-63/J-59 → SCHEMATIC DIAGRAM [DSP]
INPUT SELECTOR
CONTROL
DIB
IC10A
33
IC2
DIGITAL SIGNAL
COAXIAL
13
10
DIGITAL
INPUT
SELECTOR
IC352
4
DVD/LD
OPTICAL
11
7
24
DIR2
37
13
(12.288MHz)
XL1
13
OPTICAL SIGNAL
DETECTOR
IC351
SAT/D-TV
1
DSP
+
DIGITAL/
PRO-LOGIC/
DTS
DECODER
IC4
YSS918D-F 45
IC105A/B
8
5
2
L
3
IC104A/B
1
R
5
7
2
1M SRAM
STATIC
RAM
IC5
R
INPUT SELECTOR
CONTROL
29
I
6
CODEC
DAC
32
47
37
I
6
CODEC
ADC
11
PHONO
IC103
25
36
12
13
IC103
27
IC11A
10
IC8,9
4
30
1
2
D/A
CONVERTER
IC6(2/2)
TUNER
IC103
1
7
6
IC103
~
6
L
IC10B
22
AC3D2av
OPTICAL
• See page E-60/J-56 → SCHEMATIC DIAGRAM
[INPUT (1/2)]
21
84
3
DIGITAL
FORMAT
INTERFACE
RECEIVER
IC3
12
8
~
IC351
LFE
7
6
A/D
CONVERTER
IC6(1/2)
IC11B
26
C
1
2
L
1 CD
IC106A
1
R
2
AUDIO SIGNAL
L
DVD/LD
R
L
INPUT SELECTOR
IC101
VIDEO
AUX
L
30
29
TAPE MONITOR
IC102
R
IC12A
2
4
3
23
RL
7
6
IC106B
22
28
6
8
CCK
CLD
ERRD
CDO
ERRA
CEAC1
CEAC2
CLKAC
RXAC
TXAC
/ICAC
SCK
SDA
CECOD
SAT/D-TV
IC12B
24
RR
1
2
SCK
SDA
CECOD
R
L
IN
R
VCR
L
11
18
R
INHIBIT
IC101
OUT
12
17
L
3 IN
(PLAY) R
TAPE/MD
4 OUT L
(REC)
R
-10dB
CENTER
SUBMUTE WOOFER CONTROL
MUTE
DRIVE
DRIVE DRIVE
6-CH
LEVEL
SHIFT
DRIVE
Q116
Q115
Q121
Q117
INPUT SELECTOR
CONTROL
LIMITTER
CONTROL
DRIVE
Q124,125
C
• See page E-61/J-57 → SCHEMATIC DIAGRAM
[INPUT (2/2)]
L
12
13
14
11
9 10
1
R
2
29
8
18 22
CEAC2
CEAC1
INTD
CLD
CELC
SDT
SCK
/CONT1
/CONT2
L
/-10dB
CENTER
SURROUND
/SW-MUTE
6ch GAIN
EXTERNAL
DECODER
INPUT
R
/C-MUTE
MAIN
23
SUBWOOFER
• See page E-64/J-60 → SCHEMATIC DIAGRAM
[OPERATION (2/2)]
SW1,2
SW1
SW2
SW3
VIDEO
VIDEO AUX
DVD/LD
SAT/D-TV
VIDEO
SELECTOR &
AMP
IC303
4
3
CKB
10
5
6
OUTPUT PORT
EXPANSION
IC107
MONITOR
OUT
2
DTB
11
IN
Q305,306
VCR
OUT
28 43 44 93
3
4
DVD/LD
TUNER
CONTROL
X
RCE
RDT
RCK
METER
/ST
DO
TCE
SCK
SDT
MONITOR
OUT
/TMUTE
S-VIDEO SELECTOR
& AMP
IC301,302
6
XO
SW1,2
S VIDEO
5
SW3
DEST/RDO
VIDEO SIGNAL
15
Q307
RDS
CONTROL
IN
VCR
Q301~304
OUT
• See page E-62/J-58 → SCHEMATIC D
E-36/J-32
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ BLOCK DIAGRAM (2/2)
T1
PK1
FM ANT
RF AMP
AM/FM IF DET.
IC1
LA1266
CERAMIC
CERAMIC
FILTER
FILTER
IF AMP
Fi 1
Fi 2
MIX
1
7
IF
56
FM IF
POS
1
Q1,2
GND
FM DET
COIL
FM IF
LOCAL OSC
QUADRATURE
DET
0
S.CURV
AM ANT
LEVEL DET
AM IF
A
BUFFER
58
AM COIL PACK PK2
AM IF
AM DET
H
AM IF COIL
OSC
VT
Fi 3
T2
J
AM RF
ANT
COIL
K
MIX
AGC
Q3
OSC
COIL
FM OSC
E
F
PROGRAMABLE
DIVIDER
H
PHASE DETECTOR
CHARGE PUMP
(7.2MHz)
XL1
J
1
L
SD
F
METER
VR1
DATA SHIFT
REGISTER LATCH
I
VT
C
B7
UNIVERSAL
COUNTER
UNLOCK
DETECTOR
S.METER
OSC
N
/AM
IF
AM
OSC
M
REFERENCE
DIVIDER
PLL
IC2
LC72131
8 STRQ
A STSG
9 MONO
0 /FM
C /ST
3
4
5
6
TCE
SDT
SCK
TUNER
CONTROL
DO
• See page E-66/J-62→SCHEMATIC DIAGRAM [TUNER] J, U, C, R, T, A and L models
• See page E-67/J-63→SCHEMATIC DIAGRAM [TUNER] B and G models (RDS model
E-38/J-34
E-3
A
B
C
D
■ PRINTED CIRCUIT BOARD (Foil side)
P. C. B. DSP
1
TO: INPUT (1)
TO: INPUT (3)
#2
#1
#3
+5VD
DG
DVD-C/O
L
E
C
RL
E
LIN
+25
DVD-C/O
CECOD
SCK
CCK
DG
ERRD
CLKAC
RXAC
CEAC2
ERRA
#1
#3
#2
R
E
LFE
RR
RIN
-25
DSIG
DIB
DBS-C/O
SDT
CLD
CDO
DG
+5D
TXAC
CEAC1
/ICAC
2
TO: INPUT (1)
#1
#2
#3
17
16
IN
uPC29M33T-E1
COM
OUT
M5M51288BKJ-20LTEL
32
1
M5220FP
M5220FP
5
4
M5220FP
M5220FP
5
4
5
4
1
8
1
8
1
5
4
8
1
3
8
M5220FP
5
4
80
1
81
8
1
51
50
HD74HC02FPEL
8
14
8
23
33
NJM2904M
31
30
100
1
4
1
5
7
YSS918D-F
1
34
22
11
44
12
CS4227-KQ
YM3436DK
4
13
12
44
11
28
34
1
33
22
23
5
6
5
6
● Semiconductor Location
Ref. No.
Ref. No.
Location
IC1
D1
C3
IC2
D2
C3
IC3
D3
B3
IC4
D4
B3
D5
G4
IC5
IC6
D6
G4
IC8
D7
G4
IC9
D8
G3
IC10
D9
C4
IC11
D10
G3
D11
G3
IC12
IC15
D12
C4
Point 5
Pin 13 of IC3
V : 2V/div
H : 50nsec/div
DC range
1 : 1 probe
Location
B3
B3
B4
A3
A3
C4
C3
C3
D3
D3
C3
B3
Ref. No.
Q1
Q2
Location
F3
F4
0V
2V
SAMPLE
50ns
E-52/J-48
A
B
C
D
■ PRINTED CIRCUIT BOARD (Foil side)
1
P. C. B. INPUT (4)
5
8
uPC4570C
4
1
LB1641
2
10
1
5
8
uPC4570C
4
VOLUME
W
1
5
8
uPC4570C
4
1
3
P. C. B. INPUT (2)
FROM : POWER TRANSFORMER
4
5
Location
G3
G4
D3
D2
D2
B2
#11
● Semiconductor Location
Ref. No.
Ref. No.
Location
D351
IC351
F3
D352
IC352
F3
D401
IC401
C2
D451
IC402
C5
D452
IC403
D5
D453
IC404
D5
W502
TO :
OPERATION (1)
6
E-56/J-52
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ PRINTED CIRCUIT BOARD (Foil side)
P. C. B. INPUT (
1
TO: DSP
TO:DSP
DBS-C/O
SDT
CLD
CDO
DG
+5D
TXAC
CEAC1
/ICAC
#3
#2
R
E
LFE
RR
RIN
–25
#2
#3
L
E
C
RL
E
LIN
+25
DVD-C/O
CECOD
SCK
CCK
DG
ERRD
CLKAC
RXAC
CEAC2
ERRA
2
#2
#3
TO:
OPERATION (3)
#7
W621
#4
3
#7
+12A
–12
TIR
E
TIL
E
TOR
E
TOL
#8
#8
AXV
VE
AXL
E
AXR
#5
LC78212
9
RCK
RCE
DO
/ST
ERRA
CEAC2
RXAC
CLKAC
MG
ERRD
CCK
SCK
CECOD
DVD-C/O
VUP
CKB
PRV2
#6
1
LC1
DG
+10
E
E
–25
+25
LC2
E
E
E
E
TO: OPERATION (4)
6
E
RI
LFEI
RRI
E
E
CO
RLO
+12A
VUP
VG
#4
#5
RDT
DEST/RDO
TCE
METER
ICAC
CEAC1
TXAC
MG
+5M
CDO
CLD
SDT
FMT
VDN
DTB
CELC
DG
DG
+5D
+12A
+12B
–12
VG
C
RR
RL
R
L
#5
E-58/J-54
16
BU2090
8
TO:
OPERATION (1)
16
8
TO:
OPERATION (2)
#6
M5220L
W581
5
30
1
4
#6
LI
E
CI
RLI
LO
E
RO
LFEO
RRO
–12
VDN
+10
#4
TO : INPUT (4)
E-5
A
B
C
D
■ PRINTED CIRCUIT BOARD (Foil side)
1
•
J, U, C, A, B, G and L models
P. C. B. MAIN (2)
SWITCHED
100W MAX. TOTAL
AC OUTLETS
J,U,C
models
SWITCHED
100W MAX.(A,B models)
100W MAX.TOTAL (G,L models)
AC OUTLETS
A,B,G,L
models
● Semiconductor Location
J,U,C,A,B,G,L models
Ref. No.
D801
D814
D815
Q807
Location
B3
C4
D5
B4
2
IMPEDANCE SELECTOR
U,C,A,B,G,L only
J
only
3
G only
G only
J only
J,U,C,
A,B,L
only
LOW1
LOW1
LOW2
LOW2
E
E
HI2
HI2
HI1
HI1
G
only
4
MG
SI2
PRY
PRV1
U, C
only
BE
W806
BL
#13
RE
TO:
MAIN (1)
5
W801
FROM :
MAIN(5)
6
W202
TO:
MAIN (1)
W813
BR
W812
GY
TO : MAIN (6)
E-44/J-40
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ PRINTED CIRCUIT BOARD (Foil side)
1
•
P. C. B. MAIN (6)
R and T models only
P. C. B. MAIN (7)
R,T only
W903 RE
W901 YE
W905 OR
W902 WH
W904 BE
W906 BR
2
1
2
8
3
4
7
6
W812
GY
5
W813
BR
FROM : MAIN (1)
TO : POWER TRANSFORMER
3
240V
220V
110V
120V
1-2 / 5-6
2-3 / 6-7
3-4 / 7-8
4-5 / 8-1
P. C. B. MAIN (5)
FROM : POWER TRANSFORMER
4
U,C,R,T,A,B,G,L only
J only
+RYV
+RYV
VPB
● Semiconductor Location
Ref. No.
Location
D381
B5
D382
B5
D383
B5
J only
W381
5
#12
FROM :
MAIN (1)
U,C,R,T,A,B,G,L
only
HI1
HI1
HI2
HI2
E
E
LOW2
LOW2
LOW1
LOW1
W801
TO : MAIN(2)
6
E-46/J-42
E-4
A
B
C
D
■ PRINTED CIRCUIT BOARD (Foil side)
1
P. C. B. MAIN (1)
FROM : OPERATION (4)
2
-B
NFL
VL
NFR
VR
NFRL
VRL
NFRR
VRR
NFC
VC
+B
E
PRV1
RE
BE
3
#10
#10
LIMDT
MG
PRY
S12
SPRY
PRI
PRD
VP
PRV1
ERY
BL
R
R
RE
RE
L
L
LE
LE
4
W503
FROM : OPERATION (1)
W201
TO: MAIN (3)
W202
FROM : MAIN
5
6
E-48/J-44
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ PRINTED CIRCUIT BOARD (Foil side)
1
P. C. B. OPERATION (4)
P. C. B.
TO: INPUT (1)
VG
-12
+12B
+12A
+5D
DG
DG
+10
E
E
-25
+25
PRV1
NJM7812FA
NJM79M12FA
#6
LC1
DG
+10
E
E
-25
+25
LC2
E
E
E
E
U,C,R,T,
A,B,G,L only
#5
2
DG
DG
+5D
+12A
+12B
-12
VG
C
RR
RL
R
L
#5
#5
TO: MAIN (1)
NJM78M05
-BV
NFL
VL
NFR
VR
NFRL
VRL
NFRR
VRR
NFL
VC
+B
E
PRV1
NJM7812FA
3
4
● Semiconductor Location
5
Location
C2
C2
C2
B3
B3
E4
E3
F2
G2
G3
E3
E3
E3
E3
Ref. No.
Q101
Q102
Q103
Q104
Q105
Q106
Q107
Q108
Q109
Q110
Q111
Q112
Q113
Q114
Location
C2
C2
C2
C2
B3
B3
B3
B2
B2
B3
B3
B3
C3
B3
Ref. No.
Q115
Q116
Q117
Q118
Q119
Q301
Q302
Q303
Q304
Q305
Q306
Q307
Q721
Q722
Location
C3
B2
C2
B2
C2
G2
G2
F2
G2
G3
F3
F3
E4
E3
P. C. B
TO: OPERATI
W501
G
G
FL
FL
Ref. No.
D101
D102
D103
D104
D105
D721
D722
IC301
IC302
IC303
IC721
IC722
IC723
IC724
W501
6
E-50/J-46
E
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ PRINTED CIRCUIT BOARD (Foil side)
P. C. B. OPERATIO
TO: INPUT (1)
PRV2
CKB
VUP
DVD-C/O
CECOD
SCK
CCK
ERRD
MG
CLKAC
RXAC
CEAC2
ERRA
/ST
DO
RCE
RCK
1
#6
#6
CELC
DTB
VDN
FMT
SDT
CLD
CDO
+5M
MG
TXAC
CEAC1
/ICAC
METER
TCE
DEST/RDO
RDT
#6
FLASH
µ-COM
WRITE
CONNECTOR
2
F-RX
FCE
MG
CNVSS
1
R,T,A,L
only
2
17 18
22
25
INPUT SELECTOR
COM
F-TX
F-CK
+5BU
/RES
B
A
INPUT
MODE
J,U,C,R,T only
J,U,C only
J,U,C,R,T,
A,L
only
B,G
only
3
J,A,L
only
TUNING
MODE
AUTO/MAN'L
MONO
4
Point 3
(Pin 13 of IC501)
V : 2V/div
H : 50nsec/div
DC range
1 : 1 probe
START
MODE
PTY SEEK
EON
PRESET
/TUNING
EDIT
RDS MODE
/FREQ.
B, G only
P. C. B. OPE
SAMPLE
50ns
Point 4
CH1 : Emitter of Q504
CH2 : Collector of Q503
V : 5V or 2V/div
H : 5sec/div
DC range
1 : 1 probe
CH2
0V
(CH2)
CH1
0V
(CH1)
A/B/C/D/E
PRESET / TUNING
0V
2V
5
FM/AM
MEMORY
MAN'L/AUTO FM
5V
2V
SAMPLE
5s
● Semiconductor Location
Location
Ref. No.
D501
E2
D502
G2
D503
G2
D504
E2
D505
F3
E2
D506
D507
E2
D508
G2
D509
G2
D510
G3
D511
G3
G2
D512
IC501
E2
IC502
G2
IC581
D5
IC582
E5
Q501
D2
D2
Q502
Q503
G2
Q504
G3
Q505
F2
Q506
F2
BASS
TREBLE
N
NJM2068LD
1
1
8
Disconnect the
With the POWER
power cord from
switch turned ON,
the AC outlet.
connect the
power cord to the
AC outlet.
This waveform is not available by pushing the
power switch ON and OFF.
6
E-54/J-50
E-5
A
B
C
D
■ PRINTED CIRCUIT BOARD (Foil side)
1
There are two types of Tuner P. C. B. assemblies for this model:
One has only lead-type device and the other has lead-type and surface-
P. C. B. ASS'Y TUNER LIST
Model
RX-V496RDS/
HTR-5240RDS
mount (SMD) devices. These two P. C. B. assemblies are interchangeable.
Markets Lead Type
B, G/G
V2518900
Lead & SMD
V2519600
•
B and G models (RDS model)
P. C. B. TUNER (Lead Type)
TO : INPUT (1)
2
3
SEPARATION
ADJ.
DISCRIMINATOR
BALANCE ADJ.
1
12
24
13
AM
ANT
Rsyn
Rclk
Rdi
Rce
DEST or Rdo
DO
CLK
DI
CE
/ST
TMUTE
METER
+12
TUR
TE
TUL
MONAURAL
DISTORTION
ADJ.
22
12
1
11
1
24
12
13
GND
FM
ANT
22
12
1
11
2
4
W1
AM SENSITIVITY
ADJ.
SIGNAL
METER
ADJ.
1
Lead Type
● Semiconductor Location
5
6
Ref. No.
D1
D2
D3
IC1
IC2
IC3
IC4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Location
C3
C3
D3
B3
C4
C3
D3
B4
B4
B3
B3
C3
D2
C4
L
●
Point
V : 2V/div
1
Point
(Pin22 of IC2)
H : 50nsec/div
DC range
V : 2V/div
1 : 1 probe
2
(Pin12 of IC4)
H : 0.1µsec/div
DC range
1 : 1 probe
0V
0V
2V
SAMPLE 50us
2V
SAMPLE 0.1us
E-40/J-36
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ PRINTED CIRCUIT BOARD (Foil side)
1
P. C. B. ASS'Y TUNER LIST
There are two types of Tuner P. C. B. assemblies for this model:
One has only lead-type device and the other has lead-type and surfacemount (SMD) devices. These two P. C. B. assemblies are interchangeable.
•
Model
DSP-R496
Markets Lead Type Lead & SMD
J
V2518500 V2519200
RX-V496/HTR-5240
RX-V496/HTR-5240
U, C
R, T/T
V2518600
V2518700
V2519300
V2519400
RX-V496/HTR-5240
A, L/A
V2518800
V2519500
J, U, C, R, T, A and L models
P. C. B. TUNER (Lead Type)
TO : INPUT (1)
2
DISCRIMINATOR
BALANCE
ADJ.
SEPARATION
ADJ.
Rsyn
Rclk
Rdi
Rce
DEST or Rdo
DO
CLK
DI
CE
/ST
TMUTE
METER
+12
TUR
TE
TUL
MONAURAL
DISTORTION
ADJ.
FREQUENCY
STEP
(R,T only)
1
12
3
1
24
AM
ANT
11
13
12
22
GND
FM
ANT
11
1
22
12
4
W1
SIGNAL
METER
ADJ.
AM SENSITIVITY
ADJ.
5
Lead Type
● Semiconductor Location
Ref. No.
D1
D2
D3
IC1
IC2
IC3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Location
C3
C3
D3
B3
C4
C3
B4
B4
B4
B3
C3
D3
C4
6
Lead Type & SMD
● Semiconductor Location
CIRCUIT CHANGES BY MARKET.
J
U,C
R,T
A,B,G,L
Point
R48
V : 2V/div
T3
1
(Pin22 of IC2)
H : 0.1µsec/div
DC range
J41
SW1
J42
0V
R55
R57
R58
2V
R60
:USED
E-42/J-38
1
SAMPLE 0.1us
1 : 1 probe
Ref. No.
D1
D2
D3
IC1
IC2
IC3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Location
G5
G5
H4
F2
G3
G2
F3
F3
F3
F2
G2
H2
G3
:NOT USED
E-4
A
B
C
D
DSP-R496/RX-V496/RX-V496RDS/HTR-5240/HTR-5240RDS
■ SCHEMATIC DIAGRAM [DSP]
4Y
4B
4A
3Y
3B
3A
IC2 : HD74HC02FPEL
Quad 2-Input NOR
Vcc
TO INPUT(3) #1
page F-61/J-57 E-4
1
14
13
12
11
10
9
8
IC1 : NJM2904M
IC8~12 : M5220FP
Dual OP-Amp
A OUT
A –IN
A +IN
4.8 8
03
DIGITAL
IN
2
0
4
0
3
4
5
6
7
1A
1B
2Y
2A
2B
GND
2
2
1Y
V–
1
1
0
1
4.8
2.4
~
7
2.4
5
2.4
3.1
2.4
2.4
1.5
0
0
2.4
0.7
4.5
0.1
0
3.1
0
0
0
0
0
0
4.7
4.7
0
DIGITAL FORMAT INTERFACE RECEIVER
(DIR2)
0
4.8
4
4.8
0
0
4.7
0
0
2.0
2.0
4.8
4.7
0
0
0
DSP + AC-3/P
DEC
(AC
0
0
0
0
0
0
0
0
5
4.8
4.8
S
0
4.8
4.8
2.3 8
2.3
2.2
2.3
4.8
2.3
2.4
10
2.3
2.4
4
2.3
5
1.5
1.4
0
4.8
6
0
3.1
0
6
13
0
7
0
~
~
0
0
0
2.3
0
0
02
3
0
4.8
14
0
0.7
0.7
0
0
0.1
0.1
0.1
0.1
4.7
2.4
4.8
11
0.112
4.8
3
5
Point 5
Pin 13 of IC3
V : 2V/div
H : 50nsec/div
DC range
1 : 1 probe
A
C
B
D
■ SCHEMATIC DIAGRAM [INPUT (1/2)]
TO DSP #3 page E-63/J-59 L-
1
MAIN L
PHONO (MM) EQ AMP
11.5
0
0
2
0
AUDIO
SIGNAL
0
0
0
–11.6
1
MAIN L
3
INPUT
SELECTOR
IN
3 (PLAY)
M
C
4
OUT
4 (REC)
0
0
00 0 0
0 0
0 0
0
0
0
0
0
0 0 0 0
0 0
0 0
0
0
5
0
0
0
TUNER LEVEL
CONTROL
11.9
0
0
0
IN
0
0
6
OUT
–12.0
0
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